diff options
Diffstat (limited to 'arch')
195 files changed, 3834 insertions, 3500 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c1f1a7eee953..8b768937c663 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -644,8 +644,9 @@ config ARCH_MSM | |||
644 | stack and controls some vital subsystems | 644 | stack and controls some vital subsystems |
645 | (clock and power control, etc). | 645 | (clock and power control, etc). |
646 | 646 | ||
647 | config ARCH_SHMOBILE | 647 | config ARCH_SHMOBILE_LEGACY |
648 | bool "Renesas SH-Mobile / R-Mobile" | 648 | bool "Renesas SH-Mobile / R-Mobile (non-multiplatform)" |
649 | select ARCH_SHMOBILE | ||
649 | select ARM_PATCH_PHYS_VIRT | 650 | select ARM_PATCH_PHYS_VIRT |
650 | select CLKDEV_LOOKUP | 651 | select CLKDEV_LOOKUP |
651 | select GENERIC_CLOCKEVENTS | 652 | select GENERIC_CLOCKEVENTS |
@@ -660,7 +661,8 @@ config ARCH_SHMOBILE | |||
660 | select PM_GENERIC_DOMAINS if PM | 661 | select PM_GENERIC_DOMAINS if PM |
661 | select SPARSE_IRQ | 662 | select SPARSE_IRQ |
662 | help | 663 | help |
663 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms. | 664 | Support for Renesas's SH-Mobile and R-Mobile ARM platforms using |
665 | a non-multiplatform kernel. | ||
664 | 666 | ||
665 | config ARCH_RPC | 667 | config ARCH_RPC |
666 | bool "RiscPC" | 668 | bool "RiscPC" |
@@ -723,6 +725,7 @@ config ARCH_S3C64XX | |||
723 | bool "Samsung S3C64XX" | 725 | bool "Samsung S3C64XX" |
724 | select ARCH_HAS_CPUFREQ | 726 | select ARCH_HAS_CPUFREQ |
725 | select ARCH_REQUIRE_GPIOLIB | 727 | select ARCH_REQUIRE_GPIOLIB |
728 | select ARM_AMBA | ||
726 | select ARM_VIC | 729 | select ARM_VIC |
727 | select CLKDEV_LOOKUP | 730 | select CLKDEV_LOOKUP |
728 | select CLKSRC_SAMSUNG_PWM | 731 | select CLKSRC_SAMSUNG_PWM |
@@ -1053,6 +1056,8 @@ config ARM_TIMER_SP804 | |||
1053 | select CLKSRC_MMIO | 1056 | select CLKSRC_MMIO |
1054 | select CLKSRC_OF if OF | 1057 | select CLKSRC_OF if OF |
1055 | 1058 | ||
1059 | source "arch/arm/firmware/Kconfig" | ||
1060 | |||
1056 | source arch/arm/mm/Kconfig | 1061 | source arch/arm/mm/Kconfig |
1057 | 1062 | ||
1058 | config ARM_NR_BANKS | 1063 | config ARM_NR_BANKS |
@@ -1611,7 +1616,7 @@ config HZ_FIXED | |||
1611 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ | 1616 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ |
1612 | ARCH_S5PV210 || ARCH_EXYNOS4 | 1617 | ARCH_S5PV210 || ARCH_EXYNOS4 |
1613 | default AT91_TIMER_HZ if ARCH_AT91 | 1618 | default AT91_TIMER_HZ if ARCH_AT91 |
1614 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE | 1619 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
1615 | default 0 | 1620 | default 0 |
1616 | 1621 | ||
1617 | choice | 1622 | choice |
@@ -1796,8 +1801,8 @@ config ARCH_WANT_GENERAL_HUGETLB | |||
1796 | source "mm/Kconfig" | 1801 | source "mm/Kconfig" |
1797 | 1802 | ||
1798 | config FORCE_MAX_ZONEORDER | 1803 | config FORCE_MAX_ZONEORDER |
1799 | int "Maximum zone order" if ARCH_SHMOBILE | 1804 | int "Maximum zone order" if ARCH_SHMOBILE_LEGACY |
1800 | range 11 64 if ARCH_SHMOBILE | 1805 | range 11 64 if ARCH_SHMOBILE_LEGACY |
1801 | default "12" if SOC_AM33XX | 1806 | default "12" if SOC_AM33XX |
1802 | default "9" if SA1111 | 1807 | default "9" if SA1111 |
1803 | default "11" | 1808 | default "11" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index c99b1086d83d..aa791d17179b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -190,7 +190,6 @@ machine-$(CONFIG_ARCH_S5PC100) += s5pc100 | |||
190 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 | 190 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 |
191 | machine-$(CONFIG_ARCH_SA1100) += sa1100 | 191 | machine-$(CONFIG_ARCH_SA1100) += sa1100 |
192 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile | 192 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile |
193 | machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile | ||
194 | machine-$(CONFIG_ARCH_SIRF) += prima2 | 193 | machine-$(CONFIG_ARCH_SIRF) += prima2 |
195 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga | 194 | machine-$(CONFIG_ARCH_SOCFPGA) += socfpga |
196 | machine-$(CONFIG_ARCH_STI) += sti | 195 | machine-$(CONFIG_ARCH_STI) += sti |
@@ -268,6 +267,7 @@ core-$(CONFIG_KVM_ARM_HOST) += arch/arm/kvm/ | |||
268 | core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ | 267 | core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/ |
269 | core-y += arch/arm/net/ | 268 | core-y += arch/arm/net/ |
270 | core-y += arch/arm/crypto/ | 269 | core-y += arch/arm/crypto/ |
270 | core-y += arch/arm/firmware/ | ||
271 | core-y += $(machdirs) $(platdirs) | 271 | core-y += $(machdirs) $(platdirs) |
272 | 272 | ||
273 | drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ | 273 | drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ |
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index e7190bb5998e..f54d5a25c7ee 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile | |||
@@ -64,7 +64,7 @@ else | |||
64 | endif | 64 | endif |
65 | endif | 65 | endif |
66 | 66 | ||
67 | ifeq ($(CONFIG_ARCH_SHMOBILE),y) | 67 | ifeq ($(CONFIG_ARCH_SHMOBILE_LEGACY),y) |
68 | OBJS += head-shmobile.o | 68 | OBJS += head-shmobile.o |
69 | endif | 69 | endif |
70 | 70 | ||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a65b24f..402481775bbe 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile | |||
@@ -30,6 +30,7 @@ dtb-$(CONFIG_ARCH_AT91) += pm9g45.dtb | |||
30 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb | 30 | dtb-$(CONFIG_ARCH_AT91) += at91sam9n12ek.dtb |
31 | # sam9x5 | 31 | # sam9x5 |
32 | dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb | 32 | dtb-$(CONFIG_ARCH_AT91) += at91-ariag25.dtb |
33 | dtb-$(CONFIG_ARCH_AT91) += at91-cosino_mega2560.dtb | ||
33 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb | 34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g15ek.dtb |
34 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb | 35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g25ek.dtb |
35 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb | 36 | dtb-$(CONFIG_ARCH_AT91) += at91sam9g35ek.dtb |
@@ -216,7 +217,7 @@ dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ | |||
216 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb | 217 | dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb |
217 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ | 218 | dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ |
218 | s3c6410-smdk6410.dtb | 219 | s3c6410-smdk6410.dtb |
219 | dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ | 220 | dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \ |
220 | r7s72100-genmai.dtb \ | 221 | r7s72100-genmai.dtb \ |
221 | r8a7740-armadillo800eva.dtb \ | 222 | r8a7740-armadillo800eva.dtb \ |
222 | r8a7778-bockw.dtb \ | 223 | r8a7778-bockw.dtb \ |
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts index 3a1de9eb5111..3c4f6d983cbd 100644 --- a/arch/arm/boot/dts/animeo_ip.dts +++ b/arch/arm/boot/dts/animeo_ip.dts | |||
@@ -90,34 +90,19 @@ | |||
90 | nand-on-flash-bbt; | 90 | nand-on-flash-bbt; |
91 | status = "okay"; | 91 | status = "okay"; |
92 | 92 | ||
93 | at91bootstrap@0 { | 93 | barebox@0 { |
94 | label = "at91bootstrap"; | ||
95 | reg = <0x0 0x8000>; | ||
96 | }; | ||
97 | |||
98 | barebox@8000 { | ||
99 | label = "barebox"; | 94 | label = "barebox"; |
100 | reg = <0x8000 0x40000>; | 95 | reg = <0x0 0x58000>; |
101 | }; | ||
102 | |||
103 | bareboxenv@48000 { | ||
104 | label = "bareboxenv"; | ||
105 | reg = <0x48000 0x8000>; | ||
106 | }; | ||
107 | |||
108 | user_block@0x50000 { | ||
109 | label = "user_block"; | ||
110 | reg = <0x50000 0xb0000>; | ||
111 | }; | 96 | }; |
112 | 97 | ||
113 | kernel@100000 { | 98 | u_boot_env@58000 { |
114 | label = "kernel"; | 99 | label = "u_boot_env"; |
115 | reg = <0x100000 0x1b0000>; | 100 | reg = <0x58000 0x8000>; |
116 | }; | 101 | }; |
117 | 102 | ||
118 | root@2b0000 { | 103 | ubi@60000 { |
119 | label = "root"; | 104 | label = "ubi"; |
120 | reg = <0x2b0000 0x1D50000>; | 105 | reg = <0x60000 0x1FA0000>; |
121 | }; | 106 | }; |
122 | }; | 107 | }; |
123 | 108 | ||
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi new file mode 100644 index 000000000000..2093c4d7cd6a --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino.dtsi | |||
@@ -0,0 +1,122 @@ | |||
1 | /* | ||
2 | * at91-cosino.dtsi - Device Tree file for Cosino core module | ||
3 | * | ||
4 | * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> | ||
5 | * HCE Engineering | ||
6 | * | ||
7 | * Derived from at91sam9x5ek.dtsi by: | ||
8 | * Copyright (C) 2012 Atmel, | ||
9 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
10 | * | ||
11 | * Licensed under GPLv2 or later. | ||
12 | */ | ||
13 | |||
14 | #include "at91sam9g35.dtsi" | ||
15 | |||
16 | / { | ||
17 | model = "HCE Cosino core module"; | ||
18 | compatible = "hce,cosino", "atmel,at91sam9x5", "atmel,at91sam9"; | ||
19 | |||
20 | chosen { | ||
21 | bootargs = "console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait"; | ||
22 | }; | ||
23 | |||
24 | memory { | ||
25 | reg = <0x20000000 0x8000000>; | ||
26 | }; | ||
27 | |||
28 | clocks { | ||
29 | #address-cells = <1>; | ||
30 | #size-cells = <1>; | ||
31 | ranges; | ||
32 | |||
33 | main_clock: clock@0 { | ||
34 | compatible = "atmel,osc", "fixed-clock"; | ||
35 | clock-frequency = <12000000>; | ||
36 | }; | ||
37 | }; | ||
38 | |||
39 | ahb { | ||
40 | apb { | ||
41 | mmc0: mmc@f0008000 { | ||
42 | pinctrl-0 = < | ||
43 | &pinctrl_board_mmc0 | ||
44 | &pinctrl_mmc0_slot0_clk_cmd_dat0 | ||
45 | &pinctrl_mmc0_slot0_dat1_3>; | ||
46 | status = "okay"; | ||
47 | slot@0 { | ||
48 | reg = <0>; | ||
49 | bus-width = <4>; | ||
50 | cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>; | ||
51 | }; | ||
52 | }; | ||
53 | |||
54 | dbgu: serial@fffff200 { | ||
55 | status = "okay"; | ||
56 | }; | ||
57 | |||
58 | usart0: serial@f801c000 { | ||
59 | status = "okay"; | ||
60 | }; | ||
61 | |||
62 | i2c0: i2c@f8010000 { | ||
63 | status = "okay"; | ||
64 | }; | ||
65 | |||
66 | adc0: adc@f804c000 { | ||
67 | atmel,adc-clock-rate = <1000000>; | ||
68 | atmel,adc-ts-wires = <4>; | ||
69 | atmel,adc-ts-pressure-threshold = <10000>; | ||
70 | status = "okay"; | ||
71 | }; | ||
72 | |||
73 | pinctrl@fffff400 { | ||
74 | mmc0 { | ||
75 | pinctrl_board_mmc0: mmc0-board { | ||
76 | atmel,pins = | ||
77 | <AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD15 gpio CD pin pull up and deglitch */ | ||
78 | }; | ||
79 | }; | ||
80 | }; | ||
81 | |||
82 | watchdog@fffffe40 { | ||
83 | status = "okay"; | ||
84 | }; | ||
85 | }; | ||
86 | |||
87 | nand0: nand@40000000 { | ||
88 | nand-bus-width = <8>; | ||
89 | nand-ecc-mode = "hw"; | ||
90 | atmel,has-pmecc; /* Enable PMECC */ | ||
91 | atmel,pmecc-cap = <4>; | ||
92 | atmel,pmecc-sector-size = <512>; | ||
93 | nand-on-flash-bbt; | ||
94 | status = "okay"; | ||
95 | |||
96 | at91bootstrap@0 { | ||
97 | label = "at91bootstrap"; | ||
98 | reg = <0x0 0x40000>; | ||
99 | }; | ||
100 | |||
101 | uboot@40000 { | ||
102 | label = "u-boot"; | ||
103 | reg = <0x40000 0x80000>; | ||
104 | }; | ||
105 | |||
106 | ubootenv@c0000 { | ||
107 | label = "U-Boot Env"; | ||
108 | reg = <0xc0000 0x140000>; | ||
109 | }; | ||
110 | |||
111 | kernel@200000 { | ||
112 | label = "kernel"; | ||
113 | reg = <0x200000 0x600000>; | ||
114 | }; | ||
115 | |||
116 | rootfs@800000 { | ||
117 | label = "rootfs"; | ||
118 | reg = <0x800000 0x0f800000>; | ||
119 | }; | ||
120 | }; | ||
121 | }; | ||
122 | }; | ||
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts new file mode 100644 index 000000000000..f9415dd11f17 --- /dev/null +++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts | |||
@@ -0,0 +1,84 @@ | |||
1 | /* | ||
2 | * at91-cosino_mega2560.dts - Device Tree file for Cosino board with | ||
3 | * Mega 2560 extension | ||
4 | * | ||
5 | * Copyright (C) 2013 - Rodolfo Giometti <giometti@linux.it> | ||
6 | * HCE Engineering | ||
7 | * | ||
8 | * Derived from at91sam9g35ek.dts by: | ||
9 | * Copyright (C) 2012 Atmel, | ||
10 | * 2012 Nicolas Ferre <nicolas.ferre@atmel.com> | ||
11 | * | ||
12 | * Licensed under GPLv2 or later. | ||
13 | */ | ||
14 | |||
15 | /dts-v1/; | ||
16 | #include "at91-cosino.dtsi" | ||
17 | |||
18 | / { | ||
19 | model = "HCE Cosino Mega 2560"; | ||
20 | compatible = "hce,cosino_mega2560", "atmel,at91sam9x5", "atmel,at91sam9"; | ||
21 | |||
22 | ahb { | ||
23 | apb { | ||
24 | macb0: ethernet@f802c000 { | ||
25 | phy-mode = "rmii"; | ||
26 | status = "okay"; | ||
27 | }; | ||
28 | |||
29 | adc0: adc@f804c000 { | ||
30 | atmel,adc-clock-rate = <1000000>; | ||
31 | atmel,adc-ts-wires = <4>; | ||
32 | atmel,adc-ts-pressure-threshold = <10000>; | ||
33 | status = "okay"; | ||
34 | }; | ||
35 | |||
36 | |||
37 | tsadcc: tsadcc@f804c000 { | ||
38 | status = "okay"; | ||
39 | }; | ||
40 | |||
41 | rtc@fffffeb0 { | ||
42 | status = "okay"; | ||
43 | }; | ||
44 | |||
45 | usart1: serial@f8020000 { | ||
46 | status = "okay"; | ||
47 | }; | ||
48 | |||
49 | usart2: serial@f8024000 { | ||
50 | status = "okay"; | ||
51 | }; | ||
52 | |||
53 | usb2: gadget@f803c000 { | ||
54 | atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>; | ||
55 | status = "okay"; | ||
56 | }; | ||
57 | |||
58 | mmc1: mmc@f000c000 { | ||
59 | pinctrl-0 = < | ||
60 | &pinctrl_mmc1_slot0_clk_cmd_dat0 | ||
61 | &pinctrl_mmc1_slot0_dat1_3>; | ||
62 | status = "okay"; | ||
63 | slot@0 { | ||
64 | reg = <0>; | ||
65 | bus-width = <4>; | ||
66 | non-removable; | ||
67 | }; | ||
68 | }; | ||
69 | }; | ||
70 | |||
71 | usb0: ohci@00600000 { | ||
72 | status = "okay"; | ||
73 | num-ports = <3>; | ||
74 | atmel,vbus-gpio = <0 /* &pioD 18 GPIO_ACTIVE_LOW */ | ||
75 | &pioD 19 GPIO_ACTIVE_LOW | ||
76 | &pioD 20 GPIO_ACTIVE_LOW | ||
77 | >; | ||
78 | }; | ||
79 | |||
80 | usb1: ehci@00700000 { | ||
81 | status = "okay"; | ||
82 | }; | ||
83 | }; | ||
84 | }; | ||
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi index f77065506f1e..c61b16fba79b 100644 --- a/arch/arm/boot/dts/at91rm9200.dtsi +++ b/arch/arm/boot/dts/at91rm9200.dtsi | |||
@@ -191,12 +191,12 @@ | |||
191 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ | 191 | AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA18 periph A */ |
192 | }; | 192 | }; |
193 | 193 | ||
194 | pinctrl_uart0_rts: uart0_rts-0 { | 194 | pinctrl_uart0_cts: uart0_cts-0 { |
195 | atmel,pins = | 195 | atmel,pins = |
196 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ | 196 | <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ |
197 | }; | 197 | }; |
198 | 198 | ||
199 | pinctrl_uart0_cts: uart0_cts-0 { | 199 | pinctrl_uart0_rts: uart0_rts-0 { |
200 | atmel,pins = | 200 | atmel,pins = |
201 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ | 201 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ |
202 | }; | 202 | }; |
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts index d2d72c3b44c4..df6b0aa0e4dd 100644 --- a/arch/arm/boot/dts/at91rm9200ek.dts +++ b/arch/arm/boot/dts/at91rm9200ek.dts | |||
@@ -29,10 +29,22 @@ | |||
29 | 29 | ||
30 | ahb { | 30 | ahb { |
31 | apb { | 31 | apb { |
32 | dbgu: serial@fffff200 { | 32 | usb1: gadget@fffb0000 { |
33 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; | ||
34 | atmel,pullup-gpio = <&pioD 5 GPIO_ACTIVE_HIGH>; | ||
33 | status = "okay"; | 35 | status = "okay"; |
34 | }; | 36 | }; |
35 | 37 | ||
38 | macb0: ethernet@fffbc000 { | ||
39 | phy-mode = "rmii"; | ||
40 | status = "okay"; | ||
41 | |||
42 | phy0: ethernet-phy { | ||
43 | interrupt-parent = <&pioC>; | ||
44 | interrupts = <4 IRQ_TYPE_EDGE_BOTH>; | ||
45 | }; | ||
46 | }; | ||
47 | |||
36 | usart1: serial@fffc4000 { | 48 | usart1: serial@fffc4000 { |
37 | pinctrl-0 = | 49 | pinctrl-0 = |
38 | <&pinctrl_uart1 | 50 | <&pinctrl_uart1 |
@@ -44,16 +56,6 @@ | |||
44 | status = "okay"; | 56 | status = "okay"; |
45 | }; | 57 | }; |
46 | 58 | ||
47 | macb0: ethernet@fffbc000 { | ||
48 | phy-mode = "rmii"; | ||
49 | status = "okay"; | ||
50 | }; | ||
51 | |||
52 | usb1: gadget@fffb0000 { | ||
53 | atmel,vbus-gpio = <&pioD 4 GPIO_ACTIVE_HIGH>; | ||
54 | status = "okay"; | ||
55 | }; | ||
56 | |||
57 | spi0: spi@fffe0000 { | 59 | spi0: spi@fffe0000 { |
58 | status = "okay"; | 60 | status = "okay"; |
59 | cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; | 61 | cs-gpios = <&pioA 3 0>, <0>, <0>, <0>; |
@@ -63,12 +65,45 @@ | |||
63 | reg = <0>; | 65 | reg = <0>; |
64 | }; | 66 | }; |
65 | }; | 67 | }; |
68 | |||
69 | dbgu: serial@fffff200 { | ||
70 | status = "okay"; | ||
71 | }; | ||
66 | }; | 72 | }; |
67 | 73 | ||
68 | usb0: ohci@00300000 { | 74 | usb0: ohci@00300000 { |
69 | num-ports = <2>; | 75 | num-ports = <2>; |
70 | status = "okay"; | 76 | status = "okay"; |
71 | }; | 77 | }; |
78 | |||
79 | nor_flash@10000000 { | ||
80 | compatible = "cfi-flash"; | ||
81 | reg = <0x10000000 0x800000>; | ||
82 | linux,mtd-name = "physmap-flash.0"; | ||
83 | bank-width = <2>; | ||
84 | #address-cells = <1>; | ||
85 | #size-cells = <1>; | ||
86 | |||
87 | barebox@0 { | ||
88 | label = "barebox"; | ||
89 | reg = <0x00000 0x40000>; | ||
90 | }; | ||
91 | |||
92 | bareboxenv@40000 { | ||
93 | label = "bareboxenv"; | ||
94 | reg = <0x40000 0x10000>; | ||
95 | }; | ||
96 | |||
97 | kernel@50000 { | ||
98 | label = "kernel"; | ||
99 | reg = <0x50000 0x300000>; | ||
100 | }; | ||
101 | |||
102 | root@350000 { | ||
103 | label = "root"; | ||
104 | reg = <0x350000 0x4B0000>; | ||
105 | }; | ||
106 | }; | ||
72 | }; | 107 | }; |
73 | 108 | ||
74 | leds { | 109 | leds { |
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index d5bd65f74602..22e255ab6963 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi | |||
@@ -366,6 +366,34 @@ | |||
366 | }; | 366 | }; |
367 | }; | 367 | }; |
368 | 368 | ||
369 | fb { | ||
370 | pinctrl_fb: fb-0 { | ||
371 | atmel,pins = | ||
372 | <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */ | ||
373 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */ | ||
374 | AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */ | ||
375 | AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */ | ||
376 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */ | ||
377 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */ | ||
378 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */ | ||
379 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */ | ||
380 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */ | ||
381 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */ | ||
382 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */ | ||
383 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */ | ||
384 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */ | ||
385 | AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */ | ||
386 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */ | ||
387 | AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */ | ||
388 | AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */ | ||
389 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */ | ||
390 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */ | ||
391 | AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */ | ||
392 | AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */ | ||
393 | AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */ | ||
394 | }; | ||
395 | }; | ||
396 | |||
369 | pioA: gpio@fffff200 { | 397 | pioA: gpio@fffff200 { |
370 | compatible = "atmel,at91rm9200-gpio"; | 398 | compatible = "atmel,at91rm9200-gpio"; |
371 | reg = <0xfffff200 0x200>; | 399 | reg = <0xfffff200 0x200>; |
@@ -549,6 +577,15 @@ | |||
549 | }; | 577 | }; |
550 | }; | 578 | }; |
551 | 579 | ||
580 | fb0: fb@0x00700000 { | ||
581 | compatible = "atmel,at91sam9263-lcdc"; | ||
582 | reg = <0x00700000 0x1000>; | ||
583 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>; | ||
584 | pinctrl-names = "default"; | ||
585 | pinctrl-0 = <&pinctrl_fb>; | ||
586 | status = "disabled"; | ||
587 | }; | ||
588 | |||
552 | nand0: nand@40000000 { | 589 | nand0: nand@40000000 { |
553 | compatible = "atmel,at91rm9200-nand"; | 590 | compatible = "atmel,at91rm9200-nand"; |
554 | #address-cells = <1>; | 591 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts index 70f835b55c0b..15009c9f2293 100644 --- a/arch/arm/boot/dts/at91sam9263ek.dts +++ b/arch/arm/boot/dts/at91sam9263ek.dts | |||
@@ -95,6 +95,36 @@ | |||
95 | }; | 95 | }; |
96 | }; | 96 | }; |
97 | 97 | ||
98 | fb0: fb@0x00700000 { | ||
99 | display = <&display0>; | ||
100 | status = "okay"; | ||
101 | |||
102 | display0: display { | ||
103 | bits-per-pixel = <16>; | ||
104 | atmel,lcdcon-backlight; | ||
105 | atmel,dmacon = <0x1>; | ||
106 | atmel,lcdcon2 = <0x80008002>; | ||
107 | atmel,guard-time = <1>; | ||
108 | |||
109 | display-timings { | ||
110 | native-mode = <&timing0>; | ||
111 | timing0: timing0 { | ||
112 | clock-frequency = <4965000>; | ||
113 | hactive = <240>; | ||
114 | vactive = <320>; | ||
115 | hback-porch = <1>; | ||
116 | hfront-porch = <33>; | ||
117 | vback-porch = <1>; | ||
118 | vfront-porch = <0>; | ||
119 | hsync-len = <5>; | ||
120 | vsync-len = <1>; | ||
121 | hsync-active = <1>; | ||
122 | vsync-active = <1>; | ||
123 | }; | ||
124 | }; | ||
125 | }; | ||
126 | }; | ||
127 | |||
98 | nand0: nand@40000000 { | 128 | nand0: nand@40000000 { |
99 | nand-bus-width = <8>; | 129 | nand-bus-width = <8>; |
100 | nand-ecc-mode = "soft"; | 130 | nand-ecc-mode = "soft"; |
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index c3e514837074..d7af9ecb85d2 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi | |||
@@ -143,6 +143,22 @@ | |||
143 | }; | 143 | }; |
144 | }; | 144 | }; |
145 | 145 | ||
146 | i2c0 { | ||
147 | pinctrl_i2c0: i2c0-0 { | ||
148 | atmel,pins = | ||
149 | <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA21 periph A TWCK0 */ | ||
150 | AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A TWD0 */ | ||
151 | }; | ||
152 | }; | ||
153 | |||
154 | i2c1 { | ||
155 | pinctrl_i2c1: i2c1-0 { | ||
156 | atmel,pins = | ||
157 | <AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB11 periph A TWCK1 */ | ||
158 | AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB10 periph A TWD1 */ | ||
159 | }; | ||
160 | }; | ||
161 | |||
146 | usart0 { | 162 | usart0 { |
147 | pinctrl_usart0: usart0-0 { | 163 | pinctrl_usart0: usart0-0 { |
148 | atmel,pins = | 164 | atmel,pins = |
@@ -425,6 +441,42 @@ | |||
425 | }; | 441 | }; |
426 | }; | 442 | }; |
427 | 443 | ||
444 | fb { | ||
445 | pinctrl_fb: fb-0 { | ||
446 | atmel,pins = | ||
447 | <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE0 periph A */ | ||
448 | AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE2 periph A */ | ||
449 | AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE3 periph A */ | ||
450 | AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE4 periph A */ | ||
451 | AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE5 periph A */ | ||
452 | AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE6 periph A */ | ||
453 | AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE7 periph A */ | ||
454 | AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE8 periph A */ | ||
455 | AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE9 periph A */ | ||
456 | AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE10 periph A */ | ||
457 | AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE11 periph A */ | ||
458 | AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE12 periph A */ | ||
459 | AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE13 periph A */ | ||
460 | AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE14 periph A */ | ||
461 | AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE15 periph A */ | ||
462 | AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE16 periph A */ | ||
463 | AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE17 periph A */ | ||
464 | AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE18 periph A */ | ||
465 | AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE19 periph A */ | ||
466 | AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE20 periph A */ | ||
467 | AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */ | ||
468 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE22 periph A */ | ||
469 | AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */ | ||
470 | AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */ | ||
471 | AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */ | ||
472 | AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */ | ||
473 | AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */ | ||
474 | AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */ | ||
475 | AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */ | ||
476 | AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */ | ||
477 | }; | ||
478 | }; | ||
479 | |||
428 | pioA: gpio@fffff200 { | 480 | pioA: gpio@fffff200 { |
429 | compatible = "atmel,at91rm9200-gpio"; | 481 | compatible = "atmel,at91rm9200-gpio"; |
430 | reg = <0xfffff200 0x200>; | 482 | reg = <0xfffff200 0x200>; |
@@ -542,6 +594,8 @@ | |||
542 | compatible = "atmel,at91sam9g10-i2c"; | 594 | compatible = "atmel,at91sam9g10-i2c"; |
543 | reg = <0xfff84000 0x100>; | 595 | reg = <0xfff84000 0x100>; |
544 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; | 596 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; |
597 | pinctrl-names = "default"; | ||
598 | pinctrl-0 = <&pinctrl_i2c0>; | ||
545 | #address-cells = <1>; | 599 | #address-cells = <1>; |
546 | #size-cells = <0>; | 600 | #size-cells = <0>; |
547 | status = "disabled"; | 601 | status = "disabled"; |
@@ -551,6 +605,8 @@ | |||
551 | compatible = "atmel,at91sam9g10-i2c"; | 605 | compatible = "atmel,at91sam9g10-i2c"; |
552 | reg = <0xfff88000 0x100>; | 606 | reg = <0xfff88000 0x100>; |
553 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; | 607 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; |
608 | pinctrl-names = "default"; | ||
609 | pinctrl-0 = <&pinctrl_i2c1>; | ||
554 | #address-cells = <1>; | 610 | #address-cells = <1>; |
555 | #size-cells = <0>; | 611 | #size-cells = <0>; |
556 | status = "disabled"; | 612 | status = "disabled"; |
@@ -618,6 +674,7 @@ | |||
618 | compatible = "atmel,hsmci"; | 674 | compatible = "atmel,hsmci"; |
619 | reg = <0xfff80000 0x600>; | 675 | reg = <0xfff80000 0x600>; |
620 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; | 676 | interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; |
677 | pinctrl-names = "default"; | ||
621 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; | 678 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>; |
622 | dma-names = "rxtx"; | 679 | dma-names = "rxtx"; |
623 | #address-cells = <1>; | 680 | #address-cells = <1>; |
@@ -629,6 +686,7 @@ | |||
629 | compatible = "atmel,hsmci"; | 686 | compatible = "atmel,hsmci"; |
630 | reg = <0xfffd0000 0x600>; | 687 | reg = <0xfffd0000 0x600>; |
631 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; | 688 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>; |
689 | pinctrl-names = "default"; | ||
632 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; | 690 | dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>; |
633 | dma-names = "rxtx"; | 691 | dma-names = "rxtx"; |
634 | #address-cells = <1>; | 692 | #address-cells = <1>; |
@@ -727,6 +785,15 @@ | |||
727 | }; | 785 | }; |
728 | }; | 786 | }; |
729 | 787 | ||
788 | fb0: fb@0x00500000 { | ||
789 | compatible = "atmel,at91sam9g45-lcdc"; | ||
790 | reg = <0x00500000 0x1000>; | ||
791 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; | ||
792 | pinctrl-names = "default"; | ||
793 | pinctrl-0 = <&pinctrl_fb>; | ||
794 | status = "disabled"; | ||
795 | }; | ||
796 | |||
730 | nand0: nand@40000000 { | 797 | nand0: nand@40000000 { |
731 | compatible = "atmel,at91rm9200-nand"; | 798 | compatible = "atmel,at91rm9200-nand"; |
732 | #address-cells = <1>; | 799 | #address-cells = <1>; |
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index a4b00e5c61c0..7b76dbde8c41 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts | |||
@@ -123,6 +123,35 @@ | |||
123 | }; | 123 | }; |
124 | }; | 124 | }; |
125 | 125 | ||
126 | fb0: fb@0x00500000 { | ||
127 | display = <&display0>; | ||
128 | status = "okay"; | ||
129 | |||
130 | display0: display { | ||
131 | bits-per-pixel = <32>; | ||
132 | atmel,lcdcon-backlight; | ||
133 | atmel,dmacon = <0x1>; | ||
134 | atmel,lcdcon2 = <0x80008002>; | ||
135 | atmel,guard-time = <9>; | ||
136 | atmel,lcd-wiring-mode = "RGB"; | ||
137 | |||
138 | display-timings { | ||
139 | native-mode = <&timing0>; | ||
140 | timing0: timing0 { | ||
141 | clock-frequency = <9000000>; | ||
142 | hactive = <480>; | ||
143 | vactive = <272>; | ||
144 | hback-porch = <1>; | ||
145 | hfront-porch = <1>; | ||
146 | vback-porch = <40>; | ||
147 | vfront-porch = <1>; | ||
148 | hsync-len = <45>; | ||
149 | vsync-len = <1>; | ||
150 | }; | ||
151 | }; | ||
152 | }; | ||
153 | }; | ||
154 | |||
126 | nand0: nand@40000000 { | 155 | nand0: nand@40000000 { |
127 | nand-bus-width = <8>; | 156 | nand-bus-width = <8>; |
128 | nand-ecc-mode = "soft"; | 157 | nand-ecc-mode = "soft"; |
diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index 1e12aeff403b..aa537ed13f0a 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi | |||
@@ -85,6 +85,8 @@ | |||
85 | reg = <0x7e205000 0x1000>; | 85 | reg = <0x7e205000 0x1000>; |
86 | interrupts = <2 21>; | 86 | interrupts = <2 21>; |
87 | clocks = <&clk_i2c>; | 87 | clocks = <&clk_i2c>; |
88 | #address-cells = <1>; | ||
89 | #size-cells = <0>; | ||
88 | status = "disabled"; | 90 | status = "disabled"; |
89 | }; | 91 | }; |
90 | 92 | ||
@@ -93,6 +95,8 @@ | |||
93 | reg = <0x7e804000 0x1000>; | 95 | reg = <0x7e804000 0x1000>; |
94 | interrupts = <2 21>; | 96 | interrupts = <2 21>; |
95 | clocks = <&clk_i2c>; | 97 | clocks = <&clk_i2c>; |
98 | #address-cells = <1>; | ||
99 | #size-cells = <0>; | ||
96 | status = "disabled"; | 100 | status = "disabled"; |
97 | }; | 101 | }; |
98 | 102 | ||
diff --git a/arch/arm/boot/dts/cros5250-common.dtsi b/arch/arm/boot/dts/cros5250-common.dtsi index dc259e8b8a73..9b186ac06c8b 100644 --- a/arch/arm/boot/dts/cros5250-common.dtsi +++ b/arch/arm/boot/dts/cros5250-common.dtsi | |||
@@ -27,6 +27,13 @@ | |||
27 | i2c2_bus: i2c2-bus { | 27 | i2c2_bus: i2c2-bus { |
28 | samsung,pin-pud = <0>; | 28 | samsung,pin-pud = <0>; |
29 | }; | 29 | }; |
30 | |||
31 | max77686_irq: max77686-irq { | ||
32 | samsung,pins = "gpx3-2"; | ||
33 | samsung,pin-function = <0>; | ||
34 | samsung,pin-pud = <0>; | ||
35 | samsung,pin-drv = <0>; | ||
36 | }; | ||
30 | }; | 37 | }; |
31 | 38 | ||
32 | i2c@12C60000 { | 39 | i2c@12C60000 { |
@@ -35,6 +42,11 @@ | |||
35 | 42 | ||
36 | max77686@09 { | 43 | max77686@09 { |
37 | compatible = "maxim,max77686"; | 44 | compatible = "maxim,max77686"; |
45 | interrupt-parent = <&gpx3>; | ||
46 | interrupts = <2 0>; | ||
47 | pinctrl-names = "default"; | ||
48 | pinctrl-0 = <&max77686_irq>; | ||
49 | wakeup-source; | ||
38 | reg = <0x09>; | 50 | reg = <0x09>; |
39 | 51 | ||
40 | voltage-regulators { | 52 | voltage-regulators { |
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 59154dc15fe4..fb28b2ecb1db 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi | |||
@@ -161,7 +161,7 @@ | |||
161 | clocks = <&clks 197>, <&clks 3>, | 161 | clocks = <&clks 197>, <&clks 3>, |
162 | <&clks 197>, <&clks 107>, | 162 | <&clks 197>, <&clks 107>, |
163 | <&clks 0>, <&clks 118>, | 163 | <&clks 0>, <&clks 118>, |
164 | <&clks 62>, <&clks 139>, | 164 | <&clks 0>, <&clks 139>, |
165 | <&clks 0>; | 165 | <&clks 0>; |
166 | clock-names = "core", "rxtx0", | 166 | clock-names = "core", "rxtx0", |
167 | "rxtx1", "rxtx2", | 167 | "rxtx1", "rxtx2", |
diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi index b0ee342598f0..68221fab978d 100644 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ b/arch/arm/boot/dts/omap-zoom-common.dtsi | |||
@@ -13,7 +13,7 @@ | |||
13 | * they probably share the same GPIO IRQ | 13 | * they probably share the same GPIO IRQ |
14 | * REVISIT: Add timing support from slls644g.pdf | 14 | * REVISIT: Add timing support from slls644g.pdf |
15 | */ | 15 | */ |
16 | 8250@3,0 { | 16 | uart@3,0 { |
17 | compatible = "ns16550a"; | 17 | compatible = "ns16550a"; |
18 | reg = <3 0 0x100>; | 18 | reg = <3 0 0x100>; |
19 | bank-width = <2>; | 19 | bank-width = <2>; |
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index a2bfcde858a6..d0c5b37e248c 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi | |||
@@ -9,6 +9,7 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <dt-bindings/gpio/gpio.h> | 11 | #include <dt-bindings/gpio/gpio.h> |
12 | #include <dt-bindings/interrupt-controller/irq.h> | ||
12 | #include <dt-bindings/pinctrl/omap.h> | 13 | #include <dt-bindings/pinctrl/omap.h> |
13 | 14 | ||
14 | #include "skeleton.dtsi" | 15 | #include "skeleton.dtsi" |
@@ -21,6 +22,8 @@ | |||
21 | serial0 = &uart1; | 22 | serial0 = &uart1; |
22 | serial1 = &uart2; | 23 | serial1 = &uart2; |
23 | serial2 = &uart3; | 24 | serial2 = &uart3; |
25 | i2c0 = &i2c1; | ||
26 | i2c1 = &i2c2; | ||
24 | }; | 27 | }; |
25 | 28 | ||
26 | cpus { | 29 | cpus { |
@@ -53,6 +56,28 @@ | |||
53 | ranges; | 56 | ranges; |
54 | ti,hwmods = "l3_main"; | 57 | ti,hwmods = "l3_main"; |
55 | 58 | ||
59 | aes: aes@480a6000 { | ||
60 | compatible = "ti,omap2-aes"; | ||
61 | ti,hwmods = "aes"; | ||
62 | reg = <0x480a6000 0x50>; | ||
63 | dmas = <&sdma 9 &sdma 10>; | ||
64 | dma-names = "tx", "rx"; | ||
65 | }; | ||
66 | |||
67 | hdq1w: 1w@480b2000 { | ||
68 | compatible = "ti,omap2420-1w"; | ||
69 | ti,hwmods = "hdq1w"; | ||
70 | reg = <0x480b2000 0x1000>; | ||
71 | interrupts = <58>; | ||
72 | }; | ||
73 | |||
74 | mailbox: mailbox@48094000 { | ||
75 | compatible = "ti,omap2-mailbox"; | ||
76 | ti,hwmods = "mailbox"; | ||
77 | reg = <0x48094000 0x200>; | ||
78 | interrupts = <26>; | ||
79 | }; | ||
80 | |||
56 | intc: interrupt-controller@1 { | 81 | intc: interrupt-controller@1 { |
57 | compatible = "ti,omap2-intc"; | 82 | compatible = "ti,omap2-intc"; |
58 | interrupt-controller; | 83 | interrupt-controller; |
@@ -63,6 +88,7 @@ | |||
63 | 88 | ||
64 | sdma: dma-controller@48056000 { | 89 | sdma: dma-controller@48056000 { |
65 | compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; | 90 | compatible = "ti,omap2430-sdma", "ti,omap2420-sdma"; |
91 | ti,hwmods = "dma"; | ||
66 | reg = <0x48056000 0x1000>; | 92 | reg = <0x48056000 0x1000>; |
67 | interrupts = <12>, | 93 | interrupts = <12>, |
68 | <13>, | 94 | <13>, |
@@ -73,21 +99,91 @@ | |||
73 | #dma-requests = <64>; | 99 | #dma-requests = <64>; |
74 | }; | 100 | }; |
75 | 101 | ||
102 | i2c1: i2c@48070000 { | ||
103 | compatible = "ti,omap2-i2c"; | ||
104 | ti,hwmods = "i2c1"; | ||
105 | reg = <0x48070000 0x80>; | ||
106 | #address-cells = <1>; | ||
107 | #size-cells = <0>; | ||
108 | interrupts = <56>; | ||
109 | dmas = <&sdma 27 &sdma 28>; | ||
110 | dma-names = "tx", "rx"; | ||
111 | }; | ||
112 | |||
113 | i2c2: i2c@48072000 { | ||
114 | compatible = "ti,omap2-i2c"; | ||
115 | ti,hwmods = "i2c2"; | ||
116 | reg = <0x48072000 0x80>; | ||
117 | #address-cells = <1>; | ||
118 | #size-cells = <0>; | ||
119 | interrupts = <57>; | ||
120 | dmas = <&sdma 29 &sdma 30>; | ||
121 | dma-names = "tx", "rx"; | ||
122 | }; | ||
123 | |||
124 | mcspi1: mcspi@48098000 { | ||
125 | compatible = "ti,omap2-mcspi"; | ||
126 | ti,hwmods = "mcspi1"; | ||
127 | reg = <0x48098000 0x100>; | ||
128 | interrupts = <65>; | ||
129 | dmas = <&sdma 35 &sdma 36 &sdma 37 &sdma 38 | ||
130 | &sdma 39 &sdma 40 &sdma 41 &sdma 42>; | ||
131 | dma-names = "tx0", "rx0", "tx1", "rx1", | ||
132 | "tx2", "rx2", "tx3", "rx3"; | ||
133 | }; | ||
134 | |||
135 | mcspi2: mcspi@4809a000 { | ||
136 | compatible = "ti,omap2-mcspi"; | ||
137 | ti,hwmods = "mcspi2"; | ||
138 | reg = <0x4809a000 0x100>; | ||
139 | interrupts = <66>; | ||
140 | dmas = <&sdma 43 &sdma 44 &sdma 45 &sdma 46>; | ||
141 | dma-names = "tx0", "rx0", "tx1", "rx1"; | ||
142 | }; | ||
143 | |||
144 | rng: rng@480a0000 { | ||
145 | compatible = "ti,omap2-rng"; | ||
146 | ti,hwmods = "rng"; | ||
147 | reg = <0x480a0000 0x50>; | ||
148 | interrupts = <36>; | ||
149 | }; | ||
150 | |||
151 | sham: sham@480a4000 { | ||
152 | compatible = "ti,omap2-sham"; | ||
153 | ti,hwmods = "sham"; | ||
154 | reg = <0x480a4000 0x64>; | ||
155 | interrupts = <51>; | ||
156 | dmas = <&sdma 13>; | ||
157 | dma-names = "rx"; | ||
158 | }; | ||
159 | |||
76 | uart1: serial@4806a000 { | 160 | uart1: serial@4806a000 { |
77 | compatible = "ti,omap2-uart"; | 161 | compatible = "ti,omap2-uart"; |
78 | ti,hwmods = "uart1"; | 162 | ti,hwmods = "uart1"; |
163 | reg = <0x4806a000 0x2000>; | ||
164 | interrupts = <72>; | ||
165 | dmas = <&sdma 49 &sdma 50>; | ||
166 | dma-names = "tx", "rx"; | ||
79 | clock-frequency = <48000000>; | 167 | clock-frequency = <48000000>; |
80 | }; | 168 | }; |
81 | 169 | ||
82 | uart2: serial@4806c000 { | 170 | uart2: serial@4806c000 { |
83 | compatible = "ti,omap2-uart"; | 171 | compatible = "ti,omap2-uart"; |
84 | ti,hwmods = "uart2"; | 172 | ti,hwmods = "uart2"; |
173 | reg = <0x4806c000 0x400>; | ||
174 | interrupts = <73>; | ||
175 | dmas = <&sdma 51 &sdma 52>; | ||
176 | dma-names = "tx", "rx"; | ||
85 | clock-frequency = <48000000>; | 177 | clock-frequency = <48000000>; |
86 | }; | 178 | }; |
87 | 179 | ||
88 | uart3: serial@4806e000 { | 180 | uart3: serial@4806e000 { |
89 | compatible = "ti,omap2-uart"; | 181 | compatible = "ti,omap2-uart"; |
90 | ti,hwmods = "uart3"; | 182 | ti,hwmods = "uart3"; |
183 | reg = <0x4806e000 0x400>; | ||
184 | interrupts = <74>; | ||
185 | dmas = <&sdma 53 &sdma 54>; | ||
186 | dma-names = "tx", "rx"; | ||
91 | clock-frequency = <48000000>; | 187 | clock-frequency = <48000000>; |
92 | }; | 188 | }; |
93 | 189 | ||
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index c8f9c55169ea..60c605de22dd 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi | |||
@@ -114,6 +114,15 @@ | |||
114 | dma-names = "tx", "rx"; | 114 | dma-names = "tx", "rx"; |
115 | }; | 115 | }; |
116 | 116 | ||
117 | msdi1: mmc@4809c000 { | ||
118 | compatible = "ti,omap2420-mmc"; | ||
119 | ti,hwmods = "msdi1"; | ||
120 | reg = <0x4809c000 0x80>; | ||
121 | interrupts = <83>; | ||
122 | dmas = <&sdma 61 &sdma 62>; | ||
123 | dma-names = "tx", "rx"; | ||
124 | }; | ||
125 | |||
117 | timer1: timer@48028000 { | 126 | timer1: timer@48028000 { |
118 | compatible = "ti,omap2420-timer"; | 127 | compatible = "ti,omap2420-timer"; |
119 | reg = <0x48028000 0x400>; | 128 | reg = <0x48028000 0x400>; |
@@ -121,5 +130,19 @@ | |||
121 | ti,hwmods = "timer1"; | 130 | ti,hwmods = "timer1"; |
122 | ti,timer-alwon; | 131 | ti,timer-alwon; |
123 | }; | 132 | }; |
133 | |||
134 | wd_timer2: wdt@48022000 { | ||
135 | compatible = "ti,omap2-wdt"; | ||
136 | ti,hwmods = "wd_timer2"; | ||
137 | reg = <0x48022000 0x80>; | ||
138 | }; | ||
124 | }; | 139 | }; |
125 | }; | 140 | }; |
141 | |||
142 | &i2c1 { | ||
143 | compatible = "ti,omap2420-i2c"; | ||
144 | }; | ||
145 | |||
146 | &i2c2 { | ||
147 | compatible = "ti,omap2420-i2c"; | ||
148 | }; | ||
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index c535a5a2b27f..d624345666f5 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi | |||
@@ -175,6 +175,25 @@ | |||
175 | dma-names = "tx", "rx"; | 175 | dma-names = "tx", "rx"; |
176 | }; | 176 | }; |
177 | 177 | ||
178 | mmc1: mmc@4809c000 { | ||
179 | compatible = "ti,omap2-hsmmc"; | ||
180 | reg = <0x4809c000 0x200>; | ||
181 | interrupts = <83>; | ||
182 | ti,hwmods = "mmc1"; | ||
183 | ti,dual-volt; | ||
184 | dmas = <&sdma 61>, <&sdma 62>; | ||
185 | dma-names = "tx", "rx"; | ||
186 | }; | ||
187 | |||
188 | mmc2: mmc@480b4000 { | ||
189 | compatible = "ti,omap2-hsmmc"; | ||
190 | reg = <0x480b4000 0x200>; | ||
191 | interrupts = <86>; | ||
192 | ti,hwmods = "mmc2"; | ||
193 | dmas = <&sdma 47>, <&sdma 48>; | ||
194 | dma-names = "tx", "rx"; | ||
195 | }; | ||
196 | |||
178 | timer1: timer@49018000 { | 197 | timer1: timer@49018000 { |
179 | compatible = "ti,omap2420-timer"; | 198 | compatible = "ti,omap2420-timer"; |
180 | reg = <0x49018000 0x400>; | 199 | reg = <0x49018000 0x400>; |
@@ -182,5 +201,35 @@ | |||
182 | ti,hwmods = "timer1"; | 201 | ti,hwmods = "timer1"; |
183 | ti,timer-alwon; | 202 | ti,timer-alwon; |
184 | }; | 203 | }; |
204 | |||
205 | mcspi3: mcspi@480b8000 { | ||
206 | compatible = "ti,omap2-mcspi"; | ||
207 | ti,hwmods = "mcspi3"; | ||
208 | reg = <0x480b8000 0x100>; | ||
209 | interrupts = <91>; | ||
210 | dmas = <&sdma 15 &sdma 16 &sdma 23 &sdma 24>; | ||
211 | dma-names = "tx0", "rx0", "tx1", "rx1"; | ||
212 | }; | ||
213 | |||
214 | usb_otg_hs: usb_otg_hs@480ac000 { | ||
215 | compatible = "ti,omap2-musb"; | ||
216 | ti,hwmods = "usb_otg_hs"; | ||
217 | reg = <0x480ac000 0x1000>; | ||
218 | interrupts = <93>; | ||
219 | }; | ||
220 | |||
221 | wd_timer2: wdt@49016000 { | ||
222 | compatible = "ti,omap2-wdt"; | ||
223 | ti,hwmods = "wd_timer2"; | ||
224 | reg = <0x49016000 0x80>; | ||
225 | }; | ||
185 | }; | 226 | }; |
186 | }; | 227 | }; |
228 | |||
229 | &i2c1 { | ||
230 | compatible = "ti,omap2430-i2c"; | ||
231 | }; | ||
232 | |||
233 | &i2c2 { | ||
234 | compatible = "ti,omap2430-i2c"; | ||
235 | }; | ||
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5cdaba4cea86..070c5c3a2291 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <dt-bindings/pinctrl/at91.h> | 13 | #include <dt-bindings/pinctrl/at91.h> |
14 | #include <dt-bindings/interrupt-controller/irq.h> | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | #include <dt-bindings/gpio/gpio.h> | 15 | #include <dt-bindings/gpio/gpio.h> |
16 | #include <dt-bindings/clk/at91.h> | ||
16 | 17 | ||
17 | / { | 18 | / { |
18 | model = "Atmel SAMA5D3 family SoC"; | 19 | model = "Atmel SAMA5D3 family SoC"; |
@@ -56,6 +57,14 @@ | |||
56 | reg = <0x20000000 0x8000000>; | 57 | reg = <0x20000000 0x8000000>; |
57 | }; | 58 | }; |
58 | 59 | ||
60 | clocks { | ||
61 | adc_op_clk: adc_op_clk{ | ||
62 | compatible = "fixed-clock"; | ||
63 | #clock-cells = <0>; | ||
64 | clock-frequency = <20000000>; | ||
65 | }; | ||
66 | }; | ||
67 | |||
59 | ahb { | 68 | ahb { |
60 | compatible = "simple-bus"; | 69 | compatible = "simple-bus"; |
61 | #address-cells = <1>; | 70 | #address-cells = <1>; |
@@ -79,6 +88,8 @@ | |||
79 | status = "disabled"; | 88 | status = "disabled"; |
80 | #address-cells = <1>; | 89 | #address-cells = <1>; |
81 | #size-cells = <0>; | 90 | #size-cells = <0>; |
91 | clocks = <&mci0_clk>; | ||
92 | clock-names = "mci_clk"; | ||
82 | }; | 93 | }; |
83 | 94 | ||
84 | spi0: spi@f0004000 { | 95 | spi0: spi@f0004000 { |
@@ -92,6 +103,8 @@ | |||
92 | dma-names = "tx", "rx"; | 103 | dma-names = "tx", "rx"; |
93 | pinctrl-names = "default"; | 104 | pinctrl-names = "default"; |
94 | pinctrl-0 = <&pinctrl_spi0>; | 105 | pinctrl-0 = <&pinctrl_spi0>; |
106 | clocks = <&spi0_clk>; | ||
107 | clock-names = "spi_clk"; | ||
95 | status = "disabled"; | 108 | status = "disabled"; |
96 | }; | 109 | }; |
97 | 110 | ||
@@ -101,6 +114,8 @@ | |||
101 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; | 114 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
102 | pinctrl-names = "default"; | 115 | pinctrl-names = "default"; |
103 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | 116 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; |
117 | clocks = <&ssc0_clk>; | ||
118 | clock-names = "pclk"; | ||
104 | status = "disabled"; | 119 | status = "disabled"; |
105 | }; | 120 | }; |
106 | 121 | ||
@@ -108,6 +123,8 @@ | |||
108 | compatible = "atmel,at91sam9x5-tcb"; | 123 | compatible = "atmel,at91sam9x5-tcb"; |
109 | reg = <0xf0010000 0x100>; | 124 | reg = <0xf0010000 0x100>; |
110 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; | 125 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
126 | clocks = <&tcb0_clk>; | ||
127 | clock-names = "t0_clk"; | ||
111 | }; | 128 | }; |
112 | 129 | ||
113 | i2c0: i2c@f0014000 { | 130 | i2c0: i2c@f0014000 { |
@@ -121,6 +138,7 @@ | |||
121 | pinctrl-0 = <&pinctrl_i2c0>; | 138 | pinctrl-0 = <&pinctrl_i2c0>; |
122 | #address-cells = <1>; | 139 | #address-cells = <1>; |
123 | #size-cells = <0>; | 140 | #size-cells = <0>; |
141 | clocks = <&twi0_clk>; | ||
124 | status = "disabled"; | 142 | status = "disabled"; |
125 | }; | 143 | }; |
126 | 144 | ||
@@ -135,6 +153,7 @@ | |||
135 | pinctrl-0 = <&pinctrl_i2c1>; | 153 | pinctrl-0 = <&pinctrl_i2c1>; |
136 | #address-cells = <1>; | 154 | #address-cells = <1>; |
137 | #size-cells = <0>; | 155 | #size-cells = <0>; |
156 | clocks = <&twi1_clk>; | ||
138 | status = "disabled"; | 157 | status = "disabled"; |
139 | }; | 158 | }; |
140 | 159 | ||
@@ -144,6 +163,8 @@ | |||
144 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; | 163 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
145 | pinctrl-names = "default"; | 164 | pinctrl-names = "default"; |
146 | pinctrl-0 = <&pinctrl_usart0>; | 165 | pinctrl-0 = <&pinctrl_usart0>; |
166 | clocks = <&usart0_clk>; | ||
167 | clock-names = "usart"; | ||
147 | status = "disabled"; | 168 | status = "disabled"; |
148 | }; | 169 | }; |
149 | 170 | ||
@@ -153,6 +174,8 @@ | |||
153 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; | 174 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
154 | pinctrl-names = "default"; | 175 | pinctrl-names = "default"; |
155 | pinctrl-0 = <&pinctrl_usart1>; | 176 | pinctrl-0 = <&pinctrl_usart1>; |
177 | clocks = <&usart1_clk>; | ||
178 | clock-names = "usart"; | ||
156 | status = "disabled"; | 179 | status = "disabled"; |
157 | }; | 180 | }; |
158 | 181 | ||
@@ -174,6 +197,8 @@ | |||
174 | status = "disabled"; | 197 | status = "disabled"; |
175 | #address-cells = <1>; | 198 | #address-cells = <1>; |
176 | #size-cells = <0>; | 199 | #size-cells = <0>; |
200 | clocks = <&mci1_clk>; | ||
201 | clock-names = "mci_clk"; | ||
177 | }; | 202 | }; |
178 | 203 | ||
179 | spi1: spi@f8008000 { | 204 | spi1: spi@f8008000 { |
@@ -187,6 +212,8 @@ | |||
187 | dma-names = "tx", "rx"; | 212 | dma-names = "tx", "rx"; |
188 | pinctrl-names = "default"; | 213 | pinctrl-names = "default"; |
189 | pinctrl-0 = <&pinctrl_spi1>; | 214 | pinctrl-0 = <&pinctrl_spi1>; |
215 | clocks = <&spi1_clk>; | ||
216 | clock-names = "spi_clk"; | ||
190 | status = "disabled"; | 217 | status = "disabled"; |
191 | }; | 218 | }; |
192 | 219 | ||
@@ -196,6 +223,8 @@ | |||
196 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; | 223 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
197 | pinctrl-names = "default"; | 224 | pinctrl-names = "default"; |
198 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | 225 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; |
226 | clocks = <&ssc1_clk>; | ||
227 | clock-names = "pclk"; | ||
199 | status = "disabled"; | 228 | status = "disabled"; |
200 | }; | 229 | }; |
201 | 230 | ||
@@ -219,6 +248,9 @@ | |||
219 | &pinctrl_adc0_ad10 | 248 | &pinctrl_adc0_ad10 |
220 | &pinctrl_adc0_ad11 | 249 | &pinctrl_adc0_ad11 |
221 | >; | 250 | >; |
251 | clocks = <&adc_clk>, | ||
252 | <&adc_op_clk>; | ||
253 | clock-names = "adc_clk", "adc_op_clk"; | ||
222 | atmel,adc-channel-base = <0x50>; | 254 | atmel,adc-channel-base = <0x50>; |
223 | atmel,adc-channels-used = <0xfff>; | 255 | atmel,adc-channels-used = <0xfff>; |
224 | atmel,adc-drdy-mask = <0x1000000>; | 256 | atmel,adc-drdy-mask = <0x1000000>; |
@@ -272,8 +304,11 @@ | |||
272 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, | 304 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
273 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; | 305 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; |
274 | dma-names = "tx", "rx"; | 306 | dma-names = "tx", "rx"; |
307 | pinctrl-names = "default"; | ||
308 | pinctrl-0 = <&pinctrl_i2c2>; | ||
275 | #address-cells = <1>; | 309 | #address-cells = <1>; |
276 | #size-cells = <0>; | 310 | #size-cells = <0>; |
311 | clocks = <&twi2_clk>; | ||
277 | status = "disabled"; | 312 | status = "disabled"; |
278 | }; | 313 | }; |
279 | 314 | ||
@@ -283,6 +318,8 @@ | |||
283 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; | 318 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
284 | pinctrl-names = "default"; | 319 | pinctrl-names = "default"; |
285 | pinctrl-0 = <&pinctrl_usart2>; | 320 | pinctrl-0 = <&pinctrl_usart2>; |
321 | clocks = <&usart2_clk>; | ||
322 | clock-names = "usart"; | ||
286 | status = "disabled"; | 323 | status = "disabled"; |
287 | }; | 324 | }; |
288 | 325 | ||
@@ -292,25 +329,35 @@ | |||
292 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; | 329 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
293 | pinctrl-names = "default"; | 330 | pinctrl-names = "default"; |
294 | pinctrl-0 = <&pinctrl_usart3>; | 331 | pinctrl-0 = <&pinctrl_usart3>; |
332 | clocks = <&usart3_clk>; | ||
333 | clock-names = "usart"; | ||
295 | status = "disabled"; | 334 | status = "disabled"; |
296 | }; | 335 | }; |
297 | 336 | ||
298 | sha@f8034000 { | 337 | sha@f8034000 { |
299 | compatible = "atmel,sam9g46-sha"; | 338 | compatible = "atmel,at91sam9g46-sha"; |
300 | reg = <0xf8034000 0x100>; | 339 | reg = <0xf8034000 0x100>; |
301 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; | 340 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
341 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; | ||
342 | dma-names = "tx"; | ||
302 | }; | 343 | }; |
303 | 344 | ||
304 | aes@f8038000 { | 345 | aes@f8038000 { |
305 | compatible = "atmel,sam9g46-aes"; | 346 | compatible = "atmel,at91sam9g46-aes"; |
306 | reg = <0xf8038000 0x100>; | 347 | reg = <0xf8038000 0x100>; |
307 | interrupts = <43 4 0>; | 348 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; |
349 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, | ||
350 | <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; | ||
351 | dma-names = "tx", "rx"; | ||
308 | }; | 352 | }; |
309 | 353 | ||
310 | tdes@f803c000 { | 354 | tdes@f803c000 { |
311 | compatible = "atmel,sam9g46-tdes"; | 355 | compatible = "atmel,at91sam9g46-tdes"; |
312 | reg = <0xf803c000 0x100>; | 356 | reg = <0xf803c000 0x100>; |
313 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; | 357 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
358 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, | ||
359 | <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; | ||
360 | dma-names = "tx", "rx"; | ||
314 | }; | 361 | }; |
315 | 362 | ||
316 | dma0: dma-controller@ffffe600 { | 363 | dma0: dma-controller@ffffe600 { |
@@ -318,6 +365,8 @@ | |||
318 | reg = <0xffffe600 0x200>; | 365 | reg = <0xffffe600 0x200>; |
319 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; | 366 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
320 | #dma-cells = <2>; | 367 | #dma-cells = <2>; |
368 | clocks = <&dma0_clk>; | ||
369 | clock-names = "dma_clk"; | ||
321 | }; | 370 | }; |
322 | 371 | ||
323 | dma1: dma-controller@ffffe800 { | 372 | dma1: dma-controller@ffffe800 { |
@@ -325,6 +374,8 @@ | |||
325 | reg = <0xffffe800 0x200>; | 374 | reg = <0xffffe800 0x200>; |
326 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; | 375 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
327 | #dma-cells = <2>; | 376 | #dma-cells = <2>; |
377 | clocks = <&dma1_clk>; | ||
378 | clock-names = "dma_clk"; | ||
328 | }; | 379 | }; |
329 | 380 | ||
330 | ramc0: ramc@ffffea00 { | 381 | ramc0: ramc@ffffea00 { |
@@ -338,6 +389,8 @@ | |||
338 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; | 389 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
339 | pinctrl-names = "default"; | 390 | pinctrl-names = "default"; |
340 | pinctrl-0 = <&pinctrl_dbgu>; | 391 | pinctrl-0 = <&pinctrl_dbgu>; |
392 | clocks = <&dbgu_clk>; | ||
393 | clock-names = "usart"; | ||
341 | status = "disabled"; | 394 | status = "disabled"; |
342 | }; | 395 | }; |
343 | 396 | ||
@@ -443,6 +496,14 @@ | |||
443 | }; | 496 | }; |
444 | }; | 497 | }; |
445 | 498 | ||
499 | i2c2 { | ||
500 | pinctrl_i2c2: i2c2-0 { | ||
501 | atmel,pins = | ||
502 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ | ||
503 | AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ | ||
504 | }; | ||
505 | }; | ||
506 | |||
446 | isi { | 507 | isi { |
447 | pinctrl_isi: isi-0 { | 508 | pinctrl_isi: isi-0 { |
448 | atmel,pins = | 509 | atmel,pins = |
@@ -626,6 +687,7 @@ | |||
626 | gpio-controller; | 687 | gpio-controller; |
627 | interrupt-controller; | 688 | interrupt-controller; |
628 | #interrupt-cells = <2>; | 689 | #interrupt-cells = <2>; |
690 | clocks = <&pioA_clk>; | ||
629 | }; | 691 | }; |
630 | 692 | ||
631 | pioB: gpio@fffff400 { | 693 | pioB: gpio@fffff400 { |
@@ -636,6 +698,7 @@ | |||
636 | gpio-controller; | 698 | gpio-controller; |
637 | interrupt-controller; | 699 | interrupt-controller; |
638 | #interrupt-cells = <2>; | 700 | #interrupt-cells = <2>; |
701 | clocks = <&pioB_clk>; | ||
639 | }; | 702 | }; |
640 | 703 | ||
641 | pioC: gpio@fffff600 { | 704 | pioC: gpio@fffff600 { |
@@ -646,6 +709,7 @@ | |||
646 | gpio-controller; | 709 | gpio-controller; |
647 | interrupt-controller; | 710 | interrupt-controller; |
648 | #interrupt-cells = <2>; | 711 | #interrupt-cells = <2>; |
712 | clocks = <&pioC_clk>; | ||
649 | }; | 713 | }; |
650 | 714 | ||
651 | pioD: gpio@fffff800 { | 715 | pioD: gpio@fffff800 { |
@@ -656,6 +720,7 @@ | |||
656 | gpio-controller; | 720 | gpio-controller; |
657 | interrupt-controller; | 721 | interrupt-controller; |
658 | #interrupt-cells = <2>; | 722 | #interrupt-cells = <2>; |
723 | clocks = <&pioD_clk>; | ||
659 | }; | 724 | }; |
660 | 725 | ||
661 | pioE: gpio@fffffa00 { | 726 | pioE: gpio@fffffa00 { |
@@ -666,12 +731,334 @@ | |||
666 | gpio-controller; | 731 | gpio-controller; |
667 | interrupt-controller; | 732 | interrupt-controller; |
668 | #interrupt-cells = <2>; | 733 | #interrupt-cells = <2>; |
734 | clocks = <&pioE_clk>; | ||
669 | }; | 735 | }; |
670 | }; | 736 | }; |
671 | 737 | ||
672 | pmc: pmc@fffffc00 { | 738 | pmc: pmc@fffffc00 { |
673 | compatible = "atmel,at91rm9200-pmc"; | 739 | compatible = "atmel,sama5d3-pmc"; |
674 | reg = <0xfffffc00 0x120>; | 740 | reg = <0xfffffc00 0x120>; |
741 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | ||
742 | interrupt-controller; | ||
743 | #address-cells = <1>; | ||
744 | #size-cells = <0>; | ||
745 | #interrupt-cells = <1>; | ||
746 | |||
747 | clk32k: slck { | ||
748 | compatible = "fixed-clock"; | ||
749 | #clock-cells = <0>; | ||
750 | clock-frequency = <32768>; | ||
751 | }; | ||
752 | |||
753 | main: mainck { | ||
754 | compatible = "atmel,at91rm9200-clk-main"; | ||
755 | #clock-cells = <0>; | ||
756 | interrupt-parent = <&pmc>; | ||
757 | interrupts = <AT91_PMC_MOSCS>; | ||
758 | clocks = <&clk32k>; | ||
759 | }; | ||
760 | |||
761 | plla: pllack { | ||
762 | compatible = "atmel,sama5d3-clk-pll"; | ||
763 | #clock-cells = <0>; | ||
764 | interrupt-parent = <&pmc>; | ||
765 | interrupts = <AT91_PMC_LOCKA>; | ||
766 | clocks = <&main>; | ||
767 | reg = <0>; | ||
768 | atmel,clk-input-range = <8000000 50000000>; | ||
769 | #atmel,pll-clk-output-range-cells = <4>; | ||
770 | atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; | ||
771 | }; | ||
772 | |||
773 | plladiv: plladivck { | ||
774 | compatible = "atmel,at91sam9x5-clk-plldiv"; | ||
775 | #clock-cells = <0>; | ||
776 | clocks = <&plla>; | ||
777 | }; | ||
778 | |||
779 | utmi: utmick { | ||
780 | compatible = "atmel,at91sam9x5-clk-utmi"; | ||
781 | #clock-cells = <0>; | ||
782 | interrupt-parent = <&pmc>; | ||
783 | interrupts = <AT91_PMC_LOCKU>; | ||
784 | clocks = <&main>; | ||
785 | }; | ||
786 | |||
787 | mck: masterck { | ||
788 | compatible = "atmel,at91sam9x5-clk-master"; | ||
789 | #clock-cells = <0>; | ||
790 | interrupt-parent = <&pmc>; | ||
791 | interrupts = <AT91_PMC_MCKRDY>; | ||
792 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | ||
793 | atmel,clk-output-range = <0 166000000>; | ||
794 | atmel,clk-divisors = <1 2 4 3>; | ||
795 | }; | ||
796 | |||
797 | usb: usbck { | ||
798 | compatible = "atmel,at91sam9x5-clk-usb"; | ||
799 | #clock-cells = <0>; | ||
800 | clocks = <&plladiv>, <&utmi>; | ||
801 | }; | ||
802 | |||
803 | prog: progck { | ||
804 | compatible = "atmel,at91sam9x5-clk-programmable"; | ||
805 | #address-cells = <1>; | ||
806 | #size-cells = <0>; | ||
807 | interrupt-parent = <&pmc>; | ||
808 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | ||
809 | |||
810 | prog0: prog0 { | ||
811 | #clock-cells = <0>; | ||
812 | reg = <0>; | ||
813 | interrupts = <AT91_PMC_PCKRDY(0)>; | ||
814 | }; | ||
815 | |||
816 | prog1: prog1 { | ||
817 | #clock-cells = <0>; | ||
818 | reg = <1>; | ||
819 | interrupts = <AT91_PMC_PCKRDY(1)>; | ||
820 | }; | ||
821 | |||
822 | prog2: prog2 { | ||
823 | #clock-cells = <0>; | ||
824 | reg = <2>; | ||
825 | interrupts = <AT91_PMC_PCKRDY(2)>; | ||
826 | }; | ||
827 | }; | ||
828 | |||
829 | smd: smdclk { | ||
830 | compatible = "atmel,at91sam9x5-clk-smd"; | ||
831 | #clock-cells = <0>; | ||
832 | clocks = <&plladiv>, <&utmi>; | ||
833 | }; | ||
834 | |||
835 | systemck { | ||
836 | compatible = "atmel,at91rm9200-clk-system"; | ||
837 | #address-cells = <1>; | ||
838 | #size-cells = <0>; | ||
839 | |||
840 | ddrck: ddrck { | ||
841 | #clock-cells = <0>; | ||
842 | reg = <2>; | ||
843 | clocks = <&mck>; | ||
844 | }; | ||
845 | |||
846 | smdck: smdck { | ||
847 | #clock-cells = <0>; | ||
848 | reg = <4>; | ||
849 | clocks = <&smd>; | ||
850 | }; | ||
851 | |||
852 | uhpck: uhpck { | ||
853 | #clock-cells = <0>; | ||
854 | reg = <6>; | ||
855 | clocks = <&usb>; | ||
856 | }; | ||
857 | |||
858 | udpck: udpck { | ||
859 | #clock-cells = <0>; | ||
860 | reg = <7>; | ||
861 | clocks = <&usb>; | ||
862 | }; | ||
863 | |||
864 | pck0: pck0 { | ||
865 | #clock-cells = <0>; | ||
866 | reg = <8>; | ||
867 | clocks = <&prog0>; | ||
868 | }; | ||
869 | |||
870 | pck1: pck1 { | ||
871 | #clock-cells = <0>; | ||
872 | reg = <9>; | ||
873 | clocks = <&prog1>; | ||
874 | }; | ||
875 | |||
876 | pck2: pck2 { | ||
877 | #clock-cells = <0>; | ||
878 | reg = <10>; | ||
879 | clocks = <&prog2>; | ||
880 | }; | ||
881 | }; | ||
882 | |||
883 | periphck { | ||
884 | compatible = "atmel,at91sam9x5-clk-peripheral"; | ||
885 | #address-cells = <1>; | ||
886 | #size-cells = <0>; | ||
887 | clocks = <&mck>; | ||
888 | |||
889 | dbgu_clk: dbgu_clk { | ||
890 | #clock-cells = <0>; | ||
891 | reg = <2>; | ||
892 | }; | ||
893 | |||
894 | pioA_clk: pioA_clk { | ||
895 | #clock-cells = <0>; | ||
896 | reg = <6>; | ||
897 | }; | ||
898 | |||
899 | pioB_clk: pioB_clk { | ||
900 | #clock-cells = <0>; | ||
901 | reg = <7>; | ||
902 | }; | ||
903 | |||
904 | pioC_clk: pioC_clk { | ||
905 | #clock-cells = <0>; | ||
906 | reg = <8>; | ||
907 | }; | ||
908 | |||
909 | pioD_clk: pioD_clk { | ||
910 | #clock-cells = <0>; | ||
911 | reg = <9>; | ||
912 | }; | ||
913 | |||
914 | pioE_clk: pioE_clk { | ||
915 | #clock-cells = <0>; | ||
916 | reg = <10>; | ||
917 | }; | ||
918 | |||
919 | usart0_clk: usart0_clk { | ||
920 | #clock-cells = <0>; | ||
921 | reg = <12>; | ||
922 | atmel,clk-output-range = <0 66000000>; | ||
923 | }; | ||
924 | |||
925 | usart1_clk: usart1_clk { | ||
926 | #clock-cells = <0>; | ||
927 | reg = <13>; | ||
928 | atmel,clk-output-range = <0 66000000>; | ||
929 | }; | ||
930 | |||
931 | usart2_clk: usart2_clk { | ||
932 | #clock-cells = <0>; | ||
933 | reg = <14>; | ||
934 | atmel,clk-output-range = <0 66000000>; | ||
935 | }; | ||
936 | |||
937 | usart3_clk: usart3_clk { | ||
938 | #clock-cells = <0>; | ||
939 | reg = <15>; | ||
940 | atmel,clk-output-range = <0 66000000>; | ||
941 | }; | ||
942 | |||
943 | twi0_clk: twi0_clk { | ||
944 | reg = <18>; | ||
945 | #clock-cells = <0>; | ||
946 | atmel,clk-output-range = <0 16625000>; | ||
947 | }; | ||
948 | |||
949 | twi1_clk: twi1_clk { | ||
950 | #clock-cells = <0>; | ||
951 | reg = <19>; | ||
952 | atmel,clk-output-range = <0 16625000>; | ||
953 | }; | ||
954 | |||
955 | twi2_clk: twi2_clk { | ||
956 | #clock-cells = <0>; | ||
957 | reg = <20>; | ||
958 | atmel,clk-output-range = <0 16625000>; | ||
959 | }; | ||
960 | |||
961 | mci0_clk: mci0_clk { | ||
962 | #clock-cells = <0>; | ||
963 | reg = <21>; | ||
964 | }; | ||
965 | |||
966 | mci1_clk: mci1_clk { | ||
967 | #clock-cells = <0>; | ||
968 | reg = <22>; | ||
969 | }; | ||
970 | |||
971 | spi0_clk: spi0_clk { | ||
972 | #clock-cells = <0>; | ||
973 | reg = <24>; | ||
974 | atmel,clk-output-range = <0 133000000>; | ||
975 | }; | ||
976 | |||
977 | spi1_clk: spi1_clk { | ||
978 | #clock-cells = <0>; | ||
979 | reg = <25>; | ||
980 | atmel,clk-output-range = <0 133000000>; | ||
981 | }; | ||
982 | |||
983 | tcb0_clk: tcb0_clk { | ||
984 | #clock-cells = <0>; | ||
985 | reg = <26>; | ||
986 | atmel,clk-output-range = <0 133000000>; | ||
987 | }; | ||
988 | |||
989 | pwm_clk: pwm_clk { | ||
990 | #clock-cells = <0>; | ||
991 | reg = <28>; | ||
992 | }; | ||
993 | |||
994 | adc_clk: adc_clk { | ||
995 | #clock-cells = <0>; | ||
996 | reg = <29>; | ||
997 | atmel,clk-output-range = <0 66000000>; | ||
998 | }; | ||
999 | |||
1000 | dma0_clk: dma0_clk { | ||
1001 | #clock-cells = <0>; | ||
1002 | reg = <30>; | ||
1003 | }; | ||
1004 | |||
1005 | dma1_clk: dma1_clk { | ||
1006 | #clock-cells = <0>; | ||
1007 | reg = <31>; | ||
1008 | }; | ||
1009 | |||
1010 | uhphs_clk: uhphs_clk { | ||
1011 | #clock-cells = <0>; | ||
1012 | reg = <32>; | ||
1013 | }; | ||
1014 | |||
1015 | udphs_clk: udphs_clk { | ||
1016 | #clock-cells = <0>; | ||
1017 | reg = <33>; | ||
1018 | }; | ||
1019 | |||
1020 | isi_clk: isi_clk { | ||
1021 | #clock-cells = <0>; | ||
1022 | reg = <37>; | ||
1023 | }; | ||
1024 | |||
1025 | ssc0_clk: ssc0_clk { | ||
1026 | #clock-cells = <0>; | ||
1027 | reg = <38>; | ||
1028 | atmel,clk-output-range = <0 66000000>; | ||
1029 | }; | ||
1030 | |||
1031 | ssc1_clk: ssc1_clk { | ||
1032 | #clock-cells = <0>; | ||
1033 | reg = <39>; | ||
1034 | atmel,clk-output-range = <0 66000000>; | ||
1035 | }; | ||
1036 | |||
1037 | sha_clk: sha_clk { | ||
1038 | #clock-cells = <0>; | ||
1039 | reg = <42>; | ||
1040 | }; | ||
1041 | |||
1042 | aes_clk: aes_clk { | ||
1043 | #clock-cells = <0>; | ||
1044 | reg = <43>; | ||
1045 | }; | ||
1046 | |||
1047 | tdes_clk: tdes_clk { | ||
1048 | #clock-cells = <0>; | ||
1049 | reg = <44>; | ||
1050 | }; | ||
1051 | |||
1052 | trng_clk: trng_clk { | ||
1053 | #clock-cells = <0>; | ||
1054 | reg = <45>; | ||
1055 | }; | ||
1056 | |||
1057 | fuse_clk: fuse_clk { | ||
1058 | #clock-cells = <0>; | ||
1059 | reg = <48>; | ||
1060 | }; | ||
1061 | }; | ||
675 | }; | 1062 | }; |
676 | 1063 | ||
677 | rstc@fffffe00 { | 1064 | rstc@fffffe00 { |
@@ -683,6 +1070,7 @@ | |||
683 | compatible = "atmel,at91sam9260-pit"; | 1070 | compatible = "atmel,at91sam9260-pit"; |
684 | reg = <0xfffffe30 0xf>; | 1071 | reg = <0xfffffe30 0xf>; |
685 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; | 1072 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
1073 | clocks = <&mck>; | ||
686 | }; | 1074 | }; |
687 | 1075 | ||
688 | watchdog@fffffe40 { | 1076 | watchdog@fffffe40 { |
@@ -705,6 +1093,8 @@ | |||
705 | reg = <0x00500000 0x100000 | 1093 | reg = <0x00500000 0x100000 |
706 | 0xf8030000 0x4000>; | 1094 | 0xf8030000 0x4000>; |
707 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; | 1095 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
1096 | clocks = <&udphs_clk>, <&utmi>; | ||
1097 | clock-names = "pclk", "hclk"; | ||
708 | status = "disabled"; | 1098 | status = "disabled"; |
709 | 1099 | ||
710 | ep0 { | 1100 | ep0 { |
@@ -817,6 +1207,9 @@ | |||
817 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | 1207 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
818 | reg = <0x00600000 0x100000>; | 1208 | reg = <0x00600000 0x100000>; |
819 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; | 1209 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
1210 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, | ||
1211 | <&uhpck>; | ||
1212 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | ||
820 | status = "disabled"; | 1213 | status = "disabled"; |
821 | }; | 1214 | }; |
822 | 1215 | ||
@@ -824,6 +1217,8 @@ | |||
824 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | 1217 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
825 | reg = <0x00700000 0x100000>; | 1218 | reg = <0x00700000 0x100000>; |
826 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; | 1219 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
1220 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; | ||
1221 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | ||
827 | status = "disabled"; | 1222 | status = "disabled"; |
828 | }; | 1223 | }; |
829 | 1224 | ||
diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 8ed3260cef66..a0775851cce5 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi | |||
@@ -32,12 +32,30 @@ | |||
32 | 32 | ||
33 | }; | 33 | }; |
34 | 34 | ||
35 | pmc: pmc@fffffc00 { | ||
36 | periphck { | ||
37 | can0_clk: can0_clk { | ||
38 | #clock-cells = <0>; | ||
39 | reg = <40>; | ||
40 | atmel,clk-output-range = <0 66000000>; | ||
41 | }; | ||
42 | |||
43 | can1_clk: can0_clk { | ||
44 | #clock-cells = <0>; | ||
45 | reg = <41>; | ||
46 | atmel,clk-output-range = <0 66000000>; | ||
47 | }; | ||
48 | }; | ||
49 | }; | ||
50 | |||
35 | can0: can@f000c000 { | 51 | can0: can@f000c000 { |
36 | compatible = "atmel,at91sam9x5-can"; | 52 | compatible = "atmel,at91sam9x5-can"; |
37 | reg = <0xf000c000 0x300>; | 53 | reg = <0xf000c000 0x300>; |
38 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; | 54 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; |
39 | pinctrl-names = "default"; | 55 | pinctrl-names = "default"; |
40 | pinctrl-0 = <&pinctrl_can0_rx_tx>; | 56 | pinctrl-0 = <&pinctrl_can0_rx_tx>; |
57 | clocks = <&can0_clk>; | ||
58 | clock-names = "can_clk"; | ||
41 | status = "disabled"; | 59 | status = "disabled"; |
42 | }; | 60 | }; |
43 | 61 | ||
@@ -47,6 +65,8 @@ | |||
47 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; | 65 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; |
48 | pinctrl-names = "default"; | 66 | pinctrl-names = "default"; |
49 | pinctrl-0 = <&pinctrl_can1_rx_tx>; | 67 | pinctrl-0 = <&pinctrl_can1_rx_tx>; |
68 | clocks = <&can1_clk>; | ||
69 | clock-names = "can_clk"; | ||
50 | status = "disabled"; | 70 | status = "disabled"; |
51 | }; | 71 | }; |
52 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 4d4f351f1f9f..fe2af9276312 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi | |||
@@ -31,12 +31,23 @@ | |||
31 | }; | 31 | }; |
32 | }; | 32 | }; |
33 | 33 | ||
34 | pmc: pmc@fffffc00 { | ||
35 | periphck { | ||
36 | macb1_clk: macb1_clk { | ||
37 | #clock-cells = <0>; | ||
38 | reg = <35>; | ||
39 | }; | ||
40 | }; | ||
41 | }; | ||
42 | |||
34 | macb1: ethernet@f802c000 { | 43 | macb1: ethernet@f802c000 { |
35 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; | 44 | compatible = "cdns,at32ap7000-macb", "cdns,macb"; |
36 | reg = <0xf802c000 0x100>; | 45 | reg = <0xf802c000 0x100>; |
37 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; | 46 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; |
38 | pinctrl-names = "default"; | 47 | pinctrl-names = "default"; |
39 | pinctrl-0 = <&pinctrl_macb1_rmii>; | 48 | pinctrl-0 = <&pinctrl_macb1_rmii>; |
49 | clocks = <&macb1_clk>, <&macb1_clk>; | ||
50 | clock-names = "hclk", "pclk"; | ||
40 | status = "disabled"; | 51 | status = "disabled"; |
41 | }; | 52 | }; |
42 | }; | 53 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 0ba8be30ccd8..a6cb0508762f 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi | |||
@@ -64,12 +64,23 @@ | |||
64 | }; | 64 | }; |
65 | }; | 65 | }; |
66 | 66 | ||
67 | pmc: pmc@fffffc00 { | ||
68 | periphck { | ||
69 | macb0_clk: macb0_clk { | ||
70 | #clock-cells = <0>; | ||
71 | reg = <34>; | ||
72 | }; | ||
73 | }; | ||
74 | }; | ||
75 | |||
67 | macb0: ethernet@f0028000 { | 76 | macb0: ethernet@f0028000 { |
68 | compatible = "cdns,pc302-gem", "cdns,gem"; | 77 | compatible = "cdns,pc302-gem", "cdns,gem"; |
69 | reg = <0xf0028000 0x100>; | 78 | reg = <0xf0028000 0x100>; |
70 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; | 79 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; |
71 | pinctrl-names = "default"; | 80 | pinctrl-names = "default"; |
72 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; | 81 | pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; |
82 | clocks = <&macb0_clk>, <&macb0_clk>; | ||
83 | clock-names = "hclk", "pclk"; | ||
73 | status = "disabled"; | 84 | status = "disabled"; |
74 | }; | 85 | }; |
75 | }; | 86 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 01f52a79f8ba..85d302701565 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi | |||
@@ -50,6 +50,23 @@ | |||
50 | }; | 50 | }; |
51 | }; | 51 | }; |
52 | }; | 52 | }; |
53 | |||
54 | pmc: pmc@fffffc00 { | ||
55 | periphck { | ||
56 | lcdc_clk: lcdc_clk { | ||
57 | #clock-cells = <0>; | ||
58 | reg = <36>; | ||
59 | }; | ||
60 | }; | ||
61 | |||
62 | systemck { | ||
63 | lcdck: lcdck { | ||
64 | #clock-cells = <0>; | ||
65 | reg = <3>; | ||
66 | clocks = <&mck>; | ||
67 | }; | ||
68 | }; | ||
69 | }; | ||
53 | }; | 70 | }; |
54 | }; | 71 | }; |
55 | }; | 72 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 38e88e39e551..b029fe7ef17a 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi | |||
@@ -9,6 +9,7 @@ | |||
9 | 9 | ||
10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
12 | #include <dt-bindings/clk/at91.h> | ||
12 | 13 | ||
13 | / { | 14 | / { |
14 | ahb { | 15 | ahb { |
@@ -30,6 +31,15 @@ | |||
30 | }; | 31 | }; |
31 | }; | 32 | }; |
32 | 33 | ||
34 | pmc: pmc@fffffc00 { | ||
35 | periphck { | ||
36 | mci2_clk: mci2_clk { | ||
37 | #clock-cells = <0>; | ||
38 | reg = <23>; | ||
39 | }; | ||
40 | }; | ||
41 | }; | ||
42 | |||
33 | mmc2: mmc@f8004000 { | 43 | mmc2: mmc@f8004000 { |
34 | compatible = "atmel,hsmci"; | 44 | compatible = "atmel,hsmci"; |
35 | reg = <0xf8004000 0x600>; | 45 | reg = <0xf8004000 0x600>; |
@@ -38,6 +48,8 @@ | |||
38 | dma-names = "rxtx"; | 48 | dma-names = "rxtx"; |
39 | pinctrl-names = "default"; | 49 | pinctrl-names = "default"; |
40 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; | 50 | pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; |
51 | clocks = <&mci2_clk>; | ||
52 | clock-names = "mci_clk"; | ||
41 | status = "disabled"; | 53 | status = "disabled"; |
42 | #address-cells = <1>; | 54 | #address-cells = <1>; |
43 | #size-cells = <0>; | 55 | #size-cells = <0>; |
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 5264bb4a6998..382b04431f66 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi | |||
@@ -9,6 +9,7 @@ | |||
9 | 9 | ||
10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
12 | #include <dt-bindings/clk/at91.h> | ||
12 | 13 | ||
13 | / { | 14 | / { |
14 | aliases { | 15 | aliases { |
@@ -17,10 +18,21 @@ | |||
17 | 18 | ||
18 | ahb { | 19 | ahb { |
19 | apb { | 20 | apb { |
21 | pmc: pmc@fffffc00 { | ||
22 | periphck { | ||
23 | tcb1_clk: tcb1_clk { | ||
24 | #clock-cells = <0>; | ||
25 | reg = <27>; | ||
26 | }; | ||
27 | }; | ||
28 | }; | ||
29 | |||
20 | tcb1: timer@f8014000 { | 30 | tcb1: timer@f8014000 { |
21 | compatible = "atmel,at91sam9x5-tcb"; | 31 | compatible = "atmel,at91sam9x5-tcb"; |
22 | reg = <0xf8014000 0x100>; | 32 | reg = <0xf8014000 0x100>; |
23 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; | 33 | interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; |
34 | clocks = <&tcb1_clk>; | ||
35 | clock-names = "t0_clk"; | ||
24 | }; | 36 | }; |
25 | }; | 37 | }; |
26 | }; | 38 | }; |
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 98fcb2d57446..a9fa75e41652 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi | |||
@@ -9,8 +9,14 @@ | |||
9 | 9 | ||
10 | #include <dt-bindings/pinctrl/at91.h> | 10 | #include <dt-bindings/pinctrl/at91.h> |
11 | #include <dt-bindings/interrupt-controller/irq.h> | 11 | #include <dt-bindings/interrupt-controller/irq.h> |
12 | #include <dt-bindings/clk/at91.h> | ||
12 | 13 | ||
13 | / { | 14 | / { |
15 | aliases { | ||
16 | serial5 = &uart0; | ||
17 | serial6 = &uart1; | ||
18 | }; | ||
19 | |||
14 | ahb { | 20 | ahb { |
15 | apb { | 21 | apb { |
16 | pinctrl@fffff200 { | 22 | pinctrl@fffff200 { |
@@ -31,12 +37,30 @@ | |||
31 | }; | 37 | }; |
32 | }; | 38 | }; |
33 | 39 | ||
40 | pmc: pmc@fffffc00 { | ||
41 | periphck { | ||
42 | uart0_clk: uart0_clk { | ||
43 | #clock-cells = <0>; | ||
44 | reg = <16>; | ||
45 | atmel,clk-output-range = <0 66000000>; | ||
46 | }; | ||
47 | |||
48 | uart1_clk: uart1_clk { | ||
49 | #clock-cells = <0>; | ||
50 | reg = <17>; | ||
51 | atmel,clk-output-range = <0 66000000>; | ||
52 | }; | ||
53 | }; | ||
54 | }; | ||
55 | |||
34 | uart0: serial@f0024000 { | 56 | uart0: serial@f0024000 { |
35 | compatible = "atmel,at91sam9260-usart"; | 57 | compatible = "atmel,at91sam9260-usart"; |
36 | reg = <0xf0024000 0x200>; | 58 | reg = <0xf0024000 0x200>; |
37 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; | 59 | interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; |
38 | pinctrl-names = "default"; | 60 | pinctrl-names = "default"; |
39 | pinctrl-0 = <&pinctrl_uart0>; | 61 | pinctrl-0 = <&pinctrl_uart0>; |
62 | clocks = <&uart0_clk>; | ||
63 | clock-names = "usart"; | ||
40 | status = "disabled"; | 64 | status = "disabled"; |
41 | }; | 65 | }; |
42 | 66 | ||
@@ -46,6 +70,8 @@ | |||
46 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; | 70 | interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; |
47 | pinctrl-names = "default"; | 71 | pinctrl-names = "default"; |
48 | pinctrl-0 = <&pinctrl_uart1>; | 72 | pinctrl-0 = <&pinctrl_uart1>; |
73 | clocks = <&uart1_clk>; | ||
74 | clock-names = "usart"; | ||
49 | status = "disabled"; | 75 | status = "disabled"; |
50 | }; | 76 | }; |
51 | }; | 77 | }; |
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 726a0f35100c..f55ed072c8e6 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi | |||
@@ -18,17 +18,6 @@ | |||
18 | reg = <0x20000000 0x20000000>; | 18 | reg = <0x20000000 0x20000000>; |
19 | }; | 19 | }; |
20 | 20 | ||
21 | clocks { | ||
22 | #address-cells = <1>; | ||
23 | #size-cells = <1>; | ||
24 | ranges; | ||
25 | |||
26 | main_clock: clock@0 { | ||
27 | compatible = "atmel,osc", "fixed-clock"; | ||
28 | clock-frequency = <12000000>; | ||
29 | }; | ||
30 | }; | ||
31 | |||
32 | ahb { | 21 | ahb { |
33 | apb { | 22 | apb { |
34 | spi0: spi@f0004000 { | 23 | spi0: spi@f0004000 { |
@@ -38,6 +27,12 @@ | |||
38 | macb0: ethernet@f0028000 { | 27 | macb0: ethernet@f0028000 { |
39 | phy-mode = "rgmii"; | 28 | phy-mode = "rgmii"; |
40 | }; | 29 | }; |
30 | |||
31 | pmc: pmc@fffffc00 { | ||
32 | main: mainck { | ||
33 | clock-frequency = <12000000>; | ||
34 | }; | ||
35 | }; | ||
41 | }; | 36 | }; |
42 | 37 | ||
43 | nand0: nand@60000000 { | 38 | nand0: nand@60000000 { |
diff --git a/arch/arm/boot/dts/sama5d3xdm.dtsi b/arch/arm/boot/dts/sama5d3xdm.dtsi index 1c296d6b2f2a..f9bdde542ced 100644 --- a/arch/arm/boot/dts/sama5d3xdm.dtsi +++ b/arch/arm/boot/dts/sama5d3xdm.dtsi | |||
@@ -18,6 +18,7 @@ | |||
18 | interrupts = <31 0x0>; | 18 | interrupts = <31 0x0>; |
19 | pinctrl-names = "default"; | 19 | pinctrl-names = "default"; |
20 | pinctrl-0 = <&pinctrl_qt1070_irq>; | 20 | pinctrl-0 = <&pinctrl_qt1070_irq>; |
21 | wakeup-source; | ||
21 | }; | 22 | }; |
22 | }; | 23 | }; |
23 | 24 | ||
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig index 1ce39940795d..cb26c62dc722 100644 --- a/arch/arm/configs/ape6evm_defconfig +++ b/arch/arm/configs/ape6evm_defconfig | |||
@@ -13,7 +13,7 @@ CONFIG_EMBEDDED=y | |||
13 | CONFIG_PERF_EVENTS=y | 13 | CONFIG_PERF_EVENTS=y |
14 | CONFIG_SLAB=y | 14 | CONFIG_SLAB=y |
15 | # CONFIG_BLOCK is not set | 15 | # CONFIG_BLOCK is not set |
16 | CONFIG_ARCH_SHMOBILE=y | 16 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
17 | CONFIG_ARCH_R8A73A4=y | 17 | CONFIG_ARCH_R8A73A4=y |
18 | CONFIG_MACH_APE6EVM=y | 18 | CONFIG_MACH_APE6EVM=y |
19 | # CONFIG_ARM_THUMB is not set | 19 | # CONFIG_ARM_THUMB is not set |
diff --git a/arch/arm/configs/armadillo800eva_defconfig b/arch/arm/configs/armadillo800eva_defconfig index fae939d3d7f0..5abf1a2e3160 100644 --- a/arch/arm/configs/armadillo800eva_defconfig +++ b/arch/arm/configs/armadillo800eva_defconfig | |||
@@ -15,7 +15,7 @@ CONFIG_MODULE_FORCE_UNLOAD=y | |||
15 | # CONFIG_BLK_DEV_BSG is not set | 15 | # CONFIG_BLK_DEV_BSG is not set |
16 | # CONFIG_IOSCHED_DEADLINE is not set | 16 | # CONFIG_IOSCHED_DEADLINE is not set |
17 | # CONFIG_IOSCHED_CFQ is not set | 17 | # CONFIG_IOSCHED_CFQ is not set |
18 | CONFIG_ARCH_SHMOBILE=y | 18 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
19 | CONFIG_ARCH_R8A7740=y | 19 | CONFIG_ARCH_R8A7740=y |
20 | CONFIG_MACH_ARMADILLO800EVA=y | 20 | CONFIG_MACH_ARMADILLO800EVA=y |
21 | # CONFIG_SH_TIMER_TMU is not set | 21 | # CONFIG_SH_TIMER_TMU is not set |
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig index b38cd107f82d..1dd39716d7cb 100644 --- a/arch/arm/configs/bockw_defconfig +++ b/arch/arm/configs/bockw_defconfig | |||
@@ -8,7 +8,7 @@ CONFIG_SYSCTL_SYSCALL=y | |||
8 | CONFIG_EMBEDDED=y | 8 | CONFIG_EMBEDDED=y |
9 | CONFIG_SLAB=y | 9 | CONFIG_SLAB=y |
10 | # CONFIG_IOSCHED_CFQ is not set | 10 | # CONFIG_IOSCHED_CFQ is not set |
11 | CONFIG_ARCH_SHMOBILE=y | 11 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
12 | CONFIG_ARCH_R8A7778=y | 12 | CONFIG_ARCH_R8A7778=y |
13 | CONFIG_MACH_BOCKW=y | 13 | CONFIG_MACH_BOCKW=y |
14 | CONFIG_MEMORY_START=0x60000000 | 14 | CONFIG_MEMORY_START=0x60000000 |
diff --git a/arch/arm/configs/koelsch_defconfig b/arch/arm/configs/koelsch_defconfig index 825c16dee8a0..7fd65a01ec7e 100644 --- a/arch/arm/configs/koelsch_defconfig +++ b/arch/arm/configs/koelsch_defconfig | |||
@@ -9,7 +9,7 @@ CONFIG_EMBEDDED=y | |||
9 | CONFIG_PERF_EVENTS=y | 9 | CONFIG_PERF_EVENTS=y |
10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
11 | # CONFIG_BLOCK is not set | 11 | # CONFIG_BLOCK is not set |
12 | CONFIG_ARCH_SHMOBILE=y | 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
13 | CONFIG_ARCH_R8A7791=y | 13 | CONFIG_ARCH_R8A7791=y |
14 | CONFIG_MACH_KOELSCH=y | 14 | CONFIG_MACH_KOELSCH=y |
15 | # CONFIG_SWP_EMULATE is not set | 15 | # CONFIG_SWP_EMULATE is not set |
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig index 6c37f4a98eb8..217f1dda2965 100644 --- a/arch/arm/configs/kzm9d_defconfig +++ b/arch/arm/configs/kzm9d_defconfig | |||
@@ -13,7 +13,7 @@ CONFIG_SLAB=y | |||
13 | # CONFIG_BLK_DEV_BSG is not set | 13 | # CONFIG_BLK_DEV_BSG is not set |
14 | # CONFIG_IOSCHED_DEADLINE is not set | 14 | # CONFIG_IOSCHED_DEADLINE is not set |
15 | # CONFIG_IOSCHED_CFQ is not set | 15 | # CONFIG_IOSCHED_CFQ is not set |
16 | CONFIG_ARCH_SHMOBILE=y | 16 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
17 | CONFIG_ARCH_EMEV2=y | 17 | CONFIG_ARCH_EMEV2=y |
18 | CONFIG_MACH_KZM9D=y | 18 | CONFIG_MACH_KZM9D=y |
19 | CONFIG_MEMORY_START=0x40000000 | 19 | CONFIG_MEMORY_START=0x40000000 |
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig index 1ad028023a64..9934dbc23d64 100644 --- a/arch/arm/configs/kzm9g_defconfig +++ b/arch/arm/configs/kzm9g_defconfig | |||
@@ -22,7 +22,7 @@ CONFIG_MODULE_UNLOAD=y | |||
22 | # CONFIG_BLK_DEV_BSG is not set | 22 | # CONFIG_BLK_DEV_BSG is not set |
23 | # CONFIG_IOSCHED_DEADLINE is not set | 23 | # CONFIG_IOSCHED_DEADLINE is not set |
24 | # CONFIG_IOSCHED_CFQ is not set | 24 | # CONFIG_IOSCHED_CFQ is not set |
25 | CONFIG_ARCH_SHMOBILE=y | 25 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
26 | CONFIG_ARCH_SH73A0=y | 26 | CONFIG_ARCH_SH73A0=y |
27 | CONFIG_MACH_KZM9G=y | 27 | CONFIG_MACH_KZM9G=y |
28 | CONFIG_MEMORY_START=0x41000000 | 28 | CONFIG_MEMORY_START=0x41000000 |
diff --git a/arch/arm/configs/lager_defconfig b/arch/arm/configs/lager_defconfig index 35bff5e0d57a..35dc8b2be47f 100644 --- a/arch/arm/configs/lager_defconfig +++ b/arch/arm/configs/lager_defconfig | |||
@@ -12,7 +12,7 @@ CONFIG_SLAB=y | |||
12 | # CONFIG_BLK_DEV_BSG is not set | 12 | # CONFIG_BLK_DEV_BSG is not set |
13 | # CONFIG_IOSCHED_DEADLINE is not set | 13 | # CONFIG_IOSCHED_DEADLINE is not set |
14 | # CONFIG_IOSCHED_CFQ is not set | 14 | # CONFIG_IOSCHED_CFQ is not set |
15 | CONFIG_ARCH_SHMOBILE=y | 15 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
16 | CONFIG_ARCH_R8A7790=y | 16 | CONFIG_ARCH_R8A7790=y |
17 | CONFIG_MACH_LAGER=y | 17 | CONFIG_MACH_LAGER=y |
18 | # CONFIG_SH_TIMER_TMU is not set | 18 | # CONFIG_SH_TIMER_TMU is not set |
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig index 9fb11895b2e2..a61e1653fc5e 100644 --- a/arch/arm/configs/mackerel_defconfig +++ b/arch/arm/configs/mackerel_defconfig | |||
@@ -14,7 +14,7 @@ CONFIG_MODULE_UNLOAD=y | |||
14 | # CONFIG_BLK_DEV_BSG is not set | 14 | # CONFIG_BLK_DEV_BSG is not set |
15 | # CONFIG_IOSCHED_DEADLINE is not set | 15 | # CONFIG_IOSCHED_DEADLINE is not set |
16 | # CONFIG_IOSCHED_CFQ is not set | 16 | # CONFIG_IOSCHED_CFQ is not set |
17 | CONFIG_ARCH_SHMOBILE=y | 17 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
18 | CONFIG_ARCH_SH7372=y | 18 | CONFIG_ARCH_SH7372=y |
19 | CONFIG_MACH_MACKEREL=y | 19 | CONFIG_MACH_MACKEREL=y |
20 | CONFIG_MEMORY_SIZE=0x10000000 | 20 | CONFIG_MEMORY_SIZE=0x10000000 |
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig index 5cc6360340b1..6981338cd08d 100644 --- a/arch/arm/configs/marzen_defconfig +++ b/arch/arm/configs/marzen_defconfig | |||
@@ -9,7 +9,7 @@ CONFIG_SYSCTL_SYSCALL=y | |||
9 | CONFIG_EMBEDDED=y | 9 | CONFIG_EMBEDDED=y |
10 | CONFIG_SLAB=y | 10 | CONFIG_SLAB=y |
11 | # CONFIG_IOSCHED_CFQ is not set | 11 | # CONFIG_IOSCHED_CFQ is not set |
12 | CONFIG_ARCH_SHMOBILE=y | 12 | CONFIG_ARCH_SHMOBILE_LEGACY=y |
13 | CONFIG_ARCH_R8A7779=y | 13 | CONFIG_ARCH_R8A7779=y |
14 | CONFIG_MACH_MARZEN=y | 14 | CONFIG_MACH_MARZEN=y |
15 | CONFIG_MEMORY_START=0x60000000 | 15 | CONFIG_MEMORY_START=0x60000000 |
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index 4934295bb4f0..da753e31c850 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig | |||
@@ -33,6 +33,7 @@ CONFIG_PCI=y | |||
33 | CONFIG_PCI_MSI=y | 33 | CONFIG_PCI_MSI=y |
34 | CONFIG_PCI_TEGRA=y | 34 | CONFIG_PCI_TEGRA=y |
35 | CONFIG_PCIEPORTBUS=y | 35 | CONFIG_PCIEPORTBUS=y |
36 | CONFIG_TRUSTED_FOUNDATIONS=y | ||
36 | CONFIG_SMP=y | 37 | CONFIG_SMP=y |
37 | CONFIG_PREEMPT=y | 38 | CONFIG_PREEMPT=y |
38 | CONFIG_AEABI=y | 39 | CONFIG_AEABI=y |
diff --git a/arch/arm/firmware/Kconfig b/arch/arm/firmware/Kconfig new file mode 100644 index 000000000000..bb00ccf00d66 --- /dev/null +++ b/arch/arm/firmware/Kconfig | |||
@@ -0,0 +1,28 @@ | |||
1 | config ARCH_SUPPORTS_FIRMWARE | ||
2 | bool | ||
3 | |||
4 | config ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
5 | bool | ||
6 | select ARCH_SUPPORTS_FIRMWARE | ||
7 | |||
8 | menu "Firmware options" | ||
9 | depends on ARCH_SUPPORTS_FIRMWARE | ||
10 | |||
11 | config TRUSTED_FOUNDATIONS | ||
12 | bool "Trusted Foundations secure monitor support" | ||
13 | depends on ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
14 | help | ||
15 | Some devices (including most Tegra-based consumer devices on the | ||
16 | market) are booted with the Trusted Foundations secure monitor | ||
17 | active, requiring some core operations to be performed by the secure | ||
18 | monitor instead of the kernel. | ||
19 | |||
20 | This option allows the kernel to invoke the secure monitor whenever | ||
21 | required on devices using Trusted Foundations. See | ||
22 | arch/arm/include/asm/trusted_foundations.h or the | ||
23 | tl,trusted-foundations device tree binding documentation for details | ||
24 | on how to use it. | ||
25 | |||
26 | Say n if you don't know what this is about. | ||
27 | |||
28 | endmenu | ||
diff --git a/arch/arm/firmware/Makefile b/arch/arm/firmware/Makefile new file mode 100644 index 000000000000..a71f16536b6c --- /dev/null +++ b/arch/arm/firmware/Makefile | |||
@@ -0,0 +1 @@ | |||
obj-$(CONFIG_TRUSTED_FOUNDATIONS) += trusted_foundations.o | |||
diff --git a/arch/arm/firmware/trusted_foundations.c b/arch/arm/firmware/trusted_foundations.c new file mode 100644 index 000000000000..ef1e3d8f4af0 --- /dev/null +++ b/arch/arm/firmware/trusted_foundations.c | |||
@@ -0,0 +1,81 @@ | |||
1 | /* | ||
2 | * Trusted Foundations support for ARM CPUs | ||
3 | * | ||
4 | * Copyright (c) 2013, NVIDIA Corporation. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
14 | * more details. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/init.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <asm/firmware.h> | ||
21 | #include <asm/trusted_foundations.h> | ||
22 | |||
23 | #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200 | ||
24 | |||
25 | static void __naked tf_generic_smc(u32 type, u32 arg1, u32 arg2) | ||
26 | { | ||
27 | asm volatile( | ||
28 | ".arch_extension sec\n\t" | ||
29 | "stmfd sp!, {r4 - r11, lr}\n\t" | ||
30 | __asmeq("%0", "r0") | ||
31 | __asmeq("%1", "r1") | ||
32 | __asmeq("%2", "r2") | ||
33 | "mov r3, #0\n\t" | ||
34 | "mov r4, #0\n\t" | ||
35 | "smc #0\n\t" | ||
36 | "ldmfd sp!, {r4 - r11, pc}" | ||
37 | : | ||
38 | : "r" (type), "r" (arg1), "r" (arg2) | ||
39 | : "memory"); | ||
40 | } | ||
41 | |||
42 | static int tf_set_cpu_boot_addr(int cpu, unsigned long boot_addr) | ||
43 | { | ||
44 | tf_generic_smc(TF_SET_CPU_BOOT_ADDR_SMC, boot_addr, 0); | ||
45 | |||
46 | return 0; | ||
47 | } | ||
48 | |||
49 | static const struct firmware_ops trusted_foundations_ops = { | ||
50 | .set_cpu_boot_addr = tf_set_cpu_boot_addr, | ||
51 | }; | ||
52 | |||
53 | void register_trusted_foundations(struct trusted_foundations_platform_data *pd) | ||
54 | { | ||
55 | /* | ||
56 | * we are not using version information for now since currently | ||
57 | * supported SMCs are compatible with all TF releases | ||
58 | */ | ||
59 | register_firmware_ops(&trusted_foundations_ops); | ||
60 | } | ||
61 | |||
62 | void of_register_trusted_foundations(void) | ||
63 | { | ||
64 | struct device_node *node; | ||
65 | struct trusted_foundations_platform_data pdata; | ||
66 | int err; | ||
67 | |||
68 | node = of_find_compatible_node(NULL, NULL, "tlm,trusted-foundations"); | ||
69 | if (!node) | ||
70 | return; | ||
71 | |||
72 | err = of_property_read_u32(node, "tlm,version-major", | ||
73 | &pdata.version_major); | ||
74 | if (err != 0) | ||
75 | panic("Trusted Foundation: missing version-major property\n"); | ||
76 | err = of_property_read_u32(node, "tlm,version-minor", | ||
77 | &pdata.version_minor); | ||
78 | if (err != 0) | ||
79 | panic("Trusted Foundation: missing version-minor property\n"); | ||
80 | register_trusted_foundations(&pdata); | ||
81 | } | ||
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h new file mode 100644 index 000000000000..3bd36e2c5f2e --- /dev/null +++ b/arch/arm/include/asm/trusted_foundations.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2013, NVIDIA Corporation. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
12 | * more details. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * Support for the Trusted Foundations secure monitor. | ||
17 | * | ||
18 | * Trusted Foundation comes active on some ARM consumer devices (most | ||
19 | * Tegra-based devices sold on the market are concerned). Such devices can only | ||
20 | * perform some basic operations, like setting the CPU reset vector, through | ||
21 | * SMC calls to the secure monitor. The calls are completely specific to | ||
22 | * Trusted Foundations, and do *not* follow the SMC calling convention or the | ||
23 | * PSCI standard. | ||
24 | */ | ||
25 | |||
26 | #ifndef __ASM_ARM_TRUSTED_FOUNDATIONS_H | ||
27 | #define __ASM_ARM_TRUSTED_FOUNDATIONS_H | ||
28 | |||
29 | #include <linux/kconfig.h> | ||
30 | #include <linux/printk.h> | ||
31 | #include <linux/bug.h> | ||
32 | #include <linux/of.h> | ||
33 | |||
34 | struct trusted_foundations_platform_data { | ||
35 | unsigned int version_major; | ||
36 | unsigned int version_minor; | ||
37 | }; | ||
38 | |||
39 | #if IS_ENABLED(CONFIG_TRUSTED_FOUNDATIONS) | ||
40 | |||
41 | void register_trusted_foundations(struct trusted_foundations_platform_data *pd); | ||
42 | void of_register_trusted_foundations(void); | ||
43 | |||
44 | #else /* CONFIG_TRUSTED_FOUNDATIONS */ | ||
45 | |||
46 | static inline void register_trusted_foundations( | ||
47 | struct trusted_foundations_platform_data *pd) | ||
48 | { | ||
49 | /* | ||
50 | * If we try to register TF, this means the system needs it to continue. | ||
51 | * Its absence if thus a fatal error. | ||
52 | */ | ||
53 | panic("No support for Trusted Foundations, stopping...\n"); | ||
54 | } | ||
55 | |||
56 | static inline void of_register_trusted_foundations(void) | ||
57 | { | ||
58 | /* | ||
59 | * If we find the target should enable TF but does not support it, | ||
60 | * fail as the system won't be able to do much anyway | ||
61 | */ | ||
62 | if (of_find_compatible_node(NULL, NULL, "tl,trusted-foundations")) | ||
63 | register_trusted_foundations(NULL); | ||
64 | } | ||
65 | #endif /* CONFIG_TRUSTED_FOUNDATIONS */ | ||
66 | |||
67 | #endif | ||
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 699b71e7f7ec..b4f7d6ffa30b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
@@ -1,15 +1,33 @@ | |||
1 | if ARCH_AT91 | 1 | if ARCH_AT91 |
2 | 2 | ||
3 | config HAVE_AT91_UTMI | ||
4 | bool | ||
5 | |||
6 | config HAVE_AT91_USB_CLK | ||
7 | bool | ||
8 | |||
3 | config HAVE_AT91_DBGU0 | 9 | config HAVE_AT91_DBGU0 |
4 | bool | 10 | bool |
5 | 11 | ||
6 | config HAVE_AT91_DBGU1 | 12 | config HAVE_AT91_DBGU1 |
7 | bool | 13 | bool |
8 | 14 | ||
15 | config AT91_USE_OLD_CLK | ||
16 | bool | ||
17 | |||
9 | config AT91_PMC_UNIT | 18 | config AT91_PMC_UNIT |
10 | bool | 19 | bool |
11 | default !ARCH_AT91X40 | 20 | default !ARCH_AT91X40 |
12 | 21 | ||
22 | config COMMON_CLK_AT91 | ||
23 | bool | ||
24 | default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK | ||
25 | select COMMON_CLK | ||
26 | |||
27 | config OLD_CLK_AT91 | ||
28 | bool | ||
29 | default AT91_PMC_UNIT && AT91_USE_OLD_CLK | ||
30 | |||
13 | config AT91_SAM9_ALT_RESET | 31 | config AT91_SAM9_ALT_RESET |
14 | bool | 32 | bool |
15 | default !ARCH_AT91X40 | 33 | default !ARCH_AT91X40 |
@@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET | |||
21 | config AT91_SAM9_TIME | 39 | config AT91_SAM9_TIME |
22 | bool | 40 | bool |
23 | 41 | ||
42 | config HAVE_AT91_SMD | ||
43 | bool | ||
44 | |||
24 | config SOC_AT91SAM9 | 45 | config SOC_AT91SAM9 |
25 | bool | 46 | bool |
26 | select AT91_SAM9_TIME | 47 | select AT91_SAM9_TIME |
@@ -65,6 +86,9 @@ config SOC_SAMA5D3 | |||
65 | select SOC_SAMA5 | 86 | select SOC_SAMA5 |
66 | select HAVE_FB_ATMEL | 87 | select HAVE_FB_ATMEL |
67 | select HAVE_AT91_DBGU1 | 88 | select HAVE_AT91_DBGU1 |
89 | select HAVE_AT91_UTMI | ||
90 | select HAVE_AT91_SMD | ||
91 | select HAVE_AT91_USB_CLK | ||
68 | help | 92 | help |
69 | Select this if you are using one of Atmel's SAMA5D3 family SoC. | 93 | Select this if you are using one of Atmel's SAMA5D3 family SoC. |
70 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. | 94 | This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. |
@@ -78,11 +102,15 @@ config SOC_AT91RM9200 | |||
78 | select HAVE_AT91_DBGU0 | 102 | select HAVE_AT91_DBGU0 |
79 | select MULTI_IRQ_HANDLER | 103 | select MULTI_IRQ_HANDLER |
80 | select SPARSE_IRQ | 104 | select SPARSE_IRQ |
105 | select AT91_USE_OLD_CLK | ||
106 | select HAVE_AT91_USB_CLK | ||
81 | 107 | ||
82 | config SOC_AT91SAM9260 | 108 | config SOC_AT91SAM9260 |
83 | bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" | 109 | bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" |
84 | select HAVE_AT91_DBGU0 | 110 | select HAVE_AT91_DBGU0 |
85 | select SOC_AT91SAM9 | 111 | select SOC_AT91SAM9 |
112 | select AT91_USE_OLD_CLK | ||
113 | select HAVE_AT91_USB_CLK | ||
86 | help | 114 | help |
87 | Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE | 115 | Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE |
88 | or AT91SAM9G20 SoC. | 116 | or AT91SAM9G20 SoC. |
@@ -92,6 +120,8 @@ config SOC_AT91SAM9261 | |||
92 | select HAVE_AT91_DBGU0 | 120 | select HAVE_AT91_DBGU0 |
93 | select HAVE_FB_ATMEL | 121 | select HAVE_FB_ATMEL |
94 | select SOC_AT91SAM9 | 122 | select SOC_AT91SAM9 |
123 | select AT91_USE_OLD_CLK | ||
124 | select HAVE_AT91_USB_CLK | ||
95 | help | 125 | help |
96 | Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. | 126 | Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. |
97 | 127 | ||
@@ -100,18 +130,25 @@ config SOC_AT91SAM9263 | |||
100 | select HAVE_AT91_DBGU1 | 130 | select HAVE_AT91_DBGU1 |
101 | select HAVE_FB_ATMEL | 131 | select HAVE_FB_ATMEL |
102 | select SOC_AT91SAM9 | 132 | select SOC_AT91SAM9 |
133 | select AT91_USE_OLD_CLK | ||
134 | select HAVE_AT91_USB_CLK | ||
103 | 135 | ||
104 | config SOC_AT91SAM9RL | 136 | config SOC_AT91SAM9RL |
105 | bool "AT91SAM9RL" | 137 | bool "AT91SAM9RL" |
106 | select HAVE_AT91_DBGU0 | 138 | select HAVE_AT91_DBGU0 |
107 | select HAVE_FB_ATMEL | 139 | select HAVE_FB_ATMEL |
108 | select SOC_AT91SAM9 | 140 | select SOC_AT91SAM9 |
141 | select AT91_USE_OLD_CLK | ||
142 | select HAVE_AT91_UTMI | ||
109 | 143 | ||
110 | config SOC_AT91SAM9G45 | 144 | config SOC_AT91SAM9G45 |
111 | bool "AT91SAM9G45 or AT91SAM9M10 families" | 145 | bool "AT91SAM9G45 or AT91SAM9M10 families" |
112 | select HAVE_AT91_DBGU1 | 146 | select HAVE_AT91_DBGU1 |
113 | select HAVE_FB_ATMEL | 147 | select HAVE_FB_ATMEL |
114 | select SOC_AT91SAM9 | 148 | select SOC_AT91SAM9 |
149 | select AT91_USE_OLD_CLK | ||
150 | select HAVE_AT91_UTMI | ||
151 | select HAVE_AT91_USB_CLK | ||
115 | help | 152 | help |
116 | Select this if you are using one of Atmel's AT91SAM9G45 family SoC. | 153 | Select this if you are using one of Atmel's AT91SAM9G45 family SoC. |
117 | This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. | 154 | This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. |
@@ -121,6 +158,10 @@ config SOC_AT91SAM9X5 | |||
121 | select HAVE_AT91_DBGU0 | 158 | select HAVE_AT91_DBGU0 |
122 | select HAVE_FB_ATMEL | 159 | select HAVE_FB_ATMEL |
123 | select SOC_AT91SAM9 | 160 | select SOC_AT91SAM9 |
161 | select AT91_USE_OLD_CLK | ||
162 | select HAVE_AT91_UTMI | ||
163 | select HAVE_AT91_SMD | ||
164 | select HAVE_AT91_USB_CLK | ||
124 | help | 165 | help |
125 | Select this if you are using one of Atmel's AT91SAM9x5 family SoC. | 166 | Select this if you are using one of Atmel's AT91SAM9x5 family SoC. |
126 | This means that your SAM9 name finishes with a '5' (except if it is | 167 | This means that your SAM9 name finishes with a '5' (except if it is |
@@ -133,6 +174,8 @@ config SOC_AT91SAM9N12 | |||
133 | select HAVE_AT91_DBGU0 | 174 | select HAVE_AT91_DBGU0 |
134 | select HAVE_FB_ATMEL | 175 | select HAVE_FB_ATMEL |
135 | select SOC_AT91SAM9 | 176 | select SOC_AT91SAM9 |
177 | select AT91_USE_OLD_CLK | ||
178 | select HAVE_AT91_USB_CLK | ||
136 | help | 179 | help |
137 | Select this if you are using Atmel's AT91SAM9N12 SoC. | 180 | Select this if you are using Atmel's AT91SAM9N12 SoC. |
138 | 181 | ||
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index ca900be144ce..b736b571e882 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt | |||
@@ -12,26 +12,32 @@ config ARCH_AT91_NONE | |||
12 | config ARCH_AT91RM9200 | 12 | config ARCH_AT91RM9200 |
13 | bool "AT91RM9200" | 13 | bool "AT91RM9200" |
14 | select SOC_AT91RM9200 | 14 | select SOC_AT91RM9200 |
15 | select AT91_USE_OLD_CLK | ||
15 | 16 | ||
16 | config ARCH_AT91SAM9260 | 17 | config ARCH_AT91SAM9260 |
17 | bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" | 18 | bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" |
18 | select SOC_AT91SAM9260 | 19 | select SOC_AT91SAM9260 |
20 | select AT91_USE_OLD_CLK | ||
19 | 21 | ||
20 | config ARCH_AT91SAM9261 | 22 | config ARCH_AT91SAM9261 |
21 | bool "AT91SAM9261 or AT91SAM9G10" | 23 | bool "AT91SAM9261 or AT91SAM9G10" |
22 | select SOC_AT91SAM9261 | 24 | select SOC_AT91SAM9261 |
25 | select AT91_USE_OLD_CLK | ||
23 | 26 | ||
24 | config ARCH_AT91SAM9263 | 27 | config ARCH_AT91SAM9263 |
25 | bool "AT91SAM9263" | 28 | bool "AT91SAM9263" |
26 | select SOC_AT91SAM9263 | 29 | select SOC_AT91SAM9263 |
30 | select AT91_USE_OLD_CLK | ||
27 | 31 | ||
28 | config ARCH_AT91SAM9RL | 32 | config ARCH_AT91SAM9RL |
29 | bool "AT91SAM9RL" | 33 | bool "AT91SAM9RL" |
30 | select SOC_AT91SAM9RL | 34 | select SOC_AT91SAM9RL |
35 | select AT91_USE_OLD_CLK | ||
31 | 36 | ||
32 | config ARCH_AT91SAM9G45 | 37 | config ARCH_AT91SAM9G45 |
33 | bool "AT91SAM9G45" | 38 | bool "AT91SAM9G45" |
34 | select SOC_AT91SAM9G45 | 39 | select SOC_AT91SAM9G45 |
40 | select AT91_USE_OLD_CLK | ||
35 | 41 | ||
36 | config ARCH_AT91X40 | 42 | config ARCH_AT91X40 |
37 | bool "AT91x40" | 43 | bool "AT91x40" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 90aab2d5a07f..705b38a179ec 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
@@ -7,7 +7,7 @@ obj-m := | |||
7 | obj-n := | 7 | obj-n := |
8 | obj- := | 8 | obj- := |
9 | 9 | ||
10 | obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | 10 | obj-$(CONFIG_OLD_CLK_AT91) += clock.o |
11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o | 11 | obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o |
12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o | 12 | obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o |
13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o | 13 | obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o |
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 25805f2f6010..e47f5fd232f5 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c | |||
@@ -12,13 +12,13 @@ | |||
12 | 12 | ||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/reboot.h> | 14 | #include <linux/reboot.h> |
15 | #include <linux/clk/at91_pmc.h> | ||
15 | 16 | ||
16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
20 | #include <mach/at91rm9200.h> | 21 | #include <mach/at91rm9200.h> |
21 | #include <mach/at91_pmc.h> | ||
22 | #include <mach/at91_st.h> | 22 | #include <mach/at91_st.h> |
23 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
24 | 24 | ||
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index d6a1fa85371d..6c821e562159 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c | |||
@@ -11,6 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/clk/at91_pmc.h> | ||
14 | 15 | ||
15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
@@ -20,7 +21,6 @@ | |||
20 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
21 | #include <mach/at91_dbgu.h> | 22 | #include <mach/at91_dbgu.h> |
22 | #include <mach/at91sam9260.h> | 23 | #include <mach/at91sam9260.h> |
23 | #include <mach/at91_pmc.h> | ||
24 | 24 | ||
25 | #include "at91_aic.h" | 25 | #include "at91_aic.h" |
26 | #include "at91_rstc.h" | 26 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 23ba1d8a1531..6276b4c1acfe 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
@@ -11,6 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/clk/at91_pmc.h> | ||
14 | 15 | ||
15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
@@ -19,7 +20,6 @@ | |||
19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
20 | #include <mach/cpu.h> | 21 | #include <mach/cpu.h> |
21 | #include <mach/at91sam9261.h> | 22 | #include <mach/at91sam9261.h> |
22 | #include <mach/at91_pmc.h> | ||
23 | 23 | ||
24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
25 | #include "at91_rstc.h" | 25 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 7eccb0fc57bc..37b90f4b990c 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c | |||
@@ -11,6 +11,7 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/clk/at91_pmc.h> | ||
14 | 15 | ||
15 | #include <asm/proc-fns.h> | 16 | #include <asm/proc-fns.h> |
16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
@@ -18,7 +19,6 @@ | |||
18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
20 | #include <mach/at91sam9263.h> | 21 | #include <mach/at91sam9263.h> |
21 | #include <mach/at91_pmc.h> | ||
22 | 22 | ||
23 | #include "at91_aic.h" | 23 | #include "at91_aic.h" |
24 | #include "at91_rstc.h" | 24 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index bb392320a0dd..0f04ffe9c5a8 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c | |||
@@ -39,6 +39,7 @@ | |||
39 | static u32 pit_cycle; /* write-once */ | 39 | static u32 pit_cycle; /* write-once */ |
40 | static u32 pit_cnt; /* access only w/system irq blocked */ | 40 | static u32 pit_cnt; /* access only w/system irq blocked */ |
41 | static void __iomem *pit_base_addr __read_mostly; | 41 | static void __iomem *pit_base_addr __read_mostly; |
42 | static struct clk *mck; | ||
42 | 43 | ||
43 | static inline unsigned int pit_read(unsigned int reg_offset) | 44 | static inline unsigned int pit_read(unsigned int reg_offset) |
44 | { | 45 | { |
@@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void) | |||
195 | if (!pit_base_addr) | 196 | if (!pit_base_addr) |
196 | goto node_err; | 197 | goto node_err; |
197 | 198 | ||
199 | mck = of_clk_get(np, 0); | ||
200 | |||
198 | /* Get the interrupts property */ | 201 | /* Get the interrupts property */ |
199 | ret = irq_of_parse_and_map(np, 0); | 202 | ret = irq_of_parse_and_map(np, 0); |
200 | if (!ret) { | 203 | if (!ret) { |
201 | pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); | 204 | pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); |
205 | if (!IS_ERR(mck)) | ||
206 | clk_put(mck); | ||
202 | goto ioremap_err; | 207 | goto ioremap_err; |
203 | } | 208 | } |
204 | at91sam926x_pit_irq.irq = ret; | 209 | at91sam926x_pit_irq.irq = ret; |
@@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void) | |||
230 | unsigned bits; | 235 | unsigned bits; |
231 | int ret; | 236 | int ret; |
232 | 237 | ||
238 | mck = ERR_PTR(-ENOENT); | ||
239 | |||
233 | /* For device tree enabled device: initialize here */ | 240 | /* For device tree enabled device: initialize here */ |
234 | of_at91sam926x_pit_init(); | 241 | of_at91sam926x_pit_init(); |
235 | 242 | ||
@@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void) | |||
237 | * Use our actual MCK to figure out how many MCK/16 ticks per | 244 | * Use our actual MCK to figure out how many MCK/16 ticks per |
238 | * 1/HZ period (instead of a compile-time constant LATCH). | 245 | * 1/HZ period (instead of a compile-time constant LATCH). |
239 | */ | 246 | */ |
240 | pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; | 247 | if (IS_ERR(mck)) |
248 | mck = clk_get(NULL, "mck"); | ||
249 | |||
250 | if (IS_ERR(mck)) | ||
251 | panic("AT91: PIT: Unable to get mck clk\n"); | ||
252 | pit_rate = clk_get_rate(mck) / 16; | ||
241 | pit_cycle = (pit_rate + HZ/2) / HZ; | 253 | pit_cycle = (pit_rate + HZ/2) / HZ; |
242 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); | 254 | WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); |
243 | 255 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9405aa08b104..2f455ce35268 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
@@ -12,13 +12,13 @@ | |||
12 | 12 | ||
13 | #include <linux/module.h> | 13 | #include <linux/module.h> |
14 | #include <linux/dma-mapping.h> | 14 | #include <linux/dma-mapping.h> |
15 | #include <linux/clk/at91_pmc.h> | ||
15 | 16 | ||
16 | #include <asm/irq.h> | 17 | #include <asm/irq.h> |
17 | #include <asm/mach/arch.h> | 18 | #include <asm/mach/arch.h> |
18 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
19 | #include <asm/system_misc.h> | 20 | #include <asm/system_misc.h> |
20 | #include <mach/at91sam9g45.h> | 21 | #include <mach/at91sam9g45.h> |
21 | #include <mach/at91_pmc.h> | ||
22 | #include <mach/cpu.h> | 22 | #include <mach/cpu.h> |
23 | 23 | ||
24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 388ec3aec4b9..4ef088c62eab 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c | |||
@@ -8,12 +8,12 @@ | |||
8 | 8 | ||
9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
10 | #include <linux/dma-mapping.h> | 10 | #include <linux/dma-mapping.h> |
11 | #include <linux/clk/at91_pmc.h> | ||
11 | 12 | ||
12 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
13 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
14 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
15 | #include <mach/at91sam9n12.h> | 16 | #include <mach/at91sam9n12.h> |
16 | #include <mach/at91_pmc.h> | ||
17 | #include <mach/cpu.h> | 17 | #include <mach/cpu.h> |
18 | 18 | ||
19 | #include "board.h" | 19 | #include "board.h" |
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 0750ffb7e6b1..3651517abedf 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c | |||
@@ -10,6 +10,7 @@ | |||
10 | */ | 10 | */ |
11 | 11 | ||
12 | #include <linux/module.h> | 12 | #include <linux/module.h> |
13 | #include <linux/clk/at91_pmc.h> | ||
13 | 14 | ||
14 | #include <asm/proc-fns.h> | 15 | #include <asm/proc-fns.h> |
15 | #include <asm/irq.h> | 16 | #include <asm/irq.h> |
@@ -19,7 +20,6 @@ | |||
19 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
20 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
21 | #include <mach/at91sam9rl.h> | 22 | #include <mach/at91sam9rl.h> |
22 | #include <mach/at91_pmc.h> | ||
23 | 23 | ||
24 | #include "at91_aic.h" | 24 | #include "at91_aic.h" |
25 | #include "at91_rstc.h" | 25 | #include "at91_rstc.h" |
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e8a2e075a1b8..3e8ec26e39dc 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c | |||
@@ -8,12 +8,12 @@ | |||
8 | 8 | ||
9 | #include <linux/module.h> | 9 | #include <linux/module.h> |
10 | #include <linux/dma-mapping.h> | 10 | #include <linux/dma-mapping.h> |
11 | #include <linux/clk/at91_pmc.h> | ||
11 | 12 | ||
12 | #include <asm/irq.h> | 13 | #include <asm/irq.h> |
13 | #include <asm/mach/arch.h> | 14 | #include <asm/mach/arch.h> |
14 | #include <asm/mach/map.h> | 15 | #include <asm/mach/map.h> |
15 | #include <mach/at91sam9x5.h> | 16 | #include <mach/at91sam9x5.h> |
16 | #include <mach/at91_pmc.h> | ||
17 | #include <mach/cpu.h> | 17 | #include <mach/cpu.h> |
18 | 18 | ||
19 | #include "board.h" | 19 | #include "board.h" |
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index bf00d15d954d..075ec0576ada 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/of_irq.h> | 16 | #include <linux/of_irq.h> |
17 | #include <linux/of_platform.h> | 17 | #include <linux/of_platform.h> |
18 | #include <linux/phy.h> | 18 | #include <linux/phy.h> |
19 | #include <linux/clk-provider.h> | ||
19 | 20 | ||
20 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
21 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
@@ -26,6 +27,13 @@ | |||
26 | #include "at91_aic.h" | 27 | #include "at91_aic.h" |
27 | #include "generic.h" | 28 | #include "generic.h" |
28 | 29 | ||
30 | static void __init sama5_dt_timer_init(void) | ||
31 | { | ||
32 | #if defined(CONFIG_COMMON_CLK) | ||
33 | of_clk_init(NULL); | ||
34 | #endif | ||
35 | at91sam926x_pit_init(); | ||
36 | } | ||
29 | 37 | ||
30 | static const struct of_device_id irq_of_match[] __initconst = { | 38 | static const struct of_device_id irq_of_match[] __initconst = { |
31 | 39 | ||
@@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = { | |||
72 | 80 | ||
73 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") | 81 | DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") |
74 | /* Maintainer: Atmel */ | 82 | /* Maintainer: Atmel */ |
75 | .init_time = at91sam926x_pit_init, | 83 | .init_time = sama5_dt_timer_init, |
76 | .map_io = at91_map_io, | 84 | .map_io = at91_map_io, |
77 | .handle_irq = at91_aic5_handle_irq, | 85 | .handle_irq = at91_aic5_handle_irq, |
78 | .init_early = at91_dt_initialize, | 86 | .init_early = at91_dt_initialize, |
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 6b2630a92f71..72b257944733 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
@@ -24,9 +24,9 @@ | |||
24 | #include <linux/clk.h> | 24 | #include <linux/clk.h> |
25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
26 | #include <linux/of_address.h> | 26 | #include <linux/of_address.h> |
27 | #include <linux/clk/at91_pmc.h> | ||
27 | 28 | ||
28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
29 | #include <mach/at91_pmc.h> | ||
30 | #include <mach/cpu.h> | 30 | #include <mach/cpu.h> |
31 | 31 | ||
32 | #include <asm/proc-fns.h> | 32 | #include <asm/proc-fns.h> |
@@ -884,6 +884,11 @@ static int __init at91_pmc_init(unsigned long main_clock) | |||
884 | #if defined(CONFIG_OF) | 884 | #if defined(CONFIG_OF) |
885 | static struct of_device_id pmc_ids[] = { | 885 | static struct of_device_id pmc_ids[] = { |
886 | { .compatible = "atmel,at91rm9200-pmc" }, | 886 | { .compatible = "atmel,at91rm9200-pmc" }, |
887 | { .compatible = "atmel,at91sam9260-pmc" }, | ||
888 | { .compatible = "atmel,at91sam9g45-pmc" }, | ||
889 | { .compatible = "atmel,at91sam9n12-pmc" }, | ||
890 | { .compatible = "atmel,at91sam9x5-pmc" }, | ||
891 | { .compatible = "atmel,sama5d3-pmc" }, | ||
887 | { /*sentinel*/ } | 892 | { /*sentinel*/ } |
888 | }; | 893 | }; |
889 | 894 | ||
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 26dee3ce9397..631fa3b8c16d 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
@@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void); | |||
46 | extern void at91x40_timer_init(void); | 46 | extern void at91x40_timer_init(void); |
47 | 47 | ||
48 | /* Clocks */ | 48 | /* Clocks */ |
49 | #ifdef CONFIG_AT91_PMC_UNIT | 49 | #ifdef CONFIG_OLD_CLK_AT91 |
50 | extern int __init at91_clock_init(unsigned long main_clock); | 50 | extern int __init at91_clock_init(unsigned long main_clock); |
51 | extern int __init at91_dt_clock_init(void); | 51 | extern int __init at91_dt_clock_init(void); |
52 | #else | 52 | #else |
53 | static int inline at91_clock_init(unsigned long main_clock) { return 0; } | 53 | static int inline at91_clock_init(unsigned long main_clock) { return 0; } |
54 | static int inline at91_dt_clock_init(void) { return 0; } | ||
54 | #endif | 55 | #endif |
55 | struct device; | 56 | struct device; |
56 | 57 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h deleted file mode 100644 index c604cc69acb5..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ /dev/null | |||
@@ -1,190 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-at91/include/mach/at91_pmc.h | ||
3 | * | ||
4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
5 | * Copyright (C) SAN People | ||
6 | * | ||
7 | * Power Management Controller (PMC) - System peripherals registers. | ||
8 | * Based on AT91RM9200 datasheet revision E. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifndef AT91_PMC_H | ||
17 | #define AT91_PMC_H | ||
18 | |||
19 | #ifndef __ASSEMBLY__ | ||
20 | extern void __iomem *at91_pmc_base; | ||
21 | |||
22 | #define at91_pmc_read(field) \ | ||
23 | __raw_readl(at91_pmc_base + field) | ||
24 | |||
25 | #define at91_pmc_write(field, value) \ | ||
26 | __raw_writel(value, at91_pmc_base + field) | ||
27 | #else | ||
28 | .extern at91_pmc_base | ||
29 | #endif | ||
30 | |||
31 | #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ | ||
32 | #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ | ||
33 | |||
34 | #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ | ||
35 | #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ | ||
36 | #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ | ||
37 | #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ | ||
38 | #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ | ||
39 | #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ | ||
40 | #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ | ||
41 | #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ | ||
42 | #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ | ||
43 | #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ | ||
44 | #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ | ||
45 | #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ | ||
46 | #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ | ||
47 | #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ | ||
48 | |||
49 | #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ | ||
50 | #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ | ||
51 | #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ | ||
52 | |||
53 | #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ | ||
54 | #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ | ||
55 | #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ | ||
56 | #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ | ||
57 | #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ | ||
58 | |||
59 | #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ | ||
60 | #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ | ||
61 | #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ | ||
62 | #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ | ||
63 | #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ | ||
64 | #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ | ||
65 | #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ | ||
66 | #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ | ||
67 | |||
68 | #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ | ||
69 | #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ | ||
70 | #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ | ||
71 | |||
72 | #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ | ||
73 | #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ | ||
74 | #define AT91_PMC_DIV (0xff << 0) /* Divider */ | ||
75 | #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ | ||
76 | #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ | ||
77 | #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ | ||
78 | #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) | ||
79 | #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ | ||
80 | #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) | ||
81 | #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ | ||
82 | #define AT91_PMC_USBDIV_1 (0 << 28) | ||
83 | #define AT91_PMC_USBDIV_2 (1 << 28) | ||
84 | #define AT91_PMC_USBDIV_4 (2 << 28) | ||
85 | #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ | ||
86 | |||
87 | #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ | ||
88 | #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ | ||
89 | #define AT91_PMC_CSS_SLOW (0 << 0) | ||
90 | #define AT91_PMC_CSS_MAIN (1 << 0) | ||
91 | #define AT91_PMC_CSS_PLLA (2 << 0) | ||
92 | #define AT91_PMC_CSS_PLLB (3 << 0) | ||
93 | #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ | ||
94 | #define PMC_PRES_OFFSET 2 | ||
95 | #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ | ||
96 | #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) | ||
97 | #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) | ||
98 | #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) | ||
99 | #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) | ||
100 | #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) | ||
101 | #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) | ||
102 | #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) | ||
103 | #define PMC_ALT_PRES_OFFSET 4 | ||
104 | #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ | ||
105 | #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) | ||
106 | #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) | ||
107 | #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) | ||
108 | #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) | ||
109 | #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) | ||
110 | #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) | ||
111 | #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) | ||
112 | #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ | ||
113 | #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ | ||
114 | #define AT91RM9200_PMC_MDIV_2 (1 << 8) | ||
115 | #define AT91RM9200_PMC_MDIV_3 (2 << 8) | ||
116 | #define AT91RM9200_PMC_MDIV_4 (3 << 8) | ||
117 | #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ | ||
118 | #define AT91SAM9_PMC_MDIV_2 (1 << 8) | ||
119 | #define AT91SAM9_PMC_MDIV_4 (2 << 8) | ||
120 | #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ | ||
121 | #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ | ||
122 | #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ | ||
123 | #define AT91_PMC_PDIV_1 (0 << 12) | ||
124 | #define AT91_PMC_PDIV_2 (1 << 12) | ||
125 | #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ | ||
126 | #define AT91_PMC_PLLADIV2_OFF (0 << 12) | ||
127 | #define AT91_PMC_PLLADIV2_ON (1 << 12) | ||
128 | |||
129 | #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ | ||
130 | #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ | ||
131 | #define AT91_PMC_USBS_PLLA (0 << 0) | ||
132 | #define AT91_PMC_USBS_UPLL (1 << 0) | ||
133 | #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ | ||
134 | #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ | ||
135 | #define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) | ||
136 | #define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) | ||
137 | |||
138 | #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ | ||
139 | #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ | ||
140 | #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ | ||
141 | #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) | ||
142 | |||
143 | #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ | ||
144 | #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ | ||
145 | #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ | ||
146 | #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ | ||
147 | #define AT91_PMC_CSSMCK_CSS (0 << 8) | ||
148 | #define AT91_PMC_CSSMCK_MCK (1 << 8) | ||
149 | |||
150 | #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ | ||
151 | #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ | ||
152 | #define AT91_PMC_SR 0x68 /* Status Register */ | ||
153 | #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ | ||
154 | #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ | ||
155 | #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ | ||
156 | #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ | ||
157 | #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ | ||
158 | #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ | ||
159 | #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ | ||
160 | #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ | ||
161 | #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ | ||
162 | #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ | ||
163 | #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ | ||
164 | #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ | ||
165 | #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ | ||
166 | |||
167 | #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ | ||
168 | #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ | ||
169 | #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ | ||
170 | #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ | ||
171 | |||
172 | #define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ | ||
173 | #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ | ||
174 | #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ | ||
175 | |||
176 | #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ | ||
177 | #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ | ||
178 | #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ | ||
179 | |||
180 | #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ | ||
181 | #define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ | ||
182 | #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ | ||
183 | #define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ | ||
184 | #define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ | ||
185 | #define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ | ||
186 | #define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ | ||
187 | #define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ | ||
188 | #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ | ||
189 | |||
190 | #endif | ||
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 9986542e8060..d43b79f56e94 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
@@ -19,13 +19,13 @@ | |||
19 | #include <linux/module.h> | 19 | #include <linux/module.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/clk/at91_pmc.h> | ||
22 | 23 | ||
23 | #include <asm/irq.h> | 24 | #include <asm/irq.h> |
24 | #include <linux/atomic.h> | 25 | #include <linux/atomic.h> |
25 | #include <asm/mach/time.h> | 26 | #include <asm/mach/time.h> |
26 | #include <asm/mach/irq.h> | 27 | #include <asm/mach/irq.h> |
27 | 28 | ||
28 | #include <mach/at91_pmc.h> | ||
29 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
30 | 30 | ||
31 | #include "at91_aic.h" | 31 | #include "at91_aic.h" |
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 098c28ddf025..20018779bae7 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S | |||
@@ -13,8 +13,8 @@ | |||
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/linkage.h> | 15 | #include <linux/linkage.h> |
16 | #include <linux/clk/at91_pmc.h> | ||
16 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
17 | #include <mach/at91_pmc.h> | ||
18 | #include <mach/at91_ramc.h> | 18 | #include <mach/at91_ramc.h> |
19 | 19 | ||
20 | 20 | ||
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index 3ea86428ee09..3d775d08de08 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c | |||
@@ -9,360 +9,19 @@ | |||
9 | 9 | ||
10 | #include <linux/module.h> | 10 | #include <linux/module.h> |
11 | #include <linux/dma-mapping.h> | 11 | #include <linux/dma-mapping.h> |
12 | #include <linux/clk/at91_pmc.h> | ||
12 | 13 | ||
13 | #include <asm/irq.h> | 14 | #include <asm/irq.h> |
14 | #include <asm/mach/arch.h> | 15 | #include <asm/mach/arch.h> |
15 | #include <asm/mach/map.h> | 16 | #include <asm/mach/map.h> |
16 | #include <mach/sama5d3.h> | 17 | #include <mach/sama5d3.h> |
17 | #include <mach/at91_pmc.h> | ||
18 | #include <mach/cpu.h> | 18 | #include <mach/cpu.h> |
19 | 19 | ||
20 | #include "soc.h" | 20 | #include "soc.h" |
21 | #include "generic.h" | 21 | #include "generic.h" |
22 | #include "clock.h" | ||
23 | #include "sam9_smc.h" | 22 | #include "sam9_smc.h" |
24 | 23 | ||
25 | /* -------------------------------------------------------------------- | 24 | /* -------------------------------------------------------------------- |
26 | * Clocks | ||
27 | * -------------------------------------------------------------------- */ | ||
28 | |||
29 | /* | ||
30 | * The peripheral clocks. | ||
31 | */ | ||
32 | |||
33 | static struct clk pioA_clk = { | ||
34 | .name = "pioA_clk", | ||
35 | .pid = SAMA5D3_ID_PIOA, | ||
36 | .type = CLK_TYPE_PERIPHERAL, | ||
37 | }; | ||
38 | static struct clk pioB_clk = { | ||
39 | .name = "pioB_clk", | ||
40 | .pid = SAMA5D3_ID_PIOB, | ||
41 | .type = CLK_TYPE_PERIPHERAL, | ||
42 | }; | ||
43 | static struct clk pioC_clk = { | ||
44 | .name = "pioC_clk", | ||
45 | .pid = SAMA5D3_ID_PIOC, | ||
46 | .type = CLK_TYPE_PERIPHERAL, | ||
47 | }; | ||
48 | static struct clk pioD_clk = { | ||
49 | .name = "pioD_clk", | ||
50 | .pid = SAMA5D3_ID_PIOD, | ||
51 | .type = CLK_TYPE_PERIPHERAL, | ||
52 | }; | ||
53 | static struct clk pioE_clk = { | ||
54 | .name = "pioE_clk", | ||
55 | .pid = SAMA5D3_ID_PIOE, | ||
56 | .type = CLK_TYPE_PERIPHERAL, | ||
57 | }; | ||
58 | static struct clk usart0_clk = { | ||
59 | .name = "usart0_clk", | ||
60 | .pid = SAMA5D3_ID_USART0, | ||
61 | .type = CLK_TYPE_PERIPHERAL, | ||
62 | .div = AT91_PMC_PCR_DIV2, | ||
63 | }; | ||
64 | static struct clk usart1_clk = { | ||
65 | .name = "usart1_clk", | ||
66 | .pid = SAMA5D3_ID_USART1, | ||
67 | .type = CLK_TYPE_PERIPHERAL, | ||
68 | .div = AT91_PMC_PCR_DIV2, | ||
69 | }; | ||
70 | static struct clk usart2_clk = { | ||
71 | .name = "usart2_clk", | ||
72 | .pid = SAMA5D3_ID_USART2, | ||
73 | .type = CLK_TYPE_PERIPHERAL, | ||
74 | .div = AT91_PMC_PCR_DIV2, | ||
75 | }; | ||
76 | static struct clk usart3_clk = { | ||
77 | .name = "usart3_clk", | ||
78 | .pid = SAMA5D3_ID_USART3, | ||
79 | .type = CLK_TYPE_PERIPHERAL, | ||
80 | .div = AT91_PMC_PCR_DIV2, | ||
81 | }; | ||
82 | static struct clk uart0_clk = { | ||
83 | .name = "uart0_clk", | ||
84 | .pid = SAMA5D3_ID_UART0, | ||
85 | .type = CLK_TYPE_PERIPHERAL, | ||
86 | .div = AT91_PMC_PCR_DIV2, | ||
87 | }; | ||
88 | static struct clk uart1_clk = { | ||
89 | .name = "uart1_clk", | ||
90 | .pid = SAMA5D3_ID_UART1, | ||
91 | .type = CLK_TYPE_PERIPHERAL, | ||
92 | .div = AT91_PMC_PCR_DIV2, | ||
93 | }; | ||
94 | static struct clk twi0_clk = { | ||
95 | .name = "twi0_clk", | ||
96 | .pid = SAMA5D3_ID_TWI0, | ||
97 | .type = CLK_TYPE_PERIPHERAL, | ||
98 | .div = AT91_PMC_PCR_DIV2, | ||
99 | }; | ||
100 | static struct clk twi1_clk = { | ||
101 | .name = "twi1_clk", | ||
102 | .pid = SAMA5D3_ID_TWI1, | ||
103 | .type = CLK_TYPE_PERIPHERAL, | ||
104 | .div = AT91_PMC_PCR_DIV2, | ||
105 | }; | ||
106 | static struct clk twi2_clk = { | ||
107 | .name = "twi2_clk", | ||
108 | .pid = SAMA5D3_ID_TWI2, | ||
109 | .type = CLK_TYPE_PERIPHERAL, | ||
110 | .div = AT91_PMC_PCR_DIV2, | ||
111 | }; | ||
112 | static struct clk mmc0_clk = { | ||
113 | .name = "mci0_clk", | ||
114 | .pid = SAMA5D3_ID_HSMCI0, | ||
115 | .type = CLK_TYPE_PERIPHERAL, | ||
116 | }; | ||
117 | static struct clk mmc1_clk = { | ||
118 | .name = "mci1_clk", | ||
119 | .pid = SAMA5D3_ID_HSMCI1, | ||
120 | .type = CLK_TYPE_PERIPHERAL, | ||
121 | }; | ||
122 | static struct clk mmc2_clk = { | ||
123 | .name = "mci2_clk", | ||
124 | .pid = SAMA5D3_ID_HSMCI2, | ||
125 | .type = CLK_TYPE_PERIPHERAL, | ||
126 | }; | ||
127 | static struct clk spi0_clk = { | ||
128 | .name = "spi0_clk", | ||
129 | .pid = SAMA5D3_ID_SPI0, | ||
130 | .type = CLK_TYPE_PERIPHERAL, | ||
131 | }; | ||
132 | static struct clk spi1_clk = { | ||
133 | .name = "spi1_clk", | ||
134 | .pid = SAMA5D3_ID_SPI1, | ||
135 | .type = CLK_TYPE_PERIPHERAL, | ||
136 | }; | ||
137 | static struct clk tcb0_clk = { | ||
138 | .name = "tcb0_clk", | ||
139 | .pid = SAMA5D3_ID_TC0, | ||
140 | .type = CLK_TYPE_PERIPHERAL, | ||
141 | .div = AT91_PMC_PCR_DIV2, | ||
142 | }; | ||
143 | static struct clk tcb1_clk = { | ||
144 | .name = "tcb1_clk", | ||
145 | .pid = SAMA5D3_ID_TC1, | ||
146 | .type = CLK_TYPE_PERIPHERAL, | ||
147 | .div = AT91_PMC_PCR_DIV2, | ||
148 | }; | ||
149 | static struct clk adc_clk = { | ||
150 | .name = "adc_clk", | ||
151 | .pid = SAMA5D3_ID_ADC, | ||
152 | .type = CLK_TYPE_PERIPHERAL, | ||
153 | .div = AT91_PMC_PCR_DIV2, | ||
154 | }; | ||
155 | static struct clk adc_op_clk = { | ||
156 | .name = "adc_op_clk", | ||
157 | .type = CLK_TYPE_PERIPHERAL, | ||
158 | .rate_hz = 5000000, | ||
159 | }; | ||
160 | static struct clk dma0_clk = { | ||
161 | .name = "dma0_clk", | ||
162 | .pid = SAMA5D3_ID_DMA0, | ||
163 | .type = CLK_TYPE_PERIPHERAL, | ||
164 | }; | ||
165 | static struct clk dma1_clk = { | ||
166 | .name = "dma1_clk", | ||
167 | .pid = SAMA5D3_ID_DMA1, | ||
168 | .type = CLK_TYPE_PERIPHERAL, | ||
169 | }; | ||
170 | static struct clk uhphs_clk = { | ||
171 | .name = "uhphs", | ||
172 | .pid = SAMA5D3_ID_UHPHS, | ||
173 | .type = CLK_TYPE_PERIPHERAL, | ||
174 | }; | ||
175 | static struct clk udphs_clk = { | ||
176 | .name = "udphs_clk", | ||
177 | .pid = SAMA5D3_ID_UDPHS, | ||
178 | .type = CLK_TYPE_PERIPHERAL, | ||
179 | }; | ||
180 | /* gmac only for sama5d33, sama5d34, sama5d35 */ | ||
181 | static struct clk macb0_clk = { | ||
182 | .name = "macb0_clk", | ||
183 | .pid = SAMA5D3_ID_GMAC, | ||
184 | .type = CLK_TYPE_PERIPHERAL, | ||
185 | }; | ||
186 | /* emac only for sama5d31, sama5d35 */ | ||
187 | static struct clk macb1_clk = { | ||
188 | .name = "macb1_clk", | ||
189 | .pid = SAMA5D3_ID_EMAC, | ||
190 | .type = CLK_TYPE_PERIPHERAL, | ||
191 | }; | ||
192 | /* lcd only for sama5d31, sama5d33, sama5d34 */ | ||
193 | static struct clk lcdc_clk = { | ||
194 | .name = "lcdc_clk", | ||
195 | .pid = SAMA5D3_ID_LCDC, | ||
196 | .type = CLK_TYPE_PERIPHERAL, | ||
197 | }; | ||
198 | /* isi only for sama5d33, sama5d35 */ | ||
199 | static struct clk isi_clk = { | ||
200 | .name = "isi_clk", | ||
201 | .pid = SAMA5D3_ID_ISI, | ||
202 | .type = CLK_TYPE_PERIPHERAL, | ||
203 | }; | ||
204 | static struct clk can0_clk = { | ||
205 | .name = "can0_clk", | ||
206 | .pid = SAMA5D3_ID_CAN0, | ||
207 | .type = CLK_TYPE_PERIPHERAL, | ||
208 | .div = AT91_PMC_PCR_DIV2, | ||
209 | }; | ||
210 | static struct clk can1_clk = { | ||
211 | .name = "can1_clk", | ||
212 | .pid = SAMA5D3_ID_CAN1, | ||
213 | .type = CLK_TYPE_PERIPHERAL, | ||
214 | .div = AT91_PMC_PCR_DIV2, | ||
215 | }; | ||
216 | static struct clk ssc0_clk = { | ||
217 | .name = "ssc0_clk", | ||
218 | .pid = SAMA5D3_ID_SSC0, | ||
219 | .type = CLK_TYPE_PERIPHERAL, | ||
220 | .div = AT91_PMC_PCR_DIV2, | ||
221 | }; | ||
222 | static struct clk ssc1_clk = { | ||
223 | .name = "ssc1_clk", | ||
224 | .pid = SAMA5D3_ID_SSC1, | ||
225 | .type = CLK_TYPE_PERIPHERAL, | ||
226 | .div = AT91_PMC_PCR_DIV2, | ||
227 | }; | ||
228 | static struct clk sha_clk = { | ||
229 | .name = "sha_clk", | ||
230 | .pid = SAMA5D3_ID_SHA, | ||
231 | .type = CLK_TYPE_PERIPHERAL, | ||
232 | .div = AT91_PMC_PCR_DIV8, | ||
233 | }; | ||
234 | static struct clk aes_clk = { | ||
235 | .name = "aes_clk", | ||
236 | .pid = SAMA5D3_ID_AES, | ||
237 | .type = CLK_TYPE_PERIPHERAL, | ||
238 | }; | ||
239 | static struct clk tdes_clk = { | ||
240 | .name = "tdes_clk", | ||
241 | .pid = SAMA5D3_ID_TDES, | ||
242 | .type = CLK_TYPE_PERIPHERAL, | ||
243 | }; | ||
244 | |||
245 | static struct clk *periph_clocks[] __initdata = { | ||
246 | &pioA_clk, | ||
247 | &pioB_clk, | ||
248 | &pioC_clk, | ||
249 | &pioD_clk, | ||
250 | &pioE_clk, | ||
251 | &usart0_clk, | ||
252 | &usart1_clk, | ||
253 | &usart2_clk, | ||
254 | &usart3_clk, | ||
255 | &uart0_clk, | ||
256 | &uart1_clk, | ||
257 | &twi0_clk, | ||
258 | &twi1_clk, | ||
259 | &twi2_clk, | ||
260 | &mmc0_clk, | ||
261 | &mmc1_clk, | ||
262 | &mmc2_clk, | ||
263 | &spi0_clk, | ||
264 | &spi1_clk, | ||
265 | &tcb0_clk, | ||
266 | &tcb1_clk, | ||
267 | &adc_clk, | ||
268 | &adc_op_clk, | ||
269 | &dma0_clk, | ||
270 | &dma1_clk, | ||
271 | &uhphs_clk, | ||
272 | &udphs_clk, | ||
273 | &macb0_clk, | ||
274 | &macb1_clk, | ||
275 | &lcdc_clk, | ||
276 | &isi_clk, | ||
277 | &can0_clk, | ||
278 | &can1_clk, | ||
279 | &ssc0_clk, | ||
280 | &ssc1_clk, | ||
281 | &sha_clk, | ||
282 | &aes_clk, | ||
283 | &tdes_clk, | ||
284 | }; | ||
285 | |||
286 | static struct clk pck0 = { | ||
287 | .name = "pck0", | ||
288 | .pmc_mask = AT91_PMC_PCK0, | ||
289 | .type = CLK_TYPE_PROGRAMMABLE, | ||
290 | .id = 0, | ||
291 | }; | ||
292 | |||
293 | static struct clk pck1 = { | ||
294 | .name = "pck1", | ||
295 | .pmc_mask = AT91_PMC_PCK1, | ||
296 | .type = CLK_TYPE_PROGRAMMABLE, | ||
297 | .id = 1, | ||
298 | }; | ||
299 | |||
300 | static struct clk pck2 = { | ||
301 | .name = "pck2", | ||
302 | .pmc_mask = AT91_PMC_PCK2, | ||
303 | .type = CLK_TYPE_PROGRAMMABLE, | ||
304 | .id = 2, | ||
305 | }; | ||
306 | |||
307 | static struct clk_lookup periph_clocks_lookups[] = { | ||
308 | /* lookup table for DT entries */ | ||
309 | CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), | ||
310 | CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), | ||
311 | CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), | ||
312 | CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), | ||
313 | CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), | ||
314 | CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), | ||
315 | CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), | ||
316 | CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), | ||
317 | CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), | ||
318 | CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), | ||
319 | CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), | ||
320 | CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), | ||
321 | CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), | ||
322 | CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), | ||
323 | CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), | ||
324 | CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), | ||
325 | CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), | ||
326 | CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), | ||
327 | CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), | ||
328 | CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), | ||
329 | CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), | ||
330 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), | ||
331 | CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), | ||
332 | CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), | ||
333 | CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), | ||
334 | CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), | ||
335 | CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), | ||
336 | CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), | ||
337 | CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), | ||
338 | CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), | ||
339 | CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), | ||
340 | CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), | ||
341 | CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), | ||
342 | CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), | ||
343 | CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), | ||
344 | CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), | ||
345 | CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), | ||
346 | CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), | ||
347 | CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), | ||
348 | }; | ||
349 | |||
350 | static void __init sama5d3_register_clocks(void) | ||
351 | { | ||
352 | int i; | ||
353 | |||
354 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
355 | clk_register(periph_clocks[i]); | ||
356 | |||
357 | clkdev_add_table(periph_clocks_lookups, | ||
358 | ARRAY_SIZE(periph_clocks_lookups)); | ||
359 | |||
360 | clk_register(&pck0); | ||
361 | clk_register(&pck1); | ||
362 | clk_register(&pck2); | ||
363 | } | ||
364 | |||
365 | /* -------------------------------------------------------------------- | ||
366 | * AT91SAM9x5 processor initialization | 25 | * AT91SAM9x5 processor initialization |
367 | * -------------------------------------------------------------------- */ | 26 | * -------------------------------------------------------------------- */ |
368 | 27 | ||
@@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void) | |||
378 | 37 | ||
379 | AT91_SOC_START(sama5d3) | 38 | AT91_SOC_START(sama5d3) |
380 | .map_io = sama5d3_map_io, | 39 | .map_io = sama5d3_map_io, |
381 | .register_clocks = sama5d3_register_clocks, | ||
382 | .init = sama5d3_initialize, | 40 | .init = sama5d3_initialize, |
383 | AT91_SOC_END | 41 | AT91_SOC_END |
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 094b3459c288..7d3f7cc61081 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c | |||
@@ -11,6 +11,7 @@ | |||
11 | #include <linux/pm.h> | 11 | #include <linux/pm.h> |
12 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
13 | #include <linux/pinctrl/machine.h> | 13 | #include <linux/pinctrl/machine.h> |
14 | #include <linux/clk/at91_pmc.h> | ||
14 | 15 | ||
15 | #include <asm/system_misc.h> | 16 | #include <asm/system_misc.h> |
16 | #include <asm/mach/map.h> | 17 | #include <asm/mach/map.h> |
@@ -18,7 +19,6 @@ | |||
18 | #include <mach/hardware.h> | 19 | #include <mach/hardware.h> |
19 | #include <mach/cpu.h> | 20 | #include <mach/cpu.h> |
20 | #include <mach/at91_dbgu.h> | 21 | #include <mach/at91_dbgu.h> |
21 | #include <mach/at91_pmc.h> | ||
22 | 22 | ||
23 | #include "at91_shdwc.h" | 23 | #include "at91_shdwc.h" |
24 | #include "soc.h" | 24 | #include "soc.h" |
@@ -491,7 +491,8 @@ void __init at91rm9200_dt_initialize(void) | |||
491 | at91_dt_clock_init(); | 491 | at91_dt_clock_init(); |
492 | 492 | ||
493 | /* Register the processor-specific clocks */ | 493 | /* Register the processor-specific clocks */ |
494 | at91_boot_soc.register_clocks(); | 494 | if (at91_boot_soc.register_clocks) |
495 | at91_boot_soc.register_clocks(); | ||
495 | 496 | ||
496 | at91_boot_soc.init(); | 497 | at91_boot_soc.init(); |
497 | } | 498 | } |
@@ -506,7 +507,8 @@ void __init at91_dt_initialize(void) | |||
506 | at91_dt_clock_init(); | 507 | at91_dt_clock_init(); |
507 | 508 | ||
508 | /* Register the processor-specific clocks */ | 509 | /* Register the processor-specific clocks */ |
509 | at91_boot_soc.register_clocks(); | 510 | if (at91_boot_soc.register_clocks) |
511 | at91_boot_soc.register_clocks(); | ||
510 | 512 | ||
511 | if (at91_boot_soc.init) | 513 | if (at91_boot_soc.init) |
512 | at91_boot_soc.init(); | 514 | at91_boot_soc.init(); |
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 1f25f3e99c05..adcef406ff0a 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
@@ -19,11 +19,11 @@ secure-common = omap-smc.o omap-secure.o | |||
19 | 19 | ||
20 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) | 20 | obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common) |
21 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) | 21 | obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common) |
22 | obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) | 22 | obj-$(CONFIG_ARCH_OMAP4) += $(hwmod-common) $(secure-common) |
23 | obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) | 23 | obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) |
24 | obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) | 24 | obj-$(CONFIG_SOC_OMAP5) += $(hwmod-common) $(secure-common) |
25 | obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) | 25 | obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) |
26 | obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) | 26 | obj-$(CONFIG_SOC_DRA7XX) += $(hwmod-common) $(secure-common) |
27 | 27 | ||
28 | ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) | 28 | ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) |
29 | obj-y += mcbsp.o | 29 | obj-y += mcbsp.o |
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index f7644febee81..e30ef6797c63 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h | |||
@@ -299,7 +299,6 @@ struct omap_sdrc_params; | |||
299 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | 299 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
300 | struct omap_sdrc_params *sdrc_cs1); | 300 | struct omap_sdrc_params *sdrc_cs1); |
301 | struct omap2_hsmmc_info; | 301 | struct omap2_hsmmc_info; |
302 | extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); | ||
303 | extern void omap_reserve(void); | 302 | extern void omap_reserve(void); |
304 | 303 | ||
305 | struct omap_hwmod; | 304 | struct omap_hwmod; |
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index a4e536b11ec9..58347bb874a0 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c | |||
@@ -32,7 +32,6 @@ | |||
32 | 32 | ||
33 | #include "soc.h" | 33 | #include "soc.h" |
34 | #include "iomap.h" | 34 | #include "iomap.h" |
35 | #include "mux.h" | ||
36 | #include "control.h" | 35 | #include "control.h" |
37 | #include "display.h" | 36 | #include "display.h" |
38 | #include "prm.h" | 37 | #include "prm.h" |
@@ -102,90 +101,13 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { | |||
102 | { "dss_hdmi", "omapdss_hdmi", -1 }, | 101 | { "dss_hdmi", "omapdss_hdmi", -1 }, |
103 | }; | 102 | }; |
104 | 103 | ||
105 | static void __init omap4_tpd12s015_mux_pads(void) | ||
106 | { | ||
107 | omap_mux_init_signal("hdmi_cec", | ||
108 | OMAP_PIN_INPUT_PULLUP); | ||
109 | omap_mux_init_signal("hdmi_ddc_scl", | ||
110 | OMAP_PIN_INPUT_PULLUP); | ||
111 | omap_mux_init_signal("hdmi_ddc_sda", | ||
112 | OMAP_PIN_INPUT_PULLUP); | ||
113 | } | ||
114 | |||
115 | static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) | ||
116 | { | ||
117 | u32 reg; | ||
118 | u16 control_i2c_1; | ||
119 | |||
120 | /* | ||
121 | * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and | ||
122 | * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable | ||
123 | * internal pull up resistor. | ||
124 | */ | ||
125 | if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) { | ||
126 | control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1; | ||
127 | reg = omap4_ctrl_pad_readl(control_i2c_1); | ||
128 | reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK | | ||
129 | OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK); | ||
130 | omap4_ctrl_pad_writel(reg, control_i2c_1); | ||
131 | } | ||
132 | } | ||
133 | |||
134 | static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) | ||
135 | { | ||
136 | u32 enable_mask, enable_shift; | ||
137 | u32 pipd_mask, pipd_shift; | ||
138 | u32 reg; | ||
139 | |||
140 | if (dsi_id == 0) { | ||
141 | enable_mask = OMAP4_DSI1_LANEENABLE_MASK; | ||
142 | enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; | ||
143 | pipd_mask = OMAP4_DSI1_PIPD_MASK; | ||
144 | pipd_shift = OMAP4_DSI1_PIPD_SHIFT; | ||
145 | } else if (dsi_id == 1) { | ||
146 | enable_mask = OMAP4_DSI2_LANEENABLE_MASK; | ||
147 | enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; | ||
148 | pipd_mask = OMAP4_DSI2_PIPD_MASK; | ||
149 | pipd_shift = OMAP4_DSI2_PIPD_SHIFT; | ||
150 | } else { | ||
151 | return -ENODEV; | ||
152 | } | ||
153 | |||
154 | reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); | ||
155 | |||
156 | reg &= ~enable_mask; | ||
157 | reg &= ~pipd_mask; | ||
158 | |||
159 | reg |= (lanes << enable_shift) & enable_mask; | ||
160 | reg |= (lanes << pipd_shift) & pipd_mask; | ||
161 | |||
162 | omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); | ||
163 | |||
164 | return 0; | ||
165 | } | ||
166 | |||
167 | int __init omap_hdmi_init(enum omap_hdmi_flags flags) | ||
168 | { | ||
169 | if (cpu_is_omap44xx()) { | ||
170 | omap4_hdmi_mux_pads(flags); | ||
171 | omap4_tpd12s015_mux_pads(); | ||
172 | } | ||
173 | |||
174 | return 0; | ||
175 | } | ||
176 | |||
177 | static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) | 104 | static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) |
178 | { | 105 | { |
179 | if (cpu_is_omap44xx()) | ||
180 | return omap4_dsi_mux_pads(dsi_id, lane_mask); | ||
181 | |||
182 | return 0; | 106 | return 0; |
183 | } | 107 | } |
184 | 108 | ||
185 | static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) | 109 | static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) |
186 | { | 110 | { |
187 | if (cpu_is_omap44xx()) | ||
188 | omap4_dsi_mux_pads(dsi_id, 0); | ||
189 | } | 111 | } |
190 | 112 | ||
191 | static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) | 113 | static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) |
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index 81de56251955..d24926e6340f 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c | |||
@@ -1502,6 +1502,22 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, | |||
1502 | } | 1502 | } |
1503 | 1503 | ||
1504 | /* | 1504 | /* |
1505 | * For some GPMC devices we still need to rely on the bootloader | ||
1506 | * timings because the devices can be connected via FPGA. So far | ||
1507 | * the list is smc91x on the omap2 SDP boards, and 8250 on zooms. | ||
1508 | * REVISIT: Add timing support from slls644g.pdf and from the | ||
1509 | * lan91c96 manual. | ||
1510 | */ | ||
1511 | if (of_device_is_compatible(child, "ns16550a") || | ||
1512 | of_device_is_compatible(child, "smsc,lan91c94") || | ||
1513 | of_device_is_compatible(child, "smsc,lan91c111")) { | ||
1514 | dev_warn(&pdev->dev, | ||
1515 | "%s using bootloader timings on CS%d\n", | ||
1516 | child->name, cs); | ||
1517 | goto no_timings; | ||
1518 | } | ||
1519 | |||
1520 | /* | ||
1505 | * FIXME: gpmc_cs_request() will map the CS to an arbitary | 1521 | * FIXME: gpmc_cs_request() will map the CS to an arbitary |
1506 | * location in the gpmc address space. When booting with | 1522 | * location in the gpmc address space. When booting with |
1507 | * device-tree we want the NOR flash to be mapped to the | 1523 | * device-tree we want the NOR flash to be mapped to the |
@@ -1529,6 +1545,7 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, | |||
1529 | gpmc_read_timings_dt(child, &gpmc_t); | 1545 | gpmc_read_timings_dt(child, &gpmc_t); |
1530 | gpmc_cs_set_timings(cs, &gpmc_t); | 1546 | gpmc_cs_set_timings(cs, &gpmc_t); |
1531 | 1547 | ||
1548 | no_timings: | ||
1532 | if (of_platform_device_create(child, NULL, &pdev->dev)) | 1549 | if (of_platform_device_create(child, NULL, &pdev->dev)) |
1533 | return 0; | 1550 | return 0; |
1534 | 1551 | ||
@@ -1541,42 +1558,6 @@ err: | |||
1541 | return ret; | 1558 | return ret; |
1542 | } | 1559 | } |
1543 | 1560 | ||
1544 | /* | ||
1545 | * REVISIT: Add timing support from slls644g.pdf | ||
1546 | */ | ||
1547 | static int gpmc_probe_8250(struct platform_device *pdev, | ||
1548 | struct device_node *child) | ||
1549 | { | ||
1550 | struct resource res; | ||
1551 | unsigned long base; | ||
1552 | int ret, cs; | ||
1553 | |||
1554 | if (of_property_read_u32(child, "reg", &cs) < 0) { | ||
1555 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | ||
1556 | child->full_name); | ||
1557 | return -ENODEV; | ||
1558 | } | ||
1559 | |||
1560 | if (of_address_to_resource(child, 0, &res) < 0) { | ||
1561 | dev_err(&pdev->dev, "%s has malformed 'reg' property\n", | ||
1562 | child->full_name); | ||
1563 | return -ENODEV; | ||
1564 | } | ||
1565 | |||
1566 | ret = gpmc_cs_request(cs, resource_size(&res), &base); | ||
1567 | if (ret < 0) { | ||
1568 | dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); | ||
1569 | return ret; | ||
1570 | } | ||
1571 | |||
1572 | if (of_platform_device_create(child, NULL, &pdev->dev)) | ||
1573 | return 0; | ||
1574 | |||
1575 | dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name); | ||
1576 | |||
1577 | return -ENODEV; | ||
1578 | } | ||
1579 | |||
1580 | static int gpmc_probe_dt(struct platform_device *pdev) | 1561 | static int gpmc_probe_dt(struct platform_device *pdev) |
1581 | { | 1562 | { |
1582 | int ret; | 1563 | int ret; |
@@ -1618,10 +1599,9 @@ static int gpmc_probe_dt(struct platform_device *pdev) | |||
1618 | else if (of_node_cmp(child->name, "onenand") == 0) | 1599 | else if (of_node_cmp(child->name, "onenand") == 0) |
1619 | ret = gpmc_probe_onenand_child(pdev, child); | 1600 | ret = gpmc_probe_onenand_child(pdev, child); |
1620 | else if (of_node_cmp(child->name, "ethernet") == 0 || | 1601 | else if (of_node_cmp(child->name, "ethernet") == 0 || |
1621 | of_node_cmp(child->name, "nor") == 0) | 1602 | of_node_cmp(child->name, "nor") == 0 || |
1603 | of_node_cmp(child->name, "uart") == 0) | ||
1622 | ret = gpmc_probe_generic_child(pdev, child); | 1604 | ret = gpmc_probe_generic_child(pdev, child); |
1623 | else if (of_node_cmp(child->name, "8250") == 0) | ||
1624 | ret = gpmc_probe_8250(pdev, child); | ||
1625 | 1605 | ||
1626 | if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", | 1606 | if (WARN(ret < 0, "%s: probing gpmc child %s failed\n", |
1627 | __func__, child->full_name)) | 1607 | __func__, child->full_name)) |
diff --git a/arch/arm/mach-omap2/omap-secure.h b/arch/arm/mach-omap2/omap-secure.h index 8cc7d331437d..3e97c6c8ecf1 100644 --- a/arch/arm/mach-omap2/omap-secure.h +++ b/arch/arm/mach-omap2/omap-secure.h | |||
@@ -76,6 +76,13 @@ static inline void omap_barrier_reserve_memblock(void) | |||
76 | { } | 76 | { } |
77 | #endif | 77 | #endif |
78 | 78 | ||
79 | #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER | ||
79 | void set_cntfreq(void); | 80 | void set_cntfreq(void); |
81 | #else | ||
82 | static inline void set_cntfreq(void) | ||
83 | { | ||
84 | } | ||
85 | #endif | ||
86 | |||
80 | #endif /* __ASSEMBLER__ */ | 87 | #endif /* __ASSEMBLER__ */ |
81 | #endif /* OMAP_ARCH_OMAP_SECURE_H */ | 88 | #endif /* OMAP_ARCH_OMAP_SECURE_H */ |
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c index 57911430324e..b39efd46abf9 100644 --- a/arch/arm/mach-omap2/omap4-common.c +++ b/arch/arm/mach-omap2/omap4-common.c | |||
@@ -35,7 +35,6 @@ | |||
35 | #include "iomap.h" | 35 | #include "iomap.h" |
36 | #include "common.h" | 36 | #include "common.h" |
37 | #include "mmc.h" | 37 | #include "mmc.h" |
38 | #include "hsmmc.h" | ||
39 | #include "prminst44xx.h" | 38 | #include "prminst44xx.h" |
40 | #include "prcm_mpu44xx.h" | 39 | #include "prcm_mpu44xx.h" |
41 | #include "omap4-sar-layout.h" | 40 | #include "omap4-sar-layout.h" |
@@ -284,59 +283,3 @@ skip_errata_init: | |||
284 | omap_wakeupgen_init(); | 283 | omap_wakeupgen_init(); |
285 | irqchip_init(); | 284 | irqchip_init(); |
286 | } | 285 | } |
287 | |||
288 | #if defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) | ||
289 | static int omap4_twl6030_hsmmc_late_init(struct device *dev) | ||
290 | { | ||
291 | int irq = 0; | ||
292 | struct platform_device *pdev = container_of(dev, | ||
293 | struct platform_device, dev); | ||
294 | struct omap_mmc_platform_data *pdata = dev->platform_data; | ||
295 | |||
296 | /* Setting MMC1 Card detect Irq */ | ||
297 | if (pdev->id == 0) { | ||
298 | irq = twl6030_mmc_card_detect_config(); | ||
299 | if (irq < 0) { | ||
300 | dev_err(dev, "%s: Error card detect config(%d)\n", | ||
301 | __func__, irq); | ||
302 | return irq; | ||
303 | } | ||
304 | pdata->slots[0].card_detect_irq = irq; | ||
305 | pdata->slots[0].card_detect = twl6030_mmc_card_detect; | ||
306 | } | ||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | static __init void omap4_twl6030_hsmmc_set_late_init(struct device *dev) | ||
311 | { | ||
312 | struct omap_mmc_platform_data *pdata; | ||
313 | |||
314 | /* dev can be null if CONFIG_MMC_OMAP_HS is not set */ | ||
315 | if (!dev) { | ||
316 | pr_err("Failed %s\n", __func__); | ||
317 | return; | ||
318 | } | ||
319 | pdata = dev->platform_data; | ||
320 | pdata->init = omap4_twl6030_hsmmc_late_init; | ||
321 | } | ||
322 | |||
323 | int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) | ||
324 | { | ||
325 | struct omap2_hsmmc_info *c; | ||
326 | |||
327 | omap_hsmmc_init(controllers); | ||
328 | for (c = controllers; c->mmc; c++) { | ||
329 | /* pdev can be null if CONFIG_MMC_OMAP_HS is not set */ | ||
330 | if (!c->pdev) | ||
331 | continue; | ||
332 | omap4_twl6030_hsmmc_set_late_init(&c->pdev->dev); | ||
333 | } | ||
334 | |||
335 | return 0; | ||
336 | } | ||
337 | #else | ||
338 | int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers) | ||
339 | { | ||
340 | return 0; | ||
341 | } | ||
342 | #endif | ||
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 93b80e5da8d4..1f3770a8a728 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -120,7 +120,7 @@ static void omap3_save_secure_ram_context(void) | |||
120 | * will hang the system. | 120 | * will hang the system. |
121 | */ | 121 | */ |
122 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | 122 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
123 | ret = _omap_save_secure_sram((u32 *) | 123 | ret = _omap_save_secure_sram((u32 *)(unsigned long) |
124 | __pa(omap3_secure_ram_storage)); | 124 | __pa(omap3_secure_ram_storage)); |
125 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); | 125 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
126 | /* Following is for error tracking, it should not happen */ | 126 | /* Following is for error tracking, it should not happen */ |
diff --git a/arch/arm/mach-omap2/prm44xx_54xx.h b/arch/arm/mach-omap2/prm44xx_54xx.h index 7a976065e138..8d95aa543ef5 100644 --- a/arch/arm/mach-omap2/prm44xx_54xx.h +++ b/arch/arm/mach-omap2/prm44xx_54xx.h | |||
@@ -43,7 +43,7 @@ extern void omap4_prm_vcvp_write(u32 val, u8 offset); | |||
43 | extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); | 43 | extern u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset); |
44 | 44 | ||
45 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ | 45 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
46 | defined(CONFIG_SOC_DRA7XX) | 46 | defined(CONFIG_SOC_DRA7XX) || defined(CONFIG_SOC_AM43XX) |
47 | void omap44xx_prm_reconfigure_io_chain(void); | 47 | void omap44xx_prm_reconfigure_io_chain(void); |
48 | #else | 48 | #else |
49 | static inline void omap44xx_prm_reconfigure_io_chain(void) | 49 | static inline void omap44xx_prm_reconfigure_io_chain(void) |
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig index 2cb8dc55b50e..7094bccbae91 100644 --- a/arch/arm/mach-s3c64xx/Kconfig +++ b/arch/arm/mach-s3c64xx/Kconfig | |||
@@ -17,9 +17,10 @@ config CPU_S3C6410 | |||
17 | help | 17 | help |
18 | Enable S3C6410 CPU support | 18 | Enable S3C6410 CPU support |
19 | 19 | ||
20 | config S3C64XX_DMA | 20 | config S3C64XX_PL080 |
21 | bool "S3C64XX DMA" | 21 | bool "S3C64XX DMA using generic PL08x driver" |
22 | select S3C_DMA | 22 | select AMBA_PL08X |
23 | select SAMSUNG_DMADEV | ||
23 | 24 | ||
24 | config S3C64XX_SETUP_SDHCI | 25 | config S3C64XX_SETUP_SDHCI |
25 | bool | 26 | bool |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 6faedcffce04..58069a702a43 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
@@ -26,7 +26,7 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o | |||
26 | 26 | ||
27 | # DMA support | 27 | # DMA support |
28 | 28 | ||
29 | obj-$(CONFIG_S3C64XX_DMA) += dma.o | 29 | obj-$(CONFIG_S3C64XX_PL080) += pl080.o |
30 | 30 | ||
31 | # Device support | 31 | # Device support |
32 | 32 | ||
diff --git a/arch/arm/mach-s3c64xx/common.h b/arch/arm/mach-s3c64xx/common.h index bd3bd562011e..7043e7a3a67e 100644 --- a/arch/arm/mach-s3c64xx/common.h +++ b/arch/arm/mach-s3c64xx/common.h | |||
@@ -58,4 +58,9 @@ int __init s3c64xx_pm_late_initcall(void); | |||
58 | static inline int s3c64xx_pm_late_initcall(void) { return 0; } | 58 | static inline int s3c64xx_pm_late_initcall(void) { return 0; } |
59 | #endif | 59 | #endif |
60 | 60 | ||
61 | #ifdef CONFIG_S3C64XX_PL080 | ||
62 | extern struct pl08x_platform_data s3c64xx_dma0_plat_data; | ||
63 | extern struct pl08x_platform_data s3c64xx_dma1_plat_data; | ||
64 | #endif | ||
65 | |||
61 | #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ | 66 | #endif /* __ARCH_ARM_MACH_S3C64XX_COMMON_H */ |
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c deleted file mode 100644 index 7e22c2113816..000000000000 --- a/arch/arm/mach-s3c64xx/dma.c +++ /dev/null | |||
@@ -1,762 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c64xx/dma.c | ||
2 | * | ||
3 | * Copyright 2009 Openmoko, Inc. | ||
4 | * Copyright 2009 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX DMA core | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | /* | ||
16 | * NOTE: Code in this file is not used when booting with Device Tree support. | ||
17 | */ | ||
18 | |||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/module.h> | ||
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/dmapool.h> | ||
23 | #include <linux/device.h> | ||
24 | #include <linux/errno.h> | ||
25 | #include <linux/slab.h> | ||
26 | #include <linux/delay.h> | ||
27 | #include <linux/clk.h> | ||
28 | #include <linux/err.h> | ||
29 | #include <linux/io.h> | ||
30 | #include <linux/amba/pl080.h> | ||
31 | #include <linux/of.h> | ||
32 | |||
33 | #include <mach/dma.h> | ||
34 | #include <mach/map.h> | ||
35 | #include <mach/irqs.h> | ||
36 | |||
37 | #include "regs-sys.h" | ||
38 | |||
39 | /* dma channel state information */ | ||
40 | |||
41 | struct s3c64xx_dmac { | ||
42 | struct device dev; | ||
43 | struct clk *clk; | ||
44 | void __iomem *regs; | ||
45 | struct s3c2410_dma_chan *channels; | ||
46 | enum dma_ch chanbase; | ||
47 | }; | ||
48 | |||
49 | /* pool to provide LLI buffers */ | ||
50 | static struct dma_pool *dma_pool; | ||
51 | |||
52 | /* Debug configuration and code */ | ||
53 | |||
54 | static unsigned char debug_show_buffs = 0; | ||
55 | |||
56 | static void dbg_showchan(struct s3c2410_dma_chan *chan) | ||
57 | { | ||
58 | pr_debug("DMA%d: %08x->%08x L %08x C %08x,%08x S %08x\n", | ||
59 | chan->number, | ||
60 | readl(chan->regs + PL080_CH_SRC_ADDR), | ||
61 | readl(chan->regs + PL080_CH_DST_ADDR), | ||
62 | readl(chan->regs + PL080_CH_LLI), | ||
63 | readl(chan->regs + PL080_CH_CONTROL), | ||
64 | readl(chan->regs + PL080S_CH_CONTROL2), | ||
65 | readl(chan->regs + PL080S_CH_CONFIG)); | ||
66 | } | ||
67 | |||
68 | static void show_lli(struct pl080s_lli *lli) | ||
69 | { | ||
70 | pr_debug("LLI[%p] %08x->%08x, NL %08x C %08x,%08x\n", | ||
71 | lli, lli->src_addr, lli->dst_addr, lli->next_lli, | ||
72 | lli->control0, lli->control1); | ||
73 | } | ||
74 | |||
75 | static void dbg_showbuffs(struct s3c2410_dma_chan *chan) | ||
76 | { | ||
77 | struct s3c64xx_dma_buff *ptr; | ||
78 | struct s3c64xx_dma_buff *end; | ||
79 | |||
80 | pr_debug("DMA%d: buffs next %p, curr %p, end %p\n", | ||
81 | chan->number, chan->next, chan->curr, chan->end); | ||
82 | |||
83 | ptr = chan->next; | ||
84 | end = chan->end; | ||
85 | |||
86 | if (debug_show_buffs) { | ||
87 | for (; ptr != NULL; ptr = ptr->next) { | ||
88 | pr_debug("DMA%d: %08x ", | ||
89 | chan->number, ptr->lli_dma); | ||
90 | show_lli(ptr->lli); | ||
91 | } | ||
92 | } | ||
93 | } | ||
94 | |||
95 | /* End of Debug */ | ||
96 | |||
97 | static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel) | ||
98 | { | ||
99 | struct s3c2410_dma_chan *chan; | ||
100 | unsigned int start, offs; | ||
101 | |||
102 | start = 0; | ||
103 | |||
104 | if (channel >= DMACH_PCM1_TX) | ||
105 | start = 8; | ||
106 | |||
107 | for (offs = 0; offs < 8; offs++) { | ||
108 | chan = &s3c2410_chans[start + offs]; | ||
109 | if (!chan->in_use) | ||
110 | goto found; | ||
111 | } | ||
112 | |||
113 | return NULL; | ||
114 | |||
115 | found: | ||
116 | s3c_dma_chan_map[channel] = chan; | ||
117 | return chan; | ||
118 | } | ||
119 | |||
120 | int s3c2410_dma_config(enum dma_ch channel, int xferunit) | ||
121 | { | ||
122 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
123 | |||
124 | if (chan == NULL) | ||
125 | return -EINVAL; | ||
126 | |||
127 | switch (xferunit) { | ||
128 | case 1: | ||
129 | chan->hw_width = 0; | ||
130 | break; | ||
131 | case 2: | ||
132 | chan->hw_width = 1; | ||
133 | break; | ||
134 | case 4: | ||
135 | chan->hw_width = 2; | ||
136 | break; | ||
137 | default: | ||
138 | printk(KERN_ERR "%s: illegal width %d\n", __func__, xferunit); | ||
139 | return -EINVAL; | ||
140 | } | ||
141 | |||
142 | return 0; | ||
143 | } | ||
144 | EXPORT_SYMBOL(s3c2410_dma_config); | ||
145 | |||
146 | static void s3c64xx_dma_fill_lli(struct s3c2410_dma_chan *chan, | ||
147 | struct pl080s_lli *lli, | ||
148 | dma_addr_t data, int size) | ||
149 | { | ||
150 | dma_addr_t src, dst; | ||
151 | u32 control0, control1; | ||
152 | |||
153 | switch (chan->source) { | ||
154 | case DMA_FROM_DEVICE: | ||
155 | src = chan->dev_addr; | ||
156 | dst = data; | ||
157 | control0 = PL080_CONTROL_SRC_AHB2; | ||
158 | control0 |= PL080_CONTROL_DST_INCR; | ||
159 | break; | ||
160 | |||
161 | case DMA_TO_DEVICE: | ||
162 | src = data; | ||
163 | dst = chan->dev_addr; | ||
164 | control0 = PL080_CONTROL_DST_AHB2; | ||
165 | control0 |= PL080_CONTROL_SRC_INCR; | ||
166 | break; | ||
167 | default: | ||
168 | BUG(); | ||
169 | } | ||
170 | |||
171 | /* note, we do not currently setup any of the burst controls */ | ||
172 | |||
173 | control1 = size >> chan->hw_width; /* size in no of xfers */ | ||
174 | control0 |= PL080_CONTROL_PROT_SYS; /* always in priv. mode */ | ||
175 | control0 |= PL080_CONTROL_TC_IRQ_EN; /* always fire IRQ */ | ||
176 | control0 |= (u32)chan->hw_width << PL080_CONTROL_DWIDTH_SHIFT; | ||
177 | control0 |= (u32)chan->hw_width << PL080_CONTROL_SWIDTH_SHIFT; | ||
178 | |||
179 | lli->src_addr = src; | ||
180 | lli->dst_addr = dst; | ||
181 | lli->next_lli = 0; | ||
182 | lli->control0 = control0; | ||
183 | lli->control1 = control1; | ||
184 | } | ||
185 | |||
186 | static void s3c64xx_lli_to_regs(struct s3c2410_dma_chan *chan, | ||
187 | struct pl080s_lli *lli) | ||
188 | { | ||
189 | void __iomem *regs = chan->regs; | ||
190 | |||
191 | pr_debug("%s: LLI %p => regs\n", __func__, lli); | ||
192 | show_lli(lli); | ||
193 | |||
194 | writel(lli->src_addr, regs + PL080_CH_SRC_ADDR); | ||
195 | writel(lli->dst_addr, regs + PL080_CH_DST_ADDR); | ||
196 | writel(lli->next_lli, regs + PL080_CH_LLI); | ||
197 | writel(lli->control0, regs + PL080_CH_CONTROL); | ||
198 | writel(lli->control1, regs + PL080S_CH_CONTROL2); | ||
199 | } | ||
200 | |||
201 | static int s3c64xx_dma_start(struct s3c2410_dma_chan *chan) | ||
202 | { | ||
203 | struct s3c64xx_dmac *dmac = chan->dmac; | ||
204 | u32 config; | ||
205 | u32 bit = chan->bit; | ||
206 | |||
207 | dbg_showchan(chan); | ||
208 | |||
209 | pr_debug("%s: clearing interrupts\n", __func__); | ||
210 | |||
211 | /* clear interrupts */ | ||
212 | writel(bit, dmac->regs + PL080_TC_CLEAR); | ||
213 | writel(bit, dmac->regs + PL080_ERR_CLEAR); | ||
214 | |||
215 | pr_debug("%s: starting channel\n", __func__); | ||
216 | |||
217 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
218 | config |= PL080_CONFIG_ENABLE; | ||
219 | config &= ~PL080_CONFIG_HALT; | ||
220 | |||
221 | pr_debug("%s: writing config %08x\n", __func__, config); | ||
222 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
223 | |||
224 | return 0; | ||
225 | } | ||
226 | |||
227 | static int s3c64xx_dma_stop(struct s3c2410_dma_chan *chan) | ||
228 | { | ||
229 | u32 config; | ||
230 | int timeout; | ||
231 | |||
232 | pr_debug("%s: stopping channel\n", __func__); | ||
233 | |||
234 | dbg_showchan(chan); | ||
235 | |||
236 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
237 | config |= PL080_CONFIG_HALT; | ||
238 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
239 | |||
240 | timeout = 1000; | ||
241 | do { | ||
242 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
243 | pr_debug("%s: %d - config %08x\n", __func__, timeout, config); | ||
244 | if (config & PL080_CONFIG_ACTIVE) | ||
245 | udelay(10); | ||
246 | else | ||
247 | break; | ||
248 | } while (--timeout > 0); | ||
249 | |||
250 | if (config & PL080_CONFIG_ACTIVE) { | ||
251 | printk(KERN_ERR "%s: channel still active\n", __func__); | ||
252 | return -EFAULT; | ||
253 | } | ||
254 | |||
255 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
256 | config &= ~PL080_CONFIG_ENABLE; | ||
257 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
258 | |||
259 | return 0; | ||
260 | } | ||
261 | |||
262 | static inline void s3c64xx_dma_bufffdone(struct s3c2410_dma_chan *chan, | ||
263 | struct s3c64xx_dma_buff *buf, | ||
264 | enum s3c2410_dma_buffresult result) | ||
265 | { | ||
266 | if (chan->callback_fn != NULL) | ||
267 | (chan->callback_fn)(chan, buf->pw, 0, result); | ||
268 | } | ||
269 | |||
270 | static void s3c64xx_dma_freebuff(struct s3c64xx_dma_buff *buff) | ||
271 | { | ||
272 | dma_pool_free(dma_pool, buff->lli, buff->lli_dma); | ||
273 | kfree(buff); | ||
274 | } | ||
275 | |||
276 | static int s3c64xx_dma_flush(struct s3c2410_dma_chan *chan) | ||
277 | { | ||
278 | struct s3c64xx_dma_buff *buff, *next; | ||
279 | u32 config; | ||
280 | |||
281 | dbg_showchan(chan); | ||
282 | |||
283 | pr_debug("%s: flushing channel\n", __func__); | ||
284 | |||
285 | config = readl(chan->regs + PL080S_CH_CONFIG); | ||
286 | config &= ~PL080_CONFIG_ENABLE; | ||
287 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
288 | |||
289 | /* dump all the buffers associated with this channel */ | ||
290 | |||
291 | for (buff = chan->curr; buff != NULL; buff = next) { | ||
292 | next = buff->next; | ||
293 | pr_debug("%s: buff %p (next %p)\n", __func__, buff, buff->next); | ||
294 | |||
295 | s3c64xx_dma_bufffdone(chan, buff, S3C2410_RES_ABORT); | ||
296 | s3c64xx_dma_freebuff(buff); | ||
297 | } | ||
298 | |||
299 | chan->curr = chan->next = chan->end = NULL; | ||
300 | |||
301 | return 0; | ||
302 | } | ||
303 | |||
304 | int s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op) | ||
305 | { | ||
306 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
307 | |||
308 | WARN_ON(!chan); | ||
309 | if (!chan) | ||
310 | return -EINVAL; | ||
311 | |||
312 | switch (op) { | ||
313 | case S3C2410_DMAOP_START: | ||
314 | return s3c64xx_dma_start(chan); | ||
315 | |||
316 | case S3C2410_DMAOP_STOP: | ||
317 | return s3c64xx_dma_stop(chan); | ||
318 | |||
319 | case S3C2410_DMAOP_FLUSH: | ||
320 | return s3c64xx_dma_flush(chan); | ||
321 | |||
322 | /* believe PAUSE/RESUME are no-ops */ | ||
323 | case S3C2410_DMAOP_PAUSE: | ||
324 | case S3C2410_DMAOP_RESUME: | ||
325 | case S3C2410_DMAOP_STARTED: | ||
326 | case S3C2410_DMAOP_TIMEOUT: | ||
327 | return 0; | ||
328 | } | ||
329 | |||
330 | return -ENOENT; | ||
331 | } | ||
332 | EXPORT_SYMBOL(s3c2410_dma_ctrl); | ||
333 | |||
334 | /* s3c2410_dma_enque | ||
335 | * | ||
336 | */ | ||
337 | |||
338 | int s3c2410_dma_enqueue(enum dma_ch channel, void *id, | ||
339 | dma_addr_t data, int size) | ||
340 | { | ||
341 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
342 | struct s3c64xx_dma_buff *next; | ||
343 | struct s3c64xx_dma_buff *buff; | ||
344 | struct pl080s_lli *lli; | ||
345 | unsigned long flags; | ||
346 | int ret; | ||
347 | |||
348 | WARN_ON(!chan); | ||
349 | if (!chan) | ||
350 | return -EINVAL; | ||
351 | |||
352 | buff = kzalloc(sizeof(struct s3c64xx_dma_buff), GFP_ATOMIC); | ||
353 | if (!buff) { | ||
354 | printk(KERN_ERR "%s: no memory for buffer\n", __func__); | ||
355 | return -ENOMEM; | ||
356 | } | ||
357 | |||
358 | lli = dma_pool_alloc(dma_pool, GFP_ATOMIC, &buff->lli_dma); | ||
359 | if (!lli) { | ||
360 | printk(KERN_ERR "%s: no memory for lli\n", __func__); | ||
361 | ret = -ENOMEM; | ||
362 | goto err_buff; | ||
363 | } | ||
364 | |||
365 | pr_debug("%s: buff %p, dp %08x lli (%p, %08x) %d\n", | ||
366 | __func__, buff, data, lli, (u32)buff->lli_dma, size); | ||
367 | |||
368 | buff->lli = lli; | ||
369 | buff->pw = id; | ||
370 | |||
371 | s3c64xx_dma_fill_lli(chan, lli, data, size); | ||
372 | |||
373 | local_irq_save(flags); | ||
374 | |||
375 | if ((next = chan->next) != NULL) { | ||
376 | struct s3c64xx_dma_buff *end = chan->end; | ||
377 | struct pl080s_lli *endlli = end->lli; | ||
378 | |||
379 | pr_debug("enquing onto channel\n"); | ||
380 | |||
381 | end->next = buff; | ||
382 | endlli->next_lli = buff->lli_dma; | ||
383 | |||
384 | if (chan->flags & S3C2410_DMAF_CIRCULAR) { | ||
385 | struct s3c64xx_dma_buff *curr = chan->curr; | ||
386 | lli->next_lli = curr->lli_dma; | ||
387 | } | ||
388 | |||
389 | if (next == chan->curr) { | ||
390 | writel(buff->lli_dma, chan->regs + PL080_CH_LLI); | ||
391 | chan->next = buff; | ||
392 | } | ||
393 | |||
394 | show_lli(endlli); | ||
395 | chan->end = buff; | ||
396 | } else { | ||
397 | pr_debug("enquing onto empty channel\n"); | ||
398 | |||
399 | chan->curr = buff; | ||
400 | chan->next = buff; | ||
401 | chan->end = buff; | ||
402 | |||
403 | s3c64xx_lli_to_regs(chan, lli); | ||
404 | } | ||
405 | |||
406 | local_irq_restore(flags); | ||
407 | |||
408 | show_lli(lli); | ||
409 | |||
410 | dbg_showchan(chan); | ||
411 | dbg_showbuffs(chan); | ||
412 | return 0; | ||
413 | |||
414 | err_buff: | ||
415 | kfree(buff); | ||
416 | return ret; | ||
417 | } | ||
418 | |||
419 | EXPORT_SYMBOL(s3c2410_dma_enqueue); | ||
420 | |||
421 | |||
422 | int s3c2410_dma_devconfig(enum dma_ch channel, | ||
423 | enum dma_data_direction source, | ||
424 | unsigned long devaddr) | ||
425 | { | ||
426 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
427 | u32 peripheral; | ||
428 | u32 config = 0; | ||
429 | |||
430 | pr_debug("%s: channel %d, source %d, dev %08lx, chan %p\n", | ||
431 | __func__, channel, source, devaddr, chan); | ||
432 | |||
433 | WARN_ON(!chan); | ||
434 | if (!chan) | ||
435 | return -EINVAL; | ||
436 | |||
437 | peripheral = (chan->peripheral & 0xf); | ||
438 | chan->source = source; | ||
439 | chan->dev_addr = devaddr; | ||
440 | |||
441 | pr_debug("%s: peripheral %d\n", __func__, peripheral); | ||
442 | |||
443 | switch (source) { | ||
444 | case DMA_FROM_DEVICE: | ||
445 | config = 2 << PL080_CONFIG_FLOW_CONTROL_SHIFT; | ||
446 | config |= peripheral << PL080_CONFIG_SRC_SEL_SHIFT; | ||
447 | break; | ||
448 | case DMA_TO_DEVICE: | ||
449 | config = 1 << PL080_CONFIG_FLOW_CONTROL_SHIFT; | ||
450 | config |= peripheral << PL080_CONFIG_DST_SEL_SHIFT; | ||
451 | break; | ||
452 | default: | ||
453 | printk(KERN_ERR "%s: bad source\n", __func__); | ||
454 | return -EINVAL; | ||
455 | } | ||
456 | |||
457 | /* allow TC and ERR interrupts */ | ||
458 | config |= PL080_CONFIG_TC_IRQ_MASK; | ||
459 | config |= PL080_CONFIG_ERR_IRQ_MASK; | ||
460 | |||
461 | pr_debug("%s: config %08x\n", __func__, config); | ||
462 | |||
463 | writel(config, chan->regs + PL080S_CH_CONFIG); | ||
464 | |||
465 | return 0; | ||
466 | } | ||
467 | EXPORT_SYMBOL(s3c2410_dma_devconfig); | ||
468 | |||
469 | |||
470 | int s3c2410_dma_getposition(enum dma_ch channel, | ||
471 | dma_addr_t *src, dma_addr_t *dst) | ||
472 | { | ||
473 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
474 | |||
475 | WARN_ON(!chan); | ||
476 | if (!chan) | ||
477 | return -EINVAL; | ||
478 | |||
479 | if (src != NULL) | ||
480 | *src = readl(chan->regs + PL080_CH_SRC_ADDR); | ||
481 | |||
482 | if (dst != NULL) | ||
483 | *dst = readl(chan->regs + PL080_CH_DST_ADDR); | ||
484 | |||
485 | return 0; | ||
486 | } | ||
487 | EXPORT_SYMBOL(s3c2410_dma_getposition); | ||
488 | |||
489 | /* s3c2410_request_dma | ||
490 | * | ||
491 | * get control of an dma channel | ||
492 | */ | ||
493 | |||
494 | int s3c2410_dma_request(enum dma_ch channel, | ||
495 | struct s3c2410_dma_client *client, | ||
496 | void *dev) | ||
497 | { | ||
498 | struct s3c2410_dma_chan *chan; | ||
499 | unsigned long flags; | ||
500 | |||
501 | pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n", | ||
502 | channel, client->name, dev); | ||
503 | |||
504 | local_irq_save(flags); | ||
505 | |||
506 | chan = s3c64xx_dma_map_channel(channel); | ||
507 | if (chan == NULL) { | ||
508 | local_irq_restore(flags); | ||
509 | return -EBUSY; | ||
510 | } | ||
511 | |||
512 | dbg_showchan(chan); | ||
513 | |||
514 | chan->client = client; | ||
515 | chan->in_use = 1; | ||
516 | chan->peripheral = channel; | ||
517 | chan->flags = 0; | ||
518 | |||
519 | local_irq_restore(flags); | ||
520 | |||
521 | /* need to setup */ | ||
522 | |||
523 | pr_debug("%s: channel initialised, %p\n", __func__, chan); | ||
524 | |||
525 | return chan->number | DMACH_LOW_LEVEL; | ||
526 | } | ||
527 | |||
528 | EXPORT_SYMBOL(s3c2410_dma_request); | ||
529 | |||
530 | /* s3c2410_dma_free | ||
531 | * | ||
532 | * release the given channel back to the system, will stop and flush | ||
533 | * any outstanding transfers, and ensure the channel is ready for the | ||
534 | * next claimant. | ||
535 | * | ||
536 | * Note, although a warning is currently printed if the freeing client | ||
537 | * info is not the same as the registrant's client info, the free is still | ||
538 | * allowed to go through. | ||
539 | */ | ||
540 | |||
541 | int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client) | ||
542 | { | ||
543 | struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel); | ||
544 | unsigned long flags; | ||
545 | |||
546 | if (chan == NULL) | ||
547 | return -EINVAL; | ||
548 | |||
549 | local_irq_save(flags); | ||
550 | |||
551 | if (chan->client != client) { | ||
552 | printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n", | ||
553 | channel, chan->client, client); | ||
554 | } | ||
555 | |||
556 | /* sort out stopping and freeing the channel */ | ||
557 | |||
558 | |||
559 | chan->client = NULL; | ||
560 | chan->in_use = 0; | ||
561 | |||
562 | if (!(channel & DMACH_LOW_LEVEL)) | ||
563 | s3c_dma_chan_map[channel] = NULL; | ||
564 | |||
565 | local_irq_restore(flags); | ||
566 | |||
567 | return 0; | ||
568 | } | ||
569 | |||
570 | EXPORT_SYMBOL(s3c2410_dma_free); | ||
571 | |||
572 | static irqreturn_t s3c64xx_dma_irq(int irq, void *pw) | ||
573 | { | ||
574 | struct s3c64xx_dmac *dmac = pw; | ||
575 | struct s3c2410_dma_chan *chan; | ||
576 | enum s3c2410_dma_buffresult res; | ||
577 | u32 tcstat, errstat; | ||
578 | u32 bit; | ||
579 | int offs; | ||
580 | |||
581 | tcstat = readl(dmac->regs + PL080_TC_STATUS); | ||
582 | errstat = readl(dmac->regs + PL080_ERR_STATUS); | ||
583 | |||
584 | for (offs = 0, bit = 1; offs < 8; offs++, bit <<= 1) { | ||
585 | struct s3c64xx_dma_buff *buff; | ||
586 | |||
587 | if (!(errstat & bit) && !(tcstat & bit)) | ||
588 | continue; | ||
589 | |||
590 | chan = dmac->channels + offs; | ||
591 | res = S3C2410_RES_ERR; | ||
592 | |||
593 | if (tcstat & bit) { | ||
594 | writel(bit, dmac->regs + PL080_TC_CLEAR); | ||
595 | res = S3C2410_RES_OK; | ||
596 | } | ||
597 | |||
598 | if (errstat & bit) | ||
599 | writel(bit, dmac->regs + PL080_ERR_CLEAR); | ||
600 | |||
601 | /* 'next' points to the buffer that is next to the | ||
602 | * currently active buffer. | ||
603 | * For CIRCULAR queues, 'next' will be same as 'curr' | ||
604 | * when 'end' is the active buffer. | ||
605 | */ | ||
606 | buff = chan->curr; | ||
607 | while (buff && buff != chan->next | ||
608 | && buff->next != chan->next) | ||
609 | buff = buff->next; | ||
610 | |||
611 | if (!buff) | ||
612 | BUG(); | ||
613 | |||
614 | if (buff == chan->next) | ||
615 | buff = chan->end; | ||
616 | |||
617 | s3c64xx_dma_bufffdone(chan, buff, res); | ||
618 | |||
619 | /* Free the node and update curr, if non-circular queue */ | ||
620 | if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) { | ||
621 | chan->curr = buff->next; | ||
622 | s3c64xx_dma_freebuff(buff); | ||
623 | } | ||
624 | |||
625 | /* Update 'next' */ | ||
626 | buff = chan->next; | ||
627 | if (chan->next == chan->end) { | ||
628 | chan->next = chan->curr; | ||
629 | if (!(chan->flags & S3C2410_DMAF_CIRCULAR)) | ||
630 | chan->end = NULL; | ||
631 | } else { | ||
632 | chan->next = buff->next; | ||
633 | } | ||
634 | } | ||
635 | |||
636 | return IRQ_HANDLED; | ||
637 | } | ||
638 | |||
639 | static struct bus_type dma_subsys = { | ||
640 | .name = "s3c64xx-dma", | ||
641 | .dev_name = "s3c64xx-dma", | ||
642 | }; | ||
643 | |||
644 | static int s3c64xx_dma_init1(int chno, enum dma_ch chbase, | ||
645 | int irq, unsigned int base) | ||
646 | { | ||
647 | struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno]; | ||
648 | struct s3c64xx_dmac *dmac; | ||
649 | char clkname[16]; | ||
650 | void __iomem *regs; | ||
651 | void __iomem *regptr; | ||
652 | int err, ch; | ||
653 | |||
654 | dmac = kzalloc(sizeof(struct s3c64xx_dmac), GFP_KERNEL); | ||
655 | if (!dmac) { | ||
656 | printk(KERN_ERR "%s: failed to alloc mem\n", __func__); | ||
657 | return -ENOMEM; | ||
658 | } | ||
659 | |||
660 | dmac->dev.id = chno / 8; | ||
661 | dmac->dev.bus = &dma_subsys; | ||
662 | |||
663 | err = device_register(&dmac->dev); | ||
664 | if (err) { | ||
665 | printk(KERN_ERR "%s: failed to register device\n", __func__); | ||
666 | goto err_alloc; | ||
667 | } | ||
668 | |||
669 | regs = ioremap(base, 0x200); | ||
670 | if (!regs) { | ||
671 | printk(KERN_ERR "%s: failed to ioremap()\n", __func__); | ||
672 | err = -ENXIO; | ||
673 | goto err_dev; | ||
674 | } | ||
675 | |||
676 | snprintf(clkname, sizeof(clkname), "dma%d", dmac->dev.id); | ||
677 | |||
678 | dmac->clk = clk_get(NULL, clkname); | ||
679 | if (IS_ERR(dmac->clk)) { | ||
680 | printk(KERN_ERR "%s: failed to get clock %s\n", __func__, clkname); | ||
681 | err = PTR_ERR(dmac->clk); | ||
682 | goto err_map; | ||
683 | } | ||
684 | |||
685 | clk_prepare_enable(dmac->clk); | ||
686 | |||
687 | dmac->regs = regs; | ||
688 | dmac->chanbase = chbase; | ||
689 | dmac->channels = chptr; | ||
690 | |||
691 | err = request_irq(irq, s3c64xx_dma_irq, 0, "DMA", dmac); | ||
692 | if (err < 0) { | ||
693 | printk(KERN_ERR "%s: failed to get irq\n", __func__); | ||
694 | goto err_clk; | ||
695 | } | ||
696 | |||
697 | regptr = regs + PL080_Cx_BASE(0); | ||
698 | |||
699 | for (ch = 0; ch < 8; ch++, chptr++) { | ||
700 | pr_debug("%s: registering DMA %d (%p)\n", | ||
701 | __func__, chno + ch, regptr); | ||
702 | |||
703 | chptr->bit = 1 << ch; | ||
704 | chptr->number = chno + ch; | ||
705 | chptr->dmac = dmac; | ||
706 | chptr->regs = regptr; | ||
707 | regptr += PL080_Cx_STRIDE; | ||
708 | } | ||
709 | |||
710 | /* for the moment, permanently enable the controller */ | ||
711 | writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG); | ||
712 | |||
713 | printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n", | ||
714 | irq, regs, chno, chno+8); | ||
715 | |||
716 | return 0; | ||
717 | |||
718 | err_clk: | ||
719 | clk_disable_unprepare(dmac->clk); | ||
720 | clk_put(dmac->clk); | ||
721 | err_map: | ||
722 | iounmap(regs); | ||
723 | err_dev: | ||
724 | device_unregister(&dmac->dev); | ||
725 | err_alloc: | ||
726 | kfree(dmac); | ||
727 | return err; | ||
728 | } | ||
729 | |||
730 | static int __init s3c64xx_dma_init(void) | ||
731 | { | ||
732 | int ret; | ||
733 | |||
734 | /* This driver is not supported when booting with device tree. */ | ||
735 | if (of_have_populated_dt()) | ||
736 | return -ENODEV; | ||
737 | |||
738 | printk(KERN_INFO "%s: Registering DMA channels\n", __func__); | ||
739 | |||
740 | dma_pool = dma_pool_create("DMA-LLI", NULL, sizeof(struct pl080s_lli), 16, 0); | ||
741 | if (!dma_pool) { | ||
742 | printk(KERN_ERR "%s: failed to create pool\n", __func__); | ||
743 | return -ENOMEM; | ||
744 | } | ||
745 | |||
746 | ret = subsys_system_register(&dma_subsys, NULL); | ||
747 | if (ret) { | ||
748 | printk(KERN_ERR "%s: failed to create subsys\n", __func__); | ||
749 | return -ENOMEM; | ||
750 | } | ||
751 | |||
752 | /* Set all DMA configuration to be DMA, not SDMA */ | ||
753 | writel(0xffffff, S3C64XX_SDMA_SEL); | ||
754 | |||
755 | /* Register standard DMA controllers */ | ||
756 | s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000); | ||
757 | s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000); | ||
758 | |||
759 | return 0; | ||
760 | } | ||
761 | |||
762 | arch_initcall(s3c64xx_dma_init); | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h index fe1a98cf0e4c..059b1fc85037 100644 --- a/arch/arm/mach-s3c64xx/include/mach/dma.h +++ b/arch/arm/mach-s3c64xx/include/mach/dma.h | |||
@@ -11,51 +11,48 @@ | |||
11 | #ifndef __ASM_ARCH_DMA_H | 11 | #ifndef __ASM_ARCH_DMA_H |
12 | #define __ASM_ARCH_DMA_H __FILE__ | 12 | #define __ASM_ARCH_DMA_H __FILE__ |
13 | 13 | ||
14 | #define S3C_DMA_CHANNELS (16) | 14 | #define S3C64XX_DMA_CHAN(name) ((unsigned long)(name)) |
15 | |||
16 | /* DMA0/SDMA0 */ | ||
17 | #define DMACH_UART0 S3C64XX_DMA_CHAN("uart0_tx") | ||
18 | #define DMACH_UART0_SRC2 S3C64XX_DMA_CHAN("uart0_rx") | ||
19 | #define DMACH_UART1 S3C64XX_DMA_CHAN("uart1_tx") | ||
20 | #define DMACH_UART1_SRC2 S3C64XX_DMA_CHAN("uart1_rx") | ||
21 | #define DMACH_UART2 S3C64XX_DMA_CHAN("uart2_tx") | ||
22 | #define DMACH_UART2_SRC2 S3C64XX_DMA_CHAN("uart2_rx") | ||
23 | #define DMACH_UART3 S3C64XX_DMA_CHAN("uart3_tx") | ||
24 | #define DMACH_UART3_SRC2 S3C64XX_DMA_CHAN("uart3_rx") | ||
25 | #define DMACH_PCM0_TX S3C64XX_DMA_CHAN("pcm0_tx") | ||
26 | #define DMACH_PCM0_RX S3C64XX_DMA_CHAN("pcm0_rx") | ||
27 | #define DMACH_I2S0_OUT S3C64XX_DMA_CHAN("i2s0_tx") | ||
28 | #define DMACH_I2S0_IN S3C64XX_DMA_CHAN("i2s0_rx") | ||
29 | #define DMACH_SPI0_TX S3C64XX_DMA_CHAN("spi0_tx") | ||
30 | #define DMACH_SPI0_RX S3C64XX_DMA_CHAN("spi0_rx") | ||
31 | #define DMACH_HSI_I2SV40_TX S3C64XX_DMA_CHAN("i2s2_tx") | ||
32 | #define DMACH_HSI_I2SV40_RX S3C64XX_DMA_CHAN("i2s2_rx") | ||
33 | |||
34 | /* DMA1/SDMA1 */ | ||
35 | #define DMACH_PCM1_TX S3C64XX_DMA_CHAN("pcm1_tx") | ||
36 | #define DMACH_PCM1_RX S3C64XX_DMA_CHAN("pcm1_rx") | ||
37 | #define DMACH_I2S1_OUT S3C64XX_DMA_CHAN("i2s1_tx") | ||
38 | #define DMACH_I2S1_IN S3C64XX_DMA_CHAN("i2s1_rx") | ||
39 | #define DMACH_SPI1_TX S3C64XX_DMA_CHAN("spi1_tx") | ||
40 | #define DMACH_SPI1_RX S3C64XX_DMA_CHAN("spi1_rx") | ||
41 | #define DMACH_AC97_PCMOUT S3C64XX_DMA_CHAN("ac97_out") | ||
42 | #define DMACH_AC97_PCMIN S3C64XX_DMA_CHAN("ac97_in") | ||
43 | #define DMACH_AC97_MICIN S3C64XX_DMA_CHAN("ac97_mic") | ||
44 | #define DMACH_PWM S3C64XX_DMA_CHAN("pwm") | ||
45 | #define DMACH_IRDA S3C64XX_DMA_CHAN("irda") | ||
46 | #define DMACH_EXTERNAL S3C64XX_DMA_CHAN("external") | ||
47 | #define DMACH_SECURITY_RX S3C64XX_DMA_CHAN("sec_rx") | ||
48 | #define DMACH_SECURITY_TX S3C64XX_DMA_CHAN("sec_tx") | ||
15 | 49 | ||
16 | /* see mach-s3c2410/dma.h for notes on dma channel numbers */ | ||
17 | |||
18 | /* Note, for the S3C64XX architecture we keep the DMACH_ | ||
19 | * defines in the order they are allocated to [S]DMA0/[S]DMA1 | ||
20 | * so that is easy to do DHACH_ -> DMA controller conversion | ||
21 | */ | ||
22 | enum dma_ch { | 50 | enum dma_ch { |
23 | /* DMA0/SDMA0 */ | 51 | DMACH_MAX = 32 |
24 | DMACH_UART0 = 0, | 52 | }; |
25 | DMACH_UART0_SRC2, | ||
26 | DMACH_UART1, | ||
27 | DMACH_UART1_SRC2, | ||
28 | DMACH_UART2, | ||
29 | DMACH_UART2_SRC2, | ||
30 | DMACH_UART3, | ||
31 | DMACH_UART3_SRC2, | ||
32 | DMACH_PCM0_TX, | ||
33 | DMACH_PCM0_RX, | ||
34 | DMACH_I2S0_OUT, | ||
35 | DMACH_I2S0_IN, | ||
36 | DMACH_SPI0_TX, | ||
37 | DMACH_SPI0_RX, | ||
38 | DMACH_HSI_I2SV40_TX, | ||
39 | DMACH_HSI_I2SV40_RX, | ||
40 | 53 | ||
41 | /* DMA1/SDMA1 */ | 54 | struct s3c2410_dma_client { |
42 | DMACH_PCM1_TX = 16, | 55 | char *name; |
43 | DMACH_PCM1_RX, | ||
44 | DMACH_I2S1_OUT, | ||
45 | DMACH_I2S1_IN, | ||
46 | DMACH_SPI1_TX, | ||
47 | DMACH_SPI1_RX, | ||
48 | DMACH_AC97_PCMOUT, | ||
49 | DMACH_AC97_PCMIN, | ||
50 | DMACH_AC97_MICIN, | ||
51 | DMACH_PWM, | ||
52 | DMACH_IRDA, | ||
53 | DMACH_EXTERNAL, | ||
54 | DMACH_RES1, | ||
55 | DMACH_RES2, | ||
56 | DMACH_SECURITY_RX, /* SDMA1 only */ | ||
57 | DMACH_SECURITY_TX, /* SDMA1 only */ | ||
58 | DMACH_MAX /* the end */ | ||
59 | }; | 56 | }; |
60 | 57 | ||
61 | static inline bool samsung_dma_has_circular(void) | 58 | static inline bool samsung_dma_has_circular(void) |
@@ -65,67 +62,10 @@ static inline bool samsung_dma_has_circular(void) | |||
65 | 62 | ||
66 | static inline bool samsung_dma_is_dmadev(void) | 63 | static inline bool samsung_dma_is_dmadev(void) |
67 | { | 64 | { |
68 | return false; | 65 | return true; |
69 | } | 66 | } |
70 | #define S3C2410_DMAF_CIRCULAR (1 << 0) | ||
71 | |||
72 | #include <plat/dma.h> | ||
73 | |||
74 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
75 | |||
76 | struct s3c64xx_dma_buff; | ||
77 | |||
78 | /** s3c64xx_dma_buff - S3C64XX DMA buffer descriptor | ||
79 | * @next: Pointer to next buffer in queue or ring. | ||
80 | * @pw: Client provided identifier | ||
81 | * @lli: Pointer to hardware descriptor this buffer is associated with. | ||
82 | * @lli_dma: Hardare address of the descriptor. | ||
83 | */ | ||
84 | struct s3c64xx_dma_buff { | ||
85 | struct s3c64xx_dma_buff *next; | ||
86 | |||
87 | void *pw; | ||
88 | struct pl080s_lli *lli; | ||
89 | dma_addr_t lli_dma; | ||
90 | }; | ||
91 | |||
92 | struct s3c64xx_dmac; | ||
93 | |||
94 | struct s3c2410_dma_chan { | ||
95 | unsigned char number; /* number of this dma channel */ | ||
96 | unsigned char in_use; /* channel allocated */ | ||
97 | unsigned char bit; /* bit for enable/disable/etc */ | ||
98 | unsigned char hw_width; | ||
99 | unsigned char peripheral; | ||
100 | |||
101 | unsigned int flags; | ||
102 | enum dma_data_direction source; | ||
103 | |||
104 | |||
105 | dma_addr_t dev_addr; | ||
106 | |||
107 | struct s3c2410_dma_client *client; | ||
108 | struct s3c64xx_dmac *dmac; /* pointer to controller */ | ||
109 | |||
110 | void __iomem *regs; | ||
111 | |||
112 | /* cdriver callbacks */ | ||
113 | s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ | ||
114 | s3c2410_dma_opfn_t op_fn; /* channel op callback */ | ||
115 | |||
116 | /* buffer list and information */ | ||
117 | struct s3c64xx_dma_buff *curr; /* current dma buffer */ | ||
118 | struct s3c64xx_dma_buff *next; /* next buffer to load */ | ||
119 | struct s3c64xx_dma_buff *end; /* end of queue */ | ||
120 | |||
121 | /* note, when channel is running in circular mode, curr is the | ||
122 | * first buffer enqueued, end is the last and curr is where the | ||
123 | * last buffer-done event is set-at. The buffers are not freed | ||
124 | * and the last buffer hardware descriptor points back to the | ||
125 | * first. | ||
126 | */ | ||
127 | }; | ||
128 | 67 | ||
129 | #include <plat/dma-core.h> | 68 | #include <linux/amba/pl08x.h> |
69 | #include <plat/dma-ops.h> | ||
130 | 70 | ||
131 | #endif /* __ASM_ARCH_IRQ_H */ | 71 | #endif /* __ASM_ARCH_IRQ_H */ |
diff --git a/arch/arm/mach-s3c64xx/pl080.c b/arch/arm/mach-s3c64xx/pl080.c new file mode 100644 index 000000000000..901a984bddc2 --- /dev/null +++ b/arch/arm/mach-s3c64xx/pl080.c | |||
@@ -0,0 +1,244 @@ | |||
1 | /* | ||
2 | * Samsung's S3C64XX generic DMA support using amba-pl08x driver. | ||
3 | * | ||
4 | * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/amba/bus.h> | ||
13 | #include <linux/amba/pl080.h> | ||
14 | #include <linux/amba/pl08x.h> | ||
15 | #include <linux/of.h> | ||
16 | |||
17 | #include <mach/irqs.h> | ||
18 | #include <mach/map.h> | ||
19 | |||
20 | #include "regs-sys.h" | ||
21 | |||
22 | static int pl08x_get_xfer_signal(const struct pl08x_channel_data *cd) | ||
23 | { | ||
24 | return cd->min_signal; | ||
25 | } | ||
26 | |||
27 | static void pl08x_put_xfer_signal(const struct pl08x_channel_data *cd, int ch) | ||
28 | { | ||
29 | } | ||
30 | |||
31 | /* | ||
32 | * DMA0 | ||
33 | */ | ||
34 | |||
35 | static struct pl08x_channel_data s3c64xx_dma0_info[] = { | ||
36 | { | ||
37 | .bus_id = "uart0_tx", | ||
38 | .min_signal = 0, | ||
39 | .max_signal = 0, | ||
40 | .periph_buses = PL08X_AHB2, | ||
41 | }, { | ||
42 | .bus_id = "uart0_rx", | ||
43 | .min_signal = 1, | ||
44 | .max_signal = 1, | ||
45 | .periph_buses = PL08X_AHB2, | ||
46 | }, { | ||
47 | .bus_id = "uart1_tx", | ||
48 | .min_signal = 2, | ||
49 | .max_signal = 2, | ||
50 | .periph_buses = PL08X_AHB2, | ||
51 | }, { | ||
52 | .bus_id = "uart1_rx", | ||
53 | .min_signal = 3, | ||
54 | .max_signal = 3, | ||
55 | .periph_buses = PL08X_AHB2, | ||
56 | }, { | ||
57 | .bus_id = "uart2_tx", | ||
58 | .min_signal = 4, | ||
59 | .max_signal = 4, | ||
60 | .periph_buses = PL08X_AHB2, | ||
61 | }, { | ||
62 | .bus_id = "uart2_rx", | ||
63 | .min_signal = 5, | ||
64 | .max_signal = 5, | ||
65 | .periph_buses = PL08X_AHB2, | ||
66 | }, { | ||
67 | .bus_id = "uart3_tx", | ||
68 | .min_signal = 6, | ||
69 | .max_signal = 6, | ||
70 | .periph_buses = PL08X_AHB2, | ||
71 | }, { | ||
72 | .bus_id = "uart3_rx", | ||
73 | .min_signal = 7, | ||
74 | .max_signal = 7, | ||
75 | .periph_buses = PL08X_AHB2, | ||
76 | }, { | ||
77 | .bus_id = "pcm0_tx", | ||
78 | .min_signal = 8, | ||
79 | .max_signal = 8, | ||
80 | .periph_buses = PL08X_AHB2, | ||
81 | }, { | ||
82 | .bus_id = "pcm0_rx", | ||
83 | .min_signal = 9, | ||
84 | .max_signal = 9, | ||
85 | .periph_buses = PL08X_AHB2, | ||
86 | }, { | ||
87 | .bus_id = "i2s0_tx", | ||
88 | .min_signal = 10, | ||
89 | .max_signal = 10, | ||
90 | .periph_buses = PL08X_AHB2, | ||
91 | }, { | ||
92 | .bus_id = "i2s0_rx", | ||
93 | .min_signal = 11, | ||
94 | .max_signal = 11, | ||
95 | .periph_buses = PL08X_AHB2, | ||
96 | }, { | ||
97 | .bus_id = "spi0_tx", | ||
98 | .min_signal = 12, | ||
99 | .max_signal = 12, | ||
100 | .periph_buses = PL08X_AHB2, | ||
101 | }, { | ||
102 | .bus_id = "spi0_rx", | ||
103 | .min_signal = 13, | ||
104 | .max_signal = 13, | ||
105 | .periph_buses = PL08X_AHB2, | ||
106 | }, { | ||
107 | .bus_id = "i2s2_tx", | ||
108 | .min_signal = 14, | ||
109 | .max_signal = 14, | ||
110 | .periph_buses = PL08X_AHB2, | ||
111 | }, { | ||
112 | .bus_id = "i2s2_rx", | ||
113 | .min_signal = 15, | ||
114 | .max_signal = 15, | ||
115 | .periph_buses = PL08X_AHB2, | ||
116 | } | ||
117 | }; | ||
118 | |||
119 | struct pl08x_platform_data s3c64xx_dma0_plat_data = { | ||
120 | .memcpy_channel = { | ||
121 | .bus_id = "memcpy", | ||
122 | .cctl_memcpy = | ||
123 | (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | | ||
124 | PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | | ||
125 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | | ||
126 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | | ||
127 | PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | | ||
128 | PL080_CONTROL_PROT_SYS), | ||
129 | }, | ||
130 | .lli_buses = PL08X_AHB1, | ||
131 | .mem_buses = PL08X_AHB1, | ||
132 | .get_xfer_signal = pl08x_get_xfer_signal, | ||
133 | .put_xfer_signal = pl08x_put_xfer_signal, | ||
134 | .slave_channels = s3c64xx_dma0_info, | ||
135 | .num_slave_channels = ARRAY_SIZE(s3c64xx_dma0_info), | ||
136 | }; | ||
137 | |||
138 | static AMBA_AHB_DEVICE(s3c64xx_dma0, "dma-pl080s.0", 0, | ||
139 | 0x75000000, {IRQ_DMA0}, &s3c64xx_dma0_plat_data); | ||
140 | |||
141 | /* | ||
142 | * DMA1 | ||
143 | */ | ||
144 | |||
145 | static struct pl08x_channel_data s3c64xx_dma1_info[] = { | ||
146 | { | ||
147 | .bus_id = "pcm1_tx", | ||
148 | .min_signal = 0, | ||
149 | .max_signal = 0, | ||
150 | .periph_buses = PL08X_AHB2, | ||
151 | }, { | ||
152 | .bus_id = "pcm1_rx", | ||
153 | .min_signal = 1, | ||
154 | .max_signal = 1, | ||
155 | .periph_buses = PL08X_AHB2, | ||
156 | }, { | ||
157 | .bus_id = "i2s1_tx", | ||
158 | .min_signal = 2, | ||
159 | .max_signal = 2, | ||
160 | .periph_buses = PL08X_AHB2, | ||
161 | }, { | ||
162 | .bus_id = "i2s1_rx", | ||
163 | .min_signal = 3, | ||
164 | .max_signal = 3, | ||
165 | .periph_buses = PL08X_AHB2, | ||
166 | }, { | ||
167 | .bus_id = "spi1_tx", | ||
168 | .min_signal = 4, | ||
169 | .max_signal = 4, | ||
170 | .periph_buses = PL08X_AHB2, | ||
171 | }, { | ||
172 | .bus_id = "spi1_rx", | ||
173 | .min_signal = 5, | ||
174 | .max_signal = 5, | ||
175 | .periph_buses = PL08X_AHB2, | ||
176 | }, { | ||
177 | .bus_id = "ac97_out", | ||
178 | .min_signal = 6, | ||
179 | .max_signal = 6, | ||
180 | .periph_buses = PL08X_AHB2, | ||
181 | }, { | ||
182 | .bus_id = "ac97_in", | ||
183 | .min_signal = 7, | ||
184 | .max_signal = 7, | ||
185 | .periph_buses = PL08X_AHB2, | ||
186 | }, { | ||
187 | .bus_id = "ac97_mic", | ||
188 | .min_signal = 8, | ||
189 | .max_signal = 8, | ||
190 | .periph_buses = PL08X_AHB2, | ||
191 | }, { | ||
192 | .bus_id = "pwm", | ||
193 | .min_signal = 9, | ||
194 | .max_signal = 9, | ||
195 | .periph_buses = PL08X_AHB2, | ||
196 | }, { | ||
197 | .bus_id = "irda", | ||
198 | .min_signal = 10, | ||
199 | .max_signal = 10, | ||
200 | .periph_buses = PL08X_AHB2, | ||
201 | }, { | ||
202 | .bus_id = "external", | ||
203 | .min_signal = 11, | ||
204 | .max_signal = 11, | ||
205 | .periph_buses = PL08X_AHB2, | ||
206 | }, | ||
207 | }; | ||
208 | |||
209 | struct pl08x_platform_data s3c64xx_dma1_plat_data = { | ||
210 | .memcpy_channel = { | ||
211 | .bus_id = "memcpy", | ||
212 | .cctl_memcpy = | ||
213 | (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT | | ||
214 | PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT | | ||
215 | PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | | ||
216 | PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | | ||
217 | PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | | ||
218 | PL080_CONTROL_PROT_SYS), | ||
219 | }, | ||
220 | .lli_buses = PL08X_AHB1, | ||
221 | .mem_buses = PL08X_AHB1, | ||
222 | .get_xfer_signal = pl08x_get_xfer_signal, | ||
223 | .put_xfer_signal = pl08x_put_xfer_signal, | ||
224 | .slave_channels = s3c64xx_dma1_info, | ||
225 | .num_slave_channels = ARRAY_SIZE(s3c64xx_dma1_info), | ||
226 | }; | ||
227 | |||
228 | static AMBA_AHB_DEVICE(s3c64xx_dma1, "dma-pl080s.1", 0, | ||
229 | 0x75100000, {IRQ_DMA1}, &s3c64xx_dma1_plat_data); | ||
230 | |||
231 | static int __init s3c64xx_pl080_init(void) | ||
232 | { | ||
233 | /* Set all DMA configuration to be DMA, not SDMA */ | ||
234 | writel(0xffffff, S3C64XX_SDMA_SEL); | ||
235 | |||
236 | if (of_have_populated_dt()) | ||
237 | return 0; | ||
238 | |||
239 | amba_device_register(&s3c64xx_dma0_device, &iomem_resource); | ||
240 | amba_device_register(&s3c64xx_dma1_device, &iomem_resource); | ||
241 | |||
242 | return 0; | ||
243 | } | ||
244 | arch_initcall(s3c64xx_pl080_init); | ||
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig index a4a4b75109b2..8c8889211f6d 100644 --- a/arch/arm/mach-shmobile/Kconfig +++ b/arch/arm/mach-shmobile/Kconfig | |||
@@ -1,6 +1,10 @@ | |||
1 | config ARCH_SHMOBILE | ||
2 | bool | ||
3 | |||
1 | config ARCH_SHMOBILE_MULTI | 4 | config ARCH_SHMOBILE_MULTI |
2 | bool "SH-Mobile Series" if ARCH_MULTI_V7 | 5 | bool "SH-Mobile Series" if ARCH_MULTI_V7 |
3 | depends on MMU | 6 | depends on MMU |
7 | select ARCH_SHMOBILE | ||
4 | select CPU_V7 | 8 | select CPU_V7 |
5 | select GENERIC_CLOCKEVENTS | 9 | select GENERIC_CLOCKEVENTS |
6 | select HAVE_ARM_SCU if SMP | 10 | select HAVE_ARM_SCU if SMP |
@@ -8,6 +12,7 @@ config ARCH_SHMOBILE_MULTI | |||
8 | select HAVE_SMP | 12 | select HAVE_SMP |
9 | select ARM_GIC | 13 | select ARM_GIC |
10 | select MIGHT_HAVE_CACHE_L2X0 | 14 | select MIGHT_HAVE_CACHE_L2X0 |
15 | select MIGHT_HAVE_PCI | ||
11 | select NO_IOPORT | 16 | select NO_IOPORT |
12 | select PINCTRL | 17 | select PINCTRL |
13 | select ARCH_REQUIRE_GPIOLIB | 18 | select ARCH_REQUIRE_GPIOLIB |
@@ -30,7 +35,7 @@ config MACH_KZM9D | |||
30 | comment "SH-Mobile System Configuration" | 35 | comment "SH-Mobile System Configuration" |
31 | endif | 36 | endif |
32 | 37 | ||
33 | if ARCH_SHMOBILE | 38 | if ARCH_SHMOBILE_LEGACY |
34 | 39 | ||
35 | comment "SH-Mobile System Type" | 40 | comment "SH-Mobile System Type" |
36 | 41 | ||
@@ -92,23 +97,31 @@ config ARCH_R8A7790 | |||
92 | select ARCH_WANT_OPTIONAL_GPIOLIB | 97 | select ARCH_WANT_OPTIONAL_GPIOLIB |
93 | select ARM_GIC | 98 | select ARM_GIC |
94 | select CPU_V7 | 99 | select CPU_V7 |
100 | select MIGHT_HAVE_PCI | ||
95 | select SH_CLK_CPG | 101 | select SH_CLK_CPG |
96 | select RENESAS_IRQC | 102 | select RENESAS_IRQC |
97 | 103 | ||
98 | config ARCH_R8A7791 | 104 | config ARCH_R8A7791 |
99 | bool "R-Car M2 (R8A77910)" | 105 | bool "R-Car M2 (R8A77910)" |
106 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
100 | select ARM_GIC | 107 | select ARM_GIC |
101 | select CPU_V7 | 108 | select CPU_V7 |
109 | select MIGHT_HAVE_PCI | ||
102 | select SH_CLK_CPG | 110 | select SH_CLK_CPG |
111 | select RENESAS_IRQC | ||
103 | 112 | ||
104 | config ARCH_EMEV2 | 113 | config ARCH_EMEV2 |
105 | bool "Emma Mobile EV2" | 114 | bool "Emma Mobile EV2" |
106 | select ARCH_WANT_OPTIONAL_GPIOLIB | 115 | select ARCH_WANT_OPTIONAL_GPIOLIB |
107 | select ARM_GIC | 116 | select ARM_GIC |
108 | select CPU_V7 | 117 | select CPU_V7 |
118 | select MIGHT_HAVE_PCI | ||
119 | select USE_OF | ||
120 | select AUTO_ZRELADDR | ||
109 | 121 | ||
110 | config ARCH_R7S72100 | 122 | config ARCH_R7S72100 |
111 | bool "RZ/A1H (R7S72100)" | 123 | bool "RZ/A1H (R7S72100)" |
124 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
112 | select ARM_GIC | 125 | select ARM_GIC |
113 | select CPU_V7 | 126 | select CPU_V7 |
114 | select SH_CLK_CPG | 127 | select SH_CLK_CPG |
@@ -230,12 +243,7 @@ config MACH_KOELSCH | |||
230 | bool "Koelsch board" | 243 | bool "Koelsch board" |
231 | depends on ARCH_R8A7791 | 244 | depends on ARCH_R8A7791 |
232 | select USE_OF | 245 | select USE_OF |
233 | 246 | select MICREL_PHY if SH_ETH | |
234 | config MACH_KZM9D | ||
235 | bool "KZM9D board" | ||
236 | depends on ARCH_EMEV2 | ||
237 | select REGULATOR_FIXED_VOLTAGE if REGULATOR | ||
238 | select USE_OF | ||
239 | 247 | ||
240 | config MACH_KZM9G | 248 | config MACH_KZM9G |
241 | bool "KZM-A9-GT board" | 249 | bool "KZM-A9-GT board" |
@@ -274,7 +282,7 @@ source "drivers/sh/Kconfig" | |||
274 | 282 | ||
275 | endif | 283 | endif |
276 | 284 | ||
277 | if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI | 285 | if ARCH_SHMOBILE |
278 | 286 | ||
279 | menu "Timer and clock configuration" | 287 | menu "Timer and clock configuration" |
280 | 288 | ||
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile index 51db2bcafabf..c7e877499dc2 100644 --- a/arch/arm/mach-shmobile/Makefile +++ b/arch/arm/mach-shmobile/Makefile | |||
@@ -71,7 +71,6 @@ obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o | |||
71 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o | 71 | obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o |
72 | obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o | 72 | obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o |
73 | obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o | 73 | obj-$(CONFIG_MACH_KOELSCH) += board-koelsch.o |
74 | obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o | ||
75 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o | 74 | obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o |
76 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o | 75 | obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o |
77 | endif | 76 | endif |
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot index 391d72a5536c..4f30e3dc0919 100644 --- a/arch/arm/mach-shmobile/Makefile.boot +++ b/arch/arm/mach-shmobile/Makefile.boot | |||
@@ -8,7 +8,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 | |||
8 | loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 | 8 | loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 |
9 | loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 | 9 | loadaddr-$(CONFIG_MACH_GENMAI) += 0x8008000 |
10 | loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 | 10 | loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000 |
11 | loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 | ||
12 | loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 | 11 | loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 |
13 | loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 | 12 | loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 |
14 | loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 | 13 | loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 |
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 38611526fe9a..44b55ef8857e 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/mmc/sh_mmcif.h> | 25 | #include <linux/mmc/sh_mmcif.h> |
26 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
27 | #include <linux/pinctrl/machine.h> | 27 | #include <linux/pinctrl/machine.h> |
28 | #include <linux/platform_data/camera-rcar.h> | ||
28 | #include <linux/platform_data/usb-rcar-phy.h> | 29 | #include <linux/platform_data/usb-rcar-phy.h> |
29 | #include <linux/platform_device.h> | 30 | #include <linux/platform_device.h> |
30 | #include <linux/regulator/fixed.h> | 31 | #include <linux/regulator/fixed.h> |
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c deleted file mode 100644 index 30c2cc695b12..000000000000 --- a/arch/arm/mach-shmobile/board-kzm9d.c +++ /dev/null | |||
@@ -1,92 +0,0 @@ | |||
1 | /* | ||
2 | * kzm9d board support | ||
3 | * | ||
4 | * Copyright (C) 2012 Renesas Solutions Corp. | ||
5 | * Copyright (C) 2012 Magnus Damm | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; version 2 of the License. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/interrupt.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | #include <linux/regulator/fixed.h> | ||
25 | #include <linux/regulator/machine.h> | ||
26 | #include <linux/smsc911x.h> | ||
27 | #include <mach/common.h> | ||
28 | #include <mach/emev2.h> | ||
29 | #include <asm/mach-types.h> | ||
30 | #include <asm/mach/arch.h> | ||
31 | |||
32 | /* Dummy supplies, where voltage doesn't matter */ | ||
33 | static struct regulator_consumer_supply dummy_supplies[] = { | ||
34 | REGULATOR_SUPPLY("vddvario", "smsc911x"), | ||
35 | REGULATOR_SUPPLY("vdd33a", "smsc911x"), | ||
36 | }; | ||
37 | |||
38 | /* Ether */ | ||
39 | static struct resource smsc911x_resources[] = { | ||
40 | [0] = { | ||
41 | .start = 0x20000000, | ||
42 | .end = 0x2000ffff, | ||
43 | .flags = IORESOURCE_MEM, | ||
44 | }, | ||
45 | [1] = { | ||
46 | .start = EMEV2_GPIO_IRQ(1), | ||
47 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, | ||
48 | }, | ||
49 | }; | ||
50 | |||
51 | static struct smsc911x_platform_config smsc911x_platdata = { | ||
52 | .flags = SMSC911X_USE_32BIT, | ||
53 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | ||
54 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, | ||
55 | }; | ||
56 | |||
57 | static struct platform_device smsc91x_device = { | ||
58 | .name = "smsc911x", | ||
59 | .id = -1, | ||
60 | .dev = { | ||
61 | .platform_data = &smsc911x_platdata, | ||
62 | }, | ||
63 | .num_resources = ARRAY_SIZE(smsc911x_resources), | ||
64 | .resource = smsc911x_resources, | ||
65 | }; | ||
66 | |||
67 | static struct platform_device *kzm9d_devices[] __initdata = { | ||
68 | &smsc91x_device, | ||
69 | }; | ||
70 | |||
71 | void __init kzm9d_add_standard_devices(void) | ||
72 | { | ||
73 | regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); | ||
74 | |||
75 | emev2_add_standard_devices(); | ||
76 | |||
77 | platform_add_devices(kzm9d_devices, ARRAY_SIZE(kzm9d_devices)); | ||
78 | } | ||
79 | |||
80 | static const char *kzm9d_boards_compat_dt[] __initdata = { | ||
81 | "renesas,kzm9d", | ||
82 | NULL, | ||
83 | }; | ||
84 | |||
85 | DT_MACHINE_START(KZM9D_DT, "kzm9d") | ||
86 | .smp = smp_ops(emev2_smp_ops), | ||
87 | .map_io = emev2_map_io, | ||
88 | .init_early = emev2_init_delay, | ||
89 | .init_machine = kzm9d_add_standard_devices, | ||
90 | .init_late = shmobile_init_late, | ||
91 | .dt_compat = kzm9d_boards_compat_dt, | ||
92 | MACHINE_END | ||
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index 4aba20ca127e..850a8a371b43 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #define FRQCR2 0xfcfe0014 | 27 | #define FRQCR2 0xfcfe0014 |
28 | #define STBCR3 0xfcfe0420 | 28 | #define STBCR3 0xfcfe0420 |
29 | #define STBCR4 0xfcfe0424 | 29 | #define STBCR4 0xfcfe0424 |
30 | #define STBCR9 0xfcfe0438 | ||
30 | 31 | ||
31 | #define PLL_RATE 30 | 32 | #define PLL_RATE 30 |
32 | 33 | ||
@@ -144,10 +145,15 @@ struct clk div4_clks[DIV4_NR] = { | |||
144 | | CLK_ENABLE_ON_INIT), | 145 | | CLK_ENABLE_ON_INIT), |
145 | }; | 146 | }; |
146 | 147 | ||
147 | enum { MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | 148 | enum { MSTP97, MSTP96, MSTP95, MSTP94, |
149 | MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40, | ||
148 | MSTP33, MSTP_NR }; | 150 | MSTP33, MSTP_NR }; |
149 | 151 | ||
150 | static struct clk mstp_clks[MSTP_NR] = { | 152 | static struct clk mstp_clks[MSTP_NR] = { |
153 | [MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */ | ||
154 | [MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */ | ||
155 | [MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */ | ||
156 | [MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */ | ||
151 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ | 157 | [MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */ |
152 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ | 158 | [MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */ |
153 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ | 159 | [MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */ |
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index c826bca4024e..e9a3c6401845 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
@@ -585,6 +585,7 @@ static struct clk_lookup lookups[] = { | |||
585 | 585 | ||
586 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), | 586 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), |
587 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), | 587 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), |
588 | CLKDEV_DEV_ID("fe1f0000.sound", &mstp_clks[MSTP328]), | ||
588 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), | 589 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), |
589 | CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), | 590 | CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), |
590 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), | 591 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]), |
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index fb6af83858e3..dfb0fff4d24c 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c | |||
@@ -115,6 +115,8 @@ static struct clk *main_clks[] = { | |||
115 | }; | 115 | }; |
116 | 116 | ||
117 | enum { | 117 | enum { |
118 | MSTP531, MSTP530, | ||
119 | MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523, | ||
118 | MSTP331, | 120 | MSTP331, |
119 | MSTP323, MSTP322, MSTP321, | 121 | MSTP323, MSTP322, MSTP321, |
120 | MSTP311, MSTP310, | 122 | MSTP311, MSTP310, |
@@ -129,6 +131,15 @@ enum { | |||
129 | MSTP_NR }; | 131 | MSTP_NR }; |
130 | 132 | ||
131 | static struct clk mstp_clks[MSTP_NR] = { | 133 | static struct clk mstp_clks[MSTP_NR] = { |
134 | [MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */ | ||
135 | [MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */ | ||
136 | [MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */ | ||
137 | [MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */ | ||
138 | [MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */ | ||
139 | [MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */ | ||
140 | [MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */ | ||
141 | [MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */ | ||
142 | [MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */ | ||
132 | [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ | 143 | [MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */ |
133 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ | 144 | [MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */ |
134 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ | 145 | [MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */ |
@@ -173,9 +184,13 @@ static struct clk_lookup lookups[] = { | |||
173 | 184 | ||
174 | /* MSTP32 clocks */ | 185 | /* MSTP32 clocks */ |
175 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ | 186 | CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */ |
187 | CLKDEV_DEV_ID("ffe4e000.mmcif", &mstp_clks[MSTP331]), /* MMC */ | ||
176 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ | 188 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ |
189 | CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ | ||
177 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 190 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
191 | CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ | ||
178 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 192 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
193 | CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ | ||
179 | CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ | 194 | CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */ |
180 | CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ | 195 | CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */ |
181 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ | 196 | CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */ |
@@ -183,9 +198,13 @@ static struct clk_lookup lookups[] = { | |||
183 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ | 198 | CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */ |
184 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ | 199 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */ |
185 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ | 200 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ |
201 | CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ | ||
186 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ | 202 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ |
203 | CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ | ||
187 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ | 204 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ |
205 | CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ | ||
188 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ | 206 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ |
207 | CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ | ||
189 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ | 208 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ |
190 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ | 209 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ |
191 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ | 210 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ |
@@ -195,8 +214,11 @@ static struct clk_lookup lookups[] = { | |||
195 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ | 214 | CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */ |
196 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ | 215 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */ |
197 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ | 216 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ |
217 | CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ | ||
198 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ | 218 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ |
219 | CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ | ||
199 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ | 220 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ |
221 | CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ | ||
200 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ | 222 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */ |
201 | 223 | ||
202 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), | 224 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]), |
@@ -208,6 +230,15 @@ static struct clk_lookup lookups[] = { | |||
208 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), | 230 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]), |
209 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), | 231 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]), |
210 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), | 232 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]), |
233 | CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]), | ||
234 | CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]), | ||
235 | CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]), | ||
236 | CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]), | ||
237 | CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]), | ||
238 | CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]), | ||
239 | CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]), | ||
240 | CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]), | ||
241 | CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]), | ||
211 | }; | 242 | }; |
212 | 243 | ||
213 | void __init r8a7778_clock_init(void) | 244 | void __init r8a7778_clock_init(void) |
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index 1f7080fab0a5..b545c8dbb818 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c | |||
@@ -184,9 +184,13 @@ static struct clk_lookup lookups[] = { | |||
184 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ | 184 | CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */ |
185 | CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ | 185 | CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */ |
186 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ | 186 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */ |
187 | CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */ | ||
187 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ | 188 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */ |
189 | CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */ | ||
188 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ | 190 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */ |
191 | CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */ | ||
189 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ | 192 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */ |
193 | CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */ | ||
190 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ | 194 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */ |
191 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ | 195 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */ |
192 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ | 196 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */ |
@@ -194,12 +198,19 @@ static struct clk_lookup lookups[] = { | |||
194 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ | 198 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */ |
195 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ | 199 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */ |
196 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ | 200 | CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */ |
201 | CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */ | ||
197 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ | 202 | CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */ |
203 | CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */ | ||
198 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ | 204 | CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */ |
205 | CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */ | ||
199 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ | 206 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */ |
207 | CLKDEV_DEV_ID("ffe4c000.sdhi", &mstp_clks[MSTP323]), /* SDHI0 */ | ||
200 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ | 208 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */ |
209 | CLKDEV_DEV_ID("ffe4d000.sdhi", &mstp_clks[MSTP322]), /* SDHI1 */ | ||
201 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ | 210 | CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */ |
211 | CLKDEV_DEV_ID("ffe4e000.sdhi", &mstp_clks[MSTP321]), /* SDHI2 */ | ||
202 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ | 212 | CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */ |
213 | CLKDEV_DEV_ID("ffe4f000.sdhi", &mstp_clks[MSTP320]), /* SDHI3 */ | ||
203 | CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ | 214 | CLKDEV_DEV_ID("rcar-du-r8a7779", &mstp_clks[MSTP103]), /* DU */ |
204 | }; | 215 | }; |
205 | 216 | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index a64f965c7da1..b6ecea3ec7d5 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
@@ -53,6 +53,7 @@ | |||
53 | #define SMSTPCR7 0xe615014c | 53 | #define SMSTPCR7 0xe615014c |
54 | #define SMSTPCR8 0xe6150990 | 54 | #define SMSTPCR8 0xe6150990 |
55 | #define SMSTPCR9 0xe6150994 | 55 | #define SMSTPCR9 0xe6150994 |
56 | #define SMSTPCR10 0xe6150998 | ||
56 | 57 | ||
57 | #define SDCKCR 0xE6150074 | 58 | #define SDCKCR 0xE6150074 |
58 | #define SD2CKCR 0xE6150078 | 59 | #define SD2CKCR 0xE6150078 |
@@ -182,10 +183,14 @@ static struct clk div6_clks[DIV6_NR] = { | |||
182 | 183 | ||
183 | /* MSTP */ | 184 | /* MSTP */ |
184 | enum { | 185 | enum { |
186 | MSTP1015, MSTP1014, MSTP1013, MSTP1012, MSTP1011, MSTP1010, | ||
187 | MSTP1009, MSTP1008, MSTP1007, MSTP1006, MSTP1005, | ||
185 | MSTP931, MSTP930, MSTP929, MSTP928, | 188 | MSTP931, MSTP930, MSTP929, MSTP928, |
189 | MSTP917, | ||
186 | MSTP813, | 190 | MSTP813, |
187 | MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, | 191 | MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720, |
188 | MSTP717, MSTP716, | 192 | MSTP717, MSTP716, |
193 | MSTP704, | ||
189 | MSTP522, | 194 | MSTP522, |
190 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, | 195 | MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, |
191 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, | 196 | MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, |
@@ -194,10 +199,22 @@ enum { | |||
194 | }; | 199 | }; |
195 | 200 | ||
196 | static struct clk mstp_clks[MSTP_NR] = { | 201 | static struct clk mstp_clks[MSTP_NR] = { |
197 | [MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */ | 202 | [MSTP1015] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 15, 0), /* SSI0 */ |
198 | [MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */ | 203 | [MSTP1014] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 14, 0), /* SSI1 */ |
199 | [MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */ | 204 | [MSTP1013] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 13, 0), /* SSI2 */ |
200 | [MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */ | 205 | [MSTP1012] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 12, 0), /* SSI3 */ |
206 | [MSTP1011] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 11, 0), /* SSI4 */ | ||
207 | [MSTP1010] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 10, 0), /* SSI5 */ | ||
208 | [MSTP1009] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 9, 0), /* SSI6 */ | ||
209 | [MSTP1008] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 8, 0), /* SSI7 */ | ||
210 | [MSTP1007] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 7, 0), /* SSI8 */ | ||
211 | [MSTP1006] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 6, 0), /* SSI9 */ | ||
212 | [MSTP1005] = SH_CLK_MSTP32(&p_clk, SMSTPCR10, 5, 0), /* SSI ALL */ | ||
213 | [MSTP931] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 31, 0), /* I2C0 */ | ||
214 | [MSTP930] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 30, 0), /* I2C1 */ | ||
215 | [MSTP929] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 29, 0), /* I2C2 */ | ||
216 | [MSTP928] = SH_CLK_MSTP32(&p_clk, SMSTPCR9, 28, 0), /* I2C3 */ | ||
217 | [MSTP917] = SH_CLK_MSTP32(&qspi_clk, SMSTPCR9, 17, 0), /* QSPI */ | ||
201 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | 218 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ |
202 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ | 219 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ |
203 | [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ | 220 | [MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */ |
@@ -208,6 +225,7 @@ static struct clk mstp_clks[MSTP_NR] = { | |||
208 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 225 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
209 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ | 226 | [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ |
210 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ | 227 | [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */ |
228 | [MSTP704] = SH_CLK_MSTP32(&mp_clk, SMSTPCR7, 4, 0), /* HSUSB */ | ||
211 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ | 229 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ |
212 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ | 230 | [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ |
213 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ | 231 | [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ |
@@ -262,11 +280,7 @@ static struct clk_lookup lookups[] = { | |||
262 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), | 280 | CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]), |
263 | 281 | ||
264 | /* MSTP */ | 282 | /* MSTP */ |
265 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), | 283 | CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP1005]), |
266 | CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), | ||
267 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), | ||
268 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), | ||
269 | CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), | ||
270 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), | 284 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), |
271 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), | 285 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), |
272 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), | 286 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), |
@@ -278,10 +292,15 @@ static struct clk_lookup lookups[] = { | |||
278 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), | 292 | CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), |
279 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), | 293 | CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), |
280 | CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), | 294 | CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]), |
295 | CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP931]), | ||
281 | CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), | 296 | CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]), |
297 | CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP930]), | ||
282 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), | 298 | CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]), |
299 | CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP929]), | ||
283 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), | 300 | CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]), |
301 | CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP928]), | ||
284 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), | 302 | CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]), |
303 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), | ||
285 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | 304 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), |
286 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), | 305 | CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), |
287 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), | 306 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), |
@@ -296,6 +315,27 @@ static struct clk_lookup lookups[] = { | |||
296 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), | 315 | CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), |
297 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), | 316 | CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), |
298 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | 317 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), |
318 | CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]), | ||
319 | CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]), | ||
320 | |||
321 | /* ICK */ | ||
322 | CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]), | ||
323 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]), | ||
324 | CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]), | ||
325 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]), | ||
326 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]), | ||
327 | CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]), | ||
328 | CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]), | ||
329 | CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]), | ||
330 | CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]), | ||
331 | CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP1012]), | ||
332 | CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP1011]), | ||
333 | CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP1010]), | ||
334 | CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP1009]), | ||
335 | CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP1008]), | ||
336 | CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP1007]), | ||
337 | CLKDEV_ICK_ID("ssi.9", "rcar_sound", &mstp_clks[MSTP1006]), | ||
338 | |||
299 | }; | 339 | }; |
300 | 340 | ||
301 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | 341 | #define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
@@ -321,10 +361,10 @@ void __init r8a7790_clock_init(void) | |||
321 | R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); | 361 | R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66); |
322 | break; | 362 | break; |
323 | case MD(14): | 363 | case MD(14): |
324 | R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102); | 364 | R8A7790_CLOCK_ROOT(26 / 2, &extal_div2_clk, 200, 240, 122, 102); |
325 | break; | 365 | break; |
326 | case MD(13) | MD(14): | 366 | case MD(13) | MD(14): |
327 | R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88); | 367 | R8A7790_CLOCK_ROOT(30 / 2, &extal_div2_clk, 172, 208, 106, 88); |
328 | break; | 368 | break; |
329 | } | 369 | } |
330 | 370 | ||
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index c9a26f16ce5b..f5461262ee25 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c | |||
@@ -103,6 +103,7 @@ SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12); | |||
103 | SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); | 103 | SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24); |
104 | SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); | 104 | SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024)); |
105 | SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); | 105 | SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15); |
106 | SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3); | ||
106 | 107 | ||
107 | static struct clk *main_clks[] = { | 108 | static struct clk *main_clks[] = { |
108 | &extal_clk, | 109 | &extal_clk, |
@@ -116,12 +117,15 @@ static struct clk *main_clks[] = { | |||
116 | &rclk_clk, | 117 | &rclk_clk, |
117 | &mp_clk, | 118 | &mp_clk, |
118 | &cp_clk, | 119 | &cp_clk, |
120 | &zx_clk, | ||
119 | }; | 121 | }; |
120 | 122 | ||
121 | /* MSTP */ | 123 | /* MSTP */ |
122 | enum { | 124 | enum { |
123 | MSTP721, MSTP720, | 125 | MSTP813, |
126 | MSTP726, MSTP724, MSTP723, MSTP721, MSTP720, | ||
124 | MSTP719, MSTP718, MSTP715, MSTP714, | 127 | MSTP719, MSTP718, MSTP715, MSTP714, |
128 | MSTP522, | ||
125 | MSTP216, MSTP207, MSTP206, | 129 | MSTP216, MSTP207, MSTP206, |
126 | MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, | 130 | MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107, |
127 | MSTP124, | 131 | MSTP124, |
@@ -129,12 +133,17 @@ enum { | |||
129 | }; | 133 | }; |
130 | 134 | ||
131 | static struct clk mstp_clks[MSTP_NR] = { | 135 | static struct clk mstp_clks[MSTP_NR] = { |
136 | [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */ | ||
137 | [MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */ | ||
138 | [MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */ | ||
139 | [MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */ | ||
132 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ | 140 | [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ |
133 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ | 141 | [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ |
134 | [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ | 142 | [MSTP719] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 19, 0), /* SCIF2 */ |
135 | [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ | 143 | [MSTP718] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 18, 0), /* SCIF3 */ |
136 | [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ | 144 | [MSTP715] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 15, 0), /* SCIF4 */ |
137 | [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ | 145 | [MSTP714] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 14, 0), /* SCIF5 */ |
146 | [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */ | ||
138 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ | 147 | [MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */ |
139 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ | 148 | [MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */ |
140 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ | 149 | [MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */ |
@@ -164,6 +173,9 @@ static struct clk_lookup lookups[] = { | |||
164 | CLKDEV_CON_ID("peripheral_clk", &hp_clk), | 173 | CLKDEV_CON_ID("peripheral_clk", &hp_clk), |
165 | 174 | ||
166 | /* MSTP */ | 175 | /* MSTP */ |
176 | CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7791", &mstp_clks[MSTP726]), | ||
177 | CLKDEV_ICK_ID("du.0", "rcar-du-r8a7791", &mstp_clks[MSTP724]), | ||
178 | CLKDEV_ICK_ID("du.1", "rcar-du-r8a7791", &mstp_clks[MSTP723]), | ||
167 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ | 179 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */ |
168 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ | 180 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */ |
169 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ | 181 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]), /* SCIFB0 */ |
@@ -180,6 +192,9 @@ static struct clk_lookup lookups[] = { | |||
180 | CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ | 192 | CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */ |
181 | CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ | 193 | CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */ |
182 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), | 194 | CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]), |
195 | CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), | ||
196 | CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), | ||
197 | CLKDEV_DEV_ID("r8a7791-ether", &mstp_clks[MSTP813]), /* Ether */ | ||
183 | }; | 198 | }; |
184 | 199 | ||
185 | #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ | 200 | #define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index c92c023f0d27..5e6a0566f3c6 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
@@ -658,6 +658,7 @@ static struct clk_lookup lookups[] = { | |||
658 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ | 658 | CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ |
659 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ | 659 | CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */ |
660 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ | 660 | CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */ |
661 | CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */ | ||
661 | CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ | 662 | CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */ |
662 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ | 663 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */ |
663 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ | 664 | CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */ |
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h index c2eb7568d9be..fcb142a14e07 100644 --- a/arch/arm/mach-shmobile/include/mach/emev2.h +++ b/arch/arm/mach-shmobile/include/mach/emev2.h | |||
@@ -3,12 +3,7 @@ | |||
3 | 3 | ||
4 | extern void emev2_map_io(void); | 4 | extern void emev2_map_io(void); |
5 | extern void emev2_init_delay(void); | 5 | extern void emev2_init_delay(void); |
6 | extern void emev2_add_standard_devices(void); | ||
7 | extern void emev2_clock_init(void); | 6 | extern void emev2_clock_init(void); |
8 | |||
9 | #define EMEV2_GPIO_BASE 200 | ||
10 | #define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) | ||
11 | |||
12 | extern struct smp_operations emev2_smp_ops; | 7 | extern struct smp_operations emev2_smp_ops; |
13 | 8 | ||
14 | #endif /* __ASM_EMEV2_H__ */ | 9 | #endif /* __ASM_EMEV2_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h index 441886c9714b..f4076a50e970 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h | |||
@@ -20,13 +20,50 @@ | |||
20 | #define __ASM_R8A7778_H__ | 20 | #define __ASM_R8A7778_H__ |
21 | 21 | ||
22 | #include <linux/sh_eth.h> | 22 | #include <linux/sh_eth.h> |
23 | #include <linux/platform_data/camera-rcar.h> | ||
24 | 23 | ||
25 | /* HPB-DMA slave IDs */ | 24 | /* HPB-DMA slave IDs */ |
26 | enum { | 25 | enum { |
27 | HPBDMA_SLAVE_DUMMY, | 26 | HPBDMA_SLAVE_DUMMY, |
28 | HPBDMA_SLAVE_SDHI0_TX, | 27 | HPBDMA_SLAVE_SDHI0_TX, |
29 | HPBDMA_SLAVE_SDHI0_RX, | 28 | HPBDMA_SLAVE_SDHI0_RX, |
29 | HPBDMA_SLAVE_SSI0_TX, | ||
30 | HPBDMA_SLAVE_SSI0_RX, | ||
31 | HPBDMA_SLAVE_SSI1_TX, | ||
32 | HPBDMA_SLAVE_SSI1_RX, | ||
33 | HPBDMA_SLAVE_SSI2_TX, | ||
34 | HPBDMA_SLAVE_SSI2_RX, | ||
35 | HPBDMA_SLAVE_SSI3_TX, | ||
36 | HPBDMA_SLAVE_SSI3_RX, | ||
37 | HPBDMA_SLAVE_SSI4_TX, | ||
38 | HPBDMA_SLAVE_SSI4_RX, | ||
39 | HPBDMA_SLAVE_SSI5_TX, | ||
40 | HPBDMA_SLAVE_SSI5_RX, | ||
41 | HPBDMA_SLAVE_SSI6_TX, | ||
42 | HPBDMA_SLAVE_SSI6_RX, | ||
43 | HPBDMA_SLAVE_SSI7_TX, | ||
44 | HPBDMA_SLAVE_SSI7_RX, | ||
45 | HPBDMA_SLAVE_SSI8_TX, | ||
46 | HPBDMA_SLAVE_SSI8_RX, | ||
47 | HPBDMA_SLAVE_HPBIF0_TX, | ||
48 | HPBDMA_SLAVE_HPBIF0_RX, | ||
49 | HPBDMA_SLAVE_HPBIF1_TX, | ||
50 | HPBDMA_SLAVE_HPBIF1_RX, | ||
51 | HPBDMA_SLAVE_HPBIF2_TX, | ||
52 | HPBDMA_SLAVE_HPBIF2_RX, | ||
53 | HPBDMA_SLAVE_HPBIF3_TX, | ||
54 | HPBDMA_SLAVE_HPBIF3_RX, | ||
55 | HPBDMA_SLAVE_HPBIF4_TX, | ||
56 | HPBDMA_SLAVE_HPBIF4_RX, | ||
57 | HPBDMA_SLAVE_HPBIF5_TX, | ||
58 | HPBDMA_SLAVE_HPBIF5_RX, | ||
59 | HPBDMA_SLAVE_HPBIF6_TX, | ||
60 | HPBDMA_SLAVE_HPBIF6_RX, | ||
61 | HPBDMA_SLAVE_HPBIF7_TX, | ||
62 | HPBDMA_SLAVE_HPBIF7_RX, | ||
63 | HPBDMA_SLAVE_HPBIF8_TX, | ||
64 | HPBDMA_SLAVE_HPBIF8_RX, | ||
65 | HPBDMA_SLAVE_USBFUNC_TX, | ||
66 | HPBDMA_SLAVE_USBFUNC_RX, | ||
30 | }; | 67 | }; |
31 | 68 | ||
32 | extern void r8a7778_add_standard_devices(void); | 69 | extern void r8a7778_add_standard_devices(void); |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h index 051ead3c286e..200fa699f730 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h | |||
@@ -4,6 +4,7 @@ | |||
4 | void r8a7791_add_standard_devices(void); | 4 | void r8a7791_add_standard_devices(void); |
5 | void r8a7791_add_dt_devices(void); | 5 | void r8a7791_add_dt_devices(void); |
6 | void r8a7791_clock_init(void); | 6 | void r8a7791_clock_init(void); |
7 | void r8a7791_pinmux_init(void); | ||
7 | void r8a7791_init_early(void); | 8 | void r8a7791_init_early(void); |
8 | extern struct smp_operations r8a7791_smp_ops; | 9 | extern struct smp_operations r8a7791_smp_ops; |
9 | 10 | ||
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index 3ad531caf4f0..c8f2a1a69a52 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c | |||
@@ -16,24 +16,15 @@ | |||
16 | * along with this program; if not, write to the Free Software | 16 | * along with this program; if not, write to the Free Software |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
18 | */ | 18 | */ |
19 | #include <linux/clk-provider.h> | ||
19 | #include <linux/kernel.h> | 20 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | 21 | #include <linux/init.h> |
21 | #include <linux/interrupt.h> | ||
22 | #include <linux/irq.h> | ||
23 | #include <linux/platform_device.h> | ||
24 | #include <linux/platform_data/gpio-em.h> | ||
25 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
26 | #include <linux/delay.h> | ||
27 | #include <linux/input.h> | ||
28 | #include <linux/io.h> | ||
29 | #include <linux/irqchip/arm-gic.h> | ||
30 | #include <mach/common.h> | 23 | #include <mach/common.h> |
31 | #include <mach/emev2.h> | 24 | #include <mach/emev2.h> |
32 | #include <mach/irqs.h> | ||
33 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
34 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
35 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
36 | #include <asm/mach/time.h> | ||
37 | 28 | ||
38 | static struct map_desc emev2_io_desc[] __initdata = { | 29 | static struct map_desc emev2_io_desc[] __initdata = { |
39 | #ifdef CONFIG_SMP | 30 | #ifdef CONFIG_SMP |
@@ -52,150 +43,20 @@ void __init emev2_map_io(void) | |||
52 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); | 43 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); |
53 | } | 44 | } |
54 | 45 | ||
55 | /* UART */ | ||
56 | static struct resource uart0_resources[] = { | ||
57 | DEFINE_RES_MEM(0xe1020000, 0x38), | ||
58 | DEFINE_RES_IRQ(40), | ||
59 | }; | ||
60 | |||
61 | static struct resource uart1_resources[] = { | ||
62 | DEFINE_RES_MEM(0xe1030000, 0x38), | ||
63 | DEFINE_RES_IRQ(41), | ||
64 | }; | ||
65 | |||
66 | static struct resource uart2_resources[] = { | ||
67 | DEFINE_RES_MEM(0xe1040000, 0x38), | ||
68 | DEFINE_RES_IRQ(42), | ||
69 | }; | ||
70 | |||
71 | static struct resource uart3_resources[] = { | ||
72 | DEFINE_RES_MEM(0xe1050000, 0x38), | ||
73 | DEFINE_RES_IRQ(43), | ||
74 | }; | ||
75 | |||
76 | #define emev2_register_uart(idx) \ | ||
77 | platform_device_register_simple("serial8250-em", idx, \ | ||
78 | uart##idx##_resources, \ | ||
79 | ARRAY_SIZE(uart##idx##_resources)) | ||
80 | |||
81 | /* STI */ | ||
82 | static struct resource sti_resources[] = { | ||
83 | DEFINE_RES_MEM(0xe0180000, 0x54), | ||
84 | DEFINE_RES_IRQ(157), | ||
85 | }; | ||
86 | |||
87 | #define emev2_register_sti() \ | ||
88 | platform_device_register_simple("em_sti", 0, \ | ||
89 | sti_resources, \ | ||
90 | ARRAY_SIZE(sti_resources)) | ||
91 | |||
92 | /* GIO */ | ||
93 | static struct gpio_em_config gio0_config = { | ||
94 | .gpio_base = 0, | ||
95 | .irq_base = EMEV2_GPIO_IRQ(0), | ||
96 | .number_of_pins = 32, | ||
97 | }; | ||
98 | |||
99 | static struct resource gio0_resources[] = { | ||
100 | DEFINE_RES_MEM(0xe0050000, 0x2c), | ||
101 | DEFINE_RES_MEM(0xe0050040, 0x20), | ||
102 | DEFINE_RES_IRQ(99), | ||
103 | DEFINE_RES_IRQ(100), | ||
104 | }; | ||
105 | |||
106 | static struct gpio_em_config gio1_config = { | ||
107 | .gpio_base = 32, | ||
108 | .irq_base = EMEV2_GPIO_IRQ(32), | ||
109 | .number_of_pins = 32, | ||
110 | }; | ||
111 | |||
112 | static struct resource gio1_resources[] = { | ||
113 | DEFINE_RES_MEM(0xe0050080, 0x2c), | ||
114 | DEFINE_RES_MEM(0xe00500c0, 0x20), | ||
115 | DEFINE_RES_IRQ(101), | ||
116 | DEFINE_RES_IRQ(102), | ||
117 | }; | ||
118 | |||
119 | static struct gpio_em_config gio2_config = { | ||
120 | .gpio_base = 64, | ||
121 | .irq_base = EMEV2_GPIO_IRQ(64), | ||
122 | .number_of_pins = 32, | ||
123 | }; | ||
124 | |||
125 | static struct resource gio2_resources[] = { | ||
126 | DEFINE_RES_MEM(0xe0050100, 0x2c), | ||
127 | DEFINE_RES_MEM(0xe0050140, 0x20), | ||
128 | DEFINE_RES_IRQ(103), | ||
129 | DEFINE_RES_IRQ(104), | ||
130 | }; | ||
131 | |||
132 | static struct gpio_em_config gio3_config = { | ||
133 | .gpio_base = 96, | ||
134 | .irq_base = EMEV2_GPIO_IRQ(96), | ||
135 | .number_of_pins = 32, | ||
136 | }; | ||
137 | |||
138 | static struct resource gio3_resources[] = { | ||
139 | DEFINE_RES_MEM(0xe0050180, 0x2c), | ||
140 | DEFINE_RES_MEM(0xe00501c0, 0x20), | ||
141 | DEFINE_RES_IRQ(105), | ||
142 | DEFINE_RES_IRQ(106), | ||
143 | }; | ||
144 | |||
145 | static struct gpio_em_config gio4_config = { | ||
146 | .gpio_base = 128, | ||
147 | .irq_base = EMEV2_GPIO_IRQ(128), | ||
148 | .number_of_pins = 31, | ||
149 | }; | ||
150 | |||
151 | static struct resource gio4_resources[] = { | ||
152 | DEFINE_RES_MEM(0xe0050200, 0x2c), | ||
153 | DEFINE_RES_MEM(0xe0050240, 0x20), | ||
154 | DEFINE_RES_IRQ(107), | ||
155 | DEFINE_RES_IRQ(108), | ||
156 | }; | ||
157 | |||
158 | #define emev2_register_gio(idx) \ | ||
159 | platform_device_register_resndata(&platform_bus, "em_gio", \ | ||
160 | idx, gio##idx##_resources, \ | ||
161 | ARRAY_SIZE(gio##idx##_resources), \ | ||
162 | &gio##idx##_config, \ | ||
163 | sizeof(struct gpio_em_config)) | ||
164 | |||
165 | static struct resource pmu_resources[] = { | ||
166 | DEFINE_RES_IRQ(152), | ||
167 | DEFINE_RES_IRQ(153), | ||
168 | }; | ||
169 | |||
170 | #define emev2_register_pmu() \ | ||
171 | platform_device_register_simple("arm-pmu", -1, \ | ||
172 | pmu_resources, \ | ||
173 | ARRAY_SIZE(pmu_resources)) | ||
174 | |||
175 | void __init emev2_add_standard_devices(void) | ||
176 | { | ||
177 | if (!IS_ENABLED(CONFIG_COMMON_CLK)) | ||
178 | emev2_clock_init(); | ||
179 | |||
180 | emev2_register_uart(0); | ||
181 | emev2_register_uart(1); | ||
182 | emev2_register_uart(2); | ||
183 | emev2_register_uart(3); | ||
184 | emev2_register_sti(); | ||
185 | emev2_register_gio(0); | ||
186 | emev2_register_gio(1); | ||
187 | emev2_register_gio(2); | ||
188 | emev2_register_gio(3); | ||
189 | emev2_register_gio(4); | ||
190 | emev2_register_pmu(); | ||
191 | } | ||
192 | |||
193 | void __init emev2_init_delay(void) | 46 | void __init emev2_init_delay(void) |
194 | { | 47 | { |
195 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ | 48 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ |
196 | } | 49 | } |
197 | 50 | ||
198 | #ifdef CONFIG_USE_OF | 51 | static void __init emev2_add_standard_devices_dt(void) |
52 | { | ||
53 | #ifdef CONFIG_COMMON_CLK | ||
54 | of_clk_init(NULL); | ||
55 | #else | ||
56 | emev2_clock_init(); | ||
57 | #endif | ||
58 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
59 | } | ||
199 | 60 | ||
200 | static const char *emev2_boards_compat_dt[] __initdata = { | 61 | static const char *emev2_boards_compat_dt[] __initdata = { |
201 | "renesas,emev2", | 62 | "renesas,emev2", |
@@ -206,7 +67,7 @@ DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") | |||
206 | .smp = smp_ops(emev2_smp_ops), | 67 | .smp = smp_ops(emev2_smp_ops), |
207 | .map_io = emev2_map_io, | 68 | .map_io = emev2_map_io, |
208 | .init_early = emev2_init_delay, | 69 | .init_early = emev2_init_delay, |
70 | .init_machine = emev2_add_standard_devices_dt, | ||
71 | .init_late = shmobile_init_late, | ||
209 | .dt_compat = emev2_boards_compat_dt, | 72 | .dt_compat = emev2_boards_compat_dt, |
210 | MACHINE_END | 73 | MACHINE_END |
211 | |||
212 | #endif /* CONFIG_USE_OF */ | ||
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index d4eb509a1c87..9c0b3a9d5f7a 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c | |||
@@ -22,52 +22,76 @@ | |||
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
24 | #include <linux/serial_sci.h> | 24 | #include <linux/serial_sci.h> |
25 | #include <linux/sh_timer.h> | ||
25 | #include <mach/common.h> | 26 | #include <mach/common.h> |
26 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
27 | #include <mach/r7s72100.h> | 28 | #include <mach/r7s72100.h> |
28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
29 | 30 | ||
30 | #define SCIF_DATA(index, baseaddr, irq) \ | 31 | #define R7S72100_SCIF(index, baseaddr, irq) \ |
31 | [index] = { \ | 32 | static const struct plat_sci_port scif##index##_platform_data = { \ |
32 | .type = PORT_SCIF, \ | 33 | .type = PORT_SCIF, \ |
33 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ | 34 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, \ |
34 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 35 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
35 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
36 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ | 36 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \ |
37 | SCSCR_REIE, \ | 37 | SCSCR_REIE, \ |
38 | .mapbase = baseaddr, \ | 38 | }; \ |
39 | .irqs = { irq + 1, irq + 2, irq + 3, irq }, \ | 39 | \ |
40 | } | 40 | static struct resource scif##index##_resources[] = { \ |
41 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
42 | DEFINE_RES_IRQ(irq + 1), \ | ||
43 | DEFINE_RES_IRQ(irq + 2), \ | ||
44 | DEFINE_RES_IRQ(irq + 3), \ | ||
45 | DEFINE_RES_IRQ(irq), \ | ||
46 | } \ | ||
47 | |||
48 | R7S72100_SCIF(0, 0xe8007000, gic_iid(221)); | ||
49 | R7S72100_SCIF(1, 0xe8007800, gic_iid(225)); | ||
50 | R7S72100_SCIF(2, 0xe8008000, gic_iid(229)); | ||
51 | R7S72100_SCIF(3, 0xe8008800, gic_iid(233)); | ||
52 | R7S72100_SCIF(4, 0xe8009000, gic_iid(237)); | ||
53 | R7S72100_SCIF(5, 0xe8009800, gic_iid(241)); | ||
54 | R7S72100_SCIF(6, 0xe800a000, gic_iid(245)); | ||
55 | R7S72100_SCIF(7, 0xe800a800, gic_iid(249)); | ||
41 | 56 | ||
42 | enum { SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7 }; | 57 | #define r7s72100_register_scif(index) \ |
58 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
59 | scif##index##_resources, \ | ||
60 | ARRAY_SIZE(scif##index##_resources), \ | ||
61 | &scif##index##_platform_data, \ | ||
62 | sizeof(scif##index##_platform_data)) | ||
43 | 63 | ||
44 | static const struct plat_sci_port scif[] __initconst = { | 64 | |
45 | SCIF_DATA(SCIF0, 0xe8007000, gic_iid(221)), /* SCIF0 */ | 65 | static struct sh_timer_config mtu2_0_platform_data __initdata = { |
46 | SCIF_DATA(SCIF1, 0xe8007800, gic_iid(225)), /* SCIF1 */ | 66 | .name = "MTU2_0", |
47 | SCIF_DATA(SCIF2, 0xe8008000, gic_iid(229)), /* SCIF2 */ | 67 | .timer_bit = 0, |
48 | SCIF_DATA(SCIF3, 0xe8008800, gic_iid(233)), /* SCIF3 */ | 68 | .channel_offset = -0x80, |
49 | SCIF_DATA(SCIF4, 0xe8009000, gic_iid(237)), /* SCIF4 */ | 69 | .clockevent_rating = 200, |
50 | SCIF_DATA(SCIF5, 0xe8009800, gic_iid(241)), /* SCIF5 */ | ||
51 | SCIF_DATA(SCIF6, 0xe800a000, gic_iid(245)), /* SCIF6 */ | ||
52 | SCIF_DATA(SCIF7, 0xe800a800, gic_iid(249)), /* SCIF7 */ | ||
53 | }; | 70 | }; |
54 | 71 | ||
55 | static inline void r7s72100_register_scif(int idx) | 72 | static struct resource mtu2_0_resources[] __initdata = { |
56 | { | 73 | DEFINE_RES_MEM(0xfcff0300, 0x27), |
57 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 74 | DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */ |
58 | sizeof(struct plat_sci_port)); | 75 | }; |
59 | } | 76 | |
77 | #define r7s72100_register_mtu2(idx) \ | ||
78 | platform_device_register_resndata(&platform_bus, "sh_mtu2", \ | ||
79 | idx, mtu2_##idx##_resources, \ | ||
80 | ARRAY_SIZE(mtu2_##idx##_resources), \ | ||
81 | &mtu2_##idx##_platform_data, \ | ||
82 | sizeof(struct sh_timer_config)) | ||
60 | 83 | ||
61 | void __init r7s72100_add_dt_devices(void) | 84 | void __init r7s72100_add_dt_devices(void) |
62 | { | 85 | { |
63 | r7s72100_register_scif(SCIF0); | 86 | r7s72100_register_scif(0); |
64 | r7s72100_register_scif(SCIF1); | 87 | r7s72100_register_scif(1); |
65 | r7s72100_register_scif(SCIF2); | 88 | r7s72100_register_scif(2); |
66 | r7s72100_register_scif(SCIF3); | 89 | r7s72100_register_scif(3); |
67 | r7s72100_register_scif(SCIF4); | 90 | r7s72100_register_scif(4); |
68 | r7s72100_register_scif(SCIF5); | 91 | r7s72100_register_scif(5); |
69 | r7s72100_register_scif(SCIF6); | 92 | r7s72100_register_scif(6); |
70 | r7s72100_register_scif(SCIF7); | 93 | r7s72100_register_scif(7); |
94 | r7s72100_register_mtu2(0); | ||
71 | } | 95 | } |
72 | 96 | ||
73 | void __init r7s72100_init_early(void) | 97 | void __init r7s72100_init_early(void) |
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index b0f2749071be..cd36f8078325 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c | |||
@@ -40,41 +40,39 @@ void __init r8a73a4_pinmux_init(void) | |||
40 | ARRAY_SIZE(pfc_resources)); | 40 | ARRAY_SIZE(pfc_resources)); |
41 | } | 41 | } |
42 | 42 | ||
43 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 43 | #define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \ |
44 | static struct plat_sci_port scif##index##_platform_data = { \ | ||
44 | .type = scif_type, \ | 45 | .type = scif_type, \ |
45 | .mapbase = baseaddr, \ | ||
46 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 46 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
47 | .scbrr_algo_id = SCBRR_ALGO_4, \ | 47 | .scscr = _scscr, \ |
48 | .irqs = SCIx_IRQ_MUXED(irq) | 48 | }; \ |
49 | 49 | \ | |
50 | #define SCIFA_DATA(index, baseaddr, irq) \ | 50 | static struct resource scif##index##_resources[] = { \ |
51 | [index] = { \ | 51 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
52 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | 52 | DEFINE_RES_IRQ(irq), \ |
53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | ||
54 | } | 53 | } |
55 | 54 | ||
56 | #define SCIFB_DATA(index, baseaddr, irq) \ | 55 | #define R8A73A4_SCIFA(index, baseaddr, irq) \ |
57 | [index] = { \ | 56 | R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ |
58 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | 57 | index, baseaddr, irq) |
59 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
60 | } | ||
61 | 58 | ||
62 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFB3 }; | 59 | #define R8A73A4_SCIFB(index, baseaddr, irq) \ |
60 | R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ | ||
61 | index, baseaddr, irq) | ||
63 | 62 | ||
64 | static const struct plat_sci_port scif[] = { | 63 | R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
65 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 64 | R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
66 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 65 | R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
67 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 66 | R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
68 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 67 | R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
69 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 68 | R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */ |
70 | SCIFB_DATA(SCIFB3, 0xe6cf0000, gic_spi(151)), /* SCIFB3 */ | ||
71 | }; | ||
72 | 69 | ||
73 | static inline void r8a73a4_register_scif(int idx) | 70 | #define r8a73a4_register_scif(index) \ |
74 | { | 71 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ |
75 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 72 | scif##index##_resources, \ |
76 | sizeof(struct plat_sci_port)); | 73 | ARRAY_SIZE(scif##index##_resources), \ |
77 | } | 74 | &scif##index##_platform_data, \ |
75 | sizeof(scif##index##_platform_data)) | ||
78 | 76 | ||
79 | static const struct renesas_irqc_config irqc0_data = { | 77 | static const struct renesas_irqc_config irqc0_data = { |
80 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ | 78 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */ |
@@ -192,12 +190,12 @@ static struct resource cmt10_resources[] = { | |||
192 | 190 | ||
193 | void __init r8a73a4_add_dt_devices(void) | 191 | void __init r8a73a4_add_dt_devices(void) |
194 | { | 192 | { |
195 | r8a73a4_register_scif(SCIFA0); | 193 | r8a73a4_register_scif(0); |
196 | r8a73a4_register_scif(SCIFA1); | 194 | r8a73a4_register_scif(1); |
197 | r8a73a4_register_scif(SCIFB0); | 195 | r8a73a4_register_scif(2); |
198 | r8a73a4_register_scif(SCIFB1); | 196 | r8a73a4_register_scif(3); |
199 | r8a73a4_register_scif(SCIFB2); | 197 | r8a73a4_register_scif(4); |
200 | r8a73a4_register_scif(SCIFB3); | 198 | r8a73a4_register_scif(5); |
201 | r8a7790_register_cmt(10); | 199 | r8a7790_register_cmt(10); |
202 | } | 200 | } |
203 | 201 | ||
@@ -275,7 +273,7 @@ static const struct sh_dmae_pdata dma_pdata = { | |||
275 | 273 | ||
276 | static struct resource dma_resources[] = { | 274 | static struct resource dma_resources[] = { |
277 | DEFINE_RES_MEM(0xe6700020, 0x89e0), | 275 | DEFINE_RES_MEM(0xe6700020, 0x89e0), |
278 | DEFINE_RES_IRQ_NAMED(gic_spi(220), "error_irq"), | 276 | DEFINE_RES_IRQ(gic_spi(220)), |
279 | { | 277 | { |
280 | /* IRQ for channels 0-19 */ | 278 | /* IRQ for channels 0-19 */ |
281 | .start = gic_spi(200), | 279 | .start = gic_spi(200), |
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index b7d4b2c3bc29..8f3c68101d59 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
@@ -203,167 +203,38 @@ static struct platform_device irqpin3_device = { | |||
203 | }, | 203 | }, |
204 | }; | 204 | }; |
205 | 205 | ||
206 | /* SCIFA0 */ | 206 | /* SCIF */ |
207 | static struct plat_sci_port scif0_platform_data = { | 207 | #define R8A7740_SCIF(scif_type, index, baseaddr, irq) \ |
208 | .mapbase = 0xe6c40000, | 208 | static struct plat_sci_port scif##index##_platform_data = { \ |
209 | .flags = UPF_BOOT_AUTOCONF, | 209 | .type = scif_type, \ |
210 | .scscr = SCSCR_RE | SCSCR_TE, | 210 | .flags = UPF_BOOT_AUTOCONF, \ |
211 | .scbrr_algo_id = SCBRR_ALGO_4, | 211 | .scscr = SCSCR_RE | SCSCR_TE, \ |
212 | .type = PORT_SCIFA, | 212 | }; \ |
213 | .irqs = SCIx_IRQ_MUXED(gic_spi(100)), | 213 | \ |
214 | }; | 214 | static struct resource scif##index##_resources[] = { \ |
215 | 215 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
216 | static struct platform_device scif0_device = { | 216 | DEFINE_RES_IRQ(irq), \ |
217 | .name = "sh-sci", | 217 | }; \ |
218 | .id = 0, | 218 | \ |
219 | .dev = { | 219 | static struct platform_device scif##index##_device = { \ |
220 | .platform_data = &scif0_platform_data, | 220 | .name = "sh-sci", \ |
221 | }, | 221 | .id = index, \ |
222 | }; | 222 | .resource = scif##index##_resources, \ |
223 | 223 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
224 | /* SCIFA1 */ | 224 | .dev = { \ |
225 | static struct plat_sci_port scif1_platform_data = { | 225 | .platform_data = &scif##index##_platform_data, \ |
226 | .mapbase = 0xe6c50000, | 226 | }, \ |
227 | .flags = UPF_BOOT_AUTOCONF, | 227 | } |
228 | .scscr = SCSCR_RE | SCSCR_TE, | ||
229 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
230 | .type = PORT_SCIFA, | ||
231 | .irqs = SCIx_IRQ_MUXED(gic_spi(101)), | ||
232 | }; | ||
233 | |||
234 | static struct platform_device scif1_device = { | ||
235 | .name = "sh-sci", | ||
236 | .id = 1, | ||
237 | .dev = { | ||
238 | .platform_data = &scif1_platform_data, | ||
239 | }, | ||
240 | }; | ||
241 | |||
242 | /* SCIFA2 */ | ||
243 | static struct plat_sci_port scif2_platform_data = { | ||
244 | .mapbase = 0xe6c60000, | ||
245 | .flags = UPF_BOOT_AUTOCONF, | ||
246 | .scscr = SCSCR_RE | SCSCR_TE, | ||
247 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
248 | .type = PORT_SCIFA, | ||
249 | .irqs = SCIx_IRQ_MUXED(gic_spi(102)), | ||
250 | }; | ||
251 | |||
252 | static struct platform_device scif2_device = { | ||
253 | .name = "sh-sci", | ||
254 | .id = 2, | ||
255 | .dev = { | ||
256 | .platform_data = &scif2_platform_data, | ||
257 | }, | ||
258 | }; | ||
259 | |||
260 | /* SCIFA3 */ | ||
261 | static struct plat_sci_port scif3_platform_data = { | ||
262 | .mapbase = 0xe6c70000, | ||
263 | .flags = UPF_BOOT_AUTOCONF, | ||
264 | .scscr = SCSCR_RE | SCSCR_TE, | ||
265 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
266 | .type = PORT_SCIFA, | ||
267 | .irqs = SCIx_IRQ_MUXED(gic_spi(103)), | ||
268 | }; | ||
269 | |||
270 | static struct platform_device scif3_device = { | ||
271 | .name = "sh-sci", | ||
272 | .id = 3, | ||
273 | .dev = { | ||
274 | .platform_data = &scif3_platform_data, | ||
275 | }, | ||
276 | }; | ||
277 | |||
278 | /* SCIFA4 */ | ||
279 | static struct plat_sci_port scif4_platform_data = { | ||
280 | .mapbase = 0xe6c80000, | ||
281 | .flags = UPF_BOOT_AUTOCONF, | ||
282 | .scscr = SCSCR_RE | SCSCR_TE, | ||
283 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
284 | .type = PORT_SCIFA, | ||
285 | .irqs = SCIx_IRQ_MUXED(gic_spi(104)), | ||
286 | }; | ||
287 | |||
288 | static struct platform_device scif4_device = { | ||
289 | .name = "sh-sci", | ||
290 | .id = 4, | ||
291 | .dev = { | ||
292 | .platform_data = &scif4_platform_data, | ||
293 | }, | ||
294 | }; | ||
295 | |||
296 | /* SCIFA5 */ | ||
297 | static struct plat_sci_port scif5_platform_data = { | ||
298 | .mapbase = 0xe6cb0000, | ||
299 | .flags = UPF_BOOT_AUTOCONF, | ||
300 | .scscr = SCSCR_RE | SCSCR_TE, | ||
301 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
302 | .type = PORT_SCIFA, | ||
303 | .irqs = SCIx_IRQ_MUXED(gic_spi(105)), | ||
304 | }; | ||
305 | |||
306 | static struct platform_device scif5_device = { | ||
307 | .name = "sh-sci", | ||
308 | .id = 5, | ||
309 | .dev = { | ||
310 | .platform_data = &scif5_platform_data, | ||
311 | }, | ||
312 | }; | ||
313 | |||
314 | /* SCIFA6 */ | ||
315 | static struct plat_sci_port scif6_platform_data = { | ||
316 | .mapbase = 0xe6cc0000, | ||
317 | .flags = UPF_BOOT_AUTOCONF, | ||
318 | .scscr = SCSCR_RE | SCSCR_TE, | ||
319 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
320 | .type = PORT_SCIFA, | ||
321 | .irqs = SCIx_IRQ_MUXED(gic_spi(106)), | ||
322 | }; | ||
323 | |||
324 | static struct platform_device scif6_device = { | ||
325 | .name = "sh-sci", | ||
326 | .id = 6, | ||
327 | .dev = { | ||
328 | .platform_data = &scif6_platform_data, | ||
329 | }, | ||
330 | }; | ||
331 | |||
332 | /* SCIFA7 */ | ||
333 | static struct plat_sci_port scif7_platform_data = { | ||
334 | .mapbase = 0xe6cd0000, | ||
335 | .flags = UPF_BOOT_AUTOCONF, | ||
336 | .scscr = SCSCR_RE | SCSCR_TE, | ||
337 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
338 | .type = PORT_SCIFA, | ||
339 | .irqs = SCIx_IRQ_MUXED(gic_spi(107)), | ||
340 | }; | ||
341 | |||
342 | static struct platform_device scif7_device = { | ||
343 | .name = "sh-sci", | ||
344 | .id = 7, | ||
345 | .dev = { | ||
346 | .platform_data = &scif7_platform_data, | ||
347 | }, | ||
348 | }; | ||
349 | |||
350 | /* SCIFB */ | ||
351 | static struct plat_sci_port scifb_platform_data = { | ||
352 | .mapbase = 0xe6c30000, | ||
353 | .flags = UPF_BOOT_AUTOCONF, | ||
354 | .scscr = SCSCR_RE | SCSCR_TE, | ||
355 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
356 | .type = PORT_SCIFB, | ||
357 | .irqs = SCIx_IRQ_MUXED(gic_spi(108)), | ||
358 | }; | ||
359 | 228 | ||
360 | static struct platform_device scifb_device = { | 229 | R8A7740_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(100)); |
361 | .name = "sh-sci", | 230 | R8A7740_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(101)); |
362 | .id = 8, | 231 | R8A7740_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(102)); |
363 | .dev = { | 232 | R8A7740_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(103)); |
364 | .platform_data = &scifb_platform_data, | 233 | R8A7740_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(104)); |
365 | }, | 234 | R8A7740_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(105)); |
366 | }; | 235 | R8A7740_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(106)); |
236 | R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107)); | ||
237 | R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108)); | ||
367 | 238 | ||
368 | /* CMT */ | 239 | /* CMT */ |
369 | static struct sh_timer_config cmt10_platform_data = { | 240 | static struct sh_timer_config cmt10_platform_data = { |
@@ -528,7 +399,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = { | |||
528 | &scif5_device, | 399 | &scif5_device, |
529 | &scif6_device, | 400 | &scif6_device, |
530 | &scif7_device, | 401 | &scif7_device, |
531 | &scifb_device, | 402 | &scif8_device, |
532 | &cmt10_device, | 403 | &cmt10_device, |
533 | }; | 404 | }; |
534 | 405 | ||
@@ -981,7 +852,7 @@ void __init r8a7740_add_standard_devices(void) | |||
981 | rmobile_add_device_to_domain("A3SP", &scif5_device); | 852 | rmobile_add_device_to_domain("A3SP", &scif5_device); |
982 | rmobile_add_device_to_domain("A3SP", &scif6_device); | 853 | rmobile_add_device_to_domain("A3SP", &scif6_device); |
983 | rmobile_add_device_to_domain("A3SP", &scif7_device); | 854 | rmobile_add_device_to_domain("A3SP", &scif7_device); |
984 | rmobile_add_device_to_domain("A3SP", &scifb_device); | 855 | rmobile_add_device_to_domain("A3SP", &scif8_device); |
985 | rmobile_add_device_to_domain("A3SP", &i2c1_device); | 856 | rmobile_add_device_to_domain("A3SP", &i2c1_device); |
986 | } | 857 | } |
987 | 858 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 03fcc5974ef9..6d694526e4ca 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
@@ -44,24 +44,31 @@ | |||
44 | #include <asm/hardware/cache-l2x0.h> | 44 | #include <asm/hardware/cache-l2x0.h> |
45 | 45 | ||
46 | /* SCIF */ | 46 | /* SCIF */ |
47 | #define SCIF_INFO(baseaddr, irq) \ | 47 | #define R8A7778_SCIF(index, baseaddr, irq) \ |
48 | { \ | 48 | static struct plat_sci_port scif##index##_platform_data = { \ |
49 | .mapbase = baseaddr, \ | ||
50 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 49 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ | 50 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ |
52 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
53 | .type = PORT_SCIF, \ | 51 | .type = PORT_SCIF, \ |
54 | .irqs = SCIx_IRQ_MUXED(irq), \ | 52 | }; \ |
53 | \ | ||
54 | static struct resource scif##index##_resources[] = { \ | ||
55 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
56 | DEFINE_RES_IRQ(irq), \ | ||
55 | } | 57 | } |
56 | 58 | ||
57 | static struct plat_sci_port scif_platform_data[] __initdata = { | 59 | R8A7778_SCIF(0, 0xffe40000, gic_iid(0x66)); |
58 | SCIF_INFO(0xffe40000, gic_iid(0x66)), | 60 | R8A7778_SCIF(1, 0xffe41000, gic_iid(0x67)); |
59 | SCIF_INFO(0xffe41000, gic_iid(0x67)), | 61 | R8A7778_SCIF(2, 0xffe42000, gic_iid(0x68)); |
60 | SCIF_INFO(0xffe42000, gic_iid(0x68)), | 62 | R8A7778_SCIF(3, 0xffe43000, gic_iid(0x69)); |
61 | SCIF_INFO(0xffe43000, gic_iid(0x69)), | 63 | R8A7778_SCIF(4, 0xffe44000, gic_iid(0x6a)); |
62 | SCIF_INFO(0xffe44000, gic_iid(0x6a)), | 64 | R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b)); |
63 | SCIF_INFO(0xffe45000, gic_iid(0x6b)), | 65 | |
64 | }; | 66 | #define r8a7778_register_scif(index) \ |
67 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
68 | scif##index##_resources, \ | ||
69 | ARRAY_SIZE(scif##index##_resources), \ | ||
70 | &scif##index##_platform_data, \ | ||
71 | sizeof(scif##index##_platform_data)) | ||
65 | 72 | ||
66 | /* TMU */ | 73 | /* TMU */ |
67 | static struct resource sh_tmu0_resources[] __initdata = { | 74 | static struct resource sh_tmu0_resources[] __initdata = { |
@@ -287,8 +294,6 @@ static void __init r8a7778_register_hspi(int id) | |||
287 | 294 | ||
288 | void __init r8a7778_add_dt_devices(void) | 295 | void __init r8a7778_add_dt_devices(void) |
289 | { | 296 | { |
290 | int i; | ||
291 | |||
292 | #ifdef CONFIG_CACHE_L2X0 | 297 | #ifdef CONFIG_CACHE_L2X0 |
293 | void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); | 298 | void __iomem *base = ioremap_nocache(0xf0100000, 0x1000); |
294 | if (base) { | 299 | if (base) { |
@@ -300,11 +305,12 @@ void __init r8a7778_add_dt_devices(void) | |||
300 | } | 305 | } |
301 | #endif | 306 | #endif |
302 | 307 | ||
303 | for (i = 0; i < ARRAY_SIZE(scif_platform_data); i++) | 308 | r8a7778_register_scif(0); |
304 | platform_device_register_data(&platform_bus, "sh-sci", i, | 309 | r8a7778_register_scif(1); |
305 | &scif_platform_data[i], | 310 | r8a7778_register_scif(2); |
306 | sizeof(struct plat_sci_port)); | 311 | r8a7778_register_scif(3); |
307 | 312 | r8a7778_register_scif(4); | |
313 | r8a7778_register_scif(5); | ||
308 | r8a7778_register_tmu(0); | 314 | r8a7778_register_tmu(0); |
309 | r8a7778_register_tmu(1); | 315 | r8a7778_register_tmu(1); |
310 | } | 316 | } |
@@ -319,6 +325,52 @@ void __init r8a7778_add_dt_devices(void) | |||
319 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ | 325 | #define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1) /* SDHI0 */ |
320 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ | 326 | #define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0 /* SDHI0 */ |
321 | 327 | ||
328 | #define HPBDMA_SSI(_id) \ | ||
329 | { \ | ||
330 | .id = HPBDMA_SLAVE_SSI## _id ##_TX, \ | ||
331 | .addr = 0xffd91008 + (_id * 0x40), \ | ||
332 | .dcr = HPB_DMAE_DCR_CT | \ | ||
333 | HPB_DMAE_DCR_DIP | \ | ||
334 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
335 | HPB_DMAE_DCR_DMDL | \ | ||
336 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
337 | .port = _id + (_id << 8), \ | ||
338 | .dma_ch = (28 + _id), \ | ||
339 | }, { \ | ||
340 | .id = HPBDMA_SLAVE_SSI## _id ##_RX, \ | ||
341 | .addr = 0xffd9100c + (_id * 0x40), \ | ||
342 | .dcr = HPB_DMAE_DCR_CT | \ | ||
343 | HPB_DMAE_DCR_DIP | \ | ||
344 | HPB_DMAE_DCR_SMDL | \ | ||
345 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
346 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
347 | .port = _id + (_id << 8), \ | ||
348 | .dma_ch = (28 + _id), \ | ||
349 | } | ||
350 | |||
351 | #define HPBDMA_HPBIF(_id) \ | ||
352 | { \ | ||
353 | .id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \ | ||
354 | .addr = 0xffda0000 + (_id * 0x1000), \ | ||
355 | .dcr = HPB_DMAE_DCR_CT | \ | ||
356 | HPB_DMAE_DCR_DIP | \ | ||
357 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
358 | HPB_DMAE_DCR_DMDL | \ | ||
359 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
360 | .port = 0x1111, \ | ||
361 | .dma_ch = (28 + _id), \ | ||
362 | }, { \ | ||
363 | .id = HPBDMA_SLAVE_HPBIF## _id ##_RX, \ | ||
364 | .addr = 0xffda0000 + (_id * 0x1000), \ | ||
365 | .dcr = HPB_DMAE_DCR_CT | \ | ||
366 | HPB_DMAE_DCR_DIP | \ | ||
367 | HPB_DMAE_DCR_SMDL | \ | ||
368 | HPB_DMAE_DCR_SPDS_32BIT | \ | ||
369 | HPB_DMAE_DCR_DPDS_32BIT, \ | ||
370 | .port = 0x1111, \ | ||
371 | .dma_ch = (28 + _id), \ | ||
372 | } | ||
373 | |||
322 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | 374 | static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { |
323 | { | 375 | { |
324 | .id = HPBDMA_SLAVE_SDHI0_TX, | 376 | .id = HPBDMA_SLAVE_SDHI0_TX, |
@@ -348,12 +400,86 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = { | |||
348 | .port = 0x0D0C, | 400 | .port = 0x0D0C, |
349 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, | 401 | .flags = HPB_DMAE_SET_ASYNC_RESET | HPB_DMAE_SET_ASYNC_MODE, |
350 | .dma_ch = 22, | 402 | .dma_ch = 22, |
403 | }, { | ||
404 | .id = HPBDMA_SLAVE_USBFUNC_TX, /* for D0 */ | ||
405 | .addr = 0xffe60018, | ||
406 | .dcr = HPB_DMAE_DCR_SPDS_32BIT | | ||
407 | HPB_DMAE_DCR_DMDL | | ||
408 | HPB_DMAE_DCR_DPDS_32BIT, | ||
409 | .port = 0x0000, | ||
410 | .dma_ch = 14, | ||
411 | }, { | ||
412 | .id = HPBDMA_SLAVE_USBFUNC_RX, /* for D1 */ | ||
413 | .addr = 0xffe6001c, | ||
414 | .dcr = HPB_DMAE_DCR_SMDL | | ||
415 | HPB_DMAE_DCR_SPDS_32BIT | | ||
416 | HPB_DMAE_DCR_DPDS_32BIT, | ||
417 | .port = 0x0101, | ||
418 | .dma_ch = 15, | ||
351 | }, | 419 | }, |
420 | |||
421 | HPBDMA_SSI(0), | ||
422 | HPBDMA_SSI(1), | ||
423 | HPBDMA_SSI(2), | ||
424 | HPBDMA_SSI(3), | ||
425 | HPBDMA_SSI(4), | ||
426 | HPBDMA_SSI(5), | ||
427 | HPBDMA_SSI(6), | ||
428 | HPBDMA_SSI(7), | ||
429 | HPBDMA_SSI(8), | ||
430 | |||
431 | HPBDMA_HPBIF(0), | ||
432 | HPBDMA_HPBIF(1), | ||
433 | HPBDMA_HPBIF(2), | ||
434 | HPBDMA_HPBIF(3), | ||
435 | HPBDMA_HPBIF(4), | ||
436 | HPBDMA_HPBIF(5), | ||
437 | HPBDMA_HPBIF(6), | ||
438 | HPBDMA_HPBIF(7), | ||
439 | HPBDMA_HPBIF(8), | ||
352 | }; | 440 | }; |
353 | 441 | ||
354 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { | 442 | static const struct hpb_dmae_channel hpb_dmae_channels[] = { |
443 | HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_TX), /* ch. 14 */ | ||
444 | HPB_DMAE_CHANNEL(0x7c, HPBDMA_SLAVE_USBFUNC_RX), /* ch. 15 */ | ||
355 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ | 445 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_TX), /* ch. 21 */ |
356 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ | 446 | HPB_DMAE_CHANNEL(0x7e, HPBDMA_SLAVE_SDHI0_RX), /* ch. 22 */ |
447 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_TX), /* ch. 28 */ | ||
448 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI0_RX), /* ch. 28 */ | ||
449 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_TX), /* ch. 28 */ | ||
450 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF0_RX), /* ch. 28 */ | ||
451 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_TX), /* ch. 29 */ | ||
452 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI1_RX), /* ch. 29 */ | ||
453 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_TX), /* ch. 29 */ | ||
454 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF1_RX), /* ch. 29 */ | ||
455 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_TX), /* ch. 30 */ | ||
456 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI2_RX), /* ch. 30 */ | ||
457 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_TX), /* ch. 30 */ | ||
458 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF2_RX), /* ch. 30 */ | ||
459 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_TX), /* ch. 31 */ | ||
460 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI3_RX), /* ch. 31 */ | ||
461 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_TX), /* ch. 31 */ | ||
462 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF3_RX), /* ch. 31 */ | ||
463 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_TX), /* ch. 32 */ | ||
464 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI4_RX), /* ch. 32 */ | ||
465 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_TX), /* ch. 32 */ | ||
466 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF4_RX), /* ch. 32 */ | ||
467 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_TX), /* ch. 33 */ | ||
468 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI5_RX), /* ch. 33 */ | ||
469 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_TX), /* ch. 33 */ | ||
470 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF5_RX), /* ch. 33 */ | ||
471 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_TX), /* ch. 34 */ | ||
472 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI6_RX), /* ch. 34 */ | ||
473 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_TX), /* ch. 34 */ | ||
474 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF6_RX), /* ch. 34 */ | ||
475 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_TX), /* ch. 35 */ | ||
476 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI7_RX), /* ch. 35 */ | ||
477 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_TX), /* ch. 35 */ | ||
478 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF7_RX), /* ch. 35 */ | ||
479 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_TX), /* ch. 36 */ | ||
480 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_SSI8_RX), /* ch. 36 */ | ||
481 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_TX), /* ch. 36 */ | ||
482 | HPB_DMAE_CHANNEL(0x7f, HPBDMA_SLAVE_HPBIF8_RX), /* ch. 36 */ | ||
357 | }; | 483 | }; |
358 | 484 | ||
359 | static struct hpb_dmae_pdata dma_platform_data __initdata = { | 485 | static struct hpb_dmae_pdata dma_platform_data __initdata = { |
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 13049e9d691c..339292e85838 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
@@ -188,107 +188,35 @@ void __init r8a7779_pinmux_init(void) | |||
188 | ARRAY_SIZE(r8a7779_pinctrl_devices)); | 188 | ARRAY_SIZE(r8a7779_pinctrl_devices)); |
189 | } | 189 | } |
190 | 190 | ||
191 | static struct plat_sci_port scif0_platform_data = { | 191 | /* SCIF */ |
192 | .mapbase = 0xffe40000, | 192 | #define R8A7779_SCIF(index, baseaddr, irq) \ |
193 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 193 | static struct plat_sci_port scif##index##_platform_data = { \ |
194 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 194 | .type = PORT_SCIF, \ |
195 | .scbrr_algo_id = SCBRR_ALGO_2, | 195 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
196 | .type = PORT_SCIF, | 196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, \ |
197 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)), | 197 | }; \ |
198 | }; | 198 | \ |
199 | 199 | static struct resource scif##index##_resources[] = { \ | |
200 | static struct platform_device scif0_device = { | 200 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
201 | .name = "sh-sci", | 201 | DEFINE_RES_IRQ(irq), \ |
202 | .id = 0, | 202 | }; \ |
203 | .dev = { | 203 | \ |
204 | .platform_data = &scif0_platform_data, | 204 | static struct platform_device scif##index##_device = { \ |
205 | }, | 205 | .name = "sh-sci", \ |
206 | }; | 206 | .id = index, \ |
207 | 207 | .resource = scif##index##_resources, \ | |
208 | static struct plat_sci_port scif1_platform_data = { | 208 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ |
209 | .mapbase = 0xffe41000, | 209 | .dev = { \ |
210 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 210 | .platform_data = &scif##index##_platform_data, \ |
211 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 211 | }, \ |
212 | .scbrr_algo_id = SCBRR_ALGO_2, | 212 | } |
213 | .type = PORT_SCIF, | ||
214 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)), | ||
215 | }; | ||
216 | |||
217 | static struct platform_device scif1_device = { | ||
218 | .name = "sh-sci", | ||
219 | .id = 1, | ||
220 | .dev = { | ||
221 | .platform_data = &scif1_platform_data, | ||
222 | }, | ||
223 | }; | ||
224 | |||
225 | static struct plat_sci_port scif2_platform_data = { | ||
226 | .mapbase = 0xffe42000, | ||
227 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
228 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
229 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
230 | .type = PORT_SCIF, | ||
231 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)), | ||
232 | }; | ||
233 | |||
234 | static struct platform_device scif2_device = { | ||
235 | .name = "sh-sci", | ||
236 | .id = 2, | ||
237 | .dev = { | ||
238 | .platform_data = &scif2_platform_data, | ||
239 | }, | ||
240 | }; | ||
241 | |||
242 | static struct plat_sci_port scif3_platform_data = { | ||
243 | .mapbase = 0xffe43000, | ||
244 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
245 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
246 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
247 | .type = PORT_SCIF, | ||
248 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)), | ||
249 | }; | ||
250 | |||
251 | static struct platform_device scif3_device = { | ||
252 | .name = "sh-sci", | ||
253 | .id = 3, | ||
254 | .dev = { | ||
255 | .platform_data = &scif3_platform_data, | ||
256 | }, | ||
257 | }; | ||
258 | |||
259 | static struct plat_sci_port scif4_platform_data = { | ||
260 | .mapbase = 0xffe44000, | ||
261 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
262 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
263 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
264 | .type = PORT_SCIF, | ||
265 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)), | ||
266 | }; | ||
267 | |||
268 | static struct platform_device scif4_device = { | ||
269 | .name = "sh-sci", | ||
270 | .id = 4, | ||
271 | .dev = { | ||
272 | .platform_data = &scif4_platform_data, | ||
273 | }, | ||
274 | }; | ||
275 | |||
276 | static struct plat_sci_port scif5_platform_data = { | ||
277 | .mapbase = 0xffe45000, | ||
278 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | ||
279 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | ||
280 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
281 | .type = PORT_SCIF, | ||
282 | .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)), | ||
283 | }; | ||
284 | 213 | ||
285 | static struct platform_device scif5_device = { | 214 | R8A7779_SCIF(0, 0xffe40000, gic_iid(0x78)); |
286 | .name = "sh-sci", | 215 | R8A7779_SCIF(1, 0xffe41000, gic_iid(0x79)); |
287 | .id = 5, | 216 | R8A7779_SCIF(2, 0xffe42000, gic_iid(0x7a)); |
288 | .dev = { | 217 | R8A7779_SCIF(3, 0xffe43000, gic_iid(0x7b)); |
289 | .platform_data = &scif5_platform_data, | 218 | R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c)); |
290 | }, | 219 | R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d)); |
291 | }; | ||
292 | 220 | ||
293 | /* TMU */ | 221 | /* TMU */ |
294 | static struct sh_timer_config tmu00_platform_data = { | 222 | static struct sh_timer_config tmu00_platform_data = { |
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bcebbcb00..66476d21544d 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
@@ -63,6 +63,27 @@ R8A7790_GPIO(5); | |||
63 | &r8a7790_gpio##idx##_platform_data, \ | 63 | &r8a7790_gpio##idx##_platform_data, \ |
64 | sizeof(r8a7790_gpio##idx##_platform_data)) | 64 | sizeof(r8a7790_gpio##idx##_platform_data)) |
65 | 65 | ||
66 | static struct resource i2c_resources[] __initdata = { | ||
67 | /* I2C0 */ | ||
68 | DEFINE_RES_MEM(0xE6508000, 0x40), | ||
69 | DEFINE_RES_IRQ(gic_spi(287)), | ||
70 | /* I2C1 */ | ||
71 | DEFINE_RES_MEM(0xE6518000, 0x40), | ||
72 | DEFINE_RES_IRQ(gic_spi(288)), | ||
73 | /* I2C2 */ | ||
74 | DEFINE_RES_MEM(0xE6530000, 0x40), | ||
75 | DEFINE_RES_IRQ(gic_spi(286)), | ||
76 | /* I2C3 */ | ||
77 | DEFINE_RES_MEM(0xE6540000, 0x40), | ||
78 | DEFINE_RES_IRQ(gic_spi(290)), | ||
79 | |||
80 | }; | ||
81 | |||
82 | #define r8a7790_register_i2c(idx) \ | ||
83 | platform_device_register_simple( \ | ||
84 | "i2c-rcar", idx, \ | ||
85 | i2c_resources + (2 * idx), 2); \ | ||
86 | |||
66 | void __init r8a7790_pinmux_init(void) | 87 | void __init r8a7790_pinmux_init(void) |
67 | { | 88 | { |
68 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, | 89 | platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, |
@@ -73,63 +94,57 @@ void __init r8a7790_pinmux_init(void) | |||
73 | r8a7790_register_gpio(3); | 94 | r8a7790_register_gpio(3); |
74 | r8a7790_register_gpio(4); | 95 | r8a7790_register_gpio(4); |
75 | r8a7790_register_gpio(5); | 96 | r8a7790_register_gpio(5); |
97 | r8a7790_register_i2c(0); | ||
98 | r8a7790_register_i2c(1); | ||
99 | r8a7790_register_i2c(2); | ||
100 | r8a7790_register_i2c(3); | ||
76 | } | 101 | } |
77 | 102 | ||
78 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 103 | #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq) \ |
79 | .type = scif_type, \ | 104 | static struct plat_sci_port scif##index##_platform_data = { \ |
80 | .mapbase = baseaddr, \ | 105 | .type = scif_type, \ |
81 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | 106 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
82 | .irqs = SCIx_IRQ_MUXED(irq) | 107 | .scscr = _scscr, \ |
83 | 108 | }; \ | |
84 | #define SCIFA_DATA(index, baseaddr, irq) \ | 109 | \ |
85 | [index] = { \ | 110 | static struct resource scif##index##_resources[] = { \ |
86 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | 111 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
87 | .scbrr_algo_id = SCBRR_ALGO_4, \ | 112 | DEFINE_RES_IRQ(irq), \ |
88 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ | ||
89 | } | ||
90 | |||
91 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
92 | [index] = { \ | ||
93 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
94 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
95 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
96 | } | ||
97 | |||
98 | #define SCIF_DATA(index, baseaddr, irq) \ | ||
99 | [index] = { \ | ||
100 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | ||
101 | .scbrr_algo_id = SCBRR_ALGO_2, \ | ||
102 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
103 | } | ||
104 | |||
105 | #define HSCIF_DATA(index, baseaddr, irq) \ | ||
106 | [index] = { \ | ||
107 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | ||
108 | .scbrr_algo_id = SCBRR_ALGO_6, \ | ||
109 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
110 | } | 113 | } |
111 | 114 | ||
112 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | 115 | #define R8A7790_SCIF(index, baseaddr, irq) \ |
113 | HSCIF0, HSCIF1 }; | 116 | __R8A7790_SCIF(PORT_SCIF, SCSCR_RE | SCSCR_TE, \ |
114 | 117 | index, baseaddr, irq) | |
115 | static const struct plat_sci_port scif[] __initconst = { | 118 | |
116 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 119 | #define R8A7790_SCIFA(index, baseaddr, irq) \ |
117 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 120 | __R8A7790_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \ |
118 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 121 | index, baseaddr, irq) |
119 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 122 | |
120 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 123 | #define R8A7790_SCIFB(index, baseaddr, irq) \ |
121 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | 124 | __R8A7790_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \ |
122 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | 125 | index, baseaddr, irq) |
123 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | 126 | |
124 | HSCIF_DATA(HSCIF0, 0xe62c0000, gic_spi(154)), /* HSCIF0 */ | 127 | #define R8A7790_HSCIF(index, baseaddr, irq) \ |
125 | HSCIF_DATA(HSCIF1, 0xe62c8000, gic_spi(155)), /* HSCIF1 */ | 128 | __R8A7790_SCIF(PORT_HSCIF, SCSCR_RE | SCSCR_TE, \ |
126 | }; | 129 | index, baseaddr, irq) |
127 | 130 | ||
128 | static inline void r8a7790_register_scif(int idx) | 131 | R8A7790_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
129 | { | 132 | R8A7790_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
130 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 133 | R8A7790_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
131 | sizeof(struct plat_sci_port)); | 134 | R8A7790_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
132 | } | 135 | R8A7790_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
136 | R8A7790_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ | ||
137 | R8A7790_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ | ||
138 | R8A7790_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ | ||
139 | R8A7790_HSCIF(8, 0xe62c0000, gic_spi(154)); /* HSCIF0 */ | ||
140 | R8A7790_HSCIF(9, 0xe62c8000, gic_spi(155)); /* HSCIF1 */ | ||
141 | |||
142 | #define r8a7790_register_scif(index) \ | ||
143 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
144 | scif##index##_resources, \ | ||
145 | ARRAY_SIZE(scif##index##_resources), \ | ||
146 | &scif##index##_platform_data, \ | ||
147 | sizeof(scif##index##_platform_data)) | ||
133 | 148 | ||
134 | static const struct renesas_irqc_config irqc0_data __initconst = { | 149 | static const struct renesas_irqc_config irqc0_data __initconst = { |
135 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ | 150 | .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ |
@@ -182,16 +197,16 @@ static const struct resource cmt00_resources[] __initconst = { | |||
182 | 197 | ||
183 | void __init r8a7790_add_dt_devices(void) | 198 | void __init r8a7790_add_dt_devices(void) |
184 | { | 199 | { |
185 | r8a7790_register_scif(SCIFA0); | 200 | r8a7790_register_scif(0); |
186 | r8a7790_register_scif(SCIFA1); | 201 | r8a7790_register_scif(1); |
187 | r8a7790_register_scif(SCIFB0); | 202 | r8a7790_register_scif(2); |
188 | r8a7790_register_scif(SCIFB1); | 203 | r8a7790_register_scif(3); |
189 | r8a7790_register_scif(SCIFB2); | 204 | r8a7790_register_scif(4); |
190 | r8a7790_register_scif(SCIFA2); | 205 | r8a7790_register_scif(5); |
191 | r8a7790_register_scif(SCIF0); | 206 | r8a7790_register_scif(6); |
192 | r8a7790_register_scif(SCIF1); | 207 | r8a7790_register_scif(7); |
193 | r8a7790_register_scif(HSCIF0); | 208 | r8a7790_register_scif(8); |
194 | r8a7790_register_scif(HSCIF1); | 209 | r8a7790_register_scif(9); |
195 | r8a7790_register_cmt(00); | 210 | r8a7790_register_cmt(00); |
196 | } | 211 | } |
197 | 212 | ||
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index d9393d61ee27..e28404e43860 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c | |||
@@ -22,6 +22,7 @@ | |||
22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
23 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
25 | #include <linux/platform_data/gpio-rcar.h> | ||
25 | #include <linux/platform_data/irq-renesas-irqc.h> | 26 | #include <linux/platform_data/irq-renesas-irqc.h> |
26 | #include <linux/serial_sci.h> | 27 | #include <linux/serial_sci.h> |
27 | #include <linux/sh_timer.h> | 28 | #include <linux/sh_timer.h> |
@@ -31,66 +32,101 @@ | |||
31 | #include <mach/rcar-gen2.h> | 32 | #include <mach/rcar-gen2.h> |
32 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
33 | 34 | ||
34 | #define SCIF_COMMON(scif_type, baseaddr, irq) \ | 35 | static const struct resource pfc_resources[] __initconst = { |
35 | .type = scif_type, \ | 36 | DEFINE_RES_MEM(0xe6060000, 0x250), |
36 | .mapbase = baseaddr, \ | 37 | }; |
37 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ | ||
38 | .irqs = SCIx_IRQ_MUXED(irq) | ||
39 | |||
40 | #define SCIFA_DATA(index, baseaddr, irq) \ | ||
41 | [index] = { \ | ||
42 | SCIF_COMMON(PORT_SCIFA, baseaddr, irq), \ | ||
43 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
44 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
45 | } | ||
46 | |||
47 | #define SCIFB_DATA(index, baseaddr, irq) \ | ||
48 | [index] = { \ | ||
49 | SCIF_COMMON(PORT_SCIFB, baseaddr, irq), \ | ||
50 | .scbrr_algo_id = SCBRR_ALGO_4, \ | ||
51 | .scscr = SCSCR_RE | SCSCR_TE, \ | ||
52 | } | ||
53 | 38 | ||
54 | #define SCIF_DATA(index, baseaddr, irq) \ | 39 | #define r8a7791_register_pfc() \ |
55 | [index] = { \ | 40 | platform_device_register_simple("pfc-r8a7791", -1, pfc_resources, \ |
56 | SCIF_COMMON(PORT_SCIF, baseaddr, irq), \ | 41 | ARRAY_SIZE(pfc_resources)) |
57 | .scbrr_algo_id = SCBRR_ALGO_2, \ | 42 | |
58 | .scscr = SCSCR_RE | SCSCR_TE, \ | 43 | #define R8A7791_GPIO(idx, base, nr) \ |
44 | static const struct resource r8a7791_gpio##idx##_resources[] __initconst = { \ | ||
45 | DEFINE_RES_MEM((base), 0x50), \ | ||
46 | DEFINE_RES_IRQ(gic_spi(4 + (idx))), \ | ||
47 | }; \ | ||
48 | \ | ||
49 | static const struct gpio_rcar_config \ | ||
50 | r8a7791_gpio##idx##_platform_data __initconst = { \ | ||
51 | .gpio_base = 32 * (idx), \ | ||
52 | .irq_base = 0, \ | ||
53 | .number_of_pins = (nr), \ | ||
54 | .pctl_name = "pfc-r8a7791", \ | ||
55 | .has_both_edge_trigger = 1, \ | ||
56 | }; \ | ||
57 | |||
58 | R8A7791_GPIO(0, 0xe6050000, 32); | ||
59 | R8A7791_GPIO(1, 0xe6051000, 32); | ||
60 | R8A7791_GPIO(2, 0xe6052000, 32); | ||
61 | R8A7791_GPIO(3, 0xe6053000, 32); | ||
62 | R8A7791_GPIO(4, 0xe6054000, 32); | ||
63 | R8A7791_GPIO(5, 0xe6055000, 32); | ||
64 | R8A7791_GPIO(6, 0xe6055400, 32); | ||
65 | R8A7791_GPIO(7, 0xe6055800, 26); | ||
66 | |||
67 | #define r8a7791_register_gpio(idx) \ | ||
68 | platform_device_register_resndata(&platform_bus, "gpio_rcar", idx, \ | ||
69 | r8a7791_gpio##idx##_resources, \ | ||
70 | ARRAY_SIZE(r8a7791_gpio##idx##_resources), \ | ||
71 | &r8a7791_gpio##idx##_platform_data, \ | ||
72 | sizeof(r8a7791_gpio##idx##_platform_data)) | ||
73 | |||
74 | void __init r8a7791_pinmux_init(void) | ||
75 | { | ||
76 | r8a7791_register_pfc(); | ||
77 | r8a7791_register_gpio(0); | ||
78 | r8a7791_register_gpio(1); | ||
79 | r8a7791_register_gpio(2); | ||
80 | r8a7791_register_gpio(3); | ||
81 | r8a7791_register_gpio(4); | ||
82 | r8a7791_register_gpio(5); | ||
83 | r8a7791_register_gpio(6); | ||
84 | r8a7791_register_gpio(7); | ||
59 | } | 85 | } |
60 | 86 | ||
61 | #define HSCIF_DATA(index, baseaddr, irq) \ | 87 | #define __R8A7791_SCIF(scif_type, index, baseaddr, irq) \ |
62 | [index] = { \ | 88 | static struct plat_sci_port scif##index##_platform_data = { \ |
63 | SCIF_COMMON(PORT_HSCIF, baseaddr, irq), \ | 89 | .type = scif_type, \ |
64 | .scbrr_algo_id = SCBRR_ALGO_6, \ | 90 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \ |
65 | .scscr = SCSCR_RE | SCSCR_TE, \ | 91 | .scscr = SCSCR_RE | SCSCR_TE, \ |
92 | }; \ | ||
93 | \ | ||
94 | static struct resource scif##index##_resources[] = { \ | ||
95 | DEFINE_RES_MEM(baseaddr, 0x100), \ | ||
96 | DEFINE_RES_IRQ(irq), \ | ||
66 | } | 97 | } |
67 | 98 | ||
68 | enum { SCIFA0, SCIFA1, SCIFB0, SCIFB1, SCIFB2, SCIFA2, SCIF0, SCIF1, | 99 | #define R8A7791_SCIF(index, baseaddr, irq) \ |
69 | SCIF2, SCIF3, SCIF4, SCIF5, SCIFA3, SCIFA4, SCIFA5 }; | 100 | __R8A7791_SCIF(PORT_SCIF, index, baseaddr, irq) |
70 | 101 | ||
71 | static const struct plat_sci_port scif[] __initconst = { | 102 | #define R8A7791_SCIFA(index, baseaddr, irq) \ |
72 | SCIFA_DATA(SCIFA0, 0xe6c40000, gic_spi(144)), /* SCIFA0 */ | 103 | __R8A7791_SCIF(PORT_SCIFA, index, baseaddr, irq) |
73 | SCIFA_DATA(SCIFA1, 0xe6c50000, gic_spi(145)), /* SCIFA1 */ | 104 | |
74 | SCIFB_DATA(SCIFB0, 0xe6c20000, gic_spi(148)), /* SCIFB0 */ | 105 | #define R8A7791_SCIFB(index, baseaddr, irq) \ |
75 | SCIFB_DATA(SCIFB1, 0xe6c30000, gic_spi(149)), /* SCIFB1 */ | 106 | __R8A7791_SCIF(PORT_SCIFB, index, baseaddr, irq) |
76 | SCIFB_DATA(SCIFB2, 0xe6ce0000, gic_spi(150)), /* SCIFB2 */ | 107 | |
77 | SCIFA_DATA(SCIFA2, 0xe6c60000, gic_spi(151)), /* SCIFA2 */ | 108 | R8A7791_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */ |
78 | SCIF_DATA(SCIF0, 0xe6e60000, gic_spi(152)), /* SCIF0 */ | 109 | R8A7791_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */ |
79 | SCIF_DATA(SCIF1, 0xe6e68000, gic_spi(153)), /* SCIF1 */ | 110 | R8A7791_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */ |
80 | SCIF_DATA(SCIF2, 0xe6e58000, gic_spi(22)), /* SCIF2 */ | 111 | R8A7791_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */ |
81 | SCIF_DATA(SCIF3, 0xe6ea8000, gic_spi(23)), /* SCIF3 */ | 112 | R8A7791_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */ |
82 | SCIF_DATA(SCIF4, 0xe6ee0000, gic_spi(24)), /* SCIF4 */ | 113 | R8A7791_SCIFA(5, 0xe6c60000, gic_spi(151)); /* SCIFA2 */ |
83 | SCIF_DATA(SCIF5, 0xe6ee8000, gic_spi(25)), /* SCIF5 */ | 114 | R8A7791_SCIF(6, 0xe6e60000, gic_spi(152)); /* SCIF0 */ |
84 | SCIFA_DATA(SCIFA3, 0xe6c70000, gic_spi(29)), /* SCIFA3 */ | 115 | R8A7791_SCIF(7, 0xe6e68000, gic_spi(153)); /* SCIF1 */ |
85 | SCIFA_DATA(SCIFA4, 0xe6c78000, gic_spi(30)), /* SCIFA4 */ | 116 | R8A7791_SCIF(8, 0xe6e58000, gic_spi(22)); /* SCIF2 */ |
86 | SCIFA_DATA(SCIFA5, 0xe6c80000, gic_spi(31)), /* SCIFA5 */ | 117 | R8A7791_SCIF(9, 0xe6ea8000, gic_spi(23)); /* SCIF3 */ |
87 | }; | 118 | R8A7791_SCIF(10, 0xe6ee0000, gic_spi(24)); /* SCIF4 */ |
88 | 119 | R8A7791_SCIF(11, 0xe6ee8000, gic_spi(25)); /* SCIF5 */ | |
89 | static inline void r8a7791_register_scif(int idx) | 120 | R8A7791_SCIFA(12, 0xe6c70000, gic_spi(29)); /* SCIFA3 */ |
90 | { | 121 | R8A7791_SCIFA(13, 0xe6c78000, gic_spi(30)); /* SCIFA4 */ |
91 | platform_device_register_data(&platform_bus, "sh-sci", idx, &scif[idx], | 122 | R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */ |
92 | sizeof(struct plat_sci_port)); | 123 | |
93 | } | 124 | #define r8a7791_register_scif(index) \ |
125 | platform_device_register_resndata(&platform_bus, "sh-sci", index, \ | ||
126 | scif##index##_resources, \ | ||
127 | ARRAY_SIZE(scif##index##_resources), \ | ||
128 | &scif##index##_platform_data, \ | ||
129 | sizeof(scif##index##_platform_data)) | ||
94 | 130 | ||
95 | static const struct sh_timer_config cmt00_platform_data __initconst = { | 131 | static const struct sh_timer_config cmt00_platform_data __initconst = { |
96 | .name = "CMT00", | 132 | .name = "CMT00", |
@@ -136,23 +172,34 @@ static struct resource irqc0_resources[] = { | |||
136 | &irqc##idx##_data, \ | 172 | &irqc##idx##_data, \ |
137 | sizeof(struct renesas_irqc_config)) | 173 | sizeof(struct renesas_irqc_config)) |
138 | 174 | ||
175 | static const struct resource thermal_resources[] __initconst = { | ||
176 | DEFINE_RES_MEM(0xe61f0000, 0x14), | ||
177 | DEFINE_RES_MEM(0xe61f0100, 0x38), | ||
178 | DEFINE_RES_IRQ(gic_spi(69)), | ||
179 | }; | ||
180 | |||
181 | #define r8a7791_register_thermal() \ | ||
182 | platform_device_register_simple("rcar_thermal", -1, \ | ||
183 | thermal_resources, \ | ||
184 | ARRAY_SIZE(thermal_resources)) | ||
185 | |||
139 | void __init r8a7791_add_dt_devices(void) | 186 | void __init r8a7791_add_dt_devices(void) |
140 | { | 187 | { |
141 | r8a7791_register_scif(SCIFA0); | 188 | r8a7791_register_scif(0); |
142 | r8a7791_register_scif(SCIFA1); | 189 | r8a7791_register_scif(1); |
143 | r8a7791_register_scif(SCIFB0); | 190 | r8a7791_register_scif(2); |
144 | r8a7791_register_scif(SCIFB1); | 191 | r8a7791_register_scif(3); |
145 | r8a7791_register_scif(SCIFB2); | 192 | r8a7791_register_scif(4); |
146 | r8a7791_register_scif(SCIFA2); | 193 | r8a7791_register_scif(5); |
147 | r8a7791_register_scif(SCIF0); | 194 | r8a7791_register_scif(6); |
148 | r8a7791_register_scif(SCIF1); | 195 | r8a7791_register_scif(7); |
149 | r8a7791_register_scif(SCIF2); | 196 | r8a7791_register_scif(8); |
150 | r8a7791_register_scif(SCIF3); | 197 | r8a7791_register_scif(9); |
151 | r8a7791_register_scif(SCIF4); | 198 | r8a7791_register_scif(10); |
152 | r8a7791_register_scif(SCIF5); | 199 | r8a7791_register_scif(11); |
153 | r8a7791_register_scif(SCIFA3); | 200 | r8a7791_register_scif(12); |
154 | r8a7791_register_scif(SCIFA4); | 201 | r8a7791_register_scif(13); |
155 | r8a7791_register_scif(SCIFA5); | 202 | r8a7791_register_scif(14); |
156 | r8a7791_register_cmt(00); | 203 | r8a7791_register_cmt(00); |
157 | } | 204 | } |
158 | 205 | ||
@@ -160,6 +207,7 @@ void __init r8a7791_add_standard_devices(void) | |||
160 | { | 207 | { |
161 | r8a7791_add_dt_devices(); | 208 | r8a7791_add_dt_devices(); |
162 | r8a7791_register_irqc(0); | 209 | r8a7791_register_irqc(0); |
210 | r8a7791_register_thermal(); | ||
163 | } | 211 | } |
164 | 212 | ||
165 | void __init r8a7791_init_early(void) | 213 | void __init r8a7791_init_early(void) |
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 5734c24bf6c7..69ccc6c6fd33 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c | |||
@@ -18,6 +18,7 @@ | |||
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/clk/shmobile.h> | ||
21 | #include <linux/clocksource.h> | 22 | #include <linux/clocksource.h> |
22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
23 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void) | |||
44 | 45 | ||
45 | void __init rcar_gen2_timer_init(void) | 46 | void __init rcar_gen2_timer_init(void) |
46 | { | 47 | { |
47 | #ifdef CONFIG_ARM_ARCH_TIMER | 48 | #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK) |
48 | u32 mode = rcar_gen2_read_mode_pins(); | 49 | u32 mode = rcar_gen2_read_mode_pins(); |
50 | #endif | ||
51 | #ifdef CONFIG_ARM_ARCH_TIMER | ||
49 | void __iomem *base; | 52 | void __iomem *base; |
50 | int extal_mhz = 0; | 53 | int extal_mhz = 0; |
51 | u32 freq; | 54 | u32 freq; |
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void) | |||
78 | /* Remap "armgcnt address map" space */ | 81 | /* Remap "armgcnt address map" space */ |
79 | base = ioremap(0xe6080000, PAGE_SIZE); | 82 | base = ioremap(0xe6080000, PAGE_SIZE); |
80 | 83 | ||
81 | /* Update registers with correct frequency */ | 84 | /* |
82 | iowrite32(freq, base + CNTFID0); | 85 | * Update the timer if it is either not running, or is not at the |
83 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | 86 | * right frequency. The timer is only configurable in secure mode |
87 | * so this avoids an abort if the loader started the timer and | ||
88 | * entered the kernel in non-secure mode. | ||
89 | */ | ||
90 | |||
91 | if ((ioread32(base + CNTCR) & 1) == 0 || | ||
92 | ioread32(base + CNTFID0) != freq) { | ||
93 | /* Update registers with correct frequency */ | ||
94 | iowrite32(freq, base + CNTFID0); | ||
95 | asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq)); | ||
96 | |||
97 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
98 | iowrite32(1, base + CNTCR); | ||
99 | } | ||
84 | 100 | ||
85 | /* make sure arch timer is started by setting bit 0 of CNTCR */ | ||
86 | iowrite32(1, base + CNTCR); | ||
87 | iounmap(base); | 101 | iounmap(base); |
88 | #endif /* CONFIG_ARM_ARCH_TIMER */ | 102 | #endif /* CONFIG_ARM_ARCH_TIMER */ |
89 | 103 | ||
104 | #ifdef CONFIG_COMMON_CLK | ||
105 | rcar_gen2_clocks_init(mode); | ||
106 | #endif | ||
90 | clocksource_of_init(); | 107 | clocksource_of_init(); |
91 | } | 108 | } |
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 311878391e18..27301278c208 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
@@ -86,138 +86,36 @@ void __init sh7372_pinmux_init(void) | |||
86 | platform_device_register(&sh7372_pfc_device); | 86 | platform_device_register(&sh7372_pfc_device); |
87 | } | 87 | } |
88 | 88 | ||
89 | /* SCIFA0 */ | 89 | /* SCIF */ |
90 | static struct plat_sci_port scif0_platform_data = { | 90 | #define SH7372_SCIF(scif_type, index, baseaddr, irq) \ |
91 | .mapbase = 0xe6c40000, | 91 | static struct plat_sci_port scif##index##_platform_data = { \ |
92 | .flags = UPF_BOOT_AUTOCONF, | 92 | .type = scif_type, \ |
93 | .scscr = SCSCR_RE | SCSCR_TE, | 93 | .flags = UPF_BOOT_AUTOCONF, \ |
94 | .scbrr_algo_id = SCBRR_ALGO_4, | 94 | .scscr = SCSCR_RE | SCSCR_TE, \ |
95 | .type = PORT_SCIFA, | 95 | }; \ |
96 | .irqs = { evt2irq(0x0c00), evt2irq(0x0c00), | 96 | \ |
97 | evt2irq(0x0c00), evt2irq(0x0c00) }, | 97 | static struct resource scif##index##_resources[] = { \ |
98 | }; | 98 | DEFINE_RES_MEM(baseaddr, 0x100), \ |
99 | 99 | DEFINE_RES_IRQ(irq), \ | |
100 | static struct platform_device scif0_device = { | 100 | }; \ |
101 | .name = "sh-sci", | 101 | \ |
102 | .id = 0, | 102 | static struct platform_device scif##index##_device = { \ |
103 | .dev = { | 103 | .name = "sh-sci", \ |
104 | .platform_data = &scif0_platform_data, | 104 | .id = index, \ |
105 | }, | 105 | .resource = scif##index##_resources, \ |
106 | }; | 106 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ |
107 | 107 | .dev = { \ | |
108 | /* SCIFA1 */ | 108 | .platform_data = &scif##index##_platform_data, \ |
109 | static struct plat_sci_port scif1_platform_data = { | 109 | }, \ |
110 | .mapbase = 0xe6c50000, | 110 | } |
111 | .flags = UPF_BOOT_AUTOCONF, | ||
112 | .scscr = SCSCR_RE | SCSCR_TE, | ||
113 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
114 | .type = PORT_SCIFA, | ||
115 | .irqs = { evt2irq(0x0c20), evt2irq(0x0c20), | ||
116 | evt2irq(0x0c20), evt2irq(0x0c20) }, | ||
117 | }; | ||
118 | |||
119 | static struct platform_device scif1_device = { | ||
120 | .name = "sh-sci", | ||
121 | .id = 1, | ||
122 | .dev = { | ||
123 | .platform_data = &scif1_platform_data, | ||
124 | }, | ||
125 | }; | ||
126 | |||
127 | /* SCIFA2 */ | ||
128 | static struct plat_sci_port scif2_platform_data = { | ||
129 | .mapbase = 0xe6c60000, | ||
130 | .flags = UPF_BOOT_AUTOCONF, | ||
131 | .scscr = SCSCR_RE | SCSCR_TE, | ||
132 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
133 | .type = PORT_SCIFA, | ||
134 | .irqs = { evt2irq(0x0c40), evt2irq(0x0c40), | ||
135 | evt2irq(0x0c40), evt2irq(0x0c40) }, | ||
136 | }; | ||
137 | |||
138 | static struct platform_device scif2_device = { | ||
139 | .name = "sh-sci", | ||
140 | .id = 2, | ||
141 | .dev = { | ||
142 | .platform_data = &scif2_platform_data, | ||
143 | }, | ||
144 | }; | ||
145 | |||
146 | /* SCIFA3 */ | ||
147 | static struct plat_sci_port scif3_platform_data = { | ||
148 | .mapbase = 0xe6c70000, | ||
149 | .flags = UPF_BOOT_AUTOCONF, | ||
150 | .scscr = SCSCR_RE | SCSCR_TE, | ||
151 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
152 | .type = PORT_SCIFA, | ||
153 | .irqs = { evt2irq(0x0c60), evt2irq(0x0c60), | ||
154 | evt2irq(0x0c60), evt2irq(0x0c60) }, | ||
155 | }; | ||
156 | |||
157 | static struct platform_device scif3_device = { | ||
158 | .name = "sh-sci", | ||
159 | .id = 3, | ||
160 | .dev = { | ||
161 | .platform_data = &scif3_platform_data, | ||
162 | }, | ||
163 | }; | ||
164 | |||
165 | /* SCIFA4 */ | ||
166 | static struct plat_sci_port scif4_platform_data = { | ||
167 | .mapbase = 0xe6c80000, | ||
168 | .flags = UPF_BOOT_AUTOCONF, | ||
169 | .scscr = SCSCR_RE | SCSCR_TE, | ||
170 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
171 | .type = PORT_SCIFA, | ||
172 | .irqs = { evt2irq(0x0d20), evt2irq(0x0d20), | ||
173 | evt2irq(0x0d20), evt2irq(0x0d20) }, | ||
174 | }; | ||
175 | |||
176 | static struct platform_device scif4_device = { | ||
177 | .name = "sh-sci", | ||
178 | .id = 4, | ||
179 | .dev = { | ||
180 | .platform_data = &scif4_platform_data, | ||
181 | }, | ||
182 | }; | ||
183 | |||
184 | /* SCIFA5 */ | ||
185 | static struct plat_sci_port scif5_platform_data = { | ||
186 | .mapbase = 0xe6cb0000, | ||
187 | .flags = UPF_BOOT_AUTOCONF, | ||
188 | .scscr = SCSCR_RE | SCSCR_TE, | ||
189 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
190 | .type = PORT_SCIFA, | ||
191 | .irqs = { evt2irq(0x0d40), evt2irq(0x0d40), | ||
192 | evt2irq(0x0d40), evt2irq(0x0d40) }, | ||
193 | }; | ||
194 | |||
195 | static struct platform_device scif5_device = { | ||
196 | .name = "sh-sci", | ||
197 | .id = 5, | ||
198 | .dev = { | ||
199 | .platform_data = &scif5_platform_data, | ||
200 | }, | ||
201 | }; | ||
202 | |||
203 | /* SCIFB */ | ||
204 | static struct plat_sci_port scif6_platform_data = { | ||
205 | .mapbase = 0xe6c30000, | ||
206 | .flags = UPF_BOOT_AUTOCONF, | ||
207 | .scscr = SCSCR_RE | SCSCR_TE, | ||
208 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
209 | .type = PORT_SCIFB, | ||
210 | .irqs = { evt2irq(0x0d60), evt2irq(0x0d60), | ||
211 | evt2irq(0x0d60), evt2irq(0x0d60) }, | ||
212 | }; | ||
213 | 111 | ||
214 | static struct platform_device scif6_device = { | 112 | SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00)); |
215 | .name = "sh-sci", | 113 | SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20)); |
216 | .id = 6, | 114 | SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40)); |
217 | .dev = { | 115 | SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60)); |
218 | .platform_data = &scif6_platform_data, | 116 | SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20)); |
219 | }, | 117 | SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40)); |
220 | }; | 118 | SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60)); |
221 | 119 | ||
222 | /* CMT */ | 120 | /* CMT */ |
223 | static struct sh_timer_config cmt2_platform_data = { | 121 | static struct sh_timer_config cmt2_platform_data = { |
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 22de17417fd7..00b348ec48b8 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
@@ -71,167 +71,38 @@ void __init sh73a0_pinmux_init(void) | |||
71 | ARRAY_SIZE(pfc_resources)); | 71 | ARRAY_SIZE(pfc_resources)); |
72 | } | 72 | } |
73 | 73 | ||
74 | static struct plat_sci_port scif0_platform_data = { | 74 | /* SCIF */ |
75 | .mapbase = 0xe6c40000, | 75 | #define SH73A0_SCIF(scif_type, index, baseaddr, irq) \ |
76 | .flags = UPF_BOOT_AUTOCONF, | 76 | static struct plat_sci_port scif##index##_platform_data = { \ |
77 | .scscr = SCSCR_RE | SCSCR_TE, | 77 | .type = scif_type, \ |
78 | .scbrr_algo_id = SCBRR_ALGO_4, | 78 | .flags = UPF_BOOT_AUTOCONF, \ |
79 | .type = PORT_SCIFA, | 79 | .scscr = SCSCR_RE | SCSCR_TE, \ |
80 | .irqs = { gic_spi(72), gic_spi(72), | 80 | }; \ |
81 | gic_spi(72), gic_spi(72) }, | 81 | \ |
82 | }; | 82 | static struct resource scif##index##_resources[] = { \ |
83 | 83 | DEFINE_RES_MEM(baseaddr, 0x100), \ | |
84 | static struct platform_device scif0_device = { | 84 | DEFINE_RES_IRQ(irq), \ |
85 | .name = "sh-sci", | 85 | }; \ |
86 | .id = 0, | 86 | \ |
87 | .dev = { | 87 | static struct platform_device scif##index##_device = { \ |
88 | .platform_data = &scif0_platform_data, | 88 | .name = "sh-sci", \ |
89 | }, | 89 | .id = index, \ |
90 | }; | 90 | .resource = scif##index##_resources, \ |
91 | 91 | .num_resources = ARRAY_SIZE(scif##index##_resources), \ | |
92 | static struct plat_sci_port scif1_platform_data = { | 92 | .dev = { \ |
93 | .mapbase = 0xe6c50000, | 93 | .platform_data = &scif##index##_platform_data, \ |
94 | .flags = UPF_BOOT_AUTOCONF, | 94 | }, \ |
95 | .scscr = SCSCR_RE | SCSCR_TE, | 95 | } |
96 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
97 | .type = PORT_SCIFA, | ||
98 | .irqs = { gic_spi(73), gic_spi(73), | ||
99 | gic_spi(73), gic_spi(73) }, | ||
100 | }; | ||
101 | |||
102 | static struct platform_device scif1_device = { | ||
103 | .name = "sh-sci", | ||
104 | .id = 1, | ||
105 | .dev = { | ||
106 | .platform_data = &scif1_platform_data, | ||
107 | }, | ||
108 | }; | ||
109 | |||
110 | static struct plat_sci_port scif2_platform_data = { | ||
111 | .mapbase = 0xe6c60000, | ||
112 | .flags = UPF_BOOT_AUTOCONF, | ||
113 | .scscr = SCSCR_RE | SCSCR_TE, | ||
114 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
115 | .type = PORT_SCIFA, | ||
116 | .irqs = { gic_spi(74), gic_spi(74), | ||
117 | gic_spi(74), gic_spi(74) }, | ||
118 | }; | ||
119 | |||
120 | static struct platform_device scif2_device = { | ||
121 | .name = "sh-sci", | ||
122 | .id = 2, | ||
123 | .dev = { | ||
124 | .platform_data = &scif2_platform_data, | ||
125 | }, | ||
126 | }; | ||
127 | |||
128 | static struct plat_sci_port scif3_platform_data = { | ||
129 | .mapbase = 0xe6c70000, | ||
130 | .flags = UPF_BOOT_AUTOCONF, | ||
131 | .scscr = SCSCR_RE | SCSCR_TE, | ||
132 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
133 | .type = PORT_SCIFA, | ||
134 | .irqs = { gic_spi(75), gic_spi(75), | ||
135 | gic_spi(75), gic_spi(75) }, | ||
136 | }; | ||
137 | |||
138 | static struct platform_device scif3_device = { | ||
139 | .name = "sh-sci", | ||
140 | .id = 3, | ||
141 | .dev = { | ||
142 | .platform_data = &scif3_platform_data, | ||
143 | }, | ||
144 | }; | ||
145 | |||
146 | static struct plat_sci_port scif4_platform_data = { | ||
147 | .mapbase = 0xe6c80000, | ||
148 | .flags = UPF_BOOT_AUTOCONF, | ||
149 | .scscr = SCSCR_RE | SCSCR_TE, | ||
150 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
151 | .type = PORT_SCIFA, | ||
152 | .irqs = { gic_spi(78), gic_spi(78), | ||
153 | gic_spi(78), gic_spi(78) }, | ||
154 | }; | ||
155 | |||
156 | static struct platform_device scif4_device = { | ||
157 | .name = "sh-sci", | ||
158 | .id = 4, | ||
159 | .dev = { | ||
160 | .platform_data = &scif4_platform_data, | ||
161 | }, | ||
162 | }; | ||
163 | |||
164 | static struct plat_sci_port scif5_platform_data = { | ||
165 | .mapbase = 0xe6cb0000, | ||
166 | .flags = UPF_BOOT_AUTOCONF, | ||
167 | .scscr = SCSCR_RE | SCSCR_TE, | ||
168 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
169 | .type = PORT_SCIFA, | ||
170 | .irqs = { gic_spi(79), gic_spi(79), | ||
171 | gic_spi(79), gic_spi(79) }, | ||
172 | }; | ||
173 | |||
174 | static struct platform_device scif5_device = { | ||
175 | .name = "sh-sci", | ||
176 | .id = 5, | ||
177 | .dev = { | ||
178 | .platform_data = &scif5_platform_data, | ||
179 | }, | ||
180 | }; | ||
181 | |||
182 | static struct plat_sci_port scif6_platform_data = { | ||
183 | .mapbase = 0xe6cc0000, | ||
184 | .flags = UPF_BOOT_AUTOCONF, | ||
185 | .scscr = SCSCR_RE | SCSCR_TE, | ||
186 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
187 | .type = PORT_SCIFA, | ||
188 | .irqs = { gic_spi(156), gic_spi(156), | ||
189 | gic_spi(156), gic_spi(156) }, | ||
190 | }; | ||
191 | |||
192 | static struct platform_device scif6_device = { | ||
193 | .name = "sh-sci", | ||
194 | .id = 6, | ||
195 | .dev = { | ||
196 | .platform_data = &scif6_platform_data, | ||
197 | }, | ||
198 | }; | ||
199 | |||
200 | static struct plat_sci_port scif7_platform_data = { | ||
201 | .mapbase = 0xe6cd0000, | ||
202 | .flags = UPF_BOOT_AUTOCONF, | ||
203 | .scscr = SCSCR_RE | SCSCR_TE, | ||
204 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
205 | .type = PORT_SCIFA, | ||
206 | .irqs = { gic_spi(143), gic_spi(143), | ||
207 | gic_spi(143), gic_spi(143) }, | ||
208 | }; | ||
209 | |||
210 | static struct platform_device scif7_device = { | ||
211 | .name = "sh-sci", | ||
212 | .id = 7, | ||
213 | .dev = { | ||
214 | .platform_data = &scif7_platform_data, | ||
215 | }, | ||
216 | }; | ||
217 | |||
218 | static struct plat_sci_port scif8_platform_data = { | ||
219 | .mapbase = 0xe6c30000, | ||
220 | .flags = UPF_BOOT_AUTOCONF, | ||
221 | .scscr = SCSCR_RE | SCSCR_TE, | ||
222 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
223 | .type = PORT_SCIFB, | ||
224 | .irqs = { gic_spi(80), gic_spi(80), | ||
225 | gic_spi(80), gic_spi(80) }, | ||
226 | }; | ||
227 | 96 | ||
228 | static struct platform_device scif8_device = { | 97 | SH73A0_SCIF(PORT_SCIFA, 0, 0xe6c40000, gic_spi(72)); |
229 | .name = "sh-sci", | 98 | SH73A0_SCIF(PORT_SCIFA, 1, 0xe6c50000, gic_spi(73)); |
230 | .id = 8, | 99 | SH73A0_SCIF(PORT_SCIFA, 2, 0xe6c60000, gic_spi(74)); |
231 | .dev = { | 100 | SH73A0_SCIF(PORT_SCIFA, 3, 0xe6c70000, gic_spi(75)); |
232 | .platform_data = &scif8_platform_data, | 101 | SH73A0_SCIF(PORT_SCIFA, 4, 0xe6c80000, gic_spi(78)); |
233 | }, | 102 | SH73A0_SCIF(PORT_SCIFA, 5, 0xe6cb0000, gic_spi(79)); |
234 | }; | 103 | SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156)); |
104 | SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143)); | ||
105 | SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80)); | ||
235 | 106 | ||
236 | static struct sh_timer_config cmt10_platform_data = { | 107 | static struct sh_timer_config cmt10_platform_data = { |
237 | .name = "CMT10", | 108 | .name = "CMT10", |
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f58b27..00b85fd9285d 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig | |||
@@ -2,6 +2,7 @@ config ARCH_TEGRA | |||
2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 | 2 | bool "NVIDIA Tegra" if ARCH_MULTI_V7 |
3 | select ARCH_HAS_CPUFREQ | 3 | select ARCH_HAS_CPUFREQ |
4 | select ARCH_REQUIRE_GPIOLIB | 4 | select ARCH_REQUIRE_GPIOLIB |
5 | select ARCH_SUPPORTS_TRUSTED_FOUNDATIONS | ||
5 | select ARM_GIC | 6 | select ARM_GIC |
6 | select CLKSRC_MMIO | 7 | select CLKSRC_MMIO |
7 | select CLKSRC_OF | 8 | select CLKSRC_OF |
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c index d4639c506622..9a4e910c3796 100644 --- a/arch/arm/mach-tegra/fuse.c +++ b/arch/arm/mach-tegra/fuse.c | |||
@@ -209,13 +209,3 @@ void __init tegra_init_fuse(void) | |||
209 | tegra_sku_id, tegra_cpu_process_id, | 209 | tegra_sku_id, tegra_cpu_process_id, |
210 | tegra_core_process_id); | 210 | tegra_core_process_id); |
211 | } | 211 | } |
212 | |||
213 | unsigned long long tegra_chip_uid(void) | ||
214 | { | ||
215 | unsigned long long lo, hi; | ||
216 | |||
217 | lo = tegra_fuse_readl(FUSE_UID_LOW); | ||
218 | hi = tegra_fuse_readl(FUSE_UID_HIGH); | ||
219 | return (hi << 32ull) | lo; | ||
220 | } | ||
221 | EXPORT_SYMBOL(tegra_chip_uid); | ||
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 568f5bbf979d..146fe8e0ae7c 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c | |||
@@ -21,6 +21,7 @@ | |||
21 | 21 | ||
22 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
23 | #include <asm/hardware/cache-l2x0.h> | 23 | #include <asm/hardware/cache-l2x0.h> |
24 | #include <asm/firmware.h> | ||
24 | 25 | ||
25 | #include "iomap.h" | 26 | #include "iomap.h" |
26 | #include "irammap.h" | 27 | #include "irammap.h" |
@@ -33,26 +34,18 @@ | |||
33 | 34 | ||
34 | static bool is_enabled; | 35 | static bool is_enabled; |
35 | 36 | ||
36 | static void __init tegra_cpu_reset_handler_enable(void) | 37 | static void __init tegra_cpu_reset_handler_set(const u32 reset_address) |
37 | { | 38 | { |
38 | void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); | ||
39 | void __iomem *evp_cpu_reset = | 39 | void __iomem *evp_cpu_reset = |
40 | IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); | 40 | IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100); |
41 | void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); | 41 | void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE); |
42 | u32 reg; | 42 | u32 reg; |
43 | 43 | ||
44 | BUG_ON(is_enabled); | ||
45 | BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); | ||
46 | |||
47 | memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, | ||
48 | tegra_cpu_reset_handler_size); | ||
49 | |||
50 | /* | 44 | /* |
51 | * NOTE: This must be the one and only write to the EVP CPU reset | 45 | * NOTE: This must be the one and only write to the EVP CPU reset |
52 | * vector in the entire system. | 46 | * vector in the entire system. |
53 | */ | 47 | */ |
54 | writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset, | 48 | writel(reset_address, evp_cpu_reset); |
55 | evp_cpu_reset); | ||
56 | wmb(); | 49 | wmb(); |
57 | reg = readl(evp_cpu_reset); | 50 | reg = readl(evp_cpu_reset); |
58 | 51 | ||
@@ -66,8 +59,33 @@ static void __init tegra_cpu_reset_handler_enable(void) | |||
66 | writel(reg, sb_ctrl); | 59 | writel(reg, sb_ctrl); |
67 | wmb(); | 60 | wmb(); |
68 | } | 61 | } |
62 | } | ||
63 | |||
64 | static void __init tegra_cpu_reset_handler_enable(void) | ||
65 | { | ||
66 | void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE); | ||
67 | const u32 reset_address = TEGRA_IRAM_RESET_BASE + | ||
68 | tegra_cpu_reset_handler_offset; | ||
69 | int err; | ||
70 | |||
71 | BUG_ON(is_enabled); | ||
72 | BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE); | ||
69 | 73 | ||
70 | is_enabled = true; | 74 | memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start, |
75 | tegra_cpu_reset_handler_size); | ||
76 | |||
77 | err = call_firmware_op(set_cpu_boot_addr, 0, reset_address); | ||
78 | switch (err) { | ||
79 | case -ENOSYS: | ||
80 | tegra_cpu_reset_handler_set(reset_address); | ||
81 | /* pass-through */ | ||
82 | case 0: | ||
83 | is_enabled = true; | ||
84 | break; | ||
85 | default: | ||
86 | pr_crit("Cannot set CPU reset handler: %d\n", err); | ||
87 | BUG(); | ||
88 | } | ||
71 | } | 89 | } |
72 | 90 | ||
73 | void __init tegra_cpu_reset_handler_init(void) | 91 | void __init tegra_cpu_reset_handler_init(void) |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 73368176c6e8..09a1f8d98ca2 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
@@ -40,6 +40,7 @@ | |||
40 | #include <asm/mach/arch.h> | 40 | #include <asm/mach/arch.h> |
41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
42 | #include <asm/setup.h> | 42 | #include <asm/setup.h> |
43 | #include <asm/trusted_foundations.h> | ||
43 | 44 | ||
44 | #include "apbio.h" | 45 | #include "apbio.h" |
45 | #include "board.h" | 46 | #include "board.h" |
@@ -90,6 +91,7 @@ static void __init tegra_init_cache(void) | |||
90 | 91 | ||
91 | static void __init tegra_init_early(void) | 92 | static void __init tegra_init_early(void) |
92 | { | 93 | { |
94 | of_register_trusted_foundations(); | ||
93 | tegra_apb_io_init(); | 95 | tegra_apb_io_init(); |
94 | tegra_init_fuse(); | 96 | tegra_init_fuse(); |
95 | tegra_cpu_reset_handler_init(); | 97 | tegra_cpu_reset_handler_init(); |
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c index 033d34dcbd3f..c26ef5b92ca7 100644 --- a/arch/arm/mach-vexpress/spc.c +++ b/arch/arm/mach-vexpress/spc.c | |||
@@ -53,6 +53,11 @@ | |||
53 | #define A15_BX_ADDR0 0x68 | 53 | #define A15_BX_ADDR0 0x68 |
54 | #define A7_BX_ADDR0 0x78 | 54 | #define A7_BX_ADDR0 0x78 |
55 | 55 | ||
56 | /* SPC CPU/cluster reset statue */ | ||
57 | #define STANDBYWFI_STAT 0x3c | ||
58 | #define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu)) | ||
59 | #define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu))) | ||
60 | |||
56 | /* SPC system config interface registers */ | 61 | /* SPC system config interface registers */ |
57 | #define SYSCFG_WDATA 0x70 | 62 | #define SYSCFG_WDATA 0x70 |
58 | #define SYSCFG_RDATA 0x74 | 63 | #define SYSCFG_RDATA 0x74 |
@@ -213,6 +218,41 @@ void ve_spc_powerdown(u32 cluster, bool enable) | |||
213 | writel_relaxed(enable, info->baseaddr + pwdrn_reg); | 218 | writel_relaxed(enable, info->baseaddr + pwdrn_reg); |
214 | } | 219 | } |
215 | 220 | ||
221 | static u32 standbywfi_cpu_mask(u32 cpu, u32 cluster) | ||
222 | { | ||
223 | return cluster_is_a15(cluster) ? | ||
224 | STANDBYWFI_STAT_A15_CPU_MASK(cpu) | ||
225 | : STANDBYWFI_STAT_A7_CPU_MASK(cpu); | ||
226 | } | ||
227 | |||
228 | /** | ||
229 | * ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) | ||
230 | * | ||
231 | * @cpu: mpidr[7:0] bitfield describing CPU affinity level within cluster | ||
232 | * @cluster: mpidr[15:8] bitfield describing cluster affinity level | ||
233 | * | ||
234 | * @return: non-zero if and only if the specified CPU is in WFI | ||
235 | * | ||
236 | * Take care when interpreting the result of this function: a CPU might | ||
237 | * be in WFI temporarily due to idle, and is not necessarily safely | ||
238 | * parked. | ||
239 | */ | ||
240 | int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster) | ||
241 | { | ||
242 | int ret; | ||
243 | u32 mask = standbywfi_cpu_mask(cpu, cluster); | ||
244 | |||
245 | if (cluster >= MAX_CLUSTERS) | ||
246 | return 1; | ||
247 | |||
248 | ret = readl_relaxed(info->baseaddr + STANDBYWFI_STAT); | ||
249 | |||
250 | pr_debug("%s: PCFGREG[0x%X] = 0x%08X, mask = 0x%X\n", | ||
251 | __func__, STANDBYWFI_STAT, ret, mask); | ||
252 | |||
253 | return ret & mask; | ||
254 | } | ||
255 | |||
216 | static int ve_spc_get_performance(int cluster, u32 *freq) | 256 | static int ve_spc_get_performance(int cluster, u32 *freq) |
217 | { | 257 | { |
218 | struct ve_spc_opp *opps = info->opps[cluster]; | 258 | struct ve_spc_opp *opps = info->opps[cluster]; |
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h index dbd44c3720f9..793d065243b9 100644 --- a/arch/arm/mach-vexpress/spc.h +++ b/arch/arm/mach-vexpress/spc.h | |||
@@ -20,5 +20,6 @@ void ve_spc_global_wakeup_irq(bool set); | |||
20 | void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); | 20 | void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set); |
21 | void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); | 21 | void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr); |
22 | void ve_spc_powerdown(u32 cluster, bool enable); | 22 | void ve_spc_powerdown(u32 cluster, bool enable); |
23 | int ve_spc_cpu_in_wfi(u32 cpu, u32 cluster); | ||
23 | 24 | ||
24 | #endif | 25 | #endif |
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c index 05a364c5077a..29e7785a54bc 100644 --- a/arch/arm/mach-vexpress/tc2_pm.c +++ b/arch/arm/mach-vexpress/tc2_pm.c | |||
@@ -12,6 +12,7 @@ | |||
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/delay.h> | ||
15 | #include <linux/init.h> | 16 | #include <linux/init.h> |
16 | #include <linux/io.h> | 17 | #include <linux/io.h> |
17 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
@@ -32,11 +33,17 @@ | |||
32 | #include "spc.h" | 33 | #include "spc.h" |
33 | 34 | ||
34 | /* SCC conf registers */ | 35 | /* SCC conf registers */ |
36 | #define RESET_CTRL 0x018 | ||
37 | #define RESET_A15_NCORERESET(cpu) (1 << (2 + (cpu))) | ||
38 | #define RESET_A7_NCORERESET(cpu) (1 << (16 + (cpu))) | ||
39 | |||
35 | #define A15_CONF 0x400 | 40 | #define A15_CONF 0x400 |
36 | #define A7_CONF 0x500 | 41 | #define A7_CONF 0x500 |
37 | #define SYS_INFO 0x700 | 42 | #define SYS_INFO 0x700 |
38 | #define SPC_BASE 0xb00 | 43 | #define SPC_BASE 0xb00 |
39 | 44 | ||
45 | static void __iomem *scc; | ||
46 | |||
40 | /* | 47 | /* |
41 | * We can't use regular spinlocks. In the switcher case, it is possible | 48 | * We can't use regular spinlocks. In the switcher case, it is possible |
42 | * for an outbound CPU to call power_down() after its inbound counterpart | 49 | * for an outbound CPU to call power_down() after its inbound counterpart |
@@ -190,6 +197,55 @@ static void tc2_pm_power_down(void) | |||
190 | tc2_pm_down(0); | 197 | tc2_pm_down(0); |
191 | } | 198 | } |
192 | 199 | ||
200 | static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster) | ||
201 | { | ||
202 | u32 mask = cluster ? | ||
203 | RESET_A7_NCORERESET(cpu) | ||
204 | : RESET_A15_NCORERESET(cpu); | ||
205 | |||
206 | return !(readl_relaxed(scc + RESET_CTRL) & mask); | ||
207 | } | ||
208 | |||
209 | #define POLL_MSEC 10 | ||
210 | #define TIMEOUT_MSEC 1000 | ||
211 | |||
212 | static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster) | ||
213 | { | ||
214 | unsigned tries; | ||
215 | |||
216 | pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); | ||
217 | BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER); | ||
218 | |||
219 | for (tries = 0; tries < TIMEOUT_MSEC / POLL_MSEC; ++tries) { | ||
220 | /* | ||
221 | * Only examine the hardware state if the target CPU has | ||
222 | * caught up at least as far as tc2_pm_down(): | ||
223 | */ | ||
224 | if (ACCESS_ONCE(tc2_pm_use_count[cpu][cluster]) == 0) { | ||
225 | pr_debug("%s(cpu=%u, cluster=%u): RESET_CTRL = 0x%08X\n", | ||
226 | __func__, cpu, cluster, | ||
227 | readl_relaxed(scc + RESET_CTRL)); | ||
228 | |||
229 | /* | ||
230 | * We need the CPU to reach WFI, but the power | ||
231 | * controller may put the cluster in reset and | ||
232 | * power it off as soon as that happens, before | ||
233 | * we have a chance to see STANDBYWFI. | ||
234 | * | ||
235 | * So we need to check for both conditions: | ||
236 | */ | ||
237 | if (tc2_core_in_reset(cpu, cluster) || | ||
238 | ve_spc_cpu_in_wfi(cpu, cluster)) | ||
239 | return 0; /* success: the CPU is halted */ | ||
240 | } | ||
241 | |||
242 | /* Otherwise, wait and retry: */ | ||
243 | msleep(POLL_MSEC); | ||
244 | } | ||
245 | |||
246 | return -ETIMEDOUT; /* timeout */ | ||
247 | } | ||
248 | |||
193 | static void tc2_pm_suspend(u64 residency) | 249 | static void tc2_pm_suspend(u64 residency) |
194 | { | 250 | { |
195 | unsigned int mpidr, cpu, cluster; | 251 | unsigned int mpidr, cpu, cluster; |
@@ -232,10 +288,11 @@ static void tc2_pm_powered_up(void) | |||
232 | } | 288 | } |
233 | 289 | ||
234 | static const struct mcpm_platform_ops tc2_pm_power_ops = { | 290 | static const struct mcpm_platform_ops tc2_pm_power_ops = { |
235 | .power_up = tc2_pm_power_up, | 291 | .power_up = tc2_pm_power_up, |
236 | .power_down = tc2_pm_power_down, | 292 | .power_down = tc2_pm_power_down, |
237 | .suspend = tc2_pm_suspend, | 293 | .power_down_finish = tc2_pm_power_down_finish, |
238 | .powered_up = tc2_pm_powered_up, | 294 | .suspend = tc2_pm_suspend, |
295 | .powered_up = tc2_pm_powered_up, | ||
239 | }; | 296 | }; |
240 | 297 | ||
241 | static bool __init tc2_pm_usage_count_init(void) | 298 | static bool __init tc2_pm_usage_count_init(void) |
@@ -269,7 +326,6 @@ static void __naked tc2_pm_power_up_setup(unsigned int affinity_level) | |||
269 | static int __init tc2_pm_init(void) | 326 | static int __init tc2_pm_init(void) |
270 | { | 327 | { |
271 | int ret, irq; | 328 | int ret, irq; |
272 | void __iomem *scc; | ||
273 | u32 a15_cluster_id, a7_cluster_id, sys_info; | 329 | u32 a15_cluster_id, a7_cluster_id, sys_info; |
274 | struct device_node *np; | 330 | struct device_node *np; |
275 | 331 | ||
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c index 99a3590f0349..ac07e871f6a7 100644 --- a/arch/arm/plat-samsung/devs.c +++ b/arch/arm/plat-samsung/devs.c | |||
@@ -1468,6 +1468,8 @@ void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
1468 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; | 1468 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio; |
1469 | #if defined(CONFIG_PL330_DMA) | 1469 | #if defined(CONFIG_PL330_DMA) |
1470 | pd.filter = pl330_filter; | 1470 | pd.filter = pl330_filter; |
1471 | #elif defined(CONFIG_S3C64XX_PL080) | ||
1472 | pd.filter = pl08x_filter_id; | ||
1471 | #elif defined(CONFIG_S3C24XX_DMAC) | 1473 | #elif defined(CONFIG_S3C24XX_DMAC) |
1472 | pd.filter = s3c24xx_dma_filter; | 1474 | pd.filter = s3c24xx_dma_filter; |
1473 | #endif | 1475 | #endif |
@@ -1509,8 +1511,10 @@ void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
1509 | pd.num_cs = num_cs; | 1511 | pd.num_cs = num_cs; |
1510 | pd.src_clk_nr = src_clk_nr; | 1512 | pd.src_clk_nr = src_clk_nr; |
1511 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; | 1513 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio; |
1512 | #ifdef CONFIG_PL330_DMA | 1514 | #if defined(CONFIG_PL330_DMA) |
1513 | pd.filter = pl330_filter; | 1515 | pd.filter = pl330_filter; |
1516 | #elif defined(CONFIG_S3C64XX_PL080) | ||
1517 | pd.filter = pl08x_filter_id; | ||
1514 | #endif | 1518 | #endif |
1515 | 1519 | ||
1516 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); | 1520 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1); |
@@ -1550,8 +1554,10 @@ void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr, | |||
1550 | pd.num_cs = num_cs; | 1554 | pd.num_cs = num_cs; |
1551 | pd.src_clk_nr = src_clk_nr; | 1555 | pd.src_clk_nr = src_clk_nr; |
1552 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; | 1556 | pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio; |
1553 | #ifdef CONFIG_PL330_DMA | 1557 | #if defined(CONFIG_PL330_DMA) |
1554 | pd.filter = pl330_filter; | 1558 | pd.filter = pl330_filter; |
1559 | #elif defined(CONFIG_S3C64XX_PL080) | ||
1560 | pd.filter = pl08x_filter_id; | ||
1555 | #endif | 1561 | #endif |
1556 | 1562 | ||
1557 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); | 1563 | s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2); |
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c index ec0d731b0e7b..886326ee6f6c 100644 --- a/arch/arm/plat-samsung/dma-ops.c +++ b/arch/arm/plat-samsung/dma-ops.c | |||
@@ -18,6 +18,12 @@ | |||
18 | 18 | ||
19 | #include <mach/dma.h> | 19 | #include <mach/dma.h> |
20 | 20 | ||
21 | #if defined(CONFIG_PL330_DMA) | ||
22 | #define dma_filter pl330_filter | ||
23 | #elif defined(CONFIG_S3C64XX_PL080) | ||
24 | #define dma_filter pl08x_filter_id | ||
25 | #endif | ||
26 | |||
21 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | 27 | static unsigned samsung_dmadev_request(enum dma_ch dma_ch, |
22 | struct samsung_dma_req *param, | 28 | struct samsung_dma_req *param, |
23 | struct device *dev, char *ch_name) | 29 | struct device *dev, char *ch_name) |
@@ -30,7 +36,7 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch, | |||
30 | if (dev->of_node) | 36 | if (dev->of_node) |
31 | return (unsigned)dma_request_slave_channel(dev, ch_name); | 37 | return (unsigned)dma_request_slave_channel(dev, ch_name); |
32 | else | 38 | else |
33 | return (unsigned)dma_request_channel(mask, pl330_filter, | 39 | return (unsigned)dma_request_channel(mask, dma_filter, |
34 | (void *)dma_ch); | 40 | (void *)dma_ch); |
35 | } | 41 | } |
36 | 42 | ||
diff --git a/arch/arm64/boot/dts/foundation-v8.dts b/arch/arm64/boot/dts/foundation-v8.dts index 84fcc5018284..519c4b2c0687 100644 --- a/arch/arm64/boot/dts/foundation-v8.dts +++ b/arch/arm64/boot/dts/foundation-v8.dts | |||
@@ -6,6 +6,8 @@ | |||
6 | 6 | ||
7 | /dts-v1/; | 7 | /dts-v1/; |
8 | 8 | ||
9 | /memreserve/ 0x80000000 0x00010000; | ||
10 | |||
9 | / { | 11 | / { |
10 | model = "Foundation-v8A"; | 12 | model = "Foundation-v8A"; |
11 | compatible = "arm,foundation-aarch64", "arm,vexpress"; | 13 | compatible = "arm,foundation-aarch64", "arm,vexpress"; |
diff --git a/arch/arm64/include/asm/irqflags.h b/arch/arm64/include/asm/irqflags.h index aa11943b8502..b2fcfbc51ecc 100644 --- a/arch/arm64/include/asm/irqflags.h +++ b/arch/arm64/include/asm/irqflags.h | |||
@@ -56,6 +56,9 @@ static inline void arch_local_irq_disable(void) | |||
56 | #define local_fiq_enable() asm("msr daifclr, #1" : : : "memory") | 56 | #define local_fiq_enable() asm("msr daifclr, #1" : : : "memory") |
57 | #define local_fiq_disable() asm("msr daifset, #1" : : : "memory") | 57 | #define local_fiq_disable() asm("msr daifset, #1" : : : "memory") |
58 | 58 | ||
59 | #define local_async_enable() asm("msr daifclr, #4" : : : "memory") | ||
60 | #define local_async_disable() asm("msr daifset, #4" : : : "memory") | ||
61 | |||
59 | /* | 62 | /* |
60 | * Save the current interrupt enable state. | 63 | * Save the current interrupt enable state. |
61 | */ | 64 | */ |
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 17bd3af0a117..7f2b60affbb4 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h | |||
@@ -25,10 +25,11 @@ | |||
25 | * Software defined PTE bits definition. | 25 | * Software defined PTE bits definition. |
26 | */ | 26 | */ |
27 | #define PTE_VALID (_AT(pteval_t, 1) << 0) | 27 | #define PTE_VALID (_AT(pteval_t, 1) << 0) |
28 | #define PTE_PROT_NONE (_AT(pteval_t, 1) << 2) /* only when !PTE_VALID */ | 28 | #define PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !pte_present() */ |
29 | #define PTE_FILE (_AT(pteval_t, 1) << 3) /* only when !pte_present() */ | ||
30 | #define PTE_DIRTY (_AT(pteval_t, 1) << 55) | 29 | #define PTE_DIRTY (_AT(pteval_t, 1) << 55) |
31 | #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) | 30 | #define PTE_SPECIAL (_AT(pteval_t, 1) << 56) |
31 | /* bit 57 for PMD_SECT_SPLITTING */ | ||
32 | #define PTE_PROT_NONE (_AT(pteval_t, 1) << 58) /* only when !PTE_VALID */ | ||
32 | 33 | ||
33 | /* | 34 | /* |
34 | * VMALLOC and SPARSEMEM_VMEMMAP ranges. | 35 | * VMALLOC and SPARSEMEM_VMEMMAP ranges. |
@@ -254,7 +255,7 @@ static inline int has_transparent_hugepage(void) | |||
254 | #define pgprot_noncached(prot) \ | 255 | #define pgprot_noncached(prot) \ |
255 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE)) | 256 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE)) |
256 | #define pgprot_writecombine(prot) \ | 257 | #define pgprot_writecombine(prot) \ |
257 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_GRE)) | 258 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) |
258 | #define pgprot_dmacoherent(prot) \ | 259 | #define pgprot_dmacoherent(prot) \ |
259 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) | 260 | __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)) |
260 | #define __HAVE_PHYS_MEM_ACCESS_PROT | 261 | #define __HAVE_PHYS_MEM_ACCESS_PROT |
@@ -357,18 +358,20 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |||
357 | 358 | ||
358 | /* | 359 | /* |
359 | * Encode and decode a swap entry: | 360 | * Encode and decode a swap entry: |
360 | * bits 0, 2: present (must both be zero) | 361 | * bits 0-1: present (must be zero) |
361 | * bit 3: PTE_FILE | 362 | * bit 2: PTE_FILE |
362 | * bits 4-8: swap type | 363 | * bits 3-8: swap type |
363 | * bits 9-63: swap offset | 364 | * bits 9-57: swap offset |
364 | */ | 365 | */ |
365 | #define __SWP_TYPE_SHIFT 4 | 366 | #define __SWP_TYPE_SHIFT 3 |
366 | #define __SWP_TYPE_BITS 6 | 367 | #define __SWP_TYPE_BITS 6 |
368 | #define __SWP_OFFSET_BITS 49 | ||
367 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) | 369 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
368 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | 370 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) |
371 | #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1) | ||
369 | 372 | ||
370 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) | 373 | #define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK) |
371 | #define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT) | 374 | #define __swp_offset(x) (((x).val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK) |
372 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) | 375 | #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) }) |
373 | 376 | ||
374 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | 377 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) |
@@ -382,15 +385,15 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; | |||
382 | 385 | ||
383 | /* | 386 | /* |
384 | * Encode and decode a file entry: | 387 | * Encode and decode a file entry: |
385 | * bits 0, 2: present (must both be zero) | 388 | * bits 0-1: present (must be zero) |
386 | * bit 3: PTE_FILE | 389 | * bit 2: PTE_FILE |
387 | * bits 4-63: file offset / PAGE_SIZE | 390 | * bits 3-57: file offset / PAGE_SIZE |
388 | */ | 391 | */ |
389 | #define pte_file(pte) (pte_val(pte) & PTE_FILE) | 392 | #define pte_file(pte) (pte_val(pte) & PTE_FILE) |
390 | #define pte_to_pgoff(x) (pte_val(x) >> 4) | 393 | #define pte_to_pgoff(x) (pte_val(x) >> 3) |
391 | #define pgoff_to_pte(x) __pte(((x) << 4) | PTE_FILE) | 394 | #define pgoff_to_pte(x) __pte(((x) << 3) | PTE_FILE) |
392 | 395 | ||
393 | #define PTE_FILE_MAX_BITS 60 | 396 | #define PTE_FILE_MAX_BITS 55 |
394 | 397 | ||
395 | extern int kern_addr_valid(unsigned long addr); | 398 | extern int kern_addr_valid(unsigned long addr); |
396 | 399 | ||
diff --git a/arch/arm64/kernel/debug-monitors.c b/arch/arm64/kernel/debug-monitors.c index 6a0a9b132d7a..4ae68579031d 100644 --- a/arch/arm64/kernel/debug-monitors.c +++ b/arch/arm64/kernel/debug-monitors.c | |||
@@ -248,7 +248,8 @@ static int brk_handler(unsigned long addr, unsigned int esr, | |||
248 | int aarch32_break_handler(struct pt_regs *regs) | 248 | int aarch32_break_handler(struct pt_regs *regs) |
249 | { | 249 | { |
250 | siginfo_t info; | 250 | siginfo_t info; |
251 | unsigned int instr; | 251 | u32 arm_instr; |
252 | u16 thumb_instr; | ||
252 | bool bp = false; | 253 | bool bp = false; |
253 | void __user *pc = (void __user *)instruction_pointer(regs); | 254 | void __user *pc = (void __user *)instruction_pointer(regs); |
254 | 255 | ||
@@ -257,18 +258,21 @@ int aarch32_break_handler(struct pt_regs *regs) | |||
257 | 258 | ||
258 | if (compat_thumb_mode(regs)) { | 259 | if (compat_thumb_mode(regs)) { |
259 | /* get 16-bit Thumb instruction */ | 260 | /* get 16-bit Thumb instruction */ |
260 | get_user(instr, (u16 __user *)pc); | 261 | get_user(thumb_instr, (u16 __user *)pc); |
261 | if (instr == AARCH32_BREAK_THUMB2_LO) { | 262 | thumb_instr = le16_to_cpu(thumb_instr); |
263 | if (thumb_instr == AARCH32_BREAK_THUMB2_LO) { | ||
262 | /* get second half of 32-bit Thumb-2 instruction */ | 264 | /* get second half of 32-bit Thumb-2 instruction */ |
263 | get_user(instr, (u16 __user *)(pc + 2)); | 265 | get_user(thumb_instr, (u16 __user *)(pc + 2)); |
264 | bp = instr == AARCH32_BREAK_THUMB2_HI; | 266 | thumb_instr = le16_to_cpu(thumb_instr); |
267 | bp = thumb_instr == AARCH32_BREAK_THUMB2_HI; | ||
265 | } else { | 268 | } else { |
266 | bp = instr == AARCH32_BREAK_THUMB; | 269 | bp = thumb_instr == AARCH32_BREAK_THUMB; |
267 | } | 270 | } |
268 | } else { | 271 | } else { |
269 | /* 32-bit ARM instruction */ | 272 | /* 32-bit ARM instruction */ |
270 | get_user(instr, (u32 __user *)pc); | 273 | get_user(arm_instr, (u32 __user *)pc); |
271 | bp = (instr & ~0xf0000000) == AARCH32_BREAK_ARM; | 274 | arm_instr = le32_to_cpu(arm_instr); |
275 | bp = (arm_instr & ~0xf0000000) == AARCH32_BREAK_ARM; | ||
272 | } | 276 | } |
273 | 277 | ||
274 | if (!bp) | 278 | if (!bp) |
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e1166145ca29..4d2c6f3f0c41 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S | |||
@@ -309,15 +309,12 @@ el1_irq: | |||
309 | #ifdef CONFIG_TRACE_IRQFLAGS | 309 | #ifdef CONFIG_TRACE_IRQFLAGS |
310 | bl trace_hardirqs_off | 310 | bl trace_hardirqs_off |
311 | #endif | 311 | #endif |
312 | #ifdef CONFIG_PREEMPT | 312 | |
313 | get_thread_info tsk | ||
314 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count | ||
315 | add w0, w24, #1 // increment it | ||
316 | str w0, [tsk, #TI_PREEMPT] | ||
317 | #endif | ||
318 | irq_handler | 313 | irq_handler |
314 | |||
319 | #ifdef CONFIG_PREEMPT | 315 | #ifdef CONFIG_PREEMPT |
320 | str w24, [tsk, #TI_PREEMPT] // restore preempt count | 316 | get_thread_info tsk |
317 | ldr w24, [tsk, #TI_PREEMPT] // restore preempt count | ||
321 | cbnz w24, 1f // preempt count != 0 | 318 | cbnz w24, 1f // preempt count != 0 |
322 | ldr x0, [tsk, #TI_FLAGS] // get flags | 319 | ldr x0, [tsk, #TI_FLAGS] // get flags |
323 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? | 320 | tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling? |
@@ -507,22 +504,10 @@ el0_irq_naked: | |||
507 | #ifdef CONFIG_TRACE_IRQFLAGS | 504 | #ifdef CONFIG_TRACE_IRQFLAGS |
508 | bl trace_hardirqs_off | 505 | bl trace_hardirqs_off |
509 | #endif | 506 | #endif |
510 | get_thread_info tsk | 507 | |
511 | #ifdef CONFIG_PREEMPT | ||
512 | ldr w24, [tsk, #TI_PREEMPT] // get preempt count | ||
513 | add w23, w24, #1 // increment it | ||
514 | str w23, [tsk, #TI_PREEMPT] | ||
515 | #endif | ||
516 | irq_handler | 508 | irq_handler |
517 | #ifdef CONFIG_PREEMPT | 509 | get_thread_info tsk |
518 | ldr w0, [tsk, #TI_PREEMPT] | 510 | |
519 | str w24, [tsk, #TI_PREEMPT] | ||
520 | cmp w0, w23 | ||
521 | b.eq 1f | ||
522 | mov x1, #0 | ||
523 | str x1, [x1] // BUG | ||
524 | 1: | ||
525 | #endif | ||
526 | #ifdef CONFIG_TRACE_IRQFLAGS | 511 | #ifdef CONFIG_TRACE_IRQFLAGS |
527 | bl trace_hardirqs_on | 512 | bl trace_hardirqs_on |
528 | #endif | 513 | #endif |
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index fecdbf7de82e..6777a2192b83 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c | |||
@@ -636,28 +636,27 @@ static int compat_gpr_get(struct task_struct *target, | |||
636 | 636 | ||
637 | for (i = 0; i < num_regs; ++i) { | 637 | for (i = 0; i < num_regs; ++i) { |
638 | unsigned int idx = start + i; | 638 | unsigned int idx = start + i; |
639 | void *reg; | 639 | compat_ulong_t reg; |
640 | 640 | ||
641 | switch (idx) { | 641 | switch (idx) { |
642 | case 15: | 642 | case 15: |
643 | reg = (void *)&task_pt_regs(target)->pc; | 643 | reg = task_pt_regs(target)->pc; |
644 | break; | 644 | break; |
645 | case 16: | 645 | case 16: |
646 | reg = (void *)&task_pt_regs(target)->pstate; | 646 | reg = task_pt_regs(target)->pstate; |
647 | break; | 647 | break; |
648 | case 17: | 648 | case 17: |
649 | reg = (void *)&task_pt_regs(target)->orig_x0; | 649 | reg = task_pt_regs(target)->orig_x0; |
650 | break; | 650 | break; |
651 | default: | 651 | default: |
652 | reg = (void *)&task_pt_regs(target)->regs[idx]; | 652 | reg = task_pt_regs(target)->regs[idx]; |
653 | } | 653 | } |
654 | 654 | ||
655 | ret = copy_to_user(ubuf, reg, sizeof(compat_ulong_t)); | 655 | ret = copy_to_user(ubuf, ®, sizeof(reg)); |
656 | |||
657 | if (ret) | 656 | if (ret) |
658 | break; | 657 | break; |
659 | else | 658 | |
660 | ubuf += sizeof(compat_ulong_t); | 659 | ubuf += sizeof(reg); |
661 | } | 660 | } |
662 | 661 | ||
663 | return ret; | 662 | return ret; |
@@ -685,28 +684,28 @@ static int compat_gpr_set(struct task_struct *target, | |||
685 | 684 | ||
686 | for (i = 0; i < num_regs; ++i) { | 685 | for (i = 0; i < num_regs; ++i) { |
687 | unsigned int idx = start + i; | 686 | unsigned int idx = start + i; |
688 | void *reg; | 687 | compat_ulong_t reg; |
688 | |||
689 | ret = copy_from_user(®, ubuf, sizeof(reg)); | ||
690 | if (ret) | ||
691 | return ret; | ||
692 | |||
693 | ubuf += sizeof(reg); | ||
689 | 694 | ||
690 | switch (idx) { | 695 | switch (idx) { |
691 | case 15: | 696 | case 15: |
692 | reg = (void *)&newregs.pc; | 697 | newregs.pc = reg; |
693 | break; | 698 | break; |
694 | case 16: | 699 | case 16: |
695 | reg = (void *)&newregs.pstate; | 700 | newregs.pstate = reg; |
696 | break; | 701 | break; |
697 | case 17: | 702 | case 17: |
698 | reg = (void *)&newregs.orig_x0; | 703 | newregs.orig_x0 = reg; |
699 | break; | 704 | break; |
700 | default: | 705 | default: |
701 | reg = (void *)&newregs.regs[idx]; | 706 | newregs.regs[idx] = reg; |
702 | } | 707 | } |
703 | 708 | ||
704 | ret = copy_from_user(reg, ubuf, sizeof(compat_ulong_t)); | ||
705 | |||
706 | if (ret) | ||
707 | goto out; | ||
708 | else | ||
709 | ubuf += sizeof(compat_ulong_t); | ||
710 | } | 709 | } |
711 | 710 | ||
712 | if (valid_user_regs(&newregs.user_regs)) | 711 | if (valid_user_regs(&newregs.user_regs)) |
@@ -714,7 +713,6 @@ static int compat_gpr_set(struct task_struct *target, | |||
714 | else | 713 | else |
715 | ret = -EINVAL; | 714 | ret = -EINVAL; |
716 | 715 | ||
717 | out: | ||
718 | return ret; | 716 | return ret; |
719 | } | 717 | } |
720 | 718 | ||
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index 0bc5e4cbc017..bd9bbd0e44ed 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c | |||
@@ -205,6 +205,11 @@ u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID }; | |||
205 | 205 | ||
206 | void __init setup_arch(char **cmdline_p) | 206 | void __init setup_arch(char **cmdline_p) |
207 | { | 207 | { |
208 | /* | ||
209 | * Unmask asynchronous aborts early to catch possible system errors. | ||
210 | */ | ||
211 | local_async_enable(); | ||
212 | |||
208 | setup_processor(); | 213 | setup_processor(); |
209 | 214 | ||
210 | setup_machine_fdt(__fdt_pointer); | 215 | setup_machine_fdt(__fdt_pointer); |
diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index a5aeefab03c3..a0c2ca602cf8 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c | |||
@@ -160,6 +160,7 @@ asmlinkage void secondary_start_kernel(void) | |||
160 | 160 | ||
161 | local_irq_enable(); | 161 | local_irq_enable(); |
162 | local_fiq_enable(); | 162 | local_fiq_enable(); |
163 | local_async_enable(); | ||
163 | 164 | ||
164 | /* | 165 | /* |
165 | * OK, it's off to the idle thread for us | 166 | * OK, it's off to the idle thread for us |
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile index 8a2463670a5b..0f4344e6fbca 100644 --- a/arch/powerpc/Makefile +++ b/arch/powerpc/Makefile | |||
@@ -75,8 +75,10 @@ LDEMULATION := lppc | |||
75 | GNUTARGET := powerpcle | 75 | GNUTARGET := powerpcle |
76 | MULTIPLEWORD := -mno-multiple | 76 | MULTIPLEWORD := -mno-multiple |
77 | else | 77 | else |
78 | ifeq ($(call cc-option-yn,-mbig-endian),y) | ||
78 | override CC += -mbig-endian | 79 | override CC += -mbig-endian |
79 | override AS += -mbig-endian | 80 | override AS += -mbig-endian |
81 | endif | ||
80 | override LD += -EB | 82 | override LD += -EB |
81 | LDEMULATION := ppc | 83 | LDEMULATION := ppc |
82 | GNUTARGET := powerpc | 84 | GNUTARGET := powerpc |
@@ -128,7 +130,12 @@ CFLAGS-$(CONFIG_POWER5_CPU) += $(call cc-option,-mcpu=power5) | |||
128 | CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6) | 130 | CFLAGS-$(CONFIG_POWER6_CPU) += $(call cc-option,-mcpu=power6) |
129 | CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7) | 131 | CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7) |
130 | 132 | ||
133 | # Altivec option not allowed with e500mc64 in GCC. | ||
134 | ifeq ($(CONFIG_ALTIVEC),y) | ||
135 | E5500_CPU := -mcpu=powerpc64 | ||
136 | else | ||
131 | E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64) | 137 | E5500_CPU := $(call cc-option,-mcpu=e500mc64,-mcpu=powerpc64) |
138 | endif | ||
132 | CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU) | 139 | CFLAGS-$(CONFIG_E5500_CPU) += $(E5500_CPU) |
133 | CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU)) | 140 | CFLAGS-$(CONFIG_E6500_CPU) += $(call cc-option,-mcpu=e6500,$(E5500_CPU)) |
134 | 141 | ||
diff --git a/arch/powerpc/boot/dts/xcalibur1501.dts b/arch/powerpc/boot/dts/xcalibur1501.dts index cc00f4ddd9a7..c409cbafb126 100644 --- a/arch/powerpc/boot/dts/xcalibur1501.dts +++ b/arch/powerpc/boot/dts/xcalibur1501.dts | |||
@@ -637,14 +637,14 @@ | |||
637 | tlu@2f000 { | 637 | tlu@2f000 { |
638 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 638 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
639 | reg = <0x2f000 0x1000>; | 639 | reg = <0x2f000 0x1000>; |
640 | interupts = <61 2 >; | 640 | interrupts = <61 2>; |
641 | interrupt-parent = <&mpic>; | 641 | interrupt-parent = <&mpic>; |
642 | }; | 642 | }; |
643 | 643 | ||
644 | tlu@15000 { | 644 | tlu@15000 { |
645 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 645 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
646 | reg = <0x15000 0x1000>; | 646 | reg = <0x15000 0x1000>; |
647 | interupts = <75 2>; | 647 | interrupts = <75 2>; |
648 | interrupt-parent = <&mpic>; | 648 | interrupt-parent = <&mpic>; |
649 | }; | 649 | }; |
650 | }; | 650 | }; |
diff --git a/arch/powerpc/boot/dts/xpedite5301.dts b/arch/powerpc/boot/dts/xpedite5301.dts index 53c1c6a9752f..04cb410da48b 100644 --- a/arch/powerpc/boot/dts/xpedite5301.dts +++ b/arch/powerpc/boot/dts/xpedite5301.dts | |||
@@ -547,14 +547,14 @@ | |||
547 | tlu@2f000 { | 547 | tlu@2f000 { |
548 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 548 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
549 | reg = <0x2f000 0x1000>; | 549 | reg = <0x2f000 0x1000>; |
550 | interupts = <61 2 >; | 550 | interrupts = <61 2>; |
551 | interrupt-parent = <&mpic>; | 551 | interrupt-parent = <&mpic>; |
552 | }; | 552 | }; |
553 | 553 | ||
554 | tlu@15000 { | 554 | tlu@15000 { |
555 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 555 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
556 | reg = <0x15000 0x1000>; | 556 | reg = <0x15000 0x1000>; |
557 | interupts = <75 2>; | 557 | interrupts = <75 2>; |
558 | interrupt-parent = <&mpic>; | 558 | interrupt-parent = <&mpic>; |
559 | }; | 559 | }; |
560 | }; | 560 | }; |
diff --git a/arch/powerpc/boot/dts/xpedite5330.dts b/arch/powerpc/boot/dts/xpedite5330.dts index 215225983150..73f8620f1ce7 100644 --- a/arch/powerpc/boot/dts/xpedite5330.dts +++ b/arch/powerpc/boot/dts/xpedite5330.dts | |||
@@ -583,14 +583,14 @@ | |||
583 | tlu@2f000 { | 583 | tlu@2f000 { |
584 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 584 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
585 | reg = <0x2f000 0x1000>; | 585 | reg = <0x2f000 0x1000>; |
586 | interupts = <61 2 >; | 586 | interrupts = <61 2>; |
587 | interrupt-parent = <&mpic>; | 587 | interrupt-parent = <&mpic>; |
588 | }; | 588 | }; |
589 | 589 | ||
590 | tlu@15000 { | 590 | tlu@15000 { |
591 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 591 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
592 | reg = <0x15000 0x1000>; | 592 | reg = <0x15000 0x1000>; |
593 | interupts = <75 2>; | 593 | interrupts = <75 2>; |
594 | interrupt-parent = <&mpic>; | 594 | interrupt-parent = <&mpic>; |
595 | }; | 595 | }; |
596 | }; | 596 | }; |
diff --git a/arch/powerpc/boot/dts/xpedite5370.dts b/arch/powerpc/boot/dts/xpedite5370.dts index 11dbda10d756..cd0ea2b99362 100644 --- a/arch/powerpc/boot/dts/xpedite5370.dts +++ b/arch/powerpc/boot/dts/xpedite5370.dts | |||
@@ -545,14 +545,14 @@ | |||
545 | tlu@2f000 { | 545 | tlu@2f000 { |
546 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 546 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
547 | reg = <0x2f000 0x1000>; | 547 | reg = <0x2f000 0x1000>; |
548 | interupts = <61 2 >; | 548 | interrupts = <61 2>; |
549 | interrupt-parent = <&mpic>; | 549 | interrupt-parent = <&mpic>; |
550 | }; | 550 | }; |
551 | 551 | ||
552 | tlu@15000 { | 552 | tlu@15000 { |
553 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; | 553 | compatible = "fsl,mpc8572-tlu", "fsl_tlu"; |
554 | reg = <0x15000 0x1000>; | 554 | reg = <0x15000 0x1000>; |
555 | interupts = <75 2>; | 555 | interrupts = <75 2>; |
556 | interrupt-parent = <&mpic>; | 556 | interrupt-parent = <&mpic>; |
557 | }; | 557 | }; |
558 | }; | 558 | }; |
diff --git a/arch/powerpc/boot/util.S b/arch/powerpc/boot/util.S index 5143228e3e5f..6636b1d7821b 100644 --- a/arch/powerpc/boot/util.S +++ b/arch/powerpc/boot/util.S | |||
@@ -71,18 +71,32 @@ udelay: | |||
71 | add r4,r4,r5 | 71 | add r4,r4,r5 |
72 | addi r4,r4,-1 | 72 | addi r4,r4,-1 |
73 | divw r4,r4,r5 /* BUS ticks */ | 73 | divw r4,r4,r5 /* BUS ticks */ |
74 | #ifdef CONFIG_8xx | ||
75 | 1: mftbu r5 | ||
76 | mftb r6 | ||
77 | mftbu r7 | ||
78 | #else | ||
74 | 1: mfspr r5, SPRN_TBRU | 79 | 1: mfspr r5, SPRN_TBRU |
75 | mfspr r6, SPRN_TBRL | 80 | mfspr r6, SPRN_TBRL |
76 | mfspr r7, SPRN_TBRU | 81 | mfspr r7, SPRN_TBRU |
82 | #endif | ||
77 | cmpw 0,r5,r7 | 83 | cmpw 0,r5,r7 |
78 | bne 1b /* Get [synced] base time */ | 84 | bne 1b /* Get [synced] base time */ |
79 | addc r9,r6,r4 /* Compute end time */ | 85 | addc r9,r6,r4 /* Compute end time */ |
80 | addze r8,r5 | 86 | addze r8,r5 |
87 | #ifdef CONFIG_8xx | ||
88 | 2: mftbu r5 | ||
89 | #else | ||
81 | 2: mfspr r5, SPRN_TBRU | 90 | 2: mfspr r5, SPRN_TBRU |
91 | #endif | ||
82 | cmpw 0,r5,r8 | 92 | cmpw 0,r5,r8 |
83 | blt 2b | 93 | blt 2b |
84 | bgt 3f | 94 | bgt 3f |
95 | #ifdef CONFIG_8xx | ||
96 | mftb r6 | ||
97 | #else | ||
85 | mfspr r6, SPRN_TBRL | 98 | mfspr r6, SPRN_TBRL |
99 | #endif | ||
86 | cmpw 0,r6,r9 | 100 | cmpw 0,r6,r9 |
87 | blt 2b | 101 | blt 2b |
88 | 3: blr | 102 | 3: blr |
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h index 16cb92d215d2..694012877bf7 100644 --- a/arch/powerpc/include/asm/pgalloc-64.h +++ b/arch/powerpc/include/asm/pgalloc-64.h | |||
@@ -16,6 +16,7 @@ struct vmemmap_backing { | |||
16 | unsigned long phys; | 16 | unsigned long phys; |
17 | unsigned long virt_addr; | 17 | unsigned long virt_addr; |
18 | }; | 18 | }; |
19 | extern struct vmemmap_backing *vmemmap_list; | ||
19 | 20 | ||
20 | /* | 21 | /* |
21 | * Functions that deal with pagetables that could be at any level of | 22 | * Functions that deal with pagetables that could be at any level of |
diff --git a/arch/powerpc/include/asm/ppc_asm.h b/arch/powerpc/include/asm/ppc_asm.h index 3c1acc31a092..f595b98079ee 100644 --- a/arch/powerpc/include/asm/ppc_asm.h +++ b/arch/powerpc/include/asm/ppc_asm.h | |||
@@ -366,6 +366,8 @@ BEGIN_FTR_SECTION_NESTED(96); \ | |||
366 | cmpwi dest,0; \ | 366 | cmpwi dest,0; \ |
367 | beq- 90b; \ | 367 | beq- 90b; \ |
368 | END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) | 368 | END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96) |
369 | #elif defined(CONFIG_8xx) | ||
370 | #define MFTB(dest) mftb dest | ||
369 | #else | 371 | #else |
370 | #define MFTB(dest) mfspr dest, SPRN_TBRL | 372 | #define MFTB(dest) mfspr dest, SPRN_TBRL |
371 | #endif | 373 | #endif |
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 5c45787d551e..fa8388ed94c5 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -1174,12 +1174,19 @@ | |||
1174 | 1174 | ||
1175 | #else /* __powerpc64__ */ | 1175 | #else /* __powerpc64__ */ |
1176 | 1176 | ||
1177 | #if defined(CONFIG_8xx) | ||
1178 | #define mftbl() ({unsigned long rval; \ | ||
1179 | asm volatile("mftbl %0" : "=r" (rval)); rval;}) | ||
1180 | #define mftbu() ({unsigned long rval; \ | ||
1181 | asm volatile("mftbu %0" : "=r" (rval)); rval;}) | ||
1182 | #else | ||
1177 | #define mftbl() ({unsigned long rval; \ | 1183 | #define mftbl() ({unsigned long rval; \ |
1178 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ | 1184 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1179 | "i" (SPRN_TBRL)); rval;}) | 1185 | "i" (SPRN_TBRL)); rval;}) |
1180 | #define mftbu() ({unsigned long rval; \ | 1186 | #define mftbu() ({unsigned long rval; \ |
1181 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ | 1187 | asm volatile("mfspr %0, %1" : "=r" (rval) : \ |
1182 | "i" (SPRN_TBRU)); rval;}) | 1188 | "i" (SPRN_TBRU)); rval;}) |
1189 | #endif | ||
1183 | #endif /* !__powerpc64__ */ | 1190 | #endif /* !__powerpc64__ */ |
1184 | 1191 | ||
1185 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) | 1192 | #define mttbl(v) asm volatile("mttbl %0":: "r"(v)) |
diff --git a/arch/powerpc/include/asm/timex.h b/arch/powerpc/include/asm/timex.h index 18908caa1f3b..2cf846edb3fc 100644 --- a/arch/powerpc/include/asm/timex.h +++ b/arch/powerpc/include/asm/timex.h | |||
@@ -29,7 +29,11 @@ static inline cycles_t get_cycles(void) | |||
29 | ret = 0; | 29 | ret = 0; |
30 | 30 | ||
31 | __asm__ __volatile__( | 31 | __asm__ __volatile__( |
32 | #ifdef CONFIG_8xx | ||
33 | "97: mftb %0\n" | ||
34 | #else | ||
32 | "97: mfspr %0, %2\n" | 35 | "97: mfspr %0, %2\n" |
36 | #endif | ||
33 | "99:\n" | 37 | "99:\n" |
34 | ".section __ftr_fixup,\"a\"\n" | 38 | ".section __ftr_fixup,\"a\"\n" |
35 | ".align 2\n" | 39 | ".align 2\n" |
@@ -41,7 +45,11 @@ static inline cycles_t get_cycles(void) | |||
41 | " .long 0\n" | 45 | " .long 0\n" |
42 | " .long 0\n" | 46 | " .long 0\n" |
43 | ".previous" | 47 | ".previous" |
48 | #ifdef CONFIG_8xx | ||
49 | : "=r" (ret) : "i" (CPU_FTR_601)); | ||
50 | #else | ||
44 | : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); | 51 | : "=r" (ret) : "i" (CPU_FTR_601), "i" (SPRN_TBRL)); |
52 | #endif | ||
45 | return ret; | 53 | return ret; |
46 | #endif | 54 | #endif |
47 | } | 55 | } |
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c index e1ec57e87b3b..88a7fb458dfd 100644 --- a/arch/powerpc/kernel/machine_kexec.c +++ b/arch/powerpc/kernel/machine_kexec.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/ftrace.h> | 18 | #include <linux/ftrace.h> |
19 | 19 | ||
20 | #include <asm/machdep.h> | 20 | #include <asm/machdep.h> |
21 | #include <asm/pgalloc.h> | ||
21 | #include <asm/prom.h> | 22 | #include <asm/prom.h> |
22 | #include <asm/sections.h> | 23 | #include <asm/sections.h> |
23 | 24 | ||
@@ -75,6 +76,17 @@ void arch_crash_save_vmcoreinfo(void) | |||
75 | #ifndef CONFIG_NEED_MULTIPLE_NODES | 76 | #ifndef CONFIG_NEED_MULTIPLE_NODES |
76 | VMCOREINFO_SYMBOL(contig_page_data); | 77 | VMCOREINFO_SYMBOL(contig_page_data); |
77 | #endif | 78 | #endif |
79 | #if defined(CONFIG_PPC64) && defined(CONFIG_SPARSEMEM_VMEMMAP) | ||
80 | VMCOREINFO_SYMBOL(vmemmap_list); | ||
81 | VMCOREINFO_SYMBOL(mmu_vmemmap_psize); | ||
82 | VMCOREINFO_SYMBOL(mmu_psize_defs); | ||
83 | VMCOREINFO_STRUCT_SIZE(vmemmap_backing); | ||
84 | VMCOREINFO_OFFSET(vmemmap_backing, list); | ||
85 | VMCOREINFO_OFFSET(vmemmap_backing, phys); | ||
86 | VMCOREINFO_OFFSET(vmemmap_backing, virt_addr); | ||
87 | VMCOREINFO_STRUCT_SIZE(mmu_psize_def); | ||
88 | VMCOREINFO_OFFSET(mmu_psize_def, shift); | ||
89 | #endif | ||
78 | } | 90 | } |
79 | 91 | ||
80 | /* | 92 | /* |
diff --git a/arch/powerpc/kernel/nvram_64.c b/arch/powerpc/kernel/nvram_64.c index fd82c289ab1c..28b898e68185 100644 --- a/arch/powerpc/kernel/nvram_64.c +++ b/arch/powerpc/kernel/nvram_64.c | |||
@@ -210,7 +210,7 @@ static void __init nvram_print_partitions(char * label) | |||
210 | printk(KERN_WARNING "--------%s---------\n", label); | 210 | printk(KERN_WARNING "--------%s---------\n", label); |
211 | printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n"); | 211 | printk(KERN_WARNING "indx\t\tsig\tchks\tlen\tname\n"); |
212 | list_for_each_entry(tmp_part, &nvram_partitions, partition) { | 212 | list_for_each_entry(tmp_part, &nvram_partitions, partition) { |
213 | printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12s\n", | 213 | printk(KERN_WARNING "%4d \t%02x\t%02x\t%d\t%12.12s\n", |
214 | tmp_part->index, tmp_part->header.signature, | 214 | tmp_part->index, tmp_part->header.signature, |
215 | tmp_part->header.checksum, tmp_part->header.length, | 215 | tmp_part->header.checksum, tmp_part->header.length, |
216 | tmp_part->header.name); | 216 | tmp_part->header.name); |
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c index 1844298f5ea4..68027bfa5f8e 100644 --- a/arch/powerpc/kernel/signal_32.c +++ b/arch/powerpc/kernel/signal_32.c | |||
@@ -445,6 +445,12 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, | |||
445 | #endif /* CONFIG_ALTIVEC */ | 445 | #endif /* CONFIG_ALTIVEC */ |
446 | if (copy_fpr_to_user(&frame->mc_fregs, current)) | 446 | if (copy_fpr_to_user(&frame->mc_fregs, current)) |
447 | return 1; | 447 | return 1; |
448 | |||
449 | /* | ||
450 | * Clear the MSR VSX bit to indicate there is no valid state attached | ||
451 | * to this context, except in the specific case below where we set it. | ||
452 | */ | ||
453 | msr &= ~MSR_VSX; | ||
448 | #ifdef CONFIG_VSX | 454 | #ifdef CONFIG_VSX |
449 | /* | 455 | /* |
450 | * Copy VSR 0-31 upper half from thread_struct to local | 456 | * Copy VSR 0-31 upper half from thread_struct to local |
@@ -457,15 +463,7 @@ static int save_user_regs(struct pt_regs *regs, struct mcontext __user *frame, | |||
457 | if (copy_vsx_to_user(&frame->mc_vsregs, current)) | 463 | if (copy_vsx_to_user(&frame->mc_vsregs, current)) |
458 | return 1; | 464 | return 1; |
459 | msr |= MSR_VSX; | 465 | msr |= MSR_VSX; |
460 | } else if (!ctx_has_vsx_region) | 466 | } |
461 | /* | ||
462 | * With a small context structure we can't hold the VSX | ||
463 | * registers, hence clear the MSR value to indicate the state | ||
464 | * was not saved. | ||
465 | */ | ||
466 | msr &= ~MSR_VSX; | ||
467 | |||
468 | |||
469 | #endif /* CONFIG_VSX */ | 467 | #endif /* CONFIG_VSX */ |
470 | #ifdef CONFIG_SPE | 468 | #ifdef CONFIG_SPE |
471 | /* save spe registers */ | 469 | /* save spe registers */ |
diff --git a/arch/powerpc/kernel/signal_64.c b/arch/powerpc/kernel/signal_64.c index e66f67b8b9e6..42991045349f 100644 --- a/arch/powerpc/kernel/signal_64.c +++ b/arch/powerpc/kernel/signal_64.c | |||
@@ -122,6 +122,12 @@ static long setup_sigcontext(struct sigcontext __user *sc, struct pt_regs *regs, | |||
122 | flush_fp_to_thread(current); | 122 | flush_fp_to_thread(current); |
123 | /* copy fpr regs and fpscr */ | 123 | /* copy fpr regs and fpscr */ |
124 | err |= copy_fpr_to_user(&sc->fp_regs, current); | 124 | err |= copy_fpr_to_user(&sc->fp_regs, current); |
125 | |||
126 | /* | ||
127 | * Clear the MSR VSX bit to indicate there is no valid state attached | ||
128 | * to this context, except in the specific case below where we set it. | ||
129 | */ | ||
130 | msr &= ~MSR_VSX; | ||
125 | #ifdef CONFIG_VSX | 131 | #ifdef CONFIG_VSX |
126 | /* | 132 | /* |
127 | * Copy VSX low doubleword to local buffer for formatting, | 133 | * Copy VSX low doubleword to local buffer for formatting, |
diff --git a/arch/powerpc/kernel/vdso32/gettimeofday.S b/arch/powerpc/kernel/vdso32/gettimeofday.S index 6b1f2a6d5517..6b2b69616e77 100644 --- a/arch/powerpc/kernel/vdso32/gettimeofday.S +++ b/arch/powerpc/kernel/vdso32/gettimeofday.S | |||
@@ -232,9 +232,15 @@ __do_get_tspec: | |||
232 | lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) | 232 | lwz r6,(CFG_TB_ORIG_STAMP+4)(r9) |
233 | 233 | ||
234 | /* Get a stable TB value */ | 234 | /* Get a stable TB value */ |
235 | #ifdef CONFIG_8xx | ||
236 | 2: mftbu r3 | ||
237 | mftbl r4 | ||
238 | mftbu r0 | ||
239 | #else | ||
235 | 2: mfspr r3, SPRN_TBRU | 240 | 2: mfspr r3, SPRN_TBRU |
236 | mfspr r4, SPRN_TBRL | 241 | mfspr r4, SPRN_TBRL |
237 | mfspr r0, SPRN_TBRU | 242 | mfspr r0, SPRN_TBRU |
243 | #endif | ||
238 | cmplw cr0,r3,r0 | 244 | cmplw cr0,r3,r0 |
239 | bne- 2b | 245 | bne- 2b |
240 | 246 | ||
diff --git a/arch/powerpc/mm/hugetlbpage-book3e.c b/arch/powerpc/mm/hugetlbpage-book3e.c index 3bc700655fc8..74551b5e41e5 100644 --- a/arch/powerpc/mm/hugetlbpage-book3e.c +++ b/arch/powerpc/mm/hugetlbpage-book3e.c | |||
@@ -117,6 +117,5 @@ void flush_hugetlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | |||
117 | struct hstate *hstate = hstate_file(vma->vm_file); | 117 | struct hstate *hstate = hstate_file(vma->vm_file); |
118 | unsigned long tsize = huge_page_shift(hstate) - 10; | 118 | unsigned long tsize = huge_page_shift(hstate) - 10; |
119 | 119 | ||
120 | __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr, tsize, 0); | 120 | __flush_tlb_page(vma->vm_mm, vmaddr, tsize, 0); |
121 | |||
122 | } | 121 | } |
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 41cd68dee681..358d74303138 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c | |||
@@ -305,7 +305,7 @@ void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr, | |||
305 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) | 305 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) |
306 | { | 306 | { |
307 | #ifdef CONFIG_HUGETLB_PAGE | 307 | #ifdef CONFIG_HUGETLB_PAGE |
308 | if (is_vm_hugetlb_page(vma)) | 308 | if (vma && is_vm_hugetlb_page(vma)) |
309 | flush_hugetlb_page(vma, vmaddr); | 309 | flush_hugetlb_page(vma, vmaddr); |
310 | #endif | 310 | #endif |
311 | 311 | ||
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype index 132f8726a257..bca2465a9c34 100644 --- a/arch/powerpc/platforms/Kconfig.cputype +++ b/arch/powerpc/platforms/Kconfig.cputype | |||
@@ -404,13 +404,27 @@ config PPC_DOORBELL | |||
404 | 404 | ||
405 | endmenu | 405 | endmenu |
406 | 406 | ||
407 | config CPU_LITTLE_ENDIAN | 407 | choice |
408 | bool "Build little endian kernel" | 408 | prompt "Endianness selection" |
409 | default n | 409 | default CPU_BIG_ENDIAN |
410 | help | 410 | help |
411 | This option selects whether a big endian or little endian kernel will | 411 | This option selects whether a big endian or little endian kernel will |
412 | be built. | 412 | be built. |
413 | 413 | ||
414 | config CPU_BIG_ENDIAN | ||
415 | bool "Build big endian kernel" | ||
416 | help | ||
417 | Build a big endian kernel. | ||
418 | |||
419 | If unsure, select this option. | ||
420 | |||
421 | config CPU_LITTLE_ENDIAN | ||
422 | bool "Build little endian kernel" | ||
423 | help | ||
424 | Build a little endian kernel. | ||
425 | |||
414 | Note that if cross compiling a little endian kernel, | 426 | Note that if cross compiling a little endian kernel, |
415 | CROSS_COMPILE must point to a toolchain capable of targeting | 427 | CROSS_COMPILE must point to a toolchain capable of targeting |
416 | little endian powerpc. | 428 | little endian powerpc. |
429 | |||
430 | endchoice | ||
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig index 314fced4fc14..5877e71901b3 100644 --- a/arch/s390/Kconfig +++ b/arch/s390/Kconfig | |||
@@ -101,7 +101,7 @@ config S390 | |||
101 | select GENERIC_CPU_DEVICES if !SMP | 101 | select GENERIC_CPU_DEVICES if !SMP |
102 | select GENERIC_FIND_FIRST_BIT | 102 | select GENERIC_FIND_FIRST_BIT |
103 | select GENERIC_SMP_IDLE_THREAD | 103 | select GENERIC_SMP_IDLE_THREAD |
104 | select GENERIC_TIME_VSYSCALL_OLD | 104 | select GENERIC_TIME_VSYSCALL |
105 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB | 105 | select HAVE_ALIGNED_STRUCT_PAGE if SLUB |
106 | select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 | 106 | select HAVE_ARCH_JUMP_LABEL if !MARCH_G5 |
107 | select HAVE_ARCH_SECCOMP_FILTER | 107 | select HAVE_ARCH_SECCOMP_FILTER |
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c index 46cae138ece2..4363528dc8fd 100644 --- a/arch/s390/crypto/aes_s390.c +++ b/arch/s390/crypto/aes_s390.c | |||
@@ -35,7 +35,6 @@ static u8 *ctrblk; | |||
35 | static char keylen_flag; | 35 | static char keylen_flag; |
36 | 36 | ||
37 | struct s390_aes_ctx { | 37 | struct s390_aes_ctx { |
38 | u8 iv[AES_BLOCK_SIZE]; | ||
39 | u8 key[AES_MAX_KEY_SIZE]; | 38 | u8 key[AES_MAX_KEY_SIZE]; |
40 | long enc; | 39 | long enc; |
41 | long dec; | 40 | long dec; |
@@ -441,30 +440,36 @@ static int cbc_aes_set_key(struct crypto_tfm *tfm, const u8 *in_key, | |||
441 | return aes_set_key(tfm, in_key, key_len); | 440 | return aes_set_key(tfm, in_key, key_len); |
442 | } | 441 | } |
443 | 442 | ||
444 | static int cbc_aes_crypt(struct blkcipher_desc *desc, long func, void *param, | 443 | static int cbc_aes_crypt(struct blkcipher_desc *desc, long func, |
445 | struct blkcipher_walk *walk) | 444 | struct blkcipher_walk *walk) |
446 | { | 445 | { |
446 | struct s390_aes_ctx *sctx = crypto_blkcipher_ctx(desc->tfm); | ||
447 | int ret = blkcipher_walk_virt(desc, walk); | 447 | int ret = blkcipher_walk_virt(desc, walk); |
448 | unsigned int nbytes = walk->nbytes; | 448 | unsigned int nbytes = walk->nbytes; |
449 | struct { | ||
450 | u8 iv[AES_BLOCK_SIZE]; | ||
451 | u8 key[AES_MAX_KEY_SIZE]; | ||
452 | } param; | ||
449 | 453 | ||
450 | if (!nbytes) | 454 | if (!nbytes) |
451 | goto out; | 455 | goto out; |
452 | 456 | ||
453 | memcpy(param, walk->iv, AES_BLOCK_SIZE); | 457 | memcpy(param.iv, walk->iv, AES_BLOCK_SIZE); |
458 | memcpy(param.key, sctx->key, sctx->key_len); | ||
454 | do { | 459 | do { |
455 | /* only use complete blocks */ | 460 | /* only use complete blocks */ |
456 | unsigned int n = nbytes & ~(AES_BLOCK_SIZE - 1); | 461 | unsigned int n = nbytes & ~(AES_BLOCK_SIZE - 1); |
457 | u8 *out = walk->dst.virt.addr; | 462 | u8 *out = walk->dst.virt.addr; |
458 | u8 *in = walk->src.virt.addr; | 463 | u8 *in = walk->src.virt.addr; |
459 | 464 | ||
460 | ret = crypt_s390_kmc(func, param, out, in, n); | 465 | ret = crypt_s390_kmc(func, ¶m, out, in, n); |
461 | if (ret < 0 || ret != n) | 466 | if (ret < 0 || ret != n) |
462 | return -EIO; | 467 | return -EIO; |
463 | 468 | ||
464 | nbytes &= AES_BLOCK_SIZE - 1; | 469 | nbytes &= AES_BLOCK_SIZE - 1; |
465 | ret = blkcipher_walk_done(desc, walk, nbytes); | 470 | ret = blkcipher_walk_done(desc, walk, nbytes); |
466 | } while ((nbytes = walk->nbytes)); | 471 | } while ((nbytes = walk->nbytes)); |
467 | memcpy(walk->iv, param, AES_BLOCK_SIZE); | 472 | memcpy(walk->iv, param.iv, AES_BLOCK_SIZE); |
468 | 473 | ||
469 | out: | 474 | out: |
470 | return ret; | 475 | return ret; |
@@ -481,7 +486,7 @@ static int cbc_aes_encrypt(struct blkcipher_desc *desc, | |||
481 | return fallback_blk_enc(desc, dst, src, nbytes); | 486 | return fallback_blk_enc(desc, dst, src, nbytes); |
482 | 487 | ||
483 | blkcipher_walk_init(&walk, dst, src, nbytes); | 488 | blkcipher_walk_init(&walk, dst, src, nbytes); |
484 | return cbc_aes_crypt(desc, sctx->enc, sctx->iv, &walk); | 489 | return cbc_aes_crypt(desc, sctx->enc, &walk); |
485 | } | 490 | } |
486 | 491 | ||
487 | static int cbc_aes_decrypt(struct blkcipher_desc *desc, | 492 | static int cbc_aes_decrypt(struct blkcipher_desc *desc, |
@@ -495,7 +500,7 @@ static int cbc_aes_decrypt(struct blkcipher_desc *desc, | |||
495 | return fallback_blk_dec(desc, dst, src, nbytes); | 500 | return fallback_blk_dec(desc, dst, src, nbytes); |
496 | 501 | ||
497 | blkcipher_walk_init(&walk, dst, src, nbytes); | 502 | blkcipher_walk_init(&walk, dst, src, nbytes); |
498 | return cbc_aes_crypt(desc, sctx->dec, sctx->iv, &walk); | 503 | return cbc_aes_crypt(desc, sctx->dec, &walk); |
499 | } | 504 | } |
500 | 505 | ||
501 | static struct crypto_alg cbc_aes_alg = { | 506 | static struct crypto_alg cbc_aes_alg = { |
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h index 316c8503a3b4..114258eeaacd 100644 --- a/arch/s390/include/asm/page.h +++ b/arch/s390/include/asm/page.h | |||
@@ -48,33 +48,21 @@ static inline void clear_page(void *page) | |||
48 | : "memory", "cc"); | 48 | : "memory", "cc"); |
49 | } | 49 | } |
50 | 50 | ||
51 | /* | ||
52 | * copy_page uses the mvcl instruction with 0xb0 padding byte in order to | ||
53 | * bypass caches when copying a page. Especially when copying huge pages | ||
54 | * this keeps L1 and L2 data caches alive. | ||
55 | */ | ||
51 | static inline void copy_page(void *to, void *from) | 56 | static inline void copy_page(void *to, void *from) |
52 | { | 57 | { |
53 | if (MACHINE_HAS_MVPG) { | 58 | register void *reg2 asm ("2") = to; |
54 | register unsigned long reg0 asm ("0") = 0; | 59 | register unsigned long reg3 asm ("3") = 0x1000; |
55 | asm volatile( | 60 | register void *reg4 asm ("4") = from; |
56 | " mvpg %0,%1" | 61 | register unsigned long reg5 asm ("5") = 0xb0001000; |
57 | : : "a" (to), "a" (from), "d" (reg0) | 62 | asm volatile( |
58 | : "memory", "cc"); | 63 | " mvcl 2,4" |
59 | } else | 64 | : "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5) |
60 | asm volatile( | 65 | : : "memory", "cc"); |
61 | " mvc 0(256,%0),0(%1)\n" | ||
62 | " mvc 256(256,%0),256(%1)\n" | ||
63 | " mvc 512(256,%0),512(%1)\n" | ||
64 | " mvc 768(256,%0),768(%1)\n" | ||
65 | " mvc 1024(256,%0),1024(%1)\n" | ||
66 | " mvc 1280(256,%0),1280(%1)\n" | ||
67 | " mvc 1536(256,%0),1536(%1)\n" | ||
68 | " mvc 1792(256,%0),1792(%1)\n" | ||
69 | " mvc 2048(256,%0),2048(%1)\n" | ||
70 | " mvc 2304(256,%0),2304(%1)\n" | ||
71 | " mvc 2560(256,%0),2560(%1)\n" | ||
72 | " mvc 2816(256,%0),2816(%1)\n" | ||
73 | " mvc 3072(256,%0),3072(%1)\n" | ||
74 | " mvc 3328(256,%0),3328(%1)\n" | ||
75 | " mvc 3584(256,%0),3584(%1)\n" | ||
76 | " mvc 3840(256,%0),3840(%1)\n" | ||
77 | : : "a" (to), "a" (from) : "memory"); | ||
78 | } | 66 | } |
79 | 67 | ||
80 | #define clear_user_page(page, vaddr, pg) clear_page(page) | 68 | #define clear_user_page(page, vaddr, pg) clear_page(page) |
diff --git a/arch/s390/include/asm/vdso.h b/arch/s390/include/asm/vdso.h index a73eb2e1e918..bc9746a7d47c 100644 --- a/arch/s390/include/asm/vdso.h +++ b/arch/s390/include/asm/vdso.h | |||
@@ -26,8 +26,9 @@ struct vdso_data { | |||
26 | __u64 wtom_clock_nsec; /* 0x28 */ | 26 | __u64 wtom_clock_nsec; /* 0x28 */ |
27 | __u32 tz_minuteswest; /* Minutes west of Greenwich 0x30 */ | 27 | __u32 tz_minuteswest; /* Minutes west of Greenwich 0x30 */ |
28 | __u32 tz_dsttime; /* Type of dst correction 0x34 */ | 28 | __u32 tz_dsttime; /* Type of dst correction 0x34 */ |
29 | __u32 ectg_available; | 29 | __u32 ectg_available; /* ECTG instruction present 0x38 */ |
30 | __u32 ntp_mult; /* NTP adjusted multiplier 0x3C */ | 30 | __u32 tk_mult; /* Mult. used for xtime_nsec 0x3c */ |
31 | __u32 tk_shift; /* Shift used for xtime_nsec 0x40 */ | ||
31 | }; | 32 | }; |
32 | 33 | ||
33 | struct vdso_per_cpu_data { | 34 | struct vdso_per_cpu_data { |
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c index 2416138ebd3e..496116cd65ec 100644 --- a/arch/s390/kernel/asm-offsets.c +++ b/arch/s390/kernel/asm-offsets.c | |||
@@ -65,7 +65,8 @@ int main(void) | |||
65 | DEFINE(__VDSO_WTOM_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); | 65 | DEFINE(__VDSO_WTOM_NSEC, offsetof(struct vdso_data, wtom_clock_nsec)); |
66 | DEFINE(__VDSO_TIMEZONE, offsetof(struct vdso_data, tz_minuteswest)); | 66 | DEFINE(__VDSO_TIMEZONE, offsetof(struct vdso_data, tz_minuteswest)); |
67 | DEFINE(__VDSO_ECTG_OK, offsetof(struct vdso_data, ectg_available)); | 67 | DEFINE(__VDSO_ECTG_OK, offsetof(struct vdso_data, ectg_available)); |
68 | DEFINE(__VDSO_NTP_MULT, offsetof(struct vdso_data, ntp_mult)); | 68 | DEFINE(__VDSO_TK_MULT, offsetof(struct vdso_data, tk_mult)); |
69 | DEFINE(__VDSO_TK_SHIFT, offsetof(struct vdso_data, tk_shift)); | ||
69 | DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base)); | 70 | DEFINE(__VDSO_ECTG_BASE, offsetof(struct vdso_per_cpu_data, ectg_timer_base)); |
70 | DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time)); | 71 | DEFINE(__VDSO_ECTG_USER, offsetof(struct vdso_per_cpu_data, ectg_user_time)); |
71 | /* constants used by the vdso */ | 72 | /* constants used by the vdso */ |
diff --git a/arch/s390/kernel/compat_signal.c b/arch/s390/kernel/compat_signal.c index 6e2442978409..95e7ba0fbb7e 100644 --- a/arch/s390/kernel/compat_signal.c +++ b/arch/s390/kernel/compat_signal.c | |||
@@ -194,7 +194,7 @@ static int restore_sigregs32(struct pt_regs *regs,_sigregs32 __user *sregs) | |||
194 | return -EINVAL; | 194 | return -EINVAL; |
195 | 195 | ||
196 | /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ | 196 | /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ |
197 | regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | | 197 | regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) | |
198 | (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_USER) << 32 | | 198 | (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_USER) << 32 | |
199 | (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_RI) << 32 | | 199 | (__u64)(user_sregs.regs.psw.mask & PSW32_MASK_RI) << 32 | |
200 | (__u64)(user_sregs.regs.psw.addr & PSW32_ADDR_AMODE); | 200 | (__u64)(user_sregs.regs.psw.addr & PSW32_ADDR_AMODE); |
diff --git a/arch/s390/kernel/pgm_check.S b/arch/s390/kernel/pgm_check.S index 4a460c44e17e..813ec7260878 100644 --- a/arch/s390/kernel/pgm_check.S +++ b/arch/s390/kernel/pgm_check.S | |||
@@ -78,7 +78,7 @@ PGM_CHECK_DEFAULT /* 34 */ | |||
78 | PGM_CHECK_DEFAULT /* 35 */ | 78 | PGM_CHECK_DEFAULT /* 35 */ |
79 | PGM_CHECK_DEFAULT /* 36 */ | 79 | PGM_CHECK_DEFAULT /* 36 */ |
80 | PGM_CHECK_DEFAULT /* 37 */ | 80 | PGM_CHECK_DEFAULT /* 37 */ |
81 | PGM_CHECK_DEFAULT /* 38 */ | 81 | PGM_CHECK_64BIT(do_dat_exception) /* 38 */ |
82 | PGM_CHECK_64BIT(do_dat_exception) /* 39 */ | 82 | PGM_CHECK_64BIT(do_dat_exception) /* 39 */ |
83 | PGM_CHECK_64BIT(do_dat_exception) /* 3a */ | 83 | PGM_CHECK_64BIT(do_dat_exception) /* 3a */ |
84 | PGM_CHECK_64BIT(do_dat_exception) /* 3b */ | 84 | PGM_CHECK_64BIT(do_dat_exception) /* 3b */ |
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c index fb535874a246..d8fd508ccd1e 100644 --- a/arch/s390/kernel/signal.c +++ b/arch/s390/kernel/signal.c | |||
@@ -94,7 +94,7 @@ static int restore_sigregs(struct pt_regs *regs, _sigregs __user *sregs) | |||
94 | return -EINVAL; | 94 | return -EINVAL; |
95 | 95 | ||
96 | /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ | 96 | /* Use regs->psw.mask instead of PSW_USER_BITS to preserve PER bit. */ |
97 | regs->psw.mask = (regs->psw.mask & ~PSW_MASK_USER) | | 97 | regs->psw.mask = (regs->psw.mask & ~(PSW_MASK_USER | PSW_MASK_RI)) | |
98 | (user_sregs.regs.psw.mask & (PSW_MASK_USER | PSW_MASK_RI)); | 98 | (user_sregs.regs.psw.mask & (PSW_MASK_USER | PSW_MASK_RI)); |
99 | /* Check for invalid user address space control. */ | 99 | /* Check for invalid user address space control. */ |
100 | if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) | 100 | if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) |
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c index 064c3082ab33..dd95f1631621 100644 --- a/arch/s390/kernel/time.c +++ b/arch/s390/kernel/time.c | |||
@@ -108,20 +108,10 @@ static void fixup_clock_comparator(unsigned long long delta) | |||
108 | set_clock_comparator(S390_lowcore.clock_comparator); | 108 | set_clock_comparator(S390_lowcore.clock_comparator); |
109 | } | 109 | } |
110 | 110 | ||
111 | static int s390_next_ktime(ktime_t expires, | 111 | static int s390_next_event(unsigned long delta, |
112 | struct clock_event_device *evt) | 112 | struct clock_event_device *evt) |
113 | { | 113 | { |
114 | struct timespec ts; | 114 | S390_lowcore.clock_comparator = get_tod_clock() + delta; |
115 | u64 nsecs; | ||
116 | |||
117 | ts.tv_sec = ts.tv_nsec = 0; | ||
118 | monotonic_to_bootbased(&ts); | ||
119 | nsecs = ktime_to_ns(ktime_add(timespec_to_ktime(ts), expires)); | ||
120 | do_div(nsecs, 125); | ||
121 | S390_lowcore.clock_comparator = sched_clock_base_cc + (nsecs << 9); | ||
122 | /* Program the maximum value if we have an overflow (== year 2042) */ | ||
123 | if (unlikely(S390_lowcore.clock_comparator < sched_clock_base_cc)) | ||
124 | S390_lowcore.clock_comparator = -1ULL; | ||
125 | set_clock_comparator(S390_lowcore.clock_comparator); | 115 | set_clock_comparator(S390_lowcore.clock_comparator); |
126 | return 0; | 116 | return 0; |
127 | } | 117 | } |
@@ -146,15 +136,14 @@ void init_cpu_timer(void) | |||
146 | cpu = smp_processor_id(); | 136 | cpu = smp_processor_id(); |
147 | cd = &per_cpu(comparators, cpu); | 137 | cd = &per_cpu(comparators, cpu); |
148 | cd->name = "comparator"; | 138 | cd->name = "comparator"; |
149 | cd->features = CLOCK_EVT_FEAT_ONESHOT | | 139 | cd->features = CLOCK_EVT_FEAT_ONESHOT; |
150 | CLOCK_EVT_FEAT_KTIME; | ||
151 | cd->mult = 16777; | 140 | cd->mult = 16777; |
152 | cd->shift = 12; | 141 | cd->shift = 12; |
153 | cd->min_delta_ns = 1; | 142 | cd->min_delta_ns = 1; |
154 | cd->max_delta_ns = LONG_MAX; | 143 | cd->max_delta_ns = LONG_MAX; |
155 | cd->rating = 400; | 144 | cd->rating = 400; |
156 | cd->cpumask = cpumask_of(cpu); | 145 | cd->cpumask = cpumask_of(cpu); |
157 | cd->set_next_ktime = s390_next_ktime; | 146 | cd->set_next_event = s390_next_event; |
158 | cd->set_mode = s390_set_mode; | 147 | cd->set_mode = s390_set_mode; |
159 | 148 | ||
160 | clockevents_register_device(cd); | 149 | clockevents_register_device(cd); |
@@ -221,21 +210,30 @@ struct clocksource * __init clocksource_default_clock(void) | |||
221 | return &clocksource_tod; | 210 | return &clocksource_tod; |
222 | } | 211 | } |
223 | 212 | ||
224 | void update_vsyscall_old(struct timespec *wall_time, struct timespec *wtm, | 213 | void update_vsyscall(struct timekeeper *tk) |
225 | struct clocksource *clock, u32 mult) | ||
226 | { | 214 | { |
227 | if (clock != &clocksource_tod) | 215 | u64 nsecps; |
216 | |||
217 | if (tk->clock != &clocksource_tod) | ||
228 | return; | 218 | return; |
229 | 219 | ||
230 | /* Make userspace gettimeofday spin until we're done. */ | 220 | /* Make userspace gettimeofday spin until we're done. */ |
231 | ++vdso_data->tb_update_count; | 221 | ++vdso_data->tb_update_count; |
232 | smp_wmb(); | 222 | smp_wmb(); |
233 | vdso_data->xtime_tod_stamp = clock->cycle_last; | 223 | vdso_data->xtime_tod_stamp = tk->clock->cycle_last; |
234 | vdso_data->xtime_clock_sec = wall_time->tv_sec; | 224 | vdso_data->xtime_clock_sec = tk->xtime_sec; |
235 | vdso_data->xtime_clock_nsec = wall_time->tv_nsec; | 225 | vdso_data->xtime_clock_nsec = tk->xtime_nsec; |
236 | vdso_data->wtom_clock_sec = wtm->tv_sec; | 226 | vdso_data->wtom_clock_sec = |
237 | vdso_data->wtom_clock_nsec = wtm->tv_nsec; | 227 | tk->xtime_sec + tk->wall_to_monotonic.tv_sec; |
238 | vdso_data->ntp_mult = mult; | 228 | vdso_data->wtom_clock_nsec = tk->xtime_nsec + |
229 | + (tk->wall_to_monotonic.tv_nsec << tk->shift); | ||
230 | nsecps = (u64) NSEC_PER_SEC << tk->shift; | ||
231 | while (vdso_data->wtom_clock_nsec >= nsecps) { | ||
232 | vdso_data->wtom_clock_nsec -= nsecps; | ||
233 | vdso_data->wtom_clock_sec++; | ||
234 | } | ||
235 | vdso_data->tk_mult = tk->mult; | ||
236 | vdso_data->tk_shift = tk->shift; | ||
239 | smp_wmb(); | 237 | smp_wmb(); |
240 | ++vdso_data->tb_update_count; | 238 | ++vdso_data->tb_update_count; |
241 | } | 239 | } |
diff --git a/arch/s390/kernel/vdso32/clock_gettime.S b/arch/s390/kernel/vdso32/clock_gettime.S index b2224e0b974c..5be8e472f57d 100644 --- a/arch/s390/kernel/vdso32/clock_gettime.S +++ b/arch/s390/kernel/vdso32/clock_gettime.S | |||
@@ -38,25 +38,26 @@ __kernel_clock_gettime: | |||
38 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) | 38 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) |
39 | brc 3,2f | 39 | brc 3,2f |
40 | ahi %r0,-1 | 40 | ahi %r0,-1 |
41 | 2: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ | 41 | 2: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
42 | lr %r2,%r0 | 42 | lr %r2,%r0 |
43 | l %r0,__VDSO_NTP_MULT(%r5) | 43 | l %r0,__VDSO_TK_MULT(%r5) |
44 | ltr %r1,%r1 | 44 | ltr %r1,%r1 |
45 | mr %r0,%r0 | 45 | mr %r0,%r0 |
46 | jnm 3f | 46 | jnm 3f |
47 | a %r0,__VDSO_NTP_MULT(%r5) | 47 | a %r0,__VDSO_TK_MULT(%r5) |
48 | 3: alr %r0,%r2 | 48 | 3: alr %r0,%r2 |
49 | srdl %r0,12 | 49 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */ |
50 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | ||
51 | al %r1,__VDSO_XTIME_NSEC+4(%r5) | 50 | al %r1,__VDSO_XTIME_NSEC+4(%r5) |
52 | brc 12,4f | 51 | brc 12,4f |
53 | ahi %r0,1 | 52 | ahi %r0,1 |
54 | 4: l %r2,__VDSO_XTIME_SEC+4(%r5) | 53 | 4: al %r0,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic.nsec */ |
55 | al %r0,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic */ | ||
56 | al %r1,__VDSO_WTOM_NSEC+4(%r5) | 54 | al %r1,__VDSO_WTOM_NSEC+4(%r5) |
57 | brc 12,5f | 55 | brc 12,5f |
58 | ahi %r0,1 | 56 | ahi %r0,1 |
59 | 5: al %r2,__VDSO_WTOM_SEC+4(%r5) | 57 | 5: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ |
58 | srdl %r0,0(%r2) /* >> tk->shift */ | ||
59 | l %r2,__VDSO_XTIME_SEC+4(%r5) | ||
60 | al %r2,__VDSO_WTOM_SEC+4(%r5) | ||
60 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ | 61 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ |
61 | jne 1b | 62 | jne 1b |
62 | basr %r5,0 | 63 | basr %r5,0 |
@@ -86,20 +87,21 @@ __kernel_clock_gettime: | |||
86 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) | 87 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) |
87 | brc 3,12f | 88 | brc 3,12f |
88 | ahi %r0,-1 | 89 | ahi %r0,-1 |
89 | 12: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ | 90 | 12: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
90 | lr %r2,%r0 | 91 | lr %r2,%r0 |
91 | l %r0,__VDSO_NTP_MULT(%r5) | 92 | l %r0,__VDSO_TK_MULT(%r5) |
92 | ltr %r1,%r1 | 93 | ltr %r1,%r1 |
93 | mr %r0,%r0 | 94 | mr %r0,%r0 |
94 | jnm 13f | 95 | jnm 13f |
95 | a %r0,__VDSO_NTP_MULT(%r5) | 96 | a %r0,__VDSO_TK_MULT(%r5) |
96 | 13: alr %r0,%r2 | 97 | 13: alr %r0,%r2 |
97 | srdl %r0,12 | 98 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */ |
98 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | ||
99 | al %r1,__VDSO_XTIME_NSEC+4(%r5) | 99 | al %r1,__VDSO_XTIME_NSEC+4(%r5) |
100 | brc 12,14f | 100 | brc 12,14f |
101 | ahi %r0,1 | 101 | ahi %r0,1 |
102 | 14: l %r2,__VDSO_XTIME_SEC+4(%r5) | 102 | 14: l %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ |
103 | srdl %r0,0(%r2) /* >> tk->shift */ | ||
104 | l %r2,__VDSO_XTIME_SEC+4(%r5) | ||
103 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ | 105 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ |
104 | jne 11b | 106 | jne 11b |
105 | basr %r5,0 | 107 | basr %r5,0 |
diff --git a/arch/s390/kernel/vdso32/gettimeofday.S b/arch/s390/kernel/vdso32/gettimeofday.S index 2d3633175e3b..fd621a950f7c 100644 --- a/arch/s390/kernel/vdso32/gettimeofday.S +++ b/arch/s390/kernel/vdso32/gettimeofday.S | |||
@@ -35,15 +35,14 @@ __kernel_gettimeofday: | |||
35 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) | 35 | sl %r1,__VDSO_XTIME_STAMP+4(%r5) |
36 | brc 3,3f | 36 | brc 3,3f |
37 | ahi %r0,-1 | 37 | ahi %r0,-1 |
38 | 3: ms %r0,__VDSO_NTP_MULT(%r5) /* cyc2ns(clock,cycle_delta) */ | 38 | 3: ms %r0,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
39 | st %r0,24(%r15) | 39 | st %r0,24(%r15) |
40 | l %r0,__VDSO_NTP_MULT(%r5) | 40 | l %r0,__VDSO_TK_MULT(%r5) |
41 | ltr %r1,%r1 | 41 | ltr %r1,%r1 |
42 | mr %r0,%r0 | 42 | mr %r0,%r0 |
43 | jnm 4f | 43 | jnm 4f |
44 | a %r0,__VDSO_NTP_MULT(%r5) | 44 | a %r0,__VDSO_TK_MULT(%r5) |
45 | 4: al %r0,24(%r15) | 45 | 4: al %r0,24(%r15) |
46 | srdl %r0,12 | ||
47 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | 46 | al %r0,__VDSO_XTIME_NSEC(%r5) /* + xtime */ |
48 | al %r1,__VDSO_XTIME_NSEC+4(%r5) | 47 | al %r1,__VDSO_XTIME_NSEC+4(%r5) |
49 | brc 12,5f | 48 | brc 12,5f |
@@ -51,6 +50,8 @@ __kernel_gettimeofday: | |||
51 | 5: mvc 24(4,%r15),__VDSO_XTIME_SEC+4(%r5) | 50 | 5: mvc 24(4,%r15),__VDSO_XTIME_SEC+4(%r5) |
52 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ | 51 | cl %r4,__VDSO_UPD_COUNT+4(%r5) /* check update counter */ |
53 | jne 1b | 52 | jne 1b |
53 | l %r4,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ | ||
54 | srdl %r0,0(%r4) /* >> tk->shift */ | ||
54 | l %r4,24(%r15) /* get tv_sec from stack */ | 55 | l %r4,24(%r15) /* get tv_sec from stack */ |
55 | basr %r5,0 | 56 | basr %r5,0 |
56 | 6: ltr %r0,%r0 | 57 | 6: ltr %r0,%r0 |
diff --git a/arch/s390/kernel/vdso64/clock_gettime.S b/arch/s390/kernel/vdso64/clock_gettime.S index d46c95ed5f19..0add1072ba30 100644 --- a/arch/s390/kernel/vdso64/clock_gettime.S +++ b/arch/s390/kernel/vdso64/clock_gettime.S | |||
@@ -34,14 +34,15 @@ __kernel_clock_gettime: | |||
34 | tmll %r4,0x0001 /* pending update ? loop */ | 34 | tmll %r4,0x0001 /* pending update ? loop */ |
35 | jnz 0b | 35 | jnz 0b |
36 | stck 48(%r15) /* Store TOD clock */ | 36 | stck 48(%r15) /* Store TOD clock */ |
37 | lgf %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ | ||
38 | lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */ | ||
39 | alg %r0,__VDSO_WTOM_SEC(%r5) /* + wall_to_monotonic.sec */ | ||
37 | lg %r1,48(%r15) | 40 | lg %r1,48(%r15) |
38 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ | 41 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ |
39 | msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ | 42 | msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
40 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ | 43 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */ |
41 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | 44 | alg %r1,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic.nsec */ |
42 | lg %r0,__VDSO_XTIME_SEC(%r5) | 45 | srlg %r1,%r1,0(%r2) /* >> tk->shift */ |
43 | alg %r1,__VDSO_WTOM_NSEC(%r5) /* + wall_to_monotonic */ | ||
44 | alg %r0,__VDSO_WTOM_SEC(%r5) | ||
45 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ | 46 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ |
46 | jne 0b | 47 | jne 0b |
47 | larl %r5,13f | 48 | larl %r5,13f |
@@ -62,12 +63,13 @@ __kernel_clock_gettime: | |||
62 | tmll %r4,0x0001 /* pending update ? loop */ | 63 | tmll %r4,0x0001 /* pending update ? loop */ |
63 | jnz 5b | 64 | jnz 5b |
64 | stck 48(%r15) /* Store TOD clock */ | 65 | stck 48(%r15) /* Store TOD clock */ |
66 | lgf %r2,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ | ||
65 | lg %r1,48(%r15) | 67 | lg %r1,48(%r15) |
66 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ | 68 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ |
67 | msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ | 69 | msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
68 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ | 70 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */ |
69 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime */ | 71 | srlg %r1,%r1,0(%r2) /* >> tk->shift */ |
70 | lg %r0,__VDSO_XTIME_SEC(%r5) | 72 | lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */ |
71 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ | 73 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ |
72 | jne 5b | 74 | jne 5b |
73 | larl %r5,13f | 75 | larl %r5,13f |
diff --git a/arch/s390/kernel/vdso64/gettimeofday.S b/arch/s390/kernel/vdso64/gettimeofday.S index 36ee674722ec..d0860d1d0ccc 100644 --- a/arch/s390/kernel/vdso64/gettimeofday.S +++ b/arch/s390/kernel/vdso64/gettimeofday.S | |||
@@ -31,12 +31,13 @@ __kernel_gettimeofday: | |||
31 | stck 48(%r15) /* Store TOD clock */ | 31 | stck 48(%r15) /* Store TOD clock */ |
32 | lg %r1,48(%r15) | 32 | lg %r1,48(%r15) |
33 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ | 33 | sg %r1,__VDSO_XTIME_STAMP(%r5) /* TOD - cycle_last */ |
34 | msgf %r1,__VDSO_NTP_MULT(%r5) /* * NTP adjustment */ | 34 | msgf %r1,__VDSO_TK_MULT(%r5) /* * tk->mult */ |
35 | srlg %r1,%r1,12 /* cyc2ns(clock,cycle_delta) */ | 35 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + tk->xtime_nsec */ |
36 | alg %r1,__VDSO_XTIME_NSEC(%r5) /* + xtime.tv_nsec */ | 36 | lg %r0,__VDSO_XTIME_SEC(%r5) /* tk->xtime_sec */ |
37 | lg %r0,__VDSO_XTIME_SEC(%r5) /* xtime.tv_sec */ | ||
38 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ | 37 | clg %r4,__VDSO_UPD_COUNT(%r5) /* check update counter */ |
39 | jne 0b | 38 | jne 0b |
39 | lgf %r5,__VDSO_TK_SHIFT(%r5) /* Timekeeper shift */ | ||
40 | srlg %r1,%r1,0(%r5) /* >> tk->shift */ | ||
40 | larl %r5,5f | 41 | larl %r5,5f |
41 | 2: clg %r1,0(%r5) | 42 | 2: clg %r1,0(%r5) |
42 | jl 3f | 43 | jl 3f |
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c index 97e03caf7825..dbdab3e7a1a6 100644 --- a/arch/s390/lib/uaccess_pt.c +++ b/arch/s390/lib/uaccess_pt.c | |||
@@ -78,11 +78,14 @@ static size_t copy_in_kernel(size_t count, void __user *to, | |||
78 | * contains the (negative) exception code. | 78 | * contains the (negative) exception code. |
79 | */ | 79 | */ |
80 | #ifdef CONFIG_64BIT | 80 | #ifdef CONFIG_64BIT |
81 | |||
81 | static unsigned long follow_table(struct mm_struct *mm, | 82 | static unsigned long follow_table(struct mm_struct *mm, |
82 | unsigned long address, int write) | 83 | unsigned long address, int write) |
83 | { | 84 | { |
84 | unsigned long *table = (unsigned long *)__pa(mm->pgd); | 85 | unsigned long *table = (unsigned long *)__pa(mm->pgd); |
85 | 86 | ||
87 | if (unlikely(address > mm->context.asce_limit - 1)) | ||
88 | return -0x38UL; | ||
86 | switch (mm->context.asce_bits & _ASCE_TYPE_MASK) { | 89 | switch (mm->context.asce_bits & _ASCE_TYPE_MASK) { |
87 | case _ASCE_TYPE_REGION1: | 90 | case _ASCE_TYPE_REGION1: |
88 | table = table + ((address >> 53) & 0x7ff); | 91 | table = table + ((address >> 53) & 0x7ff); |
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c index 4df4d4ffe39b..3860b0be56c7 100644 --- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c +++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c | |||
@@ -61,51 +61,63 @@ static DECLARE_INTC_DESC(intc_desc, "sh7619", vectors, NULL, | |||
61 | NULL, prio_registers, NULL); | 61 | NULL, prio_registers, NULL); |
62 | 62 | ||
63 | static struct plat_sci_port scif0_platform_data = { | 63 | static struct plat_sci_port scif0_platform_data = { |
64 | .mapbase = 0xf8400000, | ||
65 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 65 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
68 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
69 | .irqs = SCIx_IRQ_MUXED(88), | 67 | }; |
68 | |||
69 | static struct resource scif0_resources[] = { | ||
70 | DEFINE_RES_MEM(0xf8400000, 0x100), | ||
71 | DEFINE_RES_IRQ(88), | ||
70 | }; | 72 | }; |
71 | 73 | ||
72 | static struct platform_device scif0_device = { | 74 | static struct platform_device scif0_device = { |
73 | .name = "sh-sci", | 75 | .name = "sh-sci", |
74 | .id = 0, | 76 | .id = 0, |
77 | .resource = scif0_resources, | ||
78 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
75 | .dev = { | 79 | .dev = { |
76 | .platform_data = &scif0_platform_data, | 80 | .platform_data = &scif0_platform_data, |
77 | }, | 81 | }, |
78 | }; | 82 | }; |
79 | 83 | ||
80 | static struct plat_sci_port scif1_platform_data = { | 84 | static struct plat_sci_port scif1_platform_data = { |
81 | .mapbase = 0xf8410000, | ||
82 | .flags = UPF_BOOT_AUTOCONF, | 85 | .flags = UPF_BOOT_AUTOCONF, |
83 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
84 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
85 | .type = PORT_SCIF, | 87 | .type = PORT_SCIF, |
86 | .irqs = SCIx_IRQ_MUXED(92), | 88 | }; |
89 | |||
90 | static struct resource scif1_resources[] = { | ||
91 | DEFINE_RES_MEM(0xf8410000, 0x100), | ||
92 | DEFINE_RES_IRQ(92), | ||
87 | }; | 93 | }; |
88 | 94 | ||
89 | static struct platform_device scif1_device = { | 95 | static struct platform_device scif1_device = { |
90 | .name = "sh-sci", | 96 | .name = "sh-sci", |
91 | .id = 1, | 97 | .id = 1, |
98 | .resource = scif1_resources, | ||
99 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
92 | .dev = { | 100 | .dev = { |
93 | .platform_data = &scif1_platform_data, | 101 | .platform_data = &scif1_platform_data, |
94 | }, | 102 | }, |
95 | }; | 103 | }; |
96 | 104 | ||
97 | static struct plat_sci_port scif2_platform_data = { | 105 | static struct plat_sci_port scif2_platform_data = { |
98 | .mapbase = 0xf8420000, | ||
99 | .flags = UPF_BOOT_AUTOCONF, | 106 | .flags = UPF_BOOT_AUTOCONF, |
100 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 107 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
101 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
102 | .type = PORT_SCIF, | 108 | .type = PORT_SCIF, |
103 | .irqs = SCIx_IRQ_MUXED(96), | 109 | }; |
110 | |||
111 | static struct resource scif2_resources[] = { | ||
112 | DEFINE_RES_MEM(0xf8420000, 0x100), | ||
113 | DEFINE_RES_IRQ(96), | ||
104 | }; | 114 | }; |
105 | 115 | ||
106 | static struct platform_device scif2_device = { | 116 | static struct platform_device scif2_device = { |
107 | .name = "sh-sci", | 117 | .name = "sh-sci", |
108 | .id = 2, | 118 | .id = 2, |
119 | .resource = scif2_resources, | ||
120 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
109 | .dev = { | 121 | .dev = { |
110 | .platform_data = &scif2_platform_data, | 122 | .platform_data = &scif2_platform_data, |
111 | }, | 123 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c index f7f1cf2af302..63e996f9a7ed 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c +++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c | |||
@@ -199,17 +199,21 @@ static struct platform_device mtu2_2_device = { | |||
199 | }; | 199 | }; |
200 | 200 | ||
201 | static struct plat_sci_port scif0_platform_data = { | 201 | static struct plat_sci_port scif0_platform_data = { |
202 | .mapbase = 0xff804000, | ||
203 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
204 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
205 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
206 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
207 | .irqs = SCIx_IRQ_MUXED(220), | 205 | }; |
206 | |||
207 | static struct resource scif0_resources[] = { | ||
208 | DEFINE_RES_MEM(0xff804000, 0x100), | ||
209 | DEFINE_RES_IRQ(220), | ||
208 | }; | 210 | }; |
209 | 211 | ||
210 | static struct platform_device scif0_device = { | 212 | static struct platform_device scif0_device = { |
211 | .name = "sh-sci", | 213 | .name = "sh-sci", |
212 | .id = 0, | 214 | .id = 0, |
215 | .resource = scif0_resources, | ||
216 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
213 | .dev = { | 217 | .dev = { |
214 | .platform_data = &scif0_platform_data, | 218 | .platform_data = &scif0_platform_data, |
215 | }, | 219 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c index 7b84785b8962..2c6874461536 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c | |||
@@ -178,136 +178,168 @@ static DECLARE_INTC_DESC(intc_desc, "sh7201", vectors, groups, | |||
178 | mask_registers, prio_registers, NULL); | 178 | mask_registers, prio_registers, NULL); |
179 | 179 | ||
180 | static struct plat_sci_port scif0_platform_data = { | 180 | static struct plat_sci_port scif0_platform_data = { |
181 | .mapbase = 0xfffe8000, | ||
182 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
184 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
185 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
186 | .irqs = SCIx_IRQ_MUXED(180), | 184 | }; |
185 | |||
186 | static struct resource scif0_resources[] = { | ||
187 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
188 | DEFINE_RES_IRQ(180), | ||
187 | }; | 189 | }; |
188 | 190 | ||
189 | static struct platform_device scif0_device = { | 191 | static struct platform_device scif0_device = { |
190 | .name = "sh-sci", | 192 | .name = "sh-sci", |
191 | .id = 0, | 193 | .id = 0, |
194 | .resource = scif0_resources, | ||
195 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
192 | .dev = { | 196 | .dev = { |
193 | .platform_data = &scif0_platform_data, | 197 | .platform_data = &scif0_platform_data, |
194 | }, | 198 | }, |
195 | }; | 199 | }; |
196 | 200 | ||
197 | static struct plat_sci_port scif1_platform_data = { | 201 | static struct plat_sci_port scif1_platform_data = { |
198 | .mapbase = 0xfffe8800, | ||
199 | .flags = UPF_BOOT_AUTOCONF, | 202 | .flags = UPF_BOOT_AUTOCONF, |
200 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
201 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
202 | .type = PORT_SCIF, | 204 | .type = PORT_SCIF, |
203 | .irqs = SCIx_IRQ_MUXED(184), | 205 | }; |
206 | |||
207 | static struct resource scif1_resources[] = { | ||
208 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
209 | DEFINE_RES_IRQ(184), | ||
204 | }; | 210 | }; |
205 | 211 | ||
206 | static struct platform_device scif1_device = { | 212 | static struct platform_device scif1_device = { |
207 | .name = "sh-sci", | 213 | .name = "sh-sci", |
208 | .id = 1, | 214 | .id = 1, |
215 | .resource = scif1_resources, | ||
216 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
209 | .dev = { | 217 | .dev = { |
210 | .platform_data = &scif1_platform_data, | 218 | .platform_data = &scif1_platform_data, |
211 | }, | 219 | }, |
212 | }; | 220 | }; |
213 | 221 | ||
214 | static struct plat_sci_port scif2_platform_data = { | 222 | static struct plat_sci_port scif2_platform_data = { |
215 | .mapbase = 0xfffe9000, | ||
216 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
217 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 224 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
218 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
219 | .type = PORT_SCIF, | 225 | .type = PORT_SCIF, |
220 | .irqs = SCIx_IRQ_MUXED(188), | 226 | }; |
227 | |||
228 | static struct resource scif2_resources[] = { | ||
229 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
230 | DEFINE_RES_IRQ(188), | ||
221 | }; | 231 | }; |
222 | 232 | ||
223 | static struct platform_device scif2_device = { | 233 | static struct platform_device scif2_device = { |
224 | .name = "sh-sci", | 234 | .name = "sh-sci", |
225 | .id = 2, | 235 | .id = 2, |
236 | .resource = scif2_resources, | ||
237 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
226 | .dev = { | 238 | .dev = { |
227 | .platform_data = &scif2_platform_data, | 239 | .platform_data = &scif2_platform_data, |
228 | }, | 240 | }, |
229 | }; | 241 | }; |
230 | 242 | ||
231 | static struct plat_sci_port scif3_platform_data = { | 243 | static struct plat_sci_port scif3_platform_data = { |
232 | .mapbase = 0xfffe9800, | ||
233 | .flags = UPF_BOOT_AUTOCONF, | 244 | .flags = UPF_BOOT_AUTOCONF, |
234 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 245 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
235 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
236 | .type = PORT_SCIF, | 246 | .type = PORT_SCIF, |
237 | .irqs = SCIx_IRQ_MUXED(192), | 247 | }; |
248 | |||
249 | static struct resource scif3_resources[] = { | ||
250 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
251 | DEFINE_RES_IRQ(192), | ||
238 | }; | 252 | }; |
239 | 253 | ||
240 | static struct platform_device scif3_device = { | 254 | static struct platform_device scif3_device = { |
241 | .name = "sh-sci", | 255 | .name = "sh-sci", |
242 | .id = 3, | 256 | .id = 3, |
257 | .resource = scif3_resources, | ||
258 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
243 | .dev = { | 259 | .dev = { |
244 | .platform_data = &scif3_platform_data, | 260 | .platform_data = &scif3_platform_data, |
245 | }, | 261 | }, |
246 | }; | 262 | }; |
247 | 263 | ||
248 | static struct plat_sci_port scif4_platform_data = { | 264 | static struct plat_sci_port scif4_platform_data = { |
249 | .mapbase = 0xfffea000, | ||
250 | .flags = UPF_BOOT_AUTOCONF, | 265 | .flags = UPF_BOOT_AUTOCONF, |
251 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 266 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
253 | .type = PORT_SCIF, | 267 | .type = PORT_SCIF, |
254 | .irqs = SCIx_IRQ_MUXED(196), | 268 | }; |
269 | |||
270 | static struct resource scif4_resources[] = { | ||
271 | DEFINE_RES_MEM(0xfffea000, 0x100), | ||
272 | DEFINE_RES_IRQ(196), | ||
255 | }; | 273 | }; |
256 | 274 | ||
257 | static struct platform_device scif4_device = { | 275 | static struct platform_device scif4_device = { |
258 | .name = "sh-sci", | 276 | .name = "sh-sci", |
259 | .id = 4, | 277 | .id = 4, |
278 | .resource = scif4_resources, | ||
279 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
260 | .dev = { | 280 | .dev = { |
261 | .platform_data = &scif4_platform_data, | 281 | .platform_data = &scif4_platform_data, |
262 | }, | 282 | }, |
263 | }; | 283 | }; |
264 | 284 | ||
265 | static struct plat_sci_port scif5_platform_data = { | 285 | static struct plat_sci_port scif5_platform_data = { |
266 | .mapbase = 0xfffea800, | ||
267 | .flags = UPF_BOOT_AUTOCONF, | 286 | .flags = UPF_BOOT_AUTOCONF, |
268 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 287 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
269 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
270 | .type = PORT_SCIF, | 288 | .type = PORT_SCIF, |
271 | .irqs = SCIx_IRQ_MUXED(200), | 289 | }; |
290 | |||
291 | static struct resource scif5_resources[] = { | ||
292 | DEFINE_RES_MEM(0xfffea800, 0x100), | ||
293 | DEFINE_RES_IRQ(200), | ||
272 | }; | 294 | }; |
273 | 295 | ||
274 | static struct platform_device scif5_device = { | 296 | static struct platform_device scif5_device = { |
275 | .name = "sh-sci", | 297 | .name = "sh-sci", |
276 | .id = 5, | 298 | .id = 5, |
299 | .resource = scif5_resources, | ||
300 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
277 | .dev = { | 301 | .dev = { |
278 | .platform_data = &scif5_platform_data, | 302 | .platform_data = &scif5_platform_data, |
279 | }, | 303 | }, |
280 | }; | 304 | }; |
281 | 305 | ||
282 | static struct plat_sci_port scif6_platform_data = { | 306 | static struct plat_sci_port scif6_platform_data = { |
283 | .mapbase = 0xfffeb000, | ||
284 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
285 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 308 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
286 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
287 | .type = PORT_SCIF, | 309 | .type = PORT_SCIF, |
288 | .irqs = SCIx_IRQ_MUXED(204), | 310 | }; |
311 | |||
312 | static struct resource scif6_resources[] = { | ||
313 | DEFINE_RES_MEM(0xfffeb000, 0x100), | ||
314 | DEFINE_RES_IRQ(204), | ||
289 | }; | 315 | }; |
290 | 316 | ||
291 | static struct platform_device scif6_device = { | 317 | static struct platform_device scif6_device = { |
292 | .name = "sh-sci", | 318 | .name = "sh-sci", |
293 | .id = 6, | 319 | .id = 6, |
320 | .resource = scif6_resources, | ||
321 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
294 | .dev = { | 322 | .dev = { |
295 | .platform_data = &scif6_platform_data, | 323 | .platform_data = &scif6_platform_data, |
296 | }, | 324 | }, |
297 | }; | 325 | }; |
298 | 326 | ||
299 | static struct plat_sci_port scif7_platform_data = { | 327 | static struct plat_sci_port scif7_platform_data = { |
300 | .mapbase = 0xfffeb800, | ||
301 | .flags = UPF_BOOT_AUTOCONF, | 328 | .flags = UPF_BOOT_AUTOCONF, |
302 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 329 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
303 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
304 | .type = PORT_SCIF, | 330 | .type = PORT_SCIF, |
305 | .irqs = SCIx_IRQ_MUXED(208), | 331 | }; |
332 | |||
333 | static struct resource scif7_resources[] = { | ||
334 | DEFINE_RES_MEM(0xfffeb800, 0x100), | ||
335 | DEFINE_RES_IRQ(208), | ||
306 | }; | 336 | }; |
307 | 337 | ||
308 | static struct platform_device scif7_device = { | 338 | static struct platform_device scif7_device = { |
309 | .name = "sh-sci", | 339 | .name = "sh-sci", |
310 | .id = 7, | 340 | .id = 7, |
341 | .resource = scif7_resources, | ||
342 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
311 | .dev = { | 343 | .dev = { |
312 | .platform_data = &scif7_platform_data, | 344 | .platform_data = &scif7_platform_data, |
313 | }, | 345 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c index bfc33f6a28c3..d55a0f30ada3 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c | |||
@@ -174,76 +174,92 @@ static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups, | |||
174 | mask_registers, prio_registers, NULL); | 174 | mask_registers, prio_registers, NULL); |
175 | 175 | ||
176 | static struct plat_sci_port scif0_platform_data = { | 176 | static struct plat_sci_port scif0_platform_data = { |
177 | .mapbase = 0xfffe8000, | ||
178 | .flags = UPF_BOOT_AUTOCONF, | 177 | .flags = UPF_BOOT_AUTOCONF, |
179 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 178 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
180 | SCSCR_REIE, | 179 | SCSCR_REIE, |
181 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
182 | .type = PORT_SCIF, | 180 | .type = PORT_SCIF, |
183 | .irqs = SCIx_IRQ_MUXED(192), | ||
184 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 181 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
185 | }; | 182 | }; |
186 | 183 | ||
184 | static struct resource scif0_resources[] = { | ||
185 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
186 | DEFINE_RES_IRQ(192), | ||
187 | }; | ||
188 | |||
187 | static struct platform_device scif0_device = { | 189 | static struct platform_device scif0_device = { |
188 | .name = "sh-sci", | 190 | .name = "sh-sci", |
189 | .id = 0, | 191 | .id = 0, |
192 | .resource = scif0_resources, | ||
193 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
190 | .dev = { | 194 | .dev = { |
191 | .platform_data = &scif0_platform_data, | 195 | .platform_data = &scif0_platform_data, |
192 | }, | 196 | }, |
193 | }; | 197 | }; |
194 | 198 | ||
195 | static struct plat_sci_port scif1_platform_data = { | 199 | static struct plat_sci_port scif1_platform_data = { |
196 | .mapbase = 0xfffe8800, | ||
197 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
198 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 201 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
199 | SCSCR_REIE, | 202 | SCSCR_REIE, |
200 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
201 | .type = PORT_SCIF, | 203 | .type = PORT_SCIF, |
202 | .irqs = SCIx_IRQ_MUXED(196), | ||
203 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 204 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
204 | }; | 205 | }; |
205 | 206 | ||
207 | static struct resource scif1_resources[] = { | ||
208 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
209 | DEFINE_RES_IRQ(196), | ||
210 | }; | ||
211 | |||
206 | static struct platform_device scif1_device = { | 212 | static struct platform_device scif1_device = { |
207 | .name = "sh-sci", | 213 | .name = "sh-sci", |
208 | .id = 1, | 214 | .id = 1, |
215 | .resource = scif1_resources, | ||
216 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
209 | .dev = { | 217 | .dev = { |
210 | .platform_data = &scif1_platform_data, | 218 | .platform_data = &scif1_platform_data, |
211 | }, | 219 | }, |
212 | }; | 220 | }; |
213 | 221 | ||
214 | static struct plat_sci_port scif2_platform_data = { | 222 | static struct plat_sci_port scif2_platform_data = { |
215 | .mapbase = 0xfffe9000, | ||
216 | .flags = UPF_BOOT_AUTOCONF, | 223 | .flags = UPF_BOOT_AUTOCONF, |
217 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 224 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
218 | SCSCR_REIE, | 225 | SCSCR_REIE, |
219 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
220 | .type = PORT_SCIF, | 226 | .type = PORT_SCIF, |
221 | .irqs = SCIx_IRQ_MUXED(200), | ||
222 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 227 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
223 | }; | 228 | }; |
224 | 229 | ||
230 | static struct resource scif2_resources[] = { | ||
231 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
232 | DEFINE_RES_IRQ(200), | ||
233 | }; | ||
234 | |||
225 | static struct platform_device scif2_device = { | 235 | static struct platform_device scif2_device = { |
226 | .name = "sh-sci", | 236 | .name = "sh-sci", |
227 | .id = 2, | 237 | .id = 2, |
238 | .resource = scif2_resources, | ||
239 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
228 | .dev = { | 240 | .dev = { |
229 | .platform_data = &scif2_platform_data, | 241 | .platform_data = &scif2_platform_data, |
230 | }, | 242 | }, |
231 | }; | 243 | }; |
232 | 244 | ||
233 | static struct plat_sci_port scif3_platform_data = { | 245 | static struct plat_sci_port scif3_platform_data = { |
234 | .mapbase = 0xfffe9800, | ||
235 | .flags = UPF_BOOT_AUTOCONF, | 246 | .flags = UPF_BOOT_AUTOCONF, |
236 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 247 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
237 | SCSCR_REIE, | 248 | SCSCR_REIE, |
238 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
239 | .type = PORT_SCIF, | 249 | .type = PORT_SCIF, |
240 | .irqs = SCIx_IRQ_MUXED(204), | ||
241 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 250 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
242 | }; | 251 | }; |
243 | 252 | ||
253 | static struct resource scif3_resources[] = { | ||
254 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
255 | DEFINE_RES_IRQ(204), | ||
256 | }; | ||
257 | |||
244 | static struct platform_device scif3_device = { | 258 | static struct platform_device scif3_device = { |
245 | .name = "sh-sci", | 259 | .name = "sh-sci", |
246 | .id = 3, | 260 | .id = 3, |
261 | .resource = scif3_resources, | ||
262 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
247 | .dev = { | 263 | .dev = { |
248 | .platform_data = &scif3_platform_data, | 264 | .platform_data = &scif3_platform_data, |
249 | }, | 265 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c index a5010741de85..241e745e3ced 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c | |||
@@ -134,68 +134,84 @@ static DECLARE_INTC_DESC(intc_desc, "sh7206", vectors, groups, | |||
134 | mask_registers, prio_registers, NULL); | 134 | mask_registers, prio_registers, NULL); |
135 | 135 | ||
136 | static struct plat_sci_port scif0_platform_data = { | 136 | static struct plat_sci_port scif0_platform_data = { |
137 | .mapbase = 0xfffe8000, | ||
138 | .flags = UPF_BOOT_AUTOCONF, | 137 | .flags = UPF_BOOT_AUTOCONF, |
139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 138 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
140 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
141 | .type = PORT_SCIF, | 139 | .type = PORT_SCIF, |
142 | .irqs = SCIx_IRQ_MUXED(240), | 140 | }; |
141 | |||
142 | static struct resource scif0_resources[] = { | ||
143 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
144 | DEFINE_RES_IRQ(240), | ||
143 | }; | 145 | }; |
144 | 146 | ||
145 | static struct platform_device scif0_device = { | 147 | static struct platform_device scif0_device = { |
146 | .name = "sh-sci", | 148 | .name = "sh-sci", |
147 | .id = 0, | 149 | .id = 0, |
150 | .resource = scif0_resources, | ||
151 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
148 | .dev = { | 152 | .dev = { |
149 | .platform_data = &scif0_platform_data, | 153 | .platform_data = &scif0_platform_data, |
150 | }, | 154 | }, |
151 | }; | 155 | }; |
152 | 156 | ||
153 | static struct plat_sci_port scif1_platform_data = { | 157 | static struct plat_sci_port scif1_platform_data = { |
154 | .mapbase = 0xfffe8800, | ||
155 | .flags = UPF_BOOT_AUTOCONF, | 158 | .flags = UPF_BOOT_AUTOCONF, |
156 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 159 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
157 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
158 | .type = PORT_SCIF, | 160 | .type = PORT_SCIF, |
159 | .irqs = SCIx_IRQ_MUXED(244), | 161 | }; |
162 | |||
163 | static struct resource scif1_resources[] = { | ||
164 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
165 | DEFINE_RES_IRQ(244), | ||
160 | }; | 166 | }; |
161 | 167 | ||
162 | static struct platform_device scif1_device = { | 168 | static struct platform_device scif1_device = { |
163 | .name = "sh-sci", | 169 | .name = "sh-sci", |
164 | .id = 1, | 170 | .id = 1, |
171 | .resource = scif1_resources, | ||
172 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
165 | .dev = { | 173 | .dev = { |
166 | .platform_data = &scif1_platform_data, | 174 | .platform_data = &scif1_platform_data, |
167 | }, | 175 | }, |
168 | }; | 176 | }; |
169 | 177 | ||
170 | static struct plat_sci_port scif2_platform_data = { | 178 | static struct plat_sci_port scif2_platform_data = { |
171 | .mapbase = 0xfffe9000, | ||
172 | .flags = UPF_BOOT_AUTOCONF, | 179 | .flags = UPF_BOOT_AUTOCONF, |
173 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 180 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
174 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
175 | .type = PORT_SCIF, | 181 | .type = PORT_SCIF, |
176 | .irqs = SCIx_IRQ_MUXED(248), | 182 | }; |
183 | |||
184 | static struct resource scif2_resources[] = { | ||
185 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
186 | DEFINE_RES_IRQ(248), | ||
177 | }; | 187 | }; |
178 | 188 | ||
179 | static struct platform_device scif2_device = { | 189 | static struct platform_device scif2_device = { |
180 | .name = "sh-sci", | 190 | .name = "sh-sci", |
181 | .id = 2, | 191 | .id = 2, |
192 | .resource = scif2_resources, | ||
193 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
182 | .dev = { | 194 | .dev = { |
183 | .platform_data = &scif2_platform_data, | 195 | .platform_data = &scif2_platform_data, |
184 | }, | 196 | }, |
185 | }; | 197 | }; |
186 | 198 | ||
187 | static struct plat_sci_port scif3_platform_data = { | 199 | static struct plat_sci_port scif3_platform_data = { |
188 | .mapbase = 0xfffe9800, | ||
189 | .flags = UPF_BOOT_AUTOCONF, | 200 | .flags = UPF_BOOT_AUTOCONF, |
190 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 201 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
191 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
192 | .type = PORT_SCIF, | 202 | .type = PORT_SCIF, |
193 | .irqs = SCIx_IRQ_MUXED(252), | 203 | }; |
204 | |||
205 | static struct resource scif3_resources[] = { | ||
206 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
207 | DEFINE_RES_IRQ(252), | ||
194 | }; | 208 | }; |
195 | 209 | ||
196 | static struct platform_device scif3_device = { | 210 | static struct platform_device scif3_device = { |
197 | .name = "sh-sci", | 211 | .name = "sh-sci", |
198 | .id = 3, | 212 | .id = 3, |
213 | .resource = scif3_resources, | ||
214 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
199 | .dev = { | 215 | .dev = { |
200 | .platform_data = &scif3_platform_data, | 216 | .platform_data = &scif3_platform_data, |
201 | }, | 217 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c index ce5c1b5aebfa..ad5b0f429882 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c | |||
@@ -226,152 +226,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups, | |||
226 | mask_registers, prio_registers, NULL); | 226 | mask_registers, prio_registers, NULL); |
227 | 227 | ||
228 | static struct plat_sci_port scif0_platform_data = { | 228 | static struct plat_sci_port scif0_platform_data = { |
229 | .mapbase = 0xfffe8000, | ||
230 | .flags = UPF_BOOT_AUTOCONF, | 229 | .flags = UPF_BOOT_AUTOCONF, |
231 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 230 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
232 | SCSCR_REIE | SCSCR_TOIE, | 231 | SCSCR_REIE | SCSCR_TOIE, |
233 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
234 | .type = PORT_SCIF, | 232 | .type = PORT_SCIF, |
235 | .irqs = { 233, 234, 235, 232 }, | ||
236 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 233 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
237 | }; | 234 | }; |
238 | 235 | ||
236 | static struct resource scif0_resources[] = { | ||
237 | DEFINE_RES_MEM(0xfffe8000, 0x100), | ||
238 | DEFINE_RES_IRQ(233), | ||
239 | DEFINE_RES_IRQ(234), | ||
240 | DEFINE_RES_IRQ(235), | ||
241 | DEFINE_RES_IRQ(232), | ||
242 | }; | ||
243 | |||
239 | static struct platform_device scif0_device = { | 244 | static struct platform_device scif0_device = { |
240 | .name = "sh-sci", | 245 | .name = "sh-sci", |
241 | .id = 0, | 246 | .id = 0, |
247 | .resource = scif0_resources, | ||
248 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
242 | .dev = { | 249 | .dev = { |
243 | .platform_data = &scif0_platform_data, | 250 | .platform_data = &scif0_platform_data, |
244 | }, | 251 | }, |
245 | }; | 252 | }; |
246 | 253 | ||
247 | static struct plat_sci_port scif1_platform_data = { | 254 | static struct plat_sci_port scif1_platform_data = { |
248 | .mapbase = 0xfffe8800, | ||
249 | .flags = UPF_BOOT_AUTOCONF, | 255 | .flags = UPF_BOOT_AUTOCONF, |
250 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 256 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
251 | SCSCR_REIE | SCSCR_TOIE, | 257 | SCSCR_REIE | SCSCR_TOIE, |
252 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
253 | .type = PORT_SCIF, | 258 | .type = PORT_SCIF, |
254 | .irqs = { 237, 238, 239, 236 }, | ||
255 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 259 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
256 | }; | 260 | }; |
257 | 261 | ||
262 | static struct resource scif1_resources[] = { | ||
263 | DEFINE_RES_MEM(0xfffe8800, 0x100), | ||
264 | DEFINE_RES_IRQ(237), | ||
265 | DEFINE_RES_IRQ(238), | ||
266 | DEFINE_RES_IRQ(239), | ||
267 | DEFINE_RES_IRQ(236), | ||
268 | }; | ||
269 | |||
258 | static struct platform_device scif1_device = { | 270 | static struct platform_device scif1_device = { |
259 | .name = "sh-sci", | 271 | .name = "sh-sci", |
260 | .id = 1, | 272 | .id = 1, |
273 | .resource = scif1_resources, | ||
274 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
261 | .dev = { | 275 | .dev = { |
262 | .platform_data = &scif1_platform_data, | 276 | .platform_data = &scif1_platform_data, |
263 | }, | 277 | }, |
264 | }; | 278 | }; |
265 | 279 | ||
266 | static struct plat_sci_port scif2_platform_data = { | 280 | static struct plat_sci_port scif2_platform_data = { |
267 | .mapbase = 0xfffe9000, | ||
268 | .flags = UPF_BOOT_AUTOCONF, | 281 | .flags = UPF_BOOT_AUTOCONF, |
269 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 282 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
270 | SCSCR_REIE | SCSCR_TOIE, | 283 | SCSCR_REIE | SCSCR_TOIE, |
271 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
272 | .type = PORT_SCIF, | 284 | .type = PORT_SCIF, |
273 | .irqs = { 241, 242, 243, 240 }, | ||
274 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 285 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
275 | }; | 286 | }; |
276 | 287 | ||
288 | static struct resource scif2_resources[] = { | ||
289 | DEFINE_RES_MEM(0xfffe9000, 0x100), | ||
290 | DEFINE_RES_IRQ(241), | ||
291 | DEFINE_RES_IRQ(242), | ||
292 | DEFINE_RES_IRQ(243), | ||
293 | DEFINE_RES_IRQ(240), | ||
294 | }; | ||
295 | |||
277 | static struct platform_device scif2_device = { | 296 | static struct platform_device scif2_device = { |
278 | .name = "sh-sci", | 297 | .name = "sh-sci", |
279 | .id = 2, | 298 | .id = 2, |
299 | .resource = scif2_resources, | ||
300 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
280 | .dev = { | 301 | .dev = { |
281 | .platform_data = &scif2_platform_data, | 302 | .platform_data = &scif2_platform_data, |
282 | }, | 303 | }, |
283 | }; | 304 | }; |
284 | 305 | ||
285 | static struct plat_sci_port scif3_platform_data = { | 306 | static struct plat_sci_port scif3_platform_data = { |
286 | .mapbase = 0xfffe9800, | ||
287 | .flags = UPF_BOOT_AUTOCONF, | 307 | .flags = UPF_BOOT_AUTOCONF, |
288 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 308 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
289 | SCSCR_REIE | SCSCR_TOIE, | 309 | SCSCR_REIE | SCSCR_TOIE, |
290 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
291 | .type = PORT_SCIF, | 310 | .type = PORT_SCIF, |
292 | .irqs = { 245, 246, 247, 244 }, | ||
293 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 311 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
294 | }; | 312 | }; |
295 | 313 | ||
314 | static struct resource scif3_resources[] = { | ||
315 | DEFINE_RES_MEM(0xfffe9800, 0x100), | ||
316 | DEFINE_RES_IRQ(245), | ||
317 | DEFINE_RES_IRQ(246), | ||
318 | DEFINE_RES_IRQ(247), | ||
319 | DEFINE_RES_IRQ(244), | ||
320 | }; | ||
321 | |||
296 | static struct platform_device scif3_device = { | 322 | static struct platform_device scif3_device = { |
297 | .name = "sh-sci", | 323 | .name = "sh-sci", |
298 | .id = 3, | 324 | .id = 3, |
325 | .resource = scif3_resources, | ||
326 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
299 | .dev = { | 327 | .dev = { |
300 | .platform_data = &scif3_platform_data, | 328 | .platform_data = &scif3_platform_data, |
301 | }, | 329 | }, |
302 | }; | 330 | }; |
303 | 331 | ||
304 | static struct plat_sci_port scif4_platform_data = { | 332 | static struct plat_sci_port scif4_platform_data = { |
305 | .mapbase = 0xfffea000, | ||
306 | .flags = UPF_BOOT_AUTOCONF, | 333 | .flags = UPF_BOOT_AUTOCONF, |
307 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 334 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
308 | SCSCR_REIE | SCSCR_TOIE, | 335 | SCSCR_REIE | SCSCR_TOIE, |
309 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
310 | .type = PORT_SCIF, | 336 | .type = PORT_SCIF, |
311 | .irqs = { 249, 250, 251, 248 }, | ||
312 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 337 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
313 | }; | 338 | }; |
314 | 339 | ||
340 | static struct resource scif4_resources[] = { | ||
341 | DEFINE_RES_MEM(0xfffea000, 0x100), | ||
342 | DEFINE_RES_IRQ(249), | ||
343 | DEFINE_RES_IRQ(250), | ||
344 | DEFINE_RES_IRQ(251), | ||
345 | DEFINE_RES_IRQ(248), | ||
346 | }; | ||
347 | |||
315 | static struct platform_device scif4_device = { | 348 | static struct platform_device scif4_device = { |
316 | .name = "sh-sci", | 349 | .name = "sh-sci", |
317 | .id = 4, | 350 | .id = 4, |
351 | .resource = scif4_resources, | ||
352 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
318 | .dev = { | 353 | .dev = { |
319 | .platform_data = &scif4_platform_data, | 354 | .platform_data = &scif4_platform_data, |
320 | }, | 355 | }, |
321 | }; | 356 | }; |
322 | 357 | ||
323 | static struct plat_sci_port scif5_platform_data = { | 358 | static struct plat_sci_port scif5_platform_data = { |
324 | .mapbase = 0xfffea800, | ||
325 | .flags = UPF_BOOT_AUTOCONF, | 359 | .flags = UPF_BOOT_AUTOCONF, |
326 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 360 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
327 | SCSCR_REIE | SCSCR_TOIE, | 361 | SCSCR_REIE | SCSCR_TOIE, |
328 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
329 | .type = PORT_SCIF, | 362 | .type = PORT_SCIF, |
330 | .irqs = { 253, 254, 255, 252 }, | ||
331 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 363 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
332 | }; | 364 | }; |
333 | 365 | ||
366 | static struct resource scif5_resources[] = { | ||
367 | DEFINE_RES_MEM(0xfffea800, 0x100), | ||
368 | DEFINE_RES_IRQ(253), | ||
369 | DEFINE_RES_IRQ(254), | ||
370 | DEFINE_RES_IRQ(255), | ||
371 | DEFINE_RES_IRQ(252), | ||
372 | }; | ||
373 | |||
334 | static struct platform_device scif5_device = { | 374 | static struct platform_device scif5_device = { |
335 | .name = "sh-sci", | 375 | .name = "sh-sci", |
336 | .id = 5, | 376 | .id = 5, |
377 | .resource = scif5_resources, | ||
378 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
337 | .dev = { | 379 | .dev = { |
338 | .platform_data = &scif5_platform_data, | 380 | .platform_data = &scif5_platform_data, |
339 | }, | 381 | }, |
340 | }; | 382 | }; |
341 | 383 | ||
342 | static struct plat_sci_port scif6_platform_data = { | 384 | static struct plat_sci_port scif6_platform_data = { |
343 | .mapbase = 0xfffeb000, | ||
344 | .flags = UPF_BOOT_AUTOCONF, | 385 | .flags = UPF_BOOT_AUTOCONF, |
345 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 386 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
346 | SCSCR_REIE | SCSCR_TOIE, | 387 | SCSCR_REIE | SCSCR_TOIE, |
347 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
348 | .type = PORT_SCIF, | 388 | .type = PORT_SCIF, |
349 | .irqs = { 257, 258, 259, 256 }, | ||
350 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 389 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
351 | }; | 390 | }; |
352 | 391 | ||
392 | static struct resource scif6_resources[] = { | ||
393 | DEFINE_RES_MEM(0xfffeb000, 0x100), | ||
394 | DEFINE_RES_IRQ(257), | ||
395 | DEFINE_RES_IRQ(258), | ||
396 | DEFINE_RES_IRQ(259), | ||
397 | DEFINE_RES_IRQ(256), | ||
398 | }; | ||
399 | |||
353 | static struct platform_device scif6_device = { | 400 | static struct platform_device scif6_device = { |
354 | .name = "sh-sci", | 401 | .name = "sh-sci", |
355 | .id = 6, | 402 | .id = 6, |
403 | .resource = scif6_resources, | ||
404 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
356 | .dev = { | 405 | .dev = { |
357 | .platform_data = &scif6_platform_data, | 406 | .platform_data = &scif6_platform_data, |
358 | }, | 407 | }, |
359 | }; | 408 | }; |
360 | 409 | ||
361 | static struct plat_sci_port scif7_platform_data = { | 410 | static struct plat_sci_port scif7_platform_data = { |
362 | .mapbase = 0xfffeb800, | ||
363 | .flags = UPF_BOOT_AUTOCONF, | 411 | .flags = UPF_BOOT_AUTOCONF, |
364 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 412 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
365 | SCSCR_REIE | SCSCR_TOIE, | 413 | SCSCR_REIE | SCSCR_TOIE, |
366 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
367 | .type = PORT_SCIF, | 414 | .type = PORT_SCIF, |
368 | .irqs = { 261, 262, 263, 260 }, | ||
369 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 415 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
370 | }; | 416 | }; |
371 | 417 | ||
418 | static struct resource scif7_resources[] = { | ||
419 | DEFINE_RES_MEM(0xfffeb800, 0x100), | ||
420 | DEFINE_RES_IRQ(261), | ||
421 | DEFINE_RES_IRQ(262), | ||
422 | DEFINE_RES_IRQ(263), | ||
423 | DEFINE_RES_IRQ(260), | ||
424 | }; | ||
425 | |||
372 | static struct platform_device scif7_device = { | 426 | static struct platform_device scif7_device = { |
373 | .name = "sh-sci", | 427 | .name = "sh-sci", |
374 | .id = 7, | 428 | .id = 7, |
429 | .resource = scif7_resources, | ||
430 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
375 | .dev = { | 431 | .dev = { |
376 | .platform_data = &scif7_platform_data, | 432 | .platform_data = &scif7_platform_data, |
377 | }, | 433 | }, |
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c index e82ae9d8d3bc..3995119f65dc 100644 --- a/arch/sh/kernel/cpu/sh2a/setup-sh7269.c +++ b/arch/sh/kernel/cpu/sh2a/setup-sh7269.c | |||
@@ -248,152 +248,208 @@ static DECLARE_INTC_DESC(intc_desc, "sh7269", vectors, groups, | |||
248 | mask_registers, prio_registers, NULL); | 248 | mask_registers, prio_registers, NULL); |
249 | 249 | ||
250 | static struct plat_sci_port scif0_platform_data = { | 250 | static struct plat_sci_port scif0_platform_data = { |
251 | .mapbase = 0xe8007000, | ||
252 | .flags = UPF_BOOT_AUTOCONF, | 251 | .flags = UPF_BOOT_AUTOCONF, |
253 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 252 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
254 | SCSCR_REIE | SCSCR_TOIE, | 253 | SCSCR_REIE | SCSCR_TOIE, |
255 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
256 | .type = PORT_SCIF, | 254 | .type = PORT_SCIF, |
257 | .irqs = { 259, 260, 261, 258 }, | ||
258 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 255 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
259 | }; | 256 | }; |
260 | 257 | ||
258 | static struct resource scif0_resources[] = { | ||
259 | DEFINE_RES_MEM(0xe8007000, 0x100), | ||
260 | DEFINE_RES_IRQ(259), | ||
261 | DEFINE_RES_IRQ(260), | ||
262 | DEFINE_RES_IRQ(261), | ||
263 | DEFINE_RES_IRQ(258), | ||
264 | }; | ||
265 | |||
261 | static struct platform_device scif0_device = { | 266 | static struct platform_device scif0_device = { |
262 | .name = "sh-sci", | 267 | .name = "sh-sci", |
263 | .id = 0, | 268 | .id = 0, |
269 | .resource = scif0_resources, | ||
270 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
264 | .dev = { | 271 | .dev = { |
265 | .platform_data = &scif0_platform_data, | 272 | .platform_data = &scif0_platform_data, |
266 | }, | 273 | }, |
267 | }; | 274 | }; |
268 | 275 | ||
269 | static struct plat_sci_port scif1_platform_data = { | 276 | static struct plat_sci_port scif1_platform_data = { |
270 | .mapbase = 0xe8007800, | ||
271 | .flags = UPF_BOOT_AUTOCONF, | 277 | .flags = UPF_BOOT_AUTOCONF, |
272 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 278 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
273 | SCSCR_REIE | SCSCR_TOIE, | 279 | SCSCR_REIE | SCSCR_TOIE, |
274 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
275 | .type = PORT_SCIF, | 280 | .type = PORT_SCIF, |
276 | .irqs = { 263, 264, 265, 262 }, | ||
277 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 281 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
278 | }; | 282 | }; |
279 | 283 | ||
284 | static struct resource scif1_resources[] = { | ||
285 | DEFINE_RES_MEM(0xe8007800, 0x100), | ||
286 | DEFINE_RES_IRQ(263), | ||
287 | DEFINE_RES_IRQ(264), | ||
288 | DEFINE_RES_IRQ(265), | ||
289 | DEFINE_RES_IRQ(262), | ||
290 | }; | ||
291 | |||
280 | static struct platform_device scif1_device = { | 292 | static struct platform_device scif1_device = { |
281 | .name = "sh-sci", | 293 | .name = "sh-sci", |
282 | .id = 1, | 294 | .id = 1, |
295 | .resource = scif1_resources, | ||
296 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
283 | .dev = { | 297 | .dev = { |
284 | .platform_data = &scif1_platform_data, | 298 | .platform_data = &scif1_platform_data, |
285 | }, | 299 | }, |
286 | }; | 300 | }; |
287 | 301 | ||
288 | static struct plat_sci_port scif2_platform_data = { | 302 | static struct plat_sci_port scif2_platform_data = { |
289 | .mapbase = 0xe8008000, | ||
290 | .flags = UPF_BOOT_AUTOCONF, | 303 | .flags = UPF_BOOT_AUTOCONF, |
291 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 304 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
292 | SCSCR_REIE | SCSCR_TOIE, | 305 | SCSCR_REIE | SCSCR_TOIE, |
293 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
294 | .type = PORT_SCIF, | 306 | .type = PORT_SCIF, |
295 | .irqs = { 267, 268, 269, 266 }, | ||
296 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 307 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
297 | }; | 308 | }; |
298 | 309 | ||
310 | static struct resource scif2_resources[] = { | ||
311 | DEFINE_RES_MEM(0xe8008000, 0x100), | ||
312 | DEFINE_RES_IRQ(267), | ||
313 | DEFINE_RES_IRQ(268), | ||
314 | DEFINE_RES_IRQ(269), | ||
315 | DEFINE_RES_IRQ(266), | ||
316 | }; | ||
317 | |||
299 | static struct platform_device scif2_device = { | 318 | static struct platform_device scif2_device = { |
300 | .name = "sh-sci", | 319 | .name = "sh-sci", |
301 | .id = 2, | 320 | .id = 2, |
321 | .resource = scif2_resources, | ||
322 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
302 | .dev = { | 323 | .dev = { |
303 | .platform_data = &scif2_platform_data, | 324 | .platform_data = &scif2_platform_data, |
304 | }, | 325 | }, |
305 | }; | 326 | }; |
306 | 327 | ||
307 | static struct plat_sci_port scif3_platform_data = { | 328 | static struct plat_sci_port scif3_platform_data = { |
308 | .mapbase = 0xe8008800, | ||
309 | .flags = UPF_BOOT_AUTOCONF, | 329 | .flags = UPF_BOOT_AUTOCONF, |
310 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 330 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
311 | SCSCR_REIE | SCSCR_TOIE, | 331 | SCSCR_REIE | SCSCR_TOIE, |
312 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
313 | .type = PORT_SCIF, | 332 | .type = PORT_SCIF, |
314 | .irqs = { 271, 272, 273, 270 }, | ||
315 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 333 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
316 | }; | 334 | }; |
317 | 335 | ||
336 | static struct resource scif3_resources[] = { | ||
337 | DEFINE_RES_MEM(0xe8008800, 0x100), | ||
338 | DEFINE_RES_IRQ(271), | ||
339 | DEFINE_RES_IRQ(272), | ||
340 | DEFINE_RES_IRQ(273), | ||
341 | DEFINE_RES_IRQ(270), | ||
342 | }; | ||
343 | |||
318 | static struct platform_device scif3_device = { | 344 | static struct platform_device scif3_device = { |
319 | .name = "sh-sci", | 345 | .name = "sh-sci", |
320 | .id = 3, | 346 | .id = 3, |
347 | .resource = scif3_resources, | ||
348 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
321 | .dev = { | 349 | .dev = { |
322 | .platform_data = &scif3_platform_data, | 350 | .platform_data = &scif3_platform_data, |
323 | }, | 351 | }, |
324 | }; | 352 | }; |
325 | 353 | ||
326 | static struct plat_sci_port scif4_platform_data = { | 354 | static struct plat_sci_port scif4_platform_data = { |
327 | .mapbase = 0xe8009000, | ||
328 | .flags = UPF_BOOT_AUTOCONF, | 355 | .flags = UPF_BOOT_AUTOCONF, |
329 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 356 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
330 | SCSCR_REIE | SCSCR_TOIE, | 357 | SCSCR_REIE | SCSCR_TOIE, |
331 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
332 | .type = PORT_SCIF, | 358 | .type = PORT_SCIF, |
333 | .irqs = { 275, 276, 277, 274 }, | ||
334 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 359 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
335 | }; | 360 | }; |
336 | 361 | ||
362 | static struct resource scif4_resources[] = { | ||
363 | DEFINE_RES_MEM(0xe8009000, 0x100), | ||
364 | DEFINE_RES_IRQ(275), | ||
365 | DEFINE_RES_IRQ(276), | ||
366 | DEFINE_RES_IRQ(277), | ||
367 | DEFINE_RES_IRQ(274), | ||
368 | }; | ||
369 | |||
337 | static struct platform_device scif4_device = { | 370 | static struct platform_device scif4_device = { |
338 | .name = "sh-sci", | 371 | .name = "sh-sci", |
339 | .id = 4, | 372 | .id = 4, |
373 | .resource = scif4_resources, | ||
374 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
340 | .dev = { | 375 | .dev = { |
341 | .platform_data = &scif4_platform_data, | 376 | .platform_data = &scif4_platform_data, |
342 | }, | 377 | }, |
343 | }; | 378 | }; |
344 | 379 | ||
345 | static struct plat_sci_port scif5_platform_data = { | 380 | static struct plat_sci_port scif5_platform_data = { |
346 | .mapbase = 0xe8009800, | ||
347 | .flags = UPF_BOOT_AUTOCONF, | 381 | .flags = UPF_BOOT_AUTOCONF, |
348 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 382 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
349 | SCSCR_REIE | SCSCR_TOIE, | 383 | SCSCR_REIE | SCSCR_TOIE, |
350 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
351 | .type = PORT_SCIF, | 384 | .type = PORT_SCIF, |
352 | .irqs = { 279, 280, 281, 278 }, | ||
353 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 385 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
354 | }; | 386 | }; |
355 | 387 | ||
388 | static struct resource scif5_resources[] = { | ||
389 | DEFINE_RES_MEM(0xe8009800, 0x100), | ||
390 | DEFINE_RES_IRQ(279), | ||
391 | DEFINE_RES_IRQ(280), | ||
392 | DEFINE_RES_IRQ(281), | ||
393 | DEFINE_RES_IRQ(278), | ||
394 | }; | ||
395 | |||
356 | static struct platform_device scif5_device = { | 396 | static struct platform_device scif5_device = { |
357 | .name = "sh-sci", | 397 | .name = "sh-sci", |
358 | .id = 5, | 398 | .id = 5, |
399 | .resource = scif5_resources, | ||
400 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
359 | .dev = { | 401 | .dev = { |
360 | .platform_data = &scif5_platform_data, | 402 | .platform_data = &scif5_platform_data, |
361 | }, | 403 | }, |
362 | }; | 404 | }; |
363 | 405 | ||
364 | static struct plat_sci_port scif6_platform_data = { | 406 | static struct plat_sci_port scif6_platform_data = { |
365 | .mapbase = 0xe800a000, | ||
366 | .flags = UPF_BOOT_AUTOCONF, | 407 | .flags = UPF_BOOT_AUTOCONF, |
367 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 408 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
368 | SCSCR_REIE | SCSCR_TOIE, | 409 | SCSCR_REIE | SCSCR_TOIE, |
369 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
370 | .type = PORT_SCIF, | 410 | .type = PORT_SCIF, |
371 | .irqs = { 283, 284, 285, 282 }, | ||
372 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 411 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
373 | }; | 412 | }; |
374 | 413 | ||
414 | static struct resource scif6_resources[] = { | ||
415 | DEFINE_RES_MEM(0xe800a000, 0x100), | ||
416 | DEFINE_RES_IRQ(283), | ||
417 | DEFINE_RES_IRQ(284), | ||
418 | DEFINE_RES_IRQ(285), | ||
419 | DEFINE_RES_IRQ(282), | ||
420 | }; | ||
421 | |||
375 | static struct platform_device scif6_device = { | 422 | static struct platform_device scif6_device = { |
376 | .name = "sh-sci", | 423 | .name = "sh-sci", |
377 | .id = 6, | 424 | .id = 6, |
425 | .resource = scif6_resources, | ||
426 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
378 | .dev = { | 427 | .dev = { |
379 | .platform_data = &scif6_platform_data, | 428 | .platform_data = &scif6_platform_data, |
380 | }, | 429 | }, |
381 | }; | 430 | }; |
382 | 431 | ||
383 | static struct plat_sci_port scif7_platform_data = { | 432 | static struct plat_sci_port scif7_platform_data = { |
384 | .mapbase = 0xe800a800, | ||
385 | .flags = UPF_BOOT_AUTOCONF, | 433 | .flags = UPF_BOOT_AUTOCONF, |
386 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | | 434 | .scscr = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | |
387 | SCSCR_REIE | SCSCR_TOIE, | 435 | SCSCR_REIE | SCSCR_TOIE, |
388 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
389 | .type = PORT_SCIF, | 436 | .type = PORT_SCIF, |
390 | .irqs = { 287, 288, 289, 286 }, | ||
391 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, | 437 | .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE, |
392 | }; | 438 | }; |
393 | 439 | ||
440 | static struct resource scif7_resources[] = { | ||
441 | DEFINE_RES_MEM(0xe800a800, 0x100), | ||
442 | DEFINE_RES_IRQ(287), | ||
443 | DEFINE_RES_IRQ(288), | ||
444 | DEFINE_RES_IRQ(289), | ||
445 | DEFINE_RES_IRQ(286), | ||
446 | }; | ||
447 | |||
394 | static struct platform_device scif7_device = { | 448 | static struct platform_device scif7_device = { |
395 | .name = "sh-sci", | 449 | .name = "sh-sci", |
396 | .id = 7, | 450 | .id = 7, |
451 | .resource = scif7_resources, | ||
452 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
397 | .dev = { | 453 | .dev = { |
398 | .platform_data = &scif7_platform_data, | 454 | .platform_data = &scif7_platform_data, |
399 | }, | 455 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index 03e4c96f2b11..c76b2543b85f 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c | |||
@@ -70,39 +70,47 @@ static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, NULL, | |||
70 | NULL, prio_registers, NULL); | 70 | NULL, prio_registers, NULL); |
71 | 71 | ||
72 | static struct plat_sci_port scif0_platform_data = { | 72 | static struct plat_sci_port scif0_platform_data = { |
73 | .mapbase = 0xa4410000, | ||
74 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
75 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | | 74 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | |
76 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, | 75 | SCSCR_RE | SCSCR_CKE1 | SCSCR_CKE0, |
77 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
78 | .type = PORT_SCIF, | 76 | .type = PORT_SCIF, |
79 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
80 | .ops = &sh770x_sci_port_ops, | 77 | .ops = &sh770x_sci_port_ops, |
81 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 78 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
82 | }; | 79 | }; |
83 | 80 | ||
81 | static struct resource scif0_resources[] = { | ||
82 | DEFINE_RES_MEM(0xa4410000, 0x100), | ||
83 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
84 | }; | ||
85 | |||
84 | static struct platform_device scif0_device = { | 86 | static struct platform_device scif0_device = { |
85 | .name = "sh-sci", | 87 | .name = "sh-sci", |
86 | .id = 0, | 88 | .id = 0, |
89 | .resource = scif0_resources, | ||
90 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
87 | .dev = { | 91 | .dev = { |
88 | .platform_data = &scif0_platform_data, | 92 | .platform_data = &scif0_platform_data, |
89 | }, | 93 | }, |
90 | }; | 94 | }; |
91 | 95 | ||
92 | static struct plat_sci_port scif1_platform_data = { | 96 | static struct plat_sci_port scif1_platform_data = { |
93 | .mapbase = 0xa4400000, | ||
94 | .flags = UPF_BOOT_AUTOCONF, | 97 | .flags = UPF_BOOT_AUTOCONF, |
95 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, | 98 | .scscr = SCSCR_TIE | SCSCR_RIE | SCSCR_TE | SCSCR_RE, |
96 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
97 | .type = PORT_SCIF, | 99 | .type = PORT_SCIF, |
98 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
99 | .ops = &sh770x_sci_port_ops, | 100 | .ops = &sh770x_sci_port_ops, |
100 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 101 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
101 | }; | 102 | }; |
102 | 103 | ||
104 | static struct resource scif1_resources[] = { | ||
105 | DEFINE_RES_MEM(0xa4400000, 0x100), | ||
106 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
107 | }; | ||
108 | |||
103 | static struct platform_device scif1_device = { | 109 | static struct platform_device scif1_device = { |
104 | .name = "sh-sci", | 110 | .name = "sh-sci", |
105 | .id = 1, | 111 | .id = 1, |
112 | .resource = scif1_resources, | ||
113 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
106 | .dev = { | 114 | .dev = { |
107 | .platform_data = &scif1_platform_data, | 115 | .platform_data = &scif1_platform_data, |
108 | }, | 116 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index ba26cd9ce69b..ff1465c0519c 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
@@ -109,20 +109,24 @@ static struct platform_device rtc_device = { | |||
109 | }; | 109 | }; |
110 | 110 | ||
111 | static struct plat_sci_port scif0_platform_data = { | 111 | static struct plat_sci_port scif0_platform_data = { |
112 | .mapbase = 0xfffffe80, | ||
113 | .port_reg = 0xa4000136, | 112 | .port_reg = 0xa4000136, |
114 | .flags = UPF_BOOT_AUTOCONF, | 113 | .flags = UPF_BOOT_AUTOCONF, |
115 | .scscr = SCSCR_TE | SCSCR_RE, | 114 | .scscr = SCSCR_TE | SCSCR_RE, |
116 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
117 | .type = PORT_SCI, | 115 | .type = PORT_SCI, |
118 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), | ||
119 | .ops = &sh770x_sci_port_ops, | 116 | .ops = &sh770x_sci_port_ops, |
120 | .regshift = 1, | 117 | .regshift = 1, |
121 | }; | 118 | }; |
122 | 119 | ||
120 | static struct resource scif0_resources[] = { | ||
121 | DEFINE_RES_MEM(0xfffffe80, 0x100), | ||
122 | DEFINE_RES_IRQ(evt2irq(0x4e0)), | ||
123 | }; | ||
124 | |||
123 | static struct platform_device scif0_device = { | 125 | static struct platform_device scif0_device = { |
124 | .name = "sh-sci", | 126 | .name = "sh-sci", |
125 | .id = 0, | 127 | .id = 0, |
128 | .resource = scif0_resources, | ||
129 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
126 | .dev = { | 130 | .dev = { |
127 | .platform_data = &scif0_platform_data, | 131 | .platform_data = &scif0_platform_data, |
128 | }, | 132 | }, |
@@ -131,19 +135,23 @@ static struct platform_device scif0_device = { | |||
131 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 135 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
132 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 136 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
133 | static struct plat_sci_port scif1_platform_data = { | 137 | static struct plat_sci_port scif1_platform_data = { |
134 | .mapbase = 0xa4000150, | ||
135 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
136 | .scscr = SCSCR_TE | SCSCR_RE, | 139 | .scscr = SCSCR_TE | SCSCR_RE, |
137 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
138 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
139 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
140 | .ops = &sh770x_sci_port_ops, | 141 | .ops = &sh770x_sci_port_ops, |
141 | .regtype = SCIx_SH3_SCIF_REGTYPE, | 142 | .regtype = SCIx_SH3_SCIF_REGTYPE, |
142 | }; | 143 | }; |
143 | 144 | ||
145 | static struct resource scif1_resources[] = { | ||
146 | DEFINE_RES_MEM(0xa4000150, 0x100), | ||
147 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
148 | }; | ||
149 | |||
144 | static struct platform_device scif1_device = { | 150 | static struct platform_device scif1_device = { |
145 | .name = "sh-sci", | 151 | .name = "sh-sci", |
146 | .id = 1, | 152 | .id = 1, |
153 | .resource = scif1_resources, | ||
154 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
147 | .dev = { | 155 | .dev = { |
148 | .platform_data = &scif1_platform_data, | 156 | .platform_data = &scif1_platform_data, |
149 | }, | 157 | }, |
@@ -152,20 +160,24 @@ static struct platform_device scif1_device = { | |||
152 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 160 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
153 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 161 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
154 | static struct plat_sci_port scif2_platform_data = { | 162 | static struct plat_sci_port scif2_platform_data = { |
155 | .mapbase = 0xa4000140, | ||
156 | .port_reg = SCIx_NOT_SUPPORTED, | 163 | .port_reg = SCIx_NOT_SUPPORTED, |
157 | .flags = UPF_BOOT_AUTOCONF, | 164 | .flags = UPF_BOOT_AUTOCONF, |
158 | .scscr = SCSCR_TE | SCSCR_RE, | 165 | .scscr = SCSCR_TE | SCSCR_RE, |
159 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
160 | .type = PORT_IRDA, | 166 | .type = PORT_IRDA, |
161 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
162 | .ops = &sh770x_sci_port_ops, | 167 | .ops = &sh770x_sci_port_ops, |
163 | .regshift = 1, | 168 | .regshift = 1, |
164 | }; | 169 | }; |
165 | 170 | ||
171 | static struct resource scif2_resources[] = { | ||
172 | DEFINE_RES_MEM(0xa4000140, 0x100), | ||
173 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
174 | }; | ||
175 | |||
166 | static struct platform_device scif2_device = { | 176 | static struct platform_device scif2_device = { |
167 | .name = "sh-sci", | 177 | .name = "sh-sci", |
168 | .id = 2, | 178 | .id = 2, |
179 | .resource = scif2_resources, | ||
180 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
169 | .dev = { | 181 | .dev = { |
170 | .platform_data = &scif2_platform_data, | 182 | .platform_data = &scif2_platform_data, |
171 | }, | 183 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 93c9c5e24a7a..e2ce9360ed5a 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
@@ -98,36 +98,44 @@ static struct platform_device rtc_device = { | |||
98 | }; | 98 | }; |
99 | 99 | ||
100 | static struct plat_sci_port scif0_platform_data = { | 100 | static struct plat_sci_port scif0_platform_data = { |
101 | .mapbase = 0xa4400000, | ||
102 | .flags = UPF_BOOT_AUTOCONF, | 101 | .flags = UPF_BOOT_AUTOCONF, |
103 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 102 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
104 | SCSCR_CKE1 | SCSCR_CKE0, | 103 | SCSCR_CKE1 | SCSCR_CKE0, |
105 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
106 | .type = PORT_SCIF, | 104 | .type = PORT_SCIF, |
107 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | 105 | }; |
106 | |||
107 | static struct resource scif0_resources[] = { | ||
108 | DEFINE_RES_MEM(0xa4400000, 0x100), | ||
109 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
108 | }; | 110 | }; |
109 | 111 | ||
110 | static struct platform_device scif0_device = { | 112 | static struct platform_device scif0_device = { |
111 | .name = "sh-sci", | 113 | .name = "sh-sci", |
112 | .id = 0, | 114 | .id = 0, |
115 | .resource = scif0_resources, | ||
116 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
113 | .dev = { | 117 | .dev = { |
114 | .platform_data = &scif0_platform_data, | 118 | .platform_data = &scif0_platform_data, |
115 | }, | 119 | }, |
116 | }; | 120 | }; |
117 | 121 | ||
118 | static struct plat_sci_port scif1_platform_data = { | 122 | static struct plat_sci_port scif1_platform_data = { |
119 | .mapbase = 0xa4410000, | ||
120 | .flags = UPF_BOOT_AUTOCONF, | 123 | .flags = UPF_BOOT_AUTOCONF, |
121 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | | 124 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE | |
122 | SCSCR_CKE1 | SCSCR_CKE0, | 125 | SCSCR_CKE1 | SCSCR_CKE0, |
123 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
124 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 127 | }; |
128 | |||
129 | static struct resource scif1_resources[] = { | ||
130 | DEFINE_RES_MEM(0xa4410000, 0x100), | ||
131 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
126 | }; | 132 | }; |
127 | 133 | ||
128 | static struct platform_device scif1_device = { | 134 | static struct platform_device scif1_device = { |
129 | .name = "sh-sci", | 135 | .name = "sh-sci", |
130 | .id = 1, | 136 | .id = 1, |
137 | .resource = scif1_resources, | ||
138 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
131 | .dev = { | 139 | .dev = { |
132 | .platform_data = &scif1_platform_data, | 140 | .platform_data = &scif1_platform_data, |
133 | }, | 141 | }, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c index 42d991f632b1..1d5729dc0724 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c | |||
@@ -52,38 +52,46 @@ static struct platform_device rtc_device = { | |||
52 | }; | 52 | }; |
53 | 53 | ||
54 | static struct plat_sci_port scif0_platform_data = { | 54 | static struct plat_sci_port scif0_platform_data = { |
55 | .mapbase = 0xa4430000, | ||
56 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
57 | .scscr = SCSCR_RE | SCSCR_TE, | 56 | .scscr = SCSCR_RE | SCSCR_TE, |
58 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
59 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
61 | .ops = &sh7720_sci_port_ops, | 58 | .ops = &sh7720_sci_port_ops, |
62 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 59 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
63 | }; | 60 | }; |
64 | 61 | ||
62 | static struct resource scif0_resources[] = { | ||
63 | DEFINE_RES_MEM(0xa4430000, 0x100), | ||
64 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
65 | }; | ||
66 | |||
65 | static struct platform_device scif0_device = { | 67 | static struct platform_device scif0_device = { |
66 | .name = "sh-sci", | 68 | .name = "sh-sci", |
67 | .id = 0, | 69 | .id = 0, |
70 | .resource = scif0_resources, | ||
71 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
68 | .dev = { | 72 | .dev = { |
69 | .platform_data = &scif0_platform_data, | 73 | .platform_data = &scif0_platform_data, |
70 | }, | 74 | }, |
71 | }; | 75 | }; |
72 | 76 | ||
73 | static struct plat_sci_port scif1_platform_data = { | 77 | static struct plat_sci_port scif1_platform_data = { |
74 | .mapbase = 0xa4438000, | ||
75 | .flags = UPF_BOOT_AUTOCONF, | 78 | .flags = UPF_BOOT_AUTOCONF, |
76 | .scscr = SCSCR_RE | SCSCR_TE, | 79 | .scscr = SCSCR_RE | SCSCR_TE, |
77 | .scbrr_algo_id = SCBRR_ALGO_4, | ||
78 | .type = PORT_SCIF, | 80 | .type = PORT_SCIF, |
79 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
80 | .ops = &sh7720_sci_port_ops, | 81 | .ops = &sh7720_sci_port_ops, |
81 | .regtype = SCIx_SH7705_SCIF_REGTYPE, | 82 | .regtype = SCIx_SH7705_SCIF_REGTYPE, |
82 | }; | 83 | }; |
83 | 84 | ||
85 | static struct resource scif1_resources[] = { | ||
86 | DEFINE_RES_MEM(0xa4438000, 0x100), | ||
87 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
88 | }; | ||
89 | |||
84 | static struct platform_device scif1_device = { | 90 | static struct platform_device scif1_device = { |
85 | .name = "sh-sci", | 91 | .name = "sh-sci", |
86 | .id = 1, | 92 | .id = 1, |
93 | .resource = scif1_resources, | ||
94 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
87 | .dev = { | 95 | .dev = { |
88 | .platform_data = &scif1_platform_data, | 96 | .platform_data = &scif1_platform_data, |
89 | }, | 97 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c index 2a5320aa73bb..a8bd778d5ac8 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c | |||
@@ -17,20 +17,24 @@ | |||
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | 18 | ||
19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
20 | .mapbase = 0xffe80000, | ||
21 | .flags = UPF_BOOT_AUTOCONF, | 20 | .flags = UPF_BOOT_AUTOCONF, |
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
23 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
24 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
25 | .irqs = { evt2irq(0x700), | 23 | }; |
26 | evt2irq(0x720), | 24 | |
27 | evt2irq(0x760), | 25 | static struct resource scif0_resources[] = { |
28 | evt2irq(0x740) }, | 26 | DEFINE_RES_MEM(0xffe80000, 0x100), |
27 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
28 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
29 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
30 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
29 | }; | 31 | }; |
30 | 32 | ||
31 | static struct platform_device scif0_device = { | 33 | static struct platform_device scif0_device = { |
32 | .name = "sh-sci", | 34 | .name = "sh-sci", |
33 | .id = 0, | 35 | .id = 0, |
36 | .resource = scif0_resources, | ||
37 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
34 | .dev = { | 38 | .dev = { |
35 | .platform_data = &scif0_platform_data, | 39 | .platform_data = &scif0_platform_data, |
36 | }, | 40 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 04a45512596f..a447a248491f 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
@@ -38,36 +38,44 @@ static struct platform_device rtc_device = { | |||
38 | }; | 38 | }; |
39 | 39 | ||
40 | static struct plat_sci_port sci_platform_data = { | 40 | static struct plat_sci_port sci_platform_data = { |
41 | .mapbase = 0xffe00000, | ||
42 | .port_reg = 0xffe0001C, | 41 | .port_reg = 0xffe0001C, |
43 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
44 | .scscr = SCSCR_TE | SCSCR_RE, | 43 | .scscr = SCSCR_TE | SCSCR_RE, |
45 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
46 | .type = PORT_SCI, | 44 | .type = PORT_SCI, |
47 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x4e0)), | ||
48 | .regshift = 2, | 45 | .regshift = 2, |
49 | }; | 46 | }; |
50 | 47 | ||
48 | static struct resource sci_resources[] = { | ||
49 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
50 | DEFINE_RES_IRQ(evt2irq(0x4e0)), | ||
51 | }; | ||
52 | |||
51 | static struct platform_device sci_device = { | 53 | static struct platform_device sci_device = { |
52 | .name = "sh-sci", | 54 | .name = "sh-sci", |
53 | .id = 0, | 55 | .id = 0, |
56 | .resource = sci_resources, | ||
57 | .num_resources = ARRAY_SIZE(sci_resources), | ||
54 | .dev = { | 58 | .dev = { |
55 | .platform_data = &sci_platform_data, | 59 | .platform_data = &sci_platform_data, |
56 | }, | 60 | }, |
57 | }; | 61 | }; |
58 | 62 | ||
59 | static struct plat_sci_port scif_platform_data = { | 63 | static struct plat_sci_port scif_platform_data = { |
60 | .mapbase = 0xffe80000, | ||
61 | .flags = UPF_BOOT_AUTOCONF, | 64 | .flags = UPF_BOOT_AUTOCONF, |
62 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, | 65 | .scscr = SCSCR_TE | SCSCR_RE | SCSCR_REIE, |
63 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
64 | .type = PORT_SCIF, | 66 | .type = PORT_SCIF, |
65 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | 67 | }; |
68 | |||
69 | static struct resource scif_resources[] = { | ||
70 | DEFINE_RES_MEM(0xffe80000, 0x100), | ||
71 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
66 | }; | 72 | }; |
67 | 73 | ||
68 | static struct platform_device scif_device = { | 74 | static struct platform_device scif_device = { |
69 | .name = "sh-sci", | 75 | .name = "sh-sci", |
70 | .id = 1, | 76 | .id = 1, |
77 | .resource = scif_resources, | ||
78 | .num_resources = ARRAY_SIZE(scif_resources), | ||
71 | .dev = { | 79 | .dev = { |
72 | .platform_data = &scif_platform_data, | 80 | .platform_data = &scif_platform_data, |
73 | }, | 81 | }, |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 98e075ada44e..1abd9fb4a386 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
@@ -128,83 +128,99 @@ static DECLARE_INTC_DESC(intc_desc_irq, "sh7760-irq", vectors_irq, groups, | |||
128 | mask_registers, prio_registers, NULL); | 128 | mask_registers, prio_registers, NULL); |
129 | 129 | ||
130 | static struct plat_sci_port scif0_platform_data = { | 130 | static struct plat_sci_port scif0_platform_data = { |
131 | .mapbase = 0xfe600000, | ||
132 | .flags = UPF_BOOT_AUTOCONF, | 131 | .flags = UPF_BOOT_AUTOCONF, |
133 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 132 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
134 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
135 | .type = PORT_SCIF, | 133 | .type = PORT_SCIF, |
136 | .irqs = { evt2irq(0x880), | ||
137 | evt2irq(0x8a0), | ||
138 | evt2irq(0x8e0), | ||
139 | evt2irq(0x8c0) }, | ||
140 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 134 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
141 | }; | 135 | }; |
142 | 136 | ||
137 | static struct resource scif0_resources[] = { | ||
138 | DEFINE_RES_MEM(0xfe600000, 0x100), | ||
139 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
140 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
141 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
142 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
143 | }; | ||
144 | |||
143 | static struct platform_device scif0_device = { | 145 | static struct platform_device scif0_device = { |
144 | .name = "sh-sci", | 146 | .name = "sh-sci", |
145 | .id = 0, | 147 | .id = 0, |
148 | .resource = scif0_resources, | ||
149 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
146 | .dev = { | 150 | .dev = { |
147 | .platform_data = &scif0_platform_data, | 151 | .platform_data = &scif0_platform_data, |
148 | }, | 152 | }, |
149 | }; | 153 | }; |
150 | 154 | ||
151 | static struct plat_sci_port scif1_platform_data = { | 155 | static struct plat_sci_port scif1_platform_data = { |
152 | .mapbase = 0xfe610000, | ||
153 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
154 | .type = PORT_SCIF, | 157 | .type = PORT_SCIF, |
155 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 158 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
156 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
157 | .irqs = { evt2irq(0xb00), | ||
158 | evt2irq(0xb20), | ||
159 | evt2irq(0xb60), | ||
160 | evt2irq(0xb40) }, | ||
161 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
162 | }; | 160 | }; |
163 | 161 | ||
162 | static struct resource scif1_resources[] = { | ||
163 | DEFINE_RES_MEM(0xfe610000, 0x100), | ||
164 | DEFINE_RES_IRQ(evt2irq(0xb00)), | ||
165 | DEFINE_RES_IRQ(evt2irq(0xb20)), | ||
166 | DEFINE_RES_IRQ(evt2irq(0xb60)), | ||
167 | DEFINE_RES_IRQ(evt2irq(0xb40)), | ||
168 | }; | ||
169 | |||
164 | static struct platform_device scif1_device = { | 170 | static struct platform_device scif1_device = { |
165 | .name = "sh-sci", | 171 | .name = "sh-sci", |
166 | .id = 1, | 172 | .id = 1, |
173 | .resource = scif1_resources, | ||
174 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
167 | .dev = { | 175 | .dev = { |
168 | .platform_data = &scif1_platform_data, | 176 | .platform_data = &scif1_platform_data, |
169 | }, | 177 | }, |
170 | }; | 178 | }; |
171 | 179 | ||
172 | static struct plat_sci_port scif2_platform_data = { | 180 | static struct plat_sci_port scif2_platform_data = { |
173 | .mapbase = 0xfe620000, | ||
174 | .flags = UPF_BOOT_AUTOCONF, | 181 | .flags = UPF_BOOT_AUTOCONF, |
175 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 182 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
176 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
177 | .type = PORT_SCIF, | 183 | .type = PORT_SCIF, |
178 | .irqs = { evt2irq(0xb80), | ||
179 | evt2irq(0xba0), | ||
180 | evt2irq(0xbe0), | ||
181 | evt2irq(0xbc0) }, | ||
182 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 184 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
183 | }; | 185 | }; |
184 | 186 | ||
187 | static struct resource scif2_resources[] = { | ||
188 | DEFINE_RES_MEM(0xfe620000, 0x100), | ||
189 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
190 | DEFINE_RES_IRQ(evt2irq(0xba0)), | ||
191 | DEFINE_RES_IRQ(evt2irq(0xbe0)), | ||
192 | DEFINE_RES_IRQ(evt2irq(0xbc0)), | ||
193 | }; | ||
194 | |||
185 | static struct platform_device scif2_device = { | 195 | static struct platform_device scif2_device = { |
186 | .name = "sh-sci", | 196 | .name = "sh-sci", |
187 | .id = 2, | 197 | .id = 2, |
198 | .resource = scif2_resources, | ||
199 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
188 | .dev = { | 200 | .dev = { |
189 | .platform_data = &scif2_platform_data, | 201 | .platform_data = &scif2_platform_data, |
190 | }, | 202 | }, |
191 | }; | 203 | }; |
192 | 204 | ||
193 | static struct plat_sci_port scif3_platform_data = { | 205 | static struct plat_sci_port scif3_platform_data = { |
194 | .mapbase = 0xfe480000, | ||
195 | .flags = UPF_BOOT_AUTOCONF, | 206 | .flags = UPF_BOOT_AUTOCONF, |
196 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 207 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
197 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
198 | .type = PORT_SCI, | 208 | .type = PORT_SCI, |
199 | .irqs = { evt2irq(0xc00), | ||
200 | evt2irq(0xc20), | ||
201 | evt2irq(0xc40), }, | ||
202 | .regshift = 2, | 209 | .regshift = 2, |
203 | }; | 210 | }; |
204 | 211 | ||
212 | static struct resource scif3_resources[] = { | ||
213 | DEFINE_RES_MEM(0xfe480000, 0x100), | ||
214 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
215 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
216 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
217 | }; | ||
218 | |||
205 | static struct platform_device scif3_device = { | 219 | static struct platform_device scif3_device = { |
206 | .name = "sh-sci", | 220 | .name = "sh-sci", |
207 | .id = 3, | 221 | .id = 3, |
222 | .resource = scif3_resources, | ||
223 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
208 | .dev = { | 224 | .dev = { |
209 | .platform_data = &scif3_platform_data, | 225 | .platform_data = &scif3_platform_data, |
210 | }, | 226 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c index b91ea8300a3e..245d19254489 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c | |||
@@ -18,68 +18,84 @@ | |||
18 | 18 | ||
19 | /* Serial */ | 19 | /* Serial */ |
20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
21 | .mapbase = 0xffe00000, | ||
22 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
24 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
25 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
26 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | 24 | }; |
25 | |||
26 | static struct resource scif0_resources[] = { | ||
27 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
28 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
27 | }; | 29 | }; |
28 | 30 | ||
29 | static struct platform_device scif0_device = { | 31 | static struct platform_device scif0_device = { |
30 | .name = "sh-sci", | 32 | .name = "sh-sci", |
31 | .id = 0, | 33 | .id = 0, |
34 | .resource = scif0_resources, | ||
35 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
32 | .dev = { | 36 | .dev = { |
33 | .platform_data = &scif0_platform_data, | 37 | .platform_data = &scif0_platform_data, |
34 | }, | 38 | }, |
35 | }; | 39 | }; |
36 | 40 | ||
37 | static struct plat_sci_port scif1_platform_data = { | 41 | static struct plat_sci_port scif1_platform_data = { |
38 | .mapbase = 0xffe10000, | ||
39 | .flags = UPF_BOOT_AUTOCONF, | 42 | .flags = UPF_BOOT_AUTOCONF, |
40 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
41 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
42 | .type = PORT_SCIF, | 44 | .type = PORT_SCIF, |
43 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | 45 | }; |
46 | |||
47 | static struct resource scif1_resources[] = { | ||
48 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
49 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
44 | }; | 50 | }; |
45 | 51 | ||
46 | static struct platform_device scif1_device = { | 52 | static struct platform_device scif1_device = { |
47 | .name = "sh-sci", | 53 | .name = "sh-sci", |
48 | .id = 1, | 54 | .id = 1, |
55 | .resource = scif1_resources, | ||
56 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
49 | .dev = { | 57 | .dev = { |
50 | .platform_data = &scif1_platform_data, | 58 | .platform_data = &scif1_platform_data, |
51 | }, | 59 | }, |
52 | }; | 60 | }; |
53 | 61 | ||
54 | static struct plat_sci_port scif2_platform_data = { | 62 | static struct plat_sci_port scif2_platform_data = { |
55 | .mapbase = 0xffe20000, | ||
56 | .flags = UPF_BOOT_AUTOCONF, | 63 | .flags = UPF_BOOT_AUTOCONF, |
57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 64 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
58 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
59 | .type = PORT_SCIF, | 65 | .type = PORT_SCIF, |
60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | 66 | }; |
67 | |||
68 | static struct resource scif2_resources[] = { | ||
69 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
70 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
61 | }; | 71 | }; |
62 | 72 | ||
63 | static struct platform_device scif2_device = { | 73 | static struct platform_device scif2_device = { |
64 | .name = "sh-sci", | 74 | .name = "sh-sci", |
65 | .id = 2, | 75 | .id = 2, |
76 | .resource = scif2_resources, | ||
77 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
66 | .dev = { | 78 | .dev = { |
67 | .platform_data = &scif2_platform_data, | 79 | .platform_data = &scif2_platform_data, |
68 | }, | 80 | }, |
69 | }; | 81 | }; |
70 | 82 | ||
71 | static struct plat_sci_port scif3_platform_data = { | 83 | static struct plat_sci_port scif3_platform_data = { |
72 | .mapbase = 0xffe30000, | ||
73 | .flags = UPF_BOOT_AUTOCONF, | 84 | .flags = UPF_BOOT_AUTOCONF, |
74 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, | 85 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, |
75 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
76 | .type = PORT_SCIF, | 86 | .type = PORT_SCIF, |
77 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc60)), | 87 | }; |
88 | |||
89 | static struct resource scif3_resources[] = { | ||
90 | DEFINE_RES_MEM(0xffe30000, 0x100), | ||
91 | DEFINE_RES_IRQ(evt2irq(0xc60)), | ||
78 | }; | 92 | }; |
79 | 93 | ||
80 | static struct platform_device scif3_device = { | 94 | static struct platform_device scif3_device = { |
81 | .name = "sh-sci", | 95 | .name = "sh-sci", |
82 | .id = 3, | 96 | .id = 3, |
97 | .resource = scif3_resources, | ||
98 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
83 | .dev = { | 99 | .dev = { |
84 | .platform_data = &scif3_platform_data, | 100 | .platform_data = &scif3_platform_data, |
85 | }, | 101 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c index 0bd09d51419f..6f56cbd76b20 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c | |||
@@ -20,18 +20,22 @@ | |||
20 | #include <asm/clock.h> | 20 | #include <asm/clock.h> |
21 | 21 | ||
22 | static struct plat_sci_port scif0_platform_data = { | 22 | static struct plat_sci_port scif0_platform_data = { |
23 | .mapbase = 0xffe00000, | ||
24 | .port_reg = 0xa405013e, | 23 | .port_reg = 0xa405013e, |
25 | .flags = UPF_BOOT_AUTOCONF, | 24 | .flags = UPF_BOOT_AUTOCONF, |
26 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
27 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
28 | .type = PORT_SCIF, | 26 | .type = PORT_SCIF, |
29 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | 27 | }; |
28 | |||
29 | static struct resource scif0_resources[] = { | ||
30 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
31 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
30 | }; | 32 | }; |
31 | 33 | ||
32 | static struct platform_device scif0_device = { | 34 | static struct platform_device scif0_device = { |
33 | .name = "sh-sci", | 35 | .name = "sh-sci", |
34 | .id = 0, | 36 | .id = 0, |
37 | .resource = scif0_resources, | ||
38 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
35 | .dev = { | 39 | .dev = { |
36 | .platform_data = &scif0_platform_data, | 40 | .platform_data = &scif0_platform_data, |
37 | }, | 41 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index 6a868b091c2d..5a94efc8d4ce 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
@@ -179,57 +179,69 @@ struct platform_device dma_device = { | |||
179 | 179 | ||
180 | /* Serial */ | 180 | /* Serial */ |
181 | static struct plat_sci_port scif0_platform_data = { | 181 | static struct plat_sci_port scif0_platform_data = { |
182 | .mapbase = 0xffe00000, | ||
183 | .flags = UPF_BOOT_AUTOCONF, | 182 | .flags = UPF_BOOT_AUTOCONF, |
184 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 183 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
185 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
186 | .type = PORT_SCIF, | 184 | .type = PORT_SCIF, |
187 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
188 | .ops = &sh7722_sci_port_ops, | 185 | .ops = &sh7722_sci_port_ops, |
189 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 186 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
190 | }; | 187 | }; |
191 | 188 | ||
189 | static struct resource scif0_resources[] = { | ||
190 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
191 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
192 | }; | ||
193 | |||
192 | static struct platform_device scif0_device = { | 194 | static struct platform_device scif0_device = { |
193 | .name = "sh-sci", | 195 | .name = "sh-sci", |
194 | .id = 0, | 196 | .id = 0, |
197 | .resource = scif0_resources, | ||
198 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
195 | .dev = { | 199 | .dev = { |
196 | .platform_data = &scif0_platform_data, | 200 | .platform_data = &scif0_platform_data, |
197 | }, | 201 | }, |
198 | }; | 202 | }; |
199 | 203 | ||
200 | static struct plat_sci_port scif1_platform_data = { | 204 | static struct plat_sci_port scif1_platform_data = { |
201 | .mapbase = 0xffe10000, | ||
202 | .flags = UPF_BOOT_AUTOCONF, | 205 | .flags = UPF_BOOT_AUTOCONF, |
203 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 206 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
204 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
205 | .type = PORT_SCIF, | 207 | .type = PORT_SCIF, |
206 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
207 | .ops = &sh7722_sci_port_ops, | 208 | .ops = &sh7722_sci_port_ops, |
208 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 209 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
209 | }; | 210 | }; |
210 | 211 | ||
212 | static struct resource scif1_resources[] = { | ||
213 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
214 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
215 | }; | ||
216 | |||
211 | static struct platform_device scif1_device = { | 217 | static struct platform_device scif1_device = { |
212 | .name = "sh-sci", | 218 | .name = "sh-sci", |
213 | .id = 1, | 219 | .id = 1, |
220 | .resource = scif1_resources, | ||
221 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
214 | .dev = { | 222 | .dev = { |
215 | .platform_data = &scif1_platform_data, | 223 | .platform_data = &scif1_platform_data, |
216 | }, | 224 | }, |
217 | }; | 225 | }; |
218 | 226 | ||
219 | static struct plat_sci_port scif2_platform_data = { | 227 | static struct plat_sci_port scif2_platform_data = { |
220 | .mapbase = 0xffe20000, | ||
221 | .flags = UPF_BOOT_AUTOCONF, | 228 | .flags = UPF_BOOT_AUTOCONF, |
222 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 229 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
223 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
224 | .type = PORT_SCIF, | 230 | .type = PORT_SCIF, |
225 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
226 | .ops = &sh7722_sci_port_ops, | 231 | .ops = &sh7722_sci_port_ops, |
227 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 232 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
228 | }; | 233 | }; |
229 | 234 | ||
235 | static struct resource scif2_resources[] = { | ||
236 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
237 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
238 | }; | ||
239 | |||
230 | static struct platform_device scif2_device = { | 240 | static struct platform_device scif2_device = { |
231 | .name = "sh-sci", | 241 | .name = "sh-sci", |
232 | .id = 2, | 242 | .id = 2, |
243 | .resource = scif2_resources, | ||
244 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
233 | .dev = { | 245 | .dev = { |
234 | .platform_data = &scif2_platform_data, | 246 | .platform_data = &scif2_platform_data, |
235 | }, | 247 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c index 28d6fd835fe0..3c5eb0993a75 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c | |||
@@ -23,111 +23,138 @@ | |||
23 | 23 | ||
24 | /* Serial */ | 24 | /* Serial */ |
25 | static struct plat_sci_port scif0_platform_data = { | 25 | static struct plat_sci_port scif0_platform_data = { |
26 | .mapbase = 0xffe00000, | ||
27 | .port_reg = 0xa4050160, | 26 | .port_reg = 0xa4050160, |
28 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
30 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
31 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
32 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
33 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 30 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
34 | }; | 31 | }; |
35 | 32 | ||
33 | static struct resource scif0_resources[] = { | ||
34 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
35 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
36 | }; | ||
37 | |||
36 | static struct platform_device scif0_device = { | 38 | static struct platform_device scif0_device = { |
37 | .name = "sh-sci", | 39 | .name = "sh-sci", |
38 | .id = 0, | 40 | .id = 0, |
41 | .resource = scif0_resources, | ||
42 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
39 | .dev = { | 43 | .dev = { |
40 | .platform_data = &scif0_platform_data, | 44 | .platform_data = &scif0_platform_data, |
41 | }, | 45 | }, |
42 | }; | 46 | }; |
43 | 47 | ||
44 | static struct plat_sci_port scif1_platform_data = { | 48 | static struct plat_sci_port scif1_platform_data = { |
45 | .mapbase = 0xffe10000, | ||
46 | .port_reg = SCIx_NOT_SUPPORTED, | 49 | .port_reg = SCIx_NOT_SUPPORTED, |
47 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
48 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
49 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
50 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
51 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
52 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
53 | }; | 54 | }; |
54 | 55 | ||
56 | static struct resource scif1_resources[] = { | ||
57 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
58 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
59 | }; | ||
60 | |||
55 | static struct platform_device scif1_device = { | 61 | static struct platform_device scif1_device = { |
56 | .name = "sh-sci", | 62 | .name = "sh-sci", |
57 | .id = 1, | 63 | .id = 1, |
64 | .resource = scif1_resources, | ||
65 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
58 | .dev = { | 66 | .dev = { |
59 | .platform_data = &scif1_platform_data, | 67 | .platform_data = &scif1_platform_data, |
60 | }, | 68 | }, |
61 | }; | 69 | }; |
62 | 70 | ||
63 | static struct plat_sci_port scif2_platform_data = { | 71 | static struct plat_sci_port scif2_platform_data = { |
64 | .mapbase = 0xffe20000, | ||
65 | .port_reg = SCIx_NOT_SUPPORTED, | 72 | .port_reg = SCIx_NOT_SUPPORTED, |
66 | .flags = UPF_BOOT_AUTOCONF, | 73 | .flags = UPF_BOOT_AUTOCONF, |
67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 74 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
68 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
69 | .type = PORT_SCIF, | 75 | .type = PORT_SCIF, |
70 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
71 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 76 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
72 | }; | 77 | }; |
73 | 78 | ||
79 | static struct resource scif2_resources[] = { | ||
80 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
81 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
82 | }; | ||
83 | |||
74 | static struct platform_device scif2_device = { | 84 | static struct platform_device scif2_device = { |
75 | .name = "sh-sci", | 85 | .name = "sh-sci", |
76 | .id = 2, | 86 | .id = 2, |
87 | .resource = scif2_resources, | ||
88 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
77 | .dev = { | 89 | .dev = { |
78 | .platform_data = &scif2_platform_data, | 90 | .platform_data = &scif2_platform_data, |
79 | }, | 91 | }, |
80 | }; | 92 | }; |
81 | 93 | ||
82 | static struct plat_sci_port scif3_platform_data = { | 94 | static struct plat_sci_port scif3_platform_data = { |
83 | .mapbase = 0xa4e30000, | ||
84 | .flags = UPF_BOOT_AUTOCONF, | 95 | .flags = UPF_BOOT_AUTOCONF, |
85 | .port_reg = SCIx_NOT_SUPPORTED, | 96 | .port_reg = SCIx_NOT_SUPPORTED, |
86 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 97 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
87 | .scbrr_algo_id = SCBRR_ALGO_3, | 98 | .sampling_rate = 8, |
88 | .type = PORT_SCIFA, | 99 | .type = PORT_SCIFA, |
89 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 100 | }; |
101 | |||
102 | static struct resource scif3_resources[] = { | ||
103 | DEFINE_RES_MEM(0xa4e30000, 0x100), | ||
104 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
90 | }; | 105 | }; |
91 | 106 | ||
92 | static struct platform_device scif3_device = { | 107 | static struct platform_device scif3_device = { |
93 | .name = "sh-sci", | 108 | .name = "sh-sci", |
94 | .id = 3, | 109 | .id = 3, |
110 | .resource = scif3_resources, | ||
111 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
95 | .dev = { | 112 | .dev = { |
96 | .platform_data = &scif3_platform_data, | 113 | .platform_data = &scif3_platform_data, |
97 | }, | 114 | }, |
98 | }; | 115 | }; |
99 | 116 | ||
100 | static struct plat_sci_port scif4_platform_data = { | 117 | static struct plat_sci_port scif4_platform_data = { |
101 | .mapbase = 0xa4e40000, | ||
102 | .port_reg = SCIx_NOT_SUPPORTED, | 118 | .port_reg = SCIx_NOT_SUPPORTED, |
103 | .flags = UPF_BOOT_AUTOCONF, | 119 | .flags = UPF_BOOT_AUTOCONF, |
104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 120 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
105 | .scbrr_algo_id = SCBRR_ALGO_3, | 121 | .sampling_rate = 8, |
106 | .type = PORT_SCIFA, | 122 | .type = PORT_SCIFA, |
107 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), | 123 | }; |
124 | |||
125 | static struct resource scif4_resources[] = { | ||
126 | DEFINE_RES_MEM(0xa4e40000, 0x100), | ||
127 | DEFINE_RES_IRQ(evt2irq(0xd00)), | ||
108 | }; | 128 | }; |
109 | 129 | ||
110 | static struct platform_device scif4_device = { | 130 | static struct platform_device scif4_device = { |
111 | .name = "sh-sci", | 131 | .name = "sh-sci", |
112 | .id = 4, | 132 | .id = 4, |
133 | .resource = scif4_resources, | ||
134 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
113 | .dev = { | 135 | .dev = { |
114 | .platform_data = &scif4_platform_data, | 136 | .platform_data = &scif4_platform_data, |
115 | }, | 137 | }, |
116 | }; | 138 | }; |
117 | 139 | ||
118 | static struct plat_sci_port scif5_platform_data = { | 140 | static struct plat_sci_port scif5_platform_data = { |
119 | .mapbase = 0xa4e50000, | ||
120 | .port_reg = SCIx_NOT_SUPPORTED, | 141 | .port_reg = SCIx_NOT_SUPPORTED, |
121 | .flags = UPF_BOOT_AUTOCONF, | 142 | .flags = UPF_BOOT_AUTOCONF, |
122 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 143 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
123 | .scbrr_algo_id = SCBRR_ALGO_3, | 144 | .sampling_rate = 8, |
124 | .type = PORT_SCIFA, | 145 | .type = PORT_SCIFA, |
125 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), | 146 | }; |
147 | |||
148 | static struct resource scif5_resources[] = { | ||
149 | DEFINE_RES_MEM(0xa4e50000, 0x100), | ||
150 | DEFINE_RES_IRQ(evt2irq(0xfa0)), | ||
126 | }; | 151 | }; |
127 | 152 | ||
128 | static struct platform_device scif5_device = { | 153 | static struct platform_device scif5_device = { |
129 | .name = "sh-sci", | 154 | .name = "sh-sci", |
130 | .id = 5, | 155 | .id = 5, |
156 | .resource = scif5_resources, | ||
157 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
131 | .dev = { | 158 | .dev = { |
132 | .platform_data = &scif5_platform_data, | 159 | .platform_data = &scif5_platform_data, |
133 | }, | 160 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c index 26b74c2f9496..60ebbc6842ff 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c | |||
@@ -290,111 +290,138 @@ static struct platform_device dma1_device = { | |||
290 | 290 | ||
291 | /* Serial */ | 291 | /* Serial */ |
292 | static struct plat_sci_port scif0_platform_data = { | 292 | static struct plat_sci_port scif0_platform_data = { |
293 | .mapbase = 0xffe00000, | ||
294 | .port_reg = SCIx_NOT_SUPPORTED, | 293 | .port_reg = SCIx_NOT_SUPPORTED, |
295 | .flags = UPF_BOOT_AUTOCONF, | 294 | .flags = UPF_BOOT_AUTOCONF, |
296 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 295 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
297 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
298 | .type = PORT_SCIF, | 296 | .type = PORT_SCIF, |
299 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc00)), | ||
300 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 297 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
301 | }; | 298 | }; |
302 | 299 | ||
300 | static struct resource scif0_resources[] = { | ||
301 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
302 | DEFINE_RES_IRQ(evt2irq(0xc00)), | ||
303 | }; | ||
304 | |||
303 | static struct platform_device scif0_device = { | 305 | static struct platform_device scif0_device = { |
304 | .name = "sh-sci", | 306 | .name = "sh-sci", |
305 | .id = 0, | 307 | .id = 0, |
308 | .resource = scif0_resources, | ||
309 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
306 | .dev = { | 310 | .dev = { |
307 | .platform_data = &scif0_platform_data, | 311 | .platform_data = &scif0_platform_data, |
308 | }, | 312 | }, |
309 | }; | 313 | }; |
310 | 314 | ||
311 | static struct plat_sci_port scif1_platform_data = { | 315 | static struct plat_sci_port scif1_platform_data = { |
312 | .mapbase = 0xffe10000, | ||
313 | .port_reg = SCIx_NOT_SUPPORTED, | 316 | .port_reg = SCIx_NOT_SUPPORTED, |
314 | .flags = UPF_BOOT_AUTOCONF, | 317 | .flags = UPF_BOOT_AUTOCONF, |
315 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 318 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
316 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
317 | .type = PORT_SCIF, | 319 | .type = PORT_SCIF, |
318 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc20)), | ||
319 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 320 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
320 | }; | 321 | }; |
321 | 322 | ||
323 | static struct resource scif1_resources[] = { | ||
324 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
325 | DEFINE_RES_IRQ(evt2irq(0xc20)), | ||
326 | }; | ||
327 | |||
322 | static struct platform_device scif1_device = { | 328 | static struct platform_device scif1_device = { |
323 | .name = "sh-sci", | 329 | .name = "sh-sci", |
324 | .id = 1, | 330 | .id = 1, |
331 | .resource = scif1_resources, | ||
332 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
325 | .dev = { | 333 | .dev = { |
326 | .platform_data = &scif1_platform_data, | 334 | .platform_data = &scif1_platform_data, |
327 | }, | 335 | }, |
328 | }; | 336 | }; |
329 | 337 | ||
330 | static struct plat_sci_port scif2_platform_data = { | 338 | static struct plat_sci_port scif2_platform_data = { |
331 | .mapbase = 0xffe20000, | ||
332 | .port_reg = SCIx_NOT_SUPPORTED, | 339 | .port_reg = SCIx_NOT_SUPPORTED, |
333 | .flags = UPF_BOOT_AUTOCONF, | 340 | .flags = UPF_BOOT_AUTOCONF, |
334 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 341 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
335 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
336 | .type = PORT_SCIF, | 342 | .type = PORT_SCIF, |
337 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xc40)), | ||
338 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, | 343 | .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE, |
339 | }; | 344 | }; |
340 | 345 | ||
346 | static struct resource scif2_resources[] = { | ||
347 | DEFINE_RES_MEM(0xffe20000, 0x100), | ||
348 | DEFINE_RES_IRQ(evt2irq(0xc40)), | ||
349 | }; | ||
350 | |||
341 | static struct platform_device scif2_device = { | 351 | static struct platform_device scif2_device = { |
342 | .name = "sh-sci", | 352 | .name = "sh-sci", |
343 | .id = 2, | 353 | .id = 2, |
354 | .resource = scif2_resources, | ||
355 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
344 | .dev = { | 356 | .dev = { |
345 | .platform_data = &scif2_platform_data, | 357 | .platform_data = &scif2_platform_data, |
346 | }, | 358 | }, |
347 | }; | 359 | }; |
348 | 360 | ||
349 | static struct plat_sci_port scif3_platform_data = { | 361 | static struct plat_sci_port scif3_platform_data = { |
350 | .mapbase = 0xa4e30000, | ||
351 | .port_reg = SCIx_NOT_SUPPORTED, | 362 | .port_reg = SCIx_NOT_SUPPORTED, |
352 | .flags = UPF_BOOT_AUTOCONF, | 363 | .flags = UPF_BOOT_AUTOCONF, |
353 | .scscr = SCSCR_RE | SCSCR_TE, | 364 | .scscr = SCSCR_RE | SCSCR_TE, |
354 | .scbrr_algo_id = SCBRR_ALGO_3, | 365 | .sampling_rate = 8, |
355 | .type = PORT_SCIFA, | 366 | .type = PORT_SCIFA, |
356 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | 367 | }; |
368 | |||
369 | static struct resource scif3_resources[] = { | ||
370 | DEFINE_RES_MEM(0xa4e30000, 0x100), | ||
371 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
357 | }; | 372 | }; |
358 | 373 | ||
359 | static struct platform_device scif3_device = { | 374 | static struct platform_device scif3_device = { |
360 | .name = "sh-sci", | 375 | .name = "sh-sci", |
361 | .id = 3, | 376 | .id = 3, |
377 | .resource = scif3_resources, | ||
378 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
362 | .dev = { | 379 | .dev = { |
363 | .platform_data = &scif3_platform_data, | 380 | .platform_data = &scif3_platform_data, |
364 | }, | 381 | }, |
365 | }; | 382 | }; |
366 | 383 | ||
367 | static struct plat_sci_port scif4_platform_data = { | 384 | static struct plat_sci_port scif4_platform_data = { |
368 | .mapbase = 0xa4e40000, | ||
369 | .port_reg = SCIx_NOT_SUPPORTED, | 385 | .port_reg = SCIx_NOT_SUPPORTED, |
370 | .flags = UPF_BOOT_AUTOCONF, | 386 | .flags = UPF_BOOT_AUTOCONF, |
371 | .scscr = SCSCR_RE | SCSCR_TE, | 387 | .scscr = SCSCR_RE | SCSCR_TE, |
372 | .scbrr_algo_id = SCBRR_ALGO_3, | 388 | .sampling_rate = 8, |
373 | .type = PORT_SCIFA, | 389 | .type = PORT_SCIFA, |
374 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xd00)), | 390 | }; |
391 | |||
392 | static struct resource scif4_resources[] = { | ||
393 | DEFINE_RES_MEM(0xa4e40000, 0x100), | ||
394 | DEFINE_RES_IRQ(evt2irq(0xd00)), | ||
375 | }; | 395 | }; |
376 | 396 | ||
377 | static struct platform_device scif4_device = { | 397 | static struct platform_device scif4_device = { |
378 | .name = "sh-sci", | 398 | .name = "sh-sci", |
379 | .id = 4, | 399 | .id = 4, |
400 | .resource = scif4_resources, | ||
401 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
380 | .dev = { | 402 | .dev = { |
381 | .platform_data = &scif4_platform_data, | 403 | .platform_data = &scif4_platform_data, |
382 | }, | 404 | }, |
383 | }; | 405 | }; |
384 | 406 | ||
385 | static struct plat_sci_port scif5_platform_data = { | 407 | static struct plat_sci_port scif5_platform_data = { |
386 | .mapbase = 0xa4e50000, | ||
387 | .port_reg = SCIx_NOT_SUPPORTED, | 408 | .port_reg = SCIx_NOT_SUPPORTED, |
388 | .flags = UPF_BOOT_AUTOCONF, | 409 | .flags = UPF_BOOT_AUTOCONF, |
389 | .scscr = SCSCR_RE | SCSCR_TE, | 410 | .scscr = SCSCR_RE | SCSCR_TE, |
390 | .scbrr_algo_id = SCBRR_ALGO_3, | 411 | .sampling_rate = 8, |
391 | .type = PORT_SCIFA, | 412 | .type = PORT_SCIFA, |
392 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xfa0)), | 413 | }; |
414 | |||
415 | static struct resource scif5_resources[] = { | ||
416 | DEFINE_RES_MEM(0xa4e50000, 0x100), | ||
417 | DEFINE_RES_IRQ(evt2irq(0xfa0)), | ||
393 | }; | 418 | }; |
394 | 419 | ||
395 | static struct platform_device scif5_device = { | 420 | static struct platform_device scif5_device = { |
396 | .name = "sh-sci", | 421 | .name = "sh-sci", |
397 | .id = 5, | 422 | .id = 5, |
423 | .resource = scif5_resources, | ||
424 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
398 | .dev = { | 425 | .dev = { |
399 | .platform_data = &scif5_platform_data, | 426 | .platform_data = &scif5_platform_data, |
400 | }, | 427 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c index f799971d453c..dad4ed1b2f94 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7734.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7734.c | |||
@@ -25,108 +25,132 @@ | |||
25 | 25 | ||
26 | /* SCIF */ | 26 | /* SCIF */ |
27 | static struct plat_sci_port scif0_platform_data = { | 27 | static struct plat_sci_port scif0_platform_data = { |
28 | .mapbase = 0xFFE40000, | ||
29 | .flags = UPF_BOOT_AUTOCONF, | 28 | .flags = UPF_BOOT_AUTOCONF, |
30 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
31 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
32 | .type = PORT_SCIF, | 30 | .type = PORT_SCIF, |
33 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8C0)), | ||
34 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 31 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
35 | }; | 32 | }; |
36 | 33 | ||
34 | static struct resource scif0_resources[] = { | ||
35 | DEFINE_RES_MEM(0xffe40000, 0x100), | ||
36 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
37 | }; | ||
38 | |||
37 | static struct platform_device scif0_device = { | 39 | static struct platform_device scif0_device = { |
38 | .name = "sh-sci", | 40 | .name = "sh-sci", |
39 | .id = 0, | 41 | .id = 0, |
42 | .resource = scif0_resources, | ||
43 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
40 | .dev = { | 44 | .dev = { |
41 | .platform_data = &scif0_platform_data, | 45 | .platform_data = &scif0_platform_data, |
42 | }, | 46 | }, |
43 | }; | 47 | }; |
44 | 48 | ||
45 | static struct plat_sci_port scif1_platform_data = { | 49 | static struct plat_sci_port scif1_platform_data = { |
46 | .mapbase = 0xFFE41000, | ||
47 | .flags = UPF_BOOT_AUTOCONF, | 50 | .flags = UPF_BOOT_AUTOCONF, |
48 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 51 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
49 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
50 | .type = PORT_SCIF, | 52 | .type = PORT_SCIF, |
51 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8E0)), | ||
52 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 53 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
53 | }; | 54 | }; |
54 | 55 | ||
56 | static struct resource scif1_resources[] = { | ||
57 | DEFINE_RES_MEM(0xffe41000, 0x100), | ||
58 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
59 | }; | ||
60 | |||
55 | static struct platform_device scif1_device = { | 61 | static struct platform_device scif1_device = { |
56 | .name = "sh-sci", | 62 | .name = "sh-sci", |
57 | .id = 1, | 63 | .id = 1, |
64 | .resource = scif1_resources, | ||
65 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
58 | .dev = { | 66 | .dev = { |
59 | .platform_data = &scif1_platform_data, | 67 | .platform_data = &scif1_platform_data, |
60 | }, | 68 | }, |
61 | }; | 69 | }; |
62 | 70 | ||
63 | static struct plat_sci_port scif2_platform_data = { | 71 | static struct plat_sci_port scif2_platform_data = { |
64 | .mapbase = 0xFFE42000, | ||
65 | .flags = UPF_BOOT_AUTOCONF, | 72 | .flags = UPF_BOOT_AUTOCONF, |
66 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
67 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
68 | .type = PORT_SCIF, | 74 | .type = PORT_SCIF, |
69 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x900)), | ||
70 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 75 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
71 | }; | 76 | }; |
72 | 77 | ||
78 | static struct resource scif2_resources[] = { | ||
79 | DEFINE_RES_MEM(0xffe42000, 0x100), | ||
80 | DEFINE_RES_IRQ(evt2irq(0x900)), | ||
81 | }; | ||
82 | |||
73 | static struct platform_device scif2_device = { | 83 | static struct platform_device scif2_device = { |
74 | .name = "sh-sci", | 84 | .name = "sh-sci", |
75 | .id = 2, | 85 | .id = 2, |
86 | .resource = scif2_resources, | ||
87 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
76 | .dev = { | 88 | .dev = { |
77 | .platform_data = &scif2_platform_data, | 89 | .platform_data = &scif2_platform_data, |
78 | }, | 90 | }, |
79 | }; | 91 | }; |
80 | 92 | ||
81 | static struct plat_sci_port scif3_platform_data = { | 93 | static struct plat_sci_port scif3_platform_data = { |
82 | .mapbase = 0xFFE43000, | ||
83 | .flags = UPF_BOOT_AUTOCONF, | 94 | .flags = UPF_BOOT_AUTOCONF, |
84 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 95 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
85 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
86 | .type = PORT_SCIF, | 96 | .type = PORT_SCIF, |
87 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x920)), | ||
88 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 97 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
89 | }; | 98 | }; |
90 | 99 | ||
100 | static struct resource scif3_resources[] = { | ||
101 | DEFINE_RES_MEM(0xffe43000, 0x100), | ||
102 | DEFINE_RES_IRQ(evt2irq(0x920)), | ||
103 | }; | ||
104 | |||
91 | static struct platform_device scif3_device = { | 105 | static struct platform_device scif3_device = { |
92 | .name = "sh-sci", | 106 | .name = "sh-sci", |
93 | .id = 3, | 107 | .id = 3, |
108 | .resource = scif3_resources, | ||
109 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
94 | .dev = { | 110 | .dev = { |
95 | .platform_data = &scif3_platform_data, | 111 | .platform_data = &scif3_platform_data, |
96 | }, | 112 | }, |
97 | }; | 113 | }; |
98 | 114 | ||
99 | static struct plat_sci_port scif4_platform_data = { | 115 | static struct plat_sci_port scif4_platform_data = { |
100 | .mapbase = 0xFFE44000, | ||
101 | .flags = UPF_BOOT_AUTOCONF, | 116 | .flags = UPF_BOOT_AUTOCONF, |
102 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 117 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
103 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
104 | .type = PORT_SCIF, | 118 | .type = PORT_SCIF, |
105 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x940)), | ||
106 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 119 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
107 | }; | 120 | }; |
108 | 121 | ||
122 | static struct resource scif4_resources[] = { | ||
123 | DEFINE_RES_MEM(0xffe44000, 0x100), | ||
124 | DEFINE_RES_IRQ(evt2irq(0x940)), | ||
125 | }; | ||
126 | |||
109 | static struct platform_device scif4_device = { | 127 | static struct platform_device scif4_device = { |
110 | .name = "sh-sci", | 128 | .name = "sh-sci", |
111 | .id = 4, | 129 | .id = 4, |
130 | .resource = scif4_resources, | ||
131 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
112 | .dev = { | 132 | .dev = { |
113 | .platform_data = &scif4_platform_data, | 133 | .platform_data = &scif4_platform_data, |
114 | }, | 134 | }, |
115 | }; | 135 | }; |
116 | 136 | ||
117 | static struct plat_sci_port scif5_platform_data = { | 137 | static struct plat_sci_port scif5_platform_data = { |
118 | .mapbase = 0xFFE43000, | ||
119 | .flags = UPF_BOOT_AUTOCONF, | 138 | .flags = UPF_BOOT_AUTOCONF, |
120 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 139 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
121 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
122 | .type = PORT_SCIF, | 140 | .type = PORT_SCIF, |
123 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x960)), | ||
124 | .regtype = SCIx_SH4_SCIF_REGTYPE, | 141 | .regtype = SCIx_SH4_SCIF_REGTYPE, |
125 | }; | 142 | }; |
126 | 143 | ||
144 | static struct resource scif5_resources[] = { | ||
145 | DEFINE_RES_MEM(0xffe43000, 0x100), | ||
146 | DEFINE_RES_IRQ(evt2irq(0x960)), | ||
147 | }; | ||
148 | |||
127 | static struct platform_device scif5_device = { | 149 | static struct platform_device scif5_device = { |
128 | .name = "sh-sci", | 150 | .name = "sh-sci", |
129 | .id = 5, | 151 | .id = 5, |
152 | .resource = scif5_resources, | ||
153 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
130 | .dev = { | 154 | .dev = { |
131 | .platform_data = &scif5_platform_data, | 155 | .platform_data = &scif5_platform_data, |
132 | }, | 156 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c index 9079a0f9ea9b..e43e5db53913 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c | |||
@@ -24,51 +24,63 @@ | |||
24 | #include <cpu/sh7757.h> | 24 | #include <cpu/sh7757.h> |
25 | 25 | ||
26 | static struct plat_sci_port scif2_platform_data = { | 26 | static struct plat_sci_port scif2_platform_data = { |
27 | .mapbase = 0xfe4b0000, /* SCIF2 */ | ||
28 | .flags = UPF_BOOT_AUTOCONF, | 27 | .flags = UPF_BOOT_AUTOCONF, |
29 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 28 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
30 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
31 | .type = PORT_SCIF, | 29 | .type = PORT_SCIF, |
32 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | 30 | }; |
31 | |||
32 | static struct resource scif2_resources[] = { | ||
33 | DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */ | ||
34 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
33 | }; | 35 | }; |
34 | 36 | ||
35 | static struct platform_device scif2_device = { | 37 | static struct platform_device scif2_device = { |
36 | .name = "sh-sci", | 38 | .name = "sh-sci", |
37 | .id = 0, | 39 | .id = 0, |
40 | .resource = scif2_resources, | ||
41 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
38 | .dev = { | 42 | .dev = { |
39 | .platform_data = &scif2_platform_data, | 43 | .platform_data = &scif2_platform_data, |
40 | }, | 44 | }, |
41 | }; | 45 | }; |
42 | 46 | ||
43 | static struct plat_sci_port scif3_platform_data = { | 47 | static struct plat_sci_port scif3_platform_data = { |
44 | .mapbase = 0xfe4c0000, /* SCIF3 */ | ||
45 | .flags = UPF_BOOT_AUTOCONF, | 48 | .flags = UPF_BOOT_AUTOCONF, |
46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 49 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
47 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
48 | .type = PORT_SCIF, | 50 | .type = PORT_SCIF, |
49 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | 51 | }; |
52 | |||
53 | static struct resource scif3_resources[] = { | ||
54 | DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */ | ||
55 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
50 | }; | 56 | }; |
51 | 57 | ||
52 | static struct platform_device scif3_device = { | 58 | static struct platform_device scif3_device = { |
53 | .name = "sh-sci", | 59 | .name = "sh-sci", |
54 | .id = 1, | 60 | .id = 1, |
61 | .resource = scif3_resources, | ||
62 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
55 | .dev = { | 63 | .dev = { |
56 | .platform_data = &scif3_platform_data, | 64 | .platform_data = &scif3_platform_data, |
57 | }, | 65 | }, |
58 | }; | 66 | }; |
59 | 67 | ||
60 | static struct plat_sci_port scif4_platform_data = { | 68 | static struct plat_sci_port scif4_platform_data = { |
61 | .mapbase = 0xfe4d0000, /* SCIF4 */ | ||
62 | .flags = UPF_BOOT_AUTOCONF, | 69 | .flags = UPF_BOOT_AUTOCONF, |
63 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 70 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
64 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
65 | .type = PORT_SCIF, | 71 | .type = PORT_SCIF, |
66 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xF00)), | 72 | }; |
73 | |||
74 | static struct resource scif4_resources[] = { | ||
75 | DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */ | ||
76 | DEFINE_RES_IRQ(evt2irq(0xf00)), | ||
67 | }; | 77 | }; |
68 | 78 | ||
69 | static struct platform_device scif4_device = { | 79 | static struct platform_device scif4_device = { |
70 | .name = "sh-sci", | 80 | .name = "sh-sci", |
71 | .id = 2, | 81 | .id = 2, |
82 | .resource = scif4_resources, | ||
83 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
72 | .dev = { | 84 | .dev = { |
73 | .platform_data = &scif4_platform_data, | 85 | .platform_data = &scif4_platform_data, |
74 | }, | 86 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c index 1686acaaf45a..5eebbd7f4c21 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c | |||
@@ -19,54 +19,66 @@ | |||
19 | #include <linux/usb/ohci_pdriver.h> | 19 | #include <linux/usb/ohci_pdriver.h> |
20 | 20 | ||
21 | static struct plat_sci_port scif0_platform_data = { | 21 | static struct plat_sci_port scif0_platform_data = { |
22 | .mapbase = 0xffe00000, | ||
23 | .flags = UPF_BOOT_AUTOCONF, | 22 | .flags = UPF_BOOT_AUTOCONF, |
24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
25 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
26 | .type = PORT_SCIF, | 24 | .type = PORT_SCIF, |
27 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
28 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 25 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
29 | }; | 26 | }; |
30 | 27 | ||
28 | static struct resource scif0_resources[] = { | ||
29 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
30 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
31 | }; | ||
32 | |||
31 | static struct platform_device scif0_device = { | 33 | static struct platform_device scif0_device = { |
32 | .name = "sh-sci", | 34 | .name = "sh-sci", |
33 | .id = 0, | 35 | .id = 0, |
36 | .resource = scif0_resources, | ||
37 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
34 | .dev = { | 38 | .dev = { |
35 | .platform_data = &scif0_platform_data, | 39 | .platform_data = &scif0_platform_data, |
36 | }, | 40 | }, |
37 | }; | 41 | }; |
38 | 42 | ||
39 | static struct plat_sci_port scif1_platform_data = { | 43 | static struct plat_sci_port scif1_platform_data = { |
40 | .mapbase = 0xffe08000, | ||
41 | .flags = UPF_BOOT_AUTOCONF, | 44 | .flags = UPF_BOOT_AUTOCONF, |
42 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 45 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
43 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
44 | .type = PORT_SCIF, | 46 | .type = PORT_SCIF, |
45 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | ||
46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 47 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
47 | }; | 48 | }; |
48 | 49 | ||
50 | static struct resource scif1_resources[] = { | ||
51 | DEFINE_RES_MEM(0xffe08000, 0x100), | ||
52 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
53 | }; | ||
54 | |||
49 | static struct platform_device scif1_device = { | 55 | static struct platform_device scif1_device = { |
50 | .name = "sh-sci", | 56 | .name = "sh-sci", |
51 | .id = 1, | 57 | .id = 1, |
58 | .resource = scif1_resources, | ||
59 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
52 | .dev = { | 60 | .dev = { |
53 | .platform_data = &scif1_platform_data, | 61 | .platform_data = &scif1_platform_data, |
54 | }, | 62 | }, |
55 | }; | 63 | }; |
56 | 64 | ||
57 | static struct plat_sci_port scif2_platform_data = { | 65 | static struct plat_sci_port scif2_platform_data = { |
58 | .mapbase = 0xffe10000, | ||
59 | .flags = UPF_BOOT_AUTOCONF, | 66 | .flags = UPF_BOOT_AUTOCONF, |
60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 67 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
61 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
62 | .type = PORT_SCIF, | 68 | .type = PORT_SCIF, |
63 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xf00)), | ||
64 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 69 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
65 | }; | 70 | }; |
66 | 71 | ||
72 | static struct resource scif2_resources[] = { | ||
73 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
74 | DEFINE_RES_IRQ(evt2irq(0xf00)), | ||
75 | }; | ||
76 | |||
67 | static struct platform_device scif2_device = { | 77 | static struct platform_device scif2_device = { |
68 | .name = "sh-sci", | 78 | .name = "sh-sci", |
69 | .id = 2, | 79 | .id = 2, |
80 | .resource = scif2_resources, | ||
81 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
70 | .dev = { | 82 | .dev = { |
71 | .platform_data = &scif2_platform_data, | 83 | .platform_data = &scif2_platform_data, |
72 | }, | 84 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c index 256ea7a45164..e1ba8cb74e5a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c | |||
@@ -16,170 +16,210 @@ | |||
16 | #include <linux/io.h> | 16 | #include <linux/io.h> |
17 | 17 | ||
18 | static struct plat_sci_port scif0_platform_data = { | 18 | static struct plat_sci_port scif0_platform_data = { |
19 | .mapbase = 0xff923000, | ||
20 | .flags = UPF_BOOT_AUTOCONF, | 19 | .flags = UPF_BOOT_AUTOCONF, |
21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 20 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
22 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
23 | .type = PORT_SCIF, | 21 | .type = PORT_SCIF, |
24 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), | 22 | }; |
23 | |||
24 | static struct resource scif0_resources[] = { | ||
25 | DEFINE_RES_MEM(0xff923000, 0x100), | ||
26 | DEFINE_RES_IRQ(evt2irq(0x9a0)), | ||
25 | }; | 27 | }; |
26 | 28 | ||
27 | static struct platform_device scif0_device = { | 29 | static struct platform_device scif0_device = { |
28 | .name = "sh-sci", | 30 | .name = "sh-sci", |
29 | .id = 0, | 31 | .id = 0, |
32 | .resource = scif0_resources, | ||
33 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
30 | .dev = { | 34 | .dev = { |
31 | .platform_data = &scif0_platform_data, | 35 | .platform_data = &scif0_platform_data, |
32 | }, | 36 | }, |
33 | }; | 37 | }; |
34 | 38 | ||
35 | static struct plat_sci_port scif1_platform_data = { | 39 | static struct plat_sci_port scif1_platform_data = { |
36 | .mapbase = 0xff924000, | ||
37 | .flags = UPF_BOOT_AUTOCONF, | 40 | .flags = UPF_BOOT_AUTOCONF, |
38 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
39 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
40 | .type = PORT_SCIF, | 42 | .type = PORT_SCIF, |
41 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), | 43 | }; |
44 | |||
45 | static struct resource scif1_resources[] = { | ||
46 | DEFINE_RES_MEM(0xff924000, 0x100), | ||
47 | DEFINE_RES_IRQ(evt2irq(0x9c0)), | ||
42 | }; | 48 | }; |
43 | 49 | ||
44 | static struct platform_device scif1_device = { | 50 | static struct platform_device scif1_device = { |
45 | .name = "sh-sci", | 51 | .name = "sh-sci", |
46 | .id = 1, | 52 | .id = 1, |
53 | .resource = scif1_resources, | ||
54 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
47 | .dev = { | 55 | .dev = { |
48 | .platform_data = &scif1_platform_data, | 56 | .platform_data = &scif1_platform_data, |
49 | }, | 57 | }, |
50 | }; | 58 | }; |
51 | 59 | ||
52 | static struct plat_sci_port scif2_platform_data = { | 60 | static struct plat_sci_port scif2_platform_data = { |
53 | .mapbase = 0xff925000, | ||
54 | .flags = UPF_BOOT_AUTOCONF, | 61 | .flags = UPF_BOOT_AUTOCONF, |
55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 62 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
56 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
57 | .type = PORT_SCIF, | 63 | .type = PORT_SCIF, |
58 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), | 64 | }; |
65 | |||
66 | static struct resource scif2_resources[] = { | ||
67 | DEFINE_RES_MEM(0xff925000, 0x100), | ||
68 | DEFINE_RES_IRQ(evt2irq(0x9e0)), | ||
59 | }; | 69 | }; |
60 | 70 | ||
61 | static struct platform_device scif2_device = { | 71 | static struct platform_device scif2_device = { |
62 | .name = "sh-sci", | 72 | .name = "sh-sci", |
63 | .id = 2, | 73 | .id = 2, |
74 | .resource = scif2_resources, | ||
75 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
64 | .dev = { | 76 | .dev = { |
65 | .platform_data = &scif2_platform_data, | 77 | .platform_data = &scif2_platform_data, |
66 | }, | 78 | }, |
67 | }; | 79 | }; |
68 | 80 | ||
69 | static struct plat_sci_port scif3_platform_data = { | 81 | static struct plat_sci_port scif3_platform_data = { |
70 | .mapbase = 0xff926000, | ||
71 | .flags = UPF_BOOT_AUTOCONF, | 82 | .flags = UPF_BOOT_AUTOCONF, |
72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 83 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
73 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
74 | .type = PORT_SCIF, | 84 | .type = PORT_SCIF, |
75 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), | 85 | }; |
86 | |||
87 | static struct resource scif3_resources[] = { | ||
88 | DEFINE_RES_MEM(0xff926000, 0x100), | ||
89 | DEFINE_RES_IRQ(evt2irq(0xa00)), | ||
76 | }; | 90 | }; |
77 | 91 | ||
78 | static struct platform_device scif3_device = { | 92 | static struct platform_device scif3_device = { |
79 | .name = "sh-sci", | 93 | .name = "sh-sci", |
80 | .id = 3, | 94 | .id = 3, |
95 | .resource = scif3_resources, | ||
96 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
81 | .dev = { | 97 | .dev = { |
82 | .platform_data = &scif3_platform_data, | 98 | .platform_data = &scif3_platform_data, |
83 | }, | 99 | }, |
84 | }; | 100 | }; |
85 | 101 | ||
86 | static struct plat_sci_port scif4_platform_data = { | 102 | static struct plat_sci_port scif4_platform_data = { |
87 | .mapbase = 0xff927000, | ||
88 | .flags = UPF_BOOT_AUTOCONF, | 103 | .flags = UPF_BOOT_AUTOCONF, |
89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 104 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
90 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
91 | .type = PORT_SCIF, | 105 | .type = PORT_SCIF, |
92 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), | 106 | }; |
107 | |||
108 | static struct resource scif4_resources[] = { | ||
109 | DEFINE_RES_MEM(0xff927000, 0x100), | ||
110 | DEFINE_RES_IRQ(evt2irq(0xa20)), | ||
93 | }; | 111 | }; |
94 | 112 | ||
95 | static struct platform_device scif4_device = { | 113 | static struct platform_device scif4_device = { |
96 | .name = "sh-sci", | 114 | .name = "sh-sci", |
97 | .id = 4, | 115 | .id = 4, |
116 | .resource = scif4_resources, | ||
117 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
98 | .dev = { | 118 | .dev = { |
99 | .platform_data = &scif4_platform_data, | 119 | .platform_data = &scif4_platform_data, |
100 | }, | 120 | }, |
101 | }; | 121 | }; |
102 | 122 | ||
103 | static struct plat_sci_port scif5_platform_data = { | 123 | static struct plat_sci_port scif5_platform_data = { |
104 | .mapbase = 0xff928000, | ||
105 | .flags = UPF_BOOT_AUTOCONF, | 124 | .flags = UPF_BOOT_AUTOCONF, |
106 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 125 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
107 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
108 | .type = PORT_SCIF, | 126 | .type = PORT_SCIF, |
109 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), | 127 | }; |
128 | |||
129 | static struct resource scif5_resources[] = { | ||
130 | DEFINE_RES_MEM(0xff928000, 0x100), | ||
131 | DEFINE_RES_IRQ(evt2irq(0xa40)), | ||
110 | }; | 132 | }; |
111 | 133 | ||
112 | static struct platform_device scif5_device = { | 134 | static struct platform_device scif5_device = { |
113 | .name = "sh-sci", | 135 | .name = "sh-sci", |
114 | .id = 5, | 136 | .id = 5, |
137 | .resource = scif5_resources, | ||
138 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
115 | .dev = { | 139 | .dev = { |
116 | .platform_data = &scif5_platform_data, | 140 | .platform_data = &scif5_platform_data, |
117 | }, | 141 | }, |
118 | }; | 142 | }; |
119 | 143 | ||
120 | static struct plat_sci_port scif6_platform_data = { | 144 | static struct plat_sci_port scif6_platform_data = { |
121 | .mapbase = 0xff929000, | ||
122 | .flags = UPF_BOOT_AUTOCONF, | 145 | .flags = UPF_BOOT_AUTOCONF, |
123 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 146 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
124 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
125 | .type = PORT_SCIF, | 147 | .type = PORT_SCIF, |
126 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), | 148 | }; |
149 | |||
150 | static struct resource scif6_resources[] = { | ||
151 | DEFINE_RES_MEM(0xff929000, 0x100), | ||
152 | DEFINE_RES_IRQ(evt2irq(0xa60)), | ||
127 | }; | 153 | }; |
128 | 154 | ||
129 | static struct platform_device scif6_device = { | 155 | static struct platform_device scif6_device = { |
130 | .name = "sh-sci", | 156 | .name = "sh-sci", |
131 | .id = 6, | 157 | .id = 6, |
158 | .resource = scif6_resources, | ||
159 | .num_resources = ARRAY_SIZE(scif6_resources), | ||
132 | .dev = { | 160 | .dev = { |
133 | .platform_data = &scif6_platform_data, | 161 | .platform_data = &scif6_platform_data, |
134 | }, | 162 | }, |
135 | }; | 163 | }; |
136 | 164 | ||
137 | static struct plat_sci_port scif7_platform_data = { | 165 | static struct plat_sci_port scif7_platform_data = { |
138 | .mapbase = 0xff92a000, | ||
139 | .flags = UPF_BOOT_AUTOCONF, | 166 | .flags = UPF_BOOT_AUTOCONF, |
140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 167 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
141 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
142 | .type = PORT_SCIF, | 168 | .type = PORT_SCIF, |
143 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), | 169 | }; |
170 | |||
171 | static struct resource scif7_resources[] = { | ||
172 | DEFINE_RES_MEM(0xff92a000, 0x100), | ||
173 | DEFINE_RES_IRQ(evt2irq(0xa80)), | ||
144 | }; | 174 | }; |
145 | 175 | ||
146 | static struct platform_device scif7_device = { | 176 | static struct platform_device scif7_device = { |
147 | .name = "sh-sci", | 177 | .name = "sh-sci", |
148 | .id = 7, | 178 | .id = 7, |
179 | .resource = scif7_resources, | ||
180 | .num_resources = ARRAY_SIZE(scif7_resources), | ||
149 | .dev = { | 181 | .dev = { |
150 | .platform_data = &scif7_platform_data, | 182 | .platform_data = &scif7_platform_data, |
151 | }, | 183 | }, |
152 | }; | 184 | }; |
153 | 185 | ||
154 | static struct plat_sci_port scif8_platform_data = { | 186 | static struct plat_sci_port scif8_platform_data = { |
155 | .mapbase = 0xff92b000, | ||
156 | .flags = UPF_BOOT_AUTOCONF, | 187 | .flags = UPF_BOOT_AUTOCONF, |
157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 188 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
158 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
159 | .type = PORT_SCIF, | 189 | .type = PORT_SCIF, |
160 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), | 190 | }; |
191 | |||
192 | static struct resource scif8_resources[] = { | ||
193 | DEFINE_RES_MEM(0xff92b000, 0x100), | ||
194 | DEFINE_RES_IRQ(evt2irq(0xaa0)), | ||
161 | }; | 195 | }; |
162 | 196 | ||
163 | static struct platform_device scif8_device = { | 197 | static struct platform_device scif8_device = { |
164 | .name = "sh-sci", | 198 | .name = "sh-sci", |
165 | .id = 8, | 199 | .id = 8, |
200 | .resource = scif8_resources, | ||
201 | .num_resources = ARRAY_SIZE(scif8_resources), | ||
166 | .dev = { | 202 | .dev = { |
167 | .platform_data = &scif8_platform_data, | 203 | .platform_data = &scif8_platform_data, |
168 | }, | 204 | }, |
169 | }; | 205 | }; |
170 | 206 | ||
171 | static struct plat_sci_port scif9_platform_data = { | 207 | static struct plat_sci_port scif9_platform_data = { |
172 | .mapbase = 0xff92c000, | ||
173 | .flags = UPF_BOOT_AUTOCONF, | 208 | .flags = UPF_BOOT_AUTOCONF, |
174 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, | 209 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
175 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
176 | .type = PORT_SCIF, | 210 | .type = PORT_SCIF, |
177 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), | 211 | }; |
212 | |||
213 | static struct resource scif9_resources[] = { | ||
214 | DEFINE_RES_MEM(0xff92c000, 0x100), | ||
215 | DEFINE_RES_IRQ(evt2irq(0xac0)), | ||
178 | }; | 216 | }; |
179 | 217 | ||
180 | static struct platform_device scif9_device = { | 218 | static struct platform_device scif9_device = { |
181 | .name = "sh-sci", | 219 | .name = "sh-sci", |
182 | .id = 9, | 220 | .id = 9, |
221 | .resource = scif9_resources, | ||
222 | .num_resources = ARRAY_SIZE(scif9_resources), | ||
183 | .dev = { | 223 | .dev = { |
184 | .platform_data = &scif9_platform_data, | 224 | .platform_data = &scif9_platform_data, |
185 | }, | 225 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index de45b704687a..668e54bafa86 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c | |||
@@ -18,36 +18,44 @@ | |||
18 | #include <cpu/dma-register.h> | 18 | #include <cpu/dma-register.h> |
19 | 19 | ||
20 | static struct plat_sci_port scif0_platform_data = { | 20 | static struct plat_sci_port scif0_platform_data = { |
21 | .mapbase = 0xffe00000, | ||
22 | .flags = UPF_BOOT_AUTOCONF, | 21 | .flags = UPF_BOOT_AUTOCONF, |
23 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
24 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
25 | .type = PORT_SCIF, | 23 | .type = PORT_SCIF, |
26 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
27 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 24 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
28 | }; | 25 | }; |
29 | 26 | ||
27 | static struct resource scif0_resources[] = { | ||
28 | DEFINE_RES_MEM(0xffe00000, 0x100), | ||
29 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
30 | }; | ||
31 | |||
30 | static struct platform_device scif0_device = { | 32 | static struct platform_device scif0_device = { |
31 | .name = "sh-sci", | 33 | .name = "sh-sci", |
32 | .id = 0, | 34 | .id = 0, |
35 | .resource = scif0_resources, | ||
36 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
33 | .dev = { | 37 | .dev = { |
34 | .platform_data = &scif0_platform_data, | 38 | .platform_data = &scif0_platform_data, |
35 | }, | 39 | }, |
36 | }; | 40 | }; |
37 | 41 | ||
38 | static struct plat_sci_port scif1_platform_data = { | 42 | static struct plat_sci_port scif1_platform_data = { |
39 | .mapbase = 0xffe10000, | ||
40 | .flags = UPF_BOOT_AUTOCONF, | 43 | .flags = UPF_BOOT_AUTOCONF, |
41 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 44 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
42 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
43 | .type = PORT_SCIF, | 45 | .type = PORT_SCIF, |
44 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xb80)), | ||
45 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 46 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
46 | }; | 47 | }; |
47 | 48 | ||
49 | static struct resource scif1_resources[] = { | ||
50 | DEFINE_RES_MEM(0xffe10000, 0x100), | ||
51 | DEFINE_RES_IRQ(evt2irq(0xb80)), | ||
52 | }; | ||
53 | |||
48 | static struct platform_device scif1_device = { | 54 | static struct platform_device scif1_device = { |
49 | .name = "sh-sci", | 55 | .name = "sh-sci", |
50 | .id = 1, | 56 | .id = 1, |
57 | .resource = scif1_resources, | ||
58 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
51 | .dev = { | 59 | .dev = { |
52 | .platform_data = &scif1_platform_data, | 60 | .platform_data = &scif1_platform_data, |
53 | }, | 61 | }, |
@@ -409,9 +417,7 @@ void __init plat_early_device_setup(void) | |||
409 | { | 417 | { |
410 | if (mach_is_sh2007()) { | 418 | if (mach_is_sh2007()) { |
411 | scif0_platform_data.scscr &= ~SCSCR_CKE1; | 419 | scif0_platform_data.scscr &= ~SCSCR_CKE1; |
412 | scif0_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
413 | scif1_platform_data.scscr &= ~SCSCR_CKE1; | 420 | scif1_platform_data.scscr &= ~SCSCR_CKE1; |
414 | scif1_platform_data.scbrr_algo_id = SCBRR_ALGO_2; | ||
415 | } | 421 | } |
416 | 422 | ||
417 | early_platform_add_devices(sh7780_early_devices, | 423 | early_platform_add_devices(sh7780_early_devices, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index 0968ecb962e6..4aa679140209 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
@@ -20,108 +20,132 @@ | |||
20 | #include <cpu/dma-register.h> | 20 | #include <cpu/dma-register.h> |
21 | 21 | ||
22 | static struct plat_sci_port scif0_platform_data = { | 22 | static struct plat_sci_port scif0_platform_data = { |
23 | .mapbase = 0xffea0000, | ||
24 | .flags = UPF_BOOT_AUTOCONF, | 23 | .flags = UPF_BOOT_AUTOCONF, |
25 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 24 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
26 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
27 | .type = PORT_SCIF, | 25 | .type = PORT_SCIF, |
28 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x700)), | ||
29 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 26 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
30 | }; | 27 | }; |
31 | 28 | ||
29 | static struct resource scif0_resources[] = { | ||
30 | DEFINE_RES_MEM(0xffea0000, 0x100), | ||
31 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
32 | }; | ||
33 | |||
32 | static struct platform_device scif0_device = { | 34 | static struct platform_device scif0_device = { |
33 | .name = "sh-sci", | 35 | .name = "sh-sci", |
34 | .id = 0, | 36 | .id = 0, |
37 | .resource = scif0_resources, | ||
38 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
35 | .dev = { | 39 | .dev = { |
36 | .platform_data = &scif0_platform_data, | 40 | .platform_data = &scif0_platform_data, |
37 | }, | 41 | }, |
38 | }; | 42 | }; |
39 | 43 | ||
40 | static struct plat_sci_port scif1_platform_data = { | 44 | static struct plat_sci_port scif1_platform_data = { |
41 | .mapbase = 0xffeb0000, | ||
42 | .flags = UPF_BOOT_AUTOCONF, | 45 | .flags = UPF_BOOT_AUTOCONF, |
43 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 46 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
44 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
45 | .type = PORT_SCIF, | 47 | .type = PORT_SCIF, |
46 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), | ||
47 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 48 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
48 | }; | 49 | }; |
49 | 50 | ||
51 | static struct resource scif1_resources[] = { | ||
52 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
53 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
54 | }; | ||
55 | |||
50 | static struct platform_device scif1_device = { | 56 | static struct platform_device scif1_device = { |
51 | .name = "sh-sci", | 57 | .name = "sh-sci", |
52 | .id = 1, | 58 | .id = 1, |
59 | .resource = scif1_resources, | ||
60 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
53 | .dev = { | 61 | .dev = { |
54 | .platform_data = &scif1_platform_data, | 62 | .platform_data = &scif1_platform_data, |
55 | }, | 63 | }, |
56 | }; | 64 | }; |
57 | 65 | ||
58 | static struct plat_sci_port scif2_platform_data = { | 66 | static struct plat_sci_port scif2_platform_data = { |
59 | .mapbase = 0xffec0000, | ||
60 | .flags = UPF_BOOT_AUTOCONF, | 67 | .flags = UPF_BOOT_AUTOCONF, |
61 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 68 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
62 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
63 | .type = PORT_SCIF, | 69 | .type = PORT_SCIF, |
64 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x980)), | ||
65 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 70 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
66 | }; | 71 | }; |
67 | 72 | ||
73 | static struct resource scif2_resources[] = { | ||
74 | DEFINE_RES_MEM(0xffec0000, 0x100), | ||
75 | DEFINE_RES_IRQ(evt2irq(0x980)), | ||
76 | }; | ||
77 | |||
68 | static struct platform_device scif2_device = { | 78 | static struct platform_device scif2_device = { |
69 | .name = "sh-sci", | 79 | .name = "sh-sci", |
70 | .id = 2, | 80 | .id = 2, |
81 | .resource = scif2_resources, | ||
82 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
71 | .dev = { | 83 | .dev = { |
72 | .platform_data = &scif2_platform_data, | 84 | .platform_data = &scif2_platform_data, |
73 | }, | 85 | }, |
74 | }; | 86 | }; |
75 | 87 | ||
76 | static struct plat_sci_port scif3_platform_data = { | 88 | static struct plat_sci_port scif3_platform_data = { |
77 | .mapbase = 0xffed0000, | ||
78 | .flags = UPF_BOOT_AUTOCONF, | 89 | .flags = UPF_BOOT_AUTOCONF, |
79 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 90 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
80 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
81 | .type = PORT_SCIF, | 91 | .type = PORT_SCIF, |
82 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), | ||
83 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 92 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
84 | }; | 93 | }; |
85 | 94 | ||
95 | static struct resource scif3_resources[] = { | ||
96 | DEFINE_RES_MEM(0xffed0000, 0x100), | ||
97 | DEFINE_RES_IRQ(evt2irq(0x9a0)), | ||
98 | }; | ||
99 | |||
86 | static struct platform_device scif3_device = { | 100 | static struct platform_device scif3_device = { |
87 | .name = "sh-sci", | 101 | .name = "sh-sci", |
88 | .id = 3, | 102 | .id = 3, |
103 | .resource = scif3_resources, | ||
104 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
89 | .dev = { | 105 | .dev = { |
90 | .platform_data = &scif3_platform_data, | 106 | .platform_data = &scif3_platform_data, |
91 | }, | 107 | }, |
92 | }; | 108 | }; |
93 | 109 | ||
94 | static struct plat_sci_port scif4_platform_data = { | 110 | static struct plat_sci_port scif4_platform_data = { |
95 | .mapbase = 0xffee0000, | ||
96 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
97 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 112 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
98 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
99 | .type = PORT_SCIF, | 113 | .type = PORT_SCIF, |
100 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), | ||
101 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 114 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
102 | }; | 115 | }; |
103 | 116 | ||
117 | static struct resource scif4_resources[] = { | ||
118 | DEFINE_RES_MEM(0xffee0000, 0x100), | ||
119 | DEFINE_RES_IRQ(evt2irq(0x9c0)), | ||
120 | }; | ||
121 | |||
104 | static struct platform_device scif4_device = { | 122 | static struct platform_device scif4_device = { |
105 | .name = "sh-sci", | 123 | .name = "sh-sci", |
106 | .id = 4, | 124 | .id = 4, |
125 | .resource = scif4_resources, | ||
126 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
107 | .dev = { | 127 | .dev = { |
108 | .platform_data = &scif4_platform_data, | 128 | .platform_data = &scif4_platform_data, |
109 | }, | 129 | }, |
110 | }; | 130 | }; |
111 | 131 | ||
112 | static struct plat_sci_port scif5_platform_data = { | 132 | static struct plat_sci_port scif5_platform_data = { |
113 | .mapbase = 0xffef0000, | ||
114 | .flags = UPF_BOOT_AUTOCONF, | 133 | .flags = UPF_BOOT_AUTOCONF, |
115 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 134 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
116 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
117 | .type = PORT_SCIF, | 135 | .type = PORT_SCIF, |
118 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), | ||
119 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 136 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
120 | }; | 137 | }; |
121 | 138 | ||
139 | static struct resource scif5_resources[] = { | ||
140 | DEFINE_RES_MEM(0xffef0000, 0x100), | ||
141 | DEFINE_RES_IRQ(evt2irq(0x9e0)), | ||
142 | }; | ||
143 | |||
122 | static struct platform_device scif5_device = { | 144 | static struct platform_device scif5_device = { |
123 | .name = "sh-sci", | 145 | .name = "sh-sci", |
124 | .id = 5, | 146 | .id = 5, |
147 | .resource = scif5_resources, | ||
148 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
125 | .dev = { | 149 | .dev = { |
126 | .platform_data = &scif5_platform_data, | 150 | .platform_data = &scif5_platform_data, |
127 | }, | 151 | }, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c index ab52d4d4484d..5d619a551a3b 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c | |||
@@ -28,21 +28,25 @@ | |||
28 | #include <asm/mmzone.h> | 28 | #include <asm/mmzone.h> |
29 | 29 | ||
30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
31 | .mapbase = 0xffea0000, | ||
32 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
33 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
34 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
35 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
36 | .irqs = { evt2irq(0x700), | ||
37 | evt2irq(0x720), | ||
38 | evt2irq(0x760), | ||
39 | evt2irq(0x740) }, | ||
40 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 34 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
41 | }; | 35 | }; |
42 | 36 | ||
37 | static struct resource scif0_resources[] = { | ||
38 | DEFINE_RES_MEM(0xffea0000, 0x100), | ||
39 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
40 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
41 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
42 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
43 | }; | ||
44 | |||
43 | static struct platform_device scif0_device = { | 45 | static struct platform_device scif0_device = { |
44 | .name = "sh-sci", | 46 | .name = "sh-sci", |
45 | .id = 0, | 47 | .id = 0, |
48 | .resource = scif0_resources, | ||
49 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
46 | .dev = { | 50 | .dev = { |
47 | .platform_data = &scif0_platform_data, | 51 | .platform_data = &scif0_platform_data, |
48 | }, | 52 | }, |
@@ -52,90 +56,119 @@ static struct platform_device scif0_device = { | |||
52 | * The rest of these all have multiplexed IRQs | 56 | * The rest of these all have multiplexed IRQs |
53 | */ | 57 | */ |
54 | static struct plat_sci_port scif1_platform_data = { | 58 | static struct plat_sci_port scif1_platform_data = { |
55 | .mapbase = 0xffeb0000, | ||
56 | .flags = UPF_BOOT_AUTOCONF, | 59 | .flags = UPF_BOOT_AUTOCONF, |
57 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 60 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
58 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
59 | .type = PORT_SCIF, | 61 | .type = PORT_SCIF, |
60 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x780)), | ||
61 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 62 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
62 | }; | 63 | }; |
63 | 64 | ||
65 | static struct resource scif1_resources[] = { | ||
66 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
67 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
68 | }; | ||
69 | |||
70 | static struct resource scif1_demux_resources[] = { | ||
71 | DEFINE_RES_MEM(0xffeb0000, 0x100), | ||
72 | /* Placeholders, see sh7786_devices_setup() */ | ||
73 | DEFINE_RES_IRQ(0), | ||
74 | DEFINE_RES_IRQ(0), | ||
75 | DEFINE_RES_IRQ(0), | ||
76 | DEFINE_RES_IRQ(0), | ||
77 | }; | ||
78 | |||
64 | static struct platform_device scif1_device = { | 79 | static struct platform_device scif1_device = { |
65 | .name = "sh-sci", | 80 | .name = "sh-sci", |
66 | .id = 1, | 81 | .id = 1, |
82 | .resource = scif1_resources, | ||
83 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
67 | .dev = { | 84 | .dev = { |
68 | .platform_data = &scif1_platform_data, | 85 | .platform_data = &scif1_platform_data, |
69 | }, | 86 | }, |
70 | }; | 87 | }; |
71 | 88 | ||
72 | static struct plat_sci_port scif2_platform_data = { | 89 | static struct plat_sci_port scif2_platform_data = { |
73 | .mapbase = 0xffec0000, | ||
74 | .flags = UPF_BOOT_AUTOCONF, | 90 | .flags = UPF_BOOT_AUTOCONF, |
75 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 91 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
76 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
77 | .type = PORT_SCIF, | 92 | .type = PORT_SCIF, |
78 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x840)), | ||
79 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 93 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
80 | }; | 94 | }; |
81 | 95 | ||
96 | static struct resource scif2_resources[] = { | ||
97 | DEFINE_RES_MEM(0xffec0000, 0x100), | ||
98 | DEFINE_RES_IRQ(evt2irq(0x840)), | ||
99 | }; | ||
100 | |||
82 | static struct platform_device scif2_device = { | 101 | static struct platform_device scif2_device = { |
83 | .name = "sh-sci", | 102 | .name = "sh-sci", |
84 | .id = 2, | 103 | .id = 2, |
104 | .resource = scif2_resources, | ||
105 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
85 | .dev = { | 106 | .dev = { |
86 | .platform_data = &scif2_platform_data, | 107 | .platform_data = &scif2_platform_data, |
87 | }, | 108 | }, |
88 | }; | 109 | }; |
89 | 110 | ||
90 | static struct plat_sci_port scif3_platform_data = { | 111 | static struct plat_sci_port scif3_platform_data = { |
91 | .mapbase = 0xffed0000, | ||
92 | .flags = UPF_BOOT_AUTOCONF, | 112 | .flags = UPF_BOOT_AUTOCONF, |
93 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 113 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
94 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
95 | .type = PORT_SCIF, | 114 | .type = PORT_SCIF, |
96 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x860)), | ||
97 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 115 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
98 | }; | 116 | }; |
99 | 117 | ||
118 | static struct resource scif3_resources[] = { | ||
119 | DEFINE_RES_MEM(0xffed0000, 0x100), | ||
120 | DEFINE_RES_IRQ(evt2irq(0x860)), | ||
121 | }; | ||
122 | |||
100 | static struct platform_device scif3_device = { | 123 | static struct platform_device scif3_device = { |
101 | .name = "sh-sci", | 124 | .name = "sh-sci", |
102 | .id = 3, | 125 | .id = 3, |
126 | .resource = scif3_resources, | ||
127 | .num_resources = ARRAY_SIZE(scif3_resources), | ||
103 | .dev = { | 128 | .dev = { |
104 | .platform_data = &scif3_platform_data, | 129 | .platform_data = &scif3_platform_data, |
105 | }, | 130 | }, |
106 | }; | 131 | }; |
107 | 132 | ||
108 | static struct plat_sci_port scif4_platform_data = { | 133 | static struct plat_sci_port scif4_platform_data = { |
109 | .mapbase = 0xffee0000, | ||
110 | .flags = UPF_BOOT_AUTOCONF, | 134 | .flags = UPF_BOOT_AUTOCONF, |
111 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 135 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
112 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
113 | .type = PORT_SCIF, | 136 | .type = PORT_SCIF, |
114 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x880)), | ||
115 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 137 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
116 | }; | 138 | }; |
117 | 139 | ||
140 | static struct resource scif4_resources[] = { | ||
141 | DEFINE_RES_MEM(0xffee0000, 0x100), | ||
142 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
143 | }; | ||
144 | |||
118 | static struct platform_device scif4_device = { | 145 | static struct platform_device scif4_device = { |
119 | .name = "sh-sci", | 146 | .name = "sh-sci", |
120 | .id = 4, | 147 | .id = 4, |
148 | .resource = scif4_resources, | ||
149 | .num_resources = ARRAY_SIZE(scif4_resources), | ||
121 | .dev = { | 150 | .dev = { |
122 | .platform_data = &scif4_platform_data, | 151 | .platform_data = &scif4_platform_data, |
123 | }, | 152 | }, |
124 | }; | 153 | }; |
125 | 154 | ||
126 | static struct plat_sci_port scif5_platform_data = { | 155 | static struct plat_sci_port scif5_platform_data = { |
127 | .mapbase = 0xffef0000, | ||
128 | .flags = UPF_BOOT_AUTOCONF, | 156 | .flags = UPF_BOOT_AUTOCONF, |
129 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, | 157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_CKE1, |
130 | .scbrr_algo_id = SCBRR_ALGO_1, | ||
131 | .type = PORT_SCIF, | 158 | .type = PORT_SCIF, |
132 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x8a0)), | ||
133 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, | 159 | .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE, |
134 | }; | 160 | }; |
135 | 161 | ||
162 | static struct resource scif5_resources[] = { | ||
163 | DEFINE_RES_MEM(0xffef0000, 0x100), | ||
164 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
165 | }; | ||
166 | |||
136 | static struct platform_device scif5_device = { | 167 | static struct platform_device scif5_device = { |
137 | .name = "sh-sci", | 168 | .name = "sh-sci", |
138 | .id = 5, | 169 | .id = 5, |
170 | .resource = scif5_resources, | ||
171 | .num_resources = ARRAY_SIZE(scif5_resources), | ||
139 | .dev = { | 172 | .dev = { |
140 | .platform_data = &scif5_platform_data, | 173 | .platform_data = &scif5_platform_data, |
141 | }, | 174 | }, |
@@ -1037,13 +1070,16 @@ static int __init sh7786_devices_setup(void) | |||
1037 | */ | 1070 | */ |
1038 | irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); | 1071 | irq = intc_irq_lookup(sh7786_intc_desc.name, TXI1); |
1039 | if (irq > 0) { | 1072 | if (irq > 0) { |
1040 | scif1_platform_data.irqs[SCIx_TXI_IRQ] = irq; | 1073 | scif1_demux_resources[1].start = |
1041 | scif1_platform_data.irqs[SCIx_ERI_IRQ] = | ||
1042 | intc_irq_lookup(sh7786_intc_desc.name, ERI1); | 1074 | intc_irq_lookup(sh7786_intc_desc.name, ERI1); |
1043 | scif1_platform_data.irqs[SCIx_BRI_IRQ] = | 1075 | scif1_demux_resources[2].start = |
1044 | intc_irq_lookup(sh7786_intc_desc.name, BRI1); | ||
1045 | scif1_platform_data.irqs[SCIx_RXI_IRQ] = | ||
1046 | intc_irq_lookup(sh7786_intc_desc.name, RXI1); | 1076 | intc_irq_lookup(sh7786_intc_desc.name, RXI1); |
1077 | scif1_demux_resources[3].start = irq; | ||
1078 | scif1_demux_resources[4].start = | ||
1079 | intc_irq_lookup(sh7786_intc_desc.name, BRI1); | ||
1080 | |||
1081 | scif1_device.resource = scif1_demux_resources; | ||
1082 | scif1_device.num_resources = ARRAY_SIZE(scif1_demux_resources); | ||
1047 | } | 1083 | } |
1048 | 1084 | ||
1049 | ret = platform_add_devices(sh7786_early_devices, | 1085 | ret = platform_add_devices(sh7786_early_devices, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 688f7ed1bab1..0856bcbb1da0 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
@@ -28,60 +28,72 @@ | |||
28 | * all rather than adding infrastructure to hack around it. | 28 | * all rather than adding infrastructure to hack around it. |
29 | */ | 29 | */ |
30 | static struct plat_sci_port scif0_platform_data = { | 30 | static struct plat_sci_port scif0_platform_data = { |
31 | .mapbase = 0xffc30000, | ||
32 | .flags = UPF_BOOT_AUTOCONF, | 31 | .flags = UPF_BOOT_AUTOCONF, |
33 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 32 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
34 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
35 | .type = PORT_SCIF, | 33 | .type = PORT_SCIF, |
36 | .irqs = { evt2irq(0x700), | 34 | }; |
37 | evt2irq(0x720), | 35 | |
38 | evt2irq(0x760), | 36 | static struct resource scif0_resources[] = { |
39 | evt2irq(0x740) }, | 37 | DEFINE_RES_MEM(0xffc30000, 0x100), |
38 | DEFINE_RES_IRQ(evt2irq(0x700)), | ||
39 | DEFINE_RES_IRQ(evt2irq(0x720)), | ||
40 | DEFINE_RES_IRQ(evt2irq(0x760)), | ||
41 | DEFINE_RES_IRQ(evt2irq(0x740)), | ||
40 | }; | 42 | }; |
41 | 43 | ||
42 | static struct platform_device scif0_device = { | 44 | static struct platform_device scif0_device = { |
43 | .name = "sh-sci", | 45 | .name = "sh-sci", |
44 | .id = 0, | 46 | .id = 0, |
47 | .resource = scif0_resources, | ||
48 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
45 | .dev = { | 49 | .dev = { |
46 | .platform_data = &scif0_platform_data, | 50 | .platform_data = &scif0_platform_data, |
47 | }, | 51 | }, |
48 | }; | 52 | }; |
49 | 53 | ||
50 | static struct plat_sci_port scif1_platform_data = { | 54 | static struct plat_sci_port scif1_platform_data = { |
51 | .mapbase = 0xffc40000, | ||
52 | .flags = UPF_BOOT_AUTOCONF, | 55 | .flags = UPF_BOOT_AUTOCONF, |
53 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 56 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
54 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
55 | .type = PORT_SCIF, | 57 | .type = PORT_SCIF, |
56 | .irqs = { evt2irq(0x780), | 58 | }; |
57 | evt2irq(0x7a0), | 59 | |
58 | evt2irq(0x7e0), | 60 | static struct resource scif1_resources[] = { |
59 | evt2irq(0x7c0) }, | 61 | DEFINE_RES_MEM(0xffc40000, 0x100), |
62 | DEFINE_RES_IRQ(evt2irq(0x780)), | ||
63 | DEFINE_RES_IRQ(evt2irq(0x7a0)), | ||
64 | DEFINE_RES_IRQ(evt2irq(0x7e0)), | ||
65 | DEFINE_RES_IRQ(evt2irq(0x7c0)), | ||
60 | }; | 66 | }; |
61 | 67 | ||
62 | static struct platform_device scif1_device = { | 68 | static struct platform_device scif1_device = { |
63 | .name = "sh-sci", | 69 | .name = "sh-sci", |
64 | .id = 1, | 70 | .id = 1, |
71 | .resource = scif1_resources, | ||
72 | .num_resources = ARRAY_SIZE(scif1_resources), | ||
65 | .dev = { | 73 | .dev = { |
66 | .platform_data = &scif1_platform_data, | 74 | .platform_data = &scif1_platform_data, |
67 | }, | 75 | }, |
68 | }; | 76 | }; |
69 | 77 | ||
70 | static struct plat_sci_port scif2_platform_data = { | 78 | static struct plat_sci_port scif2_platform_data = { |
71 | .mapbase = 0xffc60000, | ||
72 | .flags = UPF_BOOT_AUTOCONF, | 79 | .flags = UPF_BOOT_AUTOCONF, |
73 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 80 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
74 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
75 | .type = PORT_SCIF, | 81 | .type = PORT_SCIF, |
76 | .irqs = { evt2irq(0x880), | 82 | }; |
77 | evt2irq(0x8a0), | 83 | |
78 | evt2irq(0x8e0), | 84 | static struct resource scif2_resources[] = { |
79 | evt2irq(0x8c0) }, | 85 | DEFINE_RES_MEM(0xffc60000, 0x100), |
86 | DEFINE_RES_IRQ(evt2irq(0x880)), | ||
87 | DEFINE_RES_IRQ(evt2irq(0x8a0)), | ||
88 | DEFINE_RES_IRQ(evt2irq(0x8e0)), | ||
89 | DEFINE_RES_IRQ(evt2irq(0x8c0)), | ||
80 | }; | 90 | }; |
81 | 91 | ||
82 | static struct platform_device scif2_device = { | 92 | static struct platform_device scif2_device = { |
83 | .name = "sh-sci", | 93 | .name = "sh-sci", |
84 | .id = 2, | 94 | .id = 2, |
95 | .resource = scif2_resources, | ||
96 | .num_resources = ARRAY_SIZE(scif2_resources), | ||
85 | .dev = { | 97 | .dev = { |
86 | .platform_data = &scif2_platform_data, | 98 | .platform_data = &scif2_platform_data, |
87 | }, | 99 | }, |
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c index 18419f1de963..14d68213d16b 100644 --- a/arch/sh/kernel/cpu/sh5/setup-sh5.c +++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c | |||
@@ -17,17 +17,23 @@ | |||
17 | #include <asm/addrspace.h> | 17 | #include <asm/addrspace.h> |
18 | 18 | ||
19 | static struct plat_sci_port scif0_platform_data = { | 19 | static struct plat_sci_port scif0_platform_data = { |
20 | .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000, | ||
21 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, | 20 | .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, |
22 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, | 21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, |
23 | .scbrr_algo_id = SCBRR_ALGO_2, | ||
24 | .type = PORT_SCIF, | 22 | .type = PORT_SCIF, |
25 | .irqs = { 39, 40, 42, 0 }, | 23 | }; |
24 | |||
25 | static struct resource scif0_resources[] = { | ||
26 | DEFINE_RES_MEM(PHYS_PERIPHERAL_BLOCK + 0x01030000, 0x100), | ||
27 | DEFINE_RES_IRQ(39), | ||
28 | DEFINE_RES_IRQ(40), | ||
29 | DEFINE_RES_IRQ(42), | ||
26 | }; | 30 | }; |
27 | 31 | ||
28 | static struct platform_device scif0_device = { | 32 | static struct platform_device scif0_device = { |
29 | .name = "sh-sci", | 33 | .name = "sh-sci", |
30 | .id = 0, | 34 | .id = 0, |
35 | .resource = scif0_resources, | ||
36 | .num_resources = ARRAY_SIZE(scif0_resources), | ||
31 | .dev = { | 37 | .dev = { |
32 | .platform_data = &scif0_platform_data, | 38 | .platform_data = &scif0_platform_data, |
33 | }, | 39 | }, |
diff --git a/arch/x86/crypto/Makefile b/arch/x86/crypto/Makefile index 7d6ba9db1be9..e0fc24db234a 100644 --- a/arch/x86/crypto/Makefile +++ b/arch/x86/crypto/Makefile | |||
@@ -3,8 +3,9 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no) | 5 | avx_supported := $(call as-instr,vpxor %xmm0$(comma)%xmm0$(comma)%xmm0,yes,no) |
6 | avx2_supported := $(call as-instr,vpgatherdd %ymm0$(comma)(%eax$(comma)%ymm1\ | ||
7 | $(comma)4)$(comma)%ymm2,yes,no) | ||
6 | 8 | ||
7 | obj-$(CONFIG_CRYPTO_ABLK_HELPER_X86) += ablk_helper.o | ||
8 | obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o | 9 | obj-$(CONFIG_CRYPTO_GLUE_HELPER_X86) += glue_helper.o |
9 | 10 | ||
10 | obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o | 11 | obj-$(CONFIG_CRYPTO_AES_586) += aes-i586.o |
diff --git a/arch/x86/crypto/ablk_helper.c b/arch/x86/crypto/ablk_helper.c deleted file mode 100644 index 43282fe04a8b..000000000000 --- a/arch/x86/crypto/ablk_helper.c +++ /dev/null | |||
@@ -1,149 +0,0 @@ | |||
1 | /* | ||
2 | * Shared async block cipher helpers | ||
3 | * | ||
4 | * Copyright (c) 2012 Jussi Kivilinna <jussi.kivilinna@mbnet.fi> | ||
5 | * | ||
6 | * Based on aesni-intel_glue.c by: | ||
7 | * Copyright (C) 2008, Intel Corp. | ||
8 | * Author: Huang Ying <ying.huang@intel.com> | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | ||
23 | * USA | ||
24 | * | ||
25 | */ | ||
26 | |||
27 | #include <linux/kernel.h> | ||
28 | #include <linux/crypto.h> | ||
29 | #include <linux/init.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <crypto/algapi.h> | ||
32 | #include <crypto/cryptd.h> | ||
33 | #include <asm/i387.h> | ||
34 | #include <asm/crypto/ablk_helper.h> | ||
35 | |||
36 | int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key, | ||
37 | unsigned int key_len) | ||
38 | { | ||
39 | struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); | ||
40 | struct crypto_ablkcipher *child = &ctx->cryptd_tfm->base; | ||
41 | int err; | ||
42 | |||
43 | crypto_ablkcipher_clear_flags(child, CRYPTO_TFM_REQ_MASK); | ||
44 | crypto_ablkcipher_set_flags(child, crypto_ablkcipher_get_flags(tfm) | ||
45 | & CRYPTO_TFM_REQ_MASK); | ||
46 | err = crypto_ablkcipher_setkey(child, key, key_len); | ||
47 | crypto_ablkcipher_set_flags(tfm, crypto_ablkcipher_get_flags(child) | ||
48 | & CRYPTO_TFM_RES_MASK); | ||
49 | return err; | ||
50 | } | ||
51 | EXPORT_SYMBOL_GPL(ablk_set_key); | ||
52 | |||
53 | int __ablk_encrypt(struct ablkcipher_request *req) | ||
54 | { | ||
55 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | ||
56 | struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); | ||
57 | struct blkcipher_desc desc; | ||
58 | |||
59 | desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm); | ||
60 | desc.info = req->info; | ||
61 | desc.flags = 0; | ||
62 | |||
63 | return crypto_blkcipher_crt(desc.tfm)->encrypt( | ||
64 | &desc, req->dst, req->src, req->nbytes); | ||
65 | } | ||
66 | EXPORT_SYMBOL_GPL(__ablk_encrypt); | ||
67 | |||
68 | int ablk_encrypt(struct ablkcipher_request *req) | ||
69 | { | ||
70 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | ||
71 | struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); | ||
72 | |||
73 | if (!irq_fpu_usable()) { | ||
74 | struct ablkcipher_request *cryptd_req = | ||
75 | ablkcipher_request_ctx(req); | ||
76 | |||
77 | memcpy(cryptd_req, req, sizeof(*req)); | ||
78 | ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); | ||
79 | |||
80 | return crypto_ablkcipher_encrypt(cryptd_req); | ||
81 | } else { | ||
82 | return __ablk_encrypt(req); | ||
83 | } | ||
84 | } | ||
85 | EXPORT_SYMBOL_GPL(ablk_encrypt); | ||
86 | |||
87 | int ablk_decrypt(struct ablkcipher_request *req) | ||
88 | { | ||
89 | struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req); | ||
90 | struct async_helper_ctx *ctx = crypto_ablkcipher_ctx(tfm); | ||
91 | |||
92 | if (!irq_fpu_usable()) { | ||
93 | struct ablkcipher_request *cryptd_req = | ||
94 | ablkcipher_request_ctx(req); | ||
95 | |||
96 | memcpy(cryptd_req, req, sizeof(*req)); | ||
97 | ablkcipher_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base); | ||
98 | |||
99 | return crypto_ablkcipher_decrypt(cryptd_req); | ||
100 | } else { | ||
101 | struct blkcipher_desc desc; | ||
102 | |||
103 | desc.tfm = cryptd_ablkcipher_child(ctx->cryptd_tfm); | ||
104 | desc.info = req->info; | ||
105 | desc.flags = 0; | ||
106 | |||
107 | return crypto_blkcipher_crt(desc.tfm)->decrypt( | ||
108 | &desc, req->dst, req->src, req->nbytes); | ||
109 | } | ||
110 | } | ||
111 | EXPORT_SYMBOL_GPL(ablk_decrypt); | ||
112 | |||
113 | void ablk_exit(struct crypto_tfm *tfm) | ||
114 | { | ||
115 | struct async_helper_ctx *ctx = crypto_tfm_ctx(tfm); | ||
116 | |||
117 | cryptd_free_ablkcipher(ctx->cryptd_tfm); | ||
118 | } | ||
119 | EXPORT_SYMBOL_GPL(ablk_exit); | ||
120 | |||
121 | int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name) | ||
122 | { | ||
123 | struct async_helper_ctx *ctx = crypto_tfm_ctx(tfm); | ||
124 | struct cryptd_ablkcipher *cryptd_tfm; | ||
125 | |||
126 | cryptd_tfm = cryptd_alloc_ablkcipher(drv_name, 0, 0); | ||
127 | if (IS_ERR(cryptd_tfm)) | ||
128 | return PTR_ERR(cryptd_tfm); | ||
129 | |||
130 | ctx->cryptd_tfm = cryptd_tfm; | ||
131 | tfm->crt_ablkcipher.reqsize = sizeof(struct ablkcipher_request) + | ||
132 | crypto_ablkcipher_reqsize(&cryptd_tfm->base); | ||
133 | |||
134 | return 0; | ||
135 | } | ||
136 | EXPORT_SYMBOL_GPL(ablk_init_common); | ||
137 | |||
138 | int ablk_init(struct crypto_tfm *tfm) | ||
139 | { | ||
140 | char drv_name[CRYPTO_MAX_ALG_NAME]; | ||
141 | |||
142 | snprintf(drv_name, sizeof(drv_name), "__driver-%s", | ||
143 | crypto_tfm_alg_driver_name(tfm)); | ||
144 | |||
145 | return ablk_init_common(tfm, drv_name); | ||
146 | } | ||
147 | EXPORT_SYMBOL_GPL(ablk_init); | ||
148 | |||
149 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c index f80e668785c0..835488b745ee 100644 --- a/arch/x86/crypto/aesni-intel_glue.c +++ b/arch/x86/crypto/aesni-intel_glue.c | |||
@@ -34,7 +34,7 @@ | |||
34 | #include <asm/cpu_device_id.h> | 34 | #include <asm/cpu_device_id.h> |
35 | #include <asm/i387.h> | 35 | #include <asm/i387.h> |
36 | #include <asm/crypto/aes.h> | 36 | #include <asm/crypto/aes.h> |
37 | #include <asm/crypto/ablk_helper.h> | 37 | #include <crypto/ablk_helper.h> |
38 | #include <crypto/scatterwalk.h> | 38 | #include <crypto/scatterwalk.h> |
39 | #include <crypto/internal/aead.h> | 39 | #include <crypto/internal/aead.h> |
40 | #include <linux/workqueue.h> | 40 | #include <linux/workqueue.h> |
diff --git a/arch/x86/crypto/camellia_aesni_avx2_glue.c b/arch/x86/crypto/camellia_aesni_avx2_glue.c index 414fe5d7946b..4209a76fcdaa 100644 --- a/arch/x86/crypto/camellia_aesni_avx2_glue.c +++ b/arch/x86/crypto/camellia_aesni_avx2_glue.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
15 | #include <linux/crypto.h> | 15 | #include <linux/crypto.h> |
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <crypto/ablk_helper.h> | ||
17 | #include <crypto/algapi.h> | 18 | #include <crypto/algapi.h> |
18 | #include <crypto/ctr.h> | 19 | #include <crypto/ctr.h> |
19 | #include <crypto/lrw.h> | 20 | #include <crypto/lrw.h> |
@@ -21,7 +22,6 @@ | |||
21 | #include <asm/xcr.h> | 22 | #include <asm/xcr.h> |
22 | #include <asm/xsave.h> | 23 | #include <asm/xsave.h> |
23 | #include <asm/crypto/camellia.h> | 24 | #include <asm/crypto/camellia.h> |
24 | #include <asm/crypto/ablk_helper.h> | ||
25 | #include <asm/crypto/glue_helper.h> | 25 | #include <asm/crypto/glue_helper.h> |
26 | 26 | ||
27 | #define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 | 27 | #define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 |
diff --git a/arch/x86/crypto/camellia_aesni_avx_glue.c b/arch/x86/crypto/camellia_aesni_avx_glue.c index 37fd0c0a81ea..87a041a10f4a 100644 --- a/arch/x86/crypto/camellia_aesni_avx_glue.c +++ b/arch/x86/crypto/camellia_aesni_avx_glue.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
15 | #include <linux/crypto.h> | 15 | #include <linux/crypto.h> |
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <crypto/ablk_helper.h> | ||
17 | #include <crypto/algapi.h> | 18 | #include <crypto/algapi.h> |
18 | #include <crypto/ctr.h> | 19 | #include <crypto/ctr.h> |
19 | #include <crypto/lrw.h> | 20 | #include <crypto/lrw.h> |
@@ -21,7 +22,6 @@ | |||
21 | #include <asm/xcr.h> | 22 | #include <asm/xcr.h> |
22 | #include <asm/xsave.h> | 23 | #include <asm/xsave.h> |
23 | #include <asm/crypto/camellia.h> | 24 | #include <asm/crypto/camellia.h> |
24 | #include <asm/crypto/ablk_helper.h> | ||
25 | #include <asm/crypto/glue_helper.h> | 25 | #include <asm/crypto/glue_helper.h> |
26 | 26 | ||
27 | #define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 | 27 | #define CAMELLIA_AESNI_PARALLEL_BLOCKS 16 |
diff --git a/arch/x86/crypto/cast5_avx_glue.c b/arch/x86/crypto/cast5_avx_glue.c index c6631813dc11..e6a3700489b9 100644 --- a/arch/x86/crypto/cast5_avx_glue.c +++ b/arch/x86/crypto/cast5_avx_glue.c | |||
@@ -26,13 +26,13 @@ | |||
26 | #include <linux/types.h> | 26 | #include <linux/types.h> |
27 | #include <linux/crypto.h> | 27 | #include <linux/crypto.h> |
28 | #include <linux/err.h> | 28 | #include <linux/err.h> |
29 | #include <crypto/ablk_helper.h> | ||
29 | #include <crypto/algapi.h> | 30 | #include <crypto/algapi.h> |
30 | #include <crypto/cast5.h> | 31 | #include <crypto/cast5.h> |
31 | #include <crypto/cryptd.h> | 32 | #include <crypto/cryptd.h> |
32 | #include <crypto/ctr.h> | 33 | #include <crypto/ctr.h> |
33 | #include <asm/xcr.h> | 34 | #include <asm/xcr.h> |
34 | #include <asm/xsave.h> | 35 | #include <asm/xsave.h> |
35 | #include <asm/crypto/ablk_helper.h> | ||
36 | #include <asm/crypto/glue_helper.h> | 36 | #include <asm/crypto/glue_helper.h> |
37 | 37 | ||
38 | #define CAST5_PARALLEL_BLOCKS 16 | 38 | #define CAST5_PARALLEL_BLOCKS 16 |
diff --git a/arch/x86/crypto/cast6_avx_glue.c b/arch/x86/crypto/cast6_avx_glue.c index 8d0dfb86a559..09f3677393e4 100644 --- a/arch/x86/crypto/cast6_avx_glue.c +++ b/arch/x86/crypto/cast6_avx_glue.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/types.h> | 28 | #include <linux/types.h> |
29 | #include <linux/crypto.h> | 29 | #include <linux/crypto.h> |
30 | #include <linux/err.h> | 30 | #include <linux/err.h> |
31 | #include <crypto/ablk_helper.h> | ||
31 | #include <crypto/algapi.h> | 32 | #include <crypto/algapi.h> |
32 | #include <crypto/cast6.h> | 33 | #include <crypto/cast6.h> |
33 | #include <crypto/cryptd.h> | 34 | #include <crypto/cryptd.h> |
@@ -37,7 +38,6 @@ | |||
37 | #include <crypto/xts.h> | 38 | #include <crypto/xts.h> |
38 | #include <asm/xcr.h> | 39 | #include <asm/xcr.h> |
39 | #include <asm/xsave.h> | 40 | #include <asm/xsave.h> |
40 | #include <asm/crypto/ablk_helper.h> | ||
41 | #include <asm/crypto/glue_helper.h> | 41 | #include <asm/crypto/glue_helper.h> |
42 | 42 | ||
43 | #define CAST6_PARALLEL_BLOCKS 8 | 43 | #define CAST6_PARALLEL_BLOCKS 8 |
diff --git a/arch/x86/crypto/serpent_avx2_glue.c b/arch/x86/crypto/serpent_avx2_glue.c index 23aabc6c20a5..2fae489b1524 100644 --- a/arch/x86/crypto/serpent_avx2_glue.c +++ b/arch/x86/crypto/serpent_avx2_glue.c | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
15 | #include <linux/crypto.h> | 15 | #include <linux/crypto.h> |
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <crypto/ablk_helper.h> | ||
17 | #include <crypto/algapi.h> | 18 | #include <crypto/algapi.h> |
18 | #include <crypto/ctr.h> | 19 | #include <crypto/ctr.h> |
19 | #include <crypto/lrw.h> | 20 | #include <crypto/lrw.h> |
@@ -22,7 +23,6 @@ | |||
22 | #include <asm/xcr.h> | 23 | #include <asm/xcr.h> |
23 | #include <asm/xsave.h> | 24 | #include <asm/xsave.h> |
24 | #include <asm/crypto/serpent-avx.h> | 25 | #include <asm/crypto/serpent-avx.h> |
25 | #include <asm/crypto/ablk_helper.h> | ||
26 | #include <asm/crypto/glue_helper.h> | 26 | #include <asm/crypto/glue_helper.h> |
27 | 27 | ||
28 | #define SERPENT_AVX2_PARALLEL_BLOCKS 16 | 28 | #define SERPENT_AVX2_PARALLEL_BLOCKS 16 |
diff --git a/arch/x86/crypto/serpent_avx_glue.c b/arch/x86/crypto/serpent_avx_glue.c index 9ae83cf8d21e..ff4870870972 100644 --- a/arch/x86/crypto/serpent_avx_glue.c +++ b/arch/x86/crypto/serpent_avx_glue.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/types.h> | 28 | #include <linux/types.h> |
29 | #include <linux/crypto.h> | 29 | #include <linux/crypto.h> |
30 | #include <linux/err.h> | 30 | #include <linux/err.h> |
31 | #include <crypto/ablk_helper.h> | ||
31 | #include <crypto/algapi.h> | 32 | #include <crypto/algapi.h> |
32 | #include <crypto/serpent.h> | 33 | #include <crypto/serpent.h> |
33 | #include <crypto/cryptd.h> | 34 | #include <crypto/cryptd.h> |
@@ -38,7 +39,6 @@ | |||
38 | #include <asm/xcr.h> | 39 | #include <asm/xcr.h> |
39 | #include <asm/xsave.h> | 40 | #include <asm/xsave.h> |
40 | #include <asm/crypto/serpent-avx.h> | 41 | #include <asm/crypto/serpent-avx.h> |
41 | #include <asm/crypto/ablk_helper.h> | ||
42 | #include <asm/crypto/glue_helper.h> | 42 | #include <asm/crypto/glue_helper.h> |
43 | 43 | ||
44 | /* 8-way parallel cipher functions */ | 44 | /* 8-way parallel cipher functions */ |
diff --git a/arch/x86/crypto/serpent_sse2_glue.c b/arch/x86/crypto/serpent_sse2_glue.c index 97a356ece24d..8c95f8637306 100644 --- a/arch/x86/crypto/serpent_sse2_glue.c +++ b/arch/x86/crypto/serpent_sse2_glue.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <linux/types.h> | 34 | #include <linux/types.h> |
35 | #include <linux/crypto.h> | 35 | #include <linux/crypto.h> |
36 | #include <linux/err.h> | 36 | #include <linux/err.h> |
37 | #include <crypto/ablk_helper.h> | ||
37 | #include <crypto/algapi.h> | 38 | #include <crypto/algapi.h> |
38 | #include <crypto/serpent.h> | 39 | #include <crypto/serpent.h> |
39 | #include <crypto/cryptd.h> | 40 | #include <crypto/cryptd.h> |
@@ -42,7 +43,6 @@ | |||
42 | #include <crypto/lrw.h> | 43 | #include <crypto/lrw.h> |
43 | #include <crypto/xts.h> | 44 | #include <crypto/xts.h> |
44 | #include <asm/crypto/serpent-sse2.h> | 45 | #include <asm/crypto/serpent-sse2.h> |
45 | #include <asm/crypto/ablk_helper.h> | ||
46 | #include <asm/crypto/glue_helper.h> | 46 | #include <asm/crypto/glue_helper.h> |
47 | 47 | ||
48 | static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src) | 48 | static void serpent_decrypt_cbc_xway(void *ctx, u128 *dst, const u128 *src) |
diff --git a/arch/x86/crypto/sha256_ssse3_glue.c b/arch/x86/crypto/sha256_ssse3_glue.c index 50226c4b86ed..f248546da1ca 100644 --- a/arch/x86/crypto/sha256_ssse3_glue.c +++ b/arch/x86/crypto/sha256_ssse3_glue.c | |||
@@ -281,7 +281,7 @@ static int __init sha256_ssse3_mod_init(void) | |||
281 | /* allow AVX to override SSSE3, it's a little faster */ | 281 | /* allow AVX to override SSSE3, it's a little faster */ |
282 | if (avx_usable()) { | 282 | if (avx_usable()) { |
283 | #ifdef CONFIG_AS_AVX2 | 283 | #ifdef CONFIG_AS_AVX2 |
284 | if (boot_cpu_has(X86_FEATURE_AVX2)) | 284 | if (boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_BMI2)) |
285 | sha256_transform_asm = sha256_transform_rorx; | 285 | sha256_transform_asm = sha256_transform_rorx; |
286 | else | 286 | else |
287 | #endif | 287 | #endif |
@@ -319,4 +319,4 @@ MODULE_LICENSE("GPL"); | |||
319 | MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated"); | 319 | MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated"); |
320 | 320 | ||
321 | MODULE_ALIAS("sha256"); | 321 | MODULE_ALIAS("sha256"); |
322 | MODULE_ALIAS("sha384"); | 322 | MODULE_ALIAS("sha224"); |
diff --git a/arch/x86/crypto/twofish_avx_glue.c b/arch/x86/crypto/twofish_avx_glue.c index a62ba541884e..4e3c665be129 100644 --- a/arch/x86/crypto/twofish_avx_glue.c +++ b/arch/x86/crypto/twofish_avx_glue.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/types.h> | 28 | #include <linux/types.h> |
29 | #include <linux/crypto.h> | 29 | #include <linux/crypto.h> |
30 | #include <linux/err.h> | 30 | #include <linux/err.h> |
31 | #include <crypto/ablk_helper.h> | ||
31 | #include <crypto/algapi.h> | 32 | #include <crypto/algapi.h> |
32 | #include <crypto/twofish.h> | 33 | #include <crypto/twofish.h> |
33 | #include <crypto/cryptd.h> | 34 | #include <crypto/cryptd.h> |
@@ -39,7 +40,6 @@ | |||
39 | #include <asm/xcr.h> | 40 | #include <asm/xcr.h> |
40 | #include <asm/xsave.h> | 41 | #include <asm/xsave.h> |
41 | #include <asm/crypto/twofish.h> | 42 | #include <asm/crypto/twofish.h> |
42 | #include <asm/crypto/ablk_helper.h> | ||
43 | #include <asm/crypto/glue_helper.h> | 43 | #include <asm/crypto/glue_helper.h> |
44 | #include <crypto/scatterwalk.h> | 44 | #include <crypto/scatterwalk.h> |
45 | #include <linux/workqueue.h> | 45 | #include <linux/workqueue.h> |
diff --git a/arch/x86/include/asm/crypto/ablk_helper.h b/arch/x86/include/asm/crypto/ablk_helper.h deleted file mode 100644 index 4f93df50c23e..000000000000 --- a/arch/x86/include/asm/crypto/ablk_helper.h +++ /dev/null | |||
@@ -1,31 +0,0 @@ | |||
1 | /* | ||
2 | * Shared async block cipher helpers | ||
3 | */ | ||
4 | |||
5 | #ifndef _CRYPTO_ABLK_HELPER_H | ||
6 | #define _CRYPTO_ABLK_HELPER_H | ||
7 | |||
8 | #include <linux/crypto.h> | ||
9 | #include <linux/kernel.h> | ||
10 | #include <crypto/cryptd.h> | ||
11 | |||
12 | struct async_helper_ctx { | ||
13 | struct cryptd_ablkcipher *cryptd_tfm; | ||
14 | }; | ||
15 | |||
16 | extern int ablk_set_key(struct crypto_ablkcipher *tfm, const u8 *key, | ||
17 | unsigned int key_len); | ||
18 | |||
19 | extern int __ablk_encrypt(struct ablkcipher_request *req); | ||
20 | |||
21 | extern int ablk_encrypt(struct ablkcipher_request *req); | ||
22 | |||
23 | extern int ablk_decrypt(struct ablkcipher_request *req); | ||
24 | |||
25 | extern void ablk_exit(struct crypto_tfm *tfm); | ||
26 | |||
27 | extern int ablk_init_common(struct crypto_tfm *tfm, const char *drv_name); | ||
28 | |||
29 | extern int ablk_init(struct crypto_tfm *tfm); | ||
30 | |||
31 | #endif /* _CRYPTO_ABLK_HELPER_H */ | ||
diff --git a/arch/x86/include/asm/simd.h b/arch/x86/include/asm/simd.h new file mode 100644 index 000000000000..ee80b92f0096 --- /dev/null +++ b/arch/x86/include/asm/simd.h | |||
@@ -0,0 +1,11 @@ | |||
1 | |||
2 | #include <asm/i387.h> | ||
3 | |||
4 | /* | ||
5 | * may_use_simd - whether it is allowable at this time to issue SIMD | ||
6 | * instructions or access the SIMD register file | ||
7 | */ | ||
8 | static __must_check inline bool may_use_simd(void) | ||
9 | { | ||
10 | return irq_fpu_usable(); | ||
11 | } | ||