118 files changed, 777 insertions, 1852 deletions

diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index f15f82bf3a50..e968a52e4881 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -356,15 +356,15 @@ choice
                   is nothing connected to read from the DCC.
 
         config DEBUG_SEMIHOSTING
-                bool "Kernel low-level debug output via semihosting I"
+                bool "Kernel low-level debug output via semihosting I/O"
                 help
                   Semihosting enables code running on an ARM target to use
                   the I/O facilities on a host debugger/emulator through a
-                  simple SVC calls. The host debugger or emulator must have
+                  simple SVC call. The host debugger or emulator must have
                   semihosting enabled for the special svc call to be trapped
                   otherwise the kernel will crash.
 
-                  This is known to work with OpenOCD, as wellas
+                  This is known to work with OpenOCD, as well as
                   ARM's Fast Models, or any other controlling environment
                   that implements semihosting.
 
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 210c923025b1..74381a31ee42 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -283,10 +283,10 @@ zImage Image xipImage bootpImage uImage: vmlinux
 zinstall uinstall install: vmlinux
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $@
 
-%.dtb:
+%.dtb: scripts
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
-dtbs:
+dtbs: scripts
         $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
 
 # We use MRPROPER_FILES and CLEAN_FILES now
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b8c64b80bafc..81769c1341fa 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -659,10 +659,14 @@ __armv7_mmu_cache_on:
 #ifdef CONFIG_CPU_ENDIAN_BE8
                 orr     r0, r0, #1 << 25        @ big-endian page tables
 #endif
+                mrcne   p15, 0, r6, c2, c0, 2   @ read ttb control reg
                 orrne   r0, r0, #1              @ MMU enabled
                 movne   r1, #0xfffffffd         @ domain 0 = client
+                bic     r6, r6, #1 << 31        @ 32-bit translation system
+                bic     r6, r6, #3 << 0         @ use only ttbr0
                 mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                 mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
+                mcrne   p15, 0, r6, c2, c0, 2   @ load ttb control
 #endif
                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
                 mcr     p15, 0, r0, c1, c0, 0   @ load control register
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index b98a1b36e694..c3ef1ad26b6a 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -397,7 +397,7 @@
                                 regulator@11 {
                                         reg = <11>;
                                         regulator-compatible = "ldo7";
-                                        regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+                                        regulator-name = "vdd_ldo7,avdd_hdmi";
                                         regulator-min-microvolt = <3300000>;
                                         regulator-max-microvolt = <3300000>;
                                 };
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index db2245353f0f..0d6bb738c6de 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -145,6 +145,8 @@ CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
 CONFIG_STAGING=y
 CONFIG_SENSORS_ISL29018=y
 CONFIG_SENSORS_ISL29028=y
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 03fb93621d0d..5c8b3bf4d825 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -320,4 +320,12 @@
         .size \name , . - \name
         .endm
 
+        .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
+#ifndef CONFIG_CPU_USE_DOMAINS
+        adds    \tmp, \addr, #\size - 1
+        sbcccs  \tmp, \tmp, \limit
+        bcs     \bad
+#endif
+        .endm
+
 #endif /* __ASM_ASSEMBLER_H__ */
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index e965f1b560f1..5f6ddcc56452 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -187,6 +187,7 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #define __phys_to_virt(x)       ((x) - PHYS_OFFSET + PAGE_OFFSET)
 #endif
 #endif
+#endif /* __ASSEMBLY__ */
 
 #ifndef PHYS_OFFSET
 #ifdef PLAT_PHYS_OFFSET
@@ -196,6 +197,8 @@ static inline unsigned long __phys_to_virt(unsigned long x)
 #endif
 #endif
 
+#ifndef __ASSEMBLY__
+
 /*
  * PFNs are used to describe any physical page; this means
  * PFN 0 == physical address 0.
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 314d4664eae7..99a19512ee26 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -199,6 +199,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 {
         pgtable_page_dtor(pte);
 
+#ifdef CONFIG_ARM_LPAE
+        tlb_add_flush(tlb, addr);
+#else
         /*
          * With the classic ARM MMU, a pte page has two corresponding pmd
          * entries, each covering 1MB.
@@ -206,6 +209,7 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
         addr &= PMD_MASK;
         tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
         tlb_add_flush(tlb, addr + SZ_1M);
+#endif
 
         tlb_remove_page(tlb, pte);
 }
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 479a6352e0b5..77bd79f2ffdb 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -101,28 +101,39 @@ extern int __get_user_1(void *);
 extern int __get_user_2(void *);
 extern int __get_user_4(void *);
 
-#define __get_user_x(__r2,__p,__e,__s,__i...)                           \
+#define __GUP_CLOBBER_1 "lr", "cc"
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define __GUP_CLOBBER_2 "ip", "lr", "cc"
+#else
+#define __GUP_CLOBBER_2 "lr", "cc"
+#endif
+#define __GUP_CLOBBER_4 "lr", "cc"
+
+#define __get_user_x(__r2,__p,__e,__l,__s)                              \
            __asm__ __volatile__ (                                       \
                 __asmeq("%0", "r0") __asmeq("%1", "r2")                 \
+                __asmeq("%3", "r1")                                     \
                 "bl     __get_user_" #__s                               \
                 : "=&r" (__e), "=r" (__r2)                              \
-                : "0" (__p)                                             \
-                : __i, "cc")
+                : "0" (__p), "r" (__l)                                  \
+                : __GUP_CLOBBER_##__s)
 
-#define get_user(x,p)                                                   \
+#define __get_user_check(x,p)                                                   \
         ({                                                              \
+                unsigned long __limit = current_thread_info()->addr_limit - 1; \
                 register const typeof(*(p)) __user *__p asm("r0") = (p);\
                 register unsigned long __r2 asm("r2");                  \
+                register unsigned long __l asm("r1") = __limit;         \
                 register int __e asm("r0");                             \
                 switch (sizeof(*(__p))) {                               \
                 case 1:                                                 \
-                        __get_user_x(__r2, __p, __e, 1, "lr");          \
-                        break;                                          \
+                        __get_user_x(__r2, __p, __e, __l, 1);           \
+                        break;                                          \
                 case 2:                                                 \
-                        __get_user_x(__r2, __p, __e, 2, "r3", "lr");    \
+                        __get_user_x(__r2, __p, __e, __l, 2);           \
                         break;                                          \
                 case 4:                                                 \
-                        __get_user_x(__r2, __p, __e, 4, "lr");          \
+                        __get_user_x(__r2, __p, __e, __l, 4);           \
                         break;                                          \
                 default: __e = __get_user_bad(); break;                 \
                 }                                                       \
@@ -130,42 +141,57 @@ extern int __get_user_4(void *);
                 __e;                                                    \
         })
 
+#define get_user(x,p)                                                   \
+        ({                                                              \
+                might_fault();                                          \
+                __get_user_check(x,p);                                  \
+         })
+
 extern int __put_user_1(void *, unsigned int);
 extern int __put_user_2(void *, unsigned int);
 extern int __put_user_4(void *, unsigned int);
 extern int __put_user_8(void *, unsigned long long);
 
-#define __put_user_x(__r2,__p,__e,__s)                                  \
+#define __put_user_x(__r2,__p,__e,__l,__s)                              \
            __asm__ __volatile__ (                                       \
                 __asmeq("%0", "r0") __asmeq("%2", "r2")                 \
+                __asmeq("%3", "r1")                                     \
                 "bl     __put_user_" #__s                               \
                 : "=&r" (__e)                                           \
-                : "0" (__p), "r" (__r2)                                 \
+                : "0" (__p), "r" (__r2), "r" (__l)                      \
                 : "ip", "lr", "cc")
 
-#define put_user(x,p)                                                   \
+#define __put_user_check(x,p)                                                   \
         ({                                                              \
+                unsigned long __limit = current_thread_info()->addr_limit - 1; \
                 register const typeof(*(p)) __r2 asm("r2") = (x);       \
                 register const typeof(*(p)) __user *__p asm("r0") = (p);\
+                register unsigned long __l asm("r1") = __limit;         \
                 register int __e asm("r0");                             \
                 switch (sizeof(*(__p))) {                               \
                 case 1:                                                 \
-                        __put_user_x(__r2, __p, __e, 1);                \
+                        __put_user_x(__r2, __p, __e, __l, 1);           \
                         break;                                          \
                 case 2:                                                 \
-                        __put_user_x(__r2, __p, __e, 2);                \
+                        __put_user_x(__r2, __p, __e, __l, 2);           \
                         break;                                          \
                 case 4:                                                 \
-                        __put_user_x(__r2, __p, __e, 4);                \
+                        __put_user_x(__r2, __p, __e, __l, 4);           \
                         break;                                          \
                 case 8:                                                 \
-                        __put_user_x(__r2, __p, __e, 8);                \
+                        __put_user_x(__r2, __p, __e, __l, 8);           \
                         break;                                          \
                 default: __e = __put_user_bad(); break;                 \
                 }                                                       \
                 __e;                                                    \
         })
 
+#define put_user(x,p)                                                   \
+        ({                                                              \
+                might_fault();                                          \
+                __put_user_check(x,p);                                  \
+         })
+
 #else /* CONFIG_MMU */
 
 /*
@@ -219,6 +245,7 @@ do {									\
         unsigned long __gu_addr = (unsigned long)(ptr);                 \
         unsigned long __gu_val;                                         \
         __chk_user_ptr(ptr);                                            \
+        might_fault();                                                  \
         switch (sizeof(*(ptr))) {                                       \
         case 1: __get_user_asm_byte(__gu_val,__gu_addr,err);    break;  \
         case 2: __get_user_asm_half(__gu_val,__gu_addr,err);    break;  \
@@ -300,6 +327,7 @@ do {									\
         unsigned long __pu_addr = (unsigned long)(ptr);                 \
         __typeof__(*(ptr)) __pu_val = (x);                              \
         __chk_user_ptr(ptr);                                            \
+        might_fault();                                                  \
         switch (sizeof(*(ptr))) {                                       \
         case 1: __put_user_asm_byte(__pu_val,__pu_addr,err);    break;  \
         case 2: __put_user_asm_half(__pu_val,__pu_addr,err);    break;  \
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index ba386bd94107..281bf3301241 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -159,6 +159,12 @@ static int debug_arch_supported(void)
                 arch >= ARM_DEBUG_ARCH_V7_1;
 }
 
+/* Can we determine the watchpoint access type from the fsr? */
+static int debug_exception_updates_fsr(void)
+{
+        return 0;
+}
+
 /* Determine number of WRP registers available. */
 static int get_num_wrp_resources(void)
 {
@@ -604,13 +610,14 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
                 /* Aligned */
                 break;
         case 1:
-                /* Allow single byte watchpoint. */
-                if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
-                        break;
         case 2:
                 /* Allow halfword watchpoints and breakpoints. */
                 if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
                         break;
+        case 3:
+                /* Allow single byte watchpoint. */
+                if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
+                        break;
         default:
                 ret = -EINVAL;
                 goto out;
@@ -619,18 +626,35 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         info->address &= ~alignment_mask;
         info->ctrl.len <<= offset;
 
-        /*
-         * Currently we rely on an overflow handler to take
-         * care of single-stepping the breakpoint when it fires.
-         * In the case of userspace breakpoints on a core with V7 debug,
-         * we can use the mismatch feature as a poor-man's hardware
-         * single-step, but this only works for per-task breakpoints.
-         */
-        if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
-            !core_has_mismatch_brps() || !bp->hw.bp_target)) {
-                pr_warning("overflow handler required but none found\n");
-                ret = -EINVAL;
+        if (!bp->overflow_handler) {
+                /*
+                 * Mismatch breakpoints are required for single-stepping
+                 * breakpoints.
+                 */
+                if (!core_has_mismatch_brps())
+                        return -EINVAL;
+
+                /* We don't allow mismatch breakpoints in kernel space. */
+                if (arch_check_bp_in_kernelspace(bp))
+                        return -EPERM;
+
+                /*
+                 * Per-cpu breakpoints are not supported by our stepping
+                 * mechanism.
+                 */
+                if (!bp->hw.bp_target)
+                        return -EINVAL;
+
+                /*
+                 * We only support specific access types if the fsr
+                 * reports them.
+                 */
+                if (!debug_exception_updates_fsr() &&
+                    (info->ctrl.type == ARM_BREAKPOINT_LOAD ||
+                     info->ctrl.type == ARM_BREAKPOINT_STORE))
+                        return -EINVAL;
         }
+
 out:
         return ret;
 }
@@ -706,10 +730,12 @@ static void watchpoint_handler(unsigned long addr, unsigned int fsr,
                                 goto unlock;
 
                         /* Check that the access type matches. */
-                        access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
-                                 HW_BREAKPOINT_R;
-                        if (!(access & hw_breakpoint_type(wp)))
-                                goto unlock;
+                        if (debug_exception_updates_fsr()) {
+                                access = (fsr & ARM_FSR_ACCESS_MASK) ?
+                                          HW_BREAKPOINT_W : HW_BREAKPOINT_R;
+                                if (!(access & hw_breakpoint_type(wp)))
+                                        goto unlock;
+                        }
 
                         /* We have a winner. */
                         info->trigger = addr;
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index f7945218b8c6..b0179b89a04c 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -420,20 +420,23 @@ asmlinkage void __exception do_undefinstr(struct pt_regs *regs)
 #endif
                         instr = *(u32 *) pc;
         } else if (thumb_mode(regs)) {
-                get_user(instr, (u16 __user *)pc);
+                if (get_user(instr, (u16 __user *)pc))
+                        goto die_sig;
                 if (is_wide_instruction(instr)) {
                         unsigned int instr2;
-                        get_user(instr2, (u16 __user *)pc+1);
+                        if (get_user(instr2, (u16 __user *)pc+1))
+                                goto die_sig;
                         instr <<= 16;
                         instr |= instr2;
                 }
-        } else {
-                get_user(instr, (u32 __user *)pc);
+        } else if (get_user(instr, (u32 __user *)pc)) {
+                goto die_sig;
         }
 
         if (call_undef_hook(regs, instr) == 0)
                 return;
 
+die_sig:
 #ifdef CONFIG_DEBUG_USER
         if (user_debug & UDBG_UNDEFINED) {
                 printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
index d6dacc69254e..395d5fbb8fa2 100644
--- a/arch/arm/lib/delay.c
+++ b/arch/arm/lib/delay.c
@@ -59,6 +59,7 @@ void __init init_current_timer_delay(unsigned long freq)
 {
         pr_info("Switching to timer-based delay loop\n");
         lpj_fine                        = freq / HZ;
+        loops_per_jiffy                 = lpj_fine;
         arm_delay_ops.delay             = __timer_delay;
         arm_delay_ops.const_udelay      = __timer_const_udelay;
         arm_delay_ops.udelay            = __timer_udelay;
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 11093a7c3e32..9b06bb41fca6 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -16,8 +16,9 @@
  * __get_user_X
  *
  * Inputs:      r0 contains the address
+ *              r1 contains the address limit, which must be preserved
  * Outputs:     r0 is the error code
- *              r2, r3 contains the zero-extended value
+ *              r2 contains the zero-extended value
  *              lr corrupted
  *
  * No other registers must be altered.  (see <asm/uaccess.h>
@@ -27,33 +28,39 @@
  * Note also that it is intended that __get_user_bad is not global.
  */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/errno.h>
 #include <asm/domain.h>
 
 ENTRY(__get_user_1)
+        check_uaccess r0, 1, r1, r2, __get_user_bad
 1: TUSER(ldrb)  r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
-#ifdef CONFIG_THUMB2_KERNEL
-2: TUSER(ldrb)  r2, [r0]
-3: TUSER(ldrb)  r3, [r0, #1]
+        check_uaccess r0, 2, r1, r2, __get_user_bad
+#ifdef CONFIG_CPU_USE_DOMAINS
+rb      .req    ip
+2:      ldrbt   r2, [r0], #1
+3:      ldrbt   rb, [r0], #0
 #else
-2: TUSER(ldrb)  r2, [r0], #1
-3: TUSER(ldrb)  r3, [r0]
+rb      .req    r0
+2:      ldrb    r2, [r0]
+3:      ldrb    rb, [r0, #1]
 #endif
 #ifndef __ARMEB__
-        orr     r2, r2, r3, lsl #8
+        orr     r2, r2, rb, lsl #8
 #else
-        orr     r2, r3, r2, lsl #8
+        orr     r2, rb, r2, lsl #8
 #endif
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
+        check_uaccess r0, 4, r1, r2, __get_user_bad
 4: TUSER(ldr)   r2, [r0]
         mov     r0, #0
         mov     pc, lr
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 7db25990c589..3d73dcb959b0 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -16,6 +16,7 @@
  * __put_user_X
  *
  * Inputs:      r0 contains the address
+ *              r1 contains the address limit, which must be preserved
  *              r2, r3 contains the value
  * Outputs:     r0 is the error code
  *              lr corrupted
@@ -27,16 +28,19 @@
  * Note also that it is intended that __put_user_bad is not global.
  */
 #include <linux/linkage.h>
+#include <asm/assembler.h>
 #include <asm/errno.h>
 #include <asm/domain.h>
 
 ENTRY(__put_user_1)
+        check_uaccess r0, 1, r1, ip, __put_user_bad
 1: TUSER(strb)  r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_1)
 
 ENTRY(__put_user_2)
+        check_uaccess r0, 2, r1, ip, __put_user_bad
         mov     ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
@@ -60,12 +64,14 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
+        check_uaccess r0, 4, r1, ip, __put_user_bad
 4: TUSER(str)   r2, [r0]
         mov     r0, #0
         mov     pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
+        check_uaccess r0, 8, r1, ip, __put_user_bad
 #ifdef CONFIG_THUMB2_KERNEL
 5: TUSER(str)   r2, [r0]
 6: TUSER(str)   r3, [r0, #4]
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index 46090e642d8e..6bd7300a2bc5 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -47,7 +47,7 @@ static void at91x40_idle(void)
          * Disable the processor clock.  The processor will be automatically
          * re-enabled by an interrupt or by a reset.
          */
-        __raw_writel(AT91_PS_CR_CPU, AT91_PS_CR);
+        __raw_writel(AT91_PS_CR_CPU, AT91_IO_P2V(AT91_PS_CR));
         cpu_do_idle();
 }
 
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 6ca680a1d5d1..ee06d7bcdf76 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -29,10 +29,10 @@
 #include <mach/at91_tc.h>
 
 #define at91_tc_read(field) \
-        __raw_readl(AT91_TC + field)
+        __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 
 #define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_TC + field);
+        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
 
 /*
  *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index 09242b67d277..711a7892d331 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -67,13 +67,13 @@
  * to 0xFEF78000 .. 0xFF000000.  (544Kb)
  */
 #define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+#define AT91_IO_VIRT_BASE       IOMEM(0xFF000000 - AT91_IO_SIZE)
 #else
 /*
  * Identity mapping for the non MMU case.
  */
 #define AT91_IO_PHYS_BASE       AT91_BASE_SYS
-#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
+#define AT91_IO_VIRT_BASE       IOMEM(AT91_IO_PHYS_BASE)
 #endif
 
 #define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 6f6118d1576a..97ad68a826f8 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,7 +94,7 @@ static const u32 uarts_sam9x5[] = {
         0,
 };
 
-static inline const u32* decomp_soc_detect(u32 dbgu_base)
+static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
 {
         u32 cidr, socid;
 
@@ -142,10 +142,10 @@ static inline void arch_decomp_setup(void)
         int i = 0;
         const u32* usarts;
 
-        usarts = decomp_soc_detect(AT91_BASE_DBGU0);
+        usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU0);
 
         if (!usarts)
-                usarts = decomp_soc_detect(AT91_BASE_DBGU1);
+                usarts = decomp_soc_detect((void __iomem *)AT91_BASE_DBGU1);
         if (!usarts) {
                 at91_uart = NULL;
                 return;
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 944bffb08991..e6f52de1062f 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -73,7 +73,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 {
         struct map_desc *desc = &sram_desc[bank];
 
-        desc->virtual = AT91_IO_VIRT_BASE - length;
+        desc->virtual = (unsigned long)AT91_IO_VIRT_BASE - length;
         if (bank > 0)
                 desc->virtual -= sram_desc[bank - 1].length;
 
@@ -88,7 +88,7 @@ void __init at91_init_sram(int bank, unsigned long base, unsigned int length)
 }
 
 static struct map_desc at91_io_desc __initdata = {
-        .virtual        = AT91_VA_BASE_SYS,
+        .virtual        = (unsigned long)AT91_VA_BASE_SYS,
         .pfn            = __phys_to_pfn(AT91_BASE_SYS),
         .length         = SZ_16K,
         .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 6f8068692edf..f0fe6b5350e2 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -74,22 +74,22 @@ static struct map_desc ebsa110_io_desc[] __initdata = {
          * sparse external-decode ISAIO space
          */
         {       /* IRQ_STAT/IRQ_MCLR */
-                .virtual        = IRQ_STAT,
+                .virtual        = (unsigned long)IRQ_STAT,
                 .pfn            = __phys_to_pfn(TRICK4_PHYS),
                 .length         = TRICK4_SIZE,
                 .type           = MT_DEVICE
         }, {    /* IRQ_MASK/IRQ_MSET */
-                .virtual        = IRQ_MASK,
+                .virtual        = (unsigned long)IRQ_MASK,
                 .pfn            = __phys_to_pfn(TRICK3_PHYS),
                 .length         = TRICK3_SIZE,
                 .type           = MT_DEVICE
         }, {    /* SOFT_BASE */
-                .virtual        = SOFT_BASE,
+                .virtual        = (unsigned long)SOFT_BASE,
                 .pfn            = __phys_to_pfn(TRICK1_PHYS),
                 .length         = TRICK1_SIZE,
                 .type           = MT_DEVICE
         }, {    /* PIT_BASE */
-                .virtual        = PIT_BASE,
+                .virtual        = (unsigned long)PIT_BASE,
                 .pfn            = __phys_to_pfn(TRICK0_PHYS),
                 .length         = TRICK0_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-ebsa110/core.h b/arch/arm/mach-ebsa110/core.h
index c93c9e43012d..afe137ee172e 100644
--- a/arch/arm/mach-ebsa110/core.h
+++ b/arch/arm/mach-ebsa110/core.h
@@ -31,11 +31,11 @@
 #define TRICK7_PHYS             0xf3c00000
 
 /* Virtual addresses */
-#define PIT_BASE                0xfc000000      /* trick 0 */
-#define SOFT_BASE               0xfd000000      /* trick 1 */
-#define IRQ_MASK                0xfe000000      /* trick 3 - read */
-#define IRQ_MSET                0xfe000000      /* trick 3 - write */
-#define IRQ_STAT                0xff000000      /* trick 4 - read */
-#define IRQ_MCLR                0xff000000      /* trick 4 - write */
+#define PIT_BASE                IOMEM(0xfc000000)       /* trick 0 */
+#define SOFT_BASE               IOMEM(0xfd000000)       /* trick 1 */
+#define IRQ_MASK                IOMEM(0xfe000000)       /* trick 3 - read */
+#define IRQ_MSET                IOMEM(0xfe000000)       /* trick 3 - write */
+#define IRQ_STAT                IOMEM(0xff000000)       /* trick 4 - read */
+#define IRQ_MCLR                IOMEM(0xff000000)       /* trick 4 - write */
 
 #endif
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index 774533c67066..3b00e299b624 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -166,11 +166,6 @@ static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
 }
 
-static int exynos5_clk_ip_gps_ctrl(struct clk *clk, int enable)
-{
-        return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GPS, clk, enable);
-}
-
 static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
@@ -672,10 +667,6 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
-                .name           = "gps",
-                .enable         = exynos5_clk_ip_gps_ctrl,
-                .ctrlbit        = ((1 << 3) | (1 << 2) | (1 << 0)),
-        }, {
                 .name           = "nfcon",
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 22),
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index c72b675b3e4b..9d1f3ac86db2 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -131,7 +131,6 @@
 #define EXYNOS5_PA_SYSMMU_JPEG          0x11F20000
 #define EXYNOS5_PA_SYSMMU_IOP           0x12360000
 #define EXYNOS5_PA_SYSMMU_RTIC          0x12370000
-#define EXYNOS5_PA_SYSMMU_GPS           0x12630000
 #define EXYNOS5_PA_SYSMMU_ISP           0x13260000
 #define EXYNOS5_PA_SYSMMU_DRC           0x12370000
 #define EXYNOS5_PA_SYSMMU_SCALERC       0x13280000
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index fdd8cc87c9fe..4431a62fff5b 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,10 +222,8 @@ int __init mx25_clocks_init(void)
         clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
         clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
         clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-        clk_register_clkdev(clk[ssi1_ipg_per], "per", "imx-ssi.0");
-        clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_ipg_per], "per", "imx-ssi.1");
-        clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+        clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
         clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
         clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
         clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb10bae..65fb8bcd86cb 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -230,10 +230,8 @@ int __init mx35_clocks_init()
         clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
         clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
         clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
-        clk_register_clkdev(clk[ssi1_div_post], "per", "imx-ssi.0");
-        clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.1");
-        clk_register_clkdev(clk[ssi2_div_post], "per", "imx-ssi.1");
+        clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
+        clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
         /* i.mx35 has the i.mx21 type uart */
         clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
         clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 8dc9d3edf17a..0330078ff788 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -258,13 +258,13 @@ static void __init kzm_board_init(void)
  */
 static struct map_desc kzm_io_desc[] __initdata = {
         {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length         = MX31_CS4_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = MX31_CS5_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS5_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS5_BASE_ADDR),
                 .length         = MX31_CS5_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index d37f4809c556..e774b07f48d3 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -540,7 +540,7 @@ static void __init mxc_init_audio(void)
  */
 static struct map_desc mx31ads_io_desc[] __initdata = {
         {
-                .virtual        = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual        = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn            = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length         = CS4_CS8900_MMIO_START,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index c8785b39eaed..ef57cff5abfb 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -207,7 +207,7 @@ static struct platform_device physmap_flash_device = {
  */
 static struct map_desc mx31lite_io_desc[] __initdata = {
         {
-                .virtual = MX31_CS4_BASE_ADDR_VIRT,
+                .virtual = (unsigned long)MX31_CS4_BASE_ADDR_VIRT,
                 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
                 .length = MX31_CS4_SIZE,
                 .type = MT_DEVICE
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 3fa6c51390da..a432d4325f89 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -95,8 +95,8 @@ arch_initcall(integrator_init);
  *  UART0  7    6
  *  UART1  5    4
  */
-#define SC_CTRLC        IO_ADDRESS(INTEGRATOR_SC_CTRLC)
-#define SC_CTRLS        IO_ADDRESS(INTEGRATOR_SC_CTRLS)
+#define SC_CTRLC        __io_address(INTEGRATOR_SC_CTRLC)
+#define SC_CTRLS        __io_address(INTEGRATOR_SC_CTRLS)
 
 static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
 {
diff --git a/arch/arm/mach-integrator/cpu.c b/arch/arm/mach-integrator/cpu.c
index fbb457779895..590c192cdf4d 100644
--- a/arch/arm/mach-integrator/cpu.c
+++ b/arch/arm/mach-integrator/cpu.c
@@ -25,10 +25,10 @@
 
 static struct cpufreq_driver integrator_driver;
 
-#define CM_ID   IO_ADDRESS(INTEGRATOR_HDR_ID)
-#define CM_OSC  IO_ADDRESS(INTEGRATOR_HDR_OSC)
-#define CM_STAT IO_ADDRESS(INTEGRATOR_HDR_STAT)
-#define CM_LOCK IO_ADDRESS(INTEGRATOR_HDR_LOCK)
+#define CM_ID   __io_address(INTEGRATOR_HDR_ID)
+#define CM_OSC  __io_address(INTEGRATOR_HDR_OSC)
+#define CM_STAT __io_address(INTEGRATOR_HDR_STAT)
+#define CM_LOCK __io_address(INTEGRATOR_HDR_LOCK)
 
 static const struct icst_params lclk_params = {
         .ref            = 24000000,
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index fd3ef28d2c1a..2215d96cd735 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -134,17 +134,17 @@ static struct map_desc ap_io_desc[] __initdata = {
                 .length         = SZ_4K,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_MEMORY_VADDR,
+                .virtual        = (unsigned long)PCI_MEMORY_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_MEM_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_CONFIG_VADDR,
+                .virtual        = (unsigned long)PCI_CONFIG_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = PCI_V3_VADDR,
+                .virtual        = (unsigned long)PCI_V3_VADDR,
                 .pfn            = __phys_to_pfn(PHYS_PCI_V3_BASE),
                 .length         = SZ_64K,
                 .type           = MT_DEVICE
@@ -314,9 +314,9 @@ static void __init ap_init(void)
 /*
  * Where is the timer (VA)?
  */
-#define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
-#define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
-#define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
+#define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
+#define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
+#define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
 
 static unsigned long timer_reload;
 
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 82d5c837cc74..3df5fc369361 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -59,7 +59,7 @@
 
 #define INTCP_ETH_SIZE                  0x10
 
-#define INTCP_VA_CTRL_BASE              IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
+#define INTCP_VA_CTRL_BASE              __io_address(INTEGRATOR_CP_CTL_BASE)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -265,8 +265,8 @@ static struct platform_device *intcp_devs[] __initdata = {
  */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(IO_ADDRESS(0xca000000 + 4));
-        writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE + 8));
+        unsigned int status = readl(__io_address(0xca000000 + 4));
+        writel(8, __io_address(INTEGRATOR_CP_CTL_BASE + 8));
 
         return status & 8;
 }
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 495f181fc937..bbeca59df66b 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -181,7 +181,7 @@ static DEFINE_RAW_SPINLOCK(v3_lock);
 #undef V3_LB_BASE_PREFETCH
 #define V3_LB_BASE_PREFETCH 0
 
-static unsigned long v3_open_config_window(struct pci_bus *bus,
+static void __iomem *v3_open_config_window(struct pci_bus *bus,
                                            unsigned int devfn, int offset)
 {
         unsigned int address, mapaddress, busnr;
@@ -280,7 +280,7 @@ static void v3_close_config_window(void)
 static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
                           int size, u32 *val)
 {
-        unsigned long addr;
+        void __iomem *addr;
         unsigned long flags;
         u32 v;
 
@@ -311,7 +311,7 @@ static int v3_read_config(struct pci_bus *bus, unsigned int devfn, int where,
 static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
                            int size, u32 val)
 {
-        unsigned long addr;
+        void __iomem *addr;
         unsigned long flags;
 
         raw_spin_lock_irqsave(&v3_lock, flags);
@@ -388,9 +388,9 @@ static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
  * means I can't get additional information on the reason for the pm2fb
  * problems.  I suppose I'll just have to mind-meld with the machine. ;)
  */
-#define SC_PCI     IO_ADDRESS(INTEGRATOR_SC_PCIENABLE)
-#define SC_LBFADDR IO_ADDRESS(INTEGRATOR_SC_BASE + 0x20)
-#define SC_LBFCODE IO_ADDRESS(INTEGRATOR_SC_BASE + 0x24)
+#define SC_PCI     __io_address(INTEGRATOR_SC_PCIENABLE)
+#define SC_LBFADDR __io_address(INTEGRATOR_SC_BASE + 0x20)
+#define SC_LBFCODE __io_address(INTEGRATOR_SC_BASE + 0x24)
 
 static int
 v3_pci_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e10e101645dd..7480f58267aa 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -126,18 +126,16 @@ extern unsigned long get_iop_tick_rate(void);
  * IOP13XX chipset registers
  */
 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
-#define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
+#define IOP13XX_PMMR_VIRT_MEM_BASE         (void __iomem *)(0xfee80000UL)  /* PMMR phys. address */
 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
-#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
-#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
-                                           (IOP13XX_PMMR_PHYS_MEM_BASE\
-                                           - IOP13XX_PMMR_VIRT_MEM_BASE))
+#define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (((addr) - IOP13XX_PMMR_VIRT_MEM_BASE)\
+                                           + IOP13XX_PMMR_PHYS_MEM_BASE)
+#define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (((addr) - IOP13XX_PMMR_PHYS_MEM_BASE)\
+                                           + IOP13XX_PMMR_VIRT_MEM_BASE)
 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
@@ -147,10 +145,10 @@ extern unsigned long get_iop_tick_rate(void);
 #define IOP13XX_PMMR_SIZE                  0x00080000
 
 /*=================== Defines for Platform Devices =====================*/
-#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
-#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
-#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
+#define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE + 0x00002340)
+#define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002300)
+#define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x00002340)
 
 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h
index 1afa99ef97fa..7c032d0ab24a 100644
--- a/arch/arm/mach-iop13xx/include/mach/memory.h
+++ b/arch/arm/mach-iop13xx/include/mach/memory.h
@@ -16,12 +16,12 @@
 #define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
 #define IOP13XX_PMMR_P_END   (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
 
-static inline dma_addr_t __virt_to_lbus(unsigned long x)
+static inline dma_addr_t __virt_to_lbus(void __iomem *x)
 {
         return x + IOP13XX_PMMR_PHYS_MEM_BASE - IOP13XX_PMMR_VIRT_MEM_BASE;
 }
 
-static inline unsigned long __lbus_to_virt(dma_addr_t x)
+static inline void __iomem *__lbus_to_virt(dma_addr_t x)
 {
         return x + IOP13XX_PMMR_VIRT_MEM_BASE - IOP13XX_PMMR_PHYS_MEM_BASE;
 }
@@ -38,23 +38,23 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x)
 
 #define __arch_dma_to_virt(dev, addr)                                   \
         ({                                                              \
-                unsigned long __virt;                                   \
+                void * __virt;                                          \
                 dma_addr_t __dma = addr;                                \
                 if (is_lbus_device(dev) && __is_lbus_dma(__dma))        \
                         __virt = __lbus_to_virt(__dma);                 \
                 else                                                    \
-                        __virt = __phys_to_virt(__dma);                 \
-                (void *)__virt;                                         \
+                        __virt = (void *)__phys_to_virt(__dma);         \
+                __virt;                                                 \
         })
 
 #define __arch_virt_to_dma(dev, addr)                                   \
         ({                                                              \
-                unsigned long __virt = (unsigned long)addr;             \
+                void * __virt = addr;                                   \
                 dma_addr_t __dma;                                       \
                 if (is_lbus_device(dev) && __is_lbus_virt(__virt))      \
                         __dma = __virt_to_lbus(__virt);                 \
                 else                                                    \
-                        __dma = __virt_to_phys(__virt);                 \
+                        __dma = __virt_to_phys((unsigned long)__virt);  \
                 __dma;                                                  \
         })
 
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 851dc8f2b6b5..183dc8b5511b 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -33,14 +33,14 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                 if (unlikely(!iop13xx_atux_mem_base))
                         retval = NULL;
                 else
-                        retval = (void *)(iop13xx_atux_mem_base +
+                        retval = (iop13xx_atux_mem_base +
                                  (cookie - IOP13XX_PCIX_LOWER_MEM_RA));
                 break;
         case IOP13XX_PCIE_LOWER_MEM_RA ... IOP13XX_PCIE_UPPER_MEM_RA:
                 if (unlikely(!iop13xx_atue_mem_base))
                         retval = NULL;
                 else
-                        retval = (void *)(iop13xx_atue_mem_base +
+                        retval = (iop13xx_atue_mem_base +
                                  (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                 break;
         case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
@@ -49,7 +49,7 @@ static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
                                        size, mtype, __builtin_return_address(0));
                 break;
         case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
-                retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
+                retval = IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
                 retval = __arm_ioremap_caller(cookie, size, mtype,
@@ -74,7 +74,7 @@ static void __iop13xx_iounmap(volatile void __iomem *addr)
                     goto skip;
 
         switch ((u32) addr) {
-        case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
+        case (u32)IOP13XX_PMMR_VIRT_MEM_BASE ... (u32)IOP13XX_PMMR_UPPER_MEM_VA:
                 goto skip;
         }
         __iounmap(addr);
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 91f731a2957b..9082b84aeebb 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -36,8 +36,8 @@ u32 iop13xx_atux_pmmr_offset; /* This offset can change based on strapping */
 u32 iop13xx_atue_pmmr_offset; /* This offset can change based on strapping */
 static struct pci_bus *pci_bus_atux = 0;
 static struct pci_bus *pci_bus_atue = 0;
-u32 iop13xx_atue_mem_base;
-u32 iop13xx_atux_mem_base;
+void __iomem *iop13xx_atue_mem_base;
+void __iomem *iop13xx_atux_mem_base;
 size_t iop13xx_atue_mem_size;
 size_t iop13xx_atux_mem_size;
 
@@ -88,8 +88,7 @@ void iop13xx_map_pci_memory(void)
                                 }
 
                                 if (end) {
-                                        iop13xx_atux_mem_base =
-                                        (u32) __arm_ioremap_pfn(
+                                        iop13xx_atux_mem_base = __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
                                         , 0, iop13xx_atux_mem_size, MT_DEVICE);
                                         if (!iop13xx_atux_mem_base) {
@@ -99,7 +98,7 @@ void iop13xx_map_pci_memory(void)
                                         }
                                 } else
                                         iop13xx_atux_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                 __func__, atu, iop13xx_atux_mem_size,
                                 iop13xx_atux_mem_base);
                                 break;
@@ -114,8 +113,7 @@ void iop13xx_map_pci_memory(void)
                                 }
 
                                 if (end) {
-                                        iop13xx_atue_mem_base =
-                                        (u32) __arm_ioremap_pfn(
+                                        iop13xx_atue_mem_base = __arm_ioremap_pfn(
                                         __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
                                         , 0, iop13xx_atue_mem_size, MT_DEVICE);
                                         if (!iop13xx_atue_mem_base) {
@@ -125,13 +123,13 @@ void iop13xx_map_pci_memory(void)
                                         }
                                 } else
                                         iop13xx_atue_mem_size = 0;
-                                PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
+                                PRINTK("%s: atu: %d bus_size: %d mem_base: %p\n",
                                 __func__, atu, iop13xx_atue_mem_size,
                                 iop13xx_atue_mem_base);
                                 break;
                         }
 
-                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
+                        printk("%s: Initialized (%uM @ resource/virtual: %08lx/%p)\n",
                         atu ? "ATUE" : "ATUX",
                         (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
                         SZ_1M,
diff --git a/arch/arm/mach-iop13xx/pci.h b/arch/arm/mach-iop13xx/pci.h
index c70cf5b41e31..d45a80b3080e 100644
--- a/arch/arm/mach-iop13xx/pci.h
+++ b/arch/arm/mach-iop13xx/pci.h
@@ -1,6 +1,6 @@
 #include <linux/types.h>
 
-extern u32 iop13xx_atue_mem_base;
-extern u32 iop13xx_atux_mem_base;
+extern void __iomem *iop13xx_atue_mem_base;
+extern void __iomem *iop13xx_atux_mem_base;
 extern size_t iop13xx_atue_mem_size;
 extern size_t iop13xx_atux_mem_size;
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 4a7f20d7fb6e..3181f61ea63e 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -36,7 +36,7 @@
  */
 static struct map_desc iop13xx_std_desc[] __initdata = {
         {    /* mem mapped registers */
-                .virtual = IOP13XX_PMMR_VIRT_MEM_BASE,
+                .virtual = (unsigned long)IOP13XX_PMMR_VIRT_MEM_BASE,
                 .pfn     = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
                 .length  = IOP13XX_PMMR_SIZE,
                 .type    = MT_DEVICE,
@@ -71,8 +71,8 @@ static struct resource iop13xx_uart1_resources[] = {
 
 static struct plat_serial8250_port iop13xx_uart0_data[] = {
         {
-       .membase     = (char*)(IOP13XX_UART0_VIRT),
-       .mapbase     = (IOP13XX_UART0_PHYS),
+       .membase     = IOP13XX_UART0_VIRT,
+       .mapbase     = IOP13XX_UART0_PHYS,
        .irq         = IRQ_IOP13XX_UART0,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
@@ -84,8 +84,8 @@ static struct plat_serial8250_port iop13xx_uart0_data[] = {
 
 static struct plat_serial8250_port iop13xx_uart1_data[] = {
         {
-       .membase     = (char*)(IOP13XX_UART1_VIRT),
-       .mapbase     = (IOP13XX_UART1_PHYS),
+       .membase     = IOP13XX_UART1_VIRT,
+       .mapbase     = IOP13XX_UART1_PHYS,
        .irq         = IRQ_IOP13XX_UART1,
        .uartclk     = IOP13XX_UART_XTAL,
        .regshift    = 2,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index c15a100ba779..02e20c3912ba 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -183,7 +183,7 @@ static struct i2c_board_info __initdata glantank_i2c_devices[] = {
 
 static void glantank_power_off(void)
 {
-        __raw_writeb(0x01, 0xfe8d0004);
+        __raw_writeb(0x01, IOMEM(0xfe8d0004));
 
         while (1)
                 ;
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index a9f80943d01f..fdf91a160884 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -53,24 +53,24 @@ static struct clock_event_device clockevent_ixp4xx;
  *************************************************************************/
 static struct map_desc ixp4xx_io_desc[] __initdata = {
         {       /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
-                .virtual        = IXP4XX_PERIPHERAL_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
                 .length         = IXP4XX_PERIPHERAL_REGION_SIZE,
                 .type           = MT_DEVICE
         }, {    /* Expansion Bus Config Registers */
-                .virtual        = IXP4XX_EXP_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
                 .length         = IXP4XX_EXP_CFG_REGION_SIZE,
                 .type           = MT_DEVICE
         }, {    /* PCI Registers */
-                .virtual        = IXP4XX_PCI_CFG_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
                 .length         = IXP4XX_PCI_CFG_REGION_SIZE,
                 .type           = MT_DEVICE
         },
 #ifdef CONFIG_DEBUG_LL
         {       /* Debug UART mapping */
-                .virtual        = IXP4XX_DEBUG_UART_BASE_VIRT,
+                .virtual        = (unsigned long)IXP4XX_DEBUG_UART_BASE_VIRT,
                 .pfn            = __phys_to_pfn(IXP4XX_DEBUG_UART_BASE_PHYS),
                 .length         = IXP4XX_DEBUG_UART_REGION_SIZE,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h
index b2ef65db0e91..ebc0ba31ce85 100644
--- a/arch/arm/mach-ixp4xx/include/mach/cpu.h
+++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h
@@ -14,6 +14,7 @@
 #ifndef __ASM_ARCH_CPU_H__
 #define __ASM_ARCH_CPU_H__
 
+#include <linux/io.h>
 #include <asm/cputype.h>
 
 /* Processor id value in CP15 Register 0 */
@@ -37,7 +38,7 @@
 
 static inline u32 ixp4xx_read_feature_bits(void)
 {
-        u32 val = ~*IXP4XX_EXP_CFG2;
+        u32 val = ~__raw_readl(IXP4XX_EXP_CFG2);
 
         if (cpu_is_ixp42x_rev_a0())
                 return IXP42X_FEATURE_MASK & ~(IXP4XX_FEATURE_RCOMP |
@@ -51,7 +52,7 @@ static inline u32 ixp4xx_read_feature_bits(void)
 
 static inline void ixp4xx_write_feature_bits(u32 value)
 {
-        *IXP4XX_EXP_CFG2 = ~value;
+        __raw_writel(~value, IXP4XX_EXP_CFG2);
 }
 
 #endif  /* _ASM_ARCH_CPU_H */
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
index 97c530f66e78..eb68b61ce975 100644
--- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h
@@ -49,21 +49,21 @@
  * Expansion BUS Configuration registers
  */
 #define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
-#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        IOMEM(0xFFBFE000)
 #define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * PCI Config registers
  */
 #define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
-#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFF000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        IOMEM(0xFFBFF000)
 #define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
 
 /*
  * Peripheral space
  */
 #define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
-#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBEB000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     IOMEM(0xFFBEB000)
 #define IXP4XX_PERIPHERAL_REGION_SIZE   (0x00013000)
 
 /*
@@ -73,7 +73,7 @@
  * aligned so that it * can be used with the low-level debug code.
  */
 #define IXP4XX_DEBUG_UART_BASE_PHYS     (0xC8000000)
-#define IXP4XX_DEBUG_UART_BASE_VIRT     (0xffb00000)
+#define IXP4XX_DEBUG_UART_BASE_VIRT     IOMEM(0xffb00000)
 #define IXP4XX_DEBUG_UART_REGION_SIZE   (0x00001000)
 
 #define IXP4XX_EXP_CS0_OFFSET   0x00
@@ -92,7 +92,7 @@
 /*
  * Expansion Bus Controller registers.
  */
-#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+#define IXP4XX_EXP_REG(x) ((volatile u32 __iomem *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
 
 #define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
 #define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
diff --git a/arch/arm/mach-ks8695/cpu.c b/arch/arm/mach-ks8695/cpu.c
index 7f3f24053a00..ddb24222918e 100644
--- a/arch/arm/mach-ks8695/cpu.c
+++ b/arch/arm/mach-ks8695/cpu.c
@@ -36,7 +36,7 @@
 
 static struct __initdata map_desc ks8695_io_desc[] = {
         {
-                .virtual        = KS8695_IO_VA,
+                .virtual        = (unsigned long)KS8695_IO_VA,
                 .pfn            = __phys_to_pfn(KS8695_IO_PA),
                 .length         = KS8695_IO_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index 5e0c388143da..5090338c0db2 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -33,7 +33,7 @@
  * head debug code as the initial MMU setup only deals in L1 sections.
  */
 #define KS8695_IO_PA            0x03F00000
-#define KS8695_IO_VA            0xF0000000
+#define KS8695_IO_VA            IOMEM(0xF0000000)
 #define KS8695_IO_SIZE          SZ_1M
 
 #define KS8695_PCIMEM_PA        0x60000000
diff --git a/arch/arm/mach-ks8695/include/mach/uncompress.h b/arch/arm/mach-ks8695/include/mach/uncompress.h
index 9495cb4d701a..8879d610308a 100644
--- a/arch/arm/mach-ks8695/include/mach/uncompress.h
+++ b/arch/arm/mach-ks8695/include/mach/uncompress.h
@@ -19,15 +19,15 @@
 
 static void putc(char c)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTHRE))
                 barrier();
 
-        __raw_writel(c, KS8695_UART_PA + KS8695_URTH);
+        __raw_writel(c, (void __iomem*)KS8695_UART_PA + KS8695_URTH);
 }
 
 static inline void flush(void)
 {
-        while (!(__raw_readl(KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
+        while (!(__raw_readl((void __iomem*)KS8695_UART_PA + KS8695_URLS) & URLS_URTE))
                 barrier();
 }
 
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index a48dc2dec485..0d4db8c544b5 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -177,25 +177,25 @@ u32 clk_get_pclk_div(void)
 
 static struct map_desc lpc32xx_io_desc[] __initdata = {
         {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
                 .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
                 .length         = LPC32XX_AHB0_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
                 .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
                 .length         = LPC32XX_AHB1_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
                 .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
                 .length         = LPC32XX_FABAPB_SIZE,
                 .type           = MT_DEVICE
         },
         {
-                .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
                 .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
                 .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
index 33e1dde37bd9..69065de97a3d 100644
--- a/arch/arm/mach-lpc32xx/include/mach/hardware.h
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -25,7 +25,7 @@
 /*
  * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
  */
-#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+#define IO_ADDRESS(x)   IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
                          IO_BASE)
 
 #define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
index e60c7d98922b..3c71246cd994 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/arch/arm/mach-mmp/irq.c
@@ -153,10 +153,8 @@ static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
                 status = readl_relaxed(data->reg_status) & ~mask;
                 if (status == 0)
                         break;
-                n = find_first_bit(&status, BITS_PER_LONG);
-                while (n < BITS_PER_LONG) {
+                for_each_set_bit(n, &status, BITS_PER_LONG) {
                         generic_handle_irq(icu_data[i].virq_base + n);
-                        n = find_next_bit(&status, BITS_PER_LONG, n + 1);
                 }
         }
 }
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 84183ed2ef79..c5a2eddc6cdc 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -49,13 +49,14 @@ static int msm_smd_debug_mask;
 
 struct shared_info {
         int ready;
-        unsigned state;
+        void __iomem *state;
 };
 
 static unsigned dummy_state[SMSM_STATE_COUNT];
 
 static struct shared_info smd_info = {
-        .state = (unsigned) &dummy_state,
+        /* FIXME: not a real __iomem pointer */
+        .state = &dummy_state,
 };
 
 module_param_named(debug_mask, msm_smd_debug_mask,
@@ -789,22 +790,22 @@ void *smem_alloc(unsigned id, unsigned size)
         return smem_find(id, size);
 }
 
-void *smem_item(unsigned id, unsigned *size)
+void __iomem *smem_item(unsigned id, unsigned *size)
 {
         struct smem_shared *shared = (void *) MSM_SHARED_RAM_BASE;
         struct smem_heap_entry *toc = shared->heap_toc;
 
         if (id >= SMEM_NUM_ITEMS)
-                return 0;
+                return NULL;
 
         if (toc[id].allocated) {
                 *size = toc[id].size;
-                return (void *) (MSM_SHARED_RAM_BASE + toc[id].offset);
+                return (MSM_SHARED_RAM_BASE + toc[id].offset);
         } else {
                 *size = 0;
         }
 
-        return 0;
+        return NULL;
 }
 
 void *smem_find(unsigned id, unsigned size_in)
@@ -850,7 +851,7 @@ static irqreturn_t smsm_irq_handler(int irq, void *data)
 int smsm_change_state(enum smsm_state_item item,
                       uint32_t clear_mask, uint32_t set_mask)
 {
-        unsigned long addr = smd_info.state + item * 4;
+        void __iomem *addr = smd_info.state + item * 4;
         unsigned long flags;
         unsigned state;
 
@@ -936,10 +937,10 @@ int smd_core_init(void)
         /* wait for essential items to be initialized */
         for (;;) {
                 unsigned size;
-                void *state;
+                void __iomem *state;
                 state = smem_item(SMEM_SMSM_SHARED_STATE, &size);
                 if (size == SMSM_V1_SIZE || size == SMSM_V2_SIZE) {
-                        smd_info.state = (unsigned)state;
+                        smd_info.state = state;
                         break;
                 }
         }
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
index 6316dba3bfc8..02035e459f50 100644
--- a/arch/arm/mach-nomadik/include/mach/hardware.h
+++ b/arch/arm/mach-nomadik/include/mach/hardware.h
@@ -30,7 +30,7 @@
                         - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
 
 /* used in asm code, so no casts */
-#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define IO_ADDRESS(x) IOMEM((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
 
 /*
  *   Base address defination for Nomadik Onchip Logic Block
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
index 071003bc8456..7d4687e9cbdf 100644
--- a/arch/arm/mach-nomadik/include/mach/uncompress.h
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -27,10 +27,10 @@
 struct amba_device;
 #include <linux/amba/serial.h>
 
-#define NOMADIK_UART_DR         0x101FB000
-#define NOMADIK_UART_LCRH       0x101FB02c
-#define NOMADIK_UART_CR         0x101FB030
-#define NOMADIK_UART_FR         0x101FB018
+#define NOMADIK_UART_DR         (void __iomem *)0x101FB000
+#define NOMADIK_UART_LCRH       (void __iomem *)0x101FB02c
+#define NOMADIK_UART_CR         (void __iomem *)0x101FB030
+#define NOMADIK_UART_FR         (void __iomem *)0x101FB018
 
 static void putc(const char c)
 {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index fcd4e85c4ddc..346fd26f3aa6 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -232,10 +232,11 @@ config MACH_OMAP3_PANDORA
         select OMAP_PACKAGE_CBB
         select REGULATOR_FIXED_VOLTAGE if REGULATOR
 
-config MACH_OMAP3_TOUCHBOOK
+config MACH_TOUCHBOOK
         bool "OMAP3 Touch Book"
         depends on ARCH_OMAP3
         default y
+        select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_3430SDP
         bool "OMAP 3430 SDP board"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index eb203ec193d0..7706fdfd0252 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -235,7 +235,7 @@ obj-$(CONFIG_MACH_OMAP_3630SDP)		+= board-zoom-display.o
 obj-$(CONFIG_MACH_CM_T35)               += board-cm-t35.o
 obj-$(CONFIG_MACH_CM_T3517)             += board-cm-t3517.o
 obj-$(CONFIG_MACH_IGEP0020)             += board-igep0020.o
-obj-$(CONFIG_MACH_OMAP3_TOUCHBOOK)      += board-omap3touchbook.o
+obj-$(CONFIG_MACH_TOUCHBOOK)            += board-omap3touchbook.o
 obj-$(CONFIG_MACH_OMAP_4430SDP)         += board-4430sdp.o
 obj-$(CONFIG_MACH_OMAP4_PANDA)          += board-omap4panda.o
 
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 7aa5ecaee5a2..8e06de665b14 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1036,13 +1036,13 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
-        CLK(NULL,       "gpt1_fck",             &timer1_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt2_fck",             &timer2_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt3_fck",             &timer3_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt4_fck",             &timer4_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt5_fck",             &timer5_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt6_fck",             &timer6_fck,    CK_AM33XX),
-        CLK(NULL,       "gpt7_fck",             &timer7_fck,    CK_AM33XX),
+        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
+        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
+        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
+        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
+        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
+        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
+        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
         CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
         CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index a0d68dbecfa3..f99e65cfb862 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -241,6 +241,52 @@ static void omap3_clkdm_deny_idle(struct clockdomain *clkdm)
                 _clkdm_del_autodeps(clkdm);
 }
 
+static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_add_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                        omap3_clkdm_wakeup(clkdm);
+        }
+
+        return 0;
+}
+
+static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        if (!clkdm->clktrctrl_mask)
+                return 0;
+
+        hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+
+        if (hwsup) {
+                /* Disable HW transitions when we are changing deps */
+                _disable_hwsup(clkdm);
+                _clkdm_del_autodeps(clkdm);
+                _enable_hwsup(clkdm);
+        } else {
+                if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+                        omap3_clkdm_sleep(clkdm);
+        }
+
+        return 0;
+}
+
 struct clkdm_ops omap2_clkdm_operations = {
         .clkdm_add_wkdep        = omap2_clkdm_add_wkdep,
         .clkdm_del_wkdep        = omap2_clkdm_del_wkdep,
@@ -267,6 +313,6 @@ struct clkdm_ops omap3_clkdm_operations = {
         .clkdm_wakeup           = omap3_clkdm_wakeup,
         .clkdm_allow_idle       = omap3_clkdm_allow_idle,
         .clkdm_deny_idle        = omap3_clkdm_deny_idle,
-        .clkdm_clk_enable       = omap2_clkdm_clk_enable,
-        .clkdm_clk_disable      = omap2_clkdm_clk_disable,
+        .clkdm_clk_enable       = omap3xxx_clkdm_clk_enable,
+        .clkdm_clk_disable      = omap3xxx_clkdm_clk_disable,
 };
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 766338fe4d34..975f6bda0e0b 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -67,6 +67,7 @@
 #define OMAP3430_EN_IVA2_DPLL_MASK                      (0x7 << 0)
 
 /* CM_IDLEST_IVA2 */
+#define OMAP3430_ST_IVA2_SHIFT                          0
 #define OMAP3430_ST_IVA2_MASK                           (1 << 0)
 
 /* CM_IDLEST_PLL_IVA2 */
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 4c965ab426ca..b3275babf192 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -47,7 +47,7 @@
 static void __iomem *wakeupgen_base;
 static void __iomem *sar_base;
 static DEFINE_SPINLOCK(wakeupgen_lock);
-static unsigned int irq_target_cpu[NR_IRQS];
+static unsigned int irq_target_cpu[MAX_IRQS];
 static unsigned int irq_banks = MAX_NR_REG_BANKS;
 static unsigned int max_irqs = MAX_IRQS;
 static unsigned int omap_secure_apis;
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 80b7359500f1..3615e0d9ee3c 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1889,6 +1889,7 @@ static int _enable(struct omap_hwmod *oh)
                         _enable_sysc(oh);
                 }
         } else {
+                _omap4_disable_module(oh);
                 _disable_clocks(oh);
                 pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
                          oh->name, r);
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 9f85c04202d1..94b38af17055 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -100,9 +100,9 @@ static struct omap_hwmod omap3xxx_mpu_hwmod = {
 
 /* IVA2 (IVA2) */
 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
-        { .name = "logic", .rst_shift = 0 },
-        { .name = "seq0", .rst_shift = 1 },
-        { .name = "seq1", .rst_shift = 2 },
+        { .name = "logic", .rst_shift = 0, .st_shift = 8 },
+        { .name = "seq0", .rst_shift = 1, .st_shift = 9 },
+        { .name = "seq1", .rst_shift = 2, .st_shift = 10 },
 };
 
 static struct omap_hwmod omap3xxx_iva_hwmod = {
@@ -112,6 +112,15 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .rst_lines      = omap3xxx_iva_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
         .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
+                }
+        },
 };
 
 /* timer class */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f033f950a232..f9bcb24cd515 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -4209,7 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
 };
 
 /* dsp -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_dsp__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
         .master         = &omap44xx_dsp_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "dpll_iva_m5x2_ck",
@@ -4827,7 +4827,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
 };
 
 /* iva -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_iva__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
         .master         = &omap44xx_iva_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "dpll_iva_m5x2_ck",
@@ -5361,7 +5361,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 };
 
 /* l3_main_2 -> sl2if */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sl2if = {
+static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
         .master         = &omap44xx_l3_main_2_hwmod,
         .slave          = &omap44xx_sl2if_hwmod,
         .clk            = "l3_div_ck",
@@ -6031,7 +6031,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_abe__dmic,
         &omap44xx_l4_abe__dmic_dma,
         &omap44xx_dsp__iva,
-        &omap44xx_dsp__sl2if,
+        /* &omap44xx_dsp__sl2if, */
         &omap44xx_l4_cfg__dsp,
         &omap44xx_l3_main_2__dss,
         &omap44xx_l4_per__dss,
@@ -6067,7 +6067,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__i2c4,
         &omap44xx_l3_main_2__ipu,
         &omap44xx_l3_main_2__iss,
-        &omap44xx_iva__sl2if,
+        /* &omap44xx_iva__sl2if, */
         &omap44xx_l3_main_2__iva,
         &omap44xx_l4_wkup__kbd,
         &omap44xx_l4_cfg__mailbox,
@@ -6098,7 +6098,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_cfg__cm_core,
         &omap44xx_l4_wkup__prm,
         &omap44xx_l4_wkup__scrm,
-        &omap44xx_l3_main_2__sl2if,
+        /* &omap44xx_l3_main_2__sl2if, */
         &omap44xx_l4_abe__slimbus1,
         &omap44xx_l4_abe__slimbus1_dma,
         &omap44xx_l4_per__slimbus2,
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index e17cf974d16c..5214d5bfba27 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -262,6 +262,7 @@ static u32 notrace dmtimer_read_sched_clock(void)
         return 0;
 }
 
+#ifdef CONFIG_OMAP_32K_TIMER
 /* Setup free-running counter for clocksource */
 static int __init omap2_sync32k_clocksource_init(void)
 {
@@ -301,6 +302,12 @@ static int __init omap2_sync32k_clocksource_init(void)
 
         return ret;
 }
+#else
+static inline int omap2_sync32k_clocksource_init(void)
+{
+        return -ENODEV;
+}
+#endif
 
 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
                                                 const char *fck_source)
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
index 83125c6a30b3..0c898fcf909c 100644
--- a/arch/arm/mach-prima2/include/mach/uncompress.h
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -25,11 +25,11 @@ static __inline__ void putc(char c)
          * during kernel decompression, all mappings are flat:
          *  virt_addr == phys_addr
          */
-        while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
+        while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
                 & SIRFSOC_UART1_TXFIFO_FULL)
                 barrier();
 
-        __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
+        __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
 }
 
 static inline void flush(void)
diff --git a/arch/arm/mach-s3c24xx/h1940-bluetooth.c b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
index a5eeb62ce1c2..57aee916bdb1 100644
--- a/arch/arm/mach-s3c24xx/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c24xx/h1940-bluetooth.c
@@ -138,19 +138,7 @@ static struct platform_driver h1940bt_driver = {
         .remove         = h1940bt_remove,
 };
 
-
-static int __init h1940bt_init(void)
-{
-        return platform_driver_register(&h1940bt_driver);
-}
-
-static void __exit h1940bt_exit(void)
-{
-        platform_driver_unregister(&h1940bt_driver);
-}
-
-module_init(h1940bt_init);
-module_exit(h1940bt_exit);
+module_platform_driver(h1940bt_driver);
 
 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
 MODULE_DESCRIPTION("Driver for the iPAQ H1940 bluetooth chip");
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 5a7d0c0010f7..0c7ed7a2b0cd 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -424,7 +424,8 @@ static void __init anubis_map_io(void)
                 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
         } else {
                 /* ensure that the GPIO is setup */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
         }
 }
 
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index ae73ba34ecc6..471334715c37 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -512,8 +512,8 @@ static void jive_power_off(void)
 {
         printk(KERN_INFO "powering system down...\n");
 
-        s3c2410_gpio_setpin(S3C2410_GPC(5), 1);
-        s3c_gpio_cfgpin(S3C2410_GPC(5), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPC(5), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPC(5));
 }
 
 static void __init jive_machine_init(void)
@@ -623,11 +623,11 @@ static void __init jive_machine_init(void)
         gpio_request(S3C2410_GPB(7), "jive spi");
         gpio_direction_output(S3C2410_GPB(7), 1);
 
-        s3c2410_gpio_setpin(S3C2410_GPB(6), 0);
-        s3c_gpio_cfgpin(S3C2410_GPB(6), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPB(6), GPIOF_OUT_INIT_LOW, NULL);
+        gpio_free(S3C2410_GPB(6));
 
-        s3c2410_gpio_setpin(S3C2410_GPG(8), 1);
-        s3c_gpio_cfgpin(S3C2410_GPG(8), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPG(8), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPG(8));
 
         /* initialise the WM8750 spi */
 
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index bd6d2525debe..734bbfe5ea22 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -638,9 +638,9 @@ static void __init mini2440_init(void)
         gpio_free(S3C2410_GPG(4));
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
+        gpio_request_one(S3C2410_GPB(1), GPIOF_IN, NULL);
         s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
-        s3c2410_gpio_setpin(S3C2410_GPB(1), 0);
-        s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPIO_INPUT);
+        gpio_free(S3C2410_GPB(1));
 
         /* mark the key as input, without pullups (there is one on the board) */
         for (i = 0; i < ARRAY_SIZE(mini2440_buttons); i++) {
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 5c05ba1c330f..a71a551094ef 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -119,17 +119,17 @@ static struct platform_device *nexcoder_devices[] __initdata = {
 
 static void __init nexcoder_sensorboard_init(void)
 {
-        // Initialize SCCB bus
-        s3c2410_gpio_setpin(S3C2410_GPE(14), 1); // IICSCL
-        s3c_gpio_cfgpin(S3C2410_GPE(14), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPE(15), 1); // IICSDA
-        s3c_gpio_cfgpin(S3C2410_GPE(15), S3C2410_GPIO_OUTPUT);
-
-        // Power up the sensor board
-        s3c2410_gpio_setpin(S3C2410_GPF(1), 1);
-        s3c_gpio_cfgpin(S3C2410_GPF(1), S3C2410_GPIO_OUTPUT); // CAM_GPIO7 => nLDO_PWRDN
-        s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
-        s3c_gpio_cfgpin(S3C2410_GPF(2), S3C2410_GPIO_OUTPUT); // CAM_GPIO6 => CAM_PWRDN
+        /* Initialize SCCB bus */
+        gpio_request_one(S3C2410_GPE(14), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPE(14)); /* IICSCL */
+        gpio_request_one(S3C2410_GPE(15), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPE(15)); /* IICSDA */
+
+        /* Power up the sensor board */
+        gpio_request_one(S3C2410_GPF(1), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPF(1)); /* CAM_GPIO7 => nLDO_PWRDN */
+        gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+        gpio_free(S3C2410_GPF(2)); /* CAM_GPIO6 => CAM_PWRDN */
 }
 
 static void __init nexcoder_map_io(void)
diff --git a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
index ad2792dfbee1..5876c6ba7500 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris-dvs.c
@@ -175,18 +175,7 @@ static struct platform_driver osiris_dvs_driver = {
         },
 };
 
-static int __init osiris_dvs_init(void)
-{
-        return platform_driver_register(&osiris_dvs_driver);
-}
-
-static void __exit osiris_dvs_exit(void)
-{
-        platform_driver_unregister(&osiris_dvs_driver);
-}
-
-module_init(osiris_dvs_init);
-module_exit(osiris_dvs_exit);
+module_platform_driver(osiris_dvs_driver);
 
 MODULE_DESCRIPTION("Simtec OSIRIS DVS support");
 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index 95d077255024..c0fb3c1bc548 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -274,8 +274,8 @@ static int osiris_pm_suspend(void)
         __raw_writeb(tmp, OSIRIS_VA_CTRL0);
 
         /* ensure that an nRESET is not generated on resume. */
-        s3c2410_gpio_setpin(S3C2410_GPA(21), 1);
-        s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPIO_OUTPUT);
+        gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
+        gpio_free(S3C2410_GPA(21));
 
         return 0;
 }
@@ -396,7 +396,8 @@ static void __init osiris_map_io(void)
                 osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
         } else {
                 /* write-protect line to the NAND */
-                s3c2410_gpio_setpin(S3C2410_GPA(0), 1);
+                gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPA(0));
         }
 
         /* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index cdea671e8931..ac2ea767215d 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -87,7 +87,7 @@
 #define SIMPAD_CS3_PCMCIA_SHORT         (SIMPAD_CS3_GPIO_BASE + 22)
 #define SIMPAD_CS3_GPIO_23              (SIMPAD_CS3_GPIO_BASE + 23)
 
-#define CS3_BASE        0xf1000000
+#define CS3_BASE        IOMEM(0xf1000000)
 
 long simpad_get_cs3_ro(void);
 long simpad_get_cs3_shadow(void);
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index fbd53593be54..6ca92d0d32b2 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -124,7 +124,7 @@ static struct map_desc simpad_io_desc[] __initdata = {
                 .length         = 0x00800000,
                 .type           = MT_DEVICE
         }, {    /* Simpad CS3 */
-                .virtual        = CS3_BASE,
+                .virtual        = (unsigned long)CS3_BASE,
                 .pfn            = __phys_to_pfn(SA1100_CS3_PHYS),
                 .length         = 0x00100000,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f172ca85905c..1089ee5472eb 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -432,7 +432,7 @@ static void usb1_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
-        __raw_writew(__raw_readw(0xE68B0008) | 0x600, 0xE68B0008);
+        __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
 }
 
 static struct r8a66597_platdata usb1_host_data = {
@@ -1224,9 +1224,9 @@ static struct i2c_board_info i2c1_devices[] = {
 };
 
 
-#define GPIO_PORT9CR    0xE6051009
-#define GPIO_PORT10CR   0xE605100A
-#define USCCR1          0xE6058144
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
+#define USCCR1          IOMEM(0xE6058144)
 static void __init ap4evb_init(void)
 {
         u32 srcr4;
@@ -1304,7 +1304,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_OVCN2_1,    NULL);
 
         /* setup USB phy */
-        __raw_writew(0x8a0a, 0xE6058130);       /* USBCR4 */
+        __raw_writew(0x8a0a, IOMEM(0xE6058130));        /* USBCR4 */
 
         /* enable FSI2 port A (ak4643) */
         gpio_request(GPIO_FN_FSIAIBT,   NULL);
@@ -1453,7 +1453,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_HDMI_CEC, NULL);
 
         /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
-#define SRCR4 0xe61580bc
+#define SRCR4 IOMEM(0xe61580bc)
         srcr4 = __raw_readl(SRCR4);
         __raw_writel(srcr4 | (1 << 13), SRCR4);
         udelay(50);
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 453a6e50db8b..45b33e02dff5 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -135,7 +135,7 @@
  *      usbhsf_power_ctrl()
  */
 #define IRQ7            evt2irq(0x02e0)
-#define USBCR1          0xe605810a
+#define USBCR1          IOMEM(0xe605810a)
 #define USBH            0xC6700000
 #define USBH_USBCTR     0x10834
 
@@ -950,8 +950,8 @@ clock_error:
 /*
  * board init
  */
-#define GPIO_PORT7CR    0xe6050007
-#define GPIO_PORT8CR    0xe6050008
+#define GPIO_PORT7CR    IOMEM(0xe6050007)
+#define GPIO_PORT8CR    IOMEM(0xe6050008)
 static void __init eva_init(void)
 {
         struct platform_device *usb = NULL;
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index 4129008eae29..cb8c994e1430 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -108,12 +108,12 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 #define FPGA_ETH_IRQ            (FPGA_IRQ0 + 15)
 static u16 bonito_fpga_read(u32 offset)
 {
-        return __raw_readw(0xf0003000 + offset);
+        return __raw_readw(IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_write(u32 offset, u16 val)
 {
-        __raw_writew(val, 0xf0003000 + offset);
+        __raw_writew(val, IOMEM(0xf0003000) + offset);
 }
 
 static void bonito_fpga_irq_disable(struct irq_data *data)
@@ -361,8 +361,8 @@ static void __init bonito_map_io(void)
 #define BIT_ON(sw, bit)         (sw & (1 << bit))
 #define BIT_OFF(sw, bit)        (!(sw & (1 << bit)))
 
-#define VCCQ1CR         0xE6058140
-#define VCCQ1LCDCR      0xE6058186
+#define VCCQ1CR         IOMEM(0xE6058140)
+#define VCCQ1LCDCR      IOMEM(0xE6058186)
 
 static void __init bonito_init(void)
 {
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index 796fa00ad3c4..b179d4c213bb 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -106,7 +106,7 @@ static void usb_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -279,10 +279,10 @@ static void __init g3evm_init(void)
         gpio_request(GPIO_FN_IDIN, NULL);
 
         /* setup USB phy */
-        __raw_writew(0x0300, 0xe605810a);       /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x0300, IOMEM(0xe605810a));        /* USBCR1 */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));        /* CPFCH */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));        /* CGPOSR */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));        /* USBCR2 */
 
         /* KEYSC @ CN7 */
         gpio_request(GPIO_FN_PORT42_KEYOUT0, NULL);
@@ -320,7 +320,7 @@ static void __init g3evm_init(void)
         gpio_request(GPIO_FN_WE0_XWR0_FWE, NULL);
         gpio_request(GPIO_FN_FRB, NULL);
         /* FOE, FCDE, FSC on dedicated pins */
-        __raw_writel(__raw_readl(0xe6158048) & ~(1 << 15), 0xe6158048);
+        __raw_writel(__raw_readl(IOMEM(0xe6158048)) & ~(1 << 15), IOMEM(0xe6158048));
 
         /* IrDA */
         gpio_request(GPIO_FN_IRDA_OUT, NULL);
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index fa5dfc5c8ed6..22d689322533 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -126,7 +126,7 @@ static void usb_host_port_power(int port, int power)
                 return;
 
         /* set VBOUT/PWEN and EXTLP0 in DVSTCTR */
-        __raw_writew(__raw_readw(0xe6890008) | 0x600, 0xe6890008);
+        __raw_writew(__raw_readw(IOMEM(0xe6890008)) | 0x600, IOMEM(0xe6890008));
 }
 
 static struct r8a66597_platdata usb_host_data = {
@@ -270,17 +270,17 @@ static struct platform_device *g4evm_devices[] __initdata = {
         &sdhi1_device,
 };
 
-#define GPIO_SDHID0_D0  0xe60520fc
-#define GPIO_SDHID0_D1  0xe60520fd
-#define GPIO_SDHID0_D2  0xe60520fe
-#define GPIO_SDHID0_D3  0xe60520ff
-#define GPIO_SDHICMD0   0xe6052100
+#define GPIO_SDHID0_D0  IOMEM(0xe60520fc)
+#define GPIO_SDHID0_D1  IOMEM(0xe60520fd)
+#define GPIO_SDHID0_D2  IOMEM(0xe60520fe)
+#define GPIO_SDHID0_D3  IOMEM(0xe60520ff)
+#define GPIO_SDHICMD0   IOMEM(0xe6052100)
 
-#define GPIO_SDHID1_D0  0xe6052103
-#define GPIO_SDHID1_D1  0xe6052104
-#define GPIO_SDHID1_D2  0xe6052105
-#define GPIO_SDHID1_D3  0xe6052106
-#define GPIO_SDHICMD1   0xe6052107
+#define GPIO_SDHID1_D0  IOMEM(0xe6052103)
+#define GPIO_SDHID1_D1  IOMEM(0xe6052104)
+#define GPIO_SDHID1_D2  IOMEM(0xe6052105)
+#define GPIO_SDHID1_D3  IOMEM(0xe6052106)
+#define GPIO_SDHICMD1   IOMEM(0xe6052107)
 
 static void __init g4evm_init(void)
 {
@@ -318,10 +318,10 @@ static void __init g4evm_init(void)
         gpio_request(GPIO_FN_IDIN, NULL);
 
         /* setup USB phy */
-        __raw_writew(0x0200, 0xe605810a);       /* USBCR1 */
-        __raw_writew(0x00e0, 0xe60581c0);       /* CPFCH */
-        __raw_writew(0x6010, 0xe60581c6);       /* CGPOSR */
-        __raw_writew(0x8a0a, 0xe605810c);       /* USBCR2 */
+        __raw_writew(0x0200, IOMEM(0xe605810a));       /* USBCR1 */
+        __raw_writew(0x00e0, IOMEM(0xe60581c0));       /* CPFCH */
+        __raw_writew(0x6010, IOMEM(0xe60581c6));       /* CGPOSR */
+        __raw_writew(0x8a0a, IOMEM(0xe605810c));       /* USBCR2 */
 
         /* KEYSC @ CN31 */
         gpio_request(GPIO_FN_PORT60_KEYOUT5, NULL);
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 53b7ea92c32c..5ffafc1adf99 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -133,8 +133,8 @@ static struct platform_device usb_host_device = {
 
 /* USB Func CN17 */
 struct usbhs_private {
-        unsigned int phy;
-        unsigned int cr2;
+        void __iomem *phy;
+        void __iomem *cr2;
         struct renesas_usbhs_platform_info info;
 };
 
@@ -232,8 +232,8 @@ static u32 usbhs_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs_private = {
-        .phy    = 0xe60781e0,           /* USBPHYINT */
-        .cr2    = 0xe605810c,           /* USBCR2 */
+        .phy    = IOMEM(0xe60781e0),            /* USBPHYINT */
+        .cr2    = IOMEM(0xe605810c),            /* USBCR2 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs_hardware_init,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index c129542f6aed..0dce90ee6cf2 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -583,8 +583,8 @@ out:
 #define USBHS0_POLL_INTERVAL (HZ * 5)
 
 struct usbhs_private {
-        unsigned int usbphyaddr;
-        unsigned int usbcrcaddr;
+        void __iomem *usbphyaddr;
+        void __iomem *usbcrcaddr;
         struct renesas_usbhs_platform_info info;
         struct delayed_work work;
         struct platform_device *pdev;
@@ -642,7 +642,7 @@ static void usbhs0_hardware_exit(struct platform_device *pdev)
 }
 
 static struct usbhs_private usbhs0_private = {
-        .usbcrcaddr     = 0xe605810c,           /* USBCR2 */
+        .usbcrcaddr     = IOMEM(0xe605810c),            /* USBCR2 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs0_hardware_init,
@@ -776,8 +776,8 @@ static u32 usbhs1_pipe_cfg[] = {
 };
 
 static struct usbhs_private usbhs1_private = {
-        .usbphyaddr     = 0xe60581e2,           /* USBPHY1INTAP */
-        .usbcrcaddr     = 0xe6058130,           /* USBCR4 */
+        .usbphyaddr     = IOMEM(0xe60581e2),    /* USBPHY1INTAP */
+        .usbcrcaddr     = IOMEM(0xe6058130),    /* USBCR4 */
         .info = {
                 .platform_callback = {
                         .hardware_init  = usbhs1_hardware_init,
@@ -1402,12 +1402,12 @@ static struct i2c_board_info i2c1_devices[] = {
         },
 };
 
-#define GPIO_PORT9CR    0xE6051009
-#define GPIO_PORT10CR   0xE605100A
-#define GPIO_PORT167CR  0xE60520A7
-#define GPIO_PORT168CR  0xE60520A8
-#define SRCR4           0xe61580bc
-#define USCCR1          0xE6058144
+#define GPIO_PORT9CR    IOMEM(0xE6051009)
+#define GPIO_PORT10CR   IOMEM(0xE605100A)
+#define GPIO_PORT167CR  IOMEM(0xE60520A7)
+#define GPIO_PORT168CR  IOMEM(0xE60520A8)
+#define SRCR4           IOMEM(0xe61580bc)
+#define USCCR1          IOMEM(0xE6058144)
 static void __init mackerel_init(void)
 {
         u32 srcr4;
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index ad5fccc7b5e7..6729e0032180 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -41,29 +41,29 @@
  */
 
 /* CPG registers */
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define VCLKCR1         0xE6150008
-#define VCLKCR2         0xE615000c
-#define FRQCRC          0xe61500e0
-#define FSIACKCR        0xe6150018
-#define PLLC01CR        0xe6150028
-
-#define SUBCKCR         0xe6150080
-#define USBCKCR         0xe615008c
-
-#define MSTPSR0         0xe6150030
-#define MSTPSR1         0xe6150038
-#define MSTPSR2         0xe6150040
-#define MSTPSR3         0xe6150048
-#define MSTPSR4         0xe615004c
-#define FSIBCKCR        0xe6150090
-#define HDMICKCR        0xe6150094
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define VCLKCR1         IOMEM(0xE6150008)
+#define VCLKCR2         IOMEM(0xE615000c)
+#define FRQCRC          IOMEM(0xe61500e0)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define PLLC01CR        IOMEM(0xe6150028)
+
+#define SUBCKCR         IOMEM(0xe6150080)
+#define USBCKCR         IOMEM(0xe615008c)
+
+#define MSTPSR0         IOMEM(0xe6150030)
+#define MSTPSR1         IOMEM(0xe6150038)
+#define MSTPSR2         IOMEM(0xe6150040)
+#define MSTPSR3         IOMEM(0xe6150048)
+#define MSTPSR4         IOMEM(0xe615004c)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define HDMICKCR        IOMEM(0xe6150094)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk extalr_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index 162b791b8984..ef0a95e592c4 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -24,28 +24,28 @@
 #include <mach/common.h>
 
 /* SH7367 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define SCLKACR    0xe6150010
-#define SCLKBCR    0xe6150014
-#define SUBUSBCKCR 0xe6158080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define VOUCKCR    0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define RTMSTPCR0  0xe6158030
-#define RTMSTPCR2  0xe6158038
-#define SYMSTPCR0  0xe6158040
-#define SYMSTPCR2  0xe6158048
-#define CMMSTPCR0  0xe615804c
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define SCLKACR    IOMEM(0xe6150010)
+#define SCLKBCR    IOMEM(0xe6150014)
+#define SUBUSBCKCR IOMEM(0xe6158080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define VOUCKCR    IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define RTMSTPCR0  IOMEM(0xe6158030)
+#define RTMSTPCR2  IOMEM(0xe6158038)
+#define SYMSTPCR0  IOMEM(0xe6158040)
+#define SYMSTPCR2  IOMEM(0xe6158048)
+#define CMMSTPCR0  IOMEM(0xe615804c)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 5a2894b1c965..430a90ffa120 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -24,36 +24,36 @@
 #include <mach/common.h>
 
 /* SH7372 registers */
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define FRQCRC          0xe61500e0
-#define FRQCRD          0xe61500e4
-#define VCLKCR1         0xe6150008
-#define VCLKCR2         0xe615000c
-#define VCLKCR3         0xe615001c
-#define FMSICKCR        0xe6150010
-#define FMSOCKCR        0xe6150014
-#define FSIACKCR        0xe6150018
-#define FSIBCKCR        0xe6150090
-#define SUBCKCR         0xe6150080
-#define SPUCKCR         0xe6150084
-#define VOUCKCR         0xe6150088
-#define HDMICKCR        0xe6150094
-#define DSITCKCR        0xe6150060
-#define DSI0PCKCR       0xe6150064
-#define DSI1PCKCR       0xe6150098
-#define PLLC01CR        0xe6150028
-#define PLLC2CR         0xe615002c
-#define RMSTPCR0        0xe6150110
-#define RMSTPCR1        0xe6150114
-#define RMSTPCR2        0xe6150118
-#define RMSTPCR3        0xe615011c
-#define RMSTPCR4        0xe6150120
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define FRQCRC          IOMEM(0xe61500e0)
+#define FRQCRD          IOMEM(0xe61500e4)
+#define VCLKCR1         IOMEM(0xe6150008)
+#define VCLKCR2         IOMEM(0xe615000c)
+#define VCLKCR3         IOMEM(0xe615001c)
+#define FMSICKCR        IOMEM(0xe6150010)
+#define FMSOCKCR        IOMEM(0xe6150014)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define SUBCKCR         IOMEM(0xe6150080)
+#define SPUCKCR         IOMEM(0xe6150084)
+#define VOUCKCR         IOMEM(0xe6150088)
+#define HDMICKCR        IOMEM(0xe6150094)
+#define DSITCKCR        IOMEM(0xe6150060)
+#define DSI0PCKCR       IOMEM(0xe6150064)
+#define DSI1PCKCR       IOMEM(0xe6150098)
+#define PLLC01CR        IOMEM(0xe6150028)
+#define PLLC2CR         IOMEM(0xe615002c)
+#define RMSTPCR0        IOMEM(0xe6150110)
+#define RMSTPCR1        IOMEM(0xe6150114)
+#define RMSTPCR2        IOMEM(0xe6150118)
+#define RMSTPCR3        IOMEM(0xe615011c)
+#define RMSTPCR4        IOMEM(0xe6150120)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
 
 #define FSIDIVA         0xFE1F8000
 #define FSIDIVB         0xFE1F8008
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index 85f2a3ec2c44..b8480d19e1c8 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -24,31 +24,31 @@
 #include <mach/common.h>
 
 /* SH7377 registers */
-#define RTFRQCR    0xe6150000
-#define SYFRQCR    0xe6150004
-#define CMFRQCR    0xe61500E0
-#define VCLKCR1    0xe6150008
-#define VCLKCR2    0xe615000C
-#define VCLKCR3    0xe615001C
-#define FMSICKCR   0xe6150010
-#define FMSOCKCR   0xe6150014
-#define FSICKCR    0xe6150018
-#define PLLC1CR    0xe6150028
-#define PLLC2CR    0xe615002C
-#define SUBUSBCKCR 0xe6150080
-#define SPUCKCR    0xe6150084
-#define MSUCKCR    0xe6150088
-#define MVI3CKCR   0xe6150090
-#define HDMICKCR   0xe6150094
-#define MFCK1CR    0xe6150098
-#define MFCK2CR    0xe615009C
-#define DSITCKCR   0xe6150060
-#define DSIPCKCR   0xe6150064
-#define SMSTPCR0   0xe6150130
-#define SMSTPCR1   0xe6150134
-#define SMSTPCR2   0xe6150138
-#define SMSTPCR3   0xe615013C
-#define SMSTPCR4   0xe6150140
+#define RTFRQCR    IOMEM(0xe6150000)
+#define SYFRQCR    IOMEM(0xe6150004)
+#define CMFRQCR    IOMEM(0xe61500E0)
+#define VCLKCR1    IOMEM(0xe6150008)
+#define VCLKCR2    IOMEM(0xe615000C)
+#define VCLKCR3    IOMEM(0xe615001C)
+#define FMSICKCR   IOMEM(0xe6150010)
+#define FMSOCKCR   IOMEM(0xe6150014)
+#define FSICKCR    IOMEM(0xe6150018)
+#define PLLC1CR    IOMEM(0xe6150028)
+#define PLLC2CR    IOMEM(0xe615002C)
+#define SUBUSBCKCR IOMEM(0xe6150080)
+#define SPUCKCR    IOMEM(0xe6150084)
+#define MSUCKCR    IOMEM(0xe6150088)
+#define MVI3CKCR   IOMEM(0xe6150090)
+#define HDMICKCR   IOMEM(0xe6150094)
+#define MFCK1CR    IOMEM(0xe6150098)
+#define MFCK2CR    IOMEM(0xe615009C)
+#define DSITCKCR   IOMEM(0xe6150060)
+#define DSIPCKCR   IOMEM(0xe6150064)
+#define SMSTPCR0   IOMEM(0xe6150130)
+#define SMSTPCR1   IOMEM(0xe6150134)
+#define SMSTPCR2   IOMEM(0xe6150138)
+#define SMSTPCR3   IOMEM(0xe615013C)
+#define SMSTPCR4   IOMEM(0xe6150140)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7f8da18a8580..516ff7f3e434 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -23,43 +23,43 @@
 #include <linux/clkdev.h>
 #include <mach/common.h>
 
-#define FRQCRA          0xe6150000
-#define FRQCRB          0xe6150004
-#define FRQCRD          0xe61500e4
-#define VCLKCR1         0xe6150008
-#define VCLKCR2         0xe615000C
-#define VCLKCR3         0xe615001C
-#define ZBCKCR          0xe6150010
-#define FLCKCR          0xe6150014
-#define SD0CKCR         0xe6150074
-#define SD1CKCR         0xe6150078
-#define SD2CKCR         0xe615007C
-#define FSIACKCR        0xe6150018
-#define FSIBCKCR        0xe6150090
-#define SUBCKCR         0xe6150080
-#define SPUACKCR        0xe6150084
-#define SPUVCKCR        0xe6150094
-#define MSUCKCR         0xe6150088
-#define HSICKCR         0xe615008C
-#define MFCK1CR         0xe6150098
-#define MFCK2CR         0xe615009C
-#define DSITCKCR        0xe6150060
-#define DSI0PCKCR       0xe6150064
-#define DSI1PCKCR       0xe6150068
+#define FRQCRA          IOMEM(0xe6150000)
+#define FRQCRB          IOMEM(0xe6150004)
+#define FRQCRD          IOMEM(0xe61500e4)
+#define VCLKCR1         IOMEM(0xe6150008)
+#define VCLKCR2         IOMEM(0xe615000C)
+#define VCLKCR3         IOMEM(0xe615001C)
+#define ZBCKCR          IOMEM(0xe6150010)
+#define FLCKCR          IOMEM(0xe6150014)
+#define SD0CKCR         IOMEM(0xe6150074)
+#define SD1CKCR         IOMEM(0xe6150078)
+#define SD2CKCR         IOMEM(0xe615007C)
+#define FSIACKCR        IOMEM(0xe6150018)
+#define FSIBCKCR        IOMEM(0xe6150090)
+#define SUBCKCR         IOMEM(0xe6150080)
+#define SPUACKCR        IOMEM(0xe6150084)
+#define SPUVCKCR        IOMEM(0xe6150094)
+#define MSUCKCR         IOMEM(0xe6150088)
+#define HSICKCR         IOMEM(0xe615008C)
+#define MFCK1CR         IOMEM(0xe6150098)
+#define MFCK2CR         IOMEM(0xe615009C)
+#define DSITCKCR        IOMEM(0xe6150060)
+#define DSI0PCKCR       IOMEM(0xe6150064)
+#define DSI1PCKCR       IOMEM(0xe6150068)
 #define DSI0PHYCR       0xe615006C
 #define DSI1PHYCR       0xe6150070
-#define PLLECR          0xe61500d0
-#define PLL0CR          0xe61500d8
-#define PLL1CR          0xe6150028
-#define PLL2CR          0xe615002c
-#define PLL3CR          0xe61500dc
-#define SMSTPCR0        0xe6150130
-#define SMSTPCR1        0xe6150134
-#define SMSTPCR2        0xe6150138
-#define SMSTPCR3        0xe615013c
-#define SMSTPCR4        0xe6150140
-#define SMSTPCR5        0xe6150144
-#define CKSCR           0xe61500c0
+#define PLLECR          IOMEM(0xe61500d0)
+#define PLL0CR          IOMEM(0xe61500d8)
+#define PLL1CR          IOMEM(0xe6150028)
+#define PLL2CR          IOMEM(0xe615002c)
+#define PLL3CR          IOMEM(0xe61500dc)
+#define SMSTPCR0        IOMEM(0xe6150130)
+#define SMSTPCR1        IOMEM(0xe6150134)
+#define SMSTPCR2        IOMEM(0xe6150138)
+#define SMSTPCR3        IOMEM(0xe615013c)
+#define SMSTPCR4        IOMEM(0xe6150140)
+#define SMSTPCR5        IOMEM(0xe6150144)
+#define CKSCR           IOMEM(0xe61500c0)
 
 /* Fixed 32 KHz root clock from EXTALR pin */
 static struct clk r_clk = {
diff --git a/arch/arm/mach-shmobile/include/mach/gpio.h b/arch/arm/mach-shmobile/include/mach/gpio.h
index 844507d937cb..90a92b2c1c52 100644
--- a/arch/arm/mach-shmobile/include/mach/gpio.h
+++ b/arch/arm/mach-shmobile/include/mach/gpio.h
@@ -35,12 +35,12 @@ static inline int irq_to_gpio(unsigned int irq)
  * the method to control only pull up/down/free.
  * this function should be replaced by correct gpio function
  */
-static inline void __init gpio_direction_none(u32 addr)
+static inline void __init gpio_direction_none(void __iomem * addr)
 {
         __raw_writeb(0x00, addr);
 }
 
-static inline void __init gpio_request_pullup(u32 addr)
+static inline void __init gpio_request_pullup(void __iomem * addr)
 {
         u8 data = __raw_readb(addr);
 
@@ -49,7 +49,7 @@ static inline void __init gpio_request_pullup(u32 addr)
         __raw_writeb(data, addr);
 }
 
-static inline void __init gpio_request_pulldown(u32 addr)
+static inline void __init gpio_request_pulldown(void __iomem * addr)
 {
         u8 data = __raw_readb(addr);
 
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
index f04fad4ec4fb..ef66f1a8aa2e 100644
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -29,14 +29,14 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-#define INT2SMSKCR0 0xfe7822a0
-#define INT2SMSKCR1 0xfe7822a4
-#define INT2SMSKCR2 0xfe7822a8
-#define INT2SMSKCR3 0xfe7822ac
-#define INT2SMSKCR4 0xfe7822b0
+#define INT2SMSKCR0 IOMEM(0xfe7822a0)
+#define INT2SMSKCR1 IOMEM(0xfe7822a4)
+#define INT2SMSKCR2 IOMEM(0xfe7822a8)
+#define INT2SMSKCR3 IOMEM(0xfe7822ac)
+#define INT2SMSKCR4 IOMEM(0xfe7822b0)
 
-#define INT2NTSR0 0xfe700060
-#define INT2NTSR1 0xfe700064
+#define INT2NTSR0 IOMEM(0xfe700060)
+#define INT2NTSR1 IOMEM(0xfe700064)
 
 static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
 {
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 2587a22842f2..a91caad7db7c 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -624,6 +624,9 @@ void sh7372_intcs_resume(void)
                 __raw_writeb(ffd5[k], intcs_ffd5 + k);
 }
 
+#define E694_BASE IOMEM(0xe6940000)
+#define E695_BASE IOMEM(0xe6950000)
+
 static unsigned short e694[0x200];
 static unsigned short e695[0x200];
 
@@ -632,22 +635,22 @@ void sh7372_intca_suspend(void)
         int k;
 
         for (k = 0x00; k <= 0x38; k += 4)
-                e694[k] = __raw_readw(0xe6940000 + k);
+                e694[k] = __raw_readw(E694_BASE + k);
 
         for (k = 0x80; k <= 0xb4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
 
         for (k = 0x180; k <= 0x1b4; k += 4)
-                e694[k] = __raw_readb(0xe6940000 + k);
+                e694[k] = __raw_readb(E694_BASE + k);
 
         for (k = 0x00; k <= 0x50; k += 4)
-                e695[k] = __raw_readw(0xe6950000 + k);
+                e695[k] = __raw_readw(E695_BASE + k);
 
         for (k = 0x80; k <= 0xa8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
 
         for (k = 0x180; k <= 0x1a8; k += 4)
-                e695[k] = __raw_readb(0xe6950000 + k);
+                e695[k] = __raw_readb(E695_BASE + k);
 }
 
 void sh7372_intca_resume(void)
@@ -655,20 +658,20 @@ void sh7372_intca_resume(void)
         int k;
 
         for (k = 0x00; k <= 0x38; k += 4)
-                __raw_writew(e694[k], 0xe6940000 + k);
+                __raw_writew(e694[k], E694_BASE + k);
 
         for (k = 0x80; k <= 0xb4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
 
         for (k = 0x180; k <= 0x1b4; k += 4)
-                __raw_writeb(e694[k], 0xe6940000 + k);
+                __raw_writeb(e694[k], E694_BASE + k);
 
         for (k = 0x00; k <= 0x50; k += 4)
-                __raw_writew(e695[k], 0xe6950000 + k);
+                __raw_writew(e695[k], E695_BASE + k);
 
         for (k = 0x80; k <= 0xa8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
 
         for (k = 0x180; k <= 0x1a8; k += 4)
-                __raw_writeb(e695[k], 0xe6950000 + k);
+                __raw_writeb(e695[k], E695_BASE + k);
 }
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index 588555a67d9c..f0c5e5190601 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -366,10 +366,12 @@ static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
 
 static struct irqaction sh73a0_irq_pin_cascade[32];
 
-#define PINTER0 0xe69000a0
-#define PINTER1 0xe69000a4
-#define PINTRR0 0xe69000d0
-#define PINTRR1 0xe69000d4
+#define PINTER0_PHYS 0xe69000a0
+#define PINTER1_PHYS 0xe69000a4
+#define PINTER0_VIRT IOMEM(0xe69000a0)
+#define PINTER1_VIRT IOMEM(0xe69000a4)
+#define PINTRR0 IOMEM(0xe69000d0)
+#define PINTRR1 IOMEM(0xe69000d4)
 
 #define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
 #define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
@@ -377,14 +379,14 @@ static struct irqaction sh73a0_irq_pin_cascade[32];
 #define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
 #define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
 
-INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0",              \
+INTC_PINT(intc_pint0, PINTER0_PHYS, 0xe69000b0, "sh73a0-pint0",         \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
   INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ),               \
   INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ),               \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D),       \
   INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
 
-INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",              \
+INTC_PINT(intc_pint1, PINTER1_PHYS, 0xe69000c0, "sh73a0-pint1",         \
   INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
   INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE,                         \
   INTC_PINT_V_NONE, INTC_PINT_V_NONE,                                   \
@@ -394,7 +396,7 @@ INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1",		\
 static struct irqaction sh73a0_pint0_cascade;
 static struct irqaction sh73a0_pint1_cascade;
 
-static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
+static void pint_demux(void __iomem *rr, void __iomem *er, int base_irq)
 {
         unsigned long value =  ioread32(rr) & ioread32(er);
         int k;
@@ -409,13 +411,13 @@ static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
 
 static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
+        pint_demux(PINTRR0, PINTER0_VIRT, SH73A0_PINT0_IRQ(0));
         return IRQ_HANDLED;
 }
 
 static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
 {
-        pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
+        pint_demux(PINTRR1, PINTER1_VIRT, SH73A0_PINT1_IRQ(0));
         return IRQ_HANDLED;
 }
 
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index a8562540f1d6..32e177275e47 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -20,9 +20,9 @@
 #include <mach/pm-rmobile.h>
 
 /* SYSC */
-#define SPDCR           0xe6180008
-#define SWUCR           0xe6180014
-#define PSTR            0xe6180080
+#define SPDCR           IOMEM(0xe6180008)
+#define SWUCR           IOMEM(0xe6180014)
+#define PSTR            IOMEM(0xe6180080)
 
 #define PSTR_RETRIES    100
 #define PSTR_DELAY_US   10
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 792037069226..162121842a2b 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -29,45 +29,46 @@
 #include <mach/pm-rmobile.h>
 
 /* DBG */
-#define DBGREG1 0xe6100020
-#define DBGREG9 0xe6100040
+#define DBGREG1 IOMEM(0xe6100020)
+#define DBGREG9 IOMEM(0xe6100040)
 
 /* CPGA */
-#define SYSTBCR 0xe6150024
-#define MSTPSR0 0xe6150030
-#define MSTPSR1 0xe6150038
-#define MSTPSR2 0xe6150040
-#define MSTPSR3 0xe6150048
-#define MSTPSR4 0xe615004c
-#define PLLC01STPCR 0xe61500c8
+#define SYSTBCR IOMEM(0xe6150024)
+#define MSTPSR0 IOMEM(0xe6150030)
+#define MSTPSR1 IOMEM(0xe6150038)
+#define MSTPSR2 IOMEM(0xe6150040)
+#define MSTPSR3 IOMEM(0xe6150048)
+#define MSTPSR4 IOMEM(0xe615004c)
+#define PLLC01STPCR IOMEM(0xe61500c8)
 
 /* SYSC */
-#define SBAR 0xe6180020
-#define WUPRMSK 0xe6180028
-#define WUPSMSK 0xe618002c
-#define WUPSMSK2 0xe6180048
-#define WUPSFAC 0xe6180098
-#define IRQCR 0xe618022c
-#define IRQCR2 0xe6180238
-#define IRQCR3 0xe6180244
-#define IRQCR4 0xe6180248
-#define PDNSEL 0xe6180254
+#define SBAR IOMEM(0xe6180020)
+#define WUPRMSK IOMEM(0xe6180028)
+#define WUPSMSK IOMEM(0xe618002c)
+#define WUPSMSK2 IOMEM(0xe6180048)
+#define WUPSFAC IOMEM(0xe6180098)
+#define IRQCR IOMEM(0xe618022c)
+#define IRQCR2 IOMEM(0xe6180238)
+#define IRQCR3 IOMEM(0xe6180244)
+#define IRQCR4 IOMEM(0xe6180248)
+#define PDNSEL IOMEM(0xe6180254)
 
 /* INTC */
-#define ICR1A 0xe6900000
-#define ICR2A 0xe6900004
-#define ICR3A 0xe6900008
-#define ICR4A 0xe690000c
-#define INTMSK00A 0xe6900040
-#define INTMSK10A 0xe6900044
-#define INTMSK20A 0xe6900048
-#define INTMSK30A 0xe690004c
+#define ICR1A IOMEM(0xe6900000)
+#define ICR2A IOMEM(0xe6900004)
+#define ICR3A IOMEM(0xe6900008)
+#define ICR4A IOMEM(0xe690000c)
+#define INTMSK00A IOMEM(0xe6900040)
+#define INTMSK10A IOMEM(0xe6900044)
+#define INTMSK20A IOMEM(0xe6900048)
+#define INTMSK30A IOMEM(0xe690004c)
 
 /* MFIS */
+/* FIXME: pointing where? */
 #define SMFRAM 0xe6a70000
 
 /* AP-System Core */
-#define APARMBAREA 0xe6f10020
+#define APARMBAREA IOMEM(0xe6f10020)
 
 #ifdef CONFIG_PM
 
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 2e3074ab75b3..e647f5410879 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -462,7 +462,7 @@ static void __init sh7367_earlytimer_init(void)
         shmobile_earlytimer_init();
 }
 
-#define SYMSTPCR2 0xe6158048
+#define SYMSTPCR2 IOMEM(0xe6158048)
 #define SYMSTPCR2_CMT1 (1 << 29)
 
 void __init sh7367_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 855b1506caf8..edcf98bb7012 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -484,7 +484,7 @@ static void __init sh7377_earlytimer_init(void)
         shmobile_earlytimer_init();
 }
 
-#define SMSTPCR3 0xe615013c
+#define SMSTPCR3 IOMEM(0xe615013c)
 #define SMSTPCR3_CMT1 (1 << 29)
 
 void __init sh7377_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index d230af656fc9..a13c97b4ba1d 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -759,7 +759,7 @@ static struct platform_device *sh73a0_late_devices[] __initdata = {
         &mpdma0_device,
 };
 
-#define SRCR2          0xe61580b0
+#define SRCR2          IOMEM(0xe61580b0)
 
 void __init sh73a0_add_standard_devices(void)
 {
diff --git a/arch/arm/mach-spear13xx/include/mach/spear.h b/arch/arm/mach-spear13xx/include/mach/spear.h
index 65f27def239b..07d90acc92c8 100644
--- a/arch/arm/mach-spear13xx/include/mach/spear.h
+++ b/arch/arm/mach-spear13xx/include/mach/spear.h
@@ -17,26 +17,26 @@
 #include <asm/memory.h>
 
 #define PERIP_GRP2_BASE                         UL(0xB3000000)
-#define VA_PERIP_GRP2_BASE                      UL(0xFE000000)
+#define VA_PERIP_GRP2_BASE                      IOMEM(0xFE000000)
 #define MCIF_SDHCI_BASE                         UL(0xB3000000)
 #define SYSRAM0_BASE                            UL(0xB3800000)
-#define VA_SYSRAM0_BASE                         UL(0xFE800000)
+#define VA_SYSRAM0_BASE                         IOMEM(0xFE800000)
 #define SYS_LOCATION                            (VA_SYSRAM0_BASE + 0x600)
 
 #define PERIP_GRP1_BASE                         UL(0xE0000000)
-#define VA_PERIP_GRP1_BASE                      UL(0xFD000000)
+#define VA_PERIP_GRP1_BASE                      IOMEM(0xFD000000)
 #define UART_BASE                               UL(0xE0000000)
-#define VA_UART_BASE                            UL(0xFD000000)
+#define VA_UART_BASE                            IOMEM(0xFD000000)
 #define SSP_BASE                                UL(0xE0100000)
 #define MISC_BASE                               UL(0xE0700000)
-#define VA_MISC_BASE                            IOMEM(UL(0xFD700000))
+#define VA_MISC_BASE                            IOMEM(0xFD700000)
 
 #define A9SM_AND_MPMC_BASE                      UL(0xEC000000)
-#define VA_A9SM_AND_MPMC_BASE                   UL(0xFC000000)
+#define VA_A9SM_AND_MPMC_BASE                   IOMEM(0xFC000000)
 
 /* A9SM peripheral offsets */
 #define A9SM_PERIP_BASE                         UL(0xEC800000)
-#define VA_A9SM_PERIP_BASE                      UL(0xFC800000)
+#define VA_A9SM_PERIP_BASE                      IOMEM(0xFC800000)
 #define VA_SCU_BASE                             (VA_A9SM_PERIP_BASE + 0x00)
 
 #define L2CC_BASE                               UL(0xED000000)
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index cf936b106e27..e10648801b2e 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -114,17 +114,17 @@ void __init spear13xx_l2x0_init(void)
  */
 struct map_desc spear13xx_io_desc[] __initdata = {
         {
-                .virtual        = VA_PERIP_GRP2_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP2_BASE,
                 .pfn            = __phys_to_pfn(PERIP_GRP2_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_PERIP_GRP1_BASE,
+                .virtual        = (unsigned long)VA_PERIP_GRP1_BASE,
                 .pfn            = __phys_to_pfn(PERIP_GRP1_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
         }, {
-                .virtual        = VA_A9SM_AND_MPMC_BASE,
+                .virtual        = (unsigned long)VA_A9SM_AND_MPMC_BASE,
                 .pfn            = __phys_to_pfn(A9SM_AND_MPMC_BASE),
                 .length         = SZ_16M,
                 .type           = MT_DEVICE
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index b3226f80c985..5f3c03b61f8e 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -110,13 +110,6 @@ config TEGRA_DEBUG_UART_AUTO_SCRATCH
 
 endchoice
 
-config TEGRA_SYSTEM_DMA
-        bool "Enable system DMA driver for NVIDIA Tegra SoCs"
-        default y
-        help
-          Adds system DMA functionality for NVIDIA Tegra SoCs, used by
-          several Tegra device drivers
-
 config TEGRA_EMC_SCALING_ENABLE
         bool "Enable scaling the memory frequency"
 
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 56065acbd816..0974ace45558 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -18,7 +18,6 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index 643a37809a15..b5015d0f1912 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -28,7 +28,7 @@
 
 #include "apbio.h"
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
+#if defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
@@ -37,121 +37,6 @@ static DECLARE_COMPLETION(tegra_apb_wait);
 static u32 tegra_apb_readl_direct(unsigned long offset);
 static void tegra_apb_writel_direct(u32 value, unsigned long offset);
 
-#if defined(CONFIG_TEGRA_SYSTEM_DMA)
-static struct tegra_dma_channel *tegra_apb_dma;
-
-bool tegra_apb_init(void)
-{
-        struct tegra_dma_channel *ch;
-
-        mutex_lock(&tegra_apb_dma_lock);
-
-        /* Check to see if we raced to setup */
-        if (tegra_apb_dma)
-                goto out;
-
-        ch = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-                TEGRA_DMA_SHARED);
-
-        if (!ch)
-                goto out_fail;
-
-        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
-                &tegra_apb_bb_phys, GFP_KERNEL);
-        if (!tegra_apb_bb) {
-                pr_err("%s: can not allocate bounce buffer\n", __func__);
-                tegra_dma_free_channel(ch);
-                goto out_fail;
-        }
-
-        tegra_apb_dma = ch;
-out:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return true;
-
-out_fail:
-        mutex_unlock(&tegra_apb_dma_lock);
-        return false;
-}
-
-static void apb_dma_complete(struct tegra_dma_req *req)
-{
-        complete(&tegra_apb_wait);
-}
-
-static u32 tegra_apb_readl_using_dma(unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-
-        if (!tegra_apb_dma && !tegra_apb_init())
-                return tegra_apb_readl_direct(offset);
-
-        mutex_lock(&tegra_apb_dma_lock);
-        req.complete = apb_dma_complete;
-        req.to_memory = 1;
-        req.dest_addr = tegra_apb_bb_phys;
-        req.dest_bus_width = 32;
-        req.dest_wrap = 1;
-        req.source_addr = offset;
-        req.source_bus_width = 32;
-        req.source_wrap = 4;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-
-        INIT_COMPLETION(tegra_apb_wait);
-
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-
-        if (WARN(ret == 0, "apb read dma timed out")) {
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-                *(u32 *)tegra_apb_bb = 0;
-        }
-
-        mutex_unlock(&tegra_apb_dma_lock);
-        return *((u32 *)tegra_apb_bb);
-}
-
-static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
-{
-        struct tegra_dma_req req;
-        int ret;
-
-        if (!tegra_apb_dma && !tegra_apb_init()) {
-                tegra_apb_writel_direct(value, offset);
-                return;
-        }
-
-        mutex_lock(&tegra_apb_dma_lock);
-        *((u32 *)tegra_apb_bb) = value;
-        req.complete = apb_dma_complete;
-        req.to_memory = 0;
-        req.dest_addr = offset;
-        req.dest_wrap = 4;
-        req.dest_bus_width = 32;
-        req.source_addr = tegra_apb_bb_phys;
-        req.source_bus_width = 32;
-        req.source_wrap = 1;
-        req.req_sel = TEGRA_DMA_REQ_SEL_CNTR;
-        req.size = 4;
-
-        INIT_COMPLETION(tegra_apb_wait);
-
-        tegra_dma_enqueue_req(tegra_apb_dma, &req);
-
-        ret = wait_for_completion_timeout(&tegra_apb_wait,
-                msecs_to_jiffies(50));
-
-        if (WARN(ret == 0, "apb write dma timed out"))
-                tegra_dma_dequeue_req(tegra_apb_dma, &req);
-
-        mutex_unlock(&tegra_apb_dma_lock);
-}
-
-#else
 static struct dma_chan *tegra_apb_dma_chan;
 static struct dma_slave_config dma_sconfig;
 
@@ -279,7 +164,6 @@ static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
                 pr_err("error in writing offset 0x%08lx using dma\n", offset);
         mutex_unlock(&tegra_apb_dma_lock);
 }
-#endif
 #else
 #define tegra_apb_readl_using_dma tegra_apb_readl_direct
 #define tegra_apb_writel_using_dma tegra_apb_writel_direct
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
deleted file mode 100644
index 29c5114d607c..000000000000
--- a/arch/arm/mach-tegra/dma.c
+++ /dev/null
@@ -1,823 +0,0 @@
-/*
- * arch/arm/mach-tegra/dma.c
- *
- * System DMA driver for NVIDIA Tegra SoCs
- *
- * Copyright (c) 2008-2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/err.h>
-#include <linux/irq.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <mach/dma.h>
-#include <mach/irqs.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "apbio.h"
-
-#define APB_DMA_GEN                             0x000
-#define GEN_ENABLE                              (1<<31)
-
-#define APB_DMA_CNTRL                           0x010
-
-#define APB_DMA_IRQ_MASK                        0x01c
-
-#define APB_DMA_IRQ_MASK_SET                    0x020
-
-#define APB_DMA_CHAN_CSR                        0x000
-#define CSR_ENB                                 (1<<31)
-#define CSR_IE_EOC                              (1<<30)
-#define CSR_HOLD                                (1<<29)
-#define CSR_DIR                                 (1<<28)
-#define CSR_ONCE                                (1<<27)
-#define CSR_FLOW                                (1<<21)
-#define CSR_REQ_SEL_SHIFT                       16
-#define CSR_WCOUNT_SHIFT                        2
-#define CSR_WCOUNT_MASK                         0xFFFC
-
-#define APB_DMA_CHAN_STA                                0x004
-#define STA_BUSY                                (1<<31)
-#define STA_ISE_EOC                             (1<<30)
-#define STA_HALT                                (1<<29)
-#define STA_PING_PONG                           (1<<28)
-#define STA_COUNT_SHIFT                         2
-#define STA_COUNT_MASK                          0xFFFC
-
-#define APB_DMA_CHAN_AHB_PTR                            0x010
-
-#define APB_DMA_CHAN_AHB_SEQ                            0x014
-#define AHB_SEQ_INTR_ENB                        (1<<31)
-#define AHB_SEQ_BUS_WIDTH_SHIFT                 28
-#define AHB_SEQ_BUS_WIDTH_MASK                  (0x7<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_8                     (0<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_16                    (1<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_32                    (2<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_64                    (3<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_BUS_WIDTH_128                   (4<<AHB_SEQ_BUS_WIDTH_SHIFT)
-#define AHB_SEQ_DATA_SWAP                       (1<<27)
-#define AHB_SEQ_BURST_MASK                      (0x7<<24)
-#define AHB_SEQ_BURST_1                         (4<<24)
-#define AHB_SEQ_BURST_4                         (5<<24)
-#define AHB_SEQ_BURST_8                         (6<<24)
-#define AHB_SEQ_DBL_BUF                         (1<<19)
-#define AHB_SEQ_WRAP_SHIFT                      16
-#define AHB_SEQ_WRAP_MASK                       (0x7<<AHB_SEQ_WRAP_SHIFT)
-
-#define APB_DMA_CHAN_APB_PTR                            0x018
-
-#define APB_DMA_CHAN_APB_SEQ                            0x01c
-#define APB_SEQ_BUS_WIDTH_SHIFT                 28
-#define APB_SEQ_BUS_WIDTH_MASK                  (0x7<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_8                     (0<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_16                    (1<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_32                    (2<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_64                    (3<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_BUS_WIDTH_128                   (4<<APB_SEQ_BUS_WIDTH_SHIFT)
-#define APB_SEQ_DATA_SWAP                       (1<<27)
-#define APB_SEQ_WRAP_SHIFT                      16
-#define APB_SEQ_WRAP_MASK                       (0x7<<APB_SEQ_WRAP_SHIFT)
-
-#define TEGRA_SYSTEM_DMA_CH_NR                  16
-#define TEGRA_SYSTEM_DMA_AVP_CH_NUM             4
-#define TEGRA_SYSTEM_DMA_CH_MIN                 0
-#define TEGRA_SYSTEM_DMA_CH_MAX \
-        (TEGRA_SYSTEM_DMA_CH_NR - TEGRA_SYSTEM_DMA_AVP_CH_NUM - 1)
-
-#define NV_DMA_MAX_TRASFER_SIZE 0x10000
-
-static const unsigned int ahb_addr_wrap_table[8] = {
-        0, 32, 64, 128, 256, 512, 1024, 2048
-};
-
-static const unsigned int apb_addr_wrap_table[8] = {
-        0, 1, 2, 4, 8, 16, 32, 64
-};
-
-static const unsigned int bus_width_table[5] = {
-        8, 16, 32, 64, 128
-};
-
-#define TEGRA_DMA_NAME_SIZE 16
-struct tegra_dma_channel {
-        struct list_head        list;
-        int                     id;
-        spinlock_t              lock;
-        char                    name[TEGRA_DMA_NAME_SIZE];
-        void  __iomem           *addr;
-        int                     mode;
-        int                     irq;
-        int                     req_transfer_count;
-};
-
-#define  NV_DMA_MAX_CHANNELS  32
-
-static bool tegra_dma_initialized;
-static DEFINE_MUTEX(tegra_dma_lock);
-static DEFINE_SPINLOCK(enable_lock);
-
-static DECLARE_BITMAP(channel_usage, NV_DMA_MAX_CHANNELS);
-static struct tegra_dma_channel dma_channels[NV_DMA_MAX_CHANNELS];
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-static void tegra_dma_stop(struct tegra_dma_channel *ch);
-
-void tegra_dma_flush(struct tegra_dma_channel *ch)
-{
-}
-EXPORT_SYMBOL(tegra_dma_flush);
-
-void tegra_dma_dequeue(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-
-        if (tegra_dma_is_empty(ch))
-                return;
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-
-        tegra_dma_dequeue_req(ch, req);
-        return;
-}
-
-static void tegra_dma_stop(struct tegra_dma_channel *ch)
-{
-        u32 csr;
-        u32 status;
-
-        csr = readl(ch->addr + APB_DMA_CHAN_CSR);
-        csr &= ~CSR_IE_EOC;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        csr &= ~CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-}
-
-static int tegra_dma_cancel(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        while (!list_empty(&ch->list))
-                list_del(ch->list.next);
-
-        tegra_dma_stop(ch);
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return 0;
-}
-
-static unsigned int get_channel_status(struct tegra_dma_channel *ch,
-                        struct tegra_dma_req *req, bool is_stop_dma)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        unsigned int status;
-
-        if (is_stop_dma) {
-                /*
-                 * STOP the DMA and get the transfer count.
-                 * Getting the transfer count is tricky.
-                 *  - Globally disable DMA on all channels
-                 *  - Read the channel's status register to know the number
-                 *    of pending bytes to be transfered.
-                 *  - Stop the dma channel
-                 *  - Globally re-enable DMA to resume other transfers
-                 */
-                spin_lock(&enable_lock);
-                writel(0, addr + APB_DMA_GEN);
-                udelay(20);
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-                tegra_dma_stop(ch);
-                writel(GEN_ENABLE, addr + APB_DMA_GEN);
-                spin_unlock(&enable_lock);
-                if (status & STA_ISE_EOC) {
-                        pr_err("Got Dma Int here clearing");
-                        writel(status, ch->addr + APB_DMA_CHAN_STA);
-                }
-                req->status = TEGRA_DMA_REQ_ERROR_ABORTED;
-        } else {
-                status = readl(ch->addr + APB_DMA_CHAN_STA);
-        }
-        return status;
-}
-
-/* should be called with the channel lock held */
-static unsigned int dma_active_count(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req, unsigned int status)
-{
-        unsigned int to_transfer;
-        unsigned int req_transfer_count;
-        unsigned int bytes_transferred;
-
-        to_transfer = ((status & STA_COUNT_MASK) >> STA_COUNT_SHIFT) + 1;
-        req_transfer_count = ch->req_transfer_count + 1;
-        bytes_transferred = req_transfer_count;
-        if (status & STA_BUSY)
-                bytes_transferred -= to_transfer;
-        /*
-         * In continuous transfer mode, DMA only tracks the count of the
-         * half DMA buffer. So, if the DMA already finished half the DMA
-         * then add the half buffer to the completed count.
-         */
-        if (ch->mode & TEGRA_DMA_MODE_CONTINOUS) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL)
-                        bytes_transferred += req_transfer_count;
-                if (status & STA_ISE_EOC)
-                        bytes_transferred += req_transfer_count;
-        }
-        bytes_transferred *= 4;
-        return bytes_transferred;
-}
-
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned int status;
-        struct tegra_dma_req *req = NULL;
-        int found = 0;
-        unsigned long irq_flags;
-        int stop = 0;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-
-        if (list_entry(ch->list.next, struct tegra_dma_req, node) == _req)
-                stop = 1;
-
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        list_del(&req->node);
-                        found = 1;
-                        break;
-                }
-        }
-        if (!found) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return 0;
-        }
-
-        if (!stop)
-                goto skip_stop_dma;
-
-        status = get_channel_status(ch, req, true);
-        req->bytes_transferred = dma_active_count(ch, req, status);
-
-        if (!list_empty(&ch->list)) {
-                /* if the list is not empty, queue the next request */
-                struct tegra_dma_req *next_req;
-                next_req = list_entry(ch->list.next,
-                        typeof(*next_req), node);
-                tegra_dma_update_hw(ch, next_req);
-        }
-
-skip_stop_dma:
-        req->status = -TEGRA_DMA_REQ_ERROR_ABORTED;
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-        /* Callback should be called without any lock */
-        req->complete(req);
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_dequeue_req);
-
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch)
-{
-        unsigned long irq_flags;
-        bool is_empty;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list))
-                is_empty = true;
-        else
-                is_empty = false;
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return is_empty;
-}
-EXPORT_SYMBOL(tegra_dma_is_empty);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *_req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *req;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        list_for_each_entry(req, &ch->list, node) {
-                if (req == _req) {
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        return true;
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-        return false;
-}
-EXPORT_SYMBOL(tegra_dma_is_req_inflight);
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        unsigned long irq_flags;
-        struct tegra_dma_req *_req;
-        int start_dma = 0;
-
-        if (req->size > NV_DMA_MAX_TRASFER_SIZE ||
-                req->source_addr & 0x3 || req->dest_addr & 0x3) {
-                pr_err("Invalid DMA request for channel %d\n", ch->id);
-                return -EINVAL;
-        }
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-
-        list_for_each_entry(_req, &ch->list, node) {
-                if (req == _req) {
-                    spin_unlock_irqrestore(&ch->lock, irq_flags);
-                    return -EEXIST;
-                }
-        }
-
-        req->bytes_transferred = 0;
-        req->status = 0;
-        req->buffer_status = 0;
-        if (list_empty(&ch->list))
-                start_dma = 1;
-
-        list_add_tail(&req->node, &ch->list);
-
-        if (start_dma)
-                tegra_dma_update_hw(ch, req);
-
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-
-        return 0;
-}
-EXPORT_SYMBOL(tegra_dma_enqueue_req);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode)
-{
-        int channel;
-        struct tegra_dma_channel *ch = NULL;
-
-        if (!tegra_dma_initialized)
-                return NULL;
-
-        mutex_lock(&tegra_dma_lock);
-
-        /* first channel is the shared channel */
-        if (mode & TEGRA_DMA_SHARED) {
-                channel = TEGRA_SYSTEM_DMA_CH_MIN;
-        } else {
-                channel = find_first_zero_bit(channel_usage,
-                        ARRAY_SIZE(dma_channels));
-                if (channel >= ARRAY_SIZE(dma_channels))
-                        goto out;
-        }
-        __set_bit(channel, channel_usage);
-        ch = &dma_channels[channel];
-        ch->mode = mode;
-
-out:
-        mutex_unlock(&tegra_dma_lock);
-        return ch;
-}
-EXPORT_SYMBOL(tegra_dma_allocate_channel);
-
-void tegra_dma_free_channel(struct tegra_dma_channel *ch)
-{
-        if (ch->mode & TEGRA_DMA_SHARED)
-                return;
-        tegra_dma_cancel(ch);
-        mutex_lock(&tegra_dma_lock);
-        __clear_bit(ch->id, channel_usage);
-        mutex_unlock(&tegra_dma_lock);
-}
-EXPORT_SYMBOL(tegra_dma_free_channel);
-
-static void tegra_dma_update_hw_partial(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        u32 apb_ptr;
-        u32 ahb_ptr;
-
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-        } else {
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-        }
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-        return;
-}
-
-static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req)
-{
-        int ahb_addr_wrap;
-        int apb_addr_wrap;
-        int ahb_bus_width;
-        int apb_bus_width;
-        int index;
-
-        u32 ahb_seq;
-        u32 apb_seq;
-        u32 ahb_ptr;
-        u32 apb_ptr;
-        u32 csr;
-
-        csr = CSR_IE_EOC | CSR_FLOW;
-        ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
-        apb_seq = 0;
-
-        csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
-
-        /* One shot mode is always single buffered,
-         * continuous mode is always double buffered
-         * */
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT) {
-                csr |= CSR_ONCE;
-                ch->req_transfer_count = (req->size >> 2) - 1;
-        } else {
-                ahb_seq |= AHB_SEQ_DBL_BUF;
-
-                /* In double buffered mode, we set the size to half the
-                 * requested size and interrupt when half the buffer
-                 * is full */
-                ch->req_transfer_count = (req->size >> 3) - 1;
-        }
-
-        csr |= ch->req_transfer_count << CSR_WCOUNT_SHIFT;
-
-        if (req->to_memory) {
-                apb_ptr = req->source_addr;
-                ahb_ptr = req->dest_addr;
-
-                apb_addr_wrap = req->source_wrap;
-                ahb_addr_wrap = req->dest_wrap;
-                apb_bus_width = req->source_bus_width;
-                ahb_bus_width = req->dest_bus_width;
-
-        } else {
-                csr |= CSR_DIR;
-                apb_ptr = req->dest_addr;
-                ahb_ptr = req->source_addr;
-
-                apb_addr_wrap = req->dest_wrap;
-                ahb_addr_wrap = req->source_wrap;
-                apb_bus_width = req->dest_bus_width;
-                ahb_bus_width = req->source_bus_width;
-        }
-
-        apb_addr_wrap >>= 2;
-        ahb_addr_wrap >>= 2;
-
-        /* set address wrap for APB size */
-        index = 0;
-        do  {
-                if (apb_addr_wrap_table[index] == apb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(apb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(apb_addr_wrap_table));
-        apb_seq |= index << APB_SEQ_WRAP_SHIFT;
-
-        /* set address wrap for AHB size */
-        index = 0;
-        do  {
-                if (ahb_addr_wrap_table[index] == ahb_addr_wrap)
-                        break;
-                index++;
-        } while (index < ARRAY_SIZE(ahb_addr_wrap_table));
-        BUG_ON(index == ARRAY_SIZE(ahb_addr_wrap_table));
-        ahb_seq |= index << AHB_SEQ_WRAP_SHIFT;
-
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == ahb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        ahb_seq |= index << AHB_SEQ_BUS_WIDTH_SHIFT;
-
-        for (index = 0; index < ARRAY_SIZE(bus_width_table); index++) {
-                if (bus_width_table[index] == apb_bus_width)
-                        break;
-        }
-        BUG_ON(index == ARRAY_SIZE(bus_width_table));
-        apb_seq |= index << APB_SEQ_BUS_WIDTH_SHIFT;
-
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-        writel(apb_seq, ch->addr + APB_DMA_CHAN_APB_SEQ);
-        writel(apb_ptr, ch->addr + APB_DMA_CHAN_APB_PTR);
-        writel(ahb_seq, ch->addr + APB_DMA_CHAN_AHB_SEQ);
-        writel(ahb_ptr, ch->addr + APB_DMA_CHAN_AHB_PTR);
-
-        csr |= CSR_ENB;
-        writel(csr, ch->addr + APB_DMA_CHAN_CSR);
-
-        req->status = TEGRA_DMA_REQ_INFLIGHT;
-}
-
-static void handle_oneshot_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                int bytes_transferred;
-
-                bytes_transferred = ch->req_transfer_count;
-                bytes_transferred += 1;
-                bytes_transferred <<= 2;
-
-                list_del(&req->node);
-                req->bytes_transferred = bytes_transferred;
-                req->status = TEGRA_DMA_REQ_SUCCESS;
-
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                /* Callback should be called without any lock */
-                pr_debug("%s: transferred %d bytes\n", __func__,
-                        req->bytes_transferred);
-                req->complete(req);
-                spin_lock_irqsave(&ch->lock, irq_flags);
-        }
-
-        if (!list_empty(&ch->list)) {
-                req = list_entry(ch->list.next, typeof(*req), node);
-                /* the complete function we just called may have enqueued
-                   another req, in which case dma has already started */
-                if (req->status != TEGRA_DMA_REQ_INFLIGHT)
-                        tegra_dma_update_hw(ch, req);
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static void handle_continuous_dma(struct tegra_dma_channel *ch)
-{
-        struct tegra_dma_req *req;
-        unsigned long irq_flags;
-
-        spin_lock_irqsave(&ch->lock, irq_flags);
-        if (list_empty(&ch->list)) {
-                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                return;
-        }
-
-        req = list_entry(ch->list.next, typeof(*req), node);
-        if (req) {
-                if (req->buffer_status == TEGRA_DMA_REQ_BUF_STATUS_EMPTY) {
-                        bool is_dma_ping_complete;
-                        is_dma_ping_complete = (readl(ch->addr + APB_DMA_CHAN_STA)
-                                                & STA_PING_PONG) ? true : false;
-                        if (req->to_memory)
-                                is_dma_ping_complete = !is_dma_ping_complete;
-                        /* Out of sync - Release current buffer */
-                        if (!is_dma_ping_complete) {
-                                int bytes_transferred;
-
-                                bytes_transferred = ch->req_transfer_count;
-                                bytes_transferred += 1;
-                                bytes_transferred <<= 3;
-                                req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                                req->bytes_transferred = bytes_transferred;
-                                req->status = TEGRA_DMA_REQ_SUCCESS;
-                                tegra_dma_stop(ch);
-
-                                if (!list_is_last(&req->node, &ch->list)) {
-                                        struct tegra_dma_req *next_req;
-
-                                        next_req = list_entry(req->node.next,
-                                                typeof(*next_req), node);
-                                        tegra_dma_update_hw(ch, next_req);
-                                }
-
-                                list_del(&req->node);
-
-                                /* DMA lock is NOT held when callbak is called */
-                                spin_unlock_irqrestore(&ch->lock, irq_flags);
-                                req->complete(req);
-                                return;
-                        }
-                        /* Load the next request into the hardware, if available
-                         * */
-                        if (!list_is_last(&req->node, &ch->list)) {
-                                struct tegra_dma_req *next_req;
-
-                                next_req = list_entry(req->node.next,
-                                        typeof(*next_req), node);
-                                tegra_dma_update_hw_partial(ch, next_req);
-                        }
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        /* DMA lock is NOT held when callback is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        if (likely(req->threshold))
-                                req->threshold(req);
-                        return;
-
-                } else if (req->buffer_status ==
-                        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL) {
-                        /* Callback when the buffer is completely full (i.e on
-                         * the second  interrupt */
-                        int bytes_transferred;
-
-                        bytes_transferred = ch->req_transfer_count;
-                        bytes_transferred += 1;
-                        bytes_transferred <<= 3;
-
-                        req->buffer_status = TEGRA_DMA_REQ_BUF_STATUS_FULL;
-                        req->bytes_transferred = bytes_transferred;
-                        req->status = TEGRA_DMA_REQ_SUCCESS;
-                        list_del(&req->node);
-
-                        /* DMA lock is NOT held when callbak is called */
-                        spin_unlock_irqrestore(&ch->lock, irq_flags);
-                        req->complete(req);
-                        return;
-
-                } else {
-                        BUG();
-                }
-        }
-        spin_unlock_irqrestore(&ch->lock, irq_flags);
-}
-
-static irqreturn_t dma_isr(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-        unsigned long status;
-
-        status = readl(ch->addr + APB_DMA_CHAN_STA);
-        if (status & STA_ISE_EOC)
-                writel(status, ch->addr + APB_DMA_CHAN_STA);
-        else {
-                pr_warning("Got a spurious ISR for DMA channel %d\n", ch->id);
-                return IRQ_HANDLED;
-        }
-        return IRQ_WAKE_THREAD;
-}
-
-static irqreturn_t dma_thread_fn(int irq, void *data)
-{
-        struct tegra_dma_channel *ch = data;
-
-        if (ch->mode & TEGRA_DMA_MODE_ONESHOT)
-                handle_oneshot_dma(ch);
-        else
-                handle_continuous_dma(ch);
-
-
-        return IRQ_HANDLED;
-}
-
-int __init tegra_dma_init(void)
-{
-        int ret = 0;
-        int i;
-        unsigned int irq;
-        void __iomem *addr;
-        struct clk *c;
-
-        bitmap_fill(channel_usage, NV_DMA_MAX_CHANNELS);
-
-        c = clk_get_sys("tegra-apbdma", NULL);
-        if (IS_ERR(c)) {
-                pr_err("Unable to get clock for APB DMA\n");
-                ret = PTR_ERR(c);
-                goto fail;
-        }
-        ret = clk_prepare_enable(c);
-        if (ret != 0) {
-                pr_err("Unable to enable clock for APB DMA\n");
-                goto fail;
-        }
-
-        addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        writel(GEN_ENABLE, addr + APB_DMA_GEN);
-        writel(0, addr + APB_DMA_CNTRL);
-        writel(0xFFFFFFFFul >> (31 - TEGRA_SYSTEM_DMA_CH_MAX),
-               addr + APB_DMA_IRQ_MASK_SET);
-
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-
-                ch->id = i;
-                snprintf(ch->name, TEGRA_DMA_NAME_SIZE, "dma_channel_%d", i);
-
-                ch->addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                        TEGRA_APB_DMA_CH0_SIZE * i);
-
-                spin_lock_init(&ch->lock);
-                INIT_LIST_HEAD(&ch->list);
-
-                irq = INT_APB_DMA_CH0 + i;
-                ret = request_threaded_irq(irq, dma_isr, dma_thread_fn, 0,
-                        dma_channels[i].name, ch);
-                if (ret) {
-                        pr_err("Failed to register IRQ %d for DMA %d\n",
-                                irq, i);
-                        goto fail;
-                }
-                ch->irq = irq;
-
-                __clear_bit(i, channel_usage);
-        }
-        /* mark the shared channel allocated */
-        __set_bit(TEGRA_SYSTEM_DMA_CH_MIN, channel_usage);
-
-        tegra_dma_initialized = true;
-
-        return 0;
-fail:
-        writel(0, addr + APB_DMA_GEN);
-        for (i = TEGRA_SYSTEM_DMA_CH_MIN; i <= TEGRA_SYSTEM_DMA_CH_MAX; i++) {
-                struct tegra_dma_channel *ch = &dma_channels[i];
-                if (ch->irq)
-                        free_irq(ch->irq, ch);
-        }
-        return ret;
-}
-postcore_initcall(tegra_dma_init);
-
-#ifdef CONFIG_PM
-static u32 apb_dma[5*TEGRA_SYSTEM_DMA_CH_NR + 3];
-
-void tegra_dma_suspend(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-
-        *ctx++ = readl(addr + APB_DMA_GEN);
-        *ctx++ = readl(addr + APB_DMA_CNTRL);
-        *ctx++ = readl(addr + APB_DMA_IRQ_MASK);
-
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-
-                *ctx++ = readl(addr + APB_DMA_CHAN_CSR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_AHB_SEQ);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_PTR);
-                *ctx++ = readl(addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-
-void tegra_dma_resume(void)
-{
-        void __iomem *addr = IO_ADDRESS(TEGRA_APB_DMA_BASE);
-        u32 *ctx = apb_dma;
-        int i;
-
-        writel(*ctx++, addr + APB_DMA_GEN);
-        writel(*ctx++, addr + APB_DMA_CNTRL);
-        writel(*ctx++, addr + APB_DMA_IRQ_MASK);
-
-        for (i = 0; i < TEGRA_SYSTEM_DMA_CH_NR; i++) {
-                addr = IO_ADDRESS(TEGRA_APB_DMA_CH0_BASE +
-                                  TEGRA_APB_DMA_CH0_SIZE * i);
-
-                writel(*ctx++, addr + APB_DMA_CHAN_CSR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_AHB_SEQ);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_PTR);
-                writel(*ctx++, addr + APB_DMA_CHAN_APB_SEQ);
-        }
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/dma.h b/arch/arm/mach-tegra/include/mach/dma.h
index 9077092812c0..3081cc6dda3b 100644
--- a/arch/arm/mach-tegra/include/mach/dma.h
+++ b/arch/arm/mach-tegra/include/mach/dma.h
@@ -51,101 +51,4 @@
 #define TEGRA_DMA_REQ_SEL_OWR                   25
 #define TEGRA_DMA_REQ_SEL_INVALID               31
 
-struct tegra_dma_req;
-struct tegra_dma_channel;
-
-enum tegra_dma_mode {
-        TEGRA_DMA_SHARED = 1,
-        TEGRA_DMA_MODE_CONTINOUS = 2,
-        TEGRA_DMA_MODE_ONESHOT = 4,
-};
-
-enum tegra_dma_req_error {
-        TEGRA_DMA_REQ_SUCCESS = 0,
-        TEGRA_DMA_REQ_ERROR_ABORTED,
-        TEGRA_DMA_REQ_INFLIGHT,
-};
-
-enum tegra_dma_req_buff_status {
-        TEGRA_DMA_REQ_BUF_STATUS_EMPTY = 0,
-        TEGRA_DMA_REQ_BUF_STATUS_HALF_FULL,
-        TEGRA_DMA_REQ_BUF_STATUS_FULL,
-};
-
-struct tegra_dma_req {
-        struct list_head node;
-        unsigned int modid;
-        int instance;
-
-        /* Called when the req is complete and from the DMA ISR context.
-         * When this is called the req structure is no longer queued by
-         * the DMA channel.
-         *
-         * State of the DMA depends on the number of req it has. If there are
-         * no DMA requests queued up, then it will STOP the DMA. It there are
-         * more requests in the DMA, then it will queue the next request.
-         */
-        void (*complete)(struct tegra_dma_req *req);
-
-        /*  This is a called from the DMA ISR context when the DMA is still in
-         *  progress and is actively filling same buffer.
-         *
-         *  In case of continuous mode receive, this threshold is 1/2 the buffer
-         *  size. In other cases, this will not even be called as there is no
-         *  hardware support for it.
-         *
-         * In the case of continuous mode receive, if there is next req already
-         * queued, DMA programs the HW to use that req when this req is
-         * completed. If there is no "next req" queued, then DMA ISR doesn't do
-         * anything before calling this callback.
-         *
-         *      This is mainly used by the cases, where the clients has queued
-         *      only one req and want to get some sort of DMA threshold
-         *      callback to program the next buffer.
-         *
-         */
-        void (*threshold)(struct tegra_dma_req *req);
-
-        /* 1 to copy to memory.
-         * 0 to copy from the memory to device FIFO */
-        int to_memory;
-
-        void *virt_addr;
-
-        unsigned long source_addr;
-        unsigned long dest_addr;
-        unsigned long dest_wrap;
-        unsigned long source_wrap;
-        unsigned long source_bus_width;
-        unsigned long dest_bus_width;
-        unsigned long req_sel;
-        unsigned int size;
-
-        /* Updated by the DMA driver on the conpletion of the request. */
-        int bytes_transferred;
-        int status;
-
-        /* DMA completion tracking information */
-        int buffer_status;
-
-        /* Client specific data */
-        void *dev;
-};
-
-int tegra_dma_enqueue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-int tegra_dma_dequeue_req(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-void tegra_dma_dequeue(struct tegra_dma_channel *ch);
-void tegra_dma_flush(struct tegra_dma_channel *ch);
-
-bool tegra_dma_is_req_inflight(struct tegra_dma_channel *ch,
-        struct tegra_dma_req *req);
-bool tegra_dma_is_empty(struct tegra_dma_channel *ch);
-
-struct tegra_dma_channel *tegra_dma_allocate_channel(int mode);
-void tegra_dma_free_channel(struct tegra_dma_channel *ch);
-
-int __init tegra_dma_init(void);
-
 #endif
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 119bc52ab93e..4e07eec1270d 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -63,10 +63,11 @@ static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
         pid = task_pid_nr(thread->task) << ASID_BITS;
         asm volatile(
         "       mrc     p15, 0, %0, c13, c0, 1\n"
-        "       bfi     %1, %0, #0, %2\n"
-        "       mcr     p15, 0, %1, c13, c0, 1\n"
+        "       and     %0, %0, %2\n"
+        "       orr     %0, %0, %1\n"
+        "       mcr     p15, 0, %0, c13, c0, 1\n"
         : "=r" (contextidr), "+r" (pid)
-        : "I" (ASID_BITS));
+        : "I" (~ASID_MASK));
         isb();
 
         return NOTIFY_OK;
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 051204fc4617..e59c4ab71bcb 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -489,7 +489,7 @@ static bool __in_atomic_pool(void *start, size_t size)
         void *pool_start = pool->vaddr;
         void *pool_end = pool->vaddr + pool->size;
 
-        if (start < pool_start || start > pool_end)
+        if (start < pool_start || start >= pool_end)
                 return false;
 
         if (end <= pool_end)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index a7a9e41fa2c2..18144e6a3115 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -990,8 +990,8 @@ void __init sanity_check_meminfo(void)
                  * Check whether this memory bank would partially overlap
                  * the vmalloc area.
                  */
-                if (__va(bank->start + bank->size) > vmalloc_min ||
-                    __va(bank->start + bank->size) < __va(bank->start)) {
+                if (__va(bank->start + bank->size - 1) >= vmalloc_min ||
+                    __va(bank->start + bank->size - 1) <= __va(bank->start)) {
                         unsigned long newsize = vmalloc_min - __va(bank->start);
                         printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
                                "to -%.8llx (vmalloc region overlap).\n",
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index dbced61d9fda..ee9b1f9215df 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -76,7 +76,7 @@
 #define MX31_RTIC_BASE_ADDR                     (MX31_AIPS2_BASE_ADDR + 0xec000)
 
 #define MX31_ROMP_BASE_ADDR             0x60000000
-#define MX31_ROMP_BASE_ADDR_VIRT        0xfc500000
+#define MX31_ROMP_BASE_ADDR_VIRT        IOMEM(0xfc500000)
 #define MX31_ROMP_SIZE                  SZ_1M
 
 #define MX31_AVIC_BASE_ADDR             0x68000000
@@ -92,11 +92,11 @@
 #define MX31_CS3_BASE_ADDR              0xb2000000
 
 #define MX31_CS4_BASE_ADDR              0xb4000000
-#define MX31_CS4_BASE_ADDR_VIRT         0xf6000000
+#define MX31_CS4_BASE_ADDR_VIRT         IOMEM(0xf6000000)
 #define MX31_CS4_SIZE                   SZ_32M
 
 #define MX31_CS5_BASE_ADDR              0xb6000000
-#define MX31_CS5_BASE_ADDR_VIRT         0xf8000000
+#define MX31_CS5_BASE_ADDR_VIRT         IOMEM(0xf8000000)
 #define MX31_CS5_SIZE                   SZ_32M
 
 #define MX31_X_MEMC_BASE_ADDR           0xb8000000
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index d861aa73299d..28acb383e7df 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -67,6 +67,7 @@
 
 static unsigned long omap_sram_start;
 static void __iomem *omap_sram_base;
+static unsigned long omap_sram_skip;
 static unsigned long omap_sram_size;
 static void __iomem *omap_sram_ceil;
 
@@ -105,6 +106,7 @@ static int is_sram_locked(void)
  */
 static void __init omap_detect_sram(void)
 {
+        omap_sram_skip = SRAM_BOOTLOADER_SZ;
         if (cpu_class_is_omap2()) {
                 if (is_sram_locked()) {
                         if (cpu_is_omap34xx()) {
@@ -112,6 +114,7 @@ static void __init omap_detect_sram(void)
                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
                                         omap_sram_size = 0x7000; /* 28K */
+                                        omap_sram_skip += SZ_16K;
                                 } else {
                                         omap_sram_size = 0x8000; /* 32K */
                                 }
@@ -174,8 +177,10 @@ static void __init omap_map_sram(void)
                 return;
 
 #ifdef CONFIG_OMAP4_ERRATA_I688
+        if (cpu_is_omap44xx()) {
                 omap_sram_start += PAGE_SIZE;
                 omap_sram_size -= SZ_16K;
+        }
 #endif
         if (cpu_is_omap34xx()) {
                 /*
@@ -202,8 +207,8 @@ static void __init omap_map_sram(void)
          * Looks like we need to preserve some bootloader code at the
          * beginning of SRAM for jumping to flash for reboot to work...
          */
-        memset_io(omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
-                  omap_sram_size - SRAM_BOOTLOADER_SZ);
+        memset_io(omap_sram_base + omap_sram_skip, 0,
+                  omap_sram_size - omap_sram_skip);
 }
 
 /*
@@ -217,7 +222,7 @@ void *omap_sram_push_address(unsigned long size)
 {
         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 
-        available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
+        available = omap_sram_ceil - (omap_sram_base + omap_sram_skip);
 
         if (size > available) {
                 pr_err("Not enough space in SRAM\n");
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h
index bab139201761..d1ecef0e38e0 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-fns.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h
@@ -1,98 +1 @@
-/* arch/arm/mach-s3c2410/include/mach/gpio-fns.h
- *
- * Copyright (c) 2003-2009 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - hardware
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __MACH_GPIO_FNS_H
-#define __MACH_GPIO_FNS_H __FILE__
-
-/* These functions are in the to-be-removed category and it is strongly
- * encouraged not to use these in new code. They will be marked deprecated
- * very soon.
- *
- * Most of the functionality can be either replaced by the gpiocfg calls
- * for the s3c platform or by the generic GPIOlib API.
- *
- * As of 2.6.35-rc, these will be removed, with the few drivers using them
- * either replaced or given a wrapper until the calls can be removed.
-*/
-
 #include <plat/gpio-cfg.h>
-
-static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg)
-{
-        /* 1:1 mapping between cfgpin and setcfg calls at the moment */
-        s3c_gpio_cfgpin(pin, cfg);
-}
-
-/* external functions for GPIO support
- *
- * These allow various different clients to access the same GPIO
- * registers without conflicting. If your driver only owns the entire
- * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
-*/
-
-extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
-
-/* s3c2410_gpio_getirq
- *
- * turn the given pin number into the corresponding IRQ number
- *
- * returns:
- *      < 0 = no interrupt for this pin
- *      >=0 = interrupt number for the pin
-*/
-
-extern int s3c2410_gpio_getirq(unsigned int pin);
-
-/* s3c2410_gpio_irqfilter
- *
- * set the irq filtering on the given pin
- *
- * on = 0 => disable filtering
- *      1 => enable filtering
- *
- * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
- *          width of filter (0 through 63)
- *
- *
-*/
-
-extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
-                                  unsigned int config);
-
-/* s3c2410_gpio_pullup
- *
- * This call should be replaced with s3c_gpio_setpull().
- *
- * As a note, there is currently no distinction between pull-up and pull-down
- * in the s3c24xx series devices with only an on/off configuration.
- */
-
-/* s3c2410_gpio_pullup
- *
- * configure the pull-up control on the given pin
- *
- * to = 1 => disable the pull-up
- *      0 => enable the pull-up
- *
- * eg;
- *
- *   s3c2410_gpio_pullup(S3C2410_GPB(0), 0);
- *   s3c2410_gpio_pullup(S3C2410_GPE(8), 0);
-*/
-
-extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
-
-extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
-
-extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
-
-#endif /* __MACH_GPIO_FNS_H */
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index f9431fe5b06e..23557d30e44c 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -24,7 +24,7 @@
 
 #include <asm/mach/irq.h>
 
-#define GPIO_BASE(chip)         (((unsigned long)(chip)->base) & 0xFFFFF000u)
+#define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET              0x700
 #define MASK_OFFSET             0x900
@@ -153,7 +153,7 @@ static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip)
         bank->chips[group - bank->start] = chip;
 
         gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
-                                    (void __iomem *)GPIO_BASE(chip),
+                                    GPIO_BASE(chip),
                                     handle_level_irq);
         if (!gc)
                 return -ENOMEM;
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index f34861920634..c7092e6057c5 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -38,6 +38,7 @@ config BLACKFIN
         select GENERIC_ATOMIC64
         select GENERIC_IRQ_PROBE
         select IRQ_PER_CPU if SMP
+        select USE_GENERIC_SMP_HELPERS if SMP
         select HAVE_NMI_WATCHDOG if NMI_WATCHDOG
         select GENERIC_SMP_IDLE_THREAD
         select ARCH_USES_GETTIMEOFFSET if !GENERIC_CLOCKEVENTS
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index d3d7e64ca96d..66cf00095b84 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -20,7 +20,6 @@ endif
 KBUILD_AFLAGS           += $(call cc-option,-mno-fdpic)
 KBUILD_CFLAGS_MODULE    += -mlong-calls
 LDFLAGS                 += -m elf32bfin
-KALLSYMS         += --symbol-prefix=_
 
 KBUILD_DEFCONFIG := BF537-STAMP_defconfig
 
diff --git a/arch/blackfin/include/asm/smp.h b/arch/blackfin/include/asm/smp.h
index dc3d144b4bb5..9631598dcc5d 100644
--- a/arch/blackfin/include/asm/smp.h
+++ b/arch/blackfin/include/asm/smp.h
@@ -18,6 +18,8 @@
 #define raw_smp_processor_id()  blackfin_core_id()
 
 extern void bfin_relocate_coreb_l1_mem(void);
+extern void arch_send_call_function_single_ipi(int cpu);
+extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 
 #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
 asmlinkage void blackfin_icache_flush_range_l1(unsigned long *ptr);
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 00bbe672b3b3..a40151306b77 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -48,10 +48,13 @@ unsigned long blackfin_iflush_l1_entry[NR_CPUS];
 
 struct blackfin_initial_pda __cpuinitdata initial_pda_coreb;
 
-#define BFIN_IPI_TIMER        0
-#define BFIN_IPI_RESCHEDULE   1
-#define BFIN_IPI_CALL_FUNC    2
-#define BFIN_IPI_CPU_STOP     3
+enum ipi_message_type {
+        BFIN_IPI_TIMER,
+        BFIN_IPI_RESCHEDULE,
+        BFIN_IPI_CALL_FUNC,
+        BFIN_IPI_CALL_FUNC_SINGLE,
+        BFIN_IPI_CPU_STOP,
+};
 
 struct blackfin_flush_data {
         unsigned long start;
@@ -60,35 +63,20 @@ struct blackfin_flush_data {
 
 void *secondary_stack;
 
-
-struct smp_call_struct {
-        void (*func)(void *info);
-        void *info;
-        int wait;
-        cpumask_t *waitmask;
-};
-
 static struct blackfin_flush_data smp_flush_data;
 
 static DEFINE_SPINLOCK(stop_lock);
 
-struct ipi_message {
-        unsigned long type;
-        struct smp_call_struct call_struct;
-};
-
 /* A magic number - stress test shows this is safe for common cases */
 #define BFIN_IPI_MSGQ_LEN 5
 
 /* Simple FIFO buffer, overflow leads to panic */
-struct ipi_message_queue {
-        spinlock_t lock;
+struct ipi_data {
         unsigned long count;
-        unsigned long head; /* head of the queue */
-        struct ipi_message ipi_message[BFIN_IPI_MSGQ_LEN];
+        unsigned long bits;
 };
 
-static DEFINE_PER_CPU(struct ipi_message_queue, ipi_msg_queue);
+static DEFINE_PER_CPU(struct ipi_data, bfin_ipi);
 
 static void ipi_cpu_stop(unsigned int cpu)
 {
@@ -129,28 +117,6 @@ static void ipi_flush_icache(void *info)
         blackfin_icache_flush_range(fdata->start, fdata->end);
 }
 
-static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
-{
-        int wait;
-        void (*func)(void *info);
-        void *info;
-        func = msg->call_struct.func;
-        info = msg->call_struct.info;
-        wait = msg->call_struct.wait;
-        func(info);
-        if (wait) {
-#ifdef __ARCH_SYNC_CORE_DCACHE
-                /*
-                 * 'wait' usually means synchronization between CPUs.
-                 * Invalidate D cache in case shared data was changed
-                 * by func() to ensure cache coherence.
-                 */
-                resync_core_dcache();
-#endif
-                cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
-        }
-}
-
 /* Use IRQ_SUPPLE_0 to request reschedule.
  * When returning from interrupt to user space,
  * there is chance to reschedule */
@@ -172,152 +138,95 @@ void ipi_timer(void)
 
 static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
 {
-        struct ipi_message *msg;
-        struct ipi_message_queue *msg_queue;
+        struct ipi_data *bfin_ipi_data;
         unsigned int cpu = smp_processor_id();
-        unsigned long flags;
+        unsigned long pending;
+        unsigned long msg;
 
         platform_clear_ipi(cpu, IRQ_SUPPLE_1);
 
-        msg_queue = &__get_cpu_var(ipi_msg_queue);
-
-        spin_lock_irqsave(&msg_queue->lock, flags);
-
-        while (msg_queue->count) {
-                msg = &msg_queue->ipi_message[msg_queue->head];
-                switch (msg->type) {
-                case BFIN_IPI_TIMER:
-                        ipi_timer();
-                        break;
-                case BFIN_IPI_RESCHEDULE:
-                        scheduler_ipi();
-                        break;
-                case BFIN_IPI_CALL_FUNC:
-                        ipi_call_function(cpu, msg);
-                        break;
-                case BFIN_IPI_CPU_STOP:
-                        ipi_cpu_stop(cpu);
-                        break;
-                default:
-                        printk(KERN_CRIT "CPU%u: Unknown IPI message 0x%lx\n",
-                               cpu, msg->type);
-                        break;
-                }
-                msg_queue->head++;
-                msg_queue->head %= BFIN_IPI_MSGQ_LEN;
-                msg_queue->count--;
+        bfin_ipi_data = &__get_cpu_var(bfin_ipi);
+
+        while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) {
+                msg = 0;
+                do {
+                        msg = find_next_bit(&pending, BITS_PER_LONG, msg + 1);
+                        switch (msg) {
+                        case BFIN_IPI_TIMER:
+                                ipi_timer();
+                                break;
+                        case BFIN_IPI_RESCHEDULE:
+                                scheduler_ipi();
+                                break;
+                        case BFIN_IPI_CALL_FUNC:
+                                generic_smp_call_function_interrupt();
+                                break;
+
+                        case BFIN_IPI_CALL_FUNC_SINGLE:
+                                generic_smp_call_function_single_interrupt();
+                                break;
+
+                        case BFIN_IPI_CPU_STOP:
+                                ipi_cpu_stop(cpu);
+                                break;
+                        }
+                } while (msg < BITS_PER_LONG);
+
+                smp_mb();
         }
-        spin_unlock_irqrestore(&msg_queue->lock, flags);
         return IRQ_HANDLED;
 }
 
-static void ipi_queue_init(void)
+static void bfin_ipi_init(void)
 {
         unsigned int cpu;
-        struct ipi_message_queue *msg_queue;
+        struct ipi_data *bfin_ipi_data;
         for_each_possible_cpu(cpu) {
-                msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                spin_lock_init(&msg_queue->lock);
-                msg_queue->count = 0;
-                msg_queue->head = 0;
+                bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
+                bfin_ipi_data->bits = 0;
+                bfin_ipi_data->count = 0;
         }
 }
 
-static inline void smp_send_message(cpumask_t callmap, unsigned long type,
-                                        void (*func) (void *info), void *info, int wait)
+void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
 {
         unsigned int cpu;
-        struct ipi_message_queue *msg_queue;
-        struct ipi_message *msg;
-        unsigned long flags, next_msg;
-        cpumask_t waitmask; /* waitmask is shared by all cpus */
-
-        cpumask_copy(&waitmask, &callmap);
-        for_each_cpu(cpu, &callmap) {
-                msg_queue = &per_cpu(ipi_msg_queue, cpu);
-                spin_lock_irqsave(&msg_queue->lock, flags);
-                if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
-                        next_msg = (msg_queue->head + msg_queue->count)
-                                        % BFIN_IPI_MSGQ_LEN;
-                        msg = &msg_queue->ipi_message[next_msg];
-                        msg->type = type;
-                        if (type == BFIN_IPI_CALL_FUNC) {
-                                msg->call_struct.func = func;
-                                msg->call_struct.info = info;
-                                msg->call_struct.wait = wait;
-                                msg->call_struct.waitmask = &waitmask;
-                        }
-                        msg_queue->count++;
-                } else
-                        panic("IPI message queue overflow\n");
-                spin_unlock_irqrestore(&msg_queue->lock, flags);
+        struct ipi_data *bfin_ipi_data;
+        unsigned long flags;
+
+        local_irq_save(flags);
+
+        for_each_cpu(cpu, cpumask) {
+                bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
+                smp_mb();
+                set_bit(msg, &bfin_ipi_data->bits);
+                bfin_ipi_data->count++;
                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_1);
         }
 
-        if (wait) {
-                while (!cpumask_empty(&waitmask))
-                        blackfin_dcache_invalidate_range(
-                                (unsigned long)(&waitmask),
-                                (unsigned long)(&waitmask));
-#ifdef __ARCH_SYNC_CORE_DCACHE
-                /*
-                 * Invalidate D cache in case shared data was changed by
-                 * other processors to ensure cache coherence.
-                 */
-                resync_core_dcache();
-#endif
-        }
+        local_irq_restore(flags);
 }
 
-int smp_call_function(void (*func)(void *info), void *info, int wait)
+void arch_send_call_function_single_ipi(int cpu)
 {
-        cpumask_t callmap;
-
-        preempt_disable();
-        cpumask_copy(&callmap, cpu_online_mask);
-        cpumask_clear_cpu(smp_processor_id(), &callmap);
-        if (!cpumask_empty(&callmap))
-                smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
-
-        preempt_enable();
-
-        return 0;
+        send_ipi(cpumask_of(cpu), BFIN_IPI_CALL_FUNC_SINGLE);
 }
-EXPORT_SYMBOL_GPL(smp_call_function);
 
-int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
-                                int wait)
+void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
-        unsigned int cpu = cpuid;
-        cpumask_t callmap;
-
-        if (cpu_is_offline(cpu))
-                return 0;
-        cpumask_clear(&callmap);
-        cpumask_set_cpu(cpu, &callmap);
-
-        smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
-
-        return 0;
+        send_ipi(mask, BFIN_IPI_CALL_FUNC);
 }
-EXPORT_SYMBOL_GPL(smp_call_function_single);
 
 void smp_send_reschedule(int cpu)
 {
-        cpumask_t callmap;
-        /* simply trigger an ipi */
-
-        cpumask_clear(&callmap);
-        cpumask_set_cpu(cpu, &callmap);
-
-        smp_send_message(callmap, BFIN_IPI_RESCHEDULE, NULL, NULL, 0);
+        send_ipi(cpumask_of(cpu), BFIN_IPI_RESCHEDULE);
 
         return;
 }
 
 void smp_send_msg(const struct cpumask *mask, unsigned long type)
 {
-        smp_send_message(*mask, type, NULL, NULL, 0);
+        send_ipi(mask, type);
 }
 
 void smp_timer_broadcast(const struct cpumask *mask)
@@ -333,7 +242,7 @@ void smp_send_stop(void)
         cpumask_copy(&callmap, cpu_online_mask);
         cpumask_clear_cpu(smp_processor_id(), &callmap);
         if (!cpumask_empty(&callmap))
-                smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
+                send_ipi(&callmap, BFIN_IPI_CPU_STOP);
 
         preempt_enable();
 
@@ -436,7 +345,7 @@ void __init smp_prepare_boot_cpu(void)
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         platform_prepare_cpus(max_cpus);
-        ipi_queue_init();
+        bfin_ipi_init();
         platform_request_ipi(IRQ_SUPPLE_0, ipi_handler_int0);
         platform_request_ipi(IRQ_SUPPLE_1, ipi_handler_int1);
 }
diff --git a/arch/s390/oprofile/init.c b/arch/s390/oprofile/init.c
index a1e9d69a9c90..584b93674ea4 100644
--- a/arch/s390/oprofile/init.c
+++ b/arch/s390/oprofile/init.c
@@ -169,7 +169,7 @@ static ssize_t hw_interval_write(struct file *file, char const __user *buf,
         if (*offset)
                 return -EINVAL;
         retval = oprofilefs_ulong_from_user(&val, buf, count);
-        if (retval)
+        if (retval <= 0)
                 return retval;
         if (val < oprofile_min_interval)
                 oprofile_hw_interval = oprofile_min_interval;
@@ -212,7 +212,7 @@ static ssize_t hwsampler_zero_write(struct file *file, char const __user *buf,
                 return -EINVAL;
 
         retval = oprofilefs_ulong_from_user(&val, buf, count);
-        if (retval)
+        if (retval <= 0)
                 return retval;
         if (val != 0)
                 return -EINVAL;
@@ -243,7 +243,7 @@ static ssize_t hwsampler_kernel_write(struct file *file, char const __user *buf,
                 return -EINVAL;
 
         retval = oprofilefs_ulong_from_user(&val, buf, count);
-        if (retval)
+        if (retval <= 0)
                 return retval;
 
         if (val != 0 && val != 1)
@@ -278,7 +278,7 @@ static ssize_t hwsampler_user_write(struct file *file, char const __user *buf,
                 return -EINVAL;
 
         retval = oprofilefs_ulong_from_user(&val, buf, count);
-        if (retval)
+        if (retval <= 0)
                 return retval;
 
         if (val != 0 && val != 1)
@@ -317,7 +317,7 @@ static ssize_t timer_enabled_write(struct file *file, char const __user *buf,
                 return -EINVAL;
 
         retval = oprofilefs_ulong_from_user(&val, buf, count);
-        if (retval)
+        if (retval <= 0)
                 return retval;
 
         if (val != 0 && val != 1)
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e03e79..0d3d63afa76a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
                 break;
 
         case 28: /* Atom */
+        case 54: /* Cedariew */
                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
                        sizeof(hw_cache_event_ids));
 
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b4265fcd2..da02e9cc3754 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
          * to have an operational LBR which can freeze
          * on PMU interrupt
          */
-        if (boot_cpu_data.x86_mask < 10) {
+        if (boot_cpu_data.x86_model == 28
+            && boot_cpu_data.x86_mask < 10) {
                 pr_cont("LBR disabled due to erratum");
                 return;
         }
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 4873e62db6a1..9e5bcf1e2376 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -225,6 +225,9 @@ static ssize_t microcode_write(struct file *file, const char __user *buf,
         if (do_microcode_update(buf, len) == 0)
                 ret = (ssize_t)len;
 
+        if (ret > 0)
+                perf_check_microcode();
+
         mutex_unlock(&microcode_mutex);
         put_online_cpus();
 
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index e498b18f010c..9fc9aa7ac703 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -318,7 +318,7 @@ static void pic_ioport_write(void *opaque, u32 addr, u32 val)
                 if (val & 0x10) {
                         u8 edge_irr = s->irr & ~s->elcr;
                         int i;
-                        bool found;
+                        bool found = false;
                         struct kvm_vcpu *vcpu;
 
                         s->init4 = val & 1;
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index c00f03de1b79..b1eb202ee76a 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -3619,6 +3619,7 @@ static void seg_setup(int seg)
 
 static int alloc_apic_access_page(struct kvm *kvm)
 {
+        struct page *page;
         struct kvm_userspace_memory_region kvm_userspace_mem;
         int r = 0;
 
@@ -3633,7 +3634,13 @@ static int alloc_apic_access_page(struct kvm *kvm)
         if (r)
                 goto out;
 
-        kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
+        page = gfn_to_page(kvm, 0xfee00);
+        if (is_error_page(page)) {
+                r = -EFAULT;
+                goto out;
+        }
+
+        kvm->arch.apic_access_page = page;
 out:
         mutex_unlock(&kvm->slots_lock);
         return r;
@@ -3641,6 +3648,7 @@ out:
 
 static int alloc_identity_pagetable(struct kvm *kvm)
 {
+        struct page *page;
         struct kvm_userspace_memory_region kvm_userspace_mem;
         int r = 0;
 
@@ -3656,8 +3664,13 @@ static int alloc_identity_pagetable(struct kvm *kvm)
         if (r)
                 goto out;
 
-        kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
-                        kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
+        page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
+        if (is_error_page(page)) {
+                r = -EFAULT;
+                goto out;
+        }
+
+        kvm->arch.ept_identity_pagetable = page;
 out:
         mutex_unlock(&kvm->slots_lock);
         return r;
@@ -6575,7 +6588,7 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
         /* Exposing INVPCID only when PCID is exposed */
         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
         if (vmx_invpcid_supported() &&
-            best && (best->ecx & bit(X86_FEATURE_INVPCID)) &&
+            best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
             guest_cpuid_has_pcid(vcpu)) {
                 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
@@ -6585,7 +6598,7 @@ static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
                              exec_control);
                 if (best)
-                        best->ecx &= ~bit(X86_FEATURE_INVPCID);
+                        best->ebx &= ~bit(X86_FEATURE_INVPCID);
         }
 }
 
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 148ed666e311..2966c847d489 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -5113,17 +5113,20 @@ static void post_kvm_run_save(struct kvm_vcpu *vcpu)
                         !kvm_event_needs_reinjection(vcpu);
 }
 
-static void vapic_enter(struct kvm_vcpu *vcpu)
+static int vapic_enter(struct kvm_vcpu *vcpu)
 {
         struct kvm_lapic *apic = vcpu->arch.apic;
         struct page *page;
 
         if (!apic || !apic->vapic_addr)
-                return;
+                return 0;
 
         page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
+        if (is_error_page(page))
+                return -EFAULT;
 
         vcpu->arch.apic->vapic_page = page;
+        return 0;
 }
 
 static void vapic_exit(struct kvm_vcpu *vcpu)
@@ -5430,7 +5433,11 @@ static int __vcpu_run(struct kvm_vcpu *vcpu)
         }
 
         vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
-        vapic_enter(vcpu);
+        r = vapic_enter(vcpu);
+        if (r) {
+                srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
+                return r;
+        }
 
         r = 1;
         while (r > 0) {