8 files changed, 117 insertions, 429 deletions

diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index aba9e5692958..ec872622340f 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -22,27 +22,13 @@
 static struct stedma40_chan_cfg msp0_dma_rx = {
         .high_priority = true,
         .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 static struct stedma40_chan_cfg msp0_dma_tx = {
         .high_priority = true,
         .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
 };
 
 struct msp_i2s_platform_data msp0_platform_data = {
@@ -54,27 +40,13 @@ struct msp_i2s_platform_data msp0_platform_data = {
 static struct stedma40_chan_cfg msp1_dma_rx = {
         .high_priority = true,
         .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV30_MSP3_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dev_type = DB8500_DMA_DEV30_MSP3,
 };
 
 static struct stedma40_chan_cfg msp1_dma_tx = {
         .high_priority = true,
         .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV30_MSP1_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
-        /* data_width is set during configuration */
+        .dev_type = DB8500_DMA_DEV30_MSP1,
 };
 
 struct msp_i2s_platform_data msp1_platform_data = {
@@ -86,31 +58,15 @@ struct msp_i2s_platform_data msp1_platform_data = {
 static struct stedma40_chan_cfg msp2_dma_rx = {
         .high_priority = true,
         .dir = STEDMA40_PERIPH_TO_MEM,
-
-        .src_dev_type = DB8500_DMA_DEV14_MSP2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-
-        /* MSP2 DMA doesn't work with PSIZE == 4 on DB8500v2 */
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-
-        /* data_width is set during configuration */
+        .dev_type = DB8500_DMA_DEV14_MSP2,
 };
 
 static struct stedma40_chan_cfg msp2_dma_tx = {
         .high_priority = true,
         .dir = STEDMA40_MEM_TO_PERIPH,
-
-        .src_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV14_MSP2_TX,
-
-        .src_info.psize = STEDMA40_PSIZE_LOG_4,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_4,
-
+        .dev_type = DB8500_DMA_DEV14_MSP2,
         .use_fixed_channel = true,
         .phy_channel = 1,
-
-        /* data_width is set during configuration */
 };
 
 static struct platform_device *db8500_add_msp_i2s(struct device *parent,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 0ef38775a0c1..29be714b8a73 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -35,19 +35,13 @@
 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 
 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV29_SD_MM0,
 };
 #endif
 
@@ -88,19 +82,13 @@ void mop500_sdi_tc35892_init(struct device *parent)
 static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type = DB8500_DMA_DEV32_SD_MM1_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 
 static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV32_SD_MM1_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV32_SD_MM1,
 };
 #endif
 
@@ -125,19 +113,13 @@ struct mmci_platform_data mop500_sdi1_data = {
 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV28_SD_MM2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type =  DB8500_DMA_DEV28_SD_MM2,
 };
 
 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV28_SD_MM2,
 };
 #endif
 
@@ -163,19 +145,13 @@ struct mmci_platform_data mop500_sdi2_data = {
 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV42_SD_MM4_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type =  DB8500_DMA_DEV42_SD_MM4,
 };
 
 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
-        .src_info.data_width = STEDMA40_WORD_WIDTH,
-        .dst_info.data_width = STEDMA40_WORD_WIDTH,
+        .dev_type = DB8500_DMA_DEV42_SD_MM4,
 };
 #endif
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 78389de94dde..f59d52806afe 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -425,35 +425,20 @@ void mop500_snowball_ethernet_clock_enable(void)
 static struct cryp_platform_data u8500_cryp1_platform_data = {
                 .mem_to_engine = {
                                 .dir = STEDMA40_MEM_TO_PERIPH,
-                                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-                                .dst_dev_type = DB8500_DMA_DEV48_CAC1_TX,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
                                 .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                 },
                 .engine_to_mem = {
                                 .dir = STEDMA40_PERIPH_TO_MEM,
-                                .src_dev_type = DB8500_DMA_DEV48_CAC1_RX,
-                                .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-                                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                                .dev_type = DB8500_DMA_DEV48_CAC1,
                                 .mode = STEDMA40_MODE_LOGICAL,
-                                .src_info.psize = STEDMA40_PSIZE_LOG_4,
-                                .dst_info.psize = STEDMA40_PSIZE_LOG_4,
                 }
 };
 
 static struct stedma40_chan_cfg u8500_hash_dma_cfg_tx = {
                 .dir = STEDMA40_MEM_TO_PERIPH,
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-                .dst_dev_type = DB8500_DMA_DEV50_HAC1_TX,
-                .src_info.data_width = STEDMA40_WORD_WIDTH,
-                .dst_info.data_width = STEDMA40_WORD_WIDTH,
+                .dev_type = DB8500_DMA_DEV50_HAC1_TX,
                 .mode = STEDMA40_MODE_LOGICAL,
-                .src_info.psize = STEDMA40_PSIZE_LOG_16,
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16,
 };
 
 static struct hash_platform_data u8500_hash1_platform_data = {
@@ -471,19 +456,13 @@ static struct platform_device *mop500_platform_devs[] __initdata = {
 static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV8_SSP0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
 };
 
 static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV8_SSP0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV8_SSP0,
 };
 #endif
 
@@ -512,55 +491,37 @@ static void __init mop500_spi_init(struct device *parent)
 static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV13_UART0_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV13_UART0_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV13_UART0,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV12_UART1_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV12_UART1_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV12_UART1,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_PERIPH_TO_MEM,
-        .src_dev_type =  DB8500_DMA_DEV11_UART2_RX,
-        .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV11_UART2,
 };
 
 static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
         .mode = STEDMA40_MODE_LOGICAL,
         .dir = STEDMA40_MEM_TO_PERIPH,
-        .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
-        .dst_dev_type = DB8500_DMA_DEV11_UART2_TX,
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dev_type = DB8500_DMA_DEV11_UART2,
 };
 #endif
 
@@ -676,6 +637,8 @@ static void __init snowball_init_machine(void)
 
         mop500_snowball_ethernet_clock_enable();
 
+        u8500_cryp1_hash1_init(parent);
+
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 49514b825034..6f0bfcb08907 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -93,6 +93,7 @@ extern struct amba_pl011_data uart0_plat;
 extern struct amba_pl011_data uart1_plat;
 extern struct amba_pl011_data uart2_plat;
 extern struct pl022_ssp_controller ssp0_plat;
+extern struct stedma40_platform_data dma40_plat_data;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 46cca52890bc..243b91b66ae0 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -162,26 +162,15 @@ static void __init db8500_add_gpios(struct device *parent)
         dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
 }
 
-static int usb_db8500_rx_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8
-};
-
-static int usb_db8500_tx_dma_cfg[] = {
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8
+static int usb_db8500_dma_cfg[] = {
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15,
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8
 };
 
 static const char *db8500_read_soc_id(void)
@@ -215,7 +204,7 @@ struct device * __init u8500_init_devices(void)
 
         db8500_add_rtc(parent);
         db8500_add_gpios(parent);
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
+        db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
         for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
                 platform_devs[i]->dev.parent = parent;
@@ -232,17 +221,7 @@ static struct device * __init u8500_of_init_devices(void)
 {
         struct device *parent = db8500_soc_device_init();
 
-        db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
-
-        u8500_dma40_device.dev.parent = parent;
-
-        /*
-         * Devices to be DT:ed:
-         *   u8500_dma40_device  = todo
-         *   db8500_pmu_device   = done
-         *   db8500_prcmu_device = done
-         */
-        platform_device_register(&u8500_dma40_device);
+        db8500_add_usb(parent, usb_db8500_dma_cfg, usb_db8500_dma_cfg);
 
         return parent;
 }
@@ -251,9 +230,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires call-back bindings. */
         OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
         /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", &uart1_plat),
-        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
+        OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
+        OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
         OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
         OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
@@ -289,6 +268,9 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
                 "ux500-msp-i2s.2", &msp2_platform_data),
         OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
                 "ux500-msp-i2s.3", &msp3_platform_data),
+        /* Requires clock name bindings and channel address lookup table. */
+        OF_DEV_AUXDATA("stericsson,db8500-dma40", 0x801C0000,
+                       "dma40.0", &dma40_plat_data),
         {},
 };
 
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 1cf94ce0feec..e21ffd8c1412 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -42,128 +42,7 @@ static struct resource dma40_resources[] = {
         }
 };
 
-/* Default configuration for physcial memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
-        .mode = STEDMA40_MODE_PHYSICAL,
-        .dir = STEDMA40_MEM_TO_MEM,
-
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_PHY_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-/* Default configuration for logical memcpy */
-struct stedma40_chan_cfg dma40_memcpy_conf_log = {
-        .dir = STEDMA40_MEM_TO_MEM,
-
-        .src_info.data_width = STEDMA40_BYTE_WIDTH,
-        .src_info.psize = STEDMA40_PSIZE_LOG_1,
-        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-
-        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
-        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
-        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
-};
-
-/*
- * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefore the address is constant.
- * When the address comes from a primecell it will be configured in runtime
- * and we set the address to -1 as a placeholder.
- */
-static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
-        /* PrimeCells - run-time configured */
-        [DB8500_DMA_DEV0_SPI0_TX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
-        [DB8500_DMA_DEV8_SSP0_TX] = -1,
-        [DB8500_DMA_DEV9_SSP1_TX] = -1,
-        [DB8500_DMA_DEV11_UART2_TX] = -1,
-        [DB8500_DMA_DEV12_UART1_TX] = -1,
-        [DB8500_DMA_DEV13_UART0_TX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_TX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_TX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_TX] = -1,
-        [DB8500_DMA_DEV33_SPI2_TX] = -1,
-        [DB8500_DMA_DEV35_SPI1_TX] = -1,
-        [DB8500_DMA_DEV40_SPI3_TX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_TX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_TX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_TX] = -1,
-        [DB8500_DMA_DEV14_MSP2_TX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP1_TX] = U8500_MSP1_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_TX] = U8500_CRYP1_BASE + CRYP1_TX_REG_OFFSET,
-        [DB8500_DMA_DEV50_HAC1_TX] = U8500_HASH1_BASE + HASH1_TX_REG_OFFSET,
-};
-
-/* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
-        /* MUSB - these will be runtime-reconfigured */
-        [DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
-        [DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
-        [DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
-        [DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
-        [DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
-        [DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
-        [DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
-        [DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
-        /* PrimeCells */
-        [DB8500_DMA_DEV0_SPI0_RX] = -1,
-        [DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
-        [DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
-        [DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
-        [DB8500_DMA_DEV8_SSP0_RX] = -1,
-        [DB8500_DMA_DEV9_SSP1_RX] = -1,
-        [DB8500_DMA_DEV11_UART2_RX] = -1,
-        [DB8500_DMA_DEV12_UART1_RX] = -1,
-        [DB8500_DMA_DEV13_UART0_RX] = -1,
-        [DB8500_DMA_DEV28_SD_MM2_RX] = -1,
-        [DB8500_DMA_DEV29_SD_MM0_RX] = -1,
-        [DB8500_DMA_DEV32_SD_MM1_RX] = -1,
-        [DB8500_DMA_DEV33_SPI2_RX] = -1,
-        [DB8500_DMA_DEV35_SPI1_RX] = -1,
-        [DB8500_DMA_DEV40_SPI3_RX] = -1,
-        [DB8500_DMA_DEV41_SD_MM3_RX] = -1,
-        [DB8500_DMA_DEV42_SD_MM4_RX] = -1,
-        [DB8500_DMA_DEV43_SD_MM5_RX] = -1,
-        [DB8500_DMA_DEV14_MSP2_RX] = U8500_MSP2_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV30_MSP3_RX] = U8500_MSP3_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX] = U8500_MSP0_BASE + MSP_TX_RX_REG_OFFSET,
-        [DB8500_DMA_DEV48_CAC1_RX] = U8500_CRYP1_BASE + CRYP1_RX_REG_OFFSET,
-};
-
-/* Reserved event lines for memcpy only */
-static int dma40_memcpy_event[] = {
-        DB8500_DMA_MEMCPY_TX_0,
-        DB8500_DMA_MEMCPY_TX_1,
-        DB8500_DMA_MEMCPY_TX_2,
-        DB8500_DMA_MEMCPY_TX_3,
-        DB8500_DMA_MEMCPY_TX_4,
-        DB8500_DMA_MEMCPY_TX_5,
-};
-
-static struct stedma40_platform_data dma40_plat_data = {
-        .dev_len = DB8500_DMA_NR_DEV,
-        .dev_rx = dma40_rx_map,
-        .dev_tx = dma40_tx_map,
-        .memcpy = dma40_memcpy_event,
-        .memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
-        .memcpy_conf_phy = &dma40_memcpy_conf_phy,
-        .memcpy_conf_log = &dma40_memcpy_conf_log,
+struct stedma40_platform_data dma40_plat_data = {
         .disabled_channels = {-1},
 };
 
diff --git a/arch/arm/mach-ux500/ste-dma40-db8500.h b/arch/arm/mach-ux500/ste-dma40-db8500.h
index a616419bea76..0296ae5b0fd9 100644
--- a/arch/arm/mach-ux500/ste-dma40-db8500.h
+++ b/arch/arm/mach-ux500/ste-dma40-db8500.h
@@ -12,133 +12,74 @@
 
 #define DB8500_DMA_NR_DEV 64
 
-enum dma_src_dev_type {
-        DB8500_DMA_DEV0_SPI0_RX = 0,
-        DB8500_DMA_DEV1_SD_MMC0_RX = 1,
-        DB8500_DMA_DEV2_SD_MMC1_RX = 2,
-        DB8500_DMA_DEV3_SD_MMC2_RX = 3,
-        DB8500_DMA_DEV4_I2C1_RX = 4,
-        DB8500_DMA_DEV5_I2C3_RX = 5,
-        DB8500_DMA_DEV6_I2C2_RX = 6,
-        DB8500_DMA_DEV7_I2C4_RX = 7, /* Only on V1 and later */
-        DB8500_DMA_DEV8_SSP0_RX = 8,
-        DB8500_DMA_DEV9_SSP1_RX = 9,
-        DB8500_DMA_DEV10_MCDE_RX = 10,
-        DB8500_DMA_DEV11_UART2_RX = 11,
-        DB8500_DMA_DEV12_UART1_RX = 12,
-        DB8500_DMA_DEV13_UART0_RX = 13,
-        DB8500_DMA_DEV14_MSP2_RX = 14,
-        DB8500_DMA_DEV15_I2C0_RX = 15,
-        DB8500_DMA_DEV16_USB_OTG_IEP_7_15 = 16,
-        DB8500_DMA_DEV17_USB_OTG_IEP_6_14 = 17,
-        DB8500_DMA_DEV18_USB_OTG_IEP_5_13 = 18,
-        DB8500_DMA_DEV19_USB_OTG_IEP_4_12 = 19,
-        DB8500_DMA_DEV20_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
-        DB8500_DMA_DEV21_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
-        DB8500_DMA_DEV22_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
-        DB8500_DMA_DEV23_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
-        DB8500_DMA_DEV24_SRC_SXA0_RX_TX = 24,
-        DB8500_DMA_DEV25_SRC_SXA1_RX_TX = 25,
-        DB8500_DMA_DEV26_SRC_SXA2_RX_TX = 26,
-        DB8500_DMA_DEV27_SRC_SXA3_RX_TX = 27,
-        DB8500_DMA_DEV28_SD_MM2_RX = 28,
-        DB8500_DMA_DEV29_SD_MM0_RX = 29,
-        DB8500_DMA_DEV30_MSP1_RX = 30,
+/*
+ * Unless otherwise specified, all channels numbers are used for
+ * TX & RX, and can be used for either source or destination
+ * channels.
+ */
+enum dma_dev_type {
+        DB8500_DMA_DEV0_SPI0 = 0,
+        DB8500_DMA_DEV1_SD_MMC0 = 1,
+        DB8500_DMA_DEV2_SD_MMC1 = 2,
+        DB8500_DMA_DEV3_SD_MMC2 = 3,
+        DB8500_DMA_DEV4_I2C1 = 4,
+        DB8500_DMA_DEV5_I2C3 = 5,
+        DB8500_DMA_DEV6_I2C2 = 6,
+        DB8500_DMA_DEV7_I2C4 = 7,                       /* Only on V1 and later */
+        DB8500_DMA_DEV8_SSP0 = 8,
+        DB8500_DMA_DEV9_SSP1 = 9,
+        DB8500_DMA_DEV10_MCDE_RX = 10,                  /* RX only */
+        DB8500_DMA_DEV11_UART2 = 11,
+        DB8500_DMA_DEV12_UART1 = 12,
+        DB8500_DMA_DEV13_UART0 = 13,
+        DB8500_DMA_DEV14_MSP2 = 14,
+        DB8500_DMA_DEV15_I2C0 = 15,
+        DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
+        DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
+        DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
+        DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
+        DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
+        DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
+        DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
+        DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
+        DB8500_DMA_DEV24_SXA0 = 24,
+        DB8500_DMA_DEV25_SXA1 = 25,
+        DB8500_DMA_DEV26_SXA2 = 26,
+        DB8500_DMA_DEV27_SXA3 = 27,
+        DB8500_DMA_DEV28_SD_MM2 = 28,
+        DB8500_DMA_DEV29_SD_MM0 = 29,
+        DB8500_DMA_DEV30_MSP1 = 30,
         /* On DB8500v2, MSP3 RX replaces MSP1 RX */
-        DB8500_DMA_DEV30_MSP3_RX = 30,
-        DB8500_DMA_DEV31_MSP0_RX_SLIM0_CH0_RX = 31,
-        DB8500_DMA_DEV32_SD_MM1_RX = 32,
-        DB8500_DMA_DEV33_SPI2_RX = 33,
-        DB8500_DMA_DEV34_I2C3_RX2 = 34,
-        DB8500_DMA_DEV35_SPI1_RX = 35,
-        DB8500_DMA_DEV36_USB_OTG_IEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_IEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_IEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_IEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_RX = 40,
-        DB8500_DMA_DEV41_SD_MM3_RX = 41,
-        DB8500_DMA_DEV42_SD_MM4_RX = 42,
-        DB8500_DMA_DEV43_SD_MM5_RX = 43,
-        DB8500_DMA_DEV44_SRC_SXA4_RX_TX = 44,
-        DB8500_DMA_DEV45_SRC_SXA5_RX_TX = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_RX_SRC_SXA6_RX_TX = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_RX_SRC_SXA7_RX_TX = 47,
-        DB8500_DMA_DEV48_CAC1_RX = 48,
-        /* 49, 50 and 51 are not used */
-        DB8500_DMA_DEV52_SLIM0_CH4_RX_HSI_RX_CH4 = 52,
-        DB8500_DMA_DEV53_SLIM0_CH5_RX_HSI_RX_CH5 = 53,
-        DB8500_DMA_DEV54_SLIM0_CH6_RX_HSI_RX_CH6 = 54,
-        DB8500_DMA_DEV55_SLIM0_CH7_RX_HSI_RX_CH7 = 55,
-        /* 56, 57, 58, 59 and 60 are not used */
-        DB8500_DMA_DEV61_CAC0_RX = 61,
-        /* 62 and 63 are not used */
-};
-
-enum dma_dest_dev_type {
-        DB8500_DMA_DEV0_SPI0_TX = 0,
-        DB8500_DMA_DEV1_SD_MMC0_TX = 1,
-        DB8500_DMA_DEV2_SD_MMC1_TX = 2,
-        DB8500_DMA_DEV3_SD_MMC2_TX = 3,
-        DB8500_DMA_DEV4_I2C1_TX = 4,
-        DB8500_DMA_DEV5_I2C3_TX = 5,
-        DB8500_DMA_DEV6_I2C2_TX = 6,
-        DB8500_DMA_DEV7_I2C4_TX = 7, /* Only on V1 and later */
-        DB8500_DMA_DEV8_SSP0_TX = 8,
-        DB8500_DMA_DEV9_SSP1_TX = 9,
-        /* 10 is not used*/
-        DB8500_DMA_DEV11_UART2_TX = 11,
-        DB8500_DMA_DEV12_UART1_TX = 12,
-        DB8500_DMA_DEV13_UART0_TX = 13,
-        DB8500_DMA_DEV14_MSP2_TX = 14,
-        DB8500_DMA_DEV15_I2C0_TX = 15,
-        DB8500_DMA_DEV16_USB_OTG_OEP_7_15 = 16,
-        DB8500_DMA_DEV17_USB_OTG_OEP_6_14 = 17,
-        DB8500_DMA_DEV18_USB_OTG_OEP_5_13 = 18,
-        DB8500_DMA_DEV19_USB_OTG_OEP_4_12 = 19,
-        DB8500_DMA_DEV20_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
-        DB8500_DMA_DEV21_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
-        DB8500_DMA_DEV22_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
-        DB8500_DMA_DEV23_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
-        DB8500_DMA_DEV24_DST_SXA0_RX_TX = 24,
-        DB8500_DMA_DEV25_DST_SXA1_RX_TX = 25,
-        DB8500_DMA_DEV26_DST_SXA2_RX_TX = 26,
-        DB8500_DMA_DEV27_DST_SXA3_RX_TX = 27,
-        DB8500_DMA_DEV28_SD_MM2_TX = 28,
-        DB8500_DMA_DEV29_SD_MM0_TX = 29,
-        DB8500_DMA_DEV30_MSP1_TX = 30,
-        DB8500_DMA_DEV31_MSP0_TX_SLIM0_CH0_TX = 31,
-        DB8500_DMA_DEV32_SD_MM1_TX = 32,
-        DB8500_DMA_DEV33_SPI2_TX = 33,
-        DB8500_DMA_DEV34_I2C3_TX2 = 34,
-        DB8500_DMA_DEV35_SPI1_TX = 35,
-        DB8500_DMA_DEV36_USB_OTG_OEP_3_11 = 36,
-        DB8500_DMA_DEV37_USB_OTG_OEP_2_10 = 37,
-        DB8500_DMA_DEV38_USB_OTG_OEP_1_9 = 38,
-        DB8500_DMA_DEV39_USB_OTG_OEP_8 = 39,
-        DB8500_DMA_DEV40_SPI3_TX = 40,
-        DB8500_DMA_DEV41_SD_MM3_TX = 41,
-        DB8500_DMA_DEV42_SD_MM4_TX = 42,
-        DB8500_DMA_DEV43_SD_MM5_TX = 43,
-        DB8500_DMA_DEV44_DST_SXA4_RX_TX = 44,
-        DB8500_DMA_DEV45_DST_SXA5_RX_TX = 45,
-        DB8500_DMA_DEV46_SLIM0_CH8_TX_DST_SXA6_RX_TX = 46,
-        DB8500_DMA_DEV47_SLIM0_CH9_TX_DST_SXA7_RX_TX = 47,
-        DB8500_DMA_DEV48_CAC1_TX  = 48,
-        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,
-        DB8500_DMA_DEV50_HAC1_TX = 50,
-        DB8500_DMA_MEMCPY_TX_0 = 51,
-        DB8500_DMA_DEV52_SLIM1_CH4_TX_HSI_TX_CH4 = 52,
-        DB8500_DMA_DEV53_SLIM1_CH5_TX_HSI_TX_CH5 = 53,
-        DB8500_DMA_DEV54_SLIM1_CH6_TX_HSI_TX_CH6 = 54,
-        DB8500_DMA_DEV55_SLIM1_CH7_TX_HSI_TX_CH7 = 55,
-        DB8500_DMA_MEMCPY_TX_1 = 56,
-        DB8500_DMA_MEMCPY_TX_2 = 57,
-        DB8500_DMA_MEMCPY_TX_3 = 58,
-        DB8500_DMA_MEMCPY_TX_4 = 59,
-        DB8500_DMA_MEMCPY_TX_5 = 60,
-        DB8500_DMA_DEV61_CAC0_TX = 61,
-        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,
-        DB8500_DMA_DEV63_HAC0_TX = 63,
+        DB8500_DMA_DEV30_MSP3 = 30,
+        DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
+        DB8500_DMA_DEV32_SD_MM1 = 32,
+        DB8500_DMA_DEV33_SPI2 = 33,
+        DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
+        DB8500_DMA_DEV35_SPI1 = 35,
+        DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
+        DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
+        DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
+        DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
+        DB8500_DMA_DEV40_SPI3 = 40,
+        DB8500_DMA_DEV41_SD_MM3 = 41,
+        DB8500_DMA_DEV42_SD_MM4 = 42,
+        DB8500_DMA_DEV43_SD_MM5 = 43,
+        DB8500_DMA_DEV44_SXA4 = 44,
+        DB8500_DMA_DEV45_SXA5 = 45,
+        DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
+        DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
+        DB8500_DMA_DEV48_CAC1 = 48,
+        DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49,          /* TX only */
+        DB8500_DMA_DEV50_HAC1_TX = 50,                  /* TX only */
+        DB8500_DMA_MEMCPY_TX_0 = 51,                    /* TX only */
+        DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
+        DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
+        DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
+        DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
+        /* 56 -> 60 are channels reserved for memcpy only */
+        DB8500_DMA_DEV61_CAC0 = 61,
+        DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62,          /* TX only */
+        DB8500_DMA_DEV63_HAC0_TX = 63,                  /* TX only */
 };
 
 #endif
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 2dfc72f7cd8a..72754e369417 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -15,21 +15,11 @@
 #define MUSB_DMA40_RX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
                 .dir = STEDMA40_PERIPH_TO_MEM, \
-                .dst_dev_type = STEDMA40_DEV_DST_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
         }
 
 #define MUSB_DMA40_TX_CH { \
                 .mode = STEDMA40_MODE_LOGICAL, \
                 .dir = STEDMA40_MEM_TO_PERIPH, \
-                .src_dev_type = STEDMA40_DEV_SRC_MEMORY, \
-                .src_info.data_width = STEDMA40_WORD_WIDTH, \
-                .dst_info.data_width = STEDMA40_WORD_WIDTH, \
-                .src_info.psize = STEDMA40_PSIZE_LOG_16, \
-                .dst_info.psize = STEDMA40_PSIZE_LOG_16, \
         }
 
 static struct stedma40_chan_cfg musb_dma_rx_ch[UX500_MUSB_DMA_NUM_RX_CHANNELS]
@@ -125,20 +115,20 @@ struct platform_device ux500_musb_device = {
         .resource = usb_resources,
 };
 
-static inline void ux500_usb_dma_update_rx_ch_config(int *src_dev_type)
+static inline void ux500_usb_dma_update_rx_ch_config(int *dev_type)
 {
         u32 idx;
 
         for (idx = 0; idx < UX500_MUSB_DMA_NUM_RX_CHANNELS; idx++)
-                musb_dma_rx_ch[idx].src_dev_type = src_dev_type[idx];
+                musb_dma_rx_ch[idx].dev_type = dev_type[idx];
 }
 
-static inline void ux500_usb_dma_update_tx_ch_config(int *dst_dev_type)
+static inline void ux500_usb_dma_update_tx_ch_config(int *dev_type)
 {
         u32 idx;
 
         for (idx = 0; idx < UX500_MUSB_DMA_NUM_TX_CHANNELS; idx++)
-                musb_dma_tx_ch[idx].dst_dev_type = dst_dev_type[idx];
+                musb_dma_tx_ch[idx].dev_type = dev_type[idx];
 }
 
 void ux500_add_usb(struct device *parent, resource_size_t base, int irq,