2 files changed, 23 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index bcc9e63c8070..8e45ea44317e 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -81,6 +81,15 @@
                 reg = <0x10023CA0 0x20>;
         };
 
+        l2c: l2-cache-controller@10502000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x10502000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+                arm,tag-latency = <2 2 1>;
+                arm,data-latency = <2 2 1>;
+        };
+
         gic: interrupt-controller@10490000 {
                 cpu-offset = <0x8000>;
         };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 93b70402e943..8bc97c415c9a 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -54,6 +54,20 @@
                 reg = <0x10023CA0 0x20>;
         };
 
+        l2c: l2-cache-controller@10502000 {
+                compatible = "arm,pl310-cache";
+                reg = <0x10502000 0x1000>;
+                cache-unified;
+                cache-level = <2>;
+                arm,tag-latency = <2 2 1>;
+                arm,data-latency = <3 2 1>;
+                arm,double-linefill = <1>;
+                arm,double-linefill-incr = <0>;
+                arm,double-linefill-wrap = <1>;
+                arm,prefetch-drop = <1>;
+                arm,prefetch-offset = <7>;
+        };
+
         clock: clock-controller@10030000 {
                 compatible = "samsung,exynos4412-clock";
                 reg = <0x10030000 0x20000>;