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-rw-r--r--arch/powerpc/boot/dts/mpc5121.dtsi95
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc5121.dtsi b/arch/powerpc/boot/dts/mpc5121.dtsi
index 1d533e083e3c..2c0e1552d20b 100644
--- a/arch/powerpc/boot/dts/mpc5121.dtsi
+++ b/arch/powerpc/boot/dts/mpc5121.dtsi
@@ -51,6 +51,10 @@
51 compatible = "fsl,mpc5121-mbx"; 51 compatible = "fsl,mpc5121-mbx";
52 reg = <0x20000000 0x4000>; 52 reg = <0x20000000 0x4000>;
53 interrupts = <66 0x8>; 53 interrupts = <66 0x8>;
54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
57 clock-names = "mbx-bus", "mbx-3d", "mbx";
54 }; 58 };
55 59
56 sram@30000000 { 60 sram@30000000 {
@@ -64,6 +68,8 @@
64 interrupts = <6 8>; 68 interrupts = <6 8>;
65 #address-cells = <1>; 69 #address-cells = <1>;
66 #size-cells = <1>; 70 #size-cells = <1>;
71 clocks = <&clks MPC512x_CLK_NFC>;
72 clock-names = "ipg";
67 }; 73 };
68 74
69 localbus@80000020 { 75 localbus@80000020 {
@@ -155,12 +161,24 @@
155 compatible = "fsl,mpc5121-mscan"; 161 compatible = "fsl,mpc5121-mscan";
156 reg = <0x1300 0x80>; 162 reg = <0x1300 0x80>;
157 interrupts = <12 0x8>; 163 interrupts = <12 0x8>;
164 clocks = <&clks MPC512x_CLK_BDLC>,
165 <&clks MPC512x_CLK_IPS>,
166 <&clks MPC512x_CLK_SYS>,
167 <&clks MPC512x_CLK_REF>,
168 <&clks MPC512x_CLK_MSCAN0_MCLK>;
169 clock-names = "ipg", "ips", "sys", "ref", "mclk";
158 }; 170 };
159 171
160 can@1380 { 172 can@1380 {
161 compatible = "fsl,mpc5121-mscan"; 173 compatible = "fsl,mpc5121-mscan";
162 reg = <0x1380 0x80>; 174 reg = <0x1380 0x80>;
163 interrupts = <13 0x8>; 175 interrupts = <13 0x8>;
176 clocks = <&clks MPC512x_CLK_BDLC>,
177 <&clks MPC512x_CLK_IPS>,
178 <&clks MPC512x_CLK_SYS>,
179 <&clks MPC512x_CLK_REF>,
180 <&clks MPC512x_CLK_MSCAN1_MCLK>;
181 clock-names = "ipg", "ips", "sys", "ref", "mclk";
164 }; 182 };
165 183
166 sdhc@1500 { 184 sdhc@1500 {
@@ -169,6 +187,9 @@
169 interrupts = <8 0x8>; 187 interrupts = <8 0x8>;
170 dmas = <&dma0 30>; 188 dmas = <&dma0 30>;
171 dma-names = "rx-tx"; 189 dma-names = "rx-tx";
190 clocks = <&clks MPC512x_CLK_IPS>,
191 <&clks MPC512x_CLK_SDHC>;
192 clock-names = "ipg", "per";
172 }; 193 };
173 194
174 i2c@1700 { 195 i2c@1700 {
@@ -177,6 +198,8 @@
177 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 198 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
178 reg = <0x1700 0x20>; 199 reg = <0x1700 0x20>;
179 interrupts = <9 0x8>; 200 interrupts = <9 0x8>;
201 clocks = <&clks MPC512x_CLK_I2C>;
202 clock-names = "ipg";
180 }; 203 };
181 204
182 i2c@1720 { 205 i2c@1720 {
@@ -185,6 +208,8 @@
185 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 208 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
186 reg = <0x1720 0x20>; 209 reg = <0x1720 0x20>;
187 interrupts = <10 0x8>; 210 interrupts = <10 0x8>;
211 clocks = <&clks MPC512x_CLK_I2C>;
212 clock-names = "ipg";
188 }; 213 };
189 214
190 i2c@1740 { 215 i2c@1740 {
@@ -193,6 +218,8 @@
193 compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 218 compatible = "fsl,mpc5121-i2c", "fsl-i2c";
194 reg = <0x1740 0x20>; 219 reg = <0x1740 0x20>;
195 interrupts = <11 0x8>; 220 interrupts = <11 0x8>;
221 clocks = <&clks MPC512x_CLK_I2C>;
222 clock-names = "ipg";
196 }; 223 };
197 224
198 i2ccontrol@1760 { 225 i2ccontrol@1760 {
@@ -204,30 +231,48 @@
204 compatible = "fsl,mpc5121-axe"; 231 compatible = "fsl,mpc5121-axe";
205 reg = <0x2000 0x100>; 232 reg = <0x2000 0x100>;
206 interrupts = <42 0x8>; 233 interrupts = <42 0x8>;
234 clocks = <&clks MPC512x_CLK_AXE>;
235 clock-names = "ipg";
207 }; 236 };
208 237
209 display@2100 { 238 display@2100 {
210 compatible = "fsl,mpc5121-diu"; 239 compatible = "fsl,mpc5121-diu";
211 reg = <0x2100 0x100>; 240 reg = <0x2100 0x100>;
212 interrupts = <64 0x8>; 241 interrupts = <64 0x8>;
242 clocks = <&clks MPC512x_CLK_DIU>;
243 clock-names = "ipg";
213 }; 244 };
214 245
215 can@2300 { 246 can@2300 {
216 compatible = "fsl,mpc5121-mscan"; 247 compatible = "fsl,mpc5121-mscan";
217 reg = <0x2300 0x80>; 248 reg = <0x2300 0x80>;
218 interrupts = <90 0x8>; 249 interrupts = <90 0x8>;
250 clocks = <&clks MPC512x_CLK_BDLC>,
251 <&clks MPC512x_CLK_IPS>,
252 <&clks MPC512x_CLK_SYS>,
253 <&clks MPC512x_CLK_REF>,
254 <&clks MPC512x_CLK_MSCAN2_MCLK>;
255 clock-names = "ipg", "ips", "sys", "ref", "mclk";
219 }; 256 };
220 257
221 can@2380 { 258 can@2380 {
222 compatible = "fsl,mpc5121-mscan"; 259 compatible = "fsl,mpc5121-mscan";
223 reg = <0x2380 0x80>; 260 reg = <0x2380 0x80>;
224 interrupts = <91 0x8>; 261 interrupts = <91 0x8>;
262 clocks = <&clks MPC512x_CLK_BDLC>,
263 <&clks MPC512x_CLK_IPS>,
264 <&clks MPC512x_CLK_SYS>,
265 <&clks MPC512x_CLK_REF>,
266 <&clks MPC512x_CLK_MSCAN3_MCLK>;
267 clock-names = "ipg", "ips", "sys", "ref", "mclk";
225 }; 268 };
226 269
227 viu@2400 { 270 viu@2400 {
228 compatible = "fsl,mpc5121-viu"; 271 compatible = "fsl,mpc5121-viu";
229 reg = <0x2400 0x400>; 272 reg = <0x2400 0x400>;
230 interrupts = <67 0x8>; 273 interrupts = <67 0x8>;
274 clocks = <&clks MPC512x_CLK_VIU>;
275 clock-names = "ipg";
231 }; 276 };
232 277
233 mdio@2800 { 278 mdio@2800 {
@@ -235,6 +280,8 @@
235 reg = <0x2800 0x800>; 280 reg = <0x2800 0x800>;
236 #address-cells = <1>; 281 #address-cells = <1>;
237 #size-cells = <0>; 282 #size-cells = <0>;
283 clocks = <&clks MPC512x_CLK_FEC>;
284 clock-names = "per";
238 }; 285 };
239 286
240 eth0: ethernet@2800 { 287 eth0: ethernet@2800 {
@@ -243,6 +290,8 @@
243 reg = <0x2800 0x800>; 290 reg = <0x2800 0x800>;
244 local-mac-address = [ 00 00 00 00 00 00 ]; 291 local-mac-address = [ 00 00 00 00 00 00 ];
245 interrupts = <4 0x8>; 292 interrupts = <4 0x8>;
293 clocks = <&clks MPC512x_CLK_FEC>;
294 clock-names = "per";
246 }; 295 };
247 296
248 /* USB1 using external ULPI PHY */ 297 /* USB1 using external ULPI PHY */
@@ -254,6 +303,8 @@
254 interrupts = <43 0x8>; 303 interrupts = <43 0x8>;
255 dr_mode = "otg"; 304 dr_mode = "otg";
256 phy_type = "ulpi"; 305 phy_type = "ulpi";
306 clocks = <&clks MPC512x_CLK_USB1>;
307 clock-names = "ipg";
257 }; 308 };
258 309
259 /* USB0 using internal UTMI PHY */ 310 /* USB0 using internal UTMI PHY */
@@ -265,6 +316,8 @@
265 interrupts = <44 0x8>; 316 interrupts = <44 0x8>;
266 dr_mode = "otg"; 317 dr_mode = "otg";
267 phy_type = "utmi_wide"; 318 phy_type = "utmi_wide";
319 clocks = <&clks MPC512x_CLK_USB2>;
320 clock-names = "ipg";
268 }; 321 };
269 322
270 /* IO control */ 323 /* IO control */
@@ -283,6 +336,8 @@
283 compatible = "fsl,mpc5121-pata"; 336 compatible = "fsl,mpc5121-pata";
284 reg = <0x10200 0x100>; 337 reg = <0x10200 0x100>;
285 interrupts = <5 0x8>; 338 interrupts = <5 0x8>;
339 clocks = <&clks MPC512x_CLK_PATA>;
340 clock-names = "ipg";
286 }; 341 };
287 342
288 /* 512x PSCs are not 52xx PSC compatible */ 343 /* 512x PSCs are not 52xx PSC compatible */
@@ -294,6 +349,9 @@
294 interrupts = <40 0x8>; 349 interrupts = <40 0x8>;
295 fsl,rx-fifo-size = <16>; 350 fsl,rx-fifo-size = <16>;
296 fsl,tx-fifo-size = <16>; 351 fsl,tx-fifo-size = <16>;
352 clocks = <&clks MPC512x_CLK_PSC0>,
353 <&clks MPC512x_CLK_PSC0_MCLK>;
354 clock-names = "ipg", "mclk";
297 }; 355 };
298 356
299 /* PSC1 */ 357 /* PSC1 */
@@ -303,6 +361,9 @@
303 interrupts = <40 0x8>; 361 interrupts = <40 0x8>;
304 fsl,rx-fifo-size = <16>; 362 fsl,rx-fifo-size = <16>;
305 fsl,tx-fifo-size = <16>; 363 fsl,tx-fifo-size = <16>;
364 clocks = <&clks MPC512x_CLK_PSC1>,
365 <&clks MPC512x_CLK_PSC1_MCLK>;
366 clock-names = "ipg", "mclk";
306 }; 367 };
307 368
308 /* PSC2 */ 369 /* PSC2 */
@@ -312,6 +373,9 @@
312 interrupts = <40 0x8>; 373 interrupts = <40 0x8>;
313 fsl,rx-fifo-size = <16>; 374 fsl,rx-fifo-size = <16>;
314 fsl,tx-fifo-size = <16>; 375 fsl,tx-fifo-size = <16>;
376 clocks = <&clks MPC512x_CLK_PSC2>,
377 <&clks MPC512x_CLK_PSC2_MCLK>;
378 clock-names = "ipg", "mclk";
315 }; 379 };
316 380
317 /* PSC3 */ 381 /* PSC3 */
@@ -321,6 +385,9 @@
321 interrupts = <40 0x8>; 385 interrupts = <40 0x8>;
322 fsl,rx-fifo-size = <16>; 386 fsl,rx-fifo-size = <16>;
323 fsl,tx-fifo-size = <16>; 387 fsl,tx-fifo-size = <16>;
388 clocks = <&clks MPC512x_CLK_PSC3>,
389 <&clks MPC512x_CLK_PSC3_MCLK>;
390 clock-names = "ipg", "mclk";
324 }; 391 };
325 392
326 /* PSC4 */ 393 /* PSC4 */
@@ -330,6 +397,9 @@
330 interrupts = <40 0x8>; 397 interrupts = <40 0x8>;
331 fsl,rx-fifo-size = <16>; 398 fsl,rx-fifo-size = <16>;
332 fsl,tx-fifo-size = <16>; 399 fsl,tx-fifo-size = <16>;
400 clocks = <&clks MPC512x_CLK_PSC4>,
401 <&clks MPC512x_CLK_PSC4_MCLK>;
402 clock-names = "ipg", "mclk";
333 }; 403 };
334 404
335 /* PSC5 */ 405 /* PSC5 */
@@ -339,6 +409,9 @@
339 interrupts = <40 0x8>; 409 interrupts = <40 0x8>;
340 fsl,rx-fifo-size = <16>; 410 fsl,rx-fifo-size = <16>;
341 fsl,tx-fifo-size = <16>; 411 fsl,tx-fifo-size = <16>;
412 clocks = <&clks MPC512x_CLK_PSC5>,
413 <&clks MPC512x_CLK_PSC5_MCLK>;
414 clock-names = "ipg", "mclk";
342 }; 415 };
343 416
344 /* PSC6 */ 417 /* PSC6 */
@@ -348,6 +421,9 @@
348 interrupts = <40 0x8>; 421 interrupts = <40 0x8>;
349 fsl,rx-fifo-size = <16>; 422 fsl,rx-fifo-size = <16>;
350 fsl,tx-fifo-size = <16>; 423 fsl,tx-fifo-size = <16>;
424 clocks = <&clks MPC512x_CLK_PSC6>,
425 <&clks MPC512x_CLK_PSC6_MCLK>;
426 clock-names = "ipg", "mclk";
351 }; 427 };
352 428
353 /* PSC7 */ 429 /* PSC7 */
@@ -357,6 +433,9 @@
357 interrupts = <40 0x8>; 433 interrupts = <40 0x8>;
358 fsl,rx-fifo-size = <16>; 434 fsl,rx-fifo-size = <16>;
359 fsl,tx-fifo-size = <16>; 435 fsl,tx-fifo-size = <16>;
436 clocks = <&clks MPC512x_CLK_PSC7>,
437 <&clks MPC512x_CLK_PSC7_MCLK>;
438 clock-names = "ipg", "mclk";
360 }; 439 };
361 440
362 /* PSC8 */ 441 /* PSC8 */
@@ -366,6 +445,9 @@
366 interrupts = <40 0x8>; 445 interrupts = <40 0x8>;
367 fsl,rx-fifo-size = <16>; 446 fsl,rx-fifo-size = <16>;
368 fsl,tx-fifo-size = <16>; 447 fsl,tx-fifo-size = <16>;
448 clocks = <&clks MPC512x_CLK_PSC8>,
449 <&clks MPC512x_CLK_PSC8_MCLK>;
450 clock-names = "ipg", "mclk";
369 }; 451 };
370 452
371 /* PSC9 */ 453 /* PSC9 */
@@ -375,6 +457,9 @@
375 interrupts = <40 0x8>; 457 interrupts = <40 0x8>;
376 fsl,rx-fifo-size = <16>; 458 fsl,rx-fifo-size = <16>;
377 fsl,tx-fifo-size = <16>; 459 fsl,tx-fifo-size = <16>;
460 clocks = <&clks MPC512x_CLK_PSC9>,
461 <&clks MPC512x_CLK_PSC9_MCLK>;
462 clock-names = "ipg", "mclk";
378 }; 463 };
379 464
380 /* PSC10 */ 465 /* PSC10 */
@@ -384,6 +469,9 @@
384 interrupts = <40 0x8>; 469 interrupts = <40 0x8>;
385 fsl,rx-fifo-size = <16>; 470 fsl,rx-fifo-size = <16>;
386 fsl,tx-fifo-size = <16>; 471 fsl,tx-fifo-size = <16>;
472 clocks = <&clks MPC512x_CLK_PSC10>,
473 <&clks MPC512x_CLK_PSC10_MCLK>;
474 clock-names = "ipg", "mclk";
387 }; 475 };
388 476
389 /* PSC11 */ 477 /* PSC11 */
@@ -393,12 +481,17 @@
393 interrupts = <40 0x8>; 481 interrupts = <40 0x8>;
394 fsl,rx-fifo-size = <16>; 482 fsl,rx-fifo-size = <16>;
395 fsl,tx-fifo-size = <16>; 483 fsl,tx-fifo-size = <16>;
484 clocks = <&clks MPC512x_CLK_PSC11>,
485 <&clks MPC512x_CLK_PSC11_MCLK>;
486 clock-names = "ipg", "mclk";
396 }; 487 };
397 488
398 pscfifo@11f00 { 489 pscfifo@11f00 {
399 compatible = "fsl,mpc5121-psc-fifo"; 490 compatible = "fsl,mpc5121-psc-fifo";
400 reg = <0x11f00 0x100>; 491 reg = <0x11f00 0x100>;
401 interrupts = <40 0x8>; 492 interrupts = <40 0x8>;
493 clocks = <&clks MPC512x_CLK_PSC_FIFO>;
494 clock-names = "ipg";
402 }; 495 };
403 496
404 dma0: dma@14000 { 497 dma0: dma@14000 {
@@ -416,6 +509,8 @@
416 #address-cells = <3>; 509 #address-cells = <3>;
417 #size-cells = <2>; 510 #size-cells = <2>;
418 #interrupt-cells = <1>; 511 #interrupt-cells = <1>;
512 clocks = <&clks MPC512x_CLK_PCI>;
513 clock-names = "ipg";
419 514
420 reg = <0x80008500 0x100 /* internal registers */ 515 reg = <0x80008500 0x100 /* internal registers */
421 0x80008300 0x8>; /* config space access registers */ 516 0x80008300 0x8>; /* config space access registers */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-07 23:10:07 -0400