diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/cache.h | 16 | ||||
-rw-r--r-- | arch/arm/include/asm/page.h | 7 | ||||
-rw-r--r-- | arch/arm/mach-mx2/clock_imx21.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-mx2/clock_imx27.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-mx3/clock-imx35.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-mx3/clock.c | 2 | ||||
-rw-r--r-- | arch/arm/mm/proc-v7.S | 36 |
7 files changed, 45 insertions, 22 deletions
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index cb7a9e97fd7e..feaa75f0013e 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h | |||
@@ -7,4 +7,20 @@ | |||
7 | #define L1_CACHE_SHIFT 5 | 7 | #define L1_CACHE_SHIFT 5 |
8 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) | 8 | #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) |
9 | 9 | ||
10 | /* | ||
11 | * Memory returned by kmalloc() may be used for DMA, so we must make | ||
12 | * sure that all such allocations are cache aligned. Otherwise, | ||
13 | * unrelated code may cause parts of the buffer to be read into the | ||
14 | * cache before the transfer is done, causing old data to be seen by | ||
15 | * the CPU. | ||
16 | */ | ||
17 | #define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES | ||
18 | |||
19 | /* | ||
20 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. | ||
21 | */ | ||
22 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | ||
23 | #define ARCH_SLAB_MINALIGN 8 | ||
24 | #endif | ||
25 | |||
10 | #endif | 26 | #endif |
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index e6eb8a67b807..7b522770f29d 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h | |||
@@ -202,13 +202,6 @@ typedef struct page *pgtable_t; | |||
202 | (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ | 202 | (((current->personality & READ_IMPLIES_EXEC) ? VM_EXEC : 0) | \ |
203 | VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) | 203 | VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) |
204 | 204 | ||
205 | /* | ||
206 | * With EABI on ARMv5 and above we must have 64-bit aligned slab pointers. | ||
207 | */ | ||
208 | #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) | ||
209 | #define ARCH_SLAB_MINALIGN 8 | ||
210 | #endif | ||
211 | |||
212 | #include <asm-generic/page.h> | 205 | #include <asm-generic/page.h> |
213 | 206 | ||
214 | #endif | 207 | #endif |
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c index 999d013e06e3..e4b08ca804ea 100644 --- a/arch/arm/mach-mx2/clock_imx21.c +++ b/arch/arm/mach-mx2/clock_imx21.c | |||
@@ -890,7 +890,7 @@ static struct clk clko_clk = { | |||
890 | .con_id = n, \ | 890 | .con_id = n, \ |
891 | .clk = &c, \ | 891 | .clk = &c, \ |
892 | }, | 892 | }, |
893 | static struct clk_lookup lookups[] __initdata = { | 893 | static struct clk_lookup lookups[] = { |
894 | /* It's unlikely that any driver wants one of them directly: | 894 | /* It's unlikely that any driver wants one of them directly: |
895 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) | 895 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) |
896 | _REGISTER_CLOCK(NULL, "ckil", ckil_clk) | 896 | _REGISTER_CLOCK(NULL, "ckil", ckil_clk) |
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index 3f7280c490f0..2c971442f3f2 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c | |||
@@ -621,7 +621,7 @@ DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); | |||
621 | .clk = &c, \ | 621 | .clk = &c, \ |
622 | }, | 622 | }, |
623 | 623 | ||
624 | static struct clk_lookup lookups[] __initdata = { | 624 | static struct clk_lookup lookups[] = { |
625 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | 625 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
626 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | 626 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
627 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | 627 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c index 53a112d4e04a..3c1e06f56dd6 100644 --- a/arch/arm/mach-mx3/clock-imx35.c +++ b/arch/arm/mach-mx3/clock-imx35.c | |||
@@ -404,7 +404,7 @@ DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | |||
404 | .clk = &c, \ | 404 | .clk = &c, \ |
405 | }, | 405 | }, |
406 | 406 | ||
407 | static struct clk_lookup lookups[] __initdata = { | 407 | static struct clk_lookup lookups[] = { |
408 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | 408 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) |
409 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | 409 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
410 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | 410 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) |
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index 9957a11533a4..a68fcf981edf 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c | |||
@@ -516,7 +516,7 @@ DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); | |||
516 | .clk = &c, \ | 516 | .clk = &c, \ |
517 | }, | 517 | }, |
518 | 518 | ||
519 | static struct clk_lookup lookups[] __initdata = { | 519 | static struct clk_lookup lookups[] = { |
520 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | 520 | _REGISTER_CLOCK(NULL, "emi", emi_clk) |
521 | _REGISTER_CLOCK(NULL, "cspi", cspi1_clk) | 521 | _REGISTER_CLOCK(NULL, "cspi", cspi1_clk) |
522 | _REGISTER_CLOCK(NULL, "cspi", cspi2_clk) | 522 | _REGISTER_CLOCK(NULL, "cspi", cspi2_clk) |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 3397f1e64d76..a08d9d2380d3 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -184,23 +184,37 @@ __v7_setup: | |||
184 | stmia r12, {r0-r5, r7, r9, r11, lr} | 184 | stmia r12, {r0-r5, r7, r9, r11, lr} |
185 | bl v7_flush_dcache_all | 185 | bl v7_flush_dcache_all |
186 | ldmia r12, {r0-r5, r7, r9, r11, lr} | 186 | ldmia r12, {r0-r5, r7, r9, r11, lr} |
187 | |||
188 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register | ||
189 | and r10, r0, #0xff000000 @ ARM? | ||
190 | teq r10, #0x41000000 | ||
191 | bne 2f | ||
192 | and r5, r0, #0x00f00000 @ variant | ||
193 | and r6, r0, #0x0000000f @ revision | ||
194 | orr r0, r6, r5, lsr #20-4 @ combine variant and revision | ||
195 | |||
187 | #ifdef CONFIG_ARM_ERRATA_430973 | 196 | #ifdef CONFIG_ARM_ERRATA_430973 |
188 | mrc p15, 0, r10, c1, c0, 1 @ read aux control register | 197 | teq r5, #0x00100000 @ only present in r1p* |
189 | orr r10, r10, #(1 << 6) @ set IBE to 1 | 198 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
190 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register | 199 | orreq r10, r10, #(1 << 6) @ set IBE to 1 |
200 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | ||
191 | #endif | 201 | #endif |
192 | #ifdef CONFIG_ARM_ERRATA_458693 | 202 | #ifdef CONFIG_ARM_ERRATA_458693 |
193 | mrc p15, 0, r10, c1, c0, 1 @ read aux control register | 203 | teq r0, #0x20 @ only present in r2p0 |
194 | orr r10, r10, #(1 << 5) @ set L1NEON to 1 | 204 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
195 | orr r10, r10, #(1 << 9) @ set PLDNOP to 1 | 205 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 |
196 | mcr p15, 0, r10, c1, c0, 1 @ write aux control register | 206 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 |
207 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | ||
197 | #endif | 208 | #endif |
198 | #ifdef CONFIG_ARM_ERRATA_460075 | 209 | #ifdef CONFIG_ARM_ERRATA_460075 |
199 | mrc p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register | 210 | teq r0, #0x20 @ only present in r2p0 |
200 | orr r10, r10, #(1 << 22) @ set the Write Allocate disable bit | 211 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
201 | mcr p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | 212 | tsteq r10, #1 << 22 |
213 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit | ||
214 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | ||
202 | #endif | 215 | #endif |
203 | mov r10, #0 | 216 | |
217 | 2: mov r10, #0 | ||
204 | #ifdef HARVARD_CACHE | 218 | #ifdef HARVARD_CACHE |
205 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | 219 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate |
206 | #endif | 220 | #endif |