aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig72
-rw-r--r--arch/mips/kernel/traps.c15
2 files changed, 53 insertions, 34 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 002845e820f3..05663e5ddd39 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -308,6 +308,7 @@ config MIPS_ATLAS
308 select SYS_SUPPORTS_64BIT_KERNEL 308 select SYS_SUPPORTS_64BIT_KERNEL
309 select SYS_SUPPORTS_BIG_ENDIAN 309 select SYS_SUPPORTS_BIG_ENDIAN
310 select SYS_SUPPORTS_LITTLE_ENDIAN 310 select SYS_SUPPORTS_LITTLE_ENDIAN
311 select SYS_SUPPORTS_MULTITHREADING if EXPERIMENTAL
311 help 312 help
312 This enables support for the MIPS Technologies Atlas evaluation 313 This enables support for the MIPS Technologies Atlas evaluation
313 board. 314 board.
@@ -336,6 +337,7 @@ config MIPS_MALTA
336 select SYS_SUPPORTS_64BIT_KERNEL 337 select SYS_SUPPORTS_64BIT_KERNEL
337 select SYS_SUPPORTS_BIG_ENDIAN 338 select SYS_SUPPORTS_BIG_ENDIAN
338 select SYS_SUPPORTS_LITTLE_ENDIAN 339 select SYS_SUPPORTS_LITTLE_ENDIAN
340 select SYS_SUPPORTS_MULTITHREADING
339 help 341 help
340 This enables support for the MIPS Technologies Malta evaluation 342 This enables support for the MIPS Technologies Malta evaluation
341 board. 343 board.
@@ -1495,34 +1497,57 @@ config SIBYTE_DMA_PAGEOPS
1495config CPU_HAS_PREFETCH 1497config CPU_HAS_PREFETCH
1496 bool 1498 bool
1497 1499
1498config MIPS_MT
1499 bool "Enable MIPS MT"
1500 depends on CPU_MIPS32_R2
1501 #depends on CPU_MIPS64_R2 # later ...
1502
1503choice 1500choice
1504 prompt "MIPS MT options" 1501 prompt "MIPS MT options"
1505 depends on MIPS_MT 1502
1503config MIPS_MT_DISABLED
1504 bool "Disable multithreading support."
1505 help
1506 Use this option if your workload can't take advantage of
1507 MIPS hardware multithreading support. On systems that don't have
1508 the option of an MT-enabled processor this option will be the only
1509 option in this menu.
1506 1510
1507config MIPS_MT_SMTC 1511config MIPS_MT_SMTC
1508 bool "SMTC: Use all TCs on all VPEs for SMP" 1512 bool "SMTC: Use all TCs on all VPEs for SMP"
1513 depends on CPU_MIPS32_R2
1514 #depends on CPU_MIPS64_R2 # once there is hardware ...
1515 depends on SYS_SUPPORTS_MULTITHREADING
1509 select CPU_MIPSR2_IRQ_VI 1516 select CPU_MIPSR2_IRQ_VI
1510 select CPU_MIPSR2_SRS 1517 select CPU_MIPSR2_SRS
1518 select MIPS_MT
1511 select SMP 1519 select SMP
1520 help
1521 This is a kernel model which is known a SMTC or lately has been
1522 marketesed into SMVP.
1512 1523
1513config MIPS_MT_SMP 1524config MIPS_MT_SMP
1514 bool "Use 1 TC on each available VPE for SMP" 1525 bool "Use 1 TC on each available VPE for SMP"
1526 depends on SYS_SUPPORTS_MULTITHREADING
1527 select CPU_MIPSR2_IRQ_VI
1528 select CPU_MIPSR2_SRS
1529 select MIPS_MT
1515 select SMP 1530 select SMP
1531 help
1532 This is a kernel model which is also known a VSMP or lately
1533 has been marketesed into SMVP.
1516 1534
1517config MIPS_VPE_LOADER 1535config MIPS_VPE_LOADER
1518 bool "VPE loader support." 1536 bool "VPE loader support."
1519 depends on MIPS_MT 1537 depends on SYS_SUPPORTS_MULTITHREADING
1538 select MIPS_MT
1520 help 1539 help
1521 Includes a loader for loading an elf relocatable object 1540 Includes a loader for loading an elf relocatable object
1522 onto another VPE and running it. 1541 onto another VPE and running it.
1523 1542
1524endchoice 1543endchoice
1525 1544
1545config MIPS_MT
1546 bool
1547
1548config SYS_SUPPORTS_MULTITHREADING
1549 bool
1550
1526config MIPS_MT_FPAFF 1551config MIPS_MT_FPAFF
1527 bool "Dynamic FPU affinity for FP-intensive threads" 1552 bool "Dynamic FPU affinity for FP-intensive threads"
1528 depends on MIPS_MT 1553 depends on MIPS_MT
@@ -1579,32 +1604,23 @@ config CPU_HAS_LLSC
1579config CPU_HAS_WB 1604config CPU_HAS_WB
1580 bool 1605 bool
1581 1606
1607#
1608# Vectored interrupt mode is an R2 feature
1609#
1582config CPU_MIPSR2_IRQ_VI 1610config CPU_MIPSR2_IRQ_VI
1583 bool "Vectored interrupt mode" 1611 bool
1584 depends on CPU_MIPSR2
1585 help
1586 Vectored interrupt mode allowing faster dispatching of interrupts.
1587 The board support code needs to be written to take advantage of this
1588 mode. Compatibility code is included to allow the kernel to run on
1589 a CPU that does not support vectored interrupts. It's safe to
1590 say Y here.
1591 1612
1613#
1614# Extended interrupt mode is an R2 feature
1615#
1592config CPU_MIPSR2_IRQ_EI 1616config CPU_MIPSR2_IRQ_EI
1593 bool "External interrupt controller mode" 1617 bool
1594 depends on CPU_MIPSR2
1595 help
1596 Extended interrupt mode takes advantage of an external interrupt
1597 controller to allow fast dispatching from many possible interrupt
1598 sources. Say N unless you know that external interrupt support is
1599 required.
1600 1618
1619#
1620# Shadow registers are an R2 feature
1621#
1601config CPU_MIPSR2_SRS 1622config CPU_MIPSR2_SRS
1602 bool "Make shadow set registers available for interrupt handlers" 1623 bool
1603 depends on CPU_MIPSR2_IRQ_VI || CPU_MIPSR2_IRQ_EI
1604 help
1605 Allow the kernel to use shadow register sets for fast interrupts.
1606 Interrupt handlers must be specially written to use shadow sets.
1607 Say N unless you know that shadow register set upport is needed.
1608 1624
1609config CPU_HAS_SYNC 1625config CPU_HAS_SYNC
1610 bool 1626 bool
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ad16eceb24dd..67971938a2cb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1050,7 +1050,7 @@ void *set_except_vector(int n, void *addr)
1050 return (void *)old_handler; 1050 return (void *)old_handler;
1051} 1051}
1052 1052
1053#ifdef CONFIG_CPU_MIPSR2 1053#ifdef CONFIG_CPU_MIPSR2_SRS
1054/* 1054/*
1055 * MIPSR2 shadow register set allocation 1055 * MIPSR2 shadow register set allocation
1056 * FIXME: SMP... 1056 * FIXME: SMP...
@@ -1069,11 +1069,9 @@ static struct shadow_registers {
1069 1069
1070static void mips_srs_init(void) 1070static void mips_srs_init(void)
1071{ 1071{
1072#ifdef CONFIG_CPU_MIPSR2_SRS
1073 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1; 1072 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1074 printk(KERN_INFO "%d MIPSR2 register sets available\n", 1073 printk(KERN_INFO "%d MIPSR2 register sets available\n",
1075 shadow_registers.sr_supported); 1074 shadow_registers.sr_supported);
1076#endif
1077 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */ 1075 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1078} 1076}
1079 1077
@@ -1198,7 +1196,14 @@ void *set_vi_handler(int n, void *addr)
1198{ 1196{
1199 return set_vi_srs_handler(n, addr, 0); 1197 return set_vi_srs_handler(n, addr, 0);
1200} 1198}
1201#endif 1199
1200#else
1201
1202static inline void mips_srs_init(void)
1203{
1204}
1205
1206#endif /* CONFIG_CPU_MIPSR2_SRS */
1202 1207
1203/* 1208/*
1204 * This is used by native signal handling 1209 * This is used by native signal handling
@@ -1388,9 +1393,7 @@ void __init trap_init(void)
1388 else 1393 else
1389 ebase = CAC_BASE; 1394 ebase = CAC_BASE;
1390 1395
1391#ifdef CONFIG_CPU_MIPSR2
1392 mips_srs_init(); 1396 mips_srs_init();
1393#endif
1394 1397
1395 per_cpu_trap_init(); 1398 per_cpu_trap_init();
1396 1399