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-rw-r--r--arch/arm/mach-pxa/include/mach/regs-ssp.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h
index 3c04cde2cf1f..cf31986f6f05 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ssp.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h
@@ -41,6 +41,9 @@
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) 41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ 42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ 43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
44#endif
45
46#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
44#define SSCR0_EDSS (1 << 20) /* Extended data size select */ 47#define SSCR0_EDSS (1 << 20) /* Extended data size select */
45#define SSCR0_NCS (1 << 21) /* Network clock select */ 48#define SSCR0_NCS (1 << 21) /* Network clock select */
46#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */ 49#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */