406 files changed, 13597 insertions, 8545 deletions

diff --git a/arch/alpha/include/asm/pgtable.h b/arch/alpha/include/asm/pgtable.h
index 3f0c59f6d8aa..71a243294142 100644
--- a/arch/alpha/include/asm/pgtable.h
+++ b/arch/alpha/include/asm/pgtable.h
@@ -329,7 +329,7 @@ extern pgd_t swapper_pg_dir[1024];
  * tables contain all the necessary information.
  */
 extern inline void update_mmu_cache(struct vm_area_struct * vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 184a6bd54825..3b181284970f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -12,6 +12,7 @@ config ARM
         select HAVE_IDE
         select RTC_LIB
         select SYS_SUPPORTS_APM_EMULATION
+        select GENERIC_ATOMIC64 if (!CPU_32v6K)
         select HAVE_OPROFILE
         select HAVE_ARCH_KGDB
         select HAVE_KPROBES if (!XIP_KERNEL)
@@ -20,6 +21,8 @@ config ARM
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
+        select HAVE_PERF_EVENTS
+        select PERF_USE_VMALLOC
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -52,6 +55,9 @@ config HAVE_TCM
         bool
         select GENERIC_ALLOCATOR
 
+config HAVE_PROC_CPU
+        bool
+
 config NO_IOPORT
         bool
 
@@ -161,6 +167,11 @@ config ARCH_MTD_XIP
 config GENERIC_HARDIRQS_NO__DO_IRQ
         def_bool y
 
+config ARM_L1_CACHE_SHIFT_6
+        bool
+        help
+          Setting ARM L1 cache line size to 64 Bytes.
+
 if OPROFILE
 
 config OPROFILE_ARMV6
@@ -550,10 +561,20 @@ config ARCH_W90X900
           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 
+config ARCH_NUC93X
+        bool "Nuvoton NUC93X CPU"
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        help
+          Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
+          low-power and high performance MPEG-4/JPEG multimedia controller chip.
+
 config ARCH_PNX4008
         bool "Philips Nexperia PNX4008 Mobile"
         select CPU_ARM926T
         select HAVE_CLK
+        select COMMON_CLKDEV
         help
           This enables support for Philips PNX4008 mobile platform.
 
@@ -638,6 +659,7 @@ config ARCH_S5PC1XX
         select GENERIC_GPIO
         select HAVE_CLK
         select CPU_V7
+        select ARM_L1_CACHE_SHIFT_6
         help
           Samsung S5PC1XX series based systems
 
@@ -785,6 +807,8 @@ source "arch/arm/plat-nomadik/Kconfig"
 
 source "arch/arm/mach-ns9xxx/Kconfig"
 
+source "arch/arm/mach-nuc93x/Kconfig"
+
 source "arch/arm/plat-omap/Kconfig"
 
 source "arch/arm/mach-omap1/Kconfig"
@@ -867,6 +891,11 @@ config XSCALE_PMU
         depends on CPU_XSCALE && !XSCALE_PMU_TIMER
         default y
 
+config CPU_HAS_PMU
+        depends on CPU_V6 || CPU_V7 || XSCALE_PMU
+        default y
+        bool
+
 if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
@@ -921,6 +950,19 @@ config ARM_ERRATA_460075
           ACTLR register. Note that setting specific bits in the ACTLR register
           may not be available in non-secure mode.
 
+config PL310_ERRATA_588369
+        bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
+        depends on CACHE_L2X0 && ARCH_OMAP4
+        help
+           The PL310 L2 cache controller implements three types of Clean &
+           Invalidate maintenance operations: by Physical Address
+           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+           They are architecturally defined to behave as the execution of a
+           clean operation followed immediately by an invalidate operation,
+           both performing to the same memory location. This functionality
+           is not correctly implemented in PL310 as clean lines are not
+           invalidated as a result of these operations. Note that this errata
+           uses Texas Instrument's secure monitor api.
 endmenu
 
 source "arch/arm/common/Kconfig"
@@ -1171,6 +1213,14 @@ config HIGHPTE
         depends on HIGHMEM
         depends on !OUTER_CACHE
 
+config HW_PERF_EVENTS
+        bool "Enable hardware performance counter support for perf events"
+        depends on PERF_EVENTS && CPU_HAS_PMU && (CPU_V6 || CPU_V7)
+        default y
+        help
+          Enable hardware performance counter support for perf events. If
+          disabled, perf events will use software events only.
+
 source "mm/Kconfig"
 
 config LEDS
@@ -1230,6 +1280,7 @@ config ALIGNMENT_TRAP
         bool
         depends on CPU_CP15_MMU
         default y if !ARCH_EBSA110
+        select HAVE_PROC_CPU if PROC_FS
         help
           ARM processors cannot fetch/store information which is not
           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 356d702c0808..81f54ca30788 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -171,6 +171,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)            := ux500
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
+machine-$(CONFIG_ARCH_NUC93X)           := nuc93x
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
 
 # Platform directory name.  This list is sorted alphanumerically
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 2d4d88ba73bf..97c89e7de7d3 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -5,7 +5,7 @@
 #
 
 HEAD    = head.o
-OBJS    = misc.o
+OBJS    = misc.o decompress.o
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
 
 #
@@ -106,10 +106,6 @@ lib1funcs = $(obj)/lib1funcs.o
 $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
         $(call cmd,shipped)
 
-# Don't allow any static data in misc.o, which
-# would otherwise mess up our GOT table
-CFLAGS_misc.o := -Dstatic=
-
 $(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
                 $(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
         $(call if_changed,ld)
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
new file mode 100644
index 000000000000..0da382f33157
--- /dev/null
+++ b/arch/arm/boot/compressed/decompress.c
@@ -0,0 +1,45 @@
+#define _LINUX_STRING_H_
+
+#include <linux/compiler.h>     /* for inline */
+#include <linux/types.h>        /* for size_t */
+#include <linux/stddef.h>       /* for NULL */
+#include <linux/linkage.h>
+#include <asm/string.h>
+
+extern unsigned long free_mem_ptr;
+extern unsigned long free_mem_end_ptr;
+extern void error(char *);
+
+#define STATIC static
+
+#define ARCH_HAS_DECOMP_WDOG
+
+/* Diagnostic functions */
+#ifdef DEBUG
+#  define Assert(cond,msg) {if(!(cond)) error(msg);}
+#  define Trace(x) fprintf x
+#  define Tracev(x) {if (verbose) fprintf x ;}
+#  define Tracevv(x) {if (verbose>1) fprintf x ;}
+#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
+#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
+#else
+#  define Assert(cond,msg)
+#  define Trace(x)
+#  define Tracev(x)
+#  define Tracevv(x)
+#  define Tracec(c,x)
+#  define Tracecv(c,x)
+#endif
+
+#ifdef CONFIG_KERNEL_GZIP
+#include "../../../../lib/decompress_inflate.c"
+#endif
+
+#ifdef CONFIG_KERNEL_LZO
+#include "../../../../lib/decompress_unlzo.c"
+#endif
+
+void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
+{
+        decompress(input, len, NULL, NULL, output, NULL, error);
+}
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4fddc509e78e..99b75aa1c2ec 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -22,13 +22,13 @@
 #if defined(CONFIG_DEBUG_ICEDCC)
 
 #ifdef CONFIG_CPU_V6
-                .macro  loadsp, rb
+                .macro  loadsp, rb, tmp
                 .endm
                 .macro  writeb, ch, rb
                 mcr     p14, 0, \ch, c0, c5, 0
                 .endm
 #elif defined(CONFIG_CPU_V7)
-                .macro  loadsp, rb
+                .macro  loadsp, rb, tmp
                 .endm
                 .macro  writeb, ch, rb
 wait:           mrc     p14, 0, pc, c0, c1, 0
@@ -36,13 +36,13 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
                 mcr     p14, 0, \ch, c0, c5, 0
                 .endm
 #elif defined(CONFIG_CPU_XSCALE)
-                .macro  loadsp, rb
+                .macro  loadsp, rb, tmp
                 .endm
                 .macro  writeb, ch, rb
                 mcr     p14, 0, \ch, c8, c0, 0
                 .endm
 #else
-                .macro  loadsp, rb
+                .macro  loadsp, rb, tmp
                 .endm
                 .macro  writeb, ch, rb
                 mcr     p14, 0, \ch, c1, c0, 0
@@ -58,7 +58,7 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
                 .endm
 
 #if defined(CONFIG_ARCH_SA1100)
-                .macro  loadsp, rb
+                .macro  loadsp, rb, tmp
                 mov     \rb, #0x80000000        @ physical base address
 #ifdef CONFIG_DEBUG_LL_SER3
                 add     \rb, \rb, #0x00050000   @ Ser3
@@ -67,13 +67,13 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 #endif
                 .endm
 #elif defined(CONFIG_ARCH_S3C2410)
-                .macro loadsp, rb
+                .macro loadsp, rb, tmp
                 mov     \rb, #0x50000000
                 add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
                 .endm
 #else
-                .macro  loadsp, rb
-                addruart \rb
+                .macro  loadsp, rb, tmp
+                addruart \rb, \tmp
                 .endm
 #endif
 #endif
@@ -1025,7 +1025,7 @@ phex:		adr	r3, phexbuf
                 strb    r2, [r3, r1]
                 b       1b
 
-puts:           loadsp  r3
+puts:           loadsp  r3, r1
 1:              ldrb    r2, [r0], #1
                 teq     r2, #0
                 moveq   pc, lr
@@ -1042,7 +1042,7 @@ puts:		loadsp	r3
 putc:
                 mov     r2, r0
                 mov     r0, #0
-                loadsp  r3
+                loadsp  r3, r1
                 b       2b
 
 memdump:        mov     r12, r0
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 56a0d116d271..d32bc71c1f78 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -23,8 +23,8 @@ unsigned int __machine_arch_type;
 #include <linux/compiler.h>     /* for inline */
 #include <linux/types.h>        /* for size_t */
 #include <linux/stddef.h>       /* for NULL */
-#include <asm/string.h>
 #include <linux/linkage.h>
+#include <asm/string.h>
 
 #include <asm/unaligned.h>
 
@@ -117,57 +117,7 @@ static void putstr(const char *ptr)
 
 #endif
 
-#define __ptr_t void *
-
-#define memzero(s,n) __memzero(s,n)
-
-/*
- * Optimised C version of memzero for the ARM.
- */
-void __memzero (__ptr_t s, size_t n)
-{
-        union { void *vp; unsigned long *ulp; unsigned char *ucp; } u;
-        int i;
-
-        u.vp = s;
-
-        for (i = n >> 5; i > 0; i--) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 4) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 3) {
-                *u.ulp++ = 0;
-                *u.ulp++ = 0;
-        }
-
-        if (n & 1 << 2)
-                *u.ulp++ = 0;
-
-        if (n & 1 << 1) {
-                *u.ucp++ = 0;
-                *u.ucp++ = 0;
-        }
-
-        if (n & 1)
-                *u.ucp++ = 0;
-}
-
-static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
-                            size_t __n)
+void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
         int i = 0;
         unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
@@ -204,59 +154,20 @@ static inline __ptr_t memcpy(__ptr_t __dest, __const __ptr_t __src,
 /*
  * gzip delarations
  */
-#define STATIC static
-
-/* Diagnostic functions */
-#ifdef DEBUG
-#  define Assert(cond,msg) {if(!(cond)) error(msg);}
-#  define Trace(x) fprintf x
-#  define Tracev(x) {if (verbose) fprintf x ;}
-#  define Tracevv(x) {if (verbose>1) fprintf x ;}
-#  define Tracec(c,x) {if (verbose && (c)) fprintf x ;}
-#  define Tracecv(c,x) {if (verbose>1 && (c)) fprintf x ;}
-#else
-#  define Assert(cond,msg)
-#  define Trace(x)
-#  define Tracev(x)
-#  define Tracevv(x)
-#  define Tracec(c,x)
-#  define Tracecv(c,x)
-#endif
-
-static void error(char *m);
-
 extern char input_data[];
 extern char input_data_end[];
 
-static unsigned char *output_data;
-static unsigned long output_ptr;
-
-static void error(char *m);
+unsigned char *output_data;
+unsigned long output_ptr;
 
-static void putstr(const char *);
-
-static unsigned long free_mem_ptr;
-static unsigned long free_mem_end_ptr;
-
-#ifdef STANDALONE_DEBUG
-#define NO_INFLATE_MALLOC
-#endif
-
-#define ARCH_HAS_DECOMP_WDOG
-
-#ifdef CONFIG_KERNEL_GZIP
-#include "../../../../lib/decompress_inflate.c"
-#endif
-
-#ifdef CONFIG_KERNEL_LZO
-#include "../../../../lib/decompress_unlzo.c"
-#endif
+unsigned long free_mem_ptr;
+unsigned long free_mem_end_ptr;
 
 #ifndef arch_error
 #define arch_error(x)
 #endif
 
-static void error(char *x)
+void error(char *x)
 {
         arch_error(x);
 
@@ -272,6 +183,8 @@ asmlinkage void __div0(void)
         error("Attempting division by 0!");
 }
 
+extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
+
 #ifndef STANDALONE_DEBUG
 
 unsigned long
@@ -292,8 +205,8 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
         output_ptr = get_unaligned_le32(tmp);
 
         putstr("Uncompressing Linux...");
-        decompress(input_data, input_data_end - input_data,
-                        NULL, NULL, output_data, NULL, error);
+        do_decompress(input_data, input_data_end - input_data,
+                        output_data, error);
         putstr(" done, booting the kernel.\n");
         return output_ptr;
 }
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index a5924b9b88bd..7ca9ecff652f 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -14,6 +14,13 @@ SECTIONS
   /DISCARD/ : {
     *(.ARM.exidx*)
     *(.ARM.extab*)
+    /*
+     * Discard any r/w data - this produces a link error if we have any,
+     * which is required for PIC decompression.  Local data generates
+     * GOTOFF relocations, which prevents it being relocated independently
+     * of the text/got segments.
+     */
+    *(.data)
   }
 
   . = TEXT_START;
@@ -40,7 +47,6 @@ SECTIONS
   .got                  : { *(.got) }
   _got_end = .;
   .got.plt              : { *(.got.plt) }
-  .data                 : { *(.data) }
   _edata = .;
 
   . = BSS_START;
diff --git a/arch/arm/common/clkdev.c b/arch/arm/common/clkdev.c
index aae5bc01acc8..446b696196e3 100644
--- a/arch/arm/common/clkdev.c
+++ b/arch/arm/common/clkdev.c
@@ -99,6 +99,16 @@ void clkdev_add(struct clk_lookup *cl)
 }
 EXPORT_SYMBOL(clkdev_add);
 
+void __init clkdev_add_table(struct clk_lookup *cl, size_t num)
+{
+        mutex_lock(&clocks_mutex);
+        while (num--) {
+                list_add_tail(&cl->node, &clocks);
+                cl++;
+        }
+        mutex_unlock(&clocks_mutex);
+}
+
 #define MAX_DEV_ID      20
 #define MAX_CON_ID      16
 
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index cc32c1e54a59..cc0a932bbea9 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -277,7 +277,7 @@ static inline dma_addr_t map_single(struct device *dev, void *ptr, size_t size,
                  * We don't need to sync the DMA buffer since
                  * it was allocated via the coherent allocators.
                  */
-                dma_cache_maint(ptr, size, dir);
+                __dma_single_cpu_to_dev(ptr, size, dir);
         }
 
         return dma_addr;
@@ -315,6 +315,8 @@ static inline void unmap_single(struct device *dev, dma_addr_t dma_addr,
                         __cpuc_flush_dcache_area(ptr, size);
                 }
                 free_safe_buffer(dev->archdata.dmabounce, buf);
+        } else {
+                __dma_single_dev_to_cpu(dma_to_virt(dev, dma_addr), size, dir);
         }
 }
 
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index f232941de8ab..1cf999ade4bc 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -18,6 +18,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
+
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
@@ -28,48 +29,6 @@
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
 
-static void vic_ack_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-        /* moreover, clear the soft-triggered, in case it was the reason */
-        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
-}
-
-static void vic_mask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
-}
-
-static void vic_unmask_irq(unsigned int irq)
-{
-        void __iomem *base = get_irq_chip_data(irq);
-        irq &= 31;
-        writel(1 << irq, base + VIC_INT_ENABLE);
-}
-
-/**
- * vic_init2 - common initialisation code
- * @base: Base of the VIC.
- *
- * Common initialisation code for registeration
- * and resume.
-*/
-static void vic_init2(void __iomem *base)
-{
-        int i;
-
-        for (i = 0; i < 16; i++) {
-                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                writel(VIC_VECT_CNTL_ENABLE | i, reg);
-        }
-
-        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-}
-
 #if defined(CONFIG_PM)
 /**
  * struct vic_device - VIC PM device
@@ -99,13 +58,34 @@ struct vic_device {
 /* we cannot allocate memory when VICs are initially registered */
 static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
 
+static int vic_id;
+
 static inline struct vic_device *to_vic(struct sys_device *sys)
 {
         return container_of(sys, struct vic_device, sysdev);
 }
+#endif /* CONFIG_PM */
 
-static int vic_id;
+/**
+ * vic_init2 - common initialisation code
+ * @base: Base of the VIC.
+ *
+ * Common initialisation code for registeration
+ * and resume.
+*/
+static void vic_init2(void __iomem *base)
+{
+        int i;
+
+        for (i = 0; i < 16; i++) {
+                void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                writel(VIC_VECT_CNTL_ENABLE | i, reg);
+        }
+
+        writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+}
 
+#if defined(CONFIG_PM)
 static int vic_class_resume(struct sys_device *dev)
 {
         struct vic_device *vic = to_vic(dev);
@@ -159,31 +139,6 @@ struct sysdev_class vic_class = {
 };
 
 /**
- * vic_pm_register - Register a VIC for later power management control
- * @base: The base address of the VIC.
- * @irq: The base IRQ for the VIC.
- * @resume_sources: bitmask of interrupts allowed for resume sources.
- *
- * Register the VIC with the system device tree so that it can be notified
- * of suspend and resume requests and ensure that the correct actions are
- * taken to re-instate the settings on resume.
- */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
-{
-        struct vic_device *v;
-
-        if (vic_id >= ARRAY_SIZE(vic_devices))
-                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-        else {
-                v = &vic_devices[vic_id];
-                v->base = base;
-                v->resume_sources = resume_sources;
-                v->irq = irq;
-                vic_id++;
-        }
-}
-
-/**
  * vic_pm_init - initicall to register VIC pm
  *
  * This is called via late_initcall() to register
@@ -219,9 +174,60 @@ static int __init vic_pm_init(void)
 
         return 0;
 }
-
 late_initcall(vic_pm_init);
 
+/**
+ * vic_pm_register - Register a VIC for later power management control
+ * @base: The base address of the VIC.
+ * @irq: The base IRQ for the VIC.
+ * @resume_sources: bitmask of interrupts allowed for resume sources.
+ *
+ * Register the VIC with the system device tree so that it can be notified
+ * of suspend and resume requests and ensure that the correct actions are
+ * taken to re-instate the settings on resume.
+ */
+static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+{
+        struct vic_device *v;
+
+        if (vic_id >= ARRAY_SIZE(vic_devices))
+                printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
+        else {
+                v = &vic_devices[vic_id];
+                v->base = base;
+                v->resume_sources = resume_sources;
+                v->irq = irq;
+                vic_id++;
+        }
+}
+#else
+static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+#endif /* CONFIG_PM */
+
+static void vic_ack_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+        /* moreover, clear the soft-triggered, in case it was the reason */
+        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
+
+static void vic_mask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+}
+
+static void vic_unmask_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE);
+}
+
+#if defined(CONFIG_PM)
 static struct vic_device *vic_from_irq(unsigned int irq)
 {
         struct vic_device *v = vic_devices;
@@ -255,10 +261,7 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 
         return 0;
 }
-
 #else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
-
 #define vic_set_wake NULL
 #endif /* CONFIG_PM */
 
@@ -270,9 +273,62 @@ static struct irq_chip vic_chip = {
         .set_wake = vic_set_wake,
 };
 
-/* The PL190 cell from ARM has been modified by ST, so handle both here */
-static void vik_init_st(void __iomem *base, unsigned int irq_start,
-                         u32 vic_sources);
+/*
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
+                                u32 vic_sources)
+{
+        unsigned int i;
+        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+
+        /* Disable all interrupts initially. */
+
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
+
+        /*
+         * Make sure we clear all existing interrupts. The vector registers
+         * in this cell are after the second block of general registers,
+         * so we can address them using standard offsets, but only from
+         * the second base address, which is 0x20 in the page
+         */
+        if (vic_2nd_block) {
+                writel(0, base + VIC_PL190_VECT_ADDR);
+                for (i = 0; i < 19; i++) {
+                        unsigned int value;
+
+                        value = readl(base + VIC_PL190_VECT_ADDR);
+                        writel(value, base + VIC_PL190_VECT_ADDR);
+                }
+                /* ST has 16 vectors as well, but we don't enable them by now */
+                for (i = 0; i < 16; i++) {
+                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                        writel(0, reg);
+                }
+
+                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+        }
+
+        for (i = 0; i < 32; i++) {
+                if (vic_sources & (1 << i)) {
+                        unsigned int irq = irq_start + i;
+
+                        set_irq_chip(irq, &vic_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+}
 
 /**
  * vic_init - initialise a vectored interrupt controller
@@ -299,7 +355,7 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
         switch(vendor) {
         case AMBA_VENDOR_ST:
-                vik_init_st(base, irq_start, vic_sources);
+                vic_init_st(base, irq_start, vic_sources);
                 return;
         default:
                 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
@@ -343,60 +399,3 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
         vic_pm_register(base, irq_start, resume_sources);
 }
-
-/*
- * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
- * The original cell has 32 interrupts, while the modified one has 64,
- * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
- * the probe function is called twice, with base set to offset 000
- *  and 020 within the page. We call this "second block".
- */
-static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
-                                u32 vic_sources)
-{
-        unsigned int i;
-        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
-
-        /* Disable all interrupts initially. */
-
-        writel(0, base + VIC_INT_SELECT);
-        writel(0, base + VIC_INT_ENABLE);
-        writel(~0, base + VIC_INT_ENABLE_CLEAR);
-        writel(0, base + VIC_IRQ_STATUS);
-        writel(0, base + VIC_ITCR);
-        writel(~0, base + VIC_INT_SOFT_CLEAR);
-
-        /*
-         * Make sure we clear all existing interrupts. The vector registers
-         * in this cell are after the second block of general registers,
-         * so we can address them using standard offsets, but only from
-         * the second base address, which is 0x20 in the page
-         */
-        if (vic_2nd_block) {
-                writel(0, base + VIC_PL190_VECT_ADDR);
-                for (i = 0; i < 19; i++) {
-                        unsigned int value;
-
-                        value = readl(base + VIC_PL190_VECT_ADDR);
-                        writel(value, base + VIC_PL190_VECT_ADDR);
-                }
-                /* ST has 16 vectors as well, but we don't enable them by now */
-                for (i = 0; i < 16; i++) {
-                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
-                        writel(0, reg);
-                }
-
-                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
-        }
-
-        for (i = 0; i < 32; i++) {
-                if (vic_sources & (1 << i)) {
-                        unsigned int irq = irq_start + i;
-
-                        set_irq_chip(irq, &vic_chip);
-                        set_irq_chip_data(irq, base);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-                }
-        }
-}
diff --git a/arch/arm/configs/at572d940hfek_defconfig b/arch/arm/configs/at572d940hfek_defconfig
new file mode 100644
index 000000000000..76d724b8041a
--- /dev/null
+++ b/arch/arm/configs/at572d940hfek_defconfig
@@ -0,0 +1,1640 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.28-rc7
+# Fri Dec  5 10:58:47 2008
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+# CONFIG_NO_IOPORT is not set
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION="-AT572D940HF"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+# CONFIG_TASK_DELAY_ACCT is not set
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+# CONFIG_CGROUP_NS is not set
+# CONFIG_CGROUP_FREEZER is not set
+# CONFIG_CGROUP_DEVICE is not set
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_USER_SCHED is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_CPUACCT=y
+# CONFIG_RESOURCE_COUNTERS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_COMPAT_BRK=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_MARKERS=y
+CONFIG_OPROFILE=m
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+CONFIG_BLK_DEV_IO_TRACE=y
+# CONFIG_LSF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_CLASSIC_RCU=y
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS7500 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IMX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_MSM is not set
+
+#
+# Boot options
+#
+
+#
+# Power management
+#
+
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_ARCH_AT572D940HF=y
+CONFIG_AT91_PMC_UNIT=y
+
+#
+# AT572D940HF Board Type
+#
+CONFIG_MACH_AT572D940HFEB=y
+
+#
+# AT91 Board Options
+#
+# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
+# CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16 is not set
+CONFIG_NUM_SERIAL=3
+
+#
+# AT91 Feature Selections
+#
+CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+# CONFIG_OUTER_CACHE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+CONFIG_ARCH_FLATMEM_HAS_HOLES=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_RESOURCES_64BIT=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_UNEVICTABLE_LRU=y
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="mem=48M console=ttyS0 initrd=0x21100000,3145728 root=/dev/ram0 rw ip=172.16.1.181"
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=m
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+
+#
+# Network testing
+#
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_TCPPROBE=m
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=m
+CONFIG_CAN_DEBUG_DEVICES=y
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+# CONFIG_IEEE80211_CRYPT_CCMP is not set
+# CONFIG_IEEE80211_CRYPT_TKIP is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=m
+CONFIG_MTD=m
+CONFIG_MTD_DEBUG=y
+CONFIG_MTD_DEBUG_VERBOSE=1
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_MTD_OOPS=m
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_GEN_PROBE=m
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_CFI_UTIL=m
+CONFIG_MTD_RAM=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_PHYSMAP_START=0x8000000
+CONFIG_MTD_PHYSMAP_LEN=0x4000000
+CONFIG_MTD_PHYSMAP_BANKWIDTH=2
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+CONFIG_MTD_PLATRAM=m
+
+#
+# Self-contained MTD device drivers
+#
+CONFIG_MTD_DATAFLASH=m
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+# CONFIG_MTD_DATAFLASH_OTP is not set
+CONFIG_MTD_M25P80=m
+CONFIG_M25PXX_USE_FAST_READ=y
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTDRAM_TOTAL_SIZE=4096
+CONFIG_MTDRAM_ERASE_SIZE=128
+CONFIG_MTD_BLOCK2MTD=m
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
+# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
+# CONFIG_MTD_NAND_ATMEL is not set
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_ALAUDA=m
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+CONFIG_MTD_UBI_GLUEBI=y
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+CONFIG_MISC_DEVICES=y
+CONFIG_ATMEL_TCLIB=y
+CONFIG_ATMEL_TCB_CLKSRC=y
+CONFIG_ATMEL_TCB_CLKSRC_BLOCK=0
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_ICS932S401 is not set
+CONFIG_ATMEL_SSC=m
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+CONFIG_SCSI_ISCSI_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_EQUALIZER=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_BROADCOM_PHY=m
+CONFIG_ICPLUS_PHY=m
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_FIXED_PHY is not set
+CONFIG_MDIO_BITBANG=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_SMC911X is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+
+#
+# Wireless LAN
+#
+CONFIG_WLAN_PRE80211=y
+CONFIG_STRIP=m
+CONFIG_WLAN_80211=y
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_DEBUG is not set
+CONFIG_USB_ZD1201=m
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_IWLWIFI_LEDS is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+# CONFIG_USB_NET_SMSC95XX is not set
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+CONFIG_USB_KC2190=y
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WAN is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=m
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_SUNKBD=m
+CONFIG_KEYBOARD_LKKBD=m
+CONFIG_KEYBOARD_XTKBD=m
+CONFIG_KEYBOARD_NEWTON=m
+CONFIG_KEYBOARD_STOWAWAY=m
+CONFIG_KEYBOARD_GPIO=m
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=m
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_LIFEBOOK=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+CONFIG_MOUSE_APPLETOUCH=m
+# CONFIG_MOUSE_BCM5974 is not set
+CONFIG_MOUSE_VSXXXAA=m
+CONFIG_MOUSE_GPIO=m
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_RISCOM8 is not set
+CONFIG_SPECIALIX=m
+CONFIG_RIO=m
+# CONFIG_RIO_OLDPCI is not set
+CONFIG_STALDRV=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_IPMI_HANDLER=m
+# CONFIG_IPMI_PANIC_EVENT is not set
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI=m
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+CONFIG_NVRAM=m
+CONFIG_R3964=m
+CONFIG_RAW_DRIVER=m
+CONFIG_MAX_RAW_DEVS=256
+CONFIG_TCG_TPM=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_I2C=m
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+CONFIG_DS1682=m
+# CONFIG_AT24 is not set
+CONFIG_SENSORS_EEPROM=m
+CONFIG_SENSORS_PCF8574=m
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+CONFIG_SENSORS_PCF8591=m
+CONFIG_SENSORS_MAX6875=m
+CONFIG_SENSORS_TSL2550=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_ATMEL=y
+CONFIG_SPI_BITBANG=m
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_AT25=m
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+# CONFIG_SND_PCM_OSS_PLUGINS is not set
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_DRIVERS=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+# CONFIG_SND_AT73C213 is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_CAIAQ=m
+CONFIG_SND_USB_CAIAQ_INPUT=y
+# CONFIG_SND_SOC is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=m
+# CONFIG_HID_DEBUG is not set
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB HID Boot Protocol drivers
+#
+CONFIG_USB_KBD=m
+CONFIG_USB_MOUSE=m
+
+#
+# Special HID drivers
+#
+CONFIG_HID_COMPAT=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_BRIGHT=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DELL=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_HID_SUNPLUS=m
+# CONFIG_THRUSTMASTER_FF is not set
+# CONFIG_ZEROPLUS_FF is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
+#
+
+#
+# see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+CONFIG_USB_STORAGE_KARMA=y
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_EZUSB=y
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP2101 is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_OTI6858 is not set
+CONFIG_USB_SERIAL_SPCP8X5=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+CONFIG_USB_SERIAL_DEBUG=m
+
+#
+# USB Miscellaneous drivers
+#
+CONFIG_USB_EMI62=m
+CONFIG_USB_EMI26=m
+CONFIG_USB_ADUTUX=m
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+CONFIG_USB_TEST=m
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=m
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_DEBUG_FS=y
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=m
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_MIDI_GADGET=m
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+CONFIG_MMC_SPI=m
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+# CONFIG_LEDS_PCA955X is not set
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+CONFIG_RTC_DRV_DS1305=y
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_JBD_DEBUG=y
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+CONFIG_REISERFS_CHECK=y
+CONFIG_REISERFS_PROC_INFO=y
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+CONFIG_GENERIC_ACL=y
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+CONFIG_NTFS_FS=m
+# CONFIG_NTFS_DEBUG is not set
+CONFIG_NTFS_RW=y
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=m
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_JFFS2_CMODE_NONE is not set
+# CONFIG_JFFS2_CMODE_PRIORITY is not set
+# CONFIG_JFFS2_CMODE_SIZE is not set
+CONFIG_JFFS2_CMODE_FAVOURLZO=y
+# CONFIG_UBIFS_FS is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_LDM_DEBUG=y
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+CONFIG_NLS_CODEPAGE_850=m
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+# CONFIG_DLM_DEBUG is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_GF128MUL=m
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=m
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=m
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+CONFIG_REED_SOLOMON=m
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/omap_4430sdp_defconfig b/arch/arm/configs/omap_4430sdp_defconfig
index 3de640ac294b..c48d7b893869 100644
--- a/arch/arm/configs/omap_4430sdp_defconfig
+++ b/arch/arm/configs/omap_4430sdp_defconfig
@@ -242,10 +242,13 @@ CONFIG_CPU_CP15_MMU=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_HAS_TLS_REG=y
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_PL310_ERRATA_588369=y
 CONFIG_ARM_GIC=y
 
 #
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index d0daeab2234e..e8ddec2cb158 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -235,6 +235,234 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 #define smp_mb__before_atomic_inc()     smp_mb()
 #define smp_mb__after_atomic_inc()      smp_mb()
 
+#ifndef CONFIG_GENERIC_ATOMIC64
+typedef struct {
+        u64 __aligned(8) counter;
+} atomic64_t;
+
+#define ATOMIC64_INIT(i) { (i) }
+
+static inline u64 atomic64_read(atomic64_t *v)
+{
+        u64 result;
+
+        __asm__ __volatile__("@ atomic64_read\n"
+"       ldrexd  %0, %H0, [%1]"
+        : "=&r" (result)
+        : "r" (&v->counter)
+        );
+
+        return result;
+}
+
+static inline void atomic64_set(atomic64_t *v, u64 i)
+{
+        u64 tmp;
+
+        __asm__ __volatile__("@ atomic64_set\n"
+"1:     ldrexd  %0, %H0, [%1]\n"
+"       strexd  %0, %2, %H2, [%1]\n"
+"       teq     %0, #0\n"
+"       bne     1b"
+        : "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline void atomic64_add(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        __asm__ __volatile__("@ atomic64_add\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       adds    %0, %0, %3\n"
+"       adc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_add_return\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       adds    %0, %0, %3\n"
+"       adc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline void atomic64_sub(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        __asm__ __volatile__("@ atomic64_sub\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, %3\n"
+"       sbc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_sub_return\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, %3\n"
+"       sbc     %H0, %H0, %H3\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
+{
+        u64 oldval;
+        unsigned long res;
+
+        smp_mb();
+
+        do {
+                __asm__ __volatile__("@ atomic64_cmpxchg\n"
+                "ldrexd         %1, %H1, [%2]\n"
+                "mov            %0, #0\n"
+                "teq            %1, %3\n"
+                "teqeq          %H1, %H3\n"
+                "strexdeq       %0, %4, %H4, [%2]"
+                : "=&r" (res), "=&r" (oldval)
+                : "r" (&ptr->counter), "r" (old), "r" (new)
+                : "cc");
+        } while (res);
+
+        smp_mb();
+
+        return oldval;
+}
+
+static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_xchg\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       strexd  %1, %3, %H3, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&ptr->counter), "r" (new)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline u64 atomic64_dec_if_positive(atomic64_t *v)
+{
+        u64 result;
+        unsigned long tmp;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_dec_if_positive\n"
+"1:     ldrexd  %0, %H0, [%2]\n"
+"       subs    %0, %0, #1\n"
+"       sbc     %H0, %H0, #0\n"
+"       teq     %H0, #0\n"
+"       bmi     2f\n"
+"       strexd  %1, %0, %H0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b\n"
+"2:"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter)
+        : "cc");
+
+        smp_mb();
+
+        return result;
+}
+
+static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
+{
+        u64 val;
+        unsigned long tmp;
+        int ret = 1;
+
+        smp_mb();
+
+        __asm__ __volatile__("@ atomic64_add_unless\n"
+"1:     ldrexd  %0, %H0, [%3]\n"
+"       teq     %0, %4\n"
+"       teqeq   %H0, %H4\n"
+"       moveq   %1, #0\n"
+"       beq     2f\n"
+"       adds    %0, %0, %5\n"
+"       adc     %H0, %H0, %H5\n"
+"       strexd  %2, %0, %H0, [%3]\n"
+"       teq     %2, #0\n"
+"       bne     1b\n"
+"2:"
+        : "=&r" (val), "=&r" (ret), "=&r" (tmp)
+        : "r" (&v->counter), "r" (u), "r" (a)
+        : "cc");
+
+        if (ret)
+                smp_mb();
+
+        return ret;
+}
+
+#define atomic64_add_negative(a, v)     (atomic64_add_return((a), (v)) < 0)
+#define atomic64_inc(v)                 atomic64_add(1LL, (v))
+#define atomic64_inc_return(v)          atomic64_add_return(1LL, (v))
+#define atomic64_inc_and_test(v)        (atomic64_inc_return(v) == 0)
+#define atomic64_sub_and_test(a, v)     (atomic64_sub_return((a), (v)) == 0)
+#define atomic64_dec(v)                 atomic64_sub(1LL, (v))
+#define atomic64_dec_return(v)          atomic64_sub_return(1LL, (v))
+#define atomic64_dec_and_test(v)        (atomic64_dec_return((v)) == 0)
+#define atomic64_inc_not_zero(v)        atomic64_add_unless((v), 1LL, 0LL)
+
+#else /* !CONFIG_GENERIC_ATOMIC64 */
+#include <asm-generic/atomic64.h>
+#endif
 #include <asm-generic/atomic-long.h>
 #endif
 #endif
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 5fe4a2ad7fa3..72da7e045c6b 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -197,21 +197,6 @@
  *      DMA Cache Coherency
  *      ===================
  *
- *      dma_inv_range(start, end)
- *
- *              Invalidate (discard) the specified virtual address range.
- *              May not write back any entries.  If 'start' or 'end'
- *              are not cache line aligned, those lines must be written
- *              back.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
- *      dma_clean_range(start, end)
- *
- *              Clean (write back) the specified virtual address range.
- *              - start  - virtual start address
- *              - end    - virtual end address
- *
  *      dma_flush_range(start, end)
  *
  *              Clean and invalidate the specified virtual address range.
@@ -228,8 +213,9 @@ struct cpu_cache_fns {
         void (*coherent_user_range)(unsigned long, unsigned long);
         void (*flush_kern_dcache_area)(void *, size_t);
 
-        void (*dma_inv_range)(const void *, const void *);
-        void (*dma_clean_range)(const void *, const void *);
+        void (*dma_map_area)(const void *, size_t, int);
+        void (*dma_unmap_area)(const void *, size_t, int);
+
         void (*dma_flush_range)(const void *, const void *);
 };
 
@@ -259,8 +245,8 @@ extern struct cpu_cache_fns cpu_cache;
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                  cpu_cache.dma_inv_range
-#define dmac_clean_range                cpu_cache.dma_clean_range
+#define dmac_map_area                   cpu_cache.dma_map_area
+#define dmac_unmap_area         cpu_cache.dma_unmap_area
 #define dmac_flush_range                cpu_cache.dma_flush_range
 
 #else
@@ -285,12 +271,12 @@ extern void __cpuc_flush_dcache_area(void *, size_t);
  * is visible to DMA, or data written by DMA to system memory is
  * visible to the CPU.
  */
-#define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
-#define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
+#define dmac_map_area                   __glue(_CACHE,_dma_map_area)
+#define dmac_unmap_area         __glue(_CACHE,_dma_unmap_area)
 #define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
 
-extern void dmac_inv_range(const void *, const void *);
-extern void dmac_clean_range(const void *, const void *);
+extern void dmac_map_area(const void *, size_t, int);
+extern void dmac_unmap_area(const void *, size_t, int);
 extern void dmac_flush_range(const void *, const void *);
 
 #endif
@@ -331,12 +317,8 @@ static inline void outer_flush_range(unsigned long start, unsigned long end)
  * processes address space.  Really, we want to allow our "user
  * space" model to handle this.
  */
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-        do {                                                    \
-                memcpy(dst, src, len);                          \
-                flush_ptrace_access(vma, page, vaddr, dst, len, 1);\
-        } while (0)
-
+extern void copy_to_user_page(struct vm_area_struct *, struct page *,
+        unsigned long, void *, const void *, unsigned long);
 #define copy_from_user_page(vma, page, vaddr, dst, src, len) \
         do {                                                    \
                 memcpy(dst, src, len);                          \
@@ -370,17 +352,6 @@ vivt_flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         }
 }
 
-static inline void
-vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
-                         unsigned long len, int write)
-{
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
-                unsigned long addr = (unsigned long)kaddr;
-                __cpuc_coherent_kern_range(addr, addr + len);
-        }
-}
-
 #ifndef CONFIG_CPU_CACHE_VIPT
 #define flush_cache_mm(mm) \
                 vivt_flush_cache_mm(mm)
@@ -388,15 +359,10 @@ vivt_flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
                 vivt_flush_cache_range(vma,start,end)
 #define flush_cache_page(vma,addr,pfn) \
                 vivt_flush_cache_page(vma,addr,pfn)
-#define flush_ptrace_access(vma,page,ua,ka,len,write) \
-                vivt_flush_ptrace_access(vma,page,ua,ka,len,write)
 #else
 extern void flush_cache_mm(struct mm_struct *mm);
 extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 extern void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn);
-extern void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                                unsigned long uaddr, void *kaddr,
-                                unsigned long len, int write);
 #endif
 
 #define flush_cache_dup_mm(mm) flush_cache_mm(mm)
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index b6ec7c627b39..7a0690da5e63 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -27,4 +27,7 @@ struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
 void clkdev_add(struct clk_lookup *cl);
 void clkdev_drop(struct clk_lookup *cl);
 
+void clkdev_add_table(struct clk_lookup *, size_t);
+int clk_add_alias(const char *, const char *, char *, struct device *);
+
 #endif
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index a96300bf83fd..256ee1c9f51a 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -57,18 +57,58 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
 #endif
 
 /*
- * DMA-consistent mapping functions.  These allocate/free a region of
- * uncached, unwrite-buffered mapped memory space for use with DMA
- * devices.  This is the "generic" version.  The PCI specific version
- * is in pci.h
+ * The DMA API is built upon the notion of "buffer ownership".  A buffer
+ * is either exclusively owned by the CPU (and therefore may be accessed
+ * by it) or exclusively owned by the DMA device.  These helper functions
+ * represent the transitions between these two ownership states.
  *
- * Note: Drivers should NOT use this function directly, as it will break
- * platforms with CONFIG_DMABOUNCE.
- * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
+ * Note, however, that on later ARMs, this notion does not work due to
+ * speculative prefetches.  We model our approach on the assumption that
+ * the CPU does do speculative prefetches, which means we clean caches
+ * before transfers and delay cache invalidation until transfer completion.
+ *
+ * Private support functions: these are not part of the API and are
+ * liable to change.  Drivers must not use these.
  */
-extern void dma_cache_maint(const void *kaddr, size_t size, int rw);
-extern void dma_cache_maint_page(struct page *page, unsigned long offset,
-                                 size_t size, int rw);
+static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        extern void ___dma_single_cpu_to_dev(const void *, size_t,
+                enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_single_cpu_to_dev(kaddr, size, dir);
+}
+
+static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
+{
+        extern void ___dma_single_dev_to_cpu(const void *, size_t,
+                enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_single_dev_to_cpu(kaddr, size, dir);
+}
+
+static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_cpu_to_dev(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_page_cpu_to_dev(page, off, size, dir);
+}
+
+static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        extern void ___dma_page_dev_to_cpu(struct page *, unsigned long,
+                size_t, enum dma_data_direction);
+
+        if (!arch_is_coherent())
+                ___dma_page_dev_to_cpu(page, off, size, dir);
+}
 
 /*
  * Return whether the given device DMA address mask can be supported
@@ -304,8 +344,7 @@ static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        if (!arch_is_coherent())
-                dma_cache_maint(cpu_addr, size, dir);
+        __dma_single_cpu_to_dev(cpu_addr, size, dir);
 
         return virt_to_dma(dev, cpu_addr);
 }
@@ -329,8 +368,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        if (!arch_is_coherent())
-                dma_cache_maint_page(page, offset, size, dir);
+        __dma_page_cpu_to_dev(page, offset, size, dir);
 
         return page_to_dma(dev, page) + offset;
 }
@@ -352,7 +390,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
 static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle), size, dir);
 }
 
 /**
@@ -372,7 +410,8 @@ static inline void dma_unmap_single(struct device *dev, dma_addr_t handle,
 static inline void dma_unmap_page(struct device *dev, dma_addr_t handle,
                 size_t size, enum dma_data_direction dir)
 {
-        /* nothing to do */
+        __dma_page_dev_to_cpu(dma_to_page(dev, handle), handle & ~PAGE_MASK,
+                size, dir);
 }
 #endif /* CONFIG_DMABOUNCE */
 
@@ -400,7 +439,10 @@ static inline void dma_sync_single_range_for_cpu(struct device *dev,
 {
         BUG_ON(!valid_dma_direction(dir));
 
-        dmabounce_sync_for_cpu(dev, handle, offset, size, dir);
+        if (!dmabounce_sync_for_cpu(dev, handle, offset, size, dir))
+                return;
+
+        __dma_single_dev_to_cpu(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_range_for_device(struct device *dev,
@@ -412,8 +454,7 @@ static inline void dma_sync_single_range_for_device(struct device *dev,
         if (!dmabounce_sync_for_device(dev, handle, offset, size, dir))
                 return;
 
-        if (!arch_is_coherent())
-                dma_cache_maint(dma_to_virt(dev, handle) + offset, size, dir);
+        __dma_single_cpu_to_dev(dma_to_virt(dev, handle) + offset, size, dir);
 }
 
 static inline void dma_sync_single_for_cpu(struct device *dev,
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index d2a59cfc30ce..c980156f3263 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -69,9 +69,16 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 /*
  * __arm_ioremap takes CPU physical address.
  * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
+ * The _caller variety takes a __builtin_return_address(0) value for
+ * /proc/vmalloc to use - and should only be used in non-inline functions.
  */
-extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
-extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
+extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
+        size_t, unsigned int, void *);
+extern void __iomem *__arm_ioremap_caller(unsigned long, size_t, unsigned int,
+        void *);
+
+extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
+extern void __iomem *__arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iounmap(volatile void __iomem *addr);
 
 /*
diff --git a/arch/arm/include/asm/mach/time.h b/arch/arm/include/asm/mach/time.h
index b2cc1fcd0400..8bffc3ff3acf 100644
--- a/arch/arm/include/asm/mach/time.h
+++ b/arch/arm/include/asm/mach/time.h
@@ -46,12 +46,4 @@ struct sys_timer {
 extern struct sys_timer *system_timer;
 extern void timer_tick(void);
 
-/*
- * Kernel time keeping support.
- */
-struct timespec;
-extern int (*set_rtc)(void);
-extern void save_time_delta(struct timespec *delta, struct timespec *rtc);
-extern void restore_time_delta(struct timespec *delta, struct timespec *rtc);
-
 #endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 5421d82a2572..4312ee5e3d0b 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -76,6 +76,17 @@
  */
 #define IOREMAP_MAX_ORDER       24
 
+/*
+ * Size of DMA-consistent memory region.  Must be multiple of 2M,
+ * between 2MB and 14MB inclusive.
+ */
+#ifndef CONSISTENT_DMA_SIZE
+#define CONSISTENT_DMA_SIZE     SZ_2M
+#endif
+
+#define CONSISTENT_END          (0xffe00000UL)
+#define CONSISTENT_BASE         (CONSISTENT_END - CONSISTENT_DMA_SIZE)
+
 #else /* CONFIG_MMU */
 
 /*
@@ -93,11 +104,11 @@
 #endif
 
 #ifndef PHYS_OFFSET
-#define PHYS_OFFSET             (CONFIG_DRAM_BASE)
+#define PHYS_OFFSET             UL(CONFIG_DRAM_BASE)
 #endif
 
 #ifndef END_MEM
-#define END_MEM                 (CONFIG_DRAM_BASE + CONFIG_DRAM_SIZE)
+#define END_MEM                 (UL(CONFIG_DRAM_BASE) + CONFIG_DRAM_SIZE)
 #endif
 
 #ifndef PAGE_OFFSET
@@ -113,14 +124,6 @@
 #endif /* !CONFIG_MMU */
 
 /*
- * Size of DMA-consistent memory region.  Must be multiple of 2M,
- * between 2MB and 14MB inclusive.
- */
-#ifndef CONSISTENT_DMA_SIZE
-#define CONSISTENT_DMA_SIZE SZ_2M
-#endif
-
-/*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
  * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
diff --git a/arch/arm/include/asm/mmu.h b/arch/arm/include/asm/mmu.h
index b561584d04a1..68870c776671 100644
--- a/arch/arm/include/asm/mmu.h
+++ b/arch/arm/include/asm/mmu.h
@@ -6,6 +6,7 @@
 typedef struct {
 #ifdef CONFIG_CPU_HAS_ASID
         unsigned int id;
+        spinlock_t id_lock;
 #endif
         unsigned int kvm_seq;
 } mm_context_t;
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index de6cefb329dd..a0b3cac0547c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -43,12 +43,23 @@ void __check_kvm_seq(struct mm_struct *mm);
 #define ASID_FIRST_VERSION      (1 << ASID_BITS)
 
 extern unsigned int cpu_last_asid;
+#ifdef CONFIG_SMP
+DECLARE_PER_CPU(struct mm_struct *, current_mm);
+#endif
 
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
 
 static inline void check_context(struct mm_struct *mm)
 {
+        /*
+         * This code is executed with interrupts enabled. Therefore,
+         * mm->context.id cannot be updated to the latest ASID version
+         * on a different CPU (and condition below not triggered)
+         * without first getting an IPI to reset the context. The
+         * alternative is to take a read_lock on mm->context.id_lock
+         * (after changing its type to rwlock_t).
+         */
         if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
                 __new_context(mm);
 
@@ -108,6 +119,10 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 __flush_icache_all();
 #endif
         if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
+#ifdef CONFIG_SMP
+                struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
+                *crt_mm = next;
+#endif
                 check_context(next);
                 cpu_switch_mm(next->pgd, next);
                 if (cache_is_vivt())
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 3a32af4cce30..a485ac3c8696 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -117,11 +117,12 @@
 #endif
 
 struct page;
+struct vm_area_struct;
 
 struct cpu_user_fns {
         void (*cpu_clear_user_highpage)(struct page *page, unsigned long vaddr);
         void (*cpu_copy_user_highpage)(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 };
 
 #ifdef MULTI_USER
@@ -137,7 +138,7 @@ extern struct cpu_user_fns cpu_user;
 
 extern void __cpu_clear_user_highpage(struct page *page, unsigned long vaddr);
 extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
-                        unsigned long vaddr);
+                        unsigned long vaddr, struct vm_area_struct *vma);
 #endif
 
 #define clear_user_highpage(page,vaddr)         \
@@ -145,7 +146,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from,
 
 #define __HAVE_ARCH_COPY_USER_HIGHPAGE
 #define copy_user_highpage(to,from,vaddr,vma)   \
-        __cpu_copy_user_highpage(to, from, vaddr)
+        __cpu_copy_user_highpage(to, from, vaddr, vma)
 
 #define clear_page(page)        memset((void *)(page), 0, PAGE_SIZE)
 extern void copy_page(void *to, const void *from);
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
new file mode 100644
index 000000000000..49e3049aba32
--- /dev/null
+++ b/arch/arm/include/asm/perf_event.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/arch/arm/include/asm/perf_event.h
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARM_PERF_EVENT_H__
+#define __ARM_PERF_EVENT_H__
+
+/*
+ * NOP: on *most* (read: all supported) ARM platforms, the performance
+ * counter interrupts are regular interrupts and not an NMI. This
+ * means that when we receive the interrupt we can call
+ * perf_event_do_pending() that handles all of the work with
+ * interrupts enabled.
+ */
+static inline void
+set_perf_event_pending(void)
+{
+}
+
+/* ARM performance counters start from 1 (in the cp15 accesses) so use the
+ * same indexes here for consistency. */
+#define PERF_EVENT_INDEX_OFFSET 1
+
+#endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pgtable-nommu.h b/arch/arm/include/asm/pgtable-nommu.h
index b011f2e939aa..013cfcdc4839 100644
--- a/arch/arm/include/asm/pgtable-nommu.h
+++ b/arch/arm/include/asm/pgtable-nommu.h
@@ -86,8 +86,8 @@ extern unsigned int kobjsize(const void *objp);
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
  */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
+#define VMALLOC_START   0UL
+#define VMALLOC_END     0xffffffffUL
 
 #define FIRST_USER_ADDRESS      (0)
 
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
new file mode 100644
index 000000000000..2829b9f981a1
--- /dev/null
+++ b/arch/arm/include/asm/pmu.h
@@ -0,0 +1,75 @@
+/*
+ *  linux/arch/arm/include/asm/pmu.h
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ARM_PMU_H__
+#define __ARM_PMU_H__
+
+#ifdef CONFIG_CPU_HAS_PMU
+
+struct pmu_irqs {
+        const int   *irqs;
+        int         num_irqs;
+};
+
+/**
+ * reserve_pmu() - reserve the hardware performance counters
+ *
+ * Reserve the hardware performance counters in the system for exclusive use.
+ * The 'struct pmu_irqs' for the system is returned on success, ERR_PTR()
+ * encoded error on failure.
+ */
+extern const struct pmu_irqs *
+reserve_pmu(void);
+
+/**
+ * release_pmu() - Relinquish control of the performance counters
+ *
+ * Release the performance counters and allow someone else to use them.
+ * Callers must have disabled the counters and released IRQs before calling
+ * this. The 'struct pmu_irqs' returned from reserve_pmu() must be passed as
+ * a cookie.
+ */
+extern int
+release_pmu(const struct pmu_irqs *irqs);
+
+/**
+ * init_pmu() - Initialise the PMU.
+ *
+ * Initialise the system ready for PMU enabling. This should typically set the
+ * IRQ affinity and nothing else. The users (oprofile/perf events etc) will do
+ * the actual hardware initialisation.
+ */
+extern int
+init_pmu(void);
+
+#else /* CONFIG_CPU_HAS_PMU */
+
+static inline const struct pmu_irqs *
+reserve_pmu(void)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline int
+release_pmu(const struct pmu_irqs *irqs)
+{
+        return -ENODEV;
+}
+
+static inline int
+init_pmu(void)
+{
+        return -ENODEV;
+}
+
+#endif /* CONFIG_CPU_HAS_PMU */
+
+#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 5ccce0a9b03c..f392fb4437af 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -223,18 +223,6 @@ extern struct meminfo meminfo;
 #define bank_phys_end(bank)     ((bank)->start + (bank)->size)
 #define bank_phys_size(bank)    (bank)->size
 
-/*
- * Early command line parameters.
- */
-struct early_params {
-        const char *arg;
-        void (*fn)(char **p);
-};
-
-#define __early_param(name,fn)                                  \
-static struct early_params __early_##fn __used                  \
-__attribute__((__section__(".early_param.init"))) = { name, fn }
-
 #endif  /*  __KERNEL__  */
 
 #endif
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index 59303e200845..e6215305544a 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,4 +13,9 @@ static inline int tlb_ops_need_broadcast(void)
         return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+static inline int cache_ops_need_broadcast(void)
+{
+        return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
+}
+
 #endif
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index c91c64cab922..17eb355707dd 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -5,6 +5,22 @@
 #error SMP not supported on pre-ARMv6 CPUs
 #endif
 
+static inline void dsb_sev(void)
+{
+#if __LINUX_ARM_ARCH__ >= 7
+        __asm__ __volatile__ (
+                "dsb\n"
+                "sev"
+        );
+#elif defined(CONFIG_CPU_32v6K)
+        __asm__ __volatile__ (
+                "mcr p15, 0, %0, c7, c10, 4\n"
+                "sev"
+                : : "r" (0)
+        );
+#endif
+}
+
 /*
  * ARMv6 Spin-locking.
  *
@@ -69,13 +85,11 @@ static inline void arch_spin_unlock(arch_spinlock_t *lock)
 
         __asm__ __volatile__(
 "       str     %1, [%0]\n"
-#ifdef CONFIG_CPU_32v6K
-"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
-"       sev"
-#endif
         :
         : "r" (&lock->lock), "r" (0)
         : "cc");
+
+        dsb_sev();
 }
 
 /*
@@ -132,13 +146,11 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
 
         __asm__ __volatile__(
         "str    %1, [%0]\n"
-#ifdef CONFIG_CPU_32v6K
-"       mcr     p15, 0, %1, c7, c10, 4\n" /* DSB */
-"       sev\n"
-#endif
         :
         : "r" (&rw->lock), "r" (0)
         : "cc");
+
+        dsb_sev();
 }
 
 /* write_can_lock - would write_trylock() succeed? */
@@ -188,14 +200,12 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
 "       strex   %1, %0, [%2]\n"
 "       teq     %1, #0\n"
 "       bne     1b"
-#ifdef CONFIG_CPU_32v6K
-"\n     cmp     %0, #0\n"
-"       mcreq   p15, 0, %0, c7, c10, 4\n"
-"       seveq"
-#endif
         : "=&r" (tmp), "=&r" (tmp2)
         : "r" (&rw->lock)
         : "cc");
+
+        if (tmp == 0)
+                dsb_sev();
 }
 
 static inline int arch_read_trylock(arch_rwlock_t *rw)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 058e7e90881d..ca88e6a84707 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -73,8 +73,7 @@ extern unsigned int mem_fclk_21285;
 
 struct pt_regs;
 
-void die(const char *msg, struct pt_regs *regs, int err)
-                __attribute__((noreturn));
+void die(const char *msg, struct pt_regs *regs, int err);
 
 struct siginfo;
 void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 2dfb7d7a66e9..b74970ec02c4 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -115,7 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *);
 extern void iwmmxt_task_release(struct thread_info *);
 extern void iwmmxt_task_switch(struct thread_info *);
 
-extern void vfp_sync_state(struct thread_info *thread);
+extern void vfp_sync_hwstate(struct thread_info *);
+extern void vfp_flush_hwstate(struct thread_info *);
 
 #endif
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index c2f1605de359..e085e2c545eb 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -529,7 +529,8 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
-extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
+extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep);
 
 #endif
 
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index dd00f747e2ad..26d302c28e13 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -17,6 +17,7 @@ obj-y		:= compat.o elf.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o return_address.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
@@ -46,6 +47,8 @@ obj-$(CONFIG_CPU_XSCALE)	+= xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
+obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
+obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
 AFLAGS_iwmmxt.o                 := -Wa,-mcpu=iwmmxt
 
 ifneq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 4a881258bb17..883511522fca 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -12,6 +12,7 @@
  */
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/dma-mapping.h>
 #include <asm/mach/arch.h>
 #include <asm/thread_info.h>
 #include <asm/memory.h>
@@ -112,5 +113,9 @@ int main(void)
 #ifdef MULTI_PABORT
   DEFINE(PROCESSOR_PABT_FUNC,   offsetof(struct processor, _prefetch_abort));
 #endif
+  BLANK();
+  DEFINE(DMA_BIDIRECTIONAL,     DMA_BIDIRECTIONAL);
+  DEFINE(DMA_TO_DEVICE,         DMA_TO_DEVICE);
+  DEFINE(DMA_FROM_DEVICE,       DMA_FROM_DEVICE);
   return 0; 
 }
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 5c91addcaebc..a38b4879441d 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -24,7 +24,7 @@
 
 #if defined(CONFIG_CPU_V6)
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 .endm
 
                 .macro  senduart, rd, rx
@@ -51,7 +51,7 @@
 
 #elif defined(CONFIG_CPU_V7)
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 .endm
 
                 .macro  senduart, rd, rx
@@ -71,7 +71,7 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 
 #elif defined(CONFIG_CPU_XSCALE)
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 .endm
 
                 .macro  senduart, rd, rx
@@ -98,7 +98,7 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 
 #else
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 .endm
 
                 .macro  senduart, rd, rx
@@ -164,7 +164,7 @@ ENDPROC(printhex2)
                 .ltorg
 
 ENTRY(printascii)
-                addruart r3
+                addruart r3, r1
                 b       2f
 1:              waituart r2, r3
                 senduart r1, r3
@@ -180,7 +180,7 @@ ENTRY(printascii)
 ENDPROC(printascii)
 
 ENTRY(printch)
-                addruart r3
+                addruart r3, r1
                 mov     r1, r0
                 mov     r0, #0
                 b       1b
diff --git a/arch/arm/kernel/leds.c b/arch/arm/kernel/leds.c
new file mode 100644
index 000000000000..31a316c1777b
--- /dev/null
+++ b/arch/arm/kernel/leds.c
@@ -0,0 +1,115 @@
+/*
+ * LED support code, ripped out of arch/arm/kernel/time.c
+ *
+ *  Copyright (C) 1994-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <asm/leds.h>
+
+static void dummy_leds_event(led_event_t evt)
+{
+}
+
+void (*leds_event)(led_event_t) = dummy_leds_event;
+
+struct leds_evt_name {
+        const char      name[8];
+        int             on;
+        int             off;
+};
+
+static const struct leds_evt_name evt_names[] = {
+        { "amber", led_amber_on, led_amber_off },
+        { "blue",  led_blue_on,  led_blue_off  },
+        { "green", led_green_on, led_green_off },
+        { "red",   led_red_on,   led_red_off   },
+};
+
+static ssize_t leds_store(struct sys_device *dev,
+                        struct sysdev_attribute *attr,
+                        const char *buf, size_t size)
+{
+        int ret = -EINVAL, len = strcspn(buf, " ");
+
+        if (len > 0 && buf[len] == '\0')
+                len--;
+
+        if (strncmp(buf, "claim", len) == 0) {
+                leds_event(led_claim);
+                ret = size;
+        } else if (strncmp(buf, "release", len) == 0) {
+                leds_event(led_release);
+                ret = size;
+        } else {
+                int i;
+
+                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
+                        if (strlen(evt_names[i].name) != len ||
+                            strncmp(buf, evt_names[i].name, len) != 0)
+                                continue;
+                        if (strncmp(buf+len, " on", 3) == 0) {
+                                leds_event(evt_names[i].on);
+                                ret = size;
+                        } else if (strncmp(buf+len, " off", 4) == 0) {
+                                leds_event(evt_names[i].off);
+                                ret = size;
+                        }
+                        break;
+                }
+        }
+        return ret;
+}
+
+static SYSDEV_ATTR(event, 0200, NULL, leds_store);
+
+static int leds_suspend(struct sys_device *dev, pm_message_t state)
+{
+        leds_event(led_stop);
+        return 0;
+}
+
+static int leds_resume(struct sys_device *dev)
+{
+        leds_event(led_start);
+        return 0;
+}
+
+static int leds_shutdown(struct sys_device *dev)
+{
+        leds_event(led_halted);
+        return 0;
+}
+
+static struct sysdev_class leds_sysclass = {
+        .name           = "leds",
+        .shutdown       = leds_shutdown,
+        .suspend        = leds_suspend,
+        .resume         = leds_resume,
+};
+
+static struct sys_device leds_device = {
+        .id             = 0,
+        .cls            = &leds_sysclass,
+};
+
+static int __init leds_init(void)
+{
+        int ret;
+        ret = sysdev_class_register(&leds_sysclass);
+        if (ret == 0)
+                ret = sysdev_register(&leds_device);
+        if (ret == 0)
+                ret = sysdev_create_file(&leds_device, &attr_event);
+        return ret;
+}
+
+device_initcall(leds_init);
+
+EXPORT_SYMBOL(leds_event);
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
new file mode 100644
index 000000000000..c54ceb3d1f97
--- /dev/null
+++ b/arch/arm/kernel/perf_event.c
@@ -0,0 +1,2276 @@
+#undef DEBUG
+
+/*
+ * ARM performance counter support.
+ *
+ * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
+ *
+ * ARMv7 support: Jean Pihet <jpihet@mvista.com>
+ * 2010 (c) MontaVista Software, LLC.
+ *
+ * This code is based on the sparc64 perf event code, which is in turn based
+ * on the x86 code. Callchain code is based on the ARM OProfile backtrace
+ * code.
+ */
+#define pr_fmt(fmt) "hw perfevents: " fmt
+
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/perf_event.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+
+#include <asm/cputype.h>
+#include <asm/irq.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+#include <asm/stacktrace.h>
+
+static const struct pmu_irqs *pmu_irqs;
+
+/*
+ * Hardware lock to serialize accesses to PMU registers. Needed for the
+ * read/modify/write sequences.
+ */
+DEFINE_SPINLOCK(pmu_lock);
+
+/*
+ * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
+ * another platform that supports more, we need to increase this to be the
+ * largest of all platforms.
+ *
+ * ARMv7 supports up to 32 events:
+ *  cycle counter CCNT + 31 events counters CNT0..30.
+ *  Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
+ */
+#define ARMPMU_MAX_HWEVENTS             33
+
+/* The events for a given CPU. */
+struct cpu_hw_events {
+        /*
+         * The events that are active on the CPU for the given index. Index 0
+         * is reserved.
+         */
+        struct perf_event       *events[ARMPMU_MAX_HWEVENTS];
+
+        /*
+         * A 1 bit for an index indicates that the counter is being used for
+         * an event. A 0 means that the counter can be used.
+         */
+        unsigned long           used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
+
+        /*
+         * A 1 bit for an index indicates that the counter is actively being
+         * used.
+         */
+        unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+struct arm_pmu {
+        char            *name;
+        irqreturn_t     (*handle_irq)(int irq_num, void *dev);
+        void            (*enable)(struct hw_perf_event *evt, int idx);
+        void            (*disable)(struct hw_perf_event *evt, int idx);
+        int             (*event_map)(int evt);
+        u64             (*raw_event)(u64);
+        int             (*get_event_idx)(struct cpu_hw_events *cpuc,
+                                         struct hw_perf_event *hwc);
+        u32             (*read_counter)(int idx);
+        void            (*write_counter)(int idx, u32 val);
+        void            (*start)(void);
+        void            (*stop)(void);
+        int             num_events;
+        u64             max_period;
+};
+
+/* Set at runtime when we know what CPU type we are. */
+static const struct arm_pmu *armpmu;
+
+#define HW_OP_UNSUPPORTED               0xFFFF
+
+#define C(_x) \
+        PERF_COUNT_HW_CACHE_##_x
+
+#define CACHE_OP_UNSUPPORTED            0xFFFF
+
+static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                     [PERF_COUNT_HW_CACHE_OP_MAX]
+                                     [PERF_COUNT_HW_CACHE_RESULT_MAX];
+
+static int
+armpmu_map_cache_event(u64 config)
+{
+        unsigned int cache_type, cache_op, cache_result, ret;
+
+        cache_type = (config >>  0) & 0xff;
+        if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
+                return -EINVAL;
+
+        cache_op = (config >>  8) & 0xff;
+        if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
+                return -EINVAL;
+
+        cache_result = (config >> 16) & 0xff;
+        if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+                return -EINVAL;
+
+        ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
+
+        if (ret == CACHE_OP_UNSUPPORTED)
+                return -ENOENT;
+
+        return ret;
+}
+
+static int
+armpmu_event_set_period(struct perf_event *event,
+                        struct hw_perf_event *hwc,
+                        int idx)
+{
+        s64 left = atomic64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+
+        if (unlikely(left <= -period)) {
+                left = period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (unlikely(left <= 0)) {
+                left += period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+
+        if (left > (s64)armpmu->max_period)
+                left = armpmu->max_period;
+
+        atomic64_set(&hwc->prev_count, (u64)-left);
+
+        armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
+
+        perf_event_update_userpage(event);
+
+        return ret;
+}
+
+static u64
+armpmu_event_update(struct perf_event *event,
+                    struct hw_perf_event *hwc,
+                    int idx)
+{
+        int shift = 64 - 32;
+        s64 prev_raw_count, new_raw_count;
+        s64 delta;
+
+again:
+        prev_raw_count = atomic64_read(&hwc->prev_count);
+        new_raw_count = armpmu->read_counter(idx);
+
+        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                             new_raw_count) != prev_raw_count)
+                goto again;
+
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+
+        atomic64_add(delta, &event->count);
+        atomic64_sub(delta, &hwc->period_left);
+
+        return new_raw_count;
+}
+
+static void
+armpmu_disable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx = hwc->idx;
+
+        WARN_ON(idx < 0);
+
+        clear_bit(idx, cpuc->active_mask);
+        armpmu->disable(hwc, idx);
+
+        barrier();
+
+        armpmu_event_update(event, hwc, idx);
+        cpuc->events[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+
+        perf_event_update_userpage(event);
+}
+
+static void
+armpmu_read(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /* Don't read disabled counters! */
+        if (hwc->idx < 0)
+                return;
+
+        armpmu_event_update(event, hwc, hwc->idx);
+}
+
+static void
+armpmu_unthrottle(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+
+        /*
+         * Set the period again. Some counters can't be stopped, so when we
+         * were throttled we simply disabled the IRQ source and the counter
+         * may have been left counting. If we don't do this step then we may
+         * get an interrupt too soon or *way* too late if the overflow has
+         * happened since disabling.
+         */
+        armpmu_event_set_period(event, hwc, hwc->idx);
+        armpmu->enable(hwc, hwc->idx);
+}
+
+static int
+armpmu_enable(struct perf_event *event)
+{
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+        struct hw_perf_event *hwc = &event->hw;
+        int idx;
+        int err = 0;
+
+        /* If we don't have a space for the counter then finish early. */
+        idx = armpmu->get_event_idx(cpuc, hwc);
+        if (idx < 0) {
+                err = idx;
+                goto out;
+        }
+
+        /*
+         * If there is an event in the counter we are going to use then make
+         * sure it is disabled.
+         */
+        event->hw.idx = idx;
+        armpmu->disable(hwc, idx);
+        cpuc->events[idx] = event;
+        set_bit(idx, cpuc->active_mask);
+
+        /* Set the period for the event. */
+        armpmu_event_set_period(event, hwc, idx);
+
+        /* Enable the event. */
+        armpmu->enable(hwc, idx);
+
+        /* Propagate our changes to the userspace mapping. */
+        perf_event_update_userpage(event);
+
+out:
+        return err;
+}
+
+static struct pmu pmu = {
+        .enable     = armpmu_enable,
+        .disable    = armpmu_disable,
+        .unthrottle = armpmu_unthrottle,
+        .read       = armpmu_read,
+};
+
+static int
+validate_event(struct cpu_hw_events *cpuc,
+               struct perf_event *event)
+{
+        struct hw_perf_event fake_event = event->hw;
+
+        if (event->pmu && event->pmu != &pmu)
+                return 0;
+
+        return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
+}
+
+static int
+validate_group(struct perf_event *event)
+{
+        struct perf_event *sibling, *leader = event->group_leader;
+        struct cpu_hw_events fake_pmu;
+
+        memset(&fake_pmu, 0, sizeof(fake_pmu));
+
+        if (!validate_event(&fake_pmu, leader))
+                return -ENOSPC;
+
+        list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
+                if (!validate_event(&fake_pmu, sibling))
+                        return -ENOSPC;
+        }
+
+        if (!validate_event(&fake_pmu, event))
+                return -ENOSPC;
+
+        return 0;
+}
+
+static int
+armpmu_reserve_hardware(void)
+{
+        int i;
+        int err;
+
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                pr_warning("unable to reserve pmu\n");
+                return PTR_ERR(pmu_irqs);
+        }
+
+        init_pmu();
+
+        if (pmu_irqs->num_irqs < 1) {
+                pr_err("no irqs for PMUs defined\n");
+                return -ENODEV;
+        }
+
+        for (i = 0; i < pmu_irqs->num_irqs; ++i) {
+                err = request_irq(pmu_irqs->irqs[i], armpmu->handle_irq,
+                                  IRQF_DISABLED, "armpmu", NULL);
+                if (err) {
+                        pr_warning("unable to request IRQ%d for ARM "
+                                   "perf counters\n", pmu_irqs->irqs[i]);
+                        break;
+                }
+        }
+
+        if (err) {
+                for (i = i - 1; i >= 0; --i)
+                        free_irq(pmu_irqs->irqs[i], NULL);
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
+
+        return err;
+}
+
+static void
+armpmu_release_hardware(void)
+{
+        int i;
+
+        for (i = pmu_irqs->num_irqs - 1; i >= 0; --i)
+                free_irq(pmu_irqs->irqs[i], NULL);
+        armpmu->stop();
+
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
+}
+
+static atomic_t active_events = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmu_reserve_mutex);
+
+static void
+hw_perf_event_destroy(struct perf_event *event)
+{
+        if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
+                armpmu_release_hardware();
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+}
+
+static int
+__hw_perf_event_init(struct perf_event *event)
+{
+        struct hw_perf_event *hwc = &event->hw;
+        int mapping, err;
+
+        /* Decode the generic type into an ARM event identifier. */
+        if (PERF_TYPE_HARDWARE == event->attr.type) {
+                mapping = armpmu->event_map(event->attr.config);
+        } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
+                mapping = armpmu_map_cache_event(event->attr.config);
+        } else if (PERF_TYPE_RAW == event->attr.type) {
+                mapping = armpmu->raw_event(event->attr.config);
+        } else {
+                pr_debug("event type %x not supported\n", event->attr.type);
+                return -EOPNOTSUPP;
+        }
+
+        if (mapping < 0) {
+                pr_debug("event %x:%llx not supported\n", event->attr.type,
+                         event->attr.config);
+                return mapping;
+        }
+
+        /*
+         * Check whether we need to exclude the counter from certain modes.
+         * The ARM performance counters are on all of the time so if someone
+         * has asked us for some excludes then we have to fail.
+         */
+        if (event->attr.exclude_kernel || event->attr.exclude_user ||
+            event->attr.exclude_hv || event->attr.exclude_idle) {
+                pr_debug("ARM performance counters do not support "
+                         "mode exclusion\n");
+                return -EPERM;
+        }
+
+        /*
+         * We don't assign an index until we actually place the event onto
+         * hardware. Use -1 to signify that we haven't decided where to put it
+         * yet. For SMP systems, each core has it's own PMU so we can't do any
+         * clever allocation or constraints checking at this point.
+         */
+        hwc->idx = -1;
+
+        /*
+         * Store the event encoding into the config_base field. config and
+         * event_base are unused as the only 2 things we need to know are
+         * the event mapping and the counter to use. The counter to use is
+         * also the indx and the config_base is the event type.
+         */
+        hwc->config_base            = (unsigned long)mapping;
+        hwc->config                 = 0;
+        hwc->event_base             = 0;
+
+        if (!hwc->sample_period) {
+                hwc->sample_period  = armpmu->max_period;
+                hwc->last_period    = hwc->sample_period;
+                atomic64_set(&hwc->period_left, hwc->sample_period);
+        }
+
+        err = 0;
+        if (event->group_leader != event) {
+                err = validate_group(event);
+                if (err)
+                        return -EINVAL;
+        }
+
+        return err;
+}
+
+const struct pmu *
+hw_perf_event_init(struct perf_event *event)
+{
+        int err = 0;
+
+        if (!armpmu)
+                return ERR_PTR(-ENODEV);
+
+        event->destroy = hw_perf_event_destroy;
+
+        if (!atomic_inc_not_zero(&active_events)) {
+                if (atomic_read(&active_events) > perf_max_events) {
+                        atomic_dec(&active_events);
+                        return ERR_PTR(-ENOSPC);
+                }
+
+                mutex_lock(&pmu_reserve_mutex);
+                if (atomic_read(&active_events) == 0) {
+                        err = armpmu_reserve_hardware();
+                }
+
+                if (!err)
+                        atomic_inc(&active_events);
+                mutex_unlock(&pmu_reserve_mutex);
+        }
+
+        if (err)
+                return ERR_PTR(err);
+
+        err = __hw_perf_event_init(event);
+        if (err)
+                hw_perf_event_destroy(event);
+
+        return err ? ERR_PTR(err) : &pmu;
+}
+
+void
+hw_perf_enable(void)
+{
+        /* Enable all of the perf events on hardware. */
+        int idx;
+        struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+        if (!armpmu)
+                return;
+
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+
+                if (!event)
+                        continue;
+
+                armpmu->enable(&event->hw, idx);
+        }
+
+        armpmu->start();
+}
+
+void
+hw_perf_disable(void)
+{
+        if (armpmu)
+                armpmu->stop();
+}
+
+/*
+ * ARMv6 Performance counter handling code.
+ *
+ * ARMv6 has 2 configurable performance counters and a single cycle counter.
+ * They all share a single reset bit but can be written to zero so we can use
+ * that for a reset.
+ *
+ * The counters can't be individually enabled or disabled so when we remove
+ * one event and replace it with another we could get spurious counts from the
+ * wrong event. However, we can take advantage of the fact that the
+ * performance counters can export events to the event bus, and the event bus
+ * itself can be monitored. This requires that we *don't* export the events to
+ * the event bus. The procedure for disabling a configurable counter is:
+ *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
+ *        effectively stops the counter from counting.
+ *      - disable the counter's interrupt generation (each counter has it's
+ *        own interrupt enable bit).
+ * Once stopped, the counter value can be written as 0 to reset.
+ *
+ * To enable a counter:
+ *      - enable the counter's interrupt generation.
+ *      - set the new event type.
+ *
+ * Note: the dedicated cycle counter only counts cycles and can't be
+ * enabled/disabled independently of the others. When we want to disable the
+ * cycle counter, we have to just disable the interrupt reporting and start
+ * ignoring that counter. When re-enabling, we have to reset the value and
+ * enable the interrupt.
+ */
+
+enum armv6_perf_types {
+        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
+        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
+        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
+        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
+        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
+        ARMV6_PERFCTR_BR_EXEC               = 0x5,
+        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
+        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
+        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
+        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
+        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
+        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
+        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
+        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
+        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
+        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
+        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
+        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
+        ARMV6_PERFCTR_NOP                   = 0x20,
+};
+
+enum armv6_counters {
+        ARMV6_CYCLE_COUNTER = 1,
+        ARMV6_COUNTER0,
+        ARMV6_COUNTER1,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+enum armv6mpcore_perf_types {
+        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
+        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
+        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
+        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
+        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
+        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
+        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
+        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
+        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
+        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
+        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
+        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
+        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
+        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
+        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
+        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+static inline unsigned long
+armv6_pmcr_read(void)
+{
+        u32 val;
+        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void
+armv6_pmcr_write(unsigned long val)
+{
+        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
+}
+
+#define ARMV6_PMCR_ENABLE               (1 << 0)
+#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
+#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
+#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
+#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
+#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
+#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
+#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
+#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
+#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
+#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
+#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
+#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
+#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
+
+#define ARMV6_PMCR_OVERFLOWED_MASK \
+        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
+         ARMV6_PMCR_CCOUNT_OVERFLOW)
+
+static inline int
+armv6_pmcr_has_overflowed(unsigned long pmcr)
+{
+        return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
+}
+
+static inline int
+armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
+                                  enum armv6_counters counter)
+{
+        int ret = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
+        else if (ARMV6_COUNTER0 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
+        else if (ARMV6_COUNTER1 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return ret;
+}
+
+static inline u32
+armv6pmu_read_counter(int counter)
+{
+        unsigned long value = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return value;
+}
+
+static inline void
+armv6pmu_write_counter(int counter,
+                       u32 value)
+{
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+}
+
+void
+armv6pmu_enable_event(struct hw_perf_event *hwc,
+                      int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = 0;
+                evt     = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
+                          ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
+                          ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the event
+         * that we're interested in.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t
+armv6pmu_handle_irq(int irq_num,
+                    void *dev)
+{
+        unsigned long pmcr = armv6_pmcr_read();
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        if (!armv6_pmcr_has_overflowed(pmcr))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        /*
+         * The interrupts are cleared by writing the overflow flags back to
+         * the control register. All of the other bits don't have any effect
+         * if they are rewritten, so write the whole value back.
+         */
+        armv6_pmcr_write(pmcr);
+
+        data.addr = 0;
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts enabled. For
+         * platforms that can have the PMU interrupts raised as a PMI, this
+         * will not work.
+         */
+        perf_event_do_pending();
+
+        return IRQ_HANDLED;
+}
+
+static void
+armv6pmu_start(void)
+{
+        unsigned long flags, val;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val |= ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+void
+armv6pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline int
+armv6pmu_event_map(int config)
+{
+        int mapping = armv6_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static inline int
+armv6mpcore_pmu_event_map(int config)
+{
+        int mapping = armv6mpcore_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static u64
+armv6pmu_raw_event(u64 config)
+{
+        return config & 0xff;
+}
+
+static int
+armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                       struct hw_perf_event *event)
+{
+        /* Always place a cycle counter into the cycle counter. */
+        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
+                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV6_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * counter0 and counter1.
+                 */
+                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
+                        return ARMV6_COUNTER1;
+                }
+
+                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
+                        return ARMV6_COUNTER0;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static void
+armv6pmu_disable_event(struct hw_perf_event *hwc,
+                       int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+                evt     = 0;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the number
+         * of ETM bus signal assertion cycles. The external reporting should
+         * be disabled and so this should never increment.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
+                              int idx)
+{
+        unsigned long val, mask, flags, evt = 0;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
+         * simply disable the interrupt reporting.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static const struct arm_pmu armv6pmu = {
+        .name                   = "v6",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6pmu_disable_event,
+        .event_map              = armv6pmu_event_map,
+        .raw_event              = armv6pmu_raw_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+/*
+ * ARMv6mpcore is almost identical to single core ARMv6 with the exception
+ * that some of the events have different enumerations and that there is no
+ * *hack* to stop the programmable counters. To stop the counters we simply
+ * disable the interrupt reporting and update the event. When unthrottling we
+ * reset the period and enable the interrupt reporting.
+ */
+static const struct arm_pmu armv6mpcore_pmu = {
+        .name                   = "v6mpcore",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6mpcore_pmu_disable_event,
+        .event_map              = armv6mpcore_pmu_event_map,
+        .raw_event              = armv6pmu_raw_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+/*
+ * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
+ *
+ * Copied from ARMv6 code, with the low level code inspired
+ *  by the ARMv7 Oprofile code.
+ *
+ * Cortex-A8 has up to 4 configurable performance counters and
+ *  a single cycle counter.
+ * Cortex-A9 has up to 31 configurable performance counters and
+ *  a single cycle counter.
+ *
+ * All counters can be enabled/disabled and IRQ masked separately. The cycle
+ *  counter and all 4 performance counters together can be reset separately.
+ */
+
+#define ARMV7_PMU_CORTEX_A8_NAME                "ARMv7 Cortex-A8"
+
+#define ARMV7_PMU_CORTEX_A9_NAME                "ARMv7 Cortex-A9"
+
+/* Common ARMv7 event types */
+enum armv7_perf_types {
+        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
+        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
+        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_DWRITE                    = 0x07,
+
+        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+         * It counts:
+         *  - all branch instructions,
+         *  - instructions that explicitly write the PC,
+         *  - exception generating instructions.
+         */
+        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+
+        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
+
+        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
+};
+
+/* ARMv7 Cortex-A8 specific event types */
+enum armv7_a8_perf_types {
+        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+
+        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+
+        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
+        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
+        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
+        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
+        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
+        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
+        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
+        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
+        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
+        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
+        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
+        ARMV7_PERFCTR_L1_INST                   = 0x50,
+        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
+        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
+        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
+        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
+        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
+        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
+        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
+        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
+        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
+        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
+
+        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
+        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
+        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
+};
+
+/* ARMv7 Cortex-A9 specific event types */
+enum armv7_a9_perf_types {
+        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+
+        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
+        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
+
+        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
+        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
+        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
+        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
+        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
+        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
+        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
+        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
+        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
+
+        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
+
+        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
+        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
+        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
+        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
+        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
+
+        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
+        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
+        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
+        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
+        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
+        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
+        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
+
+        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
+        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
+
+        ARMV7_PERFCTR_ISB_INST                  = 0x90,
+        ARMV7_PERFCTR_DSB_INST                  = 0x91,
+        ARMV7_PERFCTR_DMB_INST                  = 0x92,
+        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
+
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
+        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
+        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
+        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
+        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
+};
+
+/*
+ * Cortex-A8 HW events mapping
+ *
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Cortex-A9 HW events mapping
+ */
+static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        =
+                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
+        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Perf Events counters
+ */
+enum armv7_counters {
+        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
+        ARMV7_COUNTER0                  = 2,    /* First event counter */
+};
+
+/*
+ * The cycle counter is ARMV7_CYCLE_COUNTER.
+ * The first event counter is ARMV7_COUNTER0.
+ * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
+ */
+#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
+
+/*
+ * ARMv7 low level PMNC access
+ */
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
+#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
+#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
+#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
+#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
+#define ARMV7_PMNC_N_MASK       0x1f
+#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define ARMV7_CNT0              0       /* First event counter */
+#define ARMV7_CCNT              31      /* Cycle counter */
+
+/* Perf Event to low level counters mapping */
+#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENC: counters overflow interrupt disable reg
+ */
+#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define ARMV7_EVTSEL_MASK       0x7f            /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
+#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
+#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
+
+static inline unsigned long armv7_pmnc_read(void)
+{
+        u32 val;
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void armv7_pmnc_write(unsigned long val)
+{
+        val &= ARMV7_PMNC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
+}
+
+static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
+{
+        return pmnc & ARMV7_OVERFLOWED_MASK;
+}
+
+static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum armv7_counters counter)
+{
+        int ret;
+
+        if (counter == ARMV7_CYCLE_COUNTER)
+                ret = pmnc & ARMV7_FLAG_C;
+        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
+                ret = pmnc & ARMV7_FLAG_P(counter);
+        else
+                pr_err("CPU%u checking wrong counter %d overflow status\n",
+                        smp_processor_id(), counter);
+
+        return ret;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
+                pr_err("CPU%u selecting wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7pmu_read_counter(int idx)
+{
+        unsigned long value = 0;
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
+                                     : "=r" (value));
+        } else
+                pr_err("CPU%u reading wrong counter %d\n",
+                        smp_processor_id(), idx);
+
+        return value;
+}
+
+static inline void armv7pmu_write_counter(int idx, u32 value)
+{
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
+                                     : : "r" (value));
+        } else
+                pr_err("CPU%u writing wrong counter %d\n",
+                        smp_processor_id(), idx);
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
+{
+        if (armv7_pmnc_select_counter(idx) == idx) {
+                val &= ARMV7_EVTSEL_MASK;
+                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        }
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENS_C;
+        else
+                val = ARMV7_CNTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
+{
+        u32 val;
+
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENC_C;
+        else
+                val = ARMV7_CNTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENS_C;
+        else
+                val = ARMV7_INTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENC_C;
+        else
+                val = ARMV7_INTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+        u32 val;
+
+        /* Read */
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+        /* Write to clear flags */
+        val &= ARMV7_FLAG_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+        return val;
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+        u32 val;
+        unsigned int cnt;
+
+        printk(KERN_INFO "PMNC registers dump:\n");
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+        printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+        printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+
+        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
+                armv7_pmnc_select_counter(cnt);
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+        }
+}
+#endif
+
+void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Enable counter and interrupt, and set the counter to count
+         * the event that we're interested in.
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Set event (if destined for PMNx counters)
+         * We don't need to set the event if it's a cycle count
+         */
+        if (idx != ARMV7_CYCLE_COUNTER)
+                armv7_pmnc_write_evtsel(idx, hwc->config_base);
+
+        /*
+         * Enable interrupt for this counter
+         */
+        armv7_pmnc_enable_intens(idx);
+
+        /*
+         * Enable counter
+         */
+        armv7_pmnc_enable_counter(idx);
+
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Disable counter and interrupt
+         */
+        spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Disable interrupt for this counter
+         */
+        armv7_pmnc_disable_intens(idx);
+
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * Get and reset the IRQ flags
+         */
+        pmnc = armv7_pmnc_getreset_flags();
+
+        /*
+         * Did an overflow occur?
+         */
+        if (!armv7_pmnc_has_overflowed(pmnc))
+                return IRQ_NONE;
+
+        /*
+         * Handle the counter(s) overflow(s)
+         */
+        regs = get_irq_regs();
+
+        data.addr = 0;
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts enabled. For
+         * platforms that can have the PMU interrupts raised as a PMI, this
+         * will not work.
+         */
+        perf_event_do_pending();
+
+        return IRQ_HANDLED;
+}
+
+static void armv7pmu_start(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        /* Enable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_stop(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&pmu_lock, flags);
+        /* Disable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
+        spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline int armv7_a8_pmu_event_map(int config)
+{
+        int mapping = armv7_a8_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static inline int armv7_a9_pmu_event_map(int config)
+{
+        int mapping = armv7_a9_perf_map[config];
+        if (HW_OP_UNSUPPORTED == mapping)
+                mapping = -EOPNOTSUPP;
+        return mapping;
+}
+
+static u64 armv7pmu_raw_event(u64 config)
+{
+        return config & 0xff;
+}
+
+static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                                  struct hw_perf_event *event)
+{
+        int idx;
+
+        /* Always place a cycle counter into the cycle counter. */
+        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
+                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV7_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * the events counters
+                 */
+                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
+                        if (!test_and_set_bit(idx, cpuc->used_mask))
+                                return idx;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static struct arm_pmu armv7pmu = {
+        .handle_irq             = armv7pmu_handle_irq,
+        .enable                 = armv7pmu_enable_event,
+        .disable                = armv7pmu_disable_event,
+        .raw_event              = armv7pmu_raw_event,
+        .read_counter           = armv7pmu_read_counter,
+        .write_counter          = armv7pmu_write_counter,
+        .get_event_idx          = armv7pmu_get_event_idx,
+        .start                  = armv7pmu_start,
+        .stop                   = armv7pmu_stop,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static u32 __init armv7_reset_read_pmnc(void)
+{
+        u32 nb_cnt;
+
+        /* Initialize & Reset PMNC: C and P bits */
+        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
+
+        /* Read the nb of CNTx counters supported from PMNC */
+        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
+
+        /* Add the CPU cycles counter and return */
+        return nb_cnt + 1;
+}
+
+static int __init
+init_hw_perf_events(void)
+{
+        unsigned long cpuid = read_cpuid_id();
+        unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+        unsigned long part_number = (cpuid & 0xFFF0);
+
+        /* We only support ARM CPUs implemented by ARM at the moment. */
+        if (0x41 == implementor) {
+                switch (part_number) {
+                case 0xB360:    /* ARM1136 */
+                case 0xB560:    /* ARM1156 */
+                case 0xB760:    /* ARM1176 */
+                        armpmu = &armv6pmu;
+                        memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
+                                        sizeof(armv6_perf_cache_map));
+                        perf_max_events = armv6pmu.num_events;
+                        break;
+                case 0xB020:    /* ARM11mpcore */
+                        armpmu = &armv6mpcore_pmu;
+                        memcpy(armpmu_perf_cache_map,
+                               armv6mpcore_perf_cache_map,
+                               sizeof(armv6mpcore_perf_cache_map));
+                        perf_max_events = armv6mpcore_pmu.num_events;
+                        break;
+                case 0xC080:    /* Cortex-A8 */
+                        armv7pmu.name = ARMV7_PMU_CORTEX_A8_NAME;
+                        memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
+                                sizeof(armv7_a8_perf_cache_map));
+                        armv7pmu.event_map = armv7_a8_pmu_event_map;
+                        armpmu = &armv7pmu;
+
+                        /* Reset PMNC and read the nb of CNTx counters
+                            supported */
+                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        perf_max_events = armv7pmu.num_events;
+                        break;
+                case 0xC090:    /* Cortex-A9 */
+                        armv7pmu.name = ARMV7_PMU_CORTEX_A9_NAME;
+                        memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
+                                sizeof(armv7_a9_perf_cache_map));
+                        armv7pmu.event_map = armv7_a9_pmu_event_map;
+                        armpmu = &armv7pmu;
+
+                        /* Reset PMNC and read the nb of CNTx counters
+                            supported */
+                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        perf_max_events = armv7pmu.num_events;
+                        break;
+                default:
+                        pr_info("no hardware support available\n");
+                        perf_max_events = -1;
+                }
+        }
+
+        if (armpmu)
+                pr_info("enabled with %s PMU driver, %d counters available\n",
+                        armpmu->name, armpmu->num_events);
+
+        return 0;
+}
+arch_initcall(init_hw_perf_events);
+
+/*
+ * Callchain handling code.
+ */
+static inline void
+callchain_store(struct perf_callchain_entry *entry,
+                u64 ip)
+{
+        if (entry->nr < PERF_MAX_STACK_DEPTH)
+                entry->ip[entry->nr++] = ip;
+}
+
+/*
+ * The registers we're interested in are at the end of the variable
+ * length saved register structure. The fp points at the end of this
+ * structure so the address of this struct is:
+ * (struct frame_tail *)(xxx->fp)-1
+ *
+ * This code has been adapted from the ARM OProfile support.
+ */
+struct frame_tail {
+        struct frame_tail   *fp;
+        unsigned long       sp;
+        unsigned long       lr;
+} __attribute__((packed));
+
+/*
+ * Get the return address for a single stackframe and return a pointer to the
+ * next frame tail.
+ */
+static struct frame_tail *
+user_backtrace(struct frame_tail *tail,
+               struct perf_callchain_entry *entry)
+{
+        struct frame_tail buftail;
+
+        /* Also check accessibility of one struct frame_tail beyond */
+        if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
+                return NULL;
+        if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
+                return NULL;
+
+        callchain_store(entry, buftail.lr);
+
+        /*
+         * Frame pointers should strictly progress back up the stack
+         * (towards higher addresses).
+         */
+        if (tail >= buftail.fp)
+                return NULL;
+
+        return buftail.fp - 1;
+}
+
+static void
+perf_callchain_user(struct pt_regs *regs,
+                    struct perf_callchain_entry *entry)
+{
+        struct frame_tail *tail;
+
+        callchain_store(entry, PERF_CONTEXT_USER);
+
+        if (!user_mode(regs))
+                regs = task_pt_regs(current);
+
+        tail = (struct frame_tail *)regs->ARM_fp - 1;
+
+        while (tail && !((unsigned long)tail & 0x3))
+                tail = user_backtrace(tail, entry);
+}
+
+/*
+ * Gets called by walk_stackframe() for every stackframe. This will be called
+ * whist unwinding the stackframe and is like a subroutine return so we use
+ * the PC.
+ */
+static int
+callchain_trace(struct stackframe *fr,
+                void *data)
+{
+        struct perf_callchain_entry *entry = data;
+        callchain_store(entry, fr->pc);
+        return 0;
+}
+
+static void
+perf_callchain_kernel(struct pt_regs *regs,
+                      struct perf_callchain_entry *entry)
+{
+        struct stackframe fr;
+
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        fr.fp = regs->ARM_fp;
+        fr.sp = regs->ARM_sp;
+        fr.lr = regs->ARM_lr;
+        fr.pc = regs->ARM_pc;
+        walk_stackframe(&fr, callchain_trace, entry);
+}
+
+static void
+perf_do_callchain(struct pt_regs *regs,
+                  struct perf_callchain_entry *entry)
+{
+        int is_user;
+
+        if (!regs)
+                return;
+
+        is_user = user_mode(regs);
+
+        if (!current || !current->pid)
+                return;
+
+        if (is_user && current->state != TASK_RUNNING)
+                return;
+
+        if (!is_user)
+                perf_callchain_kernel(regs, entry);
+
+        if (current->mm)
+                perf_callchain_user(regs, entry);
+}
+
+static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
+
+struct perf_callchain_entry *
+perf_callchain(struct pt_regs *regs)
+{
+        struct perf_callchain_entry *entry = &__get_cpu_var(pmc_irq_entry);
+
+        entry->nr = 0;
+        perf_do_callchain(regs, entry);
+        return entry;
+}
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
new file mode 100644
index 000000000000..a124312e343f
--- /dev/null
+++ b/arch/arm/kernel/pmu.c
@@ -0,0 +1,103 @@
+/*
+ *  linux/arch/arm/kernel/pmu.c
+ *
+ *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/cpumask.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/pmu.h>
+
+/*
+ * Define the IRQs for the system. We could use something like a platform
+ * device but that seems fairly heavyweight for this. Also, the performance
+ * counters can't be removed or hotplugged.
+ *
+ * Ordering is important: init_pmu() will use the ordering to set the affinity
+ * to the corresponding core. e.g. the first interrupt will go to cpu 0, the
+ * second goes to cpu 1 etc.
+ */
+static const int irqs[] = {
+#if defined(CONFIG_ARCH_OMAP2)
+        3,
+#elif defined(CONFIG_ARCH_BCMRING)
+        IRQ_PMUIRQ,
+#elif defined(CONFIG_MACH_REALVIEW_EB)
+        IRQ_EB11MP_PMU_CPU0,
+        IRQ_EB11MP_PMU_CPU1,
+        IRQ_EB11MP_PMU_CPU2,
+        IRQ_EB11MP_PMU_CPU3,
+#elif defined(CONFIG_ARCH_OMAP3)
+        INT_34XX_BENCH_MPU_EMUL,
+#elif defined(CONFIG_ARCH_IOP32X)
+        IRQ_IOP32X_CORE_PMU,
+#elif defined(CONFIG_ARCH_IOP33X)
+        IRQ_IOP33X_CORE_PMU,
+#elif defined(CONFIG_ARCH_PXA)
+        IRQ_PMU,
+#endif
+};
+
+static const struct pmu_irqs pmu_irqs = {
+        .irqs       = irqs,
+        .num_irqs   = ARRAY_SIZE(irqs),
+};
+
+static volatile long pmu_lock;
+
+const struct pmu_irqs *
+reserve_pmu(void)
+{
+        return test_and_set_bit_lock(0, &pmu_lock) ? ERR_PTR(-EBUSY) :
+                &pmu_irqs;
+}
+EXPORT_SYMBOL_GPL(reserve_pmu);
+
+int
+release_pmu(const struct pmu_irqs *irqs)
+{
+        if (WARN_ON(irqs != &pmu_irqs))
+                return -EINVAL;
+        clear_bit_unlock(0, &pmu_lock);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(release_pmu);
+
+static int
+set_irq_affinity(int irq,
+                 unsigned int cpu)
+{
+#ifdef CONFIG_SMP
+        int err = irq_set_affinity(irq, cpumask_of(cpu));
+        if (err)
+                pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+                           irq, cpu);
+        return err;
+#else
+        return 0;
+#endif
+}
+
+int
+init_pmu(void)
+{
+        int i, err = 0;
+
+        for (i = 0; i < pmu_irqs.num_irqs; ++i) {
+                err = set_irq_affinity(pmu_irqs.irqs[i], i);
+                if (err)
+                        break;
+        }
+
+        return err;
+}
+EXPORT_SYMBOL_GPL(init_pmu);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index a2ea3854cb3c..08f899fb76a6 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -499,10 +499,41 @@ static struct undef_hook thumb_break_hook = {
         .fn             = break_trap,
 };
 
+static int thumb2_break_trap(struct pt_regs *regs, unsigned int instr)
+{
+        unsigned int instr2;
+        void __user *pc;
+
+        /* Check the second half of the instruction.  */
+        pc = (void __user *)(instruction_pointer(regs) + 2);
+
+        if (processor_mode(regs) == SVC_MODE) {
+                instr2 = *(u16 *) pc;
+        } else {
+                get_user(instr2, (u16 __user *)pc);
+        }
+
+        if (instr2 == 0xa000) {
+                ptrace_break(current, regs);
+                return 0;
+        } else {
+                return 1;
+        }
+}
+
+static struct undef_hook thumb2_break_hook = {
+        .instr_mask     = 0xffff,
+        .instr_val      = 0xf7f0,
+        .cpsr_mask      = PSR_T_BIT,
+        .cpsr_val       = PSR_T_BIT,
+        .fn             = thumb2_break_trap,
+};
+
 static int __init ptrace_break_init(void)
 {
         register_undef_hook(&arm_break_hook);
         register_undef_hook(&thumb_break_hook);
+        register_undef_hook(&thumb2_break_hook);
         return 0;
 }
 
@@ -669,7 +700,7 @@ static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
         union vfp_state *vfp = &thread->vfpstate;
         struct user_vfp __user *ufp = data;
 
-        vfp_sync_state(thread);
+        vfp_sync_hwstate(thread);
 
         /* copy the floating point registers */
         if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
@@ -692,7 +723,7 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
         union vfp_state *vfp = &thread->vfpstate;
         struct user_vfp __user *ufp = data;
 
-        vfp_sync_state(thread);
+        vfp_sync_hwstate(thread);
 
         /* copy the floating point registers */
         if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
@@ -703,6 +734,8 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
         if (get_user(vfp->hard.fpscr, &ufp->fpscr))
                 return -EFAULT;
 
+        vfp_flush_hwstate(thread);
+
         return 0;
 }
 #endif
@@ -712,26 +745,10 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
         int ret;
 
         switch (request) {
-                /*
-                 * read word at location "addr" in the child process.
-                 */
-                case PTRACE_PEEKTEXT:
-                case PTRACE_PEEKDATA:
-                        ret = generic_ptrace_peekdata(child, addr, data);
-                        break;
-
                 case PTRACE_PEEKUSR:
                         ret = ptrace_read_user(child, addr, (unsigned long __user *)data);
                         break;
 
-                /*
-                 * write the word at location addr.
-                 */
-                case PTRACE_POKETEXT:
-                case PTRACE_POKEDATA:
-                        ret = generic_ptrace_pokedata(child, addr, data);
-                        break;
-
                 case PTRACE_POKEUSR:
                         ret = ptrace_write_user(child, addr, data);
                         break;
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 621acad8ea43..c91c77b54dea 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -24,6 +24,7 @@
 #include <linux/interrupt.h>
 #include <linux/smp.h>
 #include <linux/fs.h>
+#include <linux/proc_fs.h>
 
 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -118,7 +119,7 @@ EXPORT_SYMBOL(elf_platform);
 
 static const char *cpu_name;
 static const char *machine_name;
-static char __initdata command_line[COMMAND_LINE_SIZE];
+static char __initdata cmd_line[COMMAND_LINE_SIZE];
 
 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
@@ -418,10 +419,11 @@ static int __init arm_add_memory(unsigned long start, unsigned long size)
  * Pick out the memory size.  We look for mem=size@start,
  * where start and size are "size[KkMm]"
  */
-static void __init early_mem(char **p)
+static int __init early_mem(char *p)
 {
         static int usermem __initdata = 0;
         unsigned long size, start;
+        char *endp;
 
         /*
          * If the user specifies memory size, we
@@ -434,52 +436,15 @@ static void __init early_mem(char **p)
         }
 
         start = PHYS_OFFSET;
-        size  = memparse(*p, p);
-        if (**p == '@')
-                start = memparse(*p + 1, p);
+        size  = memparse(p, &endp);
+        if (*endp == '@')
+                start = memparse(endp + 1, NULL);
 
         arm_add_memory(start, size);
-}
-__early_param("mem=", early_mem);
 
-/*
- * Initial parsing of the command line.
- */
-static void __init parse_cmdline(char **cmdline_p, char *from)
-{
-        char c = ' ', *to = command_line;
-        int len = 0;
-
-        for (;;) {
-                if (c == ' ') {
-                        extern struct early_params __early_begin, __early_end;
-                        struct early_params *p;
-
-                        for (p = &__early_begin; p < &__early_end; p++) {
-                                int arglen = strlen(p->arg);
-
-                                if (memcmp(from, p->arg, arglen) == 0) {
-                                        if (to != command_line)
-                                                to -= 1;
-                                        from += arglen;
-                                        p->fn(&from);
-
-                                        while (*from != ' ' && *from != '\0')
-                                                from++;
-                                        break;
-                                }
-                        }
-                }
-                c = *from++;
-                if (!c)
-                        break;
-                if (COMMAND_LINE_SIZE <= ++len)
-                        break;
-                *to++ = c;
-        }
-        *to = '\0';
-        *cmdline_p = command_line;
+        return 0;
 }
+early_param("mem", early_mem);
 
 static void __init
 setup_ramdisk(int doload, int prompt, int image_start, unsigned int rd_sz)
@@ -740,9 +705,15 @@ void __init setup_arch(char **cmdline_p)
         init_mm.end_data   = (unsigned long) _edata;
         init_mm.brk        = (unsigned long) _end;
 
-        memcpy(boot_command_line, from, COMMAND_LINE_SIZE);
-        boot_command_line[COMMAND_LINE_SIZE-1] = '\0';
-        parse_cmdline(cmdline_p, from);
+        /* parse_early_param needs a boot_command_line */
+        strlcpy(boot_command_line, from, COMMAND_LINE_SIZE);
+
+        /* populate cmd_line too for later use, preserving boot_command_line */
+        strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
+        *cmdline_p = cmd_line;
+
+        parse_early_param();
+
         paging_init(mdesc);
         request_standard_resources(&meminfo, mdesc);
 
@@ -783,9 +754,21 @@ static int __init topology_init(void)
 
         return 0;
 }
-
 subsys_initcall(topology_init);
 
+#ifdef CONFIG_HAVE_PROC_CPU
+static int __init proc_cpu_init(void)
+{
+        struct proc_dir_entry *res;
+
+        res = proc_mkdir("cpu", NULL);
+        if (!res)
+                return -ENOMEM;
+        return 0;
+}
+fs_initcall(proc_cpu_init);
+#endif
+
 static const char *hwcap_str[] = {
         "swp",
         "half",
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index d38cdf2c8276..28753805d2d1 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -10,11 +10,6 @@
  *
  *  This file contains the ARM-specific time handling details:
  *  reading the RTC at bootup, etc...
- *
- *  1994-07-02  Alan Modra
- *              fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
- *  1998-12-20  Updated NTP code according to technical memorandum Jan '96
- *              "A Kernel Model for Precision Timekeeping" by Dave Mills
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
@@ -77,11 +72,6 @@ unsigned long profile_pc(struct pt_regs *regs)
 EXPORT_SYMBOL(profile_pc);
 #endif
 
-/*
- * hook for setting the RTC's idea of the current time.
- */
-int (*set_rtc)(void);
-
 #ifndef CONFIG_GENERIC_TIME
 static unsigned long dummy_gettimeoffset(void)
 {
@@ -89,140 +79,6 @@ static unsigned long dummy_gettimeoffset(void)
 }
 #endif
 
-static unsigned long next_rtc_update;
-
-/*
- * If we have an externally synchronized linux clock, then update
- * CMOS clock accordingly every ~11 minutes.  set_rtc() has to be
- * called as close as possible to 500 ms before the new second
- * starts.
- */
-static inline void do_set_rtc(void)
-{
-        if (!ntp_synced() || set_rtc == NULL)
-                return;
-
-        if (next_rtc_update &&
-            time_before((unsigned long)xtime.tv_sec, next_rtc_update))
-                return;
-
-        if (xtime.tv_nsec < 500000000 - ((unsigned) tick_nsec >> 1) &&
-            xtime.tv_nsec >= 500000000 + ((unsigned) tick_nsec >> 1))
-                return;
-
-        if (set_rtc())
-                /*
-                 * rtc update failed.  Try again in 60s
-                 */
-                next_rtc_update = xtime.tv_sec + 60;
-        else
-                next_rtc_update = xtime.tv_sec + 660;
-}
-
-#ifdef CONFIG_LEDS
-
-static void dummy_leds_event(led_event_t evt)
-{
-}
-
-void (*leds_event)(led_event_t) = dummy_leds_event;
-
-struct leds_evt_name {
-        const char      name[8];
-        int             on;
-        int             off;
-};
-
-static const struct leds_evt_name evt_names[] = {
-        { "amber", led_amber_on, led_amber_off },
-        { "blue",  led_blue_on,  led_blue_off  },
-        { "green", led_green_on, led_green_off },
-        { "red",   led_red_on,   led_red_off   },
-};
-
-static ssize_t leds_store(struct sys_device *dev,
-                        struct sysdev_attribute *attr,
-                        const char *buf, size_t size)
-{
-        int ret = -EINVAL, len = strcspn(buf, " ");
-
-        if (len > 0 && buf[len] == '\0')
-                len--;
-
-        if (strncmp(buf, "claim", len) == 0) {
-                leds_event(led_claim);
-                ret = size;
-        } else if (strncmp(buf, "release", len) == 0) {
-                leds_event(led_release);
-                ret = size;
-        } else {
-                int i;
-
-                for (i = 0; i < ARRAY_SIZE(evt_names); i++) {
-                        if (strlen(evt_names[i].name) != len ||
-                            strncmp(buf, evt_names[i].name, len) != 0)
-                                continue;
-                        if (strncmp(buf+len, " on", 3) == 0) {
-                                leds_event(evt_names[i].on);
-                                ret = size;
-                        } else if (strncmp(buf+len, " off", 4) == 0) {
-                                leds_event(evt_names[i].off);
-                                ret = size;
-                        }
-                        break;
-                }
-        }
-        return ret;
-}
-
-static SYSDEV_ATTR(event, 0200, NULL, leds_store);
-
-static int leds_suspend(struct sys_device *dev, pm_message_t state)
-{
-        leds_event(led_stop);
-        return 0;
-}
-
-static int leds_resume(struct sys_device *dev)
-{
-        leds_event(led_start);
-        return 0;
-}
-
-static int leds_shutdown(struct sys_device *dev)
-{
-        leds_event(led_halted);
-        return 0;
-}
-
-static struct sysdev_class leds_sysclass = {
-        .name           = "leds",
-        .shutdown       = leds_shutdown,
-        .suspend        = leds_suspend,
-        .resume         = leds_resume,
-};
-
-static struct sys_device leds_device = {
-        .id             = 0,
-        .cls            = &leds_sysclass,
-};
-
-static int __init leds_init(void)
-{
-        int ret;
-        ret = sysdev_class_register(&leds_sysclass);
-        if (ret == 0)
-                ret = sysdev_register(&leds_device);
-        if (ret == 0)
-                ret = sysdev_create_file(&leds_device, &attr_event);
-        return ret;
-}
-
-device_initcall(leds_init);
-
-EXPORT_SYMBOL(leds_event);
-#endif
-
 #ifdef CONFIG_LEDS_TIMER
 static inline void do_leds(void)
 {
@@ -295,39 +151,6 @@ int do_settimeofday(struct timespec *tv)
 EXPORT_SYMBOL(do_settimeofday);
 #endif /* !CONFIG_GENERIC_TIME */
 
-/**
- * save_time_delta - Save the offset between system time and RTC time
- * @delta: pointer to timespec to store delta
- * @rtc: pointer to timespec for current RTC time
- *
- * Return a delta between the system time and the RTC time, such
- * that system time can be restored later with restore_time_delta()
- */
-void save_time_delta(struct timespec *delta, struct timespec *rtc)
-{
-        set_normalized_timespec(delta,
-                                xtime.tv_sec - rtc->tv_sec,
-                                xtime.tv_nsec - rtc->tv_nsec);
-}
-EXPORT_SYMBOL(save_time_delta);
-
-/**
- * restore_time_delta - Restore the current system time
- * @delta: delta returned by save_time_delta()
- * @rtc: pointer to timespec for current RTC time
- */
-void restore_time_delta(struct timespec *delta, struct timespec *rtc)
-{
-        struct timespec ts;
-
-        set_normalized_timespec(&ts,
-                                delta->tv_sec + rtc->tv_sec,
-                                delta->tv_nsec + rtc->tv_nsec);
-
-        do_settimeofday(&ts);
-}
-EXPORT_SYMBOL(restore_time_delta);
-
 #ifndef CONFIG_GENERIC_CLOCKEVENTS
 /*
  * Kernel system timer support.
@@ -336,7 +159,6 @@ void timer_tick(void)
 {
         profile_tick(CPU_PROFILING);
         do_leds();
-        do_set_rtc();
         write_seqlock(&xtime_lock);
         do_timer(1);
         write_sequnlock(&xtime_lock);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3f361a783f43..1621e5327b2a 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -12,15 +12,17 @@
  *  'linux/arch/arm/lib/traps.S'.  Mostly a debugging aid, but will probably
  *  kill the offending process.
  */
-#include <linux/module.h>
 #include <linux/signal.h>
-#include <linux/spinlock.h>
 #include <linux/personality.h>
 #include <linux/kallsyms.h>
-#include <linux/delay.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
 #include <linux/hardirq.h>
+#include <linux/kdebug.h>
+#include <linux/module.h>
+#include <linux/kexec.h>
+#include <linux/delay.h>
 #include <linux/init.h>
-#include <linux/uaccess.h>
 
 #include <asm/atomic.h>
 #include <asm/cacheflush.h>
@@ -224,14 +226,21 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
 #define S_SMP ""
 #endif
 
-static void __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
+static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
 {
         struct task_struct *tsk = thread->task;
         static int die_counter;
+        int ret;
 
         printk(KERN_EMERG "Internal error: %s: %x [#%d]" S_PREEMPT S_SMP "\n",
                str, err, ++die_counter);
         sysfs_printk_last_file();
+
+        /* trap and error numbers are mostly meaningless on ARM */
+        ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV);
+        if (ret == NOTIFY_STOP)
+                return ret;
+
         print_modules();
         __show_regs(regs);
         printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n",
@@ -243,6 +252,8 @@ static void __die(const char *str, int err, struct thread_info *thread, struct p
                 dump_backtrace(regs, tsk);
                 dump_instr(KERN_EMERG, regs);
         }
+
+        return ret;
 }
 
 DEFINE_SPINLOCK(die_lock);
@@ -250,16 +261,21 @@ DEFINE_SPINLOCK(die_lock);
 /*
  * This function is protected against re-entrancy.
  */
-NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
+void die(const char *str, struct pt_regs *regs, int err)
 {
         struct thread_info *thread = current_thread_info();
+        int ret;
 
         oops_enter();
 
         spin_lock_irq(&die_lock);
         console_verbose();
         bust_spinlocks(1);
-        __die(str, err, thread, regs);
+        ret = __die(str, err, thread, regs);
+
+        if (regs && kexec_should_crash(thread->task))
+                crash_kexec(regs);
+
         bust_spinlocks(0);
         add_taint(TAINT_DIE);
         spin_unlock_irq(&die_lock);
@@ -267,11 +283,10 @@ NORET_TYPE void die(const char *str, struct pt_regs *regs, int err)
 
         if (in_interrupt())
                 panic("Fatal exception in interrupt");
-
         if (panic_on_oops)
                 panic("Fatal exception");
-
-        do_exit(SIGSEGV);
+        if (ret != NOTIFY_STOP)
+                do_exit(SIGSEGV);
 }
 
 void arm_notify_die(const char *str, struct pt_regs *regs,
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 4957e13ef55b..b16c07914b55 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -43,10 +43,6 @@ SECTIONS
 
                 INIT_SETUP(16)
 
-                __early_begin = .;
-                        *(.early_param.init)
-                __early_end = .;
-
                 INIT_CALLS
                 CON_INITCALL
                 SECURITY_INITCALL
diff --git a/arch/arm/mach-aaec2000/include/mach/debug-macro.S b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
index 0b6351d7c389..a9cac368bfe6 100644
--- a/arch/arm/mach-aaec2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-aaec2000/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
  */
 
 #include "hardware.h"
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x80000000                @ physical
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0b2ee953f164..2db43a5ddd9b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -89,6 +89,12 @@ config ARCH_AT91CAP9
         select GENERIC_CLOCKEVENTS
         select HAVE_FB_ATMEL
 
+config ARCH_AT572D940HF
+        bool "AT572D940HF"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+
 config ARCH_AT91X40
         bool "AT91x40"
 
@@ -390,6 +396,23 @@ endif
 
 # ----------------------------------------------------------
 
+if ARCH_AT572D940HF
+
+comment "AT572D940HF Board Type"
+
+config MACH_AT572D940HFEB
+        bool "AT572D940HF-EK"
+        depends on ARCH_AT572D940HF
+        select HAVE_AT91_DATAFLASH_CARD
+        select HAVE_NAND_ATMEL_BUSWIDTH_16
+        help
+          Select this if you are using Atmel's AT572D940HF-EK evaluation kit.
+          <http://www.atmel.com/products/diopsis/default.asp>
+
+endif
+
+# ----------------------------------------------------------
+
 if ARCH_AT91X40
 
 comment "AT91X40 Board Type"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 709fbad4a3ee..027dd570dcc3 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_ARCH_AT91SAM9RL)	+= at91sam9rl.o at91sam926x_time.o at91sam9rl_devi
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
  obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT572D940HF)  += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
 
 # AT91RM9200 board-specific support
@@ -69,6 +70,9 @@ obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
 
+# AT572D940HF board-specific support
+obj-$(CONFIG_MACH_AT572D940HFEB) += board-at572d940hf_ek.o
+
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
 
diff --git a/arch/arm/mach-at91/at572d940hf.c b/arch/arm/mach-at91/at572d940hf.c
new file mode 100644
index 000000000000..a6b9c68c003a
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf.c
@@ -0,0 +1,377 @@
+/*
+ * arch/arm/mach-at91/at572d940hf.c
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/module.h>
+
+#include <asm/mach/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at572d940hf.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+
+#include "generic.h"
+#include "clock.h"
+
+static struct map_desc at572d940hf_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT572D940HF_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT572D940HF_SRAM_BASE),
+                .length         = AT572D940HF_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+        .name           = "macb_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+        .name           = "mci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MCI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udc_clk = {
+        .name           = "udc_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UDP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc2_clk = {
+        .name           = "ssc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc0_clk = {
+        .name           = "tc0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc1_clk = {
+        .name           = "tc1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tc2_clk = {
+        .name           = "tc2_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TC2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_UHP,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc3_clk = {
+        .name           = "ssc3_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_SSC3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can0_clk = {
+        .name           = "can0_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk can1_clk = {
+        .name           = "can1_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_CAN1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mAgicV_clk = {
+        .name           = "mAgicV_clk",
+        .pmc_mask       = 1 << AT572D940HF_ID_MSIRQ0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+
+
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &macb_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &mmc_clk,
+        &udc_clk,
+        &twi0_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &ssc2_clk,
+        &tc0_clk,
+        &tc1_clk,
+        &tc2_clk,
+        &ohci_clk,
+        &ssc3_clk,
+        &twi1_clk,
+        &can0_clk,
+        &can1_clk,
+        &mAgicV_clk,
+        /* irq0 .. irq2 */
+};
+
+/*
+ * The five programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static struct clk pck2 = {
+        .name           = "pck2",
+        .pmc_mask       = AT91_PMC_PCK2,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 2,
+};
+static struct clk pck3 = {
+        .name           = "pck3",
+        .pmc_mask       = AT91_PMC_PCK3,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 3,
+};
+
+static struct clk mAgicV_mem_clk = {
+        .name           = "mAgicV_mem_clk",
+        .pmc_mask       = AT91_PMC_PCK4,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 4,
+};
+
+/* HClocks */
+static struct clk hck0 = {
+        .name           = "hck0",
+        .pmc_mask       = AT91_PMC_HCK0,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 0,
+};
+static struct clk hck1 = {
+        .name           = "hck1",
+        .pmc_mask       = AT91_PMC_HCK1,
+        .type           = CLK_TYPE_SYSTEM,
+        .id             = 1,
+};
+
+static void __init at572d940hf_register_clocks(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+
+        clk_register(&pck0);
+        clk_register(&pck1);
+        clk_register(&pck2);
+        clk_register(&pck3);
+        clk_register(&mAgicV_mem_clk);
+
+        clk_register(&hck0);
+        clk_register(&hck1);
+}
+
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+
+static struct at91_gpio_bank at572d940hf_gpio[] = {
+        {
+                .id             = AT572D940HF_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT572D940HF_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }
+};
+
+static void at572d940hf_reset(void)
+{
+        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+
+
+/* --------------------------------------------------------------------
+ *  AT572D940HF processor initialization
+ * -------------------------------------------------------------------- */
+
+void __init at572d940hf_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at572d940hf_io_desc, ARRAY_SIZE(at572d940hf_io_desc));
+
+        at91_arch_reset = at572d940hf_reset;
+        at91_extern_irq = (1 << AT572D940HF_ID_IRQ0) | (1 << AT572D940HF_ID_IRQ1)
+                        | (1 << AT572D940HF_ID_IRQ2);
+
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+
+        /* Register the processor-specific clocks */
+        at572d940hf_register_clocks();
+
+        /* Register GPIO subsystem */
+        at91_gpio_init(at572d940hf_gpio, 3);
+}
+
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller */
+        7,      /* System Peripherals */
+        0,      /* Parallel IO Controller A */
+        0,      /* Parallel IO Controller B */
+        0,      /* Parallel IO Controller C */
+        3,      /* Ethernet */
+        6,      /* USART 0 */
+        6,      /* USART 1 */
+        6,      /* USART 2 */
+        0,      /* Multimedia Card Interface */
+        4,      /* USB Device Port */
+        0,      /* Two-Wire Interface 0 */
+        6,      /* Serial Peripheral Interface 0 */
+        6,      /* Serial Peripheral Interface 1 */
+        5,      /* Serial Synchronous Controller 0 */
+        5,      /* Serial Synchronous Controller 1 */
+        5,      /* Serial Synchronous Controller 2 */
+        0,      /* Timer Counter 0 */
+        0,      /* Timer Counter 1 */
+        0,      /* Timer Counter 2 */
+        3,      /* USB Host port */
+        3,      /* Serial Synchronous Controller 3 */
+        0,      /* Two-Wire Interface 1 */
+        0,      /* CAN Controller 0 */
+        0,      /* CAN Controller 1 */
+        0,      /* mAgicV HALT line */
+        0,      /* mAgicV SIRQ0 line */
+        0,      /* mAgicV exception line */
+        0,      /* mAgicV end of DMA line */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+        0,      /* Advanced Interrupt Controller */
+};
+
+void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at572d940hf_default_irq_priority;
+
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
+
diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
new file mode 100644
index 000000000000..0fc20a240782
--- /dev/null
+++ b/arch/arm/mach-at91/at572d940hf_devices.c
@@ -0,0 +1,970 @@
+/*
+ * arch/arm/mach-at91/at572d940hf_devices.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
+ * Copyright (C) 2005 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at572d940hf.h>
+#include <mach/at572d940hf_matrix.h>
+#include <mach/at91sam9_smc.h>
+
+#include "generic.h"
+#include "sam9_smc.h"
+
+
+/* --------------------------------------------------------------------
+ *  USB Host
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_data;
+
+static struct resource usbh_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_UHP_BASE,
+                .end    = AT572D940HF_UHP_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UHP,
+                .end    = AT572D940HF_ID_UHP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_usbh_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_data,
+        },
+        .resource       = usbh_resources,
+        .num_resources  = ARRAY_SIZE(usbh_resources),
+};
+
+void __init at91_add_device_usbh(struct at91_usbh_data *data)
+{
+        if (!data)
+                return;
+
+        usbh_data = *data;
+        platform_device_register(&at572d940hf_usbh_device);
+
+}
+#else
+void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  USB Device (Gadget)
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_USB_GADGET_AT91
+static struct at91_udc_data udc_data;
+
+static struct resource udc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_UDP,
+                .end    = AT572D940HF_BASE_UDP + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_UDP,
+                .end    = AT572D940HF_ID_UDP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_udc_device = {
+        .name           = "at91_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data          = &udc_data,
+        },
+        .resource       = udc_resources,
+        .num_resources  = ARRAY_SIZE(udc_resources),
+};
+
+void __init at91_add_device_udc(struct at91_udc_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->vbus_pin) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+        }
+
+        /* Pullup pin is handled internally */
+
+        udc_data = *data;
+        platform_device_register(&at572d940hf_udc_device);
+}
+#else
+void __init at91_add_device_udc(struct at91_udc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_EMAC,
+                .end    = AT572D940HF_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_EMAC,
+                .end    = AT572D940HF_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                        .dma_mask               = &eth_dmamask,
+                        .coherent_dma_mask      = DMA_BIT_MASK(32),
+                        .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+
+        /* Only RMII is supported */
+        data->is_rmii = 1;
+
+        /* Pins used for RMII */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA20, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA23, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA21, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA22, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* EMDC */
+
+        eth_data = *data;
+        platform_device_register(&at572d940hf_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  MMC / SD
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
+static u64 mmc_dmamask = DMA_BIT_MASK(32);
+static struct at91_mmc_data mmc_data;
+
+static struct resource mmc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_MCI,
+                .end    = AT572D940HF_BASE_MCI + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_MCI,
+                .end    = AT572D940HF_ID_MCI,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_mmc_device = {
+        .name           = "at91_mci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &mmc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &mmc_data,
+        },
+        .resource       = mmc_resources,
+        .num_resources  = ARRAY_SIZE(mmc_resources),
+};
+
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
+{
+        if (!data)
+                return;
+
+        /* input/irq */
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 1);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        if (data->wp_pin)
+                at91_set_gpio_input(data->wp_pin, 1);
+        if (data->vcc_pin)
+                at91_set_gpio_output(data->vcc_pin, 0);
+
+        /* CLK */
+        at91_set_A_periph(AT91_PIN_PC22, 0);
+
+        /* CMD */
+        at91_set_A_periph(AT91_PIN_PC23, 1);
+
+        /* DAT0, maybe DAT1..DAT3 */
+        at91_set_A_periph(AT91_PIN_PC24, 1);
+        if (data->wire4) {
+                at91_set_A_periph(AT91_PIN_PC25, 1);
+                at91_set_A_periph(AT91_PIN_PC26, 1);
+                at91_set_A_periph(AT91_PIN_PC27, 1);
+        }
+
+        mmc_data = *data;
+        platform_device_register(&at572d940hf_mmc_device);
+}
+#else
+void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+
+#define NAND_BASE       AT91_CHIPSELECT_3
+
+static struct resource nand_resources[] = {
+        {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at572d940hf_nand_device = {
+        .name           = "atmel_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+        unsigned long csa;
+
+        if (!data)
+                return;
+
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+
+        at91_set_A_periph(AT91_PIN_PB28, 0);            /* A[22] */
+        at91_set_B_periph(AT91_PIN_PA28, 0);            /* NANDOE */
+        at91_set_B_periph(AT91_PIN_PA29, 0);            /* NANDWE */
+
+        nand_data = *data;
+        platform_device_register(&at572d940hf_nand_device);
+}
+
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+
+static struct i2c_gpio_platform_data pdata = {
+        .sda_pin                = AT91_PIN_PC7,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PC8,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+
+static struct platform_device at572d940hf_twi_device {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &pdata,
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        at91_set_GPIO_periph(AT91_PIN_PC7, 1);          /* TWD (SDA) */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+        at91_set_GPIO_periph(AT91_PIN_PA8, 1);          /* TWCK (SCL) */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi_device);
+}
+
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+
+static struct resource twi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI0,
+                .end    = AT572D940HF_BASE_TWI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI0,
+                .end    = AT572D940HF_ID_TWI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_twi0_device = {
+        .name           = "at91_i2c",
+        .id             = 0,
+        .resource       = twi0_resources,
+        .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+
+static struct resource twi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TWI1,
+                .end    = AT572D940HF_BASE_TWI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TWI1,
+                .end    = AT572D940HF_ID_TWI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_twi1_device = {
+        .name           = "at91_i2c",
+        .id             = 1,
+        .resource       = twi1_resources,
+        .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
+{
+        /* pins used for TWI0 interface */
+        at91_set_A_periph(AT91_PIN_PC7, 0);             /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC7, 1);
+
+        at91_set_A_periph(AT91_PIN_PC8, 0);             /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC8, 1);
+
+        /* pins used for TWI1 interface */
+        at91_set_A_periph(AT91_PIN_PC20, 0);            /* TWD */
+        at91_set_multi_drive(AT91_PIN_PC20, 1);
+
+        at91_set_A_periph(AT91_PIN_PC21, 0);            /* TWCK */
+        at91_set_multi_drive(AT91_PIN_PC21, 1);
+
+        i2c_register_board_info(0, devices, nr_devices);
+        platform_device_register(&at572d940hf_twi0_device);
+        platform_device_register(&at572d940hf_twi1_device);
+}
+#else
+void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI0,
+                .end    = AT572D940HF_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI0,
+                .end    = AT572D940HF_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PA4, AT91_PIN_PA5, AT91_PIN_PA6 };
+
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_SPI1,
+                .end    = AT572D940HF_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_SPI1,
+                .end    = AT572D940HF_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PC3, AT91_PIN_PC4, AT91_PIN_PC5, AT91_PIN_PC6 };
+
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+
+        spi_register_board_info(devices, nr_devices);
+
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
+
+                at91_clock_associate("spi0_clk", &at572d940hf_spi0_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PC0, 0);     /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PC1, 0);     /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PC2, 0);     /* SPI1_SPCK */
+
+                at91_clock_associate("spi1_clk", &at572d940hf_spi1_device.dev, "spi_clk");
+                platform_device_register(&at572d940hf_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  Timer/Counter blocks
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_ATMEL_TCLIB
+
+static struct resource tcb_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_TCB,
+                .end    = AT572D940HF_BASE_TCB + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_TC0,
+                .end    = AT572D940HF_ID_TC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = AT572D940HF_ID_TC1,
+                .end    = AT572D940HF_ID_TC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = AT572D940HF_ID_TC2,
+                .end    = AT572D940HF_ID_TC2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device at572d940hf_tcb_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb_resources,
+        .num_resources  = ARRAY_SIZE(tcb_resources),
+};
+
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has a separate clock and irq for each TC channel */
+        at91_clock_associate("tc0_clk", &at572d940hf_tcb_device.dev, "t0_clk");
+        at91_clock_associate("tc1_clk", &at572d940hf_tcb_device.dev, "t1_clk");
+        at91_clock_associate("tc2_clk", &at572d940hf_tcb_device.dev, "t2_clk");
+        platform_device_register(&at572d940hf_tcb_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+static struct platform_device at572d940hf_rtt_device = {
+        .name           = "at91_rtt",
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+
+static void __init at91_add_device_rtt(void)
+{
+        platform_device_register(&at572d940hf_rtt_device);
+}
+
+
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
+static struct platform_device at572d940hf_wdt_device = {
+        .name           = "at91_wdt",
+        .id             = -1,
+        .num_resources  = 0,
+};
+
+static void __init at91_add_device_watchdog(void)
+{
+        platform_device_register(&at572d940hf_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &dbgu_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &dbgu_data,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PC31, 1);            /* DTXD */
+        at91_set_A_periph(AT91_PIN_PC30, 0);            /* DRXD */
+}
+
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US0,
+                .end    = AT572D940HF_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US0,
+                .end    = AT572D940HF_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &uart0_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart0_data,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+
+static inline void configure_usart0_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PA8, 1);             /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PA7, 0);             /* RXD0 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PA10, 0);    /* RTS0 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PA9, 0);     /* CTS0 */
+}
+
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US1,
+                .end    = AT572D940HF_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US1,
+                .end    = AT572D940HF_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .dma_mask               = &uart1_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart1_data,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+
+static inline void configure_usart1_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC10, 1);            /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PC9 , 0);            /* RXD1 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC12, 0);    /* RTS1 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC11, 0);    /* CTS1 */
+}
+
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_BASE_US2,
+                .end    = AT572D940HF_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT572D940HF_ID_US2,
+                .end    = AT572D940HF_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device at572d940hf_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .dma_mask               = &uart2_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart2_data,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+
+static inline void configure_usart2_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PC15, 1);            /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PC14, 0);            /* RXD2 */
+
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PC17, 0);    /* RTS2 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PC16, 0);    /* CTS2 */
+}
+
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+        struct platform_device *pdev;
+
+        switch (id) {
+                case 0:         /* DBGU */
+                        pdev = &at572d940hf_dbgu_device;
+                        configure_dbgu_pins();
+                        at91_clock_associate("mck", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US0:
+                        pdev = &at572d940hf_uart0_device;
+                        configure_usart0_pins(pins);
+                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US1:
+                        pdev = &at572d940hf_uart1_device;
+                        configure_usart1_pins(pins);
+                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                        break;
+                case AT572D940HF_ID_US2:
+                        pdev = &at572d940hf_uart2_device;
+                        configure_usart2_pins(pins);
+                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                        break;
+                default:
+                        return;
+        }
+        pdev->id = portnr;              /* update to mapped ID */
+
+        if (portnr < ATMEL_MAX_UART)
+                at91_uarts[portnr] = pdev;
+}
+
+void __init at91_set_serial_console(unsigned portnr)
+{
+        if (portnr < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[portnr];
+}
+
+void __init at91_add_device_serial(void)
+{
+        int i;
+
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+
+
+/* --------------------------------------------------------------------
+ *  mAgic
+ * -------------------------------------------------------------------- */
+
+#ifdef CONFIG_MAGICV
+static struct resource mAgic_resources[] = {
+        {
+                .start = AT91_MAGIC_PM_BASE,
+                .end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_I_BASE,
+                .end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_F_BASE,
+                .end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_DM_DB_BASE,
+                .end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_REGS_BASE,
+                .end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = AT91_MAGIC_EXTPAGE_BASE,
+                .end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start  = AT572D940HF_ID_MSIRQ0,
+                .end    = AT572D940HF_ID_MSIRQ0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MHALT,
+                .end    = AT572D940HF_ID_MHALT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEXC,
+                .end    = AT572D940HF_ID_MEXC,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = AT572D940HF_ID_MEDMA,
+                .end    = AT572D940HF_ID_MEDMA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mAgic_device = {
+        .name           = "mAgic",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(mAgic_resources),
+        .resource       = mAgic_resources,
+};
+
+void __init at91_add_device_mAgic(void)
+{
+        platform_device_register(&mAgic_device);
+}
+#else
+void __init at91_add_device_mAgic(void) {}
+#endif
+
+
+/* -------------------------------------------------------------------- */
+
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        at91_add_device_rtt();
+        at91_add_device_watchdog();
+        at91_add_device_tc();
+        return 0;
+}
+
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
new file mode 100644
index 000000000000..5daff277f53e
--- /dev/null
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -0,0 +1,328 @@
+/*
+ * linux/arch/arm/mach-at91/board-at572d940hf_ek.c
+ *
+ * Copyright (C) 2008 Atmel Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ds1305.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+
+static void __init eb_map_io(void)
+{
+        /* Initialize processor: 12.500 MHz crystal */
+        at572d940hf_initialize(12000000);
+
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+
+        /* USART0 on ttyS1. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US0, 1, 0);
+
+        /* USART1 on ttyS2. (Rx & Tx only) */
+        at91_register_uart(AT572D940HF_ID_US1, 2, 0);
+
+        /* USART2 on ttyS3. (Tx & Rx only */
+        at91_register_uart(AT572D940HF_ID_US2, 3, 0);
+
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+
+static void __init eb_init_irq(void)
+{
+        at572d940hf_init_interrupts(NULL);
+}
+
+
+/*
+ * USB Host Port
+ */
+static struct at91_usbh_data __initdata eb_usbh_data = {
+        .ports          = 2,
+};
+
+
+/*
+ * USB Device Port
+ */
+static struct at91_udc_data __initdata eb_udc_data = {
+        .vbus_pin       = 0,            /* no VBUS detection,UDC always on */
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+
+
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata eb_mmc_data = {
+        .wire4          = 1,
+/*      .det_pin        = ... not connected */
+/*      .wp_pin         = ... not connected */
+/*      .vcc_pin        = ... not connected */
+};
+
+
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata eb_eth_data = {
+        .phy_irq_pin    = AT91_PIN_PB25,
+        .is_rmii        = 1,
+};
+
+/*
+ * NOR flash
+ */
+
+static struct mtd_partition eb_nor_partitions[] = {
+        {
+                .name           = "Raw Environment",
+                .offset         = 0,
+                .size           = SZ_4M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "OS FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = 3 * SZ_1M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "APP FS",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+                .mask_flags     = 0,
+        },
+};
+
+static void nor_flash_set_vpp(struct map_info* mi, int i) {
+};
+
+static struct physmap_flash_data nor_flash_data = {
+        .width          = 4,
+        .parts          = eb_nor_partitions,
+        .nr_parts       = ARRAY_SIZE(eb_nor_partitions),
+        .set_vpp        = nor_flash_set_vpp,
+};
+
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = AT91_CHIPSELECT_0,
+                .end    = AT91_CHIPSELECT_0 + SZ_16M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                                .platform_data = &nor_flash_data,
+                        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+
+static struct sam9_smc_config __initdata eb_nor_smc_config = {
+        .ncs_read_setup         = 1,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 7,
+        .nrd_pulse              = 7,
+        .ncs_write_pulse        = 7,
+        .nwe_pulse              = 7,
+
+        .read_cycle             = 9,
+        .write_cycle            = 9,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_32,
+        .tdf_cycles             = 1,
+};
+
+static void __init eb_add_device_nor(void)
+{
+        /* configure chip-select 0 (NOR) */
+        sam9_smc_configure(0, &eb_nor_smc_config);
+        platform_device_register(&nor_flash);
+}
+
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata eb_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = SZ_16M,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        }
+};
+
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(eb_nand_partition);
+        return eb_nand_partition;
+}
+
+static struct atmel_nand_data __initdata eb_nand_data = {
+        .ale            = 22,
+        .cle            = 21,
+/*      .det_pin        = ... not connected */
+/*      .rdy_pin        = AT91_PIN_PC16, */
+        .enable_pin     = AT91_PIN_PA15,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+
+static struct sam9_smc_config __initdata eb_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 0,
+        .ncs_write_setup        = 1,
+        .nwe_setup              = 1,
+
+        .ncs_read_pulse         = 3,
+        .nrd_pulse              = 3,
+        .ncs_write_pulse        = 3,
+        .nwe_pulse              = 3,
+
+        .read_cycle             = 5,
+        .write_cycle            = 5,
+
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 12,
+};
+
+static void __init eb_add_device_nand(void)
+{
+        /* setup bus-width (8 or 16) */
+        if (eb_nand_data.bus_width_16)
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                eb_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &eb_nand_smc_config);
+
+        at91_add_device_nand(&eb_nand_data);
+}
+
+
+/*
+ * SPI devices
+ */
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = AT572D940HF_ID_IRQ1,
+                .end    = AT572D940HF_ID_IRQ1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct ds1305_platform_data ds1306_data = {
+        .is_ds1306      = true,
+        .en_1hz         = false,
+};
+
+static struct spi_board_info eb_spi_devices[] = {
+        {       /* RTC Dallas DS1306 */
+                .modalias       = "rtc-ds1305",
+                .chip_select    = 3,
+                .mode           = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA,
+                .max_speed_hz   = 500000,
+                .bus_num        = 0,
+                .irq            = AT572D940HF_ID_IRQ1,
+                .platform_data  = (void *) &ds1306_data,
+        },
+#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
+        {       /* Dataflash card */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+#endif
+};
+
+static void __init eb_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&eb_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&eb_udc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* NOR */
+        eb_add_device_nor();
+        /* NAND */
+        eb_add_device_nand();
+        /* SPI */
+        at91_add_device_spi(eb_spi_devices, ARRAY_SIZE(eb_spi_devices));
+        /* MMC */
+        at91_add_device_mmc(0, &eb_mmc_data);
+        /* Ethernet */
+        at91_add_device_eth(&eb_eth_data);
+        /* mAgic */
+        at91_add_device_mAgic();
+}
+
+MACHINE_START(AT572D940HFEB, "Atmel AT91D940HF-EB")
+        /* Maintainer: Atmel <costa.antonior@gmail.com> */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = eb_map_io,
+        .init_irq       = eb_init_irq,
+        .init_machine   = eb_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index c042dcf4725f..7f7da439341f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -29,6 +29,7 @@
 #include <mach/cpu.h>
 
 #include "clock.h"
+#include "generic.h"
 
 
 /*
@@ -628,7 +629,7 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
-                   cpu_is_at91sam9g10()) {
+                   cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
         } else if (cpu_is_at91cap9()) {
@@ -711,12 +712,13 @@ int __init at91_clock_init(unsigned long main_clock)
         /*
          * USB HS clock init
          */
-        if (cpu_has_utmi())
+        if (cpu_has_utmi()) {
                 /*
                  * multiplier is hard-wired to 40
                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
                  */
                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
+        }
 
         /*
          * USB FS clock init
@@ -746,7 +748,7 @@ int __init at91_clock_init(unsigned long main_clock)
                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
         } else {
-                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
         }
 
         /* Register the PMC's standard clocks */
diff --git a/arch/arm/mach-at91/clock.h b/arch/arm/mach-at91/clock.h
index 1ba3b95ff359..6cf4b78e175d 100644
--- a/arch/arm/mach-at91/clock.h
+++ b/arch/arm/mach-at91/clock.h
@@ -22,7 +22,7 @@ struct clk {
         struct clk      *parent;
         u32             pmc_mask;
         void            (*mode)(struct clk *, int);
-        unsigned        id:2;           /* PCK0..3, or 32k/main/a/b */
+        unsigned        id:3;           /* PCK0..4, or 32k/main/a/b */
         unsigned        type;           /* clock type */
         u16             users;
 };
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 88e413b38480..65c3dc5ba0d0 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -17,6 +17,7 @@ extern void __init at91sam9rl_initialize(unsigned long main_clock);
 extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
+extern void __init at572d940hf_initialize(unsigned long main_clock);
 
  /* Interrupts */
 extern void __init at91rm9200_init_interrupts(unsigned int priority[]);
@@ -27,6 +28,7 @@ extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
+extern void __init at572d940hf_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 
  /* Timer */
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
new file mode 100644
index 000000000000..2d9b0af9c4d5
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach/at572d940hf.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef AT572D940HF_H
+#define AT572D940HF_H
+
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Peripherals */
+#define AT572D940HF_ID_PIOA     2       /* Parallel IO Controller A */
+#define AT572D940HF_ID_PIOB     3       /* Parallel IO Controller B */
+#define AT572D940HF_ID_PIOC     4       /* Parallel IO Controller C */
+#define AT572D940HF_ID_EMAC     5       /* MACB ethernet controller */
+#define AT572D940HF_ID_US0      6       /* USART 0 */
+#define AT572D940HF_ID_US1      7       /* USART 1 */
+#define AT572D940HF_ID_US2      8       /* USART 2 */
+#define AT572D940HF_ID_MCI      9       /* Multimedia Card Interface */
+#define AT572D940HF_ID_UDP      10      /* USB Device Port */
+#define AT572D940HF_ID_TWI0     11      /* Two-Wire Interface 0 */
+#define AT572D940HF_ID_SPI0     12      /* Serial Peripheral Interface 0 */
+#define AT572D940HF_ID_SPI1     13      /* Serial Peripheral Interface 1 */
+#define AT572D940HF_ID_SSC0     14      /* Serial Synchronous Controller 0 */
+#define AT572D940HF_ID_SSC1     15      /* Serial Synchronous Controller 1 */
+#define AT572D940HF_ID_SSC2     16      /* Serial Synchronous Controller 2 */
+#define AT572D940HF_ID_TC0      17      /* Timer Counter 0 */
+#define AT572D940HF_ID_TC1      18      /* Timer Counter 1 */
+#define AT572D940HF_ID_TC2      19      /* Timer Counter 2 */
+#define AT572D940HF_ID_UHP      20      /* USB Host port */
+#define AT572D940HF_ID_SSC3     21      /* Serial Synchronous Controller 3 */
+#define AT572D940HF_ID_TWI1     22      /* Two-Wire Interface 1 */
+#define AT572D940HF_ID_CAN0     23      /* CAN Controller 0 */
+#define AT572D940HF_ID_CAN1     24      /* CAN Controller 1 */
+#define AT572D940HF_ID_MHALT    25      /* mAgicV HALT line */
+#define AT572D940HF_ID_MSIRQ0   26      /* mAgicV SIRQ0 line */
+#define AT572D940HF_ID_MEXC     27      /* mAgicV exception line */
+#define AT572D940HF_ID_MEDMA    28      /* mAgicV end of DMA line */
+#define AT572D940HF_ID_IRQ0     29      /* External Interrupt Source (IRQ0) */
+#define AT572D940HF_ID_IRQ1     30      /* External Interrupt Source (IRQ1) */
+#define AT572D940HF_ID_IRQ2     31      /* External Interrupt Source (IRQ2) */
+
+
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT572D940HF_BASE_TCB    0xfffa0000
+#define AT572D940HF_BASE_TC0    0xfffa0000
+#define AT572D940HF_BASE_TC1    0xfffa0040
+#define AT572D940HF_BASE_TC2    0xfffa0080
+#define AT572D940HF_BASE_UDP    0xfffa4000
+#define AT572D940HF_BASE_MCI    0xfffa8000
+#define AT572D940HF_BASE_TWI0   0xfffac000
+#define AT572D940HF_BASE_US0    0xfffb0000
+#define AT572D940HF_BASE_US1    0xfffb4000
+#define AT572D940HF_BASE_US2    0xfffb8000
+#define AT572D940HF_BASE_SSC0   0xfffbc000
+#define AT572D940HF_BASE_SSC1   0xfffc0000
+#define AT572D940HF_BASE_SSC2   0xfffc4000
+#define AT572D940HF_BASE_SPI0   0xfffc8000
+#define AT572D940HF_BASE_SPI1   0xfffcc000
+#define AT572D940HF_BASE_SSC3   0xfffd0000
+#define AT572D940HF_BASE_TWI1   0xfffd4000
+#define AT572D940HF_BASE_EMAC   0xfffd8000
+#define AT572D940HF_BASE_CAN0   0xfffdc000
+#define AT572D940HF_BASE_CAN1   0xfffe0000
+#define AT91_BASE_SYS           0xffffea00
+
+
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+
+#define AT91_USART0     AT572D940HF_ID_US0
+#define AT91_USART1     AT572D940HF_ID_US1
+#define AT91_USART2     AT572D940HF_ID_US2
+
+
+/*
+ * Internal Memory.
+ */
+#define AT572D940HF_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT572D940HF_SRAM_SIZE   (48 * SZ_1K)    /* Internal SRAM size (48Kb) */
+
+#define AT572D940HF_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT572D940HF_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
+
+#define AT572D940HF_UHP_BASE    0x00500000      /* USB Host controller */
+
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
new file mode 100644
index 000000000000..b6751df09488
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at572d940hf_matrix.h
@@ -0,0 +1,123 @@
+/*
+ * include/mach//at572d940hf_matrix.h
+ *
+ * Antonio R. Costa <costa.antonior@gmail.com>
+ * Copyright (C) 2008 Atmel
+ *
+ * Copyright (C) 2005 SAN People
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef AT572D940HF_MATRIX_H
+#define AT572D940HF_MATRIX_H
+
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0xff << 0)     /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0x7  << 18)    /* Fixed Index of Default Master */
+#define         AT91_MATRIX_ARBT                (3    << 24)    /* Arbitration Type */
+#define                 AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define                 AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+
+#define AT91_MATRIX_SFR0        (AT91_MATRIX + 0x110)   /* Special Function Register 0 */
+#define AT91_MATRIX_SFR1        (AT91_MATRIX + 0x114)   /* Special Function Register 1 */
+#define AT91_MATRIX_SFR2        (AT91_MATRIX + 0x118)   /* Special Function Register 2 */
+#define AT91_MATRIX_SFR3        (AT91_MATRIX + 0x11C)   /* Special Function Register 3 */
+#define AT91_MATRIX_SFR4        (AT91_MATRIX + 0x120)   /* Special Function Register 4 */
+#define AT91_MATRIX_SFR5        (AT91_MATRIX + 0x124)   /* Special Function Register 5 */
+#define AT91_MATRIX_SFR6        (AT91_MATRIX + 0x128)   /* Special Function Register 6 */
+#define AT91_MATRIX_SFR7        (AT91_MATRIX + 0x12C)   /* Special Function Register 7 */
+#define AT91_MATRIX_SFR8        (AT91_MATRIX + 0x130)   /* Special Function Register 8 */
+#define AT91_MATRIX_SFR9        (AT91_MATRIX + 0x134)   /* Special Function Register 9 */
+#define AT91_MATRIX_SFR10       (AT91_MATRIX + 0x138)   /* Special Function Register 10 */
+#define AT91_MATRIX_SFR11       (AT91_MATRIX + 0x13C)   /* Special Function Register 11 */
+#define AT91_MATRIX_SFR12       (AT91_MATRIX + 0x140)   /* Special Function Register 12 */
+#define AT91_MATRIX_SFR13       (AT91_MATRIX + 0x144)   /* Special Function Register 13 */
+#define AT91_MATRIX_SFR14       (AT91_MATRIX + 0x148)   /* Special Function Register 14 */
+#define AT91_MATRIX_SFR15       (AT91_MATRIX + 0x14C)   /* Special Function Register 15 */
+
+
+/*
+ * The following registers / bits are not defined in the Datasheet (Revision A)
+ */
+
+#define AT91_MATRIX_TCR         (AT91_MATRIX + 0x100)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_16             (5 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define                 AT91_MATRIX_ITCM_64             (7 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_16             (5 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_CS1A                (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_CS1A_SMC            (0 << 1)
+#define                 AT91_MATRIX_CS1A_SDRAMC         (1 << 1)
+#define         AT91_MATRIX_CS3A                (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_CS3A_SMC            (0 << 3)
+#define                 AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define         AT91_MATRIX_CS4A                (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_CS4A_SMC            (0 << 4)
+#define                 AT91_MATRIX_CS4A_SMC_CF1        (1 << 4)
+#define         AT91_MATRIX_CS5A                (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_CS5A_SMC            (0 << 5)
+#define                 AT91_MATRIX_CS5A_SMC_CF2        (1 << 5)
+#define         AT91_MATRIX_DBPUC               (1 << 8)        /* Data Bus Pull-up Configuration */
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 64589eaaaee8..e46f93e34aab 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -32,6 +32,7 @@
 #define         AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
 #define         AT91_PMC_PCK2           (1 << 10)               /* Programmable Clock 2 */
 #define         AT91_PMC_PCK3           (1 << 11)               /* Programmable Clock 3 */
+#define         AT91_PMC_PCK4           (1 << 12)               /* Programmable Clock 4 [AT572D940HF only] */
 #define         AT91_PMC_HCK0           (1 << 16)               /* AHB Clock (USB host) [AT91SAM9261 only] */
 #define         AT91_PMC_HCK1           (1 << 17)               /* AHB Clock (LCD) [AT91SAM9261 only] */
 
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index bb6f6a7ba5e0..ceaec6c16eb2 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -87,7 +87,7 @@ struct at91_eth_data {
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
 
 #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
-        || defined(CONFIG_ARCH_AT91SAM9G45)
+        || defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT572D940HF)
 #define eth_platform_data       at91_eth_data
 #endif
 
@@ -205,6 +205,9 @@ extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
 extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
 extern void __init at91_pwm_leds(struct gpio_led *leds, int nr);
 
+ /* AT572D940HF DSP */
+extern void __init at91_add_device_mAgic(void);
+
 /* FIXME: this needs a better location, but gets stuff building again */
 extern int at91_suspend_entering_slow_clock(void);
 
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c22df30ed5e5..5a0650101d45 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -33,6 +33,8 @@
 #define ARCH_ID_AT91SAM9XE256   0x329a93a0
 #define ARCH_ID_AT91SAM9XE512   0x329aa3a0
 
+#define ARCH_ID_AT572D940HF     0x0e0303e0
+
 #define ARCH_ID_AT91M40800      0x14080044
 #define ARCH_ID_AT91R40807      0x44080746
 #define ARCH_ID_AT91M40807      0x14080745
@@ -141,6 +143,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91cap9_revC()  (0)
 #endif
 
+#ifdef CONFIG_ARCH_AT572D940HF
+#define cpu_is_at572d940hf() (at91_cpu_identify() == ARCH_ID_AT572D940HF)
+#else
+#define cpu_is_at572d940hf() (0)
+#endif
+
 /*
  * Since this is ARM, we will never run on any AVR32 CPU. But these
  * definitions may reduce clutter in common drivers.
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index 29052ba66ada..9e750a1c1b5a 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
 #include <mach/hardware.h>
 #include <mach/at91_dbgu.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                         @ MMU enabled?
         ldreq   \rx, =(AT91_BASE_SYS + AT91_DBGU)               @ System peripherals (phys address)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a0df8b022df2..3d64a75e3ed5 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -32,6 +32,8 @@
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
 #include <mach/at91x40.h>
+#elif defined(CONFIG_ARCH_AT572D940HF)
+#include <mach/at572d940hf.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index 31ac2d97f14c..05a6e8af80c4 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -82,6 +82,11 @@
 #define AT91X40_MASTER_CLOCK    40000000
 #define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 
+#elif defined(CONFIG_ARCH_AT572D940HF)
+
+#define AT572D940HF_MASTER_CLOCK        80000000
+#define CLOCK_TICK_RATE         (AT572D940HF_MASTER_CLOCK/16)
+
 #endif
 
 #endif
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index e590bbe0a7b4..72e405df0fb0 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -142,8 +142,7 @@ void __init bcmring_amba_init(void)
 
         chipcHw_busInterfaceClockEnable(bus_clock);
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 64baf9f87408..fedd8076a689 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 
 #include <asm/hardware/clps7111.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #CLPS7111_PHYS_BASE
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 033bfede6b67..0ebe185610bf 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -91,10 +91,14 @@ config MACH_DAVINCI_DM6467_EVM
         bool "TI DM6467 EVM"
         default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
+        select MACH_DAVINCI_DM6467TEVM
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
 
+config MACH_DAVINCI_DM6467TEVM
+        bool
+
 config MACH_DAVINCI_DM365_EVM
         bool "TI DM365 EVM"
         default ARCH_DAVINCI_DM365
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index eeb9230d8844..6aac880eb794 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -26,7 +26,7 @@ obj-$(CONFIG_MACH_SFFSDR)		+= board-sffsdr.o
 obj-$(CONFIG_MACH_NEUROS_OSD2)          += board-neuros-osd2.o
 obj-$(CONFIG_MACH_DAVINCI_DM355_EVM)    += board-dm355-evm.o
 obj-$(CONFIG_MACH_DM355_LEOPARD)        += board-dm355-leopard.o
-obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)   += board-dm646x-evm.o
+obj-$(CONFIG_MACH_DAVINCI_DM6467_EVM)   += board-dm646x-evm.o cdce949.o
 obj-$(CONFIG_MACH_DAVINCI_DM365_EVM)    += board-dm365-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA830_EVM)    += board-da830-evm.o
 obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)    += board-da850-evm.o
@@ -34,3 +34,4 @@ obj-$(CONFIG_MACH_DAVINCI_DA850_EVM)	+= board-da850-evm.o
 # Power Management
 obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
+obj-$(CONFIG_SUSPEND)                   += pm.o sleep.o
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 31dc9901e556..dc19870b23cd 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -112,7 +112,7 @@ static __init void da830_evm_usb_init(void)
          * Set up USB clock/mode in the CFGCHIP2 register.
          * FYI:  CFGCHIP2 is 0x0000ef00 initially.
          */
-        cfgchip2 = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
+        cfgchip2 = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
 
         /* USB2.0 PHY reference clock is 24 MHz */
         cfgchip2 &= ~CFGCHIP2_REFFREQ;
@@ -139,7 +139,7 @@ static __init void da830_evm_usb_init(void)
         cfgchip2 |=  CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN;
 #endif
 
-        __raw_writel(cfgchip2, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP2_REG));
+        __raw_writel(cfgchip2, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP2_REG));
 
         /* USB_REFCLKIN is not used. */
         ret = davinci_cfg_reg(DA830_USB0_DRVVBUS);
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 07de8db14581..411284d0b0fa 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -46,8 +46,20 @@
 
 static struct mtd_partition da850_evm_norflash_partition[] = {
         {
-                .name           = "NOR filesystem",
+                .name           = "bootloaders + env",
                 .offset         = 0,
+                .size           = SZ_512K,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "kernel",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = SZ_2M,
+                .mask_flags     = 0,
+        },
+        {
+                .name           = "filesystem",
+                .offset         = MTDPART_OFS_APPEND,
                 .size           = MTDPART_SIZ_FULL,
                 .mask_flags     = 0,
         },
@@ -77,6 +89,18 @@ static struct platform_device da850_evm_norflash_device = {
         .resource       = da850_evm_norflash_resource,
 };
 
+static struct davinci_pm_config da850_pm_pdata = {
+        .sleepcount = 128,
+};
+
+static struct platform_device da850_pm_device = {
+        .name           = "pm-davinci",
+        .dev = {
+                .platform_data  = &da850_pm_pdata,
+        },
+        .id             = -1,
+};
+
 /* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash
  * (128K blocks). It may be used instead of the (default) SPI flash
  * to boot, using TI's tools to install the secondary boot loader
@@ -119,6 +143,7 @@ static struct davinci_nand_pdata da850_evm_nandflash_data = {
         .parts          = da850_evm_nandflash_partition,
         .nr_parts       = ARRAY_SIZE(da850_evm_nandflash_partition),
         .ecc_mode       = NAND_ECC_HW,
+        .ecc_bits       = 4,
         .options        = NAND_USE_FLASH_BBT,
 };
 
@@ -537,7 +562,7 @@ static int __init da850_evm_config_emac(void)
         if (!machine_is_davinci_da850_evm())
                 return 0;
 
-        cfg_chip3_base = DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG);
+        cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 
         val = __raw_readl(cfg_chip3_base);
 
@@ -696,6 +721,11 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: cpuidle registration failed: %d\n",
                                 ret);
+
+        ret = da850_register_pm(&da850_pm_device);
+        if (ret)
+                pr_warning("da850_evm_init: suspend registration failed: %d\n",
+                                ret);
 }
 
 #ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 077ecf4fecda..aa48e3f69715 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -111,6 +111,8 @@ static struct platform_device davinci_nand_device = {
 static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_freq       = 400   /* kHz */,
         .bus_delay      = 0     /* usec */,
+        .sda_pin        = 15,
+        .scl_pin        = 14,
 };
 
 static struct snd_platform_data dm355_evm_snd_data;
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 38e9033d2e86..d15beceb632e 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -24,6 +24,8 @@
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/nand.h>
 #include <linux/input.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -571,6 +573,24 @@ static void __init dm365_evm_map_io(void)
         dm365_init();
 }
 
+static struct spi_eeprom at25640 = {
+        .byte_len       = SZ_64K / 8,
+        .name           = "at25640",
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+
+static struct spi_board_info dm365_evm_spi_info[] __initconst = {
+        {
+                .modalias       = "at25",
+                .platform_data  = &at25640,
+                .max_speed_hz   = 10 * 1000 * 1000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = SPI_MODE_0,
+        },
+};
+
 static __init void dm365_evm_init(void)
 {
         evm_init_i2c();
@@ -587,6 +607,9 @@ static __init void dm365_evm_init(void)
         dm365_init_asp(&dm365_evm_snd_data);
         dm365_init_rtc();
         dm365_init_ks(&dm365evm_ks_data);
+
+        dm365_init_spi0(BIT(0), dm365_evm_spi_info,
+                        ARRAY_SIZE(dm365_evm_spi_info));
 }
 
 static __init void dm365_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index e9612cf727b7..976e11b7fa4a 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -629,6 +629,8 @@ static struct i2c_board_info __initdata i2c_info[] =  {
 static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_freq       = 20 /* kHz */,
         .bus_delay      = 100 /* usec */,
+        .sda_pin        = 44,
+        .scl_pin        = 43,
 };
 
 static void __init evm_init_i2c(void)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 8d0b0e01c59b..5ba3cb2daaa0 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -30,6 +30,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/clk.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -39,54 +40,13 @@
 #include <mach/serial.h>
 #include <mach/i2c.h>
 #include <mach/nand.h>
+#include <mach/clock.h>
+#include <mach/cdce949.h>
 
-#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
-    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
-#define HAS_ATA 1
-#else
-#define HAS_ATA 0
-#endif
-
-#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x20008000
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x42000000
+#include "clock.h"
 
 #define NAND_BLOCK_SIZE         SZ_128K
 
-/* CPLD Register 0 bits to control ATA */
-#define DM646X_EVM_ATA_RST              BIT(0)
-#define DM646X_EVM_ATA_PWD              BIT(1)
-
-#define DM646X_EVM_PHY_MASK             (0x2)
-#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
-
-#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
-#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
-#define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
-#define VCH2CLK_SYSCLK8         (BIT(9))
-#define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
-#define VCH3CLK_MASK            (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
-#define VCH3CLK_SYSCLK8         (BIT(13))
-#define VCH3CLK_AUXCLK          (BIT(14) | BIT(13))
-
-#define VIDCH2CLK               (BIT(10))
-#define VIDCH3CLK               (BIT(11))
-#define VIDCH1CLK               (BIT(4))
-#define TVP7002_INPUT           (BIT(4))
-#define TVP5147_INPUT           (~BIT(4))
-#define VPIF_INPUT_ONE_CHANNEL  (BIT(5))
-#define VPIF_INPUT_TWO_CHANNEL  (~BIT(5))
-#define TVP5147_CH0             "tvp514x-0"
-#define TVP5147_CH1             "tvp514x-1"
-
-static void __iomem *vpif_vidclkctl_reg;
-static void __iomem *vpif_vsclkdis_reg;
-/* spin lock for updating above registers */
-static spinlock_t vpif_reg_lock;
-
-static struct davinci_uart_config uart_config __initdata = {
-        .enabled_uarts = (1 << 0),
-};
-
 /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
  * and U-Boot environment this avoids dependency on any particular combination
  * of UBL, U-Boot or flashing tools etc.
@@ -120,6 +80,9 @@ static struct davinci_nand_pdata davinci_nand_data = {
         .options                = 0,
 };
 
+#define DAVINCI_ASYNC_EMIF_CONTROL_BASE         0x20008000
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        0x42000000
+
 static struct resource davinci_nand_resources[] = {
         {
                 .start          = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
@@ -144,6 +107,17 @@ static struct platform_device davinci_nand_device = {
         },
 };
 
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+    defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+/* CPLD Register 0 bits to control ATA */
+#define DM646X_EVM_ATA_RST              BIT(0)
+#define DM646X_EVM_ATA_PWD              BIT(1)
+
 /* CPLD Register 0 Client: used for I/O Control */
 static int cpld_reg0_probe(struct i2c_client *client,
                            const struct i2c_device_id *id)
@@ -417,6 +391,9 @@ static struct i2c_board_info __initdata i2c_info[] =  {
         {
                 I2C_BOARD_INFO("cpld_video", 0x3b),
         },
+        {
+                I2C_BOARD_INFO("cdce949", 0x6c),
+        },
 };
 
 static struct davinci_i2c_platform_data i2c_pdata = {
@@ -424,6 +401,30 @@ static struct davinci_i2c_platform_data i2c_pdata = {
         .bus_delay      = 0 /* usec */,
 };
 
+#define VIDCLKCTL_OFFSET        (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
+#define VSCLKDIS_OFFSET         (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
+#define VCH2CLK_MASK            (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
+#define VCH2CLK_SYSCLK8         (BIT(9))
+#define VCH2CLK_AUXCLK          (BIT(9) | BIT(8))
+#define VCH3CLK_MASK            (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
+#define VCH3CLK_SYSCLK8         (BIT(13))
+#define VCH3CLK_AUXCLK          (BIT(14) | BIT(13))
+
+#define VIDCH2CLK               (BIT(10))
+#define VIDCH3CLK               (BIT(11))
+#define VIDCH1CLK               (BIT(4))
+#define TVP7002_INPUT           (BIT(4))
+#define TVP5147_INPUT           (~BIT(4))
+#define VPIF_INPUT_ONE_CHANNEL  (BIT(5))
+#define VPIF_INPUT_TWO_CHANNEL  (~BIT(5))
+#define TVP5147_CH0             "tvp514x-0"
+#define TVP5147_CH1             "tvp514x-1"
+
+static void __iomem *vpif_vidclkctl_reg;
+static void __iomem *vpif_vsclkdis_reg;
+/* spin lock for updating above registers */
+static spinlock_t vpif_reg_lock;
+
 static int set_vpif_clock(int mux_mode, int hd)
 {
         unsigned long flags;
@@ -685,11 +686,44 @@ static void __init evm_init_i2c(void)
         evm_init_video();
 }
 
+#define CDCE949_XIN_RATE        27000000
+
+/* CDCE949 support - "lpsc" field is overridden to work as clock number */
+static struct clk cdce_clk_in = {
+        .name   = "cdce_xin",
+        .rate   = CDCE949_XIN_RATE,
+};
+
+static struct clk_lookup cdce_clks[] = {
+        CLK(NULL, "xin", &cdce_clk_in),
+        CLK(NULL, NULL, NULL),
+};
+
+static void __init cdce_clk_init(void)
+{
+        struct clk_lookup *c;
+        struct clk *clk;
+
+        for (c = cdce_clks; c->clk; c++) {
+                clk = c->clk;
+                clkdev_add(c);
+                clk_register(clk);
+        }
+}
+
 static void __init davinci_map_io(void)
 {
         dm646x_init();
+        cdce_clk_init();
 }
 
+static struct davinci_uart_config uart_config __initdata = {
+        .enabled_uarts = (1 << 0),
+};
+
+#define DM646X_EVM_PHY_MASK             (0x2)
+#define DM646X_EVM_MDIO_FREQUENCY       (2200000) /* PHY bus frequency */
+
 static __init void evm_init(void)
 {
         struct davinci_soc_info *soc_info = &davinci_soc_info;
@@ -713,6 +747,17 @@ static __init void davinci_dm646x_evm_irq_init(void)
         davinci_irq_init();
 }
 
+#define DM646X_EVM_REF_FREQ             27000000
+#define DM6467T_EVM_REF_FREQ            33000000
+
+void __init dm646x_board_setup_refclk(struct clk *clk)
+{
+        if (machine_is_davinci_dm6467tevm())
+                clk->rate = DM6467T_EVM_REF_FREQ;
+        else
+                clk->rate = DM646X_EVM_REF_FREQ;
+}
+
 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .phys_io      = IO_PHYS,
         .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
@@ -723,3 +768,13 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
         .init_machine = evm_init,
 MACHINE_END
 
+MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
+        .phys_io      = IO_PHYS,
+        .io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
+        .boot_params  = (0x80000100),
+        .map_io       = davinci_map_io,
+        .init_irq     = davinci_dm646x_evm_irq_init,
+        .timer        = &davinci_timer,
+        .init_machine = evm_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-davinci/cdce949.c b/arch/arm/mach-davinci/cdce949.c
new file mode 100644
index 000000000000..aec375690543
--- /dev/null
+++ b/arch/arm/mach-davinci/cdce949.c
@@ -0,0 +1,293 @@
+/*
+ * TI CDCE949 clock synthesizer driver
+ *
+ * Note: This implementation assumes an input of 27MHz to the CDCE.
+ * This is by no means constrained by CDCE hardware although the datasheet
+ * does use this as an example for all illustrations and more importantly:
+ * that is the crystal input on boards it is currently used on.
+ *
+ * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+
+#include <mach/clock.h>
+
+#include "clock.h"
+
+static struct i2c_client *cdce_i2c_client;
+static DEFINE_MUTEX(cdce_mutex);
+
+/* CDCE register descriptor */
+struct cdce_reg {
+        u8      addr;
+        u8      val;
+};
+
+/* Per-Output (Y1, Y2 etc.) frequency descriptor */
+struct cdce_freq {
+        /* Frequency in KHz */
+        unsigned long frequency;
+        /*
+         * List of registers to program to obtain a particular frequency.
+         * 0x0 in register address and value is the end of list marker.
+         */
+        struct cdce_reg *reglist;
+};
+
+#define CDCE_FREQ_TABLE_ENTRY(line, out)                \
+{                                                       \
+        .reglist        = cdce_y ##line## _ ##out,              \
+        .frequency      = out,                          \
+}
+
+/* List of CDCE outputs  */
+struct cdce_output {
+        /* List of frequencies on this output */
+        struct cdce_freq *freq_table;
+        /* Number of possible frequencies */
+        int size;
+};
+
+/*
+ * Finding out the values to program into CDCE949 registers for a particular
+ * frequency output is not a simple calculation. Have a look at the datasheet
+ * for the details. There is desktop software available to help users with
+ * the calculations. Here, we just depend on the output of that software
+ * (or hand calculations) instead trying to runtime calculate the register
+ * values and inflicting misery on ourselves.
+ */
+static struct cdce_reg cdce_y1_148500[] = {
+        { 0x13, 0x00 },
+        /* program PLL1_0 multiplier */
+        { 0x18, 0xaf },
+        { 0x19, 0x50 },
+        { 0x1a, 0x02 },
+        { 0x1b, 0xc9 },
+        /* program PLL1_11 multiplier */
+        { 0x1c, 0x00 },
+        { 0x1d, 0x40 },
+        { 0x1e, 0x02 },
+        { 0x1f, 0xc9 },
+        /* output state selection */
+        { 0x15, 0x00 },
+        { 0x14, 0xef },
+        /* switch MUX to PLL1 output */
+        { 0x14, 0x6f },
+        { 0x16, 0x06 },
+        /* set P2DIV divider, P3DIV and input crystal */
+        { 0x17, 0x06 },
+        { 0x01, 0x00 },
+        { 0x05, 0x48 },
+        { 0x02, 0x80 },
+        /* enable and disable PLL */
+        { 0x02, 0xbc },
+        { 0x03, 0x01 },
+        { },
+};
+
+static struct cdce_reg cdce_y1_74250[] = {
+        { 0x13, 0x00 },
+        { 0x18, 0xaf },
+        { 0x19, 0x50 },
+        { 0x1a, 0x02 },
+        { 0x1b, 0xc9 },
+        { 0x1c, 0x00 },
+        { 0x1d, 0x40 },
+        { 0x1e, 0x02 },
+        { 0x1f, 0xc9 },
+        /* output state selection */
+        { 0x15, 0x00 },
+        { 0x14, 0xef },
+        /* switch MUX to PLL1 output */
+        { 0x14, 0x6f },
+        { 0x16, 0x06 },
+        /* set P2DIV divider, P3DIV and input crystal */
+        { 0x17, 0x06 },
+        { 0x01, 0x00 },
+        { 0x05, 0x48 },
+        { 0x02, 0x80 },
+        /* enable and disable PLL */
+        { 0x02, 0xbc },
+        { 0x03, 0x02 },
+        { },
+};
+
+static struct cdce_reg cdce_y1_27000[] = {
+        { 0x13, 0x00 },
+        { 0x18, 0x00 },
+        { 0x19, 0x40 },
+        { 0x1a, 0x02 },
+        { 0x1b, 0x08 },
+        { 0x1c, 0x00 },
+        { 0x1d, 0x40 },
+        { 0x1e, 0x02 },
+        { 0x1f, 0x08 },
+        { 0x15, 0x02 },
+        { 0x14, 0xed },
+        { 0x16, 0x01 },
+        { 0x17, 0x01 },
+        { 0x01, 0x00 },
+        { 0x05, 0x50 },
+        { 0x02, 0xb4 },
+        { 0x03, 0x01 },
+        { },
+};
+
+static struct cdce_freq cdce_y1_freqs[] = {
+        CDCE_FREQ_TABLE_ENTRY(1, 148500),
+        CDCE_FREQ_TABLE_ENTRY(1, 74250),
+        CDCE_FREQ_TABLE_ENTRY(1, 27000),
+};
+
+static struct cdce_reg cdce_y5_13500[] = {
+        { 0x27, 0x08 },
+        { 0x28, 0x00 },
+        { 0x29, 0x40 },
+        { 0x2a, 0x02 },
+        { 0x2b, 0x08 },
+        { 0x24, 0x6f },
+        { },
+};
+
+static struct cdce_reg cdce_y5_16875[] = {
+        { 0x27, 0x08 },
+        { 0x28, 0x9f },
+        { 0x29, 0xb0 },
+        { 0x2a, 0x02 },
+        { 0x2b, 0x89 },
+        { 0x24, 0x6f },
+        { },
+};
+
+static struct cdce_reg cdce_y5_27000[] = {
+        { 0x27, 0x04 },
+        { 0x28, 0x00 },
+        { 0x29, 0x40 },
+        { 0x2a, 0x02 },
+        { 0x2b, 0x08 },
+        { 0x24, 0x6f },
+        { },
+};
+static struct cdce_reg cdce_y5_54000[] = {
+        { 0x27, 0x04 },
+        { 0x28, 0xff },
+        { 0x29, 0x80 },
+        { 0x2a, 0x02 },
+        { 0x2b, 0x07 },
+        { 0x24, 0x6f },
+        { },
+};
+
+static struct cdce_reg cdce_y5_81000[] = {
+        { 0x27, 0x02 },
+        { 0x28, 0xbf },
+        { 0x29, 0xa0 },
+        { 0x2a, 0x03 },
+        { 0x2b, 0x0a },
+        { 0x24, 0x6f },
+        { },
+};
+
+static struct cdce_freq cdce_y5_freqs[] = {
+        CDCE_FREQ_TABLE_ENTRY(5, 13500),
+        CDCE_FREQ_TABLE_ENTRY(5, 16875),
+        CDCE_FREQ_TABLE_ENTRY(5, 27000),
+        CDCE_FREQ_TABLE_ENTRY(5, 54000),
+        CDCE_FREQ_TABLE_ENTRY(5, 81000),
+};
+
+
+static struct cdce_output output_list[] = {
+        [1]     = { cdce_y1_freqs, ARRAY_SIZE(cdce_y1_freqs) },
+        [5]     = { cdce_y5_freqs, ARRAY_SIZE(cdce_y5_freqs) },
+};
+
+int cdce_set_rate(struct clk *clk, unsigned long rate)
+{
+        int i, ret = 0;
+        struct cdce_freq *freq_table = output_list[clk->lpsc].freq_table;
+        struct cdce_reg  *regs = NULL;
+
+        if (!cdce_i2c_client)
+                return -ENODEV;
+
+        if (!freq_table)
+                return -EINVAL;
+
+        for (i = 0; i < output_list[clk->lpsc].size; i++) {
+                if (freq_table[i].frequency == rate / 1000) {
+                        regs = freq_table[i].reglist;
+                        break;
+                }
+        }
+
+        if (!regs)
+                return -EINVAL;
+
+        mutex_lock(&cdce_mutex);
+        for (i = 0; regs[i].addr; i++) {
+                ret = i2c_smbus_write_byte_data(cdce_i2c_client,
+                                        regs[i].addr | 0x80, regs[i].val);
+                if (ret)
+                        break;
+        }
+        mutex_unlock(&cdce_mutex);
+
+        if (!ret)
+                clk->rate = rate;
+
+        return ret;
+}
+
+static int cdce_probe(struct i2c_client *client,
+                                        const struct i2c_device_id *id)
+{
+        cdce_i2c_client = client;
+        return 0;
+}
+
+static int __devexit cdce_remove(struct i2c_client *client)
+{
+        cdce_i2c_client = NULL;
+        return 0;
+}
+
+static const struct i2c_device_id cdce_id[] = {
+        {"cdce949", 0},
+        {},
+};
+MODULE_DEVICE_TABLE(i2c, cdce_id);
+
+static struct i2c_driver cdce_driver = {
+        .driver = {
+                .owner  = THIS_MODULE,
+                .name   = "cdce949",
+        },
+        .probe          = cdce_probe,
+        .remove         = __devexit_p(cdce_remove),
+        .id_table       = cdce_id,
+};
+
+static int __init cdce_init(void)
+{
+        return i2c_add_driver(&cdce_driver);
+}
+subsys_initcall(cdce_init);
+
+static void __exit cdce_exit(void)
+{
+        i2c_del_driver(&cdce_driver);
+}
+module_exit(cdce_exit);
+
+MODULE_AUTHOR("Texas Instruments");
+MODULE_DESCRIPTION("CDCE949 clock synthesizer driver");
+MODULE_LICENSE("GPL v2");
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index baece65cb9c0..bf6218ee94e1 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -49,7 +49,8 @@ static void __clk_disable(struct clk *clk)
 {
         if (WARN_ON(clk->usecount == 0))
                 return;
-        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
+        if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
+            (clk->flags & CLK_PSC))
                 davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc, 0);
         if (clk->parent)
                 __clk_disable(clk->parent);
@@ -124,9 +125,10 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         if (clk == NULL || IS_ERR(clk))
                 return ret;
 
-        spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->set_rate)
                 ret = clk->set_rate(clk, rate);
+
+        spin_lock_irqsave(&clockfw_lock, flags);
         if (ret == 0) {
                 if (clk->recalc)
                         clk->rate = clk->recalc(clk);
@@ -363,6 +365,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 {
         u32 ctrl;
         unsigned int locktime;
+        unsigned long flags;
 
         if (pll->base == NULL)
                 return -EINVAL;
@@ -376,25 +379,23 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
                 locktime = ((2000 * prediv) / 100);
                 prediv = (prediv - 1) | PLLDIV_EN;
         } else {
-                locktime = 20;
+                locktime = PLL_LOCK_TIME;
         }
         if (postdiv)
                 postdiv = (postdiv - 1) | PLLDIV_EN;
         if (mult)
                 mult = mult - 1;
 
+        /* Protect against simultaneous calls to PLL setting seqeunce */
+        spin_lock_irqsave(&clockfw_lock, flags);
+
         ctrl = __raw_readl(pll->base + PLLCTL);
 
         /* Switch the PLL to bypass mode */
         ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
         __raw_writel(ctrl, pll->base + PLLCTL);
 
-        /*
-         * Wait for 4 OSCIN/CLKIN cycles to ensure that the PLLC has switched
-         * to bypass mode. Delay of 1us ensures we are good for all > 4MHz
-         * OSCIN/CLKIN inputs. Typically the input is ~25MHz.
-         */
-        udelay(1);
+        udelay(PLL_BYPASS_TIME);
 
         /* Reset and enable PLL */
         ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
@@ -408,11 +409,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
         if (pll->flags & PLL_HAS_POSTDIV)
                 __raw_writel(postdiv, pll->base + POSTDIV);
 
-        /*
-         * Wait for PLL to reset properly, OMAP-L138 datasheet says
-         * 'min' time = 125ns
-         */
-        udelay(1);
+        udelay(PLL_RESET_TIME);
 
         /* Bring PLL out of reset */
         ctrl |= PLLCTL_PLLRST;
@@ -424,17 +421,20 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
         ctrl |= PLLCTL_PLLEN;
         __raw_writel(ctrl, pll->base + PLLCTL);
 
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
         return 0;
 }
 EXPORT_SYMBOL(davinci_set_pllrate);
 
-int __init davinci_clk_init(struct davinci_clk *clocks)
+int __init davinci_clk_init(struct clk_lookup *clocks)
   {
-        struct davinci_clk *c;
+        struct clk_lookup *c;
         struct clk *clk;
+        size_t num_clocks = 0;
 
-        for (c = clocks; c->lk.clk; c++) {
-                clk = c->lk.clk;
+        for (c = clocks; c->clk; c++) {
+                clk = c->clk;
 
                 if (!clk->recalc) {
 
@@ -457,35 +457,23 @@ int __init davinci_clk_init(struct davinci_clk *clocks)
                 if (clk->lpsc)
                         clk->flags |= CLK_PSC;
 
-                clkdev_add(&c->lk);
                 clk_register(clk);
+                num_clocks++;
 
                 /* Turn on clocks that Linux doesn't otherwise manage */
                 if (clk->flags & ALWAYS_ENABLED)
                         clk_enable(clk);
         }
 
-        return 0;
-}
-
-#ifdef CONFIG_PROC_FS
-#include <linux/proc_fs.h>
-#include <linux/seq_file.h>
+        clkdev_add_table(clocks, num_clocks);
 
-static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
-{
-        return *pos < 1 ? (void *)1 : NULL;
+        return 0;
 }
 
-static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
-{
-        ++*pos;
-        return NULL;
-}
+#ifdef CONFIG_DEBUG_FS
 
-static void davinci_ck_stop(struct seq_file *m, void *v)
-{
-}
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
 
 #define CLKNAME_MAX     10              /* longest clock name */
 #define NEST_DELTA      2
@@ -525,41 +513,38 @@ dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
 
 static int davinci_ck_show(struct seq_file *m, void *v)
 {
-        /* Show clock tree; we know the main oscillator is first.
-         * We trust nonzero usecounts equate to PSC enables...
+        struct clk *clk;
+
+        /*
+         * Show clock tree; We trust nonzero usecounts equate to PSC enables...
          */
         mutex_lock(&clocks_mutex);
-        if (!list_empty(&clocks))
-                dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
+        list_for_each_entry(clk, &clocks, node)
+                if (!clk->parent)
+                        dump_clock(m, 0, clk);
         mutex_unlock(&clocks_mutex);
 
         return 0;
 }
 
-static const struct seq_operations davinci_ck_op = {
-        .start  = davinci_ck_start,
-        .next   = davinci_ck_next,
-        .stop   = davinci_ck_stop,
-        .show   = davinci_ck_show
-};
-
 static int davinci_ck_open(struct inode *inode, struct file *file)
 {
-        return seq_open(file, &davinci_ck_op);
+        return single_open(file, davinci_ck_show, NULL);
 }
 
-static const struct file_operations proc_davinci_ck_operations = {
+static const struct file_operations davinci_ck_operations = {
         .open           = davinci_ck_open,
         .read           = seq_read,
         .llseek         = seq_lseek,
-        .release        = seq_release,
+        .release        = single_release,
 };
 
-static int __init davinci_ck_proc_init(void)
+static int __init davinci_clk_debugfs_init(void)
 {
-        proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
+        debugfs_create_file("davinci_clocks", S_IFREG | S_IRUGO, NULL, NULL,
+                                                &davinci_ck_operations);
         return 0;
 
 }
-__initcall(davinci_ck_proc_init);
-#endif /* CONFIG_DEBUG_PROC_FS */
+device_initcall(davinci_clk_debugfs_init);
+#endif /* CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index c92d77a3008d..aa0a61150325 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -12,9 +12,6 @@
 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
 #define __ARCH_ARM_DAVINCI_CLOCK_H
 
-#include <linux/list.h>
-#include <asm/clkdev.h>
-
 #define DAVINCI_PLL1_BASE 0x01c40800
 #define DAVINCI_PLL2_BASE 0x01c40c00
 #define MAX_PLL 2
@@ -53,6 +50,26 @@
 #define PLLDIV_EN       BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+/*
+ * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
+ * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
+ * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
+ * is ~25MHz. Units are micro seconds.
+ */
+#define PLL_BYPASS_TIME         1
+/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
+#define PLL_RESET_TIME          1
+/*
+ * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
+ * Units are micro seconds.
+ */
+#define PLL_LOCK_TIME           20
+
+#ifndef __ASSEMBLER__
+
+#include <linux/list.h>
+#include <asm/clkdev.h>
+
 struct pll_data {
         u32 phys_base;
         void __iomem *base;
@@ -89,23 +106,19 @@ struct clk {
 #define CLK_PLL                 BIT(4) /* PLL-derived clock */
 #define PRE_PLL                 BIT(5) /* source is before PLL mult/div */
 
-struct davinci_clk {
-        struct clk_lookup lk;
-};
-
-#define CLK(dev, con, ck)               \
-        {                               \
-                .lk = {                 \
-                        .dev_id = dev,  \
-                        .con_id = con,  \
-                        .clk = ck,      \
-                },                      \
-        }
+#define CLK(dev, con, ck)       \
+        {                       \
+                .dev_id = dev,  \
+                .con_id = con,  \
+                .clk = ck,      \
+        }                       \
 
-int davinci_clk_init(struct davinci_clk *clocks);
+int davinci_clk_init(struct clk_lookup *clocks);
 int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
                                 unsigned int mult, unsigned int postdiv);
 
 extern struct platform_device davinci_wdt_device;
 
 #endif
+
+#endif
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index c2de94cde56a..94f27cbcd55a 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -11,13 +11,13 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/etherdevice.h>
+#include <linux/davinci_emac.h>
 
 #include <asm/tlb.h>
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
 #include <mach/cputype.h>
-#include <mach/emac.h>
 
 #include "clock.h"
 
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index 97a90f36fc92..bd59f31b8a95 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -19,6 +19,7 @@
 #include <asm/proc-fns.h>
 
 #include <mach/cpuidle.h>
+#include <mach/memory.h>
 
 #define DAVINCI_CPUIDLE_MAX_STATES      2
 
@@ -39,10 +40,6 @@ static struct cpuidle_driver davinci_idle_driver = {
 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
 static void __iomem *ddr2_reg_base;
 
-#define DDR2_SDRCR_OFFSET       0xc
-#define DDR2_SRPD_BIT           BIT(23)
-#define DDR2_LPMODEN_BIT        BIT(31)
-
 static void davinci_save_ddr_power(int enter, bool pdown)
 {
         u32 val;
@@ -109,8 +106,6 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
         int ret;
         struct cpuidle_device *device;
         struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
-        struct resource *ddr2_regs;
-        resource_size_t len;
 
         device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
 
@@ -119,28 +114,12 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
                 return -ENOENT;
         }
 
-        ddr2_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!ddr2_regs) {
-                dev_err(&pdev->dev, "cannot get DDR2 controller register base");
-                return -ENODEV;
-        }
-
-        len = resource_size(ddr2_regs);
-
-        ddr2_regs = request_mem_region(ddr2_regs->start, len, ddr2_regs->name);
-        if (!ddr2_regs)
-                return -EBUSY;
-
-        ddr2_reg_base = ioremap(ddr2_regs->start, len);
-        if (!ddr2_reg_base) {
-                ret = -ENOMEM;
-                goto ioremap_fail;
-        }
+        ddr2_reg_base = pdata->ddr2_ctlr_base;
 
         ret = cpuidle_register_driver(&davinci_idle_driver);
         if (ret) {
                 dev_err(&pdev->dev, "failed to register driver\n");
-                goto driver_register_fail;
+                return ret;
         }
 
         /* Wait for interrupt state */
@@ -167,18 +146,11 @@ static int __init davinci_cpuidle_probe(struct platform_device *pdev)
         ret = cpuidle_register_device(device);
         if (ret) {
                 dev_err(&pdev->dev, "failed to register device\n");
-                goto device_register_fail;
+                cpuidle_unregister_driver(&davinci_idle_driver);
+                return ret;
         }
 
         return 0;
-
-device_register_fail:
-        cpuidle_unregister_driver(&davinci_idle_driver);
-driver_register_fail:
-        iounmap(ddr2_reg_base);
-ioremap_fail:
-        release_mem_region(ddr2_regs->start, len);
-        return ret;
 }
 
 static struct platform_driver davinci_cpuidle_driver = {
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index b22b5cf04250..122e61a9f505 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -371,7 +371,7 @@ static struct clk rmii_clk = {
         .parent         = &pll0_sysclk7,
 };
 
-static struct davinci_clk da830_clks[] = {
+static struct clk_lookup da830_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
         CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
@@ -1208,13 +1208,13 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
 
 void __init da830_init(void)
 {
-        da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
-        if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
+        da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+        if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
                 return;
 
         davinci_soc_info_da830.jtag_id_base =
-                                        DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
-        davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
+                                        DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
+        davinci_soc_info_da830.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
         davinci_common_init(&davinci_soc_info_da830);
 }
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 717806c6cef9..d0fd7566712a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -26,6 +26,7 @@
 #include <mach/time.h>
 #include <mach/da8xx.h>
 #include <mach/cpufreq.h>
+#include <mach/pm.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -40,6 +41,7 @@
 #define DA850_REF_FREQ          24000000
 
 #define CFGCHIP3_ASYNC3_CLKSRC  BIT(4)
+#define CFGCHIP3_PLL1_MASTER_LOCK       BIT(5)
 #define CFGCHIP0_PLL_MASTER_LOCK        BIT(4)
 
 static int da850_set_armrate(struct clk *clk, unsigned long rate);
@@ -333,7 +335,7 @@ static struct clk aemif_clk = {
         .flags          = ALWAYS_ENABLED,
 };
 
-static struct davinci_clk da850_clks[] = {
+static struct clk_lookup da850_clks[] = {
         CLK(NULL,               "ref",          &ref_clk),
         CLK(NULL,               "pll0",         &pll0_clk),
         CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
@@ -535,6 +537,7 @@ static const struct mux_config da850_pins[] = {
         MUX_CFG(DA850, GPIO2_15,        5,      0,      15,     8,      false)
         MUX_CFG(DA850, GPIO4_0,         10,     28,     15,     8,      false)
         MUX_CFG(DA850, GPIO4_1,         10,     24,     15,     8,      false)
+        MUX_CFG(DA850, RTC_ALARM,       0,      28,     15,     2,      false)
 #endif
 };
 
@@ -770,6 +773,12 @@ static struct map_desc da850_io_desc[] = {
                 .length         = DA8XX_CP_INTC_SIZE,
                 .type           = MT_DEVICE
         },
+        {
+                .virtual        = SRAM_VIRT,
+                .pfn            = __phys_to_pfn(DA8XX_ARM_RAM_BASE),
+                .length         = SZ_8K,
+                .type           = MT_DEVICE
+        },
 };
 
 static void __iomem *da850_psc_bases[] = {
@@ -825,12 +834,12 @@ static struct davinci_timer_info da850_timer_info = {
 static void da850_set_async3_src(int pllnum)
 {
         struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
-        struct davinci_clk *c;
+        struct clk_lookup *c;
         unsigned int v;
         int ret;
 
-        for (c = da850_clks; c->lk.clk; c++) {
-                clk = c->lk.clk;
+        for (c = da850_clks; c->clk; c++) {
+                clk = c->clk;
                 if (clk->flags & DA850_CLK_ASYNC3) {
                         ret = clk_set_parent(clk, newparent);
                         WARN(ret, "DA850: unable to re-parent clock %s",
@@ -838,12 +847,12 @@ static void da850_set_async3_src(int pllnum)
                 }
        }
 
-        v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
         if (pllnum)
                 v |= CFGCHIP3_ASYNC3_CLKSRC;
         else
                 v &= ~CFGCHIP3_ASYNC3_CLKSRC;
-        __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP3_REG));
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 }
 
 #ifdef CONFIG_CPU_FREQ
@@ -987,7 +996,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         unsigned int prediv, mult, postdiv;
         struct da850_opp *opp;
         struct pll_data *pll = clk->pll_data;
-        unsigned int v;
         int ret;
 
         opp = (struct da850_opp *) da850_freq_table[index].index;
@@ -995,11 +1003,6 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         mult = opp->mult;
         postdiv = opp->postdiv;
 
-        /* Unlock writing to PLL registers */
-        v = __raw_readl(DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
-        v &= ~CFGCHIP0_PLL_MASTER_LOCK;
-        __raw_writel(v, DA8XX_SYSCFG_VIRT(DA8XX_CFGCHIP0_REG));
-
         ret = davinci_set_pllrate(pll, prediv, mult, postdiv);
         if (WARN_ON(ret))
                 return ret;
@@ -1028,6 +1031,43 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 }
 #endif
 
+int da850_register_pm(struct platform_device *pdev)
+{
+        int ret;
+        struct davinci_pm_config *pdata = pdev->dev.platform_data;
+
+        ret = davinci_cfg_reg(DA850_RTC_ALARM);
+        if (ret)
+                return ret;
+
+        pdata->ddr2_ctlr_base = da8xx_get_mem_ctlr();
+        pdata->deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG);
+        pdata->ddrpsc_num = DA8XX_LPSC1_EMIF3C;
+
+        pdata->cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K);
+        if (!pdata->cpupll_reg_base)
+                return -ENOMEM;
+
+        pdata->ddrpll_reg_base = ioremap(DA8XX_PLL1_BASE, SZ_4K);
+        if (!pdata->ddrpll_reg_base) {
+                ret = -ENOMEM;
+                goto no_ddrpll_mem;
+        }
+
+        pdata->ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K);
+        if (!pdata->ddrpsc_reg_base) {
+                ret = -ENOMEM;
+                goto no_ddrpsc_mem;
+        }
+
+        return platform_device_register(pdev);
+
+no_ddrpsc_mem:
+        iounmap(pdata->ddrpll_reg_base);
+no_ddrpll_mem:
+        iounmap(pdata->cpupll_reg_base);
+        return ret;
+}
 
 static struct davinci_soc_info davinci_soc_info_da850 = {
         .io_desc                = da850_io_desc,
@@ -1049,17 +1089,25 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
         .gpio_irq               = IRQ_DA8XX_GPIO0,
         .serial_dev             = &da8xx_serial_device,
         .emac_pdata             = &da8xx_emac_pdata,
+        .sram_dma               = DA8XX_ARM_RAM_BASE,
+        .sram_len               = SZ_8K,
 };
 
 void __init da850_init(void)
 {
-        da8xx_syscfg_base = ioremap(DA8XX_SYSCFG_BASE, SZ_4K);
-        if (WARN(!da8xx_syscfg_base, "Unable to map syscfg module"))
+        unsigned int v;
+
+        da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
+        if (WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"))
+                return;
+
+        da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K);
+        if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
                 return;
 
         davinci_soc_info_da850.jtag_id_base =
-                                        DA8XX_SYSCFG_VIRT(DA8XX_JTAG_ID_REG);
-        davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG_VIRT(0x120);
+                                        DA8XX_SYSCFG0_VIRT(DA8XX_JTAG_ID_REG);
+        davinci_soc_info_da850.pinmux_base = DA8XX_SYSCFG0_VIRT(0x120);
 
         davinci_common_init(&davinci_soc_info_da850);
 
@@ -1071,4 +1119,14 @@ void __init da850_init(void)
          * be any noticible change even in non-DVFS use cases.
          */
         da850_set_async3_src(1);
+
+        /* Unlock writing to PLL0 registers */
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
+        v &= ~CFGCHIP0_PLL_MASTER_LOCK;
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
+
+        /* Unlock writing to PLL1 registers */
+        v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+        v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
+        __raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
 }
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index a5105f03fd86..0a96791d3b0f 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -24,8 +24,10 @@
 #include "clock.h"
 
 #define DA8XX_TPCC_BASE                 0x01c00000
+#define DA850_TPCC1_BASE                0x01e30000
 #define DA8XX_TPTC0_BASE                0x01c08000
 #define DA8XX_TPTC1_BASE                0x01c08400
+#define DA850_TPTC2_BASE                0x01e38000
 #define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
 #define DA8XX_I2C0_BASE                 0x01c22000
 #define DA8XX_RTC_BASE                  0x01C23000
@@ -42,7 +44,8 @@
 #define DA8XX_MDIO_REG_OFFSET           0x4000
 #define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
 
-void __iomem *da8xx_syscfg_base;
+void __iomem *da8xx_syscfg0_base;
+void __iomem *da8xx_syscfg1_base;
 
 static struct plat_serial8250_port da8xx_serial_pdata[] = {
         {
@@ -82,11 +85,6 @@ struct platform_device da8xx_serial_device = {
         },
 };
 
-static const s8 da8xx_dma_chan_no_event[] = {
-        20, 21,
-        -1
-};
-
 static const s8 da8xx_queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
         {0, 0},
@@ -101,20 +99,52 @@ static const s8 da8xx_queue_priority_mapping[][2] = {
         {-1, -1}
 };
 
-static struct edma_soc_info da8xx_edma_info[] = {
+static const s8 da850_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {-1, -1}
+};
+
+static const s8 da850_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {-1, -1}
+};
+
+static struct edma_soc_info da830_edma_info[] = {
         {
                 .n_channel              = 32,
                 .n_region               = 4,
                 .n_slot                 = 128,
                 .n_tc                   = 2,
                 .n_cc                   = 1,
-                .noevent                = da8xx_dma_chan_no_event,
                 .queue_tc_mapping       = da8xx_queue_tc_mapping,
                 .queue_priority_mapping = da8xx_queue_priority_mapping,
         },
 };
 
-static struct resource da8xx_edma_resources[] = {
+static struct edma_soc_info da850_edma_info[] = {
+        {
+                .n_channel              = 32,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 2,
+                .n_cc                   = 1,
+                .queue_tc_mapping       = da8xx_queue_tc_mapping,
+                .queue_priority_mapping = da8xx_queue_priority_mapping,
+        },
+        {
+                .n_channel              = 32,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 1,
+                .n_cc                   = 1,
+                .queue_tc_mapping       = da850_queue_tc_mapping,
+                .queue_priority_mapping = da850_queue_priority_mapping,
+        },
+};
+
+static struct resource da830_edma_resources[] = {
         {
                 .name   = "edma_cc0",
                 .start  = DA8XX_TPCC_BASE,
@@ -145,19 +175,91 @@ static struct resource da8xx_edma_resources[] = {
         },
 };
 
-static struct platform_device da8xx_edma_device = {
+static struct resource da850_edma_resources[] = {
+        {
+                .name   = "edma_cc0",
+                .start  = DA8XX_TPCC_BASE,
+                .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = DA8XX_TPTC0_BASE,
+                .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = DA8XX_TPTC1_BASE,
+                .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_cc1",
+                .start  = DA850_TPCC1_BASE,
+                .end    = DA850_TPCC1_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc2",
+                .start  = DA850_TPTC2_BASE,
+                .end    = DA850_TPTC2_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma0",
+                .start  = IRQ_DA8XX_CCINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma0_err",
+                .start  = IRQ_DA8XX_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma1",
+                .start  = IRQ_DA850_CCINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma1_err",
+                .start  = IRQ_DA850_CCERRINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da830_edma_device = {
         .name           = "edma",
         .id             = -1,
         .dev = {
-                .platform_data  = da8xx_edma_info,
+                .platform_data = da830_edma_info,
         },
-        .num_resources  = ARRAY_SIZE(da8xx_edma_resources),
-        .resource       = da8xx_edma_resources,
+        .num_resources  = ARRAY_SIZE(da830_edma_resources),
+        .resource       = da830_edma_resources,
+};
+
+static struct platform_device da850_edma_device = {
+        .name           = "edma",
+        .id             = -1,
+        .dev = {
+                .platform_data = da850_edma_info,
+        },
+        .num_resources  = ARRAY_SIZE(da850_edma_resources),
+        .resource       = da850_edma_resources,
 };
 
 int __init da8xx_register_edma(void)
 {
-        return platform_device_register(&da8xx_edma_device);
+        struct platform_device *pdev;
+
+        if (cpu_is_davinci_da830())
+                pdev = &da830_edma_device;
+        else if (cpu_is_davinci_da850())
+                pdev = &da850_edma_device;
+        else
+                return -ENODEV;
+
+        return platform_device_register(pdev);
 }
 
 static struct resource da8xx_i2c_resources0[] = {
@@ -495,6 +597,19 @@ int da8xx_register_rtc(void)
         return ret;
 }
 
+static void __iomem *da8xx_ddr2_ctlr_base;
+void __iomem * __init da8xx_get_mem_ctlr(void)
+{
+        if (da8xx_ddr2_ctlr_base)
+                return da8xx_ddr2_ctlr_base;
+
+        da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
+        if (!da8xx_ddr2_ctlr_base)
+                pr_warning("%s: Unable to map DDR2 controller", __func__);
+
+        return da8xx_ddr2_ctlr_base;
+}
+
 static struct resource da8xx_cpuidle_resources[] = {
         {
                 .start          = DA8XX_DDR2_CTL_BASE,
@@ -520,6 +635,7 @@ static struct platform_device da8xx_cpuidle_device = {
 
 int __init da8xx_register_cpuidle(void)
 {
+        da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
+
         return platform_device_register(&da8xx_cpuidle_device);
 }
-
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index d84e85414d20..3dc0a88712eb 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -29,6 +29,7 @@
 #include <mach/serial.h>
 #include <mach/common.h>
 #include <mach/asp.h>
+#include <mach/spi.h>
 
 #include "clock.h"
 #include "mux.h"
@@ -334,7 +335,7 @@ static struct clk usb_clk = {
         .lpsc = DAVINCI_LPSC_USB,
 };
 
-static struct davinci_clk dm355_clks[] = {
+static struct clk_lookup dm355_clks[] = {
         CLK(NULL, "ref", &ref_clk),
         CLK(NULL, "pll1", &pll1_clk),
         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -362,9 +363,9 @@ static struct davinci_clk dm355_clks[] = {
         CLK("davinci-asp.1", NULL, &asp1_clk),
         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
-        CLK(NULL, "spi0", &spi0_clk),
-        CLK(NULL, "spi1", &spi1_clk),
-        CLK(NULL, "spi2", &spi2_clk),
+        CLK("spi_davinci.0", NULL, &spi0_clk),
+        CLK("spi_davinci.1", NULL, &spi1_clk),
+        CLK("spi_davinci.2", NULL, &spi2_clk),
         CLK(NULL, "gpio", &gpio_clk),
         CLK(NULL, "aemif", &aemif_clk),
         CLK(NULL, "pwm0", &pwm0_clk),
@@ -391,24 +392,40 @@ static struct resource dm355_spi0_resources[] = {
                 .flags = IORESOURCE_MEM,
         },
         {
-                .start = IRQ_DM355_SPINT0_1,
+                .start = IRQ_DM355_SPINT0_0,
                 .flags = IORESOURCE_IRQ,
         },
-        /* Not yet used, so not included:
-         * IORESOURCE_IRQ:
-         *  - IRQ_DM355_SPINT0_0
-         * IORESOURCE_DMA:
-         *  - DAVINCI_DMA_SPI_SPIX
-         *  - DAVINCI_DMA_SPI_SPIR
-         */
+        {
+                .start = 17,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = 16,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = EVENTQ_1,
+                .flags = IORESOURCE_DMA,
+        },
 };
 
+static struct davinci_spi_platform_data dm355_spi0_pdata = {
+        .version        = SPI_VERSION_1,
+        .num_chipselect = 2,
+        .clk_internal   = 1,
+        .cs_hold        = 1,
+        .intr_level     = 0,
+        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
+        .c2tdelay       = 0,
+        .t2cdelay       = 0,
+};
 static struct platform_device dm355_spi0_device = {
         .name = "spi_davinci",
         .id = 0,
         .dev = {
                 .dma_mask = &dm355_spi0_dma_mask,
                 .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &dm355_spi0_pdata,
         },
         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
         .resource = dm355_spi0_resources,
@@ -563,13 +580,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static const s8 dma_chan_dm355_no_event[] = {
-        12, 13, 24, 56, 57,
-        58, 59, 60, 61, 62,
-        63,
-        -1
-};
-
 static const s8
 queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
@@ -593,7 +603,6 @@ static struct edma_soc_info dm355_edma_info[] = {
                 .n_slot                 = 128,
                 .n_tc                   = 2,
                 .n_cc                   = 1,
-                .noevent                = dma_chan_dm355_no_event,
                 .queue_tc_mapping       = queue_tc_mapping,
                 .queue_priority_mapping = queue_priority_mapping,
         },
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index ce9da43a628b..27772e18e45b 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach/map.h>
 
@@ -32,6 +33,8 @@
 #include <mach/common.h>
 #include <mach/asp.h>
 #include <mach/keyscan.h>
+#include <mach/spi.h>
+
 
 #include "clock.h"
 #include "mux.h"
@@ -403,7 +406,7 @@ static struct clk mjcp_clk = {
         .lpsc           = DM365_LPSC_MJCP,
 };
 
-static struct davinci_clk dm365_clks[] = {
+static struct clk_lookup dm365_clks[] = {
         CLK(NULL, "ref", &ref_clk),
         CLK(NULL, "pll1", &pll1_clk),
         CLK(NULL, "pll1_aux", &pll1_aux_clk),
@@ -455,7 +458,7 @@ static struct davinci_clk dm365_clks[] = {
         CLK(NULL, "timer3", &timer3_clk),
         CLK(NULL, "usb", &usb_clk),
         CLK("davinci_emac.1", NULL, &emac_clk),
-        CLK("voice_codec", NULL, &voicecodec_clk),
+        CLK("davinci_voicecodec", NULL, &voicecodec_clk),
         CLK("davinci-asp.0", NULL, &asp0_clk),
         CLK(NULL, "rto", &rto_clk),
         CLK(NULL, "mjcp", &mjcp_clk),
@@ -606,9 +609,78 @@ INT_CFG(DM365,  INT_NSF_DISABLE,     25,    1,    0,     false)
 
 EVT_CFG(DM365,  EVT2_ASP_TX,         0,     1,    0,     false)
 EVT_CFG(DM365,  EVT3_ASP_RX,         1,     1,    0,     false)
+EVT_CFG(DM365,  EVT2_VC_TX,          0,     1,    1,     false)
+EVT_CFG(DM365,  EVT3_VC_RX,          1,     1,    1,     false)
 #endif
 };
 
+static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
+
+static struct davinci_spi_platform_data dm365_spi0_pdata = {
+        .version        = SPI_VERSION_1,
+        .num_chipselect = 2,
+        .clk_internal   = 1,
+        .cs_hold        = 1,
+        .intr_level     = 0,
+        .poll_mode      = 1,    /* 0 -> interrupt mode 1-> polling mode */
+        .c2tdelay       = 0,
+        .t2cdelay       = 0,
+};
+
+static struct resource dm365_spi0_resources[] = {
+        {
+                .start = 0x01c66000,
+                .end   = 0x01c667ff,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_DM365_SPIINT0_0,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = 17,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = 16,
+                .flags = IORESOURCE_DMA,
+        },
+        {
+                .start = EVENTQ_3,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm365_spi0_device = {
+        .name = "spi_davinci",
+        .id = 0,
+        .dev = {
+                .dma_mask = &dm365_spi0_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+                .platform_data = &dm365_spi0_pdata,
+        },
+        .num_resources = ARRAY_SIZE(dm365_spi0_resources),
+        .resource = dm365_spi0_resources,
+};
+
+void __init dm365_init_spi0(unsigned chipselect_mask,
+                struct spi_board_info *info, unsigned len)
+{
+        davinci_cfg_reg(DM365_SPI0_SCLK);
+        davinci_cfg_reg(DM365_SPI0_SDI);
+        davinci_cfg_reg(DM365_SPI0_SDO);
+
+        /* not all slaves will be wired up */
+        if (chipselect_mask & BIT(0))
+                davinci_cfg_reg(DM365_SPI0_SDENA0);
+        if (chipselect_mask & BIT(1))
+                davinci_cfg_reg(DM365_SPI0_SDENA1);
+
+        spi_register_board_info(info, len);
+
+        platform_device_register(&dm365_spi0_device);
+}
+
 static struct emac_platform_data dm365_emac_pdata = {
         .ctrl_reg_offset        = DM365_EMAC_CNTRL_OFFSET,
         .ctrl_mod_reg_offset    = DM365_EMAC_CNTRL_MOD_OFFSET,
@@ -754,7 +826,7 @@ static struct edma_soc_info dm365_edma_info[] = {
                 .n_cc                   = 1,
                 .queue_tc_mapping       = dm365_queue_tc_mapping,
                 .queue_priority_mapping = dm365_queue_priority_mapping,
-                .default_queue          = EVENTQ_2,
+                .default_queue          = EVENTQ_3,
         },
 };
 
@@ -835,6 +907,31 @@ static struct platform_device dm365_asp_device = {
         .resource       = dm365_asp_resources,
 };
 
+static struct resource dm365_vc_resources[] = {
+        {
+                .start  = DAVINCI_DM365_VC_BASE,
+                .end    = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = DAVINCI_DMA_VC_TX,
+                .end    = DAVINCI_DMA_VC_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        {
+                .start  = DAVINCI_DMA_VC_RX,
+                .end    = DAVINCI_DMA_VC_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device dm365_vc_device = {
+        .name           = "davinci_voicecodec",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(dm365_vc_resources),
+        .resource       = dm365_vc_resources,
+};
+
 static struct resource dm365_rtc_resources[] = {
         {
                 .start = DM365_RTC_BASE,
@@ -991,6 +1088,14 @@ void __init dm365_init_asp(struct snd_platform_data *pdata)
         platform_device_register(&dm365_asp_device);
 }
 
+void __init dm365_init_vc(struct snd_platform_data *pdata)
+{
+        davinci_cfg_reg(DM365_EVT2_VC_TX);
+        davinci_cfg_reg(DM365_EVT3_VC_RX);
+        dm365_vc_device.dev.platform_data = pdata;
+        platform_device_register(&dm365_vc_device);
+}
+
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
 {
         dm365_ks_device.dev.platform_data = pdata;
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 92aeb5600680..2f2ae8bc77bb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -277,7 +277,7 @@ static struct clk timer2_clk = {
         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 };
 
-struct davinci_clk dm644x_clks[] = {
+struct clk_lookup dm644x_clks[] = {
         CLK(NULL, "ref", &ref_clk),
         CLK(NULL, "pll1", &pll1_clk),
         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
@@ -479,15 +479,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static const s8 dma_chan_dm644x_no_event[] = {
-         0,  1, 12, 13, 14,
-        15, 25, 30, 31, 45,
-        46, 47, 55, 56, 57,
-        58, 59, 60, 61, 62,
-        63,
-        -1
-};
-
 static const s8
 queue_tc_mapping[][2] = {
         /* {event queue no, TC no} */
@@ -511,7 +502,6 @@ static struct edma_soc_info dm644x_edma_info[] = {
                 .n_slot                 = 128,
                 .n_tc                   = 2,
                 .n_cc                   = 1,
-                .noevent                = dma_chan_dm644x_no_event,
                 .queue_tc_mapping       = queue_tc_mapping,
                 .queue_priority_mapping = queue_priority_mapping,
         },
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 829a44bcf799..893baf4ad37d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -42,7 +42,6 @@
 /*
  * Device specific clocks
  */
-#define DM646X_REF_FREQ         27000000
 #define DM646X_AUX_FREQ         24000000
 
 static struct pll_data pll1_data = {
@@ -57,7 +56,6 @@ static struct pll_data pll2_data = {
 
 static struct clk ref_clk = {
         .name = "ref_clk",
-        .rate = DM646X_REF_FREQ,
 };
 
 static struct clk aux_clkin = {
@@ -313,7 +311,7 @@ static struct clk vpif1_clk = {
         .flags = ALWAYS_ENABLED,
 };
 
-struct davinci_clk dm646x_clks[] = {
+struct clk_lookup dm646x_clks[] = {
         CLK(NULL, "ref", &ref_clk),
         CLK(NULL, "aux", &aux_clkin),
         CLK(NULL, "pll1", &pll1_clk),
@@ -513,14 +511,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 
 /*----------------------------------------------------------------------*/
 
-static const s8 dma_chan_dm646x_no_event[] = {
-         0,  1,  2,  3, 13,
-        14, 15, 24, 25, 26,
-        27, 30, 31, 54, 55,
-        56,
-        -1
-};
-
 /* Four Transfer Controllers on DM646x */
 static const s8
 dm646x_queue_tc_mapping[][2] = {
@@ -549,7 +539,6 @@ static struct edma_soc_info dm646x_edma_info[] = {
                 .n_slot                 = 512,
                 .n_tc                   = 4,
                 .n_cc                   = 1,
-                .noevent                = dma_chan_dm646x_no_event,
                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
                 .queue_priority_mapping = dm646x_queue_priority_mapping,
         },
@@ -925,6 +914,7 @@ void dm646x_setup_vpif(struct vpif_display_config *display_config,
 
 void __init dm646x_init(void)
 {
+        dm646x_board_setup_refclk(&ref_clk);
         davinci_common_init(&davinci_soc_info_dm646x);
 }
 
diff --git a/arch/arm/mach-davinci/dma.c b/arch/arm/mach-davinci/dma.c
index 648fbb760ae1..15dd886df04c 100644
--- a/arch/arm/mach-davinci/dma.c
+++ b/arch/arm/mach-davinci/dma.c
@@ -226,11 +226,11 @@ struct edma {
          */
         DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
 
-        /* The edma_noevent bit for each channel is clear unless
-         * it doesn't trigger DMA events on this platform.  It uses a
-         * bit of SOC-specific initialization code.
+        /* The edma_unused bit for each channel is clear unless
+         * it is not being used on this platform. It uses a bit
+         * of SOC-specific initialization code.
          */
-        DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
+        DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH);
 
         unsigned        irq_res_start;
         unsigned        irq_res_end;
@@ -243,6 +243,7 @@ struct edma {
 };
 
 static struct edma *edma_info[EDMA_MAX_CC];
+static int arch_num_cc;
 
 /* dummy param set used to (re)initialize parameter RAM slots */
 static const struct edmacc_param dummy_paramset = {
@@ -555,8 +556,27 @@ static int reserve_contiguous_slots(int ctlr, unsigned int id,
         return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1);
 }
 
+static int prepare_unused_channel_list(struct device *dev, void *data)
+{
+        struct platform_device *pdev = to_platform_device(dev);
+        int i, ctlr;
+
+        for (i = 0; i < pdev->num_resources; i++) {
+                if ((pdev->resource[i].flags & IORESOURCE_DMA) &&
+                                (int)pdev->resource[i].start >= 0) {
+                        ctlr = EDMA_CTLR(pdev->resource[i].start);
+                        clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
+                                        edma_info[ctlr]->edma_unused);
+                }
+        }
+
+        return 0;
+}
+
 /*-----------------------------------------------------------------------*/
 
+static bool unused_chan_list_done;
+
 /* Resource alloc/free:  dma channels, parameter RAM slots */
 
 /**
@@ -594,7 +614,22 @@ int edma_alloc_channel(int channel,
                 void *data,
                 enum dma_event_q eventq_no)
 {
-        unsigned i, done, ctlr = 0;
+        unsigned i, done = 0, ctlr = 0;
+        int ret = 0;
+
+        if (!unused_chan_list_done) {
+                /*
+                 * Scan all the platform devices to find out the EDMA channels
+                 * used and clear them in the unused list, making the rest
+                 * available for ARM usage.
+                 */
+                ret = bus_for_each_dev(&platform_bus_type, NULL, NULL,
+                                prepare_unused_channel_list);
+                if (ret < 0)
+                        return ret;
+
+                unused_chan_list_done = true;
+        }
 
         if (channel >= 0) {
                 ctlr = EDMA_CTLR(channel);
@@ -602,15 +637,15 @@ int edma_alloc_channel(int channel,
         }
 
         if (channel < 0) {
-                for (i = 0; i < EDMA_MAX_CC; i++) {
+                for (i = 0; i < arch_num_cc; i++) {
                         channel = 0;
                         for (;;) {
                                 channel = find_next_bit(edma_info[i]->
-                                                edma_noevent,
+                                                edma_unused,
                                                 edma_info[i]->num_channels,
                                                 channel);
                                 if (channel == edma_info[i]->num_channels)
-                                        return -ENOMEM;
+                                        break;
                                 if (!test_and_set_bit(channel,
                                                 edma_info[i]->edma_inuse)) {
                                         done = 1;
@@ -622,6 +657,8 @@ int edma_alloc_channel(int channel,
                         if (done)
                                 break;
                 }
+                if (!done)
+                        return -ENOMEM;
         } else if (channel >= edma_info[ctlr]->num_channels) {
                 return -EINVAL;
         } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
@@ -642,7 +679,7 @@ int edma_alloc_channel(int channel,
 
         map_dmach_queue(ctlr, channel, eventq_no);
 
-        return channel;
+        return EDMA_CTLR_CHAN(ctlr, channel);
 }
 EXPORT_SYMBOL(edma_alloc_channel);
 
@@ -1219,7 +1256,7 @@ int edma_start(unsigned channel)
                 unsigned int mask = (1 << (channel & 0x1f));
 
                 /* EDMA channels without event association */
-                if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
+                if (test_bit(channel, edma_info[ctlr]->edma_unused)) {
                         pr_debug("EDMA: ESR%d %08x\n", j,
                                 edma_shadow0_read_array(ctlr, SH_ESR, j));
                         edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
@@ -1344,7 +1381,6 @@ static int __init edma_probe(struct platform_device *pdev)
         const s8                (*queue_tc_mapping)[2];
         int                     i, j, found = 0;
         int                     status = -1;
-        const s8                *noevent;
         int                     irq[EDMA_MAX_CC] = {0, 0};
         int                     err_irq[EDMA_MAX_CC] = {0, 0};
         struct resource         *r[EDMA_MAX_CC] = {NULL};
@@ -1407,11 +1443,9 @@ static int __init edma_probe(struct platform_device *pdev)
                         memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
                                         &dummy_paramset, PARM_SIZE);
 
-                noevent = info[j].noevent;
-                if (noevent) {
-                        while (*noevent != -1)
-                                set_bit(*noevent++, edma_info[j]->edma_noevent);
-                }
+                /* Mark all channels as unused */
+                memset(edma_info[j]->edma_unused, 0xff,
+                        sizeof(edma_info[j]->edma_unused));
 
                 sprintf(irq_name, "edma%d", j);
                 irq[j] = platform_get_irq_byname(pdev, irq_name);
@@ -1467,6 +1501,7 @@ static int __init edma_probe(struct platform_device *pdev)
                         edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
                         edma_write_array(j, EDMA_QRAE, i, 0x0);
                 }
+                arch_num_cc++;
         }
 
         if (tc_errs_handled) {
diff --git a/arch/arm/mach-davinci/include/mach/cdce949.h b/arch/arm/mach-davinci/include/mach/cdce949.h
new file mode 100644
index 000000000000..c73331fae341
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/cdce949.h
@@ -0,0 +1,19 @@
+/*
+ * TI CDCE949 off-chip clock synthesizer support
+ *
+ * 2009 (C) Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+#ifndef _MACH_DAVINCI_CDCE949_H
+#define _MACH_DAVINCI_CDCE949_H
+
+#include <linux/clk.h>
+
+#include <mach/clock.h>
+
+int cdce_set_rate(struct clk *clk, unsigned long rate);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 6ca2c9a0a482..50a955f05ef9 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -43,7 +43,7 @@ struct davinci_soc_info {
         void __iomem                    *jtag_id_base;
         struct davinci_id               *ids;
         unsigned long                   ids_num;
-        struct davinci_clk              *cpu_clks;
+        struct clk_lookup               *cpu_clks;
         void __iomem                    **psc_bases;
         unsigned long                   psc_bases_num;
         void __iomem                    *pinmux_base;
diff --git a/arch/arm/mach-davinci/include/mach/cpuidle.h b/arch/arm/mach-davinci/include/mach/cpuidle.h
index cbfc6a9c81b4..74f088b0edfb 100644
--- a/arch/arm/mach-davinci/include/mach/cpuidle.h
+++ b/arch/arm/mach-davinci/include/mach/cpuidle.h
@@ -12,6 +12,7 @@
 
 struct davinci_cpuidle_config {
         u32 ddr2_pdown;
+        void __iomem *ddr2_ctlr_base;
 };
 
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 90704910d343..cc9be7fee627 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -13,15 +13,17 @@
 
 #include <video/da8xx-fb.h>
 
+#include <linux/davinci_emac.h>
 #include <mach/serial.h>
 #include <mach/edma.h>
 #include <mach/i2c.h>
-#include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/mmc.h>
 #include <mach/usb.h>
+#include <mach/pm.h>
 
-extern void __iomem *da8xx_syscfg_base;
+extern void __iomem *da8xx_syscfg0_base;
+extern void __iomem *da8xx_syscfg1_base;
 
 /*
  * The cp_intc interrupt controller for the da8xx isn't in the same
@@ -34,13 +36,17 @@ extern void __iomem *da8xx_syscfg_base;
 #define DA8XX_CP_INTC_SIZE      SZ_8K
 #define DA8XX_CP_INTC_VIRT      (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
 
-#define DA8XX_SYSCFG_BASE       (IO_PHYS + 0x14000)
-#define DA8XX_SYSCFG_VIRT(x)    (da8xx_syscfg_base + (x))
+#define DA8XX_SYSCFG0_BASE      (IO_PHYS + 0x14000)
+#define DA8XX_SYSCFG0_VIRT(x)   (da8xx_syscfg0_base + (x))
 #define DA8XX_JTAG_ID_REG       0x18
 #define DA8XX_CFGCHIP0_REG      0x17c
 #define DA8XX_CFGCHIP2_REG      0x184
 #define DA8XX_CFGCHIP3_REG      0x188
 
+#define DA8XX_SYSCFG1_BASE      (IO_PHYS + 0x22C000)
+#define DA8XX_SYSCFG1_VIRT(x)   (da8xx_syscfg1_base + (x))
+#define DA8XX_DEEPSLEEP_REG     0x8
+
 #define DA8XX_PSC0_BASE         0x01c10000
 #define DA8XX_PLL0_BASE         0x01c11000
 #define DA8XX_TIMER64P0_BASE    0x01c20000
@@ -48,11 +54,13 @@ extern void __iomem *da8xx_syscfg_base;
 #define DA8XX_GPIO_BASE         0x01e26000
 #define DA8XX_PSC1_BASE         0x01e27000
 #define DA8XX_LCD_CNTRL_BASE    0x01e13000
+#define DA8XX_PLL1_BASE         0x01e1a000
 #define DA8XX_MMCSD0_BASE       0x01c40000
 #define DA8XX_AEMIF_CS2_BASE    0x60000000
 #define DA8XX_AEMIF_CS3_BASE    0x62000000
 #define DA8XX_AEMIF_CTL_BASE    0x68000000
 #define DA8XX_DDR2_CTL_BASE     0xb0000000
+#define DA8XX_ARM_RAM_BASE      0xffff0000
 
 #define PINMUX0                 0x00
 #define PINMUX1                 0x04
@@ -90,6 +98,8 @@ void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata);
 int da8xx_register_rtc(void);
 int da850_register_cpufreq(void);
 int da8xx_register_cpuidle(void);
+void __iomem * __init da8xx_get_mem_ctlr(void);
+int da850_register_pm(struct platform_device *pdev);
 
 extern struct platform_device da8xx_serial_device;
 extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index 17ab5236da66..3cd93a801d9b 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
 #include <linux/serial_reg.h>
 #define UART_SHIFT      2
 
-                .macro addruart, rx
+                .macro addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x01000000        @ physical base address
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
index 9fc5a64a5364..3a37b5a6983c 100644
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ b/arch/arm/mach-davinci/include/mach/dm365.h
@@ -14,8 +14,8 @@
 #define __ASM_ARCH_DM665_H
 
 #include <linux/platform_device.h>
+#include <linux/davinci_emac.h>
 #include <mach/hardware.h>
-#include <mach/emac.h>
 #include <mach/asp.h>
 #include <mach/keyscan.h>
 #include <media/davinci/vpfe_capture.h>
@@ -32,10 +32,17 @@
 
 #define DM365_RTC_BASE                  (0x01C69000)
 
+#define DAVINCI_DM365_VC_BASE           (0x01D0C000)
+#define DAVINCI_DMA_VC_TX               2
+#define DAVINCI_DMA_VC_RX               3
+
 void __init dm365_init(void);
 void __init dm365_init_asp(struct snd_platform_data *pdata);
+void __init dm365_init_vc(struct snd_platform_data *pdata);
 void __init dm365_init_ks(struct davinci_ks_platform_data *pdata);
 void __init dm365_init_rtc(void);
+void dm365_init_spi0(unsigned chipselect_mask,
+                        struct spi_board_info *info, unsigned len);
 
 void dm365_set_vpfe_config(struct vpfe_config *cfg);
 #endif /* __ASM_ARCH_DM365_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm644x.h b/arch/arm/mach-davinci/include/mach/dm644x.h
index 44e8f0fae9ea..1a8b09ccc3c8 100644
--- a/arch/arm/mach-davinci/include/mach/dm644x.h
+++ b/arch/arm/mach-davinci/include/mach/dm644x.h
@@ -22,8 +22,8 @@
 #ifndef __ASM_ARCH_DM644X_H
 #define __ASM_ARCH_DM644X_H
 
+#include <linux/davinci_emac.h>
 #include <mach/hardware.h>
-#include <mach/emac.h>
 #include <mach/asp.h>
 #include <media/davinci/vpfe_capture.h>
 
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 8cec746ae9d2..846da98b619a 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -12,10 +12,11 @@
 #define __ASM_ARCH_DM646X_H
 
 #include <mach/hardware.h>
-#include <mach/emac.h>
 #include <mach/asp.h>
 #include <linux/i2c.h>
 #include <linux/videodev2.h>
+#include <linux/clk.h>
+#include <linux/davinci_emac.h>
 
 #define DM646X_EMAC_BASE                (0x01C80000)
 #define DM646X_EMAC_CNTRL_OFFSET        (0x0000)
@@ -30,6 +31,7 @@ void __init dm646x_init(void);
 void __init dm646x_init_ide(void);
 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
+void __init dm646x_board_setup_refclk(struct clk *clk);
 
 void dm646x_video_init(void);
 
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index eb8bfd7925e7..ced3092af5ba 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -280,8 +280,6 @@ struct edma_soc_info {
         unsigned        n_cc;
         enum dma_event_q        default_queue;
 
-        /* list of channels with no even trigger; terminated by "-1" */
-        const s8        *noevent;
         const s8        (*queue_tc_mapping)[2];
         const s8        (*queue_priority_mapping)[2];
 };
diff --git a/arch/arm/mach-davinci/include/mach/emac.h b/arch/arm/mach-davinci/include/mach/emac.h
deleted file mode 100644
index beff4fb7c845..000000000000
--- a/arch/arm/mach-davinci/include/mach/emac.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * TI DaVinci EMAC platform support
- *
- * Author: Kevin Hilman, Deep Root Systems, LLC
- *
- * 2007 (c) Deep Root Systems, LLC. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef _MACH_DAVINCI_EMAC_H
-#define _MACH_DAVINCI_EMAC_H
-
-#include <linux/if_ether.h>
-#include <linux/memory.h>
-
-struct emac_platform_data {
-        char mac_addr[ETH_ALEN];
-        u32 ctrl_reg_offset;
-        u32 ctrl_mod_reg_offset;
-        u32 ctrl_ram_offset;
-        u32 mdio_reg_offset;
-        u32 ctrl_ram_size;
-        u32 phy_mask;
-        u32 mdio_max_freq;
-        u8 rmii_en;
-        u8 version;
-};
-
-enum {
-        EMAC_VERSION_1, /* DM644x */
-        EMAC_VERSION_2, /* DM646x */
-};
-
-void davinci_get_mac_addr(struct memory_accessor *mem_acc, void *context);
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/hardware.h b/arch/arm/mach-davinci/include/mach/hardware.h
index 41c89386e39b..c45ba1f62a11 100644
--- a/arch/arm/mach-davinci/include/mach/hardware.h
+++ b/arch/arm/mach-davinci/include/mach/hardware.h
@@ -27,7 +27,7 @@
 /*
  * I/O mapping
  */
-#define IO_PHYS                         0x01c00000
+#define IO_PHYS                         0x01c00000UL
 #define IO_OFFSET                       0xfd000000 /* Virtual IO = 0xfec00000 */
 #define IO_SIZE                         0x00400000
 #define IO_VIRT                         (IO_PHYS + IO_OFFSET)
diff --git a/arch/arm/mach-davinci/include/mach/i2c.h b/arch/arm/mach-davinci/include/mach/i2c.h
index c248e9b7e825..39fdceac8414 100644
--- a/arch/arm/mach-davinci/include/mach/i2c.h
+++ b/arch/arm/mach-davinci/include/mach/i2c.h
@@ -16,6 +16,8 @@
 struct davinci_i2c_platform_data {
         unsigned int    bus_freq;       /* standard bus frequency (kHz) */
         unsigned int    bus_delay;      /* post-transaction delay (usec) */
+        unsigned int    sda_pin;        /* GPIO pin ID to use for SDA */
+        unsigned int    scl_pin;        /* GPIO pin ID to use for SCL */
 };
 
 /* for board setup code */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 80309aed534a..a91edfb8beea 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -31,6 +31,11 @@
 #define PHYS_OFFSET DAVINCI_DDR_BASE
 #endif
 
+#define DDR2_SDRCR_OFFSET       0xc
+#define DDR2_SRPD_BIT           BIT(23)
+#define DDR2_MCLKSTOPEN_BIT     BIT(30)
+#define DDR2_LPMODEN_BIT        BIT(31)
+
 /*
  * Increase size of DMA-consistent memory region
  */
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index b60c693985ff..2a68c1d8a24b 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -327,6 +327,8 @@ enum davinci_dm365_index {
         /* EDMA event muxing */
         DM365_EVT2_ASP_TX,
         DM365_EVT3_ASP_RX,
+        DM365_EVT2_VC_TX,
+        DM365_EVT3_VC_RX,
         DM365_EVT26_MMC0_RX,
 };
 
@@ -899,6 +901,7 @@ enum davinci_da850_index {
         DA850_GPIO2_15,
         DA850_GPIO4_0,
         DA850_GPIO4_1,
+        DA850_RTC_ALARM,
 };
 
 #ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/pm.h b/arch/arm/mach-davinci/include/mach/pm.h
new file mode 100644
index 000000000000..37b19bf35a85
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/pm.h
@@ -0,0 +1,54 @@
+/*
+ * TI DaVinci platform support for power management.
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef _MACH_DAVINCI_PM_H
+#define _MACH_DAVINCI_PM_H
+
+/*
+ * Caution: Assembly code in sleep.S makes assumtion on the order
+ * of the members of this structure.
+ */
+struct davinci_pm_config {
+        void __iomem *ddr2_ctlr_base;
+        void __iomem *ddrpsc_reg_base;
+        int ddrpsc_num;
+        void __iomem *ddrpll_reg_base;
+        void __iomem *deepsleep_reg;
+        void __iomem *cpupll_reg_base;
+        /*
+         * Note on SLEEPCOUNT:
+         * The SLEEPCOUNT feature is mainly intended for cases in which
+         * the internal oscillator is used. The internal oscillator is
+         * fully disabled in deep sleep mode.  When you exist deep sleep
+         * mode, the oscillator will be turned on and will generate very
+         * small oscillations which will not be detected by the deep sleep
+         * counter.  Eventually those oscillations will grow to an amplitude
+         * large enough to start incrementing the deep sleep counter.
+         * In this case recommendation from hardware engineers is that the
+         * SLEEPCOUNT be set to 4096.  This means that 4096 valid clock cycles
+         * must be detected before the clock is passed to the rest of the
+         * system.
+         * In the case that the internal oscillator is not used and the
+         * clock is generated externally, the SLEEPCOUNT value can be very
+         * small since the clock input is assumed to be stable before SoC
+         * is taken out of deepsleep mode.  A value of 128 would be more than
+         * adequate.
+         */
+        int sleepcount;
+};
+
+extern unsigned int davinci_cpu_suspend_sz;
+extern void davinci_cpu_suspend(struct davinci_pm_config *);
+
+#endif
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 171173c1dbad..651f6d8158fa 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -180,8 +180,23 @@
 #define DA8XX_LPSC1_CR_P3_SS            26
 #define DA8XX_LPSC1_L3_CBA_RAM          31
 
+/* PSC register offsets */
+#define EPCPR           0x070
+#define PTCMD           0x120
+#define PTSTAT          0x128
+#define PDSTAT          0x200
+#define PDCTL1          0x304
+#define MDSTAT          0x800
+#define MDCTL           0xA00
+
+#define MDSTAT_STATE_MASK 0x1f
+
+#ifndef __ASSEMBLER__
+
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 unsigned int id, char enable);
 
+#endif
+
 #endif /* __ASM_ARCH_PSC_H */
diff --git a/arch/arm/mach-davinci/include/mach/spi.h b/arch/arm/mach-davinci/include/mach/spi.h
new file mode 100644
index 000000000000..910efbf099c0
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/spi.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2009 Texas Instruments.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ARCH_ARM_DAVINCI_SPI_H
+#define __ARCH_ARM_DAVINCI_SPI_H
+
+enum {
+        SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+        SPI_VERSION_2, /* For DA8xx */
+};
+
+struct davinci_spi_platform_data {
+        u8      version;
+        u8      num_chipselect;
+        u8      wdelay;
+        u8      odd_parity;
+        u8      parity_enable;
+        u8      wait_enable;
+        u8      timer_disable;
+        u8      clk_internal;
+        u8      cs_hold;
+        u8      intr_level;
+        u8      poll_mode;
+        u8      use_dma;
+        u8      c2tdelay;
+        u8      t2cdelay;
+};
+
+#endif  /* __ARCH_ARM_DAVINCI_SPI_H */
diff --git a/arch/arm/mach-davinci/include/mach/timex.h b/arch/arm/mach-davinci/include/mach/timex.h
index 52827567841d..9b885298f106 100644
--- a/arch/arm/mach-davinci/include/mach/timex.h
+++ b/arch/arm/mach-davinci/include/mach/timex.h
@@ -11,7 +11,12 @@
 #ifndef __ASM_ARCH_TIMEX_H
 #define __ASM_ARCH_TIMEX_H
 
-/* The source frequency for the timers is the 27MHz clock */
+/*
+ * Alert: Not all timers of the DaVinci family run at a frequency of 27MHz,
+ * but we should be fine as long as CLOCK_TICK_RATE or LATCH (see include/
+ * linux/jiffies.h) are not used directly in code. Currently none of the
+ * code relevant to DaVinci platform depends on these values directly.
+ */
 #define CLOCK_TICK_RATE 27000000
 
 #endif /* __ASM_ARCH_TIMEX_H__ */
diff --git a/arch/arm/mach-davinci/io.c b/arch/arm/mach-davinci/io.c
index 49912b48b1b0..a1c0b6b99edf 100644
--- a/arch/arm/mach-davinci/io.c
+++ b/arch/arm/mach-davinci/io.c
@@ -24,7 +24,7 @@ void __iomem *davinci_ioremap(unsigned long p, size_t size, unsigned int type)
         if (BETWEEN(p, IO_PHYS, IO_SIZE))
                 return XLATE(p, IO_PHYS, IO_VIRT);
 
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(davinci_ioremap);
 
diff --git a/arch/arm/mach-davinci/pm.c b/arch/arm/mach-davinci/pm.c
new file mode 100644
index 000000000000..fab953b43dea
--- /dev/null
+++ b/arch/arm/mach-davinci/pm.c
@@ -0,0 +1,158 @@
+/*
+ * DaVinci Power Management Routines
+ *
+ * Copyright (C) 2009 Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+
+#include <asm/cacheflush.h>
+#include <asm/delay.h>
+
+#include <mach/da8xx.h>
+#include <mach/sram.h>
+#include <mach/pm.h>
+
+#include "clock.h"
+
+#define DEEPSLEEP_SLEEPCOUNT_MASK       0xFFFF
+
+static void (*davinci_sram_suspend) (struct davinci_pm_config *);
+static struct davinci_pm_config *pdata;
+
+static void davinci_sram_push(void *dest, void *src, unsigned int size)
+{
+        memcpy(dest, src, size);
+        flush_icache_range((unsigned long)dest, (unsigned long)(dest + size));
+}
+
+static void davinci_pm_suspend(void)
+{
+        unsigned val;
+
+        if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
+
+                /* Switch CPU PLL to bypass mode */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+
+                udelay(PLL_BYPASS_TIME);
+
+                /* Powerdown CPU PLL */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val |= PLLCTL_PLLPWRDN;
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+        }
+
+        /* Configure sleep count in deep sleep register */
+        val = __raw_readl(pdata->deepsleep_reg);
+        val &= ~DEEPSLEEP_SLEEPCOUNT_MASK,
+        val |= pdata->sleepcount;
+        __raw_writel(val, pdata->deepsleep_reg);
+
+        /* System goes to sleep in this call */
+        davinci_sram_suspend(pdata);
+
+        if (pdata->cpupll_reg_base != pdata->ddrpll_reg_base) {
+
+                /* put CPU PLL in reset */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val &= ~PLLCTL_PLLRST;
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+
+                /* put CPU PLL in power down */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val &= ~PLLCTL_PLLPWRDN;
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+
+                /* wait for CPU PLL reset */
+                udelay(PLL_RESET_TIME);
+
+                /* bring CPU PLL out of reset */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val |= PLLCTL_PLLRST;
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+
+                /* Wait for CPU PLL to lock */
+                udelay(PLL_LOCK_TIME);
+
+                /* Remove CPU PLL from bypass mode */
+                val = __raw_readl(pdata->cpupll_reg_base + PLLCTL);
+                val &= ~PLLCTL_PLLENSRC;
+                val |= PLLCTL_PLLEN;
+                __raw_writel(val, pdata->cpupll_reg_base + PLLCTL);
+        }
+}
+
+static int davinci_pm_enter(suspend_state_t state)
+{
+        int ret = 0;
+
+        switch (state) {
+        case PM_SUSPEND_STANDBY:
+        case PM_SUSPEND_MEM:
+                davinci_pm_suspend();
+                break;
+        default:
+                ret = -EINVAL;
+        }
+
+        return ret;
+}
+
+static struct platform_suspend_ops davinci_pm_ops = {
+        .enter          = davinci_pm_enter,
+        .valid          = suspend_valid_only_mem,
+};
+
+static int __init davinci_pm_probe(struct platform_device *pdev)
+{
+        pdata = pdev->dev.platform_data;
+        if (!pdata) {
+                dev_err(&pdev->dev, "cannot get platform data\n");
+                return -ENOENT;
+        }
+
+        davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL);
+        if (!davinci_sram_suspend) {
+                dev_err(&pdev->dev, "cannot allocate SRAM memory\n");
+                return -ENOMEM;
+        }
+
+        davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend,
+                                                davinci_cpu_suspend_sz);
+
+        suspend_set_ops(&davinci_pm_ops);
+
+        return 0;
+}
+
+static int __exit davinci_pm_remove(struct platform_device *pdev)
+{
+        sram_free(davinci_sram_suspend, davinci_cpu_suspend_sz);
+        return 0;
+}
+
+static struct platform_driver davinci_pm_driver = {
+        .driver = {
+                .name    = "pm-davinci",
+                .owner   = THIS_MODULE,
+        },
+        .remove = __exit_p(davinci_pm_remove),
+};
+
+static int __init davinci_pm_init(void)
+{
+        return platform_driver_probe(&davinci_pm_driver, davinci_pm_probe);
+}
+late_initcall(davinci_pm_init);
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 04a3cb72c5ab..adf6b5c7f1e5 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -25,17 +25,6 @@
 #include <mach/cputype.h>
 #include <mach/psc.h>
 
-/* PSC register offsets */
-#define EPCPR           0x070
-#define PTCMD           0x120
-#define PTSTAT          0x128
-#define PDSTAT          0x200
-#define PDCTL1          0x304
-#define MDSTAT          0x800
-#define MDCTL           0xA00
-
-#define MDSTAT_STATE_MASK 0x1f
-
 /* Return nonzero iff the domain's clock is active */
 int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
 {
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
new file mode 100644
index 000000000000..fb5e72b532b0
--- /dev/null
+++ b/arch/arm/mach-davinci/sleep.S
@@ -0,0 +1,224 @@
+/*
+ * (C) Copyright 2009, Texas Instruments, Inc. http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* replicated define because linux/bitops.h cannot be included in assembly */
+#define BIT(nr)                 (1 << (nr))
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/psc.h>
+#include <mach/memory.h>
+
+#include "clock.h"
+
+/* Arbitrary, hardware currently does not update PHYRDY correctly */
+#define PHYRDY_CYCLES           0x1000
+
+/* Assume 25 MHz speed for the cycle conversions since PLLs are bypassed */
+#define PLL_BYPASS_CYCLES       (PLL_BYPASS_TIME * 25)
+#define PLL_RESET_CYCLES        (PLL_RESET_TIME * 25)
+#define PLL_LOCK_CYCLES         (PLL_LOCK_TIME * 25)
+
+#define DEEPSLEEP_SLEEPENABLE_BIT       BIT(31)
+
+        .text
+/*
+ * Move DaVinci into deep sleep state
+ *
+ * Note: This code is copied to internal SRAM by PM code. When the DaVinci
+ *       wakes up it continues execution at the point it went to sleep.
+ * Register Usage:
+ *      r0: contains virtual base for DDR2 controller
+ *      r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
+ *      r2: contains PSC number for DDR2
+ *      r3: contains virtual base DDR2 PLL controller
+ *      r4: contains virtual address of the DEEPSLEEP register
+ */
+ENTRY(davinci_cpu_suspend)
+        stmfd   sp!, {r0-r12, lr}               @ save registers on stack
+
+        ldr     ip, CACHE_FLUSH
+        blx     ip
+
+        ldmia   r0, {r0-r4}
+
+        /*
+         * Switch DDR to self-refresh mode.
+         */
+
+        /* calculate SDRCR address */
+        ldr     ip, [r0, #DDR2_SDRCR_OFFSET]
+        bic     ip, ip, #DDR2_SRPD_BIT
+        orr     ip, ip, #DDR2_LPMODEN_BIT
+        str     ip, [r0, #DDR2_SDRCR_OFFSET]
+
+        ldr     ip, [r0, #DDR2_SDRCR_OFFSET]
+        orr     ip, ip, #DDR2_MCLKSTOPEN_BIT
+        str     ip, [r0, #DDR2_SDRCR_OFFSET]
+
+       mov      ip, #PHYRDY_CYCLES
+1:     subs     ip, ip, #0x1
+       bne      1b
+
+       /* Disable DDR2 LPSC */
+        mov     r7, r0
+        mov     r0, #0x2
+        bl davinci_ddr_psc_config
+        mov     r0, r7
+
+        /* Disable clock to DDR PHY */
+        ldr     ip, [r3, #PLLDIV1]
+        bic     ip, ip, #PLLDIV_EN
+        str     ip, [r3, #PLLDIV1]
+
+        /* Put the DDR PLL in bypass and power down */
+        ldr     ip, [r3, #PLLCTL]
+        bic     ip, ip, #PLLCTL_PLLENSRC
+        bic     ip, ip, #PLLCTL_PLLEN
+        str     ip, [r3, #PLLCTL]
+
+        /* Wait for PLL to switch to bypass */
+       mov      ip, #PLL_BYPASS_CYCLES
+2:     subs     ip, ip, #0x1
+       bne      2b
+
+       /* Power down the PLL */
+        ldr     ip, [r3, #PLLCTL]
+        orr     ip, ip, #PLLCTL_PLLPWRDN
+        str     ip, [r3, #PLLCTL]
+
+        /* Go to deep sleep */
+        ldr     ip, [r4]
+        orr     ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
+        /* System goes to sleep beyond after this instruction */
+        str     ip, [r4]
+
+        /* Wake up from sleep */
+
+        /* Clear sleep enable */
+        ldr     ip, [r4]
+        bic     ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
+        str     ip, [r4]
+
+        /* initialize the DDR PLL controller */
+
+        /* Put PLL in reset */
+        ldr     ip, [r3, #PLLCTL]
+        bic     ip, ip, #PLLCTL_PLLRST
+        str     ip, [r3, #PLLCTL]
+
+        /* Clear PLL power down */
+        ldr     ip, [r3, #PLLCTL]
+        bic     ip, ip, #PLLCTL_PLLPWRDN
+        str     ip, [r3, #PLLCTL]
+
+       mov      ip, #PLL_RESET_CYCLES
+3:     subs     ip, ip, #0x1
+       bne      3b
+
+       /* Bring PLL out of reset */
+        ldr     ip, [r3, #PLLCTL]
+        orr     ip, ip, #PLLCTL_PLLRST
+        str     ip, [r3, #PLLCTL]
+
+        /* Wait for PLL to lock (assume prediv = 1, 25MHz OSCIN) */
+       mov      ip, #PLL_LOCK_CYCLES
+4:     subs     ip, ip, #0x1
+       bne      4b
+
+       /* Remove PLL from bypass mode */
+        ldr     ip, [r3, #PLLCTL]
+        bic     ip, ip, #PLLCTL_PLLENSRC
+        orr     ip, ip, #PLLCTL_PLLEN
+        str     ip, [r3, #PLLCTL]
+
+        /* Start 2x clock to DDR2 */
+
+        ldr     ip, [r3, #PLLDIV1]
+        orr     ip, ip, #PLLDIV_EN
+        str     ip, [r3, #PLLDIV1]
+
+        /* Enable VCLK */
+
+       /* Enable DDR2 LPSC */
+        mov     r7, r0
+        mov     r0, #0x3
+        bl davinci_ddr_psc_config
+        mov     r0, r7
+
+        /* clear  MCLKSTOPEN */
+
+        ldr     ip, [r0, #DDR2_SDRCR_OFFSET]
+        bic     ip, ip, #DDR2_MCLKSTOPEN_BIT
+        str     ip, [r0, #DDR2_SDRCR_OFFSET]
+
+        ldr     ip, [r0, #DDR2_SDRCR_OFFSET]
+        bic     ip, ip, #DDR2_LPMODEN_BIT
+        str     ip, [r0, #DDR2_SDRCR_OFFSET]
+
+        /* Restore registers and return */
+        ldmfd   sp!, {r0-r12, pc}
+
+ENDPROC(davinci_cpu_suspend)
+
+/*
+ * Disables or Enables DDR2 LPSC
+ * Register Usage:
+ *      r0: Enable or Disable LPSC r0 = 0x3 => Enable, r0 = 0x2 => Disable LPSC
+ *      r1: contains virtual base for DDR2 Power and Sleep controller (PSC)
+ *      r2: contains PSC number for DDR2
+ */
+ENTRY(davinci_ddr_psc_config)
+        /* Set next state in mdctl for DDR2 */
+        mov     r6, #MDCTL
+        add     r6, r6, r2, lsl #2
+        ldr     ip, [r1, r6]
+        bic     ip, ip, #MDSTAT_STATE_MASK
+        orr     ip, ip, r0
+        str     ip, [r1, r6]
+
+        /* Enable the Power Domain Transition Command */
+        ldr     ip, [r1, #PTCMD]
+        orr     ip, ip, #0x1
+        str     ip, [r1, #PTCMD]
+
+        /* Check for Transition Complete (PTSTAT) */
+ptstat_done:
+        ldr     ip, [r1, #PTSTAT]
+        and     ip, ip, #0x1
+        cmp     ip, #0x0
+        bne     ptstat_done
+
+        /* Check for DDR2 clock disable completion; */
+        mov     r6, #MDSTAT
+        add     r6, r6, r2, lsl #2
+ddr2clk_stop_done:
+        ldr     ip, [r1, r6]
+        and     ip, ip, #MDSTAT_STATE_MASK
+        cmp     ip, r0
+        bne     ddr2clk_stop_done
+
+        mov     pc, lr
+ENDPROC(davinci_ddr_psc_config)
+
+CACHE_FLUSH:
+        .word   arm926_flush_kern_cache_all
+
+ENTRY(davinci_cpu_suspend_sz)
+        .word   . - davinci_cpu_suspend
+ENDPROC(davinci_cpu_suspend_sz)
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
index 9b89ec7d3040..1521d13f1d14 100644
--- a/arch/arm/mach-dove/include/mach/debug-macro.S
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =DOVE_SB_REGS_PHYS_BASE
diff --git a/arch/arm/mach-dove/include/mach/vmalloc.h b/arch/arm/mach-dove/include/mach/vmalloc.h
index 8b2c974755c6..a28792cf761e 100644
--- a/arch/arm/mach-dove/include/mach/vmalloc.h
+++ b/arch/arm/mach-dove/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-dove/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfd800000
+#define VMALLOC_END     0xfd800000UL
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
index 1dde8227f3a2..ebbd89f0e6c0 100644
--- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 **/
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mov     \rx, #0xf0000000
                 orr     \rx, \rx, #0x00000be0
                 .endm
diff --git a/arch/arm/mach-ep93xx/Kconfig b/arch/arm/mach-ep93xx/Kconfig
index 9167c3d2a5ed..3a08b18f6433 100644
--- a/arch/arm/mach-ep93xx/Kconfig
+++ b/arch/arm/mach-ep93xx/Kconfig
@@ -161,6 +161,20 @@ config MACH_MICRO9S
           Say 'Y' here if you want your kernel to support the
           Contec Micro9-Slim board.
 
+config MACH_SIM_ONE
+        bool "Support Simplemachines Sim.One board"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the
+          Simplemachines Sim.One board.
+
+config MACH_SNAPPER_CL15
+        bool "Support Bluewater Systems Snapper CL15 Module"
+        depends on EP93XX_SDCE0_PHYS_OFFSET
+        help
+          Say 'Y' here if you want your kernel to support the Bluewater
+          Systems Snapper CL15 Module.
+
 config MACH_TS72XX
         bool "Support Technologic Systems TS-72xx SBC"
         depends on EP93XX_SDCE3_SYNC_PHYS_OFFSET
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile
index eae6199a9891..33ee2c863d18 100644
--- a/arch/arm/mach-ep93xx/Makefile
+++ b/arch/arm/mach-ep93xx/Makefile
@@ -10,4 +10,6 @@ obj-$(CONFIG_MACH_ADSSPHERE)	+= adssphere.o
 obj-$(CONFIG_MACH_EDB93XX)      += edb93xx.o
 obj-$(CONFIG_MACH_GESBC9312)    += gesbc9312.o
 obj-$(CONFIG_MACH_MICRO9)       += micro9.o
+obj-$(CONFIG_MACH_SIM_ONE)      += simone.o
+obj-$(CONFIG_MACH_SNAPPER_CL15) += snappercl15.o
 obj-$(CONFIG_MACH_TS72XX)       += ts72xx.o
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 1d0f9d8aff2e..5f80092b6ace 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -10,6 +10,8 @@
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -445,37 +447,39 @@ static void __init ep93xx_dma_clock_init(void)
 static int __init ep93xx_clock_init(void)
 {
         u32 value;
-        int i;
 
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
-        if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
+        /* Determine the bootloader configured pll1 rate */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET1);
+        if (!(value & EP93XX_SYSCON_CLKSET1_NBYP1))
                 clk_pll1.rate = clk_xtali.rate;
-        } else {
+        else
                 clk_pll1.rate = calc_pll_rate(value);
-        }
+
+        /* Initialize the pll1 derived clocks */
         clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7];
         clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7];
         clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3];
         ep93xx_dma_clock_init();
 
-        value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
-        if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
+        /* Determine the bootloader configured pll2 rate */
+        value = __raw_readl(EP93XX_SYSCON_CLKSET2);
+        if (!(value & EP93XX_SYSCON_CLKSET2_NBYP2))
                 clk_pll2.rate = clk_xtali.rate;
-        } else if (value & 0x00040000) {                /* PLL2 enabled?  */
+        else if (value & EP93XX_SYSCON_CLKSET2_PLL2_EN)
                 clk_pll2.rate = calc_pll_rate(value);
-        } else {
+        else
                 clk_pll2.rate = 0;
-        }
+
+        /* Initialize the pll2 derived clocks */
         clk_usb_host.rate = clk_pll2.rate / (((value >> 28) & 0xf) + 1);
 
-        printk(KERN_INFO "ep93xx: PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
+        pr_info("PLL1 running at %ld MHz, PLL2 at %ld MHz\n",
                 clk_pll1.rate / 1000000, clk_pll2.rate / 1000000);
-        printk(KERN_INFO "ep93xx: FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
+        pr_info("FCLK %ld MHz, HCLK %ld MHz, PCLK %ld MHz\n",
                 clk_f.rate / 1000000, clk_h.rate / 1000000,
                 clk_p.rate / 1000000);
 
-        for (i = 0; i < ARRAY_SIZE(clocks); i++)
-                clkdev_add(&clocks[i]);
+        clkdev_add_table(clocks, ARRAY_SIZE(clocks));
         return 0;
 }
 arch_initcall(ep93xx_clock_init);
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 1f0d66561bbe..90fb591cbffa 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -14,12 +14,15 @@
  * your option) any later version.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
 #include <linux/dma-mapping.h>
 #include <linux/timex.h>
+#include <linux/irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
@@ -35,7 +38,6 @@
 
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <asm/mach/irq.h>
 
 #include <asm/hardware/vic.h>
 
@@ -82,13 +84,40 @@ void __init ep93xx_map_io(void)
  * to use this timer for something else.  We also use timer 4 for keeping
  * track of lost jiffies.
  */
-static unsigned int last_jiffy_time;
-
+#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
+#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
+#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
+#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
+#define EP93XX_TIMER123_CONTROL_ENABLE  (1 << 7)
+#define EP93XX_TIMER123_CONTROL_MODE    (1 << 6)
+#define EP93XX_TIMER123_CONTROL_CLKSEL  (1 << 3)
+#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
+#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
+#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
+#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
+#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
+#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
+#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
+#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
+#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
+#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
+#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
+#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
+
+#define EP93XX_TIMER123_CLOCK           508469
+#define EP93XX_TIMER4_CLOCK             983040
+
+#define TIMER1_RELOAD                   ((EP93XX_TIMER123_CLOCK / HZ) - 1)
 #define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 
+static unsigned int last_jiffy_time;
+
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
+        /* Writing any value clears the timer interrupt */
         __raw_writel(1, EP93XX_TIMER1_CLEAR);
+
+        /* Recover lost jiffies */
         while ((signed long)
                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
                                                 >= TIMER4_TICKS_PER_JIFFY) {
@@ -107,13 +136,18 @@ static struct irqaction ep93xx_timer_irq = {
 
 static void __init ep93xx_timer_init(void)
 {
+        u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
+                    EP93XX_TIMER123_CONTROL_CLKSEL;
+
         /* Enable periodic HZ timer.  */
-        __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
-        __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
-        __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
+        __raw_writel(tmode, EP93XX_TIMER1_CONTROL);
+        __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD);
+        __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
+                        EP93XX_TIMER1_CONTROL);
 
         /* Enable lost jiffy timer.  */
-        __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
+        __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
+                        EP93XX_TIMER4_VALUE_HIGH);
 
         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 }
@@ -135,237 +169,16 @@ struct sys_timer ep93xx_timer = {
 
 
 /*************************************************************************
- * GPIO handling for EP93xx
- *************************************************************************/
-static unsigned char gpio_int_unmasked[3];
-static unsigned char gpio_int_enabled[3];
-static unsigned char gpio_int_type1[3];
-static unsigned char gpio_int_type2[3];
-static unsigned char gpio_int_debounce[3];
-
-/* Port ordering is: A B F */
-static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
-static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
-static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
-static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
-static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
-
-void ep93xx_gpio_update_int_params(unsigned port)
-{
-        BUG_ON(port > 2);
-
-        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
-
-        __raw_writeb(gpio_int_type2[port],
-                EP93XX_GPIO_REG(int_type2_register_offset[port]));
-
-        __raw_writeb(gpio_int_type1[port],
-                EP93XX_GPIO_REG(int_type1_register_offset[port]));
-
-        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
-                EP93XX_GPIO_REG(int_en_register_offset[port]));
-}
-
-void ep93xx_gpio_int_mask(unsigned line)
-{
-        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
-}
-
-void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if (enable)
-                gpio_int_debounce[port] |= port_mask;
-        else
-                gpio_int_debounce[port] &= ~port_mask;
-
-        __raw_writeb(gpio_int_debounce[port],
-                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
-}
-EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
-
-/*************************************************************************
  * EP93xx IRQ handling
  *************************************************************************/
-static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        unsigned char status;
-        int i;
-
-        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-
-        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
-        for (i = 0; i < 8; i++) {
-                if (status & (1 << i)) {
-                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
-                        generic_handle_irq(gpio_irq);
-                }
-        }
-}
-
-static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-        /*
-         * map discontiguous hw irq range to continous sw irq range:
-         *
-         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
-         */
-        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
-        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
-
-        generic_handle_irq(gpio_irq);
-}
-
-static void ep93xx_gpio_irq_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-                ep93xx_gpio_update_int_params(port);
-        }
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-        int port_mask = 1 << (line & 7);
-
-        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
-                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
-
-        gpio_int_unmasked[port] &= ~port_mask;
-        ep93xx_gpio_update_int_params(port);
-
-        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
-}
-
-static void ep93xx_gpio_irq_mask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] &= ~(1 << (line & 7));
-        ep93xx_gpio_update_int_params(port);
-}
-
-static void ep93xx_gpio_irq_unmask(unsigned int irq)
-{
-        int line = irq_to_gpio(irq);
-        int port = line >> 3;
-
-        gpio_int_unmasked[port] |= 1 << (line & 7);
-        ep93xx_gpio_update_int_params(port);
-}
-
-
-/*
- * gpio_int_type1 controls whether the interrupt is level (0) or
- * edge (1) triggered, while gpio_int_type2 controls whether it
- * triggers on low/falling (0) or high/rising (1).
- */
-static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
-{
-        struct irq_desc *desc = irq_desc + irq;
-        const int gpio = irq_to_gpio(irq);
-        const int port = gpio >> 3;
-        const int port_mask = 1 << (gpio & 7);
-
-        gpio_direction_input(gpio);
-
-        switch (type) {
-        case IRQ_TYPE_EDGE_RISING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_EDGE_FALLING:
-                gpio_int_type1[port] |= port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_edge_irq;
-                break;
-        case IRQ_TYPE_LEVEL_HIGH:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_LEVEL_LOW:
-                gpio_int_type1[port] &= ~port_mask;
-                gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_level_irq;
-                break;
-        case IRQ_TYPE_EDGE_BOTH:
-                gpio_int_type1[port] |= port_mask;
-                /* set initial polarity based on current input level */
-                if (gpio_get_value(gpio))
-                        gpio_int_type2[port] &= ~port_mask; /* falling */
-                else
-                        gpio_int_type2[port] |= port_mask; /* rising */
-                desc->handle_irq = handle_edge_irq;
-                break;
-        default:
-                pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
-                       type, gpio);
-                return -EINVAL;
-        }
-
-        gpio_int_enabled[port] |= port_mask;
-
-        desc->status &= ~IRQ_TYPE_SENSE_MASK;
-        desc->status |= type & IRQ_TYPE_SENSE_MASK;
-
-        ep93xx_gpio_update_int_params(port);
-
-        return 0;
-}
-
-static struct irq_chip ep93xx_gpio_irq_chip = {
-        .name           = "GPIO",
-        .ack            = ep93xx_gpio_irq_ack,
-        .mask_ack       = ep93xx_gpio_irq_mask_ack,
-        .mask           = ep93xx_gpio_irq_mask,
-        .unmask         = ep93xx_gpio_irq_unmask,
-        .set_type       = ep93xx_gpio_irq_type,
-};
-
+extern void ep93xx_gpio_init_irq(void);
 
 void __init ep93xx_init_irq(void)
 {
-        int gpio_irq;
-
         vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
         vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
 
-        for (gpio_irq = gpio_to_irq(0);
-             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
-                set_irq_handler(gpio_irq, handle_level_irq);
-                set_irq_flags(gpio_irq, IRQF_VALID);
-        }
-
-        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+        ep93xx_gpio_init_irq();
 }
 
 
@@ -572,9 +385,9 @@ void __init ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
          * CMOS driver.
          */
         if (data->sda_is_open_drain && data->sda_pin != EP93XX_GPIO_LINE_EEDAT)
-                pr_warning("ep93xx: sda != EEDAT, open drain has no effect\n");
+                pr_warning("sda != EEDAT, open drain has no effect\n");
         if (data->scl_is_open_drain && data->scl_pin != EP93XX_GPIO_LINE_EECLK)
-                pr_warning("ep93xx: scl != EECLK, open drain has no effect\n");
+                pr_warning("scl != EECLK, open drain has no effect\n");
 
         __raw_writel((data->sda_is_open_drain << 1) |
                      (data->scl_is_open_drain << 0),
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c
index dbcac9c40a28..8904ca4e2e24 100644
--- a/arch/arm/mach-ep93xx/dma-m2p.c
+++ b/arch/arm/mach-ep93xx/dma-m2p.c
@@ -28,6 +28,8 @@
  * with this implementation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
@@ -173,7 +175,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
 
         switch (m2p_channel_state(ch)) {
         case STATE_IDLE:
-                pr_crit("m2p_irq: dma interrupt without a dma buffer\n");
+                pr_crit("dma interrupt without a dma buffer\n");
                 BUG();
                 break;
 
@@ -197,7 +199,7 @@ static irqreturn_t m2p_irq(int irq, void *dev_id)
                 break;
 
         case STATE_NEXT:
-                pr_crit("m2p_irq: dma interrupt while next\n");
+                pr_crit("dma interrupt while next\n");
                 BUG();
                 break;
         }
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index a4a7be308000..d22d67ac8b99 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -118,12 +118,33 @@ static void __init edb93xx_register_i2c(void)
         }
 }
 
+
+/*************************************************************************
+ * EDB93xx pwm
+ *************************************************************************/
+static void __init edb93xx_register_pwm(void)
+{
+        if (machine_is_edb9301() ||
+            machine_is_edb9302() || machine_is_edb9302a()) {
+                /* EP9301 and EP9302 only have pwm.1 (EGPIO14) */
+                ep93xx_register_pwm(0, 1);
+        } else if (machine_is_edb9307() || machine_is_edb9307a()) {
+                /* EP9307 only has pwm.0 (PWMOUT) */
+                ep93xx_register_pwm(1, 0);
+        } else {
+                /* EP9312 and EP9315 have both */
+                ep93xx_register_pwm(1, 1);
+        }
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
         ep93xx_init_devices();
         edb93xx_register_flash();
         ep93xx_register_eth(&edb93xx_eth_data, 1);
         edb93xx_register_i2c();
+        edb93xx_register_pwm();
 }
 
 
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 1ea8871e03a9..cc377ae8c428 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -13,6 +13,8 @@
  *  published by the Free Software Foundation.
  */
 
+#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
+
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/seq_file.h>
@@ -22,6 +24,235 @@
 
 #include <mach/hardware.h>
 
+/*************************************************************************
+ * GPIO handling for EP93xx
+ *************************************************************************/
+static unsigned char gpio_int_unmasked[3];
+static unsigned char gpio_int_enabled[3];
+static unsigned char gpio_int_type1[3];
+static unsigned char gpio_int_type2[3];
+static unsigned char gpio_int_debounce[3];
+
+/* Port ordering is: A B F */
+static const u8 int_type1_register_offset[3]    = { 0x90, 0xac, 0x4c };
+static const u8 int_type2_register_offset[3]    = { 0x94, 0xb0, 0x50 };
+static const u8 eoi_register_offset[3]          = { 0x98, 0xb4, 0x54 };
+static const u8 int_en_register_offset[3]       = { 0x9c, 0xb8, 0x58 };
+static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
+
+void ep93xx_gpio_update_int_params(unsigned port)
+{
+        BUG_ON(port > 2);
+
+        __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
+
+        __raw_writeb(gpio_int_type2[port],
+                EP93XX_GPIO_REG(int_type2_register_offset[port]));
+
+        __raw_writeb(gpio_int_type1[port],
+                EP93XX_GPIO_REG(int_type1_register_offset[port]));
+
+        __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
+                EP93XX_GPIO_REG(int_en_register_offset[port]));
+}
+
+void ep93xx_gpio_int_mask(unsigned line)
+{
+        gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
+}
+
+void ep93xx_gpio_int_debounce(unsigned int irq, int enable)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if (enable)
+                gpio_int_debounce[port] |= port_mask;
+        else
+                gpio_int_debounce[port] &= ~port_mask;
+
+        __raw_writeb(gpio_int_debounce[port],
+                EP93XX_GPIO_REG(int_debounce_register_offset[port]));
+}
+EXPORT_SYMBOL(ep93xx_gpio_int_debounce);
+
+static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned char status;
+        int i;
+
+        status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+
+        status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
+        for (i = 0; i < 8; i++) {
+                if (status & (1 << i)) {
+                        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
+                        generic_handle_irq(gpio_irq);
+                }
+        }
+}
+
+static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        /*
+         * map discontiguous hw irq range to continous sw irq range:
+         *
+         *  IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
+         */
+        int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
+        int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
+
+        generic_handle_irq(gpio_irq);
+}
+
+static void ep93xx_gpio_irq_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+                ep93xx_gpio_update_int_params(port);
+        }
+
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+        int port_mask = 1 << (line & 7);
+
+        if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+                gpio_int_type2[port] ^= port_mask; /* switch edge direction */
+
+        gpio_int_unmasked[port] &= ~port_mask;
+        ep93xx_gpio_update_int_params(port);
+
+        __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
+}
+
+static void ep93xx_gpio_irq_mask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+
+        gpio_int_unmasked[port] &= ~(1 << (line & 7));
+        ep93xx_gpio_update_int_params(port);
+}
+
+static void ep93xx_gpio_irq_unmask(unsigned int irq)
+{
+        int line = irq_to_gpio(irq);
+        int port = line >> 3;
+
+        gpio_int_unmasked[port] |= 1 << (line & 7);
+        ep93xx_gpio_update_int_params(port);
+}
+
+/*
+ * gpio_int_type1 controls whether the interrupt is level (0) or
+ * edge (1) triggered, while gpio_int_type2 controls whether it
+ * triggers on low/falling (0) or high/rising (1).
+ */
+static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
+{
+        struct irq_desc *desc = irq_desc + irq;
+        const int gpio = irq_to_gpio(irq);
+        const int port = gpio >> 3;
+        const int port_mask = 1 << (gpio & 7);
+
+        gpio_direction_input(gpio);
+
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_EDGE_FALLING:
+                gpio_int_type1[port] |= port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_edge_irq;
+                break;
+        case IRQ_TYPE_LEVEL_HIGH:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] |= port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_LEVEL_LOW:
+                gpio_int_type1[port] &= ~port_mask;
+                gpio_int_type2[port] &= ~port_mask;
+                desc->handle_irq = handle_level_irq;
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                gpio_int_type1[port] |= port_mask;
+                /* set initial polarity based on current input level */
+                if (gpio_get_value(gpio))
+                        gpio_int_type2[port] &= ~port_mask; /* falling */
+                else
+                        gpio_int_type2[port] |= port_mask; /* rising */
+                desc->handle_irq = handle_edge_irq;
+                break;
+        default:
+                pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
+                return -EINVAL;
+        }
+
+        gpio_int_enabled[port] |= port_mask;
+
+        desc->status &= ~IRQ_TYPE_SENSE_MASK;
+        desc->status |= type & IRQ_TYPE_SENSE_MASK;
+
+        ep93xx_gpio_update_int_params(port);
+
+        return 0;
+}
+
+static struct irq_chip ep93xx_gpio_irq_chip = {
+        .name           = "GPIO",
+        .ack            = ep93xx_gpio_irq_ack,
+        .mask_ack       = ep93xx_gpio_irq_mask_ack,
+        .mask           = ep93xx_gpio_irq_mask,
+        .unmask         = ep93xx_gpio_irq_unmask,
+        .set_type       = ep93xx_gpio_irq_type,
+};
+
+void __init ep93xx_gpio_init_irq(void)
+{
+        int gpio_irq;
+
+        for (gpio_irq = gpio_to_irq(0);
+             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
+                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
+                set_irq_handler(gpio_irq, handle_level_irq);
+                set_irq_flags(gpio_irq, IRQF_VALID);
+        }
+
+        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
+        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+}
+
+
+/*************************************************************************
+ * gpiolib interface for EP93xx on-chip GPIOs
+ *************************************************************************/
 struct ep93xx_gpio_chip {
         struct gpio_chip        chip;
 
@@ -31,10 +262,6 @@ struct ep93xx_gpio_chip {
 
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
 
-/* From core.c */
-extern void ep93xx_gpio_int_mask(unsigned line);
-extern void ep93xx_gpio_update_int_params(unsigned port);
-
 static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
index 802858bc8095..5cd22444e223 100644
--- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  */
 #include <mach/ep93xx-regs.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                         @ MMU enabled?
                 ldreq   \rx, =EP93XX_APB_PHYS_BASE      @ Physical base
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index d55194a4c093..93e2ecc79ceb 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -92,21 +92,6 @@
 
 /* APB peripherals */
 #define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
-#define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
-#define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
-#define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
-#define EP93XX_TIMER1_CONTROL           EP93XX_TIMER_REG(0x08)
-#define EP93XX_TIMER1_CLEAR             EP93XX_TIMER_REG(0x0c)
-#define EP93XX_TIMER2_LOAD              EP93XX_TIMER_REG(0x20)
-#define EP93XX_TIMER2_VALUE             EP93XX_TIMER_REG(0x24)
-#define EP93XX_TIMER2_CONTROL           EP93XX_TIMER_REG(0x28)
-#define EP93XX_TIMER2_CLEAR             EP93XX_TIMER_REG(0x2c)
-#define EP93XX_TIMER4_VALUE_LOW         EP93XX_TIMER_REG(0x60)
-#define EP93XX_TIMER4_VALUE_HIGH        EP93XX_TIMER_REG(0x64)
-#define EP93XX_TIMER3_LOAD              EP93XX_TIMER_REG(0x80)
-#define EP93XX_TIMER3_VALUE             EP93XX_TIMER_REG(0x84)
-#define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
-#define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
 
 #define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
 
@@ -167,8 +152,11 @@
 #define EP93XX_SYSCON_PWRCNT_DMA_M2P1   (1<<16)
 #define EP93XX_SYSCON_HALT              EP93XX_SYSCON_REG(0x08)
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
-#define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET1           EP93XX_SYSCON_REG(0x20)
+#define EP93XX_SYSCON_CLKSET1_NBYP1     (1<<23)
+#define EP93XX_SYSCON_CLKSET2           EP93XX_SYSCON_REG(0x24)
+#define EP93XX_SYSCON_CLKSET2_NBYP2     (1<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN   (1<<18)
 #define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
 #define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
 #define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
index 62d17421e48c..1e2f4e97f428 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx_keypad.h
@@ -5,6 +5,8 @@
 #ifndef __ASM_ARCH_EP93XX_KEYPAD_H
 #define __ASM_ARCH_EP93XX_KEYPAD_H
 
+struct matrix_keymap_data;
+
 /* flags for the ep93xx_keypad driver */
 #define EP93XX_KEYPAD_DISABLE_3_KEY     (1<<0)  /* disable 3-key reset */
 #define EP93XX_KEYPAD_DIAG_MODE         (1<<1)  /* diagnostic mode */
@@ -15,15 +17,13 @@
 
 /**
  * struct ep93xx_keypad_platform_data - platform specific device structure
- * @matrix_key_map:             array of keycodes defining the keypad matrix
- * @matrix_key_map_size:        ARRAY_SIZE(matrix_key_map)
- * @debounce:                   debounce start count; terminal count is 0xff
- * @prescale:                   row/column counter pre-scaler load value
- * @flags:                      see above
+ * @keymap_data:        pointer to &matrix_keymap_data
+ * @debounce:           debounce start count; terminal count is 0xff
+ * @prescale:           row/column counter pre-scaler load value
+ * @flags:              see above
  */
 struct ep93xx_keypad_platform_data {
-        unsigned int    *matrix_key_map;
-        int             matrix_key_map_size;
+        struct matrix_keymap_data *keymap_data;
         unsigned int    debounce;
         unsigned int    prescale;
         unsigned int    flags;
diff --git a/arch/arm/mach-ep93xx/include/mach/vmalloc.h b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
index aed21cd3fe2d..1b3f25d03d39 100644
--- a/arch/arm/mach-ep93xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ep93xx/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-ep93xx/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
new file mode 100644
index 000000000000..cd93990f1b99
--- /dev/null
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -0,0 +1,97 @@
+/*
+ * arch/arm/mach-ep93xx/simone.c
+ * Simplemachines Sim.One support.
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * Based on the 2.6.24.7 support:
+ *   Copyright (C) 2009 Simplemachines
+ *   MMC support by Peter Ivanov <ivanovp@gmail.com>, 2007
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static struct physmap_flash_data simone_flash_data = {
+        .width          = 2,
+};
+
+static struct resource simone_flash_resource = {
+        .start          = EP93XX_CS6_PHYS_BASE,
+        .end            = EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+
+static struct platform_device simone_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .num_resources  = 1,
+        .resource       = &simone_flash_resource,
+        .dev = {
+                .platform_data  = &simone_flash_data,
+        },
+};
+
+static struct ep93xx_eth_data simone_eth_data = {
+        .phy_id         = 1,
+};
+
+static struct ep93xxfb_mach_info simone_fb_info = {
+        .num_modes      = EP93XXFB_USE_MODEDB,
+        .bpp            = 16,
+        .flags          = EP93XXFB_USE_SDCSN0 | EP93XXFB_PCLK_FALLING,
+};
+
+static struct i2c_gpio_platform_data simone_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata simone_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("ds1337", 0x68),
+        },
+};
+
+static void __init simone_init_machine(void)
+{
+        ep93xx_init_devices();
+
+        platform_device_register(&simone_flash);
+        ep93xx_register_eth(&simone_eth_data, 1);
+        ep93xx_register_fb(&simone_fb_info);
+        ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
+                            ARRAY_SIZE(simone_i2c_board_info));
+}
+
+MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
+/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = simone_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
new file mode 100644
index 000000000000..51134b0382ca
--- /dev/null
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -0,0 +1,172 @@
+/*
+ * arch/arm/mach-ep93xx/snappercl15.c
+ * Bluewater Systems Snapper CL15 system module
+ *
+ * Copyright (C) 2009 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan@bluewatersys.com>
+ *
+ * NAND code adapted from driver by:
+ *   Andre Renaud <andre@bluewatersys.com>
+ *   James R. McKaskill
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or (at
+ * your option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+#include <linux/fb.h>
+
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/nand.h>
+
+#include <mach/hardware.h>
+#include <mach/fb.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define SNAPPERCL15_NAND_BASE   (EP93XX_CS7_PHYS_BASE + SZ_16M)
+
+#define SNAPPERCL15_NAND_WPN    (1 << 8)  /* Write protect (active low) */
+#define SNAPPERCL15_NAND_ALE    (1 << 9)  /* Address latch */
+#define SNAPPERCL15_NAND_CLE    (1 << 10) /* Command latch */
+#define SNAPPERCL15_NAND_CEN    (1 << 11) /* Chip enable (active low) */
+#define SNAPPERCL15_NAND_RDY    (1 << 14) /* Device ready */
+
+#define NAND_CTRL_ADDR(chip)    (chip->IO_ADDR_W + 0x40)
+
+static void snappercl15_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                      unsigned int ctrl)
+{
+        struct nand_chip *chip = mtd->priv;
+        static u16 nand_state = SNAPPERCL15_NAND_WPN;
+        u16 set;
+
+        if (ctrl & NAND_CTRL_CHANGE) {
+                set = SNAPPERCL15_NAND_CEN | SNAPPERCL15_NAND_WPN;
+
+                if (ctrl & NAND_NCE)
+                        set &= ~SNAPPERCL15_NAND_CEN;
+                if (ctrl & NAND_CLE)
+                        set |= SNAPPERCL15_NAND_CLE;
+                if (ctrl & NAND_ALE)
+                        set |= SNAPPERCL15_NAND_ALE;
+
+                nand_state &= ~(SNAPPERCL15_NAND_CEN |
+                                SNAPPERCL15_NAND_CLE |
+                                SNAPPERCL15_NAND_ALE);
+                nand_state |= set;
+                __raw_writew(nand_state, NAND_CTRL_ADDR(chip));
+        }
+
+        if (cmd != NAND_CMD_NONE)
+                __raw_writew((cmd & 0xff) | nand_state, chip->IO_ADDR_W);
+}
+
+static int snappercl15_nand_dev_ready(struct mtd_info *mtd)
+{
+        struct nand_chip *chip = mtd->priv;
+
+        return !!(__raw_readw(NAND_CTRL_ADDR(chip)) & SNAPPERCL15_NAND_RDY);
+}
+
+static const char *snappercl15_nand_part_probes[] = {"cmdlinepart", NULL};
+
+static struct mtd_partition snappercl15_nand_parts[] = {
+        {
+                .name           = "Kernel",
+                .offset         = 0,
+                .size           = SZ_2M,
+        },
+        {
+                .name           = "Filesystem",
+                .offset         = MTDPART_OFS_APPEND,
+                .size           = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct platform_nand_data snappercl15_nand_data = {
+        .chip = {
+                .nr_chips               = 1,
+                .part_probe_types       = snappercl15_nand_part_probes,
+                .partitions             = snappercl15_nand_parts,
+                .nr_partitions          = ARRAY_SIZE(snappercl15_nand_parts),
+                .options                = NAND_NO_AUTOINCR,
+                .chip_delay             = 25,
+        },
+        .ctrl = {
+                .dev_ready              = snappercl15_nand_dev_ready,
+                .cmd_ctrl               = snappercl15_nand_cmd_ctrl,
+        },
+};
+
+static struct resource snappercl15_nand_resource[] = {
+        {
+                .start          = SNAPPERCL15_NAND_BASE,
+                .end            = SNAPPERCL15_NAND_BASE + SZ_4K - 1,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device snappercl15_nand_device = {
+        .name                   = "gen_nand",
+        .id                     = -1,
+        .dev.platform_data      = &snappercl15_nand_data,
+        .resource               = snappercl15_nand_resource,
+        .num_resources          = ARRAY_SIZE(snappercl15_nand_resource),
+};
+
+static struct ep93xx_eth_data snappercl15_eth_data = {
+        .phy_id                 = 1,
+};
+
+static struct i2c_gpio_platform_data snappercl15_i2c_gpio_data = {
+        .sda_pin                = EP93XX_GPIO_LINE_EEDAT,
+        .sda_is_open_drain      = 0,
+        .scl_pin                = EP93XX_GPIO_LINE_EECLK,
+        .scl_is_open_drain      = 0,
+        .udelay                 = 0,
+        .timeout                = 0,
+};
+
+static struct i2c_board_info __initdata snappercl15_i2c_data[] = {
+        {
+                /* Audio codec */
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+static struct ep93xxfb_mach_info snappercl15_fb_info = {
+        .num_modes              = EP93XXFB_USE_MODEDB,
+        .bpp                    = 16,
+};
+
+static void __init snappercl15_init_machine(void)
+{
+        ep93xx_init_devices();
+        ep93xx_register_eth(&snappercl15_eth_data, 1);
+        ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
+                            ARRAY_SIZE(snappercl15_i2c_data));
+        ep93xx_register_fb(&snappercl15_fb_info);
+        platform_device_register(&snappercl15_nand_device);
+}
+
+MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
+        /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+        .phys_io        = EP93XX_APB_PHYS_BASE,
+        .io_pg_offst    = ((EP93XX_APB_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = EP93XX_SDCE0_PHYS_BASE + 0x100,
+        .map_io         = ep93xx_map_io,
+        .init_irq       = ep93xx_init_irq,
+        .timer          = &ep93xx_timer,
+        .init_machine   = snappercl15_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 41febc796b1c..e3bc3f6f6b10 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -32,12 +32,13 @@ unsigned int mem_fclk_21285 = 50000000;
 
 EXPORT_SYMBOL(mem_fclk_21285);
 
-static void __init early_fclk(char **arg)
+static int __init early_fclk(char *arg)
 {
-        mem_fclk_21285 = simple_strtoul(*arg, arg, 0);
+        mem_fclk_21285 = simple_strtoul(arg, NULL, 0);
+        return 0;
 }
 
-__early_param("mem_fclk_21285=", early_fclk);
+early_param("mem_fclk_21285", early_fclk);
 
 static int __init parse_tag_memclk(const struct tag *tag)
 {
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index 4329b8123570..60dda1318f22 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -15,7 +15,7 @@
 
 #ifndef CONFIG_DEBUG_DC21285_PORT
         /* For NetWinder debugging */
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x7c000000        @ physical
@@ -32,7 +32,7 @@
                 .equ    dc21285_high, ARMCSR_BASE & 0xff000000
                 .equ    dc21285_low,  ARMCSR_BASE & 0x00ffffff
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x42000000
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S
index d04a6eaeae14..ad477047069d 100644
--- a/arch/arm/mach-gemini/include/mach/debug-macro.S
+++ b/arch/arm/mach-gemini/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  */
 #include <mach/hardware.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =GEMINI_UART_BASE                  @ physical
diff --git a/arch/arm/mach-gemini/include/mach/vmalloc.h b/arch/arm/mach-gemini/include/mach/vmalloc.h
index 83e536d9436c..45371eb86fcb 100644
--- a/arch/arm/mach-gemini/include/mach/vmalloc.h
+++ b/arch/arm/mach-gemini/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * (at your option) any later version.
  */
 
-#define VMALLOC_END     0xF0000000
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index 6294a1344dda..a9ee8f0d48b7 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
                 .equ    io_virt, IO_BASE
                 .equ    io_phys, IO_START
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                @ MMU enabled?
                 moveq   \rx, #io_phys          @ physical base address
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index a0f60e55da6a..8b390e36ba69 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -144,8 +144,7 @@ static int __init integrator_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                 struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S
index d347d659ea30..87a6888ae011 100644
--- a/arch/arm/mach-integrator/include/mach/debug-macro.S
+++ b/arch/arm/mach-integrator/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x16000000        @ physical base address
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 3f35293d457a..66ef86d6d9e3 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -558,9 +558,7 @@ static void __init intcp_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(cp_lookups); i++)
-                clkdev_add(&cp_lookups[i]);
-
+        clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
index 9037d2e8557c..c9d6ba46963d 100644
--- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  * published by the Free Software Foundation.
  */
 
-        .macro  addruart, rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                 @ mmu enabled?
         moveq   \rx, #0xff000000        @ physical
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 529580997814..48642e66c566 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -61,9 +61,9 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                                  (cookie - IOP13XX_PCIE_LOWER_MEM_RA));
                 break;
         case IOP13XX_PBI_LOWER_MEM_RA ... IOP13XX_PBI_UPPER_MEM_RA:
-                retval = __arm_ioremap(IOP13XX_PBI_LOWER_MEM_PA +
+                retval = __arm_ioremap_caller(IOP13XX_PBI_LOWER_MEM_PA +
                                        (cookie - IOP13XX_PBI_LOWER_MEM_RA),
-                                       size, mtype);
+                                       size, mtype, __builtin_return_address(0));
                 break;
         case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
                 retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
@@ -75,7 +75,8 @@ void * __iomem __iop13xx_ioremap(unsigned long cookie, size_t size,
                 retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
-                retval = __arm_ioremap(cookie, size, mtype);
+                retval = __arm_ioremap_caller(cookie, size, mtype,
+                                __builtin_return_address(0));
         }
 
         return retval;
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
index 58b01664ffba..736afe1edd1f 100644
--- a/arch/arm/mach-iop32x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  * published by the Free Software Foundation.
  */
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 mov     \rx, #0xfe000000        @ physical as well as virtual
                 orr     \rx, \rx, #0x00800000   @ location of the UART
                 .endm
diff --git a/arch/arm/mach-iop32x/include/mach/vmalloc.h b/arch/arm/mach-iop32x/include/mach/vmalloc.h
index 85ceb09d85f0..c4862d48e583 100644
--- a/arch/arm/mach-iop32x/include/mach/vmalloc.h
+++ b/arch/arm/mach-iop32x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-iop32x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
index a60c9ef05cc3..addb2da78422 100644
--- a/arch/arm/mach-iop33x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  * published by the Free Software Foundation.
  */
 
-                .macro  addruart, rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ mmu enabled?
                 moveq   \rx, #0xff000000        @ physical
diff --git a/arch/arm/mach-iop33x/include/mach/vmalloc.h b/arch/arm/mach-iop33x/include/mach/vmalloc.h
index f9f99dea9bc4..48331dc23704 100644
--- a/arch/arm/mach-iop33x/include/mach/vmalloc.h
+++ b/arch/arm/mach-iop33x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-iop33x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
index 904ff56d2246..6a827681680f 100644
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0xc0000000        @ Physical base
diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
index d195e35aed3b..61c8dae24f95 100644
--- a/arch/arm/mach-ixp2000/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h
@@ -17,4 +17,4 @@
  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  * area for the same reason. ;)
  */
-#define VMALLOC_END         0xfb000000
+#define VMALLOC_END         0xfb000000UL
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
index 905db3188724..a82e375465e2 100644
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
  */
 #include <mach/ixp23xx.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                         @ mmu enabled?
                 ldreq   \rx, =IXP23XX_PERIPHERAL_PHYS   @ physical
diff --git a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
index dd519f678d10..896c56a1c00e 100644
--- a/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp23xx/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  * specific static I/O.
  */
 
-#define VMALLOC_END     (0xec000000)
+#define VMALLOC_END     (0xec000000UL)
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 3bbf40f6d964..71728d36d501 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -427,6 +427,17 @@ static void __init ixp4xx_clocksource_init(void)
 }
 
 /*
+ * sched_clock()
+ */
+unsigned long long sched_clock(void)
+{
+        cycle_t cyc = ixp4xx_get_cycles(NULL);
+        struct clocksource *cs = &clocksource_ixp4xx;
+
+        return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
+}
+
+/*
  * clockevents
  */
 static int ixp4xx_set_next_event(unsigned long evt,
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index 7c6a6912acde..893873eb2a0d 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
  * published by the Free Software Foundation.
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0xc8000000
diff --git a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
index 7b3580b53adf..9bcd64d59854 100644
--- a/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ixp4xx/include/mach/vmalloc.h
@@ -1,5 +1,5 @@
 /*
  * arch/arm/mach-ixp4xx/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (0xFF000000)
+#define VMALLOC_END       (0xff000000UL)
 
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
index a4a55c199d77..d0606774dea7 100644
--- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
 
 #include <mach/bridge-regs.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =KIRKWOOD_REGS_PHYS_BASE
diff --git a/arch/arm/mach-kirkwood/include/mach/vmalloc.h b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
index 8f48260dcdad..bf162ca3d2c1 100644
--- a/arch/arm/mach-kirkwood/include/mach/vmalloc.h
+++ b/arch/arm/mach-kirkwood/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-kirkwood/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S
index 3782c3559497..cf2095da2372 100644
--- a/arch/arm/mach-ks8695/include/mach/debug-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
 #include <mach/hardware.h>
 #include <mach/regs-uart.h>
 
-        .macro  addruart, rx
+        .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                         @ MMU enabled?
                 ldreq   \rx, =KS8695_UART_PA            @ physical base address
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
index 34eed2a63e69..b69ed344c7c9 100644
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
                 .equ    io_virt, IO_BASE
                 .equ    io_phys, IO_START
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #io_phys           @ physical base address
diff --git a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
index 85141ed5383d..c0dcbbba22ba 100644
--- a/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
+++ b/arch/arm/mach-lh7a40x/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
         @ It is not known if this will be appropriate for every 40x
         @ board.
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 mov     \rx, #0x00000700        @ offset from base
diff --git a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
index 3fbd49490bb9..d62da7358b16 100644
--- a/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
+++ b/arch/arm/mach-lh7a40x/include/mach/vmalloc.h
@@ -7,4 +7,4 @@
  *  version 2 as published by the Free Software Foundation.
  *
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
index a8c20bd2f951..3136c913a92c 100644
--- a/arch/arm/mach-loki/include/mach/debug-macro.S
+++ b/arch/arm/mach-loki/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
 
 #include <mach/loki.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =LOKI_REGS_PHYS_BASE
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h
index 8dc3bfcbf9f0..5dcbd865443f 100644
--- a/arch/arm/mach-loki/include/mach/vmalloc.h
+++ b/arch/arm/mach-loki/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-loki/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 2a46ed5cc2a2..886e05648f08 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,11 +88,3 @@ unsigned long clk_get_rate(struct clk *clk)
         return rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index eefffbe683b0..016ae94691c0 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -68,5 +68,3 @@ struct clk clk_##_name = {					\
 
 extern struct clk clk_pxa168_gpio;
 extern struct clk clk_pxa168_timers;
-
-extern void clks_register(struct clk_lookup *, size_t);
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index a850f87de51d..76deff238e1c 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
 
 #include <mach/addr-map.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                         @ MMU enabled?
                 ldreq   \rx, =APB_PHYS_BASE             @ physical
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h
index b60ccaf9fee7..1d0bac003ad0 100644
--- a/arch/arm/mach-mmp/include/mach/vmalloc.h
+++ b/arch/arm/mach-mmp/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * linux/arch/arm/mach-mmp/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 37dbdde17fac..1873c821df90 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -94,7 +94,7 @@ static int __init pxa168_init(void)
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa168_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
-                clks_register(ARRAY_AND_SIZE(pxa168_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index d4049508a4df..46f2d69bef3c 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -131,7 +131,7 @@ static int __init pxa910_init(void)
                 mfp_init_base(MFPR_VIRT_BASE);
                 mfp_init_addr(pxa910_mfp_addr_map);
                 pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
-                clks_register(ARRAY_AND_SIZE(pxa910_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index d48747ebcd3d..528750f307e9 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
 #include <mach/msm_iomap.h>
 
 #ifdef CONFIG_MSM_DEBUG_UART
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         @ see if the MMU is enabled and select appropriate base address
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1
@@ -40,7 +40,7 @@
         beq     1001b
         .endm
 #else
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         .endm
 
         .macro  senduart,rd,rx
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 1c5e7dac086f..05f96b780aa6 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -76,5 +76,6 @@ __msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
                         mtype = MT_DEVICE_NONSHARED;
         }
 
-        return __arm_ioremap(phys_addr, size, mtype);
+        return __arm_ioremap_caller(phys_addr, size, mtype,
+                __builtin_return_address(0));
 }
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
index a06442fbd341..cd81689c4621 100644
--- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
 
 #include <mach/mv78xx0.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =MV78XX0_REGS_PHYS_BASE
diff --git a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
index 1c4954386a84..ba26fe98e640 100644
--- a/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
+++ b/arch/arm/mach-mv78xx0/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-mv78xx0/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END     0xfe000000
+#define VMALLOC_END     0xfe000000UL
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index d1b588519ad2..6cf2d4a7511d 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -570,7 +570,6 @@ static struct clk_lookup lookups[] __initdata = {
 int __init mx1_clocks_init(unsigned long fref)
 {
         unsigned int reg;
-        int i;
 
         /* disable clocks we are able to */
         __raw_writel(0, SCM_GCCR);
@@ -592,8 +591,7 @@ int __init mx1_clocks_init(unsigned long fref)
         reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
         clko_clk.parent = (struct clk *)clko_clocks[reg];
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         clk_enable(&hclk);
         clk_enable(&fclk);
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 91901b5d56c2..e82b489d1215 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -968,7 +968,6 @@ static struct clk_lookup lookups[] = {
  */
 int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
-        int i;
         u32 cscr;
 
         external_low_reference = lref;
@@ -986,8 +985,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
         else
                 spll_clk.parent = &fpm_clk;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clock gates */
         __raw_writel(0, CCM_PCCR0);
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index b010bf9ceaab..18c53a6487fa 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -719,7 +719,6 @@ static void __init to2_adjust_clocks(void)
 int __init mx27_clocks_init(unsigned long fref)
 {
         u32 cscr = __raw_readl(CCM_CSCR);
-        int i;
 
         external_high_reference = fref;
 
@@ -736,8 +735,7 @@ int __init mx27_clocks_init(unsigned long fref)
 
         to2_adjust_clocks();
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks we do not need */
         __raw_writel(0, CCM_PCCR0);
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 6acc88bcdc40..37e1359ad0c0 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -218,10 +218,7 @@ static struct clk_lookup lookups[] = {
 
 int __init mx25_clocks_init(void)
 {
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 7584b4c6c556..f3f41fa4f21b 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -485,15 +485,13 @@ static struct clk_lookup lookups[] = {
 
 int __init mx35_clocks_init()
 {
-        int i;
         unsigned int ll = 0;
 
 #if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
         ll = (3 << 16);
 #endif
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* Turn off all clocks except the ones we need to survive, namely:
          * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 27a318af0d20..b5c39a016db7 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -578,12 +578,10 @@ static struct clk_lookup lookups[] = {
 int __init mx31_clocks_init(unsigned long fref)
 {
         u32 reg;
-        int i;
 
         ckih_rate = fref;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         /* change the csi_clk parent if necessary */
         reg = __raw_readl(MXC_CCM_CCMR);
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
index ecfa37fef8ad..5c85075d8a56 100644
--- a/arch/arm/mach-mxc91231/clock.c
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -624,7 +624,6 @@ static struct clk_lookup lookups[] = {
 int __init mxc91231_clocks_init(unsigned long fref)
 {
         void __iomem *gpt_base;
-        int i;
 
         ckih_rate = fref;
 
@@ -632,8 +631,7 @@ int __init mxc91231_clocks_init(unsigned long fref)
         sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
         sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
         mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S
index 11b9d5b46390..e96339e71d88 100644
--- a/arch/arm/mach-netx/include/mach/debug-macro.S
+++ b/arch/arm/mach-netx/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 
 #include "hardware.h"
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x00100000                @ physical
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
index e876990e1569..4f92acfba954 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x10000000        @ physical base address
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
index be12e31ea528..f83d574d9445 100644
--- a/arch/arm/mach-nomadik/include/mach/vmalloc.h
+++ b/arch/arm/mach-nomadik/include/mach/vmalloc.h
@@ -1,2 +1,2 @@
 
-#define VMALLOC_END       0xe8000000
+#define VMALLOC_END       0xe8000000UL
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
index c9530fba00aa..0859336a8e6d 100644
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
 
 #include <mach/regs-board-a9m9750dev.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, =NS9XXX_CSxSTAT_PHYS(0)
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
index fe964d3bcc47..c8651974c4b0 100644
--- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+++ b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
@@ -11,6 +11,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END     (0xf0000000)
+#define VMALLOC_END     (0xf0000000UL)
 
 #endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/Kconfig b/arch/arm/mach-nuc93x/Kconfig
new file mode 100644
index 000000000000..2bc40a280fad
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_NUC93X
+
+config CPU_NUC932
+        bool
+        help
+          Support for NUC932 of Nuvoton NUC93X CPUs.
+
+menu "NUC932 Machines"
+
+config MACH_NUC932EVB
+        bool "Nuvoton NUC932 Evaluation Board"
+        default y
+        select CPU_NUC932
+        help
+           Say Y here if you are using the Nuvoton NUC932EVB
+
+endmenu
+
+endif
diff --git a/arch/arm/mach-nuc93x/Makefile b/arch/arm/mach-nuc93x/Makefile
new file mode 100644
index 000000000000..440e2dec6c8a
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Makefile
@@ -0,0 +1,14 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Object file lists.
+
+obj-y                           := irq.o time.o dev.o cpu.o clock.o
+# NUC932 CPU support files
+
+obj-$(CONFIG_CPU_NUC932)        += nuc932.o
+
+# machine support
+
+obj-$(CONFIG_MACH_NUC932EVB)    += mach-nuc932evb.o
diff --git a/arch/arm/mach-nuc93x/Makefile.boot b/arch/arm/mach-nuc93x/Makefile.boot
new file mode 100644
index 000000000000..a057b546b6e5
--- /dev/null
+++ b/arch/arm/mach-nuc93x/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y      := 0x00008000
+params_phys-y   := 0x00000100
+
diff --git a/arch/arm/mach-nuc93x/clock.c b/arch/arm/mach-nuc93x/clock.c
new file mode 100644
index 000000000000..0521efbc48c9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/clock.c
@@ -0,0 +1,83 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+
+#include "clock.h"
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (clk->enabled++ == 0)
+                (clk->enable)(clk, 1);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+
+        WARN_ON(clk->enabled == 0);
+
+        spin_lock_irqsave(&clocks_lock, flags);
+        if (--clk->enabled == 0)
+                (clk->enable)(clk, 0);
+        spin_unlock_irqrestore(&clocks_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 27000000;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void nuc93x_clk_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->cken;
+        unsigned long clken;
+
+        clken = __raw_readl(NUC93X_VA_CLKPWR);
+
+        if (enable)
+                clken |= clocks;
+        else
+                clken &= ~clocks;
+
+        __raw_writel(clken, NUC93X_VA_CLKPWR);
+}
+
+void clks_register(struct clk_lookup *clks, size_t num)
+{
+        int i;
+
+        for (i = 0; i < num; i++)
+                clkdev_add(&clks[i]);
+}
diff --git a/arch/arm/mach-nuc93x/clock.h b/arch/arm/mach-nuc93x/clock.h
new file mode 100644
index 000000000000..18e51be4816f
--- /dev/null
+++ b/arch/arm/mach-nuc93x/clock.h
@@ -0,0 +1,36 @@
+/*
+ * linux/arch/arm/mach-nuc93x/clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <asm/clkdev.h>
+
+void nuc93x_clk_enable(struct clk *clk, int enable);
+void clks_register(struct clk_lookup *clks, size_t num);
+
+struct clk {
+        unsigned long           cken;
+        unsigned int            enabled;
+        void                    (*enable)(struct clk *, int enable);
+};
+
+#define DEFINE_CLK(_name, _ctrlbit)                     \
+struct clk clk_##_name = {                              \
+                .enable = nuc93x_clk_enable,            \
+                .cken   = (1 << _ctrlbit),              \
+        }
+
+#define DEF_CLKLOOK(_clk, _devname, _conname)           \
+        {                                               \
+                .clk            = _clk,                 \
+                .dev_id         = _devname,             \
+                .con_id         = _conname,             \
+        }
+
diff --git a/arch/arm/mach-nuc93x/cpu.c b/arch/arm/mach-nuc93x/cpu.c
new file mode 100644
index 000000000000..f6ff5d87354c
--- /dev/null
+++ b/arch/arm/mach-nuc93x/cpu.c
@@ -0,0 +1,135 @@
+/*
+ * linux/arch/arm/mach-nuc93x/cpu.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC93x series cpu common support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-ebi.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* Initial IO mappings */
+
+static struct map_desc nuc93x_iodesc[] __initdata = {
+        IODESC_ENT(IRQ),
+        IODESC_ENT(GCR),
+        IODESC_ENT(UART),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(EBI),
+};
+
+/* Initial nuc932 clock declarations. */
+static DEFINE_CLK(audio, 2);
+static DEFINE_CLK(sd, 3);
+static DEFINE_CLK(jpg, 4);
+static DEFINE_CLK(video, 5);
+static DEFINE_CLK(vpost, 6);
+static DEFINE_CLK(2d, 7);
+static DEFINE_CLK(gpu, 8);
+static DEFINE_CLK(gdma, 9);
+static DEFINE_CLK(adc, 10);
+static DEFINE_CLK(uart, 11);
+static DEFINE_CLK(spi, 12);
+static DEFINE_CLK(pwm, 13);
+static DEFINE_CLK(timer, 14);
+static DEFINE_CLK(wdt, 15);
+static DEFINE_CLK(ac97, 16);
+static DEFINE_CLK(i2s, 16);
+static DEFINE_CLK(usbck, 17);
+static DEFINE_CLK(usb48, 18);
+static DEFINE_CLK(usbh, 19);
+static DEFINE_CLK(i2c, 20);
+static DEFINE_CLK(ext, 0);
+
+static struct clk_lookup nuc932_clkregs[] = {
+       DEF_CLKLOOK(&clk_audio, "nuc932-audio", NULL),
+       DEF_CLKLOOK(&clk_sd, "nuc932-sd", NULL),
+       DEF_CLKLOOK(&clk_jpg, "nuc932-jpg", "NULL"),
+       DEF_CLKLOOK(&clk_video, "nuc932-video", "NULL"),
+       DEF_CLKLOOK(&clk_vpost, "nuc932-vpost", NULL),
+       DEF_CLKLOOK(&clk_2d, "nuc932-2d", NULL),
+       DEF_CLKLOOK(&clk_gpu, "nuc932-gpu", NULL),
+       DEF_CLKLOOK(&clk_gdma, "nuc932-gdma", "NULL"),
+       DEF_CLKLOOK(&clk_adc, "nuc932-adc", NULL),
+       DEF_CLKLOOK(&clk_uart, NULL, "uart"),
+       DEF_CLKLOOK(&clk_spi, "nuc932-spi", NULL),
+       DEF_CLKLOOK(&clk_pwm, "nuc932-pwm", NULL),
+       DEF_CLKLOOK(&clk_timer, NULL, "timer"),
+       DEF_CLKLOOK(&clk_wdt, "nuc932-wdt", NULL),
+       DEF_CLKLOOK(&clk_ac97, "nuc932-ac97", NULL),
+       DEF_CLKLOOK(&clk_i2s, "nuc932-i2s", NULL),
+       DEF_CLKLOOK(&clk_usbck, "nuc932-usbck", NULL),
+       DEF_CLKLOOK(&clk_usb48, "nuc932-usb48", NULL),
+       DEF_CLKLOOK(&clk_usbh, "nuc932-usbh", NULL),
+       DEF_CLKLOOK(&clk_i2c, "nuc932-i2c", NULL),
+       DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+};
+
+/* Initial serial platform data */
+
+struct plat_serial8250_port nuc93x_uart_data[] = {
+        NUC93X_8250PORT(UART0),
+        {},
+};
+
+struct platform_device nuc93x_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = nuc93x_uart_data,
+        },
+};
+
+/*Init NUC93x evb io*/
+
+void __init nuc93x_map_io(struct map_desc *mach_desc, int mach_size)
+{
+        unsigned long idcode = 0x0;
+
+        iotable_init(mach_desc, mach_size);
+        iotable_init(nuc93x_iodesc, ARRAY_SIZE(nuc93x_iodesc));
+
+        idcode = __raw_readl(NUC93XPDID);
+        if (idcode == NUC932_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
+        else
+                printk(KERN_ERR "CPU type detect error!\n");
+
+}
+
+/*Init NUC93x clock*/
+
+void __init nuc93x_init_clocks(void)
+{
+        clks_register(nuc932_clkregs, ARRAY_SIZE(nuc932_clkregs));
+}
+
diff --git a/arch/arm/mach-nuc93x/cpu.h b/arch/arm/mach-nuc93x/cpu.h
new file mode 100644
index 000000000000..9def28197bc9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/cpu.h
@@ -0,0 +1,48 @@
+/*
+ * arch/arm/mach-nuc93x/cpu.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Header file for NUC93X CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define IODESC_ENT(y)                                   \
+{                                                       \
+        .virtual = (unsigned long)NUC93X_VA_##y,        \
+        .pfn     = __phys_to_pfn(NUC93X_PA_##y),        \
+        .length  = NUC93X_SZ_##y,                       \
+        .type    = MT_DEVICE,                           \
+}
+
+#define NUC93X_8250PORT(name)                                   \
+{                                                               \
+        .membase        = name##_BA,                            \
+        .mapbase        = name##_PA,                            \
+        .irq            = IRQ_##name,                           \
+        .uartclk        = 57139200,                             \
+        .regshift       = 2,                                    \
+        .iotype         = UPIO_MEM,                             \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
+}
+
+/*Cpu identifier register*/
+
+#define NUC93XPDID      NUC93X_VA_GCR
+#define NUC932_CPUID    0x29550091
+
+/* extern file from cpu.c */
+
+extern void nuc93x_clock_source(struct device *dev, unsigned char *src);
+extern void nuc93x_init_clocks(void);
+extern void nuc93x_map_io(struct map_desc *mach_desc, int mach_size);
+extern void nuc93x_board_init(struct platform_device **device, int size);
+extern struct platform_device nuc93x_serial_device;
+
diff --git a/arch/arm/mach-nuc93x/dev.c b/arch/arm/mach-nuc93x/dev.c
new file mode 100644
index 000000000000..a962ae9578d6
--- /dev/null
+++ b/arch/arm/mach-nuc93x/dev.c
@@ -0,0 +1,42 @@
+/*
+ * linux/arch/arm/mach-nuc93x/dev.c
+ *
+ * Copyright (C) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+
+#include "cpu.h"
+
+/*Here should be your evb resourse,such as LCD*/
+
+static struct platform_device *nuc93x_public_dev[] __initdata = {
+        &nuc93x_serial_device,
+};
+
+/* Provide adding specific CPU platform devices API */
+
+void __init nuc93x_board_init(struct platform_device **device, int size)
+{
+        platform_add_devices(device, size);
+        platform_add_devices(nuc93x_public_dev, ARRAY_SIZE(nuc93x_public_dev));
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/clkdev.h b/arch/arm/mach-nuc93x/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/entry-macro.S b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1352cbda3797
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/entry-macro.S
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ */
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \base, #AIC_BA
+
+                ldr     \irqnr, [ \base, #AIC_IPER]
+                ldr     \irqnr, [ \base, #AIC_ISNR]
+                cmp     \irqnr, #0
+
+        .endm
+
+        /* currently don't need an disable_fiq macro */
+
+        .macro  disable_fiq
+        .endm
diff --git a/arch/arm/mach-nuc93x/include/mach/hardware.h b/arch/arm/mach-nuc93x/include/mach/hardware.h
new file mode 100644
index 000000000000..fb5c6fcb142e
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/hardware.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/hardware.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
new file mode 100644
index 000000000000..72e5051c7534
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/io.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/io.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+
+#define __mem_pci(a)    (a)
+#define __io(a)         __typesafe_io(a)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/irqs.h b/arch/arm/mach-nuc93x/include/mach/irqs.h
new file mode 100644
index 000000000000..7c4aa71edb44
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/irqs.h
@@ -0,0 +1,59 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/irqs.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define NUC93X_IRQ(x)   (x)
+
+/* Main cpu interrupts */
+
+#define IRQ_WDT         NUC93X_IRQ(1)
+#define IRQ_IRQ0        NUC93X_IRQ(2)
+#define IRQ_IRQ1        NUC93X_IRQ(3)
+#define IRQ_IRQ2        NUC93X_IRQ(4)
+#define IRQ_IRQ3        NUC93X_IRQ(5)
+#define IRQ_USBH        NUC93X_IRQ(6)
+#define IRQ_APU         NUC93X_IRQ(7)
+#define IRQ_VPOST       NUC93X_IRQ(8)
+#define IRQ_ADC         NUC93X_IRQ(9)
+#define IRQ_UART0       NUC93X_IRQ(10)
+#define IRQ_TIMER0      NUC93X_IRQ(11)
+#define IRQ_GPU0        NUC93X_IRQ(12)
+#define IRQ_GPU1        NUC93X_IRQ(13)
+#define IRQ_GPU2        NUC93X_IRQ(14)
+#define IRQ_GPU3        NUC93X_IRQ(15)
+#define IRQ_GPU4        NUC93X_IRQ(16)
+#define IRQ_VIN         NUC93X_IRQ(17)
+#define IRQ_USBD        NUC93X_IRQ(18)
+#define IRQ_VRAMLD      NUC93X_IRQ(19)
+#define IRQ_GDMA0       NUC93X_IRQ(20)
+#define IRQ_GDMA1       NUC93X_IRQ(21)
+#define IRQ_SDIO        NUC93X_IRQ(22)
+#define IRQ_FMI         NUC93X_IRQ(22)
+#define IRQ_JPEG        NUC93X_IRQ(23)
+#define IRQ_SPI0        NUC93X_IRQ(24)
+#define IRQ_SPI1        NUC93X_IRQ(25)
+#define IRQ_RTC         NUC93X_IRQ(26)
+#define IRQ_PWM0        NUC93X_IRQ(27)
+#define IRQ_PWM1        NUC93X_IRQ(28)
+#define IRQ_PWM2        NUC93X_IRQ(29)
+#define IRQ_PWM3        NUC93X_IRQ(30)
+#define IRQ_I2SAC97     NUC93X_IRQ(31)
+#define IRQ_CAP0        IRQ_PWM0
+#define IRQ_CAP1        IRQ_PWM1
+#define IRQ_CAP2        IRQ_PWM2
+#define IRQ_CAP3        IRQ_PWM3
+#define NR_IRQS         (IRQ_I2SAC97 + 1)
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/map.h b/arch/arm/mach-nuc93x/include/mach/map.h
new file mode 100644
index 000000000000..fd0b5e89f0e7
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/map.h
@@ -0,0 +1,139 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/map.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+#define MAP_OFFSET      (0xfff00000)
+#define CLK_OFFSET      (0x10)
+
+#ifndef __ASSEMBLY__
+#define NUC93X_ADDR(x)  ((void __iomem *)(0xF0000000 + ((x)&(~MAP_OFFSET))))
+#else
+#define NUC93X_ADDR(x)  (0xF0000000 + ((x)&(~MAP_OFFSET)))
+#endif
+
+ /*
+  * nuc932 hardware register definition
+  */
+
+#define NUC93X_PA_IRQ           (0xFFF83000)
+#define NUC93X_PA_GCR           (0xFFF00000)
+#define NUC93X_PA_EBI           (0xFFF01000)
+#define NUC93X_PA_UART          (0xFFF80000)
+#define NUC93X_PA_TIMER         (0xFFF81000)
+#define NUC93X_PA_GPIO          (0xFFF84000)
+#define NUC93X_PA_GDMA          (0xFFF03000)
+#define NUC93X_PA_USBHOST       (0xFFF0d000)
+#define NUC93X_PA_I2C           (0xFFF89000)
+#define NUC93X_PA_LCD           (0xFFF06000)
+#define NUC93X_PA_GE            (0xFFF05000)
+#define NUC93X_PA_ADC           (0xFFF85000)
+#define NUC93X_PA_RTC           (0xFFF87000)
+#define NUC93X_PA_PWM           (0xFFF82000)
+#define NUC93X_PA_ACTL          (0xFFF0a000)
+#define NUC93X_PA_USBDEV        (0xFFF0C000)
+#define NUC93X_PA_JEPEG         (0xFFF0e000)
+#define NUC93X_PA_CACHE_T       (0xFFF60000)
+#define NUC93X_PA_VRAM          (0xFFF0b000)
+#define NUC93X_PA_DMAC          (0xFFF09000)
+#define NUC93X_PA_I2SM          (0xFFF08000)
+#define NUC93X_PA_CACHE         (0xFFF02000)
+#define NUC93X_PA_GPU           (0xFFF04000)
+#define NUC93X_PA_VIDEOIN       (0xFFF07000)
+#define NUC93X_PA_SPI0          (0xFFF86000)
+#define NUC93X_PA_SPI1          (0xFFF88000)
+
+ /*
+  * nuc932 virtual address mapping.
+  * interrupt controller is the first thing we put in, to make
+  * the assembly code for the irq detection easier
+  */
+
+#define NUC93X_VA_IRQ           NUC93X_ADDR(0x00000000)
+#define NUC93X_SZ_IRQ           SZ_4K
+
+#define NUC93X_VA_GCR           NUC93X_ADDR(NUC93X_PA_IRQ)
+#define NUC93X_VA_CLKPWR        (NUC93X_VA_GCR+CLK_OFFSET)
+#define NUC93X_SZ_GCR           SZ_4K
+
+/* EBI management */
+
+#define NUC93X_VA_EBI           NUC93X_ADDR(NUC93X_PA_EBI)
+#define NUC93X_SZ_EBI           SZ_4K
+
+/* UARTs */
+
+#define NUC93X_VA_UART          NUC93X_ADDR(NUC93X_PA_UART)
+#define NUC93X_SZ_UART          SZ_4K
+
+/* Timers */
+
+#define NUC93X_VA_TIMER NUC93X_ADDR(NUC93X_PA_TIMER)
+#define NUC93X_SZ_TIMER SZ_4K
+
+/* GPIO ports */
+
+#define NUC93X_VA_GPIO          NUC93X_ADDR(NUC93X_PA_GPIO)
+#define NUC93X_SZ_GPIO          SZ_4K
+
+/* GDMA control */
+
+#define NUC93X_VA_GDMA          NUC93X_ADDR(NUC93X_PA_GDMA)
+#define NUC93X_SZ_GDMA          SZ_4K
+
+/* I2C hardware controller */
+
+#define NUC93X_VA_I2C           NUC93X_ADDR(NUC93X_PA_I2C)
+#define NUC93X_SZ_I2C           SZ_4K
+
+/* LCD controller*/
+
+#define NUC93X_VA_LCD           NUC93X_ADDR(NUC93X_PA_LCD)
+#define NUC93X_SZ_LCD           SZ_4K
+
+/* 2D controller*/
+
+#define NUC93X_VA_GE            NUC93X_ADDR(NUC93X_PA_GE)
+#define NUC93X_SZ_GE            SZ_4K
+
+/* ADC */
+
+#define NUC93X_VA_ADC           NUC93X_ADDR(NUC93X_PA_ADC)
+#define NUC93X_SZ_ADC           SZ_4K
+
+/* RTC */
+
+#define NUC93X_VA_RTC           NUC93X_ADDR(NUC93X_PA_RTC)
+#define NUC93X_SZ_RTC           SZ_4K
+
+/* Pulse Width Modulation(PWM) Registers */
+
+#define NUC93X_VA_PWM           NUC93X_ADDR(NUC93X_PA_PWM)
+#define NUC93X_SZ_PWM           SZ_4K
+
+/* Audio Controller controller */
+
+#define NUC93X_VA_ACTL          NUC93X_ADDR(NUC93X_PA_ACTL)
+#define NUC93X_SZ_ACTL          SZ_4K
+
+/* USB Device port */
+
+#define NUC93X_VA_USBDEV        NUC93X_ADDR(NUC93X_PA_USBDEV)
+#define NUC93X_SZ_USBDEV        SZ_4K
+
+/* USB host controller*/
+#define NUC93X_VA_USBHOST       NUC93X_ADDR(NUC93X_PA_USBHOST)
+#define NUC93X_SZ_USBHOST       SZ_4K
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h
new file mode 100644
index 000000000000..323ab0db3f7d
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/memory.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/memory.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-clock.h b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
new file mode 100644
index 000000000000..5cb2954fbec2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-clock.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H
+
+/* Clock Control Registers  */
+#define CLK_BA          NUC93X_VA_CLKPWR
+#define REG_CLKEN       (CLK_BA + 0x00)
+#define REG_CLKSEL      (CLK_BA + 0x04)
+#define REG_CLKDIV      (CLK_BA + 0x08)
+#define REG_PLLCON0     (CLK_BA + 0x0C)
+#define REG_PLLCON1     (CLK_BA + 0x10)
+#define REG_PMCON       (CLK_BA + 0x14)
+#define REG_IRQWAKECON  (CLK_BA + 0x18)
+#define REG_IRQWAKEFLAG (CLK_BA + 0x1C)
+#define REG_IPSRST      (CLK_BA + 0x20)
+#define REG_CLKEN1      (CLK_BA + 0x24)
+#define REG_CLKDIV1     (CLK_BA + 0x28)
+
+/* Define PLL freq setting */
+#define PLL_DISABLE             0x12B63
+#define PLL_66MHZ               0x2B63
+#define PLL_100MHZ              0x4F64
+#define PLL_120MHZ              0x4F63
+#define PLL_166MHZ              0x4124
+#define PLL_200MHZ              0x4F24
+
+/* Define AHB:CPUFREQ ratio */
+#define AHB_CPUCLK_1_1          0x00
+#define AHB_CPUCLK_1_2          0x01
+#define AHB_CPUCLK_1_4          0x02
+#define AHB_CPUCLK_1_8          0x03
+
+/* Define APB:AHB ratio */
+#define APB_AHB_1_2             0x01
+#define APB_AHB_1_4             0x02
+#define APB_AHB_1_8             0x03
+
+/* Define clock skew */
+#define DEFAULTSKEW             0x48
+
+#endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-ebi.h b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
new file mode 100644
index 000000000000..3c72550e28e4
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-ebi.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-ebi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_EBI_H
+#define __ASM_ARCH_REGS_EBI_H
+
+/* EBI Control Registers */
+
+#define EBI_BA          NUC93X_VA_EBI
+#define REG_EBICON      (EBI_BA + 0x00)
+#define REG_ROMCON      (EBI_BA + 0x04)
+#define REG_SDCONF0     (EBI_BA + 0x08)
+#define REG_SDCONF1     (EBI_BA + 0x0C)
+#define REG_SDTIME0     (EBI_BA + 0x10)
+#define REG_SDTIME1     (EBI_BA + 0x14)
+#define REG_EXT0CON     (EBI_BA + 0x18)
+#define REG_EXT1CON     (EBI_BA + 0x1C)
+#define REG_EXT2CON     (EBI_BA + 0x20)
+#define REG_EXT3CON     (EBI_BA + 0x24)
+#define REG_EXT4CON     (EBI_BA + 0x28)
+#define REG_CKSKEW      (EBI_BA + 0x2C)
+
+#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-irq.h b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
new file mode 100644
index 000000000000..23021592de51
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-irq.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H
+
+/* Advance Interrupt Controller (AIC) Registers */
+
+#define AIC_BA                  NUC93X_VA_IRQ
+
+#define REG_AIC_IRQSC           (AIC_BA+0x80)
+#define REG_AIC_GEN             (AIC_BA+0x84)
+#define REG_AIC_GASR            (AIC_BA+0x88)
+#define REG_AIC_GSCR            (AIC_BA+0x8C)
+#define REG_AIC_IRSR            (AIC_BA+0x100)
+#define REG_AIC_IASR            (AIC_BA+0x104)
+#define REG_AIC_ISR             (AIC_BA+0x108)
+#define REG_AIC_IPER            (AIC_BA+0x10C)
+#define REG_AIC_ISNR            (AIC_BA+0x110)
+#define REG_AIC_IMR             (AIC_BA+0x114)
+#define REG_AIC_OISR            (AIC_BA+0x118)
+#define REG_AIC_MECR            (AIC_BA+0x120)
+#define REG_AIC_MDCR            (AIC_BA+0x124)
+#define REG_AIC_SSCR            (AIC_BA+0x128)
+#define REG_AIC_SCCR            (AIC_BA+0x12C)
+#define REG_AIC_EOSCR           (AIC_BA+0x130)
+#define AIC_IPER                (0x10C)
+#define AIC_ISNR                (0x110)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-serial.h b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
new file mode 100644
index 000000000000..767a047a8bc2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-serial.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-serial.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define UART0_BA        NUC93X_VA_UART
+#define UART1_BA        (NUC93X_VA_UART+0x100)
+
+#define UART0_PA        NUC93X_PA_UART
+#define UART1_PA        (NUC93X_PA_UART+0x100)
+
+
+#ifndef __ASSEMBLY__
+
+struct nuc93x_uart_clksrc {
+        const char      *name;
+        unsigned int    divisor;
+        unsigned int    min_baud;
+        unsigned int    max_baud;
+};
+
+struct nuc93x_uartcfg {
+        unsigned char   hwport;
+        unsigned char   unused;
+        unsigned short  flags;
+        unsigned long   uart_flags;
+
+        unsigned long   ucon;
+        unsigned long   ulcon;
+        unsigned long   ufcon;
+
+        struct nuc93x_uart_clksrc *clocks;
+        unsigned int    clocks_size;
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff --git a/arch/arm/mach-nuc93x/include/mach/regs-timer.h b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
new file mode 100644
index 000000000000..394be9614d36
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/regs-timer.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/regs-timer.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H
+
+/* Timer Registers */
+
+#define TMR_BA                  NUC93X_VA_TIMER
+#define REG_TCSR0               (TMR_BA+0x00)
+#define REG_TICR0               (TMR_BA+0x08)
+#define REG_TDR0                (TMR_BA+0x10)
+#define REG_TISR                (TMR_BA+0x18)
+#define REG_WTCR                (TMR_BA+0x1C)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/system.h b/arch/arm/mach-nuc93x/include/mach/system.h
new file mode 100644
index 000000000000..d26bd9a52844
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/system.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/machnuc93x/include/mach/system.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/system.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <asm/proc-fns.h>
+
+static void arch_idle(void)
+{
+}
+
+static void arch_reset(char mode, const char *cmd)
+{
+        cpu_reset(0);
+}
+
diff --git a/arch/arm/mach-nuc93x/include/mach/timex.h b/arch/arm/mach-nuc93x/include/mach/timex.h
new file mode 100644
index 000000000000..0c719cc91aa9
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/timex.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/timex.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE Now, I don't use it. */
+
+#define CLOCK_TICK_RATE 27000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
new file mode 100644
index 000000000000..73082cd61e84
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -0,0 +1,50 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/uncompress.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+/* Defines for UART registers */
+
+#include <mach/regs-serial.h>
+#include <mach/map.h>
+#include <linux/serial_reg.h>
+
+#define arch_decomp_wdog()
+
+#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
+static u32 * uart_base = (u32 *)UART0_PA;
+
+static void putc(int ch)
+{
+        /* Check THRE and TEMT bits before we transmit the character.
+         */
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
+                barrier();
+
+        *uart_base = ch;
+}
+
+static inline void flush(void)
+{
+}
+
+static void arch_decomp_setup(void)
+{
+}
+
+#endif/* __ASM_NUC93X_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
new file mode 100644
index 000000000000..98a21b81dec0
--- /dev/null
+++ b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-nuc93x/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ * All rights reserved.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END       (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
new file mode 100644
index 000000000000..a7a88ea4ec31
--- /dev/null
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-nuc93x/irq.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/ptrace.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-irq.h>
+
+static void nuc93x_irq_mask(unsigned int irq)
+{
+        __raw_writel(1 << irq, REG_AIC_MDCR);
+}
+
+/*
+ * By the w90p910 spec,any irq,only write 1
+ * to REG_AIC_EOSCR for ACK
+ */
+
+static void nuc93x_irq_ack(unsigned int irq)
+{
+        __raw_writel(0x01, REG_AIC_EOSCR);
+}
+
+static void nuc93x_irq_unmask(unsigned int irq)
+{
+        __raw_writel(1 << irq, REG_AIC_MECR);
+
+}
+
+static struct irq_chip nuc93x_irq_chip = {
+        .ack       = nuc93x_irq_ack,
+        .mask      = nuc93x_irq_mask,
+        .unmask    = nuc93x_irq_unmask,
+};
+
+void __init nuc93x_init_irq(void)
+{
+        int irqno;
+
+        __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
+
+        for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
+                set_irq_chip(irqno, &nuc93x_irq_chip);
+                set_irq_handler(irqno, handle_level_irq);
+                set_irq_flags(irqno, IRQF_VALID);
+        }
+}
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
new file mode 100644
index 000000000000..9f79266f08e2
--- /dev/null
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -0,0 +1,45 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+
+#include "nuc932.h"
+
+static void __init nuc932evb_map_io(void)
+{
+        nuc932_map_io();
+        nuc932_init_clocks();
+        nuc932_init_uartclk();
+}
+
+static void __init nuc932evb_init(void)
+{
+        nuc932_board_init();
+}
+
+MACHINE_START(NUC932EVB, "NUC932EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = NUC93X_PA_UART,
+        .io_pg_offst    = (((u32)NUC93X_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc932evb_map_io,
+        .init_irq       = nuc93x_init_irq,
+        .init_machine   = nuc932evb_init,
+        .timer          = &nuc93x_timer,
+MACHINE_END
diff --git a/arch/arm/mach-nuc93x/nuc932.c b/arch/arm/mach-nuc93x/nuc932.c
new file mode 100644
index 000000000000..3966ead686fc
--- /dev/null
+++ b/arch/arm/mach-nuc93x/nuc932.c
@@ -0,0 +1,65 @@
+/*
+ * linux/arch/arm/mach-nuc93x/nuc932.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC932 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+
+#include "cpu.h"
+#include "clock.h"
+
+/* define specific CPU platform device */
+
+static struct platform_device *nuc932_dev[] __initdata = {
+};
+
+/* define specific CPU platform io map */
+
+static struct map_desc nuc932evb_iodesc[] __initdata = {
+};
+
+/*Init NUC932 evb io*/
+
+void __init nuc932_map_io(void)
+{
+        nuc93x_map_io(nuc932evb_iodesc, ARRAY_SIZE(nuc932evb_iodesc));
+}
+
+/*Init NUC932 clock*/
+
+void __init nuc932_init_clocks(void)
+{
+        nuc93x_init_clocks();
+}
+
+/*enable NUC932 uart clock*/
+
+void __init nuc932_init_uartclk(void)
+{
+        struct clk *ck_uart = clk_get(NULL, "uart");
+        BUG_ON(IS_ERR(ck_uart));
+
+        clk_enable(ck_uart);
+}
+
+/*Init NUC932 board info*/
+
+void __init nuc932_board_init(void)
+{
+        nuc93x_board_init(nuc932_dev, ARRAY_SIZE(nuc932_dev));
+}
diff --git a/arch/arm/mach-nuc93x/nuc932.h b/arch/arm/mach-nuc93x/nuc932.h
new file mode 100644
index 000000000000..9a66edd5338f
--- /dev/null
+++ b/arch/arm/mach-nuc93x/nuc932.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-nuc93x/nuc932.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC93x CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct map_desc;
+struct sys_timer;
+
+/* core initialisation functions */
+
+extern void nuc93x_init_irq(void);
+extern struct sys_timer nuc93x_timer;
+
+/* extern file from nuc932.c */
+
+extern void nuc932_board_init(void);
+extern void nuc932_init_clocks(void);
+extern void nuc932_map_io(void);
+extern void nuc932_init_uartclk(void);
diff --git a/arch/arm/mach-nuc93x/time.c b/arch/arm/mach-nuc93x/time.c
new file mode 100644
index 000000000000..2f90f9dc6e30
--- /dev/null
+++ b/arch/arm/mach-nuc93x/time.c
@@ -0,0 +1,100 @@
+/*
+ * linux/arch/arm/mach-nuc93x/time.c
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+
+#include <mach/system.h>
+#include <mach/map.h>
+#include <mach/regs-timer.h>
+
+#define RESETINT        0x01
+#define PERIOD          (0x01 << 27)
+#define ONESHOT         (0x00 << 27)
+#define COUNTEN         (0x01 << 30)
+#define INTEN           (0x01 << 29)
+
+#define TICKS_PER_SEC   100
+#define PRESCALE        0x63 /* Divider = prescale + 1 */
+
+unsigned int timer0_load;
+
+static unsigned long nuc93x_gettimeoffset(void)
+{
+        return 0;
+}
+
+/*IRQ handler for the timer*/
+
+static irqreturn_t nuc93x_timer_interrupt(int irq, void *dev_id)
+{
+        timer_tick();
+        __raw_writel(0x01, REG_TISR); /* clear TIF0 */
+        return IRQ_HANDLED;
+}
+
+static struct irqaction nuc93x_timer_irq = {
+        .name           = "nuc93x Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = nuc93x_timer_interrupt,
+};
+
+/*Set up timer reg.*/
+
+static void nuc93x_timer_setup(void)
+{
+        struct clk *ck_ext = clk_get(NULL, "ext");
+        struct clk *ck_timer = clk_get(NULL, "timer");
+        unsigned int rate, val = 0;
+
+        BUG_ON(IS_ERR(ck_ext) || IS_ERR(ck_timer));
+
+        clk_enable(ck_timer);
+        rate = clk_get_rate(ck_ext);
+        clk_put(ck_ext);
+        rate = rate / (PRESCALE + 0x01);
+
+         /* set a known state */
+        __raw_writel(0x00, REG_TCSR0);
+        __raw_writel(RESETINT, REG_TISR);
+
+        timer0_load = (rate / TICKS_PER_SEC);
+        __raw_writel(timer0_load, REG_TICR0);
+
+        val |= (PERIOD | COUNTEN | INTEN | PRESCALE);;
+        __raw_writel(val, REG_TCSR0);
+
+}
+
+static void __init nuc93x_timer_init(void)
+{
+        nuc93x_timer_setup();
+        setup_irq(IRQ_TIMER0, &nuc93x_timer_irq);
+}
+
+struct sys_timer nuc93x_timer = {
+        .init           = nuc93x_timer_init,
+        .offset         = nuc93x_gettimeoffset,
+        .resume         = nuc93x_timer_setup
+};
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index aedb746fc33c..8c74cab2fa8b 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0xff000000        @ physical base address
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 0c6be6b4a7e2..8ba8fb5b2514 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,6 +28,7 @@
 #include <plat/control.h>
 #include <plat/timer-gp.h>
 #include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
 
 static struct platform_device sdp4430_lcd_device = {
         .name           = "sdp4430_lcd",
@@ -50,6 +51,59 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
         { OMAP_TAG_LCD,         &sdp4430_lcd_config },
 };
 
+#ifdef CONFIG_CACHE_L2X0
+noinline void omap_smc1(u32 fn, u32 arg)
+{
+        register u32 r12 asm("r12") = fn;
+        register u32 r0 asm("r0") = arg;
+
+        /* This is common routine cache secure monitor API used to
+         * modify the PL310 secure registers.
+         * r0 contains the value to be modified and "r12" contains
+         * the monitor API number. It uses few CPU registers
+         * internally and hence they need be backed up including
+         * link register "lr".
+         * Explicitly save r11 and r12 the compiler generated code
+         * won't save it.
+         */
+        asm volatile(
+                "stmfd r13!, {r11,r12}\n"
+                "dsb\n"
+                "smc\n"
+                "ldmfd r13!, {r11,r12}\n"
+                : "+r" (r0), "+r" (r12)
+                :
+                : "r4", "r5", "r10", "lr", "cc");
+}
+EXPORT_SYMBOL(omap_smc1);
+
+static int __init omap_l2_cache_init(void)
+{
+        void __iomem *l2cache_base;
+
+        /* To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!cpu_is_omap44xx())
+                return -ENODEV;
+
+        /* Static mapping, never released */
+        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
+        BUG_ON(!l2cache_base);
+
+        /* Enable PL310 L2 Cache controller */
+        omap_smc1(0x102, 0x1);
+
+        /* 32KB way size, 16-way associativity,
+        * parity disabled
+        */
+        l2x0_init(l2cache_base, 0x0e050000, 0xc0000fff);
+
+        return 0;
+}
+early_initcall(omap_l2_cache_init);
+#endif
+
 static void __init gic_init_irq(void)
 {
         void __iomem *base;
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index e9f255df9163..86979d7bd871 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
 #ifdef  CONFIG_ARCH_OMAP2
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S
index c7f808bfe272..91e0e39bb23f 100644
--- a/arch/arm/mach-orion5x/include/mach/debug-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
 
 #include <mach/orion5x.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                                 @ MMU enabled?
         ldreq   \rx, =ORION5X_REGS_PHYS_BASE
diff --git a/arch/arm/mach-orion5x/include/mach/vmalloc.h b/arch/arm/mach-orion5x/include/mach/vmalloc.h
index 7147a297e97f..06b50aeff7b9 100644
--- a/arch/arm/mach-orion5x/include/mach/vmalloc.h
+++ b/arch/arm/mach-orion5x/include/mach/vmalloc.h
@@ -2,4 +2,4 @@
  * arch/arm/mach-orion5x/include/mach/vmalloc.h
  */
 
-#define VMALLOC_END       0xfd800000
+#define VMALLOC_END       0xfd800000UL
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
index 898c0e88acbc..9d1975fa4d9f 100644
--- a/arch/arm/mach-pnx4008/clock.c
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -22,8 +22,9 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 
-#include <mach/hardware.h>
+#include <asm/clkdev.h>
 
+#include <mach/hardware.h>
 #include <mach/clock.h>
 #include "clock.h"
 
@@ -56,18 +57,19 @@ static void propagate_rate(struct clk *clk)
         }
 }
 
-static inline void clk_reg_disable(struct clk *clk)
+static void clk_reg_disable(struct clk *clk)
 {
         if (clk->enable_reg)
                 __raw_writel(__raw_readl(clk->enable_reg) &
                              ~(1 << clk->enable_shift), clk->enable_reg);
 }
 
-static inline void clk_reg_enable(struct clk *clk)
+static int clk_reg_enable(struct clk *clk)
 {
         if (clk->enable_reg)
                 __raw_writel(__raw_readl(clk->enable_reg) |
                              (1 << clk->enable_shift), clk->enable_reg);
+        return 0;
 }
 
 static inline void clk_reg_disable1(struct clk *clk)
@@ -636,31 +638,34 @@ static struct clk flash_ck = {
 static struct clk i2c0_ck = {
         .name = "i2c0_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 0,
         .enable_reg = I2CCLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk i2c1_ck = {
         .name = "i2c1_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 1,
         .enable_reg = I2CCLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk i2c2_ck = {
         .name = "i2c2_ck",
         .parent = &per_ck,
-        .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
+        .flags = NEEDS_INITIALIZATION | FIXED_RATE,
         .enable_shift = 2,
         .enable_reg = USB_OTG_CLKCTRL_REG,
+        .rate = 13000000,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 static struct clk spi0_ck = {
@@ -738,16 +743,16 @@ static struct clk wdt_ck = {
         .name = "wdt_ck",
         .parent = &per_ck,
         .flags = NEEDS_INITIALIZATION,
-        .round_rate = &on_off_round_rate,
-        .set_rate = &on_off_set_rate,
         .enable_shift = 0,
         .enable_reg = TIMCLKCTRL_REG,
+        .enable = clk_reg_enable,
+        .disable = clk_reg_disable,
 };
 
 /* These clocks are visible outside this module
  * and can be initialized
  */
-static struct clk *onchip_clks[] = {
+static struct clk *onchip_clks[] __initdata = {
         &ck_13MHz,
         &ck_pll1,
         &ck_pll4,
@@ -777,49 +782,74 @@ static struct clk *onchip_clks[] = {
         &wdt_ck,
 };
 
-static int local_clk_enable(struct clk *clk)
-{
-        int ret = 0;
-
-        if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
-            && clk->user_rate)
-                ret = clk->set_rate(clk, clk->user_rate);
-        return ret;
-}
+static struct clk_lookup onchip_clkreg[] = {
+        { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
+        { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
+        { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
+        { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
+        { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
+        { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
+        { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
+        { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
+        { .clk = &dma_ck,       .con_id = "dma_ck"      },
+        { .clk = &flash_ck,     .con_id = "flash_ck"    },
+        { .clk = &dum_ck,       .con_id = "dum_ck"      },
+        { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
+        { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
+        { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
+        { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
+        { .clk = &ms_ck,        .con_id = "ms_ck"       },
+        { .clk = &touch_ck,     .con_id = "touch_ck"    },
+        { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
+        { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
+        { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
+        { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
+        { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
+        { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
+        { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
+        { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
+        { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
+        { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
+};
 
 static void local_clk_disable(struct clk *clk)
 {
-        if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
-                clk->set_rate(clk, 0);
-}
+        if (WARN_ON(clk->usecount == 0))
+                return;
 
-static void local_clk_unuse(struct clk *clk)
-{
-        if (clk->usecount > 0 && !(--clk->usecount)) {
-                local_clk_disable(clk);
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
+                        clk->set_rate(clk, 0);
                 if (clk->parent)
-                        local_clk_unuse(clk->parent);
+                        local_clk_disable(clk->parent);
         }
 }
 
-static int local_clk_use(struct clk *clk)
+static int local_clk_enable(struct clk *clk)
 {
         int ret = 0;
-        if (clk->usecount++ == 0) {
-                if (clk->parent)
-                        ret = local_clk_use(clk->parent);
 
-                if (ret != 0) {
-                        clk->usecount--;
-                        goto out;
+        if (clk->usecount == 0) {
+                if (clk->parent) {
+                        ret = local_clk_enable(clk->parent);
+                        if (ret != 0)
+                                goto out;
                 }
 
-                ret = local_clk_enable(clk);
+                if (clk->enable)
+                        ret = clk->enable(clk);
+                else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
+                            && clk->user_rate)
+                        ret = clk->set_rate(clk, clk->user_rate);
 
                 if (ret != 0 && clk->parent) {
-                        local_clk_unuse(clk->parent);
-                        clk->usecount--;
+                        local_clk_disable(clk->parent);
+                        goto out;
                 }
+
+                clk->usecount++;
         }
 out:
         return ret;
@@ -866,35 +896,6 @@ out:
 
 EXPORT_SYMBOL(clk_set_rate);
 
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *clk = ERR_PTR(-ENOENT);
-        struct clk **clkp;
-
-        clock_lock();
-        for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
-             clkp++) {
-                if (strcmp(id, (*clkp)->name) == 0
-                    && try_module_get((*clkp)->owner)) {
-                        clk = (*clkp);
-                        break;
-                }
-        }
-        clock_unlock();
-
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
-        clock_lock();
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-        clock_unlock();
-}
-EXPORT_SYMBOL(clk_put);
-
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long ret;
@@ -907,10 +908,10 @@ EXPORT_SYMBOL(clk_get_rate);
 
 int clk_enable(struct clk *clk)
 {
-        int ret = 0;
+        int ret;
 
         clock_lock();
-        ret = local_clk_use(clk);
+        ret = local_clk_enable(clk);
         clock_unlock();
         return ret;
 }
@@ -920,7 +921,7 @@ EXPORT_SYMBOL(clk_enable);
 void clk_disable(struct clk *clk)
 {
         clock_lock();
-        local_clk_unuse(clk);
+        local_clk_disable(clk);
         clock_unlock();
 }
 
@@ -967,18 +968,24 @@ static int __init clk_init(void)
 
         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
              clkp++) {
-                if (((*clkp)->flags & NEEDS_INITIALIZATION)
-                    && ((*clkp)->set_rate)) {
-                        (*clkp)->user_rate = (*clkp)->rate;
-                        local_set_rate((*clkp), (*clkp)->user_rate);
-                        if ((*clkp)->set_parent)
-                                (*clkp)->set_parent((*clkp), (*clkp)->parent);
+                struct clk *clk = *clkp;
+                if (clk->flags & NEEDS_INITIALIZATION) {
+                        if (clk->set_rate) {
+                                clk->user_rate = clk->rate;
+                                local_set_rate(clk, clk->user_rate);
+                                if (clk->set_parent)
+                                        clk->set_parent(clk, clk->parent);
+                        }
+                        if (clk->enable && clk->usecount)
+                                clk->enable(clk);
+                        if (clk->disable && !clk->usecount)
+                                clk->disable(clk);
                 }
                 pr_debug("%s: clock %s, rate %ld\n",
-                        __func__, (*clkp)->name, (*clkp)->rate);
+                        __func__, clk->name, clk->rate);
         }
 
-        local_clk_use(&ck_pll4);
+        local_clk_enable(&ck_pll4);
 
         /* if ck_13MHz is not used, disable it. */
         if (ck_13MHz.usecount == 0)
@@ -987,6 +994,8 @@ static int __init clk_init(void)
         /* Disable autoclocking */
         __raw_writeb(0xff, AUTOCLK_CTRL);
 
+        clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
+
         return 0;
 }
 
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
index cd58f372cfd0..39720d6c0d01 100644
--- a/arch/arm/mach-pnx4008/clock.h
+++ b/arch/arm/mach-pnx4008/clock.h
@@ -14,8 +14,6 @@
 #define __ARCH_ARM_PNX4008_CLOCK_H__
 
 struct clk {
-        struct list_head node;
-        struct module *owner;
         const char *name;
         struct clk *parent;
         struct clk *propagate_next;
@@ -29,9 +27,11 @@ struct clk {
         u8 enable_shift1;
         u32 enable_reg1;
         u32 parent_switch_reg;
-         u32(*round_rate) (struct clk *, u32);
+        u32(*round_rate) (struct clk *, u32);
         int (*set_rate) (struct clk *, u32);
         int (*set_parent) (struct clk * clk, struct clk * parent);
+        int (*enable)(struct clk *);
+        void (*disable)(struct clk *);
 };
 
 /* Flags */
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
index f3fea29c00d3..8103f9644e2d 100644
--- a/arch/arm/mach-pnx4008/i2c.c
+++ b/arch/arm/mach-pnx4008/i2c.c
@@ -18,120 +18,24 @@
 #include <mach/irqs.h>
 #include <mach/i2c.h>
 
-static int set_clock_run(struct platform_device *pdev)
-{
-        struct clk *clk;
-        char name[10];
-        int retval = 0;
-
-        snprintf(name, 10, "i2c%d_ck", pdev->id);
-        clk = clk_get(&pdev->dev, name);
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, 1);
-                clk_put(clk);
-        } else
-                retval = -ENOENT;
-
-        return retval;
-}
-
-static int set_clock_stop(struct platform_device *pdev)
-{
-        struct clk *clk;
-        char name[10];
-        int retval = 0;
-
-        snprintf(name, 10, "i2c%d_ck", pdev->id);
-        clk = clk_get(&pdev->dev, name);
-        if (!IS_ERR(clk)) {
-                clk_set_rate(clk, 0);
-                clk_put(clk);
-        } else
-                retval = -ENOENT;
-
-        return retval;
-}
-
-static int i2c_pnx_suspend(struct platform_device *pdev, pm_message_t state)
-{
-        int retval = 0;
-#ifdef CONFIG_PM
-        retval = set_clock_run(pdev);
-#endif
-        return retval;
-}
-
-static int i2c_pnx_resume(struct platform_device *pdev)
-{
-        int retval = 0;
-#ifdef CONFIG_PM
-        retval = set_clock_run(pdev);
-#endif
-        return retval;
-}
-
-static u32 calculate_input_freq(struct platform_device *pdev)
-{
-        return HCLK_MHZ;
-}
-
-
-static struct i2c_pnx_algo_data pnx_algo_data0 = {
+static struct i2c_pnx_data i2c0_data = {
+        .name = I2C_CHIP_NAME "0",
         .base = PNX4008_I2C1_BASE,
         .irq = I2C_1_INT,
 };
 
-static struct i2c_pnx_algo_data pnx_algo_data1 = {
+static struct i2c_pnx_data i2c1_data = {
+        .name = I2C_CHIP_NAME "1",
         .base = PNX4008_I2C2_BASE,
         .irq = I2C_2_INT,
 };
 
-static struct i2c_pnx_algo_data pnx_algo_data2 = {
+static struct i2c_pnx_data i2c2_data = {
+        .name = "USB-I2C",
         .base = (PNX4008_USB_CONFIG_BASE + 0x300),
         .irq = USB_I2C_INT,
 };
 
-static struct i2c_adapter pnx_adapter0 = {
-        .name = I2C_CHIP_NAME "0",
-        .algo_data = &pnx_algo_data0,
-};
-static struct i2c_adapter pnx_adapter1 = {
-        .name = I2C_CHIP_NAME "1",
-        .algo_data = &pnx_algo_data1,
-};
-
-static struct i2c_adapter pnx_adapter2 = {
-        .name = "USB-I2C",
-        .algo_data = &pnx_algo_data2,
-};
-
-static struct i2c_pnx_data i2c0_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter0,
-};
-
-static struct i2c_pnx_data i2c1_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter1,
-};
-
-static struct i2c_pnx_data i2c2_data = {
-        .suspend = i2c_pnx_suspend,
-        .resume = i2c_pnx_resume,
-        .calculate_input_freq = calculate_input_freq,
-        .set_clock_run = set_clock_run,
-        .set_clock_stop = set_clock_stop,
-        .adapter = &pnx_adapter2,
-};
-
 static struct platform_device i2c0_device = {
         .name = "pnx-i2c",
         .id = 0,
diff --git a/arch/arm/mach-pnx4008/include/mach/clkdev.h b/arch/arm/mach-pnx4008/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
index 6d1407f319f8..6ca8bd30bf46 100644
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 mov     \rx, #0x00090000
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
index 5ff0196c0f16..b383c7de7ab4 100644
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ b/arch/arm/mach-pnx4008/include/mach/timex.h
@@ -14,60 +14,6 @@
 #ifndef __PNX4008_TIMEX_H
 #define __PNX4008_TIMEX_H
 
-#include <linux/io.h>
-#include <mach/hardware.h>
-
 #define CLOCK_TICK_RATE         1000000
 
-#define TICKS2USECS(x)  (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT        1
-#define RESET_COUNT0   (1<<1)
-#define STOP_COUNT0    (1<<2)
-#define MR1_INT        (1<<3)
-#define RESET_COUNT1   (1<<4)
-#define STOP_COUNT1    (1<<5)
-#define MR2_INT        (1<<6)
-#define RESET_COUNT2   (1<<7)
-#define STOP_COUNT2    (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB     1
-#define RESET_COUNT    (1<<1)
-#define DEBUG_EN       (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT     1
-#define MATCH1_INT     (1<<1)
-#define MATCH2_INT     (1<<2)
-#define RTC_TICK0      (1<<4)
-#define RTC_TICK1      (1<<5)
-
 #endif
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
index b3d8d53e32ef..1f0585329be4 100644
--- a/arch/arm/mach-pnx4008/pm.c
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -21,6 +21,8 @@
 #include <linux/io.h>
 
 #include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
 #include <mach/pm.h>
 #include <mach/clock.h>
 
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index fc0ba183fe12..0c8aad4bb0dc 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -30,6 +30,8 @@
 #include <asm/mach/time.h>
 #include <asm/errno.h>
 
+#include "time.h"
+
 /*! Note: all timers are UPCOUNTING */
 
 /*!
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
new file mode 100644
index 000000000000..75e88c570aa7
--- /dev/null
+++ b/arch/arm/mach-pnx4008/time.h
@@ -0,0 +1,70 @@
+/*
+ * arch/arm/mach-pnx4008/include/mach/timex.h
+ *
+ * PNX4008 timers header file
+ *
+ * Author: Dmitry Chigirev <source@mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef PNX_TIME_H
+#define PNX_TIME_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+
+#define TICKS2USECS(x)  (x)
+
+/* MilliSecond Timer - Chapter 21 Page 202 */
+
+#define MSTIM_INT     IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
+#define MSTIM_CTRL    IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
+#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
+#define MSTIM_MCTRL   IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
+#define MSTIM_MATCH0  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
+#define MSTIM_MATCH1  IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
+
+/* High Speed Timer - Chpater 22, Page 205 */
+
+#define HSTIM_INT     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
+#define HSTIM_CTRL    IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
+#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
+#define HSTIM_PMATCH  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
+#define HSTIM_PCOUNT  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
+#define HSTIM_MCTRL   IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
+#define HSTIM_MATCH0  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
+#define HSTIM_MATCH1  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
+#define HSTIM_MATCH2  IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
+#define HSTIM_CCR     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
+#define HSTIM_CR0     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
+#define HSTIM_CR1     IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
+
+/* IMPORTANT: both timers are UPCOUNTING */
+
+/* xSTIM_MCTRL bit definitions */
+#define MR0_INT        1
+#define RESET_COUNT0   (1<<1)
+#define STOP_COUNT0    (1<<2)
+#define MR1_INT        (1<<3)
+#define RESET_COUNT1   (1<<4)
+#define STOP_COUNT1    (1<<5)
+#define MR2_INT        (1<<6)
+#define RESET_COUNT2   (1<<7)
+#define STOP_COUNT2    (1<<8)
+
+/* xSTIM_CTRL bit definitions */
+#define COUNT_ENAB     1
+#define RESET_COUNT    (1<<1)
+#define DEBUG_EN       (1<<2)
+
+/* xSTIM_INT bit definitions */
+#define MATCH0_INT     1
+#define MATCH1_INT     (1<<1)
+#define MATCH2_INT     (1<<2)
+#define RTC_TICK0      (1<<4)
+#define RTC_TICK1      (1<<5)
+
+#endif
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 49ae38292310..abba0089a2ae 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -78,11 +78,3 @@ const struct clkops clk_cken_ops = {
         .enable         = clk_cken_enable,
         .disable        = clk_cken_disable,
 };
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 978a3667e90d..d8488742b807 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -67,7 +67,3 @@ extern void clk_pxa3xx_cken_enable(struct clk *);
 extern void clk_pxa3xx_cken_disable(struct clk *);
 #endif
 
-void clks_register(struct clk_lookup *clks, size_t num);
-int clk_add_alias(const char *alias, const char *alias_name, char *id,
-        struct device *dev);
-
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 91417f035069..96ed13081639 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -128,6 +128,6 @@ static struct clk_lookup eseries_clkregs[] = {
 
 void eseries_register_clks(void)
 {
-        clks_register(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
+        clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
 }
 
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
index 55d6a175ab19..01cf81393fe2 100644
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ b/arch/arm/mach-pxa/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
 
 #include "hardware.h"
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x40000000                @ physical
diff --git a/arch/arm/mach-pxa/include/mach/vmalloc.h b/arch/arm/mach-pxa/include/mach/vmalloc.h
index e90c5eeb81dd..bfecfbf5f460 100644
--- a/arch/arm/mach-pxa/include/mach/vmalloc.h
+++ b/arch/arm/mach-pxa/include/mach/vmalloc.h
@@ -8,4 +8,4 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 2c1b0b70d01d..0b9ad30bfd51 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -349,7 +349,7 @@ static int __init pxa25x_init(void)
 
                 reset_status = RCSR;
 
-                clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
+                clkdev_add_table(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 16)))
                         return ret;
@@ -370,7 +370,7 @@ static int __init pxa25x_init(void)
 
         /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
         if (cpu_is_pxa255())
-                clks_register(&pxa25x_hwuart_clkreg, 1);
+                clkdev_add(&pxa25x_hwuart_clkreg);
 
         return ret;
 }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6a0b73167e03..d783123e2d48 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -392,7 +392,7 @@ static int __init pxa27x_init(void)
 
                 reset_status = RCSR;
 
-                clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
+                clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index f4af6e2bef89..40bb16501d86 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -102,12 +102,12 @@ static int __init pxa300_init(void)
         if (cpu_is_pxa300() || cpu_is_pxa310()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa300_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(common_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(common_clkregs));
         }
 
         if (cpu_is_pxa310()) {
                 mfp_init_addr(pxa310_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa310_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa310_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index c7373e74a109..8d614ecd8e99 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -90,7 +90,7 @@ static int __init pxa320_init(void)
         if (cpu_is_pxa320()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa320_mfp_addr_map);
-                clks_register(ARRAY_AND_SIZE(pxa320_clkregs));
+                clkdev_add_table(ARRAY_AND_SIZE(pxa320_clkregs));
         }
 
         return 0;
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index fcb0721f4669..4d7c03e72504 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -634,7 +634,7 @@ static int __init pxa3xx_init(void)
                  */
                 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
 
-                clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
+                clkdev_add_table(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs));
 
                 if ((ret = pxa_init_dma(IRQ_DMA, 32)))
                         return ret;
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 9f293438e020..90bd4ef71b2c 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -346,10 +346,7 @@ static struct clk_lookup lookups[] = {
 
 static int __init clk_init(void)
 {
-        int i;
-
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
         return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 932d8af18062..86622289b74e 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -33,7 +33,7 @@
 #error "Unknown RealView platform"
 #endif
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx,      #0x10000000
diff --git a/arch/arm/mach-realview/include/mach/vmalloc.h b/arch/arm/mach-realview/include/mach/vmalloc.h
index fe0de1b507ac..a2a4c6861407 100644
--- a/arch/arm/mach-realview/include/mach/vmalloc.h
+++ b/arch/arm/mach-realview/include/mach/vmalloc.h
@@ -18,4 +18,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END             0xf8000000
+#define VMALLOC_END             0xf8000000UL
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
index b2a939ffdcde..6fc8d66395dc 100644
--- a/arch/arm/mach-rpc/include/mach/debug-macro.S
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x03000000
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
index 4c29a89ad077..0eef78b4a6ed 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
 #define S3C2410_UART1_OFF (0x4000)
 #define SHIFT_2440TXF (14-9)
 
-        .macro addruart, rx
+        .macro addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C24XX_PA_UART
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
index f0ef0ab475f6..239476b81f3b 100644
--- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
 #include <mach/map.h>
 #include <plat/regs-serial.h>
 
-        .macro addruart, rx
+        .macro addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C24XX_PA_UART
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
index 4d4fe4849589..914656820794 100644
--- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
+++ b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
@@ -12,6 +12,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/debug-macro.S b/arch/arm/mach-s3c6400/include/mach/debug-macro.S
index b18ac5266dfc..5c88875d6a3f 100644
--- a/arch/arm/mach-s3c6400/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c6400/include/mach/debug-macro.S
@@ -21,7 +21,7 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx
+        .macro addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C_PA_UART
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index 9d142ccf654b..e181f5789482 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,7 +22,7 @@
          * aligned and add in the offset when we load the value here.
          */
 
-        .macro addruart, rx
+        .macro addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1
                 ldreq   \rx, = S3C_PA_UART
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 1f0634d92702..336adccea542 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
 */
 #include <mach/hardware.h>
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x80000000        @ physical base address
diff --git a/arch/arm/mach-sa1100/include/mach/vmalloc.h b/arch/arm/mach-sa1100/include/mach/vmalloc.h
index ec8fdc5a3606..b3d002398480 100644
--- a/arch/arm/mach-sa1100/include/mach/vmalloc.h
+++ b/arch/arm/mach-sa1100/include/mach/vmalloc.h
@@ -1,4 +1,4 @@
 /*
  * arch/arm/mach-sa1100/include/mach/vmalloc.h
  */
-#define VMALLOC_END       (0xe8000000)
+#define VMALLOC_END       (0xe8000000UL)
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index f97a7626bd58..50f071c5bf4d 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mov     \rx, #0xe0000000
                 orr     \rx, \rx, #0x000003f8
                 .endm
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 111f7ea32b38..5af71d5ba665 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -610,34 +610,34 @@ EXPORT_SYMBOL(clk_get_rate);
 
 static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 18900000)
+        if (rate <= 18900000)
                 return 18900000;
-        if (rate >= 20800000)
+        if (rate <= 20800000)
                 return 20800000;
-        if (rate >= 23100000)
+        if (rate <= 23100000)
                 return 23100000;
-        if (rate >= 26000000)
+        if (rate <= 26000000)
                 return 26000000;
-        if (rate >= 29700000)
+        if (rate <= 29700000)
                 return 29700000;
-        if (rate >= 34700000)
+        if (rate <= 34700000)
                 return 34700000;
-        if (rate >= 41600000)
+        if (rate <= 41600000)
                 return 41600000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                 return 52000000;
         return -EINVAL;
 }
 
 static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
 {
-        if (rate >= 13000000)
+        if (rate <= 13000000)
                 return 13000000;
-        if (rate >= 52000000)
+        if (rate <= 52000000)
                 return 52000000;
-        if (rate >= 104000000)
+        if (rate <= 104000000)
                 return 104000000;
-        if (rate >= 208000000)
+        if (rate <= 208000000)
                 return 208000000;
         return -EINVAL;
 }
@@ -1276,11 +1276,8 @@ static struct clk_lookup lookups[] = {
 
 static void __init clk_register(void)
 {
-        int i;
-
         /* Register the lookups */
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 }
 
 /*
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 653e25be3dd8..01b50313914c 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2009 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson AB
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -19,6 +19,7 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <mach/coh901318.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -29,6 +30,7 @@
 
 #include <mach/hardware.h>
 #include <mach/syscon.h>
+#include <mach/dma_channels.h>
 
 #include "clock.h"
 #include "mmc.h"
@@ -372,8 +374,1019 @@ static struct resource ave_resources[] = {
         },
 };
 
+static struct resource dma_resource[] = {
+        {
+                .start = U300_DMAC_BASE,
+                .end = U300_DMAC_BASE + PAGE_SIZE - 1,
+                .flags =  IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_U300_DMA,
+                .end = IRQ_U300_DMA,
+                .flags =  IORESOURCE_IRQ,
+        }
+};
+
+#ifdef CONFIG_MACH_U300_BS335
+/* points out all dma slave channels.
+ * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
+ * Select all channels from A to B, end of list is marked with -1,-1
+ */
+static int dma_slave_channels[] = {
+        U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
+        U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
+
+/* points out all dma memcpy channels. */
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
+
+#else /* CONFIG_MACH_U300_BS335 */
+
+static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
+static int dma_memcpy_channels[] = {
+        U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
+
+#endif
+
+/** register dma for memory access
+ *
+ * active  1 means dma intends to access memory
+ *         0 means dma wont access memory
+ */
+static void coh901318_access_memory_state(struct device *dev, bool active)
+{
+}
+
+#define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
+                        COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
+                        COH901318_CX_CFG_LCR_DISABLE | \
+                        COH901318_CX_CFG_TC_IRQ_ENABLE | \
+                        COH901318_CX_CFG_BE_IRQ_ENABLE)
+#define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_DISABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+#define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
+                        COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
+                        COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
+                        COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
+                        COH901318_CX_CTRL_MASTER_MODE_M1RW | \
+                        COH901318_CX_CTRL_TCP_DISABLE | \
+                        COH901318_CX_CTRL_TC_IRQ_ENABLE | \
+                        COH901318_CX_CTRL_HSP_DISABLE | \
+                        COH901318_CX_CTRL_HSS_DISABLE | \
+                        COH901318_CX_CTRL_DDMA_LEGACY | \
+                        COH901318_CX_CTRL_PRDD_SOURCE)
+
+const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
+        {
+                .number = U300_DMA_MSL_TX_0,
+                .name = "MSL TX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_1,
+                .name = "MSL TX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_2,
+                .name = "MSL TX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .desc_nbr_max = 10,
+        },
+        {
+                .number = U300_DMA_MSL_TX_3,
+                .name = "MSL TX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_4,
+                .name = "MSL TX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_MSL_TX_5,
+                .name = "MSL TX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_TX_6,
+                .name = "MSL TX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
+        },
+        {
+                .number = U300_DMA_MSL_RX_0,
+                .name = "MSL RX 0",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MSL_RX_1,
+                .name = "MSL RX 1",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_2,
+                .name = "MSL RX 2",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_3,
+                .name = "MSL RX 3",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_4,
+                .name = "MSL RX 4",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_5,
+                .name = "MSL RX 5",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_MSL_RX_6,
+                .name = "MSL RX 6",
+                .priority_high = 0,
+                .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
+        },
+        {
+                .number = U300_DMA_MMCSD_RX_TX,
+                .name = "MMCSD RX TX",
+                .priority_high = 0,
+                .dev_addr =  U300_MMCSD_BASE + 0x080,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY,
+
+        },
+        {
+                .number = U300_DMA_MSPRO_TX,
+                .name = "MSPRO TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_MSPRO_RX,
+                .name = "MSPRO RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_TX,
+                .name = "UART0 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART0_RX,
+                .name = "UART0 RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_TX,
+                .name = "APEX TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_APEX_RX,
+                .name = "APEX RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_TX,
+                .name = "PCM I2S0 TX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S0_RX,
+                .name = "PCM I2S0 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S0_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_TX,
+                .name = "PCM I2S1 TX",
+                .priority_high = 1,
+                .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_SOURCE,
+        },
+        {
+                .number = U300_DMA_PCM_I2S1_RX,
+                .name = "PCM I2S1 RX",
+                .priority_high = 1,
+                .dev_addr = U300_PCM_I2S1_BASE + 0x10,
+                .param.config = COH901318_CX_CFG_CH_DISABLE |
+                                COH901318_CX_CFG_LCR_DISABLE |
+                                COH901318_CX_CFG_TC_IRQ_ENABLE |
+                                COH901318_CX_CFG_BE_IRQ_ENABLE,
+                .param.ctrl_lli_chained = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_DISABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_DISABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+                .param.ctrl_lli_last = 0 |
+                                COH901318_CX_CTRL_TC_ENABLE |
+                                COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
+                                COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
+                                COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
+                                COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
+                                COH901318_CX_CTRL_MASTER_MODE_M1RW |
+                                COH901318_CX_CTRL_TCP_ENABLE |
+                                COH901318_CX_CTRL_TC_IRQ_ENABLE |
+                                COH901318_CX_CTRL_HSP_ENABLE |
+                                COH901318_CX_CTRL_HSS_DISABLE |
+                                COH901318_CX_CTRL_DDMA_LEGACY |
+                                COH901318_CX_CTRL_PRDD_DEST,
+        },
+        {
+                .number = U300_DMA_XGAM_CDI,
+                .name = "XGAM CDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_XGAM_PDI,
+                .name = "XGAM PDI",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_TX,
+                .name = "SPI TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_SPI_RX,
+                .name = "SPI RX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_0,
+                .name = "GENERAL 00",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_1,
+                .name = "GENERAL 01",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_2,
+                .name = "GENERAL 02",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_3,
+                .name = "GENERAL 03",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_4,
+                .name = "GENERAL 04",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_5,
+                .name = "GENERAL 05",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_6,
+                .name = "GENERAL 06",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_7,
+                .name = "GENERAL 07",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_8,
+                .name = "GENERAL 08",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+#ifdef CONFIG_MACH_U300_BS335
+        {
+                .number = U300_DMA_UART1_TX,
+                .name = "UART1 TX",
+                .priority_high = 0,
+        },
+        {
+                .number = U300_DMA_UART1_RX,
+                .name = "UART1 RX",
+                .priority_high = 0,
+        }
+#else
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_9,
+                .name = "GENERAL 09",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        },
+        {
+                .number = U300_DMA_GENERAL_PURPOSE_10,
+                .name = "GENERAL 10",
+                .priority_high = 0,
+
+                .param.config = flags_memcpy_config,
+                .param.ctrl_lli_chained = flags_memcpy_lli_chained,
+                .param.ctrl_lli = flags_memcpy_lli,
+                .param.ctrl_lli_last = flags_memcpy_lli_last,
+        }
+#endif
+};
+
+
+static struct coh901318_platform coh901318_platform = {
+        .chans_slave = dma_slave_channels,
+        .chans_memcpy = dma_memcpy_channels,
+        .access_memory_state = coh901318_access_memory_state,
+        .chan_conf = chan_config,
+        .max_channels = U300_DMA_CHANNELS,
+};
+
 static struct platform_device wdog_device = {
-        .name = "wdog",
+        .name = "coh901327_wdog",
         .id = -1,
         .num_resources = ARRAY_SIZE(wdog_resources),
         .resource = wdog_resources,
@@ -428,11 +1441,23 @@ static struct platform_device ave_device = {
         .resource = ave_resources,
 };
 
+static struct platform_device dma_device = {
+        .name           = "coh901318",
+        .id             = -1,
+        .resource       = dma_resource,
+        .num_resources  = ARRAY_SIZE(dma_resource),
+        .dev = {
+                .platform_data = &coh901318_platform,
+                .coherent_dma_mask = ~0,
+        },
+};
+
 /*
  * Notice that AMBA devices are initialized before platform devices.
  *
  */
 static struct platform_device *platform_devs[] __initdata = {
+        &dma_device,
         &i2c0_device,
         &i2c1_device,
         &keypad_device,
diff --git a/arch/arm/mach-u300/gpio.c b/arch/arm/mach-u300/gpio.c
index 0b35826b7d1d..5f61fd45a0c8 100644
--- a/arch/arm/mach-u300/gpio.c
+++ b/arch/arm/mach-u300/gpio.c
@@ -546,7 +546,7 @@ static void gpio_set_initial_values(void)
         for (i = 0; i < U300_GPIO_MAX; i++) {
                 val = 0;
                 for (j = 0; j < 8; j++)
-                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP)) << j;
+                        val |= (u32)((u300_gpio_config[i][j].pull_up == DISABLE_PULL_UP) << j);
                 local_irq_save(flags);
                 writel(val, virtbase + U300_GPIO_PXPER + i * U300_GPIO_PORTX_SPACING);
                 local_irq_restore(flags);
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index f3a1cbbeeab3..ca4a028c2661 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
  */
 #include <mach/hardware.h>
 
-        .macro  addruart,rx
+        .macro  addruart, rx, tmp
         /* If we move the adress using MMU, use this. */
         mrc     p15, 0, \rx, c1, c0
         tst     \rx, #1                 @ MMU enabled?
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/include/mach/dma_channels.h
new file mode 100644
index 000000000000..b239149ba0d0
--- /dev/null
+++ b/arch/arm/mach-u300/include/mach/dma_channels.h
@@ -0,0 +1,69 @@
+/*
+ *
+ * arch/arm/mach-u300/include/mach/dma_channels.h
+ *
+ *
+ * Copyright (C) 2007-2009 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Map file for the U300 dma driver.
+ * Author: Per Friden <per.friden@stericsson.com>
+ */
+
+#ifndef DMA_CHANNELS_H
+#define DMA_CHANNELS_H
+
+#define U300_DMA_MSL_TX_0             0
+#define U300_DMA_MSL_TX_1             1
+#define U300_DMA_MSL_TX_2             2
+#define U300_DMA_MSL_TX_3             3
+#define U300_DMA_MSL_TX_4             4
+#define U300_DMA_MSL_TX_5             5
+#define U300_DMA_MSL_TX_6             6
+#define U300_DMA_MSL_RX_0             7
+#define U300_DMA_MSL_RX_1             8
+#define U300_DMA_MSL_RX_2             9
+#define U300_DMA_MSL_RX_3             10
+#define U300_DMA_MSL_RX_4             11
+#define U300_DMA_MSL_RX_5             12
+#define U300_DMA_MSL_RX_6             13
+#define U300_DMA_MMCSD_RX_TX          14
+#define U300_DMA_MSPRO_TX             15
+#define U300_DMA_MSPRO_RX             16
+#define U300_DMA_UART0_TX             17
+#define U300_DMA_UART0_RX             18
+#define U300_DMA_APEX_TX              19
+#define U300_DMA_APEX_RX              20
+#define U300_DMA_PCM_I2S0_TX          21
+#define U300_DMA_PCM_I2S0_RX          22
+#define U300_DMA_PCM_I2S1_TX          23
+#define U300_DMA_PCM_I2S1_RX          24
+#define U300_DMA_XGAM_CDI             25
+#define U300_DMA_XGAM_PDI             26
+#define U300_DMA_SPI_TX               27
+#define U300_DMA_SPI_RX               28
+#define U300_DMA_GENERAL_PURPOSE_0    29
+#define U300_DMA_GENERAL_PURPOSE_1    30
+#define U300_DMA_GENERAL_PURPOSE_2    31
+#define U300_DMA_GENERAL_PURPOSE_3    32
+#define U300_DMA_GENERAL_PURPOSE_4    33
+#define U300_DMA_GENERAL_PURPOSE_5    34
+#define U300_DMA_GENERAL_PURPOSE_6    35
+#define U300_DMA_GENERAL_PURPOSE_7    36
+#define U300_DMA_GENERAL_PURPOSE_8    37
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_UART1_TX             38
+#define U300_DMA_UART1_RX             39
+#else
+#define U300_DMA_GENERAL_PURPOSE_9    38
+#define U300_DMA_GENERAL_PURPOSE_10   39
+#endif
+
+#ifdef CONFIG_MACH_U300_BS335
+#define U300_DMA_DEVICE_CHANNELS      32
+#else
+#define U300_DMA_DEVICE_CHANNELS      30
+#endif
+#define U300_DMA_CHANNELS             40
+
+
+#endif /* DMA_CHANNELS_H */
diff --git a/arch/arm/mach-u300/include/mach/vmalloc.h b/arch/arm/mach-u300/include/mach/vmalloc.h
index b00c51a66fbe..ec423b92b81d 100644
--- a/arch/arm/mach-u300/include/mach/vmalloc.h
+++ b/arch/arm/mach-u300/include/mach/vmalloc.h
@@ -9,4 +9,4 @@
  * End must be above the I/O registers and on an even 2MiB boundary.
  * Author: Linus Walleij <linus.walleij@stericsson.com>
  */
-#define VMALLOC_END     0xfe800000
+#define VMALLOC_END     0xfe800000UL
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index aa5afbcc90f9..803aec1d6728 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -22,6 +22,7 @@
 #include <asm/mach/arch.h>
 
 #include <plat/mtu.h>
+#include <plat/i2c.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
@@ -108,11 +109,96 @@ static struct amba_device pl022_device = {
         .periphid = SSP_PER_ID,
 };
 
+static struct amba_device pl031_device = {
+        .dev = {
+                .init_name = "pl031",
+        },
+        .res = {
+                .start = U8500_RTC_BASE,
+                .end = U8500_RTC_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        .irq = {IRQ_RTC_RTT, NO_IRQ},
+};
+
+#define U8500_I2C_RESOURCES(id, size)           \
+static struct resource u8500_i2c_resources_##id[] = {   \
+        [0] = {                                 \
+                .start  = U8500_I2C##id##_BASE, \
+                .end    = U8500_I2C##id##_BASE + size - 1, \
+                .flags  = IORESOURCE_MEM,       \
+        },                                      \
+        [1] = {                                 \
+                .start  = IRQ_I2C##id,          \
+                .end    = IRQ_I2C##id,          \
+                .flags  = IORESOURCE_IRQ        \
+        }                                       \
+}
+
+U8500_I2C_RESOURCES(0, SZ_4K);
+U8500_I2C_RESOURCES(1, SZ_4K);
+U8500_I2C_RESOURCES(2, SZ_4K);
+U8500_I2C_RESOURCES(3, SZ_4K);
+
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+static struct nmk_i2c_controller u8500_i2c_##id = { \
+        /*                              \
+         * slave data setup time, which is      \
+         * 250 ns,100ns,10ns which is 14,6,2    \
+         * respectively for a 48 Mhz    \
+         * i2c clock                    \
+         */                             \
+        .slsu           = _slsu,        \
+        /* Tx FIFO threshold */         \
+        .tft            = _tft,         \
+        /* Rx FIFO threshold */         \
+        .rft            = _rft,         \
+        /* std. mode operation */       \
+        .clk_freq       = clk,          \
+        .sm             = _sm,          \
+}
+
+/*
+ * The board uses 4 i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 1 and standard
+ * mode of operation
+ */
+U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+
+#define U8500_I2C_PDEVICE(cid)          \
+static struct platform_device i2c_controller##cid = { \
+        .name = "nmk-i2c",              \
+        .id      = cid,                 \
+        .num_resources = 2,             \
+        .resource = u8500_i2c_resources_##cid,  \
+        .dev = {                        \
+                .platform_data = &u8500_i2c_##cid \
+        }                               \
+}
+
+U8500_I2C_PDEVICE(0);
+U8500_I2C_PDEVICE(1);
+U8500_I2C_PDEVICE(2);
+U8500_I2C_PDEVICE(3);
+
 static struct amba_device *amba_devs[] __initdata = {
         &uart0_device,
         &uart1_device,
         &uart2_device,
         &pl022_device,
+        &pl031_device,
+};
+
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
+        &i2c_controller0,
+        &i2c_controller1,
+        &i2c_controller2,
+        &i2c_controller3,
 };
 
 static void __init u8500_timer_init(void)
@@ -139,6 +225,8 @@ static void __init u8500_init_machine(void)
         for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
                 amba_device_register(amba_devs[i], &iomem_resource);
 
+        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+
         spi_register_board_info(u8500_spi_devices,
                         ARRAY_SIZE(u8500_spi_devices));
 
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 20b6ebb6783a..8359a73d0041 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -85,11 +85,8 @@ static struct clk_lookup lookups[] = {
 
 static int __init clk_init(void)
 {
-        int i;
-
         /* register the clock lookups */
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
         return 0;
 }
 arch_initcall(clk_init);
diff --git a/arch/arm/mach-ux500/cpu-u8500.c b/arch/arm/mach-ux500/cpu-u8500.c
index 5f05e5850f71..397bc1f9ed94 100644
--- a/arch/arm/mach-ux500/cpu-u8500.c
+++ b/arch/arm/mach-ux500/cpu-u8500.c
@@ -33,6 +33,7 @@ static struct platform_device *platform_devs[] __initdata = {
 
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_UART2_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GIC_CPU_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GIC_DIST_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 8f21b6a95dce..09cbfda8aee5 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -8,12 +8,13 @@
  * published by the Free Software Foundation.
  *
  */
-        .macro  addruart,rx
+#include <mach/hardware.h>
+
+        .macro  addruart, rx, tmp
         mrc     p15, 0, \rx, c1, c0
-        tst     \rx, #1                 @MMU enabled?
-        moveq   \rx, #0x80000000        @MMU off, Physical address
-        movne   \rx, #0xF0000000        @MMU on, Virtual address
-        orr     \rx, \rx, #0x7000
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =U8500_UART2_BASE                  @ no, physical address
+        ldrne   \rx, =IO_ADDRESS(U8500_UART2_BASE)      @ yes, virtual address
         .endm
 
 #include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-ux500/include/mach/vmalloc.h b/arch/arm/mach-ux500/include/mach/vmalloc.h
index 86cdbbce1842..a4945cb41172 100644
--- a/arch/arm/mach-ux500/include/mach/vmalloc.h
+++ b/arch/arm/mach-ux500/include/mach/vmalloc.h
@@ -15,4 +15,4 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
-#define VMALLOC_END     0xf0000000
+#define VMALLOC_END     0xf0000000UL
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index e13be7c444ca..9ddb49b1cb71 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -851,8 +851,7 @@ void __init versatile_init(void)
 {
         int i;
 
-        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clkdev_add(&lookups[i]);
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 
         platform_device_register(&versatile_flash_device);
         platform_device_register(&versatile_i2c_device);
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S
index b4ac00eacf68..6fea7199c626 100644
--- a/arch/arm/mach-versatile/include/mach/debug-macro.S
+++ b/arch/arm/mach-versatile/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
  *
 */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx,      #0x10000000
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index b785994bab0a..2c371ff22e51 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -90,12 +90,3 @@ void nuc900_subclk_enable(struct clk *clk, int enable)
 
         __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
 }
-
-
-void clks_register(struct clk_lookup *clks, size_t num)
-{
-        int i;
-
-        for (i = 0; i < num; i++)
-                clkdev_add(&clks[i]);
-}
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index f5816a06eed6..c56ddab3d912 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -14,7 +14,6 @@
 
 void nuc900_clk_enable(struct clk *clk, int enable);
 void nuc900_subclk_enable(struct clk *clk, int enable);
-void clks_register(struct clk_lookup *clks, size_t num);
 
 struct clk {
         unsigned long           cken;
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 20dc0c96214d..642207e18198 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -45,6 +45,7 @@ static struct map_desc nuc900_iodesc[] __initdata = {
         IODESC_ENT(UART),
         IODESC_ENT(TIMER),
         IODESC_ENT(EBI),
+        IODESC_ENT(GPIO),
 };
 
 /* Initial clock declarations. */
@@ -68,6 +69,11 @@ static DEFINE_CLK(gdma, 27);
 static DEFINE_CLK(adc, 28);
 static DEFINE_CLK(usi, 29);
 static DEFINE_CLK(ext, 0);
+static DEFINE_CLK(timer0, 19);
+static DEFINE_CLK(timer1, 20);
+static DEFINE_CLK(timer2, 21);
+static DEFINE_CLK(timer3, 22);
+static DEFINE_CLK(timer4, 23);
 
 static struct clk_lookup nuc900_clkregs[] = {
         DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
@@ -90,6 +96,11 @@ static struct clk_lookup nuc900_clkregs[] = {
         DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
         DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
         DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+        DEF_CLKLOOK(&clk_timer0, NULL, "timer0"),
+        DEF_CLKLOOK(&clk_timer1, NULL, "timer1"),
+        DEF_CLKLOOK(&clk_timer2, NULL, "timer2"),
+        DEF_CLKLOOK(&clk_timer3, NULL, "timer3"),
+        DEF_CLKLOOK(&clk_timer4, NULL, "timer4"),
 };
 
 /* Initial serial platform data */
@@ -208,6 +219,6 @@ void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
 
 void __init nuc900_init_clocks(void)
 {
-        clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
+        clkdev_add_table(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
 }
 
diff --git a/arch/arm/mach-w90x900/include/mach/vmalloc.h b/arch/arm/mach-w90x900/include/mach/vmalloc.h
index 2f9dfb928533..b067e44500a4 100644
--- a/arch/arm/mach-w90x900/include/mach/vmalloc.h
+++ b/arch/arm/mach-w90x900/include/mach/vmalloc.h
@@ -18,6 +18,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index baf638487a2d..c4ed9f93f646 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -399,7 +399,7 @@ config CPU_V6
 config CPU_32v6K
         bool "Support ARM V6K processor extensions" if !SMP
         depends on CPU_V6
-        default y if SMP && !ARCH_MX3
+        default y if SMP && !(ARCH_MX3 || ARCH_OMAP2)
         help
           Say Y here if your ARMv6 processor supports the 'K' extension.
           This enables the kernel to use some instructions not present
@@ -410,7 +410,7 @@ config CPU_32v6K
 # ARMv7
 config CPU_V7
         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
-        select CPU_32v6K
+        select CPU_32v6K if !ARCH_OMAP2
         select CPU_32v7
         select CPU_ABRT_EV7
         select CPU_PABRT_V7
@@ -754,7 +754,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
         bool "Enable the L2x0 outer cache controller"
         depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
         default y
         select OUTER_CACHE
         help
@@ -779,5 +779,5 @@ config CACHE_XSC3L2
 
 config ARM_L1_CACHE_SHIFT
         int
-        default 6 if ARCH_OMAP3 || ARCH_S5PC1XX
+        default 6 if ARM_L1_CACHE_SHIFT_6
         default 5
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 62820eda84d9..edddd66faac6 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -901,11 +901,7 @@ static int __init alignment_init(void)
 #ifdef CONFIG_PROC_FS
         struct proc_dir_entry *res;
 
-        res = proc_mkdir("cpu", NULL);
-        if (!res)
-                return -ENOMEM;
-
-        res = create_proc_entry("alignment", S_IWUSR | S_IRUGO, res);
+        res = create_proc_entry("cpu/alignment", S_IWUSR | S_IRUGO, NULL);
         if (!res)
                 return -ENOMEM;
 
diff --git a/arch/arm/mm/cache-fa.S b/arch/arm/mm/cache-fa.S
index a89444a3c016..7148e53e6078 100644
--- a/arch/arm/mm/cache-fa.S
+++ b/arch/arm/mm/cache-fa.S
@@ -157,7 +157,7 @@ ENTRY(fa_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(fa_dma_inv_range)
+fa_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c14, 1          @ clean & invalidate D entry
@@ -180,7 +180,7 @@ ENTRY(fa_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(fa_dma_clean_range)
+fa_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -205,6 +205,30 @@ ENTRY(fa_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     fa_dma_clean_range
+        bcs     fa_dma_inv_range
+        b       fa_dma_flush_range
+ENDPROC(fa_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(fa_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(fa_dma_unmap_area)
+
         __INITDATA
 
         .type   fa_cache_fns, #object
@@ -215,7 +239,7 @@ ENTRY(fa_cache_fns)
         .long   fa_coherent_kern_range
         .long   fa_coherent_user_range
         .long   fa_flush_kern_dcache_area
-        .long   fa_dma_inv_range
-        .long   fa_dma_clean_range
+        .long   fa_dma_map_area
+        .long   fa_dma_unmap_area
         .long   fa_dma_flush_range
         .size   fa_cache_fns, . - fa_cache_fns
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index cb8fc6573b1b..07334632d3e2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -42,6 +42,57 @@ static inline void cache_sync(void)
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
+static inline void l2x0_clean_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+}
+
+static inline void l2x0_inv_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+
+#ifdef CONFIG_PL310_ERRATA_588369
+static void debug_writel(unsigned long val)
+{
+        extern void omap_smc1(u32 fn, u32 arg);
+
+        /*
+         * Texas Instrument secure monitor api to modify the
+         * PL310 Debug Control Register.
+         */
+        omap_smc1(0x100, val);
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+
+        /* Clean by PA followed by Invalidate by PA */
+        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_LINE_PA);
+        cache_wait(base + L2X0_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_INV_LINE_PA);
+}
+#else
+
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
+{
+}
+
+static inline void l2x0_flush_line(unsigned long addr)
+{
+        void __iomem *base = l2x0_base;
+        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        writel(addr, base + L2X0_CLEAN_INV_LINE_PA);
+}
+#endif
+
 static inline void l2x0_inv_all(void)
 {
         unsigned long flags;
@@ -62,23 +113,24 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
         spin_lock_irqsave(&l2x0_lock, flags);
         if (start & (CACHE_LINE_SIZE - 1)) {
                 start &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(start);
+                debug_writel(0x00);
                 start += CACHE_LINE_SIZE;
         }
 
         if (end & (CACHE_LINE_SIZE - 1)) {
                 end &= ~(CACHE_LINE_SIZE - 1);
-                cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                writel(end, base + L2X0_CLEAN_INV_LINE_PA);
+                debug_writel(0x03);
+                l2x0_flush_line(end);
+                debug_writel(0x00);
         }
 
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_INV_LINE_PA);
+                        l2x0_inv_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -103,8 +155,7 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_LINE_PA);
+                        l2x0_clean_line(start);
                         start += CACHE_LINE_SIZE;
                 }
 
@@ -128,11 +179,12 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
         while (start < end) {
                 unsigned long blk_end = start + min(end - start, 4096UL);
 
+                debug_writel(0x03);
                 while (start < blk_end) {
-                        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-                        writel(start, base + L2X0_CLEAN_INV_LINE_PA);
+                        l2x0_flush_line(start);
                         start += CACHE_LINE_SIZE;
                 }
+                debug_writel(0x00);
 
                 if (blk_end < end) {
                         spin_unlock_irqrestore(&l2x0_lock, flags);
diff --git a/arch/arm/mm/cache-v3.S b/arch/arm/mm/cache-v3.S
index 2a482731ea36..c2ff3c599fee 100644
--- a/arch/arm/mm/cache-v3.S
+++ b/arch/arm/mm/cache-v3.S
@@ -84,20 +84,6 @@ ENTRY(v3_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v3_dma_inv_range)
-        /* FALLTHROUGH */
-
-/*
  *      dma_flush_range(start, end)
  *
  *      Clean and invalidate the specified virtual address range.
@@ -108,18 +94,29 @@ ENTRY(v3_dma_inv_range)
 ENTRY(v3_dma_flush_range)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c0, 0           @ flush ID cache
+        mov     pc, lr
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v3_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v3_dma_flush_range
         /* FALLTHROUGH */
 
 /*
- *      dma_clean_range(start, end)
- *
- *      Clean (write back) the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
  */
-ENTRY(v3_dma_clean_range)
+ENTRY(v3_dma_map_area)
         mov     pc, lr
+ENDPROC(v3_dma_unmap_area)
+ENDPROC(v3_dma_map_area)
 
         __INITDATA
 
@@ -131,7 +128,7 @@ ENTRY(v3_cache_fns)
         .long   v3_coherent_kern_range
         .long   v3_coherent_user_range
         .long   v3_flush_kern_dcache_area
-        .long   v3_dma_inv_range
-        .long   v3_dma_clean_range
+        .long   v3_dma_map_area
+        .long   v3_dma_unmap_area
         .long   v3_dma_flush_range
         .size   v3_cache_fns, . - v3_cache_fns
diff --git a/arch/arm/mm/cache-v4.S b/arch/arm/mm/cache-v4.S
index 5c7da3e372e9..4810f7e3e813 100644
--- a/arch/arm/mm/cache-v4.S
+++ b/arch/arm/mm/cache-v4.S
@@ -94,20 +94,6 @@ ENTRY(v4_flush_kern_dcache_area)
         /* FALLTHROUGH */
 
 /*
- *      dma_inv_range(start, end)
- *
- *      Invalidate (discard) the specified virtual address range.
- *      May not write back any entries.  If 'start' or 'end'
- *      are not cache line aligned, those lines must be written
- *      back.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4_dma_inv_range)
-        /* FALLTHROUGH */
-
-/*
  *      dma_flush_range(start, end)
  *
  *      Clean and invalidate the specified virtual address range.
@@ -120,18 +106,29 @@ ENTRY(v4_dma_flush_range)
         mov     r0, #0
         mcr     p15, 0, r0, c7, c7, 0           @ flush ID cache
 #endif
+        mov     pc, lr
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4_dma_unmap_area)
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4_dma_flush_range
         /* FALLTHROUGH */
 
 /*
- *      dma_clean_range(start, end)
- *
- *      Clean (write back) the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
  */
-ENTRY(v4_dma_clean_range)
+ENTRY(v4_dma_map_area)
         mov     pc, lr
+ENDPROC(v4_dma_unmap_area)
+ENDPROC(v4_dma_map_area)
 
         __INITDATA
 
@@ -143,7 +140,7 @@ ENTRY(v4_cache_fns)
         .long   v4_coherent_kern_range
         .long   v4_coherent_user_range
         .long   v4_flush_kern_dcache_area
-        .long   v4_dma_inv_range
-        .long   v4_dma_clean_range
+        .long   v4_dma_map_area
+        .long   v4_dma_unmap_area
         .long   v4_dma_flush_range
         .size   v4_cache_fns, . - v4_cache_fns
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 3dbedf1ec0e7..df8368afa102 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -173,7 +173,7 @@ ENTRY(v4wb_coherent_user_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wb_dma_inv_range)
+v4wb_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -194,7 +194,7 @@ ENTRY(v4wb_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wb_dma_clean_range)
+v4wb_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -216,6 +216,30 @@ ENTRY(v4wb_dma_clean_range)
         .globl  v4wb_dma_flush_range
         .set    v4wb_dma_flush_range, v4wb_coherent_kern_range
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     v4wb_dma_clean_range
+        bcs     v4wb_dma_inv_range
+        b       v4wb_dma_flush_range
+ENDPROC(v4wb_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wb_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(v4wb_dma_unmap_area)
+
         __INITDATA
 
         .type   v4wb_cache_fns, #object
@@ -226,7 +250,7 @@ ENTRY(v4wb_cache_fns)
         .long   v4wb_coherent_kern_range
         .long   v4wb_coherent_user_range
         .long   v4wb_flush_kern_dcache_area
-        .long   v4wb_dma_inv_range
-        .long   v4wb_dma_clean_range
+        .long   v4wb_dma_map_area
+        .long   v4wb_dma_unmap_area
         .long   v4wb_dma_flush_range
         .size   v4wb_cache_fns, . - v4wb_cache_fns
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S
index b3b7410270b4..45c70312f43b 100644
--- a/arch/arm/mm/cache-v4wt.S
+++ b/arch/arm/mm/cache-v4wt.S
@@ -142,23 +142,12 @@ ENTRY(v4wt_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(v4wt_dma_inv_range)
+v4wt_dma_inv_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
         add     r0, r0, #CACHE_DLINESIZE
         cmp     r0, r1
         blo     1b
-        /* FALLTHROUGH */
-
-/*
- *      dma_clean_range(start, end)
- *
- *      Clean the specified virtual address range.
- *
- *      - start  - virtual start address
- *      - end    - virtual end address
- */
-ENTRY(v4wt_dma_clean_range)
         mov     pc, lr
 
 /*
@@ -172,6 +161,29 @@ ENTRY(v4wt_dma_clean_range)
         .globl  v4wt_dma_flush_range
         .equ    v4wt_dma_flush_range, v4wt_dma_inv_range
 
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v4wt_dma_inv_range
+        /* FALLTHROUGH */
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v4wt_dma_map_area)
+        mov     pc, lr
+ENDPROC(v4wt_dma_unmap_area)
+ENDPROC(v4wt_dma_map_area)
+
         __INITDATA
 
         .type   v4wt_cache_fns, #object
@@ -182,7 +194,7 @@ ENTRY(v4wt_cache_fns)
         .long   v4wt_coherent_kern_range
         .long   v4wt_coherent_user_range
         .long   v4wt_flush_kern_dcache_area
-        .long   v4wt_dma_inv_range
-        .long   v4wt_dma_clean_range
+        .long   v4wt_dma_map_area
+        .long   v4wt_dma_unmap_area
         .long   v4wt_dma_flush_range
         .size   v4wt_cache_fns, . - v4wt_cache_fns
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 4ba0a24ce6f5..9d89c67a1cc3 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -195,7 +195,7 @@ ENTRY(v6_flush_kern_dcache_area)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v6_dma_inv_range)
+v6_dma_inv_range:
         tst     r0, #D_CACHE_LINE_SIZE - 1
         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -228,7 +228,7 @@ ENTRY(v6_dma_inv_range)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v6_dma_clean_range)
+v6_dma_clean_range:
         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
 #ifdef HARVARD_CACHE
@@ -263,6 +263,32 @@ ENTRY(v6_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v6_dma_inv_range
+        b       v6_dma_clean_range
+ENDPROC(v6_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v6_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v6_dma_inv_range
+        mov     pc, lr
+ENDPROC(v6_dma_unmap_area)
+
         __INITDATA
 
         .type   v6_cache_fns, #object
@@ -273,7 +299,7 @@ ENTRY(v6_cache_fns)
         .long   v6_coherent_kern_range
         .long   v6_coherent_user_range
         .long   v6_flush_kern_dcache_area
-        .long   v6_dma_inv_range
-        .long   v6_dma_clean_range
+        .long   v6_dma_map_area
+        .long   v6_dma_unmap_area
         .long   v6_dma_flush_range
         .size   v6_cache_fns, . - v6_cache_fns
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 9073db849fb4..bcd64f265870 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -216,7 +216,7 @@ ENDPROC(v7_flush_kern_dcache_area)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v7_dma_inv_range)
+v7_dma_inv_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         tst     r0, r3
@@ -240,7 +240,7 @@ ENDPROC(v7_dma_inv_range)
  *      - start   - virtual start address of region
  *      - end     - virtual end address of region
  */
-ENTRY(v7_dma_clean_range)
+v7_dma_clean_range:
         dcache_line_size r2, r3
         sub     r3, r2, #1
         bic     r0, r0, r3
@@ -271,6 +271,32 @@ ENTRY(v7_dma_flush_range)
         mov     pc, lr
 ENDPROC(v7_dma_flush_range)
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_FROM_DEVICE
+        beq     v7_dma_inv_range
+        b       v7_dma_clean_range
+ENDPROC(v7_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(v7_dma_unmap_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        bne     v7_dma_inv_range
+        mov     pc, lr
+ENDPROC(v7_dma_unmap_area)
+
         __INITDATA
 
         .type   v7_cache_fns, #object
@@ -281,7 +307,7 @@ ENTRY(v7_cache_fns)
         .long   v7_coherent_kern_range
         .long   v7_coherent_user_range
         .long   v7_flush_kern_dcache_area
-        .long   v7_dma_inv_range
-        .long   v7_dma_clean_range
+        .long   v7_dma_map_area
+        .long   v7_dma_unmap_area
         .long   v7_dma_flush_range
         .size   v7_cache_fns, . - v7_cache_fns
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index a9e22e31eaa1..b0ee9ba3cfab 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -10,12 +10,17 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/mm.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
 
 #include <asm/mmu_context.h>
 #include <asm/tlbflush.h>
 
 static DEFINE_SPINLOCK(cpu_asid_lock);
 unsigned int cpu_last_asid = ASID_FIRST_VERSION;
+#ifdef CONFIG_SMP
+DEFINE_PER_CPU(struct mm_struct *, current_mm);
+#endif
 
 /*
  * We fork()ed a process, and we need a new context for the child
@@ -26,13 +31,109 @@ unsigned int cpu_last_asid = ASID_FIRST_VERSION;
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 {
         mm->context.id = 0;
+        spin_lock_init(&mm->context.id_lock);
 }
 
+static void flush_context(void)
+{
+        /* set the reserved ASID before flushing the TLB */
+        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (0));
+        isb();
+        local_flush_tlb_all();
+        if (icache_is_vivt_asid_tagged()) {
+                __flush_icache_all();
+                dsb();
+        }
+}
+
+#ifdef CONFIG_SMP
+
+static void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+        unsigned long flags;
+
+        /*
+         * Locking needed for multi-threaded applications where the
+         * same mm->context.id could be set from different CPUs during
+         * the broadcast. This function is also called via IPI so the
+         * mm->context.id_lock has to be IRQ-safe.
+         */
+        spin_lock_irqsave(&mm->context.id_lock, flags);
+        if (likely((mm->context.id ^ cpu_last_asid) >> ASID_BITS)) {
+                /*
+                 * Old version of ASID found. Set the new one and
+                 * reset mm_cpumask(mm).
+                 */
+                mm->context.id = asid;
+                cpumask_clear(mm_cpumask(mm));
+        }
+        spin_unlock_irqrestore(&mm->context.id_lock, flags);
+
+        /*
+         * Set the mm_cpumask(mm) bit for the current CPU.
+         */
+        cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+}
+
+/*
+ * Reset the ASID on the current CPU. This function call is broadcast
+ * from the CPU handling the ASID rollover and holding cpu_asid_lock.
+ */
+static void reset_context(void *info)
+{
+        unsigned int asid;
+        unsigned int cpu = smp_processor_id();
+        struct mm_struct *mm = per_cpu(current_mm, cpu);
+
+        /*
+         * Check if a current_mm was set on this CPU as it might still
+         * be in the early booting stages and using the reserved ASID.
+         */
+        if (!mm)
+                return;
+
+        smp_rmb();
+        asid = cpu_last_asid + cpu + 1;
+
+        flush_context();
+        set_mm_context(mm, asid);
+
+        /* set the new ASID */
+        asm("mcr        p15, 0, %0, c13, c0, 1\n" : : "r" (mm->context.id));
+        isb();
+}
+
+#else
+
+static inline void set_mm_context(struct mm_struct *mm, unsigned int asid)
+{
+        mm->context.id = asid;
+        cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
+}
+
+#endif
+
 void __new_context(struct mm_struct *mm)
 {
         unsigned int asid;
 
         spin_lock(&cpu_asid_lock);
+#ifdef CONFIG_SMP
+        /*
+         * Check the ASID again, in case the change was broadcast from
+         * another CPU before we acquired the lock.
+         */
+        if (unlikely(((mm->context.id ^ cpu_last_asid) >> ASID_BITS) == 0)) {
+                cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
+                spin_unlock(&cpu_asid_lock);
+                return;
+        }
+#endif
+        /*
+         * At this point, it is guaranteed that the current mm (with
+         * an old ASID) isn't active on any other CPU since the ASIDs
+         * are changed simultaneously via IPI.
+         */
         asid = ++cpu_last_asid;
         if (asid == 0)
                 asid = cpu_last_asid = ASID_FIRST_VERSION;
@@ -42,20 +143,15 @@ void __new_context(struct mm_struct *mm)
          * to start a new version and flush the TLB.
          */
         if (unlikely((asid & ~ASID_MASK) == 0)) {
-                asid = ++cpu_last_asid;
-                /* set the reserved ASID before flushing the TLB */
-                asm("mcr        p15, 0, %0, c13, c0, 1  @ set reserved context ID\n"
-                    :
-                    : "r" (0));
-                isb();
-                flush_tlb_all();
-                if (icache_is_vivt_asid_tagged()) {
-                        __flush_icache_all();
-                        dsb();
-                }
+                asid = cpu_last_asid + smp_processor_id() + 1;
+                flush_context();
+#ifdef CONFIG_SMP
+                smp_wmb();
+                smp_call_function(reset_context, NULL, 1);
+#endif
+                cpu_last_asid += NR_CPUS;
         }
-        spin_unlock(&cpu_asid_lock);
 
-        cpumask_copy(mm_cpumask(mm), cpumask_of(smp_processor_id()));
-        mm->context.id = asid;
+        set_mm_context(mm, asid);
+        spin_unlock(&cpu_asid_lock);
 }
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
index 70997d5bee2d..5eb4fd93893d 100644
--- a/arch/arm/mm/copypage-feroceon.c
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -68,12 +68,13 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
 }
 
 void feroceon_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         feroceon_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c
index de9c06854ad7..f72303e1d804 100644
--- a/arch/arm/mm/copypage-v3.c
+++ b/arch/arm/mm/copypage-v3.c
@@ -38,7 +38,7 @@ v3_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v3_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 7370a7142b04..598c51ad5071 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -69,7 +69,7 @@ mc_copy_user_page(void *from, void *to)
 }
 
 void v4_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index 9ab098414227..7c2eb55cd4a9 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -48,12 +48,13 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v4wb_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         v4wb_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 300efafd6643..172e6a55458e 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -44,7 +44,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
 }
 
 void v4wt_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index 0fa1319273de..8bca4dea6dfa 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -34,7 +34,7 @@ static DEFINE_SPINLOCK(v6_lock);
  * attack the kernel's existing mapping of these pages.
  */
 static void v6_copy_user_highpage_nonaliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
@@ -81,7 +81,7 @@ static void discard_old_kernel_data(void *kto)
  * Copy the page, taking account of the cache colour.
  */
 static void v6_copy_user_highpage_aliasing(struct page *to,
-        struct page *from, unsigned long vaddr)
+        struct page *from, unsigned long vaddr, struct vm_area_struct *vma)
 {
         unsigned int offset = CACHE_COLOUR(vaddr);
         unsigned long kfrom, kto;
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
index bc4525f5ab23..747ad4140fc7 100644
--- a/arch/arm/mm/copypage-xsc3.c
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -71,12 +71,13 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
 }
 
 void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto, *kfrom;
 
         kto = kmap_atomic(to, KM_USER0);
         kfrom = kmap_atomic(from, KM_USER1);
+        flush_cache_page(vma, vaddr, page_to_pfn(from));
         xsc3_mc_copy_user_page(kto, kfrom);
         kunmap_atomic(kfrom, KM_USER1);
         kunmap_atomic(kto, KM_USER0);
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 76824d3e966a..9920c0ae2096 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -91,7 +91,7 @@ mc_copy_user_page(void *from, void *to)
 }
 
 void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr)
+        unsigned long vaddr, struct vm_area_struct *vma)
 {
         void *kto = kmap_atomic(to, KM_USER1);
 
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 26325cb5d368..0da7eccf7749 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -29,9 +29,6 @@
 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
 #endif
 
-#define CONSISTENT_END  (0xffe00000)
-#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
-
 #define CONSISTENT_OFFSET(x)    (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
@@ -404,78 +401,44 @@ EXPORT_SYMBOL(dma_free_coherent);
  * platforms with CONFIG_DMABOUNCE.
  * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  */
-void dma_cache_maint(const void *start, size_t size, int direction)
+void ___dma_single_cpu_to_dev(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
 {
-        void (*inner_op)(const void *, const void *);
-        void (*outer_op)(unsigned long, unsigned long);
-
-        BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1));
-
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
+        unsigned long paddr;
+
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
 
-        inner_op(start, start + size);
-        outer_op(__pa(start), __pa(start) + size);
+        dmac_map_area(kaddr, size, dir);
+
+        paddr = __pa(kaddr);
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
 }
-EXPORT_SYMBOL(dma_cache_maint);
+EXPORT_SYMBOL(___dma_single_cpu_to_dev);
 
-static void dma_cache_maint_contiguous(struct page *page, unsigned long offset,
-                                       size_t size, int direction)
+void ___dma_single_dev_to_cpu(const void *kaddr, size_t size,
+        enum dma_data_direction dir)
 {
-        void *vaddr;
-        unsigned long paddr;
-        void (*inner_op)(const void *, const void *);
-        void (*outer_op)(unsigned long, unsigned long);
-
-        switch (direction) {
-        case DMA_FROM_DEVICE:           /* invalidate only */
-                inner_op = dmac_inv_range;
-                outer_op = outer_inv_range;
-                break;
-        case DMA_TO_DEVICE:             /* writeback only */
-                inner_op = dmac_clean_range;
-                outer_op = outer_clean_range;
-                break;
-        case DMA_BIDIRECTIONAL:         /* writeback and invalidate */
-                inner_op = dmac_flush_range;
-                outer_op = outer_flush_range;
-                break;
-        default:
-                BUG();
-        }
+        BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1));
 
-        if (!PageHighMem(page)) {
-                vaddr = page_address(page) + offset;
-                inner_op(vaddr, vaddr + size);
-        } else {
-                vaddr = kmap_high_get(page);
-                if (vaddr) {
-                        vaddr += offset;
-                        inner_op(vaddr, vaddr + size);
-                        kunmap_high(page);
-                }
+        /* FIXME: non-speculating: not required */
+        /* don't bother invalidating if DMA to device */
+        if (dir != DMA_TO_DEVICE) {
+                unsigned long paddr = __pa(kaddr);
+                outer_inv_range(paddr, paddr + size);
         }
 
-        paddr = page_to_phys(page) + offset;
-        outer_op(paddr, paddr + size);
+        dmac_unmap_area(kaddr, size, dir);
 }
+EXPORT_SYMBOL(___dma_single_dev_to_cpu);
 
-void dma_cache_maint_page(struct page *page, unsigned long offset,
-                          size_t size, int dir)
+static void dma_cache_maint_page(struct page *page, unsigned long offset,
+        size_t size, enum dma_data_direction dir,
+        void (*op)(const void *, size_t, int))
 {
         /*
          * A single sg entry may refer to multiple physically contiguous
@@ -486,20 +449,62 @@ void dma_cache_maint_page(struct page *page, unsigned long offset,
         size_t left = size;
         do {
                 size_t len = left;
-                if (PageHighMem(page) && len + offset > PAGE_SIZE) {
-                        if (offset >= PAGE_SIZE) {
-                                page += offset / PAGE_SIZE;
-                                offset %= PAGE_SIZE;
+                void *vaddr;
+
+                if (PageHighMem(page)) {
+                        if (len + offset > PAGE_SIZE) {
+                                if (offset >= PAGE_SIZE) {
+                                        page += offset / PAGE_SIZE;
+                                        offset %= PAGE_SIZE;
+                                }
+                                len = PAGE_SIZE - offset;
                         }
-                        len = PAGE_SIZE - offset;
+                        vaddr = kmap_high_get(page);
+                        if (vaddr) {
+                                vaddr += offset;
+                                op(vaddr, len, dir);
+                                kunmap_high(page);
+                        }
+                } else {
+                        vaddr = page_address(page) + offset;
+                        op(vaddr, len, dir);
                 }
-                dma_cache_maint_contiguous(page, offset, len, dir);
                 offset = 0;
                 page++;
                 left -= len;
         } while (left);
 }
-EXPORT_SYMBOL(dma_cache_maint_page);
+
+void ___dma_page_cpu_to_dev(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr;
+
+        dma_cache_maint_page(page, off, size, dir, dmac_map_area);
+
+        paddr = page_to_phys(page) + off;
+        if (dir == DMA_FROM_DEVICE) {
+                outer_inv_range(paddr, paddr + size);
+        } else {
+                outer_clean_range(paddr, paddr + size);
+        }
+        /* FIXME: non-speculating: flush on bidirectional mappings? */
+}
+EXPORT_SYMBOL(___dma_page_cpu_to_dev);
+
+void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
+        size_t size, enum dma_data_direction dir)
+{
+        unsigned long paddr = page_to_phys(page) + off;
+
+        /* FIXME: non-speculating: not required */
+        /* don't bother invalidating if DMA to device */
+        if (dir != DMA_TO_DEVICE)
+                outer_inv_range(paddr, paddr + size);
+
+        dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+}
+EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
 /**
  * dma_map_sg - map a set of SG buffers for streaming mode DMA
@@ -573,8 +578,12 @@ void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
         int i;
 
         for_each_sg(sg, s, nents, i) {
-                dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
-                                        sg_dma_len(s), dir);
+                if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0,
+                                            sg_dma_len(s), dir))
+                        continue;
+
+                __dma_page_dev_to_cpu(sg_page(s), s->offset,
+                                      s->length, dir);
         }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_cpu);
@@ -597,9 +606,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
                                         sg_dma_len(s), dir))
                         continue;
 
-                if (!arch_is_coherent())
-                        dma_cache_maint_page(sg_page(s), s->offset,
-                                             s->length, dir);
+                __dma_page_cpu_to_dev(sg_page(s), s->offset,
+                                      s->length, dir);
         }
 }
 EXPORT_SYMBOL(dma_sync_sg_for_device);
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 56ee15321b00..c9b97e9836a2 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -36,28 +36,12 @@ static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
  * Therefore those configurations which might call adjust_pte (those
  * without CONFIG_CPU_CACHE_VIPT) cannot support split page_table_lock.
  */
-static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
+static int do_adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn, pte_t *ptep)
 {
-        pgd_t *pgd;
-        pmd_t *pmd;
-        pte_t *pte, entry;
+        pte_t entry = *ptep;
         int ret;
 
-        pgd = pgd_offset(vma->vm_mm, address);
-        if (pgd_none(*pgd))
-                goto no_pgd;
-        if (pgd_bad(*pgd))
-                goto bad_pgd;
-
-        pmd = pmd_offset(pgd, address);
-        if (pmd_none(*pmd))
-                goto no_pmd;
-        if (pmd_bad(*pmd))
-                goto bad_pmd;
-
-        pte = pte_offset_map(pmd, address);
-        entry = *pte;
-
         /*
          * If this page is present, it's actually being shared.
          */
@@ -68,33 +52,55 @@ static int adjust_pte(struct vm_area_struct *vma, unsigned long address)
          * fault (ie, is old), we can safely ignore any issues.
          */
         if (ret && (pte_val(entry) & L_PTE_MT_MASK) != shared_pte_mask) {
-                unsigned long pfn = pte_pfn(entry);
                 flush_cache_page(vma, address, pfn);
                 outer_flush_range((pfn << PAGE_SHIFT),
                                   (pfn << PAGE_SHIFT) + PAGE_SIZE);
                 pte_val(entry) &= ~L_PTE_MT_MASK;
                 pte_val(entry) |= shared_pte_mask;
-                set_pte_at(vma->vm_mm, address, pte, entry);
+                set_pte_at(vma->vm_mm, address, ptep, entry);
                 flush_tlb_page(vma, address);
         }
-        pte_unmap(pte);
+
         return ret;
+}
+
+static int adjust_pte(struct vm_area_struct *vma, unsigned long address,
+        unsigned long pfn)
+{
+        spinlock_t *ptl;
+        pgd_t *pgd;
+        pmd_t *pmd;
+        pte_t *pte;
+        int ret;
+
+        pgd = pgd_offset(vma->vm_mm, address);
+        if (pgd_none_or_clear_bad(pgd))
+                return 0;
+
+        pmd = pmd_offset(pgd, address);
+        if (pmd_none_or_clear_bad(pmd))
+                return 0;
 
-bad_pgd:
-        pgd_ERROR(*pgd);
-        pgd_clear(pgd);
-no_pgd:
-        return 0;
-
-bad_pmd:
-        pmd_ERROR(*pmd);
-        pmd_clear(pmd);
-no_pmd:
-        return 0;
+        /*
+         * This is called while another page table is mapped, so we
+         * must use the nested version.  This also means we need to
+         * open-code the spin-locking.
+         */
+        ptl = pte_lockptr(vma->vm_mm, pmd);
+        pte = pte_offset_map_nested(pmd, address);
+        spin_lock(ptl);
+
+        ret = do_adjust_pte(vma, address, pfn, pte);
+
+        spin_unlock(ptl);
+        pte_unmap_nested(pte);
+
+        return ret;
 }
 
 static void
-make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
+make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
+        unsigned long addr, pte_t *ptep, unsigned long pfn)
 {
         struct mm_struct *mm = vma->vm_mm;
         struct vm_area_struct *mpnt;
@@ -122,11 +128,11 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
                 if (!(mpnt->vm_flags & VM_MAYSHARE))
                         continue;
                 offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;
-                aliases += adjust_pte(mpnt, mpnt->vm_start + offset);
+                aliases += adjust_pte(mpnt, mpnt->vm_start + offset, pfn);
         }
         flush_dcache_mmap_unlock(mapping);
         if (aliases)
-                adjust_pte(vma, addr);
+                do_adjust_pte(vma, addr, pfn, ptep);
         else
                 flush_cache_page(vma, addr, pfn);
 }
@@ -144,9 +150,10 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma, unsigne
  *
  * Note that the pte lock will be held.
  */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
+        pte_t *ptep)
 {
-        unsigned long pfn = pte_pfn(pte);
+        unsigned long pfn = pte_pfn(*ptep);
         struct address_space *mapping;
         struct page *page;
 
@@ -168,7 +175,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
 #endif
         if (mapping) {
                 if (cache_is_vivt())
-                        make_coherent(mapping, vma, addr, pfn);
+                        make_coherent(mapping, vma, addr, ptep, pfn);
                 else if (vma->vm_flags & VM_EXEC)
                         __flush_icache_all();
         }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 10e06801afb3..9d40c341e07e 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -18,6 +18,7 @@
 #include <linux/page-flags.h>
 #include <linux/sched.h>
 #include <linux/highmem.h>
+#include <linux/perf_event.h>
 
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -302,6 +303,12 @@ do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
         fault = __do_page_fault(mm, addr, fsr, tsk);
         up_read(&mm->mmap_sem);
 
+        perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, addr);
+        if (fault & VM_FAULT_MAJOR)
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0, regs, addr);
+        else if (fault & VM_FAULT_MINOR)
+                perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0, regs, addr);
+
         /*
          * Handle the "normal" case first - VM_FAULT_MAJOR / VM_FAULT_MINOR
          */
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 6f3a4b7a3b82..e34f095e2090 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -13,6 +13,7 @@
 
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
+#include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
 
@@ -87,13 +88,26 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
         if (vma->vm_flags & VM_EXEC && icache_is_vivt_asid_tagged())
                 __flush_icache_all();
 }
+#else
+#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+#endif
 
+#ifdef CONFIG_SMP
+static void flush_ptrace_access_other(void *args)
+{
+        __flush_icache_all();
+}
+#endif
+
+static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
-                         unsigned long uaddr, void *kaddr,
-                         unsigned long len, int write)
+                         unsigned long uaddr, void *kaddr, unsigned long len)
 {
         if (cache_is_vivt()) {
-                vivt_flush_ptrace_access(vma, page, uaddr, kaddr, len, write);
+                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                        unsigned long addr = (unsigned long)kaddr;
+                        __cpuc_coherent_kern_range(addr, addr + len);
+                }
                 return;
         }
 
@@ -104,16 +118,37 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
         }
 
         /* VIPT non-aliasing cache */
-        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)) &&
-            vma->vm_flags & VM_EXEC) {
+        if (vma->vm_flags & VM_EXEC) {
                 unsigned long addr = (unsigned long)kaddr;
-                /* only flushing the kernel mapping on non-aliasing VIPT */
                 __cpuc_coherent_kern_range(addr, addr + len);
+#ifdef CONFIG_SMP
+                if (cache_ops_need_broadcast())
+                        smp_call_function(flush_ptrace_access_other,
+                                          NULL, 1);
+#endif
         }
 }
-#else
-#define flush_pfn_alias(pfn,vaddr)      do { } while (0)
+
+/*
+ * Copy user data from/to a page which is mapped into a different
+ * processes address space.  Really, we want to allow our "user
+ * space" model to handle this.
+ *
+ * Note that this code needs to run on the current CPU.
+ */
+void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
+                       unsigned long uaddr, void *dst, const void *src,
+                       unsigned long len)
+{
+#ifdef CONFIG_SMP
+        preempt_disable();
 #endif
+        memcpy(dst, src, len);
+        flush_ptrace_access(vma, page, uaddr, dst, len);
+#ifdef CONFIG_SMP
+        preempt_enable();
+#endif
+}
 
 void __flush_dcache_page(struct address_space *mapping, struct page *page)
 {
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index a04ffbbbe253..7829cb5425f5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -23,6 +23,7 @@
 #include <asm/setup.h>
 #include <asm/sizes.h>
 #include <asm/tlb.h>
+#include <asm/fixmap.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -32,19 +33,21 @@
 static unsigned long phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
 
-static void __init early_initrd(char **p)
+static int __init early_initrd(char *p)
 {
         unsigned long start, size;
+        char *endp;
 
-        start = memparse(*p, p);
-        if (**p == ',') {
-                size = memparse((*p) + 1, p);
+        start = memparse(p, &endp);
+        if (*endp == ',') {
+                size = memparse(endp + 1, NULL);
 
                 phys_initrd_start = start;
                 phys_initrd_size = size;
         }
+        return 0;
 }
-__early_param("initrd=", early_initrd);
+early_param("initrd", early_initrd);
 
 static int __init parse_tag_initrd(const struct tag *tag)
 {
@@ -560,7 +563,7 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
  */
 void __init mem_init(void)
 {
-        unsigned int codesize, datasize, initsize;
+        unsigned long reserved_pages, free_pages;
         int i, node;
 
 #ifndef CONFIG_DISCONTIGMEM
@@ -596,6 +599,33 @@ void __init mem_init(void)
         totalram_pages += totalhigh_pages;
 #endif
 
+        reserved_pages = free_pages = 0;
+
+        for_each_online_node(node) {
+                pg_data_t *n = NODE_DATA(node);
+                struct page *map = pgdat_page_nr(n, 0) - n->node_start_pfn;
+
+                for_each_nodebank(i, &meminfo, node) {
+                        struct membank *bank = &meminfo.bank[i];
+                        unsigned int pfn1, pfn2;
+                        struct page *page, *end;
+
+                        pfn1 = bank_pfn_start(bank);
+                        pfn2 = bank_pfn_end(bank);
+
+                        page = map + pfn1;
+                        end  = map + pfn2;
+
+                        do {
+                                if (PageReserved(page))
+                                        reserved_pages++;
+                                else if (!page_count(page))
+                                        free_pages++;
+                                page++;
+                        } while (page < end);
+                }
+        }
+
         /*
          * Since our memory may not be contiguous, calculate the
          * real number of pages we have in this system
@@ -608,16 +638,71 @@ void __init mem_init(void)
         }
         printk(" = %luMB total\n", num_physpages >> (20 - PAGE_SHIFT));
 
-        codesize = _etext - _text;
-        datasize = _end - _data;
-        initsize = __init_end - __init_begin;
-
-        printk(KERN_NOTICE "Memory: %luKB available (%dK code, "
-                "%dK data, %dK init, %luK highmem)\n",
-                nr_free_pages() << (PAGE_SHIFT-10), codesize >> 10,
-                datasize >> 10, initsize >> 10,
+        printk(KERN_NOTICE "Memory: %luk/%luk available, %luk reserved, %luK highmem\n",
+                nr_free_pages() << (PAGE_SHIFT-10),
+                free_pages << (PAGE_SHIFT-10),
+                reserved_pages << (PAGE_SHIFT-10),
                 totalhigh_pages << (PAGE_SHIFT-10));
 
+#define MLK(b, t) b, t, ((t) - (b)) >> 10
+#define MLM(b, t) b, t, ((t) - (b)) >> 20
+#define MLK_ROUNDUP(b, t) b, t, DIV_ROUND_UP(((t) - (b)), SZ_1K)
+
+        printk(KERN_NOTICE "Virtual kernel memory layout:\n"
+                        "    vector  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+                        "    fixmap  : 0x%08lx - 0x%08lx   (%4ld kB)\n"
+#ifdef CONFIG_MMU
+                        "    DMA     : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#endif
+                        "    vmalloc : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+                        "    lowmem  : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#ifdef CONFIG_HIGHMEM
+                        "    pkmap   : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+#endif
+                        "    modules : 0x%08lx - 0x%08lx   (%4ld MB)\n"
+                        "      .init : 0x%p" " - 0x%p" "   (%4d kB)\n"
+                        "      .text : 0x%p" " - 0x%p" "   (%4d kB)\n"
+                        "      .data : 0x%p" " - 0x%p" "   (%4d kB)\n",
+
+                        MLK(UL(CONFIG_VECTORS_BASE), UL(CONFIG_VECTORS_BASE) +
+                                (PAGE_SIZE)),
+                        MLK(FIXADDR_START, FIXADDR_TOP),
+#ifdef CONFIG_MMU
+                        MLM(CONSISTENT_BASE, CONSISTENT_END),
+#endif
+                        MLM(VMALLOC_START, VMALLOC_END),
+                        MLM(PAGE_OFFSET, (unsigned long)high_memory),
+#ifdef CONFIG_HIGHMEM
+                        MLM(PKMAP_BASE, (PKMAP_BASE) + (LAST_PKMAP) *
+                                (PAGE_SIZE)),
+#endif
+                        MLM(MODULES_VADDR, MODULES_END),
+
+                        MLK_ROUNDUP(__init_begin, __init_end),
+                        MLK_ROUNDUP(_text, _etext),
+                        MLK_ROUNDUP(_data, _edata));
+
+#undef MLK
+#undef MLM
+#undef MLK_ROUNDUP
+
+        /*
+         * Check boundaries twice: Some fundamental inconsistencies can
+         * be detected at build time already.
+         */
+#ifdef CONFIG_MMU
+        BUILD_BUG_ON(VMALLOC_END                        > CONSISTENT_BASE);
+        BUG_ON(VMALLOC_END                              > CONSISTENT_BASE);
+
+        BUILD_BUG_ON(TASK_SIZE                          > MODULES_VADDR);
+        BUG_ON(TASK_SIZE                                > MODULES_VADDR);
+#endif
+
+#ifdef CONFIG_HIGHMEM
+        BUILD_BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE > PAGE_OFFSET);
+        BUG_ON(PKMAP_BASE + LAST_PKMAP * PAGE_SIZE      > PAGE_OFFSET);
+#endif
+
         if (PAGE_SIZE >= 16384 && num_physpages <= 128) {
                 extern int sysctl_overcommit_memory;
                 /*
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 0ab75c60f7cf..28c8b950ef04 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -139,8 +139,8 @@ void __check_kvm_seq(struct mm_struct *mm)
  * which requires the new ioremap'd region to be referenced, the CPU will
  * reference the _old_ region.
  *
- * Note that get_vm_area() allocates a guard 4K page, so we need to mask
- * the size back to 1MB aligned or we will overflow in the loop below.
+ * Note that get_vm_area_caller() allocates a guard 4K page, so we need to
+ * mask the size back to 1MB aligned or we will overflow in the loop below.
  */
 static void unmap_area_sections(unsigned long virt, unsigned long size)
 {
@@ -254,22 +254,8 @@ remap_area_supersections(unsigned long virt, unsigned long pfn,
 }
 #endif
 
-
-/*
- * Remap an arbitrary physical address space into the kernel virtual
- * address space. Needed when the kernel wants to access high addresses
- * directly.
- *
- * NOTE! We need to allow non-page-aligned mappings too: we will obviously
- * have to convert them into an offset in a page-aligned mapping, but the
- * caller shouldn't need to know that small detail.
- *
- * 'flags' are the extra L_PTE_ flags that you want to specify for this
- * mapping.  See <asm/pgtable.h> for more information.
- */
-void __iomem *
-__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
-                  unsigned int mtype)
+void __iomem * __arm_ioremap_pfn_caller(unsigned long pfn,
+        unsigned long offset, size_t size, unsigned int mtype, void *caller)
 {
         const struct mem_type *type;
         int err;
@@ -291,7 +277,7 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
          */
         size = PAGE_ALIGN(offset + size);
 
-        area = get_vm_area(size, VM_IOREMAP);
+        area = get_vm_area_caller(size, VM_IOREMAP, caller);
         if (!area)
                 return NULL;
         addr = (unsigned long)area->addr;
@@ -318,10 +304,9 @@ __arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
         flush_cache_vmap(addr, addr + size);
         return (void __iomem *) (offset + addr);
 }
-EXPORT_SYMBOL(__arm_ioremap_pfn);
 
-void __iomem *
-__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+void __iomem *__arm_ioremap_caller(unsigned long phys_addr, size_t size,
+        unsigned int mtype, void *caller)
 {
         unsigned long last_addr;
         unsigned long offset = phys_addr & ~PAGE_MASK;
@@ -334,7 +319,33 @@ __arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
         if (!size || last_addr < phys_addr)
                 return NULL;
 
-        return __arm_ioremap_pfn(pfn, offset, size, mtype);
+        return __arm_ioremap_pfn_caller(pfn, offset, size, mtype,
+                        caller);
+}
+
+/*
+ * Remap an arbitrary physical address space into the kernel virtual
+ * address space. Needed when the kernel wants to access high addresses
+ * directly.
+ *
+ * NOTE! We need to allow non-page-aligned mappings too: we will obviously
+ * have to convert them into an offset in a page-aligned mapping, but the
+ * caller shouldn't need to know that small detail.
+ */
+void __iomem *
+__arm_ioremap_pfn(unsigned long pfn, unsigned long offset, size_t size,
+                  unsigned int mtype)
+{
+        return __arm_ioremap_pfn_caller(pfn, offset, size, mtype,
+                        __builtin_return_address(0));
+}
+EXPORT_SYMBOL(__arm_ioremap_pfn);
+
+void __iomem *
+__arm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+{
+        return __arm_ioremap_caller(phys_addr, size, mtype,
+                        __builtin_return_address(0));
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 761ffede6a23..9d4da6ac28eb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -100,18 +100,17 @@ static struct cachepolicy cache_policies[] __initdata = {
  * writebuffer to be turned off.  (Note: the write
  * buffer should not be on and the cache off).
  */
-static void __init early_cachepolicy(char **p)
+static int __init early_cachepolicy(char *p)
 {
         int i;
 
         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
                 int len = strlen(cache_policies[i].policy);
 
-                if (memcmp(*p, cache_policies[i].policy, len) == 0) {
+                if (memcmp(p, cache_policies[i].policy, len) == 0) {
                         cachepolicy = i;
                         cr_alignment &= ~cache_policies[i].cr_mask;
                         cr_no_alignment &= ~cache_policies[i].cr_mask;
-                        *p += len;
                         break;
                 }
         }
@@ -130,36 +129,37 @@ static void __init early_cachepolicy(char **p)
         }
         flush_cache_all();
         set_cr(cr_alignment);
+        return 0;
 }
-__early_param("cachepolicy=", early_cachepolicy);
+early_param("cachepolicy", early_cachepolicy);
 
-static void __init early_nocache(char **__unused)
+static int __init early_nocache(char *__unused)
 {
         char *p = "buffered";
         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
-        early_cachepolicy(&p);
+        early_cachepolicy(p);
+        return 0;
 }
-__early_param("nocache", early_nocache);
+early_param("nocache", early_nocache);
 
-static void __init early_nowrite(char **__unused)
+static int __init early_nowrite(char *__unused)
 {
         char *p = "uncached";
         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
-        early_cachepolicy(&p);
+        early_cachepolicy(p);
+        return 0;
 }
-__early_param("nowb", early_nowrite);
+early_param("nowb", early_nowrite);
 
-static void __init early_ecc(char **p)
+static int __init early_ecc(char *p)
 {
-        if (memcmp(*p, "on", 2) == 0) {
+        if (memcmp(p, "on", 2) == 0)
                 ecc_mask = PMD_PROTECTION;
-                *p += 2;
-        } else if (memcmp(*p, "off", 3) == 0) {
+        else if (memcmp(p, "off", 3) == 0)
                 ecc_mask = 0;
-                *p += 3;
-        }
+        return 0;
 }
-__early_param("ecc=", early_ecc);
+early_param("ecc", early_ecc);
 
 static int __init noalign_setup(char *__unused)
 {
@@ -670,9 +670,9 @@ static unsigned long __initdata vmalloc_reserve = SZ_128M;
  * bytes. This can be used to increase (or decrease) the vmalloc
  * area - the default is 128m.
  */
-static void __init early_vmalloc(char **arg)
+static int __init early_vmalloc(char *arg)
 {
-        vmalloc_reserve = memparse(*arg, arg);
+        vmalloc_reserve = memparse(arg, NULL);
 
         if (vmalloc_reserve < SZ_16M) {
                 vmalloc_reserve = SZ_16M;
@@ -687,8 +687,9 @@ static void __init early_vmalloc(char **arg)
                         "vmalloc area is too big, limiting to %luMB\n",
                         vmalloc_reserve >> 20);
         }
+        return 0;
 }
-__early_param("vmalloc=", early_vmalloc);
+early_param("vmalloc", early_vmalloc);
 
 #define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
 
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 374a8311bc84..9bfeb6b9509a 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -74,6 +74,12 @@ void __iomem *__arm_ioremap_pfn(unsigned long pfn, unsigned long offset,
 }
 EXPORT_SYMBOL(__arm_ioremap_pfn);
 
+void __iomem *__arm_ioremap_pfn_caller(unsigned long pfn, unsigned long offset,
+                           size_t size, unsigned int mtype, void *caller)
+{
+        return __arm_ioremap_pfn(pfn, offset, size, mtype);
+}
+
 void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
                             unsigned int mtype)
 {
@@ -81,6 +87,12 @@ void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
 }
 EXPORT_SYMBOL(__arm_ioremap);
 
+void __iomem *__arm_ioremap(unsigned long phys_addr, size_t size,
+                            unsigned int mtype, void *caller)
+{
+        return __arm_ioremap(phys_addr, size, mtype);
+}
+
 void __iounmap(volatile void __iomem *addr)
 {
 }
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 8012e24282b2..72507c630ceb 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -265,7 +265,7 @@ ENTRY(arm1020_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020_dma_inv_range)
+arm1020_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -295,7 +295,7 @@ ENTRY(arm1020_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020_dma_clean_range)
+arm1020_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -330,6 +330,30 @@ ENTRY(arm1020_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020_dma_clean_range
+        bcs     arm1020_dma_inv_range
+        b       arm1020_dma_flush_range
+ENDPROC(arm1020_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020_dma_unmap_area)
+
 ENTRY(arm1020_cache_fns)
         .long   arm1020_flush_kern_cache_all
         .long   arm1020_flush_user_cache_all
@@ -337,8 +361,8 @@ ENTRY(arm1020_cache_fns)
         .long   arm1020_coherent_kern_range
         .long   arm1020_coherent_user_range
         .long   arm1020_flush_kern_dcache_area
-        .long   arm1020_dma_inv_range
-        .long   arm1020_dma_clean_range
+        .long   arm1020_dma_map_area
+        .long   arm1020_dma_unmap_area
         .long   arm1020_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 41fe25d234f5..d27829805609 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -258,7 +258,7 @@ ENTRY(arm1020e_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020e_dma_inv_range)
+arm1020e_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -284,7 +284,7 @@ ENTRY(arm1020e_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1020e_dma_clean_range)
+arm1020e_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -316,6 +316,30 @@ ENTRY(arm1020e_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1020e_dma_clean_range
+        bcs     arm1020e_dma_inv_range
+        b       arm1020e_dma_flush_range
+ENDPROC(arm1020e_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1020e_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1020e_dma_unmap_area)
+
 ENTRY(arm1020e_cache_fns)
         .long   arm1020e_flush_kern_cache_all
         .long   arm1020e_flush_user_cache_all
@@ -323,8 +347,8 @@ ENTRY(arm1020e_cache_fns)
         .long   arm1020e_coherent_kern_range
         .long   arm1020e_coherent_user_range
         .long   arm1020e_flush_kern_dcache_area
-        .long   arm1020e_dma_inv_range
-        .long   arm1020e_dma_clean_range
+        .long   arm1020e_dma_map_area
+        .long   arm1020e_dma_unmap_area
         .long   arm1020e_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 20a5b1b31a70..ce13e4a827de 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -247,7 +247,7 @@ ENTRY(arm1022_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1022_dma_inv_range)
+arm1022_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -273,7 +273,7 @@ ENTRY(arm1022_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1022_dma_clean_range)
+arm1022_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -305,6 +305,30 @@ ENTRY(arm1022_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1022_dma_clean_range
+        bcs     arm1022_dma_inv_range
+        b       arm1022_dma_flush_range
+ENDPROC(arm1022_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1022_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1022_dma_unmap_area)
+
 ENTRY(arm1022_cache_fns)
         .long   arm1022_flush_kern_cache_all
         .long   arm1022_flush_user_cache_all
@@ -312,8 +336,8 @@ ENTRY(arm1022_cache_fns)
         .long   arm1022_coherent_kern_range
         .long   arm1022_coherent_user_range
         .long   arm1022_flush_kern_dcache_area
-        .long   arm1022_dma_inv_range
-        .long   arm1022_dma_clean_range
+        .long   arm1022_dma_map_area
+        .long   arm1022_dma_unmap_area
         .long   arm1022_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 96aedb10fcc4..636672a29c6d 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -241,7 +241,7 @@ ENTRY(arm1026_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm1026_dma_inv_range)
+arm1026_dma_inv_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         tst     r0, #CACHE_DLINESIZE - 1
@@ -267,7 +267,7 @@ ENTRY(arm1026_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm1026_dma_clean_range)
+arm1026_dma_clean_range:
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_DISABLE
         bic     r0, r0, #CACHE_DLINESIZE - 1
@@ -299,6 +299,30 @@ ENTRY(arm1026_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm1026_dma_clean_range
+        bcs     arm1026_dma_inv_range
+        b       arm1026_dma_flush_range
+ENDPROC(arm1026_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm1026_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm1026_dma_unmap_area)
+
 ENTRY(arm1026_cache_fns)
         .long   arm1026_flush_kern_cache_all
         .long   arm1026_flush_user_cache_all
@@ -306,8 +330,8 @@ ENTRY(arm1026_cache_fns)
         .long   arm1026_coherent_kern_range
         .long   arm1026_coherent_user_range
         .long   arm1026_flush_kern_dcache_area
-        .long   arm1026_dma_inv_range
-        .long   arm1026_dma_clean_range
+        .long   arm1026_dma_map_area
+        .long   arm1026_dma_unmap_area
         .long   arm1026_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 471669e2d7cb..8be81992645d 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -239,7 +239,7 @@ ENTRY(arm920_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm920_dma_inv_range)
+arm920_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -262,7 +262,7 @@ ENTRY(arm920_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm920_dma_clean_range)
+arm920_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -288,6 +288,30 @@ ENTRY(arm920_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm920_dma_clean_range
+        bcs     arm920_dma_inv_range
+        b       arm920_dma_flush_range
+ENDPROC(arm920_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm920_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm920_dma_unmap_area)
+
 ENTRY(arm920_cache_fns)
         .long   arm920_flush_kern_cache_all
         .long   arm920_flush_user_cache_all
@@ -295,8 +319,8 @@ ENTRY(arm920_cache_fns)
         .long   arm920_coherent_kern_range
         .long   arm920_coherent_user_range
         .long   arm920_flush_kern_dcache_area
-        .long   arm920_dma_inv_range
-        .long   arm920_dma_clean_range
+        .long   arm920_dma_map_area
+        .long   arm920_dma_unmap_area
         .long   arm920_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index ee111b00fa41..c0ff8e4b1074 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -241,7 +241,7 @@ ENTRY(arm922_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm922_dma_inv_range)
+arm922_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -264,7 +264,7 @@ ENTRY(arm922_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm922_dma_clean_range)
+arm922_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -290,6 +290,30 @@ ENTRY(arm922_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm922_dma_clean_range
+        bcs     arm922_dma_inv_range
+        b       arm922_dma_flush_range
+ENDPROC(arm922_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm922_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm922_dma_unmap_area)
+
 ENTRY(arm922_cache_fns)
         .long   arm922_flush_kern_cache_all
         .long   arm922_flush_user_cache_all
@@ -297,8 +321,8 @@ ENTRY(arm922_cache_fns)
         .long   arm922_coherent_kern_range
         .long   arm922_coherent_user_range
         .long   arm922_flush_kern_dcache_area
-        .long   arm922_dma_inv_range
-        .long   arm922_dma_clean_range
+        .long   arm922_dma_map_area
+        .long   arm922_dma_unmap_area
         .long   arm922_dma_flush_range
 
 #endif
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 8deb5bde58e4..3c6cffe400f6 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -283,7 +283,7 @@ ENTRY(arm925_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_inv_range)
+arm925_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -308,7 +308,7 @@ ENTRY(arm925_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm925_dma_clean_range)
+arm925_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -341,6 +341,30 @@ ENTRY(arm925_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm925_dma_clean_range
+        bcs     arm925_dma_inv_range
+        b       arm925_dma_flush_range
+ENDPROC(arm925_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm925_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm925_dma_unmap_area)
+
 ENTRY(arm925_cache_fns)
         .long   arm925_flush_kern_cache_all
         .long   arm925_flush_user_cache_all
@@ -348,8 +372,8 @@ ENTRY(arm925_cache_fns)
         .long   arm925_coherent_kern_range
         .long   arm925_coherent_user_range
         .long   arm925_flush_kern_dcache_area
-        .long   arm925_dma_inv_range
-        .long   arm925_dma_clean_range
+        .long   arm925_dma_map_area
+        .long   arm925_dma_unmap_area
         .long   arm925_dma_flush_range
 
 ENTRY(cpu_arm925_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 64db6e275a44..75b707c9cce1 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -246,7 +246,7 @@ ENTRY(arm926_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(arm926_dma_inv_range)
+arm926_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -271,7 +271,7 @@ ENTRY(arm926_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(arm926_dma_clean_range)
+arm926_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -304,6 +304,30 @@ ENTRY(arm926_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm926_dma_clean_range
+        bcs     arm926_dma_inv_range
+        b       arm926_dma_flush_range
+ENDPROC(arm926_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm926_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm926_dma_unmap_area)
+
 ENTRY(arm926_cache_fns)
         .long   arm926_flush_kern_cache_all
         .long   arm926_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(arm926_cache_fns)
         .long   arm926_coherent_kern_range
         .long   arm926_coherent_user_range
         .long   arm926_flush_kern_dcache_area
-        .long   arm926_dma_inv_range
-        .long   arm926_dma_clean_range
+        .long   arm926_dma_map_area
+        .long   arm926_dma_unmap_area
         .long   arm926_dma_flush_range
 
 ENTRY(cpu_arm926_dcache_clean_area)
diff --git a/arch/arm/mm/proc-arm940.S b/arch/arm/mm/proc-arm940.S
index 8196b9f401fb..1af1657819eb 100644
--- a/arch/arm/mm/proc-arm940.S
+++ b/arch/arm/mm/proc-arm940.S
@@ -171,7 +171,7 @@ ENTRY(arm940_flush_kern_dcache_area)
  *      - start - virtual start address
  *      - end   - virtual end address
  */
-ENTRY(arm940_dma_inv_range)
+arm940_dma_inv_range:
         mov     ip, #0
         mov     r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
 1:      orr     r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
@@ -192,7 +192,7 @@ ENTRY(arm940_dma_inv_range)
  *      - start - virtual start address
  *      - end   - virtual end address
  */
-ENTRY(arm940_dma_clean_range)
+arm940_dma_clean_range:
 ENTRY(cpu_arm940_dcache_clean_area)
         mov     ip, #0
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
@@ -233,6 +233,30 @@ ENTRY(arm940_dma_flush_range)
         mcr     p15, 0, ip, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm940_dma_clean_range
+        bcs     arm940_dma_inv_range
+        b       arm940_dma_flush_range
+ENDPROC(arm940_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm940_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm940_dma_unmap_area)
+
 ENTRY(arm940_cache_fns)
         .long   arm940_flush_kern_cache_all
         .long   arm940_flush_user_cache_all
@@ -240,8 +264,8 @@ ENTRY(arm940_cache_fns)
         .long   arm940_coherent_kern_range
         .long   arm940_coherent_user_range
         .long   arm940_flush_kern_dcache_area
-        .long   arm940_dma_inv_range
-        .long   arm940_dma_clean_range
+        .long   arm940_dma_map_area
+        .long   arm940_dma_unmap_area
         .long   arm940_dma_flush_range
 
         __INIT
diff --git a/arch/arm/mm/proc-arm946.S b/arch/arm/mm/proc-arm946.S
index 9a951239c86c..1664b6aaff79 100644
--- a/arch/arm/mm/proc-arm946.S
+++ b/arch/arm/mm/proc-arm946.S
@@ -215,7 +215,7 @@ ENTRY(arm946_flush_kern_dcache_area)
  *      - end   - virtual end address
  * (same as arm926)
  */
-ENTRY(arm946_dma_inv_range)
+arm946_dma_inv_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -240,7 +240,7 @@ ENTRY(arm946_dma_inv_range)
  *
  * (same as arm926)
  */
-ENTRY(arm946_dma_clean_range)
+arm946_dma_clean_range:
 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -275,6 +275,30 @@ ENTRY(arm946_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     arm946_dma_clean_range
+        bcs     arm946_dma_inv_range
+        b       arm946_dma_flush_range
+ENDPROC(arm946_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(arm946_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(arm946_dma_unmap_area)
+
 ENTRY(arm946_cache_fns)
         .long   arm946_flush_kern_cache_all
         .long   arm946_flush_user_cache_all
@@ -282,8 +306,8 @@ ENTRY(arm946_cache_fns)
         .long   arm946_coherent_kern_range
         .long   arm946_coherent_user_range
         .long   arm946_flush_kern_dcache_area
-        .long   arm946_dma_inv_range
-        .long   arm946_dma_clean_range
+        .long   arm946_dma_map_area
+        .long   arm946_dma_unmap_area
         .long   arm946_dma_flush_range
 
 
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index dbc39383e66a..53e632343849 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -274,7 +274,7 @@ ENTRY(feroceon_range_flush_kern_dcache_area)
  * (same as v4wb)
  */
         .align  5
-ENTRY(feroceon_dma_inv_range)
+feroceon_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         bic     r0, r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -288,7 +288,7 @@ ENTRY(feroceon_dma_inv_range)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_dma_inv_range)
+feroceon_range_dma_inv_range:
         mrs     r2, cpsr
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -314,7 +314,7 @@ ENTRY(feroceon_range_dma_inv_range)
  * (same as v4wb)
  */
         .align  5
-ENTRY(feroceon_dma_clean_range)
+feroceon_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -324,7 +324,7 @@ ENTRY(feroceon_dma_clean_range)
         mov     pc, lr
 
         .align  5
-ENTRY(feroceon_range_dma_clean_range)
+feroceon_range_dma_clean_range:
         mrs     r2, cpsr
         cmp     r1, r0
         subne   r1, r1, #1                      @ top address is inclusive
@@ -367,6 +367,44 @@ ENTRY(feroceon_range_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_dma_clean_range
+        bcs     feroceon_dma_inv_range
+        b       feroceon_dma_flush_range
+ENDPROC(feroceon_dma_map_area)
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_range_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     feroceon_range_dma_clean_range
+        bcs     feroceon_range_dma_inv_range
+        b       feroceon_range_dma_flush_range
+ENDPROC(feroceon_range_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(feroceon_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(feroceon_dma_unmap_area)
+
 ENTRY(feroceon_cache_fns)
         .long   feroceon_flush_kern_cache_all
         .long   feroceon_flush_user_cache_all
@@ -374,8 +412,8 @@ ENTRY(feroceon_cache_fns)
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
         .long   feroceon_flush_kern_dcache_area
-        .long   feroceon_dma_inv_range
-        .long   feroceon_dma_clean_range
+        .long   feroceon_dma_map_area
+        .long   feroceon_dma_unmap_area
         .long   feroceon_dma_flush_range
 
 ENTRY(feroceon_range_cache_fns)
@@ -385,8 +423,8 @@ ENTRY(feroceon_range_cache_fns)
         .long   feroceon_coherent_kern_range
         .long   feroceon_coherent_user_range
         .long   feroceon_range_flush_kern_dcache_area
-        .long   feroceon_range_dma_inv_range
-        .long   feroceon_range_dma_clean_range
+        .long   feroceon_range_dma_map_area
+        .long   feroceon_dma_unmap_area
         .long   feroceon_range_dma_flush_range
 
         .align  5
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S
index 9674d36cc97d..caa31154e7db 100644
--- a/arch/arm/mm/proc-mohawk.S
+++ b/arch/arm/mm/proc-mohawk.S
@@ -218,7 +218,7 @@ ENTRY(mohawk_flush_kern_dcache_area)
  *
  * (same as v4wb)
  */
-ENTRY(mohawk_dma_inv_range)
+mohawk_dma_inv_range:
         tst     r0, #CACHE_DLINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
         tst     r1, #CACHE_DLINESIZE - 1
@@ -241,7 +241,7 @@ ENTRY(mohawk_dma_inv_range)
  *
  * (same as v4wb)
  */
-ENTRY(mohawk_dma_clean_range)
+mohawk_dma_clean_range:
         bic     r0, r0, #CACHE_DLINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHE_DLINESIZE
@@ -268,6 +268,30 @@ ENTRY(mohawk_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ drain WB
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     mohawk_dma_clean_range
+        bcs     mohawk_dma_inv_range
+        b       mohawk_dma_flush_range
+ENDPROC(mohawk_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(mohawk_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(mohawk_dma_unmap_area)
+
 ENTRY(mohawk_cache_fns)
         .long   mohawk_flush_kern_cache_all
         .long   mohawk_flush_user_cache_all
@@ -275,8 +299,8 @@ ENTRY(mohawk_cache_fns)
         .long   mohawk_coherent_kern_range
         .long   mohawk_coherent_user_range
         .long   mohawk_flush_kern_dcache_area
-        .long   mohawk_dma_inv_range
-        .long   mohawk_dma_clean_range
+        .long   mohawk_dma_map_area
+        .long   mohawk_dma_unmap_area
         .long   mohawk_dma_flush_range
 
 ENTRY(cpu_mohawk_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 8e4f6dca8997..e5797f1c1db7 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -257,7 +257,7 @@ ENTRY(xsc3_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xsc3_dma_inv_range)
+xsc3_dma_inv_range:
         tst     r0, #CACHELINESIZE - 1
         bic     r0, r0, #CACHELINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean L1 D line
@@ -278,7 +278,7 @@ ENTRY(xsc3_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xsc3_dma_clean_range)
+xsc3_dma_clean_range:
         bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean L1 D line
         add     r0, r0, #CACHELINESIZE
@@ -304,6 +304,30 @@ ENTRY(xsc3_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ data write barrier
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xsc3_dma_clean_range
+        bcs     xsc3_dma_inv_range
+        b       xsc3_dma_flush_range
+ENDPROC(xsc3_dma_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xsc3_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xsc3_dma_unmap_area)
+
 ENTRY(xsc3_cache_fns)
         .long   xsc3_flush_kern_cache_all
         .long   xsc3_flush_user_cache_all
@@ -311,8 +335,8 @@ ENTRY(xsc3_cache_fns)
         .long   xsc3_coherent_kern_range
         .long   xsc3_coherent_user_range
         .long   xsc3_flush_kern_dcache_area
-        .long   xsc3_dma_inv_range
-        .long   xsc3_dma_clean_range
+        .long   xsc3_dma_map_area
+        .long   xsc3_dma_unmap_area
         .long   xsc3_dma_flush_range
 
 ENTRY(cpu_xsc3_dcache_clean_area)
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index 93df47265f2d..63037e2162f2 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -315,7 +315,7 @@ ENTRY(xscale_flush_kern_dcache_area)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xscale_dma_inv_range)
+xscale_dma_inv_range:
         tst     r0, #CACHELINESIZE - 1
         bic     r0, r0, #CACHELINESIZE - 1
         mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
@@ -336,7 +336,7 @@ ENTRY(xscale_dma_inv_range)
  *      - start  - virtual start address
  *      - end    - virtual end address
  */
-ENTRY(xscale_dma_clean_range)
+xscale_dma_clean_range:
         bic     r0, r0, #CACHELINESIZE - 1
 1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
         add     r0, r0, #CACHELINESIZE
@@ -363,6 +363,43 @@ ENTRY(xscale_dma_flush_range)
         mcr     p15, 0, r0, c7, c10, 4          @ Drain Write (& Fill) Buffer
         mov     pc, lr
 
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_map_area)
+        add     r1, r1, r0
+        cmp     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        bcs     xscale_dma_inv_range
+        b       xscale_dma_flush_range
+ENDPROC(xscale_dma_map_area)
+
+/*
+ *      dma_map_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_a0_map_area)
+        add     r1, r1, r0
+        teq     r2, #DMA_TO_DEVICE
+        beq     xscale_dma_clean_range
+        b       xscale_dma_flush_range
+ENDPROC(xscsale_dma_a0_map_area)
+
+/*
+ *      dma_unmap_area(start, size, dir)
+ *      - start - kernel virtual start address
+ *      - size  - size of region
+ *      - dir   - DMA direction
+ */
+ENTRY(xscale_dma_unmap_area)
+        mov     pc, lr
+ENDPROC(xscale_dma_unmap_area)
+
 ENTRY(xscale_cache_fns)
         .long   xscale_flush_kern_cache_all
         .long   xscale_flush_user_cache_all
@@ -370,8 +407,8 @@ ENTRY(xscale_cache_fns)
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
         .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_inv_range
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_map_area
+        .long   xscale_dma_unmap_area
         .long   xscale_dma_flush_range
 
 /*
@@ -394,8 +431,8 @@ ENTRY(xscale_80200_A0_A1_cache_fns)
         .long   xscale_coherent_kern_range
         .long   xscale_coherent_user_range
         .long   xscale_flush_kern_dcache_area
-        .long   xscale_dma_flush_range
-        .long   xscale_dma_clean_range
+        .long   xscale_dma_a0_map_area
+        .long   xscale_dma_unmap_area
         .long   xscale_dma_flush_range
 
 ENTRY(cpu_xscale_dcache_clean_area)
diff --git a/arch/arm/oprofile/op_model_arm11_core.c b/arch/arm/oprofile/op_model_arm11_core.c
index ad80752cb9fb..ef3e2653b90c 100644
--- a/arch/arm/oprofile/op_model_arm11_core.c
+++ b/arch/arm/oprofile/op_model_arm11_core.c
@@ -132,7 +132,7 @@ static irqreturn_t arm11_pmu_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-int arm11_request_interrupts(int *irqs, int nr)
+int arm11_request_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
         int ret = 0;
@@ -153,7 +153,7 @@ int arm11_request_interrupts(int *irqs, int nr)
         return ret;
 }
 
-void arm11_release_interrupts(int *irqs, int nr)
+void arm11_release_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
 
diff --git a/arch/arm/oprofile/op_model_arm11_core.h b/arch/arm/oprofile/op_model_arm11_core.h
index 6f8538e5a960..1902b99d9dfd 100644
--- a/arch/arm/oprofile/op_model_arm11_core.h
+++ b/arch/arm/oprofile/op_model_arm11_core.h
@@ -39,7 +39,7 @@
 int arm11_setup_pmu(void);
 int arm11_start_pmu(void);
 int arm11_stop_pmu(void);
-int arm11_request_interrupts(int *, int);
-void arm11_release_interrupts(int *, int);
+int arm11_request_interrupts(const int *, int);
+void arm11_release_interrupts(const int *, int);
 
 #endif
diff --git a/arch/arm/oprofile/op_model_mpcore.c b/arch/arm/oprofile/op_model_mpcore.c
index 4ce0f9801e2e..f73ce875a395 100644
--- a/arch/arm/oprofile/op_model_mpcore.c
+++ b/arch/arm/oprofile/op_model_mpcore.c
@@ -32,6 +32,7 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
@@ -43,6 +44,7 @@
 #include <mach/hardware.h>
 #include <mach/board-eb.h>
 #include <asm/system.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
@@ -58,6 +60,7 @@
  * Bitmask of used SCU counters
  */
 static unsigned int scu_em_used;
+static const struct pmu_irqs *pmu_irqs;
 
 /*
  * 2 helper fns take a counter number from 0-7 (not the userspace-visible counter number)
@@ -225,33 +228,40 @@ static int em_setup_ctrs(void)
         return 0;
 }
 
-static int arm11_irqs[] = {
-        [0]     = IRQ_EB11MP_PMU_CPU0,
-        [1]     = IRQ_EB11MP_PMU_CPU1,
-        [2]     = IRQ_EB11MP_PMU_CPU2,
-        [3]     = IRQ_EB11MP_PMU_CPU3
-};
-
 static int em_start(void)
 {
         int ret;
 
-        ret = arm11_request_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                ret = PTR_ERR(pmu_irqs);
+                goto out;
+        }
+
+        ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
         if (ret == 0) {
                 em_call_function(arm11_start_pmu);
 
                 ret = scu_start();
-                if (ret)
-                        arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+                if (ret) {
+                        arm11_release_interrupts(pmu_irqs->irqs,
+                                                 pmu_irqs->num_irqs);
+                } else {
+                        release_pmu(pmu_irqs);
+                        pmu_irqs = NULL;
+                }
         }
+
+out:
         return ret;
 }
 
 static void em_stop(void)
 {
         em_call_function(arm11_stop_pmu);
-        arm11_release_interrupts(arm11_irqs, ARRAY_SIZE(arm11_irqs));
+        arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
         scu_stop();
+        release_pmu(pmu_irqs);
 }
 
 /*
@@ -283,15 +293,7 @@ static int em_setup(void)
         em_route_irq(IRQ_EB11MP_PMU_SCU6, 3);
         em_route_irq(IRQ_EB11MP_PMU_SCU7, 3);
 
-        /*
-         * Send CP15 PMU interrupts to the owner CPU.
-         */
-        em_route_irq(IRQ_EB11MP_PMU_CPU0, 0);
-        em_route_irq(IRQ_EB11MP_PMU_CPU1, 1);
-        em_route_irq(IRQ_EB11MP_PMU_CPU2, 2);
-        em_route_irq(IRQ_EB11MP_PMU_CPU3, 3);
-
-        return 0;
+        return init_pmu();
 }
 
 struct op_arm_model_spec op_mpcore_spec = {
diff --git a/arch/arm/oprofile/op_model_v6.c b/arch/arm/oprofile/op_model_v6.c
index f7d2ec5ee9a1..a22357a2fd08 100644
--- a/arch/arm/oprofile/op_model_v6.c
+++ b/arch/arm/oprofile/op_model_v6.c
@@ -19,39 +19,47 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
 #include "op_model_arm11_core.h"
 
-static int irqs[] = {
-#ifdef CONFIG_ARCH_OMAP2
-        3,
-#endif
-#ifdef CONFIG_ARCH_BCMRING
-        IRQ_PMUIRQ, /* for BCMRING, ARM PMU interrupt is 43 */
-#endif
-};
+static const struct pmu_irqs *pmu_irqs;
 
 static void armv6_pmu_stop(void)
 {
         arm11_stop_pmu();
-        arm11_release_interrupts(irqs, ARRAY_SIZE(irqs));
+        arm11_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int armv6_pmu_start(void)
 {
         int ret;
 
-        ret = arm11_request_interrupts(irqs, ARRAY_SIZE(irqs));
-        if (ret >= 0)
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs)) {
+                ret = PTR_ERR(pmu_irqs);
+                goto out;
+        }
+
+        ret = arm11_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        if (ret >= 0) {
                 ret = arm11_start_pmu();
+        } else {
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
 
+out:
         return ret;
 }
 
diff --git a/arch/arm/oprofile/op_model_v7.c b/arch/arm/oprofile/op_model_v7.c
index 2088a6c0cc0e..8642d0891ae1 100644
--- a/arch/arm/oprofile/op_model_v7.c
+++ b/arch/arm/oprofile/op_model_v7.c
@@ -11,11 +11,14 @@
  */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/smp.h>
 
+#include <asm/pmu.h>
+
 #include "op_counter.h"
 #include "op_arm_model.h"
 #include "op_model_v7.h"
@@ -295,7 +298,7 @@ static irqreturn_t armv7_pmnc_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
-int armv7_request_interrupts(int *irqs, int nr)
+int armv7_request_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
         int ret = 0;
@@ -318,7 +321,7 @@ int armv7_request_interrupts(int *irqs, int nr)
         return ret;
 }
 
-void armv7_release_interrupts(int *irqs, int nr)
+void armv7_release_interrupts(const int *irqs, int nr)
 {
         unsigned int i;
 
@@ -362,12 +365,7 @@ static void armv7_pmnc_dump_regs(void)
 }
 #endif
 
-
-static int irqs[] = {
-#ifdef CONFIG_ARCH_OMAP3
-        INT_34XX_BENCH_MPU_EMUL,
-#endif
-};
+static const struct pmu_irqs *pmu_irqs;
 
 static void armv7_pmnc_stop(void)
 {
@@ -375,19 +373,29 @@ static void armv7_pmnc_stop(void)
         armv7_pmnc_dump_regs();
 #endif
         armv7_stop_pmnc();
-        armv7_release_interrupts(irqs, ARRAY_SIZE(irqs));
+        armv7_release_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int armv7_pmnc_start(void)
 {
         int ret;
 
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs))
+                return PTR_ERR(pmu_irqs);
+
 #ifdef DEBUG
         armv7_pmnc_dump_regs();
 #endif
-        ret = armv7_request_interrupts(irqs, ARRAY_SIZE(irqs));
-        if (ret >= 0)
+        ret = armv7_request_interrupts(pmu_irqs->irqs, pmu_irqs->num_irqs);
+        if (ret >= 0) {
                 armv7_start_pmnc();
+        } else {
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
+        }
 
         return ret;
 }
diff --git a/arch/arm/oprofile/op_model_v7.h b/arch/arm/oprofile/op_model_v7.h
index 0e19bcc2e100..9ca334b39c75 100644
--- a/arch/arm/oprofile/op_model_v7.h
+++ b/arch/arm/oprofile/op_model_v7.h
@@ -97,7 +97,7 @@
 int armv7_setup_pmu(void);
 int armv7_start_pmu(void);
 int armv7_stop_pmu(void);
-int armv7_request_interrupts(int *, int);
-void armv7_release_interrupts(int *, int);
+int armv7_request_interrupts(const int *, int);
+void armv7_release_interrupts(const int *, int);
 
 #endif
diff --git a/arch/arm/oprofile/op_model_xscale.c b/arch/arm/oprofile/op_model_xscale.c
index 724ab9ce2526..1d34a02048bd 100644
--- a/arch/arm/oprofile/op_model_xscale.c
+++ b/arch/arm/oprofile/op_model_xscale.c
@@ -17,12 +17,14 @@
 /* #define DEBUG */
 #include <linux/types.h>
 #include <linux/errno.h>
+#include <linux/err.h>
 #include <linux/sched.h>
 #include <linux/oprofile.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 
 #include <asm/cputype.h>
+#include <asm/pmu.h>
 
 #include "op_counter.h"
 #include "op_arm_model.h"
@@ -33,17 +35,6 @@
 #define PMU_RESET       (CCNT_RESET | PMN_RESET)
 #define PMU_CNT64       0x008   /* Make CCNT count every 64th cycle */
 
-/* TODO do runtime detection */
-#ifdef CONFIG_ARCH_IOP32X
-#define XSCALE_PMU_IRQ  IRQ_IOP32X_CORE_PMU
-#endif
-#ifdef CONFIG_ARCH_IOP33X
-#define XSCALE_PMU_IRQ  IRQ_IOP33X_CORE_PMU
-#endif
-#ifdef CONFIG_ARCH_PXA
-#define XSCALE_PMU_IRQ  IRQ_PMU
-#endif
-
 /*
  * Different types of events that can be counted by the XScale PMU
  * as used by Oprofile userspace. Here primarily for documentation
@@ -367,6 +358,8 @@ static irqreturn_t xscale_pmu_interrupt(int irq, void *arg)
         return IRQ_HANDLED;
 }
 
+static const struct pmu_irqs *pmu_irqs;
+
 static void xscale_pmu_stop(void)
 {
         u32 pmnc = read_pmnc();
@@ -374,20 +367,30 @@ static void xscale_pmu_stop(void)
         pmnc &= ~PMU_ENABLE;
         write_pmnc(pmnc);
 
-        free_irq(XSCALE_PMU_IRQ, results);
+        free_irq(pmu_irqs->irqs[0], results);
+        release_pmu(pmu_irqs);
+        pmu_irqs = NULL;
 }
 
 static int xscale_pmu_start(void)
 {
         int ret;
-        u32 pmnc = read_pmnc();
+        u32 pmnc;
+
+        pmu_irqs = reserve_pmu();
+        if (IS_ERR(pmu_irqs))
+                return PTR_ERR(pmu_irqs);
+
+        pmnc = read_pmnc();
 
-        ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, IRQF_DISABLED,
-                        "XScale PMU", (void *)results);
+        ret = request_irq(pmu_irqs->irqs[0], xscale_pmu_interrupt,
+                          IRQF_DISABLED, "XScale PMU", (void *)results);
 
         if (ret < 0) {
                 printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
-                        XSCALE_PMU_IRQ);
+                       pmu_irqs->irqs[0]);
+                release_pmu(pmu_irqs);
+                pmu_irqs = NULL;
                 return ret;
         }
 
diff --git a/arch/arm/plat-iop/io.c b/arch/arm/plat-iop/io.c
index ed0bbece0d61..e15bc17db90b 100644
--- a/arch/arm/plat-iop/io.c
+++ b/arch/arm/plat-iop/io.c
@@ -34,7 +34,8 @@ void * __iomem __iop3xx_ioremap(unsigned long cookie, size_t size,
                 retval = (void *) IOP3XX_PMMR_PHYS_TO_VIRT(cookie);
                 break;
         default:
-                retval = __arm_ioremap(cookie, size, mtype);
+                retval = __arm_ioremap_caller(cookie, size, mtype,
+                                __builtin_return_address(0));
         }
 
         return retval;
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 996cbac6932c..6cee38df58b2 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -13,3 +13,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+ifdef CONFIG_SND_IMX_SOC
+obj-y += ssi-fiq.o
+obj-y += ssi-fiq-ksym.o
+endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 15b2b148a105..5a6ae1b9e1e8 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -52,7 +52,7 @@
 #define UART_PADDR      MXC91231_UART2_BASE_ADDR
 #define UART_VADDR      MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 ldreq   \rx, =UART_PADDR        @ physical
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 62d97623412f..44243a278434 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -21,6 +21,6 @@
 #define __ASM_ARCH_MXC_VMALLOC_H__
 
 /* vmalloc ending address */
-#define VMALLOC_END       0xF4000000
+#define VMALLOC_END       0xf4000000UL
 
 #endif /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/arch/arm/plat-mxc/ssi-fiq-ksym.c b/arch/arm/plat-mxc/ssi-fiq-ksym.c
new file mode 100644
index 000000000000..b5fad454da78
--- /dev/null
+++ b/arch/arm/plat-mxc/ssi-fiq-ksym.c
@@ -0,0 +1,20 @@
+/*
+ * Exported ksyms for the SSI FIQ handler
+ *
+ * Copyright (C) 2009, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+
+#include <mach/ssi.h>
+
+EXPORT_SYMBOL(imx_ssi_fiq_tx_buffer);
+EXPORT_SYMBOL(imx_ssi_fiq_rx_buffer);
+EXPORT_SYMBOL(imx_ssi_fiq_start);
+EXPORT_SYMBOL(imx_ssi_fiq_end);
+EXPORT_SYMBOL(imx_ssi_fiq_base);
+
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
new file mode 100644
index 000000000000..4ddce565b353
--- /dev/null
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -0,0 +1,134 @@
+/*
+ *  Copyright (C) 2009 Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+/*
+ * r8  = bit 0-15: tx offset, bit 16-31: tx buffer size
+ * r9  = bit 0-15: rx offset, bit 16-31: rx buffer size
+ */
+
+#define SSI_STX0        0x00
+#define SSI_SRX0        0x08
+#define SSI_SISR        0x14
+#define SSI_SIER        0x18
+#define SSI_SACNT       0x38
+
+#define SSI_SACNT_AC97EN        (1 << 0)
+
+#define SSI_SIER_TFE0_EN        (1 << 0)
+#define SSI_SISR_TFE0           (1 << 0)
+#define SSI_SISR_RFF0           (1 << 2)
+#define SSI_SIER_RFF0_EN        (1 << 2)
+
+                .text
+                .global imx_ssi_fiq_start
+                .global imx_ssi_fiq_end
+                .global imx_ssi_fiq_base
+                .global imx_ssi_fiq_rx_buffer
+                .global imx_ssi_fiq_tx_buffer
+
+imx_ssi_fiq_start:
+                ldr r12, imx_ssi_fiq_base
+
+                /* TX */
+                ldr r11, imx_ssi_fiq_tx_buffer
+
+                /* shall we send? */
+                ldr r13, [r12, #SSI_SIER]
+                tst r13, #SSI_SIER_TFE0_EN
+                beq 1f
+
+                /* TX FIFO empty? */
+                ldr r13, [r12, #SSI_SISR]
+                tst r13, #SSI_SISR_TFE0
+                beq 1f
+
+                mov r10, #0x10000
+                sub r10, #1
+                and r10, r10, r8        /* r10: current buffer offset */
+
+                add r11, r11, r10
+
+                ldrh r13, [r11]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #2]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #4]
+                strh r13, [r12, #SSI_STX0]
+
+                ldrh r13, [r11, #6]
+                strh r13, [r12, #SSI_STX0]
+
+                add r10, #8
+                lsr r13, r8, #16        /* r13: buffer size */
+                cmp r10, r13
+                lslgt r8, r13, #16
+                addle r8, #8
+1:
+                /* RX */
+
+                /* shall we receive? */
+                ldr r13, [r12, #SSI_SIER]
+                tst r13, #SSI_SIER_RFF0_EN
+                beq 1f
+
+                /* RX FIFO full? */
+                ldr r13, [r12, #SSI_SISR]
+                tst r13, #SSI_SISR_RFF0
+                beq 1f
+
+                ldr r11, imx_ssi_fiq_rx_buffer
+
+                mov r10, #0x10000
+                sub r10, #1
+                and r10, r10, r9        /* r10: current buffer offset */
+
+                add r11, r11, r10
+
+                ldr r13, [r12, #SSI_SACNT]
+                tst r13, #SSI_SACNT_AC97EN
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #2]
+
+                /* dummy read to skip slot 12 */
+                ldrne r13, [r12, #SSI_SRX0]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #4]
+
+                ldr r13, [r12, #SSI_SRX0]
+                strh r13, [r11, #6]
+
+                /* dummy read to skip slot 12 */
+                ldrne r13, [r12, #SSI_SRX0]
+
+                add r10, #8
+                lsr r13, r9, #16        /* r13: buffer size */
+                cmp r10, r13
+                lslgt r9, r13, #16
+                addle r9, #8
+
+1:
+                @ return from FIQ
+                subs    pc, lr, #4
+imx_ssi_fiq_base:
+                .word 0x0
+imx_ssi_fiq_rx_buffer:
+                .word 0x0
+imx_ssi_fiq_tx_buffer:
+                .word 0x0
+imx_ssi_fiq_end:
+
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
new file mode 100644
index 000000000000..1621db67a53d
--- /dev/null
+++ b/arch/arm/plat-nomadik/include/plat/i2c.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2009 ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PLAT_I2C_H
+#define __PLAT_I2C_H
+
+enum i2c_freq_mode {
+        I2C_FREQ_MODE_STANDARD,         /* up to 100 Kb/s */
+        I2C_FREQ_MODE_FAST,             /* up to 400 Kb/s */
+        I2C_FREQ_MODE_FAST_PLUS,        /* up to 1 Mb/s */
+        I2C_FREQ_MODE_HIGH_SPEED        /* up to 3.4 Mb/s */
+};
+
+/**
+ * struct nmk_i2c_controller - client specific controller configuration
+ * @clk_freq:   clock frequency for the operation mode
+ * @slsu:       Slave data setup time in ns.
+ *              The needed setup time for three modes of operation
+ *              are 250ns, 100ns and 10ns respectively thus leading
+ *              to the values of 14, 6, 2 for a 48 MHz i2c clk
+ * @tft:        Tx FIFO Threshold in bytes
+ * @rft:        Rx FIFO Threshold in bytes
+ * @sm:         speed mode
+ */
+struct nmk_i2c_controller {
+        unsigned long   clk_freq;
+        unsigned short  slsu;
+        unsigned char   tft;
+        unsigned char   rft;
+        enum i2c_freq_mode      sm;
+};
+
+#endif  /* __PLAT_I2C_H */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index e2ea04a4c8a1..2e3eec660864 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -22,6 +22,7 @@ config ARCH_OMAP3
         bool "TI OMAP3"
         select CPU_V7
         select COMMON_CLKDEV
+        select ARM_L1_CACHE_SHIFT_6
 
 config ARCH_OMAP4
         bool "TI OMAP4"
diff --git a/arch/arm/plat-omap/include/plat/omap44xx.h b/arch/arm/plat-omap/include/plat/omap44xx.h
index ef870de43c29..c7d628ecb467 100644
--- a/arch/arm/plat-omap/include/plat/omap44xx.h
+++ b/arch/arm/plat-omap/include/plat/omap44xx.h
@@ -40,6 +40,7 @@
 #define OMAP44XX_GIC_CPU_BASE           0x48240100
 #define OMAP44XX_SCU_BASE               0x48240000
 #define OMAP44XX_LOCAL_TWD_BASE         0x48240600
+#define OMAP44XX_L2CACHE_BASE           0x48242000
 #define OMAP44XX_WKUPGEN_BASE           0x48281000
 
 #define OMAP44XX_MAILBOX_BASE           (L4_44XX_BASE + 0xF4000)
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index 0cfd54f519c4..4cbd4fb3232c 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -128,7 +128,7 @@ void __iomem *omap_ioremap(unsigned long p, size_t size, unsigned int type)
                         return XLATE(p, L4_EMU_44XX_PHYS, L4_EMU_44XX_VIRT);
         }
 #endif
-        return __arm_ioremap(p, size, type);
+        return __arm_ioremap_caller(p, size, type, __builtin_return_address(0));
 }
 EXPORT_SYMBOL(omap_ioremap);
 
diff --git a/arch/arm/plat-s3c/include/mach/vmalloc.h b/arch/arm/plat-s3c/include/mach/vmalloc.h
index bfd2ca6e3074..299d95f365c9 100644
--- a/arch/arm/plat-s3c/include/mach/vmalloc.h
+++ b/arch/arm/plat-s3c/include/mach/vmalloc.h
@@ -15,6 +15,6 @@
 #ifndef __ASM_ARCH_VMALLOC_H
 #define __ASM_ARCH_VMALLOC_H
 
-#define VMALLOC_END       (0xE0000000)
+#define VMALLOC_END       (0xe0000000UL)
 
 #endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
index 5d2f19a09e44..e593a2a801c6 100644
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ b/arch/arm/plat-stmp3xxx/clock.c
@@ -1126,9 +1126,8 @@ static int __init clk_init(void)
                         if (ops && ops->set_parent)
                                 ops->set_parent(cl->clk, cl->clk->parent);
                 }
-
-                clkdev_add(cl);
         }
+        clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
         return 0;
 }
 
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
index fb3b969bf0a2..1b9348bf0e49 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
@@ -16,7 +16,7 @@
  * http://www.gnu.org/copyleft/gpl.html
  */
 
-                .macro  addruart,rx
+                .macro  addruart, rx, tmp
                 mrc     p15, 0, \rx, c1, c0
                 tst     \rx, #1                 @ MMU enabled?
                 moveq   \rx, #0x80000000        @ physical base address
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
index 541b880c1863..943c1a29d641 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
@@ -9,4 +9,4 @@
  * http://www.opensource.org/licenses/gpl-license.html
  * http://www.gnu.org/copyleft/gpl.html
  */
-#define VMALLOC_END       (0xF0000000)
+#define VMALLOC_END       0xf0000000UL
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index a63c4be99b36..7f3f59fcaa21 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -433,7 +433,11 @@ static inline void vfp_pm_init(void) { }
  * saved one. This function is used by the ptrace mechanism.
  */
 #ifdef CONFIG_SMP
-void vfp_sync_state(struct thread_info *thread)
+void vfp_sync_hwstate(struct thread_info *thread)
+{
+}
+
+void vfp_flush_hwstate(struct thread_info *thread)
 {
         /*
          * On SMP systems, the VFP state is automatically saved at every
@@ -444,35 +448,48 @@ void vfp_sync_state(struct thread_info *thread)
         thread->vfpstate.hard.cpu = NR_CPUS;
 }
 #else
-void vfp_sync_state(struct thread_info *thread)
+void vfp_sync_hwstate(struct thread_info *thread)
 {
         unsigned int cpu = get_cpu();
-        u32 fpexc = fmrx(FPEXC);
 
         /*
-         * If VFP is enabled, the previous state was already saved and
-         * last_VFP_context updated.
+         * If the thread we're interested in is the current owner of the
+         * hardware VFP state, then we need to save its state.
          */
-        if (fpexc & FPEXC_EN)
-                goto out;
+        if (last_VFP_context[cpu] == &thread->vfpstate) {
+                u32 fpexc = fmrx(FPEXC);
 
-        if (!last_VFP_context[cpu])
-                goto out;
+                /*
+                 * Save the last VFP state on this CPU.
+                 */
+                fmxr(FPEXC, fpexc | FPEXC_EN);
+                vfp_save_state(&thread->vfpstate, fpexc | FPEXC_EN);
+                fmxr(FPEXC, fpexc);
+        }
 
-        /*
-         * Save the last VFP state on this CPU.
-         */
-        fmxr(FPEXC, fpexc | FPEXC_EN);
-        vfp_save_state(last_VFP_context[cpu], fpexc);
-        fmxr(FPEXC, fpexc);
+        put_cpu();
+}
+
+void vfp_flush_hwstate(struct thread_info *thread)
+{
+        unsigned int cpu = get_cpu();
 
         /*
-         * Set the context to NULL to force a reload the next time the thread
-         * uses the VFP.
+         * If the thread we're interested in is the current owner of the
+         * hardware VFP state, then we need to save its state.
          */
-        last_VFP_context[cpu] = NULL;
+        if (last_VFP_context[cpu] == &thread->vfpstate) {
+                u32 fpexc = fmrx(FPEXC);
+
+                fmxr(FPEXC, fpexc & ~FPEXC_EN);
+
+                /*
+                 * Set the context to NULL to force a reload the next time
+                 * the thread uses the VFP.
+                 */
+                last_VFP_context[cpu] = NULL;
+        }
 
-out:
         put_cpu();
 }
 #endif
diff --git a/arch/avr32/include/asm/pgtable.h b/arch/avr32/include/asm/pgtable.h
index fecdda16f444..a9ae30c41e74 100644
--- a/arch/avr32/include/asm/pgtable.h
+++ b/arch/avr32/include/asm/pgtable.h
@@ -325,7 +325,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 struct vm_area_struct;
 extern void update_mmu_cache(struct vm_area_struct * vma,
-                             unsigned long address, pte_t pte);
+                             unsigned long address, pte_t *ptep);
 
 /*
  * Encode and decode a swap entry
diff --git a/arch/avr32/mm/tlb.c b/arch/avr32/mm/tlb.c
index 06677be98ffb..0da23109f817 100644
--- a/arch/avr32/mm/tlb.c
+++ b/arch/avr32/mm/tlb.c
@@ -101,7 +101,7 @@ static void update_dtlb(unsigned long address, pte_t pte)
 }
 
 void update_mmu_cache(struct vm_area_struct *vma,
-                      unsigned long address, pte_t pte)
+                      unsigned long address, pte_t *ptep)
 {
         unsigned long flags;
 
@@ -110,7 +110,7 @@ void update_mmu_cache(struct vm_area_struct *vma,
                 return;
 
         local_irq_save(flags);
-        update_dtlb(address, pte);
+        update_dtlb(address, *ptep);
         local_irq_restore(flags);
 }
 
diff --git a/arch/cris/arch-v10/kernel/irq.c b/arch/cris/arch-v10/kernel/irq.c
index 5d75f77f9c73..1a61efc13982 100644
--- a/arch/cris/arch-v10/kernel/irq.c
+++ b/arch/cris/arch-v10/kernel/irq.c
@@ -133,7 +133,7 @@ static void end_crisv10_irq(unsigned int irq)
 }
 
 static struct irq_chip crisv10_irq_type = {
-        .typename =    "CRISv10",
+        .name =        "CRISv10",
         .startup =     startup_crisv10_irq,
         .shutdown =    shutdown_crisv10_irq,
         .enable =      enable_crisv10_irq,
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 57668db25031..b6241198fb98 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -336,7 +336,7 @@ int set_affinity_crisv32_irq(unsigned int irq, const struct cpumask *dest)
 }
 
 static struct irq_chip crisv32_irq_type = {
-        .typename =    "CRISv32",
+        .name =        "CRISv32",
         .startup =     startup_crisv32_irq,
         .shutdown =    shutdown_crisv32_irq,
         .enable =      enable_crisv32_irq,
diff --git a/arch/cris/arch-v32/kernel/pinmux.c b/arch/cris/arch-v32/kernel/pinmux.c
index 6eb54ea1c976..f6f3637a4194 100644
--- a/arch/cris/arch-v32/kernel/pinmux.c
+++ b/arch/cris/arch-v32/kernel/pinmux.c
@@ -54,7 +54,7 @@ crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
 
         crisv32_pinmux_init();
 
-        if (port > PORTS)
+        if (port > PORTS || port < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&pinmux_lock, flags);
@@ -197,7 +197,7 @@ crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
 
         crisv32_pinmux_init();
 
-        if (port > PORTS)
+        if (port > PORTS || port < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&pinmux_lock, flags);
diff --git a/arch/cris/arch-v32/mach-a3/pinmux.c b/arch/cris/arch-v32/mach-a3/pinmux.c
index 0a28c9bedfb7..18648ef2d874 100644
--- a/arch/cris/arch-v32/mach-a3/pinmux.c
+++ b/arch/cris/arch-v32/mach-a3/pinmux.c
@@ -242,7 +242,7 @@ crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
 
         crisv32_pinmux_init();
 
-        if (port > PORTS)
+        if (port > PORTS || port < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&pinmux_lock, flags);
diff --git a/arch/cris/arch-v32/mach-fs/pinmux.c b/arch/cris/arch-v32/mach-fs/pinmux.c
index d722ad9ae626..38f29eec14a6 100644
--- a/arch/cris/arch-v32/mach-fs/pinmux.c
+++ b/arch/cris/arch-v32/mach-fs/pinmux.c
@@ -54,7 +54,7 @@ crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode mode)
 
         crisv32_pinmux_init();
 
-        if (port > PORTS)
+        if (port > PORTS || port < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&pinmux_lock, flags);
@@ -195,7 +195,7 @@ int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin)
 
         crisv32_pinmux_init();
 
-        if (port > PORTS)
+        if (port > PORTS || port < 0)
                 return -EINVAL;
 
         spin_lock_irqsave(&pinmux_lock, flags);
diff --git a/arch/cris/include/asm/pgtable.h b/arch/cris/include/asm/pgtable.h
index 1fcce00f01f4..99ea6cd1b143 100644
--- a/arch/cris/include/asm/pgtable.h
+++ b/arch/cris/include/asm/pgtable.h
@@ -270,7 +270,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; /* defined in head.S */
  * Actually I am not sure on what this could be used for.
  */
 static inline void update_mmu_cache(struct vm_area_struct * vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/cris/kernel/irq.c b/arch/cris/kernel/irq.c
index b5ce0724a88f..6d7b9eda4036 100644
--- a/arch/cris/kernel/irq.c
+++ b/arch/cris/kernel/irq.c
@@ -63,7 +63,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 #endif
-                seq_printf(p, " %14s", irq_desc[i].chip->typename);
+                seq_printf(p, " %14s", irq_desc[i].chip->name);
                 seq_printf(p, "  %s", action->name);
 
                 for (action=action->next; action; action = action->next)
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
index 22c60692b551..c18b0d32e636 100644
--- a/arch/frv/include/asm/pgtable.h
+++ b/arch/frv/include/asm/pgtable.h
@@ -505,7 +505,7 @@ static inline int pte_file(pte_t pte)
 /*
  * preload information about a newly instantiated PTE into the SCR0/SCR1 PGE cache
  */
-static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+static inline void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         struct mm_struct *mm;
         unsigned long ampr;
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 2d7f56a98e0f..9a50d7dd2a0b 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -499,23 +499,6 @@ config ARCH_PROC_KCORE_TEXT
         def_bool y
         depends on PROC_KCORE
 
-config IA32_SUPPORT
-        bool "Support for Linux/x86 binaries"
-        help
-          IA-64 processors can execute IA-32 (X86) instructions.  By
-          saying Y here, the kernel will include IA-32 system call
-          emulation support which makes it possible to transparently
-          run IA-32 Linux binaries on an IA-64 Linux system.
-          If in doubt, say Y.
-
-config COMPAT
-        bool
-        depends on IA32_SUPPORT
-        default y
-
-config COMPAT_FOR_U64_ALIGNMENT
-        def_bool COMPAT
-
 config IA64_MCA_RECOVERY
         tristate "MCA recovery from errors other than TLB."
 
diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile
index 475e2725fbde..8ae0d2604ce1 100644
--- a/arch/ia64/Makefile
+++ b/arch/ia64/Makefile
@@ -46,7 +46,6 @@ head-y := arch/ia64/kernel/head.o arch/ia64/kernel/init_task.o
 
 libs-y                          += arch/ia64/lib/
 core-y                          += arch/ia64/kernel/ arch/ia64/mm/
-core-$(CONFIG_IA32_SUPPORT)     += arch/ia64/ia32/
 core-$(CONFIG_IA64_DIG)         += arch/ia64/dig/
 core-$(CONFIG_IA64_DIG_VTD)     += arch/ia64/dig/
 core-$(CONFIG_IA64_GENERIC)     += arch/ia64/dig/
diff --git a/arch/ia64/configs/bigsur_defconfig b/arch/ia64/configs/bigsur_defconfig
index ace41096b47b..312b12094a1d 100644
--- a/arch/ia64/configs/bigsur_defconfig
+++ b/arch/ia64/configs/bigsur_defconfig
@@ -131,8 +131,6 @@ CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 # CONFIG_VIRTUAL_MEM_MAP is not set
-CONFIG_IA32_SUPPORT=y
-CONFIG_COMPAT=y
 # CONFIG_IA64_MCA_RECOVERY is not set
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig
index 75645495c2dd..6a4cc506fb5f 100644
--- a/arch/ia64/configs/generic_defconfig
+++ b/arch/ia64/configs/generic_defconfig
@@ -205,8 +205,6 @@ CONFIG_VIRTUAL_MEM_MAP=y
 CONFIG_HOLES_IN_ZONE=y
 CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
 CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y
-CONFIG_IA32_SUPPORT=y
-CONFIG_COMPAT=y
 CONFIG_COMPAT_FOR_U64_ALIGNMENT=y
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
diff --git a/arch/ia64/configs/gensparse_defconfig b/arch/ia64/configs/gensparse_defconfig
index e86fbd39c795..2dc185b0f9a3 100644
--- a/arch/ia64/configs/gensparse_defconfig
+++ b/arch/ia64/configs/gensparse_defconfig
@@ -139,8 +139,6 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
 CONFIG_NUMA=y
 CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y
-CONFIG_IA32_SUPPORT=y
-CONFIG_COMPAT=y
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
diff --git a/arch/ia64/configs/sim_defconfig b/arch/ia64/configs/sim_defconfig
index 546a772f438e..21a23cdfd41c 100644
--- a/arch/ia64/configs/sim_defconfig
+++ b/arch/ia64/configs/sim_defconfig
@@ -130,8 +130,6 @@ CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_ARCH_FLATMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
 # CONFIG_VIRTUAL_MEM_MAP is not set
-CONFIG_IA32_SUPPORT=y
-CONFIG_COMPAT=y
 # CONFIG_IA64_MCA_RECOVERY is not set
 # CONFIG_PERFMON is not set
 CONFIG_IA64_PALINFO=m
diff --git a/arch/ia64/configs/tiger_defconfig b/arch/ia64/configs/tiger_defconfig
index c522edf23c62..c5a5ea9d54ae 100644
--- a/arch/ia64/configs/tiger_defconfig
+++ b/arch/ia64/configs/tiger_defconfig
@@ -154,7 +154,6 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_VIRTUAL_MEM_MAP=y
 CONFIG_HOLES_IN_ZONE=y
-# CONFIG_IA32_SUPPORT is not set
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
diff --git a/arch/ia64/configs/xen_domu_defconfig b/arch/ia64/configs/xen_domu_defconfig
index 0bb0714dc19d..c67eafc4bb38 100644
--- a/arch/ia64/configs/xen_domu_defconfig
+++ b/arch/ia64/configs/xen_domu_defconfig
@@ -200,8 +200,6 @@ CONFIG_ARCH_SPARSEMEM_ENABLE=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_VIRTUAL_MEM_MAP=y
 CONFIG_HOLES_IN_ZONE=y
-# CONFIG_IA32_SUPPORT is not set
-# CONFIG_COMPAT_FOR_U64_ALIGNMENT is not set
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
diff --git a/arch/ia64/configs/zx1_defconfig b/arch/ia64/configs/zx1_defconfig
index 514f0635dafe..3cec65b534c2 100644
--- a/arch/ia64/configs/zx1_defconfig
+++ b/arch/ia64/configs/zx1_defconfig
@@ -150,8 +150,6 @@ CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
 CONFIG_ARCH_POPULATES_NODE_MAP=y
 CONFIG_VIRTUAL_MEM_MAP=y
 CONFIG_HOLES_IN_ZONE=y
-CONFIG_IA32_SUPPORT=y
-CONFIG_COMPAT=y
 CONFIG_IA64_MCA_RECOVERY=y
 CONFIG_PERFMON=y
 CONFIG_IA64_PALINFO=y
diff --git a/arch/ia64/hp/common/aml_nfw.c b/arch/ia64/hp/common/aml_nfw.c
index 4abd2c79bb1d..22078486d35d 100644
--- a/arch/ia64/hp/common/aml_nfw.c
+++ b/arch/ia64/hp/common/aml_nfw.c
@@ -77,7 +77,7 @@ static void aml_nfw_execute(struct ia64_nfw_context *c)
                      c->arg[4], c->arg[5], c->arg[6], c->arg[7]);
 }
 
-static void aml_nfw_read_arg(u8 *offset, u32 bit_width, acpi_integer *value)
+static void aml_nfw_read_arg(u8 *offset, u32 bit_width, u64 *value)
 {
         switch (bit_width) {
         case 8:
@@ -95,7 +95,7 @@ static void aml_nfw_read_arg(u8 *offset, u32 bit_width, acpi_integer *value)
         }
 }
 
-static void aml_nfw_write_arg(u8 *offset, u32 bit_width, acpi_integer *value)
+static void aml_nfw_write_arg(u8 *offset, u32 bit_width, u64 *value)
 {
         switch (bit_width) {
         case 8:
@@ -114,7 +114,7 @@ static void aml_nfw_write_arg(u8 *offset, u32 bit_width, acpi_integer *value)
 }
 
 static acpi_status aml_nfw_handler(u32 function, acpi_physical_address address,
-        u32 bit_width, acpi_integer *value, void *handler_context,
+        u32 bit_width, u64 *value, void *handler_context,
         void *region_context)
 {
         struct ia64_nfw_context *context = handler_context;
diff --git a/arch/ia64/ia32/Makefile b/arch/ia64/ia32/Makefile
deleted file mode 100644
index baad8c7699c0..000000000000
--- a/arch/ia64/ia32/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# Makefile for the ia32 kernel emulation subsystem.
-#
-
-obj-y := ia32_entry.o sys_ia32.o ia32_signal.o \
-         ia32_support.o ia32_traps.o binfmt_elf32.o ia32_ldt.o
-obj-$(CONFIG_AUDIT) += audit.o
-
-# Don't let GCC uses f16-f31 so that save_ia32_fpstate_live() and
-# restore_ia32_fpstate_live() can be sure the live register contain user-level state.
-CFLAGS_ia32_signal.o += -mfixed-range=f16-f31
diff --git a/arch/ia64/ia32/audit.c b/arch/ia64/ia32/audit.c
deleted file mode 100644
index 5c93ddd1e42d..000000000000
--- a/arch/ia64/ia32/audit.c
+++ /dev/null
@@ -1,42 +0,0 @@
-#include "../../x86/include/asm/unistd_32.h"
-
-unsigned ia32_dir_class[] = {
-#include <asm-generic/audit_dir_write.h>
-~0U
-};
-
-unsigned ia32_chattr_class[] = {
-#include <asm-generic/audit_change_attr.h>
-~0U
-};
-
-unsigned ia32_write_class[] = {
-#include <asm-generic/audit_write.h>
-~0U
-};
-
-unsigned ia32_read_class[] = {
-#include <asm-generic/audit_read.h>
-~0U
-};
-
-unsigned ia32_signal_class[] = {
-#include <asm-generic/audit_signal.h>
-~0U
-};
-
-int ia32_classify_syscall(unsigned syscall)
-{
-        switch(syscall) {
-        case __NR_open:
-                return 2;
-        case __NR_openat:
-                return 3;
-        case __NR_socketcall:
-                return 4;
-        case __NR_execve:
-                return 5;
-        default:
-                return 1;
-        }
-}
diff --git a/arch/ia64/ia32/binfmt_elf32.c b/arch/ia64/ia32/binfmt_elf32.c
deleted file mode 100644
index c69552bf893e..000000000000
--- a/arch/ia64/ia32/binfmt_elf32.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * IA-32 ELF support.
- *
- * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
- * Copyright (C) 2001 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * 06/16/00     A. Mallick      initialize csd/ssd/tssd/cflg for ia32_load_state
- * 04/13/01     D. Mosberger    dropped saving tssd in ar.k1---it's not needed
- * 09/14/01     D. Mosberger    fixed memory management for gdt/tss page
- */
-
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/security.h>
-
-#include <asm/param.h>
-#include <asm/signal.h>
-
-#include "ia32priv.h"
-#include "elfcore32.h"
-
-/* Override some function names */
-#undef start_thread
-#define start_thread                    ia32_start_thread
-#define elf_format                      elf32_format
-#define init_elf_binfmt                 init_elf32_binfmt
-#define exit_elf_binfmt                 exit_elf32_binfmt
-
-#undef CLOCKS_PER_SEC
-#define CLOCKS_PER_SEC  IA32_CLOCKS_PER_SEC
-
-extern void ia64_elf32_init (struct pt_regs *regs);
-
-static void elf32_set_personality (void);
-
-static unsigned long __attribute ((unused))
-randomize_stack_top(unsigned long stack_top);
-
-#define setup_arg_pages(bprm,tos,exec)          ia32_setup_arg_pages(bprm,exec)
-#define elf_map                         elf32_map
-
-#undef SET_PERSONALITY
-#define SET_PERSONALITY(ex)     elf32_set_personality()
-
-#define elf_read_implies_exec(ex, have_pt_gnu_stack)    (!(have_pt_gnu_stack))
-
-/* Ugly but avoids duplication */
-#include "../../../fs/binfmt_elf.c"
-
-extern struct page *ia32_shared_page[];
-extern unsigned long *ia32_gdt;
-extern struct page *ia32_gate_page;
-
-int
-ia32_install_shared_page (struct vm_area_struct *vma, struct vm_fault *vmf)
-{
-        vmf->page = ia32_shared_page[smp_processor_id()];
-        get_page(vmf->page);
-        return 0;
-}
-
-int
-ia32_install_gate_page (struct vm_area_struct *vma, struct vm_fault *vmf)
-{
-        vmf->page = ia32_gate_page;
-        get_page(vmf->page);
-        return 0;
-}
-
-
-static const struct vm_operations_struct ia32_shared_page_vm_ops = {
-        .fault = ia32_install_shared_page
-};
-
-static const struct vm_operations_struct ia32_gate_page_vm_ops = {
-        .fault = ia32_install_gate_page
-};
-
-void
-ia64_elf32_init (struct pt_regs *regs)
-{
-        struct vm_area_struct *vma;
-
-        /*
-         * Map GDT below 4GB, where the processor can find it.  We need to map
-         * it with privilege level 3 because the IVE uses non-privileged accesses to these
-         * tables.  IA-32 segmentation is used to protect against IA-32 accesses to them.
-         */
-        vma = kmem_cache_zalloc(vm_area_cachep, GFP_KERNEL);
-        if (vma) {
-                vma->vm_mm = current->mm;
-                vma->vm_start = IA32_GDT_OFFSET;
-                vma->vm_end = vma->vm_start + PAGE_SIZE;
-                vma->vm_page_prot = PAGE_SHARED;
-                vma->vm_flags = VM_READ|VM_MAYREAD|VM_RESERVED;
-                vma->vm_ops = &ia32_shared_page_vm_ops;
-                down_write(&current->mm->mmap_sem);
-                {
-                        if (insert_vm_struct(current->mm, vma)) {
-                                kmem_cache_free(vm_area_cachep, vma);
-                                up_write(&current->mm->mmap_sem);
-                                BUG();
-                        }
-                }
-                up_write(&current->mm->mmap_sem);
-        }
-
-        /*
-         * When user stack is not executable, push sigreturn code to stack makes
-         * segmentation fault raised when returning to kernel. So now sigreturn
-         * code is locked in specific gate page, which is pointed by pretcode
-         * when setup_frame_ia32
-         */
-        vma = kmem_cache_zalloc(vm_area_cachep, GFP_KERNEL);
-        if (vma) {
-                vma->vm_mm = current->mm;
-                vma->vm_start = IA32_GATE_OFFSET;
-                vma->vm_end = vma->vm_start + PAGE_SIZE;
-                vma->vm_page_prot = PAGE_COPY_EXEC;
-                vma->vm_flags = VM_READ | VM_MAYREAD | VM_EXEC
-                                | VM_MAYEXEC | VM_RESERVED;
-                vma->vm_ops = &ia32_gate_page_vm_ops;
-                down_write(&current->mm->mmap_sem);
-                {
-                        if (insert_vm_struct(current->mm, vma)) {
-                                kmem_cache_free(vm_area_cachep, vma);
-                                up_write(&current->mm->mmap_sem);
-                                BUG();
-                        }
-                }
-                up_write(&current->mm->mmap_sem);
-        }
-
-        /*
-         * Install LDT as anonymous memory.  This gives us all-zero segment descriptors
-         * until a task modifies them via modify_ldt().
-         */
-        vma = kmem_cache_zalloc(vm_area_cachep, GFP_KERNEL);
-        if (vma) {
-                vma->vm_mm = current->mm;
-                vma->vm_start = IA32_LDT_OFFSET;
-                vma->vm_end = vma->vm_start + PAGE_ALIGN(IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE);
-                vma->vm_page_prot = PAGE_SHARED;
-                vma->vm_flags = VM_READ|VM_WRITE|VM_MAYREAD|VM_MAYWRITE;
-                down_write(&current->mm->mmap_sem);
-                {
-                        if (insert_vm_struct(current->mm, vma)) {
-                                kmem_cache_free(vm_area_cachep, vma);
-                                up_write(&current->mm->mmap_sem);
-                                BUG();
-                        }
-                }
-                up_write(&current->mm->mmap_sem);
-        }
-
-        ia64_psr(regs)->ac = 0;         /* turn off alignment checking */
-        regs->loadrs = 0;
-        /*
-         *  According to the ABI %edx points to an `atexit' handler.  Since we don't have
-         *  one we'll set it to 0 and initialize all the other registers just to make
-         *  things more deterministic, ala the i386 implementation.
-         */
-        regs->r8 = 0;   /* %eax */
-        regs->r11 = 0;  /* %ebx */
-        regs->r9 = 0;   /* %ecx */
-        regs->r10 = 0;  /* %edx */
-        regs->r13 = 0;  /* %ebp */
-        regs->r14 = 0;  /* %esi */
-        regs->r15 = 0;  /* %edi */
-
-        current->thread.eflag = IA32_EFLAG;
-        current->thread.fsr = IA32_FSR_DEFAULT;
-        current->thread.fcr = IA32_FCR_DEFAULT;
-        current->thread.fir = 0;
-        current->thread.fdr = 0;
-
-        /*
-         * Setup GDTD.  Note: GDTD is the descrambled version of the pseudo-descriptor
-         * format defined by Figure 3-11 "Pseudo-Descriptor Format" in the IA-32
-         * architecture manual. Also note that the only fields that are not ignored are
-         * `base', `limit', 'G', `P' (must be 1) and `S' (must be 0).
-         */
-        regs->r31 = IA32_SEG_UNSCRAMBLE(IA32_SEG_DESCRIPTOR(IA32_GDT_OFFSET, IA32_PAGE_SIZE - 1,
-                                                            0, 0, 0, 1, 0, 0, 0));
-        /* Setup the segment selectors */
-        regs->r16 = (__USER_DS << 16) | __USER_DS; /* ES == DS, GS, FS are zero */
-        regs->r17 = (__USER_DS << 16) | __USER_CS; /* SS, CS; ia32_load_state() sets TSS and LDT */
-
-        ia32_load_segment_descriptors(current);
-        ia32_load_state(current);
-}
-
-/*
- * Undo the override of setup_arg_pages() without this ia32_setup_arg_pages()
- * will suffer infinite self recursion.
- */
-#undef setup_arg_pages
-
-int
-ia32_setup_arg_pages (struct linux_binprm *bprm, int executable_stack)
-{
-        int ret;
-
-        ret = setup_arg_pages(bprm, IA32_STACK_TOP, executable_stack);
-        if (!ret) {
-                /*
-                 * Can't do it in ia64_elf32_init(). Needs to be done before
-                 * calls to elf32_map()
-                 */
-                current->thread.ppl = ia32_init_pp_list();
-        }
-
-        return ret;
-}
-
-static void
-elf32_set_personality (void)
-{
-        set_personality(PER_LINUX32);
-        current->thread.map_base  = IA32_PAGE_OFFSET/3;
-}
-
-static unsigned long
-elf32_map(struct file *filep, unsigned long addr, struct elf_phdr *eppnt,
-                int prot, int type, unsigned long unused)
-{
-        unsigned long pgoff = (eppnt->p_vaddr) & ~IA32_PAGE_MASK;
-
-        return ia32_do_mmap(filep, (addr & IA32_PAGE_MASK), eppnt->p_filesz + pgoff, prot, type,
-                            eppnt->p_offset - pgoff);
-}
-
-#define cpu_uses_ia32el()       (local_cpu_data->family > 0x1f)
-
-static int __init check_elf32_binfmt(void)
-{
-        if (cpu_uses_ia32el()) {
-                printk("Please use IA-32 EL for executing IA-32 binaries\n");
-                unregister_binfmt(&elf_format);
-        }
-        return 0;
-}
-
-module_init(check_elf32_binfmt)
diff --git a/arch/ia64/ia32/elfcore32.h b/arch/ia64/ia32/elfcore32.h
deleted file mode 100644
index 657725742617..000000000000
--- a/arch/ia64/ia32/elfcore32.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * IA-32 ELF core dump support.
- *
- * Copyright (C) 2003 Arun Sharma <arun.sharma@intel.com>
- *
- * Derived from the x86_64 version
- */
-#ifndef _ELFCORE32_H_
-#define _ELFCORE32_H_
-
-#include <asm/intrinsics.h>
-#include <asm/uaccess.h>
-
-/* Override elfcore.h */
-#define _LINUX_ELFCORE_H 1
-typedef unsigned int elf_greg_t;
-
-#define ELF_NGREG (sizeof (struct user_regs_struct32) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct ia32_user_i387_struct elf_fpregset_t;
-typedef struct ia32_user_fxsr_struct elf_fpxregset_t;
-
-struct elf_siginfo
-{
-        int     si_signo;                       /* signal number */
-        int     si_code;                        /* extra code */
-        int     si_errno;                       /* errno */
-};
-
-#ifdef CONFIG_VIRT_CPU_ACCOUNTING
-/*
- * Hacks are here since types between compat_timeval (= pair of s32) and
- * ia64-native timeval (= pair of s64) are not compatible, at least a file
- * arch/ia64/ia32/../../../fs/binfmt_elf.c will get warnings from compiler on
- * use of cputime_to_timeval(), which usually an alias of jiffies_to_timeval().
- */
-#define cputime_to_timeval(a,b) \
-        do { (b)->tv_usec = 0; (b)->tv_sec = (a)/NSEC_PER_SEC; } while(0)
-#else
-#define jiffies_to_timeval(a,b) \
-        do { (b)->tv_usec = 0; (b)->tv_sec = (a)/HZ; } while(0)
-#endif
-
-struct elf_prstatus
-{
-        struct elf_siginfo pr_info;     /* Info associated with signal */
-        short   pr_cursig;              /* Current signal */
-        unsigned int pr_sigpend;        /* Set of pending signals */
-        unsigned int pr_sighold;        /* Set of held signals */
-        pid_t   pr_pid;
-        pid_t   pr_ppid;
-        pid_t   pr_pgrp;
-        pid_t   pr_sid;
-        struct compat_timeval pr_utime; /* User time */
-        struct compat_timeval pr_stime; /* System time */
-        struct compat_timeval pr_cutime;        /* Cumulative user time */
-        struct compat_timeval pr_cstime;        /* Cumulative system time */
-        elf_gregset_t pr_reg;   /* GP registers */
-        int pr_fpvalid;         /* True if math co-processor being used.  */
-};
-
-#define ELF_PRARGSZ     (80)    /* Number of chars for args */
-
-struct elf_prpsinfo
-{
-        char    pr_state;       /* numeric process state */
-        char    pr_sname;       /* char for pr_state */
-        char    pr_zomb;        /* zombie */
-        char    pr_nice;        /* nice val */
-        unsigned int pr_flag;   /* flags */
-        __u16   pr_uid;
-        __u16   pr_gid;
-        pid_t   pr_pid, pr_ppid, pr_pgrp, pr_sid;
-        /* Lots missing */
-        char    pr_fname[16];   /* filename of executable */
-        char    pr_psargs[ELF_PRARGSZ]; /* initial part of arg list */
-};
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)                \
-        pr_reg[0] = regs->r11;                          \
-        pr_reg[1] = regs->r9;                           \
-        pr_reg[2] = regs->r10;                          \
-        pr_reg[3] = regs->r14;                          \
-        pr_reg[4] = regs->r15;                          \
-        pr_reg[5] = regs->r13;                          \
-        pr_reg[6] = regs->r8;                           \
-        pr_reg[7] = regs->r16 & 0xffff;                 \
-        pr_reg[8] = (regs->r16 >> 16) & 0xffff;         \
-        pr_reg[9] = (regs->r16 >> 32) & 0xffff;         \
-        pr_reg[10] = (regs->r16 >> 48) & 0xffff;        \
-        pr_reg[11] = regs->r1;                          \
-        pr_reg[12] = regs->cr_iip;                      \
-        pr_reg[13] = regs->r17 & 0xffff;                \
-        pr_reg[14] = ia64_getreg(_IA64_REG_AR_EFLAG);   \
-        pr_reg[15] = regs->r12;                         \
-        pr_reg[16] = (regs->r17 >> 16) & 0xffff;
-
-static inline void elf_core_copy_regs(elf_gregset_t *elfregs,
-                                      struct pt_regs *regs)
-{
-        ELF_CORE_COPY_REGS((*elfregs), regs)
-}
-
-static inline int elf_core_copy_task_regs(struct task_struct *t,
-                                          elf_gregset_t* elfregs)
-{
-        ELF_CORE_COPY_REGS((*elfregs), task_pt_regs(t));
-        return 1;
-}
-
-static inline int
-elf_core_copy_task_fpregs(struct task_struct *tsk, struct pt_regs *regs, elf_fpregset_t *fpu)
-{
-        struct ia32_user_i387_struct *fpstate = (void*)fpu;
-        mm_segment_t old_fs;
-
-        if (!tsk_used_math(tsk))
-                return 0;
-        
-        old_fs = get_fs();
-        set_fs(KERNEL_DS);
-        save_ia32_fpstate(tsk, (struct ia32_user_i387_struct __user *) fpstate);
-        set_fs(old_fs);
-
-        return 1;
-}
-
-#define ELF_CORE_COPY_XFPREGS 1
-#define ELF_CORE_XFPREG_TYPE NT_PRXFPREG
-static inline int
-elf_core_copy_task_xfpregs(struct task_struct *tsk, elf_fpxregset_t *xfpu)
-{
-        struct ia32_user_fxsr_struct *fpxstate = (void*) xfpu;
-        mm_segment_t old_fs;
-
-        if (!tsk_used_math(tsk))
-                return 0;
-
-        old_fs = get_fs();
-        set_fs(KERNEL_DS);
-        save_ia32_fpxstate(tsk, (struct ia32_user_fxsr_struct __user *) fpxstate);
-        set_fs(old_fs);
-
-        return 1;
-}
-
-#endif /* _ELFCORE32_H_ */
diff --git a/arch/ia64/ia32/ia32_entry.S b/arch/ia64/ia32/ia32_entry.S
deleted file mode 100644
index 2fd7479aa216..000000000000
--- a/arch/ia64/ia32/ia32_entry.S
+++ /dev/null
@@ -1,468 +0,0 @@
-#include <asm/asmmacro.h>
-#include <asm/ia32.h>
-#include <asm/asm-offsets.h>
-#include <asm/signal.h>
-#include <asm/thread_info.h>
-
-#include "../kernel/minstate.h"
-
-        /*
-         * execve() is special because in case of success, we need to
-         * setup a null register window frame (in case an IA-32 process
-         * is exec'ing an IA-64 program).
-         */
-ENTRY(ia32_execve)
-        .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(3)
-        alloc loc1=ar.pfs,3,2,4,0
-        mov loc0=rp
-        .body
-        zxt4 out0=in0                   // filename
-        ;;                              // stop bit between alloc and call
-        zxt4 out1=in1                   // argv
-        zxt4 out2=in2                   // envp
-        add out3=16,sp                  // regs
-        br.call.sptk.few rp=sys32_execve
-1:      cmp.ge p6,p0=r8,r0
-        mov ar.pfs=loc1                 // restore ar.pfs
-        ;;
-(p6)    mov ar.pfs=r0                   // clear ar.pfs in case of success
-        sxt4 r8=r8                      // return 64-bit result
-        mov rp=loc0
-        br.ret.sptk.few rp
-END(ia32_execve)
-
-ENTRY(ia32_clone)
-        .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
-        alloc r16=ar.pfs,5,2,6,0
-        DO_SAVE_SWITCH_STACK
-        mov loc0=rp
-        mov loc1=r16                            // save ar.pfs across do_fork
-        .body
-        zxt4 out1=in1                           // newsp
-        mov out3=16                             // stacksize (compensates for 16-byte scratch area)
-        adds out2=IA64_SWITCH_STACK_SIZE+16,sp  // out2 = &regs
-        mov out0=in0                            // out0 = clone_flags
-        zxt4 out4=in2                           // out4 = parent_tidptr
-        zxt4 out5=in4                           // out5 = child_tidptr
-        br.call.sptk.many rp=do_fork
-.ret0:  .restore sp
-        adds sp=IA64_SWITCH_STACK_SIZE,sp       // pop the switch stack
-        mov ar.pfs=loc1
-        mov rp=loc0
-        br.ret.sptk.many rp
-END(ia32_clone)
-
-GLOBAL_ENTRY(ia32_ret_from_clone)
-        PT_REGS_UNWIND_INFO(0)
-{       /*
-         * Some versions of gas generate bad unwind info if the first instruction of a
-         * procedure doesn't go into the first slot of a bundle.  This is a workaround.
-         */
-        nop.m 0
-        nop.i 0
-        /*
-         * We need to call schedule_tail() to complete the scheduling process.
-         * Called by ia64_switch_to after do_fork()->copy_thread().  r8 contains the
-         * address of the previously executing task.
-         */
-        br.call.sptk.many rp=ia64_invoke_schedule_tail
-}
-.ret1:
-        adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
-        ;;
-        ld4 r2=[r2]
-        ;;
-        mov r8=0
-        and r2=_TIF_SYSCALL_TRACEAUDIT,r2
-        ;;
-        cmp.ne p6,p0=r2,r0
-(p6)    br.cond.spnt .ia32_strace_check_retval
-        ;;                                      // prevent RAW on r8
-END(ia32_ret_from_clone)
-        // fall through
-GLOBAL_ENTRY(ia32_ret_from_syscall)
-        PT_REGS_UNWIND_INFO(0)
-
-        cmp.ge p6,p7=r8,r0                      // syscall executed successfully?
-        adds r2=IA64_PT_REGS_R8_OFFSET+16,sp    // r2 = &pt_regs.r8
-        ;;
-        alloc r3=ar.pfs,0,0,0,0                 // drop the syscall argument frame
-        st8 [r2]=r8                             // store return value in slot for r8
-        br.cond.sptk.many ia64_leave_kernel
-END(ia32_ret_from_syscall)
-
-        //
-        // Invoke a system call, but do some tracing before and after the call.
-        // We MUST preserve the current register frame throughout this routine
-        // because some system calls (such as ia64_execve) directly
-        // manipulate ar.pfs.
-        //
-        // Input:
-        //      r8 = syscall number
-        //      b6 = syscall entry point
-        //
-GLOBAL_ENTRY(ia32_trace_syscall)
-        PT_REGS_UNWIND_INFO(0)
-        mov r3=-38
-        adds r2=IA64_PT_REGS_R8_OFFSET+16,sp
-        ;;
-        st8 [r2]=r3                             // initialize return code to -ENOSYS
-        br.call.sptk.few rp=syscall_trace_enter // give parent a chance to catch syscall args
-        cmp.lt p6,p0=r8,r0                      // check tracehook
-        adds r2=IA64_PT_REGS_R8_OFFSET+16,sp    // r2 = &pt_regs.r8
-        ;;
-(p6)    st8.spill [r2]=r8                       // store return value in slot for r8
-(p6)    br.spnt.few .ret4
-.ret2:  // Need to reload arguments (they may be changed by the tracing process)
-        adds r2=IA64_PT_REGS_R1_OFFSET+16,sp    // r2 = &pt_regs.r1
-        adds r3=IA64_PT_REGS_R13_OFFSET+16,sp   // r3 = &pt_regs.r13
-        mov r15=IA32_NR_syscalls
-        ;;
-        ld4 r8=[r2],IA64_PT_REGS_R9_OFFSET-IA64_PT_REGS_R1_OFFSET
-        movl r16=ia32_syscall_table
-        ;;
-        ld4 r33=[r2],8                          // r9 == ecx
-        ld4 r37=[r3],16                         // r13 == ebp
-        cmp.ltu.unc p6,p7=r8,r15
-        ;;
-        ld4 r34=[r2],8                          // r10 == edx
-        ld4 r36=[r3],8                          // r15 == edi
-(p6)    shladd r16=r8,3,r16     // force ni_syscall if not valid syscall number
-        ;;
-        ld8 r16=[r16]
-        ;;
-        ld4 r32=[r2],8                          // r11 == ebx
-        mov b6=r16
-        ld4 r35=[r3],8                          // r14 == esi
-        br.call.sptk.few rp=b6                  // do the syscall
-.ia32_strace_check_retval:
-        cmp.lt p6,p0=r8,r0                      // syscall failed?
-        adds r2=IA64_PT_REGS_R8_OFFSET+16,sp    // r2 = &pt_regs.r8
-        ;;
-        st8.spill [r2]=r8                       // store return value in slot for r8
-        br.call.sptk.few rp=syscall_trace_leave // give parent a chance to catch return value
-.ret4:  alloc r2=ar.pfs,0,0,0,0                 // drop the syscall argument frame
-        br.cond.sptk.many ia64_leave_kernel
-END(ia32_trace_syscall)
-
-GLOBAL_ENTRY(sys32_vfork)
-        alloc r16=ar.pfs,2,2,4,0;;
-        mov out0=IA64_CLONE_VFORK|IA64_CLONE_VM|SIGCHLD // out0 = clone_flags
-        br.cond.sptk.few .fork1                 // do the work
-END(sys32_vfork)
-
-GLOBAL_ENTRY(sys32_fork)
-        .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
-        alloc r16=ar.pfs,2,2,4,0
-        mov out0=SIGCHLD                        // out0 = clone_flags
-        ;;
-.fork1:
-        mov loc0=rp
-        mov loc1=r16                            // save ar.pfs across do_fork
-        DO_SAVE_SWITCH_STACK
-
-        .body
-
-        mov out1=0
-        mov out3=0
-        adds out2=IA64_SWITCH_STACK_SIZE+16,sp  // out2 = &regs
-        br.call.sptk.few rp=do_fork
-.ret5:  .restore sp
-        adds sp=IA64_SWITCH_STACK_SIZE,sp       // pop the switch stack
-        mov ar.pfs=loc1
-        mov rp=loc0
-        br.ret.sptk.many rp
-END(sys32_fork)
-
-        .rodata
-        .align 8
-        .globl ia32_syscall_table
-ia32_syscall_table:
-        data8 sys_ni_syscall      /* 0  -  old "setup(" system call*/
-        data8 sys_exit
-        data8 sys32_fork
-        data8 sys_read
-        data8 sys_write
-        data8 compat_sys_open     /* 5 */
-        data8 sys_close
-        data8 sys32_waitpid
-        data8 sys_creat
-        data8 sys_link
-        data8 sys_unlink          /* 10 */
-        data8 ia32_execve
-        data8 sys_chdir
-        data8 compat_sys_time
-        data8 sys_mknod
-        data8 sys_chmod           /* 15 */
-        data8 sys_lchown        /* 16-bit version */
-        data8 sys_ni_syscall      /* old break syscall holder */
-        data8 sys_ni_syscall
-        data8 sys32_lseek
-        data8 sys_getpid          /* 20 */
-        data8 compat_sys_mount
-        data8 sys_oldumount
-        data8 sys_setuid        /* 16-bit version */
-        data8 sys_getuid        /* 16-bit version */
-        data8 compat_sys_stime    /* 25 */
-        data8 compat_sys_ptrace
-        data8 sys32_alarm
-        data8 sys_ni_syscall
-        data8 sys_pause
-        data8 compat_sys_utime    /* 30 */
-        data8 sys_ni_syscall      /* old stty syscall holder */
-        data8 sys_ni_syscall      /* old gtty syscall holder */
-        data8 sys_access
-        data8 sys_nice
-        data8 sys_ni_syscall      /* 35 */        /* old ftime syscall holder */
-        data8 sys_sync
-        data8 sys_kill
-        data8 sys_rename
-        data8 sys_mkdir
-        data8 sys_rmdir           /* 40 */
-        data8 sys_dup
-        data8 sys_ia64_pipe
-        data8 compat_sys_times
-        data8 sys_ni_syscall      /* old prof syscall holder */
-        data8 sys32_brk           /* 45 */
-        data8 sys_setgid        /* 16-bit version */
-        data8 sys_getgid        /* 16-bit version */
-        data8 sys32_signal
-        data8 sys_geteuid       /* 16-bit version */
-        data8 sys_getegid       /* 16-bit version */      /* 50 */
-        data8 sys_acct
-        data8 sys_umount          /* recycled never used phys( */
-        data8 sys_ni_syscall      /* old lock syscall holder */
-        data8 compat_sys_ioctl
-        data8 compat_sys_fcntl    /* 55 */
-        data8 sys_ni_syscall      /* old mpx syscall holder */
-        data8 sys_setpgid
-        data8 sys_ni_syscall      /* old ulimit syscall holder */
-        data8 sys_ni_syscall
-        data8 sys_umask           /* 60 */
-        data8 sys_chroot
-        data8 compat_sys_ustat
-        data8 sys_dup2
-        data8 sys_getppid
-        data8 sys_getpgrp         /* 65 */
-        data8 sys_setsid
-        data8 sys32_sigaction
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall
-        data8 sys_setreuid      /* 16-bit version */      /* 70 */
-        data8 sys_setregid      /* 16-bit version */
-        data8 sys32_sigsuspend
-        data8 compat_sys_sigpending
-        data8 sys_sethostname
-        data8 compat_sys_setrlimit        /* 75 */
-        data8 compat_sys_old_getrlimit
-        data8 compat_sys_getrusage
-        data8 compat_sys_gettimeofday
-        data8 compat_sys_settimeofday
-        data8 sys32_getgroups16   /* 80 */
-        data8 sys32_setgroups16
-        data8 sys32_old_select
-        data8 sys_symlink
-        data8 sys_ni_syscall
-        data8 sys_readlink        /* 85 */
-        data8 sys_uselib
-        data8 sys_swapon
-        data8 sys_reboot
-        data8 compat_sys_old_readdir
-        data8 sys32_mmap          /* 90 */
-        data8 sys32_munmap
-        data8 sys_truncate
-        data8 sys_ftruncate
-        data8 sys_fchmod
-        data8 sys_fchown        /* 16-bit version */      /* 95 */
-        data8 sys_getpriority
-        data8 sys_setpriority
-        data8 sys_ni_syscall      /* old profil syscall holder */
-        data8 compat_sys_statfs
-        data8 compat_sys_fstatfs          /* 100 */
-        data8 sys_ni_syscall    /* ioperm */
-        data8 compat_sys_socketcall
-        data8 sys_syslog
-        data8 compat_sys_setitimer
-        data8 compat_sys_getitimer        /* 105 */
-        data8 compat_sys_newstat
-        data8 compat_sys_newlstat
-        data8 compat_sys_newfstat
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall    /* iopl */      /* 110 */
-        data8 sys_vhangup
-        data8 sys_ni_syscall            /* used to be sys_idle */
-        data8 sys_ni_syscall
-        data8 compat_sys_wait4
-        data8 sys_swapoff         /* 115 */
-        data8 compat_sys_sysinfo
-        data8 sys32_ipc
-        data8 sys_fsync
-        data8 sys32_sigreturn
-        data8 ia32_clone          /* 120 */
-        data8 sys_setdomainname
-        data8 sys32_newuname
-        data8 sys32_modify_ldt
-        data8 compat_sys_adjtimex
-        data8 sys32_mprotect      /* 125 */
-        data8 compat_sys_sigprocmask
-        data8 sys_ni_syscall    /* create_module */
-        data8 sys_ni_syscall    /* init_module */
-        data8 sys_ni_syscall    /* delete_module */
-        data8 sys_ni_syscall    /* get_kernel_syms */  /* 130 */
-        data8 sys32_quotactl
-        data8 sys_getpgid
-        data8 sys_fchdir
-        data8 sys_ni_syscall    /* sys_bdflush */
-        data8 sys_sysfs         /* 135 */
-        data8 sys32_personality
-        data8 sys_ni_syscall      /* for afs_syscall */
-        data8 sys_setfsuid      /* 16-bit version */
-        data8 sys_setfsgid      /* 16-bit version */
-        data8 sys_llseek          /* 140 */
-        data8 compat_sys_getdents
-        data8 compat_sys_select
-        data8 sys_flock
-        data8 sys32_msync
-        data8 compat_sys_readv    /* 145 */
-        data8 compat_sys_writev
-        data8 sys_getsid
-        data8 sys_fdatasync
-        data8 compat_sys_sysctl
-        data8 sys_mlock           /* 150 */
-        data8 sys_munlock
-        data8 sys_mlockall
-        data8 sys_munlockall
-        data8 sys_sched_setparam
-        data8 sys_sched_getparam  /* 155 */
-        data8 sys_sched_setscheduler
-        data8 sys_sched_getscheduler
-        data8 sys_sched_yield
-        data8 sys_sched_get_priority_max
-        data8 sys_sched_get_priority_min         /* 160 */
-        data8 sys32_sched_rr_get_interval
-        data8 compat_sys_nanosleep
-        data8 sys32_mremap
-        data8 sys_setresuid     /* 16-bit version */
-        data8 sys32_getresuid16 /* 16-bit version */      /* 165 */
-        data8 sys_ni_syscall    /* vm86 */
-        data8 sys_ni_syscall    /* sys_query_module */
-        data8 sys_poll
-        data8 sys_ni_syscall    /* nfsservctl */
-        data8 sys_setresgid       /* 170 */
-        data8 sys32_getresgid16
-        data8 sys_prctl
-        data8 sys32_rt_sigreturn
-        data8 sys32_rt_sigaction
-        data8 sys32_rt_sigprocmask /* 175 */
-        data8 sys_rt_sigpending
-        data8 compat_sys_rt_sigtimedwait
-        data8 sys32_rt_sigqueueinfo
-        data8 compat_sys_rt_sigsuspend
-        data8 sys32_pread         /* 180 */
-        data8 sys32_pwrite
-        data8 sys_chown /* 16-bit version */
-        data8 sys_getcwd
-        data8 sys_capget
-        data8 sys_capset          /* 185 */
-        data8 sys32_sigaltstack
-        data8 sys32_sendfile
-        data8 sys_ni_syscall              /* streams1 */
-        data8 sys_ni_syscall              /* streams2 */
-        data8 sys32_vfork         /* 190 */
-        data8 compat_sys_getrlimit
-        data8 sys32_mmap2
-        data8 sys32_truncate64
-        data8 sys32_ftruncate64
-        data8 sys32_stat64        /* 195 */
-        data8 sys32_lstat64
-        data8 sys32_fstat64
-        data8 sys_lchown
-        data8 sys_getuid
-        data8 sys_getgid          /* 200 */
-        data8 sys_geteuid
-        data8 sys_getegid
-        data8 sys_setreuid
-        data8 sys_setregid
-        data8 sys_getgroups       /* 205 */
-        data8 sys_setgroups
-        data8 sys_fchown
-        data8 sys_setresuid
-        data8 sys_getresuid
-        data8 sys_setresgid       /* 210 */
-        data8 sys_getresgid
-        data8 sys_chown
-        data8 sys_setuid
-        data8 sys_setgid
-        data8 sys_setfsuid        /* 215 */
-        data8 sys_setfsgid
-        data8 sys_pivot_root
-        data8 sys_mincore
-        data8 sys_madvise
-        data8 compat_sys_getdents64       /* 220 */
-        data8 compat_sys_fcntl64
-        data8 sys_ni_syscall            /* reserved for TUX */
-        data8 sys_ni_syscall            /* reserved for Security */
-        data8 sys_gettid
-        data8 sys_readahead       /* 225 */
-        data8 sys_setxattr
-        data8 sys_lsetxattr
-        data8 sys_fsetxattr
-        data8 sys_getxattr
-        data8 sys_lgetxattr     /* 230 */
-        data8 sys_fgetxattr
-        data8 sys_listxattr
-        data8 sys_llistxattr
-        data8 sys_flistxattr
-        data8 sys_removexattr   /* 235 */
-        data8 sys_lremovexattr
-        data8 sys_fremovexattr
-        data8 sys_tkill
-        data8 sys_sendfile64
-        data8 compat_sys_futex  /* 240 */
-        data8 compat_sys_sched_setaffinity
-        data8 compat_sys_sched_getaffinity
-        data8 sys32_set_thread_area
-        data8 sys32_get_thread_area
-        data8 compat_sys_io_setup       /* 245 */
-        data8 sys_io_destroy
-        data8 compat_sys_io_getevents
-        data8 compat_sys_io_submit
-        data8 sys_io_cancel
-        data8 sys_fadvise64     /* 250 */
-        data8 sys_ni_syscall
-        data8 sys_exit_group
-        data8 sys_lookup_dcookie
-        data8 sys_epoll_create
-        data8 sys32_epoll_ctl   /* 255 */
-        data8 sys32_epoll_wait
-        data8 sys_remap_file_pages
-        data8 sys_set_tid_address
-        data8 compat_sys_timer_create
-        data8 compat_sys_timer_settime  /* 260 */
-        data8 compat_sys_timer_gettime
-        data8 sys_timer_getoverrun
-        data8 sys_timer_delete
-        data8 compat_sys_clock_settime
-        data8 compat_sys_clock_gettime /* 265 */
-        data8 compat_sys_clock_getres
-        data8 compat_sys_clock_nanosleep
-        data8 compat_sys_statfs64
-        data8 compat_sys_fstatfs64
-        data8 sys_tgkill        /* 270 */
-        data8 compat_sys_utimes
-        data8 sys32_fadvise64_64
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall
-        data8 sys_ni_syscall    /* 275 */
-        data8 sys_ni_syscall
-        data8 compat_sys_mq_open
-        data8 sys_mq_unlink
-        data8 compat_sys_mq_timedsend
-        data8 compat_sys_mq_timedreceive        /* 280 */
-        data8 compat_sys_mq_notify
-        data8 compat_sys_mq_getsetattr
-        data8 sys_ni_syscall            /* reserved for kexec */
-        data8 compat_sys_waitid
-
-        // guard against failures to increase IA32_NR_syscalls
-        .org ia32_syscall_table + 8*IA32_NR_syscalls
diff --git a/arch/ia64/ia32/ia32_ldt.c b/arch/ia64/ia32/ia32_ldt.c
deleted file mode 100644
index 16d51c146849..000000000000
--- a/arch/ia64/ia32/ia32_ldt.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2001, 2004 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * Adapted from arch/i386/kernel/ldt.c
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/vmalloc.h>
-
-#include <asm/uaccess.h>
-
-#include "ia32priv.h"
-
-/*
- * read_ldt() is not really atomic - this is not a problem since synchronization of reads
- * and writes done to the LDT has to be assured by user-space anyway. Writes are atomic,
- * to protect the security checks done on new descriptors.
- */
-static int
-read_ldt (void __user *ptr, unsigned long bytecount)
-{
-        unsigned long bytes_left, n;
-        char __user *src, *dst;
-        char buf[256];  /* temporary buffer (don't overflow kernel stack!) */
-
-        if (bytecount > IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE)
-                bytecount = IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE;
-
-        bytes_left = bytecount;
-
-        src = (void __user *) IA32_LDT_OFFSET;
-        dst = ptr;
-
-        while (bytes_left) {
-                n = sizeof(buf);
-                if (n > bytes_left)
-                        n = bytes_left;
-
-                /*
-                 * We know we're reading valid memory, but we still must guard against
-                 * running out of memory.
-                 */
-                if (__copy_from_user(buf, src, n))
-                        return -EFAULT;
-
-                if (copy_to_user(dst, buf, n))
-                        return -EFAULT;
-
-                src += n;
-                dst += n;
-                bytes_left -= n;
-        }
-        return bytecount;
-}
-
-static int
-read_default_ldt (void __user * ptr, unsigned long bytecount)
-{
-        unsigned long size;
-        int err;
-
-        /* XXX fix me: should return equivalent of default_ldt[0] */
-        err = 0;
-        size = 8;
-        if (size > bytecount)
-                size = bytecount;
-
-        err = size;
-        if (clear_user(ptr, size))
-                err = -EFAULT;
-
-        return err;
-}
-
-static int
-write_ldt (void __user * ptr, unsigned long bytecount, int oldmode)
-{
-        struct ia32_user_desc ldt_info;
-        __u64 entry;
-        int ret;
-
-        if (bytecount != sizeof(ldt_info))
-                return -EINVAL;
-        if (copy_from_user(&ldt_info, ptr, sizeof(ldt_info)))
-                return -EFAULT;
-
-        if (ldt_info.entry_number >= IA32_LDT_ENTRIES)
-                return -EINVAL;
-        if (ldt_info.contents == 3) {
-                if (oldmode)
-                        return -EINVAL;
-                if (ldt_info.seg_not_present == 0)
-                        return -EINVAL;
-        }
-
-        if (ldt_info.base_addr == 0 && ldt_info.limit == 0
-            && (oldmode || (ldt_info.contents == 0 && ldt_info.read_exec_only == 1
-                            && ldt_info.seg_32bit == 0 && ldt_info.limit_in_pages == 0
-                            && ldt_info.seg_not_present == 1 && ldt_info.useable == 0)))
-                /* allow LDTs to be cleared by the user */
-                entry = 0;
-        else
-                /* we must set the "Accessed" bit as IVE doesn't emulate it */
-                entry = IA32_SEG_DESCRIPTOR(ldt_info.base_addr, ldt_info.limit,
-                                            (((ldt_info.read_exec_only ^ 1) << 1)
-                                             | (ldt_info.contents << 2)) | 1,
-                                            1, 3, ldt_info.seg_not_present ^ 1,
-                                            (oldmode ? 0 : ldt_info.useable),
-                                            ldt_info.seg_32bit,
-                                            ldt_info.limit_in_pages);
-        /*
-         * Install the new entry.  We know we're accessing valid (mapped) user-level
-         * memory, but we still need to guard against out-of-memory, hence we must use
-         * put_user().
-         */
-        ret = __put_user(entry, (__u64 __user *) IA32_LDT_OFFSET + ldt_info.entry_number);
-        ia32_load_segment_descriptors(current);
-        return ret;
-}
-
-asmlinkage int
-sys32_modify_ldt (int func, unsigned int ptr, unsigned int bytecount)
-{
-        int ret = -ENOSYS;
-
-        switch (func) {
-              case 0:
-                ret = read_ldt(compat_ptr(ptr), bytecount);
-                break;
-              case 1:
-                ret = write_ldt(compat_ptr(ptr), bytecount, 1);
-                break;
-              case 2:
-                ret = read_default_ldt(compat_ptr(ptr), bytecount);
-                break;
-              case 0x11:
-                ret = write_ldt(compat_ptr(ptr), bytecount, 0);
-                break;
-        }
-        return ret;
-}
diff --git a/arch/ia64/ia32/ia32_signal.c b/arch/ia64/ia32/ia32_signal.c
deleted file mode 100644
index b763ca19ef17..000000000000
--- a/arch/ia64/ia32/ia32_signal.c
+++ /dev/null
@@ -1,1010 +0,0 @@
-/*
- * IA32 Architecture-specific signal handling support.
- *
- * Copyright (C) 1999, 2001-2002, 2005 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
- * Copyright (C) 2000 VA Linux Co
- * Copyright (C) 2000 Don Dugger <n0ano@valinux.com>
- *
- * Derived from i386 and Alpha versions.
- */
-
-#include <linux/errno.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/personality.h>
-#include <linux/ptrace.h>
-#include <linux/sched.h>
-#include <linux/signal.h>
-#include <linux/smp.h>
-#include <linux/stddef.h>
-#include <linux/syscalls.h>
-#include <linux/unistd.h>
-#include <linux/wait.h>
-#include <linux/compat.h>
-
-#include <asm/intrinsics.h>
-#include <asm/uaccess.h>
-#include <asm/rse.h>
-#include <asm/sigcontext.h>
-
-#include "ia32priv.h"
-
-#include "../kernel/sigframe.h"
-
-#define A(__x)          ((unsigned long)(__x))
-
-#define DEBUG_SIG       0
-#define _BLOCKABLE      (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
-#define __IA32_NR_sigreturn            119
-#define __IA32_NR_rt_sigreturn         173
-
-struct sigframe_ia32
-{
-       int pretcode;
-       int sig;
-       struct sigcontext_ia32 sc;
-       struct _fpstate_ia32 fpstate;
-       unsigned int extramask[_COMPAT_NSIG_WORDS-1];
-       char retcode[8];
-};
-
-struct rt_sigframe_ia32
-{
-       int pretcode;
-       int sig;
-       int pinfo;
-       int puc;
-       compat_siginfo_t info;
-       struct ucontext_ia32 uc;
-       struct _fpstate_ia32 fpstate;
-       char retcode[8];
-};
-
-int
-copy_siginfo_from_user32 (siginfo_t *to, compat_siginfo_t __user *from)
-{
-        unsigned long tmp;
-        int err;
-
-        if (!access_ok(VERIFY_READ, from, sizeof(compat_siginfo_t)))
-                return -EFAULT;
-
-        err = __get_user(to->si_signo, &from->si_signo);
-        err |= __get_user(to->si_errno, &from->si_errno);
-        err |= __get_user(to->si_code, &from->si_code);
-
-        if (to->si_code < 0)
-                err |= __copy_from_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE);
-        else {
-                switch (to->si_code >> 16) {
-                      case __SI_CHLD >> 16:
-                        err |= __get_user(to->si_utime, &from->si_utime);
-                        err |= __get_user(to->si_stime, &from->si_stime);
-                        err |= __get_user(to->si_status, &from->si_status);
-                      default:
-                        err |= __get_user(to->si_pid, &from->si_pid);
-                        err |= __get_user(to->si_uid, &from->si_uid);
-                        break;
-                      case __SI_FAULT >> 16:
-                        err |= __get_user(tmp, &from->si_addr);
-                        to->si_addr = (void __user *) tmp;
-                        break;
-                      case __SI_POLL >> 16:
-                        err |= __get_user(to->si_band, &from->si_band);
-                        err |= __get_user(to->si_fd, &from->si_fd);
-                        break;
-                      case __SI_RT >> 16: /* This is not generated by the kernel as of now.  */
-                      case __SI_MESGQ >> 16:
-                        err |= __get_user(to->si_pid, &from->si_pid);
-                        err |= __get_user(to->si_uid, &from->si_uid);
-                        err |= __get_user(to->si_int, &from->si_int);
-                        break;
-                }
-        }
-        return err;
-}
-
-int
-copy_siginfo_to_user32 (compat_siginfo_t __user *to, siginfo_t *from)
-{
-        unsigned int addr;
-        int err;
-
-        if (!access_ok(VERIFY_WRITE, to, sizeof(compat_siginfo_t)))
-                return -EFAULT;
-
-        /* If you change siginfo_t structure, please be sure
-           this code is fixed accordingly.
-           It should never copy any pad contained in the structure
-           to avoid security leaks, but must copy the generic
-           3 ints plus the relevant union member.
-           This routine must convert siginfo from 64bit to 32bit as well
-           at the same time.  */
-        err = __put_user(from->si_signo, &to->si_signo);
-        err |= __put_user(from->si_errno, &to->si_errno);
-        err |= __put_user((short)from->si_code, &to->si_code);
-        if (from->si_code < 0)
-                err |= __copy_to_user(&to->_sifields._pad, &from->_sifields._pad, SI_PAD_SIZE);
-        else {
-                switch (from->si_code >> 16) {
-                case __SI_CHLD >> 16:
-                        err |= __put_user(from->si_utime, &to->si_utime);
-                        err |= __put_user(from->si_stime, &to->si_stime);
-                        err |= __put_user(from->si_status, &to->si_status);
-                default:
-                        err |= __put_user(from->si_pid, &to->si_pid);
-                        err |= __put_user(from->si_uid, &to->si_uid);
-                        break;
-                case __SI_FAULT >> 16:
-                        /* avoid type-checking warnings by copying _pad[0] in lieu of si_addr... */
-                        err |= __put_user(from->_sifields._pad[0], &to->si_addr);
-                        break;
-                case __SI_POLL >> 16:
-                        err |= __put_user(from->si_band, &to->si_band);
-                        err |= __put_user(from->si_fd, &to->si_fd);
-                        break;
-                case __SI_TIMER >> 16:
-                        err |= __put_user(from->si_tid, &to->si_tid);
-                        err |= __put_user(from->si_overrun, &to->si_overrun);
-                        addr = (unsigned long) from->si_ptr;
-                        err |= __put_user(addr, &to->si_ptr);
-                        break;
-                case __SI_RT >> 16:     /* Not generated by the kernel as of now.  */
-                case __SI_MESGQ >> 16:
-                        err |= __put_user(from->si_uid, &to->si_uid);
-                        err |= __put_user(from->si_pid, &to->si_pid);
-                        addr = (unsigned long) from->si_ptr;
-                        err |= __put_user(addr, &to->si_ptr);
-                        break;
-                }
-        }
-        return err;
-}
-
-
-/*
- *  SAVE and RESTORE of ia32 fpstate info, from ia64 current state
- *  Used in exception handler to pass the fpstate to the user, and restore
- *  the fpstate while returning from the exception handler.
- *
- *    fpstate info and their mapping to IA64 regs:
- *    fpstate    REG(BITS)      Attribute    Comments
- *    cw         ar.fcr(0:12)                with bits 7 and 6 not used
- *    sw         ar.fsr(0:15)
- *    tag        ar.fsr(16:31)               with odd numbered bits not used
- *                                           (read returns 0, writes ignored)
- *    ipoff      ar.fir(0:31)
- *    cssel      ar.fir(32:47)
- *    dataoff    ar.fdr(0:31)
- *    datasel    ar.fdr(32:47)
- *
- *    _st[(0+TOS)%8]   f8
- *    _st[(1+TOS)%8]   f9
- *    _st[(2+TOS)%8]   f10
- *    _st[(3+TOS)%8]   f11                   (f8..f11 from ptregs)
- *      : :            :                     (f12..f15 from live reg)
- *      : :            :
- *    _st[(7+TOS)%8]   f15                   TOS=sw.top(bits11:13)
- *
- *    status     Same as sw     RO
- *    magic      0                           as X86_FXSR_MAGIC in ia32
- *    mxcsr      Bits(7:15)=ar.fcr(39:47)
- *               Bits(0:5) =ar.fsr(32:37)    with bit 6 reserved
- *    _xmm[0..7] f16..f31                    (live registers)
- *                                           with _xmm[0]
- *                                             Bit(64:127)=f17(0:63)
- *                                             Bit(0:63)=f16(0:63)
- *    All other fields unused...
- */
-
-static int
-save_ia32_fpstate_live (struct _fpstate_ia32 __user *save)
-{
-        struct task_struct *tsk = current;
-        struct pt_regs *ptp;
-        struct _fpreg_ia32 *fpregp;
-        char buf[32];
-        unsigned long fsr, fcr, fir, fdr;
-        unsigned long new_fsr;
-        unsigned long num128[2];
-        unsigned long mxcsr=0;
-        int fp_tos, fr8_st_map;
-
-        if (!access_ok(VERIFY_WRITE, save, sizeof(*save)))
-                return -EFAULT;
-
-        /* Read in fsr, fcr, fir, fdr and copy onto fpstate */
-        fsr = ia64_getreg(_IA64_REG_AR_FSR);
-        fcr = ia64_getreg(_IA64_REG_AR_FCR);
-        fir = ia64_getreg(_IA64_REG_AR_FIR);
-        fdr = ia64_getreg(_IA64_REG_AR_FDR);
-
-        /*
-         * We need to clear the exception state before calling the signal handler. Clear
-         * the bits 15, bits 0-7 in fp status word. Similar to the functionality of fnclex
-         * instruction.
-         */
-        new_fsr = fsr & ~0x80ff;
-        ia64_setreg(_IA64_REG_AR_FSR, new_fsr);
-
-        __put_user(fcr & 0xffff, &save->cw);
-        __put_user(fsr & 0xffff, &save->sw);
-        __put_user((fsr>>16) & 0xffff, &save->tag);
-        __put_user(fir, &save->ipoff);
-        __put_user((fir>>32) & 0xffff, &save->cssel);
-        __put_user(fdr, &save->dataoff);
-        __put_user((fdr>>32) & 0xffff, &save->datasel);
-        __put_user(fsr & 0xffff, &save->status);
-
-        mxcsr = ((fcr>>32) & 0xff80) | ((fsr>>32) & 0x3f);
-        __put_user(mxcsr & 0xffff, &save->mxcsr);
-        __put_user( 0, &save->magic); //#define X86_FXSR_MAGIC   0x0000
-
-        /*
-         * save f8..f11  from pt_regs
-         * save f12..f15 from live register set
-         */
-        /*
-         *  Find the location where f8 has to go in fp reg stack.  This depends on
-         *  TOP(11:13) field of sw. Other f reg continue sequentially from where f8 maps
-         *  to.
-         */
-        fp_tos = (fsr>>11)&0x7;
-        fr8_st_map = (8-fp_tos)&0x7;
-        ptp = task_pt_regs(tsk);
-        fpregp = (struct _fpreg_ia32 *)(((unsigned long)buf + 15) & ~15);
-        ia64f2ia32f(fpregp, &ptp->f8);
-        copy_to_user(&save->_st[(0+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64f2ia32f(fpregp, &ptp->f9);
-        copy_to_user(&save->_st[(1+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64f2ia32f(fpregp, &ptp->f10);
-        copy_to_user(&save->_st[(2+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64f2ia32f(fpregp, &ptp->f11);
-        copy_to_user(&save->_st[(3+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-
-        ia64_stfe(fpregp, 12);
-        copy_to_user(&save->_st[(4+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64_stfe(fpregp, 13);
-        copy_to_user(&save->_st[(5+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64_stfe(fpregp, 14);
-        copy_to_user(&save->_st[(6+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-        ia64_stfe(fpregp, 15);
-        copy_to_user(&save->_st[(7+fr8_st_map)&0x7], fpregp, sizeof(struct _fpreg_ia32));
-
-        ia64_stf8(&num128[0], 16);
-        ia64_stf8(&num128[1], 17);
-        copy_to_user(&save->_xmm[0], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 18);
-        ia64_stf8(&num128[1], 19);
-        copy_to_user(&save->_xmm[1], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 20);
-        ia64_stf8(&num128[1], 21);
-        copy_to_user(&save->_xmm[2], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 22);
-        ia64_stf8(&num128[1], 23);
-        copy_to_user(&save->_xmm[3], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 24);
-        ia64_stf8(&num128[1], 25);
-        copy_to_user(&save->_xmm[4], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 26);
-        ia64_stf8(&num128[1], 27);
-        copy_to_user(&save->_xmm[5], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 28);
-        ia64_stf8(&num128[1], 29);
-        copy_to_user(&save->_xmm[6], num128, sizeof(struct _xmmreg_ia32));
-
-        ia64_stf8(&num128[0], 30);
-        ia64_stf8(&num128[1], 31);
-        copy_to_user(&save->_xmm[7], num128, sizeof(struct _xmmreg_ia32));
-        return 0;
-}
-
-static int
-restore_ia32_fpstate_live (struct _fpstate_ia32 __user *save)
-{
-        struct task_struct *tsk = current;
-        struct pt_regs *ptp;
-        unsigned int lo, hi;
-        unsigned long num128[2];
-        unsigned long num64, mxcsr;
-        struct _fpreg_ia32 *fpregp;
-        char buf[32];
-        unsigned long fsr, fcr, fir, fdr;
-        int fp_tos, fr8_st_map;
-
-        if (!access_ok(VERIFY_READ, save, sizeof(*save)))
-                return(-EFAULT);
-
-        /*
-         * Updating fsr, fcr, fir, fdr.
-         * Just a bit more complicated than save.
-         * - Need to make sure that we don't write any value other than the
-         *   specific fpstate info
-         * - Need to make sure that the untouched part of frs, fdr, fir, fcr
-         *   should remain same while writing.
-         * So, we do a read, change specific fields and write.
-         */
-        fsr = ia64_getreg(_IA64_REG_AR_FSR);
-        fcr = ia64_getreg(_IA64_REG_AR_FCR);
-        fir = ia64_getreg(_IA64_REG_AR_FIR);
-        fdr = ia64_getreg(_IA64_REG_AR_FDR);
-
-        __get_user(mxcsr, (unsigned int __user *)&save->mxcsr);
-        /* setting bits 0..5 8..12 with cw and 39..47 from mxcsr */
-        __get_user(lo, (unsigned int __user *)&save->cw);
-        num64 = mxcsr & 0xff10;
-        num64 = (num64 << 32) | (lo & 0x1f3f);
-        fcr = (fcr & (~0xff1000001f3fUL)) | num64;
-
-        /* setting bits 0..31 with sw and tag and 32..37 from mxcsr */
-        __get_user(lo, (unsigned int __user *)&save->sw);
-        /* set bits 15,7 (fsw.b, fsw.es) to reflect the current error status */
-        if ( !(lo & 0x7f) )
-                lo &= (~0x8080);
-        __get_user(hi, (unsigned int __user *)&save->tag);
-        num64 = mxcsr & 0x3f;
-        num64 = (num64 << 16) | (hi & 0xffff);
-        num64 = (num64 << 16) | (lo & 0xffff);
-        fsr = (fsr & (~0x3fffffffffUL)) | num64;
-
-        /* setting bits 0..47 with cssel and ipoff */
-        __get_user(lo, (unsigned int __user *)&save->ipoff);
-        __get_user(hi, (unsigned int __user *)&save->cssel);
-        num64 = hi & 0xffff;
-        num64 = (num64 << 32) | lo;
-        fir = (fir & (~0xffffffffffffUL)) | num64;
-
-        /* setting bits 0..47 with datasel and dataoff */
-        __get_user(lo, (unsigned int __user *)&save->dataoff);
-        __get_user(hi, (unsigned int __user *)&save->datasel);
-        num64 = hi & 0xffff;
-        num64 = (num64 << 32) | lo;
-        fdr = (fdr & (~0xffffffffffffUL)) | num64;
-
-        ia64_setreg(_IA64_REG_AR_FSR, fsr);
-        ia64_setreg(_IA64_REG_AR_FCR, fcr);
-        ia64_setreg(_IA64_REG_AR_FIR, fir);
-        ia64_setreg(_IA64_REG_AR_FDR, fdr);
-
-        /*
-         * restore f8..f11 onto pt_regs
-         * restore f12..f15 onto live registers
-         */
-        /*
-         *  Find the location where f8 has to go in fp reg stack.  This depends on
-         *  TOP(11:13) field of sw. Other f reg continue sequentially from where f8 maps
-         *  to.
-         */
-        fp_tos = (fsr>>11)&0x7;
-        fr8_st_map = (8-fp_tos)&0x7;
-        fpregp = (struct _fpreg_ia32 *)(((unsigned long)buf + 15) & ~15);
-
-        ptp = task_pt_regs(tsk);
-        copy_from_user(fpregp, &save->_st[(0+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia32f2ia64f(&ptp->f8, fpregp);
-        copy_from_user(fpregp, &save->_st[(1+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia32f2ia64f(&ptp->f9, fpregp);
-        copy_from_user(fpregp, &save->_st[(2+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia32f2ia64f(&ptp->f10, fpregp);
-        copy_from_user(fpregp, &save->_st[(3+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia32f2ia64f(&ptp->f11, fpregp);
-
-        copy_from_user(fpregp, &save->_st[(4+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia64_ldfe(12, fpregp);
-        copy_from_user(fpregp, &save->_st[(5+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia64_ldfe(13, fpregp);
-        copy_from_user(fpregp, &save->_st[(6+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia64_ldfe(14, fpregp);
-        copy_from_user(fpregp, &save->_st[(7+fr8_st_map)&0x7], sizeof(struct _fpreg_ia32));
-        ia64_ldfe(15, fpregp);
-
-        copy_from_user(num128, &save->_xmm[0], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(16, &num128[0]);
-        ia64_ldf8(17, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[1], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(18, &num128[0]);
-        ia64_ldf8(19, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[2], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(20, &num128[0]);
-        ia64_ldf8(21, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[3], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(22, &num128[0]);
-        ia64_ldf8(23, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[4], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(24, &num128[0]);
-        ia64_ldf8(25, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[5], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(26, &num128[0]);
-        ia64_ldf8(27, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[6], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(28, &num128[0]);
-        ia64_ldf8(29, &num128[1]);
-
-        copy_from_user(num128, &save->_xmm[7], sizeof(struct _xmmreg_ia32));
-        ia64_ldf8(30, &num128[0]);
-        ia64_ldf8(31, &num128[1]);
-        return 0;
-}
-
-static inline void
-sigact_set_handler (struct k_sigaction *sa, unsigned int handler, unsigned int restorer)
-{
-        if (handler + 1 <= 2)
-                /* SIG_DFL, SIG_IGN, or SIG_ERR: must sign-extend to 64-bits */
-                sa->sa.sa_handler = (__sighandler_t) A((int) handler);
-        else
-                sa->sa.sa_handler = (__sighandler_t) (((unsigned long) restorer << 32) | handler);
-}
-
-asmlinkage long
-sys32_sigsuspend (int history0, int history1, old_sigset_t mask)
-{
-        mask &= _BLOCKABLE;
-        spin_lock_irq(&current->sighand->siglock);
-        current->saved_sigmask = current->blocked;
-        siginitset(&current->blocked, mask);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        current->state = TASK_INTERRUPTIBLE;
-        schedule();
-        set_restore_sigmask();
-        return -ERESTARTNOHAND;
-}
-
-asmlinkage long
-sys32_signal (int sig, unsigned int handler)
-{
-        struct k_sigaction new_sa, old_sa;
-        int ret;
-
-        sigact_set_handler(&new_sa, handler, 0);
-        new_sa.sa.sa_flags = SA_ONESHOT | SA_NOMASK;
-        sigemptyset(&new_sa.sa.sa_mask);
-
-        ret = do_sigaction(sig, &new_sa, &old_sa);
-
-        return ret ? ret : IA32_SA_HANDLER(&old_sa);
-}
-
-asmlinkage long
-sys32_rt_sigaction (int sig, struct sigaction32 __user *act,
-                    struct sigaction32 __user *oact, unsigned int sigsetsize)
-{
-        struct k_sigaction new_ka, old_ka;
-        unsigned int handler, restorer;
-        int ret;
-
-        /* XXX: Don't preclude handling different sized sigset_t's.  */
-        if (sigsetsize != sizeof(compat_sigset_t))
-                return -EINVAL;
-
-        if (act) {
-                ret = get_user(handler, &act->sa_handler);
-                ret |= get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                ret |= get_user(restorer, &act->sa_restorer);
-                ret |= copy_from_user(&new_ka.sa.sa_mask, &act->sa_mask, sizeof(compat_sigset_t));
-                if (ret)
-                        return -EFAULT;
-
-                sigact_set_handler(&new_ka, handler, restorer);
-        }
-
-        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-
-        if (!ret && oact) {
-                ret = put_user(IA32_SA_HANDLER(&old_ka), &oact->sa_handler);
-                ret |= put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                ret |= put_user(IA32_SA_RESTORER(&old_ka), &oact->sa_restorer);
-                ret |= copy_to_user(&oact->sa_mask, &old_ka.sa.sa_mask, sizeof(compat_sigset_t));
-        }
-        return ret;
-}
-
-
-asmlinkage long
-sys32_rt_sigprocmask (int how, compat_sigset_t __user *set, compat_sigset_t __user *oset,
-                      unsigned int sigsetsize)
-{
-        mm_segment_t old_fs = get_fs();
-        sigset_t s;
-        long ret;
-
-        if (sigsetsize > sizeof(s))
-                return -EINVAL;
-
-        if (set) {
-                memset(&s, 0, sizeof(s));
-                if (copy_from_user(&s.sig, set, sigsetsize))
-                        return -EFAULT;
-        }
-        set_fs(KERNEL_DS);
-        ret = sys_rt_sigprocmask(how,
-                                 set ? (sigset_t __user *) &s : NULL,
-                                 oset ? (sigset_t __user *) &s : NULL, sizeof(s));
-        set_fs(old_fs);
-        if (ret)
-                return ret;
-        if (oset) {
-                if (copy_to_user(oset, &s.sig, sigsetsize))
-                        return -EFAULT;
-        }
-        return 0;
-}
-
-asmlinkage long
-sys32_rt_sigqueueinfo (int pid, int sig, compat_siginfo_t __user *uinfo)
-{
-        mm_segment_t old_fs = get_fs();
-        siginfo_t info;
-        int ret;
-
-        if (copy_siginfo_from_user32(&info, uinfo))
-                return -EFAULT;
-        set_fs(KERNEL_DS);
-        ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *) &info);
-        set_fs(old_fs);
-        return ret;
-}
-
-asmlinkage long
-sys32_sigaction (int sig, struct old_sigaction32 __user *act, struct old_sigaction32 __user *oact)
-{
-        struct k_sigaction new_ka, old_ka;
-        unsigned int handler, restorer;
-        int ret;
-
-        if (act) {
-                compat_old_sigset_t mask;
-
-                ret = get_user(handler, &act->sa_handler);
-                ret |= get_user(new_ka.sa.sa_flags, &act->sa_flags);
-                ret |= get_user(restorer, &act->sa_restorer);
-                ret |= get_user(mask, &act->sa_mask);
-                if (ret)
-                        return ret;
-
-                sigact_set_handler(&new_ka, handler, restorer);
-                siginitset(&new_ka.sa.sa_mask, mask);
-        }
-
-        ret = do_sigaction(sig, act ? &new_ka : NULL, oact ? &old_ka : NULL);
-
-        if (!ret && oact) {
-                ret = put_user(IA32_SA_HANDLER(&old_ka), &oact->sa_handler);
-                ret |= put_user(old_ka.sa.sa_flags, &oact->sa_flags);
-                ret |= put_user(IA32_SA_RESTORER(&old_ka), &oact->sa_restorer);
-                ret |= put_user(old_ka.sa.sa_mask.sig[0], &oact->sa_mask);
-        }
-
-        return ret;
-}
-
-static int
-setup_sigcontext_ia32 (struct sigcontext_ia32 __user *sc, struct _fpstate_ia32 __user *fpstate,
-                       struct pt_regs *regs, unsigned long mask)
-{
-        int  err = 0;
-        unsigned long flag;
-
-        if (!access_ok(VERIFY_WRITE, sc, sizeof(*sc)))
-                return -EFAULT;
-
-        err |= __put_user((regs->r16 >> 32) & 0xffff, (unsigned int __user *)&sc->fs);
-        err |= __put_user((regs->r16 >> 48) & 0xffff, (unsigned int __user *)&sc->gs);
-        err |= __put_user((regs->r16 >> 16) & 0xffff, (unsigned int __user *)&sc->es);
-        err |= __put_user(regs->r16 & 0xffff, (unsigned int __user *)&sc->ds);
-        err |= __put_user(regs->r15, &sc->edi);
-        err |= __put_user(regs->r14, &sc->esi);
-        err |= __put_user(regs->r13, &sc->ebp);
-        err |= __put_user(regs->r12, &sc->esp);
-        err |= __put_user(regs->r11, &sc->ebx);
-        err |= __put_user(regs->r10, &sc->edx);
-        err |= __put_user(regs->r9, &sc->ecx);
-        err |= __put_user(regs->r8, &sc->eax);
-#if 0
-        err |= __put_user(current->tss.trap_no, &sc->trapno);
-        err |= __put_user(current->tss.error_code, &sc->err);
-#endif
-        err |= __put_user(regs->cr_iip, &sc->eip);
-        err |= __put_user(regs->r17 & 0xffff, (unsigned int __user *)&sc->cs);
-        /*
-         *  `eflags' is in an ar register for this context
-         */
-        flag = ia64_getreg(_IA64_REG_AR_EFLAG);
-        err |= __put_user((unsigned int)flag, &sc->eflags);
-        err |= __put_user(regs->r12, &sc->esp_at_signal);
-        err |= __put_user((regs->r17 >> 16) & 0xffff, (unsigned int __user *)&sc->ss);
-
-        if ( save_ia32_fpstate_live(fpstate) < 0 )
-                err = -EFAULT;
-        else
-                err |= __put_user((u32)(u64)fpstate, &sc->fpstate);
-
-#if 0
-        tmp = save_i387(fpstate);
-        if (tmp < 0)
-                err = 1;
-        else
-                err |= __put_user(tmp ? fpstate : NULL, &sc->fpstate);
-
-        /* non-iBCS2 extensions.. */
-#endif
-        err |= __put_user(mask, &sc->oldmask);
-#if 0
-        err |= __put_user(current->tss.cr2, &sc->cr2);
-#endif
-        return err;
-}
-
-static int
-restore_sigcontext_ia32 (struct pt_regs *regs, struct sigcontext_ia32 __user *sc, int *peax)
-{
-        unsigned int err = 0;
-
-        /* Always make any pending restarted system calls return -EINTR */
-        current_thread_info()->restart_block.fn = do_no_restart_syscall;
-
-        if (!access_ok(VERIFY_READ, sc, sizeof(*sc)))
-                return(-EFAULT);
-
-#define COPY(ia64x, ia32x)      err |= __get_user(regs->ia64x, &sc->ia32x)
-
-#define copyseg_gs(tmp)         (regs->r16 |= (unsigned long) (tmp) << 48)
-#define copyseg_fs(tmp)         (regs->r16 |= (unsigned long) (tmp) << 32)
-#define copyseg_cs(tmp)         (regs->r17 |= tmp)
-#define copyseg_ss(tmp)         (regs->r17 |= (unsigned long) (tmp) << 16)
-#define copyseg_es(tmp)         (regs->r16 |= (unsigned long) (tmp) << 16)
-#define copyseg_ds(tmp)         (regs->r16 |= tmp)
-
-#define COPY_SEG(seg)                                   \
-        {                                               \
-                unsigned short tmp;                     \
-                err |= __get_user(tmp, &sc->seg);       \
-                copyseg_##seg(tmp);                     \
-        }
-#define COPY_SEG_STRICT(seg)                            \
-        {                                               \
-                unsigned short tmp;                     \
-                err |= __get_user(tmp, &sc->seg);       \
-                copyseg_##seg(tmp|3);                   \
-        }
-
-        /* To make COPY_SEGs easier, we zero r16, r17 */
-        regs->r16 = 0;
-        regs->r17 = 0;
-
-        COPY_SEG(gs);
-        COPY_SEG(fs);
-        COPY_SEG(es);
-        COPY_SEG(ds);
-        COPY(r15, edi);
-        COPY(r14, esi);
-        COPY(r13, ebp);
-        COPY(r12, esp);
-        COPY(r11, ebx);
-        COPY(r10, edx);
-        COPY(r9, ecx);
-        COPY(cr_iip, eip);
-        COPY_SEG_STRICT(cs);
-        COPY_SEG_STRICT(ss);
-        ia32_load_segment_descriptors(current);
-        {
-                unsigned int tmpflags;
-                unsigned long flag;
-
-                /*
-                 *  IA32 `eflags' is not part of `pt_regs', it's in an ar register which
-                 *  is part of the thread context.  Fortunately, we are executing in the
-                 *  IA32 process's context.
-                 */
-                err |= __get_user(tmpflags, &sc->eflags);
-                flag = ia64_getreg(_IA64_REG_AR_EFLAG);
-                flag &= ~0x40DD5;
-                flag |= (tmpflags & 0x40DD5);
-                ia64_setreg(_IA64_REG_AR_EFLAG, flag);
-
-                regs->r1 = -1;  /* disable syscall checks, r1 is orig_eax */
-        }
-
-        {
-                struct _fpstate_ia32 __user *buf = NULL;
-                u32    fpstate_ptr;
-                err |= get_user(fpstate_ptr, &(sc->fpstate));
-                buf = compat_ptr(fpstate_ptr);
-                if (buf) {
-                        err |= restore_ia32_fpstate_live(buf);
-                }
-        }
-
-#if 0
-        {
-                struct _fpstate * buf;
-                err |= __get_user(buf, &sc->fpstate);
-                if (buf) {
-                        if (!access_ok(VERIFY_READ, buf, sizeof(*buf)))
-                                goto badframe;
-                        err |= restore_i387(buf);
-                }
-        }
-#endif
-
-        err |= __get_user(*peax, &sc->eax);
-        return err;
-
-#if 0
-  badframe:
-        return 1;
-#endif
-}
-
-/*
- * Determine which stack to use..
- */
-static inline void __user *
-get_sigframe (struct k_sigaction *ka, struct pt_regs * regs, size_t frame_size)
-{
-        unsigned long esp;
-
-        /* Default to using normal stack (truncate off sign-extension of bit 31: */
-        esp = (unsigned int) regs->r12;
-
-        /* This is the X/Open sanctioned signal stack switching.  */
-        if (ka->sa.sa_flags & SA_ONSTACK) {
-                int onstack = sas_ss_flags(esp);
-
-                if (onstack == 0)
-                        esp = current->sas_ss_sp + current->sas_ss_size;
-                else if (onstack == SS_ONSTACK) {
-                        /*
-                         * If we are on the alternate signal stack and would
-                         * overflow it, don't. Return an always-bogus address
-                         * instead so we will die with SIGSEGV.
-                         */
-                        if (!likely(on_sig_stack(esp - frame_size)))
-                                return (void __user *) -1L;
-                }
-        }
-        /* Legacy stack switching not supported */
-
-        esp -= frame_size;
-        /* Align the stack pointer according to the i386 ABI,
-         * i.e. so that on function entry ((sp + 4) & 15) == 0. */
-        esp = ((esp + 4) & -16ul) - 4;
-        return (void __user *) esp;
-}
-
-static int
-setup_frame_ia32 (int sig, struct k_sigaction *ka, sigset_t *set, struct pt_regs * regs)
-{
-        struct exec_domain *ed = current_thread_info()->exec_domain;
-        struct sigframe_ia32 __user *frame;
-        int err = 0;
-
-        frame = get_sigframe(ka, regs, sizeof(*frame));
-
-        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
-                goto give_sigsegv;
-
-        err |= __put_user((ed && ed->signal_invmap && sig < 32
-                           ? (int)(ed->signal_invmap[sig]) : sig), &frame->sig);
-
-        err |= setup_sigcontext_ia32(&frame->sc, &frame->fpstate, regs, set->sig[0]);
-
-        if (_COMPAT_NSIG_WORDS > 1)
-                err |= __copy_to_user(frame->extramask, (char *) &set->sig + 4,
-                                      sizeof(frame->extramask));
-
-        /* Set up to return from userspace.  If provided, use a stub
-           already in userspace.  */
-        if (ka->sa.sa_flags & SA_RESTORER) {
-                unsigned int restorer = IA32_SA_RESTORER(ka);
-                err |= __put_user(restorer, &frame->pretcode);
-        } else {
-                /* Pointing to restorer in ia32 gate page */
-                err |= __put_user(IA32_GATE_OFFSET, &frame->pretcode);
-        }
-
-        /* This is popl %eax ; movl $,%eax ; int $0x80
-         * and there for historical reasons only.
-         * See arch/i386/kernel/signal.c
-         */
-
-        err |= __put_user(0xb858, (short __user *)(frame->retcode+0));
-        err |= __put_user(__IA32_NR_sigreturn, (int __user *)(frame->retcode+2));
-        err |= __put_user(0x80cd, (short __user *)(frame->retcode+6));
-
-        if (err)
-                goto give_sigsegv;
-
-        /* Set up registers for signal handler */
-        regs->r12 = (unsigned long) frame;
-        regs->cr_iip = IA32_SA_HANDLER(ka);
-
-        set_fs(USER_DS);
-
-#if 0
-        regs->eflags &= ~TF_MASK;
-#endif
-
-#if 0
-        printk("SIG deliver (%s:%d): sig=%d sp=%p pc=%lx ra=%x\n",
-               current->comm, current->pid, sig, (void *) frame, regs->cr_iip, frame->pretcode);
-#endif
-
-        return 1;
-
-  give_sigsegv:
-        force_sigsegv(sig, current);
-        return 0;
-}
-
-static int
-setup_rt_frame_ia32 (int sig, struct k_sigaction *ka, siginfo_t *info,
-                     sigset_t *set, struct pt_regs * regs)
-{
-        struct exec_domain *ed = current_thread_info()->exec_domain;
-        compat_uptr_t pinfo, puc;
-        struct rt_sigframe_ia32 __user *frame;
-        int err = 0;
-
-        frame = get_sigframe(ka, regs, sizeof(*frame));
-
-        if (!access_ok(VERIFY_WRITE, frame, sizeof(*frame)))
-                goto give_sigsegv;
-
-        err |= __put_user((ed && ed->signal_invmap
-                           && sig < 32 ? ed->signal_invmap[sig] : sig), &frame->sig);
-
-        pinfo = (long __user) &frame->info;
-        puc = (long __user) &frame->uc;
-        err |= __put_user(pinfo, &frame->pinfo);
-        err |= __put_user(puc, &frame->puc);
-        err |= copy_siginfo_to_user32(&frame->info, info);
-
-        /* Create the ucontext.  */
-        err |= __put_user(0, &frame->uc.uc_flags);
-        err |= __put_user(0, &frame->uc.uc_link);
-        err |= __put_user(current->sas_ss_sp, &frame->uc.uc_stack.ss_sp);
-        err |= __put_user(sas_ss_flags(regs->r12), &frame->uc.uc_stack.ss_flags);
-        err |= __put_user(current->sas_ss_size, &frame->uc.uc_stack.ss_size);
-        err |= setup_sigcontext_ia32(&frame->uc.uc_mcontext, &frame->fpstate, regs, set->sig[0]);
-        err |= __copy_to_user(&frame->uc.uc_sigmask, set, sizeof(*set));
-        if (err)
-                goto give_sigsegv;
-
-        /* Set up to return from userspace.  If provided, use a stub
-           already in userspace.  */
-        if (ka->sa.sa_flags & SA_RESTORER) {
-                unsigned int restorer = IA32_SA_RESTORER(ka);
-                err |= __put_user(restorer, &frame->pretcode);
-        } else {
-                /* Pointing to rt_restorer in ia32 gate page */
-                err |= __put_user(IA32_GATE_OFFSET + 8, &frame->pretcode);
-        }
-
-        /* This is movl $,%eax ; int $0x80
-         * and there for historical reasons only.
-         * See arch/i386/kernel/signal.c
-         */
-
-        err |= __put_user(0xb8, (char __user *)(frame->retcode+0));
-        err |= __put_user(__IA32_NR_rt_sigreturn, (int __user *)(frame->retcode+1));
-        err |= __put_user(0x80cd, (short __user *)(frame->retcode+5));
-
-        if (err)
-                goto give_sigsegv;
-
-        /* Set up registers for signal handler */
-        regs->r12 = (unsigned long) frame;
-        regs->cr_iip = IA32_SA_HANDLER(ka);
-
-        set_fs(USER_DS);
-
-#if 0
-        regs->eflags &= ~TF_MASK;
-#endif
-
-#if 0
-        printk("SIG deliver (%s:%d): sp=%p pc=%lx ra=%x\n",
-               current->comm, current->pid, (void *) frame, regs->cr_iip, frame->pretcode);
-#endif
-
-        return 1;
-
-give_sigsegv:
-        force_sigsegv(sig, current);
-        return 0;
-}
-
-int
-ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
-                   sigset_t *set, struct pt_regs *regs)
-{
-       /* Set up the stack frame */
-       if (ka->sa.sa_flags & SA_SIGINFO)
-               return setup_rt_frame_ia32(sig, ka, info, set, regs);
-       else
-               return setup_frame_ia32(sig, ka, set, regs);
-}
-
-asmlinkage long
-sys32_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4, int arg5,
-                 int arg6, int arg7, struct pt_regs regs)
-{
-        unsigned long esp = (unsigned int) regs.r12;
-        struct sigframe_ia32 __user *frame = (struct sigframe_ia32 __user *)(esp - 8);
-        sigset_t set;
-        int eax;
-
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-
-        if (__get_user(set.sig[0], &frame->sc.oldmask)
-            || (_COMPAT_NSIG_WORDS > 1 && __copy_from_user((char *) &set.sig + 4, &frame->extramask,
-                                                         sizeof(frame->extramask))))
-                goto badframe;
-
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        if (restore_sigcontext_ia32(&regs, &frame->sc, &eax))
-                goto badframe;
-        return eax;
-
-  badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
-
-asmlinkage long
-sys32_rt_sigreturn (int arg0, int arg1, int arg2, int arg3, int arg4,
-                    int arg5, int arg6, int arg7, struct pt_regs regs)
-{
-        unsigned long esp = (unsigned int) regs.r12;
-        struct rt_sigframe_ia32 __user *frame = (struct rt_sigframe_ia32 __user *)(esp - 4);
-        sigset_t set;
-        int eax;
-
-        if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
-                goto badframe;
-        if (__copy_from_user(&set, &frame->uc.uc_sigmask, sizeof(set)))
-                goto badframe;
-
-        sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked =  set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-
-        if (restore_sigcontext_ia32(&regs, &frame->uc.uc_mcontext, &eax))
-                goto badframe;
-
-        /* It is more difficult to avoid calling this function than to
-           call it and ignore errors.  */
-        do_sigaltstack((stack_t __user *) &frame->uc.uc_stack, NULL, esp);
-
-        return eax;
-
-  badframe:
-        force_sig(SIGSEGV, current);
-        return 0;
-}
diff --git a/arch/ia64/ia32/ia32_support.c b/arch/ia64/ia32/ia32_support.c
deleted file mode 100644
index a6965ddafc46..000000000000
--- a/arch/ia64/ia32/ia32_support.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * IA32 helper functions
- *
- * Copyright (C) 1999 Arun Sharma <arun.sharma@intel.com>
- * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001-2002 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * 06/16/00     A. Mallick      added csd/ssd/tssd for ia32 thread context
- * 02/19/01     D. Mosberger    dropped tssd; it's not needed
- * 09/14/01     D. Mosberger    fixed memory management for gdt/tss page
- * 09/29/01     D. Mosberger    added ia32_load_segment_descriptors()
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-
-#include <asm/intrinsics.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/system.h>
-#include <asm/processor.h>
-#include <asm/uaccess.h>
-
-#include "ia32priv.h"
-
-extern int die_if_kernel (char *str, struct pt_regs *regs, long err);
-
-struct page *ia32_shared_page[NR_CPUS];
-unsigned long *ia32_boot_gdt;
-unsigned long *cpu_gdt_table[NR_CPUS];
-struct page *ia32_gate_page;
-
-static unsigned long
-load_desc (u16 selector)
-{
-        unsigned long *table, limit, index;
-
-        if (!selector)
-                return 0;
-        if (selector & IA32_SEGSEL_TI) {
-                table = (unsigned long *) IA32_LDT_OFFSET;
-                limit = IA32_LDT_ENTRIES;
-        } else {
-                table = cpu_gdt_table[smp_processor_id()];
-                limit = IA32_PAGE_SIZE / sizeof(ia32_boot_gdt[0]);
-        }
-        index = selector >> IA32_SEGSEL_INDEX_SHIFT;
-        if (index >= limit)
-                return 0;
-        return IA32_SEG_UNSCRAMBLE(table[index]);
-}
-
-void
-ia32_load_segment_descriptors (struct task_struct *task)
-{
-        struct pt_regs *regs = task_pt_regs(task);
-
-        /* Setup the segment descriptors */
-        regs->r24 = load_desc(regs->r16 >> 16);         /* ESD */
-        regs->r27 = load_desc(regs->r16 >>  0);         /* DSD */
-        regs->r28 = load_desc(regs->r16 >> 32);         /* FSD */
-        regs->r29 = load_desc(regs->r16 >> 48);         /* GSD */
-        regs->ar_csd = load_desc(regs->r17 >>  0);      /* CSD */
-        regs->ar_ssd = load_desc(regs->r17 >> 16);      /* SSD */
-}
-
-int
-ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs)
-{
-        struct desc_struct *desc;
-        struct ia32_user_desc info;
-        int idx;
-
-        if (copy_from_user(&info, (void __user *)(childregs->r14 & 0xffffffff), sizeof(info)))
-                return -EFAULT;
-        if (LDT_empty(&info))
-                return -EINVAL;
-
-        idx = info.entry_number;
-        if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
-                return -EINVAL;
-
-        desc = child->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
-        desc->a = LDT_entry_a(&info);
-        desc->b = LDT_entry_b(&info);
-
-        /* XXX: can this be done in a cleaner way ? */
-        load_TLS(&child->thread, smp_processor_id());
-        ia32_load_segment_descriptors(child);
-        load_TLS(&current->thread, smp_processor_id());
-
-        return 0;
-}
-
-void
-ia32_save_state (struct task_struct *t)
-{
-        t->thread.eflag = ia64_getreg(_IA64_REG_AR_EFLAG);
-        t->thread.fsr   = ia64_getreg(_IA64_REG_AR_FSR);
-        t->thread.fcr   = ia64_getreg(_IA64_REG_AR_FCR);
-        t->thread.fir   = ia64_getreg(_IA64_REG_AR_FIR);
-        t->thread.fdr   = ia64_getreg(_IA64_REG_AR_FDR);
-        ia64_set_kr(IA64_KR_IO_BASE, t->thread.old_iob);
-        ia64_set_kr(IA64_KR_TSSD, t->thread.old_k1);
-}
-
-void
-ia32_load_state (struct task_struct *t)
-{
-        unsigned long eflag, fsr, fcr, fir, fdr, tssd;
-        struct pt_regs *regs = task_pt_regs(t);
-
-        eflag = t->thread.eflag;
-        fsr = t->thread.fsr;
-        fcr = t->thread.fcr;
-        fir = t->thread.fir;
-        fdr = t->thread.fdr;
-        tssd = load_desc(_TSS);                                 /* TSSD */
-
-        ia64_setreg(_IA64_REG_AR_EFLAG, eflag);
-        ia64_setreg(_IA64_REG_AR_FSR, fsr);
-        ia64_setreg(_IA64_REG_AR_FCR, fcr);
-        ia64_setreg(_IA64_REG_AR_FIR, fir);
-        ia64_setreg(_IA64_REG_AR_FDR, fdr);
-        current->thread.old_iob = ia64_get_kr(IA64_KR_IO_BASE);
-        current->thread.old_k1 = ia64_get_kr(IA64_KR_TSSD);
-        ia64_set_kr(IA64_KR_IO_BASE, IA32_IOBASE);
-        ia64_set_kr(IA64_KR_TSSD, tssd);
-
-        regs->r17 = (_TSS << 48) | (_LDT << 32) | (__u32) regs->r17;
-        regs->r30 = load_desc(_LDT);                            /* LDTD */
-        load_TLS(&t->thread, smp_processor_id());
-}
-
-/*
- * Setup IA32 GDT and TSS
- */
-void
-ia32_gdt_init (void)
-{
-        int cpu = smp_processor_id();
-
-        ia32_shared_page[cpu] = alloc_page(GFP_KERNEL);
-        if (!ia32_shared_page[cpu])
-                panic("failed to allocate ia32_shared_page[%d]\n", cpu);
-
-        cpu_gdt_table[cpu] = page_address(ia32_shared_page[cpu]);
-
-        /* Copy from the boot cpu's GDT */
-        memcpy(cpu_gdt_table[cpu], ia32_boot_gdt, PAGE_SIZE);
-}
-
-
-/*
- * Setup IA32 GDT and TSS
- */
-static void
-ia32_boot_gdt_init (void)
-{
-        unsigned long ldt_size;
-
-        ia32_shared_page[0] = alloc_page(GFP_KERNEL);
-        if (!ia32_shared_page[0])
-                panic("failed to allocate ia32_shared_page[0]\n");
-
-        ia32_boot_gdt = page_address(ia32_shared_page[0]);
-        cpu_gdt_table[0] = ia32_boot_gdt;
-
-        /* CS descriptor in IA-32 (scrambled) format */
-        ia32_boot_gdt[__USER_CS >> 3]
-                = IA32_SEG_DESCRIPTOR(0, (IA32_GATE_END-1) >> IA32_PAGE_SHIFT,
-                                      0xb, 1, 3, 1, 1, 1, 1);
-
-        /* DS descriptor in IA-32 (scrambled) format */
-        ia32_boot_gdt[__USER_DS >> 3]
-                = IA32_SEG_DESCRIPTOR(0, (IA32_GATE_END-1) >> IA32_PAGE_SHIFT,
-                                      0x3, 1, 3, 1, 1, 1, 1);
-
-        ldt_size = PAGE_ALIGN(IA32_LDT_ENTRIES*IA32_LDT_ENTRY_SIZE);
-        ia32_boot_gdt[TSS_ENTRY] = IA32_SEG_DESCRIPTOR(IA32_TSS_OFFSET, 235,
-                                                       0xb, 0, 3, 1, 1, 1, 0);
-        ia32_boot_gdt[LDT_ENTRY] = IA32_SEG_DESCRIPTOR(IA32_LDT_OFFSET, ldt_size - 1,
-                                                       0x2, 0, 3, 1, 1, 1, 0);
-}
-
-static void
-ia32_gate_page_init(void)
-{
-        unsigned long *sr;
-
-        ia32_gate_page = alloc_page(GFP_KERNEL);
-        sr = page_address(ia32_gate_page);
-        /* This is popl %eax ; movl $,%eax ; int $0x80 */
-        *sr++ = 0xb858 | (__IA32_NR_sigreturn << 16) | (0x80cdUL << 48);
-
-        /* This is movl $,%eax ; int $0x80 */
-        *sr = 0xb8 | (__IA32_NR_rt_sigreturn << 8) | (0x80cdUL << 40);
-}
-
-void
-ia32_mem_init(void)
-{
-        ia32_boot_gdt_init();
-        ia32_gate_page_init();
-}
-
-/*
- * Handle bad IA32 interrupt via syscall
- */
-void
-ia32_bad_interrupt (unsigned long int_num, struct pt_regs *regs)
-{
-        siginfo_t siginfo;
-
-        if (die_if_kernel("Bad IA-32 interrupt", regs, int_num))
-                return;
-
-        siginfo.si_signo = SIGTRAP;
-        siginfo.si_errno = int_num;     /* XXX is it OK to abuse si_errno like this? */
-        siginfo.si_flags = 0;
-        siginfo.si_isr = 0;
-        siginfo.si_addr = NULL;
-        siginfo.si_imm = 0;
-        siginfo.si_code = TRAP_BRKPT;
-        force_sig_info(SIGTRAP, &siginfo, current);
-}
-
-void
-ia32_cpu_init (void)
-{
-        /* initialize global ia32 state - CR0 and CR4 */
-        ia64_setreg(_IA64_REG_AR_CFLAG, (((ulong) IA32_CR4 << 32) | IA32_CR0));
-}
-
-static int __init
-ia32_init (void)
-{
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-        {
-                extern struct kmem_cache *ia64_partial_page_cachep;
-
-                ia64_partial_page_cachep = kmem_cache_create("ia64_partial_page_cache",
-                                        sizeof(struct ia64_partial_page),
-                                        0, SLAB_PANIC, NULL);
-        }
-#endif
-        return 0;
-}
-
-__initcall(ia32_init);
diff --git a/arch/ia64/ia32/ia32_traps.c b/arch/ia64/ia32/ia32_traps.c
deleted file mode 100644
index e486042672f1..000000000000
--- a/arch/ia64/ia32/ia32_traps.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * IA-32 exception handlers
- *
- * Copyright (C) 2000 Asit K. Mallick <asit.k.mallick@intel.com>
- * Copyright (C) 2001-2002 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- *
- * 06/16/00     A. Mallick      added siginfo for most cases (close to IA32)
- * 09/29/00     D. Mosberger    added ia32_intercept()
- */
-
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include "ia32priv.h"
-
-#include <asm/intrinsics.h>
-#include <asm/ptrace.h>
-
-int
-ia32_intercept (struct pt_regs *regs, unsigned long isr)
-{
-        switch ((isr >> 16) & 0xff) {
-              case 0:   /* Instruction intercept fault */
-              case 4:   /* Locked Data reference fault */
-              case 1:   /* Gate intercept trap */
-                return -1;
-
-              case 2:   /* System flag trap */
-                if (((isr >> 14) & 0x3) >= 2) {
-                        /* MOV SS, POP SS instructions */
-                        ia64_psr(regs)->id = 1;
-                        return 0;
-                } else
-                        return -1;
-        }
-        return -1;
-}
-
-int
-ia32_exception (struct pt_regs *regs, unsigned long isr)
-{
-        struct siginfo siginfo;
-
-        /* initialize these fields to avoid leaking kernel bits to user space: */
-        siginfo.si_errno = 0;
-        siginfo.si_flags = 0;
-        siginfo.si_isr = 0;
-        siginfo.si_imm = 0;
-        switch ((isr >> 16) & 0xff) {
-              case 1:
-              case 2:
-                siginfo.si_signo = SIGTRAP;
-                if (isr == 0)
-                        siginfo.si_code = TRAP_TRACE;
-                else if (isr & 0x4)
-                        siginfo.si_code = TRAP_BRANCH;
-                else
-                        siginfo.si_code = TRAP_BRKPT;
-                break;
-
-              case 3:
-                siginfo.si_signo = SIGTRAP;
-                siginfo.si_code = TRAP_BRKPT;
-                break;
-
-              case 0:   /* Divide fault */
-                siginfo.si_signo = SIGFPE;
-                siginfo.si_code = FPE_INTDIV;
-                break;
-
-              case 4:   /* Overflow */
-              case 5:   /* Bounds fault */
-                siginfo.si_signo = SIGFPE;
-                siginfo.si_code = 0;
-                break;
-
-              case 6:   /* Invalid Op-code */
-                siginfo.si_signo = SIGILL;
-                siginfo.si_code = ILL_ILLOPN;
-                break;
-
-              case 7:   /* FP DNA */
-              case 8:   /* Double Fault */
-              case 9:   /* Invalid TSS */
-              case 11:  /* Segment not present */
-              case 12:  /* Stack fault */
-              case 13:  /* General Protection Fault */
-                siginfo.si_signo = SIGSEGV;
-                siginfo.si_code = 0;
-                break;
-
-              case 16:  /* Pending FP error */
-                {
-                        unsigned long fsr, fcr;
-
-                        fsr = ia64_getreg(_IA64_REG_AR_FSR);
-                        fcr = ia64_getreg(_IA64_REG_AR_FCR);
-
-                        siginfo.si_signo = SIGFPE;
-                        /*
-                         * (~cwd & swd) will mask out exceptions that are not set to unmasked
-                         * status.  0x3f is the exception bits in these regs, 0x200 is the
-                         * C1 reg you need in case of a stack fault, 0x040 is the stack
-                         * fault bit.  We should only be taking one exception at a time,
-                         * so if this combination doesn't produce any single exception,
-                         * then we have a bad program that isn't synchronizing its FPU usage
-                         * and it will suffer the consequences since we won't be able to
-                         * fully reproduce the context of the exception
-                         */
-                        siginfo.si_isr = isr;
-                        siginfo.si_flags = __ISR_VALID;
-                        switch(((~fcr) & (fsr & 0x3f)) | (fsr & 0x240)) {
-                                case 0x000:
-                                default:
-                                        siginfo.si_code = 0;
-                                        break;
-                                case 0x001: /* Invalid Op */
-                                case 0x040: /* Stack Fault */
-                                case 0x240: /* Stack Fault | Direction */
-                                        siginfo.si_code = FPE_FLTINV;
-                                        break;
-                                case 0x002: /* Denormalize */
-                                case 0x010: /* Underflow */
-                                        siginfo.si_code = FPE_FLTUND;
-                                        break;
-                                case 0x004: /* Zero Divide */
-                                        siginfo.si_code = FPE_FLTDIV;
-                                        break;
-                                case 0x008: /* Overflow */
-                                        siginfo.si_code = FPE_FLTOVF;
-                                        break;
-                                case 0x020: /* Precision */
-                                        siginfo.si_code = FPE_FLTRES;
-                                        break;
-                        }
-
-                        break;
-                }
-
-              case 17:  /* Alignment check */
-                siginfo.si_signo = SIGSEGV;
-                siginfo.si_code = BUS_ADRALN;
-                break;
-
-              case 19:  /* SSE Numeric error */
-                siginfo.si_signo = SIGFPE;
-                siginfo.si_code = 0;
-                break;
-
-              default:
-                return -1;
-        }
-        force_sig_info(siginfo.si_signo, &siginfo, current);
-        return 0;
-}
diff --git a/arch/ia64/ia32/ia32priv.h b/arch/ia64/ia32/ia32priv.h
deleted file mode 100644
index 0f15349c3c6b..000000000000
--- a/arch/ia64/ia32/ia32priv.h
+++ /dev/null
@@ -1,532 +0,0 @@
-#ifndef _ASM_IA64_IA32_PRIV_H
-#define _ASM_IA64_IA32_PRIV_H
-
-
-#include <asm/ia32.h>
-
-#ifdef CONFIG_IA32_SUPPORT
-
-#include <linux/binfmts.h>
-#include <linux/compat.h>
-#include <linux/rbtree.h>
-
-#include <asm/processor.h>
-
-/*
- * 32 bit structures for IA32 support.
- */
-
-#define IA32_PAGE_SIZE          (1UL << IA32_PAGE_SHIFT)
-#define IA32_PAGE_MASK          (~(IA32_PAGE_SIZE - 1))
-#define IA32_PAGE_ALIGN(addr)   (((addr) + IA32_PAGE_SIZE - 1) & IA32_PAGE_MASK)
-#define IA32_CLOCKS_PER_SEC     100     /* Cast in stone for IA32 Linux */
-
-/*
- * partially mapped pages provide precise accounting of which 4k sub pages
- * are mapped and which ones are not, thereby improving IA-32 compatibility.
- */
-struct ia64_partial_page {
-        struct ia64_partial_page *next; /* linked list, sorted by address */
-        struct rb_node          pp_rb;
-        /* 64K is the largest "normal" page supported by ia64 ABI. So 4K*64
-         * should suffice.*/
-        unsigned long           bitmap;
-        unsigned int            base;
-};
-
-struct ia64_partial_page_list {
-        struct ia64_partial_page *pp_head; /* list head, points to the lowest
-                                           * addressed partial page */
-        struct rb_root          ppl_rb;
-        struct ia64_partial_page *pp_hint; /* pp_hint->next is the last
-                                           * accessed partial page */
-        atomic_t                pp_count; /* reference count */
-};
-
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-struct ia64_partial_page_list* ia32_init_pp_list (void);
-#else
-# define ia32_init_pp_list()    0
-#endif
-
-/* sigcontext.h */
-/*
- * As documented in the iBCS2 standard..
- *
- * The first part of "struct _fpstate" is just the
- * normal i387 hardware setup, the extra "status"
- * word is used to save the coprocessor status word
- * before entering the handler.
- */
-struct _fpreg_ia32 {
-       unsigned short significand[4];
-       unsigned short exponent;
-};
-
-struct _fpxreg_ia32 {
-        unsigned short significand[4];
-        unsigned short exponent;
-        unsigned short padding[3];
-};
-
-struct _xmmreg_ia32 {
-        unsigned int element[4];
-};
-
-
-struct _fpstate_ia32 {
-       unsigned int    cw,
-                       sw,
-                       tag,
-                       ipoff,
-                       cssel,
-                       dataoff,
-                       datasel;
-       struct _fpreg_ia32      _st[8];
-       unsigned short  status;
-       unsigned short  magic;          /* 0xffff = regular FPU data only */
-
-       /* FXSR FPU environment */
-       unsigned int         _fxsr_env[6];   /* FXSR FPU env is ignored */
-       unsigned int         mxcsr;
-       unsigned int         reserved;
-       struct _fpxreg_ia32  _fxsr_st[8];    /* FXSR FPU reg data is ignored */
-       struct _xmmreg_ia32  _xmm[8];
-       unsigned int         padding[56];
-};
-
-struct sigcontext_ia32 {
-       unsigned short gs, __gsh;
-       unsigned short fs, __fsh;
-       unsigned short es, __esh;
-       unsigned short ds, __dsh;
-       unsigned int edi;
-       unsigned int esi;
-       unsigned int ebp;
-       unsigned int esp;
-       unsigned int ebx;
-       unsigned int edx;
-       unsigned int ecx;
-       unsigned int eax;
-       unsigned int trapno;
-       unsigned int err;
-       unsigned int eip;
-       unsigned short cs, __csh;
-       unsigned int eflags;
-       unsigned int esp_at_signal;
-       unsigned short ss, __ssh;
-       unsigned int fpstate;            /* really (struct _fpstate_ia32 *) */
-       unsigned int oldmask;
-       unsigned int cr2;
-};
-
-/* user.h */
-/*
- * IA32 (Pentium III/4) FXSR, SSE support
- *
- * Provide support for the GDB 5.0+ PTRACE_{GET|SET}FPXREGS requests for
- * interacting with the FXSR-format floating point environment.  Floating
- * point data can be accessed in the regular format in the usual manner,
- * and both the standard and SIMD floating point data can be accessed via
- * the new ptrace requests.  In either case, changes to the FPU environment
- * will be reflected in the task's state as expected.
- */
-struct ia32_user_i387_struct {
-        int     cwd;
-        int     swd;
-        int     twd;
-        int     fip;
-        int     fcs;
-        int     foo;
-        int     fos;
-        /* 8*10 bytes for each FP-reg = 80 bytes */
-        struct _fpreg_ia32      st_space[8];
-};
-
-struct ia32_user_fxsr_struct {
-        unsigned short  cwd;
-        unsigned short  swd;
-        unsigned short  twd;
-        unsigned short  fop;
-        int     fip;
-        int     fcs;
-        int     foo;
-        int     fos;
-        int     mxcsr;
-        int     reserved;
-        int     st_space[32];   /* 8*16 bytes for each FP-reg = 128 bytes */
-        int     xmm_space[32];  /* 8*16 bytes for each XMM-reg = 128 bytes */
-        int     padding[56];
-};
-
-/* signal.h */
-#define IA32_SET_SA_HANDLER(ka,handler,restorer)                                \
-                                ((ka)->sa.sa_handler = (__sighandler_t)         \
-                                        (((unsigned long)(restorer) << 32)      \
-                                         | ((handler) & 0xffffffff)))
-#define IA32_SA_HANDLER(ka)     ((unsigned long) (ka)->sa.sa_handler & 0xffffffff)
-#define IA32_SA_RESTORER(ka)    ((unsigned long) (ka)->sa.sa_handler >> 32)
-
-#define __IA32_NR_sigreturn 119
-#define __IA32_NR_rt_sigreturn 173
-
-struct sigaction32 {
-       unsigned int sa_handler;         /* Really a pointer, but need to deal with 32 bits */
-       unsigned int sa_flags;
-       unsigned int sa_restorer;        /* Another 32 bit pointer */
-       compat_sigset_t sa_mask;         /* A 32 bit mask */
-};
-
-struct old_sigaction32 {
-       unsigned int  sa_handler;        /* Really a pointer, but need to deal
-                                             with 32 bits */
-       compat_old_sigset_t sa_mask;             /* A 32 bit mask */
-       unsigned int sa_flags;
-       unsigned int sa_restorer;        /* Another 32 bit pointer */
-};
-
-typedef struct sigaltstack_ia32 {
-        unsigned int    ss_sp;
-        int             ss_flags;
-        unsigned int    ss_size;
-} stack_ia32_t;
-
-struct ucontext_ia32 {
-        unsigned int      uc_flags;
-        unsigned int      uc_link;
-        stack_ia32_t      uc_stack;
-        struct sigcontext_ia32 uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-struct stat64 {
-        unsigned long long      st_dev;
-        unsigned char   __pad0[4];
-        unsigned int    __st_ino;
-        unsigned int    st_mode;
-        unsigned int    st_nlink;
-        unsigned int    st_uid;
-        unsigned int    st_gid;
-        unsigned long long      st_rdev;
-        unsigned char   __pad3[4];
-        unsigned int    st_size_lo;
-        unsigned int    st_size_hi;
-        unsigned int    st_blksize;
-        unsigned int    st_blocks;      /* Number 512-byte blocks allocated. */
-        unsigned int    __pad4;         /* future possible st_blocks high bits */
-        unsigned int    st_atime;
-        unsigned int    st_atime_nsec;
-        unsigned int    st_mtime;
-        unsigned int    st_mtime_nsec;
-        unsigned int    st_ctime;
-        unsigned int    st_ctime_nsec;
-        unsigned int    st_ino_lo;
-        unsigned int    st_ino_hi;
-};
-
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_errno;
-        int si_code;
-
-        union {
-                int _pad[((128/sizeof(int)) - 3)];
-
-                /* kill() */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        compat_timer_t _tid;            /* timer id */
-                        int _overrun;           /* overrun count */
-                        char _pad[sizeof(unsigned int) - sizeof(int)];
-                        compat_sigval_t _sigval;        /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        unsigned int _pid;      /* sender's pid */
-                        unsigned int _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        unsigned int _pid;      /* which child */
-                        unsigned int _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        unsigned int _addr;     /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} compat_siginfo_t;
-
-/*
- * IA-32 ELF specific definitions for IA-64.
- */
-
-#define _ASM_IA64_ELF_H         /* Don't include elf.h */
-
-#include <linux/sched.h>
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_386)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_386
-
-#define IA32_STACK_TOP          IA32_PAGE_OFFSET
-#define IA32_GATE_OFFSET        IA32_PAGE_OFFSET
-#define IA32_GATE_END           IA32_PAGE_OFFSET + PAGE_SIZE
-
-/*
- * The system segments (GDT, TSS, LDT) have to be mapped below 4GB so the IA-32 engine can
- * access them.
- */
-#define IA32_GDT_OFFSET         (IA32_PAGE_OFFSET + PAGE_SIZE)
-#define IA32_TSS_OFFSET         (IA32_PAGE_OFFSET + 2*PAGE_SIZE)
-#define IA32_LDT_OFFSET         (IA32_PAGE_OFFSET + 3*PAGE_SIZE)
-
-#define ELF_EXEC_PAGESIZE       IA32_PAGE_SIZE
-
-/*
- * This is the location that an ET_DYN program is loaded if exec'ed.
- * Typical use of this is to invoke "./ld.so someprog" to test out a
- * new version of the loader.  We need to make sure that it is out of
- * the way of the program that it will "exec", and that there is
- * sufficient room for the brk.
- */
-#define ELF_ET_DYN_BASE         (IA32_PAGE_OFFSET/3 + 0x1000000)
-
-void ia64_elf32_init(struct pt_regs *regs);
-#define ELF_PLAT_INIT(_r, load_addr)    ia64_elf32_init(_r)
-
-/* This macro yields a bitmask that programs can use to figure out
-   what instruction set this CPU supports.  */
-#define ELF_HWCAP       0
-
-/* This macro yields a string that ld.so will use to load
-   implementation specific libraries for optimization.  Not terribly
-   relevant until we have real hardware to play with... */
-#define ELF_PLATFORM    NULL
-
-#ifdef __KERNEL__
-# define SET_PERSONALITY(EX)                            \
-        (current->personality = PER_LINUX)
-#endif
-
-#define IA32_EFLAG      0x200
-
-/*
- * IA-32 ELF specific definitions for IA-64.
- */
-
-#define __USER_CS      0x23
-#define __USER_DS      0x2B
-
-/*
- * The per-cpu GDT has 32 entries: see <asm-i386/segment.h>
- */
-#define GDT_ENTRIES 32
-
-#define GDT_SIZE        (GDT_ENTRIES * 8)
-
-#define TSS_ENTRY 14
-#define LDT_ENTRY       (TSS_ENTRY + 1)
-
-#define IA32_SEGSEL_RPL         (0x3 << 0)
-#define IA32_SEGSEL_TI          (0x1 << 2)
-#define IA32_SEGSEL_INDEX_SHIFT 3
-
-#define _TSS                    ((unsigned long) TSS_ENTRY << IA32_SEGSEL_INDEX_SHIFT)
-#define _LDT                    ((unsigned long) LDT_ENTRY << IA32_SEGSEL_INDEX_SHIFT)
-
-#define IA32_SEG_BASE           16
-#define IA32_SEG_TYPE           40
-#define IA32_SEG_SYS            44
-#define IA32_SEG_DPL            45
-#define IA32_SEG_P              47
-#define IA32_SEG_HIGH_LIMIT     48
-#define IA32_SEG_AVL            52
-#define IA32_SEG_DB             54
-#define IA32_SEG_G              55
-#define IA32_SEG_HIGH_BASE      56
-
-#define IA32_SEG_DESCRIPTOR(base, limit, segtype, nonsysseg, dpl, segpresent, avl, segdb, gran) \
-               (((limit) & 0xffff)                                                              \
-                | (((unsigned long) (base) & 0xffffff) << IA32_SEG_BASE)                        \
-                | ((unsigned long) (segtype) << IA32_SEG_TYPE)                                  \
-                | ((unsigned long) (nonsysseg) << IA32_SEG_SYS)                                 \
-                | ((unsigned long) (dpl) << IA32_SEG_DPL)                                       \
-                | ((unsigned long) (segpresent) << IA32_SEG_P)                                  \
-                | ((((unsigned long) (limit) >> 16) & 0xf) << IA32_SEG_HIGH_LIMIT)              \
-                | ((unsigned long) (avl) << IA32_SEG_AVL)                                       \
-                | ((unsigned long) (segdb) << IA32_SEG_DB)                                      \
-                | ((unsigned long) (gran) << IA32_SEG_G)                                        \
-                | ((((unsigned long) (base) >> 24) & 0xff) << IA32_SEG_HIGH_BASE))
-
-#define SEG_LIM         32
-#define SEG_TYPE        52
-#define SEG_SYS         56
-#define SEG_DPL         57
-#define SEG_P           59
-#define SEG_AVL         60
-#define SEG_DB          62
-#define SEG_G           63
-
-/* Unscramble an IA-32 segment descriptor into the IA-64 format.  */
-#define IA32_SEG_UNSCRAMBLE(sd)                                                                  \
-        (   (((sd) >> IA32_SEG_BASE) & 0xffffff) | ((((sd) >> IA32_SEG_HIGH_BASE) & 0xff) << 24) \
-         | ((((sd) & 0xffff) | ((((sd) >> IA32_SEG_HIGH_LIMIT) & 0xf) << 16)) << SEG_LIM)        \
-         | ((((sd) >> IA32_SEG_TYPE) & 0xf) << SEG_TYPE)                                         \
-         | ((((sd) >> IA32_SEG_SYS) & 0x1) << SEG_SYS)                                           \
-         | ((((sd) >> IA32_SEG_DPL) & 0x3) << SEG_DPL)                                           \
-         | ((((sd) >> IA32_SEG_P) & 0x1) << SEG_P)                                               \
-         | ((((sd) >> IA32_SEG_AVL) & 0x1) << SEG_AVL)                                           \
-         | ((((sd) >> IA32_SEG_DB) & 0x1) << SEG_DB)                                             \
-         | ((((sd) >> IA32_SEG_G) & 0x1) << SEG_G))
-
-#define IA32_IOBASE     0x2000000000000000UL /* Virtual address for I/O space */
-
-#define IA32_CR0        0x80000001      /* Enable PG and PE bits */
-#define IA32_CR4        0x600           /* MMXEX and FXSR on */
-
-/*
- *  IA32 floating point control registers starting values
- */
-
-#define IA32_FSR_DEFAULT        0x55550000              /* set all tag bits */
-#define IA32_FCR_DEFAULT        0x17800000037fUL        /* extended precision, all masks */
-
-#define IA32_PTRACE_GETREGS     12
-#define IA32_PTRACE_SETREGS     13
-#define IA32_PTRACE_GETFPREGS   14
-#define IA32_PTRACE_SETFPREGS   15
-#define IA32_PTRACE_GETFPXREGS  18
-#define IA32_PTRACE_SETFPXREGS  19
-
-#define ia32_start_thread(regs,new_ip,new_sp) do {                              \
-        set_fs(USER_DS);                                                        \
-        ia64_psr(regs)->cpl = 3;        /* set user mode */                     \
-        ia64_psr(regs)->ri = 0;         /* clear return slot number */          \
-        ia64_psr(regs)->is = 1;         /* IA-32 instruction set */             \
-        regs->cr_iip = new_ip;                                                  \
-        regs->ar_rsc = 0xc;             /* enforced lazy mode, priv. level 3 */ \
-        regs->ar_rnat = 0;                                                      \
-        regs->loadrs = 0;                                                       \
-        regs->r12 = new_sp;                                                     \
-} while (0)
-
-/*
- * Local Descriptor Table (LDT) related declarations.
- */
-
-#define IA32_LDT_ENTRIES        8192            /* Maximum number of LDT entries supported. */
-#define IA32_LDT_ENTRY_SIZE     8               /* The size of each LDT entry. */
-
-#define LDT_entry_a(info) \
-        ((((info)->base_addr & 0x0000ffff) << 16) | ((info)->limit & 0x0ffff))
-
-#define LDT_entry_b(info)                               \
-        (((info)->base_addr & 0xff000000) |             \
-        (((info)->base_addr & 0x00ff0000) >> 16) |      \
-        ((info)->limit & 0xf0000) |                     \
-        (((info)->read_exec_only ^ 1) << 9) |           \
-        ((info)->contents << 10) |                      \
-        (((info)->seg_not_present ^ 1) << 15) |         \
-        ((info)->seg_32bit << 22) |                     \
-        ((info)->limit_in_pages << 23) |                \
-        ((info)->useable << 20) |                       \
-        0x7100)
-
-#define LDT_empty(info) (                       \
-        (info)->base_addr       == 0    &&      \
-        (info)->limit           == 0    &&      \
-        (info)->contents        == 0    &&      \
-        (info)->read_exec_only  == 1    &&      \
-        (info)->seg_32bit       == 0    &&      \
-        (info)->limit_in_pages  == 0    &&      \
-        (info)->seg_not_present == 1    &&      \
-        (info)->useable         == 0    )
-
-static inline void
-load_TLS (struct thread_struct *t, unsigned int cpu)
-{
-        extern unsigned long *cpu_gdt_table[NR_CPUS];
-
-        memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 0, &t->tls_array[0], sizeof(long));
-        memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 1, &t->tls_array[1], sizeof(long));
-        memcpy(cpu_gdt_table[cpu] + GDT_ENTRY_TLS_MIN + 2, &t->tls_array[2], sizeof(long));
-}
-
-struct ia32_user_desc {
-        unsigned int entry_number;
-        unsigned int base_addr;
-        unsigned int limit;
-        unsigned int seg_32bit:1;
-        unsigned int contents:2;
-        unsigned int read_exec_only:1;
-        unsigned int limit_in_pages:1;
-        unsigned int seg_not_present:1;
-        unsigned int useable:1;
-};
-
-struct linux_binprm;
-
-extern void ia32_init_addr_space (struct pt_regs *regs);
-extern int ia32_setup_arg_pages (struct linux_binprm *bprm, int exec_stack);
-extern unsigned long ia32_do_mmap (struct file *, unsigned long, unsigned long, int, int, loff_t);
-extern void ia32_load_segment_descriptors (struct task_struct *task);
-
-#define ia32f2ia64f(dst,src)                    \
-do {                                            \
-        ia64_ldfe(6,src);                       \
-        ia64_stop();                            \
-        ia64_stf_spill(dst, 6);                 \
-} while(0)
-
-#define ia64f2ia32f(dst,src)                    \
-do {                                            \
-        ia64_ldf_fill(6, src);                  \
-        ia64_stop();                            \
-        ia64_stfe(dst, 6);                      \
-} while(0)
-
-struct user_regs_struct32 {
-        __u32 ebx, ecx, edx, esi, edi, ebp, eax;
-        unsigned short ds, __ds, es, __es;
-        unsigned short fs, __fs, gs, __gs;
-        __u32 orig_eax, eip;
-        unsigned short cs, __cs;
-        __u32 eflags, esp;
-        unsigned short ss, __ss;
-};
-
-/* Prototypes for use in elfcore32.h */
-extern int save_ia32_fpstate (struct task_struct *, struct ia32_user_i387_struct __user *);
-extern int save_ia32_fpxstate (struct task_struct *, struct ia32_user_fxsr_struct __user *);
-
-#endif /* !CONFIG_IA32_SUPPORT */
-
-#endif /* _ASM_IA64_IA32_PRIV_H */
diff --git a/arch/ia64/ia32/sys_ia32.c b/arch/ia64/ia32/sys_ia32.c
deleted file mode 100644
index 045b746b9808..000000000000
--- a/arch/ia64/ia32/sys_ia32.c
+++ /dev/null
@@ -1,2765 +0,0 @@
-/*
- * sys_ia32.c: Conversion between 32bit and 64bit native syscalls. Derived from sys_sparc32.c.
- *
- * Copyright (C) 2000           VA Linux Co
- * Copyright (C) 2000           Don Dugger <n0ano@valinux.com>
- * Copyright (C) 1999           Arun Sharma <arun.sharma@intel.com>
- * Copyright (C) 1997,1998      Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- * Copyright (C) 1997           David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 2000-2003, 2005 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- * Copyright (C) 2004           Gordon Jin <gordon.jin@intel.com>
- *
- * These routines maintain argument size conversion between 32bit and 64bit
- * environment.
- */
-
-#include <linux/kernel.h>
-#include <linux/syscalls.h>
-#include <linux/sysctl.h>
-#include <linux/sched.h>
-#include <linux/fs.h>
-#include <linux/file.h>
-#include <linux/signal.h>
-#include <linux/resource.h>
-#include <linux/times.h>
-#include <linux/utsname.h>
-#include <linux/smp.h>
-#include <linux/smp_lock.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/mm.h>
-#include <linux/shm.h>
-#include <linux/slab.h>
-#include <linux/uio.h>
-#include <linux/socket.h>
-#include <linux/quota.h>
-#include <linux/poll.h>
-#include <linux/eventpoll.h>
-#include <linux/personality.h>
-#include <linux/ptrace.h>
-#include <linux/regset.h>
-#include <linux/stat.h>
-#include <linux/ipc.h>
-#include <linux/capability.h>
-#include <linux/compat.h>
-#include <linux/vfs.h>
-#include <linux/mman.h>
-#include <linux/mutex.h>
-
-#include <asm/intrinsics.h>
-#include <asm/types.h>
-#include <asm/uaccess.h>
-#include <asm/unistd.h>
-
-#include "ia32priv.h"
-
-#include <net/scm.h>
-#include <net/sock.h>
-
-#define DEBUG   0
-
-#if DEBUG
-# define DBG(fmt...)    printk(KERN_DEBUG fmt)
-#else
-# define DBG(fmt...)
-#endif
-
-#define ROUND_UP(x,a)   ((__typeof__(x))(((unsigned long)(x) + ((a) - 1)) & ~((a) - 1)))
-
-#define OFFSET4K(a)             ((a) & 0xfff)
-#define PAGE_START(addr)        ((addr) & PAGE_MASK)
-#define MINSIGSTKSZ_IA32        2048
-
-#define high2lowuid(uid) ((uid) > 65535 ? 65534 : (uid))
-#define high2lowgid(gid) ((gid) > 65535 ? 65534 : (gid))
-
-/*
- * Anything that modifies or inspects ia32 user virtual memory must hold this semaphore
- * while doing so.
- */
-/* XXX make per-mm: */
-static DEFINE_MUTEX(ia32_mmap_mutex);
-
-asmlinkage long
-sys32_execve (char __user *name, compat_uptr_t __user *argv, compat_uptr_t __user *envp,
-              struct pt_regs *regs)
-{
-        long error;
-        char *filename;
-        unsigned long old_map_base, old_task_size, tssd;
-
-        filename = getname(name);
-        error = PTR_ERR(filename);
-        if (IS_ERR(filename))
-                return error;
-
-        old_map_base  = current->thread.map_base;
-        old_task_size = current->thread.task_size;
-        tssd = ia64_get_kr(IA64_KR_TSSD);
-
-        /* we may be exec'ing a 64-bit process: reset map base, task-size, and io-base: */
-        current->thread.map_base  = DEFAULT_MAP_BASE;
-        current->thread.task_size = DEFAULT_TASK_SIZE;
-        ia64_set_kr(IA64_KR_IO_BASE, current->thread.old_iob);
-        ia64_set_kr(IA64_KR_TSSD, current->thread.old_k1);
-
-        error = compat_do_execve(filename, argv, envp, regs);
-        putname(filename);
-
-        if (error < 0) {
-                /* oops, execve failed, switch back to old values... */
-                ia64_set_kr(IA64_KR_IO_BASE, IA32_IOBASE);
-                ia64_set_kr(IA64_KR_TSSD, tssd);
-                current->thread.map_base  = old_map_base;
-                current->thread.task_size = old_task_size;
-        }
-
-        return error;
-}
-
-
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-
-
-static int
-get_page_prot (struct vm_area_struct *vma, unsigned long addr)
-{
-        int prot = 0;
-
-        if (!vma || vma->vm_start > addr)
-                return 0;
-
-        if (vma->vm_flags & VM_READ)
-                prot |= PROT_READ;
-        if (vma->vm_flags & VM_WRITE)
-                prot |= PROT_WRITE;
-        if (vma->vm_flags & VM_EXEC)
-                prot |= PROT_EXEC;
-        return prot;
-}
-
-/*
- * Map a subpage by creating an anonymous page that contains the union of the old page and
- * the subpage.
- */
-static unsigned long
-mmap_subpage (struct file *file, unsigned long start, unsigned long end, int prot, int flags,
-              loff_t off)
-{
-        void *page = NULL;
-        struct inode *inode;
-        unsigned long ret = 0;
-        struct vm_area_struct *vma = find_vma(current->mm, start);
-        int old_prot = get_page_prot(vma, start);
-
-        DBG("mmap_subpage(file=%p,start=0x%lx,end=0x%lx,prot=%x,flags=%x,off=0x%llx)\n",
-            file, start, end, prot, flags, off);
-
-
-        /* Optimize the case where the old mmap and the new mmap are both anonymous */
-        if ((old_prot & PROT_WRITE) && (flags & MAP_ANONYMOUS) && !vma->vm_file) {
-                if (clear_user((void __user *) start, end - start)) {
-                        ret = -EFAULT;
-                        goto out;
-                }
-                goto skip_mmap;
-        }
-
-        page = (void *) get_zeroed_page(GFP_KERNEL);
-        if (!page)
-                return -ENOMEM;
-
-        if (old_prot)
-                copy_from_user(page, (void __user *) PAGE_START(start), PAGE_SIZE);
-
-        down_write(&current->mm->mmap_sem);
-        {
-                ret = do_mmap(NULL, PAGE_START(start), PAGE_SIZE, prot | PROT_WRITE,
-                              flags | MAP_FIXED | MAP_ANONYMOUS, 0);
-        }
-        up_write(&current->mm->mmap_sem);
-
-        if (IS_ERR((void *) ret))
-                goto out;
-
-        if (old_prot) {
-                /* copy back the old page contents.  */
-                if (offset_in_page(start))
-                        copy_to_user((void __user *) PAGE_START(start), page,
-                                     offset_in_page(start));
-                if (offset_in_page(end))
-                        copy_to_user((void __user *) end, page + offset_in_page(end),
-                                     PAGE_SIZE - offset_in_page(end));
-        }
-
-        if (!(flags & MAP_ANONYMOUS)) {
-                /* read the file contents */
-                inode = file->f_path.dentry->d_inode;
-                if (!inode->i_fop || !file->f_op->read
-                    || ((*file->f_op->read)(file, (char __user *) start, end - start, &off) < 0))
-                {
-                        ret = -EINVAL;
-                        goto out;
-                }
-        }
-
- skip_mmap:
-        if (!(prot & PROT_WRITE))
-                ret = sys_mprotect(PAGE_START(start), PAGE_SIZE, prot | old_prot);
-  out:
-        if (page)
-                free_page((unsigned long) page);
-        return ret;
-}
-
-/* SLAB cache for ia64_partial_page structures */
-struct kmem_cache *ia64_partial_page_cachep;
-
-/*
- * init ia64_partial_page_list.
- * return 0 means kmalloc fail.
- */
-struct ia64_partial_page_list*
-ia32_init_pp_list(void)
-{
-        struct ia64_partial_page_list *p;
-
-        if ((p = kmalloc(sizeof(*p), GFP_KERNEL)) == NULL)
-                return p;
-        p->pp_head = NULL;
-        p->ppl_rb = RB_ROOT;
-        p->pp_hint = NULL;
-        atomic_set(&p->pp_count, 1);
-        return p;
-}
-
-/*
- * Search for the partial page with @start in partial page list @ppl.
- * If finds the partial page, return the found partial page.
- * Else, return 0 and provide @pprev, @rb_link, @rb_parent to
- * be used by later __ia32_insert_pp().
- */
-static struct ia64_partial_page *
-__ia32_find_pp(struct ia64_partial_page_list *ppl, unsigned int start,
-        struct ia64_partial_page **pprev, struct rb_node ***rb_link,
-        struct rb_node **rb_parent)
-{
-        struct ia64_partial_page *pp;
-        struct rb_node **__rb_link, *__rb_parent, *rb_prev;
-
-        pp = ppl->pp_hint;
-        if (pp && pp->base == start)
-                return pp;
-
-        __rb_link = &ppl->ppl_rb.rb_node;
-        rb_prev = __rb_parent = NULL;
-
-        while (*__rb_link) {
-                __rb_parent = *__rb_link;
-                pp = rb_entry(__rb_parent, struct ia64_partial_page, pp_rb);
-
-                if (pp->base == start) {
-                        ppl->pp_hint = pp;
-                        return pp;
-                } else if (pp->base < start) {
-                        rb_prev = __rb_parent;
-                        __rb_link = &__rb_parent->rb_right;
-                } else {
-                        __rb_link = &__rb_parent->rb_left;
-                }
-        }
-
-        *rb_link = __rb_link;
-        *rb_parent = __rb_parent;
-        *pprev = NULL;
-        if (rb_prev)
-                *pprev = rb_entry(rb_prev, struct ia64_partial_page, pp_rb);
-        return NULL;
-}
-
-/*
- * insert @pp into @ppl.
- */
-static void
-__ia32_insert_pp(struct ia64_partial_page_list *ppl,
-        struct ia64_partial_page *pp, struct ia64_partial_page *prev,
-        struct rb_node **rb_link, struct rb_node *rb_parent)
-{
-        /* link list */
-        if (prev) {
-                pp->next = prev->next;
-                prev->next = pp;
-        } else {
-                ppl->pp_head = pp;
-                if (rb_parent)
-                        pp->next = rb_entry(rb_parent,
-                                struct ia64_partial_page, pp_rb);
-                else
-                        pp->next = NULL;
-        }
-
-        /* link rb */
-        rb_link_node(&pp->pp_rb, rb_parent, rb_link);
-        rb_insert_color(&pp->pp_rb, &ppl->ppl_rb);
-
-        ppl->pp_hint = pp;
-}
-
-/*
- * delete @pp from partial page list @ppl.
- */
-static void
-__ia32_delete_pp(struct ia64_partial_page_list *ppl,
-        struct ia64_partial_page *pp, struct ia64_partial_page *prev)
-{
-        if (prev) {
-                prev->next = pp->next;
-                if (ppl->pp_hint == pp)
-                        ppl->pp_hint = prev;
-        } else {
-                ppl->pp_head = pp->next;
-                if (ppl->pp_hint == pp)
-                        ppl->pp_hint = pp->next;
-        }
-        rb_erase(&pp->pp_rb, &ppl->ppl_rb);
-        kmem_cache_free(ia64_partial_page_cachep, pp);
-}
-
-static struct ia64_partial_page *
-__pp_prev(struct ia64_partial_page *pp)
-{
-        struct rb_node *prev = rb_prev(&pp->pp_rb);
-        if (prev)
-                return rb_entry(prev, struct ia64_partial_page, pp_rb);
-        else
-                return NULL;
-}
-
-/*
- * Delete partial pages with address between @start and @end.
- * @start and @end are page aligned.
- */
-static void
-__ia32_delete_pp_range(unsigned int start, unsigned int end)
-{
-        struct ia64_partial_page *pp, *prev;
-        struct rb_node **rb_link, *rb_parent;
-
-        if (start >= end)
-                return;
-
-        pp = __ia32_find_pp(current->thread.ppl, start, &prev,
-                                        &rb_link, &rb_parent);
-        if (pp)
-                prev = __pp_prev(pp);
-        else {
-                if (prev)
-                        pp = prev->next;
-                else
-                        pp = current->thread.ppl->pp_head;
-        }
-
-        while (pp && pp->base < end) {
-                struct ia64_partial_page *tmp = pp->next;
-                __ia32_delete_pp(current->thread.ppl, pp, prev);
-                pp = tmp;
-        }
-}
-
-/*
- * Set the range between @start and @end in bitmap.
- * @start and @end should be IA32 page aligned and in the same IA64 page.
- */
-static int
-__ia32_set_pp(unsigned int start, unsigned int end, int flags)
-{
-        struct ia64_partial_page *pp, *prev;
-        struct rb_node ** rb_link, *rb_parent;
-        unsigned int pstart, start_bit, end_bit, i;
-
-        pstart = PAGE_START(start);
-        start_bit = (start % PAGE_SIZE) / IA32_PAGE_SIZE;
-        end_bit = (end % PAGE_SIZE) / IA32_PAGE_SIZE;
-        if (end_bit == 0)
-                end_bit = PAGE_SIZE / IA32_PAGE_SIZE;
-        pp = __ia32_find_pp(current->thread.ppl, pstart, &prev,
-                                        &rb_link, &rb_parent);
-        if (pp) {
-                for (i = start_bit; i < end_bit; i++)
-                        set_bit(i, &pp->bitmap);
-                /*
-                 * Check: if this partial page has been set to a full page,
-                 * then delete it.
-                 */
-                if (find_first_zero_bit(&pp->bitmap, sizeof(pp->bitmap)*8) >=
-                                PAGE_SIZE/IA32_PAGE_SIZE) {
-                        __ia32_delete_pp(current->thread.ppl, pp, __pp_prev(pp));
-                }
-                return 0;
-        }
-
-        /*
-         * MAP_FIXED may lead to overlapping mmap.
-         * In this case, the requested mmap area may already mmaped as a full
-         * page. So check vma before adding a new partial page.
-         */
-        if (flags & MAP_FIXED) {
-                struct vm_area_struct *vma = find_vma(current->mm, pstart);
-                if (vma && vma->vm_start <= pstart)
-                        return 0;
-        }
-
-        /* new a ia64_partial_page */
-        pp = kmem_cache_alloc(ia64_partial_page_cachep, GFP_KERNEL);
-        if (!pp)
-                return -ENOMEM;
-        pp->base = pstart;
-        pp->bitmap = 0;
-        for (i=start_bit; i<end_bit; i++)
-                set_bit(i, &(pp->bitmap));
-        pp->next = NULL;
-        __ia32_insert_pp(current->thread.ppl, pp, prev, rb_link, rb_parent);
-        return 0;
-}
-
-/*
- * @start and @end should be IA32 page aligned, but don't need to be in the
- * same IA64 page. Split @start and @end to make sure they're in the same IA64
- * page, then call __ia32_set_pp().
- */
-static void
-ia32_set_pp(unsigned int start, unsigned int end, int flags)
-{
-        down_write(&current->mm->mmap_sem);
-        if (flags & MAP_FIXED) {
-                /*
-                 * MAP_FIXED may lead to overlapping mmap. When this happens,
-                 * a series of complete IA64 pages results in deletion of
-                 * old partial pages in that range.
-                 */
-                __ia32_delete_pp_range(PAGE_ALIGN(start), PAGE_START(end));
-        }
-
-        if (end < PAGE_ALIGN(start)) {
-                __ia32_set_pp(start, end, flags);
-        } else {
-                if (offset_in_page(start))
-                        __ia32_set_pp(start, PAGE_ALIGN(start), flags);
-                if (offset_in_page(end))
-                        __ia32_set_pp(PAGE_START(end), end, flags);
-        }
-        up_write(&current->mm->mmap_sem);
-}
-
-/*
- * Unset the range between @start and @end in bitmap.
- * @start and @end should be IA32 page aligned and in the same IA64 page.
- * After doing that, if the bitmap is 0, then free the page and return 1,
- *      else return 0;
- * If not find the partial page in the list, then
- *      If the vma exists, then the full page is set to a partial page;
- *      Else return -ENOMEM.
- */
-static int
-__ia32_unset_pp(unsigned int start, unsigned int end)
-{
-        struct ia64_partial_page *pp, *prev;
-        struct rb_node ** rb_link, *rb_parent;
-        unsigned int pstart, start_bit, end_bit, i;
-        struct vm_area_struct *vma;
-
-        pstart = PAGE_START(start);
-        start_bit = (start % PAGE_SIZE) / IA32_PAGE_SIZE;
-        end_bit = (end % PAGE_SIZE) / IA32_PAGE_SIZE;
-        if (end_bit == 0)
-                end_bit = PAGE_SIZE / IA32_PAGE_SIZE;
-
-        pp = __ia32_find_pp(current->thread.ppl, pstart, &prev,
-                                        &rb_link, &rb_parent);
-        if (pp) {
-                for (i = start_bit; i < end_bit; i++)
-                        clear_bit(i, &pp->bitmap);
-                if (pp->bitmap == 0) {
-                        __ia32_delete_pp(current->thread.ppl, pp, __pp_prev(pp));
-                        return 1;
-                }
-                return 0;
-        }
-
-        vma = find_vma(current->mm, pstart);
-        if (!vma || vma->vm_start > pstart) {
-                return -ENOMEM;
-        }
-
-        /* new a ia64_partial_page */
-        pp = kmem_cache_alloc(ia64_partial_page_cachep, GFP_KERNEL);
-        if (!pp)
-                return -ENOMEM;
-        pp->base = pstart;
-        pp->bitmap = 0;
-        for (i = 0; i < start_bit; i++)
-                set_bit(i, &(pp->bitmap));
-        for (i = end_bit; i < PAGE_SIZE / IA32_PAGE_SIZE; i++)
-                set_bit(i, &(pp->bitmap));
-        pp->next = NULL;
-        __ia32_insert_pp(current->thread.ppl, pp, prev, rb_link, rb_parent);
-        return 0;
-}
-
-/*
- * Delete pp between PAGE_ALIGN(start) and PAGE_START(end) by calling
- * __ia32_delete_pp_range(). Unset possible partial pages by calling
- * __ia32_unset_pp().
- * The returned value see __ia32_unset_pp().
- */
-static int
-ia32_unset_pp(unsigned int *startp, unsigned int *endp)
-{
-        unsigned int start = *startp, end = *endp;
-        int ret = 0;
-
-        down_write(&current->mm->mmap_sem);
-
-        __ia32_delete_pp_range(PAGE_ALIGN(start), PAGE_START(end));
-
-        if (end < PAGE_ALIGN(start)) {
-                ret = __ia32_unset_pp(start, end);
-                if (ret == 1) {
-                        *startp = PAGE_START(start);
-                        *endp = PAGE_ALIGN(end);
-                }
-                if (ret == 0) {
-                        /* to shortcut sys_munmap() in sys32_munmap() */
-                        *startp = PAGE_START(start);
-                        *endp = PAGE_START(end);
-                }
-        } else {
-                if (offset_in_page(start)) {
-                        ret = __ia32_unset_pp(start, PAGE_ALIGN(start));
-                        if (ret == 1)
-                                *startp = PAGE_START(start);
-                        if (ret == 0)
-                                *startp = PAGE_ALIGN(start);
-                        if (ret < 0)
-                                goto out;
-                }
-                if (offset_in_page(end)) {
-                        ret = __ia32_unset_pp(PAGE_START(end), end);
-                        if (ret == 1)
-                                *endp = PAGE_ALIGN(end);
-                        if (ret == 0)
-                                *endp = PAGE_START(end);
-                }
-        }
-
- out:
-        up_write(&current->mm->mmap_sem);
-        return ret;
-}
-
-/*
- * Compare the range between @start and @end with bitmap in partial page.
- * @start and @end should be IA32 page aligned and in the same IA64 page.
- */
-static int
-__ia32_compare_pp(unsigned int start, unsigned int end)
-{
-        struct ia64_partial_page *pp, *prev;
-        struct rb_node ** rb_link, *rb_parent;
-        unsigned int pstart, start_bit, end_bit, size;
-        unsigned int first_bit, next_zero_bit;  /* the first range in bitmap */
-
-        pstart = PAGE_START(start);
-
-        pp = __ia32_find_pp(current->thread.ppl, pstart, &prev,
-                                        &rb_link, &rb_parent);
-        if (!pp)
-                return 1;
-
-        start_bit = (start % PAGE_SIZE) / IA32_PAGE_SIZE;
-        end_bit = (end % PAGE_SIZE) / IA32_PAGE_SIZE;
-        size = sizeof(pp->bitmap) * 8;
-        first_bit = find_first_bit(&pp->bitmap, size);
-        next_zero_bit = find_next_zero_bit(&pp->bitmap, size, first_bit);
-        if ((start_bit < first_bit) || (end_bit > next_zero_bit)) {
-                /* exceeds the first range in bitmap */
-                return -ENOMEM;
-        } else if ((start_bit == first_bit) && (end_bit == next_zero_bit)) {
-                first_bit = find_next_bit(&pp->bitmap, size, next_zero_bit);
-                if ((next_zero_bit < first_bit) && (first_bit < size))
-                        return 1;       /* has next range */
-                else
-                        return 0;       /* no next range */
-        } else
-                return 1;
-}
-
-/*
- * @start and @end should be IA32 page aligned, but don't need to be in the
- * same IA64 page. Split @start and @end to make sure they're in the same IA64
- * page, then call __ia32_compare_pp().
- *
- * Take this as example: the range is the 1st and 2nd 4K page.
- * Return 0 if they fit bitmap exactly, i.e. bitmap = 00000011;
- * Return 1 if the range doesn't cover whole bitmap, e.g. bitmap = 00001111;
- * Return -ENOMEM if the range exceeds the bitmap, e.g. bitmap = 00000001 or
- *      bitmap = 00000101.
- */
-static int
-ia32_compare_pp(unsigned int *startp, unsigned int *endp)
-{
-        unsigned int start = *startp, end = *endp;
-        int retval = 0;
-
-        down_write(&current->mm->mmap_sem);
-
-        if (end < PAGE_ALIGN(start)) {
-                retval = __ia32_compare_pp(start, end);
-                if (retval == 0) {
-                        *startp = PAGE_START(start);
-                        *endp = PAGE_ALIGN(end);
-                }
-        } else {
-                if (offset_in_page(start)) {
-                        retval = __ia32_compare_pp(start,
-                                                   PAGE_ALIGN(start));
-                        if (retval == 0)
-                                *startp = PAGE_START(start);
-                        if (retval < 0)
-                                goto out;
-                }
-                if (offset_in_page(end)) {
-                        retval = __ia32_compare_pp(PAGE_START(end), end);
-                        if (retval == 0)
-                                *endp = PAGE_ALIGN(end);
-                }
-        }
-
- out:
-        up_write(&current->mm->mmap_sem);
-        return retval;
-}
-
-static void
-__ia32_drop_pp_list(struct ia64_partial_page_list *ppl)
-{
-        struct ia64_partial_page *pp = ppl->pp_head;
-
-        while (pp) {
-                struct ia64_partial_page *next = pp->next;
-                kmem_cache_free(ia64_partial_page_cachep, pp);
-                pp = next;
-        }
-
-        kfree(ppl);
-}
-
-void
-ia32_drop_ia64_partial_page_list(struct task_struct *task)
-{
-        struct ia64_partial_page_list* ppl = task->thread.ppl;
-
-        if (ppl && atomic_dec_and_test(&ppl->pp_count))
-                __ia32_drop_pp_list(ppl);
-}
-
-/*
- * Copy current->thread.ppl to ppl (already initialized).
- */
-static int
-__ia32_copy_pp_list(struct ia64_partial_page_list *ppl)
-{
-        struct ia64_partial_page *pp, *tmp, *prev;
-        struct rb_node **rb_link, *rb_parent;
-
-        ppl->pp_head = NULL;
-        ppl->pp_hint = NULL;
-        ppl->ppl_rb = RB_ROOT;
-        rb_link = &ppl->ppl_rb.rb_node;
-        rb_parent = NULL;
-        prev = NULL;
-
-        for (pp = current->thread.ppl->pp_head; pp; pp = pp->next) {
-                tmp = kmem_cache_alloc(ia64_partial_page_cachep, GFP_KERNEL);
-                if (!tmp)
-                        return -ENOMEM;
-                *tmp = *pp;
-                __ia32_insert_pp(ppl, tmp, prev, rb_link, rb_parent);
-                prev = tmp;
-                rb_link = &tmp->pp_rb.rb_right;
-                rb_parent = &tmp->pp_rb;
-        }
-        return 0;
-}
-
-int
-ia32_copy_ia64_partial_page_list(struct task_struct *p,
-                                unsigned long clone_flags)
-{
-        int retval = 0;
-
-        if (clone_flags & CLONE_VM) {
-                atomic_inc(&current->thread.ppl->pp_count);
-                p->thread.ppl = current->thread.ppl;
-        } else {
-                p->thread.ppl = ia32_init_pp_list();
-                if (!p->thread.ppl)
-                        return -ENOMEM;
-                down_write(&current->mm->mmap_sem);
-                {
-                        retval = __ia32_copy_pp_list(p->thread.ppl);
-                }
-                up_write(&current->mm->mmap_sem);
-        }
-
-        return retval;
-}
-
-static unsigned long
-emulate_mmap (struct file *file, unsigned long start, unsigned long len, int prot, int flags,
-              loff_t off)
-{
-        unsigned long tmp, end, pend, pstart, ret, is_congruent, fudge = 0;
-        struct inode *inode;
-        loff_t poff;
-
-        end = start + len;
-        pstart = PAGE_START(start);
-        pend = PAGE_ALIGN(end);
-
-        if (flags & MAP_FIXED) {
-                ia32_set_pp((unsigned int)start, (unsigned int)end, flags);
-                if (start > pstart) {
-                        if (flags & MAP_SHARED)
-                                printk(KERN_INFO
-                                       "%s(%d): emulate_mmap() can't share head (addr=0x%lx)\n",
-                                       current->comm, task_pid_nr(current), start);
-                        ret = mmap_subpage(file, start, min(PAGE_ALIGN(start), end), prot, flags,
-                                           off);
-                        if (IS_ERR((void *) ret))
-                                return ret;
-                        pstart += PAGE_SIZE;
-                        if (pstart >= pend)
-                                goto out;       /* done */
-                }
-                if (end < pend) {
-                        if (flags & MAP_SHARED)
-                                printk(KERN_INFO
-                                       "%s(%d): emulate_mmap() can't share tail (end=0x%lx)\n",
-                                       current->comm, task_pid_nr(current), end);
-                        ret = mmap_subpage(file, max(start, PAGE_START(end)), end, prot, flags,
-                                           (off + len) - offset_in_page(end));
-                        if (IS_ERR((void *) ret))
-                                return ret;
-                        pend -= PAGE_SIZE;
-                        if (pstart >= pend)
-                                goto out;       /* done */
-                }
-        } else {
-                /*
-                 * If a start address was specified, use it if the entire rounded out area
-                 * is available.
-                 */
-                if (start && !pstart)
-                        fudge = 1;      /* handle case of mapping to range (0,PAGE_SIZE) */
-                tmp = arch_get_unmapped_area(file, pstart - fudge, pend - pstart, 0, flags);
-                if (tmp != pstart) {
-                        pstart = tmp;
-                        start = pstart + offset_in_page(off);   /* make start congruent with off */
-                        end = start + len;
-                        pend = PAGE_ALIGN(end);
-                }
-        }
-
-        poff = off + (pstart - start);  /* note: (pstart - start) may be negative */
-        is_congruent = (flags & MAP_ANONYMOUS) || (offset_in_page(poff) == 0);
-
-        if ((flags & MAP_SHARED) && !is_congruent)
-                printk(KERN_INFO "%s(%d): emulate_mmap() can't share contents of incongruent mmap "
-                       "(addr=0x%lx,off=0x%llx)\n", current->comm, task_pid_nr(current), start, off);
-
-        DBG("mmap_body: mapping [0x%lx-0x%lx) %s with poff 0x%llx\n", pstart, pend,
-            is_congruent ? "congruent" : "not congruent", poff);
-
-        down_write(&current->mm->mmap_sem);
-        {
-                if (!(flags & MAP_ANONYMOUS) && is_congruent)
-                        ret = do_mmap(file, pstart, pend - pstart, prot, flags | MAP_FIXED, poff);
-                else
-                        ret = do_mmap(NULL, pstart, pend - pstart,
-                                      prot | ((flags & MAP_ANONYMOUS) ? 0 : PROT_WRITE),
-                                      flags | MAP_FIXED | MAP_ANONYMOUS, 0);
-        }
-        up_write(&current->mm->mmap_sem);
-
-        if (IS_ERR((void *) ret))
-                return ret;
-
-        if (!is_congruent) {
-                /* read the file contents */
-                inode = file->f_path.dentry->d_inode;
-                if (!inode->i_fop || !file->f_op->read
-                    || ((*file->f_op->read)(file, (char __user *) pstart, pend - pstart, &poff)
-                        < 0))
-                {
-                        sys_munmap(pstart, pend - pstart);
-                        return -EINVAL;
-                }
-                if (!(prot & PROT_WRITE) && sys_mprotect(pstart, pend - pstart, prot) < 0)
-                        return -EINVAL;
-        }
-
-        if (!(flags & MAP_FIXED))
-                ia32_set_pp((unsigned int)start, (unsigned int)end, flags);
-out:
-        return start;
-}
-
-#endif /* PAGE_SHIFT > IA32_PAGE_SHIFT */
-
-static inline unsigned int
-get_prot32 (unsigned int prot)
-{
-        if (prot & PROT_WRITE)
-                /* on x86, PROT_WRITE implies PROT_READ which implies PROT_EEC */
-                prot |= PROT_READ | PROT_WRITE | PROT_EXEC;
-        else if (prot & (PROT_READ | PROT_EXEC))
-                /* on x86, there is no distinction between PROT_READ and PROT_EXEC */
-                prot |= (PROT_READ | PROT_EXEC);
-
-        return prot;
-}
-
-unsigned long
-ia32_do_mmap (struct file *file, unsigned long addr, unsigned long len, int prot, int flags,
-              loff_t offset)
-{
-        DBG("ia32_do_mmap(file=%p,addr=0x%lx,len=0x%lx,prot=%x,flags=%x,offset=0x%llx)\n",
-            file, addr, len, prot, flags, offset);
-
-        if (file && (!file->f_op || !file->f_op->mmap))
-                return -ENODEV;
-
-        len = IA32_PAGE_ALIGN(len);
-        if (len == 0)
-                return addr;
-
-        if (len > IA32_PAGE_OFFSET || addr > IA32_PAGE_OFFSET - len)
-        {
-                if (flags & MAP_FIXED)
-                        return -ENOMEM;
-                else
-                return -EINVAL;
-        }
-
-        if (OFFSET4K(offset))
-                return -EINVAL;
-
-        prot = get_prot32(prot);
-
-        if (flags & MAP_HUGETLB)
-                return -ENOMEM;
-
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-        mutex_lock(&ia32_mmap_mutex);
-        {
-                addr = emulate_mmap(file, addr, len, prot, flags, offset);
-        }
-        mutex_unlock(&ia32_mmap_mutex);
-#else
-        down_write(&current->mm->mmap_sem);
-        {
-                addr = do_mmap(file, addr, len, prot, flags, offset);
-        }
-        up_write(&current->mm->mmap_sem);
-#endif
-        DBG("ia32_do_mmap: returning 0x%lx\n", addr);
-        return addr;
-}
-
-/*
- * Linux/i386 didn't use to be able to handle more than 4 system call parameters, so these
- * system calls used a memory block for parameter passing..
- */
-
-struct mmap_arg_struct {
-        unsigned int addr;
-        unsigned int len;
-        unsigned int prot;
-        unsigned int flags;
-        unsigned int fd;
-        unsigned int offset;
-};
-
-asmlinkage long
-sys32_mmap (struct mmap_arg_struct __user *arg)
-{
-        struct mmap_arg_struct a;
-        struct file *file = NULL;
-        unsigned long addr;
-        int flags;
-
-        if (copy_from_user(&a, arg, sizeof(a)))
-                return -EFAULT;
-
-        if (OFFSET4K(a.offset))
-                return -EINVAL;
-
-        flags = a.flags;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(a.fd);
-                if (!file)
-                        return -EBADF;
-        }
-
-        addr = ia32_do_mmap(file, a.addr, a.len, a.prot, flags, a.offset);
-
-        if (file)
-                fput(file);
-        return addr;
-}
-
-asmlinkage long
-sys32_mmap2 (unsigned int addr, unsigned int len, unsigned int prot, unsigned int flags,
-             unsigned int fd, unsigned int pgoff)
-{
-        struct file *file = NULL;
-        unsigned long retval;
-
-        flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
-        if (!(flags & MAP_ANONYMOUS)) {
-                file = fget(fd);
-                if (!file)
-                        return -EBADF;
-        }
-
-        retval = ia32_do_mmap(file, addr, len, prot, flags,
-                              (unsigned long) pgoff << IA32_PAGE_SHIFT);
-
-        if (file)
-                fput(file);
-        return retval;
-}
-
-asmlinkage long
-sys32_munmap (unsigned int start, unsigned int len)
-{
-        unsigned int end = start + len;
-        long ret;
-
-#if PAGE_SHIFT <= IA32_PAGE_SHIFT
-        ret = sys_munmap(start, end - start);
-#else
-        if (OFFSET4K(start))
-                return -EINVAL;
-
-        end = IA32_PAGE_ALIGN(end);
-        if (start >= end)
-                return -EINVAL;
-
-        ret = ia32_unset_pp(&start, &end);
-        if (ret < 0)
-                return ret;
-
-        if (start >= end)
-                return 0;
-
-        mutex_lock(&ia32_mmap_mutex);
-        ret = sys_munmap(start, end - start);
-        mutex_unlock(&ia32_mmap_mutex);
-#endif
-        return ret;
-}
-
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-
-/*
- * When mprotect()ing a partial page, we set the permission to the union of the old
- * settings and the new settings.  In other words, it's only possible to make access to a
- * partial page less restrictive.
- */
-static long
-mprotect_subpage (unsigned long address, int new_prot)
-{
-        int old_prot;
-        struct vm_area_struct *vma;
-
-        if (new_prot == PROT_NONE)
-                return 0;               /* optimize case where nothing changes... */
-        vma = find_vma(current->mm, address);
-        old_prot = get_page_prot(vma, address);
-        return sys_mprotect(address, PAGE_SIZE, new_prot | old_prot);
-}
-
-#endif /* PAGE_SHIFT > IA32_PAGE_SHIFT */
-
-asmlinkage long
-sys32_mprotect (unsigned int start, unsigned int len, int prot)
-{
-        unsigned int end = start + len;
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-        long retval = 0;
-#endif
-
-        prot = get_prot32(prot);
-
-#if PAGE_SHIFT <= IA32_PAGE_SHIFT
-        return sys_mprotect(start, end - start, prot);
-#else
-        if (OFFSET4K(start))
-                return -EINVAL;
-
-        end = IA32_PAGE_ALIGN(end);
-        if (end < start)
-                return -EINVAL;
-
-        retval = ia32_compare_pp(&start, &end);
-
-        if (retval < 0)
-                return retval;
-
-        mutex_lock(&ia32_mmap_mutex);
-        {
-                if (offset_in_page(start)) {
-                        /* start address is 4KB aligned but not page aligned. */
-                        retval = mprotect_subpage(PAGE_START(start), prot);
-                        if (retval < 0)
-                                goto out;
-
-                        start = PAGE_ALIGN(start);
-                        if (start >= end)
-                                goto out;       /* retval is already zero... */
-                }
-
-                if (offset_in_page(end)) {
-                        /* end address is 4KB aligned but not page aligned. */
-                        retval = mprotect_subpage(PAGE_START(end), prot);
-                        if (retval < 0)
-                                goto out;
-
-                        end = PAGE_START(end);
-                }
-                retval = sys_mprotect(start, end - start, prot);
-        }
-  out:
-        mutex_unlock(&ia32_mmap_mutex);
-        return retval;
-#endif
-}
-
-asmlinkage long
-sys32_mremap (unsigned int addr, unsigned int old_len, unsigned int new_len,
-                unsigned int flags, unsigned int new_addr)
-{
-        long ret;
-
-#if PAGE_SHIFT <= IA32_PAGE_SHIFT
-        ret = sys_mremap(addr, old_len, new_len, flags, new_addr);
-#else
-        unsigned int old_end, new_end;
-
-        if (OFFSET4K(addr))
-                return -EINVAL;
-
-        old_len = IA32_PAGE_ALIGN(old_len);
-        new_len = IA32_PAGE_ALIGN(new_len);
-        old_end = addr + old_len;
-        new_end = addr + new_len;
-
-        if (!new_len)
-                return -EINVAL;
-
-        if ((flags & MREMAP_FIXED) && (OFFSET4K(new_addr)))
-                return -EINVAL;
-
-        if (old_len >= new_len) {
-                ret = sys32_munmap(addr + new_len, old_len - new_len);
-                if (ret && old_len != new_len)
-                        return ret;
-                ret = addr;
-                if (!(flags & MREMAP_FIXED) || (new_addr == addr))
-                        return ret;
-                old_len = new_len;
-        }
-
-        addr = PAGE_START(addr);
-        old_len = PAGE_ALIGN(old_end) - addr;
-        new_len = PAGE_ALIGN(new_end) - addr;
-
-        mutex_lock(&ia32_mmap_mutex);
-        ret = sys_mremap(addr, old_len, new_len, flags, new_addr);
-        mutex_unlock(&ia32_mmap_mutex);
-
-        if ((ret >= 0) && (old_len < new_len)) {
-                /* mremap expanded successfully */
-                ia32_set_pp(old_end, new_end, flags);
-        }
-#endif
-        return ret;
-}
-
-asmlinkage unsigned long
-sys32_alarm (unsigned int seconds)
-{
-        return alarm_setitimer(seconds);
-}
-
-struct sel_arg_struct {
-        unsigned int n;
-        unsigned int inp;
-        unsigned int outp;
-        unsigned int exp;
-        unsigned int tvp;
-};
-
-asmlinkage long
-sys32_old_select (struct sel_arg_struct __user *arg)
-{
-        struct sel_arg_struct a;
-
-        if (copy_from_user(&a, arg, sizeof(a)))
-                return -EFAULT;
-        return compat_sys_select(a.n, compat_ptr(a.inp), compat_ptr(a.outp),
-                                 compat_ptr(a.exp), compat_ptr(a.tvp));
-}
-
-#define SEMOP            1
-#define SEMGET           2
-#define SEMCTL           3
-#define SEMTIMEDOP       4
-#define MSGSND          11
-#define MSGRCV          12
-#define MSGGET          13
-#define MSGCTL          14
-#define SHMAT           21
-#define SHMDT           22
-#define SHMGET          23
-#define SHMCTL          24
-
-asmlinkage long
-sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
-{
-        int version;
-
-        version = call >> 16; /* hack for backward compatibility */
-        call &= 0xffff;
-
-        switch (call) {
-              case SEMTIMEDOP:
-                if (fifth)
-                        return compat_sys_semtimedop(first, compat_ptr(ptr),
-                                second, compat_ptr(fifth));
-                /* else fall through for normal semop() */
-              case SEMOP:
-                /* struct sembuf is the same on 32 and 64bit :)) */
-                return sys_semtimedop(first, compat_ptr(ptr), second,
-                                      NULL);
-              case SEMGET:
-                return sys_semget(first, second, third);
-              case SEMCTL:
-                return compat_sys_semctl(first, second, third, compat_ptr(ptr));
-
-              case MSGSND:
-                return compat_sys_msgsnd(first, second, third, compat_ptr(ptr));
-              case MSGRCV:
-                return compat_sys_msgrcv(first, second, fifth, third, version, compat_ptr(ptr));
-              case MSGGET:
-                return sys_msgget((key_t) first, second);
-              case MSGCTL:
-                return compat_sys_msgctl(first, second, compat_ptr(ptr));
-
-              case SHMAT:
-                return compat_sys_shmat(first, second, third, version, compat_ptr(ptr));
-                break;
-              case SHMDT:
-                return sys_shmdt(compat_ptr(ptr));
-              case SHMGET:
-                return sys_shmget(first, (unsigned)second, third);
-              case SHMCTL:
-                return compat_sys_shmctl(first, second, compat_ptr(ptr));
-
-              default:
-                return -ENOSYS;
-        }
-        return -EINVAL;
-}
-
-asmlinkage long
-compat_sys_wait4 (compat_pid_t pid, compat_uint_t * stat_addr, int options,
-                 struct compat_rusage *ru);
-
-asmlinkage long
-sys32_waitpid (int pid, unsigned int *stat_addr, int options)
-{
-        return compat_sys_wait4(pid, stat_addr, options, NULL);
-}
-
-/*
- *  The order in which registers are stored in the ptrace regs structure
- */
-#define PT_EBX  0
-#define PT_ECX  1
-#define PT_EDX  2
-#define PT_ESI  3
-#define PT_EDI  4
-#define PT_EBP  5
-#define PT_EAX  6
-#define PT_DS   7
-#define PT_ES   8
-#define PT_FS   9
-#define PT_GS   10
-#define PT_ORIG_EAX 11
-#define PT_EIP  12
-#define PT_CS   13
-#define PT_EFL  14
-#define PT_UESP 15
-#define PT_SS   16
-
-static unsigned int
-getreg (struct task_struct *child, int regno)
-{
-        struct pt_regs *child_regs;
-
-        child_regs = task_pt_regs(child);
-        switch (regno / sizeof(int)) {
-              case PT_EBX: return child_regs->r11;
-              case PT_ECX: return child_regs->r9;
-              case PT_EDX: return child_regs->r10;
-              case PT_ESI: return child_regs->r14;
-              case PT_EDI: return child_regs->r15;
-              case PT_EBP: return child_regs->r13;
-              case PT_EAX: return child_regs->r8;
-              case PT_ORIG_EAX: return child_regs->r1; /* see dispatch_to_ia32_handler() */
-              case PT_EIP: return child_regs->cr_iip;
-              case PT_UESP: return child_regs->r12;
-              case PT_EFL: return child->thread.eflag;
-              case PT_DS: case PT_ES: case PT_FS: case PT_GS: case PT_SS:
-                return __USER_DS;
-              case PT_CS: return __USER_CS;
-              default:
-                printk(KERN_ERR "ia32.getreg(): unknown register %d\n", regno);
-                break;
-        }
-        return 0;
-}
-
-static void
-putreg (struct task_struct *child, int regno, unsigned int value)
-{
-        struct pt_regs *child_regs;
-
-        child_regs = task_pt_regs(child);
-        switch (regno / sizeof(int)) {
-              case PT_EBX: child_regs->r11 = value; break;
-              case PT_ECX: child_regs->r9 = value; break;
-              case PT_EDX: child_regs->r10 = value; break;
-              case PT_ESI: child_regs->r14 = value; break;
-              case PT_EDI: child_regs->r15 = value; break;
-              case PT_EBP: child_regs->r13 = value; break;
-              case PT_EAX: child_regs->r8 = value; break;
-              case PT_ORIG_EAX: child_regs->r1 = value; break;
-              case PT_EIP: child_regs->cr_iip = value; break;
-              case PT_UESP: child_regs->r12 = value; break;
-              case PT_EFL: child->thread.eflag = value; break;
-              case PT_DS: case PT_ES: case PT_FS: case PT_GS: case PT_SS:
-                if (value != __USER_DS)
-                        printk(KERN_ERR
-                               "ia32.putreg: attempt to set invalid segment register %d = %x\n",
-                               regno, value);
-                break;
-              case PT_CS:
-                if (value != __USER_CS)
-                        printk(KERN_ERR
-                               "ia32.putreg: attempt to set invalid segment register %d = %x\n",
-                               regno, value);
-                break;
-              default:
-                printk(KERN_ERR "ia32.putreg: unknown register %d\n", regno);
-                break;
-        }
-}
-
-static void
-put_fpreg (int regno, struct _fpreg_ia32 __user *reg, struct pt_regs *ptp,
-           struct switch_stack *swp, int tos)
-{
-        struct _fpreg_ia32 *f;
-        char buf[32];
-
-        f = (struct _fpreg_ia32 *)(((unsigned long)buf + 15) & ~15);
-        if ((regno += tos) >= 8)
-                regno -= 8;
-        switch (regno) {
-              case 0:
-                ia64f2ia32f(f, &ptp->f8);
-                break;
-              case 1:
-                ia64f2ia32f(f, &ptp->f9);
-                break;
-              case 2:
-                ia64f2ia32f(f, &ptp->f10);
-                break;
-              case 3:
-                ia64f2ia32f(f, &ptp->f11);
-                break;
-              case 4:
-              case 5:
-              case 6:
-              case 7:
-                ia64f2ia32f(f, &swp->f12 + (regno - 4));
-                break;
-        }
-        copy_to_user(reg, f, sizeof(*reg));
-}
-
-static void
-get_fpreg (int regno, struct _fpreg_ia32 __user *reg, struct pt_regs *ptp,
-           struct switch_stack *swp, int tos)
-{
-
-        if ((regno += tos) >= 8)
-                regno -= 8;
-        switch (regno) {
-              case 0:
-                copy_from_user(&ptp->f8, reg, sizeof(*reg));
-                break;
-              case 1:
-                copy_from_user(&ptp->f9, reg, sizeof(*reg));
-                break;
-              case 2:
-                copy_from_user(&ptp->f10, reg, sizeof(*reg));
-                break;
-              case 3:
-                copy_from_user(&ptp->f11, reg, sizeof(*reg));
-                break;
-              case 4:
-              case 5:
-              case 6:
-              case 7:
-                copy_from_user(&swp->f12 + (regno - 4), reg, sizeof(*reg));
-                break;
-        }
-        return;
-}
-
-int
-save_ia32_fpstate (struct task_struct *tsk, struct ia32_user_i387_struct __user *save)
-{
-        struct switch_stack *swp;
-        struct pt_regs *ptp;
-        int i, tos;
-
-        if (!access_ok(VERIFY_WRITE, save, sizeof(*save)))
-                return -EFAULT;
-
-        __put_user(tsk->thread.fcr & 0xffff, &save->cwd);
-        __put_user(tsk->thread.fsr & 0xffff, &save->swd);
-        __put_user((tsk->thread.fsr>>16) & 0xffff, &save->twd);
-        __put_user(tsk->thread.fir, &save->fip);
-        __put_user((tsk->thread.fir>>32) & 0xffff, &save->fcs);
-        __put_user(tsk->thread.fdr, &save->foo);
-        __put_user((tsk->thread.fdr>>32) & 0xffff, &save->fos);
-
-        /*
-         *  Stack frames start with 16-bytes of temp space
-         */
-        swp = (struct switch_stack *)(tsk->thread.ksp + 16);
-        ptp = task_pt_regs(tsk);
-        tos = (tsk->thread.fsr >> 11) & 7;
-        for (i = 0; i < 8; i++)
-                put_fpreg(i, &save->st_space[i], ptp, swp, tos);
-        return 0;
-}
-
-static int
-restore_ia32_fpstate (struct task_struct *tsk, struct ia32_user_i387_struct __user *save)
-{
-        struct switch_stack *swp;
-        struct pt_regs *ptp;
-        int i, tos;
-        unsigned int fsrlo, fsrhi, num32;
-
-        if (!access_ok(VERIFY_READ, save, sizeof(*save)))
-                return(-EFAULT);
-
-        __get_user(num32, (unsigned int __user *)&save->cwd);
-        tsk->thread.fcr = (tsk->thread.fcr & (~0x1f3f)) | (num32 & 0x1f3f);
-        __get_user(fsrlo, (unsigned int __user *)&save->swd);
-        __get_user(fsrhi, (unsigned int __user *)&save->twd);
-        num32 = (fsrhi << 16) | fsrlo;
-        tsk->thread.fsr = (tsk->thread.fsr & (~0xffffffff)) | num32;
-        __get_user(num32, (unsigned int __user *)&save->fip);
-        tsk->thread.fir = (tsk->thread.fir & (~0xffffffff)) | num32;
-        __get_user(num32, (unsigned int __user *)&save->foo);
-        tsk->thread.fdr = (tsk->thread.fdr & (~0xffffffff)) | num32;
-
-        /*
-         *  Stack frames start with 16-bytes of temp space
-         */
-        swp = (struct switch_stack *)(tsk->thread.ksp + 16);
-        ptp = task_pt_regs(tsk);
-        tos = (tsk->thread.fsr >> 11) & 7;
-        for (i = 0; i < 8; i++)
-                get_fpreg(i, &save->st_space[i], ptp, swp, tos);
-        return 0;
-}
-
-int
-save_ia32_fpxstate (struct task_struct *tsk, struct ia32_user_fxsr_struct __user *save)
-{
-        struct switch_stack *swp;
-        struct pt_regs *ptp;
-        int i, tos;
-        unsigned long mxcsr=0;
-        unsigned long num128[2];
-
-        if (!access_ok(VERIFY_WRITE, save, sizeof(*save)))
-                return -EFAULT;
-
-        __put_user(tsk->thread.fcr & 0xffff, &save->cwd);
-        __put_user(tsk->thread.fsr & 0xffff, &save->swd);
-        __put_user((tsk->thread.fsr>>16) & 0xffff, &save->twd);
-        __put_user(tsk->thread.fir, &save->fip);
-        __put_user((tsk->thread.fir>>32) & 0xffff, &save->fcs);
-        __put_user(tsk->thread.fdr, &save->foo);
-        __put_user((tsk->thread.fdr>>32) & 0xffff, &save->fos);
-
-        /*
-         *  Stack frames start with 16-bytes of temp space
-         */
-        swp = (struct switch_stack *)(tsk->thread.ksp + 16);
-        ptp = task_pt_regs(tsk);
-        tos = (tsk->thread.fsr >> 11) & 7;
-        for (i = 0; i < 8; i++)
-                put_fpreg(i, (struct _fpreg_ia32 __user *)&save->st_space[4*i], ptp, swp, tos);
-
-        mxcsr = ((tsk->thread.fcr>>32) & 0xff80) | ((tsk->thread.fsr>>32) & 0x3f);
-        __put_user(mxcsr & 0xffff, &save->mxcsr);
-        for (i = 0; i < 8; i++) {
-                memcpy(&(num128[0]), &(swp->f16) + i*2, sizeof(unsigned long));
-                memcpy(&(num128[1]), &(swp->f17) + i*2, sizeof(unsigned long));
-                copy_to_user(&save->xmm_space[0] + 4*i, num128, sizeof(struct _xmmreg_ia32));
-        }
-        return 0;
-}
-
-static int
-restore_ia32_fpxstate (struct task_struct *tsk, struct ia32_user_fxsr_struct __user *save)
-{
-        struct switch_stack *swp;
-        struct pt_regs *ptp;
-        int i, tos;
-        unsigned int fsrlo, fsrhi, num32;
-        int mxcsr;
-        unsigned long num64;
-        unsigned long num128[2];
-
-        if (!access_ok(VERIFY_READ, save, sizeof(*save)))
-                return(-EFAULT);
-
-        __get_user(num32, (unsigned int __user *)&save->cwd);
-        tsk->thread.fcr = (tsk->thread.fcr & (~0x1f3f)) | (num32 & 0x1f3f);
-        __get_user(fsrlo, (unsigned int __user *)&save->swd);
-        __get_user(fsrhi, (unsigned int __user *)&save->twd);
-        num32 = (fsrhi << 16) | fsrlo;
-        tsk->thread.fsr = (tsk->thread.fsr & (~0xffffffff)) | num32;
-        __get_user(num32, (unsigned int __user *)&save->fip);
-        tsk->thread.fir = (tsk->thread.fir & (~0xffffffff)) | num32;
-        __get_user(num32, (unsigned int __user *)&save->foo);
-        tsk->thread.fdr = (tsk->thread.fdr & (~0xffffffff)) | num32;
-
-        /*
-         *  Stack frames start with 16-bytes of temp space
-         */
-        swp = (struct switch_stack *)(tsk->thread.ksp + 16);
-        ptp = task_pt_regs(tsk);
-        tos = (tsk->thread.fsr >> 11) & 7;
-        for (i = 0; i < 8; i++)
-        get_fpreg(i, (struct _fpreg_ia32 __user *)&save->st_space[4*i], ptp, swp, tos);
-
-        __get_user(mxcsr, (unsigned int __user *)&save->mxcsr);
-        num64 = mxcsr & 0xff10;
-        tsk->thread.fcr = (tsk->thread.fcr & (~0xff1000000000UL)) | (num64<<32);
-        num64 = mxcsr & 0x3f;
-        tsk->thread.fsr = (tsk->thread.fsr & (~0x3f00000000UL)) | (num64<<32);
-
-        for (i = 0; i < 8; i++) {
-                copy_from_user(num128, &save->xmm_space[0] + 4*i, sizeof(struct _xmmreg_ia32));
-                memcpy(&(swp->f16) + i*2, &(num128[0]), sizeof(unsigned long));
-                memcpy(&(swp->f17) + i*2, &(num128[1]), sizeof(unsigned long));
-        }
-        return 0;
-}
-
-long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
-        compat_ulong_t caddr, compat_ulong_t cdata)
-{
-        unsigned long addr = caddr;
-        unsigned long data = cdata;
-        unsigned int tmp;
-        long i, ret;
-
-        switch (request) {
-              case PTRACE_PEEKUSR:      /* read word at addr in USER area */
-                ret = -EIO;
-                if ((addr & 3) || addr > 17*sizeof(int))
-                        break;
-
-                tmp = getreg(child, addr);
-                if (!put_user(tmp, (unsigned int __user *) compat_ptr(data)))
-                        ret = 0;
-                break;
-
-              case PTRACE_POKEUSR:      /* write word at addr in USER area */
-                ret = -EIO;
-                if ((addr & 3) || addr > 17*sizeof(int))
-                        break;
-
-                putreg(child, addr, data);
-                ret = 0;
-                break;
-
-              case IA32_PTRACE_GETREGS:
-                if (!access_ok(VERIFY_WRITE, compat_ptr(data), 17*sizeof(int))) {
-                        ret = -EIO;
-                        break;
-                }
-                for (i = 0; i < (int) (17*sizeof(int)); i += sizeof(int) ) {
-                        put_user(getreg(child, i), (unsigned int __user *) compat_ptr(data));
-                        data += sizeof(int);
-                }
-                ret = 0;
-                break;
-
-              case IA32_PTRACE_SETREGS:
-                if (!access_ok(VERIFY_READ, compat_ptr(data), 17*sizeof(int))) {
-                        ret = -EIO;
-                        break;
-                }
-                for (i = 0; i < (int) (17*sizeof(int)); i += sizeof(int) ) {
-                        get_user(tmp, (unsigned int __user *) compat_ptr(data));
-                        putreg(child, i, tmp);
-                        data += sizeof(int);
-                }
-                ret = 0;
-                break;
-
-              case IA32_PTRACE_GETFPREGS:
-                ret = save_ia32_fpstate(child, (struct ia32_user_i387_struct __user *)
-                                        compat_ptr(data));
-                break;
-
-              case IA32_PTRACE_GETFPXREGS:
-                ret = save_ia32_fpxstate(child, (struct ia32_user_fxsr_struct __user *)
-                                         compat_ptr(data));
-                break;
-
-              case IA32_PTRACE_SETFPREGS:
-                ret = restore_ia32_fpstate(child, (struct ia32_user_i387_struct __user *)
-                                           compat_ptr(data));
-                break;
-
-              case IA32_PTRACE_SETFPXREGS:
-                ret = restore_ia32_fpxstate(child, (struct ia32_user_fxsr_struct __user *)
-                                            compat_ptr(data));
-                break;
-
-              default:
-                return compat_ptrace_request(child, request, caddr, cdata);
-        }
-        return ret;
-}
-
-typedef struct {
-        unsigned int    ss_sp;
-        unsigned int    ss_flags;
-        unsigned int    ss_size;
-} ia32_stack_t;
-
-asmlinkage long
-sys32_sigaltstack (ia32_stack_t __user *uss32, ia32_stack_t __user *uoss32,
-                   long arg2, long arg3, long arg4, long arg5, long arg6,
-                   long arg7, struct pt_regs pt)
-{
-        stack_t uss, uoss;
-        ia32_stack_t buf32;
-        int ret;
-        mm_segment_t old_fs = get_fs();
-
-        if (uss32) {
-                if (copy_from_user(&buf32, uss32, sizeof(ia32_stack_t)))
-                        return -EFAULT;
-                uss.ss_sp = (void __user *) (long) buf32.ss_sp;
-                uss.ss_flags = buf32.ss_flags;
-                /* MINSIGSTKSZ is different for ia32 vs ia64. We lie here to pass the
-                   check and set it to the user requested value later */
-                if ((buf32.ss_flags != SS_DISABLE) && (buf32.ss_size < MINSIGSTKSZ_IA32)) {
-                        ret = -ENOMEM;
-                        goto out;
-                }
-                uss.ss_size = MINSIGSTKSZ;
-        }
-        set_fs(KERNEL_DS);
-        ret = do_sigaltstack(uss32 ? (stack_t __user *) &uss : NULL,
-                             (stack_t __user *) &uoss, pt.r12);
-        current->sas_ss_size = buf32.ss_size;
-        set_fs(old_fs);
-out:
-        if (ret < 0)
-                return(ret);
-        if (uoss32) {
-                buf32.ss_sp = (long __user) uoss.ss_sp;
-                buf32.ss_flags = uoss.ss_flags;
-                buf32.ss_size = uoss.ss_size;
-                if (copy_to_user(uoss32, &buf32, sizeof(ia32_stack_t)))
-                        return -EFAULT;
-        }
-        return ret;
-}
-
-asmlinkage int
-sys32_msync (unsigned int start, unsigned int len, int flags)
-{
-        unsigned int addr;
-
-        if (OFFSET4K(start))
-                return -EINVAL;
-        addr = PAGE_START(start);
-        return sys_msync(addr, len + (start - addr), flags);
-}
-
-asmlinkage long
-sys32_newuname (struct new_utsname __user *name)
-{
-        int ret = sys_newuname(name);
-
-        if (!ret)
-                if (copy_to_user(name->machine, "i686\0\0\0", 8))
-                        ret = -EFAULT;
-        return ret;
-}
-
-asmlinkage long
-sys32_getresuid16 (u16 __user *ruid, u16 __user *euid, u16 __user *suid)
-{
-        uid_t a, b, c;
-        int ret;
-        mm_segment_t old_fs = get_fs();
-
-        set_fs(KERNEL_DS);
-        ret = sys_getresuid((uid_t __user *) &a, (uid_t __user *) &b, (uid_t __user *) &c);
-        set_fs(old_fs);
-
-        if (put_user(a, ruid) || put_user(b, euid) || put_user(c, suid))
-                return -EFAULT;
-        return ret;
-}
-
-asmlinkage long
-sys32_getresgid16 (u16 __user *rgid, u16 __user *egid, u16 __user *sgid)
-{
-        gid_t a, b, c;
-        int ret;
-        mm_segment_t old_fs = get_fs();
-
-        set_fs(KERNEL_DS);
-        ret = sys_getresgid((gid_t __user *) &a, (gid_t __user *) &b, (gid_t __user *) &c);
-        set_fs(old_fs);
-
-        if (ret)
-                return ret;
-
-        return put_user(a, rgid) | put_user(b, egid) | put_user(c, sgid);
-}
-
-asmlinkage long
-sys32_lseek (unsigned int fd, int offset, unsigned int whence)
-{
-        /* Sign-extension of "offset" is important here... */
-        return sys_lseek(fd, offset, whence);
-}
-
-static int
-groups16_to_user(short __user *grouplist, struct group_info *group_info)
-{
-        int i;
-        short group;
-
-        for (i = 0; i < group_info->ngroups; i++) {
-                group = (short)GROUP_AT(group_info, i);
-                if (put_user(group, grouplist+i))
-                        return -EFAULT;
-        }
-
-        return 0;
-}
-
-static int
-groups16_from_user(struct group_info *group_info, short __user *grouplist)
-{
-        int i;
-        short group;
-
-        for (i = 0; i < group_info->ngroups; i++) {
-                if (get_user(group, grouplist+i))
-                        return  -EFAULT;
-                GROUP_AT(group_info, i) = (gid_t)group;
-        }
-
-        return 0;
-}
-
-asmlinkage long
-sys32_getgroups16 (int gidsetsize, short __user *grouplist)
-{
-        const struct cred *cred = current_cred();
-        int i;
-
-        if (gidsetsize < 0)
-                return -EINVAL;
-
-        i = cred->group_info->ngroups;
-        if (gidsetsize) {
-                if (i > gidsetsize) {
-                        i = -EINVAL;
-                        goto out;
-                }
-                if (groups16_to_user(grouplist, cred->group_info)) {
-                        i = -EFAULT;
-                        goto out;
-                }
-        }
-out:
-        return i;
-}
-
-asmlinkage long
-sys32_setgroups16 (int gidsetsize, short __user *grouplist)
-{
-        struct group_info *group_info;
-        int retval;
-
-        if (!capable(CAP_SETGID))
-                return -EPERM;
-        if ((unsigned)gidsetsize > NGROUPS_MAX)
-                return -EINVAL;
-
-        group_info = groups_alloc(gidsetsize);
-        if (!group_info)
-                return -ENOMEM;
-        retval = groups16_from_user(group_info, grouplist);
-        if (retval) {
-                put_group_info(group_info);
-                return retval;
-        }
-
-        retval = set_current_groups(group_info);
-        put_group_info(group_info);
-
-        return retval;
-}
-
-asmlinkage long
-sys32_truncate64 (unsigned int path, unsigned int len_lo, unsigned int len_hi)
-{
-        return sys_truncate(compat_ptr(path), ((unsigned long) len_hi << 32) | len_lo);
-}
-
-asmlinkage long
-sys32_ftruncate64 (int fd, unsigned int len_lo, unsigned int len_hi)
-{
-        return sys_ftruncate(fd, ((unsigned long) len_hi << 32) | len_lo);
-}
-
-static int
-putstat64 (struct stat64 __user *ubuf, struct kstat *kbuf)
-{
-        int err;
-        u64 hdev;
-
-        if (clear_user(ubuf, sizeof(*ubuf)))
-                return -EFAULT;
-
-        hdev = huge_encode_dev(kbuf->dev);
-        err  = __put_user(hdev, (u32 __user*)&ubuf->st_dev);
-        err |= __put_user(hdev >> 32, ((u32 __user*)&ubuf->st_dev) + 1);
-        err |= __put_user(kbuf->ino, &ubuf->__st_ino);
-        err |= __put_user(kbuf->ino, &ubuf->st_ino_lo);
-        err |= __put_user(kbuf->ino >> 32, &ubuf->st_ino_hi);
-        err |= __put_user(kbuf->mode, &ubuf->st_mode);
-        err |= __put_user(kbuf->nlink, &ubuf->st_nlink);
-        err |= __put_user(kbuf->uid, &ubuf->st_uid);
-        err |= __put_user(kbuf->gid, &ubuf->st_gid);
-        hdev = huge_encode_dev(kbuf->rdev);
-        err  = __put_user(hdev, (u32 __user*)&ubuf->st_rdev);
-        err |= __put_user(hdev >> 32, ((u32 __user*)&ubuf->st_rdev) + 1);
-        err |= __put_user(kbuf->size, &ubuf->st_size_lo);
-        err |= __put_user((kbuf->size >> 32), &ubuf->st_size_hi);
-        err |= __put_user(kbuf->atime.tv_sec, &ubuf->st_atime);
-        err |= __put_user(kbuf->atime.tv_nsec, &ubuf->st_atime_nsec);
-        err |= __put_user(kbuf->mtime.tv_sec, &ubuf->st_mtime);
-        err |= __put_user(kbuf->mtime.tv_nsec, &ubuf->st_mtime_nsec);
-        err |= __put_user(kbuf->ctime.tv_sec, &ubuf->st_ctime);
-        err |= __put_user(kbuf->ctime.tv_nsec, &ubuf->st_ctime_nsec);
-        err |= __put_user(kbuf->blksize, &ubuf->st_blksize);
-        err |= __put_user(kbuf->blocks, &ubuf->st_blocks);
-        return err;
-}
-
-asmlinkage long
-sys32_stat64 (char __user *filename, struct stat64 __user *statbuf)
-{
-        struct kstat s;
-        long ret = vfs_stat(filename, &s);
-        if (!ret)
-                ret = putstat64(statbuf, &s);
-        return ret;
-}
-
-asmlinkage long
-sys32_lstat64 (char __user *filename, struct stat64 __user *statbuf)
-{
-        struct kstat s;
-        long ret = vfs_lstat(filename, &s);
-        if (!ret)
-                ret = putstat64(statbuf, &s);
-        return ret;
-}
-
-asmlinkage long
-sys32_fstat64 (unsigned int fd, struct stat64 __user *statbuf)
-{
-        struct kstat s;
-        long ret = vfs_fstat(fd, &s);
-        if (!ret)
-                ret = putstat64(statbuf, &s);
-        return ret;
-}
-
-asmlinkage long
-sys32_sched_rr_get_interval (pid_t pid, struct compat_timespec __user *interval)
-{
-        mm_segment_t old_fs = get_fs();
-        struct timespec t;
-        long ret;
-
-        set_fs(KERNEL_DS);
-        ret = sys_sched_rr_get_interval(pid, (struct timespec __user *) &t);
-        set_fs(old_fs);
-        if (put_compat_timespec(&t, interval))
-                return -EFAULT;
-        return ret;
-}
-
-asmlinkage long
-sys32_pread (unsigned int fd, void __user *buf, unsigned int count, u32 pos_lo, u32 pos_hi)
-{
-        return sys_pread64(fd, buf, count, ((unsigned long) pos_hi << 32) | pos_lo);
-}
-
-asmlinkage long
-sys32_pwrite (unsigned int fd, void __user *buf, unsigned int count, u32 pos_lo, u32 pos_hi)
-{
-        return sys_pwrite64(fd, buf, count, ((unsigned long) pos_hi << 32) | pos_lo);
-}
-
-asmlinkage long
-sys32_sendfile (int out_fd, int in_fd, int __user *offset, unsigned int count)
-{
-        mm_segment_t old_fs = get_fs();
-        long ret;
-        off_t of;
-
-        if (offset && get_user(of, offset))
-                return -EFAULT;
-
-        set_fs(KERNEL_DS);
-        ret = sys_sendfile(out_fd, in_fd, offset ? (off_t __user *) &of : NULL, count);
-        set_fs(old_fs);
-
-        if (offset && put_user(of, offset))
-                return -EFAULT;
-
-        return ret;
-}
-
-asmlinkage long
-sys32_personality (unsigned int personality)
-{
-        long ret;
-
-        if (current->personality == PER_LINUX32 && personality == PER_LINUX)
-                personality = PER_LINUX32;
-        ret = sys_personality(personality);
-        if (ret == PER_LINUX32)
-                ret = PER_LINUX;
-        return ret;
-}
-
-asmlinkage unsigned long
-sys32_brk (unsigned int brk)
-{
-        unsigned long ret, obrk;
-        struct mm_struct *mm = current->mm;
-
-        obrk = mm->brk;
-        ret = sys_brk(brk);
-        if (ret < obrk)
-                clear_user(compat_ptr(ret), PAGE_ALIGN(ret) - ret);
-        return ret;
-}
-
-/* Structure for ia32 emulation on ia64 */
-struct epoll_event32
-{
-        u32 events;
-        u32 data[2];
-};
-
-asmlinkage long
-sys32_epoll_ctl(int epfd, int op, int fd, struct epoll_event32 __user *event)
-{
-        mm_segment_t old_fs = get_fs();
-        struct epoll_event event64;
-        int error;
-        u32 data_halfword;
-
-        if (!access_ok(VERIFY_READ, event, sizeof(struct epoll_event32)))
-                return -EFAULT;
-
-        __get_user(event64.events, &event->events);
-        __get_user(data_halfword, &event->data[0]);
-        event64.data = data_halfword;
-        __get_user(data_halfword, &event->data[1]);
-        event64.data |= (u64)data_halfword << 32;
-
-        set_fs(KERNEL_DS);
-        error = sys_epoll_ctl(epfd, op, fd, (struct epoll_event __user *) &event64);
-        set_fs(old_fs);
-
-        return error;
-}
-
-asmlinkage long
-sys32_epoll_wait(int epfd, struct epoll_event32 __user * events, int maxevents,
-                 int timeout)
-{
-        struct epoll_event *events64 = NULL;
-        mm_segment_t old_fs = get_fs();
-        int numevents, size;
-        int evt_idx;
-        int do_free_pages = 0;
-
-        if (maxevents <= 0) {
-                return -EINVAL;
-        }
-
-        /* Verify that the area passed by the user is writeable */
-        if (!access_ok(VERIFY_WRITE, events, maxevents * sizeof(struct epoll_event32)))
-                return -EFAULT;
-
-        /*
-         * Allocate space for the intermediate copy.  If the space needed
-         * is large enough to cause kmalloc to fail, then try again with
-         * __get_free_pages.
-         */
-        size = maxevents * sizeof(struct epoll_event);
-        events64 = kmalloc(size, GFP_KERNEL);
-        if (events64 == NULL) {
-                events64 = (struct epoll_event *)
-                                __get_free_pages(GFP_KERNEL, get_order(size));
-                if (events64 == NULL)
-                        return -ENOMEM;
-                do_free_pages = 1;
-        }
-
-        /* Do the system call */
-        set_fs(KERNEL_DS); /* copy_to/from_user should work on kernel mem*/
-        numevents = sys_epoll_wait(epfd, (struct epoll_event __user *) events64,
-                                   maxevents, timeout);
-        set_fs(old_fs);
-
-        /* Don't modify userspace memory if we're returning an error */
-        if (numevents > 0) {
-                /* Translate the 64-bit structures back into the 32-bit
-                   structures */
-                for (evt_idx = 0; evt_idx < numevents; evt_idx++) {
-                        __put_user(events64[evt_idx].events,
-                                   &events[evt_idx].events);
-                        __put_user((u32)events64[evt_idx].data,
-                                   &events[evt_idx].data[0]);
-                        __put_user((u32)(events64[evt_idx].data >> 32),
-                                   &events[evt_idx].data[1]);
-                }
-        }
-
-        if (do_free_pages)
-                free_pages((unsigned long) events64, get_order(size));
-        else
-                kfree(events64);
-        return numevents;
-}
-
-/*
- * Get a yet unused TLS descriptor index.
- */
-static int
-get_free_idx (void)
-{
-        struct thread_struct *t = &current->thread;
-        int idx;
-
-        for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
-                if (desc_empty(t->tls_array + idx))
-                        return idx + GDT_ENTRY_TLS_MIN;
-        return -ESRCH;
-}
-
-static void set_tls_desc(struct task_struct *p, int idx,
-                const struct ia32_user_desc *info, int n)
-{
-        struct thread_struct *t = &p->thread;
-        struct desc_struct *desc = &t->tls_array[idx - GDT_ENTRY_TLS_MIN];
-        int cpu;
-
-        /*
-         * We must not get preempted while modifying the TLS.
-         */
-        cpu = get_cpu();
-
-        while (n-- > 0) {
-                if (LDT_empty(info)) {
-                        desc->a = 0;
-                        desc->b = 0;
-                } else {
-                        desc->a = LDT_entry_a(info);
-                        desc->b = LDT_entry_b(info);
-                }
-
-                ++info;
-                ++desc;
-        }
-
-        if (t == &current->thread)
-                load_TLS(t, cpu);
-
-        put_cpu();
-}
-
-/*
- * Set a given TLS descriptor:
- */
-asmlinkage int
-sys32_set_thread_area (struct ia32_user_desc __user *u_info)
-{
-        struct ia32_user_desc info;
-        int idx;
-
-        if (copy_from_user(&info, u_info, sizeof(info)))
-                return -EFAULT;
-        idx = info.entry_number;
-
-        /*
-         * index -1 means the kernel should try to find and allocate an empty descriptor:
-         */
-        if (idx == -1) {
-                idx = get_free_idx();
-                if (idx < 0)
-                        return idx;
-                if (put_user(idx, &u_info->entry_number))
-                        return -EFAULT;
-        }
-
-        if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
-                return -EINVAL;
-
-        set_tls_desc(current, idx, &info, 1);
-        return 0;
-}
-
-/*
- * Get the current Thread-Local Storage area:
- */
-
-#define GET_BASE(desc) (                        \
-        (((desc)->a >> 16) & 0x0000ffff) |      \
-        (((desc)->b << 16) & 0x00ff0000) |      \
-        ( (desc)->b        & 0xff000000)   )
-
-#define GET_LIMIT(desc) (                       \
-        ((desc)->a & 0x0ffff) |                 \
-         ((desc)->b & 0xf0000) )
-
-#define GET_32BIT(desc)         (((desc)->b >> 22) & 1)
-#define GET_CONTENTS(desc)      (((desc)->b >> 10) & 3)
-#define GET_WRITABLE(desc)      (((desc)->b >>  9) & 1)
-#define GET_LIMIT_PAGES(desc)   (((desc)->b >> 23) & 1)
-#define GET_PRESENT(desc)       (((desc)->b >> 15) & 1)
-#define GET_USEABLE(desc)       (((desc)->b >> 20) & 1)
-
-static void fill_user_desc(struct ia32_user_desc *info, int idx,
-                const struct desc_struct *desc)
-{
-        info->entry_number = idx;
-        info->base_addr = GET_BASE(desc);
-        info->limit = GET_LIMIT(desc);
-        info->seg_32bit = GET_32BIT(desc);
-        info->contents = GET_CONTENTS(desc);
-        info->read_exec_only = !GET_WRITABLE(desc);
-        info->limit_in_pages = GET_LIMIT_PAGES(desc);
-        info->seg_not_present = !GET_PRESENT(desc);
-        info->useable = GET_USEABLE(desc);
-}
-
-asmlinkage int
-sys32_get_thread_area (struct ia32_user_desc __user *u_info)
-{
-        struct ia32_user_desc info;
-        struct desc_struct *desc;
-        int idx;
-
-        if (get_user(idx, &u_info->entry_number))
-                return -EFAULT;
-        if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
-                return -EINVAL;
-
-        desc = current->thread.tls_array + idx - GDT_ENTRY_TLS_MIN;
-        fill_user_desc(&info, idx, desc);
-
-        if (copy_to_user(u_info, &info, sizeof(info)))
-                return -EFAULT;
-        return 0;
-}
-
-struct regset_get {
-        void *kbuf;
-        void __user *ubuf;
-};
-
-struct regset_set {
-        const void *kbuf;
-        const void __user *ubuf;
-};
-
-struct regset_getset {
-        struct task_struct *target;
-        const struct user_regset *regset;
-        union {
-                struct regset_get get;
-                struct regset_set set;
-        } u;
-        unsigned int pos;
-        unsigned int count;
-        int ret;
-};
-
-static void getfpreg(struct task_struct *task, int regno, int *val)
-{
-        switch (regno / sizeof(int)) {
-        case 0:
-                *val = task->thread.fcr & 0xffff;
-                break;
-        case 1:
-                *val = task->thread.fsr & 0xffff;
-                break;
-        case 2:
-                *val = (task->thread.fsr>>16) & 0xffff;
-                break;
-        case 3:
-                *val = task->thread.fir;
-                break;
-        case 4:
-                *val = (task->thread.fir>>32) & 0xffff;
-                break;
-        case 5:
-                *val = task->thread.fdr;
-                break;
-        case 6:
-                *val = (task->thread.fdr >> 32) & 0xffff;
-                break;
-        }
-}
-
-static void setfpreg(struct task_struct *task, int regno, int val)
-{
-        switch (regno / sizeof(int)) {
-        case 0:
-                task->thread.fcr = (task->thread.fcr & (~0x1f3f))
-                        | (val & 0x1f3f);
-                break;
-        case 1:
-                task->thread.fsr = (task->thread.fsr & (~0xffff)) | val;
-                break;
-        case 2:
-                task->thread.fsr = (task->thread.fsr & (~0xffff0000))
-                        | (val << 16);
-                break;
-        case 3:
-                task->thread.fir = (task->thread.fir & (~0xffffffff)) | val;
-                break;
-        case 5:
-                task->thread.fdr = (task->thread.fdr & (~0xffffffff)) | val;
-                break;
-        }
-}
-
-static void access_fpreg_ia32(int regno, void *reg,
-                struct pt_regs *pt, struct switch_stack *sw,
-                int tos, int write)
-{
-        void *f;
-
-        if ((regno += tos) >= 8)
-                regno -= 8;
-        if (regno < 4)
-                f = &pt->f8 + regno;
-        else if (regno <= 7)
-                f = &sw->f12 + (regno - 4);
-        else {
-                printk(KERN_ERR "regno must be less than 7 \n");
-                 return;
-        }
-
-        if (write)
-                memcpy(f, reg, sizeof(struct _fpreg_ia32));
-        else
-                memcpy(reg, f, sizeof(struct _fpreg_ia32));
-}
-
-static void do_fpregs_get(struct unw_frame_info *info, void *arg)
-{
-        struct regset_getset *dst = arg;
-        struct task_struct *task = dst->target;
-        struct pt_regs *pt;
-        int start, end, tos;
-        char buf[80];
-
-        if (dst->count == 0 || unw_unwind_to_user(info) < 0)
-                return;
-        if (dst->pos < 7 * sizeof(int)) {
-                end = min((dst->pos + dst->count),
-                        (unsigned int)(7 * sizeof(int)));
-                for (start = dst->pos; start < end; start += sizeof(int))
-                        getfpreg(task, start, (int *)(buf + start));
-                dst->ret = user_regset_copyout(&dst->pos, &dst->count,
-                                &dst->u.get.kbuf, &dst->u.get.ubuf, buf,
-                                0, 7 * sizeof(int));
-                if (dst->ret || dst->count == 0)
-                        return;
-        }
-        if (dst->pos < sizeof(struct ia32_user_i387_struct)) {
-                pt = task_pt_regs(task);
-                tos = (task->thread.fsr >> 11) & 7;
-                end = min(dst->pos + dst->count,
-                        (unsigned int)(sizeof(struct ia32_user_i387_struct)));
-                start = (dst->pos - 7 * sizeof(int)) /
-                        sizeof(struct _fpreg_ia32);
-                end = (end - 7 * sizeof(int)) / sizeof(struct _fpreg_ia32);
-                for (; start < end; start++)
-                        access_fpreg_ia32(start,
-                                (struct _fpreg_ia32 *)buf + start,
-                                pt, info->sw, tos, 0);
-                dst->ret = user_regset_copyout(&dst->pos, &dst->count,
-                                &dst->u.get.kbuf, &dst->u.get.ubuf,
-                                buf, 7 * sizeof(int),
-                                sizeof(struct ia32_user_i387_struct));
-                if (dst->ret || dst->count == 0)
-                        return;
-        }
-}
-
-static void do_fpregs_set(struct unw_frame_info *info, void *arg)
-{
-        struct regset_getset *dst = arg;
-        struct task_struct *task = dst->target;
-        struct pt_regs *pt;
-        char buf[80];
-        int end, start, tos;
-
-        if (dst->count == 0 || unw_unwind_to_user(info) < 0)
-                return;
-
-        if (dst->pos < 7 * sizeof(int)) {
-                start = dst->pos;
-                dst->ret = user_regset_copyin(&dst->pos, &dst->count,
-                                &dst->u.set.kbuf, &dst->u.set.ubuf, buf,
-                                0, 7 * sizeof(int));
-                if (dst->ret)
-                        return;
-                for (; start < dst->pos; start += sizeof(int))
-                        setfpreg(task, start, *((int *)(buf + start)));
-                if (dst->count == 0)
-                        return;
-        }
-        if (dst->pos < sizeof(struct ia32_user_i387_struct)) {
-                start = (dst->pos - 7 * sizeof(int)) /
-                        sizeof(struct _fpreg_ia32);
-                dst->ret = user_regset_copyin(&dst->pos, &dst->count,
-                                &dst->u.set.kbuf, &dst->u.set.ubuf,
-                                buf, 7 * sizeof(int),
-                                sizeof(struct ia32_user_i387_struct));
-                if (dst->ret)
-                        return;
-                pt = task_pt_regs(task);
-                tos = (task->thread.fsr >> 11) & 7;
-                end = (dst->pos - 7 * sizeof(int)) / sizeof(struct _fpreg_ia32);
-                for (; start < end; start++)
-                        access_fpreg_ia32(start,
-                                (struct _fpreg_ia32 *)buf + start,
-                                pt, info->sw, tos, 1);
-                if (dst->count == 0)
-                        return;
-        }
-}
-
-#define OFFSET(member) ((int)(offsetof(struct ia32_user_fxsr_struct, member)))
-static void getfpxreg(struct task_struct *task, int start, int end, char *buf)
-{
-        int min_val;
-
-        min_val = min(end, OFFSET(fop));
-        while (start < min_val) {
-                if (start == OFFSET(cwd))
-                        *((short *)buf) = task->thread.fcr & 0xffff;
-                else if (start == OFFSET(swd))
-                        *((short *)buf) = task->thread.fsr & 0xffff;
-                else if (start == OFFSET(twd))
-                        *((short *)buf) = (task->thread.fsr>>16) & 0xffff;
-                buf += 2;
-                start += 2;
-        }
-        /* skip fop element */
-        if (start == OFFSET(fop)) {
-                start += 2;
-                buf += 2;
-        }
-        while (start < end) {
-                if (start == OFFSET(fip))
-                        *((int *)buf) = task->thread.fir;
-                else if (start == OFFSET(fcs))
-                        *((int *)buf) = (task->thread.fir>>32) & 0xffff;
-                else if (start == OFFSET(foo))
-                        *((int *)buf) = task->thread.fdr;
-                else if (start == OFFSET(fos))
-                        *((int *)buf) = (task->thread.fdr>>32) & 0xffff;
-                else if (start == OFFSET(mxcsr))
-                        *((int *)buf) = ((task->thread.fcr>>32) & 0xff80)
-                                         | ((task->thread.fsr>>32) & 0x3f);
-                buf += 4;
-                start += 4;
-        }
-}
-
-static void setfpxreg(struct task_struct *task, int start, int end, char *buf)
-{
-        int min_val, num32;
-        short num;
-        unsigned long num64;
-
-        min_val = min(end, OFFSET(fop));
-        while (start < min_val) {
-                num = *((short *)buf);
-                if (start == OFFSET(cwd)) {
-                        task->thread.fcr = (task->thread.fcr & (~0x1f3f))
-                                                | (num & 0x1f3f);
-                } else if (start == OFFSET(swd)) {
-                        task->thread.fsr = (task->thread.fsr & (~0xffff)) | num;
-                } else if (start == OFFSET(twd)) {
-                        task->thread.fsr = (task->thread.fsr & (~0xffff0000))
-                                | (((int)num) << 16);
-                }
-                buf += 2;
-                start += 2;
-        }
-        /* skip fop element */
-        if (start == OFFSET(fop)) {
-                start += 2;
-                buf += 2;
-        }
-        while (start < end) {
-                num32 = *((int *)buf);
-                if (start == OFFSET(fip))
-                        task->thread.fir = (task->thread.fir & (~0xffffffff))
-                                                 | num32;
-                else if (start == OFFSET(foo))
-                        task->thread.fdr = (task->thread.fdr & (~0xffffffff))
-                                                 | num32;
-                else if (start == OFFSET(mxcsr)) {
-                        num64 = num32 & 0xff10;
-                        task->thread.fcr = (task->thread.fcr &
-                                (~0xff1000000000UL)) | (num64<<32);
-                        num64 = num32 & 0x3f;
-                        task->thread.fsr = (task->thread.fsr &
-                                (~0x3f00000000UL)) | (num64<<32);
-                }
-                buf += 4;
-                start += 4;
-        }
-}
-
-static void do_fpxregs_get(struct unw_frame_info *info, void *arg)
-{
-        struct regset_getset *dst = arg;
-        struct task_struct *task = dst->target;
-        struct pt_regs *pt;
-        char buf[128];
-        int start, end, tos;
-
-        if (dst->count == 0 || unw_unwind_to_user(info) < 0)
-                return;
-        if (dst->pos < OFFSET(st_space[0])) {
-                end = min(dst->pos + dst->count, (unsigned int)32);
-                getfpxreg(task, dst->pos, end, buf);
-                dst->ret = user_regset_copyout(&dst->pos, &dst->count,
-                                &dst->u.get.kbuf, &dst->u.get.ubuf, buf,
-                                0, OFFSET(st_space[0]));
-                if (dst->ret || dst->count == 0)
-                        return;
-        }
-        if (dst->pos < OFFSET(xmm_space[0])) {
-                pt = task_pt_regs(task);
-                tos = (task->thread.fsr >> 11) & 7;
-                end = min(dst->pos + dst->count,
-                                (unsigned int)OFFSET(xmm_space[0]));
-                start = (dst->pos - OFFSET(st_space[0])) / 16;
-                end = (end - OFFSET(st_space[0])) / 16;
-                for (; start < end; start++)
-                        access_fpreg_ia32(start, buf + 16 * start, pt,
-                                                info->sw, tos, 0);
-                dst->ret = user_regset_copyout(&dst->pos, &dst->count,
-                                &dst->u.get.kbuf, &dst->u.get.ubuf,
-                                buf, OFFSET(st_space[0]), OFFSET(xmm_space[0]));
-                if (dst->ret || dst->count == 0)
-                        return;
-        }
-        if (dst->pos < OFFSET(padding[0]))
-                dst->ret = user_regset_copyout(&dst->pos, &dst->count,
-                                &dst->u.get.kbuf, &dst->u.get.ubuf,
-                                &info->sw->f16, OFFSET(xmm_space[0]),
-                                OFFSET(padding[0]));
-}
-
-static void do_fpxregs_set(struct unw_frame_info *info, void *arg)
-{
-        struct regset_getset *dst = arg;
-        struct task_struct *task = dst->target;
-        char buf[128];
-        int start, end;
-
-        if (dst->count == 0 || unw_unwind_to_user(info) < 0)
-                return;
-
-        if (dst->pos < OFFSET(st_space[0])) {
-                start = dst->pos;
-                dst->ret = user_regset_copyin(&dst->pos, &dst->count,
-                                &dst->u.set.kbuf, &dst->u.set.ubuf,
-                                buf, 0, OFFSET(st_space[0]));
-                if (dst->ret)
-                        return;
-                setfpxreg(task, start, dst->pos, buf);
-                if (dst->count == 0)
-                        return;
-        }
-        if (dst->pos < OFFSET(xmm_space[0])) {
-                struct pt_regs *pt;
-                int tos;
-                pt = task_pt_regs(task);
-                tos = (task->thread.fsr >> 11) & 7;
-                start = (dst->pos - OFFSET(st_space[0])) / 16;
-                dst->ret = user_regset_copyin(&dst->pos, &dst->count,
-                                &dst->u.set.kbuf, &dst->u.set.ubuf,
-                                buf, OFFSET(st_space[0]), OFFSET(xmm_space[0]));
-                if (dst->ret)
-                        return;
-                end = (dst->pos - OFFSET(st_space[0])) / 16;
-                for (; start < end; start++)
-                        access_fpreg_ia32(start, buf + 16 * start, pt, info->sw,
-                                                 tos, 1);
-                if (dst->count == 0)
-                        return;
-        }
-        if (dst->pos < OFFSET(padding[0]))
-                dst->ret = user_regset_copyin(&dst->pos, &dst->count,
-                                &dst->u.set.kbuf, &dst->u.set.ubuf,
-                                &info->sw->f16, OFFSET(xmm_space[0]),
-                                 OFFSET(padding[0]));
-}
-#undef OFFSET
-
-static int do_regset_call(void (*call)(struct unw_frame_info *, void *),
-                struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                const void *kbuf, const void __user *ubuf)
-{
-        struct regset_getset info = { .target = target, .regset = regset,
-                .pos = pos, .count = count,
-                .u.set = { .kbuf = kbuf, .ubuf = ubuf },
-                .ret = 0 };
-
-        if (target == current)
-                unw_init_running(call, &info);
-        else {
-                struct unw_frame_info ufi;
-                memset(&ufi, 0, sizeof(ufi));
-                unw_init_from_blocked_task(&ufi, target);
-                (*call)(&ufi, &info);
-        }
-
-        return info.ret;
-}
-
-static int ia32_fpregs_get(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                void *kbuf, void __user *ubuf)
-{
-        return do_regset_call(do_fpregs_get, target, regset, pos, count,
-                kbuf, ubuf);
-}
-
-static int ia32_fpregs_set(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                const void *kbuf, const void __user *ubuf)
-{
-        return do_regset_call(do_fpregs_set, target, regset, pos, count,
-                kbuf, ubuf);
-}
-
-static int ia32_fpxregs_get(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                void *kbuf, void __user *ubuf)
-{
-        return do_regset_call(do_fpxregs_get, target, regset, pos, count,
-                kbuf, ubuf);
-}
-
-static int ia32_fpxregs_set(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                const void *kbuf, const void __user *ubuf)
-{
-        return do_regset_call(do_fpxregs_set, target, regset, pos, count,
-                kbuf, ubuf);
-}
-
-static int ia32_genregs_get(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                void *kbuf, void __user *ubuf)
-{
-        if (kbuf) {
-                u32 *kp = kbuf;
-                while (count > 0) {
-                        *kp++ = getreg(target, pos);
-                        pos += 4;
-                        count -= 4;
-                }
-        } else {
-                u32 __user *up = ubuf;
-                while (count > 0) {
-                        if (__put_user(getreg(target, pos), up++))
-                                return -EFAULT;
-                        pos += 4;
-                        count -= 4;
-                }
-        }
-        return 0;
-}
-
-static int ia32_genregs_set(struct task_struct *target,
-                const struct user_regset *regset,
-                unsigned int pos, unsigned int count,
-                const void *kbuf, const void __user *ubuf)
-{
-        int ret = 0;
-
-        if (kbuf) {
-                const u32 *kp = kbuf;
-                while (!ret && count > 0) {
-                        putreg(target, pos, *kp++);
-                        pos += 4;
-                        count -= 4;
-                }
-        } else {
-                const u32 __user *up = ubuf;
-                u32 val;
-                while (!ret && count > 0) {
-                        ret = __get_user(val, up++);
-                        if (!ret)
-                                putreg(target, pos, val);
-                        pos += 4;
-                        count -= 4;
-                }
-        }
-        return ret;
-}
-
-static int ia32_tls_active(struct task_struct *target,
-                const struct user_regset *regset)
-{
-        struct thread_struct *t = &target->thread;
-        int n = GDT_ENTRY_TLS_ENTRIES;
-        while (n > 0 && desc_empty(&t->tls_array[n -1]))
-                --n;
-        return n;
-}
-
-static int ia32_tls_get(struct task_struct *target,
-                const struct user_regset *regset, unsigned int pos,
-                unsigned int count, void *kbuf, void __user *ubuf)
-{
-        const struct desc_struct *tls;
-
-        if (pos > GDT_ENTRY_TLS_ENTRIES * sizeof(struct ia32_user_desc) ||
-                        (pos % sizeof(struct ia32_user_desc)) != 0 ||
-                        (count % sizeof(struct ia32_user_desc)) != 0)
-                return -EINVAL;
-
-        pos /= sizeof(struct ia32_user_desc);
-        count /= sizeof(struct ia32_user_desc);
-
-        tls = &target->thread.tls_array[pos];
-
-        if (kbuf) {
-                struct ia32_user_desc *info = kbuf;
-                while (count-- > 0)
-                        fill_user_desc(info++, GDT_ENTRY_TLS_MIN + pos++,
-                                        tls++);
-        } else {
-                struct ia32_user_desc __user *u_info = ubuf;
-                while (count-- > 0) {
-                        struct ia32_user_desc info;
-                        fill_user_desc(&info, GDT_ENTRY_TLS_MIN + pos++, tls++);
-                        if (__copy_to_user(u_info++, &info, sizeof(info)))
-                                return -EFAULT;
-                }
-        }
-
-        return 0;
-}
-
-static int ia32_tls_set(struct task_struct *target,
-                const struct user_regset *regset, unsigned int pos,
-                unsigned int count, const void *kbuf, const void __user *ubuf)
-{
-        struct ia32_user_desc infobuf[GDT_ENTRY_TLS_ENTRIES];
-        const struct ia32_user_desc *info;
-
-        if (pos > GDT_ENTRY_TLS_ENTRIES * sizeof(struct ia32_user_desc) ||
-                        (pos % sizeof(struct ia32_user_desc)) != 0 ||
-                        (count % sizeof(struct ia32_user_desc)) != 0)
-                return -EINVAL;
-
-        if (kbuf)
-                info = kbuf;
-        else if (__copy_from_user(infobuf, ubuf, count))
-                return -EFAULT;
-        else
-                info = infobuf;
-
-        set_tls_desc(target,
-                GDT_ENTRY_TLS_MIN + (pos / sizeof(struct ia32_user_desc)),
-                info, count / sizeof(struct ia32_user_desc));
-
-        return 0;
-}
-
-/*
- * This should match arch/i386/kernel/ptrace.c:native_regsets.
- * XXX ioperm? vm86?
- */
-static const struct user_regset ia32_regsets[] = {
-        {
-                .core_note_type = NT_PRSTATUS,
-                .n = sizeof(struct user_regs_struct32)/4,
-                .size = 4, .align = 4,
-                .get = ia32_genregs_get, .set = ia32_genregs_set
-        },
-        {
-                .core_note_type = NT_PRFPREG,
-                .n = sizeof(struct ia32_user_i387_struct) / 4,
-                .size = 4, .align = 4,
-                .get = ia32_fpregs_get, .set = ia32_fpregs_set
-        },
-        {
-                .core_note_type = NT_PRXFPREG,
-                .n = sizeof(struct ia32_user_fxsr_struct) / 4,
-                .size = 4, .align = 4,
-                .get = ia32_fpxregs_get, .set = ia32_fpxregs_set
-        },
-        {
-                .core_note_type = NT_386_TLS,
-                .n = GDT_ENTRY_TLS_ENTRIES,
-                .bias = GDT_ENTRY_TLS_MIN,
-                .size = sizeof(struct ia32_user_desc),
-                .align = sizeof(struct ia32_user_desc),
-                .active = ia32_tls_active,
-                .get = ia32_tls_get, .set = ia32_tls_set,
-        },
-};
-
-const struct user_regset_view user_ia32_view = {
-        .name = "i386", .e_machine = EM_386,
-        .regsets = ia32_regsets, .n = ARRAY_SIZE(ia32_regsets)
-};
-
-long sys32_fadvise64_64(int fd, __u32 offset_low, __u32 offset_high, 
-                        __u32 len_low, __u32 len_high, int advice)
-{ 
-        return sys_fadvise64_64(fd,
-                               (((u64)offset_high)<<32) | offset_low,
-                               (((u64)len_high)<<32) | len_low,
-                               advice); 
-} 
-
-#ifdef  NOTYET  /* UNTESTED FOR IA64 FROM HERE DOWN */
-
-asmlinkage long sys32_setreuid(compat_uid_t ruid, compat_uid_t euid)
-{
-        uid_t sruid, seuid;
-
-        sruid = (ruid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)ruid);
-        seuid = (euid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)euid);
-        return sys_setreuid(sruid, seuid);
-}
-
-asmlinkage long
-sys32_setresuid(compat_uid_t ruid, compat_uid_t euid,
-                compat_uid_t suid)
-{
-        uid_t sruid, seuid, ssuid;
-
-        sruid = (ruid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)ruid);
-        seuid = (euid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)euid);
-        ssuid = (suid == (compat_uid_t)-1) ? ((uid_t)-1) : ((uid_t)suid);
-        return sys_setresuid(sruid, seuid, ssuid);
-}
-
-asmlinkage long
-sys32_setregid(compat_gid_t rgid, compat_gid_t egid)
-{
-        gid_t srgid, segid;
-
-        srgid = (rgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)rgid);
-        segid = (egid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)egid);
-        return sys_setregid(srgid, segid);
-}
-
-asmlinkage long
-sys32_setresgid(compat_gid_t rgid, compat_gid_t egid,
-                compat_gid_t sgid)
-{
-        gid_t srgid, segid, ssgid;
-
-        srgid = (rgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)rgid);
-        segid = (egid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)egid);
-        ssgid = (sgid == (compat_gid_t)-1) ? ((gid_t)-1) : ((gid_t)sgid);
-        return sys_setresgid(srgid, segid, ssgid);
-}
-#endif /* NOTYET */
diff --git a/arch/ia64/include/asm/acpi.h b/arch/ia64/include/asm/acpi.h
index 93997bd5edc3..21adbd7f90f8 100644
--- a/arch/ia64/include/asm/acpi.h
+++ b/arch/ia64/include/asm/acpi.h
@@ -100,7 +100,32 @@ ia64_acpi_release_global_lock (unsigned int *lock)
 static inline void disable_acpi(void) { }
 static inline void pci_acpi_crs_quirks(void) { }
 
+#ifdef CONFIG_IA64_GENERIC
 const char *acpi_get_sysname (void);
+#else
+static inline const char *acpi_get_sysname (void)
+{
+# if defined (CONFIG_IA64_HP_SIM)
+        return "hpsim";
+# elif defined (CONFIG_IA64_HP_ZX1)
+        return "hpzx1";
+# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
+        return "hpzx1_swiotlb";
+# elif defined (CONFIG_IA64_SGI_SN2)
+        return "sn2";
+# elif defined (CONFIG_IA64_SGI_UV)
+        return "uv";
+# elif defined (CONFIG_IA64_DIG)
+        return "dig";
+# elif defined (CONFIG_IA64_XEN_GUEST)
+        return "xen";
+# elif defined(CONFIG_IA64_DIG_VTD)
+        return "dig_vtd";
+# else
+#       error Unknown platform.  Fix acpi.c.
+# endif
+}
+#endif
 int acpi_request_vector (u32 int_type);
 int acpi_gsi_to_irq (u32 gsi, unsigned int *irq);
 
diff --git a/arch/ia64/include/asm/ia32.h b/arch/ia64/include/asm/ia32.h
deleted file mode 100644
index 2390ee145aa1..000000000000
--- a/arch/ia64/include/asm/ia32.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef _ASM_IA64_IA32_H
-#define _ASM_IA64_IA32_H
-
-
-#include <asm/ptrace.h>
-#include <asm/signal.h>
-
-#define IA32_NR_syscalls                285     /* length of syscall table */
-#define IA32_PAGE_SHIFT                 12      /* 4KB pages */
-
-#ifndef __ASSEMBLY__
-
-# ifdef CONFIG_IA32_SUPPORT
-
-#define IA32_PAGE_OFFSET        0xc0000000
-
-extern void ia32_cpu_init (void);
-extern void ia32_mem_init (void);
-extern void ia32_gdt_init (void);
-extern int ia32_exception (struct pt_regs *regs, unsigned long isr);
-extern int ia32_intercept (struct pt_regs *regs, unsigned long isr);
-extern int ia32_clone_tls (struct task_struct *child, struct pt_regs *childregs);
-
-# endif /* !CONFIG_IA32_SUPPORT */
-
-/* Declare this unconditionally, so we don't get warnings for unreachable code.  */
-extern int ia32_setup_frame1 (int sig, struct k_sigaction *ka, siginfo_t *info,
-                              sigset_t *set, struct pt_regs *regs);
-#if PAGE_SHIFT > IA32_PAGE_SHIFT
-extern int ia32_copy_ia64_partial_page_list(struct task_struct *,
-                                        unsigned long);
-extern void ia32_drop_ia64_partial_page_list(struct task_struct *);
-#else
-# define ia32_copy_ia64_partial_page_list(a1, a2)       0
-# define ia32_drop_ia64_partial_page_list(a1)   do { ; } while (0)
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_IA64_IA32_H */
diff --git a/arch/ia64/include/asm/pgtable.h b/arch/ia64/include/asm/pgtable.h
index 69bf13857a9f..c3286f42e501 100644
--- a/arch/ia64/include/asm/pgtable.h
+++ b/arch/ia64/include/asm/pgtable.h
@@ -462,7 +462,7 @@ pte_same (pte_t a, pte_t b)
         return pte_val(a) == pte_val(b);
 }
 
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 extern void paging_init (void);
diff --git a/arch/ia64/include/asm/processor.h b/arch/ia64/include/asm/processor.h
index 7fa90f73f6be..348e44d08ce3 100644
--- a/arch/ia64/include/asm/processor.h
+++ b/arch/ia64/include/asm/processor.h
@@ -270,23 +270,6 @@ typedef struct {
                  (int __user *) (addr));                                                        \
 })
 
-#ifdef CONFIG_IA32_SUPPORT
-struct desc_struct {
-        unsigned int a, b;
-};
-
-#define desc_empty(desc)                (!((desc)->a | (desc)->b))
-#define desc_equal(desc1, desc2)        (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
-
-#define GDT_ENTRY_TLS_ENTRIES   3
-#define GDT_ENTRY_TLS_MIN       6
-#define GDT_ENTRY_TLS_MAX       (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
-
-#define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
-
-struct ia64_partial_page_list;
-#endif
-
 struct thread_struct {
         __u32 flags;                    /* various thread flags (see IA64_THREAD_*) */
         /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
@@ -298,29 +281,6 @@ struct thread_struct {
         __u64 rbs_bot;                  /* the base address for the RBS */
         int last_fph_cpu;               /* CPU that may hold the contents of f32-f127 */
 
-#ifdef CONFIG_IA32_SUPPORT
-        __u64 eflag;                    /* IA32 EFLAGS reg */
-        __u64 fsr;                      /* IA32 floating pt status reg */
-        __u64 fcr;                      /* IA32 floating pt control reg */
-        __u64 fir;                      /* IA32 fp except. instr. reg */
-        __u64 fdr;                      /* IA32 fp except. data reg */
-        __u64 old_k1;                   /* old value of ar.k1 */
-        __u64 old_iob;                  /* old IOBase value */
-        struct ia64_partial_page_list *ppl; /* partial page list for 4K page size issue */
-        /* cached TLS descriptors. */
-        struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
-
-# define INIT_THREAD_IA32       .eflag =        0,                      \
-                                .fsr =          0,                      \
-                                .fcr =          0x17800000037fULL,      \
-                                .fir =          0,                      \
-                                .fdr =          0,                      \
-                                .old_k1 =       0,                      \
-                                .old_iob =      0,                      \
-                                .ppl =          NULL,
-#else
-# define INIT_THREAD_IA32
-#endif /* CONFIG_IA32_SUPPORT */
 #ifdef CONFIG_PERFMON
         void *pfm_context;                   /* pointer to detailed PMU context */
         unsigned long pfm_needs_checking;    /* when >0, pending perfmon work on kernel exit */
@@ -342,7 +302,6 @@ struct thread_struct {
         .rbs_bot =      STACK_TOP - DEFAULT_USER_STACK_SIZE,    \
         .task_size =    DEFAULT_TASK_SIZE,                      \
         .last_fph_cpu =  -1,                                    \
-        INIT_THREAD_IA32                                        \
         INIT_THREAD_PM                                          \
         .dbr =          {0, },                                  \
         .ibr =          {0, },                                  \
@@ -485,11 +444,6 @@ extern void __ia64_load_fpu (struct ia64_fpreg *fph);
 extern void ia64_save_debug_regs (unsigned long *save_area);
 extern void ia64_load_debug_regs (unsigned long *save_area);
 
-#ifdef CONFIG_IA32_SUPPORT
-extern void ia32_save_state (struct task_struct *task);
-extern void ia32_load_state (struct task_struct *task);
-#endif
-
 #define ia64_fph_enable()       do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 #define ia64_fph_disable()      do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
 
diff --git a/arch/ia64/include/asm/scatterlist.h b/arch/ia64/include/asm/scatterlist.h
index d6f57874041d..d8e98961dec7 100644
--- a/arch/ia64/include/asm/scatterlist.h
+++ b/arch/ia64/include/asm/scatterlist.h
@@ -2,25 +2,6 @@
 #define _ASM_IA64_SCATTERLIST_H
 
 /*
- * Modified 1998-1999, 2001-2002, 2004
- *      David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
- */
-
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long sg_magic;
-#endif
-        unsigned long page_link;
-        unsigned int offset;
-        unsigned int length;    /* buffer length */
-
-        dma_addr_t dma_address;
-        unsigned int dma_length;
-};
-
-/*
  * It used to be that ISA_DMA_THRESHOLD had something to do with the
  * DMA-limits of ISA-devices.  Nowadays, its only remaining use (apart
  * from the aha1542.c driver, which isn't 64-bit clean anyhow) is to
@@ -30,9 +11,6 @@ struct scatterlist {
  */
 #define ISA_DMA_THRESHOLD       0xffffffff
 
-#define sg_dma_len(sg)          ((sg)->dma_length)
-#define sg_dma_address(sg)      ((sg)->dma_address)
-
-#define ARCH_HAS_SG_CHAIN
+#include <asm-generic/scatterlist.h>
 
 #endif /* _ASM_IA64_SCATTERLIST_H */
diff --git a/arch/ia64/include/asm/syscall.h b/arch/ia64/include/asm/syscall.h
index 2f758a42f94b..a7ff1c6ab068 100644
--- a/arch/ia64/include/asm/syscall.h
+++ b/arch/ia64/include/asm/syscall.h
@@ -22,33 +22,18 @@ static inline long syscall_get_nr(struct task_struct *task,
         if ((long)regs->cr_ifs < 0) /* Not a syscall */
                 return -1;
 
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs))
-                return regs->r1;
-#endif
-
         return regs->r15;
 }
 
 static inline void syscall_rollback(struct task_struct *task,
                                     struct pt_regs *regs)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs))
-                regs->r8 = regs->r1;
-#endif
-
         /* do nothing */
 }
 
 static inline long syscall_get_error(struct task_struct *task,
                                      struct pt_regs *regs)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs))
-                return regs->r8;
-#endif
-
         return regs->r10 == -1 ? regs->r8:0;
 }
 
@@ -62,13 +47,6 @@ static inline void syscall_set_return_value(struct task_struct *task,
                                             struct pt_regs *regs,
                                             int error, long val)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs)) {
-                regs->r8 = (long) error ? error : val;
-                return;
-        }
-#endif
-
         if (error) {
                 /* error < 0, but ia64 uses > 0 return value */
                 regs->r8 = -error;
@@ -89,37 +67,6 @@ static inline void syscall_get_arguments(struct task_struct *task,
 {
         BUG_ON(i + n > 6);
 
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs)) {
-                switch (i + n) {
-                case 6:
-                        if (!n--) break;
-                        *args++ = regs->r13;
-                case 5:
-                        if (!n--) break;
-                        *args++ = regs->r15;
-                case 4:
-                        if (!n--) break;
-                        *args++ = regs->r14;
-                case 3:
-                        if (!n--) break;
-                        *args++ = regs->r10;
-                case 2:
-                        if (!n--) break;
-                        *args++ = regs->r9;
-                case 1:
-                        if (!n--) break;
-                        *args++ = regs->r11;
-                case 0:
-                        if (!n--) break;
-                default:
-                        BUG();
-                        break;
-                }
-
-                return;
-        }
-#endif
         ia64_syscall_get_set_arguments(task, regs, i, n, args, 0);
 }
 
@@ -130,34 +77,6 @@ static inline void syscall_set_arguments(struct task_struct *task,
 {
         BUG_ON(i + n > 6);
 
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(regs)) {
-                switch (i + n) {
-                case 6:
-                        if (!n--) break;
-                        regs->r13 = *args++;
-                case 5:
-                        if (!n--) break;
-                        regs->r15 = *args++;
-                case 4:
-                        if (!n--) break;
-                        regs->r14 = *args++;
-                case 3:
-                        if (!n--) break;
-                        regs->r10 = *args++;
-                case 2:
-                        if (!n--) break;
-                        regs->r9 = *args++;
-                case 1:
-                        if (!n--) break;
-                        regs->r11 = *args++;
-                case 0:
-                        if (!n--) break;
-                }
-
-                return;
-        }
-#endif
         ia64_syscall_get_set_arguments(task, regs, i, n, args, 1);
 }
 #endif  /* _ASM_SYSCALL_H */
diff --git a/arch/ia64/include/asm/system.h b/arch/ia64/include/asm/system.h
index 927a381c20ca..9f342a574ce8 100644
--- a/arch/ia64/include/asm/system.h
+++ b/arch/ia64/include/asm/system.h
@@ -191,15 +191,6 @@ do {								\
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_IA32_SUPPORT
-# define IS_IA32_PROCESS(regs)  (ia64_psr(regs)->is != 0)
-#else
-# define IS_IA32_PROCESS(regs)          0
-struct task_struct;
-static inline void ia32_save_state(struct task_struct *t __attribute__((unused))){}
-static inline void ia32_load_state(struct task_struct *t __attribute__((unused))){}
-#endif
-
 /*
  * Context switch from one thread to another.  If the two threads have
  * different address spaces, schedule() has already taken care of
@@ -233,7 +224,7 @@ extern void ia64_account_on_switch (struct task_struct *prev, struct task_struct
 
 #define IA64_HAS_EXTRA_STATE(t)                                                 \
         ((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)       \
-         || IS_IA32_PROCESS(task_pt_regs(t)) || PERFMON_IS_SYSWIDE())
+         || PERFMON_IS_SYSWIDE())
 
 #define __switch_to(prev,next,last) do {                                                         \
         IA64_ACCOUNT_ON_SWITCH(prev, next);                                                      \
diff --git a/arch/ia64/include/asm/unistd.h b/arch/ia64/include/asm/unistd.h
index 10a8f21ca9e3..bb8b0fff32b3 100644
--- a/arch/ia64/include/asm/unistd.h
+++ b/arch/ia64/include/asm/unistd.h
@@ -335,20 +335,6 @@
 #define __ARCH_WANT_SYS_RT_SIGACTION
 #define __ARCH_WANT_SYS_RT_SIGSUSPEND
 
-#ifdef CONFIG_IA32_SUPPORT
-# define __ARCH_WANT_SYS_FADVISE64
-# define __ARCH_WANT_SYS_GETPGRP
-# define __ARCH_WANT_SYS_LLSEEK
-# define __ARCH_WANT_SYS_NICE
-# define __ARCH_WANT_SYS_OLD_GETRLIMIT
-# define __ARCH_WANT_SYS_OLDUMOUNT
-# define __ARCH_WANT_SYS_PAUSE
-# define __ARCH_WANT_SYS_SIGPENDING
-# define __ARCH_WANT_SYS_SIGPROCMASK
-# define __ARCH_WANT_COMPAT_SYS_RT_SIGSUSPEND
-# define __ARCH_WANT_COMPAT_SYS_TIME
-#endif
-
 #if !defined(__ASSEMBLY__) && !defined(ASSEMBLER)
 
 #include <linux/types.h>
diff --git a/arch/ia64/kernel/Makefile b/arch/ia64/kernel/Makefile
index e1236349c99f..4138282aefa8 100644
--- a/arch/ia64/kernel/Makefile
+++ b/arch/ia64/kernel/Makefile
@@ -8,15 +8,13 @@ endif
 
 extra-y := head.o init_task.o vmlinux.lds
 
-obj-y := acpi.o entry.o efi.o efi_stub.o gate-data.o fsys.o ia64_ksyms.o irq.o irq_ia64.o       \
+obj-y := entry.o efi.o efi_stub.o gate-data.o fsys.o ia64_ksyms.o irq.o irq_ia64.o      \
          irq_lsapic.o ivt.o machvec.o pal.o paravirt_patchlist.o patch.o process.o perfmon.o ptrace.o sal.o             \
          salinfo.o setup.o signal.o sys_ia64.o time.o traps.o unaligned.o \
          unwind.o mca.o mca_asm.o topology.o dma-mapping.o
 
+obj-$(CONFIG_ACPI)              += acpi.o acpi-ext.o
 obj-$(CONFIG_IA64_BRL_EMU)      += brl_emu.o
-obj-$(CONFIG_IA64_GENERIC)      += acpi-ext.o
-obj-$(CONFIG_IA64_HP_ZX1)       += acpi-ext.o
-obj-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += acpi-ext.o
 
 obj-$(CONFIG_IA64_PALINFO)      += palinfo.o
 obj-$(CONFIG_IOSAPIC)           += iosapic.o
diff --git a/arch/ia64/kernel/acpi.c b/arch/ia64/kernel/acpi.c
index 40574ae11401..c16fb03037d4 100644
--- a/arch/ia64/kernel/acpi.c
+++ b/arch/ia64/kernel/acpi.c
@@ -60,11 +60,6 @@
 
 #define PREFIX                  "ACPI: "
 
-void (*pm_idle) (void);
-EXPORT_SYMBOL(pm_idle);
-void (*pm_power_off) (void);
-EXPORT_SYMBOL(pm_power_off);
-
 u32 acpi_rsdt_forced;
 unsigned int acpi_cpei_override;
 unsigned int acpi_cpei_phys_cpuid;
@@ -83,12 +78,10 @@ static unsigned long __init acpi_find_rsdp(void)
                        "v1.0/r0.71 tables no longer supported\n");
         return rsdp_phys;
 }
-#endif
 
 const char __init *
 acpi_get_sysname(void)
 {
-#ifdef CONFIG_IA64_GENERIC
         unsigned long rsdp_phys;
         struct acpi_table_rsdp *rsdp;
         struct acpi_table_xsdt *xsdt;
@@ -143,30 +136,8 @@ acpi_get_sysname(void)
 #endif
 
         return "dig";
-#else
-# if defined (CONFIG_IA64_HP_SIM)
-        return "hpsim";
-# elif defined (CONFIG_IA64_HP_ZX1)
-        return "hpzx1";
-# elif defined (CONFIG_IA64_HP_ZX1_SWIOTLB)
-        return "hpzx1_swiotlb";
-# elif defined (CONFIG_IA64_SGI_SN2)
-        return "sn2";
-# elif defined (CONFIG_IA64_SGI_UV)
-        return "uv";
-# elif defined (CONFIG_IA64_DIG)
-        return "dig";
-# elif defined (CONFIG_IA64_XEN_GUEST)
-        return "xen";
-# elif defined(CONFIG_IA64_DIG_VTD)
-        return "dig_vtd";
-# else
-#       error Unknown platform.  Fix acpi.c.
-# endif
-#endif
 }
-
-#ifdef CONFIG_ACPI
+#endif /* CONFIG_IA64_GENERIC */
 
 #define ACPI_MAX_PLATFORM_INTERRUPTS    256
 
@@ -1060,5 +1031,3 @@ void acpi_restore_state_mem(void) {}
  * do_suspend_lowlevel()
  */
 void do_suspend_lowlevel(void) {}
-
-#endif                          /* CONFIG_ACPI */
diff --git a/arch/ia64/kernel/audit.c b/arch/ia64/kernel/audit.c
index f3802ae89b10..96a9d18ff4c4 100644
--- a/arch/ia64/kernel/audit.c
+++ b/arch/ia64/kernel/audit.c
@@ -30,20 +30,11 @@ static unsigned signal_class[] = {
 
 int audit_classify_arch(int arch)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        if (arch == AUDIT_ARCH_I386)
-                return 1;
-#endif
         return 0;
 }
 
 int audit_classify_syscall(int abi, unsigned syscall)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        extern int ia32_classify_syscall(unsigned);
-        if (abi == AUDIT_ARCH_I386)
-                return ia32_classify_syscall(syscall);
-#endif
         switch(syscall) {
         case __NR_open:
                 return 2;
@@ -58,18 +49,6 @@ int audit_classify_syscall(int abi, unsigned syscall)
 
 static int __init audit_classes_init(void)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        extern __u32 ia32_dir_class[];
-        extern __u32 ia32_write_class[];
-        extern __u32 ia32_read_class[];
-        extern __u32 ia32_chattr_class[];
-        extern __u32 ia32_signal_class[];
-        audit_register_class(AUDIT_CLASS_WRITE_32, ia32_write_class);
-        audit_register_class(AUDIT_CLASS_READ_32, ia32_read_class);
-        audit_register_class(AUDIT_CLASS_DIR_WRITE_32, ia32_dir_class);
-        audit_register_class(AUDIT_CLASS_CHATTR_32, ia32_chattr_class);
-        audit_register_class(AUDIT_CLASS_SIGNAL_32, ia32_signal_class);
-#endif
         audit_register_class(AUDIT_CLASS_WRITE, write_class);
         audit_register_class(AUDIT_CLASS_READ, read_class);
         audit_register_class(AUDIT_CLASS_DIR_WRITE, dir_class);
diff --git a/arch/ia64/kernel/entry.S b/arch/ia64/kernel/entry.S
index d75b872ca4dc..9a260b317d8d 100644
--- a/arch/ia64/kernel/entry.S
+++ b/arch/ia64/kernel/entry.S
@@ -71,15 +71,6 @@ ENTRY(ia64_execve)
         add out3=16,sp                  // regs
         br.call.sptk.many rp=sys_execve
 .ret0:
-#ifdef CONFIG_IA32_SUPPORT
-        /*
-         * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
-         * from pt_regs.
-         */
-        adds r16=PT(CR_IPSR)+16,sp
-        ;;
-        ld8 r16=[r16]
-#endif
         cmp4.ge p6,p7=r8,r0
         mov ar.pfs=loc1                 // restore ar.pfs
         sxt4 r8=r8                      // return 64-bit result
@@ -108,12 +99,6 @@ ENTRY(ia64_execve)
         ldf.fill f23=[sp];      ldf.fill f24=[sp];      mov f25=f0
         ldf.fill f26=[sp];      ldf.fill f27=[sp];      mov f28=f0
         ldf.fill f29=[sp];      ldf.fill f30=[sp];      mov f31=f0
-#ifdef CONFIG_IA32_SUPPORT
-        tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
-        movl loc0=ia64_ret_from_ia32_execve
-        ;;
-(p6)    mov rp=loc0
-#endif
         br.ret.sptk.many rp
 END(ia64_execve)
 
@@ -848,30 +833,6 @@ __paravirt_work_processed_syscall:
         br.cond.sptk.many rbs_switch    // B
 END(__paravirt_leave_syscall)
 
-#ifdef __IA64_ASM_PARAVIRTUALIZED_NATIVE
-#ifdef CONFIG_IA32_SUPPORT
-GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
-        PT_REGS_UNWIND_INFO(0)
-        adds r2=PT(R8)+16,sp                    // r2 = &pt_regs.r8
-        adds r3=PT(R10)+16,sp                   // r3 = &pt_regs.r10
-        ;;
-        .mem.offset 0,0
-        st8.spill [r2]=r8       // store return value in slot for r8 and set unat bit
-        .mem.offset 8,0
-        st8.spill [r3]=r0       // clear error indication in slot for r10 and set unat bit
-#ifdef CONFIG_PARAVIRT
-        ;;
-        // don't fall through, ia64_leave_kernel may be #define'd
-        br.cond.sptk.few ia64_leave_kernel
-        ;;
-#endif /* CONFIG_PARAVIRT */
-END(ia64_ret_from_ia32_execve)
-#ifndef CONFIG_PARAVIRT
-        // fall through
-#endif
-#endif /* CONFIG_IA32_SUPPORT */
-#endif /* __IA64_ASM_PARAVIRTUALIZED_NATIVE */
-
 GLOBAL_ENTRY(__paravirt_leave_kernel)
         PT_REGS_UNWIND_INFO(0)
         /*
diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
index ec9a5fdfa1b9..179fd122e837 100644
--- a/arch/ia64/kernel/ivt.S
+++ b/arch/ia64/kernel/ivt.S
@@ -49,7 +49,6 @@
 
 #include <asm/asmmacro.h>
 #include <asm/break.h>
-#include <asm/ia32.h>
 #include <asm/kregs.h>
 #include <asm/asm-offsets.h>
 #include <asm/pgtable.h>
@@ -1386,28 +1385,6 @@ END(ia32_exception)
 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept  (30,31,59,70,71)
 ENTRY(ia32_intercept)
         DBG_FAULT(46)
-#ifdef  CONFIG_IA32_SUPPORT
-        mov r31=pr
-        MOV_FROM_ISR(r16)
-        ;;
-        extr.u r17=r16,16,8     // get ISR.code
-        mov r18=ar.eflag
-        MOV_FROM_IIM(r19)       // old eflag value
-        ;;
-        cmp.ne p6,p0=2,r17
-(p6)    br.cond.spnt 1f         // not a system flag fault
-        xor r16=r18,r19
-        ;;
-        extr.u r17=r16,18,1     // get the eflags.ac bit
-        ;;
-        cmp.eq p6,p0=0,r17
-(p6)    br.cond.spnt 1f         // eflags.ac bit didn't change
-        ;;
-        mov pr=r31,-1           // restore predicate registers
-        RFI
-
-1:
-#endif  // CONFIG_IA32_SUPPORT
         FAULT(46)
 END(ia32_intercept)
 
@@ -1416,12 +1393,7 @@ END(ia32_intercept)
 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt  (74)
 ENTRY(ia32_interrupt)
         DBG_FAULT(47)
-#ifdef CONFIG_IA32_SUPPORT
-        mov r31=pr
-        br.sptk.many dispatch_to_ia32_handler
-#else
         FAULT(47)
-#endif
 END(ia32_interrupt)
 
         .org ia64_ivt+0x6c00
@@ -1715,89 +1687,3 @@ ENTRY(dispatch_illegal_op_fault)
 (p6)    br.call.dpnt.many b6=b6         // call returns to ia64_leave_kernel
         br.sptk.many ia64_leave_kernel
 END(dispatch_illegal_op_fault)
-
-#ifdef CONFIG_IA32_SUPPORT
-
-        /*
-         * There is no particular reason for this code to be here, other than that
-         * there happens to be space here that would go unused otherwise.  If this
-         * fault ever gets "unreserved", simply moved the following code to a more
-         * suitable spot...
-         */
-
-        // IA32 interrupt entry point
-
-ENTRY(dispatch_to_ia32_handler)
-        SAVE_MIN
-        ;;
-        MOV_FROM_ISR(r14)
-        SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r3, r24)
-                                // guarantee that interruption collection is on
-        ;;
-        SSM_PSR_I(p15, p15, r3)
-        adds r3=8,r2            // Base pointer for SAVE_REST
-        ;;
-        SAVE_REST
-        ;;
-        mov r15=0x80
-        shr r14=r14,16          // Get interrupt number
-        ;;
-        cmp.ne p6,p0=r14,r15
-(p6)    br.call.dpnt.many b6=non_ia32_syscall
-
-        adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
-        adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
-        ;;
-        cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
-        ld8 r8=[r14]            // get r8
-        ;;
-        st8 [r15]=r8            // save original EAX in r1 (IA32 procs don't use the GP)
-        ;;
-        alloc r15=ar.pfs,0,0,6,0        // must first in an insn group
-        ;;
-        ld4 r8=[r14],8          // r8 == eax (syscall number)
-        mov r15=IA32_NR_syscalls
-        ;;
-        cmp.ltu.unc p6,p7=r8,r15
-        ld4 out1=[r14],8        // r9 == ecx
-        ;;
-        ld4 out2=[r14],8        // r10 == edx
-        ;;
-        ld4 out0=[r14]          // r11 == ebx
-        adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
-        ;;
-        ld4 out5=[r14],PT(R14)-PT(R13)  // r13 == ebp
-        ;;
-        ld4 out3=[r14],PT(R15)-PT(R14)  // r14 == esi
-        adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
-        ;;
-        ld4 out4=[r14]          // r15 == edi
-        movl r16=ia32_syscall_table
-        ;;
-(p6)    shladd r16=r8,3,r16     // force ni_syscall if not valid syscall number
-        ld4 r2=[r2]             // r2 = current_thread_info()->flags
-        ;;
-        ld8 r16=[r16]
-        and r2=_TIF_SYSCALL_TRACEAUDIT,r2       // mask trace or audit
-        ;;
-        mov b6=r16
-        movl r15=ia32_ret_from_syscall
-        cmp.eq p8,p0=r2,r0
-        ;;
-        mov rp=r15
-(p8)    br.call.sptk.many b6=b6
-        br.cond.sptk ia32_trace_syscall
-
-non_ia32_syscall:
-        alloc r15=ar.pfs,0,0,2,0
-        mov out0=r14                            // interrupt #
-        add out1=16,sp                          // pointer to pt_regs
-        ;;                      // avoid WAW on CFM
-        br.call.sptk.many rp=ia32_bad_interrupt
-.ret1:  movl r15=ia64_leave_kernel
-        ;;
-        mov rp=r15
-        br.ret.sptk.many rp
-END(dispatch_to_ia32_handler)
-
-#endif /* CONFIG_IA32_SUPPORT */
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 6bcbe215b9a4..b81e46b1629b 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -2713,7 +2713,7 @@ pfm_context_create(pfm_context_t *ctx, void *arg, int count, struct pt_regs *reg
                         goto buffer_error;
         }
 
-        DPRINT(("ctx=%p flags=0x%x system=%d notify_block=%d excl_idle=%d no_msg=%d ctx_fd=%d \n",
+        DPRINT(("ctx=%p flags=0x%x system=%d notify_block=%d excl_idle=%d no_msg=%d ctx_fd=%d\n",
                 ctx,
                 ctx_flags,
                 ctx->ctx_fl_system,
@@ -3677,7 +3677,7 @@ pfm_restart(pfm_context_t *ctx, void *arg, int count, struct pt_regs *regs)
          * "self-monitoring".
          */
         if (CTX_OVFL_NOBLOCK(ctx) == 0 && state == PFM_CTX_MASKED) {
-                DPRINT(("unblocking [%d] \n", task_pid_nr(task)));
+                DPRINT(("unblocking [%d]\n", task_pid_nr(task)));
                 complete(&ctx->ctx_restart_done);
         } else {
                 DPRINT(("[%d] armed exit trap\n", task_pid_nr(task)));
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index 9bcec9945c12..d92765cae10a 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -33,7 +33,6 @@
 #include <asm/cpu.h>
 #include <asm/delay.h>
 #include <asm/elf.h>
-#include <asm/ia32.h>
 #include <asm/irq.h>
 #include <asm/kexec.h>
 #include <asm/pgalloc.h>
@@ -60,6 +59,10 @@ unsigned long idle_halt;
 EXPORT_SYMBOL(idle_halt);
 unsigned long idle_nomwait;
 EXPORT_SYMBOL(idle_nomwait);
+void (*pm_idle) (void);
+EXPORT_SYMBOL(pm_idle);
+void (*pm_power_off) (void);
+EXPORT_SYMBOL(pm_power_off);
 
 void
 ia64_do_show_stack (struct unw_frame_info *info, void *arg)
@@ -358,11 +361,6 @@ ia64_save_extra (struct task_struct *task)
         if (info & PFM_CPUINFO_SYST_WIDE)
                 pfm_syst_wide_update_task(task, info, 0);
 #endif
-
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(task_pt_regs(task)))
-                ia32_save_state(task);
-#endif
 }
 
 void
@@ -383,11 +381,6 @@ ia64_load_extra (struct task_struct *task)
         if (info & PFM_CPUINFO_SYST_WIDE) 
                 pfm_syst_wide_update_task(task, info, 1);
 #endif
-
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(task_pt_regs(task)))
-                ia32_load_state(task);
-#endif
 }
 
 /*
@@ -426,7 +419,7 @@ copy_thread(unsigned long clone_flags,
              unsigned long user_stack_base, unsigned long user_stack_size,
              struct task_struct *p, struct pt_regs *regs)
 {
-        extern char ia64_ret_from_clone, ia32_ret_from_clone;
+        extern char ia64_ret_from_clone;
         struct switch_stack *child_stack, *stack;
         unsigned long rbs, child_rbs, rbs_size;
         struct pt_regs *child_ptregs;
@@ -457,7 +450,7 @@ copy_thread(unsigned long clone_flags,
         memcpy((void *) child_rbs, (void *) rbs, rbs_size);
 
         if (likely(user_mode(child_ptregs))) {
-                if ((clone_flags & CLONE_SETTLS) && !IS_IA32_PROCESS(regs))
+                if (clone_flags & CLONE_SETTLS)
                         child_ptregs->r13 = regs->r16;  /* see sys_clone2() in entry.S */
                 if (user_stack_base) {
                         child_ptregs->r12 = user_stack_base + user_stack_size - 16;
@@ -477,10 +470,7 @@ copy_thread(unsigned long clone_flags,
                 child_ptregs->r13 = (unsigned long) p;          /* set `current' pointer */
         }
         child_stack->ar_bspstore = child_rbs + rbs_size;
-        if (IS_IA32_PROCESS(regs))
-                child_stack->b0 = (unsigned long) &ia32_ret_from_clone;
-        else
-                child_stack->b0 = (unsigned long) &ia64_ret_from_clone;
+        child_stack->b0 = (unsigned long) &ia64_ret_from_clone;
 
         /* copy parts of thread_struct: */
         p->thread.ksp = (unsigned long) child_stack - 16;
@@ -515,22 +505,6 @@ copy_thread(unsigned long clone_flags,
         p->thread.flags = ((current->thread.flags & ~THREAD_FLAGS_TO_CLEAR)
                            | THREAD_FLAGS_TO_SET);
         ia64_drop_fpu(p);       /* don't pick up stale state from a CPU's fph */
-#ifdef CONFIG_IA32_SUPPORT
-        /*
-         * If we're cloning an IA32 task then save the IA32 extra
-         * state from the current task to the new task
-         */
-        if (IS_IA32_PROCESS(task_pt_regs(current))) {
-                ia32_save_state(p);
-                if (clone_flags & CLONE_SETTLS)
-                        retval = ia32_clone_tls(p, child_ptregs);
-
-                /* Copy partially mapped page list */
-                if (!retval)
-                        retval = ia32_copy_ia64_partial_page_list(p,
-                                                                clone_flags);
-        }
-#endif
 
 #ifdef CONFIG_PERFMON
         if (current->thread.pfm_context)
@@ -704,15 +678,6 @@ EXPORT_SYMBOL(kernel_thread);
 int
 kernel_thread_helper (int (*fn)(void *), void *arg)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(task_pt_regs(current))) {
-                /* A kernel thread is always a 64-bit process. */
-                current->thread.map_base  = DEFAULT_MAP_BASE;
-                current->thread.task_size = DEFAULT_TASK_SIZE;
-                ia64_set_kr(IA64_KR_IO_BASE, current->thread.old_iob);
-                ia64_set_kr(IA64_KR_TSSD, current->thread.old_k1);
-        }
-#endif
         return (*fn)(arg);
 }
 
@@ -725,14 +690,6 @@ flush_thread (void)
         /* drop floating-point and debug-register state if it exists: */
         current->thread.flags &= ~(IA64_THREAD_FPH_VALID | IA64_THREAD_DBG_VALID);
         ia64_drop_fpu(current);
-#ifdef CONFIG_IA32_SUPPORT
-        if (IS_IA32_PROCESS(task_pt_regs(current))) {
-                ia32_drop_ia64_partial_page_list(current);
-                current->thread.task_size = IA32_PAGE_OFFSET;
-                set_fs(USER_DS);
-                memset(current->thread.tls_array, 0, sizeof(current->thread.tls_array));
-        }
-#endif
 }
 
 /*
@@ -753,8 +710,6 @@ exit_thread (void)
         if (current->thread.flags & IA64_THREAD_DBG_VALID)
                 pfm_release_debug_registers(current);
 #endif
-        if (IS_IA32_PROCESS(task_pt_regs(current)))
-                ia32_drop_ia64_partial_page_list(current);
 }
 
 unsigned long
diff --git a/arch/ia64/kernel/ptrace.c b/arch/ia64/kernel/ptrace.c
index 9daa87fdb018..b61afbbe076f 100644
--- a/arch/ia64/kernel/ptrace.c
+++ b/arch/ia64/kernel/ptrace.c
@@ -1250,13 +1250,8 @@ syscall_trace_enter (long arg0, long arg1, long arg2, long arg3,
                 long syscall;
                 int arch;
 
-                if (IS_IA32_PROCESS(&regs)) {
-                        syscall = regs.r1;
-                        arch = AUDIT_ARCH_I386;
-                } else {
-                        syscall = regs.r15;
-                        arch = AUDIT_ARCH_IA64;
-                }
+                syscall = regs.r15;
+                arch = AUDIT_ARCH_IA64;
 
                 audit_syscall_entry(arch, syscall, arg0, arg1, arg2, arg3);
         }
@@ -2172,11 +2167,6 @@ static const struct user_regset_view user_ia64_view = {
 
 const struct user_regset_view *task_user_regset_view(struct task_struct *tsk)
 {
-#ifdef CONFIG_IA32_SUPPORT
-        extern const struct user_regset_view user_ia32_view;
-        if (IS_IA32_PROCESS(task_pt_regs(tsk)))
-                return &user_ia32_view;
-#endif
         return &user_ia64_view;
 }
 
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index a1ea87919777..41ae6a596b50 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -46,7 +46,6 @@
 #include <linux/kexec.h>
 #include <linux/crash_dump.h>
 
-#include <asm/ia32.h>
 #include <asm/machvec.h>
 #include <asm/mca.h>
 #include <asm/meminit.h>
@@ -1016,10 +1015,6 @@ cpu_init (void)
         ia64_mmu_init(ia64_imva(cpu_data));
         ia64_mca_cpu_init(ia64_imva(cpu_data));
 
-#ifdef CONFIG_IA32_SUPPORT
-        ia32_cpu_init();
-#endif
-
         /* Clear ITC to eliminate sched_clock() overflows in human time.  */
         ia64_set_itc(0);
 
diff --git a/arch/ia64/kernel/signal.c b/arch/ia64/kernel/signal.c
index e1821ca4c7df..7bdafc8788bd 100644
--- a/arch/ia64/kernel/signal.c
+++ b/arch/ia64/kernel/signal.c
@@ -21,7 +21,6 @@
 #include <linux/unistd.h>
 #include <linux/wait.h>
 
-#include <asm/ia32.h>
 #include <asm/intrinsics.h>
 #include <asm/uaccess.h>
 #include <asm/rse.h>
@@ -425,14 +424,8 @@ static long
 handle_signal (unsigned long sig, struct k_sigaction *ka, siginfo_t *info, sigset_t *oldset,
                struct sigscratch *scr)
 {
-        if (IS_IA32_PROCESS(&scr->pt)) {
-                /* send signal to IA-32 process */
-                if (!ia32_setup_frame1(sig, ka, info, oldset, &scr->pt))
-                        return 0;
-        } else
-                /* send signal to IA-64 process */
-                if (!setup_frame(sig, ka, info, oldset, scr))
-                        return 0;
+        if (!setup_frame(sig, ka, info, oldset, scr))
+                return 0;
 
         spin_lock_irq(&current->sighand->siglock);
         sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
@@ -462,7 +455,6 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
         siginfo_t info;
         long restart = in_syscall;
         long errno = scr->pt.r8;
-#       define ERR_CODE(c)      (IS_IA32_PROCESS(&scr->pt) ? -(c) : (c))
 
         /*
          * In the ia64_leave_kernel code path, we want the common case to go fast, which
@@ -490,14 +482,7 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
                  * inferior call), thus it's important to check for restarting _after_
                  * get_signal_to_deliver().
                  */
-                if (IS_IA32_PROCESS(&scr->pt)) {
-                        if (in_syscall) {
-                                if (errno >= 0)
-                                        restart = 0;
-                                else
-                                        errno = -errno;
-                        }
-                } else if ((long) scr->pt.r10 != -1)
+                if ((long) scr->pt.r10 != -1)
                         /*
                          * A system calls has to be restarted only if one of the error codes
                          * ERESTARTNOHAND, ERESTARTSYS, or ERESTARTNOINTR is returned.  If r10
@@ -513,22 +498,18 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
                         switch (errno) {
                               case ERESTART_RESTARTBLOCK:
                               case ERESTARTNOHAND:
-                                scr->pt.r8 = ERR_CODE(EINTR);
+                                scr->pt.r8 = EINTR;
                                 /* note: scr->pt.r10 is already -1 */
                                 break;
 
                               case ERESTARTSYS:
                                 if ((ka.sa.sa_flags & SA_RESTART) == 0) {
-                                        scr->pt.r8 = ERR_CODE(EINTR);
+                                        scr->pt.r8 = EINTR;
                                         /* note: scr->pt.r10 is already -1 */
                                         break;
                                 }
                               case ERESTARTNOINTR:
-                                if (IS_IA32_PROCESS(&scr->pt)) {
-                                        scr->pt.r8 = scr->pt.r1;
-                                        scr->pt.cr_iip -= 2;
-                                } else
-                                        ia64_decrement_ip(&scr->pt);
+                                ia64_decrement_ip(&scr->pt);
                                 restart = 0; /* don't restart twice if handle_signal() fails... */
                         }
                 }
@@ -555,21 +536,14 @@ ia64_do_signal (struct sigscratch *scr, long in_syscall)
                 if (errno == ERESTARTNOHAND || errno == ERESTARTSYS || errno == ERESTARTNOINTR
                     || errno == ERESTART_RESTARTBLOCK)
                 {
-                        if (IS_IA32_PROCESS(&scr->pt)) {
-                                scr->pt.r8 = scr->pt.r1;
-                                scr->pt.cr_iip -= 2;
-                                if (errno == ERESTART_RESTARTBLOCK)
-                                        scr->pt.r8 = 0; /* x86 version of __NR_restart_syscall */
-                        } else {
-                                /*
-                                 * Note: the syscall number is in r15 which is saved in
-                                 * pt_regs so all we need to do here is adjust ip so that
-                                 * the "break" instruction gets re-executed.
-                                 */
-                                ia64_decrement_ip(&scr->pt);
-                                if (errno == ERESTART_RESTARTBLOCK)
-                                        scr->pt.r15 = __NR_restart_syscall;
-                        }
+                        /*
+                         * Note: the syscall number is in r15 which is saved in
+                         * pt_regs so all we need to do here is adjust ip so that
+                         * the "break" instruction gets re-executed.
+                         */
+                        ia64_decrement_ip(&scr->pt);
+                        if (errno == ERESTART_RESTARTBLOCK)
+                                scr->pt.r15 = __NR_restart_syscall;
                 }
         }
 
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index de100aa7ff03..e5230b2ff2c5 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -44,7 +44,6 @@
 #include <asm/cache.h>
 #include <asm/current.h>
 #include <asm/delay.h>
-#include <asm/ia32.h>
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/machvec.h>
@@ -443,10 +442,6 @@ smp_callin (void)
                 calibrate_delay();
         local_cpu_data->loops_per_jiffy = loops_per_jiffy;
 
-#ifdef CONFIG_IA32_SUPPORT
-        ia32_gdt_init();
-#endif
-
         /*
          * Allow the master to continue.
          */
diff --git a/arch/ia64/kernel/time.c b/arch/ia64/kernel/time.c
index a35c661e5e89..47a192781b0a 100644
--- a/arch/ia64/kernel/time.c
+++ b/arch/ia64/kernel/time.c
@@ -61,7 +61,7 @@ unsigned long long sched_clock(void)
 
 #ifdef CONFIG_PARAVIRT
 static void
-paravirt_clocksource_resume(void)
+paravirt_clocksource_resume(struct clocksource *cs)
 {
         if (pv_time_ops.clocksource_resume)
                 pv_time_ops.clocksource_resume();
diff --git a/arch/ia64/kernel/traps.c b/arch/ia64/kernel/traps.c
index f0cda765e681..fd80e70018a9 100644
--- a/arch/ia64/kernel/traps.c
+++ b/arch/ia64/kernel/traps.c
@@ -19,7 +19,6 @@
 #include <linux/kdebug.h>
 
 #include <asm/fpswa.h>
-#include <asm/ia32.h>
 #include <asm/intrinsics.h>
 #include <asm/processor.h>
 #include <asm/uaccess.h>
@@ -626,10 +625,6 @@ ia64_fault (unsigned long vector, unsigned long isr, unsigned long ifa,
                 break;
 
               case 45:
-#ifdef CONFIG_IA32_SUPPORT
-                if (ia32_exception(&regs, isr) == 0)
-                        return;
-#endif
                 printk(KERN_ERR "Unexpected IA-32 exception (Trap 45)\n");
                 printk(KERN_ERR "  iip - 0x%lx, ifa - 0x%lx, isr - 0x%lx\n",
                        iip, ifa, isr);
@@ -637,10 +632,6 @@ ia64_fault (unsigned long vector, unsigned long isr, unsigned long ifa,
                 break;
 
               case 46:
-#ifdef CONFIG_IA32_SUPPORT
-                if (ia32_intercept(&regs, isr) == 0)
-                        return;
-#endif
                 printk(KERN_ERR "Unexpected IA-32 intercept trap (Trap 46)\n");
                 printk(KERN_ERR "  iip - 0x%lx, ifa - 0x%lx, isr - 0x%lx, iim - 0x%lx\n",
                        iip, ifa, isr, iim);
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index 7c0d4814a68d..ca3335ea56cc 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -22,7 +22,6 @@
 #include <linux/kexec.h>
 
 #include <asm/dma.h>
-#include <asm/ia32.h>
 #include <asm/io.h>
 #include <asm/machvec.h>
 #include <asm/numa.h>
@@ -668,10 +667,6 @@ mem_init (void)
                         fsyscall_table[i] = sys_call_table[i] | 1;
         }
         setup_gate();
-
-#ifdef CONFIG_IA32_SUPPORT
-        ia32_mem_init();
-#endif
 }
 
 #ifdef CONFIG_MEMORY_HOTPLUG
diff --git a/arch/ia64/uv/kernel/setup.c b/arch/ia64/uv/kernel/setup.c
index 7a5ae633198b..f1490657bafc 100644
--- a/arch/ia64/uv/kernel/setup.c
+++ b/arch/ia64/uv/kernel/setup.c
@@ -104,7 +104,7 @@ void __init uv_setup(char **cmdline_p)
                 uv_cpu_hub_info(cpu)->lowmem_remap_top =
                         lowmem_redir_base + lowmem_redir_size;
                 uv_cpu_hub_info(cpu)->m_val = m_val;
-                uv_cpu_hub_info(cpu)->n_val = m_val;
+                uv_cpu_hub_info(cpu)->n_val = n_val;
                 uv_cpu_hub_info(cpu)->pnode_mask = (1 << n_val) -1;
                 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1;
                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
diff --git a/arch/ia64/xen/hypercall.S b/arch/ia64/xen/hypercall.S
index e32dae444dd6..08847aa12583 100644
--- a/arch/ia64/xen/hypercall.S
+++ b/arch/ia64/xen/hypercall.S
@@ -58,11 +58,6 @@ __HCALL2(xen_ptcga, HYPERPRIVOP_PTC_GA)
 __HCALL2(xen_set_rr, HYPERPRIVOP_SET_RR)
 __HCALL2(xen_set_kr, HYPERPRIVOP_SET_KR)
 
-#ifdef CONFIG_IA32_SUPPORT
-__HCALL0(xen_get_eflag, HYPERPRIVOP_GET_EFLAG)
-__HCALL1(xen_set_eflag, HYPERPRIVOP_SET_EFLAG)  // refer SDM vol1 3.1.8
-#endif /* CONFIG_IA32_SUPPORT */
-
 GLOBAL_ENTRY(xen_set_rr0_to_rr4)
         mov r8=r32
         mov r9=r33
diff --git a/arch/ia64/xen/xen_pv_ops.c b/arch/ia64/xen/xen_pv_ops.c
index 5e2270a999fa..8adc6a14272a 100644
--- a/arch/ia64/xen/xen_pv_ops.c
+++ b/arch/ia64/xen/xen_pv_ops.c
@@ -301,11 +301,6 @@ static void xen_setreg(int regnum, unsigned long val)
         case _IA64_REG_AR_KR0 ... _IA64_REG_AR_KR7:
                 xen_set_kr(regnum - _IA64_REG_AR_KR0, val);
                 break;
-#ifdef CONFIG_IA32_SUPPORT
-        case _IA64_REG_AR_EFLAG:
-                xen_set_eflag(val);
-                break;
-#endif
         case _IA64_REG_AR_ITC:
                 xen_set_itc(val);
                 break;
@@ -332,11 +327,6 @@ static unsigned long xen_getreg(int regnum)
         case _IA64_REG_PSR:
                 res = xen_get_psr();
                 break;
-#ifdef CONFIG_IA32_SUPPORT
-        case _IA64_REG_AR_EFLAG:
-                res = xen_get_eflag();
-                break;
-#endif
         case _IA64_REG_AR_ITC:
                 res = xen_get_itc();
                 break;
@@ -710,9 +700,6 @@ extern unsigned long xen_getreg(int regnum);
 
 __DEFINE_FUNC(getreg,
               __DEFINE_GET_REG(PSR, PSR)
-#ifdef CONFIG_IA32_SUPPORT
-              __DEFINE_GET_REG(AR_EFLAG, EFLAG)
-#endif
 
               /* get_itc */
               "mov r2 = " __stringify(_IA64_REG_AR_ITC) "\n"
@@ -789,9 +776,6 @@ __DEFINE_FUNC(setreg,
               ";;\n"
               "(p6) br.cond.spnt xen_set_itc\n"
 
-#ifdef CONFIG_IA32_SUPPORT
-              __DEFINE_SET_REG(AR_EFLAG, SET_EFLAG)
-#endif
               __DEFINE_SET_REG(CR_TPR, SET_TPR)
               __DEFINE_SET_REG(CR_EOI, EOI)
 
diff --git a/arch/m32r/include/asm/tlbflush.h b/arch/m32r/include/asm/tlbflush.h
index 0ef95307784e..92614b0ccf17 100644
--- a/arch/m32r/include/asm/tlbflush.h
+++ b/arch/m32r/include/asm/tlbflush.h
@@ -92,6 +92,6 @@ static __inline__ void __flush_tlb_all(void)
         );
 }
 
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 #endif  /* _ASM_M32R_TLBFLUSH_H */
diff --git a/arch/m32r/mm/fault-nommu.c b/arch/m32r/mm/fault-nommu.c
index 88469178ea6b..888aab1157ed 100644
--- a/arch/m32r/mm/fault-nommu.c
+++ b/arch/m32r/mm/fault-nommu.c
@@ -95,7 +95,7 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long error_code,
  * update_mmu_cache()
  *======================================================================*/
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
-        pte_t pte)
+        pte_t *ptep)
 {
         BUG();
 }
diff --git a/arch/m32r/mm/fault.c b/arch/m32r/mm/fault.c
index 7274b47f4c22..28ee389e5f5a 100644
--- a/arch/m32r/mm/fault.c
+++ b/arch/m32r/mm/fault.c
@@ -336,7 +336,7 @@ vmalloc_fault:
 
                 addr = (address & PAGE_MASK);
                 set_thread_fault_code(error_code);
-                update_mmu_cache(NULL, addr, *pte_k);
+                update_mmu_cache(NULL, addr, pte_k);
                 set_thread_fault_code(0);
                 return;
         }
@@ -349,7 +349,7 @@ vmalloc_fault:
 #define ITLB_END        (unsigned long *)(ITLB_BASE + (NR_TLB_ENTRIES * 8))
 #define DTLB_END        (unsigned long *)(DTLB_BASE + (NR_TLB_ENTRIES * 8))
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
-        pte_t pte)
+        pte_t *ptep)
 {
         volatile unsigned long *entry1, *entry2;
         unsigned long pte_data, flags;
@@ -365,7 +365,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr,
 
         vaddr = (vaddr & PAGE_MASK) | get_asid();
 
-        pte_data = pte_val(pte);
+        pte_data = pte_val(*ptep);
 
 #ifdef CONFIG_CHIP_OPSP
         entry1 = (unsigned long *)ITLB_BASE;
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index aca0e28581c7..87174c904d2b 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -115,7 +115,7 @@ extern void kernel_set_cachemode(void *addr, unsigned long size, int cmode);
  * they are updated on demand.
  */
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-                                    unsigned long address, pte_t pte)
+                                    unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/microblaze/include/asm/tlbflush.h b/arch/microblaze/include/asm/tlbflush.h
index eb31a0e8a772..10ec70cd8735 100644
--- a/arch/microblaze/include/asm/tlbflush.h
+++ b/arch/microblaze/include/asm/tlbflush.h
@@ -38,7 +38,7 @@ static inline void local_flush_tlb_range(struct vm_area_struct *vma,
 
 #define flush_tlb_kernel_range(start, end)      do { } while (0)
 
-#define update_mmu_cache(vma, addr, pte)        do { } while (0)
+#define update_mmu_cache(vma, addr, ptep)       do { } while (0)
 
 #define flush_tlb_all local_flush_tlb_all
 #define flush_tlb_mm local_flush_tlb_mm
diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h
index 93598ba01355..7e40f3778179 100644
--- a/arch/mips/include/asm/pgtable.h
+++ b/arch/mips/include/asm/pgtable.h
@@ -368,8 +368,9 @@ extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
         pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_tlb(vma, address, pte);
         __update_cache(vma, address, pte);
 }
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index 6dc30fc827c4..16d88577f3e0 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -466,7 +466,7 @@ static inline int set_kernel_exec(unsigned long vaddr, int enable)
  * the kernel page tables containing the necessary information by tlb-mn10300.S
  */
 extern void update_mmu_cache(struct vm_area_struct *vma,
-                             unsigned long address, pte_t pte);
+                             unsigned long address, pte_t *ptep);
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/mn10300/mm/mmu-context.c b/arch/mn10300/mm/mmu-context.c
index 31c9d27a75ae..36ba02191d40 100644
--- a/arch/mn10300/mm/mmu-context.c
+++ b/arch/mn10300/mm/mmu-context.c
@@ -51,9 +51,10 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
 /*
  * preemptively set a TLB entry
  */
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
 {
         unsigned long pteu, ptel, cnx, flags;
+        pte_t pte = *ptep;
 
         addr &= PAGE_MASK;
         ptel = pte_val(pte) & ~(xPTEL_UNUSED1 | xPTEL_UNUSED2);
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index a27d2e200fb2..01c15035e783 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -410,7 +410,7 @@ extern void paging_init (void);
 
 #define PG_dcache_dirty         PG_arch_1
 
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 /* Encode and de-code a swap entry */
 
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c
index b6ed34de14e1..1054baa2fc69 100644
--- a/arch/parisc/kernel/cache.c
+++ b/arch/parisc/kernel/cache.c
@@ -68,9 +68,9 @@ flush_cache_all_local(void)
 EXPORT_SYMBOL(flush_cache_all_local);
 
 void
-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
-        struct page *page = pte_page(pte);
+        struct page *page = pte_page(*ptep);
 
         if (pfn_valid(page_to_pfn(page)) && page_mapping(page) &&
             test_bit(PG_dcache_dirty, &page->flags)) {
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index 21207e54825b..89f158731ce3 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -209,7 +209,7 @@ extern void paging_init(void);
  * corresponding HPTE into the hash table ahead of time, instead of
  * waiting for the inevitable extra hash-table miss exception.
  */
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 extern int gup_hugepd(hugepd_t *hugepd, unsigned pdshift, unsigned long addr,
                       unsigned long end, int write, struct page **pages, int *nr);
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index b9b152558f9c..311224cdb7ad 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -494,13 +494,13 @@ EXPORT_SYMBOL(flush_icache_user_range);
  * This must always be called with the pte lock held.
  */
 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
-                      pte_t pte)
+                      pte_t *ptep)
 {
 #ifdef CONFIG_PPC_STD_MMU
         unsigned long access = 0, trap;
 
         /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
-        if (!pte_young(pte) || address >= TASK_SIZE)
+        if (!pte_young(*ptep) || address >= TASK_SIZE)
                 return;
 
         /* We try to figure out if we are coming from an instruction
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index e2fa79cf0614..9b5b9189c15e 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -43,7 +43,7 @@ extern void vmem_map_init(void);
  * The S390 doesn't have any external MMU info: the kernel page
  * tables contain all the necessary information.
  */
-#define update_mmu_cache(vma, address, pte)     do { } while (0)
+#define update_mmu_cache(vma, address, ptep)     do { } while (0)
 
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
diff --git a/arch/score/include/asm/pgtable.h b/arch/score/include/asm/pgtable.h
index 674934b40170..ccf38f06c57d 100644
--- a/arch/score/include/asm/pgtable.h
+++ b/arch/score/include/asm/pgtable.h
@@ -272,8 +272,9 @@ extern void __update_cache(struct vm_area_struct *vma,
         unsigned long address,  pte_t pte);
 
 static inline void update_mmu_cache(struct vm_area_struct *vma,
-        unsigned long address, pte_t pte)
+        unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_tlb(vma, address, pte);
         __update_cache(vma, address, pte);
 }
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index aab76528abb9..02f77450cd8f 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -153,8 +153,9 @@ extern void __update_tlb(struct vm_area_struct *vma,
                          unsigned long address, pte_t pte);
 
 static inline void
-update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
+        pte_t pte = *ptep;
         __update_cache(vma, address, pte);
         __update_tlb(vma, address, pte);
 }
diff --git a/arch/sh/include/asm/siu.h b/arch/sh/include/asm/siu.h
new file mode 100644
index 000000000000..57565a3b551f
--- /dev/null
+++ b/arch/sh/include/asm/siu.h
@@ -0,0 +1,26 @@
+/*
+ * platform header for the SIU ASoC driver
+ *
+ * Copyright (C) 2009-2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_SIU_H
+#define ASM_SIU_H
+
+#include <asm/dma-sh.h>
+
+struct device;
+
+struct siu_platform {
+        struct device *dma_dev;
+        enum sh_dmae_slave_chan_id dma_slave_tx_a;
+        enum sh_dmae_slave_chan_id dma_slave_rx_a;
+        enum sh_dmae_slave_chan_id dma_slave_tx_b;
+        enum sh_dmae_slave_chan_id dma_slave_rx_b;
+};
+
+#endif /* ASM_SIU_H */
diff --git a/arch/sh/mm/fault_32.c b/arch/sh/mm/fault_32.c
index 28e22839c665..8bf79e3b7bdd 100644
--- a/arch/sh/mm/fault_32.c
+++ b/arch/sh/mm/fault_32.c
@@ -374,7 +374,7 @@ handle_tlbmiss(struct pt_regs *regs, unsigned long writeaccess,
                 local_flush_tlb_one(get_asid(), address & PAGE_MASK);
 #endif
 
-        update_mmu_cache(NULL, address, entry);
+        update_mmu_cache(NULL, address, pte);
 
         return 0;
 }
diff --git a/arch/sparc/include/asm/pgtable_32.h b/arch/sparc/include/asm/pgtable_32.h
index e0cabe790ec1..77f906d8cc21 100644
--- a/arch/sparc/include/asm/pgtable_32.h
+++ b/arch/sparc/include/asm/pgtable_32.h
@@ -330,9 +330,9 @@ BTFIXUPDEF_CALL(void, mmu_info, struct seq_file *)
 #define FAULT_CODE_WRITE    0x2
 #define FAULT_CODE_USER     0x4
 
-BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t)
+BTFIXUPDEF_CALL(void, update_mmu_cache, struct vm_area_struct *, unsigned long, pte_t *)
 
-#define update_mmu_cache(vma,addr,pte) BTFIXUP_CALL(update_mmu_cache)(vma,addr,pte)
+#define update_mmu_cache(vma,addr,ptep) BTFIXUP_CALL(update_mmu_cache)(vma,addr,ptep)
 
 BTFIXUPDEF_CALL(void, sparc_mapiorange, unsigned int, unsigned long,
     unsigned long, unsigned int)
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index f3cb790fa2ae..f5b5fa76c02d 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -706,7 +706,7 @@ extern unsigned long find_ecache_flush_span(unsigned long size);
 #define mmu_unlockarea(vaddr, len)              do { } while(0)
 
 struct vm_area_struct;
-extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
+extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *);
 
 /* Encode and de-code a swap entry */
 #define __swp_type(entry)       (((entry).val >> PAGE_SHIFT) & 0xffUL)
diff --git a/arch/sparc/mm/fault_32.c b/arch/sparc/mm/fault_32.c
index a3413acb8f12..3fa09ba3845f 100644
--- a/arch/sparc/mm/fault_32.c
+++ b/arch/sparc/mm/fault_32.c
@@ -378,7 +378,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write,
                                unsigned long address)
 {
         extern void sun4c_update_mmu_cache(struct vm_area_struct *,
-                                           unsigned long,pte_t);
+                                           unsigned long,pte_t *);
         extern pte_t *sun4c_pte_offset_kernel(pmd_t *,unsigned long);
         struct task_struct *tsk = current;
         struct mm_struct *mm = tsk->mm;
@@ -455,7 +455,7 @@ asmlinkage void do_sun4c_fault(struct pt_regs *regs, int text_fault, int write,
                  *       on the CPU and doing a shrink_mmap() on this vma.
                  */
                 sun4c_update_mmu_cache (find_vma(current->mm, address), address,
-                                        *ptep);
+                                        ptep);
         else
                 do_sparc_fault(regs, text_fault, write, address);
 }
diff --git a/arch/sparc/mm/init_64.c b/arch/sparc/mm/init_64.c
index 1886d37d411b..9245a822a2f1 100644
--- a/arch/sparc/mm/init_64.c
+++ b/arch/sparc/mm/init_64.c
@@ -289,12 +289,13 @@ static void flush_dcache(unsigned long pfn)
         }
 }
 
-void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         struct mm_struct *mm;
         struct tsb *tsb;
         unsigned long tag, flags;
         unsigned long tsb_index, tsb_hash_shift;
+        pte_t pte = *ptep;
 
         if (tlb_type != hypervisor) {
                 unsigned long pfn = pte_pfn(pte);
diff --git a/arch/sparc/mm/nosun4c.c b/arch/sparc/mm/nosun4c.c
index 196263f895b7..4e62c27147c4 100644
--- a/arch/sparc/mm/nosun4c.c
+++ b/arch/sparc/mm/nosun4c.c
@@ -62,7 +62,7 @@ pte_t *sun4c_pte_offset_kernel(pmd_t *dir, unsigned long address)
         return NULL;
 }
 
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
 }
 
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index 367321a030dd..df49b200ca4c 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -694,7 +694,7 @@ extern void tsunami_setup_blockops(void);
  * The following code is a deadwood that may be necessary when
  * we start to make precise page flushes again. --zaitcev
  */
-static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
+static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
 {
 #if 0
         static unsigned long last;
@@ -703,10 +703,10 @@ static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long ad
 
         if (address == last) {
                 val = srmmu_hwprobe(address);
-                if (val != 0 && pte_val(pte) != val) {
+                if (val != 0 && pte_val(*ptep) != val) {
                         printk("swift_update_mmu_cache: "
                             "addr %lx put %08x probed %08x from %p\n",
-                            address, pte_val(pte), val,
+                            address, pte_val(*ptep), val,
                             __builtin_return_address(0));
                         srmmu_flush_whole_tlb();
                 }
diff --git a/arch/sparc/mm/sun4c.c b/arch/sparc/mm/sun4c.c
index a89baf0d875a..18652534b91a 100644
--- a/arch/sparc/mm/sun4c.c
+++ b/arch/sparc/mm/sun4c.c
@@ -1887,7 +1887,7 @@ static void sun4c_check_pgt_cache(int low, int high)
 /* An experiment, turn off by default for now... -DaveM */
 #define SUN4C_PRELOAD_PSEG
 
-void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
+void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 {
         unsigned long flags;
         int pseg;
@@ -1929,7 +1929,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p
                         start += PAGE_SIZE;
                 }
 #ifndef SUN4C_PRELOAD_PSEG
-                sun4c_put_pte(address, pte_val(pte));
+                sun4c_put_pte(address, pte_val(*ptep));
 #endif
                 local_irq_restore(flags);
                 return;
@@ -1940,7 +1940,7 @@ void sun4c_update_mmu_cache(struct vm_area_struct *vma, unsigned long address, p
                 add_lru(entry);
         }
 
-        sun4c_put_pte(address, pte_val(pte));
+        sun4c_put_pte(address, pte_val(*ptep));
         local_irq_restore(flags);
 }
 
diff --git a/arch/um/drivers/ubd_kern.c b/arch/um/drivers/ubd_kern.c
index 5ff554677f40..c1ff6903b622 100644
--- a/arch/um/drivers/ubd_kern.c
+++ b/arch/um/drivers/ubd_kern.c
@@ -747,7 +747,7 @@ static int ubd_open_dev(struct ubd *ubd_dev)
         ubd_dev->fd = fd;
 
         if(ubd_dev->cow.file != NULL){
-                blk_queue_max_sectors(ubd_dev->queue, 8 * sizeof(long));
+                blk_queue_max_hw_sectors(ubd_dev->queue, 8 * sizeof(long));
 
                 err = -ENOMEM;
                 ubd_dev->cow.bitmap = vmalloc(ubd_dev->cow.bitmap_len);
@@ -849,7 +849,7 @@ static int ubd_add(int n, char **error_out)
         }
         ubd_dev->queue->queuedata = ubd_dev;
 
-        blk_queue_max_hw_segments(ubd_dev->queue, MAX_SG);
+        blk_queue_max_segments(ubd_dev->queue, MAX_SG);
         err = ubd_disk_register(UBD_MAJOR, ubd_dev->size, n, &ubd_gendisk[n]);
         if(err){
                 *error_out = "Failed to register device";
diff --git a/arch/um/include/asm/pgtable.h b/arch/um/include/asm/pgtable.h
index 9ce3f165111a..a9f7251b4a8d 100644
--- a/arch/um/include/asm/pgtable.h
+++ b/arch/um/include/asm/pgtable.h
@@ -345,7 +345,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 struct mm_struct;
 extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
 
-#define update_mmu_cache(vma,address,pte) do ; while (0)
+#define update_mmu_cache(vma,address,ptep) do ; while (0)
 
 /* Encode and de-code a swap entry */
 #define __swp_type(x)                   (((x).val >> 4) & 0x3f)
diff --git a/arch/x86/include/asm/pgtable_32.h b/arch/x86/include/asm/pgtable_32.h
index 01fd9461d323..a28668396508 100644
--- a/arch/x86/include/asm/pgtable_32.h
+++ b/arch/x86/include/asm/pgtable_32.h
@@ -80,7 +80,7 @@ do {						\
  * The i386 doesn't have any external MMU info: the kernel page
  * tables contain all the necessary information.
  */
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
 
diff --git a/arch/x86/include/asm/pgtable_64.h b/arch/x86/include/asm/pgtable_64.h
index c57a30117149..181be528c612 100644
--- a/arch/x86/include/asm/pgtable_64.h
+++ b/arch/x86/include/asm/pgtable_64.h
@@ -129,7 +129,7 @@ static inline int pgd_large(pgd_t pgd) { return 0; }
 #define pte_unmap(pte) /* NOP */
 #define pte_unmap_nested(pte) /* NOP */
 
-#define update_mmu_cache(vma, address, pte) do { } while (0)
+#define update_mmu_cache(vma, address, ptep) do { } while (0)
 
 /* Encode and de-code a swap entry */
 #if _PAGE_BIT_FILE < _PAGE_BIT_PROTNONE
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 6e44519960c8..d360b56e9825 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -806,7 +806,7 @@ static int find_psb_table(struct powernow_k8_data *data)
 static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data,
                 unsigned int index)
 {
-        acpi_integer control;
+        u64 control;
 
         if (!data->acpi_data.state_count || (cpu_family == CPU_HW_PSTATE))
                 return;
@@ -824,7 +824,7 @@ static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data)
 {
         struct cpufreq_frequency_table *powernow_table;
         int ret_val = -ENODEV;
-        acpi_integer control, status;
+        u64 control, status;
 
         if (acpi_processor_register_performance(&data->acpi_data, data->cpu)) {
                 dprintk("register performance failed: bad ACPI data\n");
@@ -948,7 +948,7 @@ static int fill_powernow_table_fidvid(struct powernow_k8_data *data,
                 u32 fid;
                 u32 vid;
                 u32 freq, index;
-                acpi_integer status, control;
+                u64 status, control;
 
                 if (data->exttype) {
                         status =  data->acpi_data.states[i].status;
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index ad80a1c718c6..ee4fa1bfcb33 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -266,7 +266,7 @@ static void hpet_resume_device(void)
         force_hpet_resume();
 }
 
-static void hpet_resume_counter(void)
+static void hpet_resume_counter(struct clocksource *cs)
 {
         hpet_resume_device();
         hpet_restart_counter();
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 23066ecf12fa..208a857c679f 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -740,7 +740,7 @@ static cycle_t __vsyscall_fn vread_tsc(void)
 }
 #endif
 
-static void resume_tsc(void)
+static void resume_tsc(struct clocksource *cs)
 {
         clocksource_tsc.cycle_last = 0;
 }
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index a138770c358e..76bf35554117 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -394,7 +394,7 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 #define kern_addr_valid(addr)   (1)
 
 extern  void update_mmu_cache(struct vm_area_struct * vma,
-                              unsigned long address, pte_t pte);
+                              unsigned long address, pte_t *ptep);
 
 /*
  * remap a physical page `pfn' of size `size' with page protection `prot'
diff --git a/arch/xtensa/mm/cache.c b/arch/xtensa/mm/cache.c
index 3ba990c67676..85df4655d326 100644
--- a/arch/xtensa/mm/cache.c
+++ b/arch/xtensa/mm/cache.c
@@ -147,9 +147,9 @@ void flush_cache_page(struct vm_area_struct* vma, unsigned long address,
 #endif
 
 void
-update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t pte)
+update_mmu_cache(struct vm_area_struct * vma, unsigned long addr, pte_t *ptep)
 {
-        unsigned long pfn = pte_pfn(pte);
+        unsigned long pfn = pte_pfn(*ptep);
         struct page *page;
 
         if (!pfn_valid(pfn))