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-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h1
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h13
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h2
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h2
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h21
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h2
6 files changed, 35 insertions, 6 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 753ed810e1c6..e9c65390edd1 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -124,6 +124,7 @@
124#define ANOMALY_05000386 (0) 124#define ANOMALY_05000386 (0)
125#define ANOMALY_05000389 (0) 125#define ANOMALY_05000389 (0)
126#define ANOMALY_05000400 (0) 126#define ANOMALY_05000400 (0)
127#define ANOMALY_05000402 (0)
127#define ANOMALY_05000412 (0) 128#define ANOMALY_05000412 (0)
128#define ANOMALY_05000432 (0) 129#define ANOMALY_05000432 (0)
129#define ANOMALY_05000447 (0) 130#define ANOMALY_05000447 (0)
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index c438ca89d8c9..3f9052687fa8 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file should be up to date with: 9/* This file should be up to date with:
10 * - Revision C, 03/13/2009; ADSP-BF526 Blackfin Processor Anomaly List 10 * - Revision D, 08/14/2009; ADSP-BF526 Blackfin Processor Anomaly List
11 * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List 11 * - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
12 */ 12 */
13 13
@@ -176,7 +176,7 @@
176#define ANOMALY_05000443 (1) 176#define ANOMALY_05000443 (1)
177/* The WURESET Bit in the SYSCR Register is not Functional */ 177/* The WURESET Bit in the SYSCR Register is not Functional */
178#define ANOMALY_05000445 (1) 178#define ANOMALY_05000445 (1)
179/* USB DMA Short Packet Data Corruption */ 179/* USB DMA Mode 1 Short Packet Data Corruption */
180#define ANOMALY_05000450 (1) 180#define ANOMALY_05000450 (1)
181/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */ 181/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
182#define ANOMALY_05000451 (1) 182#define ANOMALY_05000451 (1)
@@ -186,12 +186,20 @@
186#define ANOMALY_05000456 (1) 186#define ANOMALY_05000456 (1)
187/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */ 187/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
188#define ANOMALY_05000457 (1) 188#define ANOMALY_05000457 (1)
189/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
190#define ANOMALY_05000460 (1)
189/* False Hardware Error when RETI Points to Invalid Memory */ 191/* False Hardware Error when RETI Points to Invalid Memory */
190#define ANOMALY_05000461 (1) 192#define ANOMALY_05000461 (1)
193/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
194#define ANOMALY_05000462 (1)
191/* USB Rx DMA hang */ 195/* USB Rx DMA hang */
192#define ANOMALY_05000465 (1) 196#define ANOMALY_05000465 (1)
197/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
198#define ANOMALY_05000466 (1)
193/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 199/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
194#define ANOMALY_05000467 (1) 200#define ANOMALY_05000467 (1)
201/* PLL Latches Incorrect Settings During Reset */
202#define ANOMALY_05000469 (1)
195 203
196/* Anomalies that don't exist on this proc */ 204/* Anomalies that don't exist on this proc */
197#define ANOMALY_05000099 (0) 205#define ANOMALY_05000099 (0)
@@ -238,6 +246,7 @@
238#define ANOMALY_05000362 (1) 246#define ANOMALY_05000362 (1)
239#define ANOMALY_05000363 (0) 247#define ANOMALY_05000363 (0)
240#define ANOMALY_05000400 (0) 248#define ANOMALY_05000400 (0)
249#define ANOMALY_05000402 (0)
241#define ANOMALY_05000412 (0) 250#define ANOMALY_05000412 (0)
242#define ANOMALY_05000447 (0) 251#define ANOMALY_05000447 (0)
243#define ANOMALY_05000448 (0) 252#define ANOMALY_05000448 (0)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index e66aa131f517..f091ad2d8ea8 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -143,7 +143,7 @@
143/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 143/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
144#define ANOMALY_05000371 (1) 144#define ANOMALY_05000371 (1)
145/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 145/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
146#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) 146#define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
147/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 147/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
148#define ANOMALY_05000403 (1) 148#define ANOMALY_05000403 (1)
149/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 149/* Speculative Fetches Can Cause Undesired External FIFO Operations */
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 451cf8a82a42..26b76083e14c 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -113,7 +113,7 @@
113/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */ 113/* GPIO Pins PC1 and PC4 Can Function as Normal Outputs */
114#define ANOMALY_05000375 (__SILICON_REVISION__ < 4) 114#define ANOMALY_05000375 (__SILICON_REVISION__ < 4)
115/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ 115/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
116#define ANOMALY_05000402 (__SILICON_REVISION__ < 4) 116#define ANOMALY_05000402 (__SILICON_REVISION__ == 3)
117/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 117/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
118#define ANOMALY_05000403 (1) 118#define ANOMALY_05000403 (1)
119/* Speculative Fetches Can Cause Undesired External FIFO Operations */ 119/* Speculative Fetches Can Cause Undesired External FIFO Operations */
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index cd040fe0bc5c..52b116ae522a 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -7,7 +7,7 @@
7 */ 7 */
8 8
9/* This file should be up to date with: 9/* This file should be up to date with:
10 * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -162,6 +162,8 @@
162#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 162#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
163/* Incorrect Use of Stack in Lockbox Firmware During Authentication */ 163/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
164#define ANOMALY_05000431 (__SILICON_REVISION__ < 3) 164#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
165/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
166#define ANOMALY_05000434 (1)
165/* OTP Write Accesses Not Supported */ 167/* OTP Write Accesses Not Supported */
166#define ANOMALY_05000442 (__SILICON_REVISION__ < 1) 168#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
167/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 169/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
@@ -176,12 +178,26 @@
176#define ANOMALY_05000449 (__SILICON_REVISION__ == 1) 178#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
177/* USB DMA Mode 1 Short Packet Data Corruption */ 179/* USB DMA Mode 1 Short Packet Data Corruption */
178#define ANOMALY_05000450 (1) 180#define ANOMALY_05000450 (1)
181/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
182#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
179/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */ 183/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
180#define ANOMALY_05000456 (__SILICON_REVISION__ < 3) 184#define ANOMALY_05000456 (1)
185/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
186#define ANOMALY_05000457 (1)
187/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
188#define ANOMALY_05000460 (1)
181/* False Hardware Error when RETI Points to Invalid Memory */ 189/* False Hardware Error when RETI Points to Invalid Memory */
182#define ANOMALY_05000461 (1) 190#define ANOMALY_05000461 (1)
191/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
192#define ANOMALY_05000462 (1)
193/* USB DMA RX Data Corruption */
194#define ANOMALY_05000463 (1)
195/* USB TX DMA Hang */
196#define ANOMALY_05000464 (1)
183/* USB Rx DMA hang */ 197/* USB Rx DMA hang */
184#define ANOMALY_05000465 (1) 198#define ANOMALY_05000465 (1)
199/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
200#define ANOMALY_05000466 (1)
185/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */ 201/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
186#define ANOMALY_05000467 (1) 202#define ANOMALY_05000467 (1)
187 203
@@ -230,6 +246,7 @@
230#define ANOMALY_05000364 (0) 246#define ANOMALY_05000364 (0)
231#define ANOMALY_05000380 (0) 247#define ANOMALY_05000380 (0)
232#define ANOMALY_05000400 (0) 248#define ANOMALY_05000400 (0)
249#define ANOMALY_05000402 (0)
233#define ANOMALY_05000412 (0) 250#define ANOMALY_05000412 (0)
234#define ANOMALY_05000432 (0) 251#define ANOMALY_05000432 (0)
235#define ANOMALY_05000435 (0) 252#define ANOMALY_05000435 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index a5312b2d267e..70da495c9665 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -262,6 +262,8 @@
262#define ANOMALY_05000366 (1) 262#define ANOMALY_05000366 (1)
263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ 263/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
264#define ANOMALY_05000371 (1) 264#define ANOMALY_05000371 (1)
265/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
266#define ANOMALY_05000402 (__SILICON_REVISION__ == 4)
265/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ 267/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
266#define ANOMALY_05000403 (1) 268#define ANOMALY_05000403 (1)
267/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */ 269/* TESTSET Instruction Causes Data Corruption with Writeback Data Cache Enabled */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 00:29:08 -0500