diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 4 | ||||
-rw-r--r-- | arch/arm/mach-mmp/Kconfig | 8 | ||||
-rw-r--r-- | arch/arm/mach-mmp/Makefile | 1 | ||||
-rw-r--r-- | arch/arm/mach-mmp/common.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/cputype.h | 9 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/devices.h | 10 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/irqs.h | 61 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/mfp-pxa910.h | 157 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/pxa910.h | 23 | ||||
-rw-r--r-- | arch/arm/mach-mmp/include/mach/regs-apbc.h | 25 | ||||
-rw-r--r-- | arch/arm/mach-mmp/pxa910.c | 158 | ||||
-rw-r--r-- | arch/arm/plat-pxa/include/plat/mfp.h | 30 |
12 files changed, 485 insertions, 3 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index daf35d778208..cb4486ad0f72 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -488,7 +488,7 @@ config ARCH_PXA | |||
488 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 488 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
489 | 489 | ||
490 | config ARCH_MMP | 490 | config ARCH_MMP |
491 | bool "Marvell PXA168" | 491 | bool "Marvell PXA168/910" |
492 | depends on MMU | 492 | depends on MMU |
493 | select GENERIC_GPIO | 493 | select GENERIC_GPIO |
494 | select ARCH_REQUIRE_GPIOLIB | 494 | select ARCH_REQUIRE_GPIOLIB |
@@ -499,7 +499,7 @@ config ARCH_MMP | |||
499 | select TICK_ONESHOT | 499 | select TICK_ONESHOT |
500 | select PLAT_PXA | 500 | select PLAT_PXA |
501 | help | 501 | help |
502 | Support for Marvell's PXA168 processor line. | 502 | Support for Marvell's PXA168/910 processor line. |
503 | 503 | ||
504 | config ARCH_RPC | 504 | config ARCH_RPC |
505 | bool "RiscPC" | 505 | bool "RiscPC" |
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index b52326763556..ba2e377484f7 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig | |||
@@ -1,6 +1,6 @@ | |||
1 | if ARCH_MMP | 1 | if ARCH_MMP |
2 | 2 | ||
3 | menu "Marvell PXA168 Implmentations" | 3 | menu "Marvell PXA168/910 Implmentations" |
4 | 4 | ||
5 | config MACH_ASPENITE | 5 | config MACH_ASPENITE |
6 | bool "Marvell's PXA168 Aspenite Development Board" | 6 | bool "Marvell's PXA168 Aspenite Development Board" |
@@ -24,4 +24,10 @@ config CPU_PXA168 | |||
24 | help | 24 | help |
25 | Select code specific to PXA168 | 25 | Select code specific to PXA168 |
26 | 26 | ||
27 | config CPU_PXA910 | ||
28 | bool | ||
29 | select CPU_MOHAWK | ||
30 | help | ||
31 | Select code specific to PXA910 | ||
32 | |||
27 | endif | 33 | endif |
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 0ac7644ec99d..93d2bc7459d6 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile | |||
@@ -6,6 +6,7 @@ obj-y += common.o clock.o devices.o irq.o time.o | |||
6 | 6 | ||
7 | # SoC support | 7 | # SoC support |
8 | obj-$(CONFIG_CPU_PXA168) += pxa168.o | 8 | obj-$(CONFIG_CPU_PXA168) += pxa168.o |
9 | obj-$(CONFIG_CPU_PXA910) += pxa910.o | ||
9 | 10 | ||
10 | # board support | 11 | # board support |
11 | obj-$(CONFIG_MACH_ASPENITE) += aspenite.o | 12 | obj-$(CONFIG_MACH_ASPENITE) += aspenite.o |
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index bf7a6a492de6..c33fbbc49417 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h | |||
@@ -5,7 +5,9 @@ struct sys_timer; | |||
5 | extern void timer_init(int irq); | 5 | extern void timer_init(int irq); |
6 | 6 | ||
7 | extern struct sys_timer pxa168_timer; | 7 | extern struct sys_timer pxa168_timer; |
8 | extern struct sys_timer pxa910_timer; | ||
8 | extern void __init pxa168_init_irq(void); | 9 | extern void __init pxa168_init_irq(void); |
10 | extern void __init pxa910_init_irq(void); | ||
9 | 11 | ||
10 | extern void __init icu_init_irq(void); | 12 | extern void __init icu_init_irq(void); |
11 | extern void __init pxa_map_io(void); | 13 | extern void __init pxa_map_io(void); |
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h index 4ceed7a50755..25e797b09083 100644 --- a/arch/arm/mach-mmp/include/mach/cputype.h +++ b/arch/arm/mach-mmp/include/mach/cputype.h | |||
@@ -7,6 +7,7 @@ | |||
7 | * CPU Stepping OLD_ID CPU_ID CHIP_ID | 7 | * CPU Stepping OLD_ID CPU_ID CHIP_ID |
8 | * | 8 | * |
9 | * PXA168 A0 0x41159263 0x56158400 0x00A0A333 | 9 | * PXA168 A0 0x41159263 0x56158400 0x00A0A333 |
10 | * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 | ||
10 | */ | 11 | */ |
11 | 12 | ||
12 | #ifdef CONFIG_CPU_PXA168 | 13 | #ifdef CONFIG_CPU_PXA168 |
@@ -16,6 +17,14 @@ | |||
16 | # define __cpu_is_pxa168(id) (0) | 17 | # define __cpu_is_pxa168(id) (0) |
17 | #endif | 18 | #endif |
18 | 19 | ||
20 | #ifdef CONFIG_CPU_PXA910 | ||
21 | # define __cpu_is_pxa910(id) \ | ||
22 | ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) | ||
23 | #else | ||
24 | # define __cpu_is_pxa910(id) (0) | ||
25 | #endif | ||
26 | |||
19 | #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) | 27 | #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) |
28 | #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) | ||
20 | 29 | ||
21 | #endif /* __ASM_MACH_CPUTYPE_H */ | 30 | #endif /* __ASM_MACH_CPUTYPE_H */ |
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h index bc03388d5fde..24585397217e 100644 --- a/arch/arm/mach-mmp/include/mach/devices.h +++ b/arch/arm/mach-mmp/include/mach/devices.h | |||
@@ -24,4 +24,14 @@ struct pxa_device_desc pxa168_device_##_name __initdata = { \ | |||
24 | .dma = { _dma }, \ | 24 | .dma = { _dma }, \ |
25 | }; | 25 | }; |
26 | 26 | ||
27 | #define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ | ||
28 | struct pxa_device_desc pxa910_device_##_name __initdata = { \ | ||
29 | .dev_name = "pxa910-" #_name, \ | ||
30 | .drv_name = _drv, \ | ||
31 | .id = _id, \ | ||
32 | .irq = IRQ_PXA910_##_irq, \ | ||
33 | .start = _start, \ | ||
34 | .size = _size, \ | ||
35 | .dma = { _dma }, \ | ||
36 | }; | ||
27 | extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); | 37 | extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); |
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h index 91ecb3fbca06..e83e45ebf7a4 100644 --- a/arch/arm/mach-mmp/include/mach/irqs.h +++ b/arch/arm/mach-mmp/include/mach/irqs.h | |||
@@ -49,6 +49,67 @@ | |||
49 | #define IRQ_PXA168_PMU 60 | 49 | #define IRQ_PXA168_PMU 60 |
50 | #define IRQ_PXA168_SM_INT 63 | 50 | #define IRQ_PXA168_SM_INT 63 |
51 | 51 | ||
52 | /* | ||
53 | * Interrupt numbers for PXA910 | ||
54 | */ | ||
55 | #define IRQ_PXA910_AIRQ 0 | ||
56 | #define IRQ_PXA910_SSP3 1 | ||
57 | #define IRQ_PXA910_SSP2 2 | ||
58 | #define IRQ_PXA910_SSP1 3 | ||
59 | #define IRQ_PXA910_PMIC_INT 4 | ||
60 | #define IRQ_PXA910_RTC_INT 5 | ||
61 | #define IRQ_PXA910_RTC_ALARM 6 | ||
62 | #define IRQ_PXA910_TWSI0 7 | ||
63 | #define IRQ_PXA910_GPU 8 | ||
64 | #define IRQ_PXA910_KEYPAD 9 | ||
65 | #define IRQ_PXA910_ROTARY 10 | ||
66 | #define IRQ_PXA910_TRACKBALL 11 | ||
67 | #define IRQ_PXA910_ONEWIRE 12 | ||
68 | #define IRQ_PXA910_AP1_TIMER1 13 | ||
69 | #define IRQ_PXA910_AP1_TIMER2 14 | ||
70 | #define IRQ_PXA910_AP1_TIMER3 15 | ||
71 | #define IRQ_PXA910_IPC_AP0 16 | ||
72 | #define IRQ_PXA910_IPC_AP1 17 | ||
73 | #define IRQ_PXA910_IPC_AP2 18 | ||
74 | #define IRQ_PXA910_IPC_AP3 19 | ||
75 | #define IRQ_PXA910_IPC_AP4 20 | ||
76 | #define IRQ_PXA910_IPC_CP0 21 | ||
77 | #define IRQ_PXA910_IPC_CP1 22 | ||
78 | #define IRQ_PXA910_IPC_CP2 23 | ||
79 | #define IRQ_PXA910_IPC_CP3 24 | ||
80 | #define IRQ_PXA910_IPC_CP4 25 | ||
81 | #define IRQ_PXA910_L2_DDR 26 | ||
82 | #define IRQ_PXA910_UART2 27 | ||
83 | #define IRQ_PXA910_UART3 28 | ||
84 | #define IRQ_PXA910_AP2_TIMER1 29 | ||
85 | #define IRQ_PXA910_AP2_TIMER2 30 | ||
86 | #define IRQ_PXA910_CP2_TIMER1 31 | ||
87 | #define IRQ_PXA910_CP2_TIMER2 32 | ||
88 | #define IRQ_PXA910_CP2_TIMER3 33 | ||
89 | #define IRQ_PXA910_GSSP 34 | ||
90 | #define IRQ_PXA910_CP2_WDT 35 | ||
91 | #define IRQ_PXA910_MAIN_PMU 36 | ||
92 | #define IRQ_PXA910_CP_FREQ_CHG 37 | ||
93 | #define IRQ_PXA910_AP_FREQ_CHG 38 | ||
94 | #define IRQ_PXA910_MMC 39 | ||
95 | #define IRQ_PXA910_AEU 40 | ||
96 | #define IRQ_PXA910_LCD 41 | ||
97 | #define IRQ_PXA910_CCIC 42 | ||
98 | #define IRQ_PXA910_IRE 43 | ||
99 | #define IRQ_PXA910_USB1 44 | ||
100 | #define IRQ_PXA910_NAND 45 | ||
101 | #define IRQ_PXA910_HIFI_DMA 46 | ||
102 | #define IRQ_PXA910_DMA_INT0 47 | ||
103 | #define IRQ_PXA910_DMA_INT1 48 | ||
104 | #define IRQ_PXA910_AP_GPIO 49 | ||
105 | #define IRQ_PXA910_AP2_TIMER3 50 | ||
106 | #define IRQ_PXA910_USB2 51 | ||
107 | #define IRQ_PXA910_TWSI1 54 | ||
108 | #define IRQ_PXA910_CP_GPIO 55 | ||
109 | #define IRQ_PXA910_UART1 59 /* Slow UART */ | ||
110 | #define IRQ_PXA910_AP_PMU 60 | ||
111 | #define IRQ_PXA910_SM_INT 63 /* from PinMux */ | ||
112 | |||
52 | #define IRQ_GPIO_START 64 | 113 | #define IRQ_GPIO_START 64 |
53 | #define IRQ_GPIO_NUM 128 | 114 | #define IRQ_GPIO_NUM 128 |
54 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) | 115 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) |
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h new file mode 100644 index 000000000000..48a1cbc7c56b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h | |||
@@ -0,0 +1,157 @@ | |||
1 | #ifndef __ASM_MACH_MFP_PXA910_H | ||
2 | #define __ASM_MACH_MFP_PXA910_H | ||
3 | |||
4 | #include <mach/mfp.h> | ||
5 | |||
6 | /* UART2 */ | ||
7 | #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) | ||
8 | #define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) | ||
9 | |||
10 | /* UART3 */ | ||
11 | #define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4) | ||
12 | #define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4) | ||
13 | |||
14 | /*IRDA*/ | ||
15 | #define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0) | ||
16 | |||
17 | /* SMC */ | ||
18 | #define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) | ||
19 | #define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) | ||
20 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
21 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
22 | #define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) | ||
23 | #define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) | ||
24 | |||
25 | /* I2C */ | ||
26 | #define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2) | ||
27 | #define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2) | ||
28 | |||
29 | /* SSP1 (I2S) */ | ||
30 | #define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM) | ||
31 | #define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM) | ||
32 | #define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM) | ||
33 | #define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM) | ||
34 | #define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM) | ||
35 | #define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM) | ||
36 | #define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM) | ||
37 | |||
38 | /* DFI */ | ||
39 | #define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0) | ||
40 | #define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0) | ||
41 | #define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0) | ||
42 | #define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0) | ||
43 | #define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0) | ||
44 | #define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0) | ||
45 | #define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0) | ||
46 | #define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0) | ||
47 | #define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0) | ||
48 | #define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0) | ||
49 | #define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0) | ||
50 | #define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0) | ||
51 | #define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0) | ||
52 | #define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0) | ||
53 | #define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0) | ||
54 | #define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0) | ||
55 | #define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0) | ||
56 | #define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1) | ||
57 | #define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0) | ||
58 | #define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1) | ||
59 | #define DF_REn_DF_REn MFP_CFG(DF_REn, AF1) | ||
60 | #define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0) | ||
61 | |||
62 | /*keypad*/ | ||
63 | #define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) | ||
64 | #define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) | ||
65 | #define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) | ||
66 | #define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) | ||
67 | #define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) | ||
68 | #define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) | ||
69 | #define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) | ||
70 | #define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) | ||
71 | #define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) | ||
72 | #define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) | ||
73 | #define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) | ||
74 | #define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) | ||
75 | #define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) | ||
76 | #define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) | ||
77 | #define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) | ||
78 | #define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) | ||
79 | #define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) | ||
80 | #define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) | ||
81 | #define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) | ||
82 | #define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) | ||
83 | |||
84 | /* LCD */ | ||
85 | #define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1) | ||
86 | #define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1) | ||
87 | #define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1) | ||
88 | #define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1) | ||
89 | #define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1) | ||
90 | #define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1) | ||
91 | #define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1) | ||
92 | #define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1) | ||
93 | #define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1) | ||
94 | #define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1) | ||
95 | #define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1) | ||
96 | #define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1) | ||
97 | #define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1) | ||
98 | #define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1) | ||
99 | #define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1) | ||
100 | #define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1) | ||
101 | #define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1) | ||
102 | #define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1) | ||
103 | #define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1) | ||
104 | #define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1) | ||
105 | #define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1) | ||
106 | #define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1) | ||
107 | #define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1) | ||
108 | #define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1) | ||
109 | #define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1) | ||
110 | #define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1) | ||
111 | #define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1) | ||
112 | #define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1) | ||
113 | |||
114 | #define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3) | ||
115 | #define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3) | ||
116 | #define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3) | ||
117 | #define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3) | ||
118 | |||
119 | #define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0) | ||
120 | |||
121 | /*smart panel*/ | ||
122 | #define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0) | ||
123 | #define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0) | ||
124 | #define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0) | ||
125 | |||
126 | /*1wire*/ | ||
127 | #define GPIO106_1WIRE MFP_CFG(GPIO106, AF3) | ||
128 | |||
129 | /*CCIC*/ | ||
130 | #define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM) | ||
131 | #define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM) | ||
132 | #define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM) | ||
133 | #define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM) | ||
134 | #define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM) | ||
135 | #define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM) | ||
136 | #define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM) | ||
137 | #define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM) | ||
138 | #define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM) | ||
139 | #define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM) | ||
140 | #define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM) | ||
141 | #define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM) | ||
142 | |||
143 | /* MMC1 */ | ||
144 | #define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM) | ||
145 | #define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM) | ||
146 | #define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM) | ||
147 | #define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM) | ||
148 | #define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM) | ||
149 | #define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM) | ||
150 | #define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM) | ||
151 | #define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM) | ||
152 | #define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM) | ||
153 | #define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM) | ||
154 | #define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) | ||
155 | #define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) | ||
156 | |||
157 | #endif /* __ASM_MACH MFP_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h new file mode 100644 index 000000000000..b7aeaf574c36 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa910.h | |||
@@ -0,0 +1,23 @@ | |||
1 | #ifndef __ASM_MACH_PXA910_H | ||
2 | #define __ASM_MACH_PXA910_H | ||
3 | |||
4 | #include <mach/devices.h> | ||
5 | |||
6 | extern struct pxa_device_desc pxa910_device_uart1; | ||
7 | extern struct pxa_device_desc pxa910_device_uart2; | ||
8 | |||
9 | static inline int pxa910_add_uart(int id) | ||
10 | { | ||
11 | struct pxa_device_desc *d = NULL; | ||
12 | |||
13 | switch (id) { | ||
14 | case 1: d = &pxa910_device_uart1; break; | ||
15 | case 2: d = &pxa910_device_uart2; break; | ||
16 | } | ||
17 | |||
18 | if (d == NULL) | ||
19 | return -EINVAL; | ||
20 | |||
21 | return pxa_register_device(d, NULL, 0); | ||
22 | } | ||
23 | #endif /* __ASM_MACH_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h index e0ffae594873..c6b8c9dc2026 100644 --- a/arch/arm/mach-mmp/include/mach/regs-apbc.h +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
@@ -42,6 +42,31 @@ | |||
42 | #define APBC_PXA168_UART3 APBC_REG(0x070) | 42 | #define APBC_PXA168_UART3 APBC_REG(0x070) |
43 | #define APBC_PXA168_AC97 APBC_REG(0x084) | 43 | #define APBC_PXA168_AC97 APBC_REG(0x084) |
44 | 44 | ||
45 | /* | ||
46 | * APB Clock register offsets for PXA910 | ||
47 | */ | ||
48 | #define APBC_PXA910_UART0 APBC_REG(0x000) | ||
49 | #define APBC_PXA910_UART1 APBC_REG(0x004) | ||
50 | #define APBC_PXA910_GPIO APBC_REG(0x008) | ||
51 | #define APBC_PXA910_PWM0 APBC_REG(0x00c) | ||
52 | #define APBC_PXA910_PWM1 APBC_REG(0x010) | ||
53 | #define APBC_PXA910_PWM2 APBC_REG(0x014) | ||
54 | #define APBC_PXA910_PWM3 APBC_REG(0x018) | ||
55 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) | ||
56 | #define APBC_PXA910_SSP2 APBC_REG(0x020) | ||
57 | #define APBC_PXA910_IPC APBC_REG(0x024) | ||
58 | #define APBC_PXA910_TWSI0 APBC_REG(0x02c) | ||
59 | #define APBC_PXA910_KPC APBC_REG(0x030) | ||
60 | #define APBC_PXA910_TIMERS APBC_REG(0x034) | ||
61 | #define APBC_PXA910_TBROT APBC_REG(0x038) | ||
62 | #define APBC_PXA910_AIB APBC_REG(0x03c) | ||
63 | #define APBC_PXA910_SW_JTAG APBC_REG(0x040) | ||
64 | #define APBC_PXA910_TIMERS1 APBC_REG(0x044) | ||
65 | #define APBC_PXA910_ONEWIRE APBC_REG(0x048) | ||
66 | #define APBC_PXA910_SSP3 APBC_REG(0x04c) | ||
67 | #define APBC_PXA910_ASFAR APBC_REG(0x050) | ||
68 | #define APBC_PXA910_ASSAR APBC_REG(0x054) | ||
69 | |||
45 | /* Common APB clock register bit definitions */ | 70 | /* Common APB clock register bit definitions */ |
46 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ | 71 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ |
47 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ | 72 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ |
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c new file mode 100644 index 000000000000..453f8f7758bf --- /dev/null +++ b/arch/arm/mach-mmp/pxa910.c | |||
@@ -0,0 +1,158 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-mmp/pxa910.c | ||
3 | * | ||
4 | * Code specific to PXA910 | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/module.h> | ||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/list.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #include <asm/mach/time.h> | ||
18 | #include <mach/addr-map.h> | ||
19 | #include <mach/regs-apbc.h> | ||
20 | #include <mach/regs-apmu.h> | ||
21 | #include <mach/cputype.h> | ||
22 | #include <mach/irqs.h> | ||
23 | #include <mach/gpio.h> | ||
24 | #include <mach/dma.h> | ||
25 | #include <mach/mfp.h> | ||
26 | #include <mach/devices.h> | ||
27 | |||
28 | #include "common.h" | ||
29 | #include "clock.h" | ||
30 | |||
31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | ||
32 | |||
33 | static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = | ||
34 | { | ||
35 | MFP_ADDR_X(GPIO0, GPIO54, 0xdc), | ||
36 | MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), | ||
37 | MFP_ADDR_X(GPIO100, GPIO109, 0x238), | ||
38 | |||
39 | MFP_ADDR(GPIO123, 0xcc), | ||
40 | MFP_ADDR(GPIO124, 0xd0), | ||
41 | |||
42 | MFP_ADDR(DF_IO0, 0x40), | ||
43 | MFP_ADDR(DF_IO1, 0x3c), | ||
44 | MFP_ADDR(DF_IO2, 0x38), | ||
45 | MFP_ADDR(DF_IO3, 0x34), | ||
46 | MFP_ADDR(DF_IO4, 0x30), | ||
47 | MFP_ADDR(DF_IO5, 0x2c), | ||
48 | MFP_ADDR(DF_IO6, 0x28), | ||
49 | MFP_ADDR(DF_IO7, 0x24), | ||
50 | MFP_ADDR(DF_IO8, 0x20), | ||
51 | MFP_ADDR(DF_IO9, 0x1c), | ||
52 | MFP_ADDR(DF_IO10, 0x18), | ||
53 | MFP_ADDR(DF_IO11, 0x14), | ||
54 | MFP_ADDR(DF_IO12, 0x10), | ||
55 | MFP_ADDR(DF_IO13, 0xc), | ||
56 | MFP_ADDR(DF_IO14, 0x8), | ||
57 | MFP_ADDR(DF_IO15, 0x4), | ||
58 | |||
59 | MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), | ||
60 | MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), | ||
61 | MFP_ADDR(SM_nCS0, 0x4c), | ||
62 | MFP_ADDR(SM_nCS1, 0x50), | ||
63 | MFP_ADDR(DF_WEn, 0x54), | ||
64 | MFP_ADDR(DF_REn, 0x58), | ||
65 | MFP_ADDR(DF_CLE_SM_OEn, 0x5c), | ||
66 | MFP_ADDR(DF_ALE_SM_WEn, 0x60), | ||
67 | MFP_ADDR(SM_SCLK, 0x64), | ||
68 | MFP_ADDR(DF_RDY0, 0x68), | ||
69 | MFP_ADDR(SM_BE0, 0x6c), | ||
70 | MFP_ADDR(SM_BE1, 0x70), | ||
71 | MFP_ADDR(SM_ADV, 0x74), | ||
72 | MFP_ADDR(DF_RDY1, 0x78), | ||
73 | MFP_ADDR(SM_ADVMUX, 0x7c), | ||
74 | MFP_ADDR(SM_RDY, 0x80), | ||
75 | |||
76 | MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), | ||
77 | |||
78 | MFP_ADDR_END, | ||
79 | }; | ||
80 | |||
81 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) | ||
82 | |||
83 | static void __init pxa910_init_gpio(void) | ||
84 | { | ||
85 | int i; | ||
86 | |||
87 | /* enable GPIO clock */ | ||
88 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); | ||
89 | |||
90 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | ||
91 | for (i = 0; i < 4; i++) | ||
92 | __raw_writel(0xffffffff, APMASK(i)); | ||
93 | |||
94 | pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); | ||
95 | } | ||
96 | |||
97 | void __init pxa910_init_irq(void) | ||
98 | { | ||
99 | icu_init_irq(); | ||
100 | pxa910_init_gpio(); | ||
101 | } | ||
102 | |||
103 | /* APB peripheral clocks */ | ||
104 | static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); | ||
105 | static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); | ||
106 | |||
107 | /* device and clock bindings */ | ||
108 | static struct clk_lookup pxa910_clkregs[] = { | ||
109 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
110 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
111 | }; | ||
112 | |||
113 | static int __init pxa910_init(void) | ||
114 | { | ||
115 | if (cpu_is_pxa910()) { | ||
116 | mfp_init_base(MFPR_VIRT_BASE); | ||
117 | mfp_init_addr(pxa910_mfp_addr_map); | ||
118 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); | ||
119 | clks_register(ARRAY_AND_SIZE(pxa910_clkregs)); | ||
120 | } | ||
121 | |||
122 | return 0; | ||
123 | } | ||
124 | postcore_initcall(pxa910_init); | ||
125 | |||
126 | /* system timer - clock enabled, 3.25MHz */ | ||
127 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | ||
128 | |||
129 | static void __init pxa910_timer_init(void) | ||
130 | { | ||
131 | /* reset and configure */ | ||
132 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); | ||
133 | __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); | ||
134 | |||
135 | timer_init(IRQ_PXA910_AP1_TIMER1); | ||
136 | } | ||
137 | |||
138 | struct sys_timer pxa910_timer = { | ||
139 | .init = pxa910_timer_init, | ||
140 | }; | ||
141 | |||
142 | /* on-chip devices */ | ||
143 | |||
144 | /* NOTE: there are totally 3 UARTs on PXA910: | ||
145 | * | ||
146 | * UART1 - Slow UART (can be used both by AP and CP) | ||
147 | * UART2/3 - Fast UART | ||
148 | * | ||
149 | * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, | ||
150 | * they are re-ordered as: | ||
151 | * | ||
152 | * pxa910_device_uart1 - UART2 as FFUART | ||
153 | * pxa910_device_uart2 - UART3 as BTUART | ||
154 | * | ||
155 | * UART1 is not used by AP for the moment. | ||
156 | */ | ||
157 | PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); | ||
158 | PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); | ||
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h index a22229cde096..64019464c8db 100644 --- a/arch/arm/plat-pxa/include/plat/mfp.h +++ b/arch/arm/plat-pxa/include/plat/mfp.h | |||
@@ -209,6 +209,36 @@ enum { | |||
209 | MFP_PIN_DF_IO13, | 209 | MFP_PIN_DF_IO13, |
210 | MFP_PIN_DF_IO14, | 210 | MFP_PIN_DF_IO14, |
211 | MFP_PIN_DF_IO15, | 211 | MFP_PIN_DF_IO15, |
212 | MFP_PIN_DF_nCS0_SM_nCS2, | ||
213 | MFP_PIN_DF_nCS1_SM_nCS3, | ||
214 | MFP_PIN_SM_nCS0, | ||
215 | MFP_PIN_SM_nCS1, | ||
216 | MFP_PIN_DF_WEn, | ||
217 | MFP_PIN_DF_REn, | ||
218 | MFP_PIN_DF_CLE_SM_OEn, | ||
219 | MFP_PIN_DF_ALE_SM_WEn, | ||
220 | MFP_PIN_DF_RDY0, | ||
221 | MFP_PIN_DF_RDY1, | ||
222 | |||
223 | MFP_PIN_SM_SCLK, | ||
224 | MFP_PIN_SM_BE0, | ||
225 | MFP_PIN_SM_BE1, | ||
226 | MFP_PIN_SM_ADV, | ||
227 | MFP_PIN_SM_ADVMUX, | ||
228 | MFP_PIN_SM_RDY, | ||
229 | |||
230 | MFP_PIN_MMC1_DAT7, | ||
231 | MFP_PIN_MMC1_DAT6, | ||
232 | MFP_PIN_MMC1_DAT5, | ||
233 | MFP_PIN_MMC1_DAT4, | ||
234 | MFP_PIN_MMC1_DAT3, | ||
235 | MFP_PIN_MMC1_DAT2, | ||
236 | MFP_PIN_MMC1_DAT1, | ||
237 | MFP_PIN_MMC1_DAT0, | ||
238 | MFP_PIN_MMC1_CMD, | ||
239 | MFP_PIN_MMC1_CLK, | ||
240 | MFP_PIN_MMC1_CD, | ||
241 | MFP_PIN_MMC1_WP, | ||
212 | 242 | ||
213 | /* additional pins on PXA930 */ | 243 | /* additional pins on PXA930 */ |
214 | MFP_PIN_GSIM_UIO, | 244 | MFP_PIN_GSIM_UIO, |