diff options
Diffstat (limited to 'arch')
31 files changed, 150 insertions, 131 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e60ec54df334..9d02cdb15b23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -273,6 +273,7 @@ config ARCH_EP93XX | |||
273 | select HAVE_CLK | 273 | select HAVE_CLK |
274 | select COMMON_CLKDEV | 274 | select COMMON_CLKDEV |
275 | select ARCH_REQUIRE_GPIOLIB | 275 | select ARCH_REQUIRE_GPIOLIB |
276 | select ARCH_HAS_HOLES_MEMORYMODEL | ||
276 | help | 277 | help |
277 | This enables support for the Cirrus EP93xx series of CPUs. | 278 | This enables support for the Cirrus EP93xx series of CPUs. |
278 | 279 | ||
@@ -976,10 +977,9 @@ config OABI_COMPAT | |||
976 | UNPREDICTABLE (in fact it can be predicted that it won't work | 977 | UNPREDICTABLE (in fact it can be predicted that it won't work |
977 | at all). If in doubt say Y. | 978 | at all). If in doubt say Y. |
978 | 979 | ||
979 | config ARCH_FLATMEM_HAS_HOLES | 980 | config ARCH_HAS_HOLES_MEMORYMODEL |
980 | bool | 981 | bool |
981 | default y | 982 | default n |
982 | depends on FLATMEM | ||
983 | 983 | ||
984 | # Discontigmem is deprecated | 984 | # Discontigmem is deprecated |
985 | config ARCH_DISCONTIGMEM_ENABLE | 985 | config ARCH_DISCONTIGMEM_ENABLE |
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index c6884ba1d5ed..3e1714c6523f 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -253,9 +253,9 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base) | |||
253 | } | 253 | } |
254 | 254 | ||
255 | #ifdef CONFIG_SMP | 255 | #ifdef CONFIG_SMP |
256 | void gic_raise_softirq(cpumask_t cpumask, unsigned int irq) | 256 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
257 | { | 257 | { |
258 | unsigned long map = *cpus_addr(cpumask); | 258 | unsigned long map = *cpus_addr(*mask); |
259 | 259 | ||
260 | /* this always happens on GIC0 */ | 260 | /* this always happens on GIC0 */ |
261 | writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); | 261 | writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); |
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h index 4924914af188..7f34333bb545 100644 --- a/arch/arm/include/asm/hardware/gic.h +++ b/arch/arm/include/asm/hardware/gic.h | |||
@@ -36,7 +36,7 @@ | |||
36 | void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); | 36 | void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start); |
37 | void gic_cpu_init(unsigned int gic_nr, void __iomem *base); | 37 | void gic_cpu_init(unsigned int gic_nr, void __iomem *base); |
38 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); | 38 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
39 | void gic_raise_softirq(cpumask_t cpumask, unsigned int irq); | 39 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); |
40 | #endif | 40 | #endif |
41 | 41 | ||
42 | #endif | 42 | #endif |
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index fad70da5911d..5995935338e1 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h | |||
@@ -53,17 +53,12 @@ extern void smp_store_cpu_info(unsigned int cpuid); | |||
53 | /* | 53 | /* |
54 | * Raise an IPI cross call on CPUs in callmap. | 54 | * Raise an IPI cross call on CPUs in callmap. |
55 | */ | 55 | */ |
56 | extern void smp_cross_call(cpumask_t callmap); | 56 | extern void smp_cross_call(const struct cpumask *mask); |
57 | |||
58 | /* | ||
59 | * Broadcast a timer interrupt to the other CPUs. | ||
60 | */ | ||
61 | extern void smp_send_timer(void); | ||
62 | 57 | ||
63 | /* | 58 | /* |
64 | * Broadcast a clock event to other CPUs. | 59 | * Broadcast a clock event to other CPUs. |
65 | */ | 60 | */ |
66 | extern void smp_timer_broadcast(cpumask_t mask); | 61 | extern void smp_timer_broadcast(const struct cpumask *mask); |
67 | 62 | ||
68 | /* | 63 | /* |
69 | * Boot a secondary CPU, and assign it the specified idle task. | 64 | * Boot a secondary CPU, and assign it the specified idle task. |
@@ -102,7 +97,8 @@ extern int platform_cpu_kill(unsigned int cpu); | |||
102 | extern void platform_cpu_enable(unsigned int cpu); | 97 | extern void platform_cpu_enable(unsigned int cpu); |
103 | 98 | ||
104 | extern void arch_send_call_function_single_ipi(int cpu); | 99 | extern void arch_send_call_function_single_ipi(int cpu); |
105 | extern void arch_send_call_function_ipi(cpumask_t mask); | 100 | extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
101 | #define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask | ||
106 | 102 | ||
107 | /* | 103 | /* |
108 | * Local timer interrupt handling function (can be IPI'ed). | 104 | * Local timer interrupt handling function (can be IPI'ed). |
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 7801aac3c043..6014dfd22af4 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
@@ -326,14 +326,14 @@ void __init smp_prepare_boot_cpu(void) | |||
326 | per_cpu(cpu_data, cpu).idle = current; | 326 | per_cpu(cpu_data, cpu).idle = current; |
327 | } | 327 | } |
328 | 328 | ||
329 | static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg) | 329 | static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg) |
330 | { | 330 | { |
331 | unsigned long flags; | 331 | unsigned long flags; |
332 | unsigned int cpu; | 332 | unsigned int cpu; |
333 | 333 | ||
334 | local_irq_save(flags); | 334 | local_irq_save(flags); |
335 | 335 | ||
336 | for_each_cpu_mask(cpu, callmap) { | 336 | for_each_cpu(cpu, mask) { |
337 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); | 337 | struct ipi_data *ipi = &per_cpu(ipi_data, cpu); |
338 | 338 | ||
339 | spin_lock(&ipi->lock); | 339 | spin_lock(&ipi->lock); |
@@ -344,19 +344,19 @@ static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg) | |||
344 | /* | 344 | /* |
345 | * Call the platform specific cross-CPU call function. | 345 | * Call the platform specific cross-CPU call function. |
346 | */ | 346 | */ |
347 | smp_cross_call(callmap); | 347 | smp_cross_call(mask); |
348 | 348 | ||
349 | local_irq_restore(flags); | 349 | local_irq_restore(flags); |
350 | } | 350 | } |
351 | 351 | ||
352 | void arch_send_call_function_ipi(cpumask_t mask) | 352 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
353 | { | 353 | { |
354 | send_ipi_message(mask, IPI_CALL_FUNC); | 354 | send_ipi_message(mask, IPI_CALL_FUNC); |
355 | } | 355 | } |
356 | 356 | ||
357 | void arch_send_call_function_single_ipi(int cpu) | 357 | void arch_send_call_function_single_ipi(int cpu) |
358 | { | 358 | { |
359 | send_ipi_message(cpumask_of_cpu(cpu), IPI_CALL_FUNC_SINGLE); | 359 | send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE); |
360 | } | 360 | } |
361 | 361 | ||
362 | void show_ipi_list(struct seq_file *p) | 362 | void show_ipi_list(struct seq_file *p) |
@@ -498,17 +498,10 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs) | |||
498 | 498 | ||
499 | void smp_send_reschedule(int cpu) | 499 | void smp_send_reschedule(int cpu) |
500 | { | 500 | { |
501 | send_ipi_message(cpumask_of_cpu(cpu), IPI_RESCHEDULE); | 501 | send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); |
502 | } | 502 | } |
503 | 503 | ||
504 | void smp_send_timer(void) | 504 | void smp_timer_broadcast(const struct cpumask *mask) |
505 | { | ||
506 | cpumask_t mask = cpu_online_map; | ||
507 | cpu_clear(smp_processor_id(), mask); | ||
508 | send_ipi_message(mask, IPI_TIMER); | ||
509 | } | ||
510 | |||
511 | void smp_timer_broadcast(cpumask_t mask) | ||
512 | { | 505 | { |
513 | send_ipi_message(mask, IPI_TIMER); | 506 | send_ipi_message(mask, IPI_TIMER); |
514 | } | 507 | } |
@@ -517,7 +510,7 @@ void smp_send_stop(void) | |||
517 | { | 510 | { |
518 | cpumask_t mask = cpu_online_map; | 511 | cpumask_t mask = cpu_online_map; |
519 | cpu_clear(smp_processor_id(), mask); | 512 | cpu_clear(smp_processor_id(), mask); |
520 | send_ipi_message(mask, IPI_CPU_STOP); | 513 | send_ipi_message(&mask, IPI_CPU_STOP); |
521 | } | 514 | } |
522 | 515 | ||
523 | /* | 516 | /* |
@@ -528,20 +521,17 @@ int setup_profiling_timer(unsigned int multiplier) | |||
528 | return -EINVAL; | 521 | return -EINVAL; |
529 | } | 522 | } |
530 | 523 | ||
531 | static int | 524 | static void |
532 | on_each_cpu_mask(void (*func)(void *), void *info, int wait, cpumask_t mask) | 525 | on_each_cpu_mask(void (*func)(void *), void *info, int wait, |
526 | const struct cpumask *mask) | ||
533 | { | 527 | { |
534 | int ret = 0; | ||
535 | |||
536 | preempt_disable(); | 528 | preempt_disable(); |
537 | 529 | ||
538 | ret = smp_call_function_mask(mask, func, info, wait); | 530 | smp_call_function_many(mask, func, info, wait); |
539 | if (cpu_isset(smp_processor_id(), mask)) | 531 | if (cpumask_test_cpu(smp_processor_id(), mask)) |
540 | func(info); | 532 | func(info); |
541 | 533 | ||
542 | preempt_enable(); | 534 | preempt_enable(); |
543 | |||
544 | return ret; | ||
545 | } | 535 | } |
546 | 536 | ||
547 | /**********************************************************************/ | 537 | /**********************************************************************/ |
@@ -602,20 +592,17 @@ void flush_tlb_all(void) | |||
602 | 592 | ||
603 | void flush_tlb_mm(struct mm_struct *mm) | 593 | void flush_tlb_mm(struct mm_struct *mm) |
604 | { | 594 | { |
605 | cpumask_t mask = mm->cpu_vm_mask; | 595 | on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask); |
606 | |||
607 | on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mask); | ||
608 | } | 596 | } |
609 | 597 | ||
610 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | 598 | void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) |
611 | { | 599 | { |
612 | cpumask_t mask = vma->vm_mm->cpu_vm_mask; | ||
613 | struct tlb_args ta; | 600 | struct tlb_args ta; |
614 | 601 | ||
615 | ta.ta_vma = vma; | 602 | ta.ta_vma = vma; |
616 | ta.ta_start = uaddr; | 603 | ta.ta_start = uaddr; |
617 | 604 | ||
618 | on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mask); | 605 | on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask); |
619 | } | 606 | } |
620 | 607 | ||
621 | void flush_tlb_kernel_page(unsigned long kaddr) | 608 | void flush_tlb_kernel_page(unsigned long kaddr) |
@@ -630,14 +617,13 @@ void flush_tlb_kernel_page(unsigned long kaddr) | |||
630 | void flush_tlb_range(struct vm_area_struct *vma, | 617 | void flush_tlb_range(struct vm_area_struct *vma, |
631 | unsigned long start, unsigned long end) | 618 | unsigned long start, unsigned long end) |
632 | { | 619 | { |
633 | cpumask_t mask = vma->vm_mm->cpu_vm_mask; | ||
634 | struct tlb_args ta; | 620 | struct tlb_args ta; |
635 | 621 | ||
636 | ta.ta_vma = vma; | 622 | ta.ta_vma = vma; |
637 | ta.ta_start = start; | 623 | ta.ta_start = start; |
638 | ta.ta_end = end; | 624 | ta.ta_end = end; |
639 | 625 | ||
640 | on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mask); | 626 | on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask); |
641 | } | 627 | } |
642 | 628 | ||
643 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | 629 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) |
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index e8ebeaea6c48..b2eede5531c8 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
@@ -21,15 +21,50 @@ | |||
21 | #include <asm/div64.h> | 21 | #include <asm/div64.h> |
22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
23 | 23 | ||
24 | |||
25 | /* | ||
26 | * The EP93xx has two external crystal oscillators. To generate the | ||
27 | * required high-frequency clocks, the processor uses two phase-locked- | ||
28 | * loops (PLLs) to multiply the incoming external clock signal to much | ||
29 | * higher frequencies that are then divided down by programmable dividers | ||
30 | * to produce the needed clocks. The PLLs operate independently of one | ||
31 | * another. | ||
32 | */ | ||
33 | #define EP93XX_EXT_CLK_RATE 14745600 | ||
34 | #define EP93XX_EXT_RTC_RATE 32768 | ||
35 | |||
36 | |||
24 | struct clk { | 37 | struct clk { |
25 | unsigned long rate; | 38 | unsigned long rate; |
26 | int users; | 39 | int users; |
40 | int sw_locked; | ||
27 | u32 enable_reg; | 41 | u32 enable_reg; |
28 | u32 enable_mask; | 42 | u32 enable_mask; |
43 | |||
44 | unsigned long (*get_rate)(struct clk *clk); | ||
29 | }; | 45 | }; |
30 | 46 | ||
31 | static struct clk clk_uart = { | 47 | |
32 | .rate = 14745600, | 48 | static unsigned long get_uart_rate(struct clk *clk); |
49 | |||
50 | |||
51 | static struct clk clk_uart1 = { | ||
52 | .sw_locked = 1, | ||
53 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | ||
54 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U1EN, | ||
55 | .get_rate = get_uart_rate, | ||
56 | }; | ||
57 | static struct clk clk_uart2 = { | ||
58 | .sw_locked = 1, | ||
59 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | ||
60 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U2EN, | ||
61 | .get_rate = get_uart_rate, | ||
62 | }; | ||
63 | static struct clk clk_uart3 = { | ||
64 | .sw_locked = 1, | ||
65 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | ||
66 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U3EN, | ||
67 | .get_rate = get_uart_rate, | ||
33 | }; | 68 | }; |
34 | static struct clk clk_pll1; | 69 | static struct clk clk_pll1; |
35 | static struct clk clk_f; | 70 | static struct clk clk_f; |
@@ -95,9 +130,9 @@ static struct clk clk_m2m1 = { | |||
95 | { .dev_id = dev, .con_id = con, .clk = ck } | 130 | { .dev_id = dev, .con_id = con, .clk = ck } |
96 | 131 | ||
97 | static struct clk_lookup clocks[] = { | 132 | static struct clk_lookup clocks[] = { |
98 | INIT_CK("apb:uart1", NULL, &clk_uart), | 133 | INIT_CK("apb:uart1", NULL, &clk_uart1), |
99 | INIT_CK("apb:uart2", NULL, &clk_uart), | 134 | INIT_CK("apb:uart2", NULL, &clk_uart2), |
100 | INIT_CK("apb:uart3", NULL, &clk_uart), | 135 | INIT_CK("apb:uart3", NULL, &clk_uart3), |
101 | INIT_CK(NULL, "pll1", &clk_pll1), | 136 | INIT_CK(NULL, "pll1", &clk_pll1), |
102 | INIT_CK(NULL, "fclk", &clk_f), | 137 | INIT_CK(NULL, "fclk", &clk_f), |
103 | INIT_CK(NULL, "hclk", &clk_h), | 138 | INIT_CK(NULL, "hclk", &clk_h), |
@@ -125,6 +160,8 @@ int clk_enable(struct clk *clk) | |||
125 | u32 value; | 160 | u32 value; |
126 | 161 | ||
127 | value = __raw_readl(clk->enable_reg); | 162 | value = __raw_readl(clk->enable_reg); |
163 | if (clk->sw_locked) | ||
164 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
128 | __raw_writel(value | clk->enable_mask, clk->enable_reg); | 165 | __raw_writel(value | clk->enable_mask, clk->enable_reg); |
129 | } | 166 | } |
130 | 167 | ||
@@ -138,13 +175,29 @@ void clk_disable(struct clk *clk) | |||
138 | u32 value; | 175 | u32 value; |
139 | 176 | ||
140 | value = __raw_readl(clk->enable_reg); | 177 | value = __raw_readl(clk->enable_reg); |
178 | if (clk->sw_locked) | ||
179 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
141 | __raw_writel(value & ~clk->enable_mask, clk->enable_reg); | 180 | __raw_writel(value & ~clk->enable_mask, clk->enable_reg); |
142 | } | 181 | } |
143 | } | 182 | } |
144 | EXPORT_SYMBOL(clk_disable); | 183 | EXPORT_SYMBOL(clk_disable); |
145 | 184 | ||
185 | static unsigned long get_uart_rate(struct clk *clk) | ||
186 | { | ||
187 | u32 value; | ||
188 | |||
189 | value = __raw_readl(EP93XX_SYSCON_CLOCK_CONTROL); | ||
190 | if (value & EP93XX_SYSCON_CLOCK_UARTBAUD) | ||
191 | return EP93XX_EXT_CLK_RATE; | ||
192 | else | ||
193 | return EP93XX_EXT_CLK_RATE / 2; | ||
194 | } | ||
195 | |||
146 | unsigned long clk_get_rate(struct clk *clk) | 196 | unsigned long clk_get_rate(struct clk *clk) |
147 | { | 197 | { |
198 | if (clk->get_rate) | ||
199 | return clk->get_rate(clk); | ||
200 | |||
148 | return clk->rate; | 201 | return clk->rate; |
149 | } | 202 | } |
150 | EXPORT_SYMBOL(clk_get_rate); | 203 | EXPORT_SYMBOL(clk_get_rate); |
@@ -162,7 +215,7 @@ static unsigned long calc_pll_rate(u32 config_word) | |||
162 | unsigned long long rate; | 215 | unsigned long long rate; |
163 | int i; | 216 | int i; |
164 | 217 | ||
165 | rate = 14745600; | 218 | rate = EP93XX_EXT_CLK_RATE; |
166 | rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ | 219 | rate *= ((config_word >> 11) & 0x1f) + 1; /* X1FBD */ |
167 | rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ | 220 | rate *= ((config_word >> 5) & 0x3f) + 1; /* X2FBD */ |
168 | do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ | 221 | do_div(rate, (config_word & 0x1f) + 1); /* X2IPD */ |
@@ -195,7 +248,7 @@ static int __init ep93xx_clock_init(void) | |||
195 | 248 | ||
196 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); | 249 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1); |
197 | if (!(value & 0x00800000)) { /* PLL1 bypassed? */ | 250 | if (!(value & 0x00800000)) { /* PLL1 bypassed? */ |
198 | clk_pll1.rate = 14745600; | 251 | clk_pll1.rate = EP93XX_EXT_CLK_RATE; |
199 | } else { | 252 | } else { |
200 | clk_pll1.rate = calc_pll_rate(value); | 253 | clk_pll1.rate = calc_pll_rate(value); |
201 | } | 254 | } |
@@ -206,7 +259,7 @@ static int __init ep93xx_clock_init(void) | |||
206 | 259 | ||
207 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); | 260 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); |
208 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ | 261 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ |
209 | clk_pll2.rate = 14745600; | 262 | clk_pll2.rate = EP93XX_EXT_CLK_RATE; |
210 | } else if (value & 0x00040000) { /* PLL2 enabled? */ | 263 | } else if (value & 0x00040000) { /* PLL2 enabled? */ |
211 | clk_pll2.rate = calc_pll_rate(value); | 264 | clk_pll2.rate = calc_pll_rate(value); |
212 | } else { | 265 | } else { |
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index f66be12b856e..1732de7629a5 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | |||
@@ -159,7 +159,10 @@ | |||
159 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) | 159 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) |
160 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) | 160 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) |
161 | #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) | 161 | #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) |
162 | #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE 0x00800000 | 162 | #define EP93XX_SYSCON_DEVICE_CONFIG_U3EN (1<<24) |
163 | #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE (1<<23) | ||
164 | #define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20) | ||
165 | #define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18) | ||
163 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) | 166 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) |
164 | 167 | ||
165 | #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) | 168 | #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) |
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index 6f8872913073..a0f60e55da6a 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -121,7 +121,7 @@ static struct clk uartclk = { | |||
121 | .rate = 14745600, | 121 | .rate = 14745600, |
122 | }; | 122 | }; |
123 | 123 | ||
124 | static struct clk_lookup lookups[] __initdata = { | 124 | static struct clk_lookup lookups[] = { |
125 | { /* UART0 */ | 125 | { /* UART0 */ |
126 | .dev_id = "mb:16", | 126 | .dev_id = "mb:16", |
127 | .clk = &uartclk, | 127 | .clk = &uartclk, |
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h index 2d7722be60ea..e9729a35751d 100644 --- a/arch/arm/mach-l7200/include/mach/sys-clock.h +++ b/arch/arm/mach-l7200/include/mach/sys-clock.h | |||
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | /* IO_START and IO_BASE are defined in hardware.h */ | 19 | /* IO_START and IO_BASE are defined in hardware.h */ |
20 | 20 | ||
21 | #define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF) /* Physical address */ | 21 | #define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF) /* Physical address */ |
22 | #define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */ | 22 | #define SYS_CLOCK_BASE (IO_BASE + SYS_CLOCK_OFF) /* Virtual address */ |
23 | 23 | ||
24 | /* Define the interface to the SYS_CLOCK */ | 24 | /* Define the interface to the SYS_CLOCK */ |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index efc59c49341b..e4cef333e291 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
@@ -103,10 +103,10 @@ static struct omap_clk omap24xx_clks[] = { | |||
103 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | 103 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), |
104 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | 104 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), |
105 | /* DSS domain clocks */ | 105 | /* DSS domain clocks */ |
106 | CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), | 106 | CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X), |
107 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), | 107 | CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X), |
108 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), | 108 | CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X), |
109 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), | 109 | CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), |
110 | /* L3 domain clocks */ | 110 | /* L3 domain clocks */ |
111 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | 111 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), |
112 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | 112 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), |
@@ -206,7 +206,7 @@ static struct omap_clk omap24xx_clks[] = { | |||
206 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | 206 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), |
207 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | 207 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), |
208 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | 208 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), |
209 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), | 209 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), |
210 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | 210 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
211 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | 211 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), |
212 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | 212 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), |
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 0a14dca31e30..ba05aa42bd8e 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
@@ -157,7 +157,7 @@ static struct omap_clk omap34xx_clks[] = { | |||
157 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), | 157 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), |
158 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), | 158 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), |
159 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | 159 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), |
160 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), | 160 | CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X), |
161 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | 161 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), |
162 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | 162 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), |
163 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | 163 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), |
@@ -197,11 +197,11 @@ static struct omap_clk omap34xx_clks[] = { | |||
197 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | 197 | CLK("omap_rng", "ick", &rng_ick, CK_343X), |
198 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | 198 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), |
199 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | 199 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), |
200 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), | 200 | CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X), |
201 | CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), | 201 | CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X), |
202 | CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), | 202 | CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X), |
203 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), | 203 | CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X), |
204 | CLK(NULL, "dss_ick", &dss_ick, CK_343X), | 204 | CLK("omapfb", "ick", &dss_ick, CK_343X), |
205 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | 205 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), |
206 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | 206 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), |
207 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | 207 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index 6763b8f73028..017a30e9aa1d 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
@@ -2182,7 +2182,7 @@ static struct clk wkup_32k_fck = { | |||
2182 | 2182 | ||
2183 | static struct clk gpio1_dbck = { | 2183 | static struct clk gpio1_dbck = { |
2184 | .name = "gpio1_dbck", | 2184 | .name = "gpio1_dbck", |
2185 | .ops = &clkops_omap2_dflt_wait, | 2185 | .ops = &clkops_omap2_dflt, |
2186 | .parent = &wkup_32k_fck, | 2186 | .parent = &wkup_32k_fck, |
2187 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2187 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
2188 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2188 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
@@ -2427,7 +2427,7 @@ static struct clk per_32k_alwon_fck = { | |||
2427 | 2427 | ||
2428 | static struct clk gpio6_dbck = { | 2428 | static struct clk gpio6_dbck = { |
2429 | .name = "gpio6_dbck", | 2429 | .name = "gpio6_dbck", |
2430 | .ops = &clkops_omap2_dflt_wait, | 2430 | .ops = &clkops_omap2_dflt, |
2431 | .parent = &per_32k_alwon_fck, | 2431 | .parent = &per_32k_alwon_fck, |
2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2433 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2433 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
@@ -2437,7 +2437,7 @@ static struct clk gpio6_dbck = { | |||
2437 | 2437 | ||
2438 | static struct clk gpio5_dbck = { | 2438 | static struct clk gpio5_dbck = { |
2439 | .name = "gpio5_dbck", | 2439 | .name = "gpio5_dbck", |
2440 | .ops = &clkops_omap2_dflt_wait, | 2440 | .ops = &clkops_omap2_dflt, |
2441 | .parent = &per_32k_alwon_fck, | 2441 | .parent = &per_32k_alwon_fck, |
2442 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2442 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2443 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2443 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
@@ -2447,7 +2447,7 @@ static struct clk gpio5_dbck = { | |||
2447 | 2447 | ||
2448 | static struct clk gpio4_dbck = { | 2448 | static struct clk gpio4_dbck = { |
2449 | .name = "gpio4_dbck", | 2449 | .name = "gpio4_dbck", |
2450 | .ops = &clkops_omap2_dflt_wait, | 2450 | .ops = &clkops_omap2_dflt, |
2451 | .parent = &per_32k_alwon_fck, | 2451 | .parent = &per_32k_alwon_fck, |
2452 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2452 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2453 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2453 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
@@ -2457,7 +2457,7 @@ static struct clk gpio4_dbck = { | |||
2457 | 2457 | ||
2458 | static struct clk gpio3_dbck = { | 2458 | static struct clk gpio3_dbck = { |
2459 | .name = "gpio3_dbck", | 2459 | .name = "gpio3_dbck", |
2460 | .ops = &clkops_omap2_dflt_wait, | 2460 | .ops = &clkops_omap2_dflt, |
2461 | .parent = &per_32k_alwon_fck, | 2461 | .parent = &per_32k_alwon_fck, |
2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2463 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2463 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
@@ -2467,7 +2467,7 @@ static struct clk gpio3_dbck = { | |||
2467 | 2467 | ||
2468 | static struct clk gpio2_dbck = { | 2468 | static struct clk gpio2_dbck = { |
2469 | .name = "gpio2_dbck", | 2469 | .name = "gpio2_dbck", |
2470 | .ops = &clkops_omap2_dflt_wait, | 2470 | .ops = &clkops_omap2_dflt, |
2471 | .parent = &per_32k_alwon_fck, | 2471 | .parent = &per_32k_alwon_fck, |
2472 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2472 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
2473 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2473 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 496983ade97e..894cc355818a 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
@@ -354,10 +354,12 @@ static void omap_init_mcspi(void) | |||
354 | platform_device_register(&omap2_mcspi1); | 354 | platform_device_register(&omap2_mcspi1); |
355 | platform_device_register(&omap2_mcspi2); | 355 | platform_device_register(&omap2_mcspi2); |
356 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) | 356 | #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) |
357 | platform_device_register(&omap2_mcspi3); | 357 | if (cpu_is_omap2430() || cpu_is_omap343x()) |
358 | platform_device_register(&omap2_mcspi3); | ||
358 | #endif | 359 | #endif |
359 | #ifdef CONFIG_ARCH_OMAP3 | 360 | #ifdef CONFIG_ARCH_OMAP3 |
360 | platform_device_register(&omap2_mcspi4); | 361 | if (cpu_is_omap343x()) |
362 | platform_device_register(&omap2_mcspi4); | ||
361 | #endif | 363 | #endif |
362 | } | 364 | } |
363 | 365 | ||
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index c6a7940f4287..9fd03a2ec95c 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
@@ -409,7 +409,7 @@ | |||
409 | /* PM_PREPWSTST_CAM specific bits */ | 409 | /* PM_PREPWSTST_CAM specific bits */ |
410 | 410 | ||
411 | /* PM_PWSTCTRL_USBHOST specific bits */ | 411 | /* PM_PWSTCTRL_USBHOST specific bits */ |
412 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4) | 412 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 |
413 | 413 | ||
414 | /* RM_RSTST_PER specific bits */ | 414 | /* RM_RSTST_PER specific bits */ |
415 | 415 | ||
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index 8df55f40f4c0..8622c24cd270 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
@@ -187,7 +187,7 @@ int tusb6010_platform_retime(unsigned is_refclk) | |||
187 | unsigned sysclk_ps; | 187 | unsigned sysclk_ps; |
188 | int status; | 188 | int status; |
189 | 189 | ||
190 | if (!refclk_psec || sysclk_ps == 0) | 190 | if (!refclk_psec || fclk_ps == 0) |
191 | return -ENODEV; | 191 | return -ENODEV; |
192 | 192 | ||
193 | sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; | 193 | sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60; |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 0e65344e9f53..dd031cc41847 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
@@ -46,6 +46,7 @@ | |||
46 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
47 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
48 | #include <mach/i2c.h> | 48 | #include <mach/i2c.h> |
49 | #include <mach/regs-uart.h> | ||
49 | #include <mach/viper.h> | 50 | #include <mach/viper.h> |
50 | 51 | ||
51 | #include <asm/setup.h> | 52 | #include <asm/setup.h> |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 942e1a7eb9b2..076acbc50706 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
@@ -750,14 +750,6 @@ void __init realview_timer_init(unsigned int timer_irq) | |||
750 | { | 750 | { |
751 | u32 val; | 751 | u32 val; |
752 | 752 | ||
753 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST | ||
754 | /* | ||
755 | * The dummy clock device has to be registered before the main device | ||
756 | * so that the latter will broadcast the clock events | ||
757 | */ | ||
758 | local_timer_setup(); | ||
759 | #endif | ||
760 | |||
761 | /* | 753 | /* |
762 | * set clock frequency: | 754 | * set clock frequency: |
763 | * REALVIEW_REFCLK is 32KHz | 755 | * REALVIEW_REFCLK is 32KHz |
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h index 515819efd046..dd53892d44a7 100644 --- a/arch/arm/mach-realview/include/mach/smp.h +++ b/arch/arm/mach-realview/include/mach/smp.h | |||
@@ -15,16 +15,9 @@ | |||
15 | /* | 15 | /* |
16 | * We use IRQ1 as the IPI | 16 | * We use IRQ1 as the IPI |
17 | */ | 17 | */ |
18 | static inline void smp_cross_call(cpumask_t callmap) | 18 | static inline void smp_cross_call(const struct cpumask *mask) |
19 | { | ||
20 | gic_raise_softirq(callmap, 1); | ||
21 | } | ||
22 | |||
23 | /* | ||
24 | * Do nothing on MPcore. | ||
25 | */ | ||
26 | static inline void smp_cross_call_done(cpumask_t callmap) | ||
27 | { | 19 | { |
20 | gic_raise_softirq(mask, 1); | ||
28 | } | 21 | } |
29 | 22 | ||
30 | #endif | 23 | #endif |
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c index d0d39adf6407..1c01d13460f0 100644 --- a/arch/arm/mach-realview/localtimer.c +++ b/arch/arm/mach-realview/localtimer.c | |||
@@ -189,8 +189,10 @@ void __cpuinit local_timer_setup(void) | |||
189 | struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); | 189 | struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); |
190 | 190 | ||
191 | clk->name = "dummy_timer"; | 191 | clk->name = "dummy_timer"; |
192 | clk->features = CLOCK_EVT_FEAT_DUMMY; | 192 | clk->features = CLOCK_EVT_FEAT_ONESHOT | |
193 | clk->rating = 200; | 193 | CLOCK_EVT_FEAT_PERIODIC | |
194 | CLOCK_EVT_FEAT_DUMMY; | ||
195 | clk->rating = 400; | ||
194 | clk->mult = 1; | 196 | clk->mult = 1; |
195 | clk->set_mode = dummy_timer_set_mode; | 197 | clk->set_mode = dummy_timer_set_mode; |
196 | clk->broadcast = smp_timer_broadcast; | 198 | clk->broadcast = smp_timer_broadcast; |
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index ea3c75595fa9..30a9c68591f6 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
@@ -78,13 +78,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu) | |||
78 | trace_hardirqs_off(); | 78 | trace_hardirqs_off(); |
79 | 79 | ||
80 | /* | 80 | /* |
81 | * the primary core may have used a "cross call" soft interrupt | ||
82 | * to get this processor out of WFI in the BootMonitor - make | ||
83 | * sure that we are no longer being sent this soft interrupt | ||
84 | */ | ||
85 | smp_cross_call_done(cpumask_of_cpu(cpu)); | ||
86 | |||
87 | /* | ||
88 | * if any interrupts are already enabled for the primary | 81 | * if any interrupts are already enabled for the primary |
89 | * core (e.g. timer irq), then they will not have been enabled | 82 | * core (e.g. timer irq), then they will not have been enabled |
90 | * for us: do so | 83 | * for us: do so |
@@ -136,7 +129,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
136 | * Use smp_cross_call() for this, since there's little | 129 | * Use smp_cross_call() for this, since there's little |
137 | * point duplicating the code here | 130 | * point duplicating the code here |
138 | */ | 131 | */ |
139 | smp_cross_call(cpumask_of_cpu(cpu)); | 132 | smp_cross_call(cpumask_of(cpu)); |
140 | 133 | ||
141 | timeout = jiffies + (1 * HZ); | 134 | timeout = jiffies + (1 * HZ); |
142 | while (time_before(jiffies, timeout)) { | 135 | while (time_before(jiffies, timeout)) { |
@@ -224,11 +217,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
224 | if (max_cpus > ncores) | 217 | if (max_cpus > ncores) |
225 | max_cpus = ncores; | 218 | max_cpus = ncores; |
226 | 219 | ||
227 | #ifdef CONFIG_LOCAL_TIMERS | 220 | #if defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) |
228 | /* | 221 | /* |
229 | * Enable the local timer for primary CPU. If the device is | 222 | * Enable the local timer or broadcast device for the boot CPU. |
230 | * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in | ||
231 | * realview_timer_init | ||
232 | */ | 223 | */ |
233 | local_timer_setup(); | 224 | local_timer_setup(); |
234 | #endif | 225 | #endif |
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c index 4389c160f7d0..8637dea5e150 100644 --- a/arch/arm/mach-s3c2410/mach-bast.c +++ b/arch/arm/mach-s3c2410/mach-bast.c | |||
@@ -588,8 +588,6 @@ static void __init bast_map_io(void) | |||
588 | 588 | ||
589 | s3c_device_nand.dev.platform_data = &bast_nand_info; | 589 | s3c_device_nand.dev.platform_data = &bast_nand_info; |
590 | 590 | ||
591 | s3c_i2c0_set_platdata(&bast_i2c_info); | ||
592 | |||
593 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); | 591 | s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); |
594 | s3c24xx_init_clocks(0); | 592 | s3c24xx_init_clocks(0); |
595 | s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); | 593 | s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs)); |
@@ -602,6 +600,7 @@ static void __init bast_init(void) | |||
602 | sysdev_class_register(&bast_pm_sysclass); | 600 | sysdev_class_register(&bast_pm_sysclass); |
603 | sysdev_register(&bast_pm_sysdev); | 601 | sysdev_register(&bast_pm_sysdev); |
604 | 602 | ||
603 | s3c_i2c0_set_platdata(&bast_i2c_info); | ||
605 | s3c24xx_fb_set_platdata(&bast_fb_info); | 604 | s3c24xx_fb_set_platdata(&bast_fb_info); |
606 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); | 605 | platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); |
607 | 606 | ||
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 1f929c391af7..b3bebcc5623b 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -413,7 +413,7 @@ static struct clk ref24_clk = { | |||
413 | .rate = 24000000, | 413 | .rate = 24000000, |
414 | }; | 414 | }; |
415 | 415 | ||
416 | static struct clk_lookup lookups[] __initdata = { | 416 | static struct clk_lookup lookups[] = { |
417 | { /* UART0 */ | 417 | { /* UART0 */ |
418 | .dev_id = "dev:f1", | 418 | .dev_id = "dev:f1", |
419 | .clk = &ref24_clk, | 419 | .clk = &ref24_clk, |
diff --git a/arch/arm/nwfpe/fpa11.h b/arch/arm/nwfpe/fpa11.h index 386cbd13eaf4..d3a6f9298e9e 100644 --- a/arch/arm/nwfpe/fpa11.h +++ b/arch/arm/nwfpe/fpa11.h | |||
@@ -114,4 +114,8 @@ extern unsigned int SingleCPDO(struct roundingData *roundData, | |||
114 | extern unsigned int DoubleCPDO(struct roundingData *roundData, | 114 | extern unsigned int DoubleCPDO(struct roundingData *roundData, |
115 | const unsigned int opcode, FPREG * rFd); | 115 | const unsigned int opcode, FPREG * rFd); |
116 | 116 | ||
117 | /* extneded_cpdo.c */ | ||
118 | extern unsigned int ExtendedCPDO(struct roundingData *roundData, | ||
119 | const unsigned int opcode, FPREG * rFd); | ||
120 | |||
117 | #endif | 121 | #endif |
diff --git a/arch/arm/nwfpe/fpa11_cprt.c b/arch/arm/nwfpe/fpa11_cprt.c index 9843dc533047..31c4eeec18b0 100644 --- a/arch/arm/nwfpe/fpa11_cprt.c +++ b/arch/arm/nwfpe/fpa11_cprt.c | |||
@@ -27,10 +27,6 @@ | |||
27 | #include "fpmodule.inl" | 27 | #include "fpmodule.inl" |
28 | #include "softfloat.h" | 28 | #include "softfloat.h" |
29 | 29 | ||
30 | #ifdef CONFIG_FPE_NWFPE_XP | ||
31 | extern flag floatx80_is_nan(floatx80); | ||
32 | #endif | ||
33 | |||
34 | unsigned int PerformFLT(const unsigned int opcode); | 30 | unsigned int PerformFLT(const unsigned int opcode); |
35 | unsigned int PerformFIX(const unsigned int opcode); | 31 | unsigned int PerformFIX(const unsigned int opcode); |
36 | 32 | ||
diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h index 260fe29d73f5..13e479c5da57 100644 --- a/arch/arm/nwfpe/softfloat.h +++ b/arch/arm/nwfpe/softfloat.h | |||
@@ -226,6 +226,8 @@ char floatx80_le_quiet( floatx80, floatx80 ); | |||
226 | char floatx80_lt_quiet( floatx80, floatx80 ); | 226 | char floatx80_lt_quiet( floatx80, floatx80 ); |
227 | char floatx80_is_signaling_nan( floatx80 ); | 227 | char floatx80_is_signaling_nan( floatx80 ); |
228 | 228 | ||
229 | extern flag floatx80_is_nan(floatx80); | ||
230 | |||
229 | #endif | 231 | #endif |
230 | 232 | ||
231 | static inline flag extractFloat32Sign(float32 a) | 233 | static inline flag extractFloat32Sign(float32 a) |
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c index ce6b4baeedec..3746222bed10 100644 --- a/arch/arm/plat-omap/fb.c +++ b/arch/arm/plat-omap/fb.c | |||
@@ -206,9 +206,10 @@ void __init omapfb_reserve_sdram(void) | |||
206 | config_invalid = 1; | 206 | config_invalid = 1; |
207 | return; | 207 | return; |
208 | } | 208 | } |
209 | if (rg.paddr) | 209 | if (rg.paddr) { |
210 | reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT); | 210 | reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT); |
211 | reserved += rg.size; | 211 | reserved += rg.size; |
212 | } | ||
212 | omapfb_config.mem_desc.region[i] = rg; | 213 | omapfb_config.mem_desc.region[i] = rg; |
213 | configured_regions++; | 214 | configured_regions++; |
214 | } | 215 | } |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 17d7afe42b83..ee0b21f5b094 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
@@ -307,7 +307,7 @@ static inline int gpio_valid(int gpio) | |||
307 | return 0; | 307 | return 0; |
308 | if (cpu_is_omap24xx() && gpio < 128) | 308 | if (cpu_is_omap24xx() && gpio < 128) |
309 | return 0; | 309 | return 0; |
310 | if (cpu_is_omap34xx() && gpio < 160) | 310 | if (cpu_is_omap34xx() && gpio < 192) |
311 | return 0; | 311 | return 0; |
312 | return -1; | 312 | return -1; |
313 | } | 313 | } |
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c index b6be76e2fe51..4d01ef1a25dd 100644 --- a/arch/arm/plat-s3c/clock.c +++ b/arch/arm/plat-s3c/clock.c | |||
@@ -306,8 +306,6 @@ struct clk s3c24xx_uclk = { | |||
306 | 306 | ||
307 | int s3c24xx_register_clock(struct clk *clk) | 307 | int s3c24xx_register_clock(struct clk *clk) |
308 | { | 308 | { |
309 | clk->owner = THIS_MODULE; | ||
310 | |||
311 | if (clk->enable == NULL) | 309 | if (clk->enable == NULL) |
312 | clk->enable = clk_null_enable; | 310 | clk->enable = clk_null_enable; |
313 | 311 | ||
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c index aee2aeb46c60..07326f632361 100644 --- a/arch/arm/plat-s3c24xx/dma.c +++ b/arch/arm/plat-s3c24xx/dma.c | |||
@@ -1235,7 +1235,7 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d | |||
1235 | 1235 | ||
1236 | EXPORT_SYMBOL(s3c2410_dma_getposition); | 1236 | EXPORT_SYMBOL(s3c2410_dma_getposition); |
1237 | 1237 | ||
1238 | static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev) | 1238 | static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev) |
1239 | { | 1239 | { |
1240 | return container_of(dev, struct s3c2410_dma_chan, dev); | 1240 | return container_of(dev, struct s3c2410_dma_chan, dev); |
1241 | } | 1241 | } |
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c index ee9188add8fb..78ee52cffc9e 100644 --- a/arch/arm/plat-s3c64xx/gpiolib.c +++ b/arch/arm/plat-s3c64xx/gpiolib.c | |||
@@ -57,7 +57,7 @@ | |||
57 | #if 1 | 57 | #if 1 |
58 | #define gpio_dbg(x...) do { } while(0) | 58 | #define gpio_dbg(x...) do { } while(0) |
59 | #else | 59 | #else |
60 | #define gpio_dbg(x...) printk(KERN_DEBUG ## x) | 60 | #define gpio_dbg(x...) printk(KERN_DEBUG x) |
61 | #endif | 61 | #endif |
62 | 62 | ||
63 | /* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where | 63 | /* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where |
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h index 81549516572f..2ba1767512d7 100644 --- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h +++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h | |||
@@ -61,14 +61,14 @@ | |||
61 | #define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) | 61 | #define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28) |
62 | #define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) | 62 | #define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28) |
63 | 63 | ||
64 | #define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32) | 64 | #define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0) |
65 | #define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32) | 65 | #define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0) |
66 | #define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32) | 66 | #define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0) |
67 | #define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32) | 67 | #define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0) |
68 | #define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32) | 68 | #define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0) |
69 | |||
70 | #define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36) | ||
71 | #define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36) | ||
72 | #define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36) | ||
73 | #define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36) | ||
74 | 69 | ||
70 | #define S3C64XX_GPH9_OUTPUT (0x01 << 4) | ||
71 | #define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4) | ||
72 | #define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4) | ||
73 | #define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4) | ||
74 | #define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4) | ||