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-rw-r--r--arch/alpha/kernel/process.c8
-rw-r--r--arch/alpha/kernel/smp.c12
-rw-r--r--arch/arm/configs/at91sam9260ek_defconfig2
-rw-r--r--arch/arm/configs/at91sam9261ek_defconfig2
-rw-r--r--arch/arm/configs/at91sam9263ek_defconfig2
-rw-r--r--arch/arm/configs/at91sam9rlek_defconfig2
-rw-r--r--arch/arm/configs/qil-a9260_defconfig2
-rw-r--r--arch/arm/kernel/elf.c4
-rw-r--r--arch/arm/kernel/machine_kexec.c4
-rw-r--r--arch/arm/kernel/setup.c13
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c107
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c2
-rw-r--r--arch/arm/mach-at91/gpio.c69
-rw-r--r--arch/arm/mach-at91/include/mach/board.h4
-rw-r--r--arch/arm/mach-at91/pm.c1
-rw-r--r--arch/arm/mach-davinci/board-evm.c6
-rw-r--r--arch/arm/mach-davinci/clock.c5
-rw-r--r--arch/arm/mach-davinci/usb.c1
-rw-r--r--arch/arm/mach-ep93xx/include/mach/gesbc9312.h3
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-kirkwood/irq.c2
-rw-r--r--arch/arm/mach-mv78xx0/irq.c2
-rw-r--r--arch/arm/mach-mx1/Kconfig7
-rw-r--r--arch/arm/mach-mx1/Makefile1
-rw-r--r--arch/arm/mach-mx1/clock.c40
-rw-r--r--arch/arm/mach-mx1/devices.c3
-rw-r--r--arch/arm/mach-mx1/mx1ads.c68
-rw-r--r--arch/arm/mach-mx1/scb9328.c160
-rw-r--r--arch/arm/mach-mx2/Kconfig20
-rw-r--r--arch/arm/mach-mx2/Makefile2
-rw-r--r--arch/arm/mach-mx2/Makefile.boot10
-rw-r--r--arch/arm/mach-mx2/clock_imx21.c984
-rw-r--r--arch/arm/mach-mx2/clock_imx27.c1656
-rw-r--r--arch/arm/mach-mx2/cpu_imx27.c4
-rw-r--r--arch/arm/mach-mx2/crm_regs.h313
-rw-r--r--arch/arm/mach-mx2/devices.c196
-rw-r--r--arch/arm/mach-mx2/devices.h8
-rw-r--r--arch/arm/mach-mx2/generic.c1
-rw-r--r--arch/arm/mach-mx2/mx27ads.c19
-rw-r--r--arch/arm/mach-mx2/pcm038.c82
-rw-r--r--arch/arm/mach-mx2/pcm970-baseboard.c133
-rw-r--r--arch/arm/mach-mx2/serial.c3
-rw-r--r--arch/arm/mach-mx3/Kconfig36
-rw-r--r--arch/arm/mach-mx3/Makefile8
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c487
-rw-r--r--arch/arm/mach-mx3/clock.c959
-rw-r--r--arch/arm/mach-mx3/crm_regs.h153
-rw-r--r--arch/arm/mach-mx3/devices.c193
-rw-r--r--arch/arm/mach-mx3/devices.h8
-rw-r--r--arch/arm/mach-mx3/iomux.c88
-rw-r--r--arch/arm/mach-mx3/mm.c37
-rw-r--r--arch/arm/mach-mx3/mx31ads.c328
-rw-r--r--arch/arm/mach-mx3/mx31lite.c13
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c48
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c37
-rw-r--r--arch/arm/mach-mx3/mx31moboard.c74
-rw-r--r--arch/arm/mach-mx3/mx31pdk.c44
-rw-r--r--arch/arm/mach-mx3/pcm037.c138
-rw-r--r--arch/arm/mach-mx3/qong.c312
-rw-r--r--arch/arm/mach-omap2/board-ldp.c2
-rw-r--r--arch/arm/mach-omap2/clock.c16
-rw-r--r--arch/arm/mach-orion5x/irq.c2
-rw-r--r--arch/arm/mach-rpc/riscpc.c6
-rw-r--r--arch/arm/mm/Kconfig3
-rw-r--r--arch/arm/mm/abort-ev6.S3
-rw-r--r--arch/arm/mm/mmu.c3
-rw-r--r--arch/arm/plat-mxc/Kconfig10
-rw-r--r--arch/arm/plat-mxc/Makefile3
-rw-r--r--arch/arm/plat-mxc/clock.c54
-rw-r--r--arch/arm/plat-mxc/cpu.c11
-rw-r--r--arch/arm/plat-mxc/devices.c1
-rw-r--r--arch/arm/plat-mxc/dma-mx1-mx2.c2
-rw-r--r--arch/arm/plat-mxc/gpio.c2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx27ads.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31ads.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/board-mx31moboard.h45
-rw-r--r--arch/arm/plat-mxc/include/mach/board-qong.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/clock.h6
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S3
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/imxfb.h (renamed from arch/arm/mach-imx/include/mach/imxfb.h)3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h416
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx1.h166
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx21.h126
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx27.h207
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx2x.h237
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx3.h74
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux.h127
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h78
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h200
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h200
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h329
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h29
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h290
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h74
-rw-r--r--arch/arm/plat-mxc/iomux-mx1-mx2.c2
-rw-r--r--arch/arm/plat-mxc/pwm.c300
-rw-r--r--arch/arm/plat-mxc/time.c32
-rw-r--r--arch/arm/plat-orion/gpio.c73
-rw-r--r--arch/arm/plat-orion/include/plat/gpio.h3
-rw-r--r--arch/arm/plat-s3c64xx/irq-eint.c2
-rw-r--r--arch/avr32/mach-at32ap/include/mach/board.h1
-rw-r--r--arch/blackfin/Kconfig7
-rw-r--r--arch/blackfin/Kconfig.debug6
-rw-r--r--arch/blackfin/configs/BF518F-EZBRD_defconfig63
-rw-r--r--arch/blackfin/configs/BF527-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF533-STAMP_defconfig4
-rw-r--r--arch/blackfin/configs/BF537-STAMP_defconfig14
-rw-r--r--arch/blackfin/configs/BF538-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BF548-EZKIT_defconfig6
-rw-r--r--arch/blackfin/configs/BF561-EZKIT_defconfig4
-rw-r--r--arch/blackfin/configs/BlackStamp_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF527_defconfig4
-rw-r--r--arch/blackfin/configs/CM-BF548_defconfig6
-rw-r--r--arch/blackfin/configs/IP0X_defconfig2
-rw-r--r--arch/blackfin/configs/SRV1_defconfig4
-rw-r--r--arch/blackfin/include/asm/Kbuild1
-rw-r--r--arch/blackfin/include/asm/bfin_sport.h45
-rw-r--r--arch/blackfin/include/asm/ipipe.h100
-rw-r--r--arch/blackfin/include/asm/ipipe_base.h12
-rw-r--r--arch/blackfin/include/asm/irq.h36
-rw-r--r--arch/blackfin/include/asm/thread_info.h2
-rw-r--r--arch/blackfin/kernel/Makefile8
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c4
-rw-r--r--arch/blackfin/kernel/ipipe.c176
-rw-r--r--arch/blackfin/kernel/irqchip.c14
-rw-r--r--arch/blackfin/kernel/kgdb_test.c9
-rw-r--r--arch/blackfin/kernel/ptrace.c5
-rw-r--r--arch/blackfin/kernel/setup.c10
-rw-r--r--arch/blackfin/kernel/time.c5
-rw-r--r--arch/blackfin/mach-bf518/boards/ezbrd.c33
-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h17
-rw-r--r--arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf527/boards/cm_bf527.c26
-rw-r--r--arch/blackfin/mach-bf527/boards/ezbrd.c24
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf533/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf533/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf533/boards/blackstamp.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/cm_bf533.c24
-rw-r--r--arch/blackfin/mach-bf533/boards/generic_board.c126
-rw-r--r--arch/blackfin/mach-bf533/boards/ip0x.c13
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-bf537/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf537/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537.c26
-rw-r--r--arch/blackfin/mach-bf537/boards/generic_board.c745
-rw-r--r--arch/blackfin/mach-bf537/boards/minotaur.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/pnav10.c24
-rw-r--r--arch/blackfin/mach-bf537/boards/tcm_bf537.c24
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h6
-rw-r--r--arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h4
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h22
-rw-r--r--arch/blackfin/mach-bf548/include/mach/irq.h8
-rw-r--r--arch/blackfin/mach-bf561/boards/Kconfig5
-rw-r--r--arch/blackfin/mach-bf561/boards/Makefile1
-rw-r--r--arch/blackfin/mach-bf561/boards/cm_bf561.c15
-rw-r--r--arch/blackfin/mach-bf561/boards/generic_board.c113
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h7
-rw-r--r--arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h2
-rw-r--r--arch/blackfin/mach-common/arch_checks.c9
-rw-r--r--arch/blackfin/mach-common/cache.S22
-rw-r--r--arch/blackfin/mach-common/clocks-init.c2
-rw-r--r--arch/blackfin/mach-common/dpmc_modes.S24
-rw-r--r--arch/blackfin/mach-common/entry.S61
-rw-r--r--arch/blackfin/mach-common/interrupt.S12
-rw-r--r--arch/blackfin/mach-common/ints-priority.c126
-rw-r--r--arch/blackfin/mach-common/smp.c6
-rw-r--r--arch/blackfin/mm/init.c2
-rw-r--r--arch/frv/mm/dma-alloc.c2
-rw-r--r--arch/ia64/Kconfig18
-rw-r--r--arch/ia64/configs/xen_domu_defconfig1601
-rw-r--r--arch/ia64/include/asm/kvm.h4
-rw-r--r--arch/ia64/include/asm/mmzone.h4
-rw-r--r--arch/ia64/include/asm/sn/bte.h2
-rw-r--r--arch/ia64/kernel/iosapic.c2
-rw-r--r--arch/ia64/kernel/smpboot.c5
-rw-r--r--arch/ia64/kernel/unwind.c2
-rw-r--r--arch/ia64/kvm/kvm-ia64.c4
-rw-r--r--arch/ia64/kvm/process.c17
-rw-r--r--arch/ia64/mm/numa.c4
-rw-r--r--arch/ia64/sn/kernel/bte.c7
-rw-r--r--arch/ia64/sn/kernel/io_acpi_init.c2
-rw-r--r--arch/ia64/sn/kernel/io_init.c2
-rw-r--r--arch/ia64/sn/pci/pcibr/pcibr_dma.c7
-rw-r--r--arch/ia64/xen/Kconfig3
-rw-r--r--arch/ia64/xen/xen_pv_ops.c4
-rw-r--r--arch/m68k/atari/ataints.c16
-rw-r--r--arch/m68k/atari/atakeyb.c4
-rw-r--r--arch/m68k/atari/config.c2
-rw-r--r--arch/m68k/atari/debug.c22
-rw-r--r--arch/m68k/atari/time.c8
-rw-r--r--arch/m68k/include/asm/atarihw.h4
-rw-r--r--arch/m68k/include/asm/atariints.h6
-rw-r--r--arch/m68knommu/platform/5206e/config.c1
-rw-r--r--arch/m68knommu/platform/528x/config.c228
-rw-r--r--arch/mips/Kconfig9
-rw-r--r--arch/mips/alchemy/common/time.c6
-rw-r--r--arch/mips/include/asm/compat.h7
-rw-r--r--arch/mips/include/asm/seccomp.h1
-rw-r--r--arch/mips/include/asm/spinlock.h1
-rw-r--r--arch/mips/kernel/irq.c1
-rw-r--r--arch/mips/kernel/linux32.c69
-rw-r--r--arch/mips/kernel/scall32-o32.S4
-rw-r--r--arch/mips/kernel/scall64-64.S2
-rw-r--r--arch/mips/kernel/scall64-n32.S28
-rw-r--r--arch/mips/kernel/scall64-o32.S40
-rw-r--r--arch/mips/kernel/signal.c5
-rw-r--r--arch/mips/kernel/signal32.c28
-rw-r--r--arch/mips/kernel/syscall.c26
-rw-r--r--arch/mips/mm/cache.c5
-rw-r--r--arch/mn10300/Kconfig1
-rw-r--r--arch/mn10300/unit-asb2305/pci.c2
-rw-r--r--arch/powerpc/boot/dts/mpc8313erdb.dts11
-rw-r--r--arch/powerpc/configs/83xx/mpc8313_rdb_defconfig2
-rw-r--r--arch/powerpc/include/asm/compat.h5
-rw-r--r--arch/powerpc/include/asm/pgtable-4k.h2
-rw-r--r--arch/powerpc/include/asm/pgtable-64k.h2
-rw-r--r--arch/powerpc/include/asm/pgtable-ppc32.h3
-rw-r--r--arch/powerpc/include/asm/seccomp.h4
-rw-r--r--arch/powerpc/kernel/align.c36
-rw-r--r--arch/powerpc/kernel/ftrace.c5
-rw-r--r--arch/powerpc/kernel/pci-common.c17
-rw-r--r--arch/powerpc/kvm/powerpc.c4
-rw-r--r--arch/powerpc/lib/copyuser_64.S38
-rw-r--r--arch/powerpc/lib/memcpy_64.S26
-rw-r--r--arch/powerpc/lib/sstep.c2
-rw-r--r--arch/powerpc/mm/fsl_booke_mmu.c4
-rw-r--r--arch/powerpc/mm/hash_low_32.S2
-rw-r--r--arch/powerpc/mm/numa.c5
-rw-r--r--arch/powerpc/mm/pgtable_32.c4
-rw-r--r--arch/powerpc/oprofile/cell/spu_profiler.c1
-rw-r--r--arch/powerpc/platforms/82xx/pq2ads-pci-pic.c2
-rw-r--r--arch/powerpc/platforms/86xx/gef_sbc610.c4
-rw-r--r--arch/powerpc/platforms/ps3/mm.c2
-rw-r--r--arch/powerpc/platforms/pseries/hotplug-memory.c1
-rw-r--r--arch/powerpc/sysdev/cpm2_pic.c2
-rw-r--r--arch/powerpc/sysdev/ipic.c2
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.c17
-rw-r--r--arch/s390/crypto/aes_s390.c2
-rw-r--r--arch/s390/defconfig87
-rw-r--r--arch/s390/include/asm/cputime.h2
-rw-r--r--arch/s390/include/asm/lowcore.h4
-rw-r--r--arch/s390/include/asm/setup.h2
-rw-r--r--arch/s390/kernel/irq.c2
-rw-r--r--arch/s390/kernel/setup.c9
-rw-r--r--arch/s390/kvm/kvm-s390.c4
-rw-r--r--arch/sh/boards/board-ap325rxa.c54
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c4
-rw-r--r--arch/sparc/include/asm/compat.h5
-rw-r--r--arch/sparc/include/asm/seccomp.h6
-rw-r--r--arch/sparc/kernel/chmc.c1
-rw-r--r--arch/sparc/kernel/head_64.S31
-rw-r--r--arch/sparc/kernel/nmi.c1
-rw-r--r--arch/sparc/kernel/pcr.c7
-rw-r--r--arch/sparc/lib/GENbzero.S6
-rw-r--r--arch/sparc/lib/GENcopy_from_user.S8
-rw-r--r--arch/sparc/lib/GENcopy_to_user.S8
-rw-r--r--arch/sparc/lib/NG2copy_from_user.S9
-rw-r--r--arch/sparc/lib/NG2copy_to_user.S9
-rw-r--r--arch/sparc/lib/NGbzero.S6
-rw-r--r--arch/sparc/lib/NGcopy_from_user.S9
-rw-r--r--arch/sparc/lib/NGcopy_to_user.S9
-rw-r--r--arch/sparc/lib/U1copy_from_user.S8
-rw-r--r--arch/sparc/lib/U1copy_to_user.S8
-rw-r--r--arch/sparc/lib/U3copy_from_user.S6
-rw-r--r--arch/sparc/lib/U3copy_to_user.S8
-rw-r--r--arch/sparc/lib/bzero.S6
-rw-r--r--arch/sparc/lib/copy_in_user.S61
-rw-r--r--arch/um/drivers/vde_user.c6
-rw-r--r--arch/x86/Kconfig11
-rw-r--r--arch/x86/Kconfig.cpu28
-rw-r--r--arch/x86/Kconfig.debug24
-rw-r--r--arch/x86/include/asm/a.out-core.h4
-rw-r--r--arch/x86/include/asm/cpufeature.h1
-rw-r--r--arch/x86/include/asm/efi.h2
-rw-r--r--arch/x86/include/asm/fixmap_64.h4
-rw-r--r--arch/x86/include/asm/i387.h8
-rw-r--r--arch/x86/include/asm/iomap.h3
-rw-r--r--arch/x86/include/asm/kvm.h7
-rw-r--r--arch/x86/include/asm/math_emu.h29
-rw-r--r--arch/x86/include/asm/mmzone_32.h2
-rw-r--r--arch/x86/include/asm/mmzone_64.h2
-rw-r--r--arch/x86/include/asm/mpspec.h6
-rw-r--r--arch/x86/include/asm/page.h1
-rw-r--r--arch/x86/include/asm/paravirt.h18
-rw-r--r--arch/x86/include/asm/pgtable.h26
-rw-r--r--arch/x86/include/asm/processor.h2
-rw-r--r--arch/x86/include/asm/seccomp_32.h6
-rw-r--r--arch/x86/include/asm/seccomp_64.h8
-rw-r--r--arch/x86/include/asm/spinlock.h1
-rw-r--r--arch/x86/include/asm/traps.h4
-rw-r--r--arch/x86/include/asm/xen/page.h2
-rw-r--r--arch/x86/kernel/acpi/boot.c23
-rw-r--r--arch/x86/kernel/acpi/sleep.c4
-rw-r--r--arch/x86/kernel/acpi/wakeup_64.S30
-rw-r--r--arch/x86/kernel/apic.c2
-rw-r--r--arch/x86/kernel/apm_32.c4
-rw-r--r--arch/x86/kernel/cpu/cpufreq/Kconfig11
-rw-r--r--arch/x86/kernel/cpu/cpufreq/p4-clockmod.c1
-rw-r--r--arch/x86/kernel/cpu/cpufreq/powernow-k8.c40
-rw-r--r--arch/x86/kernel/cpu/intel.c3
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_64.c7
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_amd_64.c2
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce_intel_64.c4
-rw-r--r--arch/x86/kernel/ds.c3
-rw-r--r--arch/x86/kernel/efi.c7
-rw-r--r--arch/x86/kernel/efi_64.c21
-rw-r--r--arch/x86/kernel/ftrace.c17
-rw-r--r--arch/x86/kernel/hpet.c14
-rw-r--r--arch/x86/kernel/i387.c2
-rw-r--r--arch/x86/kernel/i8237.c17
-rw-r--r--arch/x86/kernel/io_apic.c20
-rw-r--r--arch/x86/kernel/olpc.c2
-rw-r--r--arch/x86/kernel/paravirt.c26
-rw-r--r--arch/x86/kernel/process.c6
-rw-r--r--arch/x86/kernel/process_32.c3
-rw-r--r--arch/x86/kernel/process_64.c9
-rw-r--r--arch/x86/kernel/ptrace.c18
-rw-r--r--arch/x86/kernel/reboot.c8
-rw-r--r--arch/x86/kernel/setup.c7
-rw-r--r--arch/x86/kernel/time_64.c2
-rw-r--r--arch/x86/kernel/traps.c25
-rw-r--r--arch/x86/kernel/vmi_32.c11
-rw-r--r--arch/x86/kernel/vmiclock_32.c7
-rw-r--r--arch/x86/kvm/i8254.c2
-rw-r--r--arch/x86/kvm/irq.c7
-rw-r--r--arch/x86/kvm/irq.h1
-rw-r--r--arch/x86/kvm/lapic.c66
-rw-r--r--arch/x86/kvm/lapic.h2
-rw-r--r--arch/x86/kvm/mmu.c9
-rw-r--r--arch/x86/kvm/svm.c1
-rw-r--r--arch/x86/kvm/vmx.c5
-rw-r--r--arch/x86/kvm/x86.c10
-rw-r--r--arch/x86/lguest/boot.c21
-rw-r--r--arch/x86/mach-default/setup.c2
-rw-r--r--arch/x86/mach-voyager/setup.c2
-rw-r--r--arch/x86/mach-voyager/voyager_smp.c24
-rw-r--r--arch/x86/math-emu/fpu_aux.c31
-rw-r--r--arch/x86/math-emu/fpu_entry.c6
-rw-r--r--arch/x86/math-emu/fpu_proto.h4
-rw-r--r--arch/x86/math-emu/fpu_system.h16
-rw-r--r--arch/x86/math-emu/get_address.c69
-rw-r--r--arch/x86/mm/init_64.c2
-rw-r--r--arch/x86/mm/iomap_32.c11
-rw-r--r--arch/x86/mm/ioremap.c19
-rw-r--r--arch/x86/mm/kmmio.c164
-rw-r--r--arch/x86/mm/numa_64.c2
-rw-r--r--arch/x86/mm/pageattr.c30
-rw-r--r--arch/x86/mm/pat.c85
-rw-r--r--arch/x86/mm/testmmiotrace.c70
-rw-r--r--arch/x86/oprofile/op_model_ppro.c14
-rw-r--r--arch/x86/xen/enlighten.c3
-rw-r--r--arch/xtensa/Kconfig3
-rw-r--r--arch/xtensa/kernel/setup.c2
-rw-r--r--arch/xtensa/kernel/traps.c1
-rw-r--r--arch/xtensa/mm/fault.c1
-rw-r--r--arch/xtensa/platforms/iss/console.c6
370 files changed, 9924 insertions, 6468 deletions
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index f238370c907d..8d0097f10208 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -93,8 +93,8 @@ common_shutdown_1(void *generic_ptr)
93 if (cpuid != boot_cpuid) { 93 if (cpuid != boot_cpuid) {
94 flags |= 0x00040000UL; /* "remain halted" */ 94 flags |= 0x00040000UL; /* "remain halted" */
95 *pflags = flags; 95 *pflags = flags;
96 cpu_clear(cpuid, cpu_present_map); 96 set_cpu_present(cpuid, false);
97 cpu_clear(cpuid, cpu_possible_map); 97 set_cpu_possible(cpuid, false);
98 halt(); 98 halt();
99 } 99 }
100#endif 100#endif
@@ -120,8 +120,8 @@ common_shutdown_1(void *generic_ptr)
120 120
121#ifdef CONFIG_SMP 121#ifdef CONFIG_SMP
122 /* Wait for the secondaries to halt. */ 122 /* Wait for the secondaries to halt. */
123 cpu_clear(boot_cpuid, cpu_present_map); 123 set_cpu_present(boot_cpuid, false);
124 cpu_clear(boot_cpuid, cpu_possible_map); 124 set_cpu_possible(boot_cpuid, false);
125 while (cpus_weight(cpu_present_map)) 125 while (cpus_weight(cpu_present_map))
126 barrier(); 126 barrier();
127#endif 127#endif
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 00f1dc3dfd5f..b1fe5674c3a1 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -120,12 +120,12 @@ void __cpuinit
120smp_callin(void) 120smp_callin(void)
121{ 121{
122 int cpuid = hard_smp_processor_id(); 122 int cpuid = hard_smp_processor_id();
123 cpumask_t mask = cpu_online_map;
124 123
125 if (cpu_test_and_set(cpuid, mask)) { 124 if (cpu_online(cpuid)) {
126 printk("??, cpu 0x%x already present??\n", cpuid); 125 printk("??, cpu 0x%x already present??\n", cpuid);
127 BUG(); 126 BUG();
128 } 127 }
128 set_cpu_online(cpuid, true);
129 129
130 /* Turn on machine checks. */ 130 /* Turn on machine checks. */
131 wrmces(7); 131 wrmces(7);
@@ -436,8 +436,8 @@ setup_smp(void)
436 ((char *)cpubase + i*hwrpb->processor_size); 436 ((char *)cpubase + i*hwrpb->processor_size);
437 if ((cpu->flags & 0x1cc) == 0x1cc) { 437 if ((cpu->flags & 0x1cc) == 0x1cc) {
438 smp_num_probed++; 438 smp_num_probed++;
439 cpu_set(i, cpu_possible_map); 439 set_cpu_possible(i, true);
440 cpu_set(i, cpu_present_map); 440 set_cpu_present(i, true);
441 cpu->pal_revision = boot_cpu_palrev; 441 cpu->pal_revision = boot_cpu_palrev;
442 } 442 }
443 443
@@ -470,8 +470,8 @@ smp_prepare_cpus(unsigned int max_cpus)
470 470
471 /* Nothing to do on a UP box, or when told not to. */ 471 /* Nothing to do on a UP box, or when told not to. */
472 if (smp_num_probed == 1 || max_cpus == 0) { 472 if (smp_num_probed == 1 || max_cpus == 0) {
473 cpu_possible_map = cpumask_of_cpu(boot_cpuid); 473 init_cpu_possible(cpumask_of(boot_cpuid));
474 cpu_present_map = cpumask_of_cpu(boot_cpuid); 474 init_cpu_present(cpumask_of(boot_cpuid));
475 printk(KERN_INFO "SMP mode deactivated.\n"); 475 printk(KERN_INFO "SMP mode deactivated.\n");
476 return; 476 return;
477 } 477 }
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index e0ee7060f9aa..98e2f3de4bc5 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -608,7 +608,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
608# Watchdog Device Drivers 608# Watchdog Device Drivers
609# 609#
610# CONFIG_SOFT_WATCHDOG is not set 610# CONFIG_SOFT_WATCHDOG is not set
611CONFIG_AT91SAM9_WATCHDOG=y 611CONFIG_AT91SAM9X_WATCHDOG=y
612 612
613# 613#
614# USB-based Watchdog Cards 614# USB-based Watchdog Cards
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index 01d1ef97d8be..149456142392 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -700,7 +700,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
700# Watchdog Device Drivers 700# Watchdog Device Drivers
701# 701#
702# CONFIG_SOFT_WATCHDOG is not set 702# CONFIG_SOFT_WATCHDOG is not set
703CONFIG_AT91SAM9_WATCHDOG=y 703CONFIG_AT91SAM9X_WATCHDOG=y
704 704
705# 705#
706# USB-based Watchdog Cards 706# USB-based Watchdog Cards
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index 036a126725c1..21599f3c6275 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -710,7 +710,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
710# Watchdog Device Drivers 710# Watchdog Device Drivers
711# 711#
712# CONFIG_SOFT_WATCHDOG is not set 712# CONFIG_SOFT_WATCHDOG is not set
713CONFIG_AT91SAM9_WATCHDOG=y 713CONFIG_AT91SAM9X_WATCHDOG=y
714 714
715# 715#
716# USB-based Watchdog Cards 716# USB-based Watchdog Cards
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index 237a2a6a8517..e2df81a3e804 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -606,7 +606,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
606# Watchdog Device Drivers 606# Watchdog Device Drivers
607# 607#
608# CONFIG_SOFT_WATCHDOG is not set 608# CONFIG_SOFT_WATCHDOG is not set
609CONFIG_AT91SAM9_WATCHDOG=y 609CONFIG_AT91SAM9X_WATCHDOG=y
610 610
611# 611#
612# Sonics Silicon Backplane 612# Sonics Silicon Backplane
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
index cd1d717903ac..9b32d0eb89ba 100644
--- a/arch/arm/configs/qil-a9260_defconfig
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -727,7 +727,7 @@ CONFIG_WATCHDOG_NOWAYOUT=y
727# Watchdog Device Drivers 727# Watchdog Device Drivers
728# 728#
729# CONFIG_SOFT_WATCHDOG is not set 729# CONFIG_SOFT_WATCHDOG is not set
730# CONFIG_AT91SAM9_WATCHDOG is not set 730# CONFIG_AT91SAM9X_WATCHDOG is not set
731 731
732# 732#
733# USB-based Watchdog Cards 733# USB-based Watchdog Cards
diff --git a/arch/arm/kernel/elf.c b/arch/arm/kernel/elf.c
index 84849098c8e8..d4a0da1e48f4 100644
--- a/arch/arm/kernel/elf.c
+++ b/arch/arm/kernel/elf.c
@@ -74,9 +74,9 @@ EXPORT_SYMBOL(elf_set_personality);
74 */ 74 */
75int arm_elf_read_implies_exec(const struct elf32_hdr *x, int executable_stack) 75int arm_elf_read_implies_exec(const struct elf32_hdr *x, int executable_stack)
76{ 76{
77 if (executable_stack != EXSTACK_ENABLE_X) 77 if (executable_stack != EXSTACK_DISABLE_X)
78 return 1; 78 return 1;
79 if (cpu_architecture() <= CPU_ARCH_ARMv6) 79 if (cpu_architecture() < CPU_ARCH_ARMv6)
80 return 1; 80 return 1;
81 return 0; 81 return 0;
82} 82}
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 440dc62cdc3a..598ca61e7bca 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -13,8 +13,8 @@
13#include <asm/cacheflush.h> 13#include <asm/cacheflush.h>
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16const extern unsigned char relocate_new_kernel[]; 16extern const unsigned char relocate_new_kernel[];
17const extern unsigned int relocate_new_kernel_size; 17extern const unsigned int relocate_new_kernel_size;
18 18
19extern void setup_mm_for_reboot(char mode); 19extern void setup_mm_for_reboot(char mode);
20 20
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 8d21427bb679..bc5e4128f9f3 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -234,12 +234,13 @@ static void __init cacheid_init(void)
234 unsigned int cachetype = read_cpuid_cachetype(); 234 unsigned int cachetype = read_cpuid_cachetype();
235 unsigned int arch = cpu_architecture(); 235 unsigned int arch = cpu_architecture();
236 236
237 if (arch >= CPU_ARCH_ARMv7) { 237 if (arch >= CPU_ARCH_ARMv6) {
238 cacheid = CACHEID_VIPT_NONALIASING; 238 if ((cachetype & (7 << 29)) == 4 << 29) {
239 if ((cachetype & (3 << 14)) == 1 << 14) 239 /* ARMv7 register format */
240 cacheid |= CACHEID_ASID_TAGGED; 240 cacheid = CACHEID_VIPT_NONALIASING;
241 } else if (arch >= CPU_ARCH_ARMv6) { 241 if ((cachetype & (3 << 14)) == 1 << 14)
242 if (cachetype & (1 << 23)) 242 cacheid |= CACHEID_ASID_TAGGED;
243 } else if (cachetype & (1 << 23))
243 cacheid = CACHEID_VIPT_ALIASING; 244 cacheid = CACHEID_VIPT_ALIASING;
244 else 245 else
245 cacheid = CACHEID_VIPT_NONALIASING; 246 cacheid = CACHEID_VIPT_NONALIASING;
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index 9eca2209cde6..412aa49ad2fb 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -697,7 +697,7 @@ static void __init at91_add_device_rtt(void)
697 * Watchdog 697 * Watchdog
698 * -------------------------------------------------------------------- */ 698 * -------------------------------------------------------------------- */
699 699
700#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) 700#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
701static struct platform_device at91cap9_wdt_device = { 701static struct platform_device at91cap9_wdt_device = {
702 .name = "at91_wdt", 702 .name = "at91_wdt",
703 .id = -1, 703 .id = -1,
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index fdde1ea21b07..d74c9ac007e7 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -643,7 +643,7 @@ static void __init at91_add_device_rtt(void)
643 * Watchdog 643 * Watchdog
644 * -------------------------------------------------------------------- */ 644 * -------------------------------------------------------------------- */
645 645
646#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) 646#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
647static struct platform_device at91sam9260_wdt_device = { 647static struct platform_device at91sam9260_wdt_device = {
648 .name = "at91_wdt", 648 .name = "at91_wdt",
649 .id = -1, 649 .id = -1,
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 17289756f80f..59fc48311fb0 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -621,7 +621,7 @@ static void __init at91_add_device_rtt(void)
621 * Watchdog 621 * Watchdog
622 * -------------------------------------------------------------------- */ 622 * -------------------------------------------------------------------- */
623 623
624#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) 624#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
625static struct platform_device at91sam9261_wdt_device = { 625static struct platform_device at91sam9261_wdt_device = {
626 .name = "at91_wdt", 626 .name = "at91_wdt",
627 .id = -1, 627 .id = -1,
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b753cb879d8e..b7f233242315 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -347,6 +347,111 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
347void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} 347void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
348#endif 348#endif
349 349
350/* --------------------------------------------------------------------
351 * Compact Flash (PCMCIA or IDE)
352 * -------------------------------------------------------------------- */
353
354#if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \
355 defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
356
357static struct at91_cf_data cf0_data;
358
359static struct resource cf0_resources[] = {
360 [0] = {
361 .start = AT91_CHIPSELECT_4,
362 .end = AT91_CHIPSELECT_4 + SZ_256M - 1,
363 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
364 }
365};
366
367static struct platform_device cf0_device = {
368 .id = 0,
369 .dev = {
370 .platform_data = &cf0_data,
371 },
372 .resource = cf0_resources,
373 .num_resources = ARRAY_SIZE(cf0_resources),
374};
375
376static struct at91_cf_data cf1_data;
377
378static struct resource cf1_resources[] = {
379 [0] = {
380 .start = AT91_CHIPSELECT_5,
381 .end = AT91_CHIPSELECT_5 + SZ_256M - 1,
382 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT,
383 }
384};
385
386static struct platform_device cf1_device = {
387 .id = 1,
388 .dev = {
389 .platform_data = &cf1_data,
390 },
391 .resource = cf1_resources,
392 .num_resources = ARRAY_SIZE(cf1_resources),
393};
394
395void __init at91_add_device_cf(struct at91_cf_data *data)
396{
397 unsigned long ebi0_csa;
398 struct platform_device *pdev;
399
400 if (!data)
401 return;
402
403 /*
404 * assign CS4 or CS5 to SMC with Compact Flash logic support,
405 * we assume SMC timings are configured by board code,
406 * except True IDE where timings are controlled by driver
407 */
408 ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
409 switch (data->chipselect) {
410 case 4:
411 at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */
412 ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1;
413 cf0_data = *data;
414 pdev = &cf0_device;
415 break;
416 case 5:
417 at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */
418 ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2;
419 cf1_data = *data;
420 pdev = &cf1_device;
421 break;
422 default:
423 printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
424 data->chipselect);
425 return;
426 }
427 at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa);
428
429 if (data->det_pin) {
430 at91_set_gpio_input(data->det_pin, 1);
431 at91_set_deglitch(data->det_pin, 1);
432 }
433
434 if (data->irq_pin) {
435 at91_set_gpio_input(data->irq_pin, 1);
436 at91_set_deglitch(data->irq_pin, 1);
437 }
438
439 if (data->vcc_pin)
440 /* initially off */
441 at91_set_gpio_output(data->vcc_pin, 0);
442
443 /* enable EBI controlled pins */
444 at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */
445 at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */
446 at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */
447 at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */
448
449 pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf";
450 platform_device_register(pdev);
451}
452#else
453void __init at91_add_device_cf(struct at91_cf_data *data) {}
454#endif
350 455
351/* -------------------------------------------------------------------- 456/* --------------------------------------------------------------------
352 * NAND / SmartMedia 457 * NAND / SmartMedia
@@ -854,7 +959,7 @@ static void __init at91_add_device_rtt(void)
854 * Watchdog 959 * Watchdog
855 * -------------------------------------------------------------------- */ 960 * -------------------------------------------------------------------- */
856 961
857#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) 962#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
858static struct platform_device at91sam9263_wdt_device = { 963static struct platform_device at91sam9263_wdt_device = {
859 .name = "at91_wdt", 964 .name = "at91_wdt",
860 .id = -1, 965 .id = -1,
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 145324f4ec56..728186515cdf 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -609,7 +609,7 @@ static void __init at91_add_device_rtt(void)
609 * Watchdog 609 * Watchdog
610 * -------------------------------------------------------------------- */ 610 * -------------------------------------------------------------------- */
611 611
612#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) 612#if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
613static struct platform_device at91sam9rl_wdt_device = { 613static struct platform_device at91sam9rl_wdt_device = {
614 .name = "at91_wdt", 614 .name = "at91_wdt",
615 .id = -1, 615 .id = -1,
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 028e4f7a88be..f2236f0e101f 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -437,7 +437,68 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
437 437
438/*--------------------------------------------------------------------------*/ 438/*--------------------------------------------------------------------------*/
439 439
440/* This lock class tells lockdep that GPIO irqs are in a different 440#ifdef CONFIG_DEBUG_FS
441
442static int at91_gpio_show(struct seq_file *s, void *unused)
443{
444 int bank, j;
445
446 /* print heading */
447 seq_printf(s, "Pin\t");
448 for (bank = 0; bank < gpio_banks; bank++) {
449 seq_printf(s, "PIO%c\t", 'A' + bank);
450 };
451 seq_printf(s, "\n\n");
452
453 /* print pin status */
454 for (j = 0; j < 32; j++) {
455 seq_printf(s, "%i:\t", j);
456
457 for (bank = 0; bank < gpio_banks; bank++) {
458 unsigned pin = PIN_BASE + (32 * bank) + j;
459 void __iomem *pio = pin_to_controller(pin);
460 unsigned mask = pin_to_mask(pin);
461
462 if (__raw_readl(pio + PIO_PSR) & mask)
463 seq_printf(s, "GPIO:%s", __raw_readl(pio + PIO_PDSR) & mask ? "1" : "0");
464 else
465 seq_printf(s, "%s", __raw_readl(pio + PIO_ABSR) & mask ? "B" : "A");
466
467 seq_printf(s, "\t");
468 }
469
470 seq_printf(s, "\n");
471 }
472
473 return 0;
474}
475
476static int at91_gpio_open(struct inode *inode, struct file *file)
477{
478 return single_open(file, at91_gpio_show, NULL);
479}
480
481static const struct file_operations at91_gpio_operations = {
482 .open = at91_gpio_open,
483 .read = seq_read,
484 .llseek = seq_lseek,
485 .release = single_release,
486};
487
488static int __init at91_gpio_debugfs_init(void)
489{
490 /* /sys/kernel/debug/at91_gpio */
491 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
492 return 0;
493}
494postcore_initcall(at91_gpio_debugfs_init);
495
496#endif
497
498/*--------------------------------------------------------------------------*/
499
500/*
501 * This lock class tells lockdep that GPIO irqs are in a different
441 * category than their parents, so it won't report false recursion. 502 * category than their parents, so it won't report false recursion.
442 */ 503 */
443static struct lock_class_key gpio_lock_class; 504static struct lock_class_key gpio_lock_class;
@@ -456,9 +517,6 @@ void __init at91_gpio_irq_setup(void)
456 unsigned id = this->bank->id; 517 unsigned id = this->bank->id;
457 unsigned i; 518 unsigned i;
458 519
459 /* enable PIO controller's clock */
460 clk_enable(this->bank->clock);
461
462 __raw_writel(~0, this->regbase + PIO_IDR); 520 __raw_writel(~0, this->regbase + PIO_IDR);
463 521
464 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { 522 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
@@ -589,6 +647,9 @@ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
589 at91_gpio->regbase = at91_gpio->bank->offset + 647 at91_gpio->regbase = at91_gpio->bank->offset +
590 (void __iomem *)AT91_VA_BASE_SYS; 648 (void __iomem *)AT91_VA_BASE_SYS;
591 649
650 /* enable PIO controller's clock */
651 clk_enable(at91_gpio->bank->clock);
652
592 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ 653 /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */
593 if (last && last->bank->id == at91_gpio->bank->id) 654 if (last && last->bank->id == at91_gpio->bank->id)
594 last->next = at91_gpio; 655 last->next = at91_gpio;
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index fb51f0e0a83f..793fe7b25f36 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -56,6 +56,9 @@ struct at91_cf_data {
56 u8 vcc_pin; /* power switching */ 56 u8 vcc_pin; /* power switching */
57 u8 rst_pin; /* card reset */ 57 u8 rst_pin; /* card reset */
58 u8 chipselect; /* EBI Chip Select number */ 58 u8 chipselect; /* EBI Chip Select number */
59 u8 flags;
60#define AT91_CF_TRUE_IDE 0x01
61#define AT91_IDE_SWAP_A0_A2 0x02
59}; 62};
60extern void __init at91_add_device_cf(struct at91_cf_data *data); 63extern void __init at91_add_device_cf(struct at91_cf_data *data);
61 64
@@ -93,6 +96,7 @@ struct atmel_nand_data {
93 u8 enable_pin; /* chip enable */ 96 u8 enable_pin; /* chip enable */
94 u8 det_pin; /* card detect */ 97 u8 det_pin; /* card detect */
95 u8 rdy_pin; /* ready/busy */ 98 u8 rdy_pin; /* ready/busy */
99 u8 rdy_pin_active_low; /* rdy_pin value is inverted */
96 u8 ale; /* address line number connected to ALE */ 100 u8 ale; /* address line number connected to ALE */
97 u8 cle; /* address line number connected to CLE */ 101 u8 cle; /* address line number connected to CLE */
98 u8 bus_width_16; /* buswidth is 16 bit */ 102 u8 bus_width_16; /* buswidth is 16 bit */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 9bb4f043aa22..7ac812dc055a 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -332,7 +332,6 @@ static int at91_pm_enter(suspend_state_t state)
332 at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR)); 332 at91_sys_read(AT91_AIC_IPR) & at91_sys_read(AT91_AIC_IMR));
333 333
334error: 334error:
335 sdram_selfrefresh_disable();
336 target_state = PM_SUSPEND_ON; 335 target_state = PM_SUSPEND_ON;
337 at91_irq_resume(); 336 at91_irq_resume();
338 at91_gpio_resume(); 337 at91_gpio_resume();
diff --git a/arch/arm/mach-davinci/board-evm.c b/arch/arm/mach-davinci/board-evm.c
index a957d239a683..38b6a9ce2a93 100644
--- a/arch/arm/mach-davinci/board-evm.c
+++ b/arch/arm/mach-davinci/board-evm.c
@@ -311,6 +311,9 @@ evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
311 gpio_request(gpio + 7, "nCF_SEL"); 311 gpio_request(gpio + 7, "nCF_SEL");
312 gpio_direction_output(gpio + 7, 1); 312 gpio_direction_output(gpio + 7, 1);
313 313
314 /* irlml6401 sustains over 3A, switches 5V in under 8 msec */
315 setup_usb(500, 8);
316
314 return 0; 317 return 0;
315} 318}
316 319
@@ -417,9 +420,6 @@ static __init void davinci_evm_init(void)
417 platform_add_devices(davinci_evm_devices, 420 platform_add_devices(davinci_evm_devices,
418 ARRAY_SIZE(davinci_evm_devices)); 421 ARRAY_SIZE(davinci_evm_devices));
419 evm_init_i2c(); 422 evm_init_i2c();
420
421 /* irlml6401 sustains over 3A, switches 5V in under 8 msec */
422 setup_usb(500, 8);
423} 423}
424 424
425static __init void davinci_evm_irq_init(void) 425static __init void davinci_evm_irq_init(void)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 28f6dbc95bd7..abb92b7eca0c 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -231,6 +231,11 @@ static struct clk davinci_clks[] = {
231 .lpsc = DAVINCI_LPSC_GPIO, 231 .lpsc = DAVINCI_LPSC_GPIO,
232 }, 232 },
233 { 233 {
234 .name = "usb",
235 .rate = &commonrate,
236 .lpsc = DAVINCI_LPSC_USB,
237 },
238 {
234 .name = "AEMIFCLK", 239 .name = "AEMIFCLK",
235 .rate = &commonrate, 240 .rate = &commonrate,
236 .lpsc = DAVINCI_LPSC_AEMIF, 241 .lpsc = DAVINCI_LPSC_AEMIF,
diff --git a/arch/arm/mach-davinci/usb.c b/arch/arm/mach-davinci/usb.c
index 867ead2559ad..69680784448a 100644
--- a/arch/arm/mach-davinci/usb.c
+++ b/arch/arm/mach-davinci/usb.c
@@ -47,6 +47,7 @@ static struct musb_hdrc_platform_data usb_data = {
47#elif defined(CONFIG_USB_MUSB_HOST) 47#elif defined(CONFIG_USB_MUSB_HOST)
48 .mode = MUSB_HOST, 48 .mode = MUSB_HOST,
49#endif 49#endif
50 .clock = "usb",
50 .config = &musb_config, 51 .config = &musb_config,
51}; 52};
52 53
diff --git a/arch/arm/mach-ep93xx/include/mach/gesbc9312.h b/arch/arm/mach-ep93xx/include/mach/gesbc9312.h
deleted file mode 100644
index 21fe2b922aa5..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/gesbc9312.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * arch/arm/mach-ep93xx/include/mach/gesbc9312.h
3 */
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 529807d182bf..2866297310b7 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -10,7 +10,6 @@
10 10
11#include "platform.h" 11#include "platform.h"
12 12
13#include "gesbc9312.h"
14#include "ts72xx.h" 13#include "ts72xx.h"
15 14
16#endif 15#endif
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index efb86b700276..06083b23bb44 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -42,7 +42,7 @@ void __init kirkwood_init_irq(void)
42 writel(0, GPIO_EDGE_CAUSE(32)); 42 writel(0, GPIO_EDGE_CAUSE(32));
43 43
44 for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) { 44 for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
45 set_irq_chip(i, &orion_gpio_irq_level_chip); 45 set_irq_chip(i, &orion_gpio_irq_chip);
46 set_irq_handler(i, handle_level_irq); 46 set_irq_handler(i, handle_level_irq);
47 irq_desc[i].status |= IRQ_LEVEL; 47 irq_desc[i].status |= IRQ_LEVEL;
48 set_irq_flags(i, IRQF_VALID); 48 set_irq_flags(i, IRQF_VALID);
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index e273418797b4..30b7e4bcdbc7 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -40,7 +40,7 @@ void __init mv78xx0_init_irq(void)
40 writel(0, GPIO_EDGE_CAUSE(0)); 40 writel(0, GPIO_EDGE_CAUSE(0));
41 41
42 for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) { 42 for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
43 set_irq_chip(i, &orion_gpio_irq_level_chip); 43 set_irq_chip(i, &orion_gpio_irq_chip);
44 set_irq_handler(i, handle_level_irq); 44 set_irq_handler(i, handle_level_irq);
45 irq_desc[i].status |= IRQ_LEVEL; 45 irq_desc[i].status |= IRQ_LEVEL;
46 set_irq_flags(i, IRQF_VALID); 46 set_irq_flags(i, IRQF_VALID);
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
index 2b59fc74784f..eb7660f5d4b7 100644
--- a/arch/arm/mach-mx1/Kconfig
+++ b/arch/arm/mach-mx1/Kconfig
@@ -1,6 +1,6 @@
1if ARCH_MX1 1if ARCH_MX1
2 2
3comment "MX1 Platforms" 3comment "MX1 platforms:"
4 4
5config MACH_MXLADS 5config MACH_MXLADS
6 bool 6 bool
@@ -11,4 +11,9 @@ config ARCH_MX1ADS
11 help 11 help
12 Say Y here if you are using Motorola MX1ADS/MXLADS boards 12 Say Y here if you are using Motorola MX1ADS/MXLADS boards
13 13
14config MACH_SCB9328
15 bool "Synertronixx scb9328"
16 help
17 Say Y here if you are using a Synertronixx scb9328 board
18
14endif 19endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
index b969719011fa..82f1309568ef 100644
--- a/arch/arm/mach-mx1/Makefile
+++ b/arch/arm/mach-mx1/Makefile
@@ -8,3 +8,4 @@ obj-y += generic.o clock.o devices.o
8 8
9# Specific board support 9# Specific board support
10obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o 10obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o
11obj-$(CONFIG_MACH_SCB9328) += scb9328.o \ No newline at end of file
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 4bcd1ece55f5..0d0f306851d0 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -25,6 +25,7 @@
25 25
26#include <mach/clock.h> 26#include <mach/clock.h>
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/common.h>
28#include "crm_regs.h" 29#include "crm_regs.h"
29 30
30static int _clk_enable(struct clk *clk) 31static int _clk_enable(struct clk *clk)
@@ -87,33 +88,6 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
87 return clk->parent->set_rate(clk->parent, rate); 88 return clk->parent->set_rate(clk->parent, rate);
88} 89}
89 90
90/*
91 * get the system pll clock in Hz
92 *
93 * mfi + mfn / (mfd +1)
94 * f = 2 * f_ref * --------------------
95 * pd + 1
96 */
97static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref)
98{
99 unsigned long long ll;
100 unsigned long quot;
101
102 u32 mfi = (pll >> 10) & 0xf;
103 u32 mfn = pll & 0x3ff;
104 u32 mfd = (pll >> 16) & 0x3ff;
105 u32 pd = (pll >> 26) & 0xf;
106
107 mfi = mfi <= 5 ? 5 : mfi;
108
109 ll = 2 * (unsigned long long)f_ref *
110 ((mfi << 16) + (mfn << 16) / (mfd + 1));
111 quot = (pd + 1) * (1 << 16);
112 ll += quot / 2;
113 do_div(ll, quot);
114 return (unsigned long)ll;
115}
116
117static unsigned long clk16m_get_rate(struct clk *clk) 91static unsigned long clk16m_get_rate(struct clk *clk)
118{ 92{
119 return 16000000; 93 return 16000000;
@@ -188,7 +162,7 @@ static struct clk prem_clk = {
188 162
189static unsigned long system_clk_get_rate(struct clk *clk) 163static unsigned long system_clk_get_rate(struct clk *clk)
190{ 164{
191 return mx1_decode_pll(__raw_readl(CCM_SPCTL0), 165 return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
192 clk_get_rate(clk->parent)); 166 clk_get_rate(clk->parent));
193} 167}
194 168
@@ -200,7 +174,7 @@ static struct clk system_clk = {
200 174
201static unsigned long mcu_clk_get_rate(struct clk *clk) 175static unsigned long mcu_clk_get_rate(struct clk *clk)
202{ 176{
203 return mx1_decode_pll(__raw_readl(CCM_MPCTL0), 177 return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
204 clk_get_rate(clk->parent)); 178 clk_get_rate(clk->parent));
205} 179}
206 180
@@ -488,7 +462,7 @@ static struct clk clko_clk = {
488}; 462};
489 463
490static struct clk dma_clk = { 464static struct clk dma_clk = {
491 .name = "dma_clk", 465 .name = "dma",
492 .parent = &hclk, 466 .parent = &hclk,
493 .round_rate = _clk_parent_round_rate, 467 .round_rate = _clk_parent_round_rate,
494 .set_rate = _clk_parent_set_rate, 468 .set_rate = _clk_parent_set_rate,
@@ -539,7 +513,7 @@ static struct clk gpt_clk = {
539}; 513};
540 514
541static struct clk uart_clk = { 515static struct clk uart_clk = {
542 .name = "uart_clk", 516 .name = "uart",
543 .parent = &perclk[0], 517 .parent = &perclk[0],
544 .round_rate = _clk_parent_round_rate, 518 .round_rate = _clk_parent_round_rate,
545 .set_rate = _clk_parent_set_rate, 519 .set_rate = _clk_parent_set_rate,
@@ -621,7 +595,7 @@ static struct clk *mxc_clks[] = {
621 &rtc_clk, 595 &rtc_clk,
622}; 596};
623 597
624int __init mxc_clocks_init(unsigned long fref) 598int __init mx1_clocks_init(unsigned long fref)
625{ 599{
626 struct clk **clkp; 600 struct clk **clkp;
627 unsigned int reg; 601 unsigned int reg;
@@ -652,5 +626,7 @@ int __init mxc_clocks_init(unsigned long fref)
652 clk_enable(&hclk); 626 clk_enable(&hclk);
653 clk_enable(&fclk); 627 clk_enable(&fclk);
654 628
629 mxc_timer_init(&gpt_clk);
630
655 return 0; 631 return 0;
656} 632}
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 686d8d2dbb24..97f42d96d7a1 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -23,8 +23,11 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <mach/irqs.h>
26#include <mach/hardware.h> 27#include <mach/hardware.h>
27 28
29#include "devices.h"
30
28static struct resource imx_csi_resources[] = { 31static struct resource imx_csi_resources[] = {
29 [0] = { 32 [0] = {
30 .start = 0x00224000, 33 .start = 0x00224000,
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index 2e4b185fe4a9..89738fe576b1 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -16,6 +16,8 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/mtd/physmap.h> 18#include <linux/mtd/physmap.h>
19#include <linux/i2c.h>
20#include <linux/i2c/pcf857x.h>
19 21
20#include <asm/mach-types.h> 22#include <asm/mach-types.h>
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
@@ -24,7 +26,11 @@
24#include <mach/hardware.h> 26#include <mach/hardware.h>
25#include <mach/common.h> 27#include <mach/common.h>
26#include <mach/imx-uart.h> 28#include <mach/imx-uart.h>
27#include <mach/iomux-mx1-mx2.h> 29#include <mach/irqs.h>
30#ifdef CONFIG_I2C_IMX
31#include <mach/i2c.h>
32#endif
33#include <mach/iomux.h>
28#include "devices.h" 34#include "devices.h"
29 35
30/* 36/*
@@ -104,6 +110,55 @@ static struct platform_device flash_device = {
104}; 110};
105 111
106/* 112/*
113 * I2C
114 */
115
116#ifdef CONFIG_I2C_IMX
117static int i2c_pins[] = {
118 PA15_PF_I2C_SDA,
119 PA16_PF_I2C_SCL,
120};
121
122static int i2c_init(struct device *dev)
123{
124 return mxc_gpio_setup_multiple_pins(i2c_pins,
125 ARRAY_SIZE(i2c_pins), "I2C");
126}
127
128static void i2c_exit(struct device *dev)
129{
130 mxc_gpio_release_multiple_pins(i2c_pins,
131 ARRAY_SIZE(i2c_pins));
132}
133
134static struct pcf857x_platform_data pcf857x_data[] = {
135 {
136 .gpio_base = 4 * 32,
137 }, {
138 .gpio_base = 4 * 32 + 16,
139 }
140};
141
142static struct imxi2c_platform_data mx1ads_i2c_data = {
143 .bitrate = 100000,
144 .init = i2c_init,
145 .exit = i2c_exit,
146};
147
148static struct i2c_board_info mx1ads_i2c_devices[] = {
149 {
150 I2C_BOARD_INFO("pcf857x", 0x22),
151 .type = "pcf8575",
152 .platform_data = &pcf857x_data[0],
153 }, {
154 I2C_BOARD_INFO("pcf857x", 0x24),
155 .type = "pcf8575",
156 .platform_data = &pcf857x_data[1],
157 },
158};
159#endif
160
161/*
107 * Board init 162 * Board init
108 */ 163 */
109static void __init mx1ads_init(void) 164static void __init mx1ads_init(void)
@@ -114,12 +169,19 @@ static void __init mx1ads_init(void)
114 169
115 /* Physmap flash */ 170 /* Physmap flash */
116 mxc_register_device(&flash_device, &mx1ads_flash_data); 171 mxc_register_device(&flash_device, &mx1ads_flash_data);
172
173 /* I2C */
174#ifdef CONFIG_I2C_IMX
175 i2c_register_board_info(0, mx1ads_i2c_devices,
176 ARRAY_SIZE(mx1ads_i2c_devices));
177
178 mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
179#endif
117} 180}
118 181
119static void __init mx1ads_timer_init(void) 182static void __init mx1ads_timer_init(void)
120{ 183{
121 mxc_clocks_init(32000); 184 mx1_clocks_init(32000);
122 mxc_timer_init("gpt_clk");
123} 185}
124 186
125struct sys_timer mx1ads_timer = { 187struct sys_timer mx1ads_timer = {
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
new file mode 100644
index 000000000000..0e71f3fa28bf
--- /dev/null
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -0,0 +1,160 @@
1/*
2 * linux/arch/arm/mach-mx1/scb9328.c
3 *
4 * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
5 * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#include <linux/platform_device.h>
14#include <linux/mtd/physmap.h>
15#include <linux/interrupt.h>
16#include <linux/dm9000.h>
17
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/time.h>
21
22#include <mach/common.h>
23#include <mach/hardware.h>
24#include <mach/irqs.h>
25#include <mach/imx-uart.h>
26#include <mach/iomux.h>
27
28#include "devices.h"
29
30/*
31 * This scb9328 has a 32MiB flash
32 */
33static struct resource flash_resource = {
34 .start = IMX_CS0_PHYS,
35 .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
36 .flags = IORESOURCE_MEM,
37};
38
39static struct physmap_flash_data scb_flash_data = {
40 .width = 2,
41};
42
43static struct platform_device scb_flash_device = {
44 .name = "physmap-flash",
45 .id = 0,
46 .dev = {
47 .platform_data = &scb_flash_data,
48 },
49 .resource = &flash_resource,
50 .num_resources = 1,
51};
52
53/*
54 * scb9328 has a DM9000 network controller
55 * connected to CS5, with 16 bit data path
56 * and interrupt connected to GPIO 3
57 */
58
59/*
60 * internal datapath is fixed 16 bit
61 */
62static struct dm9000_plat_data dm9000_platdata = {
63 .flags = DM9000_PLATF_16BITONLY,
64};
65
66/*
67 * the DM9000 drivers wants two defined address spaces
68 * to gain access to address latch registers and the data path.
69 */
70static struct resource dm9000x_resources[] = {
71 [0] = {
72 .name = "address area",
73 .start = IMX_CS5_PHYS,
74 .end = IMX_CS5_PHYS + 1,
75 .flags = IORESOURCE_MEM /* address access */
76 },
77 [1] = {
78 .name = "data area",
79 .start = IMX_CS5_PHYS + 4,
80 .end = IMX_CS5_PHYS + 5,
81 .flags = IORESOURCE_MEM /* data access */
82 },
83 [2] = {
84 .start = IRQ_GPIOC(3),
85 .end = IRQ_GPIOC(3),
86 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL
87 },
88};
89
90static struct platform_device dm9000x_device = {
91 .name = "dm9000",
92 .id = 0,
93 .num_resources = ARRAY_SIZE(dm9000x_resources),
94 .resource = dm9000x_resources,
95 .dev = {
96 .platform_data = &dm9000_platdata,
97 }
98};
99
100static int mxc_uart1_pins[] = {
101 PC9_PF_UART1_CTS,
102 PC10_PF_UART1_RTS,
103 PC11_PF_UART1_TXD,
104 PC12_PF_UART1_RXD,
105};
106
107static int uart1_mxc_init(struct platform_device *pdev)
108{
109 return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
110 ARRAY_SIZE(mxc_uart1_pins), "UART1");
111}
112
113static int uart1_mxc_exit(struct platform_device *pdev)
114{
115 mxc_gpio_release_multiple_pins(mxc_uart1_pins,
116 ARRAY_SIZE(mxc_uart1_pins));
117 return 0;
118}
119
120static struct imxuart_platform_data uart_pdata = {
121 .init = uart1_mxc_init,
122 .exit = uart1_mxc_exit,
123 .flags = IMXUART_HAVE_RTSCTS,
124};
125
126static struct platform_device *devices[] __initdata = {
127 &scb_flash_device,
128 &dm9000x_device,
129};
130
131/*
132 * scb9328_init - Init the CPU card itself
133 */
134static void __init scb9328_init(void)
135{
136 mxc_register_device(&imx_uart1_device, &uart_pdata);
137
138 printk(KERN_INFO"Scb9328: Adding devices\n");
139 platform_add_devices(devices, ARRAY_SIZE(devices));
140}
141
142static void __init scb9328_timer_init(void)
143{
144 mx1_clocks_init(32000);
145}
146
147static struct sys_timer scb9328_timer = {
148 .init = scb9328_timer_init,
149};
150
151MACHINE_START(SCB9328, "Synertronixx scb9328")
152 /* Sascha Hauer */
153 .phys_io = 0x00200000,
154 .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc,
155 .boot_params = 0x08000100,
156 .map_io = mxc_map_io,
157 .init_irq = mxc_init_irq,
158 .timer = &scb9328_timer,
159 .init_machine = scb9328_init,
160MACHINE_END
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index 1eaa97cb716d..42a788842f49 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -1,14 +1,22 @@
1comment "MX2 family CPU support" 1if ARCH_MX2
2 depends on ARCH_MX2 2
3choice
4 prompt "CPUs:"
5 default MACH_MX21
6
7config MACH_MX21
8 bool "i.MX21 support"
9 help
10 This enables support for Freescale's MX2 based i.MX21 processor.
3 11
4config MACH_MX27 12config MACH_MX27
5 bool "i.MX27 support" 13 bool "i.MX27 support"
6 depends on ARCH_MX2
7 help 14 help
8 This enables support for Freescale's MX2 based i.MX27 processor. 15 This enables support for Freescale's MX2 based i.MX27 processor.
9 16
10comment "MX2 Platforms" 17endchoice
11 depends on ARCH_MX2 18
19comment "MX2 platforms:"
12 20
13config MACH_MX27ADS 21config MACH_MX27ADS
14 bool "MX27ADS platform" 22 bool "MX27ADS platform"
@@ -37,3 +45,5 @@ config MACH_PCM970_BASEBOARD
37 PCM970 evaluation board. 45 PCM970 evaluation board.
38 46
39endchoice 47endchoice
48
49endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index 382d86080e86..6e1a2bffc812 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -6,6 +6,8 @@
6 6
7obj-y := system.o generic.o devices.o serial.o 7obj-y := system.o generic.o devices.o serial.o
8 8
9obj-$(CONFIG_MACH_MX21) += clock_imx21.o
10
9obj-$(CONFIG_MACH_MX27) += cpu_imx27.o 11obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
10obj-$(CONFIG_MACH_MX27) += clock_imx27.o 12obj-$(CONFIG_MACH_MX27) += clock_imx27.o
11 13
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot
index 696831dcd485..e867398a8fdb 100644
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-mx2/Makefile.boot
@@ -1,3 +1,7 @@
1 zreladdr-y := 0xA0008000 1zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
2params_phys-y := 0xA0000100 2params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
3initrd_phys-y := 0xA0800000 3initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
4
5zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
6params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
7initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
new file mode 100644
index 000000000000..2dee5c87614c
--- /dev/null
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -0,0 +1,984 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/module.h>
24
25#include <mach/clock.h>
26#include <mach/common.h>
27#include <asm/clkdev.h>
28#include <asm/div64.h>
29
30#include "crm_regs.h"
31
32static int _clk_enable(struct clk *clk)
33{
34 u32 reg;
35
36 reg = __raw_readl(clk->enable_reg);
37 reg |= 1 << clk->enable_shift;
38 __raw_writel(reg, clk->enable_reg);
39 return 0;
40}
41
42static void _clk_disable(struct clk *clk)
43{
44 u32 reg;
45
46 reg = __raw_readl(clk->enable_reg);
47 reg &= ~(1 << clk->enable_shift);
48 __raw_writel(reg, clk->enable_reg);
49}
50
51static int _clk_spll_enable(struct clk *clk)
52{
53 u32 reg;
54
55 reg = __raw_readl(CCM_CSCR);
56 reg |= CCM_CSCR_SPEN;
57 __raw_writel(reg, CCM_CSCR);
58
59 while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0)
60 ;
61 return 0;
62}
63
64static void _clk_spll_disable(struct clk *clk)
65{
66 u32 reg;
67
68 reg = __raw_readl(CCM_CSCR);
69 reg &= ~CCM_CSCR_SPEN;
70 __raw_writel(reg, CCM_CSCR);
71}
72
73
74#define CSCR() (__raw_readl(CCM_CSCR))
75#define PCDR0() (__raw_readl(CCM_PCDR0))
76#define PCDR1() (__raw_readl(CCM_PCDR1))
77
78static unsigned long _clk_perclkx_round_rate(struct clk *clk,
79 unsigned long rate)
80{
81 u32 div;
82 unsigned long parent_rate;
83
84 parent_rate = clk_get_rate(clk->parent);
85
86 div = parent_rate / rate;
87 if (parent_rate % rate)
88 div++;
89
90 if (div > 64)
91 div = 64;
92
93 return parent_rate / div;
94}
95
96static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
97{
98 u32 reg;
99 u32 div;
100 unsigned long parent_rate;
101
102 parent_rate = clk_get_rate(clk->parent);
103
104 if (clk->id < 0 || clk->id > 3)
105 return -EINVAL;
106
107 div = parent_rate / rate;
108 if (div > 64 || div < 1 || ((parent_rate / div) != rate))
109 return -EINVAL;
110 div--;
111
112 reg =
113 __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
114 (clk->id << 3));
115 reg |= div << (clk->id << 3);
116 __raw_writel(reg, CCM_PCDR1);
117
118 return 0;
119}
120
121static unsigned long _clk_usb_recalc(struct clk *clk)
122{
123 unsigned long usb_pdf;
124 unsigned long parent_rate;
125
126 parent_rate = clk_get_rate(clk->parent);
127
128 usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET;
129
130 return parent_rate / (usb_pdf + 1U);
131}
132
133static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf)
134{
135 unsigned long parent_rate;
136
137 parent_rate = clk_get_rate(clk->parent);
138
139 pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
140
141 return 2UL * parent_rate / pdf;
142}
143
144static unsigned long _clk_ssi1_recalc(struct clk *clk)
145{
146 return _clk_ssix_recalc(clk,
147 (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK)
148 >> CCM_PCDR0_SSI1BAUDDIV_OFFSET);
149}
150
151static unsigned long _clk_ssi2_recalc(struct clk *clk)
152{
153 return _clk_ssix_recalc(clk,
154 (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
155 CCM_PCDR0_SSI2BAUDDIV_OFFSET);
156}
157
158static unsigned long _clk_nfc_recalc(struct clk *clk)
159{
160 unsigned long nfc_pdf;
161 unsigned long parent_rate;
162
163 parent_rate = clk_get_rate(clk->parent);
164
165 nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK)
166 >> CCM_PCDR0_NFCDIV_OFFSET;
167
168 return parent_rate / (nfc_pdf + 1);
169}
170
171static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
172{
173 return clk->parent->round_rate(clk->parent, rate);
174}
175
176static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
177{
178 return clk->parent->set_rate(clk->parent, rate);
179}
180
181static unsigned long external_high_reference; /* in Hz */
182
183static unsigned long get_high_reference_clock_rate(struct clk *clk)
184{
185 return external_high_reference;
186}
187
188/*
189 * the high frequency external clock reference
190 * Default case is 26MHz.
191 */
192static struct clk ckih_clk = {
193 .get_rate = get_high_reference_clock_rate,
194};
195
196static unsigned long external_low_reference; /* in Hz */
197
198static unsigned long get_low_reference_clock_rate(struct clk *clk)
199{
200 return external_low_reference;
201}
202
203/*
204 * the low frequency external clock reference
205 * Default case is 32.768kHz.
206 */
207static struct clk ckil_clk = {
208 .get_rate = get_low_reference_clock_rate,
209};
210
211
212static unsigned long _clk_fpm_recalc(struct clk *clk)
213{
214 return clk_get_rate(clk->parent) * 512;
215}
216
217/* Output of frequency pre multiplier */
218static struct clk fpm_clk = {
219 .parent = &ckil_clk,
220 .get_rate = _clk_fpm_recalc,
221};
222
223static unsigned long get_mpll_clk(struct clk *clk)
224{
225 uint32_t reg;
226 unsigned long ref_clk;
227 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
228 unsigned long long temp;
229
230 ref_clk = clk_get_rate(clk->parent);
231
232 reg = __raw_readl(CCM_MPCTL0);
233 pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
234 mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
235 mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
236 mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
237
238 mfi = (mfi <= 5) ? 5 : mfi;
239 temp = 2LL * ref_clk * mfn;
240 do_div(temp, mfd + 1);
241 temp = 2LL * ref_clk * mfi + temp;
242 do_div(temp, pdf + 1);
243
244 return (unsigned long)temp;
245}
246
247static struct clk mpll_clk = {
248 .parent = &ckih_clk,
249 .get_rate = get_mpll_clk,
250};
251
252static unsigned long _clk_fclk_get_rate(struct clk *clk)
253{
254 unsigned long parent_rate;
255 u32 div;
256
257 div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET;
258 parent_rate = clk_get_rate(clk->parent);
259
260 return parent_rate / (div+1);
261}
262
263static struct clk fclk_clk = {
264 .parent = &mpll_clk,
265 .get_rate = _clk_fclk_get_rate
266};
267
268static unsigned long get_spll_clk(struct clk *clk)
269{
270 uint32_t reg;
271 unsigned long ref_clk;
272 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
273 unsigned long long temp;
274
275 ref_clk = clk_get_rate(clk->parent);
276
277 reg = __raw_readl(CCM_SPCTL0);
278 pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET;
279 mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
280 mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
281 mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
282
283 mfi = (mfi <= 5) ? 5 : mfi;
284 temp = 2LL * ref_clk * mfn;
285 do_div(temp, mfd + 1);
286 temp = 2LL * ref_clk * mfi + temp;
287 do_div(temp, pdf + 1);
288
289 return (unsigned long)temp;
290}
291
292static struct clk spll_clk = {
293 .parent = &ckih_clk,
294 .get_rate = get_spll_clk,
295 .enable = _clk_spll_enable,
296 .disable = _clk_spll_disable,
297};
298
299static unsigned long get_hclk_clk(struct clk *clk)
300{
301 unsigned long rate;
302 unsigned long bclk_pdf;
303
304 bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK)
305 >> CCM_CSCR_BCLK_OFFSET;
306
307 rate = clk_get_rate(clk->parent);
308 return rate / (bclk_pdf + 1);
309}
310
311static struct clk hclk_clk = {
312 .parent = &fclk_clk,
313 .get_rate = get_hclk_clk,
314};
315
316static unsigned long get_ipg_clk(struct clk *clk)
317{
318 unsigned long rate;
319 unsigned long ipg_pdf;
320
321 ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET;
322
323 rate = clk_get_rate(clk->parent);
324 return rate / (ipg_pdf + 1);
325}
326
327static struct clk ipg_clk = {
328 .parent = &hclk_clk,
329 .get_rate = get_ipg_clk,
330};
331
332static unsigned long _clk_perclkx_recalc(struct clk *clk)
333{
334 unsigned long perclk_pdf;
335 unsigned long parent_rate;
336
337 parent_rate = clk_get_rate(clk->parent);
338
339 if (clk->id < 0 || clk->id > 3)
340 return 0;
341
342 perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK;
343
344 return parent_rate / (perclk_pdf + 1);
345}
346
347static struct clk per_clk[] = {
348 {
349 .id = 0,
350 .parent = &mpll_clk,
351 .get_rate = _clk_perclkx_recalc,
352 }, {
353 .id = 1,
354 .parent = &mpll_clk,
355 .get_rate = _clk_perclkx_recalc,
356 }, {
357 .id = 2,
358 .parent = &mpll_clk,
359 .round_rate = _clk_perclkx_round_rate,
360 .set_rate = _clk_perclkx_set_rate,
361 .get_rate = _clk_perclkx_recalc,
362 /* Enable/Disable done via lcd_clkc[1] */
363 }, {
364 .id = 3,
365 .parent = &mpll_clk,
366 .round_rate = _clk_perclkx_round_rate,
367 .set_rate = _clk_perclkx_set_rate,
368 .get_rate = _clk_perclkx_recalc,
369 /* Enable/Disable done via csi_clk[1] */
370 },
371};
372
373static struct clk uart_ipg_clk[];
374
375static struct clk uart_clk[] = {
376 {
377 .id = 0,
378 .parent = &per_clk[0],
379 .secondary = &uart_ipg_clk[0],
380 }, {
381 .id = 1,
382 .parent = &per_clk[0],
383 .secondary = &uart_ipg_clk[1],
384 }, {
385 .id = 2,
386 .parent = &per_clk[0],
387 .secondary = &uart_ipg_clk[2],
388 }, {
389 .id = 3,
390 .parent = &per_clk[0],
391 .secondary = &uart_ipg_clk[3],
392 },
393};
394
395static struct clk uart_ipg_clk[] = {
396 {
397 .id = 0,
398 .parent = &ipg_clk,
399 .enable = _clk_enable,
400 .enable_reg = CCM_PCCR_UART1_REG,
401 .enable_shift = CCM_PCCR_UART1_OFFSET,
402 .disable = _clk_disable,
403 }, {
404 .id = 1,
405 .parent = &ipg_clk,
406 .enable = _clk_enable,
407 .enable_reg = CCM_PCCR_UART2_REG,
408 .enable_shift = CCM_PCCR_UART2_OFFSET,
409 .disable = _clk_disable,
410 }, {
411 .id = 2,
412 .parent = &ipg_clk,
413 .enable = _clk_enable,
414 .enable_reg = CCM_PCCR_UART3_REG,
415 .enable_shift = CCM_PCCR_UART3_OFFSET,
416 .disable = _clk_disable,
417 }, {
418 .id = 3,
419 .parent = &ipg_clk,
420 .enable = _clk_enable,
421 .enable_reg = CCM_PCCR_UART4_REG,
422 .enable_shift = CCM_PCCR_UART4_OFFSET,
423 .disable = _clk_disable,
424 },
425};
426
427static struct clk gpt_ipg_clk[];
428
429static struct clk gpt_clk[] = {
430 {
431 .id = 0,
432 .parent = &per_clk[0],
433 .secondary = &gpt_ipg_clk[0],
434 }, {
435 .id = 1,
436 .parent = &per_clk[0],
437 .secondary = &gpt_ipg_clk[1],
438 }, {
439 .id = 2,
440 .parent = &per_clk[0],
441 .secondary = &gpt_ipg_clk[2],
442 },
443};
444
445static struct clk gpt_ipg_clk[] = {
446 {
447 .id = 0,
448 .parent = &ipg_clk,
449 .enable = _clk_enable,
450 .enable_reg = CCM_PCCR_GPT1_REG,
451 .enable_shift = CCM_PCCR_GPT1_OFFSET,
452 .disable = _clk_disable,
453 }, {
454 .id = 1,
455 .parent = &ipg_clk,
456 .enable = _clk_enable,
457 .enable_reg = CCM_PCCR_GPT2_REG,
458 .enable_shift = CCM_PCCR_GPT2_OFFSET,
459 .disable = _clk_disable,
460 }, {
461 .id = 2,
462 .parent = &ipg_clk,
463 .enable = _clk_enable,
464 .enable_reg = CCM_PCCR_GPT3_REG,
465 .enable_shift = CCM_PCCR_GPT3_OFFSET,
466 .disable = _clk_disable,
467 },
468};
469
470static struct clk pwm_clk[] = {
471 {
472 .parent = &per_clk[0],
473 .secondary = &pwm_clk[1],
474 }, {
475 .parent = &ipg_clk,
476 .enable = _clk_enable,
477 .enable_reg = CCM_PCCR_PWM_REG,
478 .enable_shift = CCM_PCCR_PWM_OFFSET,
479 .disable = _clk_disable,
480 },
481};
482
483static struct clk sdhc_ipg_clk[];
484
485static struct clk sdhc_clk[] = {
486 {
487 .id = 0,
488 .parent = &per_clk[1],
489 .secondary = &sdhc_ipg_clk[0],
490 }, {
491 .id = 1,
492 .parent = &per_clk[1],
493 .secondary = &sdhc_ipg_clk[1],
494 },
495};
496
497static struct clk sdhc_ipg_clk[] = {
498 {
499 .id = 0,
500 .parent = &ipg_clk,
501 .enable = _clk_enable,
502 .enable_reg = CCM_PCCR_SDHC1_REG,
503 .enable_shift = CCM_PCCR_SDHC1_OFFSET,
504 .disable = _clk_disable,
505 }, {
506 .id = 1,
507 .parent = &ipg_clk,
508 .enable = _clk_enable,
509 .enable_reg = CCM_PCCR_SDHC2_REG,
510 .enable_shift = CCM_PCCR_SDHC2_OFFSET,
511 .disable = _clk_disable,
512 },
513};
514
515static struct clk cspi_ipg_clk[];
516
517static struct clk cspi_clk[] = {
518 {
519 .id = 0,
520 .parent = &per_clk[1],
521 .secondary = &cspi_ipg_clk[0],
522 }, {
523 .id = 1,
524 .parent = &per_clk[1],
525 .secondary = &cspi_ipg_clk[1],
526 }, {
527 .id = 2,
528 .parent = &per_clk[1],
529 .secondary = &cspi_ipg_clk[2],
530 },
531};
532
533static struct clk cspi_ipg_clk[] = {
534 {
535 .id = 0,
536 .parent = &ipg_clk,
537 .enable = _clk_enable,
538 .enable_reg = CCM_PCCR_CSPI1_REG,
539 .enable_shift = CCM_PCCR_CSPI1_OFFSET,
540 .disable = _clk_disable,
541 }, {
542 .id = 1,
543 .parent = &ipg_clk,
544 .enable = _clk_enable,
545 .enable_reg = CCM_PCCR_CSPI2_REG,
546 .enable_shift = CCM_PCCR_CSPI2_OFFSET,
547 .disable = _clk_disable,
548 }, {
549 .id = 3,
550 .parent = &ipg_clk,
551 .enable = _clk_enable,
552 .enable_reg = CCM_PCCR_CSPI3_REG,
553 .enable_shift = CCM_PCCR_CSPI3_OFFSET,
554 .disable = _clk_disable,
555 },
556};
557
558static struct clk lcdc_clk[] = {
559 {
560 .parent = &per_clk[2],
561 .secondary = &lcdc_clk[1],
562 .round_rate = _clk_parent_round_rate,
563 .set_rate = _clk_parent_set_rate,
564 }, {
565 .parent = &ipg_clk,
566 .secondary = &lcdc_clk[2],
567 .enable = _clk_enable,
568 .enable_reg = CCM_PCCR_LCDC_REG,
569 .enable_shift = CCM_PCCR_LCDC_OFFSET,
570 .disable = _clk_disable,
571 }, {
572 .parent = &hclk_clk,
573 .enable = _clk_enable,
574 .enable_reg = CCM_PCCR_HCLK_LCDC_REG,
575 .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET,
576 .disable = _clk_disable,
577 },
578};
579
580static struct clk csi_clk[] = {
581 {
582 .parent = &per_clk[3],
583 .secondary = &csi_clk[1],
584 .round_rate = _clk_parent_round_rate,
585 .set_rate = _clk_parent_set_rate,
586 }, {
587 .parent = &hclk_clk,
588 .enable = _clk_enable,
589 .enable_reg = CCM_PCCR_HCLK_CSI_REG,
590 .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET,
591 .disable = _clk_disable,
592 },
593};
594
595static struct clk usb_clk[] = {
596 {
597 .parent = &spll_clk,
598 .get_rate = _clk_usb_recalc,
599 .enable = _clk_enable,
600 .enable_reg = CCM_PCCR_USBOTG_REG,
601 .enable_shift = CCM_PCCR_USBOTG_OFFSET,
602 .disable = _clk_disable,
603 }, {
604 .parent = &hclk_clk,
605 .enable = _clk_enable,
606 .enable_reg = CCM_PCCR_HCLK_USBOTG_REG,
607 .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET,
608 .disable = _clk_disable,
609 }
610};
611
612static struct clk ssi_ipg_clk[];
613
614static struct clk ssi_clk[] = {
615 {
616 .id = 0,
617 .parent = &mpll_clk,
618 .secondary = &ssi_ipg_clk[0],
619 .get_rate = _clk_ssi1_recalc,
620 .enable = _clk_enable,
621 .enable_reg = CCM_PCCR_SSI1_BAUD_REG,
622 .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET,
623 .disable = _clk_disable,
624 }, {
625 .id = 1,
626 .parent = &mpll_clk,
627 .secondary = &ssi_ipg_clk[1],
628 .get_rate = _clk_ssi2_recalc,
629 .enable = _clk_enable,
630 .enable_reg = CCM_PCCR_SSI2_BAUD_REG,
631 .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET,
632 .disable = _clk_disable,
633 },
634};
635
636static struct clk ssi_ipg_clk[] = {
637 {
638 .id = 0,
639 .parent = &ipg_clk,
640 .enable = _clk_enable,
641 .enable_reg = CCM_PCCR_SSI1_REG,
642 .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET,
643 .disable = _clk_disable,
644 }, {
645 .id = 1,
646 .parent = &ipg_clk,
647 .enable = _clk_enable,
648 .enable_reg = CCM_PCCR_SSI2_REG,
649 .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET,
650 .disable = _clk_disable,
651 },
652};
653
654
655static struct clk nfc_clk = {
656 .parent = &fclk_clk,
657 .get_rate = _clk_nfc_recalc,
658 .enable = _clk_enable,
659 .enable_reg = CCM_PCCR_NFC_REG,
660 .enable_shift = CCM_PCCR_NFC_OFFSET,
661 .disable = _clk_disable,
662};
663
664static struct clk dma_clk[] = {
665 {
666 .parent = &hclk_clk,
667 .enable = _clk_enable,
668 .enable_reg = CCM_PCCR_DMA_REG,
669 .enable_shift = CCM_PCCR_DMA_OFFSET,
670 .disable = _clk_disable,
671 .secondary = &dma_clk[1],
672 }, {
673 .enable = _clk_enable,
674 .enable_reg = CCM_PCCR_HCLK_DMA_REG,
675 .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET,
676 .disable = _clk_disable,
677 },
678};
679
680static struct clk brom_clk = {
681 .parent = &hclk_clk,
682 .enable = _clk_enable,
683 .enable_reg = CCM_PCCR_HCLK_BROM_REG,
684 .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET,
685 .disable = _clk_disable,
686};
687
688static struct clk emma_clk[] = {
689 {
690 .parent = &hclk_clk,
691 .enable = _clk_enable,
692 .enable_reg = CCM_PCCR_EMMA_REG,
693 .enable_shift = CCM_PCCR_EMMA_OFFSET,
694 .disable = _clk_disable,
695 .secondary = &emma_clk[1],
696 }, {
697 .enable = _clk_enable,
698 .enable_reg = CCM_PCCR_HCLK_EMMA_REG,
699 .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET,
700 .disable = _clk_disable,
701 }
702};
703
704static struct clk slcdc_clk[] = {
705 {
706 .parent = &hclk_clk,
707 .enable = _clk_enable,
708 .enable_reg = CCM_PCCR_SLCDC_REG,
709 .enable_shift = CCM_PCCR_SLCDC_OFFSET,
710 .disable = _clk_disable,
711 .secondary = &slcdc_clk[1],
712 }, {
713 .enable = _clk_enable,
714 .enable_reg = CCM_PCCR_HCLK_SLCDC_REG,
715 .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET,
716 .disable = _clk_disable,
717 }
718};
719
720static struct clk wdog_clk = {
721 .parent = &ipg_clk,
722 .enable = _clk_enable,
723 .enable_reg = CCM_PCCR_WDT_REG,
724 .enable_shift = CCM_PCCR_WDT_OFFSET,
725 .disable = _clk_disable,
726};
727
728static struct clk gpio_clk = {
729 .parent = &ipg_clk,
730 .enable = _clk_enable,
731 .enable_reg = CCM_PCCR_GPIO_REG,
732 .enable_shift = CCM_PCCR_GPIO_OFFSET,
733 .disable = _clk_disable,
734};
735
736static struct clk i2c_clk = {
737 .id = 0,
738 .parent = &ipg_clk,
739 .enable = _clk_enable,
740 .enable_reg = CCM_PCCR_I2C1_REG,
741 .enable_shift = CCM_PCCR_I2C1_OFFSET,
742 .disable = _clk_disable,
743};
744
745static struct clk kpp_clk = {
746 .parent = &ipg_clk,
747 .enable = _clk_enable,
748 .enable_reg = CCM_PCCR_KPP_REG,
749 .enable_shift = CCM_PCCR_KPP_OFFSET,
750 .disable = _clk_disable,
751};
752
753static struct clk owire_clk = {
754 .parent = &ipg_clk,
755 .enable = _clk_enable,
756 .enable_reg = CCM_PCCR_OWIRE_REG,
757 .enable_shift = CCM_PCCR_OWIRE_OFFSET,
758 .disable = _clk_disable,
759};
760
761static struct clk rtc_clk = {
762 .parent = &ipg_clk,
763 .enable = _clk_enable,
764 .enable_reg = CCM_PCCR_RTC_REG,
765 .enable_shift = CCM_PCCR_RTC_OFFSET,
766 .disable = _clk_disable,
767};
768
769static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
770{
771 u32 div;
772 unsigned long parent_rate;
773
774 parent_rate = clk_get_rate(clk->parent);
775 div = parent_rate / rate;
776 if (parent_rate % rate)
777 div++;
778
779 if (div > 8)
780 div = 8;
781
782 return parent_rate / div;
783}
784
785static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
786{
787 u32 reg;
788 u32 div;
789 unsigned long parent_rate;
790
791 parent_rate = clk_get_rate(clk->parent);
792
793 div = parent_rate / rate;
794
795 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
796 return -EINVAL;
797 div--;
798
799 reg = __raw_readl(CCM_PCDR0);
800
801 if (clk->parent == &usb_clk[0]) {
802 reg &= ~CCM_PCDR0_48MDIV_MASK;
803 reg |= div << CCM_PCDR0_48MDIV_OFFSET;
804 }
805 __raw_writel(reg, CCM_PCDR0);
806
807 return 0;
808}
809
810static unsigned long _clk_clko_recalc(struct clk *clk)
811{
812 u32 div = 0;
813 unsigned long parent_rate;
814
815 parent_rate = clk_get_rate(clk->parent);
816
817 if (clk->parent == &usb_clk[0]) /* 48M */
818 div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK
819 >> CCM_PCDR0_48MDIV_OFFSET;
820 div++;
821
822 return parent_rate / div;
823}
824
825static struct clk clko_clk;
826
827static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
828{
829 u32 reg;
830
831 reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
832
833 if (parent == &ckil_clk)
834 reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
835 else if (parent == &fpm_clk)
836 reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET;
837 else if (parent == &ckih_clk)
838 reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
839 else if (parent == mpll_clk.parent)
840 reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
841 else if (parent == spll_clk.parent)
842 reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
843 else if (parent == &mpll_clk)
844 reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
845 else if (parent == &spll_clk)
846 reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
847 else if (parent == &fclk_clk)
848 reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
849 else if (parent == &hclk_clk)
850 reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
851 else if (parent == &ipg_clk)
852 reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
853 else if (parent == &per_clk[0])
854 reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
855 else if (parent == &per_clk[1])
856 reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
857 else if (parent == &per_clk[2])
858 reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
859 else if (parent == &per_clk[3])
860 reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
861 else if (parent == &ssi_clk[0])
862 reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
863 else if (parent == &ssi_clk[1])
864 reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
865 else if (parent == &nfc_clk)
866 reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
867 else if (parent == &usb_clk[0])
868 reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET;
869 else if (parent == &clko_clk)
870 reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
871 else
872 return -EINVAL;
873
874 __raw_writel(reg, CCM_CCSR);
875
876 return 0;
877}
878
879static struct clk clko_clk = {
880 .get_rate = _clk_clko_recalc,
881 .set_rate = _clk_clko_set_rate,
882 .round_rate = _clk_clko_round_rate,
883 .set_parent = _clk_clko_set_parent,
884};
885
886
887#define _REGISTER_CLOCK(d, n, c) \
888 { \
889 .dev_id = d, \
890 .con_id = n, \
891 .clk = &c, \
892 },
893static struct clk_lookup lookups[] __initdata = {
894/* It's unlikely that any driver wants one of them directly:
895 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
896 _REGISTER_CLOCK(NULL, "ckil", ckil_clk)
897 _REGISTER_CLOCK(NULL, "fpm", fpm_clk)
898 _REGISTER_CLOCK(NULL, "mpll", mpll_clk)
899 _REGISTER_CLOCK(NULL, "spll", spll_clk)
900 _REGISTER_CLOCK(NULL, "fclk", fclk_clk)
901 _REGISTER_CLOCK(NULL, "hclk", hclk_clk)
902 _REGISTER_CLOCK(NULL, "ipg", ipg_clk)
903*/
904 _REGISTER_CLOCK(NULL, "perclk1", per_clk[0])
905 _REGISTER_CLOCK(NULL, "perclk2", per_clk[1])
906 _REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
907 _REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
908 _REGISTER_CLOCK(NULL, "clko", clko_clk)
909 _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
910 _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
911 _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
912 _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3])
913 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
914 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
915 _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
916 _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
917 _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
918 _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
919 _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
920 _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
921 _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
922 _REGISTER_CLOCK(NULL, "lcdc", lcdc_clk[0])
923 _REGISTER_CLOCK(NULL, "csi", csi_clk[0])
924 _REGISTER_CLOCK(NULL, "usb", usb_clk[0])
925 _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0])
926 _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1])
927 _REGISTER_CLOCK(NULL, "nfc", nfc_clk)
928 _REGISTER_CLOCK(NULL, "dma", dma_clk[0])
929 _REGISTER_CLOCK(NULL, "brom", brom_clk)
930 _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
931 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
932 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
933 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
934 _REGISTER_CLOCK(NULL, "i2c", i2c_clk)
935 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
936 _REGISTER_CLOCK(NULL, "owire", owire_clk)
937 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
938};
939
940/*
941 * must be called very early to get information about the
942 * available clock rate when the timer framework starts
943 */
944int __init mx21_clocks_init(unsigned long lref, unsigned long href)
945{
946 int i;
947 u32 cscr;
948
949 external_low_reference = lref;
950 external_high_reference = href;
951
952 /* detect clock reference for both system PLL */
953 cscr = CSCR();
954 if (cscr & CCM_CSCR_MCU)
955 mpll_clk.parent = &ckih_clk;
956 else
957 mpll_clk.parent = &fpm_clk;
958
959 if (cscr & CCM_CSCR_SP)
960 spll_clk.parent = &ckih_clk;
961 else
962 spll_clk.parent = &fpm_clk;
963
964 for (i = 0; i < ARRAY_SIZE(lookups); i++)
965 clkdev_add(&lookups[i]);
966
967 /* Turn off all clock gates */
968 __raw_writel(0, CCM_PCCR0);
969 __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1);
970
971 /* This turns of the serial PLL as well */
972 spll_clk.disable(&spll_clk);
973
974 /* This will propagate to all children and init all the clock rates. */
975 clk_enable(&per_clk[0]);
976 clk_enable(&gpio_clk);
977
978#ifdef CONFIG_DEBUG_LL_CONSOLE
979 clk_enable(&uart_clk[0]);
980#endif
981
982 mxc_timer_init(&gpt_clk[0]);
983 return 0;
984}
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index c69896d011a1..3f7280c490f0 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
4 * 5 *
5 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
@@ -20,23 +21,60 @@
20#include <linux/clk.h> 21#include <linux/clk.h>
21#include <linux/io.h> 22#include <linux/io.h>
22#include <linux/module.h> 23#include <linux/module.h>
23#include <linux/spinlock.h>
24 24
25#include <mach/clock.h> 25#include <asm/clkdev.h>
26#include <mach/common.h>
27#include <asm/div64.h> 26#include <asm/div64.h>
28 27
29#include "crm_regs.h" 28#include <mach/clock.h>
30 29#include <mach/common.h>
31static struct clk ckil_clk; 30#include <mach/hardware.h>
32static struct clk mpll_clk; 31
33static struct clk mpll_main_clk[]; 32/* Register offsets */
34static struct clk spll_clk; 33#define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0)
35 34#define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4)
36static int _clk_enable(struct clk *clk) 35#define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8)
36#define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC)
37#define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10)
38#define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14)
39#define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18)
40#define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c)
41#define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20)
42#define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24)
43#define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28)
44#define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c)
45#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
46#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
47
48#define CCM_CSCR_UPDATE_DIS (1 << 31)
49#define CCM_CSCR_SSI2 (1 << 23)
50#define CCM_CSCR_SSI1 (1 << 22)
51#define CCM_CSCR_VPU (1 << 21)
52#define CCM_CSCR_MSHC (1 << 20)
53#define CCM_CSCR_SPLLRES (1 << 19)
54#define CCM_CSCR_MPLLRES (1 << 18)
55#define CCM_CSCR_SP (1 << 17)
56#define CCM_CSCR_MCU (1 << 16)
57#define CCM_CSCR_OSC26MDIV (1 << 4)
58#define CCM_CSCR_OSC26M (1 << 3)
59#define CCM_CSCR_FPM (1 << 2)
60#define CCM_CSCR_SPEN (1 << 1)
61#define CCM_CSCR_MPEN (1 << 0)
62
63/* i.MX27 TO 2+ */
64#define CCM_CSCR_ARM_SRC (1 << 15)
65
66#define CCM_SPCTL1_LF (1 << 15)
67#define CCM_SPCTL1_BRMO (1 << 6)
68
69static struct clk mpll_main1_clk, mpll_main2_clk;
70
71static int clk_pccr_enable(struct clk *clk)
37{ 72{
38 unsigned long reg; 73 unsigned long reg;
39 74
75 if (!clk->enable_reg)
76 return 0;
77
40 reg = __raw_readl(clk->enable_reg); 78 reg = __raw_readl(clk->enable_reg);
41 reg |= 1 << clk->enable_shift; 79 reg |= 1 << clk->enable_shift;
42 __raw_writel(reg, clk->enable_reg); 80 __raw_writel(reg, clk->enable_reg);
@@ -44,16 +82,19 @@ static int _clk_enable(struct clk *clk)
44 return 0; 82 return 0;
45} 83}
46 84
47static void _clk_disable(struct clk *clk) 85static void clk_pccr_disable(struct clk *clk)
48{ 86{
49 unsigned long reg; 87 unsigned long reg;
50 88
89 if (!clk->enable_reg)
90 return;
91
51 reg = __raw_readl(clk->enable_reg); 92 reg = __raw_readl(clk->enable_reg);
52 reg &= ~(1 << clk->enable_shift); 93 reg &= ~(1 << clk->enable_shift);
53 __raw_writel(reg, clk->enable_reg); 94 __raw_writel(reg, clk->enable_reg);
54} 95}
55 96
56static int _clk_spll_enable(struct clk *clk) 97static int clk_spll_enable(struct clk *clk)
57{ 98{
58 unsigned long reg; 99 unsigned long reg;
59 100
@@ -61,13 +102,12 @@ static int _clk_spll_enable(struct clk *clk)
61 reg |= CCM_CSCR_SPEN; 102 reg |= CCM_CSCR_SPEN;
62 __raw_writel(reg, CCM_CSCR); 103 __raw_writel(reg, CCM_CSCR);
63 104
64 while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) 105 while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF));
65 ;
66 106
67 return 0; 107 return 0;
68} 108}
69 109
70static void _clk_spll_disable(struct clk *clk) 110static void clk_spll_disable(struct clk *clk)
71{ 111{
72 unsigned long reg; 112 unsigned long reg;
73 113
@@ -76,192 +116,30 @@ static void _clk_spll_disable(struct clk *clk)
76 __raw_writel(reg, CCM_CSCR); 116 __raw_writel(reg, CCM_CSCR);
77} 117}
78 118
79static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1) 119static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
80{
81 unsigned long reg;
82
83 reg = __raw_readl(CCM_PCCR0);
84 reg |= mask0;
85 __raw_writel(reg, CCM_PCCR0);
86
87 reg = __raw_readl(CCM_PCCR1);
88 reg |= mask1;
89 __raw_writel(reg, CCM_PCCR1);
90
91}
92
93static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1)
94{
95 unsigned long reg;
96
97 reg = __raw_readl(CCM_PCCR0);
98 reg &= ~mask0;
99 __raw_writel(reg, CCM_PCCR0);
100
101 reg = __raw_readl(CCM_PCCR1);
102 reg &= ~mask1;
103 __raw_writel(reg, CCM_PCCR1);
104}
105
106static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0)
107{
108 unsigned long reg;
109
110 reg = __raw_readl(CCM_PCCR1);
111 reg |= mask1;
112 __raw_writel(reg, CCM_PCCR1);
113
114 reg = __raw_readl(CCM_PCCR0);
115 reg |= mask0;
116 __raw_writel(reg, CCM_PCCR0);
117}
118
119static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0)
120{
121 unsigned long reg;
122
123 reg = __raw_readl(CCM_PCCR1);
124 reg &= ~mask1;
125 __raw_writel(reg, CCM_PCCR1);
126
127 reg = __raw_readl(CCM_PCCR0);
128 reg &= ~mask0;
129 __raw_writel(reg, CCM_PCCR0);
130}
131
132static int _clk_dma_enable(struct clk *clk)
133{
134 _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
135
136 return 0;
137}
138
139static void _clk_dma_disable(struct clk *clk)
140{
141 _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK);
142}
143
144static int _clk_rtic_enable(struct clk *clk)
145{
146 _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
147
148 return 0;
149}
150
151static void _clk_rtic_disable(struct clk *clk)
152{
153 _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK);
154}
155
156static int _clk_emma_enable(struct clk *clk)
157{
158 _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
159
160 return 0;
161}
162
163static void _clk_emma_disable(struct clk *clk)
164{
165 _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK);
166}
167
168static int _clk_slcdc_enable(struct clk *clk)
169{
170 _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
171
172 return 0;
173}
174
175static void _clk_slcdc_disable(struct clk *clk)
176{
177 _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK);
178}
179
180static int _clk_fec_enable(struct clk *clk)
181{
182 _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
183
184 return 0;
185}
186
187static void _clk_fec_disable(struct clk *clk)
188{
189 _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK);
190}
191
192static int _clk_vpu_enable(struct clk *clk)
193{
194 unsigned long reg;
195
196 reg = __raw_readl(CCM_PCCR1);
197 reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK;
198 __raw_writel(reg, CCM_PCCR1);
199
200 return 0;
201}
202
203static void _clk_vpu_disable(struct clk *clk)
204{ 120{
205 unsigned long reg; 121 int cscr = __raw_readl(CCM_CSCR);
206
207 reg = __raw_readl(CCM_PCCR1);
208 reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK);
209 __raw_writel(reg, CCM_PCCR1);
210}
211
212static int _clk_sahara2_enable(struct clk *clk)
213{
214 _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
215
216 return 0;
217}
218
219static void _clk_sahara2_disable(struct clk *clk)
220{
221 _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK);
222}
223
224static int _clk_mstick1_enable(struct clk *clk)
225{
226 _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
227
228 return 0;
229}
230
231static void _clk_mstick1_disable(struct clk *clk)
232{
233 _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK);
234}
235
236#define CSCR() (__raw_readl(CCM_CSCR))
237#define PCDR0() (__raw_readl(CCM_PCDR0))
238#define PCDR1() (__raw_readl(CCM_PCDR1))
239
240static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent)
241{
242 int cscr = CSCR();
243 122
244 if (clk->parent == parent) 123 if (clk->parent == parent)
245 return 0; 124 return 0;
246 125
247 if (mx27_revision() >= CHIP_REV_2_0) { 126 if (mx27_revision() >= CHIP_REV_2_0) {
248 if (parent == &mpll_main_clk[0]) { 127 if (parent == &mpll_main1_clk) {
249 cscr |= CCM_CSCR_ARM_SRC; 128 cscr |= CCM_CSCR_ARM_SRC;
250 } else { 129 } else {
251 if (parent == &mpll_main_clk[1]) 130 if (parent == &mpll_main2_clk)
252 cscr &= ~CCM_CSCR_ARM_SRC; 131 cscr &= ~CCM_CSCR_ARM_SRC;
253 else 132 else
254 return -EINVAL; 133 return -EINVAL;
255 } 134 }
256 __raw_writel(cscr, CCM_CSCR); 135 __raw_writel(cscr, CCM_CSCR);
257 } else 136 clk->parent = parent;
258 return -ENODEV; 137 return 0;
259 138 }
260 clk->parent = parent; 139 return -ENODEV;
261 return 0;
262} 140}
263 141
264static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) 142static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate)
265{ 143{
266 int div; 144 int div;
267 unsigned long parent_rate; 145 unsigned long parent_rate;
@@ -278,7 +156,7 @@ static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate)
278 return parent_rate / div; 156 return parent_rate / div;
279} 157}
280 158
281static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) 159static int set_rate_cpu(struct clk *clk, unsigned long rate)
282{ 160{
283 unsigned int div; 161 unsigned int div;
284 uint32_t reg; 162 uint32_t reg;
@@ -295,19 +173,18 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
295 173
296 reg = __raw_readl(CCM_CSCR); 174 reg = __raw_readl(CCM_CSCR);
297 if (mx27_revision() >= CHIP_REV_2_0) { 175 if (mx27_revision() >= CHIP_REV_2_0) {
298 reg &= ~CCM_CSCR_ARM_MASK; 176 reg &= ~(3 << 12);
299 reg |= div << CCM_CSCR_ARM_OFFSET; 177 reg |= div << 12;
300 reg &= ~0x06; 178 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
301 __raw_writel(reg | 0x80000000, CCM_CSCR); 179 __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR);
302 } else { 180 } else {
303 printk(KERN_ERR "Cant set CPU frequency!\n"); 181 printk(KERN_ERR "Can't set CPU frequency!\n");
304 } 182 }
305 183
306 return 0; 184 return 0;
307} 185}
308 186
309static unsigned long _clk_perclkx_round_rate(struct clk *clk, 187static unsigned long round_rate_per(struct clk *clk, unsigned long rate)
310 unsigned long rate)
311{ 188{
312 u32 div; 189 u32 div;
313 unsigned long parent_rate; 190 unsigned long parent_rate;
@@ -324,7 +201,7 @@ static unsigned long _clk_perclkx_round_rate(struct clk *clk,
324 return parent_rate / div; 201 return parent_rate / div;
325} 202}
326 203
327static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) 204static int set_rate_per(struct clk *clk, unsigned long rate)
328{ 205{
329 u32 reg; 206 u32 reg;
330 u32 div; 207 u32 div;
@@ -340,84 +217,65 @@ static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate)
340 return -EINVAL; 217 return -EINVAL;
341 div--; 218 div--;
342 219
343 reg = 220 reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3));
344 __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK <<
345 (clk->id << 3));
346 reg |= div << (clk->id << 3); 221 reg |= div << (clk->id << 3);
347 __raw_writel(reg, CCM_PCDR1); 222 __raw_writel(reg, CCM_PCDR1);
348 223
349 return 0; 224 return 0;
350} 225}
351 226
352static unsigned long _clk_usb_recalc(struct clk *clk) 227static unsigned long get_rate_usb(struct clk *clk)
353{ 228{
354 unsigned long usb_pdf; 229 unsigned long usb_pdf;
355 unsigned long parent_rate; 230 unsigned long parent_rate;
356 231
357 parent_rate = clk_get_rate(clk->parent); 232 parent_rate = clk_get_rate(clk->parent);
358 233
359 usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; 234 usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7;
360 235
361 return parent_rate / (usb_pdf + 1U); 236 return parent_rate / (usb_pdf + 1U);
362} 237}
363 238
364static unsigned long _clk_ssi1_recalc(struct clk *clk) 239static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
365{ 240{
366 unsigned long ssi1_pdf;
367 unsigned long parent_rate; 241 unsigned long parent_rate;
368 242
369 parent_rate = clk_get_rate(clk->parent); 243 parent_rate = clk_get_rate(clk->parent);
370 244
371 ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >>
372 CCM_PCDR0_SSI1BAUDDIV_OFFSET;
373
374 if (mx27_revision() >= CHIP_REV_2_0) 245 if (mx27_revision() >= CHIP_REV_2_0)
375 ssi1_pdf += 4; 246 pdf += 4; /* MX27 TO2+ */
376 else 247 else
377 ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf; 248 pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
378 249
379 return 2UL * parent_rate / ssi1_pdf; 250 return 2UL * parent_rate / pdf;
380} 251}
381 252
382static unsigned long _clk_ssi2_recalc(struct clk *clk) 253static unsigned long get_rate_ssi1(struct clk *clk)
383{ 254{
384 unsigned long ssi2_pdf; 255 return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f);
385 unsigned long parent_rate; 256}
386
387 parent_rate = clk_get_rate(clk->parent);
388
389 ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >>
390 CCM_PCDR0_SSI2BAUDDIV_OFFSET;
391
392 if (mx27_revision() >= CHIP_REV_2_0)
393 ssi2_pdf += 4;
394 else
395 ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf;
396 257
397 return 2UL * parent_rate / ssi2_pdf; 258static unsigned long get_rate_ssi2(struct clk *clk)
259{
260 return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f);
398} 261}
399 262
400static unsigned long _clk_nfc_recalc(struct clk *clk) 263static unsigned long get_rate_nfc(struct clk *clk)
401{ 264{
402 unsigned long nfc_pdf; 265 unsigned long nfc_pdf;
403 unsigned long parent_rate; 266 unsigned long parent_rate;
404 267
405 parent_rate = clk_get_rate(clk->parent); 268 parent_rate = clk_get_rate(clk->parent);
406 269
407 if (mx27_revision() >= CHIP_REV_2_0) { 270 if (mx27_revision() >= CHIP_REV_2_0)
408 nfc_pdf = 271 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
409 (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >> 272 else
410 CCM_PCDR0_NFCDIV2_OFFSET; 273 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
411 } else {
412 nfc_pdf =
413 (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >>
414 CCM_PCDR0_NFCDIV_OFFSET;
415 }
416 274
417 return parent_rate / (nfc_pdf + 1); 275 return parent_rate / (nfc_pdf + 1);
418} 276}
419 277
420static unsigned long _clk_vpu_recalc(struct clk *clk) 278static unsigned long get_rate_vpu(struct clk *clk)
421{ 279{
422 unsigned long vpu_pdf; 280 unsigned long vpu_pdf;
423 unsigned long parent_rate; 281 unsigned long parent_rate;
@@ -425,25 +283,27 @@ static unsigned long _clk_vpu_recalc(struct clk *clk)
425 parent_rate = clk_get_rate(clk->parent); 283 parent_rate = clk_get_rate(clk->parent);
426 284
427 if (mx27_revision() >= CHIP_REV_2_0) { 285 if (mx27_revision() >= CHIP_REV_2_0) {
428 vpu_pdf = 286 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
429 (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >>
430 CCM_PCDR0_VPUDIV2_OFFSET;
431 vpu_pdf += 4; 287 vpu_pdf += 4;
432 } else { 288 } else {
433 vpu_pdf = 289 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf;
434 (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >>
435 CCM_PCDR0_VPUDIV_OFFSET;
436 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; 290 vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf;
437 } 291 }
292
438 return 2UL * parent_rate / vpu_pdf; 293 return 2UL * parent_rate / vpu_pdf;
439} 294}
440 295
441static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) 296static unsigned long round_rate_parent(struct clk *clk, unsigned long rate)
442{ 297{
443 return clk->parent->round_rate(clk->parent, rate); 298 return clk->parent->round_rate(clk->parent, rate);
444} 299}
445 300
446static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) 301static unsigned long get_rate_parent(struct clk *clk)
302{
303 return clk_get_rate(clk->parent);
304}
305
306static int set_rate_parent(struct clk *clk, unsigned long rate)
447{ 307{
448 return clk->parent->set_rate(clk->parent, rate); 308 return clk->parent->set_rate(clk->parent, rate);
449} 309}
@@ -451,1112 +311,380 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
451/* in Hz */ 311/* in Hz */
452static unsigned long external_high_reference = 26000000; 312static unsigned long external_high_reference = 26000000;
453 313
454static unsigned long get_high_reference_clock_rate(struct clk *clk) 314static unsigned long get_rate_high_reference(struct clk *clk)
455{ 315{
456 return external_high_reference; 316 return external_high_reference;
457} 317}
458 318
459/*
460 * the high frequency external clock reference
461 * Default case is 26MHz. Could be changed at runtime
462 * with a call to change_external_high_reference()
463 */
464static struct clk ckih_clk = {
465 .name = "ckih",
466 .get_rate = get_high_reference_clock_rate,
467};
468
469/* in Hz */ 319/* in Hz */
470static unsigned long external_low_reference = 32768; 320static unsigned long external_low_reference = 32768;
471 321
472static unsigned long get_low_reference_clock_rate(struct clk *clk) 322static unsigned long get_rate_low_reference(struct clk *clk)
473{ 323{
474 return external_low_reference; 324 return external_low_reference;
475} 325}
476 326
477/* 327static unsigned long get_rate_fpm(struct clk *clk)
478 * the low frequency external clock reference
479 * Default case is 32.768kHz Could be changed at runtime
480 * with a call to change_external_low_reference()
481 */
482static struct clk ckil_clk = {
483 .name = "ckil",
484 .get_rate = get_low_reference_clock_rate,
485};
486
487static unsigned long get_mpll_clk(struct clk *clk)
488{ 328{
489 uint32_t reg; 329 return clk_get_rate(clk->parent) * 1024;
490 unsigned long ref_clk;
491 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
492 unsigned long long temp;
493
494 ref_clk = clk_get_rate(clk->parent);
495
496 reg = __raw_readl(CCM_MPCTL0);
497 pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET;
498 mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET;
499 mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET;
500 mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET;
501
502 mfi = (mfi <= 5) ? 5 : mfi;
503 temp = 2LL * ref_clk * mfn;
504 do_div(temp, mfd + 1);
505 temp = 2LL * ref_clk * mfi + temp;
506 do_div(temp, pdf + 1);
507
508 return (unsigned long)temp;
509} 330}
510 331
511static struct clk mpll_clk = { 332static unsigned long get_rate_mpll(struct clk *clk)
512 .name = "mpll", 333{
513 .parent = &ckih_clk, 334 return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
514 .get_rate = get_mpll_clk, 335 clk_get_rate(clk->parent));
515}; 336}
516 337
517static unsigned long _clk_mpll_main_get_rate(struct clk *clk) 338static unsigned long get_rate_mpll_main(struct clk *clk)
518{ 339{
519 unsigned long parent_rate; 340 unsigned long parent_rate;
520 341
521 parent_rate = clk_get_rate(clk->parent); 342 parent_rate = clk_get_rate(clk->parent);
522 343
523 /* i.MX27 TO2: 344 /* i.MX27 TO2:
524 * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2 345 * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
525 * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3 346 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
526 */ 347 */
527
528 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) 348 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1)
529 return 2UL * parent_rate / 3UL; 349 return 2UL * parent_rate / 3UL;
530 350
531 return parent_rate; 351 return parent_rate;
532} 352}
533 353
534static struct clk mpll_main_clk[] = { 354static unsigned long get_rate_spll(struct clk *clk)
535 {
536 /* For i.MX27 TO2, it is the MPLL path 1 of ARM core
537 * It provide the clock source whose rate is same as MPLL
538 */
539 .name = "mpll_main",
540 .id = 0,
541 .parent = &mpll_clk,
542 .get_rate = _clk_mpll_main_get_rate
543 }, {
544 /* For i.MX27 TO2, it is the MPLL path 2 of ARM core
545 * It provide the clock source whose rate is same MPLL * 2/3
546 */
547 .name = "mpll_main",
548 .id = 1,
549 .parent = &mpll_clk,
550 .get_rate = _clk_mpll_main_get_rate
551 }
552};
553
554static unsigned long get_spll_clk(struct clk *clk)
555{ 355{
556 uint32_t reg; 356 uint32_t reg;
557 unsigned long ref_clk; 357 unsigned long rate;
558 unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0;
559 unsigned long long temp;
560 358
561 ref_clk = clk_get_rate(clk->parent); 359 rate = clk_get_rate(clk->parent);
562 360
563 reg = __raw_readl(CCM_SPCTL0); 361 reg = __raw_readl(CCM_SPCTL0);
564 /*TODO: This is TO2 Bug */ 362
363 /* On TO2 we have to write the value back. Otherwise we
364 * read 0 from this register the next time.
365 */
565 if (mx27_revision() >= CHIP_REV_2_0) 366 if (mx27_revision() >= CHIP_REV_2_0)
566 __raw_writel(reg, CCM_SPCTL0); 367 __raw_writel(reg, CCM_SPCTL0);
567 368
568 pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; 369 return mxc_decode_pll(reg, rate);
569 mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET;
570 mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET;
571 mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET;
572
573 mfi = (mfi <= 5) ? 5 : mfi;
574 temp = 2LL * ref_clk * mfn;
575 do_div(temp, mfd + 1);
576 temp = 2LL * ref_clk * mfi + temp;
577 do_div(temp, pdf + 1);
578
579 return (unsigned long)temp;
580} 370}
581 371
582static struct clk spll_clk = { 372static unsigned long get_rate_cpu(struct clk *clk)
583 .name = "spll",
584 .parent = &ckih_clk,
585 .get_rate = get_spll_clk,
586 .enable = _clk_spll_enable,
587 .disable = _clk_spll_disable,
588};
589
590static unsigned long get_cpu_clk(struct clk *clk)
591{ 373{
592 u32 div; 374 u32 div;
593 unsigned long rate; 375 unsigned long rate;
594 376
595 if (mx27_revision() >= CHIP_REV_2_0) 377 if (mx27_revision() >= CHIP_REV_2_0)
596 div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET; 378 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
597 else 379 else
598 div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; 380 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
599 381
600 rate = clk_get_rate(clk->parent); 382 rate = clk_get_rate(clk->parent);
601 return rate / (div + 1); 383 return rate / (div + 1);
602} 384}
603 385
604static struct clk cpu_clk = { 386static unsigned long get_rate_ahb(struct clk *clk)
605 .name = "cpu_clk",
606 .parent = &mpll_main_clk[1],
607 .set_parent = _clk_cpu_set_parent,
608 .round_rate = _clk_cpu_round_rate,
609 .get_rate = get_cpu_clk,
610 .set_rate = _clk_cpu_set_rate,
611};
612
613static unsigned long get_ahb_clk(struct clk *clk)
614{ 387{
615 unsigned long rate; 388 unsigned long rate, bclk_pdf;
616 unsigned long bclk_pdf;
617 389
618 if (mx27_revision() >= CHIP_REV_2_0) 390 if (mx27_revision() >= CHIP_REV_2_0)
619 bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) 391 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
620 >> CCM_CSCR_AHB_OFFSET;
621 else 392 else
622 bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) 393 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
623 >> CCM_CSCR_BCLK_OFFSET;
624 394
625 rate = clk_get_rate(clk->parent); 395 rate = clk_get_rate(clk->parent);
626 return rate / (bclk_pdf + 1); 396 return rate / (bclk_pdf + 1);
627} 397}
628 398
629static struct clk ahb_clk = { 399static unsigned long get_rate_ipg(struct clk *clk)
630 .name = "ahb_clk",
631 .parent = &mpll_main_clk[1],
632 .get_rate = get_ahb_clk,
633};
634
635static unsigned long get_ipg_clk(struct clk *clk)
636{ 400{
637 unsigned long rate; 401 unsigned long rate, ipg_pdf;
638 unsigned long ipg_pdf;
639 402
640 if (mx27_revision() >= CHIP_REV_2_0) 403 if (mx27_revision() >= CHIP_REV_2_0)
641 return clk_get_rate(clk->parent); 404 return clk_get_rate(clk->parent);
642 else 405 else
643 ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; 406 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
644 407
645 rate = clk_get_rate(clk->parent); 408 rate = clk_get_rate(clk->parent);
646 return rate / (ipg_pdf + 1); 409 return rate / (ipg_pdf + 1);
647} 410}
648 411
649static struct clk ipg_clk = { 412static unsigned long get_rate_per(struct clk *clk)
650 .name = "ipg_clk",
651 .parent = &ahb_clk,
652 .get_rate = get_ipg_clk,
653};
654
655static unsigned long _clk_perclkx_recalc(struct clk *clk)
656{ 413{
657 unsigned long perclk_pdf; 414 unsigned long perclk_pdf, parent_rate;
658 unsigned long parent_rate;
659 415
660 parent_rate = clk_get_rate(clk->parent); 416 parent_rate = clk_get_rate(clk->parent);
661 417
662 if (clk->id < 0 || clk->id > 3) 418 if (clk->id < 0 || clk->id > 3)
663 return 0; 419 return 0;
664 420
665 perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; 421 perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f;
666 422
667 return parent_rate / (perclk_pdf + 1); 423 return parent_rate / (perclk_pdf + 1);
668} 424}
669 425
670static struct clk per_clk[] = { 426/*
671 { 427 * the high frequency external clock reference
672 .name = "per_clk", 428 * Default case is 26MHz. Could be changed at runtime
673 .id = 0, 429 * with a call to change_external_high_reference()
674 .parent = &mpll_main_clk[1], 430 */
675 .get_rate = _clk_perclkx_recalc, 431static struct clk ckih_clk = {
676 .enable = _clk_enable, 432 .get_rate = get_rate_high_reference,
677 .enable_reg = CCM_PCCR1,
678 .enable_shift = CCM_PCCR1_PERCLK1_OFFSET,
679 .disable = _clk_disable,
680 }, {
681 .name = "per_clk",
682 .id = 1,
683 .parent = &mpll_main_clk[1],
684 .get_rate = _clk_perclkx_recalc,
685 .enable = _clk_enable,
686 .enable_reg = CCM_PCCR1,
687 .enable_shift = CCM_PCCR1_PERCLK2_OFFSET,
688 .disable = _clk_disable,
689 }, {
690 .name = "per_clk",
691 .id = 2,
692 .parent = &mpll_main_clk[1],
693 .round_rate = _clk_perclkx_round_rate,
694 .set_rate = _clk_perclkx_set_rate,
695 .get_rate = _clk_perclkx_recalc,
696 .enable = _clk_enable,
697 .enable_reg = CCM_PCCR1,
698 .enable_shift = CCM_PCCR1_PERCLK3_OFFSET,
699 .disable = _clk_disable,
700 }, {
701 .name = "per_clk",
702 .id = 3,
703 .parent = &mpll_main_clk[1],
704 .round_rate = _clk_perclkx_round_rate,
705 .set_rate = _clk_perclkx_set_rate,
706 .get_rate = _clk_perclkx_recalc,
707 .enable = _clk_enable,
708 .enable_reg = CCM_PCCR1,
709 .enable_shift = CCM_PCCR1_PERCLK4_OFFSET,
710 .disable = _clk_disable,
711 },
712};
713
714struct clk uart1_clk[] = {
715 {
716 .name = "uart_clk",
717 .id = 0,
718 .parent = &per_clk[0],
719 .secondary = &uart1_clk[1],
720 }, {
721 .name = "uart_ipg_clk",
722 .id = 0,
723 .parent = &ipg_clk,
724 .enable = _clk_enable,
725 .enable_reg = CCM_PCCR1,
726 .enable_shift = CCM_PCCR1_UART1_OFFSET,
727 .disable = _clk_disable,
728 },
729};
730
731struct clk uart2_clk[] = {
732 {
733 .name = "uart_clk",
734 .id = 1,
735 .parent = &per_clk[0],
736 .secondary = &uart2_clk[1],
737 }, {
738 .name = "uart_ipg_clk",
739 .id = 1,
740 .parent = &ipg_clk,
741 .enable = _clk_enable,
742 .enable_reg = CCM_PCCR1,
743 .enable_shift = CCM_PCCR1_UART2_OFFSET,
744 .disable = _clk_disable,
745 },
746};
747
748struct clk uart3_clk[] = {
749 {
750 .name = "uart_clk",
751 .id = 2,
752 .parent = &per_clk[0],
753 .secondary = &uart3_clk[1],
754 }, {
755 .name = "uart_ipg_clk",
756 .id = 2,
757 .parent = &ipg_clk,
758 .enable = _clk_enable,
759 .enable_reg = CCM_PCCR1,
760 .enable_shift = CCM_PCCR1_UART3_OFFSET,
761 .disable = _clk_disable,
762 },
763};
764
765struct clk uart4_clk[] = {
766 {
767 .name = "uart_clk",
768 .id = 3,
769 .parent = &per_clk[0],
770 .secondary = &uart4_clk[1],
771 }, {
772 .name = "uart_ipg_clk",
773 .id = 3,
774 .parent = &ipg_clk,
775 .enable = _clk_enable,
776 .enable_reg = CCM_PCCR1,
777 .enable_shift = CCM_PCCR1_UART4_OFFSET,
778 .disable = _clk_disable,
779 },
780};
781
782struct clk uart5_clk[] = {
783 {
784 .name = "uart_clk",
785 .id = 4,
786 .parent = &per_clk[0],
787 .secondary = &uart5_clk[1],
788 }, {
789 .name = "uart_ipg_clk",
790 .id = 4,
791 .parent = &ipg_clk,
792 .enable = _clk_enable,
793 .enable_reg = CCM_PCCR1,
794 .enable_shift = CCM_PCCR1_UART5_OFFSET,
795 .disable = _clk_disable,
796 },
797};
798
799struct clk uart6_clk[] = {
800 {
801 .name = "uart_clk",
802 .id = 5,
803 .parent = &per_clk[0],
804 .secondary = &uart6_clk[1],
805 }, {
806 .name = "uart_ipg_clk",
807 .id = 5,
808 .parent = &ipg_clk,
809 .enable = _clk_enable,
810 .enable_reg = CCM_PCCR1,
811 .enable_shift = CCM_PCCR1_UART6_OFFSET,
812 .disable = _clk_disable,
813 },
814};
815
816static struct clk gpt1_clk[] = {
817 {
818 .name = "gpt_clk",
819 .id = 0,
820 .parent = &per_clk[0],
821 .secondary = &gpt1_clk[1],
822 }, {
823 .name = "gpt_ipg_clk",
824 .id = 0,
825 .parent = &ipg_clk,
826 .enable = _clk_enable,
827 .enable_reg = CCM_PCCR0,
828 .enable_shift = CCM_PCCR0_GPT1_OFFSET,
829 .disable = _clk_disable,
830 },
831};
832
833static struct clk gpt2_clk[] = {
834 {
835 .name = "gpt_clk",
836 .id = 1,
837 .parent = &per_clk[0],
838 .secondary = &gpt2_clk[1],
839 }, {
840 .name = "gpt_ipg_clk",
841 .id = 1,
842 .parent = &ipg_clk,
843 .enable = _clk_enable,
844 .enable_reg = CCM_PCCR0,
845 .enable_shift = CCM_PCCR0_GPT2_OFFSET,
846 .disable = _clk_disable,
847 },
848};
849
850static struct clk gpt3_clk[] = {
851 {
852 .name = "gpt_clk",
853 .id = 2,
854 .parent = &per_clk[0],
855 .secondary = &gpt3_clk[1],
856 }, {
857 .name = "gpt_ipg_clk",
858 .id = 2,
859 .parent = &ipg_clk,
860 .enable = _clk_enable,
861 .enable_reg = CCM_PCCR0,
862 .enable_shift = CCM_PCCR0_GPT3_OFFSET,
863 .disable = _clk_disable,
864 },
865};
866
867static struct clk gpt4_clk[] = {
868 {
869 .name = "gpt_clk",
870 .id = 3,
871 .parent = &per_clk[0],
872 .secondary = &gpt4_clk[1],
873 }, {
874 .name = "gpt_ipg_clk",
875 .id = 3,
876 .parent = &ipg_clk,
877 .enable = _clk_enable,
878 .enable_reg = CCM_PCCR0,
879 .enable_shift = CCM_PCCR0_GPT4_OFFSET,
880 .disable = _clk_disable,
881 },
882};
883
884static struct clk gpt5_clk[] = {
885 {
886 .name = "gpt_clk",
887 .id = 4,
888 .parent = &per_clk[0],
889 .secondary = &gpt5_clk[1],
890 }, {
891 .name = "gpt_ipg_clk",
892 .id = 4,
893 .parent = &ipg_clk,
894 .enable = _clk_enable,
895 .enable_reg = CCM_PCCR0,
896 .enable_shift = CCM_PCCR0_GPT5_OFFSET,
897 .disable = _clk_disable,
898 },
899}; 433};
900 434
901static struct clk gpt6_clk[] = { 435static struct clk mpll_clk = {
902 { 436 .parent = &ckih_clk,
903 .name = "gpt_clk", 437 .get_rate = get_rate_mpll,
904 .id = 5,
905 .parent = &per_clk[0],
906 .secondary = &gpt6_clk[1],
907 }, {
908 .name = "gpt_ipg_clk",
909 .id = 5,
910 .parent = &ipg_clk,
911 .enable = _clk_enable,
912 .enable_reg = CCM_PCCR0,
913 .enable_shift = CCM_PCCR0_GPT6_OFFSET,
914 .disable = _clk_disable,
915 },
916}; 438};
917 439
918static struct clk pwm_clk[] = { 440/* For i.MX27 TO2, it is the MPLL path 1 of ARM core
919 { 441 * It provides the clock source whose rate is same as MPLL
920 .name = "pwm_clk", 442 */
921 .parent = &per_clk[0], 443static struct clk mpll_main1_clk = {
922 .secondary = &pwm_clk[1], 444 .id = 0,
923 }, { 445 .parent = &mpll_clk,
924 .name = "pwm_clk", 446 .get_rate = get_rate_mpll_main,
925 .parent = &ipg_clk,
926 .enable = _clk_enable,
927 .enable_reg = CCM_PCCR0,
928 .enable_shift = CCM_PCCR0_PWM_OFFSET,
929 .disable = _clk_disable,
930 },
931}; 447};
932 448
933static struct clk sdhc1_clk[] = { 449/* For i.MX27 TO2, it is the MPLL path 2 of ARM core
934 { 450 * It provides the clock source whose rate is same MPLL * 2 / 3
935 .name = "sdhc_clk", 451 */
936 .id = 0, 452static struct clk mpll_main2_clk = {
937 .parent = &per_clk[1], 453 .id = 1,
938 .secondary = &sdhc1_clk[1], 454 .parent = &mpll_clk,
939 }, { 455 .get_rate = get_rate_mpll_main,
940 .name = "sdhc_ipg_clk",
941 .id = 0,
942 .parent = &ipg_clk,
943 .enable = _clk_enable,
944 .enable_reg = CCM_PCCR0,
945 .enable_shift = CCM_PCCR0_SDHC1_OFFSET,
946 .disable = _clk_disable,
947 },
948}; 456};
949 457
950static struct clk sdhc2_clk[] = { 458static struct clk ahb_clk = {
951 { 459 .parent = &mpll_main2_clk,
952 .name = "sdhc_clk", 460 .get_rate = get_rate_ahb,
953 .id = 1,
954 .parent = &per_clk[1],
955 .secondary = &sdhc2_clk[1],
956 }, {
957 .name = "sdhc_ipg_clk",
958 .id = 1,
959 .parent = &ipg_clk,
960 .enable = _clk_enable,
961 .enable_reg = CCM_PCCR0,
962 .enable_shift = CCM_PCCR0_SDHC2_OFFSET,
963 .disable = _clk_disable,
964 },
965}; 461};
966 462
967static struct clk sdhc3_clk[] = { 463static struct clk ipg_clk = {
968 { 464 .parent = &ahb_clk,
969 .name = "sdhc_clk", 465 .get_rate = get_rate_ipg,
970 .id = 2,
971 .parent = &per_clk[1],
972 .secondary = &sdhc3_clk[1],
973 }, {
974 .name = "sdhc_ipg_clk",
975 .id = 2,
976 .parent = &ipg_clk,
977 .enable = _clk_enable,
978 .enable_reg = CCM_PCCR0,
979 .enable_shift = CCM_PCCR0_SDHC3_OFFSET,
980 .disable = _clk_disable,
981 },
982}; 466};
983 467
984static struct clk cspi1_clk[] = { 468static struct clk cpu_clk = {
985 { 469 .parent = &mpll_main2_clk,
986 .name = "cspi_clk", 470 .set_parent = clk_cpu_set_parent,
987 .id = 0, 471 .round_rate = round_rate_cpu,
988 .parent = &per_clk[1], 472 .get_rate = get_rate_cpu,
989 .secondary = &cspi1_clk[1], 473 .set_rate = set_rate_cpu,
990 }, {
991 .name = "cspi_ipg_clk",
992 .id = 0,
993 .parent = &ipg_clk,
994 .enable = _clk_enable,
995 .enable_reg = CCM_PCCR0,
996 .enable_shift = CCM_PCCR0_CSPI1_OFFSET,
997 .disable = _clk_disable,
998 },
999}; 474};
1000 475
1001static struct clk cspi2_clk[] = { 476static struct clk spll_clk = {
1002 { 477 .parent = &ckih_clk,
1003 .name = "cspi_clk", 478 .get_rate = get_rate_spll,
1004 .id = 1, 479 .enable = clk_spll_enable,
1005 .parent = &per_clk[1], 480 .disable = clk_spll_disable,
1006 .secondary = &cspi2_clk[1],
1007 }, {
1008 .name = "cspi_ipg_clk",
1009 .id = 1,
1010 .parent = &ipg_clk,
1011 .enable = _clk_enable,
1012 .enable_reg = CCM_PCCR0,
1013 .enable_shift = CCM_PCCR0_CSPI2_OFFSET,
1014 .disable = _clk_disable,
1015 },
1016}; 481};
1017 482
1018static struct clk cspi3_clk[] = { 483/*
1019 { 484 * the low frequency external clock reference
1020 .name = "cspi_clk", 485 * Default case is 32.768kHz.
1021 .id = 2, 486 */
1022 .parent = &per_clk[1], 487static struct clk ckil_clk = {
1023 .secondary = &cspi3_clk[1], 488 .get_rate = get_rate_low_reference,
1024 }, {
1025 .name = "cspi_ipg_clk",
1026 .id = 2,
1027 .parent = &ipg_clk,
1028 .enable = _clk_enable,
1029 .enable_reg = CCM_PCCR0,
1030 .enable_shift = CCM_PCCR0_CSPI3_OFFSET,
1031 .disable = _clk_disable,
1032 },
1033}; 489};
1034 490
1035static struct clk lcdc_clk[] = { 491/* Output of frequency pre multiplier */
1036 { 492static struct clk fpm_clk = {
1037 .name = "lcdc_clk", 493 .parent = &ckil_clk,
1038 .parent = &per_clk[2], 494 .get_rate = get_rate_fpm,
1039 .secondary = &lcdc_clk[1],
1040 .round_rate = _clk_parent_round_rate,
1041 .set_rate = _clk_parent_set_rate,
1042 }, {
1043 .name = "lcdc_ipg_clk",
1044 .parent = &ipg_clk,
1045 .secondary = &lcdc_clk[2],
1046 .enable = _clk_enable,
1047 .enable_reg = CCM_PCCR0,
1048 .enable_shift = CCM_PCCR0_LCDC_OFFSET,
1049 .disable = _clk_disable,
1050 }, {
1051 .name = "lcdc_ahb_clk",
1052 .parent = &ahb_clk,
1053 .enable = _clk_enable,
1054 .enable_reg = CCM_PCCR1,
1055 .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET,
1056 .disable = _clk_disable,
1057 },
1058}; 495};
1059 496
1060static struct clk csi_clk[] = { 497#define PCCR0 CCM_PCCR0
1061 { 498#define PCCR1 CCM_PCCR1
1062 .name = "csi_perclk",
1063 .parent = &per_clk[3],
1064 .secondary = &csi_clk[1],
1065 .round_rate = _clk_parent_round_rate,
1066 .set_rate = _clk_parent_set_rate,
1067 }, {
1068 .name = "csi_ahb_clk",
1069 .parent = &ahb_clk,
1070 .enable = _clk_enable,
1071 .enable_reg = CCM_PCCR1,
1072 .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET,
1073 .disable = _clk_disable,
1074 },
1075};
1076 499
1077static struct clk usb_clk[] = { 500#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
1078 { 501 static struct clk name = { \
1079 .name = "usb_clk", 502 .id = i, \
1080 .parent = &spll_clk, 503 .enable_reg = er, \
1081 .get_rate = _clk_usb_recalc, 504 .enable_shift = es, \
1082 .enable = _clk_enable, 505 .get_rate = gr, \
1083 .enable_reg = CCM_PCCR1, 506 .enable = clk_pccr_enable, \
1084 .enable_shift = CCM_PCCR1_USBOTG_OFFSET, 507 .disable = clk_pccr_disable, \
1085 .disable = _clk_disable, 508 .secondary = s, \
1086 }, { 509 .parent = p, \
1087 .name = "usb_ahb_clk",
1088 .parent = &ahb_clk,
1089 .enable = _clk_enable,
1090 .enable_reg = CCM_PCCR1,
1091 .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET,
1092 .disable = _clk_disable,
1093 } 510 }
1094};
1095 511
1096static struct clk ssi1_clk[] = { 512#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
1097 { 513 static struct clk name = { \
1098 .name = "ssi_clk", 514 .id = i, \
1099 .id = 0, 515 .enable_reg = er, \
1100 .parent = &mpll_main_clk[1], 516 .enable_shift = es, \
1101 .secondary = &ssi1_clk[1], 517 .get_rate = get_rate_##getsetround, \
1102 .get_rate = _clk_ssi1_recalc, 518 .set_rate = set_rate_##getsetround, \
1103 .enable = _clk_enable, 519 .round_rate = round_rate_##getsetround, \
1104 .enable_reg = CCM_PCCR1, 520 .enable = clk_pccr_enable, \
1105 .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET, 521 .disable = clk_pccr_disable, \
1106 .disable = _clk_disable, 522 .secondary = s, \
1107 }, { 523 .parent = p, \
1108 .name = "ssi_ipg_clk", 524 }
1109 .id = 0,
1110 .parent = &ipg_clk,
1111 .enable = _clk_enable,
1112 .enable_reg = CCM_PCCR0,
1113 .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET,
1114 .disable = _clk_disable,
1115 },
1116};
1117 525
1118static struct clk ssi2_clk[] = { 526/* Forward declaration to keep the following list in order */
1119 { 527static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1,
1120 .name = "ssi_clk", 528 dma_clk1, lcdc_clk2, vpu_clk1;
1121 .id = 1, 529
1122 .parent = &mpll_main_clk[1], 530/* All clocks we can gate through PCCRx in the order of PCCRx bits */
1123 .secondary = &ssi2_clk[1], 531DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk);
1124 .get_rate = _clk_ssi2_recalc, 532DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk);
1125 .enable = _clk_enable, 533DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk);
1126 .enable_reg = CCM_PCCR1, 534DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk);
1127 .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET, 535DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk);
1128 .disable = _clk_disable, 536DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk);
1129 }, { 537DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk);
1130 .name = "ssi_ipg_clk", 538DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk);
1131 .id = 1, 539DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk);
1132 .parent = &ipg_clk, 540DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk);
1133 .enable = _clk_enable, 541DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk);
1134 .enable_reg = CCM_PCCR0, 542DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk);
1135 .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET, 543DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk);
1136 .disable = _clk_disable, 544DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk);
545DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk);
546DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk);
547DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk);
548DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk);
549DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
550DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk);
551DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk);
552DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk);
553DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk);
554DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk);
555DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk);
556DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk);
557DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk);
558DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk);
559DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk);
560DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk);
561DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk);
562
563DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk);
564DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk);
565DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk);
566DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk);
567DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk);
568DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk);
569DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk);
570DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk);
571DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk);
572DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk);
573DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk);
574DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk);
575DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk);
576DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk);
577DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk);
578DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk);
579DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk);
580DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk);
581DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk);
582DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk);
583DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk);
584DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk);
585DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk);
586DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk);
587DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk);
588DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk);
589DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk);
590DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk);
591DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
592DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
593
594/* Clocks we cannot directly gate, but drivers need their rates */
595DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
596DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
597DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
598DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
599DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
600DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
601DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
602DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
603DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
604DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
605DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
606DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
607DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
608DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
609DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
610DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
611DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
612DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
613DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
614DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
615DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
616
617#define _REGISTER_CLOCK(d, n, c) \
618 { \
619 .dev_id = d, \
620 .con_id = n, \
621 .clk = &c, \
1137 }, 622 },
1138};
1139
1140static struct clk nfc_clk = {
1141 .name = "nfc_clk",
1142 .parent = &cpu_clk,
1143 .get_rate = _clk_nfc_recalc,
1144 .enable = _clk_enable,
1145 .enable_reg = CCM_PCCR1,
1146 .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET,
1147 .disable = _clk_disable,
1148};
1149
1150static struct clk vpu_clk = {
1151 .name = "vpu_clk",
1152 .parent = &mpll_main_clk[1],
1153 .get_rate = _clk_vpu_recalc,
1154 .enable = _clk_vpu_enable,
1155 .disable = _clk_vpu_disable,
1156};
1157
1158static struct clk dma_clk = {
1159 .name = "dma_clk",
1160 .parent = &ahb_clk,
1161 .enable = _clk_dma_enable,
1162 .disable = _clk_dma_disable,
1163};
1164
1165static struct clk rtic_clk = {
1166 .name = "rtic_clk",
1167 .parent = &ahb_clk,
1168 .enable = _clk_rtic_enable,
1169 .disable = _clk_rtic_disable,
1170};
1171 623
1172static struct clk brom_clk = { 624static struct clk_lookup lookups[] __initdata = {
1173 .name = "brom_clk", 625 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1174 .parent = &ahb_clk, 626 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1175 .enable = _clk_enable, 627 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1176 .enable_reg = CCM_PCCR1, 628 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
1177 .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET, 629 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
1178 .disable = _clk_disable, 630 _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
1179}; 631 _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
1180 632 _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
1181static struct clk emma_clk = { 633 _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
1182 .name = "emma_clk", 634 _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk)
1183 .parent = &ahb_clk, 635 _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk)
1184 .enable = _clk_emma_enable, 636 _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk)
1185 .disable = _clk_emma_disable, 637 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk)
1186}; 638 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
1187 639 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
1188static struct clk slcdc_clk = { 640 _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
1189 .name = "slcdc_clk", 641 _REGISTER_CLOCK(NULL, "cspi1", cspi1_clk)
1190 .parent = &ahb_clk, 642 _REGISTER_CLOCK(NULL, "cspi2", cspi2_clk)
1191 .enable = _clk_slcdc_enable, 643 _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
1192 .disable = _clk_slcdc_disable, 644 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
1193}; 645 _REGISTER_CLOCK(NULL, "csi", csi_clk)
1194 646 _REGISTER_CLOCK(NULL, "usb", usb_clk)
1195static struct clk fec_clk = { 647 _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
1196 .name = "fec_clk", 648 _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
1197 .parent = &ahb_clk, 649 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
1198 .enable = _clk_fec_enable, 650 _REGISTER_CLOCK(NULL, "vpu", vpu_clk)
1199 .disable = _clk_fec_disable, 651 _REGISTER_CLOCK(NULL, "dma", dma_clk)
1200}; 652 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
1201 653 _REGISTER_CLOCK(NULL, "brom", brom_clk)
1202static struct clk emi_clk = { 654 _REGISTER_CLOCK(NULL, "emma", emma_clk)
1203 .name = "emi_clk", 655 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
1204 .parent = &ahb_clk, 656 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1205 .enable = _clk_enable, 657 _REGISTER_CLOCK(NULL, "emi", emi_clk)
1206 .enable_reg = CCM_PCCR1, 658 _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
1207 .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET, 659 _REGISTER_CLOCK(NULL, "ata", ata_clk)
1208 .disable = _clk_disable, 660 _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
1209}; 661 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
1210 662 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
1211static struct clk sahara2_clk = { 663 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1212 .name = "sahara_clk", 664 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1213 .parent = &ahb_clk, 665 _REGISTER_CLOCK(NULL, "iim", iim_clk)
1214 .enable = _clk_sahara2_enable, 666 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
1215 .disable = _clk_sahara2_disable, 667 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
1216}; 668 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
1217 669 _REGISTER_CLOCK(NULL, "scc", scc_clk)
1218static struct clk ata_clk = { 670};
1219 .name = "ata_clk", 671
1220 .parent = &ahb_clk, 672/* Adjust the clock path for TO2 and later */
1221 .enable = _clk_enable, 673static void __init to2_adjust_clocks(void)
1222 .enable_reg = CCM_PCCR1, 674{
1223 .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET, 675 unsigned long cscr = __raw_readl(CCM_CSCR);
1224 .disable = _clk_disable,
1225};
1226
1227static struct clk mstick1_clk = {
1228 .name = "mstick1_clk",
1229 .parent = &ipg_clk,
1230 .enable = _clk_mstick1_enable,
1231 .disable = _clk_mstick1_disable,
1232};
1233
1234static struct clk wdog_clk = {
1235 .name = "wdog_clk",
1236 .parent = &ipg_clk,
1237 .enable = _clk_enable,
1238 .enable_reg = CCM_PCCR1,
1239 .enable_shift = CCM_PCCR1_WDT_OFFSET,
1240 .disable = _clk_disable,
1241};
1242
1243static struct clk gpio_clk = {
1244 .name = "gpio_clk",
1245 .parent = &ipg_clk,
1246 .enable = _clk_enable,
1247 .enable_reg = CCM_PCCR1,
1248 .enable_shift = CCM_PCCR0_GPIO_OFFSET,
1249 .disable = _clk_disable,
1250};
1251
1252static struct clk i2c_clk[] = {
1253 {
1254 .name = "i2c_clk",
1255 .id = 0,
1256 .parent = &ipg_clk,
1257 .enable = _clk_enable,
1258 .enable_reg = CCM_PCCR0,
1259 .enable_shift = CCM_PCCR0_I2C1_OFFSET,
1260 .disable = _clk_disable,
1261 }, {
1262 .name = "i2c_clk",
1263 .id = 1,
1264 .parent = &ipg_clk,
1265 .enable = _clk_enable,
1266 .enable_reg = CCM_PCCR0,
1267 .enable_shift = CCM_PCCR0_I2C2_OFFSET,
1268 .disable = _clk_disable,
1269 },
1270};
1271
1272static struct clk iim_clk = {
1273 .name = "iim_clk",
1274 .parent = &ipg_clk,
1275 .enable = _clk_enable,
1276 .enable_reg = CCM_PCCR0,
1277 .enable_shift = CCM_PCCR0_IIM_OFFSET,
1278 .disable = _clk_disable,
1279};
1280
1281static struct clk kpp_clk = {
1282 .name = "kpp_clk",
1283 .parent = &ipg_clk,
1284 .enable = _clk_enable,
1285 .enable_reg = CCM_PCCR0,
1286 .enable_shift = CCM_PCCR0_KPP_OFFSET,
1287 .disable = _clk_disable,
1288};
1289
1290static struct clk owire_clk = {
1291 .name = "owire_clk",
1292 .parent = &ipg_clk,
1293 .enable = _clk_enable,
1294 .enable_reg = CCM_PCCR0,
1295 .enable_shift = CCM_PCCR0_OWIRE_OFFSET,
1296 .disable = _clk_disable,
1297};
1298
1299static struct clk rtc_clk = {
1300 .name = "rtc_clk",
1301 .parent = &ipg_clk,
1302 .enable = _clk_enable,
1303 .enable_reg = CCM_PCCR0,
1304 .enable_shift = CCM_PCCR0_RTC_OFFSET,
1305 .disable = _clk_disable,
1306};
1307
1308static struct clk scc_clk = {
1309 .name = "scc_clk",
1310 .parent = &ipg_clk,
1311 .enable = _clk_enable,
1312 .enable_reg = CCM_PCCR0,
1313 .enable_shift = CCM_PCCR0_SCC_OFFSET,
1314 .disable = _clk_disable,
1315};
1316
1317static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate)
1318{
1319 u32 div;
1320 unsigned long parent_rate;
1321
1322 parent_rate = clk_get_rate(clk->parent);
1323 div = parent_rate / rate;
1324 if (parent_rate % rate)
1325 div++;
1326
1327 if (div > 8)
1328 div = 8;
1329
1330 return parent_rate / div;
1331}
1332
1333static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
1334{
1335 u32 reg;
1336 u32 div;
1337 unsigned long parent_rate;
1338
1339 parent_rate = clk_get_rate(clk->parent);
1340
1341 div = parent_rate / rate;
1342
1343 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
1344 return -EINVAL;
1345 div--;
1346
1347 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK;
1348 reg |= div << CCM_PCDR0_CLKODIV_OFFSET;
1349 __raw_writel(reg, CCM_PCDR0);
1350
1351 return 0;
1352}
1353
1354static unsigned long _clk_clko_recalc(struct clk *clk)
1355{
1356 u32 div;
1357 unsigned long parent_rate;
1358
1359 parent_rate = clk_get_rate(clk->parent);
1360
1361 div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >>
1362 CCM_PCDR0_CLKODIV_OFFSET;
1363 div++;
1364
1365 return parent_rate / div;
1366}
1367
1368static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
1369{
1370 u32 reg;
1371
1372 reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK;
1373
1374 if (parent == &ckil_clk)
1375 reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET;
1376 else if (parent == &ckih_clk)
1377 reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET;
1378 else if (parent == mpll_clk.parent)
1379 reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET;
1380 else if (parent == spll_clk.parent)
1381 reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET;
1382 else if (parent == &mpll_clk)
1383 reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET;
1384 else if (parent == &spll_clk)
1385 reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET;
1386 else if (parent == &cpu_clk)
1387 reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET;
1388 else if (parent == &ahb_clk)
1389 reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET;
1390 else if (parent == &ipg_clk)
1391 reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET;
1392 else if (parent == &per_clk[0])
1393 reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET;
1394 else if (parent == &per_clk[1])
1395 reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET;
1396 else if (parent == &per_clk[2])
1397 reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET;
1398 else if (parent == &per_clk[3])
1399 reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET;
1400 else if (parent == &ssi1_clk[0])
1401 reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET;
1402 else if (parent == &ssi2_clk[0])
1403 reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET;
1404 else if (parent == &nfc_clk)
1405 reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET;
1406 else if (parent == &mstick1_clk)
1407 reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET;
1408 else if (parent == &vpu_clk)
1409 reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET;
1410 else if (parent == &usb_clk[0])
1411 reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET;
1412 else
1413 return -EINVAL;
1414
1415 __raw_writel(reg, CCM_CCSR);
1416
1417 return 0;
1418}
1419
1420static int _clk_clko_enable(struct clk *clk)
1421{
1422 u32 reg;
1423
1424 reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN;
1425 __raw_writel(reg, CCM_PCDR0);
1426
1427 return 0;
1428}
1429
1430static void _clk_clko_disable(struct clk *clk)
1431{
1432 u32 reg;
1433
1434 reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN;
1435 __raw_writel(reg, CCM_PCDR0);
1436}
1437
1438static struct clk clko_clk = {
1439 .name = "clko_clk",
1440 .get_rate = _clk_clko_recalc,
1441 .set_rate = _clk_clko_set_rate,
1442 .round_rate = _clk_clko_round_rate,
1443 .set_parent = _clk_clko_set_parent,
1444 .enable = _clk_clko_enable,
1445 .disable = _clk_clko_disable,
1446};
1447
1448static struct clk *mxc_clks[] = {
1449 &ckih_clk,
1450 &ckil_clk,
1451 &mpll_clk,
1452 &mpll_main_clk[0],
1453 &mpll_main_clk[1],
1454 &spll_clk,
1455 &cpu_clk,
1456 &ahb_clk,
1457 &ipg_clk,
1458 &per_clk[0],
1459 &per_clk[1],
1460 &per_clk[2],
1461 &per_clk[3],
1462 &clko_clk,
1463 &uart1_clk[0],
1464 &uart1_clk[1],
1465 &uart2_clk[0],
1466 &uart2_clk[1],
1467 &uart3_clk[0],
1468 &uart3_clk[1],
1469 &uart4_clk[0],
1470 &uart4_clk[1],
1471 &uart5_clk[0],
1472 &uart5_clk[1],
1473 &uart6_clk[0],
1474 &uart6_clk[1],
1475 &gpt1_clk[0],
1476 &gpt1_clk[1],
1477 &gpt2_clk[0],
1478 &gpt2_clk[1],
1479 &gpt3_clk[0],
1480 &gpt3_clk[1],
1481 &gpt4_clk[0],
1482 &gpt4_clk[1],
1483 &gpt5_clk[0],
1484 &gpt5_clk[1],
1485 &gpt6_clk[0],
1486 &gpt6_clk[1],
1487 &pwm_clk[0],
1488 &pwm_clk[1],
1489 &sdhc1_clk[0],
1490 &sdhc1_clk[1],
1491 &sdhc2_clk[0],
1492 &sdhc2_clk[1],
1493 &sdhc3_clk[0],
1494 &sdhc3_clk[1],
1495 &cspi1_clk[0],
1496 &cspi1_clk[1],
1497 &cspi2_clk[0],
1498 &cspi2_clk[1],
1499 &cspi3_clk[0],
1500 &cspi3_clk[1],
1501 &lcdc_clk[0],
1502 &lcdc_clk[1],
1503 &lcdc_clk[2],
1504 &csi_clk[0],
1505 &csi_clk[1],
1506 &usb_clk[0],
1507 &usb_clk[1],
1508 &ssi1_clk[0],
1509 &ssi1_clk[1],
1510 &ssi2_clk[0],
1511 &ssi2_clk[1],
1512 &nfc_clk,
1513 &vpu_clk,
1514 &dma_clk,
1515 &rtic_clk,
1516 &brom_clk,
1517 &emma_clk,
1518 &slcdc_clk,
1519 &fec_clk,
1520 &emi_clk,
1521 &sahara2_clk,
1522 &ata_clk,
1523 &mstick1_clk,
1524 &wdog_clk,
1525 &gpio_clk,
1526 &i2c_clk[0],
1527 &i2c_clk[1],
1528 &iim_clk,
1529 &kpp_clk,
1530 &owire_clk,
1531 &rtc_clk,
1532 &scc_clk,
1533};
1534
1535void __init change_external_low_reference(unsigned long new_ref)
1536{
1537 external_low_reference = new_ref;
1538}
1539
1540unsigned long __init clk_early_get_timer_rate(void)
1541{
1542 return clk_get_rate(&per_clk[0]);
1543}
1544
1545static void __init probe_mxc_clocks(void)
1546{
1547 int i;
1548 676
1549 if (mx27_revision() >= CHIP_REV_2_0) { 677 if (mx27_revision() >= CHIP_REV_2_0) {
1550 if (CSCR() & 0x8000) 678 if (cscr & CCM_CSCR_ARM_SRC)
1551 cpu_clk.parent = &mpll_main_clk[0]; 679 cpu_clk.parent = &mpll_main1_clk;
1552 680
1553 if (!(CSCR() & 0x00800000)) 681 if (!(cscr & CCM_CSCR_SSI2))
1554 ssi2_clk[0].parent = &spll_clk; 682 ssi1_clk.parent = &spll_clk;
1555 683
1556 if (!(CSCR() & 0x00400000)) 684 if (!(cscr & CCM_CSCR_SSI1))
1557 ssi1_clk[0].parent = &spll_clk; 685 ssi1_clk.parent = &spll_clk;
1558 686
1559 if (!(CSCR() & 0x00200000)) 687 if (!(cscr & CCM_CSCR_VPU))
1560 vpu_clk.parent = &spll_clk; 688 vpu_clk.parent = &spll_clk;
1561 } else { 689 } else {
1562 cpu_clk.parent = &mpll_clk; 690 cpu_clk.parent = &mpll_clk;
@@ -1565,11 +693,13 @@ static void __init probe_mxc_clocks(void)
1565 cpu_clk.set_rate = NULL; 693 cpu_clk.set_rate = NULL;
1566 ahb_clk.parent = &mpll_clk; 694 ahb_clk.parent = &mpll_clk;
1567 695
1568 for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) 696 per1_clk.parent = &mpll_clk;
1569 per_clk[i].parent = &mpll_clk; 697 per2_clk.parent = &mpll_clk;
698 per3_clk.parent = &mpll_clk;
699 per4_clk.parent = &mpll_clk;
1570 700
1571 ssi1_clk[0].parent = &mpll_clk; 701 ssi1_clk.parent = &mpll_clk;
1572 ssi2_clk[0].parent = &mpll_clk; 702 ssi2_clk.parent = &mpll_clk;
1573 703
1574 vpu_clk.parent = &mpll_clk; 704 vpu_clk.parent = &mpll_clk;
1575 } 705 }
@@ -1579,47 +709,47 @@ static void __init probe_mxc_clocks(void)
1579 * must be called very early to get information about the 709 * must be called very early to get information about the
1580 * available clock rate when the timer framework starts 710 * available clock rate when the timer framework starts
1581 */ 711 */
1582int __init mxc_clocks_init(unsigned long fref) 712int __init mx27_clocks_init(unsigned long fref)
1583{ 713{
1584 u32 cscr; 714 u32 cscr = __raw_readl(CCM_CSCR);
1585 struct clk **clkp; 715 int i;
1586 716
1587 external_high_reference = fref; 717 external_high_reference = fref;
1588 718
1589 /* detect clock reference for both system PLL */ 719 /* detect clock reference for both system PLLs */
1590 cscr = CSCR();
1591 if (cscr & CCM_CSCR_MCU) 720 if (cscr & CCM_CSCR_MCU)
1592 mpll_clk.parent = &ckih_clk; 721 mpll_clk.parent = &ckih_clk;
1593 else 722 else
1594 mpll_clk.parent = &ckil_clk; 723 mpll_clk.parent = &fpm_clk;
1595 724
1596 if (cscr & CCM_CSCR_SP) 725 if (cscr & CCM_CSCR_SP)
1597 spll_clk.parent = &ckih_clk; 726 spll_clk.parent = &ckih_clk;
1598 else 727 else
1599 spll_clk.parent = &ckil_clk; 728 spll_clk.parent = &fpm_clk;
1600 729
1601 probe_mxc_clocks(); 730 to2_adjust_clocks();
1602 731
1603 per_clk[0].enable(&per_clk[0]); 732 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1604 gpt1_clk[1].enable(&gpt1_clk[1]); 733 clkdev_add(&lookups[i]);
1605 734
1606 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 735 /* Turn off all clocks we do not need */
1607 clk_register(*clkp); 736 __raw_writel(0, CCM_PCCR0);
737 __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1);
1608 738
1609 /* Turn off all possible clocks */
1610 __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0);
1611 __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK,
1612 CCM_PCCR1);
1613 spll_clk.disable(&spll_clk); 739 spll_clk.disable(&spll_clk);
1614 740
1615 /* This will propagate to all children and init all the clock rates */ 741 /* enable basic clocks */
1616 742 clk_enable(&per1_clk);
1617 clk_enable(&emi_clk);
1618 clk_enable(&gpio_clk); 743 clk_enable(&gpio_clk);
744 clk_enable(&emi_clk);
1619 clk_enable(&iim_clk); 745 clk_enable(&iim_clk);
1620 clk_enable(&gpt1_clk[0]); 746
1621#ifdef CONFIG_DEBUG_LL_CONSOLE 747#ifdef CONFIG_DEBUG_LL_CONSOLE
1622 clk_enable(&uart1_clk[0]); 748 clk_enable(&uart1_clk);
1623#endif 749#endif
750
751 mxc_timer_init(&gpt1_clk);
752
1624 return 0; 753 return 0;
1625} 754}
755
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c
index 239308fe6652..d9e3bf9644c9 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-mx2/cpu_imx27.c
@@ -26,11 +26,11 @@
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28 28
29#include "crm_regs.h"
30
31static int cpu_silicon_rev = -1; 29static int cpu_silicon_rev = -1;
32static int cpu_partnumber; 30static int cpu_partnumber;
33 31
32#define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */
33
34static void query_silicon_parameter(void) 34static void query_silicon_parameter(void)
35{ 35{
36 u32 val; 36 u32 val;
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h
index 94644cd0a0fc..749de76b3f95 100644
--- a/arch/arm/mach-mx2/crm_regs.h
+++ b/arch/arm/mach-mx2/crm_regs.h
@@ -38,42 +38,36 @@
38#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) 38#define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30)
39#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) 39#define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34)
40 40
41#define CCM_CSCR_USB_OFFSET 28 41#define CCM_CSCR_PRESC_OFFSET 29
42#define CCM_CSCR_USB_MASK (0x7 << 28) 42#define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET)
43
44#define CCM_CSCR_USB_OFFSET 26
45#define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET)
43#define CCM_CSCR_SD_OFFSET 24 46#define CCM_CSCR_SD_OFFSET 24
44#define CCM_CSCR_SD_MASK (0x3 << 24) 47#define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET)
45#define CCM_CSCR_SSI2 (1 << 23) 48#define CCM_CSCR_SPLLRES (1 << 22)
46#define CCM_CSCR_SSI2_OFFSET 23 49#define CCM_CSCR_MPLLRES (1 << 21)
47#define CCM_CSCR_SSI1 (1 << 22) 50#define CCM_CSCR_SSI2_OFFSET 20
48#define CCM_CSCR_SSI1_OFFSET 22 51#define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET)
49#define CCM_CSCR_VPU (1 << 21) 52#define CCM_CSCR_SSI1_OFFSET 19
50#define CCM_CSCR_VPU_OFFSET 21 53#define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET)
51#define CCM_CSCR_MSHC (1 << 20) 54#define CCM_CSCR_FIR_OFFSET 18
52#define CCM_CSCR_SPLLRES (1 << 19) 55#define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET)
53#define CCM_CSCR_MPLLRES (1 << 18)
54#define CCM_CSCR_SP (1 << 17) 56#define CCM_CSCR_SP (1 << 17)
55#define CCM_CSCR_MCU (1 << 16) 57#define CCM_CSCR_MCU (1 << 16)
56/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ 58#define CCM_CSCR_BCLK_OFFSET 10
57#define CCM_CSCR_ARM_SRC (1 << 15) 59#define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET)
58#define CCM_CSCR_ARM_OFFSET 12 60#define CCM_CSCR_IPDIV_OFFSET 9
59#define CCM_CSCR_ARM_MASK (0x3 << 12) 61#define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET)
60/* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ 62
61#define CCM_CSCR_PRESC_OFFSET 13
62#define CCM_CSCR_PRESC_MASK (0x7 << 13)
63#define CCM_CSCR_BCLK_OFFSET 9
64#define CCM_CSCR_BCLK_MASK (0xf << 9)
65#define CCM_CSCR_IPDIV_OFFSET 8
66#define CCM_CSCR_IPDIV (1 << 8)
67/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
68#define CCM_CSCR_AHB_OFFSET 8
69#define CCM_CSCR_AHB_MASK (0x3 << 8)
70/* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/
71#define CCM_CSCR_OSC26MDIV (1 << 4) 63#define CCM_CSCR_OSC26MDIV (1 << 4)
72#define CCM_CSCR_OSC26M (1 << 3) 64#define CCM_CSCR_OSC26M (1 << 3)
73#define CCM_CSCR_FPM (1 << 2) 65#define CCM_CSCR_FPM (1 << 2)
74#define CCM_CSCR_SPEN (1 << 1) 66#define CCM_CSCR_SPEN (1 << 1)
75#define CCM_CSCR_MPEN 1 67#define CCM_CSCR_MPEN 1
76 68
69
70
77#define CCM_MPCTL0_CPLM (1 << 31) 71#define CCM_MPCTL0_CPLM (1 << 31)
78#define CCM_MPCTL0_PD_OFFSET 26 72#define CCM_MPCTL0_PD_OFFSET 26
79#define CCM_MPCTL0_PD_MASK (0xf << 26) 73#define CCM_MPCTL0_PD_MASK (0xf << 26)
@@ -109,25 +103,14 @@
109 103
110#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 104#define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26
111#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) 105#define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26)
112#define CCM_PCDR0_CLKO_EN 25
113#define CCM_PCDR0_CLKODIV_OFFSET 22
114#define CCM_PCDR0_CLKODIV_MASK (0x7 << 22)
115#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 106#define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16
116#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) 107#define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16)
117/*The difinition for i.MX27 TO2*/
118#define CCM_PCDR0_VPUDIV2_OFFSET 10
119#define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10)
120#define CCM_PCDR0_NFCDIV2_OFFSET 6
121#define CCM_PCDR0_NFCDIV2_MASK (0xf << 6)
122#define CCM_PCDR0_MSHCDIV2_MASK 0x3f
123/*The difinition for i.MX27 TO2*/
124#define CCM_PCDR0_NFCDIV_OFFSET 12 108#define CCM_PCDR0_NFCDIV_OFFSET 12
125#define CCM_PCDR0_NFCDIV_MASK (0xf << 12) 109#define CCM_PCDR0_NFCDIV_MASK (0xf << 12)
126#define CCM_PCDR0_VPUDIV_OFFSET 8 110#define CCM_PCDR0_48MDIV_OFFSET 5
127#define CCM_PCDR0_VPUDIV_MASK (0xf << 8) 111#define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET)
128#define CCM_PCDR0_MSHCDIV_OFFSET 0 112#define CCM_PCDR0_FIRIDIV_OFFSET 0
129#define CCM_PCDR0_MSHCDIV_MASK 0x1f 113#define CCM_PCDR0_FIRIDIV_MASK 0x1f
130
131#define CCM_PCDR1_PERDIV4_OFFSET 24 114#define CCM_PCDR1_PERDIV4_OFFSET 24
132#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) 115#define CCM_PCDR1_PERDIV4_MASK (0x3f << 24)
133#define CCM_PCDR1_PERDIV3_OFFSET 16 116#define CCM_PCDR1_PERDIV3_OFFSET 16
@@ -137,133 +120,135 @@
137#define CCM_PCDR1_PERDIV1_OFFSET 0 120#define CCM_PCDR1_PERDIV1_OFFSET 0
138#define CCM_PCDR1_PERDIV1_MASK 0x3f 121#define CCM_PCDR1_PERDIV1_MASK 0x3f
139 122
140#define CCM_PCCR0_CSPI1_OFFSET 31 123#define CCM_PCCR_HCLK_CSI_OFFSET 31
141#define CCM_PCCR0_CSPI1_MASK (1 << 31) 124#define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0
142#define CCM_PCCR0_CSPI2_OFFSET 30 125#define CCM_PCCR_HCLK_DMA_OFFSET 30
143#define CCM_PCCR0_CSPI2_MASK (1 << 30) 126#define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0
144#define CCM_PCCR0_CSPI3_OFFSET 29 127#define CCM_PCCR_HCLK_BROM_OFFSET 28
145#define CCM_PCCR0_CSPI3_MASK (1 << 29) 128#define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0
146#define CCM_PCCR0_DMA_OFFSET 28 129#define CCM_PCCR_HCLK_EMMA_OFFSET 27
147#define CCM_PCCR0_DMA_MASK (1 << 28) 130#define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0
148#define CCM_PCCR0_EMMA_OFFSET 27 131#define CCM_PCCR_HCLK_LCDC_OFFSET 26
149#define CCM_PCCR0_EMMA_MASK (1 << 27) 132#define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0
150#define CCM_PCCR0_FEC_OFFSET 26 133#define CCM_PCCR_HCLK_SLCDC_OFFSET 25
151#define CCM_PCCR0_FEC_MASK (1 << 26) 134#define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0
152#define CCM_PCCR0_GPIO_OFFSET 25 135#define CCM_PCCR_HCLK_USBOTG_OFFSET 24
153#define CCM_PCCR0_GPIO_MASK (1 << 25) 136#define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0
154#define CCM_PCCR0_GPT1_OFFSET 24 137#define CCM_PCCR_HCLK_BMI_OFFSET 23
155#define CCM_PCCR0_GPT1_MASK (1 << 24) 138#define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK)
156#define CCM_PCCR0_GPT2_OFFSET 23 139#define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0
157#define CCM_PCCR0_GPT2_MASK (1 << 23) 140#define CCM_PCCR_PERCLK4_OFFSET 22
158#define CCM_PCCR0_GPT3_OFFSET 22 141#define CCM_PCCR_PERCLK4_REG CCM_PCCR0
159#define CCM_PCCR0_GPT3_MASK (1 << 22) 142#define CCM_PCCR_SLCDC_OFFSET 21
160#define CCM_PCCR0_GPT4_OFFSET 21 143#define CCM_PCCR_SLCDC_REG CCM_PCCR0
161#define CCM_PCCR0_GPT4_MASK (1 << 21) 144#define CCM_PCCR_FIRI_BAUD_OFFSET 20
162#define CCM_PCCR0_GPT5_OFFSET 20 145#define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK)
163#define CCM_PCCR0_GPT5_MASK (1 << 20) 146#define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0
164#define CCM_PCCR0_GPT6_OFFSET 19 147#define CCM_PCCR_NFC_OFFSET 19
165#define CCM_PCCR0_GPT6_MASK (1 << 19) 148#define CCM_PCCR_NFC_REG CCM_PCCR0
166#define CCM_PCCR0_I2C1_OFFSET 18 149#define CCM_PCCR_LCDC_OFFSET 18
167#define CCM_PCCR0_I2C1_MASK (1 << 18) 150#define CCM_PCCR_LCDC_REG CCM_PCCR0
168#define CCM_PCCR0_I2C2_OFFSET 17 151#define CCM_PCCR_SSI1_BAUD_OFFSET 17
169#define CCM_PCCR0_I2C2_MASK (1 << 17) 152#define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0
170#define CCM_PCCR0_IIM_OFFSET 16 153#define CCM_PCCR_SSI2_BAUD_OFFSET 16
171#define CCM_PCCR0_IIM_MASK (1 << 16) 154#define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0
172#define CCM_PCCR0_KPP_OFFSET 15 155#define CCM_PCCR_EMMA_OFFSET 15
173#define CCM_PCCR0_KPP_MASK (1 << 15) 156#define CCM_PCCR_EMMA_REG CCM_PCCR0
174#define CCM_PCCR0_LCDC_OFFSET 14 157#define CCM_PCCR_USBOTG_OFFSET 14
175#define CCM_PCCR0_LCDC_MASK (1 << 14) 158#define CCM_PCCR_USBOTG_REG CCM_PCCR0
176#define CCM_PCCR0_MSHC_OFFSET 13 159#define CCM_PCCR_DMA_OFFSET 13
177#define CCM_PCCR0_MSHC_MASK (1 << 13) 160#define CCM_PCCR_DMA_REG CCM_PCCR0
178#define CCM_PCCR0_OWIRE_OFFSET 12 161#define CCM_PCCR_I2C1_OFFSET 12
179#define CCM_PCCR0_OWIRE_MASK (1 << 12) 162#define CCM_PCCR_I2C1_REG CCM_PCCR0
180#define CCM_PCCR0_PWM_OFFSET 11 163#define CCM_PCCR_GPIO_OFFSET 11
181#define CCM_PCCR0_PWM_MASK (1 << 11) 164#define CCM_PCCR_GPIO_REG CCM_PCCR0
182#define CCM_PCCR0_RTC_OFFSET 9 165#define CCM_PCCR_SDHC2_OFFSET 10
183#define CCM_PCCR0_RTC_MASK (1 << 9) 166#define CCM_PCCR_SDHC2_REG CCM_PCCR0
184#define CCM_PCCR0_RTIC_OFFSET 8 167#define CCM_PCCR_SDHC1_OFFSET 9
185#define CCM_PCCR0_RTIC_MASK (1 << 8) 168#define CCM_PCCR_SDHC1_REG CCM_PCCR0
186#define CCM_PCCR0_SAHARA_OFFSET 7 169#define CCM_PCCR_FIRI_OFFSET 8
187#define CCM_PCCR0_SAHARA_MASK (1 << 7) 170#define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK)
188#define CCM_PCCR0_SCC_OFFSET 6 171#define CCM_PCCR_FIRI_REG CCM_PCCR0
189#define CCM_PCCR0_SCC_MASK (1 << 6) 172#define CCM_PCCR_SSI2_IPG_OFFSET 7
190#define CCM_PCCR0_SDHC1_OFFSET 5 173#define CCM_PCCR_SSI2_REG CCM_PCCR0
191#define CCM_PCCR0_SDHC1_MASK (1 << 5) 174#define CCM_PCCR_SSI1_IPG_OFFSET 6
192#define CCM_PCCR0_SDHC2_OFFSET 4 175#define CCM_PCCR_SSI1_REG CCM_PCCR0
193#define CCM_PCCR0_SDHC2_MASK (1 << 4) 176#define CCM_PCCR_CSPI2_OFFSET 5
194#define CCM_PCCR0_SDHC3_OFFSET 3 177#define CCM_PCCR_CSPI2_REG CCM_PCCR0
195#define CCM_PCCR0_SDHC3_MASK (1 << 3) 178#define CCM_PCCR_CSPI1_OFFSET 4
196#define CCM_PCCR0_SLCDC_OFFSET 2 179#define CCM_PCCR_CSPI1_REG CCM_PCCR0
197#define CCM_PCCR0_SLCDC_MASK (1 << 2) 180#define CCM_PCCR_UART4_OFFSET 3
198#define CCM_PCCR0_SSI1_IPG_OFFSET 1 181#define CCM_PCCR_UART4_REG CCM_PCCR0
199#define CCM_PCCR0_SSI1_IPG_MASK (1 << 1) 182#define CCM_PCCR_UART3_OFFSET 2
200#define CCM_PCCR0_SSI2_IPG_OFFSET 0 183#define CCM_PCCR_UART3_REG CCM_PCCR0
201#define CCM_PCCR0_SSI2_IPG_MASK (1 << 0) 184#define CCM_PCCR_UART2_OFFSET 1
185#define CCM_PCCR_UART2_REG CCM_PCCR0
186#define CCM_PCCR_UART1_OFFSET 0
187#define CCM_PCCR_UART1_REG CCM_PCCR0
188
189#define CCM_PCCR_OWIRE_OFFSET 31
190#define CCM_PCCR_OWIRE_REG CCM_PCCR1
191#define CCM_PCCR_KPP_OFFSET 30
192#define CCM_PCCR_KPP_REG CCM_PCCR1
193#define CCM_PCCR_RTC_OFFSET 29
194#define CCM_PCCR_RTC_REG CCM_PCCR1
195#define CCM_PCCR_PWM_OFFSET 28
196#define CCM_PCCR_PWM_REG CCM_PCCR1
197#define CCM_PCCR_GPT3_OFFSET 27
198#define CCM_PCCR_GPT3_REG CCM_PCCR1
199#define CCM_PCCR_GPT2_OFFSET 26
200#define CCM_PCCR_GPT2_REG CCM_PCCR1
201#define CCM_PCCR_GPT1_OFFSET 25
202#define CCM_PCCR_GPT1_REG CCM_PCCR1
203#define CCM_PCCR_WDT_OFFSET 24
204#define CCM_PCCR_WDT_REG CCM_PCCR1
205#define CCM_PCCR_CSPI3_OFFSET 23
206#define CCM_PCCR_CSPI3_REG CCM_PCCR1
207
208#define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET)
209#define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET)
210#define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET)
211#define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET)
212#define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET)
213#define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET)
214#define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET)
215#define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET)
216#define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET)
217#define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET)
218#define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET)
219#define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET)
220#define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET)
221#define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET)
222#define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET)
223#define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET)
224#define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET)
225#define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET)
226#define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET)
227#define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET)
228#define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET)
229#define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET)
230#define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET)
231#define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET)
232#define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET)
233#define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET)
234#define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET)
235#define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET)
236#define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET)
237#define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET)
238#define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET)
239#define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET)
240#define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET)
241#define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET)
242#define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET)
243#define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET)
244#define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET)
202 245
203#define CCM_PCCR1_UART1_OFFSET 31
204#define CCM_PCCR1_UART1_MASK (1 << 31)
205#define CCM_PCCR1_UART2_OFFSET 30
206#define CCM_PCCR1_UART2_MASK (1 << 30)
207#define CCM_PCCR1_UART3_OFFSET 29
208#define CCM_PCCR1_UART3_MASK (1 << 29)
209#define CCM_PCCR1_UART4_OFFSET 28
210#define CCM_PCCR1_UART4_MASK (1 << 28)
211#define CCM_PCCR1_UART5_OFFSET 27
212#define CCM_PCCR1_UART5_MASK (1 << 27)
213#define CCM_PCCR1_UART6_OFFSET 26
214#define CCM_PCCR1_UART6_MASK (1 << 26)
215#define CCM_PCCR1_USBOTG_OFFSET 25
216#define CCM_PCCR1_USBOTG_MASK (1 << 25)
217#define CCM_PCCR1_WDT_OFFSET 24
218#define CCM_PCCR1_WDT_MASK (1 << 24)
219#define CCM_PCCR1_HCLK_ATA_OFFSET 23
220#define CCM_PCCR1_HCLK_ATA_MASK (1 << 23)
221#define CCM_PCCR1_HCLK_BROM_OFFSET 22
222#define CCM_PCCR1_HCLK_BROM_MASK (1 << 22)
223#define CCM_PCCR1_HCLK_CSI_OFFSET 21
224#define CCM_PCCR1_HCLK_CSI_MASK (1 << 21)
225#define CCM_PCCR1_HCLK_DMA_OFFSET 20
226#define CCM_PCCR1_HCLK_DMA_MASK (1 << 20)
227#define CCM_PCCR1_HCLK_EMI_OFFSET 19
228#define CCM_PCCR1_HCLK_EMI_MASK (1 << 19)
229#define CCM_PCCR1_HCLK_EMMA_OFFSET 18
230#define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18)
231#define CCM_PCCR1_HCLK_FEC_OFFSET 17
232#define CCM_PCCR1_HCLK_FEC_MASK (1 << 17)
233#define CCM_PCCR1_HCLK_VPU_OFFSET 16
234#define CCM_PCCR1_HCLK_VPU_MASK (1 << 16)
235#define CCM_PCCR1_HCLK_LCDC_OFFSET 15
236#define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15)
237#define CCM_PCCR1_HCLK_RTIC_OFFSET 14
238#define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14)
239#define CCM_PCCR1_HCLK_SAHARA_OFFSET 13
240#define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13)
241#define CCM_PCCR1_HCLK_SLCDC_OFFSET 12
242#define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12)
243#define CCM_PCCR1_HCLK_USBOTG_OFFSET 11
244#define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11)
245#define CCM_PCCR1_PERCLK1_OFFSET 10
246#define CCM_PCCR1_PERCLK1_MASK (1 << 10)
247#define CCM_PCCR1_PERCLK2_OFFSET 9
248#define CCM_PCCR1_PERCLK2_MASK (1 << 9)
249#define CCM_PCCR1_PERCLK3_OFFSET 8
250#define CCM_PCCR1_PERCLK3_MASK (1 << 8)
251#define CCM_PCCR1_PERCLK4_OFFSET 7
252#define CCM_PCCR1_PERCLK4_MASK (1 << 7)
253#define CCM_PCCR1_VPU_BAUD_OFFSET 6
254#define CCM_PCCR1_VPU_BAUD_MASK (1 << 6)
255#define CCM_PCCR1_SSI1_BAUD_OFFSET 5
256#define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5)
257#define CCM_PCCR1_SSI2_BAUD_OFFSET 4
258#define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4)
259#define CCM_PCCR1_NFC_BAUD_OFFSET 3
260#define CCM_PCCR1_NFC_BAUD_MASK (1 << 3)
261#define CCM_PCCR1_MSHC_BAUD_OFFSET 2
262#define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2)
263 246
264#define CCM_CCSR_32KSR (1 << 15) 247#define CCM_CCSR_32KSR (1 << 15)
248
265#define CCM_CCSR_CLKMODE1 (1 << 9) 249#define CCM_CCSR_CLKMODE1 (1 << 9)
266#define CCM_CCSR_CLKMODE0 (1 << 8) 250#define CCM_CCSR_CLKMODE0 (1 << 8)
251
267#define CCM_CCSR_CLKOSEL_OFFSET 0 252#define CCM_CCSR_CLKOSEL_OFFSET 0
268#define CCM_CCSR_CLKOSEL_MASK 0x1f 253#define CCM_CCSR_CLKOSEL_MASK 0x1f
269 254
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index 2f9240be1c76..f81aa8a8fbb4 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -34,6 +34,10 @@
34 34
35#include <mach/irqs.h> 35#include <mach/irqs.h>
36#include <mach/hardware.h> 36#include <mach/hardware.h>
37#include <mach/common.h>
38#include <mach/mmc.h>
39
40#include "devices.h"
37 41
38/* 42/*
39 * Resource definition for the MXC IrDA 43 * Resource definition for the MXC IrDA
@@ -225,37 +229,217 @@ struct platform_device mxc_nand_device = {
225 .resource = mxc_nand_resources, 229 .resource = mxc_nand_resources,
226}; 230};
227 231
232#ifdef CONFIG_FB_IMX
233/*
234 * lcdc:
235 * - i.MX1: the basic controller
236 * - i.MX21: to be checked
237 * - i.MX27: like i.MX1, with slightly variations
238 */
239static struct resource mxc_fb[] = {
240 {
241 .start = LCDC_BASE_ADDR,
242 .end = LCDC_BASE_ADDR + 0xFFF,
243 .flags = IORESOURCE_MEM,
244 },
245 {
246 .start = MXC_INT_LCDC,
247 .end = MXC_INT_LCDC,
248 .flags = IORESOURCE_IRQ,
249 }
250};
251
252/* mxc lcd driver */
253struct platform_device mxc_fb_device = {
254 .name = "imx-fb",
255 .id = 0,
256 .num_resources = ARRAY_SIZE(mxc_fb),
257 .resource = mxc_fb,
258 .dev = {
259 .coherent_dma_mask = 0xFFFFFFFF,
260 },
261};
262#endif
263
264#ifdef CONFIG_MACH_MX27
265static struct resource mxc_fec_resources[] = {
266 {
267 .start = FEC_BASE_ADDR,
268 .end = FEC_BASE_ADDR + 0xfff,
269 .flags = IORESOURCE_MEM
270 }, {
271 .start = MXC_INT_FEC,
272 .end = MXC_INT_FEC,
273 .flags = IORESOURCE_IRQ
274 },
275};
276
277struct platform_device mxc_fec_device = {
278 .name = "fec",
279 .id = 0,
280 .num_resources = ARRAY_SIZE(mxc_fec_resources),
281 .resource = mxc_fec_resources,
282};
283#endif
284
285static struct resource mxc_i2c_1_resources[] = {
286 [0] = {
287 .start = I2C_BASE_ADDR,
288 .end = I2C_BASE_ADDR + 0x0fff,
289 .flags = IORESOURCE_MEM
290 },
291 [1] = {
292 .start = MXC_INT_I2C,
293 .end = MXC_INT_I2C,
294 .flags = IORESOURCE_IRQ
295 }
296};
297
298struct platform_device mxc_i2c_device0 = {
299 .name = "imx-i2c",
300 .id = 0,
301 .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
302 .resource = mxc_i2c_1_resources
303};
304
305#ifdef CONFIG_MACH_MX27
306static struct resource mxc_i2c_2_resources[] = {
307 [0] = {
308 .start = I2C2_BASE_ADDR,
309 .end = I2C2_BASE_ADDR + 0x0fff,
310 .flags = IORESOURCE_MEM
311 },
312 [1] = {
313 .start = MXC_INT_I2C2,
314 .end = MXC_INT_I2C2,
315 .flags = IORESOURCE_IRQ
316 }
317};
318
319struct platform_device mxc_i2c_device1 = {
320 .name = "imx-i2c",
321 .id = 1,
322 .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
323 .resource = mxc_i2c_2_resources
324};
325#endif
326
327static struct resource mxc_pwm_resources[] = {
328 [0] = {
329 .start = PWM_BASE_ADDR,
330 .end = PWM_BASE_ADDR + 0x0fff,
331 .flags = IORESOURCE_MEM
332 },
333 [1] = {
334 .start = MXC_INT_PWM,
335 .end = MXC_INT_PWM,
336 .flags = IORESOURCE_IRQ,
337 }
338};
339
340struct platform_device mxc_pwm_device = {
341 .name = "mxc_pwm",
342 .id = 0,
343 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
344 .resource = mxc_pwm_resources
345};
346
347/*
348 * Resource definition for the MXC SDHC
349 */
350static struct resource mxc_sdhc1_resources[] = {
351 [0] = {
352 .start = SDHC1_BASE_ADDR,
353 .end = SDHC1_BASE_ADDR + SZ_4K - 1,
354 .flags = IORESOURCE_MEM,
355 },
356 [1] = {
357 .start = MXC_INT_SDHC1,
358 .end = MXC_INT_SDHC1,
359 .flags = IORESOURCE_IRQ,
360 },
361 [2] = {
362 .start = DMA_REQ_SDHC1,
363 .end = DMA_REQ_SDHC1,
364 .flags = IORESOURCE_DMA
365 },
366};
367
368static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
369
370struct platform_device mxc_sdhc_device0 = {
371 .name = "mxc-mmc",
372 .id = 0,
373 .dev = {
374 .dma_mask = &mxc_sdhc1_dmamask,
375 .coherent_dma_mask = 0xffffffff,
376 },
377 .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
378 .resource = mxc_sdhc1_resources,
379};
380
381static struct resource mxc_sdhc2_resources[] = {
382 [0] = {
383 .start = SDHC2_BASE_ADDR,
384 .end = SDHC2_BASE_ADDR + SZ_4K - 1,
385 .flags = IORESOURCE_MEM,
386 },
387 [1] = {
388 .start = MXC_INT_SDHC2,
389 .end = MXC_INT_SDHC2,
390 .flags = IORESOURCE_IRQ,
391 },
392 [2] = {
393 .start = DMA_REQ_SDHC2,
394 .end = DMA_REQ_SDHC2,
395 .flags = IORESOURCE_DMA
396 },
397};
398
399static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
400
401struct platform_device mxc_sdhc_device1 = {
402 .name = "mxc-mmc",
403 .id = 1,
404 .dev = {
405 .dma_mask = &mxc_sdhc2_dmamask,
406 .coherent_dma_mask = 0xffffffff,
407 },
408 .num_resources = ARRAY_SIZE(mxc_sdhc2_resources),
409 .resource = mxc_sdhc2_resources,
410};
411
228/* GPIO port description */ 412/* GPIO port description */
229static struct mxc_gpio_port imx_gpio_ports[] = { 413static struct mxc_gpio_port imx_gpio_ports[] = {
230 [0] = { 414 [0] = {
231 .chip.label = "gpio-0", 415 .chip.label = "gpio-0",
232 .irq = MXC_INT_GPIO, 416 .irq = MXC_INT_GPIO,
233 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), 417 .base = IO_ADDRESS(GPIO_BASE_ADDR),
234 .virtual_irq_start = MXC_GPIO_IRQ_START, 418 .virtual_irq_start = MXC_GPIO_IRQ_START,
235 }, 419 },
236 [1] = { 420 [1] = {
237 .chip.label = "gpio-1", 421 .chip.label = "gpio-1",
238 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), 422 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
239 .virtual_irq_start = MXC_GPIO_IRQ_START + 32, 423 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
240 }, 424 },
241 [2] = { 425 [2] = {
242 .chip.label = "gpio-2", 426 .chip.label = "gpio-2",
243 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), 427 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
244 .virtual_irq_start = MXC_GPIO_IRQ_START + 64, 428 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
245 }, 429 },
246 [3] = { 430 [3] = {
247 .chip.label = "gpio-3", 431 .chip.label = "gpio-3",
248 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), 432 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
249 .virtual_irq_start = MXC_GPIO_IRQ_START + 96, 433 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
250 }, 434 },
251 [4] = { 435 [4] = {
252 .chip.label = "gpio-4", 436 .chip.label = "gpio-4",
253 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), 437 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
254 .virtual_irq_start = MXC_GPIO_IRQ_START + 128, 438 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
255 }, 439 },
256 [5] = { 440 [5] = {
257 .chip.label = "gpio-5", 441 .chip.label = "gpio-5",
258 .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), 442 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
259 .virtual_irq_start = MXC_GPIO_IRQ_START + 160, 443 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
260 } 444 }
261}; 445};
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 1e8cb577a642..049005bb6aa9 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -1,4 +1,3 @@
1
2extern struct platform_device mxc_gpt1; 1extern struct platform_device mxc_gpt1;
3extern struct platform_device mxc_gpt2; 2extern struct platform_device mxc_gpt2;
4extern struct platform_device mxc_gpt3; 3extern struct platform_device mxc_gpt3;
@@ -14,3 +13,10 @@ extern struct platform_device mxc_uart_device4;
14extern struct platform_device mxc_uart_device5; 13extern struct platform_device mxc_uart_device5;
15extern struct platform_device mxc_w1_master_device; 14extern struct platform_device mxc_w1_master_device;
16extern struct platform_device mxc_nand_device; 15extern struct platform_device mxc_nand_device;
16extern struct platform_device mxc_fb_device;
17extern struct platform_device mxc_fec_device;
18extern struct platform_device mxc_pwm_device;
19extern struct platform_device mxc_i2c_device0;
20extern struct platform_device mxc_i2c_device1;
21extern struct platform_device mxc_sdhc_device0;
22extern struct platform_device mxc_sdhc_device1;
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index dea6521d4d5c..bd51dd04948e 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -21,6 +21,7 @@
21#include <linux/mm.h> 21#include <linux/mm.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/common.h>
24#include <asm/pgtable.h> 25#include <asm/pgtable.h>
25#include <asm/mach/map.h> 26#include <asm/mach/map.h>
26 27
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 2b5c67f54571..4a3b097adc12 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -31,7 +31,7 @@
31#include <asm/mach/map.h> 31#include <asm/mach/map.h>
32#include <mach/gpio.h> 32#include <mach/gpio.h>
33#include <mach/imx-uart.h> 33#include <mach/imx-uart.h>
34#include <mach/iomux-mx1-mx2.h> 34#include <mach/iomux.h>
35#include <mach/board-mx27ads.h> 35#include <mach/board-mx27ads.h>
36 36
37#include "devices.h" 37#include "devices.h"
@@ -135,6 +135,7 @@ static int uart_mxc_port3_exit(struct platform_device *pdev)
135{ 135{
136 mxc_gpio_release_multiple_pins(mxc_uart3_pins, 136 mxc_gpio_release_multiple_pins(mxc_uart3_pins,
137 ARRAY_SIZE(mxc_uart3_pins)); 137 ARRAY_SIZE(mxc_uart3_pins));
138 return 0;
138} 139}
139 140
140static int mxc_uart4_pins[] = { 141static int mxc_uart4_pins[] = {
@@ -179,6 +180,7 @@ static int uart_mxc_port5_exit(struct platform_device *pdev)
179 180
180static struct platform_device *platform_devices[] __initdata = { 181static struct platform_device *platform_devices[] __initdata = {
181 &mx27ads_nor_mtd_device, 182 &mx27ads_nor_mtd_device,
183 &mxc_fec_device,
182}; 184};
183 185
184static int mxc_fec_pins[] = { 186static int mxc_fec_pins[] = {
@@ -196,7 +198,7 @@ static int mxc_fec_pins[] = {
196 PD11_AOUT_FEC_TX_CLK, 198 PD11_AOUT_FEC_TX_CLK,
197 PD12_AOUT_FEC_RXD0, 199 PD12_AOUT_FEC_RXD0,
198 PD13_AOUT_FEC_RX_DV, 200 PD13_AOUT_FEC_RX_DV,
199 PD14_AOUT_FEC_CLR, 201 PD14_AOUT_FEC_RX_CLK,
200 PD15_AOUT_FEC_COL, 202 PD15_AOUT_FEC_COL,
201 PD16_AIN_FEC_TX_ER, 203 PD16_AIN_FEC_TX_ER,
202 PF23_AIN_FEC_TX_EN 204 PF23_AIN_FEC_TX_EN
@@ -208,12 +210,6 @@ static void gpio_fec_active(void)
208 ARRAY_SIZE(mxc_fec_pins), "FEC"); 210 ARRAY_SIZE(mxc_fec_pins), "FEC");
209} 211}
210 212
211static void gpio_fec_inactive(void)
212{
213 mxc_gpio_release_multiple_pins(mxc_fec_pins,
214 ARRAY_SIZE(mxc_fec_pins));
215}
216
217static struct imxuart_platform_data uart_pdata[] = { 213static struct imxuart_platform_data uart_pdata[] = {
218 { 214 {
219 .init = uart_mxc_port0_init, 215 .init = uart_mxc_port0_init,
@@ -263,11 +259,10 @@ static void __init mx27ads_timer_init(void)
263 if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) 259 if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0)
264 fref = 27000000; 260 fref = 27000000;
265 261
266 mxc_clocks_init(fref); 262 mx27_clocks_init(fref);
267 mxc_timer_init("gpt_clk.0");
268} 263}
269 264
270struct sys_timer mx27ads_timer = { 265static struct sys_timer mx27ads_timer = {
271 .init = mx27ads_timer_init, 266 .init = mx27ads_timer_init,
272}; 267};
273 268
@@ -280,7 +275,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = {
280 }, 275 },
281}; 276};
282 277
283void __init mx27ads_map_io(void) 278static void __init mx27ads_map_io(void)
284{ 279{
285 mxc_map_io(); 280 mxc_map_io();
286 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); 281 iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc));
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index dfd4156da7d5..aa4eaa61d1b5 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -20,11 +20,18 @@
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/mtd/physmap.h> 21#include <linux/mtd/physmap.h>
22#include <linux/mtd/plat-ram.h> 22#include <linux/mtd/plat-ram.h>
23#include <linux/io.h>
24#include <linux/i2c.h>
25#include <linux/i2c/at24.h>
26
23#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
24#include <asm/mach-types.h> 28#include <asm/mach-types.h>
25#include <mach/common.h> 29#include <mach/common.h>
26#include <mach/hardware.h> 30#include <mach/hardware.h>
27#include <mach/iomux-mx1-mx2.h> 31#include <mach/iomux.h>
32#ifdef CONFIG_I2C_IMX
33#include <mach/i2c.h>
34#endif
28#include <asm/mach/time.h> 35#include <asm/mach/time.h>
29#include <mach/imx-uart.h> 36#include <mach/imx-uart.h>
30#include <mach/board-pcm038.h> 37#include <mach/board-pcm038.h>
@@ -121,10 +128,10 @@ static int uart_mxc_port1_exit(struct platform_device *pdev)
121 return 0; 128 return 0;
122} 129}
123 130
124static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, 131static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
125 PE9_PF_UART3_RXD, 132 PE9_PF_UART3_RXD,
126 PE10_PF_UART3_CTS, 133 PE10_PF_UART3_CTS,
127 PE9_PF_UART3_RXD }; 134 PE11_PF_UART3_RTS };
128 135
129static int uart_mxc_port2_init(struct platform_device *pdev) 136static int uart_mxc_port2_init(struct platform_device *pdev)
130{ 137{
@@ -170,7 +177,7 @@ static int mxc_fec_pins[] = {
170 PD11_AOUT_FEC_TX_CLK, 177 PD11_AOUT_FEC_TX_CLK,
171 PD12_AOUT_FEC_RXD0, 178 PD12_AOUT_FEC_RXD0,
172 PD13_AOUT_FEC_RX_DV, 179 PD13_AOUT_FEC_RX_DV,
173 PD14_AOUT_FEC_CLR, 180 PD14_AOUT_FEC_RX_CLK,
174 PD15_AOUT_FEC_COL, 181 PD15_AOUT_FEC_COL,
175 PD16_AIN_FEC_TX_ER, 182 PD16_AIN_FEC_TX_ER,
176 PF23_AIN_FEC_TX_EN 183 PF23_AIN_FEC_TX_EN
@@ -182,12 +189,6 @@ static void gpio_fec_active(void)
182 ARRAY_SIZE(mxc_fec_pins), "FEC"); 189 ARRAY_SIZE(mxc_fec_pins), "FEC");
183} 190}
184 191
185static void gpio_fec_inactive(void)
186{
187 mxc_gpio_release_multiple_pins(mxc_fec_pins,
188 ARRAY_SIZE(mxc_fec_pins));
189}
190
191static struct mxc_nand_platform_data pcm038_nand_board_info = { 192static struct mxc_nand_platform_data pcm038_nand_board_info = {
192 .width = 1, 193 .width = 1,
193 .hw_ecc = 1, 194 .hw_ecc = 1,
@@ -196,6 +197,7 @@ static struct mxc_nand_platform_data pcm038_nand_board_info = {
196static struct platform_device *platform_devices[] __initdata = { 197static struct platform_device *platform_devices[] __initdata = {
197 &pcm038_nor_mtd_device, 198 &pcm038_nor_mtd_device,
198 &mxc_w1_master_device, 199 &mxc_w1_master_device,
200 &mxc_fec_device,
199 &pcm038_sram_mtd_device, 201 &pcm038_sram_mtd_device,
200}; 202};
201 203
@@ -208,6 +210,51 @@ static void __init pcm038_init_sram(void)
208 __raw_writel(0x22220a00, CSCR_A(1)); 210 __raw_writel(0x22220a00, CSCR_A(1));
209} 211}
210 212
213#ifdef CONFIG_I2C_IMX
214static int mxc_i2c1_pins[] = {
215 PC5_PF_I2C2_SDA,
216 PC6_PF_I2C2_SCL
217};
218
219static int pcm038_i2c_1_init(struct device *dev)
220{
221 return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
222 "I2C1");
223}
224
225static void pcm038_i2c_1_exit(struct device *dev)
226{
227 mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
228}
229
230static struct imxi2c_platform_data pcm038_i2c_1_data = {
231 .bitrate = 100000,
232 .init = pcm038_i2c_1_init,
233 .exit = pcm038_i2c_1_exit,
234};
235
236static struct at24_platform_data board_eeprom = {
237 .byte_len = 4096,
238 .page_size = 32,
239 .flags = AT24_FLAG_ADDR16,
240};
241
242static struct i2c_board_info pcm038_i2c_devices[] = {
243 [0] = {
244 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
245 .platform_data = &board_eeprom,
246 },
247 [1] = {
248 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
249 .type = "pcf8563"
250 },
251 [2] = {
252 I2C_BOARD_INFO("lm75", 0x4a),
253 .type = "lm75"
254 }
255};
256#endif
257
211static void __init pcm038_init(void) 258static void __init pcm038_init(void)
212{ 259{
213 gpio_fec_active(); 260 gpio_fec_active();
@@ -217,9 +264,17 @@ static void __init pcm038_init(void)
217 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); 264 mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
218 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); 265 mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
219 266
220 mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ 267 mxc_gpio_mode(PE16_AF_OWIRE);
221 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); 268 mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
222 269
270#ifdef CONFIG_I2C_IMX
271 /* only the i2c master 1 is used on this CPU card */
272 i2c_register_board_info(1, pcm038_i2c_devices,
273 ARRAY_SIZE(pcm038_i2c_devices));
274
275 mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
276#endif
277
223 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 278 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
224 279
225#ifdef CONFIG_MACH_PCM970_BASEBOARD 280#ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -229,11 +284,10 @@ static void __init pcm038_init(void)
229 284
230static void __init pcm038_timer_init(void) 285static void __init pcm038_timer_init(void)
231{ 286{
232 mxc_clocks_init(26000000); 287 mx27_clocks_init(26000000);
233 mxc_timer_init("gpt_clk.0");
234} 288}
235 289
236struct sys_timer pcm038_timer = { 290static struct sys_timer pcm038_timer = {
237 .init = pcm038_timer_init, 291 .init = pcm038_timer_init,
238}; 292};
239 293
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index a560cd6ad23d..bf4e520bc1bc 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -17,9 +17,138 @@
17 */ 17 */
18 18
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <mach/hardware.h> 20#include <linux/gpio.h>
21#include <linux/irq.h>
22
21#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
22 24
25#include <mach/hardware.h>
26#include <mach/common.h>
27#include <mach/mmc.h>
28#include <mach/imxfb.h>
29#include <mach/iomux.h>
30
31#include "devices.h"
32
33static int pcm970_sdhc2_get_ro(struct device *dev)
34{
35 return gpio_get_value(GPIO_PORTC + 28);
36}
37
38static int pcm970_sdhc2_pins[] = {
39 PB4_PF_SD2_D0,
40 PB5_PF_SD2_D1,
41 PB6_PF_SD2_D2,
42 PB7_PF_SD2_D3,
43 PB8_PF_SD2_CMD,
44 PB9_PF_SD2_CLK,
45};
46
47static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data)
48{
49 int ret;
50
51 ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins,
52 ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2");
53 if(ret)
54 return ret;
55
56 ret = request_irq(IRQ_GPIOC(29), detect_irq, 0,
57 "imx-mmc-detect", data);
58 if (ret)
59 goto out_release_gpio;
60
61 set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING);
62
63 ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro");
64 if (ret)
65 goto out_release_gpio;
66
67 mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN);
68 gpio_direction_input(GPIO_PORTC + 28);
69
70 return 0;
71
72out_release_gpio:
73 mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
74 ARRAY_SIZE(pcm970_sdhc2_pins));
75 return ret;
76}
77
78static void pcm970_sdhc2_exit(struct device *dev, void *data)
79{
80 free_irq(IRQ_GPIOC(29), data);
81 gpio_free(GPIO_PORTC + 28);
82 mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins,
83 ARRAY_SIZE(pcm970_sdhc2_pins));
84}
85
86static struct imxmmc_platform_data sdhc_pdata = {
87 .get_ro = pcm970_sdhc2_get_ro,
88 .init = pcm970_sdhc2_init,
89 .exit = pcm970_sdhc2_exit,
90};
91
92static int mxc_fb_pins[] = {
93 PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2,
94 PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6,
95 PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10,
96 PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14,
97 PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV,
98 PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC,
99 PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD
100};
101
102static int pcm038_fb_init(struct platform_device *pdev)
103{
104 return mxc_gpio_setup_multiple_pins(mxc_fb_pins,
105 ARRAY_SIZE(mxc_fb_pins), "FB");
106}
107
108static int pcm038_fb_exit(struct platform_device *pdev)
109{
110 mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins));
111
112 return 0;
113}
114
115/*
116 * Connected is a portrait Sharp-QVGA display
117 * of type: LQ035Q7DH06
118 */
119static struct imx_fb_platform_data pcm038_fb_data = {
120 .pixclock = 188679, /* in ps (5.3MHz) */
121 .xres = 240,
122 .yres = 320,
123
124 .bpp = 16,
125 .hsync_len = 7,
126 .left_margin = 5,
127 .right_margin = 16,
128
129 .vsync_len = 1,
130 .upper_margin = 7,
131 .lower_margin = 9,
132 .fixed_screen_cpu = 0,
133
134 /*
135 * - HSYNC active high
136 * - VSYNC active high
137 * - clk notenabled while idle
138 * - clock not inverted
139 * - data not inverted
140 * - data enable low active
141 * - enable sharp mode
142 */
143 .pcr = 0xFA0080C0,
144 .pwmr = 0x00A903FF,
145 .lscr1 = 0x00120300,
146 .dmacr = 0x00020010,
147
148 .init = pcm038_fb_init,
149 .exit = pcm038_fb_exit,
150};
151
23/* 152/*
24 * system init for baseboard usage. Will be called by pcm038 init. 153 * system init for baseboard usage. Will be called by pcm038 init.
25 * 154 *
@@ -28,4 +157,6 @@
28 */ 157 */
29void __init pcm970_baseboard_init(void) 158void __init pcm970_baseboard_init(void)
30{ 159{
160 mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
161 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
31} 162}
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
index 16debc296dad..40a485cdc10e 100644
--- a/arch/arm/mach-mx2/serial.c
+++ b/arch/arm/mach-mx2/serial.c
@@ -22,6 +22,7 @@
22#include <linux/serial.h> 22#include <linux/serial.h>
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <mach/imx-uart.h> 24#include <mach/imx-uart.h>
25#include "devices.h"
25 26
26static struct resource uart0[] = { 27static struct resource uart0[] = {
27 { 28 {
@@ -99,6 +100,7 @@ struct platform_device mxc_uart_device3 = {
99 .num_resources = ARRAY_SIZE(uart3), 100 .num_resources = ARRAY_SIZE(uart3),
100}; 101};
101 102
103#ifdef CONFIG_MACH_MX27
102static struct resource uart4[] = { 104static struct resource uart4[] = {
103 { 105 {
104 .start = UART5_BASE_ADDR, 106 .start = UART5_BASE_ADDR,
@@ -136,3 +138,4 @@ struct platform_device mxc_uart_device5 = {
136 .resource = uart5, 138 .resource = uart5,
137 .num_resources = ARRAY_SIZE(uart5), 139 .num_resources = ARRAY_SIZE(uart5),
138}; 140};
141#endif
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index e79659e8176e..d6235583e979 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,21 +1,40 @@
1menu "MX3 Options" 1if ARCH_MX3
2 depends on ARCH_MX3 2
3config ARCH_MX31
4 bool
5
6config ARCH_MX35
7 bool
8
9comment "MX3 platforms:"
3 10
4config MACH_MX31ADS 11config MACH_MX31ADS
5 bool "Support MX31ADS platforms" 12 bool "Support MX31ADS platforms"
13 select ARCH_MX31
6 default y 14 default y
7 help 15 help
8 Include support for MX31ADS platform. This includes specific 16 Include support for MX31ADS platform. This includes specific
9 configurations for the board and its peripherals. 17 configurations for the board and its peripherals.
10 18
19config MACH_MX31ADS_WM1133_EV1
20 bool "Support Wolfson Microelectronics 1133-EV1 module"
21 depends on MACH_MX31ADS
22 select MFD_WM8350_CONFIG_MODE_0
23 select MFD_WM8352_CONFIG_MODE_0
24 help
25 Include support for the Wolfson Microelectronics 1133-EV1 PMU
26 and audio module for the MX31ADS platform.
27
11config MACH_PCM037 28config MACH_PCM037
12 bool "Support Phytec pcm037 platforms" 29 bool "Support Phytec pcm037 (i.MX31) platforms"
30 select ARCH_MX31
13 help 31 help
14 Include support for Phytec pcm037 platform. This includes 32 Include support for Phytec pcm037 platform. This includes
15 specific configurations for the board and its peripherals. 33 specific configurations for the board and its peripherals.
16 34
17config MACH_MX31LITE 35config MACH_MX31LITE
18 bool "Support MX31 LITEKIT (LogicPD)" 36 bool "Support MX31 LITEKIT (LogicPD)"
37 select ARCH_MX31
19 default n 38 default n
20 help 39 help
21 Include support for MX31 LITEKIT platform. This includes specific 40 Include support for MX31 LITEKIT platform. This includes specific
@@ -23,6 +42,7 @@ config MACH_MX31LITE
23 42
24config MACH_MX31_3DS 43config MACH_MX31_3DS
25 bool "Support MX31PDK (3DS)" 44 bool "Support MX31PDK (3DS)"
45 select ARCH_MX31
26 default n 46 default n
27 help 47 help
28 Include support for MX31PDK (3DS) platform. This includes specific 48 Include support for MX31PDK (3DS) platform. This includes specific
@@ -30,10 +50,18 @@ config MACH_MX31_3DS
30 50
31config MACH_MX31MOBOARD 51config MACH_MX31MOBOARD
32 bool "Support mx31moboard platforms (EPFL Mobots group)" 52 bool "Support mx31moboard platforms (EPFL Mobots group)"
53 select ARCH_MX31
33 default n 54 default n
34 help 55 help
35 Include support for mx31moboard platform. This includes specific 56 Include support for mx31moboard platform. This includes specific
36 configurations for the board and its peripherals. 57 configurations for the board and its peripherals.
37 58
38endmenu 59config MACH_QONG
60 bool "Support Dave/DENX QongEVB-LITE platform"
61 select ARCH_MX31
62 default n
63 help
64 Include support for Dave/DENX QongEVB-LITE platform. This includes
65 specific configurations for the board and its peripherals.
39 66
67endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5a151540fe83..272c8a953b30 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -4,9 +4,13 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o clock.o devices.o iomux.o 7obj-y := mm.o devices.o
8obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o
9obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
8obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o 10obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
9obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o 11obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
10obj-$(CONFIG_MACH_PCM037) += pcm037.o 12obj-$(CONFIG_MACH_PCM037) += pcm037.o
11obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o 13obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o
12obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o 14obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \
15 mx31moboard-marxbot.o
16obj-$(CONFIG_MACH_QONG) += qong.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
new file mode 100644
index 000000000000..53a112d4e04a
--- /dev/null
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -0,0 +1,487 @@
1/*
2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <asm/clkdev.h>
26
27#include <mach/clock.h>
28#include <mach/hardware.h>
29#include <mach/common.h>
30
31#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
32
33#define CCM_CCMR 0x00
34#define CCM_PDR0 0x04
35#define CCM_PDR1 0x08
36#define CCM_PDR2 0x0C
37#define CCM_PDR3 0x10
38#define CCM_PDR4 0x14
39#define CCM_RCSR 0x18
40#define CCM_MPCTL 0x1C
41#define CCM_PPCTL 0x20
42#define CCM_ACMR 0x24
43#define CCM_COSR 0x28
44#define CCM_CGR0 0x2C
45#define CCM_CGR1 0x30
46#define CCM_CGR2 0x34
47#define CCM_CGR3 0x38
48
49#ifdef HAVE_SET_RATE_SUPPORT
50static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
51{
52 u32 min_pre, temp_pre, old_err, err;
53
54 min_pre = (div - 1) / maxpost + 1;
55 old_err = 8;
56
57 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
58 if (div > (temp_pre * maxpost))
59 break;
60
61 if (div < (temp_pre * temp_pre))
62 continue;
63
64 err = div % temp_pre;
65
66 if (err == 0) {
67 *pre = temp_pre;
68 break;
69 }
70
71 err = temp_pre - err;
72
73 if (err < old_err) {
74 old_err = err;
75 *pre = temp_pre;
76 }
77 }
78
79 *post = (div + *pre - 1) / *pre;
80}
81
82/* get the best values for a 3-bit divider combined with a 6-bit divider */
83static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
84{
85 if (div >= 512) {
86 *pre = 8;
87 *post = 64;
88 } else if (div >= 64) {
89 calc_dividers(div, pre, post, 64);
90 } else if (div <= 8) {
91 *pre = div;
92 *post = 1;
93 } else {
94 *pre = 1;
95 *post = div;
96 }
97}
98
99/* get the best values for two cascaded 3-bit dividers */
100static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
101{
102 if (div >= 64) {
103 *pre = *post = 8;
104 } else if (div > 8) {
105 calc_dividers(div, pre, post, 8);
106 } else {
107 *pre = 1;
108 *post = div;
109 }
110}
111#endif
112
113static unsigned long get_rate_mpll(void)
114{
115 ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
116
117 return mxc_decode_pll(mpctl, 24000000);
118}
119
120static unsigned long get_rate_ppll(void)
121{
122 ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
123
124 return mxc_decode_pll(ppctl, 24000000);
125}
126
127struct arm_ahb_div {
128 unsigned char arm, ahb, sel;
129};
130
131static struct arm_ahb_div clk_consumer[] = {
132 { .arm = 1, .ahb = 4, .sel = 0},
133 { .arm = 1, .ahb = 3, .sel = 1},
134 { .arm = 2, .ahb = 2, .sel = 0},
135 { .arm = 0, .ahb = 0, .sel = 0},
136 { .arm = 0, .ahb = 0, .sel = 0},
137 { .arm = 0, .ahb = 0, .sel = 0},
138 { .arm = 4, .ahb = 1, .sel = 0},
139 { .arm = 1, .ahb = 5, .sel = 0},
140 { .arm = 1, .ahb = 8, .sel = 0},
141 { .arm = 1, .ahb = 6, .sel = 1},
142 { .arm = 2, .ahb = 4, .sel = 0},
143 { .arm = 0, .ahb = 0, .sel = 0},
144 { .arm = 0, .ahb = 0, .sel = 0},
145 { .arm = 0, .ahb = 0, .sel = 0},
146 { .arm = 4, .ahb = 2, .sel = 0},
147 { .arm = 0, .ahb = 0, .sel = 0},
148};
149
150static struct arm_ahb_div clk_automotive[] = {
151 { .arm = 1, .ahb = 3, .sel = 0},
152 { .arm = 1, .ahb = 2, .sel = 1},
153 { .arm = 2, .ahb = 1, .sel = 1},
154 { .arm = 0, .ahb = 0, .sel = 0},
155 { .arm = 1, .ahb = 6, .sel = 0},
156 { .arm = 1, .ahb = 4, .sel = 1},
157 { .arm = 2, .ahb = 2, .sel = 1},
158 { .arm = 0, .ahb = 0, .sel = 0},
159};
160
161static unsigned long get_rate_arm(void)
162{
163 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
164 struct arm_ahb_div *aad;
165 unsigned long fref = get_rate_mpll();
166
167 if (pdr0 & 1) {
168 /* consumer path */
169 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
170 if (aad->sel)
171 fref = fref * 2 / 3;
172 } else {
173 /* auto path */
174 aad = &clk_automotive[(pdr0 >> 9) & 0x7];
175 if (aad->sel)
176 fref = fref * 3 / 4;
177 }
178 return fref / aad->arm;
179}
180
181static unsigned long get_rate_ahb(struct clk *clk)
182{
183 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
184 struct arm_ahb_div *aad;
185 unsigned long fref = get_rate_mpll();
186
187 if (pdr0 & 1)
188 /* consumer path */
189 aad = &clk_consumer[(pdr0 >> 16) & 0xf];
190 else
191 /* auto path */
192 aad = &clk_automotive[(pdr0 >> 9) & 0x7];
193
194 return fref / aad->ahb;
195}
196
197static unsigned long get_rate_ipg(struct clk *clk)
198{
199 return get_rate_ahb(NULL) >> 1;
200}
201
202static unsigned long get_3_3_div(unsigned long in)
203{
204 return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1);
205}
206
207static unsigned long get_rate_uart(struct clk *clk)
208{
209 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
210 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
211 unsigned long div = get_3_3_div(pdr4 >> 10);
212
213 if (pdr3 & (1 << 14))
214 return get_rate_arm() / div;
215 else
216 return get_rate_ppll() / div;
217}
218
219static unsigned long get_rate_sdhc(struct clk *clk)
220{
221 unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
222 unsigned long div, rate;
223
224 if (pdr3 & (1 << 6))
225 rate = get_rate_arm();
226 else
227 rate = get_rate_ppll();
228
229 switch (clk->id) {
230 default:
231 case 0:
232 div = pdr3 & 0x3f;
233 break;
234 case 1:
235 div = (pdr3 >> 8) & 0x3f;
236 break;
237 case 2:
238 div = (pdr3 >> 16) & 0x3f;
239 break;
240 }
241
242 return rate / get_3_3_div(div);
243}
244
245static unsigned long get_rate_mshc(struct clk *clk)
246{
247 unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
248 unsigned long div1, div2, rate;
249
250 if (pdr1 & (1 << 7))
251 rate = get_rate_arm();
252 else
253 rate = get_rate_ppll();
254
255 div1 = (pdr1 >> 29) & 0x7;
256 div2 = (pdr1 >> 22) & 0x3f;
257
258 return rate / ((div1 + 1) * (div2 + 1));
259}
260
261static unsigned long get_rate_ssi(struct clk *clk)
262{
263 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
264 unsigned long div1, div2, rate;
265
266 if (pdr2 & (1 << 6))
267 rate = get_rate_arm();
268 else
269 rate = get_rate_ppll();
270
271 switch (clk->id) {
272 default:
273 case 0:
274 div1 = pdr2 & 0x3f;
275 div2 = (pdr2 >> 24) & 0x7;
276 break;
277 case 1:
278 div1 = (pdr2 >> 8) & 0x3f;
279 div2 = (pdr2 >> 27) & 0x7;
280 break;
281 }
282
283 return rate / ((div1 + 1) * (div2 + 1));
284}
285
286static unsigned long get_rate_csi(struct clk *clk)
287{
288 unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
289 unsigned long rate;
290
291 if (pdr2 & (1 << 7))
292 rate = get_rate_arm();
293 else
294 rate = get_rate_ppll();
295
296 return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
297}
298
299static unsigned long get_rate_ipg_per(struct clk *clk)
300{
301 unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
302 unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
303 unsigned long div1, div2;
304
305 if (pdr0 & (1 << 26)) {
306 div1 = (pdr4 >> 19) & 0x7;
307 div2 = (pdr4 >> 16) & 0x7;
308 return get_rate_arm() / ((div1 + 1) * (div2 + 1));
309 } else {
310 div1 = (pdr0 >> 12) & 0x7;
311 return get_rate_ahb(NULL) / div1;
312 }
313}
314
315static int clk_cgr_enable(struct clk *clk)
316{
317 u32 reg;
318
319 reg = __raw_readl(clk->enable_reg);
320 reg |= 3 << clk->enable_shift;
321 __raw_writel(reg, clk->enable_reg);
322
323 return 0;
324}
325
326static void clk_cgr_disable(struct clk *clk)
327{
328 u32 reg;
329
330 reg = __raw_readl(clk->enable_reg);
331 reg &= ~(3 << clk->enable_shift);
332 __raw_writel(reg, clk->enable_reg);
333}
334
335#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
336 static struct clk name = { \
337 .id = i, \
338 .enable_reg = CCM_BASE + er, \
339 .enable_shift = es, \
340 .get_rate = gr, \
341 .set_rate = sr, \
342 .enable = clk_cgr_enable, \
343 .disable = clk_cgr_disable, \
344 }
345
346DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
347DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
348DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL);
349DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
350DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
351DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
352DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
353DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
354DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
355DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
356DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL);
357DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL);
358DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
359DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
360DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
361DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
362
363DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL);
364DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL);
365DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL);
366DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL);
367DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL);
368DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
369DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
370DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
371DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
372DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL);
373DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
374DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
375DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
376DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
377DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
378DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL);
379
380DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
381DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
382DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
383DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
384DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
385DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
386DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
387DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
388DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
389DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
390DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
391DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL);
392DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
393DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
394DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL);
395
396DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
397DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
398DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
399
400#define _REGISTER_CLOCK(d, n, c) \
401 { \
402 .dev_id = d, \
403 .con_id = n, \
404 .clk = &c, \
405 },
406
407static struct clk_lookup lookups[] __initdata = {
408 _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
409 _REGISTER_CLOCK(NULL, "ata", ata_clk)
410 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
411 _REGISTER_CLOCK(NULL, "can", can1_clk)
412 _REGISTER_CLOCK(NULL, "can", can2_clk)
413 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
414 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
415 _REGISTER_CLOCK(NULL, "ect", ect_clk)
416 _REGISTER_CLOCK(NULL, "edio", edio_clk)
417 _REGISTER_CLOCK(NULL, "emi", emi_clk)
418 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
419 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
420 _REGISTER_CLOCK(NULL, "esai", esai_clk)
421 _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk)
422 _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk)
423 _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk)
424 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
425 _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
426 _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
427 _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
428 _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
429 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
430 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
431 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
432 _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
433 _REGISTER_CLOCK(NULL, "ipu", ipu_clk)
434 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
435 _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
436 _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
437 _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
438 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
439 _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
440 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
441 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
442 _REGISTER_CLOCK(NULL, "scc", scc_clk)
443 _REGISTER_CLOCK(NULL, "sdma", sdma_clk)
444 _REGISTER_CLOCK(NULL, "spba", spba_clk)
445 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
446 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
447 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
448 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
449 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
450 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
451 _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk)
452 _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
453 _REGISTER_CLOCK(NULL, "max", max_clk)
454 _REGISTER_CLOCK(NULL, "admux", admux_clk)
455 _REGISTER_CLOCK(NULL, "csi", csi_clk)
456 _REGISTER_CLOCK(NULL, "iim", iim_clk)
457 _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
458};
459
460int __init mx35_clocks_init()
461{
462 int i;
463 unsigned int ll = 0;
464
465 mxc_set_cpu_type(MXC_CPU_MX35);
466
467#ifdef CONFIG_DEBUG_LL_CONSOLE
468 ll = (3 << 16);
469#endif
470
471 for (i = 0; i < ARRAY_SIZE(lookups); i++)
472 clkdev_add(&lookups[i]);
473
474 /* Turn off all clocks except the ones we need to survive, namely:
475 * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
476 */
477 __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
478 __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
479 CCM_BASE + CCM_CGR1);
480 __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
481 __raw_writel(0, CCM_BASE + CCM_CGR3);
482
483 mxc_timer_init(&gpt_clk);
484
485 return 0;
486}
487
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index b1746aae1f89..ca46f4801c3d 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -23,9 +23,13 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/io.h> 25#include <linux/io.h>
26
27#include <asm/clkdev.h>
28#include <asm/div64.h>
29
26#include <mach/clock.h> 30#include <mach/clock.h>
27#include <mach/hardware.h> 31#include <mach/hardware.h>
28#include <asm/div64.h> 32#include <mach/common.h>
29 33
30#include "crm_regs.h" 34#include "crm_regs.h"
31 35
@@ -64,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
64} 68}
65 69
66static struct clk mcu_pll_clk; 70static struct clk mcu_pll_clk;
67static struct clk mcu_main_clk;
68static struct clk usb_pll_clk;
69static struct clk serial_pll_clk; 71static struct clk serial_pll_clk;
70static struct clk ipg_clk; 72static struct clk ipg_clk;
71static struct clk ckih_clk; 73static struct clk ckih_clk;
72static struct clk ahb_clk;
73 74
74static int _clk_enable(struct clk *clk) 75static int cgr_enable(struct clk *clk)
75{ 76{
76 u32 reg; 77 u32 reg;
77 78
79 if (!clk->enable_reg)
80 return 0;
81
78 reg = __raw_readl(clk->enable_reg); 82 reg = __raw_readl(clk->enable_reg);
79 reg |= 3 << clk->enable_shift; 83 reg |= 3 << clk->enable_shift;
80 __raw_writel(reg, clk->enable_reg); 84 __raw_writel(reg, clk->enable_reg);
@@ -82,133 +86,69 @@ static int _clk_enable(struct clk *clk)
82 return 0; 86 return 0;
83} 87}
84 88
85static void _clk_disable(struct clk *clk) 89static void cgr_disable(struct clk *clk)
86{ 90{
87 u32 reg; 91 u32 reg;
88 92
93 if (!clk->enable_reg)
94 return;
95
89 reg = __raw_readl(clk->enable_reg); 96 reg = __raw_readl(clk->enable_reg);
90 reg &= ~(3 << clk->enable_shift); 97 reg &= ~(3 << clk->enable_shift);
98
99 /* special case for EMI clock */
100 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
101 reg |= (1 << clk->enable_shift);
102
91 __raw_writel(reg, clk->enable_reg); 103 __raw_writel(reg, clk->enable_reg);
92} 104}
93 105
94static void _clk_emi_disable(struct clk *clk) 106static unsigned long pll_ref_get_rate(void)
95{ 107{
96 u32 reg; 108 unsigned long ccmr;
109 unsigned int prcs;
97 110
98 reg = __raw_readl(clk->enable_reg); 111 ccmr = __raw_readl(MXC_CCM_CCMR);
99 reg &= ~(3 << clk->enable_shift); 112 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
100 reg |= (1 << clk->enable_shift); 113 if (prcs == 0x1)
101 __raw_writel(reg, clk->enable_reg); 114 return CKIL_CLK_FREQ * 1024;
115 else
116 return clk_get_rate(&ckih_clk);
102} 117}
103 118
104static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) 119static unsigned long usb_pll_get_rate(struct clk *clk)
105{ 120{
106 u32 reg; 121 unsigned long reg;
107 signed long pd = 1; /* Pre-divider */
108 signed long mfi; /* Multiplication Factor (Integer part) */
109 signed long mfn; /* Multiplication Factor (Integer part) */
110 signed long mfd; /* Multiplication Factor (Denominator Part) */
111 signed long tmp;
112 u32 ref_freq = clk_get_rate(clk->parent);
113 122
114 while (((ref_freq / pd) * 10) > rate) 123 reg = __raw_readl(MXC_CCM_UPCTL);
115 pd++;
116 124
117 if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) 125 return mxc_decode_pll(reg, pll_ref_get_rate());
118 return -EINVAL; 126}
119 127
120 /* the ref_freq/2 in the following is to round up */ 128static unsigned long serial_pll_get_rate(struct clk *clk)
121 mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; 129{
122 if (mfi < 5 || mfi > 15) 130 unsigned long reg;
123 return -EINVAL;
124 131
125 /* pick a mfd value that will work 132 reg = __raw_readl(MXC_CCM_SRPCTL);
126 * then solve for mfn */
127 mfd = ref_freq / 50000;
128
129 /*
130 * pll_freq * pd * mfd
131 * mfn = -------------------- - (mfi * mfd)
132 * 2 * ref_freq
133 */
134 /* the tmp/2 is for rounding */
135 tmp = ref_freq / 10000;
136 mfn =
137 ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
138 (mfi * mfd);
139
140 mfn = mfn & 0x3ff;
141 pd--;
142 mfd--;
143
144 /* Change the Pll value */
145 reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
146 (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
147 (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
148
149 if (clk == &mcu_pll_clk)
150 __raw_writel(reg, MXC_CCM_MPCTL);
151 else if (clk == &usb_pll_clk)
152 __raw_writel(reg, MXC_CCM_UPCTL);
153 else if (clk == &serial_pll_clk)
154 __raw_writel(reg, MXC_CCM_SRPCTL);
155 133
156 return 0; 134 return mxc_decode_pll(reg, pll_ref_get_rate());
157} 135}
158 136
159static unsigned long _clk_pll_get_rate(struct clk *clk) 137static unsigned long mcu_pll_get_rate(struct clk *clk)
160{ 138{
161 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
162 unsigned long reg, ccmr; 139 unsigned long reg, ccmr;
163 s64 temp;
164 unsigned int prcs;
165 140
166 ccmr = __raw_readl(MXC_CCM_CCMR); 141 ccmr = __raw_readl(MXC_CCM_CCMR);
167 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
168 if (prcs == 0x1)
169 ref_clk = CKIL_CLK_FREQ * 1024;
170 else
171 ref_clk = clk_get_rate(&ckih_clk);
172
173 if (clk == &mcu_pll_clk) {
174 if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
175 return ref_clk;
176 if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
177 return ref_clk;
178 reg = __raw_readl(MXC_CCM_MPCTL);
179 } else if (clk == &usb_pll_clk)
180 reg = __raw_readl(MXC_CCM_UPCTL);
181 else if (clk == &serial_pll_clk)
182 reg = __raw_readl(MXC_CCM_SRPCTL);
183 else {
184 BUG();
185 return 0;
186 }
187
188 pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET;
189 mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET;
190 mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET;
191 mfi = (mfi <= 5) ? 5 : mfi;
192 mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK;
193 142
194 if (mfn >= 0x200) { 143 if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
195 mfn |= 0xFFFFFE00; 144 return clk_get_rate(&ckih_clk);
196 mfn_abs = -mfn;
197 }
198
199 ref_clk *= 2;
200 ref_clk /= pdf + 1;
201 145
202 temp = (u64) ref_clk * mfn_abs; 146 reg = __raw_readl(MXC_CCM_MPCTL);
203 do_div(temp, mfd + 1);
204 if (mfn < 0)
205 temp = -temp;
206 temp = (ref_clk * mfi) + temp;
207 147
208 return temp; 148 return mxc_decode_pll(reg, pll_ref_get_rate());
209} 149}
210 150
211static int _clk_usb_pll_enable(struct clk *clk) 151static int usb_pll_enable(struct clk *clk)
212{ 152{
213 u32 reg; 153 u32 reg;
214 154
@@ -222,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk)
222 return 0; 162 return 0;
223} 163}
224 164
225static void _clk_usb_pll_disable(struct clk *clk) 165static void usb_pll_disable(struct clk *clk)
226{ 166{
227 u32 reg; 167 u32 reg;
228 168
@@ -231,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk)
231 __raw_writel(reg, MXC_CCM_CCMR); 171 __raw_writel(reg, MXC_CCM_CCMR);
232} 172}
233 173
234static int _clk_serial_pll_enable(struct clk *clk) 174static int serial_pll_enable(struct clk *clk)
235{ 175{
236 u32 reg; 176 u32 reg;
237 177
@@ -245,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk)
245 return 0; 185 return 0;
246} 186}
247 187
248static void _clk_serial_pll_disable(struct clk *clk) 188static void serial_pll_disable(struct clk *clk)
249{ 189{
250 u32 reg; 190 u32 reg;
251 191
@@ -258,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk)
258#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) 198#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
259#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) 199#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
260 200
261static unsigned long _clk_mcu_main_get_rate(struct clk *clk) 201static unsigned long mcu_main_get_rate(struct clk *clk)
262{ 202{
263 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); 203 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
264 204
@@ -268,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
268 return clk_get_rate(&mcu_pll_clk); 208 return clk_get_rate(&mcu_pll_clk);
269} 209}
270 210
271static unsigned long _clk_hclk_get_rate(struct clk *clk) 211static unsigned long ahb_get_rate(struct clk *clk)
272{ 212{
273 unsigned long max_pdf; 213 unsigned long max_pdf;
274 214
@@ -277,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk)
277 return clk_get_rate(clk->parent) / (max_pdf + 1); 217 return clk_get_rate(clk->parent) / (max_pdf + 1);
278} 218}
279 219
280static unsigned long _clk_ipg_get_rate(struct clk *clk) 220static unsigned long ipg_get_rate(struct clk *clk)
281{ 221{
282 unsigned long ipg_pdf; 222 unsigned long ipg_pdf;
283 223
@@ -286,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk)
286 return clk_get_rate(clk->parent) / (ipg_pdf + 1); 226 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
287} 227}
288 228
289static unsigned long _clk_nfc_get_rate(struct clk *clk) 229static unsigned long nfc_get_rate(struct clk *clk)
290{ 230{
291 unsigned long nfc_pdf; 231 unsigned long nfc_pdf;
292 232
@@ -295,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk)
295 return clk_get_rate(clk->parent) / (nfc_pdf + 1); 235 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
296} 236}
297 237
298static unsigned long _clk_hsp_get_rate(struct clk *clk) 238static unsigned long hsp_get_rate(struct clk *clk)
299{ 239{
300 unsigned long hsp_pdf; 240 unsigned long hsp_pdf;
301 241
@@ -304,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk)
304 return clk_get_rate(clk->parent) / (hsp_pdf + 1); 244 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
305} 245}
306 246
307static unsigned long _clk_usb_get_rate(struct clk *clk) 247static unsigned long usb_get_rate(struct clk *clk)
308{ 248{
309 unsigned long usb_pdf, usb_prepdf; 249 unsigned long usb_pdf, usb_prepdf;
310 250
@@ -315,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk)
315 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); 255 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
316} 256}
317 257
318static unsigned long _clk_csi_get_rate(struct clk *clk) 258static unsigned long csi_get_rate(struct clk *clk)
319{ 259{
320 u32 reg, pre, post; 260 u32 reg, pre, post;
321 261
@@ -329,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk)
329 return clk_get_rate(clk->parent) / (pre * post); 269 return clk_get_rate(clk->parent) / (pre * post);
330} 270}
331 271
332static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) 272static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
333{ 273{
334 u32 pre, post, parent = clk_get_rate(clk->parent); 274 u32 pre, post, parent = clk_get_rate(clk->parent);
335 u32 div = parent / rate; 275 u32 div = parent / rate;
@@ -342,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
342 return parent / (pre * post); 282 return parent / (pre * post);
343} 283}
344 284
345static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) 285static int csi_set_rate(struct clk *clk, unsigned long rate)
346{ 286{
347 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 287 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
348 288
@@ -363,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
363 return 0; 303 return 0;
364} 304}
365 305
366static unsigned long _clk_per_get_rate(struct clk *clk) 306static unsigned long ssi1_get_rate(struct clk *clk)
367{
368 unsigned long per_pdf;
369
370 per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
371 MXC_CCM_PDR0_PER_PODF_OFFSET);
372 return clk_get_rate(clk->parent) / (per_pdf + 1);
373}
374
375static unsigned long _clk_ssi1_get_rate(struct clk *clk)
376{ 307{
377 unsigned long ssi1_pdf, ssi1_prepdf; 308 unsigned long ssi1_pdf, ssi1_prepdf;
378 309
@@ -383,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk)
383 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); 314 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
384} 315}
385 316
386static unsigned long _clk_ssi2_get_rate(struct clk *clk) 317static unsigned long ssi2_get_rate(struct clk *clk)
387{ 318{
388 unsigned long ssi2_pdf, ssi2_prepdf; 319 unsigned long ssi2_pdf, ssi2_prepdf;
389 320
@@ -394,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk)
394 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); 325 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
395} 326}
396 327
397static unsigned long _clk_firi_get_rate(struct clk *clk) 328static unsigned long firi_get_rate(struct clk *clk)
398{ 329{
399 unsigned long firi_pdf, firi_prepdf; 330 unsigned long firi_pdf, firi_prepdf;
400 331
@@ -405,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk)
405 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); 336 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
406} 337}
407 338
408static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) 339static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
409{ 340{
410 u32 pre, post; 341 u32 pre, post;
411 u32 parent = clk_get_rate(clk->parent); 342 u32 parent = clk_get_rate(clk->parent);
@@ -420,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
420 351
421} 352}
422 353
423static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) 354static int firi_set_rate(struct clk *clk, unsigned long rate)
424{ 355{
425 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 356 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
426 357
@@ -441,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
441 return 0; 372 return 0;
442} 373}
443 374
444static unsigned long _clk_mbx_get_rate(struct clk *clk) 375static unsigned long mbx_get_rate(struct clk *clk)
445{ 376{
446 return clk_get_rate(clk->parent) / 2; 377 return clk_get_rate(clk->parent) / 2;
447} 378}
448 379
449static unsigned long _clk_mstick1_get_rate(struct clk *clk) 380static unsigned long mstick1_get_rate(struct clk *clk)
450{ 381{
451 unsigned long msti_pdf; 382 unsigned long msti_pdf;
452 383
@@ -455,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk)
455 return clk_get_rate(clk->parent) / (msti_pdf + 1); 386 return clk_get_rate(clk->parent) / (msti_pdf + 1);
456} 387}
457 388
458static unsigned long _clk_mstick2_get_rate(struct clk *clk) 389static unsigned long mstick2_get_rate(struct clk *clk)
459{ 390{
460 unsigned long msti_pdf; 391 unsigned long msti_pdf;
461 392
@@ -472,661 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
472} 403}
473 404
474static struct clk ckih_clk = { 405static struct clk ckih_clk = {
475 .name = "ckih",
476 .get_rate = clk_ckih_get_rate, 406 .get_rate = clk_ckih_get_rate,
477}; 407};
478 408
479static unsigned long clk_ckil_get_rate(struct clk *clk)
480{
481 return CKIL_CLK_FREQ;
482}
483
484static struct clk ckil_clk = {
485 .name = "ckil",
486 .get_rate = clk_ckil_get_rate,
487};
488
489static struct clk mcu_pll_clk = { 409static struct clk mcu_pll_clk = {
490 .name = "mcu_pll",
491 .parent = &ckih_clk, 410 .parent = &ckih_clk,
492 .set_rate = _clk_pll_set_rate, 411 .get_rate = mcu_pll_get_rate,
493 .get_rate = _clk_pll_get_rate,
494}; 412};
495 413
496static struct clk mcu_main_clk = { 414static struct clk mcu_main_clk = {
497 .name = "mcu_main_clk",
498 .parent = &mcu_pll_clk, 415 .parent = &mcu_pll_clk,
499 .get_rate = _clk_mcu_main_get_rate, 416 .get_rate = mcu_main_get_rate,
500}; 417};
501 418
502static struct clk serial_pll_clk = { 419static struct clk serial_pll_clk = {
503 .name = "serial_pll",
504 .parent = &ckih_clk, 420 .parent = &ckih_clk,
505 .set_rate = _clk_pll_set_rate, 421 .get_rate = serial_pll_get_rate,
506 .get_rate = _clk_pll_get_rate, 422 .enable = serial_pll_enable,
507 .enable = _clk_serial_pll_enable, 423 .disable = serial_pll_disable,
508 .disable = _clk_serial_pll_disable,
509}; 424};
510 425
511static struct clk usb_pll_clk = { 426static struct clk usb_pll_clk = {
512 .name = "usb_pll",
513 .parent = &ckih_clk, 427 .parent = &ckih_clk,
514 .set_rate = _clk_pll_set_rate, 428 .get_rate = usb_pll_get_rate,
515 .get_rate = _clk_pll_get_rate, 429 .enable = usb_pll_enable,
516 .enable = _clk_usb_pll_enable, 430 .disable = usb_pll_disable,
517 .disable = _clk_usb_pll_disable,
518}; 431};
519 432
520static struct clk ahb_clk = { 433static struct clk ahb_clk = {
521 .name = "ahb_clk",
522 .parent = &mcu_main_clk, 434 .parent = &mcu_main_clk,
523 .get_rate = _clk_hclk_get_rate, 435 .get_rate = ahb_get_rate,
524}; 436};
525 437
526static struct clk per_clk = { 438#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
527 .name = "per_clk", 439 static struct clk name = { \
528 .parent = &usb_pll_clk, 440 .id = i, \
529 .get_rate = _clk_per_get_rate, 441 .enable_reg = er, \
530}; 442 .enable_shift = es, \
531 443 .get_rate = gr, \
532static struct clk perclk_clk = { 444 .enable = cgr_enable, \
533 .name = "perclk_clk", 445 .disable = cgr_disable, \
534 .parent = &ipg_clk, 446 .secondary = s, \
535}; 447 .parent = p, \
536 448 }
537static struct clk cspi_clk[] = {
538 {
539 .name = "cspi_clk",
540 .id = 0,
541 .parent = &ipg_clk,
542 .enable = _clk_enable,
543 .enable_reg = MXC_CCM_CGR2,
544 .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
545 .disable = _clk_disable,},
546 {
547 .name = "cspi_clk",
548 .id = 1,
549 .parent = &ipg_clk,
550 .enable = _clk_enable,
551 .enable_reg = MXC_CCM_CGR2,
552 .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
553 .disable = _clk_disable,},
554 {
555 .name = "cspi_clk",
556 .id = 2,
557 .parent = &ipg_clk,
558 .enable = _clk_enable,
559 .enable_reg = MXC_CCM_CGR0,
560 .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
561 .disable = _clk_disable,},
562};
563
564static struct clk ipg_clk = {
565 .name = "ipg_clk",
566 .parent = &ahb_clk,
567 .get_rate = _clk_ipg_get_rate,
568};
569
570static struct clk emi_clk = {
571 .name = "emi_clk",
572 .parent = &ahb_clk,
573 .enable = _clk_enable,
574 .enable_reg = MXC_CCM_CGR2,
575 .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
576 .disable = _clk_emi_disable,
577};
578
579static struct clk gpt_clk = {
580 .name = "gpt_clk",
581 .parent = &perclk_clk,
582 .enable = _clk_enable,
583 .enable_reg = MXC_CCM_CGR0,
584 .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
585 .disable = _clk_disable,
586};
587
588static struct clk pwm_clk = {
589 .name = "pwm_clk",
590 .parent = &perclk_clk,
591 .enable = _clk_enable,
592 .enable_reg = MXC_CCM_CGR0,
593 .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
594 .disable = _clk_disable,
595};
596
597static struct clk epit_clk[] = {
598 {
599 .name = "epit_clk",
600 .id = 0,
601 .parent = &perclk_clk,
602 .enable = _clk_enable,
603 .enable_reg = MXC_CCM_CGR0,
604 .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
605 .disable = _clk_disable,},
606 {
607 .name = "epit_clk",
608 .id = 1,
609 .parent = &perclk_clk,
610 .enable = _clk_enable,
611 .enable_reg = MXC_CCM_CGR0,
612 .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
613 .disable = _clk_disable,},
614};
615
616static struct clk nfc_clk = {
617 .name = "nfc_clk",
618 .parent = &ahb_clk,
619 .get_rate = _clk_nfc_get_rate,
620};
621
622static struct clk scc_clk = {
623 .name = "scc_clk",
624 .parent = &ipg_clk,
625};
626
627static struct clk ipu_clk = {
628 .name = "ipu_clk",
629 .parent = &mcu_main_clk,
630 .get_rate = _clk_hsp_get_rate,
631 .enable = _clk_enable,
632 .enable_reg = MXC_CCM_CGR1,
633 .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
634 .disable = _clk_disable,
635};
636
637static struct clk kpp_clk = {
638 .name = "kpp_clk",
639 .parent = &ipg_clk,
640 .enable = _clk_enable,
641 .enable_reg = MXC_CCM_CGR1,
642 .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
643 .disable = _clk_disable,
644};
645
646static struct clk wdog_clk = {
647 .name = "wdog_clk",
648 .parent = &ipg_clk,
649 .enable = _clk_enable,
650 .enable_reg = MXC_CCM_CGR1,
651 .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
652 .disable = _clk_disable,
653};
654static struct clk rtc_clk = {
655 .name = "rtc_clk",
656 .parent = &ipg_clk,
657 .enable = _clk_enable,
658 .enable_reg = MXC_CCM_CGR1,
659 .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
660 .disable = _clk_disable,
661};
662
663static struct clk usb_clk[] = {
664 {
665 .name = "usb_clk",
666 .parent = &usb_pll_clk,
667 .get_rate = _clk_usb_get_rate,},
668 {
669 .name = "usb_ahb_clk",
670 .parent = &ahb_clk,
671 .enable = _clk_enable,
672 .enable_reg = MXC_CCM_CGR1,
673 .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
674 .disable = _clk_disable,},
675};
676
677static struct clk csi_clk = {
678 .name = "csi_clk",
679 .parent = &serial_pll_clk,
680 .get_rate = _clk_csi_get_rate,
681 .round_rate = _clk_csi_round_rate,
682 .set_rate = _clk_csi_set_rate,
683 .enable = _clk_enable,
684 .enable_reg = MXC_CCM_CGR1,
685 .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
686 .disable = _clk_disable,
687};
688
689static struct clk uart_clk[] = {
690 {
691 .name = "uart_clk",
692 .id = 0,
693 .parent = &perclk_clk,
694 .enable = _clk_enable,
695 .enable_reg = MXC_CCM_CGR0,
696 .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
697 .disable = _clk_disable,},
698 {
699 .name = "uart_clk",
700 .id = 1,
701 .parent = &perclk_clk,
702 .enable = _clk_enable,
703 .enable_reg = MXC_CCM_CGR0,
704 .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
705 .disable = _clk_disable,},
706 {
707 .name = "uart_clk",
708 .id = 2,
709 .parent = &perclk_clk,
710 .enable = _clk_enable,
711 .enable_reg = MXC_CCM_CGR1,
712 .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
713 .disable = _clk_disable,},
714 {
715 .name = "uart_clk",
716 .id = 3,
717 .parent = &perclk_clk,
718 .enable = _clk_enable,
719 .enable_reg = MXC_CCM_CGR1,
720 .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
721 .disable = _clk_disable,},
722 {
723 .name = "uart_clk",
724 .id = 4,
725 .parent = &perclk_clk,
726 .enable = _clk_enable,
727 .enable_reg = MXC_CCM_CGR1,
728 .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
729 .disable = _clk_disable,},
730};
731
732static struct clk i2c_clk[] = {
733 {
734 .name = "i2c_clk",
735 .id = 0,
736 .parent = &perclk_clk,
737 .enable = _clk_enable,
738 .enable_reg = MXC_CCM_CGR0,
739 .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
740 .disable = _clk_disable,},
741 {
742 .name = "i2c_clk",
743 .id = 1,
744 .parent = &perclk_clk,
745 .enable = _clk_enable,
746 .enable_reg = MXC_CCM_CGR0,
747 .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
748 .disable = _clk_disable,},
749 {
750 .name = "i2c_clk",
751 .id = 2,
752 .parent = &perclk_clk,
753 .enable = _clk_enable,
754 .enable_reg = MXC_CCM_CGR0,
755 .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
756 .disable = _clk_disable,},
757};
758
759static struct clk owire_clk = {
760 .name = "owire_clk",
761 .parent = &perclk_clk,
762 .enable_reg = MXC_CCM_CGR1,
763 .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
764 .enable = _clk_enable,
765 .disable = _clk_disable,
766};
767
768static struct clk sdhc_clk[] = {
769 {
770 .name = "sdhc_clk",
771 .id = 0,
772 .parent = &perclk_clk,
773 .enable = _clk_enable,
774 .enable_reg = MXC_CCM_CGR0,
775 .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
776 .disable = _clk_disable,},
777 {
778 .name = "sdhc_clk",
779 .id = 1,
780 .parent = &perclk_clk,
781 .enable = _clk_enable,
782 .enable_reg = MXC_CCM_CGR0,
783 .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
784 .disable = _clk_disable,},
785};
786
787static struct clk ssi_clk[] = {
788 {
789 .name = "ssi_clk",
790 .parent = &serial_pll_clk,
791 .get_rate = _clk_ssi1_get_rate,
792 .enable = _clk_enable,
793 .enable_reg = MXC_CCM_CGR0,
794 .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
795 .disable = _clk_disable,},
796 {
797 .name = "ssi_clk",
798 .id = 1,
799 .parent = &serial_pll_clk,
800 .get_rate = _clk_ssi2_get_rate,
801 .enable = _clk_enable,
802 .enable_reg = MXC_CCM_CGR2,
803 .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
804 .disable = _clk_disable,},
805};
806
807static struct clk firi_clk = {
808 .name = "firi_clk",
809 .parent = &usb_pll_clk,
810 .round_rate = _clk_firi_round_rate,
811 .set_rate = _clk_firi_set_rate,
812 .get_rate = _clk_firi_get_rate,
813 .enable = _clk_enable,
814 .enable_reg = MXC_CCM_CGR2,
815 .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
816 .disable = _clk_disable,
817};
818
819static struct clk ata_clk = {
820 .name = "ata_clk",
821 .parent = &ipg_clk,
822 .enable = _clk_enable,
823 .enable_reg = MXC_CCM_CGR0,
824 .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
825 .disable = _clk_disable,
826};
827
828static struct clk mbx_clk = {
829 .name = "mbx_clk",
830 .parent = &ahb_clk,
831 .enable = _clk_enable,
832 .enable_reg = MXC_CCM_CGR2,
833 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
834 .get_rate = _clk_mbx_get_rate,
835};
836
837static struct clk vpu_clk = {
838 .name = "vpu_clk",
839 .parent = &ahb_clk,
840 .enable = _clk_enable,
841 .enable_reg = MXC_CCM_CGR2,
842 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
843 .get_rate = _clk_mbx_get_rate,
844};
845
846static struct clk rtic_clk = {
847 .name = "rtic_clk",
848 .parent = &ahb_clk,
849 .enable = _clk_enable,
850 .enable_reg = MXC_CCM_CGR2,
851 .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
852 .disable = _clk_disable,
853};
854
855static struct clk rng_clk = {
856 .name = "rng_clk",
857 .parent = &ipg_clk,
858 .enable = _clk_enable,
859 .enable_reg = MXC_CCM_CGR0,
860 .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
861 .disable = _clk_disable,
862};
863
864static struct clk sdma_clk[] = {
865 {
866 .name = "sdma_ahb_clk",
867 .parent = &ahb_clk,
868 .enable = _clk_enable,
869 .enable_reg = MXC_CCM_CGR0,
870 .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
871 .disable = _clk_disable,},
872 {
873 .name = "sdma_ipg_clk",
874 .parent = &ipg_clk,}
875};
876
877static struct clk mpeg4_clk = {
878 .name = "mpeg4_clk",
879 .parent = &ahb_clk,
880 .enable = _clk_enable,
881 .enable_reg = MXC_CCM_CGR1,
882 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
883 .disable = _clk_disable,
884};
885
886static struct clk vl2cc_clk = {
887 .name = "vl2cc_clk",
888 .parent = &ahb_clk,
889 .enable = _clk_enable,
890 .enable_reg = MXC_CCM_CGR1,
891 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
892 .disable = _clk_disable,
893};
894
895static struct clk mstick_clk[] = {
896 {
897 .name = "mstick_clk",
898 .id = 0,
899 .parent = &usb_pll_clk,
900 .get_rate = _clk_mstick1_get_rate,
901 .enable = _clk_enable,
902 .enable_reg = MXC_CCM_CGR1,
903 .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
904 .disable = _clk_disable,},
905 {
906 .name = "mstick_clk",
907 .id = 1,
908 .parent = &usb_pll_clk,
909 .get_rate = _clk_mstick2_get_rate,
910 .enable = _clk_enable,
911 .enable_reg = MXC_CCM_CGR1,
912 .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
913 .disable = _clk_disable,},
914};
915
916static struct clk iim_clk = {
917 .name = "iim_clk",
918 .parent = &ipg_clk,
919 .enable = _clk_enable,
920 .enable_reg = MXC_CCM_CGR0,
921 .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
922 .disable = _clk_disable,
923};
924
925static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
926{
927 u32 div, parent = clk_get_rate(clk->parent);
928
929 div = parent / rate;
930 if (parent % rate)
931 div++;
932
933 if (div > 8)
934 div = 16;
935 else if (div > 4)
936 div = 8;
937 else if (div > 2)
938 div = 4;
939
940 return parent / div;
941}
942
943static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
944{
945 u32 reg, div, parent = clk_get_rate(clk->parent);
946
947 div = parent / rate;
948
949 if (div == 16)
950 div = 4;
951 else if (div == 8)
952 div = 3;
953 else if (div == 4)
954 div = 2;
955 else if (div == 2)
956 div = 1;
957 else if (div == 1)
958 div = 0;
959 else
960 return -EINVAL;
961
962 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
963 reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
964 __raw_writel(reg, MXC_CCM_COSR);
965
966 return 0;
967}
968
969static unsigned long _clk_cko1_get_rate(struct clk *clk)
970{
971 u32 div;
972
973 div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
974 MXC_CCM_COSR_CLKOUTDIV_OFFSET;
975
976 return clk_get_rate(clk->parent) / (1 << div);
977}
978
979static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
980{
981 u32 reg;
982
983 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
984
985 if (parent == &mcu_main_clk)
986 reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
987 else if (parent == &ipg_clk)
988 reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
989 else if (parent == &usb_pll_clk)
990 reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
991 else if (parent == mcu_main_clk.parent)
992 reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
993 else if (parent == &ahb_clk)
994 reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
995 else if (parent == &serial_pll_clk)
996 reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
997 else if (parent == &ckih_clk)
998 reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
999 else if (parent == &emi_clk)
1000 reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
1001 else if (parent == &ipu_clk)
1002 reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
1003 else if (parent == &nfc_clk)
1004 reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
1005 else if (parent == &uart_clk[0])
1006 reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
1007 else
1008 return -EINVAL;
1009
1010 __raw_writel(reg, MXC_CCM_COSR);
1011
1012 return 0;
1013}
1014
1015static int _clk_cko1_enable(struct clk *clk)
1016{
1017 u32 reg;
1018
1019 reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
1020 __raw_writel(reg, MXC_CCM_COSR);
1021 449
1022 return 0; 450#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
1023} 451 static struct clk name = { \
452 .id = i, \
453 .enable_reg = er, \
454 .enable_shift = es, \
455 .get_rate = getsetround##_get_rate, \
456 .set_rate = getsetround##_set_rate, \
457 .round_rate = getsetround##_round_rate, \
458 .enable = cgr_enable, \
459 .disable = cgr_disable, \
460 .secondary = s, \
461 .parent = p, \
462 }
1024 463
1025static void _clk_cko1_disable(struct clk *clk) 464DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
465
466DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
467DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
468DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
469DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
470DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
471DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
472DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
473DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
474DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
475DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
476DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
477DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
478DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
479DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
480DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
481DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
482
483DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
484DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
485DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
486DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk);
487DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk);
488DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
489DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
490DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
491DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
492DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
493DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
494DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
495DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
496DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
497
498DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
499DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
500DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
501DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
502DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
503DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
504DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
505
506DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
507DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
508DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
509DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
510DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
511
512#define _REGISTER_CLOCK(d, n, c) \
513 { \
514 .dev_id = d, \
515 .con_id = n, \
516 .clk = &c, \
517 },
518
519static struct clk_lookup lookups[] __initdata = {
520 _REGISTER_CLOCK(NULL, "emi", emi_clk)
521 _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
522 _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
523 _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
524 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
525 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
526 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
527 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
528 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
529 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
530 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
531 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
532 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
533 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
534 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
535 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
536 _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk)
537 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
538 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
539 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
540 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
541 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
542 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
543 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
544 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
545 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
546 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
547 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
548 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
549 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
550 _REGISTER_CLOCK(NULL, "firi", firi_clk)
551 _REGISTER_CLOCK(NULL, "ata", ata_clk)
552 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
553 _REGISTER_CLOCK(NULL, "rng", rng_clk)
554 _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
555 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
556 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
557 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
558 _REGISTER_CLOCK(NULL, "scc", scc_clk)
559 _REGISTER_CLOCK(NULL, "iim", iim_clk)
560 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
561 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
562};
563
564int __init mx31_clocks_init(unsigned long fref)
1026{ 565{
1027 u32 reg; 566 u32 reg;
567 int i;
1028 568
1029 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; 569 mxc_set_cpu_type(MXC_CPU_MX31);
1030 __raw_writel(reg, MXC_CCM_COSR);
1031}
1032
1033static struct clk cko1_clk = {
1034 .name = "cko1_clk",
1035 .get_rate = _clk_cko1_get_rate,
1036 .set_rate = _clk_cko1_set_rate,
1037 .round_rate = _clk_cko1_round_rate,
1038 .set_parent = _clk_cko1_set_parent,
1039 .enable = _clk_cko1_enable,
1040 .disable = _clk_cko1_disable,
1041};
1042
1043static struct clk *mxc_clks[] = {
1044 &ckih_clk,
1045 &ckil_clk,
1046 &mcu_pll_clk,
1047 &usb_pll_clk,
1048 &serial_pll_clk,
1049 &mcu_main_clk,
1050 &ahb_clk,
1051 &per_clk,
1052 &perclk_clk,
1053 &cko1_clk,
1054 &emi_clk,
1055 &cspi_clk[0],
1056 &cspi_clk[1],
1057 &cspi_clk[2],
1058 &ipg_clk,
1059 &gpt_clk,
1060 &pwm_clk,
1061 &wdog_clk,
1062 &rtc_clk,
1063 &epit_clk[0],
1064 &epit_clk[1],
1065 &nfc_clk,
1066 &ipu_clk,
1067 &kpp_clk,
1068 &usb_clk[0],
1069 &usb_clk[1],
1070 &csi_clk,
1071 &uart_clk[0],
1072 &uart_clk[1],
1073 &uart_clk[2],
1074 &uart_clk[3],
1075 &uart_clk[4],
1076 &i2c_clk[0],
1077 &i2c_clk[1],
1078 &i2c_clk[2],
1079 &owire_clk,
1080 &sdhc_clk[0],
1081 &sdhc_clk[1],
1082 &ssi_clk[0],
1083 &ssi_clk[1],
1084 &firi_clk,
1085 &ata_clk,
1086 &rtic_clk,
1087 &rng_clk,
1088 &sdma_clk[0],
1089 &sdma_clk[1],
1090 &mstick_clk[0],
1091 &mstick_clk[1],
1092 &scc_clk,
1093 &iim_clk,
1094};
1095
1096int __init mxc_clocks_init(unsigned long fref)
1097{
1098 u32 reg;
1099 struct clk **clkp;
1100 570
1101 ckih_rate = fref; 571 ckih_rate = fref;
1102 572
1103 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 573 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1104 clk_register(*clkp); 574 clkdev_add(&lookups[i]);
1105
1106 if (cpu_is_mx31()) {
1107 clk_register(&mpeg4_clk);
1108 clk_register(&mbx_clk);
1109 } else {
1110 clk_register(&vpu_clk);
1111 clk_register(&vl2cc_clk);
1112 }
1113 575
1114 /* Turn off all possible clocks */ 576 /* Turn off all possible clocks */
1115 __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); 577 __raw_writel((3 << 4), MXC_CCM_CGR0);
1116 __raw_writel(0, MXC_CCM_CGR1); 578 __raw_writel(0, MXC_CCM_CGR1);
1117 579 __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
1118 __raw_writel(MXC_CCM_CGR2_EMI_MASK |
1119 MXC_CCM_CGR2_IPMUX1_MASK |
1120 MXC_CCM_CGR2_IPMUX2_MASK |
1121 MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */
1122 MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */
1123 MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */
1124 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for 580 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
1125 MX32, but still required to be set */ 581 MX32, but still required to be set */
1126 MXC_CCM_CGR2); 582 MXC_CCM_CGR2);
1127 583
1128 clk_disable(&cko1_clk); 584 usb_pll_disable(&usb_pll_clk);
1129 clk_disable(&usb_pll_clk);
1130 585
1131 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); 586 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
1132 587
@@ -1143,6 +598,8 @@ int __init mxc_clocks_init(unsigned long fref)
1143 __raw_writel(reg, MXC_CCM_PMCR1); 598 __raw_writel(reg, MXC_CCM_PMCR1);
1144 } 599 }
1145 600
601 mxc_timer_init(&ipg_clk);
602
1146 return 0; 603 return 0;
1147} 604}
1148 605
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index 4a0e0ede23bb..adfa3627ad84 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -91,47 +91,6 @@
91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
93 93
94#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11)
95#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11)
96#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11)
97#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11)
98#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11)
99#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11)
100#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11)
101#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11)
102
103#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6)
104#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6)
105#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6)
106#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6)
107
108#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3)
109#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3)
110#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3)
111#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3)
112#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3)
113#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3)
114#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3)
115#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3)
116
117#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8)
118#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8)
119#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8)
120#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8)
121#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8)
122#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8)
123#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8)
124#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8)
125
126#define MXC_CCM_PDR0_MCU_DIV_1 0x0
127#define MXC_CCM_PDR0_MCU_DIV_2 0x1
128#define MXC_CCM_PDR0_MCU_DIV_3 0x2
129#define MXC_CCM_PDR0_MCU_DIV_4 0x3
130#define MXC_CCM_PDR0_MCU_DIV_5 0x4
131#define MXC_CCM_PDR0_MCU_DIV_6 0x5
132#define MXC_CCM_PDR0_MCU_DIV_7 0x6
133#define MXC_CCM_PDR0_MCU_DIV_8 0x7
134
135#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 94#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
136#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 95#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
137#define MXC_CCM_PDR1_USB_PODF_OFFSET 27 96#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
@@ -152,118 +111,6 @@
152/* Bit definitions for RCSR */ 111/* Bit definitions for RCSR */
153#define MXC_CCM_RCSR_NF16B 0x80000000 112#define MXC_CCM_RCSR_NF16B 0x80000000
154 113
155/* Bit definitions for both MCU, USB and SR PLL control registers */
156#define MXC_CCM_PCTL_BRM 0x80000000
157#define MXC_CCM_PCTL_PD_OFFSET 26
158#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
159#define MXC_CCM_PCTL_MFD_OFFSET 16
160#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
161#define MXC_CCM_PCTL_MFI_OFFSET 10
162#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
163#define MXC_CCM_PCTL_MFN_OFFSET 0
164#define MXC_CCM_PCTL_MFN_MASK 0x3FF
165
166#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0
167#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0)
168#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2
169#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2)
170#define MXC_CCM_CGR0_GPT_OFFSET 4
171#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4)
172#define MXC_CCM_CGR0_EPIT1_OFFSET 6
173#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6)
174#define MXC_CCM_CGR0_EPIT2_OFFSET 8
175#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8)
176#define MXC_CCM_CGR0_IIM_OFFSET 10
177#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10)
178#define MXC_CCM_CGR0_ATA_OFFSET 12
179#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12)
180#define MXC_CCM_CGR0_SDMA_OFFSET 14
181#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14)
182#define MXC_CCM_CGR0_CSPI3_OFFSET 16
183#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16)
184#define MXC_CCM_CGR0_RNG_OFFSET 18
185#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18)
186#define MXC_CCM_CGR0_UART1_OFFSET 20
187#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20)
188#define MXC_CCM_CGR0_UART2_OFFSET 22
189#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22)
190#define MXC_CCM_CGR0_SSI1_OFFSET 24
191#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24)
192#define MXC_CCM_CGR0_I2C1_OFFSET 26
193#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26)
194#define MXC_CCM_CGR0_I2C2_OFFSET 28
195#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28)
196#define MXC_CCM_CGR0_I2C3_OFFSET 30
197#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30)
198
199#define MXC_CCM_CGR1_HANTRO_OFFSET 0
200#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0)
201#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2
202#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2)
203#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4
204#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4)
205#define MXC_CCM_CGR1_CSI_OFFSET 6
206#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6)
207#define MXC_CCM_CGR1_RTC_OFFSET 8
208#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8)
209#define MXC_CCM_CGR1_WDOG_OFFSET 10
210#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10)
211#define MXC_CCM_CGR1_PWM_OFFSET 12
212#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12)
213#define MXC_CCM_CGR1_SIM_OFFSET 14
214#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14)
215#define MXC_CCM_CGR1_ECT_OFFSET 16
216#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16)
217#define MXC_CCM_CGR1_USBOTG_OFFSET 18
218#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18)
219#define MXC_CCM_CGR1_KPP_OFFSET 20
220#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
221#define MXC_CCM_CGR1_IPU_OFFSET 22
222#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22)
223#define MXC_CCM_CGR1_UART3_OFFSET 24
224#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24)
225#define MXC_CCM_CGR1_UART4_OFFSET 26
226#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26)
227#define MXC_CCM_CGR1_UART5_OFFSET 28
228#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28)
229#define MXC_CCM_CGR1_OWIRE_OFFSET 30
230#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30)
231
232#define MXC_CCM_CGR2_SSI2_OFFSET 0
233#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0)
234#define MXC_CCM_CGR2_CSPI1_OFFSET 2
235#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2)
236#define MXC_CCM_CGR2_CSPI2_OFFSET 4
237#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4)
238#define MXC_CCM_CGR2_GACC_OFFSET 6
239#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6)
240#define MXC_CCM_CGR2_EMI_OFFSET 8
241#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8)
242#define MXC_CCM_CGR2_RTIC_OFFSET 10
243#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10)
244#define MXC_CCM_CGR2_FIRI_OFFSET 12
245#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12)
246#define MXC_CCM_CGR2_IPMUX1_OFFSET 14
247#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14)
248#define MXC_CCM_CGR2_IPMUX2_OFFSET 16
249#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16)
250
251/* These new CGR2 bits are added in MX32 */
252#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18
253#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18)
254#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20
255#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20)
256#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22
257#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22)
258#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24
259#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24)
260#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25
261#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25)
262#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26
263#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26)
264#define MXC_CCM_CGR2_APMENA_OFFSET 30
265#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30)
266
267/* 114/*
268 * LTR0 register offsets 115 * LTR0 register offsets
269 */ 116 */
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f8428800f286..380be0c9b213 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,6 +25,8 @@
25#include <mach/irqs.h> 25#include <mach/irqs.h>
26#include <mach/imx-uart.h> 26#include <mach/imx-uart.h>
27 27
28#include "devices.h"
29
28static struct resource uart0[] = { 30static struct resource uart0[] = {
29 { 31 {
30 .start = UART1_BASE_ADDR, 32 .start = UART1_BASE_ADDR,
@@ -82,6 +84,7 @@ struct platform_device mxc_uart_device2 = {
82 .num_resources = ARRAY_SIZE(uart2), 84 .num_resources = ARRAY_SIZE(uart2),
83}; 85};
84 86
87#ifdef CONFIG_ARCH_MX31
85static struct resource uart3[] = { 88static struct resource uart3[] = {
86 { 89 {
87 .start = UART4_BASE_ADDR, 90 .start = UART4_BASE_ADDR,
@@ -119,6 +122,7 @@ struct platform_device mxc_uart_device4 = {
119 .resource = uart4, 122 .resource = uart4,
120 .num_resources = ARRAY_SIZE(uart4), 123 .num_resources = ARRAY_SIZE(uart4),
121}; 124};
125#endif /* CONFIG_ARCH_MX31 */
122 126
123/* GPIO port description */ 127/* GPIO port description */
124static struct mxc_gpio_port imx_gpio_ports[] = { 128static struct mxc_gpio_port imx_gpio_ports[] = {
@@ -164,8 +168,8 @@ struct platform_device mxc_w1_master_device = {
164 168
165static struct resource mxc_nand_resources[] = { 169static struct resource mxc_nand_resources[] = {
166 { 170 {
167 .start = NFC_BASE_ADDR, 171 .start = 0, /* runtime dependent */
168 .end = NFC_BASE_ADDR + 0xfff, 172 .end = 0,
169 .flags = IORESOURCE_MEM 173 .flags = IORESOURCE_MEM
170 }, { 174 }, {
171 .start = MXC_INT_NANDFC, 175 .start = MXC_INT_NANDFC,
@@ -180,3 +184,188 @@ struct platform_device mxc_nand_device = {
180 .num_resources = ARRAY_SIZE(mxc_nand_resources), 184 .num_resources = ARRAY_SIZE(mxc_nand_resources),
181 .resource = mxc_nand_resources, 185 .resource = mxc_nand_resources,
182}; 186};
187
188static struct resource mxc_i2c0_resources[] = {
189 {
190 .start = I2C_BASE_ADDR,
191 .end = I2C_BASE_ADDR + SZ_4K - 1,
192 .flags = IORESOURCE_MEM,
193 },
194 {
195 .start = MXC_INT_I2C,
196 .end = MXC_INT_I2C,
197 .flags = IORESOURCE_IRQ,
198 },
199};
200
201struct platform_device mxc_i2c_device0 = {
202 .name = "imx-i2c",
203 .id = 0,
204 .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
205 .resource = mxc_i2c0_resources,
206};
207
208static struct resource mxc_i2c1_resources[] = {
209 {
210 .start = I2C2_BASE_ADDR,
211 .end = I2C2_BASE_ADDR + SZ_4K - 1,
212 .flags = IORESOURCE_MEM,
213 },
214 {
215 .start = MXC_INT_I2C2,
216 .end = MXC_INT_I2C2,
217 .flags = IORESOURCE_IRQ,
218 },
219};
220
221struct platform_device mxc_i2c_device1 = {
222 .name = "imx-i2c",
223 .id = 1,
224 .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
225 .resource = mxc_i2c1_resources,
226};
227
228static struct resource mxc_i2c2_resources[] = {
229 {
230 .start = I2C3_BASE_ADDR,
231 .end = I2C3_BASE_ADDR + SZ_4K - 1,
232 .flags = IORESOURCE_MEM,
233 },
234 {
235 .start = MXC_INT_I2C3,
236 .end = MXC_INT_I2C3,
237 .flags = IORESOURCE_IRQ,
238 },
239};
240
241struct platform_device mxc_i2c_device2 = {
242 .name = "imx-i2c",
243 .id = 2,
244 .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
245 .resource = mxc_i2c2_resources,
246};
247
248#ifdef CONFIG_ARCH_MX31
249static struct resource mxcsdhc0_resources[] = {
250 {
251 .start = MMC_SDHC1_BASE_ADDR,
252 .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
253 .flags = IORESOURCE_MEM,
254 }, {
255 .start = MXC_INT_MMC_SDHC1,
256 .end = MXC_INT_MMC_SDHC1,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct resource mxcsdhc1_resources[] = {
262 {
263 .start = MMC_SDHC2_BASE_ADDR,
264 .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
265 .flags = IORESOURCE_MEM,
266 }, {
267 .start = MXC_INT_MMC_SDHC2,
268 .end = MXC_INT_MMC_SDHC2,
269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273struct platform_device mxcsdhc_device0 = {
274 .name = "mxc-mmc",
275 .id = 0,
276 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
277 .resource = mxcsdhc0_resources,
278};
279
280struct platform_device mxcsdhc_device1 = {
281 .name = "mxc-mmc",
282 .id = 1,
283 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
284 .resource = mxcsdhc1_resources,
285};
286#endif /* CONFIG_ARCH_MX31 */
287
288/* i.MX31 Image Processing Unit */
289
290/* The resource order is important! */
291static struct resource mx3_ipu_rsrc[] = {
292 {
293 .start = IPU_CTRL_BASE_ADDR,
294 .end = IPU_CTRL_BASE_ADDR + 0x5F,
295 .flags = IORESOURCE_MEM,
296 }, {
297 .start = IPU_CTRL_BASE_ADDR + 0x88,
298 .end = IPU_CTRL_BASE_ADDR + 0xB3,
299 .flags = IORESOURCE_MEM,
300 }, {
301 .start = MXC_INT_IPU_SYN,
302 .end = MXC_INT_IPU_SYN,
303 .flags = IORESOURCE_IRQ,
304 }, {
305 .start = MXC_INT_IPU_ERR,
306 .end = MXC_INT_IPU_ERR,
307 .flags = IORESOURCE_IRQ,
308 },
309};
310
311struct platform_device mx3_ipu = {
312 .name = "ipu-core",
313 .id = -1,
314 .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
315 .resource = mx3_ipu_rsrc,
316};
317
318static struct resource fb_resources[] = {
319 {
320 .start = IPU_CTRL_BASE_ADDR + 0xB4,
321 .end = IPU_CTRL_BASE_ADDR + 0x1BF,
322 .flags = IORESOURCE_MEM,
323 },
324};
325
326struct platform_device mx3_fb = {
327 .name = "mx3_sdc_fb",
328 .id = -1,
329 .num_resources = ARRAY_SIZE(fb_resources),
330 .resource = fb_resources,
331 .dev = {
332 .coherent_dma_mask = 0xffffffff,
333 },
334};
335
336#ifdef CONFIG_ARCH_MX35
337static struct resource mxc_fec_resources[] = {
338 {
339 .start = MXC_FEC_BASE_ADDR,
340 .end = MXC_FEC_BASE_ADDR + 0xfff,
341 .flags = IORESOURCE_MEM
342 }, {
343 .start = MXC_INT_FEC,
344 .end = MXC_INT_FEC,
345 .flags = IORESOURCE_IRQ
346 },
347};
348
349struct platform_device mxc_fec_device = {
350 .name = "fec",
351 .id = 0,
352 .num_resources = ARRAY_SIZE(mxc_fec_resources),
353 .resource = mxc_fec_resources,
354};
355#endif
356
357static int mx3_devices_init(void)
358{
359 if (cpu_is_mx31()) {
360 mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
361 mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
362 }
363 if (cpu_is_mx35()) {
364 mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
365 mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
366 }
367
368 return 0;
369}
370
371subsys_initcall(mx3_devices_init);
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 9949ef4e0694..88c04b296fab 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -6,3 +6,11 @@ extern struct platform_device mxc_uart_device3;
6extern struct platform_device mxc_uart_device4; 6extern struct platform_device mxc_uart_device4;
7extern struct platform_device mxc_w1_master_device; 7extern struct platform_device mxc_w1_master_device;
8extern struct platform_device mxc_nand_device; 8extern struct platform_device mxc_nand_device;
9extern struct platform_device mxc_i2c_device0;
10extern struct platform_device mxc_i2c_device1;
11extern struct platform_device mxc_i2c_device2;
12extern struct platform_device mx3_ipu;
13extern struct platform_device mx3_fb;
14extern struct platform_device mxc_fec_device;
15extern struct platform_device mxcsdhc_device0;
16extern struct platform_device mxcsdhc_device1;
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c
index 7a5088b519a8..40ffc5a664d9 100644
--- a/arch/arm/mach-mx3/iomux.c
+++ b/arch/arm/mach-mx3/iomux.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> 3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
4 * 5 *
5 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 7 * modify it under the terms of the GNU General Public License
@@ -21,6 +22,7 @@
21#include <linux/spinlock.h> 22#include <linux/spinlock.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/kernel.h>
24#include <mach/hardware.h> 26#include <mach/hardware.h>
25#include <mach/gpio.h> 27#include <mach/gpio.h>
26#include <mach/iomux-mx3.h> 28#include <mach/iomux-mx3.h>
@@ -38,6 +40,8 @@
38static DEFINE_SPINLOCK(gpio_mux_lock); 40static DEFINE_SPINLOCK(gpio_mux_lock);
39 41
40#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) 42#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
43
44unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
41/* 45/*
42 * set the mode for a IOMUX pin. 46 * set the mode for a IOMUX pin.
43 */ 47 */
@@ -50,9 +54,6 @@ int mxc_iomux_mode(unsigned int pin_mode)
50 field = pin_mode & 0x3; 54 field = pin_mode & 0x3;
51 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; 55 mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
52 56
53 pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n",
54 __func__, (pin_mode & IOMUX_REG_MASK), field, mode);
55
56 spin_lock(&gpio_mux_lock); 57 spin_lock(&gpio_mux_lock);
57 58
58 l = __raw_readl(reg); 59 l = __raw_readl(reg);
@@ -93,6 +94,86 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
93EXPORT_SYMBOL(mxc_iomux_set_pad); 94EXPORT_SYMBOL(mxc_iomux_set_pad);
94 95
95/* 96/*
97 * setups a single pin:
98 * - reserves the pin so that it is not claimed by another driver
99 * - setups the iomux according to the configuration
100 * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
101 */
102int mxc_iomux_setup_pin(const unsigned int pin, const char *label)
103{
104 unsigned pad = pin & IOMUX_PADNUM_MASK;
105 unsigned gpio;
106
107 if (pad >= (PIN_MAX + 1)) {
108 printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
109 pad, label ? label : "?");
110 return -EINVAL;
111 }
112
113 if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
114 printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
115 pad, label ? label : "?");
116 return -EINVAL;
117 }
118 mxc_iomux_mode(pin);
119
120 /* if we have a gpio, we can allocate it */
121 gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
122 if (gpio < (GPIO_PORT_MAX + 1) * 32)
123 if (gpio_request(gpio, label))
124 return -EINVAL;
125
126 return 0;
127}
128EXPORT_SYMBOL(mxc_iomux_setup_pin);
129
130int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
131 const char *label)
132{
133 unsigned int *p = pin_list;
134 int i;
135 int ret = -EINVAL;
136
137 for (i = 0; i < count; i++) {
138 if (mxc_iomux_setup_pin(*p, label))
139 goto setup_error;
140 p++;
141 }
142 return 0;
143
144setup_error:
145 mxc_iomux_release_multiple_pins(pin_list, i);
146 return ret;
147}
148EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
149
150void mxc_iomux_release_pin(const unsigned int pin)
151{
152 unsigned pad = pin & IOMUX_PADNUM_MASK;
153 unsigned gpio;
154
155 if (pad < (PIN_MAX + 1))
156 clear_bit(pad, mxc_pin_alloc_map);
157
158 gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT;
159 if (gpio < (GPIO_PORT_MAX + 1) * 32)
160 gpio_free(gpio);
161}
162EXPORT_SYMBOL(mxc_iomux_release_pin);
163
164void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
165{
166 unsigned int *p = pin_list;
167 int i;
168
169 for (i = 0; i < count; i++) {
170 mxc_iomux_release_pin(*p);
171 p++;
172 }
173}
174EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
175
176/*
96 * This function enables/disables the general purpose function for a particular 177 * This function enables/disables the general purpose function for a particular
97 * signal. 178 * signal.
98 */ 179 */
@@ -111,4 +192,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
111 spin_unlock(&gpio_mux_lock); 192 spin_unlock(&gpio_mux_lock);
112} 193}
113EXPORT_SYMBOL(mxc_iomux_set_gpr); 194EXPORT_SYMBOL(mxc_iomux_set_gpr);
114
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 0589b5cd33c7..9e1459cb4b74 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -22,10 +22,14 @@
22 22
23#include <linux/mm.h> 23#include <linux/mm.h>
24#include <linux/init.h> 24#include <linux/init.h>
25#include <mach/hardware.h> 25#include <linux/err.h>
26
26#include <asm/pgtable.h> 27#include <asm/pgtable.h>
27#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/hardware/cache-l2x0.h>
30
28#include <mach/common.h> 31#include <mach/common.h>
32#include <mach/hardware.h>
29 33
30/*! 34/*!
31 * @file mm.c 35 * @file mm.c
@@ -50,6 +54,16 @@ static struct map_desc mxc_io_desc[] __initdata = {
50 .pfn = __phys_to_pfn(AVIC_BASE_ADDR), 54 .pfn = __phys_to_pfn(AVIC_BASE_ADDR),
51 .length = AVIC_SIZE, 55 .length = AVIC_SIZE,
52 .type = MT_DEVICE_NONSHARED 56 .type = MT_DEVICE_NONSHARED
57 }, {
58 .virtual = AIPS1_BASE_ADDR_VIRT,
59 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
60 .length = AIPS1_SIZE,
61 .type = MT_DEVICE_NONSHARED
62 }, {
63 .virtual = AIPS2_BASE_ADDR_VIRT,
64 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
65 .length = AIPS2_SIZE,
66 .type = MT_DEVICE_NONSHARED
53 }, 67 },
54}; 68};
55 69
@@ -62,3 +76,24 @@ void __init mxc_map_io(void)
62{ 76{
63 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 77 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
64} 78}
79
80#ifdef CONFIG_CACHE_L2X0
81static int mxc_init_l2x0(void)
82{
83 void __iomem *l2x0_base;
84
85 l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
86 if (IS_ERR(l2x0_base)) {
87 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
88 PTR_ERR(l2x0_base));
89 return 0;
90 }
91
92 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
93
94 return 0;
95}
96
97arch_initcall(mxc_init_l2x0);
98#endif
99
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index f902a7c37c31..83e5e8e1276f 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -22,6 +22,8 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25#include <linux/gpio.h>
26#include <linux/i2c.h>
25#include <linux/irq.h> 27#include <linux/irq.h>
26 28
27#include <mach/hardware.h> 29#include <mach/hardware.h>
@@ -35,6 +37,12 @@
35#include <mach/imx-uart.h> 37#include <mach/imx-uart.h>
36#include <mach/iomux-mx3.h> 38#include <mach/iomux-mx3.h>
37 39
40#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
41#include <linux/mfd/wm8350/audio.h>
42#include <linux/mfd/wm8350/core.h>
43#include <linux/mfd/wm8350/pmic.h>
44#endif
45
38#include "devices.h" 46#include "devices.h"
39 47
40/*! 48/*!
@@ -94,13 +102,16 @@ static struct imxuart_platform_data uart_pdata = {
94 .flags = IMXUART_HAVE_RTSCTS, 102 .flags = IMXUART_HAVE_RTSCTS,
95}; 103};
96 104
105static int uart_pins[] = {
106 MX31_PIN_CTS1__CTS1,
107 MX31_PIN_RTS1__RTS1,
108 MX31_PIN_TXD1__TXD1,
109 MX31_PIN_RXD1__RXD1
110};
111
97static inline void mxc_init_imx_uart(void) 112static inline void mxc_init_imx_uart(void)
98{ 113{
99 mxc_iomux_mode(MX31_PIN_CTS1__CTS1); 114 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
100 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
101 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
102 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
103
104 mxc_register_device(&mxc_uart_device0, &uart_pdata); 115 mxc_register_device(&mxc_uart_device0, &uart_pdata);
105} 116}
106#else /* !SERIAL_IMX */ 117#else /* !SERIAL_IMX */
@@ -176,7 +187,7 @@ static void __init mx31ads_init_expio(void)
176 /* 187 /*
177 * Configure INT line as GPIO input 188 * Configure INT line as GPIO input
178 */ 189 */
179 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO)); 190 mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
180 191
181 /* disable the interrupt and clear the status */ 192 /* disable the interrupt and clear the status */
182 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); 193 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
@@ -191,26 +202,301 @@ static void __init mx31ads_init_expio(void)
191 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); 202 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
192} 203}
193 204
205#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
206/* This section defines setup for the Wolfson Microelectronics
207 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
208 * regulator definitions may be shared with them, but for now they can
209 * only be used with this board so would generate warnings about
210 * unused statics and some of the configuration is specific to this
211 * module.
212 */
213
214/* CPU */
215static struct regulator_consumer_supply sw1a_consumers[] = {
216 {
217 .supply = "cpu_vcc",
218 }
219};
220
221static struct regulator_init_data sw1a_data = {
222 .constraints = {
223 .name = "SW1A",
224 .min_uV = 1275000,
225 .max_uV = 1600000,
226 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
227 REGULATOR_CHANGE_MODE,
228 .valid_modes_mask = REGULATOR_MODE_NORMAL |
229 REGULATOR_MODE_FAST,
230 .state_mem = {
231 .uV = 1400000,
232 .mode = REGULATOR_MODE_NORMAL,
233 .enabled = 1,
234 },
235 .initial_state = PM_SUSPEND_MEM,
236 .always_on = 1,
237 .boot_on = 1,
238 },
239 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
240 .consumer_supplies = sw1a_consumers,
241};
242
243/* System IO - High */
244static struct regulator_init_data viohi_data = {
245 .constraints = {
246 .name = "VIOHO",
247 .min_uV = 2800000,
248 .max_uV = 2800000,
249 .state_mem = {
250 .uV = 2800000,
251 .mode = REGULATOR_MODE_NORMAL,
252 .enabled = 1,
253 },
254 .initial_state = PM_SUSPEND_MEM,
255 .always_on = 1,
256 .boot_on = 1,
257 },
258};
259
260/* System IO - Low */
261static struct regulator_init_data violo_data = {
262 .constraints = {
263 .name = "VIOLO",
264 .min_uV = 1800000,
265 .max_uV = 1800000,
266 .state_mem = {
267 .uV = 1800000,
268 .mode = REGULATOR_MODE_NORMAL,
269 .enabled = 1,
270 },
271 .initial_state = PM_SUSPEND_MEM,
272 .always_on = 1,
273 .boot_on = 1,
274 },
275};
276
277/* DDR RAM */
278static struct regulator_init_data sw2a_data = {
279 .constraints = {
280 .name = "SW2A",
281 .min_uV = 1800000,
282 .max_uV = 1800000,
283 .valid_modes_mask = REGULATOR_MODE_NORMAL,
284 .state_mem = {
285 .uV = 1800000,
286 .mode = REGULATOR_MODE_NORMAL,
287 .enabled = 1,
288 },
289 .state_disk = {
290 .mode = REGULATOR_MODE_NORMAL,
291 .enabled = 0,
292 },
293 .always_on = 1,
294 .boot_on = 1,
295 .initial_state = PM_SUSPEND_MEM,
296 },
297};
298
299static struct regulator_init_data ldo1_data = {
300 .constraints = {
301 .name = "VCAM/VMMC1/VMMC2",
302 .min_uV = 2800000,
303 .max_uV = 2800000,
304 .valid_modes_mask = REGULATOR_MODE_NORMAL,
305 .apply_uV = 1,
306 },
307};
308
309static struct regulator_consumer_supply ldo2_consumers[] = {
310 {
311 .supply = "AVDD",
312 },
313 {
314 .supply = "HPVDD",
315 },
316};
317
318/* CODEC and SIM */
319static struct regulator_init_data ldo2_data = {
320 .constraints = {
321 .name = "VESIM/VSIM/AVDD",
322 .min_uV = 3300000,
323 .max_uV = 3300000,
324 .valid_modes_mask = REGULATOR_MODE_NORMAL,
325 .apply_uV = 1,
326 },
327 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
328 .consumer_supplies = ldo2_consumers,
329};
330
331/* General */
332static struct regulator_init_data vdig_data = {
333 .constraints = {
334 .name = "VDIG",
335 .min_uV = 1500000,
336 .max_uV = 1500000,
337 .valid_modes_mask = REGULATOR_MODE_NORMAL,
338 .apply_uV = 1,
339 .always_on = 1,
340 .boot_on = 1,
341 },
342};
343
344/* Tranceivers */
345static struct regulator_init_data ldo4_data = {
346 .constraints = {
347 .name = "VRF1/CVDD_2.775",
348 .min_uV = 2500000,
349 .max_uV = 2500000,
350 .valid_modes_mask = REGULATOR_MODE_NORMAL,
351 .apply_uV = 1,
352 .always_on = 1,
353 .boot_on = 1,
354 },
355};
356
357static struct wm8350_led_platform_data wm8350_led_data = {
358 .name = "wm8350:white",
359 .default_trigger = "heartbeat",
360 .max_uA = 27899,
361};
362
363static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
364 .vmid_discharge_msecs = 1000,
365 .drain_msecs = 30,
366 .cap_discharge_msecs = 700,
367 .vmid_charge_msecs = 700,
368 .vmid_s_curve = WM8350_S_CURVE_SLOW,
369 .dis_out4 = WM8350_DISCHARGE_SLOW,
370 .dis_out3 = WM8350_DISCHARGE_SLOW,
371 .dis_out2 = WM8350_DISCHARGE_SLOW,
372 .dis_out1 = WM8350_DISCHARGE_SLOW,
373 .vroi_out4 = WM8350_TIE_OFF_500R,
374 .vroi_out3 = WM8350_TIE_OFF_500R,
375 .vroi_out2 = WM8350_TIE_OFF_500R,
376 .vroi_out1 = WM8350_TIE_OFF_500R,
377 .vroi_enable = 0,
378 .codec_current_on = WM8350_CODEC_ISEL_1_0,
379 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
380 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
381};
382
383static int mx31_wm8350_init(struct wm8350 *wm8350)
384{
385 int i;
386
387 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
388 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
389 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
390 WM8350_GPIO_DEBOUNCE_ON);
391
392 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
393 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
394 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
395 WM8350_GPIO_DEBOUNCE_ON);
396
397 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
398 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
399 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
400 WM8350_GPIO_DEBOUNCE_OFF);
401
402 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
403 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
404 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
405 WM8350_GPIO_DEBOUNCE_OFF);
406
407 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
408 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
409 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
410 WM8350_GPIO_DEBOUNCE_OFF);
411
412 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
413 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
414 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
415 WM8350_GPIO_DEBOUNCE_OFF);
416
417 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
418 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
419 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
420 WM8350_GPIO_DEBOUNCE_OFF);
421
422 /* Fix up for our own supplies. */
423 for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++)
424 ldo2_consumers[i].dev = wm8350->dev;
425
426 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
427 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
428 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
429 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
430 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
431 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
432 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
433 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
434
435 /* LEDs */
436 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
437 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
438 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
439 WM8350_ISINK_FLASH_DISABLE,
440 WM8350_ISINK_FLASH_TRIG_BIT,
441 WM8350_ISINK_FLASH_DUR_32MS,
442 WM8350_ISINK_FLASH_ON_INSTANT,
443 WM8350_ISINK_FLASH_OFF_INSTANT,
444 WM8350_ISINK_FLASH_MODE_EN);
445 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
446 WM8350_ISINK_MODE_BOOST,
447 WM8350_ISINK_ILIM_NORMAL,
448 WM8350_DC5_RMP_20V,
449 WM8350_DC5_FBSRC_ISINKA);
450 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
451 &wm8350_led_data);
452
453 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
454
455 return 0;
456}
457
458static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
459 .init = mx31_wm8350_init,
460};
461#endif
462
463#if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE)
464static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
465#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
466 {
467 I2C_BOARD_INFO("wm8350", 0x1a),
468 .platform_data = &mx31_wm8350_pdata,
469 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
470 },
471#endif
472};
473
474static void mxc_init_i2c(void)
475{
476 i2c_register_board_info(1, mx31ads_i2c1_devices,
477 ARRAY_SIZE(mx31ads_i2c1_devices));
478
479 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
480 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
481
482 mxc_register_device(&mxc_i2c_device1, NULL);
483}
484#else
485static void mxc_init_i2c(void)
486{
487}
488#endif
489
194/*! 490/*!
195 * This structure defines static mappings for the i.MX31ADS board. 491 * This structure defines static mappings for the i.MX31ADS board.
196 */ 492 */
197static struct map_desc mx31ads_io_desc[] __initdata = { 493static struct map_desc mx31ads_io_desc[] __initdata = {
198 { 494 {
199 .virtual = AIPS1_BASE_ADDR_VIRT,
200 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
201 .length = AIPS1_SIZE,
202 .type = MT_DEVICE_NONSHARED
203 }, {
204 .virtual = SPBA0_BASE_ADDR_VIRT, 495 .virtual = SPBA0_BASE_ADDR_VIRT,
205 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 496 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
206 .length = SPBA0_SIZE, 497 .length = SPBA0_SIZE,
207 .type = MT_DEVICE_NONSHARED 498 .type = MT_DEVICE_NONSHARED
208 }, { 499 }, {
209 .virtual = AIPS2_BASE_ADDR_VIRT,
210 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
211 .length = AIPS2_SIZE,
212 .type = MT_DEVICE_NONSHARED
213 }, {
214 .virtual = CS4_BASE_ADDR_VIRT, 500 .virtual = CS4_BASE_ADDR_VIRT,
215 .pfn = __phys_to_pfn(CS4_BASE_ADDR), 501 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
216 .length = CS4_SIZE / 2, 502 .length = CS4_SIZE / 2,
@@ -221,13 +507,13 @@ static struct map_desc mx31ads_io_desc[] __initdata = {
221/*! 507/*!
222 * Set up static virtual mappings. 508 * Set up static virtual mappings.
223 */ 509 */
224void __init mx31ads_map_io(void) 510static void __init mx31ads_map_io(void)
225{ 511{
226 mxc_map_io(); 512 mxc_map_io();
227 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); 513 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
228} 514}
229 515
230void __init mx31ads_init_irq(void) 516static void __init mx31ads_init_irq(void)
231{ 517{
232 mxc_init_irq(); 518 mxc_init_irq();
233 mx31ads_init_expio(); 519 mx31ads_init_expio();
@@ -240,15 +526,15 @@ static void __init mxc_board_init(void)
240{ 526{
241 mxc_init_extuart(); 527 mxc_init_extuart();
242 mxc_init_imx_uart(); 528 mxc_init_imx_uart();
529 mxc_init_i2c();
243} 530}
244 531
245static void __init mx31ads_timer_init(void) 532static void __init mx31ads_timer_init(void)
246{ 533{
247 mxc_clocks_init(26000000); 534 mx31_clocks_init(26000000);
248 mxc_timer_init("ipg_clk.0");
249} 535}
250 536
251struct sys_timer mx31ads_timer = { 537static struct sys_timer mx31ads_timer = {
252 .init = mx31ads_timer_init, 538 .init = mx31ads_timer_init,
253}; 539};
254 540
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index c43440070143..894d98cd9941 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -42,21 +42,11 @@
42 */ 42 */
43static struct map_desc mx31lite_io_desc[] __initdata = { 43static struct map_desc mx31lite_io_desc[] __initdata = {
44 { 44 {
45 .virtual = AIPS1_BASE_ADDR_VIRT,
46 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
47 .length = AIPS1_SIZE,
48 .type = MT_DEVICE_NONSHARED
49 }, {
50 .virtual = SPBA0_BASE_ADDR_VIRT, 45 .virtual = SPBA0_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), 46 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
52 .length = SPBA0_SIZE, 47 .length = SPBA0_SIZE,
53 .type = MT_DEVICE_NONSHARED 48 .type = MT_DEVICE_NONSHARED
54 }, { 49 }, {
55 .virtual = AIPS2_BASE_ADDR_VIRT,
56 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
57 .length = AIPS2_SIZE,
58 .type = MT_DEVICE_NONSHARED
59 }, {
60 .virtual = CS4_BASE_ADDR_VIRT, 50 .virtual = CS4_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(CS4_BASE_ADDR), 51 .pfn = __phys_to_pfn(CS4_BASE_ADDR),
62 .length = CS4_SIZE, 52 .length = CS4_SIZE,
@@ -82,8 +72,7 @@ static void __init mxc_board_init(void)
82 72
83static void __init mx31lite_timer_init(void) 73static void __init mx31lite_timer_init(void)
84{ 74{
85 mxc_clocks_init(26000000); 75 mx31_clocks_init(26000000);
86 mxc_timer_init("ipg_clk.0");
87} 76}
88 77
89struct sys_timer mx31lite_timer = { 78struct sys_timer mx31lite_timer = {
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
new file mode 100644
index 000000000000..d080b4add79c
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23
24#include <mach/hardware.h>
25#include <mach/common.h>
26#include <mach/imx-uart.h>
27#include <mach/iomux-mx3.h>
28
29#include "devices.h"
30
31static struct imxuart_platform_data uart_pdata = {
32 .flags = IMXUART_HAVE_RTSCTS,
33};
34
35static int mxc_uart1_pins[] = {
36 MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
37 MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
38};
39
40/*
41 * system init for baseboard usage. Will be called by mx31moboard init.
42 */
43void __init mx31moboard_devboard_init(void)
44{
45 printk(KERN_INFO "Initializing mx31devboard peripherals\n");
46 mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1");
47 mxc_register_device(&mxc_uart_device1, &uart_pdata);
48}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
new file mode 100644
index 000000000000..9ef9566823fb
--- /dev/null
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -0,0 +1,37 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21
22#include <linux/platform_device.h>
23
24#include <mach/hardware.h>
25#include <mach/common.h>
26#include <mach/imx-uart.h>
27#include <mach/iomux-mx3.h>
28
29#include "devices.h"
30
31/*
32 * system init for baseboard usage. Will be called by mx31moboard init.
33 */
34void __init mx31moboard_marxbot_init(void)
35{
36 printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
37}
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index c29098af7394..34c2a1b99d4f 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -32,6 +32,7 @@
32#include <mach/common.h> 32#include <mach/common.h>
33#include <mach/imx-uart.h> 33#include <mach/imx-uart.h>
34#include <mach/iomux-mx3.h> 34#include <mach/iomux-mx3.h>
35#include <mach/board-mx31moboard.h>
35 36
36#include "devices.h" 37#include "devices.h"
37 38
@@ -63,6 +64,18 @@ static struct platform_device *devices[] __initdata = {
63 &mx31moboard_flash, 64 &mx31moboard_flash,
64}; 65};
65 66
67static int mxc_uart0_pins[] = {
68 MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1,
69 MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
70};
71static int mxc_uart4_pins[] = {
72 MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
73 MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
74};
75
76static int mx31moboard_baseboard;
77core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
78
66/* 79/*
67 * Board specific initialization. 80 * Board specific initialization.
68 */ 81 */
@@ -70,58 +83,29 @@ static void __init mxc_board_init(void)
70{ 83{
71 platform_add_devices(devices, ARRAY_SIZE(devices)); 84 platform_add_devices(devices, ARRAY_SIZE(devices));
72 85
73 mxc_iomux_mode(MX31_PIN_CTS1__CTS1); 86 mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0");
74 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
75 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
76 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
77
78 mxc_register_device(&mxc_uart_device0, &uart_pdata); 87 mxc_register_device(&mxc_uart_device0, &uart_pdata);
79 88
80 mxc_iomux_mode(MX31_PIN_CTS2__CTS2); 89 mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4");
81 mxc_iomux_mode(MX31_PIN_RTS2__RTS2);
82 mxc_iomux_mode(MX31_PIN_TXD2__TXD2);
83 mxc_iomux_mode(MX31_PIN_RXD2__RXD2);
84
85 mxc_register_device(&mxc_uart_device1, &uart_pdata);
86
87 mxc_iomux_mode(MX31_PIN_PC_RST__CTS5);
88 mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5);
89 mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5);
90 mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5);
91
92 mxc_register_device(&mxc_uart_device4, &uart_pdata); 90 mxc_register_device(&mxc_uart_device4, &uart_pdata);
93}
94 91
95/* 92 switch (mx31moboard_baseboard) {
96 * This structure defines static mappings for the mx31moboard. 93 case MX31NOBOARD:
97 */ 94 break;
98static struct map_desc mx31moboard_io_desc[] __initdata = { 95 case MX31DEVBOARD:
99 { 96 mx31moboard_devboard_init();
100 .virtual = AIPS1_BASE_ADDR_VIRT, 97 break;
101 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), 98 case MX31MARXBOT:
102 .length = AIPS1_SIZE, 99 mx31moboard_marxbot_init();
103 .type = MT_DEVICE_NONSHARED 100 break;
104 }, { 101 default:
105 .virtual = AIPS2_BASE_ADDR_VIRT, 102 printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard);
106 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), 103 }
107 .length = AIPS2_SIZE,
108 .type = MT_DEVICE_NONSHARED
109 },
110};
111
112/*
113 * Set up static virtual mappings.
114 */
115void __init mx31moboard_map_io(void)
116{
117 mxc_map_io();
118 iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc));
119} 104}
120 105
121static void __init mx31moboard_timer_init(void) 106static void __init mx31moboard_timer_init(void)
122{ 107{
123 mxc_clocks_init(26000000); 108 mx31_clocks_init(26000000);
124 mxc_timer_init("ipg_clk.0");
125} 109}
126 110
127struct sys_timer mx31moboard_timer = { 111struct sys_timer mx31moboard_timer = {
@@ -133,7 +117,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
133 .phys_io = AIPS1_BASE_ADDR, 117 .phys_io = AIPS1_BASE_ADDR,
134 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 118 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
135 .boot_params = PHYS_OFFSET + 0x100, 119 .boot_params = PHYS_OFFSET + 0x100,
136 .map_io = mx31moboard_map_io, 120 .map_io = mxc_map_io,
137 .init_irq = mxc_init_irq, 121 .init_irq = mxc_init_irq,
138 .init_machine = mxc_board_init, 122 .init_machine = mxc_board_init,
139 .timer = &mx31moboard_timer, 123 .timer = &mx31moboard_timer,
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index d464d068a4a6..bc63f1785691 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -45,40 +45,17 @@ static struct imxuart_platform_data uart_pdata = {
45 .flags = IMXUART_HAVE_RTSCTS, 45 .flags = IMXUART_HAVE_RTSCTS,
46}; 46};
47 47
48static inline void mxc_init_imx_uart(void) 48static int uart_pins[] = {
49{ 49 MX31_PIN_CTS1__CTS1,
50 mxc_iomux_mode(MX31_PIN_CTS1__CTS1); 50 MX31_PIN_RTS1__RTS1,
51 mxc_iomux_mode(MX31_PIN_RTS1__RTS1); 51 MX31_PIN_TXD1__TXD1,
52 mxc_iomux_mode(MX31_PIN_TXD1__TXD1); 52 MX31_PIN_RXD1__RXD1
53 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
54
55 mxc_register_device(&mxc_uart_device0, &uart_pdata);
56}
57
58/*!
59 * This structure defines static mappings for the i.MX31PDK board.
60 */
61static struct map_desc mx31pdk_io_desc[] __initdata = {
62 {
63 .virtual = AIPS1_BASE_ADDR_VIRT,
64 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
65 .length = AIPS1_SIZE,
66 .type = MT_DEVICE_NONSHARED
67 }, {
68 .virtual = AIPS2_BASE_ADDR_VIRT,
69 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
70 .length = AIPS2_SIZE,
71 .type = MT_DEVICE_NONSHARED
72 },
73}; 53};
74 54
75/*! 55static inline void mxc_init_imx_uart(void)
76 * Set up static virtual mappings.
77 */
78static void __init mx31pdk_map_io(void)
79{ 56{
80 mxc_map_io(); 57 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
81 iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); 58 mxc_register_device(&mxc_uart_device0, &uart_pdata);
82} 59}
83 60
84/*! 61/*!
@@ -91,8 +68,7 @@ static void __init mxc_board_init(void)
91 68
92static void __init mx31pdk_timer_init(void) 69static void __init mx31pdk_timer_init(void)
93{ 70{
94 mxc_clocks_init(26000000); 71 mx31_clocks_init(26000000);
95 mxc_timer_init("ipg_clk.0");
96} 72}
97 73
98static struct sys_timer mx31pdk_timer = { 74static struct sys_timer mx31pdk_timer = {
@@ -108,7 +84,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
108 .phys_io = AIPS1_BASE_ADDR, 84 .phys_io = AIPS1_BASE_ADDR,
109 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 85 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
110 .boot_params = PHYS_OFFSET + 0x100, 86 .boot_params = PHYS_OFFSET + 0x100,
111 .map_io = mx31pdk_map_io, 87 .map_io = mxc_map_io,
112 .init_irq = mxc_init_irq, 88 .init_irq = mxc_init_irq,
113 .init_machine = mxc_board_init, 89 .init_machine = mxc_board_init,
114 .timer = &mx31pdk_timer, 90 .timer = &mx31pdk_timer,
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 8cea82587222..5fce022114de 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -26,6 +26,8 @@
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/smc911x.h> 27#include <linux/smc911x.h>
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/i2c.h>
30#include <linux/i2c/at24.h>
29 31
30#include <mach/hardware.h> 32#include <mach/hardware.h>
31#include <asm/mach-types.h> 33#include <asm/mach-types.h>
@@ -37,6 +39,10 @@
37#include <mach/iomux-mx3.h> 39#include <mach/iomux-mx3.h>
38#include <mach/board-pcm037.h> 40#include <mach/board-pcm037.h>
39#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
42#include <mach/mmc.h>
43#ifdef CONFIG_I2C_IMX
44#include <mach/i2c.h>
45#endif
40 46
41#include "devices.h" 47#include "devices.h"
42 48
@@ -117,12 +123,90 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = {
117 .hw_ecc = 1, 123 .hw_ecc = 1,
118}; 124};
119 125
126#ifdef CONFIG_I2C_IMX
127static int i2c_1_pins[] = {
128 MX31_PIN_CSPI2_MOSI__SCL,
129 MX31_PIN_CSPI2_MISO__SDA,
130};
131
132static int pcm037_i2c_1_init(struct device *dev)
133{
134 return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins),
135 "i2c-1");
136}
137
138static void pcm037_i2c_1_exit(struct device *dev)
139{
140 mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins));
141}
142
143static struct imxi2c_platform_data pcm037_i2c_1_data = {
144 .bitrate = 100000,
145 .init = pcm037_i2c_1_init,
146 .exit = pcm037_i2c_1_exit,
147};
148
149static struct at24_platform_data board_eeprom = {
150 .byte_len = 4096,
151 .page_size = 32,
152 .flags = AT24_FLAG_ADDR16,
153};
154
155static struct i2c_board_info pcm037_i2c_devices[] = {
156 {
157 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
158 .platform_data = &board_eeprom,
159 }, {
160 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
161 .type = "pcf8563",
162 }
163};
164#endif
165
166static int sdhc1_pins[] = {
167 MX31_PIN_SD1_DATA3__SD1_DATA3,
168 MX31_PIN_SD1_DATA2__SD1_DATA2,
169 MX31_PIN_SD1_DATA1__SD1_DATA1,
170 MX31_PIN_SD1_DATA0__SD1_DATA0,
171 MX31_PIN_SD1_CLK__SD1_CLK,
172 MX31_PIN_SD1_CMD__SD1_CMD,
173};
174
175static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data)
176{
177 return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins),
178 "sdhc-1");
179}
180
181static void pcm970_sdhc1_exit(struct device *dev, void *data)
182{
183 mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins));
184}
185
186/* No card and rw detection at the moment */
187static struct imxmmc_platform_data sdhc_pdata = {
188 .init = pcm970_sdhc1_init,
189 .exit = pcm970_sdhc1_exit,
190};
191
120static struct platform_device *devices[] __initdata = { 192static struct platform_device *devices[] __initdata = {
121 &pcm037_flash, 193 &pcm037_flash,
122 &pcm037_eth, 194 &pcm037_eth,
123 &pcm037_sram_device, 195 &pcm037_sram_device,
124}; 196};
125 197
198static int uart0_pins[] = {
199 MX31_PIN_CTS1__CTS1,
200 MX31_PIN_RTS1__RTS1,
201 MX31_PIN_TXD1__TXD1,
202 MX31_PIN_RXD1__RXD1
203};
204
205static int uart2_pins[] = {
206 MX31_PIN_CSPI3_MOSI__RXD3,
207 MX31_PIN_CSPI3_MISO__TXD3
208};
209
126/* 210/*
127 * Board specific initialization. 211 * Board specific initialization.
128 */ 212 */
@@ -130,59 +214,33 @@ static void __init mxc_board_init(void)
130{ 214{
131 platform_add_devices(devices, ARRAY_SIZE(devices)); 215 platform_add_devices(devices, ARRAY_SIZE(devices));
132 216
133 mxc_iomux_mode(MX31_PIN_CTS1__CTS1); 217 mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0");
134 mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
135 mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
136 mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
137
138 mxc_register_device(&mxc_uart_device0, &uart_pdata); 218 mxc_register_device(&mxc_uart_device0, &uart_pdata);
139 219
140 mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3); 220 mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2");
141 mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3);
142
143 mxc_register_device(&mxc_uart_device2, &uart_pdata); 221 mxc_register_device(&mxc_uart_device2, &uart_pdata);
144 222
145 mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE); 223 mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire");
146 mxc_register_device(&mxc_w1_master_device, NULL); 224 mxc_register_device(&mxc_w1_master_device, NULL);
147 225
148 /* SMSC9215 IRQ pin */ 226 /* SMSC9215 IRQ pin */
149 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)); 227 if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
150 if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth")) 228 "pcm037-eth"))
151 gpio_direction_input(MX31_PIN_GPIO3_1); 229 gpio_direction_input(MX31_PIN_GPIO3_1);
152 230
153 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); 231#ifdef CONFIG_I2C_IMX
154} 232 i2c_register_board_info(1, pcm037_i2c_devices,
233 ARRAY_SIZE(pcm037_i2c_devices));
155 234
156/* 235 mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
157 * This structure defines static mappings for the pcm037 board. 236#endif
158 */ 237 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
159static struct map_desc pcm037_io_desc[] __initdata = { 238 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
160 {
161 .virtual = AIPS1_BASE_ADDR_VIRT,
162 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
163 .length = AIPS1_SIZE,
164 .type = MT_DEVICE_NONSHARED
165 }, {
166 .virtual = AIPS2_BASE_ADDR_VIRT,
167 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
168 .length = AIPS2_SIZE,
169 .type = MT_DEVICE_NONSHARED
170 },
171};
172
173/*
174 * Set up static virtual mappings.
175 */
176void __init pcm037_map_io(void)
177{
178 mxc_map_io();
179 iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc));
180} 239}
181 240
182static void __init pcm037_timer_init(void) 241static void __init pcm037_timer_init(void)
183{ 242{
184 mxc_clocks_init(26000000); 243 mx31_clocks_init(26000000);
185 mxc_timer_init("ipg_clk.0");
186} 244}
187 245
188struct sys_timer pcm037_timer = { 246struct sys_timer pcm037_timer = {
@@ -194,7 +252,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
194 .phys_io = AIPS1_BASE_ADDR, 252 .phys_io = AIPS1_BASE_ADDR,
195 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, 253 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
196 .boot_params = PHYS_OFFSET + 0x100, 254 .boot_params = PHYS_OFFSET + 0x100,
197 .map_io = pcm037_map_io, 255 .map_io = mxc_map_io,
198 .init_irq = mxc_init_irq, 256 .init_irq = mxc_init_irq,
199 .init_machine = mxc_board_init, 257 .init_machine = mxc_board_init,
200 .timer = &pcm037_timer, 258 .timer = &pcm037_timer,
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
new file mode 100644
index 000000000000..6c4283cec6f4
--- /dev/null
+++ b/arch/arm/mach-mx3/qong.c
@@ -0,0 +1,312 @@
1/*
2 * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/types.h>
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/memory.h>
23#include <linux/platform_device.h>
24#include <linux/mtd/physmap.h>
25#include <linux/mtd/nand.h>
26#include <linux/gpio.h>
27
28#include <mach/hardware.h>
29#include <mach/irqs.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33#include <asm/mach/map.h>
34#include <mach/common.h>
35#include <asm/page.h>
36#include <asm/setup.h>
37#include <mach/board-qong.h>
38#include <mach/imx-uart.h>
39#include <mach/iomux-mx3.h>
40#include "devices.h"
41
42/* FPGA defines */
43#define QONG_FPGA_VERSION(major, minor, rev) \
44 (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
45
46#define QONG_FPGA_BASEADDR CS1_BASE_ADDR
47#define QONG_FPGA_PERIPH_SIZE (1 << 24)
48
49#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
50#define QONG_FPGA_CTRL_SIZE 0x10
51/* FPGA control registers */
52#define QONG_FPGA_CTRL_VERSION 0x00
53
54#define QONG_DNET_ID 1
55#define QONG_DNET_BASEADDR \
56 (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
57#define QONG_DNET_SIZE 0x00001000
58
59#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
60
61/*
62 * This file contains the board-specific initialization routines.
63 */
64
65static struct imxuart_platform_data uart_pdata = {
66 .flags = IMXUART_HAVE_RTSCTS,
67};
68
69static int uart_pins[] = {
70 MX31_PIN_CTS1__CTS1,
71 MX31_PIN_RTS1__RTS1,
72 MX31_PIN_TXD1__TXD1,
73 MX31_PIN_RXD1__RXD1
74};
75
76static inline void mxc_init_imx_uart(void)
77{
78 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
79 "uart-0");
80 mxc_register_device(&mxc_uart_device0, &uart_pdata);
81}
82
83static struct resource dnet_resources[] = {
84 [0] = {
85 .name = "dnet-memory",
86 .start = QONG_DNET_BASEADDR,
87 .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = QONG_FPGA_IRQ,
92 .end = QONG_FPGA_IRQ,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97static struct platform_device dnet_device = {
98 .name = "dnet",
99 .id = -1,
100 .num_resources = ARRAY_SIZE(dnet_resources),
101 .resource = dnet_resources,
102};
103
104static int __init qong_init_dnet(void)
105{
106 int ret;
107
108 ret = platform_device_register(&dnet_device);
109 return ret;
110}
111
112/* MTD NOR flash */
113
114static struct physmap_flash_data qong_flash_data = {
115 .width = 2,
116};
117
118static struct resource qong_flash_resource = {
119 .start = CS0_BASE_ADDR,
120 .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
121 .flags = IORESOURCE_MEM,
122};
123
124static struct platform_device qong_nor_mtd_device = {
125 .name = "physmap-flash",
126 .id = 0,
127 .dev = {
128 .platform_data = &qong_flash_data,
129 },
130 .resource = &qong_flash_resource,
131 .num_resources = 1,
132};
133
134static void qong_init_nor_mtd(void)
135{
136 (void)platform_device_register(&qong_nor_mtd_device);
137}
138
139/*
140 * Hardware specific access to control-lines
141 */
142static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
143{
144 struct nand_chip *nand_chip = mtd->priv;
145
146 if (cmd == NAND_CMD_NONE)
147 return;
148
149 if (ctrl & NAND_CLE)
150 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
151 else
152 writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
153}
154
155/*
156 * Read the Device Ready pin.
157 */
158static int qong_nand_device_ready(struct mtd_info *mtd)
159{
160 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
161}
162
163static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
164{
165 if (chip >= 0)
166 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
167 else
168 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
169}
170
171static struct platform_nand_data qong_nand_data = {
172 .chip = {
173 .chip_delay = 20,
174 .options = 0,
175 },
176 .ctrl = {
177 .cmd_ctrl = qong_nand_cmd_ctrl,
178 .dev_ready = qong_nand_device_ready,
179 .select_chip = qong_nand_select_chip,
180 }
181};
182
183static struct resource qong_nand_resource = {
184 .start = CS3_BASE_ADDR,
185 .end = CS3_BASE_ADDR + SZ_32M - 1,
186 .flags = IORESOURCE_MEM,
187};
188
189static struct platform_device qong_nand_device = {
190 .name = "gen_nand",
191 .id = -1,
192 .dev = {
193 .platform_data = &qong_nand_data,
194 },
195 .num_resources = 1,
196 .resource = &qong_nand_resource,
197};
198
199static void __init qong_init_nand_mtd(void)
200{
201 /* init CS */
202 __raw_writel(0x00004f00, CSCR_U(3));
203 __raw_writel(0x20013b31, CSCR_L(3));
204 __raw_writel(0x00020800, CSCR_A(3));
205 mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
206
207 /* enable pin */
208 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
209 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
210 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
211
212 /* ready/busy pin */
213 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
214 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
215 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
216
217 /* write protect pin */
218 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
219 if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
220 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
221
222 platform_device_register(&qong_nand_device);
223}
224
225static void __init qong_init_fpga(void)
226{
227 void __iomem *regs;
228 u32 fpga_ver;
229
230 regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
231 if (!regs) {
232 printk(KERN_ERR "%s: failed to map registers, aborting.\n",
233 __func__);
234 return;
235 }
236
237 fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
238 iounmap(regs);
239 printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
240 (fpga_ver & 0xF000) >> 12,
241 (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
242 if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
243 printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
244 "devices won't be registered!\n");
245 return;
246 }
247
248 /* register FPGA-based devices */
249 qong_init_nand_mtd();
250 qong_init_dnet();
251}
252
253/*
254 * This structure defines the MX31 memory map.
255 */
256static struct map_desc qong_io_desc[] __initdata = {
257 {
258 .virtual = AIPS1_BASE_ADDR_VIRT,
259 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
260 .length = AIPS1_SIZE,
261 .type = MT_DEVICE_NONSHARED
262 }, {
263 .virtual = AIPS2_BASE_ADDR_VIRT,
264 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
265 .length = AIPS2_SIZE,
266 .type = MT_DEVICE_NONSHARED
267 }
268};
269
270/*
271 * Set up static virtual mappings.
272 */
273static void __init qong_map_io(void)
274{
275 mxc_map_io();
276 iotable_init(qong_io_desc, ARRAY_SIZE(qong_io_desc));
277}
278
279/*
280 * Board specific initialization.
281 */
282static void __init mxc_board_init(void)
283{
284 mxc_init_imx_uart();
285 qong_init_nor_mtd();
286 qong_init_fpga();
287}
288
289static void __init qong_timer_init(void)
290{
291 mx31_clocks_init(26000000);
292}
293
294static struct sys_timer qong_timer = {
295 .init = qong_timer_init,
296};
297
298/*
299 * The following uses standard kernel macros defined in arch.h in order to
300 * initialize __mach_desc_QONG data structure.
301 */
302
303MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
304 /* Maintainer: DENX Software Engineering GmbH */
305 .phys_io = AIPS1_BASE_ADDR,
306 .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
307 .boot_params = PHYS_OFFSET + 0x100,
308 .map_io = qong_map_io,
309 .init_irq = mxc_init_irq,
310 .init_machine = mxc_board_init,
311 .timer = &qong_timer,
312MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f6a13451d1fd..6031e179926b 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -81,7 +81,7 @@ static inline void __init ldp_init_smc911x(void)
81 } 81 }
82 82
83 ldp_smc911x_resources[0].start = cs_mem_base + 0x0; 83 ldp_smc911x_resources[0].start = cs_mem_base + 0x0;
84 ldp_smc911x_resources[0].end = cs_mem_base + 0xf; 84 ldp_smc911x_resources[0].end = cs_mem_base + 0xff;
85 udelay(100); 85 udelay(100);
86 86
87 eth_gpio = LDP_SMC911X_GPIO; 87 eth_gpio = LDP_SMC911X_GPIO;
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ad721e0cbf7a..ce4d46a4a838 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -565,7 +565,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
565 * 565 *
566 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor, 566 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
567 * find the corresponding register field value. The return register value is 567 * find the corresponding register field value. The return register value is
568 * the value before left-shifting. Returns 0xffffffff on error 568 * the value before left-shifting. Returns ~0 on error
569 */ 569 */
570u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) 570u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
571{ 571{
@@ -577,7 +577,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
577 577
578 clks = omap2_get_clksel_by_parent(clk, clk->parent); 578 clks = omap2_get_clksel_by_parent(clk, clk->parent);
579 if (clks == NULL) 579 if (clks == NULL)
580 return 0; 580 return ~0;
581 581
582 for (clkr = clks->rates; clkr->div; clkr++) { 582 for (clkr = clks->rates; clkr->div; clkr++) {
583 if ((clkr->flags & cpu_mask) && (clkr->div == div)) 583 if ((clkr->flags & cpu_mask) && (clkr->div == div))
@@ -588,7 +588,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
588 printk(KERN_ERR "clock: Could not find divisor %d for " 588 printk(KERN_ERR "clock: Could not find divisor %d for "
589 "clock %s parent %s\n", div, clk->name, 589 "clock %s parent %s\n", div, clk->name,
590 clk->parent->name); 590 clk->parent->name);
591 return 0; 591 return ~0;
592 } 592 }
593 593
594 return clkr->val; 594 return clkr->val;
@@ -708,7 +708,7 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
708 return 0; 708 return 0;
709 709
710 for (clkr = clks->rates; clkr->div; clkr++) { 710 for (clkr = clks->rates; clkr->div; clkr++) {
711 if (clkr->flags & (cpu_mask | DEFAULT_RATE)) 711 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
712 break; /* Found the default rate for this platform */ 712 break; /* Found the default rate for this platform */
713 } 713 }
714 714
@@ -746,7 +746,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
746 return -EINVAL; 746 return -EINVAL;
747 747
748 if (clk->usecount > 0) 748 if (clk->usecount > 0)
749 _omap2_clk_disable(clk); 749 omap2_clk_disable(clk);
750 750
751 /* Set new source value (previous dividers if any in effect) */ 751 /* Set new source value (previous dividers if any in effect) */
752 reg_val = __raw_readl(src_addr) & ~field_mask; 752 reg_val = __raw_readl(src_addr) & ~field_mask;
@@ -759,11 +759,11 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
759 wmb(); 759 wmb();
760 } 760 }
761 761
762 if (clk->usecount > 0)
763 _omap2_clk_enable(clk);
764
765 clk->parent = new_parent; 762 clk->parent = new_parent;
766 763
764 if (clk->usecount > 0)
765 omap2_clk_enable(clk);
766
767 /* CLKSEL clocks follow their parents' rates, divided by a divisor */ 767 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
768 clk->rate = new_parent->rate; 768 clk->rate = new_parent->rate;
769 769
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 0caae43301e5..e03f7b45cb0d 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -44,7 +44,7 @@ void __init orion5x_init_irq(void)
44 * User can use set_type() if he wants to use edge types handlers. 44 * User can use set_type() if he wants to use edge types handlers.
45 */ 45 */
46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) { 46 for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
47 set_irq_chip(i, &orion_gpio_irq_level_chip); 47 set_irq_chip(i, &orion_gpio_irq_chip);
48 set_irq_handler(i, handle_level_irq); 48 set_irq_handler(i, handle_level_irq);
49 irq_desc[i].status |= IRQ_LEVEL; 49 irq_desc[i].status |= IRQ_LEVEL;
50 set_irq_flags(i, IRQF_VALID); 50 set_irq_flags(i, IRQF_VALID);
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index e88d417736af..c7fc01e9d1f6 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -19,6 +19,7 @@
19#include <linux/serial_8250.h> 19#include <linux/serial_8250.h>
20#include <linux/ata_platform.h> 20#include <linux/ata_platform.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/i2c.h>
22 23
23#include <asm/elf.h> 24#include <asm/elf.h>
24#include <asm/mach-types.h> 25#include <asm/mach-types.h>
@@ -201,8 +202,13 @@ static struct platform_device *devs[] __initdata = {
201 &pata_device, 202 &pata_device,
202}; 203};
203 204
205static struct i2c_board_info i2c_rtc = {
206 I2C_BOARD_INFO("pcf8583", 0x50)
207};
208
204static int __init rpc_init(void) 209static int __init rpc_init(void)
205{ 210{
211 i2c_register_board_info(0, &i2c_rtc, 1);
206 return platform_add_devices(devs, ARRAY_SIZE(devs)); 212 return platform_add_devices(devs, ARRAY_SIZE(devs));
207} 213}
208 214
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d490f3773c01..0d8581f11211 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -704,7 +704,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
704 704
705config CACHE_L2X0 705config CACHE_L2X0
706 bool "Enable the L2x0 outer cache controller" 706 bool "Enable the L2x0 outer cache controller"
707 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP 707 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
708 REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31
708 default y 709 default y
709 select OUTER_CACHE 710 select OUTER_CACHE
710 help 711 help
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 8a7f65ba14b7..94077fbd96b7 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -23,7 +23,8 @@ ENTRY(v6_early_abort)
23#ifdef CONFIG_CPU_32v6K 23#ifdef CONFIG_CPU_32v6K
24 clrex 24 clrex
25#else 25#else
26 strex r0, r1, [sp] @ Clear the exclusive monitor 26 sub r1, sp, #4 @ Get unused stack location
27 strex r0, r1, [r1] @ Clear the exclusive monitor
27#endif 28#endif
28 mrc p15, 0, r1, c5, c0, 0 @ get FSR 29 mrc p15, 0, r1, c5, c0, 0 @ get FSR
29 mrc p15, 0, r0, c6, c0, 0 @ get FAR 30 mrc p15, 0, r0, c6, c0, 0 @ get FAR
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index aa424e1da8a1..8c6fc5a6237e 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -716,7 +716,8 @@ static void __init sanity_check_meminfo(void)
716 * Check whether this memory bank would entirely overlap 716 * Check whether this memory bank would entirely overlap
717 * the vmalloc area. 717 * the vmalloc area.
718 */ 718 */
719 if (__va(bank->start) >= VMALLOC_MIN) { 719 if (__va(bank->start) >= VMALLOC_MIN ||
720 __va(bank->start) < PAGE_OFFSET) {
720 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " 721 printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
721 "(vmalloc region overlap).\n", 722 "(vmalloc region overlap).\n",
722 bank->start, bank->start + bank->size - 1); 723 bank->start, bank->start + bank->size - 1);
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 9cc2b16fdf79..17d0e9906d5f 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -3,7 +3,7 @@ if ARCH_MXC
3menu "Freescale MXC Implementations" 3menu "Freescale MXC Implementations"
4 4
5choice 5choice
6 prompt "MXC/iMX Base Type" 6 prompt "Freescale CPU family:"
7 default ARCH_MX3 7 default ARCH_MX3
8 8
9config ARCH_MX1 9config ARCH_MX1
@@ -15,12 +15,14 @@ config ARCH_MX1
15config ARCH_MX2 15config ARCH_MX2
16 bool "MX2-based" 16 bool "MX2-based"
17 select CPU_ARM926T 17 select CPU_ARM926T
18 select COMMON_CLKDEV
18 help 19 help
19 This enables support for systems based on the Freescale i.MX2 family 20 This enables support for systems based on the Freescale i.MX2 family
20 21
21config ARCH_MX3 22config ARCH_MX3
22 bool "MX3-based" 23 bool "MX3-based"
23 select CPU_V6 24 select CPU_V6
25 select COMMON_CLKDEV
24 help 26 help
25 This enables support for systems based on the Freescale i.MX3 family 27 This enables support for systems based on the Freescale i.MX3 family
26 28
@@ -43,4 +45,10 @@ config MXC_IRQ_PRIOR
43 requirements for timing. 45 requirements for timing.
44 Say N here, unless you have a specialized requirement. 46 Say N here, unless you have a specialized requirement.
45 47
48config MXC_PWM
49 tristate "Enable PWM driver"
50 depends on ARCH_MXC
51 help
52 Enable support for the i.MX PWM controller(s).
53
46endif 54endif
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index db74a929179d..564fd4ebf38a 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,8 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o 6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o
7 7
8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o 8obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o 9obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o
10obj-$(CONFIG_MXC_PWM) += pwm.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 0a38f0b396eb..92e13566cd4f 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -48,6 +48,11 @@ static DEFINE_MUTEX(clocks_mutex);
48 *-------------------------------------------------------------------------*/ 48 *-------------------------------------------------------------------------*/
49 49
50/* 50/*
51 * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
52 * MXC architectures have switched to using clkdev.
53 */
54#ifndef CONFIG_COMMON_CLKDEV
55/*
51 * Retrieve a clock by name. 56 * Retrieve a clock by name.
52 * 57 *
53 * Note that we first try to use device id on the bus 58 * Note that we first try to use device id on the bus
@@ -110,6 +115,7 @@ found:
110 return clk; 115 return clk;
111} 116}
112EXPORT_SYMBOL(clk_get); 117EXPORT_SYMBOL(clk_get);
118#endif
113 119
114static void __clk_disable(struct clk *clk) 120static void __clk_disable(struct clk *clk)
115{ 121{
@@ -187,6 +193,7 @@ unsigned long clk_get_rate(struct clk *clk)
187} 193}
188EXPORT_SYMBOL(clk_get_rate); 194EXPORT_SYMBOL(clk_get_rate);
189 195
196#ifndef CONFIG_COMMON_CLKDEV
190/* Decrement the clock's module reference count */ 197/* Decrement the clock's module reference count */
191void clk_put(struct clk *clk) 198void clk_put(struct clk *clk)
192{ 199{
@@ -194,6 +201,7 @@ void clk_put(struct clk *clk)
194 module_put(clk->owner); 201 module_put(clk->owner);
195} 202}
196EXPORT_SYMBOL(clk_put); 203EXPORT_SYMBOL(clk_put);
204#endif
197 205
198/* Round the requested clock rate to the nearest supported 206/* Round the requested clock rate to the nearest supported
199 * rate that is less than or equal to the requested rate. 207 * rate that is less than or equal to the requested rate.
@@ -257,6 +265,7 @@ struct clk *clk_get_parent(struct clk *clk)
257} 265}
258EXPORT_SYMBOL(clk_get_parent); 266EXPORT_SYMBOL(clk_get_parent);
259 267
268#ifndef CONFIG_COMMON_CLKDEV
260/* 269/*
261 * Add a new clock to the clock tree. 270 * Add a new clock to the clock tree.
262 */ 271 */
@@ -327,4 +336,49 @@ static int __init mxc_setup_proc_entry(void)
327} 336}
328 337
329late_initcall(mxc_setup_proc_entry); 338late_initcall(mxc_setup_proc_entry);
339#endif /* CONFIG_PROC_FS */
340#endif
341
342/*
343 * Get the resulting clock rate from a PLL register value and the input
344 * frequency. PLLs with this register layout can at least be found on
345 * MX1, MX21, MX27 and MX31
346 *
347 * mfi + mfn / (mfd + 1)
348 * f = 2 * f_ref * --------------------
349 * pd + 1
350 */
351unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
352{
353 long long ll;
354 int mfn_abs;
355 unsigned int mfi, mfn, mfd, pd;
356
357 mfi = (reg_val >> 10) & 0xf;
358 mfn = reg_val & 0x3ff;
359 mfd = (reg_val >> 16) & 0x3ff;
360 pd = (reg_val >> 26) & 0xf;
361
362 mfi = mfi <= 5 ? 5 : mfi;
363
364 mfn_abs = mfn;
365
366#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
367 if (mfn >= 0x200) {
368 mfn |= 0xFFFFFE00;
369 mfn_abs = -mfn;
370 }
330#endif 371#endif
372
373 freq *= 2;
374 freq /= pd + 1;
375
376 ll = (unsigned long long)freq * mfn_abs;
377
378 do_div(ll, mfd + 1);
379 if (mfn < 0)
380 ll = -ll;
381 ll = (freq * mfi) + ll;
382
383 return ll;
384}
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c
new file mode 100644
index 000000000000..386e0d52cf58
--- /dev/null
+++ b/arch/arm/plat-mxc/cpu.c
@@ -0,0 +1,11 @@
1
2#include <linux/module.h>
3
4unsigned int __mxc_cpu_type;
5EXPORT_SYMBOL(__mxc_cpu_type);
6
7void mxc_set_cpu_type(unsigned int type)
8{
9 __mxc_cpu_type = type;
10}
11
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index c66748267c45..56f2fb5cc456 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -19,6 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <mach/common.h>
22 23
23int __init mxc_register_device(struct platform_device *pdev, void *data) 24int __init mxc_register_device(struct platform_device *pdev, void *data)
24{ 25{
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index a9bab15f0fd0..e364a5ed10f1 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -802,7 +802,7 @@ static int __init imx_dma_init(void)
802 int ret = 0; 802 int ret = 0;
803 int i; 803 int i;
804 804
805 dma_clk = clk_get(NULL, "dma_clk"); 805 dma_clk = clk_get(NULL, "dma");
806 clk_enable(dma_clk); 806 clk_enable(dma_clk);
807 807
808 /* reset DMA module */ 808 /* reset DMA module */
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index ccbd94adc668..c6483bad8a26 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -200,8 +200,8 @@ static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
200static int mxc_gpio_direction_output(struct gpio_chip *chip, 200static int mxc_gpio_direction_output(struct gpio_chip *chip,
201 unsigned offset, int value) 201 unsigned offset, int value)
202{ 202{
203 _set_gpio_direction(chip, offset, 1);
204 mxc_gpio_set(chip, offset, value); 203 mxc_gpio_set(chip, offset, value);
204 _set_gpio_direction(chip, offset, 1);
205 return 0; 205 return 0;
206} 206}
207 207
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index 8f34a05afc87..1cac9d1135cd 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -48,7 +48,8 @@
48 * Base address of PBC controller, CS4 48 * Base address of PBC controller, CS4
49 */ 49 */
50#define PBC_BASE_ADDRESS 0xEB000000 50#define PBC_BASE_ADDRESS 0xEB000000
51#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) 51#define PBC_REG_ADDR(offset) (void __force __iomem *) \
52 (PBC_BASE_ADDRESS + (offset))
52 53
53/* 54/*
54 * PBC Interupt name definitions 55 * PBC Interupt name definitions
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 451d510d08c3..318c72ada13d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -11,6 +11,8 @@
11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 11#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ 12#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
13 13
14#include <mach/hardware.h>
15
14/* Base address of PBC controller */ 16/* Base address of PBC controller */
15#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) 17#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
16/* Offsets for the PBC Controller register */ 18/* Offsets for the PBC Controller register */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
new file mode 100644
index 000000000000..f8aef1babb75
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
20#define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__
28
29enum mx31moboard_boards {
30 MX31NOBOARD = 0,
31 MX31DEVBOARD = 1,
32 MX31MARXBOT = 2,
33};
34
35/*
36 * This CPU module needs a baseboard to work. After basic initializing
37 * its own devices, it calls baseboard's init function.
38 */
39
40extern void mx31moboard_devboard_init(void);
41extern void mx31moboard_marxbot_init(void);
42
43#endif
44
45#endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
new file mode 100644
index 000000000000..4ff762dd45cf
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
12#define __ASM_ARCH_MXC_BOARD_QONG_H__
13
14/* mandatory for CONFIG_LL_DEBUG */
15
16#define MXC_LL_UART_PADDR UART1_BASE_ADDR
17#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
18
19/* NOR FLASH */
20#define QONG_NOR_SIZE (128*1024*1024)
21
22#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
index d21f78e78819..43a82d0c534d 100644
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ b/arch/arm/plat-mxc/include/mach/clock.h
@@ -26,9 +26,13 @@
26struct module; 26struct module;
27 27
28struct clk { 28struct clk {
29#ifndef CONFIG_COMMON_CLKDEV
30 /* As soon as i.MX1 and i.MX31 switched to clkdev, this
31 * block can go away */
29 struct list_head node; 32 struct list_head node;
30 struct module *owner; 33 struct module *owner;
31 const char *name; 34 const char *name;
35#endif
32 int id; 36 int id;
33 /* Source clock this clk depends on */ 37 /* Source clock this clk depends on */
34 struct clk *parent; 38 struct clk *parent;
@@ -63,5 +67,7 @@ struct clk {
63int clk_register(struct clk *clk); 67int clk_register(struct clk *clk);
64void clk_unregister(struct clk *clk); 68void clk_unregister(struct clk *clk);
65 69
70unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
71
66#endif /* __ASSEMBLY__ */ 72#endif /* __ASSEMBLY__ */
67#endif /* __ASM_ARCH_MXC_CLOCK_H__ */ 73#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 6350287a59b9..b2f9b72644db 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -12,12 +12,18 @@
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct platform_device; 14struct platform_device;
15struct clk;
15 16
16extern void mxc_map_io(void); 17extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 18extern void mxc_init_irq(void);
18extern void mxc_timer_init(const char *clk_timer); 19extern void mxc_timer_init(struct clk *timer_clk);
19extern int mxc_clocks_init(unsigned long fref); 20extern int mx1_clocks_init(unsigned long fref);
21extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
22extern int mx27_clocks_init(unsigned long fref);
23extern int mx31_clocks_init(unsigned long fref);
24extern int mx35_clocks_init(void);
20extern int mxc_register_gpios(void); 25extern int mxc_register_gpios(void);
21extern int mxc_register_device(struct platform_device *pdev, void *data); 26extern int mxc_register_device(struct platform_device *pdev, void *data);
27extern void mxc_set_cpu_type(unsigned int type);
22 28
23#endif 29#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 602768b427e2..4f773148bc20 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -31,6 +31,9 @@
31#ifdef CONFIG_MACH_MX31_3DS 31#ifdef CONFIG_MACH_MX31_3DS
32#include <mach/board-mx31pdk.h> 32#include <mach/board-mx31pdk.h>
33#endif 33#endif
34#ifdef CONFIG_MACH_QONG
35#include <mach/board-qong.h>
36#endif
34 .macro addruart,rx 37 .macro addruart,rx
35 mrc p15, 0, \rx, c1, c0 38 mrc p15, 0, \rx, c1, c0
36 tst \rx, #1 @ MMU enabled? 39 tst \rx, #1 @ MMU enabled?
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index a612d8bb73c8..42e4ee37ca1f 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -23,10 +23,16 @@
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#ifdef CONFIG_ARCH_MX3 25#ifdef CONFIG_ARCH_MX3
26# include <mach/mx31.h> 26#include <mach/mx3x.h>
27#include <mach/mx31.h>
28#include <mach/mx35.h>
27#endif 29#endif
28 30
29#ifdef CONFIG_ARCH_MX2 31#ifdef CONFIG_ARCH_MX2
32# include <mach/mx2x.h>
33# ifdef CONFIG_MACH_MX21
34# include <mach/mx21.h>
35# endif
30# ifdef CONFIG_MACH_MX27 36# ifdef CONFIG_MACH_MX27
31# include <mach/mx27.h> 37# include <mach/mx27.h>
32# endif 38# endif
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 870d0d939616..762a7b0430e2 100644
--- a/arch/arm/mach-imx/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -76,6 +76,9 @@ struct imx_fb_platform_data {
76 u_char * fixed_screen_cpu; 76 u_char * fixed_screen_cpu;
77 dma_addr_t fixed_screen_dma; 77 dma_addr_t fixed_screen_dma;
78 78
79 int (*init)(struct platform_device*);
80 int (*exit)(struct platform_device*);
81
79 void (*lcd_power)(int); 82 void (*lcd_power)(int);
80 void (*backlight_power)(int); 83 void (*backlight_power)(int);
81}; 84};
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
deleted file mode 100644
index 95a383be628e..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
+++ /dev/null
@@ -1,416 +0,0 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef _MXC_GPIO_MX1_MX2_H
20#define _MXC_GPIO_MX1_MX2_H
21
22#include <linux/io.h>
23
24/*
25 * GPIO Module and I/O Multiplexer
26 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
27 */
28#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
29#define MXC_DDIR(x) (0x00 + ((x) << 8))
30#define MXC_OCR1(x) (0x04 + ((x) << 8))
31#define MXC_OCR2(x) (0x08 + ((x) << 8))
32#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
33#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
34#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
35#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
36#define MXC_DR(x) (0x1c + ((x) << 8))
37#define MXC_GIUS(x) (0x20 + ((x) << 8))
38#define MXC_SSR(x) (0x24 + ((x) << 8))
39#define MXC_ICR1(x) (0x28 + ((x) << 8))
40#define MXC_ICR2(x) (0x2c + ((x) << 8))
41#define MXC_IMR(x) (0x30 + ((x) << 8))
42#define MXC_ISR(x) (0x34 + ((x) << 8))
43#define MXC_GPR(x) (0x38 + ((x) << 8))
44#define MXC_SWR(x) (0x3c + ((x) << 8))
45#define MXC_PUEN(x) (0x40 + ((x) << 8))
46
47#ifdef CONFIG_ARCH_MX1
48# define GPIO_PORT_MAX 3
49#endif
50#ifdef CONFIG_ARCH_MX2
51# define GPIO_PORT_MAX 5
52#endif
53
54#ifndef GPIO_PORT_MAX
55# error "GPIO config port count unknown!"
56#endif
57
58#define GPIO_PIN_MASK 0x1f
59
60#define GPIO_PORT_SHIFT 5
61#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
62
63#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
64#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
65#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
66#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
67#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
68#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
69
70#define GPIO_OUT (1 << 8)
71#define GPIO_IN (0 << 8)
72#define GPIO_PUEN (1 << 9)
73
74#define GPIO_PF (1 << 10)
75#define GPIO_AF (1 << 11)
76
77#define GPIO_OCR_SHIFT 12
78#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
79#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
80#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
81#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
82#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
83
84#define GPIO_AOUT_SHIFT 14
85#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
86#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
87#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
89#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
90
91#define GPIO_BOUT_SHIFT 16
92#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
93#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
94#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
96#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
97
98extern void mxc_gpio_mode(int gpio_mode);
99extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
100 const char *label);
101extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
102
103/*-------------------------------------------------------------------------*/
104
105/* assignements for GPIO alternate/primary functions */
106
107/* FIXME: This list is not completed. The correct directions are
108 * missing on some (many) pins
109 */
110#ifdef CONFIG_ARCH_MX1
111#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0)
112#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
113#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1)
114#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
115#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
116#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
117#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
118#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
119#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
120#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
121#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
122#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
123#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
124#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
125#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
126#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
127#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
128#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
129#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
130#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
131#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17)
132#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
133#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
134#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
135#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
136#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
137#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
138#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
139#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
140#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
141#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
142#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
143#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
144#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
145#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
146#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
147#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
148#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
149#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
150#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
151#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
152#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
153#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
154#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
155#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
156#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
157#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
158#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
159#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
160#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
161#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
162#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
163#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
164#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
165#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
166#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
167#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
168#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
169#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
170#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
171#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
172#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
173#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
174#define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22)
175#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
176#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
177#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
178#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
179#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
180#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
181#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
182#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
183#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
184#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
185#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
186#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
187#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
188#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
189#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
190#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
191#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
192#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
193#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
194#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
195#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
196#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
197#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
198#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
199#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
200#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
201#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26)
202#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
203#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
204#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29)
205#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
206#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31)
207#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
208#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
209#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
210#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
211#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
212#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
213#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
214#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
215#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
216#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9)
217#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
218#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
219#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10)
220#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
221#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
222#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
223#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
224#define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
225#define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
226#define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
227#define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
228#define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
229#define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
230#define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
231#define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
232#define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
233#define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
234#define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
235#define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
236#define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
237#define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
238#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
239#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
240#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
241#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
242#endif
243
244#ifdef CONFIG_ARCH_MX2
245#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
246#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
247#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
248#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
249#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
253#define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
254#define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
255#define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
256#define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
257#define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
258#define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
259#define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
260#define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
261#define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
262#define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
263#define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
264#define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
265#define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
266#define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
267#define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
268#define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
269#define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
270#define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
271#define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
272#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
273#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
278#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
279#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
280#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
281#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
282#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
283#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
284#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
285#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
286#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11)
287#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
288#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
289#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
290#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13)
291#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
292#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
293#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
294#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
295#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
296#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
297#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
298#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19)
299#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
300#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
301#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
302#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
303#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
304#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
305#define PB24_PF_USB_OC_B (GPIO_PORTB | GPIO_PF | 24)
306#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
307#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
308#define PB27_PF_USBH1_OE_B (GPIO_PORTB | GPIO_PF | 27)
309#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
310#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
311#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
312#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
313#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
314#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
315#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
316#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
317#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
318#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
319#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
320#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
321#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
322#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
323#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
324#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
325#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
326#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
327#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
328#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
329#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19)
330#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20)
331#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21)
332#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22)
333#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23)
334#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24)
335#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25)
336#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26)
337#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27)
338#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28)
339#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29)
340#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30)
341#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31)
342#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
343#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
344#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
345#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
346#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
347#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
348#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
349#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
350#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
351#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
352#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
353#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
354#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
355#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
356#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
357#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
358#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
359#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
360#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
361#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
362#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
363#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
364#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
365#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
366#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
367#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
368#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
369#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
370#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
371#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
372#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
373#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
374#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
375#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
376#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
377#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
378#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
379#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
380#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
381#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
382#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
383#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
384#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
385#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
386#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
387#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
388#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
389#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
390#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
391#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
392#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
393#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18)
394#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
395#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19)
396#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20)
397#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21)
398#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
399#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22)
400#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
401#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23)
402#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
403#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
404#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
405#endif
406
407/* decode irq number to use with IMR(x), ISR(x) and friends */
408#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
409
410#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
411#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
412#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
413#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
414#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
415
416#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
new file mode 100644
index 000000000000..bf23305c19cc
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h
@@ -0,0 +1,166 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3*
4* This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*
13* You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA.
17*/
18
19#ifndef _MXC_IOMUX_MX1_H
20#define _MXC_IOMUX_MX1_H
21
22#ifndef GPIO_PORTA
23#error Please include mach/iomux.h
24#endif
25
26/* FIXME: This list is not completed. The correct directions are
27* missing on some (many) pins
28*/
29
30
31/* Primary GPIO pin functions */
32
33#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
34#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
35#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1)
36#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
37#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2)
38#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
39#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
40#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
41#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
42#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
43#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
44#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
45#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
46#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
47#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
48#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
49#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
50#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
51#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
52#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
53#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
54#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
55#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
56#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
57#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
58#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
59#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
60#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
61#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
62#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
63#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
64#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
65#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
66#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
67#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
68#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
69#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
70#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
71#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
72#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
73#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
74#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
75#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
76#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
77#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
78#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
79#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
80#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
81#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
82#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
83#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
84#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
85#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
86#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
87#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
88#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
89#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
90#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16)
91#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17)
92#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
93#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
94#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
95#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
96#define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22)
97#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
98#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
99#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
100#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
101#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
102#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28)
103#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29)
104#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30)
105#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31)
106#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
107#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
108#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
109#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6)
110#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
111#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
112#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
113#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10)
114#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
115#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12)
116#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
117#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
118#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
119#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
120#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
121#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24)
122#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25)
123#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26)
124#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27)
125#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28)
126#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29)
127#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
128#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31)
129#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6)
130#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
131#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7)
132#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
133#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
134#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8)
135#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
136#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
137#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9)
138#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9)
139#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10)
140#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10)
141#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10)
142#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11)
143#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12)
144#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13)
145#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14)
146#define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15)
147#define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16)
148#define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
149#define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
150#define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19)
151#define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20)
152#define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21)
153#define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22)
154#define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23)
155#define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24)
156#define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
157#define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
158#define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
159#define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
160#define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
161#define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30)
162#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
163#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
164
165
166#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
new file mode 100644
index 000000000000..63aaa972e275
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h
@@ -0,0 +1,126 @@
1/*
2* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
3*
4* This program is free software; you can redistribute it and/or
5* modify it under the terms of the GNU General Public License
6* as published by the Free Software Foundation; either version 2
7* of the License, or (at your option) any later version.
8* This program is distributed in the hope that it will be useful,
9* but WITHOUT ANY WARRANTY; without even the implied warranty of
10* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11* GNU General Public License for more details.
12*
13* You should have received a copy of the GNU General Public License
14* along with this program; if not, write to the Free Software
15* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16* MA 02110-1301, USA.
17*/
18
19#ifndef _MXC_IOMUX_MX21_H
20#define _MXC_IOMUX_MX21_H
21
22#ifndef GPIO_PORTA
23#error Please include mach/iomux.h
24#endif
25
26
27/* Primary GPIO pin functions */
28
29#define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22)
30#define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25)
31#define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5)
32#define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6)
33#define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7)
34#define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8)
35#define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9)
36#define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10)
37#define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11)
38#define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12)
39#define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13)
40#define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16)
41#define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17)
42#define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18)
43#define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19)
44#define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0)
45#define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1)
46#define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2)
47#define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1)
48#define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3)
49#define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7)
50#define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8)
51#define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9)
52#define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10)
53#define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11)
54#define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12)
55#define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13)
56#define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14)
57#define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16)
58
59/* Alternate GPIO pin functions */
60
61#define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5)
62#define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6)
63#define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7)
64#define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8)
65#define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9)
66#define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10)
67#define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11)
68#define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12)
69#define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13)
70#define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14)
71#define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15)
72#define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16)
73#define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17)
74#define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18)
75#define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19)
76#define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20)
77#define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21)
78#define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22)
79#define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23)
80#define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29)
81#define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30)
82
83/* AIN GPIO pin functions */
84
85#define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
86#define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21)
87#define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22)
88#define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23)
89#define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24)
90#define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8)
91#define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0)
92#define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1)
93#define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2)
94#define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3)
95#define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4)
96#define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5)
97
98/* BIN GPIO pin functions */
99
100#define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
101#define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27)
102
103/* CIN GPIO pin functions */
104
105#define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26)
106
107/* AOUT GPIO pin functions */
108
109#define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29)
110#define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19)
111#define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20)
112#define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25)
113#define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26)
114#define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9)
115#define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6)
116#define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7)
117#define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8)
118#define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9)
119#define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10)
120#define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11)
121#define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12)
122#define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13)
123#define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14)
124
125
126#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
new file mode 100644
index 000000000000..5ac158b70f61
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h
@@ -0,0 +1,207 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_MX27_H
21#define _MXC_IOMUX_MX27_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27
28/* Primary GPIO pin functions */
29
30#define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0)
31#define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1)
32#define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2)
33#define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3)
34#define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4)
35#define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22)
36#define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25)
37#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5)
38#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6)
39#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7)
40#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8)
41#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9)
42#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10)
43#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11)
44#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12)
45#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13)
46#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16)
47#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17)
48#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18)
49#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19)
50#define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25)
51#define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27)
52#define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0)
53#define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1)
54#define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2)
55#define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3)
56#define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4)
57#define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5)
58#define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6)
59#define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7)
60#define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8)
61#define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9)
62#define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10)
63#define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11)
64#define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12)
65#define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13)
66#define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14)
67#define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15)
68#define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16)
69#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0)
70#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1)
71#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2)
72#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24)
73#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25)
74#define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1)
75#define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3)
76#define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7)
77#define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8)
78#define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9)
79#define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10)
80#define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11)
81#define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12)
82#define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13)
83#define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14)
84#define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16)
85#define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17)
86#define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18)
87#define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19)
88#define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20)
89#define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23)
90
91/* Alternate GPIO pin functions */
92
93#define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4)
94#define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5)
95#define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6)
96#define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7)
97#define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8)
98#define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9)
99#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10)
100#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11)
101#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12)
102#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13)
103#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18)
104#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19)
105#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20)
106#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21)
107#define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8)
108#define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24)
109#define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26)
110#define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1)
111#define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6)
112#define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7)
113#define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9)
114#define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2)
115#define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3)
116#define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4)
117#define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5)
118#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8)
119#define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10)
120#define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11)
121#define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12)
122#define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13)
123#define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14)
124#define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15)
125#define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16)
126#define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1)
127#define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3)
128#define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5)
129#define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7)
130#define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8)
131#define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9)
132#define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10)
133#define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11)
134#define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12)
135#define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13)
136#define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14)
137#define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15)
138#define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16)
139#define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17)
140#define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18)
141#define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19)
142#define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20)
143#define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22)
144#define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23)
145
146/* AIN GPIO pin functions */
147
148#define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14)
149#define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15)
150#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0)
151#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1)
152#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2)
153#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3)
154#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9)
155#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16)
156#define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27)
157#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23)
158
159/* BIN GPIO pin functions */
160
161#define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14)
162
163/* CIN GPIO pin functions */
164
165#define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2)
166#define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3)
167#define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4)
168#define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5)
169#define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6)
170#define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7)
171#define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8)
172#define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9)
173#define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10)
174#define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11)
175#define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12)
176#define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13)
177#define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14)
178#define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15)
179#define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16)
180#define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23)
181#define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27)
182/* LCDC_TESTx on PBxx omitted, because it's not clear what they do */
183
184/* AOUT GPIO pin functions */
185
186#define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14)
187#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4)
188#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5)
189#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6)
190#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7)
191#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10)
192#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11)
193#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12)
194#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13)
195#define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14)
196#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15)
197
198#define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17)
199#define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18)
200#define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19)
201#define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28)
202#define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29)
203#define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30)
204#define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31)
205
206
207#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
new file mode 100644
index 000000000000..fb5ae638e79f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h
@@ -0,0 +1,237 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_MX2x_H
21#define _MXC_IOMUX_MX2x_H
22
23#ifndef GPIO_PORTA
24#error Please include mach/iomux.h
25#endif
26
27
28/* Primary GPIO pin functions */
29
30#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5)
31#define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6)
32#define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7)
33#define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8)
34#define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9)
35#define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10)
36#define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11)
37#define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12)
38#define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13)
39#define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14)
40#define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15)
41#define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16)
42#define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17)
43#define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18)
44#define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19)
45#define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20)
46#define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21)
47#define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22)
48#define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23)
49#define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24)
50#define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25)
51#define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26)
52#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27)
53#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28)
54#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29)
55#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30)
56#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31)
57#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
58#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
59#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
60#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
61#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
62#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
63#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10)
64#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11)
65#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12)
66#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13)
67#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14)
68#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15)
69#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16)
70#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17)
71#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18)
72#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19)
73#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20)
74#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21)
75#define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23)
76#define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24)
77#define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26)
78#define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27)
79#define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28)
80#define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29)
81#define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30)
82#define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31)
83#define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14)
84#define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15)
85#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20)
86#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21)
87#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22)
88#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23)
89#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24)
90#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25)
91#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26)
92#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27)
93#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28)
94#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29)
95#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30)
96#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31)
97#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17)
98#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18)
99#define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19)
100#define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20)
101#define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21)
102#define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22)
103#define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23)
104#define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24)
105#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25)
106#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26)
107#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27)
108#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28)
109#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29)
110#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30)
111#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31)
112#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3)
113#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4)
114#define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5)
115#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6)
116#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7)
117#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8)
118#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9)
119#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10)
120#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11)
121#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12)
122#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13)
123#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14)
124#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15)
125#define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16)
126#define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17)
127#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18)
128#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19)
129#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20)
130#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21)
131#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22)
132#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23)
133#define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0)
134#define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2)
135#define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4)
136#define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5)
137#define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6)
138#define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15)
139#define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21)
140#define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22)
141
142/* Alternate GPIO pin functions */
143
144#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26)
145#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28)
146#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29)
147#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31)
148#define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28)
149#define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29)
150#define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30)
151#define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31)
152#define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19)
153#define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20)
154#define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21)
155#define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22)
156#define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23)
157#define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24)
158#define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26)
159#define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0)
160#define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1)
161#define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2)
162#define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3)
163#define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4)
164#define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6)
165#define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7)
166#define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16)
167#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18)
168#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21)
169#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22)
170#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23)
171
172/* AIN GPIO pin functions */
173
174#define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6)
175#define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7)
176#define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8)
177#define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0)
178#define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11)
179#define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13)
180#define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15)
181#define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17)
182#define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19)
183#define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21)
184#define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22)
185#define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24)
186#define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25)
187#define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26)
188#define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27)
189#define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6)
190#define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7)
191#define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8)
192#define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9)
193#define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25)
194#define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26)
195#define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27)
196#define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28)
197#define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29)
198#define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30)
199#define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31)
200#define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5)
201#define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6)
202#define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7)
203#define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8)
204#define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9)
205#define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10)
206#define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11)
207#define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12)
208#define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13)
209#define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5)
210
211/* BIN GPIO pin functions */
212
213#define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5)
214
215/* CIN GPIO pin functions */
216
217#define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14)
218#define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15)
219#define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16)
220#define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17)
221#define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18)
222#define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19)
223#define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20)
224#define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21)
225#define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30)
226#define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5)
227
228/* AOUT GPIO pin functions */
229
230#define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29)
231#define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31)
232#define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8)
233#define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15)
234#define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21)
235
236
237#endif
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index c9198c0aea18..ab838cfe94f9 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -92,7 +92,7 @@ enum iomux_gp_func {
92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, 92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
93 MUX_TAMPER_DETECT_EN = 1 << 16, 93 MUX_TAMPER_DETECT_EN = 1 << 16,
94 MUX_PGP_USB_4WIRE = 1 << 17, 94 MUX_PGP_USB_4WIRE = 1 << 17,
95 MUX_PGB_USB_COMMON = 1 << 18, 95 MUX_PGP_USB_COMMON = 1 << 18,
96 MUX_SDHC_MEMSTICK1 = 1 << 19, 96 MUX_SDHC_MEMSTICK1 = 1 << 19,
97 MUX_SDHC_MEMSTICK2 = 1 << 20, 97 MUX_SDHC_MEMSTICK2 = 1 << 20,
98 MUX_PGP_SPLL_BYP = 1 << 21, 98 MUX_PGP_SPLL_BYP = 1 << 21,
@@ -109,21 +109,44 @@ enum iomux_gp_func {
109}; 109};
110 110
111/* 111/*
112 * This function enables/disables the general purpose function for a particular 112 * setups a single pin:
113 * signal. 113 * - reserves the pin so that it is not claimed by another driver
114 * - setups the iomux according to the configuration
115 * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
116 */
117int mxc_iomux_setup_pin(const unsigned int pin, const char *label);
118/*
119 * setups mutliple pins
120 * convenient way to call the above function with tables
114 */ 121 */
115void iomux_config_gpr(enum iomux_gp_func , bool); 122int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
123 const char *label);
116 124
117/* 125/*
118 * set the mode for a IOMUX pin. 126 * releases a single pin:
127 * - make it available for a future use by another driver
128 * - frees the GPIO if the pin was configured as GPIO
129 * - DOES NOT reconfigure the IOMUX in its reset state
119 */ 130 */
120int mxc_iomux_mode(unsigned int); 131void mxc_iomux_release_pin(const unsigned int pin);
132/*
133 * releases multiple pins
134 * convenvient way to call the above function with tables
135 */
136void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
121 137
122/* 138/*
123 * This function enables/disables the general purpose function for a particular 139 * This function enables/disables the general purpose function for a particular
124 * signal. 140 * signal.
125 */ 141 */
126void mxc_iomux_set_gpr(enum iomux_gp_func, bool); 142void mxc_iomux_set_gpr(enum iomux_gp_func, bool en);
143
144/*
145 * This function only configures the iomux hardware.
146 * It is called by the setup functions and should not be called directly anymore.
147 * It is here visible for backward compatibility
148 */
149int mxc_iomux_mode(unsigned int pin_mode);
127 150
128#define IOMUX_PADNUM_MASK 0x1ff 151#define IOMUX_PADNUM_MASK 0x1ff
129#define IOMUX_GPIONUM_SHIFT 9 152#define IOMUX_GPIONUM_SHIFT 9
@@ -144,6 +167,11 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
144 MXC_GPIO_IRQ_START) 167 MXC_GPIO_IRQ_START)
145 168
146/* 169/*
170 * The number of gpio devices among the pads
171 */
172#define GPIO_PORT_MAX 3
173
174/*
147 * This enumeration is constructed based on the Section 175 * This enumeration is constructed based on the Section
148 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated 176 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
149 * value is constructed based on the rules described above. 177 * value is constructed based on the rules described above.
@@ -480,6 +508,9 @@ enum iomux_pins {
480 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), 508 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
481}; 509};
482 510
511#define PIN_MAX 327
512#define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */
513
483/* 514/*
484 * Convenience values for use with mxc_iomux_mode() 515 * Convenience values for use with mxc_iomux_mode()
485 * 516 *
@@ -507,7 +538,9 @@ enum iomux_pins {
507#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) 538#define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC)
508#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) 539#define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC)
509#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) 540#define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC)
541#define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)
510#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) 542#define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC)
543#define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)
511#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) 544#define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC)
512#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) 545#define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC)
513#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) 546#define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC)
@@ -525,6 +558,33 @@ enum iomux_pins {
525#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) 558#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
526#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) 559#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
527#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) 560#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
561#define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC)
562#define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC)
563#define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC)
564#define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC)
565#define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC)
566#define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC)
567#define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC)
568#define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC)
569#define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC)
570#define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC)
571#define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC)
572#define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC)
573#define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC)
574#define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC)
575#define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC)
576#define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC)
577#define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC)
578#define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC)
579#define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC)
580#define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC)
581#define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC)
582#define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC)
583#define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC)
584#define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC)
585#define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC)
586#define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC)
587#define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO)
528 588
529/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 589/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
530 * cspi1_ss1*/ 590 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
new file mode 100644
index 000000000000..171f8adc1109
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -0,0 +1,127 @@
1/*
2* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3* Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de>
4*
5* This program is free software; you can redistribute it and/or
6* modify it under the terms of the GNU General Public License
7* as published by the Free Software Foundation; either version 2
8* of the License, or (at your option) any later version.
9* This program is distributed in the hope that it will be useful,
10* but WITHOUT ANY WARRANTY; without even the implied warranty of
11* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12* GNU General Public License for more details.
13*
14* You should have received a copy of the GNU General Public License
15* along with this program; if not, write to the Free Software
16* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17* MA 02110-1301, USA.
18*/
19
20#ifndef _MXC_IOMUX_H
21#define _MXC_IOMUX_H
22
23/*
24* GPIO Module and I/O Multiplexer
25* x = 0..3 for reg_A, reg_B, reg_C, reg_D
26*/
27#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
28#define MXC_DDIR(x) (0x00 + ((x) << 8))
29#define MXC_OCR1(x) (0x04 + ((x) << 8))
30#define MXC_OCR2(x) (0x08 + ((x) << 8))
31#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
32#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
33#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
34#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
35#define MXC_DR(x) (0x1c + ((x) << 8))
36#define MXC_GIUS(x) (0x20 + ((x) << 8))
37#define MXC_SSR(x) (0x24 + ((x) << 8))
38#define MXC_ICR1(x) (0x28 + ((x) << 8))
39#define MXC_ICR2(x) (0x2c + ((x) << 8))
40#define MXC_IMR(x) (0x30 + ((x) << 8))
41#define MXC_ISR(x) (0x34 + ((x) << 8))
42#define MXC_GPR(x) (0x38 + ((x) << 8))
43#define MXC_SWR(x) (0x3c + ((x) << 8))
44#define MXC_PUEN(x) (0x40 + ((x) << 8))
45
46#ifdef CONFIG_ARCH_MX1
47# define GPIO_PORT_MAX 3
48#endif
49#ifdef CONFIG_ARCH_MX2
50# define GPIO_PORT_MAX 5
51#endif
52
53#ifndef GPIO_PORT_MAX
54# error "GPIO config port count unknown!"
55#endif
56
57#define GPIO_PIN_MASK 0x1f
58
59#define GPIO_PORT_SHIFT 5
60#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
61
62#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
63#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
64#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
65#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
66#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
67#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
68
69#define GPIO_OUT (1 << 8)
70#define GPIO_IN (0 << 8)
71#define GPIO_PUEN (1 << 9)
72
73#define GPIO_PF (1 << 10)
74#define GPIO_AF (1 << 11)
75
76#define GPIO_OCR_SHIFT 12
77#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
78#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
79#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
80#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
81#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
82
83#define GPIO_AOUT_SHIFT 14
84#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
85#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
86#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
87#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
88#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
89
90#define GPIO_BOUT_SHIFT 16
91#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
92#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
93#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
94#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
95#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
96
97
98#ifdef CONFIG_ARCH_MX1
99#include <mach/iomux-mx1.h>
100#endif
101#ifdef CONFIG_ARCH_MX2
102#include <mach/iomux-mx2x.h>
103#ifdef CONFIG_MACH_MX21
104#include <mach/iomux-mx21.h>
105#endif
106#ifdef CONFIG_MACH_MX27
107#include <mach/iomux-mx27.h>
108#endif
109#endif
110
111
112/* decode irq number to use with IMR(x), ISR(x) and friends */
113#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
114
115#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
116#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
117#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
118#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
119#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
120
121
122extern void mxc_gpio_mode(int gpio_mode);
123extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
124 const char *label);
125extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
126
127#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 0b808399097f..e0783e619580 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -14,7 +14,12 @@
14#if defined CONFIG_ARCH_MX1 14#if defined CONFIG_ARCH_MX1
15#define PHYS_OFFSET UL(0x08000000) 15#define PHYS_OFFSET UL(0x08000000)
16#elif defined CONFIG_ARCH_MX2 16#elif defined CONFIG_ARCH_MX2
17#ifdef CONFIG_MACH_MX21
18#define PHYS_OFFSET UL(0xC0000000)
19#endif
20#ifdef CONFIG_MACH_MX27
17#define PHYS_OFFSET UL(0xA0000000) 21#define PHYS_OFFSET UL(0xA0000000)
22#endif
18#elif defined CONFIG_ARCH_MX3 23#elif defined CONFIG_ARCH_MX3
19#define PHYS_OFFSET UL(0x80000000) 24#define PHYS_OFFSET UL(0x80000000)
20#endif 25#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
new file mode 100644
index 000000000000..e8c4cf56c24e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -0,0 +1,78 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
5 *
6 * This contains i.MX21-specific hardware definitions. For those
7 * hardware pieces that are common between i.MX21 and i.MX27, have a
8 * look at mx2x.h.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25#ifndef __ASM_ARCH_MXC_MX21_H__
26#define __ASM_ARCH_MXC_MX21_H__
27
28#ifndef __ASM_ARCH_MXC_HARDWARE_H__
29#error "Do not include directly."
30#endif
31
32
33/* Memory regions and CS */
34#define SDRAM_BASE_ADDR 0xC0000000
35#define CSD1_BASE_ADDR 0xC4000000
36
37#define CS0_BASE_ADDR 0xC8000000
38#define CS1_BASE_ADDR 0xCC000000
39#define CS2_BASE_ADDR 0xD0000000
40#define CS3_BASE_ADDR 0xD1000000
41#define CS4_BASE_ADDR 0xD2000000
42#define CS5_BASE_ADDR 0xDD000000
43#define PCMCIA_MEM_BASE_ADDR 0xD4000000
44
45/* NAND, SDRAM, WEIM etc controllers */
46#define X_MEMC_BASE_ADDR 0xDF000000
47#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
48#define X_MEMC_SIZE SZ_256K
49
50#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
51#define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
52#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
53#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
54
55#define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */
56
57/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
58#define ARCH_NR_GPIOS (6*32 + 16)
59
60/* fixed interrupt numbers */
61#define MXC_INT_USBCTRL 58
62#define MXC_INT_USBCTRL 58
63#define MXC_INT_USBMNP 57
64#define MXC_INT_USBFUNC 56
65#define MXC_INT_USBHOST 55
66#define MXC_INT_USBDMA 54
67#define MXC_INT_USBWKUP 53
68#define MXC_INT_EMMADEC 50
69#define MXC_INT_EMMAENC 49
70#define MXC_INT_BMI 30
71#define MXC_INT_FIRI 9
72
73/* fixed DMA request numbers */
74#define DMA_REQ_BMI_RX 29
75#define DMA_REQ_BMI_TX 28
76#define DMA_REQ_FIRI_RX 4
77
78#endif /* __ASM_ARCH_MXC_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 0313be720552..6e93f2c0b7bb 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -2,6 +2,10 @@
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 * 4 *
5 * This contains i.MX27-specific hardware definitions. For those
6 * hardware pieces that are common between i.MX21 and i.MX27, have a
7 * look at mx2x.h.
8 *
5 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 10 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2 11 * as published by the Free Software Foundation; either version 2
@@ -27,35 +31,6 @@
27/* IRAM */ 31/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ 32#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29 33
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) 34#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) 35#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) 36#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
@@ -64,55 +39,24 @@
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) 39#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) 40#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) 41#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) 42#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR 43#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) 44#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
76#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
77#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
78#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
79#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) 45#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
80
81#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) 46#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
82#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) 47#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
83#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) 48#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
84#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) 49#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
85#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) 50#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
86 51
87#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) 52/* ROM patch */
88#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
89
90/* ROMP and AVIC */
91#define ROMP_BASE_ADDR 0x10041000 53#define ROMP_BASE_ADDR 0x10041000
92 54
93#define AVIC_BASE_ADDR 0x10040000
94
95#define SAHB1_BASE_ADDR 0x80000000
96#define SAHB1_BASE_ADDR_VIRT 0xF4100000
97#define SAHB1_SIZE SZ_1M
98
99#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
100#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) 55#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
101 56
102/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
103#define X_MEMC_BASE_ADDR 0xD8000000
104#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
105#define X_MEMC_SIZE SZ_1M
106
107#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
108#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
109#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
110#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
111#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
112
113/* Memory regions and CS */ 57/* Memory regions and CS */
114#define SDRAM_BASE_ADDR 0xA0000000 58#define SDRAM_BASE_ADDR 0xA0000000
115#define CSD1_BASE_ADDR 0xB0000000 59#define CSD1_BASE_ADDR 0xB0000000
116 60
117#define CS0_BASE_ADDR 0xC0000000 61#define CS0_BASE_ADDR 0xC0000000
118#define CS1_BASE_ADDR 0xC8000000 62#define CS1_BASE_ADDR 0xC8000000
@@ -122,44 +66,20 @@
122#define CS5_BASE_ADDR 0xD6000000 66#define CS5_BASE_ADDR 0xD6000000
123#define PCMCIA_MEM_BASE_ADDR 0xDC000000 67#define PCMCIA_MEM_BASE_ADDR 0xDC000000
124 68
125/* 69/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
126 * This macro defines the physical to virtual address mapping for all the 70#define X_MEMC_BASE_ADDR 0xD8000000
127 * peripheral modules. It is used by passing in the physical address as x 71#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
128 * and returning the virtual address. If the physical address is not mapped, 72#define X_MEMC_SIZE SZ_1M
129 * it returns 0xDEADBEEF
130 */
131#define IO_ADDRESS(x) \
132 (void __iomem *) \
133 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
134 AIPI_IO_ADDRESS(x) : \
135 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
136 SAHB1_IO_ADDRESS(x) : \
137 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
138 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
139
140/* define the address mapping macros: in physical address order */
141#define AIPI_IO_ADDRESS(x) \
142 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
143
144#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
145
146#define SAHB1_IO_ADDRESS(x) \
147 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
148
149#define CS4_IO_ADDRESS(x) \
150 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
151
152#define X_MEMC_IO_ADDRESS(x) \
153 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
154 73
155#define PCMCIA_IO_ADDRESS(x) \ 74#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
156 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) 75#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
76#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
77#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
78#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
157 79
158/* fixed interrput numbers */ 80/* fixed interrupt numbers */
159#define MXC_INT_CCM 63 81#define MXC_INT_CCM 63
160#define MXC_INT_IIM 62 82#define MXC_INT_IIM 62
161#define MXC_INT_LCDC 61
162#define MXC_INT_SLCDC 60
163#define MXC_INT_SAHARA 59 83#define MXC_INT_SAHARA 59
164#define MXC_INT_SCC_SCM 58 84#define MXC_INT_SCC_SCM 58
165#define MXC_INT_SCC_SMN 57 85#define MXC_INT_SCC_SMN 57
@@ -167,54 +87,12 @@
167#define MXC_INT_USB2 55 87#define MXC_INT_USB2 55
168#define MXC_INT_USB1 54 88#define MXC_INT_USB1 54
169#define MXC_INT_VPU 53 89#define MXC_INT_VPU 53
170#define MXC_INT_EMMAPP 52
171#define MXC_INT_EMMAPRP 51
172#define MXC_INT_FEC 50 90#define MXC_INT_FEC 50
173#define MXC_INT_UART5 49 91#define MXC_INT_UART5 49
174#define MXC_INT_UART6 48 92#define MXC_INT_UART6 48
175#define MXC_INT_DMACH15 47
176#define MXC_INT_DMACH14 46
177#define MXC_INT_DMACH13 45
178#define MXC_INT_DMACH12 44
179#define MXC_INT_DMACH11 43
180#define MXC_INT_DMACH10 42
181#define MXC_INT_DMACH9 41
182#define MXC_INT_DMACH8 40
183#define MXC_INT_DMACH7 39
184#define MXC_INT_DMACH6 38
185#define MXC_INT_DMACH5 37
186#define MXC_INT_DMACH4 36
187#define MXC_INT_DMACH3 35
188#define MXC_INT_DMACH2 34
189#define MXC_INT_DMACH1 33
190#define MXC_INT_DMACH0 32
191#define MXC_INT_CSI 31
192#define MXC_INT_ATA 30 93#define MXC_INT_ATA 30
193#define MXC_INT_NANDFC 29
194#define MXC_INT_PCMCIA 28
195#define MXC_INT_WDOG 27
196#define MXC_INT_GPT1 26
197#define MXC_INT_GPT2 25
198#define MXC_INT_GPT3 24
199#define MXC_INT_GPT INT_GPT1
200#define MXC_INT_PWM 23
201#define MXC_INT_RTC 22
202#define MXC_INT_KPP 21
203#define MXC_INT_UART1 20
204#define MXC_INT_UART2 19
205#define MXC_INT_UART3 18
206#define MXC_INT_UART4 17
207#define MXC_INT_CSPI1 16
208#define MXC_INT_CSPI2 15
209#define MXC_INT_SSI1 14
210#define MXC_INT_SSI2 13
211#define MXC_INT_I2C 12
212#define MXC_INT_SDHC1 11
213#define MXC_INT_SDHC2 10
214#define MXC_INT_SDHC3 9 94#define MXC_INT_SDHC3 9
215#define MXC_INT_GPIO 8
216#define MXC_INT_SDHC 7 95#define MXC_INT_SDHC 7
217#define MXC_INT_CSPI3 6
218#define MXC_INT_RTIC 5 96#define MXC_INT_RTIC 5
219#define MXC_INT_GPT4 4 97#define MXC_INT_GPT4 4
220#define MXC_INT_GPT5 3 98#define MXC_INT_GPT5 3
@@ -228,36 +106,9 @@
228#define DMA_REQ_UART6_TX 34 106#define DMA_REQ_UART6_TX 34
229#define DMA_REQ_UART5_RX 33 107#define DMA_REQ_UART5_RX 33
230#define DMA_REQ_UART5_TX 32 108#define DMA_REQ_UART5_TX 32
231#define DMA_REQ_CSI_RX 31
232#define DMA_REQ_CSI_STAT 30
233#define DMA_REQ_ATA_RCV 29 109#define DMA_REQ_ATA_RCV 29
234#define DMA_REQ_ATA_TX 28 110#define DMA_REQ_ATA_TX 28
235#define DMA_REQ_UART1_TX 27
236#define DMA_REQ_UART1_RX 26
237#define DMA_REQ_UART2_TX 25
238#define DMA_REQ_UART2_RX 24
239#define DMA_REQ_UART3_TX 23
240#define DMA_REQ_UART3_RX 22
241#define DMA_REQ_UART4_TX 21
242#define DMA_REQ_UART4_RX 20
243#define DMA_REQ_CSPI1_TX 19
244#define DMA_REQ_CSPI1_RX 18
245#define DMA_REQ_CSPI2_TX 17
246#define DMA_REQ_CSPI2_RX 16
247#define DMA_REQ_SSI1_TX1 15
248#define DMA_REQ_SSI1_RX1 14
249#define DMA_REQ_SSI1_TX0 13
250#define DMA_REQ_SSI1_RX0 12
251#define DMA_REQ_SSI2_TX1 11
252#define DMA_REQ_SSI2_RX1 10
253#define DMA_REQ_SSI2_TX0 9
254#define DMA_REQ_SSI2_RX0 8
255#define DMA_REQ_SDHC1 7
256#define DMA_REQ_SDHC2 6
257#define DMA_REQ_MSHC 4 111#define DMA_REQ_MSHC 4
258#define DMA_REQ_EXT 3
259#define DMA_REQ_CSPI3_TX 2
260#define DMA_REQ_CSPI3_RX 1
261 112
262/* silicon revisions specific to i.MX27 */ 113/* silicon revisions specific to i.MX27 */
263#define CHIP_REV_1_0 0x00 114#define CHIP_REV_1_0 0x00
@@ -267,25 +118,8 @@
267extern int mx27_revision(void); 118extern int mx27_revision(void);
268#endif 119#endif
269 120
270/* gpio and gpio based interrupt handling */
271#define GPIO_DR 0x1C
272#define GPIO_GDIR 0x00
273#define GPIO_PSR 0x24
274#define GPIO_ICR1 0x28
275#define GPIO_ICR2 0x2C
276#define GPIO_IMR 0x30
277#define GPIO_ISR 0x34
278#define GPIO_INT_LOW_LEV 0x3
279#define GPIO_INT_HIGH_LEV 0x2
280#define GPIO_INT_RISE_EDGE 0x0
281#define GPIO_INT_FALL_EDGE 0x1
282#define GPIO_INT_NONE 0x4
283
284/* Mandatory defines used globally */ 121/* Mandatory defines used globally */
285 122
286/* this is an i.MX27 CPU */
287#define cpu_is_mx27() (1)
288
289/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ 123/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
290#define ARCH_NR_GPIOS (192 + 16) 124#define ARCH_NR_GPIOS (192 + 16)
291 125
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
new file mode 100644
index 000000000000..fc40d3ab8c5b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -0,0 +1,200 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This contains hardware definitions that are common between i.MX21 and
6 * i.MX27.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#ifndef __ASM_ARCH_MXC_MX2x_H__
24#define __ASM_ARCH_MXC_MX2x_H__
25
26#ifndef __ASM_ARCH_MXC_HARDWARE_H__
27#error "Do not include directly."
28#endif
29
30/* The following addresses are common between i.MX21 and i.MX27 */
31
32/* Register offests */
33#define AIPI_BASE_ADDR 0x10000000
34#define AIPI_BASE_ADDR_VIRT 0xF4000000
35#define AIPI_SIZE SZ_1M
36
37#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
38#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
39#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
40#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
41#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
42#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
43#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
44#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
45#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
46#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
47#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
48#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
49#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
50#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
51#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
52#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
53#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
54#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
55#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
56#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
57#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
58#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
59#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
60#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
61#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
62#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
63#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
64#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
65#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
66#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
67#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
68#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
69
70#define AVIC_BASE_ADDR 0x10040000
71
72#define SAHB1_BASE_ADDR 0x80000000
73#define SAHB1_BASE_ADDR_VIRT 0xF4100000
74#define SAHB1_SIZE SZ_1M
75
76#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
77
78/*
79 * This macro defines the physical to virtual address mapping for all the
80 * peripheral modules. It is used by passing in the physical address as x
81 * and returning the virtual address. If the physical address is not mapped,
82 * it returns 0xDEADBEEF
83 */
84#define IO_ADDRESS(x) \
85 (void __force __iomem *) \
86 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
87 AIPI_IO_ADDRESS(x) : \
88 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
89 SAHB1_IO_ADDRESS(x) : \
90 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
91 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
92
93/* define the address mapping macros: in physical address order */
94#define AIPI_IO_ADDRESS(x) \
95 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
96
97#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
98
99#define SAHB1_IO_ADDRESS(x) \
100 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
101
102#define CS4_IO_ADDRESS(x) \
103 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
104
105#define X_MEMC_IO_ADDRESS(x) \
106 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
107
108#define PCMCIA_IO_ADDRESS(x) \
109 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
110
111/* fixed interrupt numbers */
112#define MXC_INT_LCDC 61
113#define MXC_INT_SLCDC 60
114#define MXC_INT_EMMAPP 52
115#define MXC_INT_EMMAPRP 51
116#define MXC_INT_DMACH15 47
117#define MXC_INT_DMACH14 46
118#define MXC_INT_DMACH13 45
119#define MXC_INT_DMACH12 44
120#define MXC_INT_DMACH11 43
121#define MXC_INT_DMACH10 42
122#define MXC_INT_DMACH9 41
123#define MXC_INT_DMACH8 40
124#define MXC_INT_DMACH7 39
125#define MXC_INT_DMACH6 38
126#define MXC_INT_DMACH5 37
127#define MXC_INT_DMACH4 36
128#define MXC_INT_DMACH3 35
129#define MXC_INT_DMACH2 34
130#define MXC_INT_DMACH1 33
131#define MXC_INT_DMACH0 32
132#define MXC_INT_CSI 31
133#define MXC_INT_NANDFC 29
134#define MXC_INT_PCMCIA 28
135#define MXC_INT_WDOG 27
136#define MXC_INT_GPT1 26
137#define MXC_INT_GPT2 25
138#define MXC_INT_GPT3 24
139#define MXC_INT_GPT INT_GPT1
140#define MXC_INT_PWM 23
141#define MXC_INT_RTC 22
142#define MXC_INT_KPP 21
143#define MXC_INT_UART1 20
144#define MXC_INT_UART2 19
145#define MXC_INT_UART3 18
146#define MXC_INT_UART4 17
147#define MXC_INT_CSPI1 16
148#define MXC_INT_CSPI2 15
149#define MXC_INT_SSI1 14
150#define MXC_INT_SSI2 13
151#define MXC_INT_I2C 12
152#define MXC_INT_SDHC1 11
153#define MXC_INT_SDHC2 10
154#define MXC_INT_GPIO 8
155#define MXC_INT_CSPI3 6
156
157/* gpio and gpio based interrupt handling */
158#define GPIO_DR 0x1C
159#define GPIO_GDIR 0x00
160#define GPIO_PSR 0x24
161#define GPIO_ICR1 0x28
162#define GPIO_ICR2 0x2C
163#define GPIO_IMR 0x30
164#define GPIO_ISR 0x34
165#define GPIO_INT_LOW_LEV 0x3
166#define GPIO_INT_HIGH_LEV 0x2
167#define GPIO_INT_RISE_EDGE 0x0
168#define GPIO_INT_FALL_EDGE 0x1
169#define GPIO_INT_NONE 0x4
170
171/* fixed DMA request numbers */
172#define DMA_REQ_CSI_RX 31
173#define DMA_REQ_CSI_STAT 30
174#define DMA_REQ_UART1_TX 27
175#define DMA_REQ_UART1_RX 26
176#define DMA_REQ_UART2_TX 25
177#define DMA_REQ_UART2_RX 24
178#define DMA_REQ_UART3_TX 23
179#define DMA_REQ_UART3_RX 22
180#define DMA_REQ_UART4_TX 21
181#define DMA_REQ_UART4_RX 20
182#define DMA_REQ_CSPI1_TX 19
183#define DMA_REQ_CSPI1_RX 18
184#define DMA_REQ_CSPI2_TX 17
185#define DMA_REQ_CSPI2_RX 16
186#define DMA_REQ_SSI1_TX1 15
187#define DMA_REQ_SSI1_RX1 14
188#define DMA_REQ_SSI1_TX0 13
189#define DMA_REQ_SSI1_RX0 12
190#define DMA_REQ_SSI2_TX1 11
191#define DMA_REQ_SSI2_RX1 10
192#define DMA_REQ_SSI2_TX0 9
193#define DMA_REQ_SSI2_RX0 8
194#define DMA_REQ_SDHC1 7
195#define DMA_REQ_SDHC2 6
196#define DMA_REQ_EXT 3
197#define DMA_REQ_CSPI3_TX 2
198#define DMA_REQ_CSPI3_RX 1
199
200#endif /* __ASM_ARCH_MXC_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index de026654b00e..0b06941b6139 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -1,360 +1,45 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * F8000000 1FFC0000 16K IRAM
24 * F9000000 30000000 256M L2CC
25 * FC000000 43F00000 1M AIPS 1
26 * FC100000 50000000 1M SPBA
27 * FC200000 53F00000 1M AIPS 2
28 * FC500000 60000000 128M ROMPATCH
29 * FC400000 68000000 128M AVIC
30 * 70000000 256M IPU (MAX M2)
31 * 80000000 256M CSD0 SDRAM/DDR
32 * 90000000 256M CSD1 SDRAM/DDR
33 * A0000000 128M CS0 Flash
34 * A8000000 128M CS1 Flash
35 * B0000000 32M CS2
36 * B2000000 32M CS3
37 * F4000000 B4000000 32M CS4
38 * B6000000 32M CS5
39 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
40 * C0000000 64M PCMCIA/CF
41 */
42
43#define CS0_BASE_ADDR 0xA0000000
44#define CS1_BASE_ADDR 0xA8000000
45#define CS2_BASE_ADDR 0xB0000000
46#define CS3_BASE_ADDR 0xB2000000
47
48#define CS4_BASE_ADDR 0xB4000000
49#define CS4_BASE_ADDR_VIRT 0xF4000000
50#define CS4_SIZE SZ_32M
51
52#define CS5_BASE_ADDR 0xB6000000
53#define PCMCIA_MEM_BASE_ADDR 0xBC000000
54
55/*
56 * IRAM 2 * IRAM
57 */ 3 */
58#define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ 4#define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */
59#define IRAM_BASE_ADDR_VIRT 0xF8000000 5#define MX31_IRAM_SIZE SZ_16K
60#define IRAM_SIZE SZ_16K
61
62/*
63 * L2CC
64 */
65#define L2CC_BASE_ADDR 0x30000000
66#define L2CC_BASE_ADDR_VIRT 0xF9000000
67#define L2CC_SIZE SZ_1M
68
69/*
70 * AIPS 1
71 */
72#define AIPS1_BASE_ADDR 0x43F00000
73#define AIPS1_BASE_ADDR_VIRT 0xFC000000
74#define AIPS1_SIZE SZ_1M
75 6
76#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
77#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
78#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
79#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
80#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
81#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
82#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
83#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
84#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) 7#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
85#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) 8#define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
86#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
87#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
88#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
89#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
90#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
91#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
92#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
93#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
94#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) 9#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
95#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) 10#define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
96#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
97#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
98
99/*
100 * SPBA global module enabled #0
101 */
102#define SPBA0_BASE_ADDR 0x50000000
103#define SPBA0_BASE_ADDR_VIRT 0xFC100000
104#define SPBA0_SIZE SZ_1M
105 11
106#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) 12#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
107#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) 13#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
108#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
109#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
110#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
111#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) 14#define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000)
112#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) 15#define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000)
113#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
114#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
115#define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
116#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
117 16
118/*
119 * AIPS 2
120 */
121#define AIPS2_BASE_ADDR 0x53F00000
122#define AIPS2_BASE_ADDR_VIRT 0xFC200000
123#define AIPS2_SIZE SZ_1M
124#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
125#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) 17#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
126#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) 18#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000)
127#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
128#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
129#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
130#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
131#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
132#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) 19#define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000)
133#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) 20#define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000)
134#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
135#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
136#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
137#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) 21#define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
138#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
139#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
140#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
141#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
142#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
143#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
144#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
145
146/*
147 * ROMP and AVIC
148 */
149#define ROMP_BASE_ADDR 0x60000000
150#define ROMP_BASE_ADDR_VIRT 0xFC500000
151#define ROMP_SIZE SZ_1M
152
153#define AVIC_BASE_ADDR 0x68000000
154#define AVIC_BASE_ADDR_VIRT 0xFC400000
155#define AVIC_SIZE SZ_1M
156
157/*
158 * NAND, SDRAM, WEIM, M3IF, EMI controllers
159 */
160#define X_MEMC_BASE_ADDR 0xB8000000
161#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
162#define X_MEMC_SIZE SZ_64K
163 22
164#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) 23#define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000)
165#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
166#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
167#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
168#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
169#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
170 24
171/*
172 * Memory regions and CS
173 */
174#define IPU_MEM_BASE_ADDR 0x70000000
175#define CSD0_BASE_ADDR 0x80000000
176#define CSD1_BASE_ADDR 0x90000000
177#define CS0_BASE_ADDR 0xA0000000
178#define CS1_BASE_ADDR 0xA8000000
179#define CS2_BASE_ADDR 0xB0000000
180#define CS3_BASE_ADDR 0xB2000000
181
182#define CS4_BASE_ADDR 0xB4000000
183#define CS4_BASE_ADDR_VIRT 0xF4000000
184#define CS4_SIZE SZ_32M
185
186#define CS5_BASE_ADDR 0xB6000000
187#define PCMCIA_MEM_BASE_ADDR 0xBC000000
188
189/*!
190 * This macro defines the physical to virtual address mapping for all the
191 * peripheral modules. It is used by passing in the physical address as x
192 * and returning the virtual address. If the physical address is not mapped,
193 * it returns 0xDEADBEEF
194 */
195#define IO_ADDRESS(x) \
196 (void __iomem *) \
197 (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
198 ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
199 ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
200 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
201 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
202 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
203 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
204 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
205 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
206 0xDEADBEEF)
207
208/*
209 * define the address mapping macros: in physical address order
210 */
211
212#define IRAM_IO_ADDRESS(x) \
213 (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
214
215#define L2CC_IO_ADDRESS(x) \
216 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
217
218#define AIPS1_IO_ADDRESS(x) \
219 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
220
221#define SPBA0_IO_ADDRESS(x) \
222 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
223
224#define AIPS2_IO_ADDRESS(x) \
225 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
226
227#define ROMP_IO_ADDRESS(x) \
228 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
229
230#define AVIC_IO_ADDRESS(x) \
231 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
232
233#define CS4_IO_ADDRESS(x) \
234 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
235
236#define X_MEMC_IO_ADDRESS(x) \
237 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
238
239#define PCMCIA_IO_ADDRESS(x) \
240 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
241
242/*
243 * Interrupt numbers
244 */
245#define MXC_INT_PEN_ADS7843 0
246#define MXC_INT_RESV1 1
247#define MXC_INT_CS8900A 2
248#define MXC_INT_I2C3 3
249#define MXC_INT_I2C2 4
250#define MXC_INT_MPEG4_ENCODER 5 25#define MXC_INT_MPEG4_ENCODER 5
251#define MXC_INT_RTIC 6
252#define MXC_INT_FIRI 7 26#define MXC_INT_FIRI 7
253#define MXC_INT_MMC_SDHC2 8 27#define MX31_INT_MMC_SDHC2 8
254#define MXC_INT_MMC_SDHC1 9 28#define MXC_INT_MMC_SDHC1 9
255#define MXC_INT_I2C 10 29#define MX31_INT_SSI2 11
256#define MXC_INT_SSI2 11 30#define MX31_INT_SSI1 12
257#define MXC_INT_SSI1 12
258#define MXC_INT_CSPI2 13
259#define MXC_INT_CSPI1 14
260#define MXC_INT_ATA 15
261#define MXC_INT_MBX 16 31#define MXC_INT_MBX 16
262#define MXC_INT_CSPI3 17 32#define MXC_INT_CSPI3 17
263#define MXC_INT_UART3 18
264#define MXC_INT_IIM 19
265#define MXC_INT_SIM2 20 33#define MXC_INT_SIM2 20
266#define MXC_INT_SIM1 21 34#define MXC_INT_SIM1 21
267#define MXC_INT_RNGA 22 35#define MXC_INT_CCM_DVFS 31
268#define MXC_INT_EVTMON 23
269#define MXC_INT_KPP 24
270#define MXC_INT_RTC 25
271#define MXC_INT_PWM 26
272#define MXC_INT_EPIT2 27
273#define MXC_INT_EPIT1 28
274#define MXC_INT_GPT 29
275#define MXC_INT_RESV30 30
276#define MXC_INT_RESV31 31
277#define MXC_INT_UART2 32
278#define MXC_INT_NANDFC 33
279#define MXC_INT_SDMA 34
280#define MXC_INT_USB1 35 36#define MXC_INT_USB1 35
281#define MXC_INT_USB2 36 37#define MXC_INT_USB2 36
282#define MXC_INT_USB3 37 38#define MXC_INT_USB3 37
283#define MXC_INT_USB4 38 39#define MXC_INT_USB4 38
284#define MXC_INT_MSHC1 39
285#define MXC_INT_MSHC2 40 40#define MXC_INT_MSHC2 40
286#define MXC_INT_IPU_ERR 41
287#define MXC_INT_IPU_SYN 42
288#define MXC_INT_RESV43 43
289#define MXC_INT_RESV44 44
290#define MXC_INT_UART1 45
291#define MXC_INT_UART4 46 41#define MXC_INT_UART4 46
292#define MXC_INT_UART5 47 42#define MXC_INT_UART5 47
293#define MXC_INT_ECT 48
294#define MXC_INT_SCC_SCM 49
295#define MXC_INT_SCC_SMN 50
296#define MXC_INT_GPIO2 51
297#define MXC_INT_GPIO1 52
298#define MXC_INT_CCM 53 43#define MXC_INT_CCM 53
299#define MXC_INT_PCMCIA 54 44#define MXC_INT_PCMCIA 54
300#define MXC_INT_WDOG 55
301#define MXC_INT_GPIO3 56
302#define MXC_INT_RESV57 57
303#define MXC_INT_EXT_POWER 58
304#define MXC_INT_EXT_TEMPER 59
305#define MXC_INT_EXT_SENSOR60 60
306#define MXC_INT_EXT_SENSOR61 61
307#define MXC_INT_EXT_WDOG 62
308#define MXC_INT_EXT_TV 63
309
310#define PROD_SIGNATURE 0x1 /* For MX31 */
311
312/* silicon revisions specific to i.MX31 */
313#define CHIP_REV_1_0 0x10
314#define CHIP_REV_1_1 0x11
315#define CHIP_REV_1_2 0x12
316#define CHIP_REV_1_3 0x13
317#define CHIP_REV_2_0 0x20
318#define CHIP_REV_2_1 0x21
319#define CHIP_REV_2_2 0x22
320#define CHIP_REV_2_3 0x23
321#define CHIP_REV_3_0 0x30
322#define CHIP_REV_3_1 0x31
323#define CHIP_REV_3_2 0x32
324
325#define SYSTEM_REV_MIN CHIP_REV_1_0
326#define SYSTEM_REV_NUM 3
327
328/* gpio and gpio based interrupt handling */
329#define GPIO_DR 0x00
330#define GPIO_GDIR 0x04
331#define GPIO_PSR 0x08
332#define GPIO_ICR1 0x0C
333#define GPIO_ICR2 0x10
334#define GPIO_IMR 0x14
335#define GPIO_ISR 0x18
336#define GPIO_INT_LOW_LEV 0x0
337#define GPIO_INT_HIGH_LEV 0x1
338#define GPIO_INT_RISE_EDGE 0x2
339#define GPIO_INT_FALL_EDGE 0x3
340#define GPIO_INT_NONE 0x4
341
342/* Mandatory defines used globally */
343
344/* this CPU supports up to 96 GPIOs */
345#define ARCH_NR_GPIOS 96
346
347#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
348
349/* this is a i.MX31 CPU */
350#define cpu_is_mx31() (1)
351
352extern unsigned int system_rev;
353
354static inline int mx31_revision(void)
355{
356 return system_rev;
357}
358#endif
359 45
360#endif /* __ASM_ARCH_MXC_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
new file mode 100644
index 000000000000..6465fefb42e3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -0,0 +1,29 @@
1/*
2 * IRAM
3 */
4#define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */
5#define MX35_IRAM_SIZE SZ_128K
6
7#define MXC_FEC_BASE_ADDR 0x50038000
8#define MX35_NFC_BASE_ADDR 0xBB000000
9
10/*
11 * Interrupt numbers
12 */
13#define MXC_INT_OWIRE 2
14#define MX35_INT_MMC_SDHC1 7
15#define MXC_INT_MMC_SDHC2 8
16#define MXC_INT_MMC_SDHC3 9
17#define MX35_INT_SSI1 11
18#define MX35_INT_SSI2 12
19#define MXC_INT_GPU2D 16
20#define MXC_INT_ASRC 17
21#define MXC_INT_USBHS 35
22#define MXC_INT_USBOTG 37
23#define MXC_INT_ESAI 40
24#define MXC_INT_CAN1 43
25#define MXC_INT_CAN2 44
26#define MXC_INT_MLB 46
27#define MXC_INT_SPDIF 47
28#define MXC_INT_FEC 57
29
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
new file mode 100644
index 000000000000..3878c6085d5c
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -0,0 +1,290 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MX31_H__
12#define __ASM_ARCH_MXC_MX31_H__
13
14#ifndef __ASM_ARCH_MXC_HARDWARE_H__
15#error "Do not include directly."
16#endif
17
18/*
19 * MX31 memory map:
20 *
21 * Virt Phys Size What
22 * ---------------------------------------------------------------------------
23 * FC000000 43F00000 1M AIPS 1
24 * FC100000 50000000 1M SPBA
25 * FC200000 53F00000 1M AIPS 2
26 * FC500000 60000000 128M ROMPATCH
27 * FC400000 68000000 128M AVIC
28 * 70000000 256M IPU (MAX M2)
29 * 80000000 256M CSD0 SDRAM/DDR
30 * 90000000 256M CSD1 SDRAM/DDR
31 * A0000000 128M CS0 Flash
32 * A8000000 128M CS1 Flash
33 * B0000000 32M CS2
34 * B2000000 32M CS3
35 * F4000000 B4000000 32M CS4
36 * B6000000 32M CS5
37 * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
38 * C0000000 64M PCMCIA/CF
39 */
40
41#define CS0_BASE_ADDR 0xA0000000
42#define CS1_BASE_ADDR 0xA8000000
43#define CS2_BASE_ADDR 0xB0000000
44#define CS3_BASE_ADDR 0xB2000000
45
46#define CS4_BASE_ADDR 0xB4000000
47#define CS4_BASE_ADDR_VIRT 0xF4000000
48#define CS4_SIZE SZ_32M
49
50#define CS5_BASE_ADDR 0xB6000000
51#define PCMCIA_MEM_BASE_ADDR 0xBC000000
52
53/*
54 * L2CC
55 */
56#define L2CC_BASE_ADDR 0x30000000
57#define L2CC_SIZE SZ_1M
58
59/*
60 * AIPS 1
61 */
62#define AIPS1_BASE_ADDR 0x43F00000
63#define AIPS1_BASE_ADDR_VIRT 0xFC000000
64#define AIPS1_SIZE SZ_1M
65
66#define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000)
67#define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000)
68#define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000)
69#define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000)
70#define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000)
71#define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000)
72#define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
73#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
74#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
75#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
76#define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
77#define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
78#define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
79#define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
80#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
81#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
82#define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
83#define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000)
84
85/*
86 * SPBA global module enabled #0
87 */
88#define SPBA0_BASE_ADDR 0x50000000
89#define SPBA0_BASE_ADDR_VIRT 0xFC100000
90#define SPBA0_SIZE SZ_1M
91
92#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000)
93#define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
94#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
95#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
96#define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
97#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
98
99/*
100 * AIPS 2
101 */
102#define AIPS2_BASE_ADDR 0x53F00000
103#define AIPS2_BASE_ADDR_VIRT 0xFC200000
104#define AIPS2_SIZE SZ_1M
105#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
106#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
107#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
108#define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
109#define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
110#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
111#define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
112#define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
113#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
114#define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
115#define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
116#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000)
117#define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
118#define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
119#define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
120#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
121
122/*
123 * ROMP and AVIC
124 */
125#define ROMP_BASE_ADDR 0x60000000
126#define ROMP_BASE_ADDR_VIRT 0xFC500000
127#define ROMP_SIZE SZ_1M
128
129#define AVIC_BASE_ADDR 0x68000000
130#define AVIC_BASE_ADDR_VIRT 0xFC400000
131#define AVIC_SIZE SZ_1M
132
133/*
134 * NAND, SDRAM, WEIM, M3IF, EMI controllers
135 */
136#define X_MEMC_BASE_ADDR 0xB8000000
137#define X_MEMC_BASE_ADDR_VIRT 0xFC320000
138#define X_MEMC_SIZE SZ_64K
139
140#define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
141#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
142#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
143#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
144#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
145
146/*
147 * Memory regions and CS
148 */
149#define IPU_MEM_BASE_ADDR 0x70000000
150#define CSD0_BASE_ADDR 0x80000000
151#define CSD1_BASE_ADDR 0x90000000
152
153/*!
154 * This macro defines the physical to virtual address mapping for all the
155 * peripheral modules. It is used by passing in the physical address as x
156 * and returning the virtual address. If the physical address is not mapped,
157 * it returns 0xDEADBEEF
158 */
159#define IO_ADDRESS(x) \
160 (void __force __iomem *) \
161 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
162 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
163 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
164 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
165 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
166 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
167 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
168 0xDEADBEEF)
169
170/*
171 * define the address mapping macros: in physical address order
172 */
173#define L2CC_IO_ADDRESS(x) \
174 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
175
176#define AIPS1_IO_ADDRESS(x) \
177 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
178
179#define SPBA0_IO_ADDRESS(x) \
180 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
181
182#define AIPS2_IO_ADDRESS(x) \
183 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
184
185#define ROMP_IO_ADDRESS(x) \
186 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
187
188#define AVIC_IO_ADDRESS(x) \
189 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
190
191#define CS4_IO_ADDRESS(x) \
192 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
193
194#define X_MEMC_IO_ADDRESS(x) \
195 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
196
197#define PCMCIA_IO_ADDRESS(x) \
198 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
199
200/*
201 * Interrupt numbers
202 */
203#define MXC_INT_I2C3 3
204#define MXC_INT_I2C2 4
205#define MXC_INT_RTIC 6
206#define MXC_INT_I2C 10
207#define MXC_INT_CSPI2 13
208#define MXC_INT_CSPI1 14
209#define MXC_INT_ATA 15
210#define MXC_INT_UART3 18
211#define MXC_INT_IIM 19
212#define MXC_INT_RNGA 22
213#define MXC_INT_EVTMON 23
214#define MXC_INT_KPP 24
215#define MXC_INT_RTC 25
216#define MXC_INT_PWM 26
217#define MXC_INT_EPIT2 27
218#define MXC_INT_EPIT1 28
219#define MXC_INT_GPT 29
220#define MXC_INT_POWER_FAIL 30
221#define MXC_INT_UART2 32
222#define MXC_INT_NANDFC 33
223#define MXC_INT_SDMA 34
224#define MXC_INT_MSHC1 39
225#define MXC_INT_IPU_ERR 41
226#define MXC_INT_IPU_SYN 42
227#define MXC_INT_UART1 45
228#define MXC_INT_ECT 48
229#define MXC_INT_SCC_SCM 49
230#define MXC_INT_SCC_SMN 50
231#define MXC_INT_GPIO2 51
232#define MXC_INT_GPIO1 52
233#define MXC_INT_WDOG 55
234#define MXC_INT_GPIO3 56
235#define MXC_INT_EXT_POWER 58
236#define MXC_INT_EXT_TEMPER 59
237#define MXC_INT_EXT_SENSOR60 60
238#define MXC_INT_EXT_SENSOR61 61
239#define MXC_INT_EXT_WDOG 62
240#define MXC_INT_EXT_TV 63
241
242#define PROD_SIGNATURE 0x1 /* For MX31 */
243
244/* silicon revisions specific to i.MX31 */
245#define CHIP_REV_1_0 0x10
246#define CHIP_REV_1_1 0x11
247#define CHIP_REV_1_2 0x12
248#define CHIP_REV_1_3 0x13
249#define CHIP_REV_2_0 0x20
250#define CHIP_REV_2_1 0x21
251#define CHIP_REV_2_2 0x22
252#define CHIP_REV_2_3 0x23
253#define CHIP_REV_3_0 0x30
254#define CHIP_REV_3_1 0x31
255#define CHIP_REV_3_2 0x32
256
257#define SYSTEM_REV_MIN CHIP_REV_1_0
258#define SYSTEM_REV_NUM 3
259
260/* gpio and gpio based interrupt handling */
261#define GPIO_DR 0x00
262#define GPIO_GDIR 0x04
263#define GPIO_PSR 0x08
264#define GPIO_ICR1 0x0C
265#define GPIO_ICR2 0x10
266#define GPIO_IMR 0x14
267#define GPIO_ISR 0x18
268#define GPIO_INT_LOW_LEV 0x0
269#define GPIO_INT_HIGH_LEV 0x1
270#define GPIO_INT_RISE_EDGE 0x2
271#define GPIO_INT_FALL_EDGE 0x3
272#define GPIO_INT_NONE 0x4
273
274/* Mandatory defines used globally */
275
276/* this CPU supports up to 96 GPIOs */
277#define ARCH_NR_GPIOS 96
278
279#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
280
281extern unsigned int system_rev;
282
283static inline int mx31_revision(void)
284{
285 return system_rev;
286}
287#endif
288
289#endif /* __ASM_ARCH_MXC_MX31_H__ */
290
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index f6caab062131..5fa2a07f4eaf 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -24,13 +24,74 @@
24#error "Do not include directly." 24#error "Do not include directly."
25#endif 25#endif
26 26
27/* clean up all things that are not used */ 27#define MXC_CPU_MX1 1
28#ifndef CONFIG_ARCH_MX3 28#define MXC_CPU_MX21 21
29# define cpu_is_mx31() (0) 29#define MXC_CPU_MX27 27
30#define MXC_CPU_MX31 31
31#define MXC_CPU_MX35 35
32
33#ifndef __ASSEMBLY__
34extern unsigned int __mxc_cpu_type;
35#endif
36
37#ifdef CONFIG_ARCH_MX1
38# ifdef mxc_cpu_type
39# undef mxc_cpu_type
40# define mxc_cpu_type __mxc_cpu_type
41# else
42# define mxc_cpu_type MXC_CPU_MX1
43# endif
44# define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1)
45#else
46# define cpu_is_mx1() (0)
47#endif
48
49#ifdef CONFIG_MACH_MX21
50# ifdef mxc_cpu_type
51# undef mxc_cpu_type
52# define mxc_cpu_type __mxc_cpu_type
53# else
54# define mxc_cpu_type MXC_CPU_MX21
55# endif
56# define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21)
57#else
58# define cpu_is_mx21() (0)
30#endif 59#endif
31 60
32#ifndef CONFIG_MACH_MX27 61#ifdef CONFIG_MACH_MX27
33# define cpu_is_mx27() (0) 62# ifdef mxc_cpu_type
63# undef mxc_cpu_type
64# define mxc_cpu_type __mxc_cpu_type
65# else
66# define mxc_cpu_type MXC_CPU_MX27
67# endif
68# define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27)
69#else
70# define cpu_is_mx27() (0)
71#endif
72
73#ifdef CONFIG_ARCH_MX31
74# ifdef mxc_cpu_type
75# undef mxc_cpu_type
76# define mxc_cpu_type __mxc_cpu_type
77# else
78# define mxc_cpu_type MXC_CPU_MX31
79# endif
80# define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31)
81#else
82# define cpu_is_mx31() (0)
83#endif
84
85#ifdef CONFIG_ARCH_MX35
86# ifdef mxc_cpu_type
87# undef mxc_cpu_type
88# define mxc_cpu_type __mxc_cpu_type
89# else
90# define mxc_cpu_type MXC_CPU_MX35
91# endif
92# define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35)
93#else
94# define cpu_is_mx35() (0)
34#endif 95#endif
35 96
36#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) 97#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
@@ -39,4 +100,7 @@
39#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) 100#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
40#endif 101#endif
41 102
103#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
104#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
105
42#endif /* __ASM_ARCH_MXC_H__ */ 106#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c
index df6f18395686..a37163ce280b 100644
--- a/arch/arm/plat-mxc/iomux-mx1-mx2.c
+++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c
@@ -32,7 +32,7 @@
32 32
33#include <mach/hardware.h> 33#include <mach/hardware.h>
34#include <asm/mach/map.h> 34#include <asm/mach/map.h>
35#include <mach/iomux-mx1-mx2.h> 35#include <mach/iomux.h>
36 36
37void mxc_gpio_mode(int gpio_mode) 37void mxc_gpio_mode(int gpio_mode)
38{ 38{
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
new file mode 100644
index 000000000000..9bffbc507cc2
--- /dev/null
+++ b/arch/arm/plat-mxc/pwm.c
@@ -0,0 +1,300 @@
1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/pwm.h>
18
19#if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21
20#define PWM_VER_1
21
22#define PWMCR 0x00 /* PWM Control Register */
23#define PWMSR 0x04 /* PWM Sample Register */
24#define PWMPR 0x08 /* PWM Period Register */
25#define PWMCNR 0x0C /* PWM Counter Register */
26
27#define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */
28#define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */
29#define PWMCR_SWR (1 << 16) /* Software Reset */
30#define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */
31#define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */
32#define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */
33#define PWMCR_IRQ (1 << 7) /* Interrupt Request */
34#define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */
35#define PWMCR_FIFOAV (1 << 5) /* FIFO Available */
36#define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */
37#define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
38#define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */
39
40#define MAX_DIV (128 * 16)
41#endif
42
43#if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31
44#define PWM_VER_2
45
46#define PWMCR 0x00 /* PWM Control Register */
47#define PWMSR 0x04 /* PWM Status Register */
48#define PWMIR 0x08 /* PWM Interrupt Register */
49#define PWMSAR 0x0C /* PWM Sample Register */
50#define PWMPR 0x10 /* PWM Period Register */
51#define PWMCNR 0x14 /* PWM Counter Register */
52
53#define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */
54#define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */
55#define PWMCR_SWR (1 << 3) /* Software Reset */
56#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */
57#define PWMCR_CLKSRC(x) (((x) & 0x3) << 16)
58#define PWMCR_CLKSRC_OFF (0 << 16)
59#define PWMCR_CLKSRC_IPG (1 << 16)
60#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
61#define PWMCR_CLKSRC_CLK32 (3 << 16)
62#define PWMCR_POUTC
63#define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */
64#define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */
65#define PWMCR_DBGEN (1 << 22) /* Debug Mode */
66#define PWMCR_WAITEN (1 << 23) /* Wait Mode */
67#define PWMCR_DOZEN (1 << 24) /* Doze Mode */
68#define PWMCR_STOPEN (1 << 25) /* Stop Mode */
69#define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */
70
71#define MAX_DIV 4096
72#endif
73
74#define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
75#define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
76#define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
77
78struct pwm_device {
79 struct list_head node;
80 struct platform_device *pdev;
81
82 const char *label;
83 struct clk *clk;
84
85 int clk_enabled;
86 void __iomem *mmio_base;
87
88 unsigned int use_count;
89 unsigned int pwm_id;
90};
91
92int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
93{
94 unsigned long long c;
95 unsigned long period_cycles, duty_cycles, prescale;
96
97 if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
98 return -EINVAL;
99
100 c = clk_get_rate(pwm->clk);
101 c = c * period_ns;
102 do_div(c, 1000000000);
103 period_cycles = c;
104
105 prescale = period_cycles / 0x10000 + 1;
106
107 period_cycles /= prescale;
108 c = (unsigned long long)period_cycles * duty_ns;
109 do_div(c, period_ns);
110 duty_cycles = c;
111
112#ifdef PWM_VER_2
113 writel(duty_cycles, pwm->mmio_base + PWMSAR);
114 writel(period_cycles, pwm->mmio_base + PWMPR);
115 writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN,
116 pwm->mmio_base + PWMCR);
117#elif defined PWM_VER_1
118#error PWM not yet working on MX1 / MX21
119#endif
120
121 return 0;
122}
123EXPORT_SYMBOL(pwm_config);
124
125int pwm_enable(struct pwm_device *pwm)
126{
127 int rc = 0;
128
129 if (!pwm->clk_enabled) {
130 rc = clk_enable(pwm->clk);
131 if (!rc)
132 pwm->clk_enabled = 1;
133 }
134 return rc;
135}
136EXPORT_SYMBOL(pwm_enable);
137
138void pwm_disable(struct pwm_device *pwm)
139{
140 if (pwm->clk_enabled) {
141 clk_disable(pwm->clk);
142 pwm->clk_enabled = 0;
143 }
144}
145EXPORT_SYMBOL(pwm_disable);
146
147static DEFINE_MUTEX(pwm_lock);
148static LIST_HEAD(pwm_list);
149
150struct pwm_device *pwm_request(int pwm_id, const char *label)
151{
152 struct pwm_device *pwm;
153 int found = 0;
154
155 mutex_lock(&pwm_lock);
156
157 list_for_each_entry(pwm, &pwm_list, node) {
158 if (pwm->pwm_id == pwm_id) {
159 found = 1;
160 break;
161 }
162 }
163
164 if (found) {
165 if (pwm->use_count == 0) {
166 pwm->use_count++;
167 pwm->label = label;
168 } else
169 pwm = ERR_PTR(-EBUSY);
170 } else
171 pwm = ERR_PTR(-ENOENT);
172
173 mutex_unlock(&pwm_lock);
174 return pwm;
175}
176EXPORT_SYMBOL(pwm_request);
177
178void pwm_free(struct pwm_device *pwm)
179{
180 mutex_lock(&pwm_lock);
181
182 if (pwm->use_count) {
183 pwm->use_count--;
184 pwm->label = NULL;
185 } else
186 pr_warning("PWM device already freed\n");
187
188 mutex_unlock(&pwm_lock);
189}
190EXPORT_SYMBOL(pwm_free);
191
192static int __devinit mxc_pwm_probe(struct platform_device *pdev)
193{
194 struct pwm_device *pwm;
195 struct resource *r;
196 int ret = 0;
197
198 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
199 if (pwm == NULL) {
200 dev_err(&pdev->dev, "failed to allocate memory\n");
201 return -ENOMEM;
202 }
203
204 pwm->clk = clk_get(&pdev->dev, "pwm");
205
206 if (IS_ERR(pwm->clk)) {
207 ret = PTR_ERR(pwm->clk);
208 goto err_free;
209 }
210
211 pwm->clk_enabled = 0;
212
213 pwm->use_count = 0;
214 pwm->pwm_id = pdev->id;
215 pwm->pdev = pdev;
216
217 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
218 if (r == NULL) {
219 dev_err(&pdev->dev, "no memory resource defined\n");
220 ret = -ENODEV;
221 goto err_free_clk;
222 }
223
224 r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
225 if (r == NULL) {
226 dev_err(&pdev->dev, "failed to request memory resource\n");
227 ret = -EBUSY;
228 goto err_free_clk;
229 }
230
231 pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
232 if (pwm->mmio_base == NULL) {
233 dev_err(&pdev->dev, "failed to ioremap() registers\n");
234 ret = -ENODEV;
235 goto err_free_mem;
236 }
237
238 mutex_lock(&pwm_lock);
239 list_add_tail(&pwm->node, &pwm_list);
240 mutex_unlock(&pwm_lock);
241
242 platform_set_drvdata(pdev, pwm);
243 return 0;
244
245err_free_mem:
246 release_mem_region(r->start, r->end - r->start + 1);
247err_free_clk:
248 clk_put(pwm->clk);
249err_free:
250 kfree(pwm);
251 return ret;
252}
253
254static int __devexit mxc_pwm_remove(struct platform_device *pdev)
255{
256 struct pwm_device *pwm;
257 struct resource *r;
258
259 pwm = platform_get_drvdata(pdev);
260 if (pwm == NULL)
261 return -ENODEV;
262
263 mutex_lock(&pwm_lock);
264 list_del(&pwm->node);
265 mutex_unlock(&pwm_lock);
266
267 iounmap(pwm->mmio_base);
268
269 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
270 release_mem_region(r->start, r->end - r->start + 1);
271
272 clk_put(pwm->clk);
273
274 kfree(pwm);
275 return 0;
276}
277
278static struct platform_driver mxc_pwm_driver = {
279 .driver = {
280 .name = "mxc_pwm",
281 },
282 .probe = mxc_pwm_probe,
283 .remove = __devexit_p(mxc_pwm_remove),
284};
285
286static int __init mxc_pwm_init(void)
287{
288 return platform_driver_register(&mxc_pwm_driver);
289}
290arch_initcall(mxc_pwm_init);
291
292static void __exit mxc_pwm_exit(void)
293{
294 platform_driver_unregister(&mxc_pwm_driver);
295}
296module_exit(mxc_pwm_exit);
297
298MODULE_LICENSE("GPL v2");
299MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
300
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 758a1293bcfa..ef1b3cd85bd3 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -34,9 +34,6 @@
34static struct clock_event_device clockevent_mxc; 34static struct clock_event_device clockevent_mxc;
35static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; 35static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED;
36 36
37/* clock source for the timer */
38static struct clk *timer_clk;
39
40/* clock source */ 37/* clock source */
41 38
42static cycle_t mxc_get_cycles(void) 39static cycle_t mxc_get_cycles(void)
@@ -53,13 +50,11 @@ static struct clocksource clocksource_mxc = {
53 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
54}; 51};
55 52
56static int __init mxc_clocksource_init(void) 53static int __init mxc_clocksource_init(struct clk *timer_clk)
57{ 54{
58 unsigned int clock; 55 unsigned int c = clk_get_rate(timer_clk);
59
60 clock = clk_get_rate(timer_clk);
61 56
62 clocksource_mxc.mult = clocksource_hz2mult(clock, 57 clocksource_mxc.mult = clocksource_hz2mult(c,
63 clocksource_mxc.shift); 58 clocksource_mxc.shift);
64 clocksource_register(&clocksource_mxc); 59 clocksource_register(&clocksource_mxc);
65 60
@@ -177,13 +172,11 @@ static struct clock_event_device clockevent_mxc = {
177 .rating = 200, 172 .rating = 200,
178}; 173};
179 174
180static int __init mxc_clockevent_init(void) 175static int __init mxc_clockevent_init(struct clk *timer_clk)
181{ 176{
182 unsigned int clock; 177 unsigned int c = clk_get_rate(timer_clk);
183
184 clock = clk_get_rate(timer_clk);
185 178
186 clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC, 179 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
187 clockevent_mxc.shift); 180 clockevent_mxc.shift);
188 clockevent_mxc.max_delta_ns = 181 clockevent_mxc.max_delta_ns =
189 clockevent_delta2ns(0xfffffffe, &clockevent_mxc); 182 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
@@ -197,14 +190,8 @@ static int __init mxc_clockevent_init(void)
197 return 0; 190 return 0;
198} 191}
199 192
200void __init mxc_timer_init(const char *clk_timer) 193void __init mxc_timer_init(struct clk *timer_clk)
201{ 194{
202 timer_clk = clk_get(NULL, clk_timer);
203 if (!timer_clk) {
204 printk(KERN_ERR"Cannot determine timer clock. Giving up.\n");
205 return;
206 }
207
208 clk_enable(timer_clk); 195 clk_enable(timer_clk);
209 196
210 /* 197 /*
@@ -219,10 +206,9 @@ void __init mxc_timer_init(const char *clk_timer)
219 TIMER_BASE + MXC_TCTL); 206 TIMER_BASE + MXC_TCTL);
220 207
221 /* init and register the timer to the framework */ 208 /* init and register the timer to the framework */
222 mxc_clocksource_init(); 209 mxc_clocksource_init(timer_clk);
223 mxc_clockevent_init(); 210 mxc_clockevent_init(timer_clk);
224 211
225 /* Make irqs happen */ 212 /* Make irqs happen */
226 setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); 213 setup_irq(TIMER_INTERRUPT, &mxc_timer_irq);
227} 214}
228
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 967186425ca1..0d12c2164766 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -265,51 +265,36 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
265 * polarity LEVEL mask 265 * polarity LEVEL mask
266 * 266 *
267 ****************************************************************************/ 267 ****************************************************************************/
268static void gpio_irq_edge_ack(u32 irq)
269{
270 int pin = irq_to_gpio(irq);
271
272 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
273}
274
275static void gpio_irq_edge_mask(u32 irq)
276{
277 int pin = irq_to_gpio(irq);
278 u32 u;
279
280 u = readl(GPIO_EDGE_MASK(pin));
281 u &= ~(1 << (pin & 31));
282 writel(u, GPIO_EDGE_MASK(pin));
283}
284 268
285static void gpio_irq_edge_unmask(u32 irq) 269static void gpio_irq_ack(u32 irq)
286{ 270{
287 int pin = irq_to_gpio(irq); 271 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
288 u32 u; 272 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
289 273 int pin = irq_to_gpio(irq);
290 u = readl(GPIO_EDGE_MASK(pin)); 274 writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
291 u |= 1 << (pin & 31); 275 }
292 writel(u, GPIO_EDGE_MASK(pin));
293} 276}
294 277
295static void gpio_irq_level_mask(u32 irq) 278static void gpio_irq_mask(u32 irq)
296{ 279{
297 int pin = irq_to_gpio(irq); 280 int pin = irq_to_gpio(irq);
298 u32 u; 281 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
299 282 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
300 u = readl(GPIO_LEVEL_MASK(pin)); 283 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
284 u32 u = readl(reg);
301 u &= ~(1 << (pin & 31)); 285 u &= ~(1 << (pin & 31));
302 writel(u, GPIO_LEVEL_MASK(pin)); 286 writel(u, reg);
303} 287}
304 288
305static void gpio_irq_level_unmask(u32 irq) 289static void gpio_irq_unmask(u32 irq)
306{ 290{
307 int pin = irq_to_gpio(irq); 291 int pin = irq_to_gpio(irq);
308 u32 u; 292 int type = irq_desc[irq].status & IRQ_TYPE_SENSE_MASK;
309 293 u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
310 u = readl(GPIO_LEVEL_MASK(pin)); 294 GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
295 u32 u = readl(reg);
311 u |= 1 << (pin & 31); 296 u |= 1 << (pin & 31);
312 writel(u, GPIO_LEVEL_MASK(pin)); 297 writel(u, reg);
313} 298}
314 299
315static int gpio_irq_set_type(u32 irq, u32 type) 300static int gpio_irq_set_type(u32 irq, u32 type)
@@ -331,9 +316,9 @@ static int gpio_irq_set_type(u32 irq, u32 type)
331 * Set edge/level type. 316 * Set edge/level type.
332 */ 317 */
333 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { 318 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
334 desc->chip = &orion_gpio_irq_edge_chip; 319 desc->handle_irq = handle_edge_irq;
335 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 320 } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
336 desc->chip = &orion_gpio_irq_level_chip; 321 desc->handle_irq = handle_level_irq;
337 } else { 322 } else {
338 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type); 323 printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
339 return -EINVAL; 324 return -EINVAL;
@@ -371,19 +356,11 @@ static int gpio_irq_set_type(u32 irq, u32 type)
371 return 0; 356 return 0;
372} 357}
373 358
374struct irq_chip orion_gpio_irq_edge_chip = { 359struct irq_chip orion_gpio_irq_chip = {
375 .name = "orion_gpio_irq_edge", 360 .name = "orion_gpio",
376 .ack = gpio_irq_edge_ack, 361 .ack = gpio_irq_ack,
377 .mask = gpio_irq_edge_mask, 362 .mask = gpio_irq_mask,
378 .unmask = gpio_irq_edge_unmask, 363 .unmask = gpio_irq_unmask,
379 .set_type = gpio_irq_set_type,
380};
381
382struct irq_chip orion_gpio_irq_level_chip = {
383 .name = "orion_gpio_irq_level",
384 .mask = gpio_irq_level_mask,
385 .mask_ack = gpio_irq_level_mask,
386 .unmask = gpio_irq_level_unmask,
387 .set_type = gpio_irq_set_type, 364 .set_type = gpio_irq_set_type,
388}; 365};
389 366
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 54deaf274b52..ec743e82c876 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -31,8 +31,7 @@ void orion_gpio_set_blink(unsigned pin, int blink);
31/* 31/*
32 * GPIO interrupt handling. 32 * GPIO interrupt handling.
33 */ 33 */
34extern struct irq_chip orion_gpio_irq_edge_chip; 34extern struct irq_chip orion_gpio_irq_chip;
35extern struct irq_chip orion_gpio_irq_level_chip;
36void orion_gpio_irq_handler(int irqoff); 35void orion_gpio_irq_handler(int irqoff);
37 36
38 37
diff --git a/arch/arm/plat-s3c64xx/irq-eint.c b/arch/arm/plat-s3c64xx/irq-eint.c
index 1f7cc0067f5c..ebb305ce7689 100644
--- a/arch/arm/plat-s3c64xx/irq-eint.c
+++ b/arch/arm/plat-s3c64xx/irq-eint.c
@@ -55,7 +55,7 @@ static void s3c_irq_eint_unmask(unsigned int irq)
55 u32 mask; 55 u32 mask;
56 56
57 mask = __raw_readl(S3C64XX_EINT0MASK); 57 mask = __raw_readl(S3C64XX_EINT0MASK);
58 mask |= eint_irq_to_bit(irq); 58 mask &= ~eint_irq_to_bit(irq);
59 __raw_writel(mask, S3C64XX_EINT0MASK); 59 __raw_writel(mask, S3C64XX_EINT0MASK);
60} 60}
61 61
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index aafaf7a78886..cff8e84f78f2 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -116,6 +116,7 @@ struct atmel_nand_data {
116 int enable_pin; /* chip enable */ 116 int enable_pin; /* chip enable */
117 int det_pin; /* card detect */ 117 int det_pin; /* card detect */
118 int rdy_pin; /* ready/busy */ 118 int rdy_pin; /* ready/busy */
119 u8 rdy_pin_active_low; /* rdy_pin value is inverted */
119 u8 ale; /* address line number connected to ALE */ 120 u8 ale; /* address line number connected to ALE */
120 u8 cle; /* address line number connected to CLE */ 121 u8 cle; /* address line number connected to CLE */
121 u8 bus_width_16; /* buswidth is 16 bit */ 122 u8 bus_width_16; /* buswidth is 16 bit */
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8f1f97d56e1e..0c1f86e3e44a 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -1129,6 +1129,7 @@ endchoice
1129 1129
1130config PM_WAKEUP_BY_GPIO 1130config PM_WAKEUP_BY_GPIO
1131 bool "Allow Wakeup from Standby by GPIO" 1131 bool "Allow Wakeup from Standby by GPIO"
1132 depends on PM && !BF54x
1132 1133
1133config PM_WAKEUP_GPIO_NUMBER 1134config PM_WAKEUP_GPIO_NUMBER
1134 int "GPIO number" 1135 int "GPIO number"
@@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP
1168 default n 1169 default n
1169 help 1170 help
1170 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) 1171 Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
1172 (all processors, except ADSP-BF549). This option sets
1173 the general-purpose wake-up enable (GPWE) control bit to enable
1174 wake-up upon detection of an active low signal on the /GPW (PH7) pin.
1175 On ADSP-BF549 this option enables the the same functionality on the
1176 /MRXON pin also PH7.
1177
1171endmenu 1178endmenu
1172 1179
1173menu "CPU Frequency scaling" 1180menu "CPU Frequency scaling"
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 5f981d9ca625..79e7e63ab709 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -21,12 +21,6 @@ config DEBUG_STACK_USAGE
21config HAVE_ARCH_KGDB 21config HAVE_ARCH_KGDB
22 def_bool y 22 def_bool y
23 23
24config KGDB_TESTCASE
25 tristate "KGDB: for test case in expect"
26 default n
27 help
28 This is a kgdb test case for automated testing.
29
30config DEBUG_VERBOSE 24config DEBUG_VERBOSE
31 bool "Verbose fault messages" 25 bool "Verbose fault messages"
32 default y 26 default y
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig
index 4fdb9e04759f..281f4b60e603 100644
--- a/arch/blackfin/configs/BF518F-EZBRD_defconfig
+++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc2 3# Linux kernel version: 2.6.28
4# Fri Jan 9 17:58:41 2009 4# Fri Feb 20 10:01:44 2009
5# 5#
6# CONFIG_MMU is not set 6# CONFIG_MMU is not set
7# CONFIG_FPU is not set 7# CONFIG_FPU is not set
@@ -133,10 +133,15 @@ CONFIG_BF518=y
133# CONFIG_BF538 is not set 133# CONFIG_BF538 is not set
134# CONFIG_BF539 is not set 134# CONFIG_BF539 is not set
135# CONFIG_BF542 is not set 135# CONFIG_BF542 is not set
136# CONFIG_BF542M is not set
136# CONFIG_BF544 is not set 137# CONFIG_BF544 is not set
138# CONFIG_BF544M is not set
137# CONFIG_BF547 is not set 139# CONFIG_BF547 is not set
140# CONFIG_BF547M is not set
138# CONFIG_BF548 is not set 141# CONFIG_BF548 is not set
142# CONFIG_BF548M is not set
139# CONFIG_BF549 is not set 143# CONFIG_BF549 is not set
144# CONFIG_BF549M is not set
140# CONFIG_BF561 is not set 145# CONFIG_BF561 is not set
141CONFIG_BF_REV_MIN=0 146CONFIG_BF_REV_MIN=0
142CONFIG_BF_REV_MAX=2 147CONFIG_BF_REV_MAX=2
@@ -426,7 +431,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
426# CONFIG_TIPC is not set 431# CONFIG_TIPC is not set
427# CONFIG_ATM is not set 432# CONFIG_ATM is not set
428# CONFIG_BRIDGE is not set 433# CONFIG_BRIDGE is not set
429# CONFIG_NET_DSA is not set 434CONFIG_NET_DSA=y
435# CONFIG_NET_DSA_TAG_DSA is not set
436# CONFIG_NET_DSA_TAG_EDSA is not set
437# CONFIG_NET_DSA_TAG_TRAILER is not set
438CONFIG_NET_DSA_TAG_STPID=y
439# CONFIG_NET_DSA_MV88E6XXX is not set
440# CONFIG_NET_DSA_MV88E6060 is not set
441# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
442# CONFIG_NET_DSA_MV88E6131 is not set
443# CONFIG_NET_DSA_MV88E6123_61_65 is not set
444CONFIG_NET_DSA_KSZ8893M=y
430# CONFIG_VLAN_8021Q is not set 445# CONFIG_VLAN_8021Q is not set
431# CONFIG_DECNET is not set 446# CONFIG_DECNET is not set
432# CONFIG_LLC2 is not set 447# CONFIG_LLC2 is not set
@@ -529,6 +544,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y
529# 544#
530# Self-contained MTD device drivers 545# Self-contained MTD device drivers
531# 546#
547# CONFIG_MTD_DATAFLASH is not set
548# CONFIG_MTD_M25P80 is not set
532# CONFIG_MTD_SLRAM is not set 549# CONFIG_MTD_SLRAM is not set
533# CONFIG_MTD_PHRAM is not set 550# CONFIG_MTD_PHRAM is not set
534# CONFIG_MTD_MTDRAM is not set 551# CONFIG_MTD_MTDRAM is not set
@@ -561,7 +578,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
561# CONFIG_BLK_DEV_HD is not set 578# CONFIG_BLK_DEV_HD is not set
562CONFIG_MISC_DEVICES=y 579CONFIG_MISC_DEVICES=y
563# CONFIG_EEPROM_93CX6 is not set 580# CONFIG_EEPROM_93CX6 is not set
581# CONFIG_ICS932S401 is not set
564# CONFIG_ENCLOSURE_SERVICES is not set 582# CONFIG_ENCLOSURE_SERVICES is not set
583# CONFIG_C2PORT is not set
565CONFIG_HAVE_IDE=y 584CONFIG_HAVE_IDE=y
566# CONFIG_IDE is not set 585# CONFIG_IDE is not set
567 586
@@ -607,6 +626,7 @@ CONFIG_BFIN_RX_DESC_NUM=20
607# CONFIG_SMC91X is not set 626# CONFIG_SMC91X is not set
608# CONFIG_SMSC911X is not set 627# CONFIG_SMSC911X is not set
609# CONFIG_DM9000 is not set 628# CONFIG_DM9000 is not set
629# CONFIG_ENC28J60 is not set
610# CONFIG_IBM_NEW_EMAC_ZMII is not set 630# CONFIG_IBM_NEW_EMAC_ZMII is not set
611# CONFIG_IBM_NEW_EMAC_RGMII is not set 631# CONFIG_IBM_NEW_EMAC_RGMII is not set
612# CONFIG_IBM_NEW_EMAC_TAH is not set 632# CONFIG_IBM_NEW_EMAC_TAH is not set
@@ -764,7 +784,23 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
764# CONFIG_I2C_DEBUG_ALGO is not set 784# CONFIG_I2C_DEBUG_ALGO is not set
765# CONFIG_I2C_DEBUG_BUS is not set 785# CONFIG_I2C_DEBUG_BUS is not set
766# CONFIG_I2C_DEBUG_CHIP is not set 786# CONFIG_I2C_DEBUG_CHIP is not set
767# CONFIG_SPI is not set 787CONFIG_SPI=y
788# CONFIG_SPI_DEBUG is not set
789CONFIG_SPI_MASTER=y
790
791#
792# SPI Master Controller Drivers
793#
794CONFIG_SPI_BFIN=y
795# CONFIG_SPI_BFIN_LOCK is not set
796# CONFIG_SPI_BITBANG is not set
797
798#
799# SPI Protocol Masters
800#
801# CONFIG_SPI_AT25 is not set
802# CONFIG_SPI_SPIDEV is not set
803# CONFIG_SPI_TLE62X0 is not set
768CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y 804CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
769# CONFIG_GPIOLIB is not set 805# CONFIG_GPIOLIB is not set
770# CONFIG_W1 is not set 806# CONFIG_W1 is not set
@@ -788,8 +824,10 @@ CONFIG_BFIN_WDT=y
788# CONFIG_MFD_SM501 is not set 824# CONFIG_MFD_SM501 is not set
789# CONFIG_HTC_PASIC3 is not set 825# CONFIG_HTC_PASIC3 is not set
790# CONFIG_MFD_TMIO is not set 826# CONFIG_MFD_TMIO is not set
827# CONFIG_PMIC_DA903X is not set
791# CONFIG_MFD_WM8400 is not set 828# CONFIG_MFD_WM8400 is not set
792# CONFIG_MFD_WM8350_I2C is not set 829# CONFIG_MFD_WM8350_I2C is not set
830# CONFIG_REGULATOR is not set
793 831
794# 832#
795# Multimedia devices 833# Multimedia devices
@@ -861,10 +899,18 @@ CONFIG_RTC_INTF_DEV=y
861# CONFIG_RTC_DRV_M41T80 is not set 899# CONFIG_RTC_DRV_M41T80 is not set
862# CONFIG_RTC_DRV_S35390A is not set 900# CONFIG_RTC_DRV_S35390A is not set
863# CONFIG_RTC_DRV_FM3130 is not set 901# CONFIG_RTC_DRV_FM3130 is not set
902# CONFIG_RTC_DRV_RX8581 is not set
864 903
865# 904#
866# SPI RTC drivers 905# SPI RTC drivers
867# 906#
907# CONFIG_RTC_DRV_M41T94 is not set
908# CONFIG_RTC_DRV_DS1305 is not set
909# CONFIG_RTC_DRV_DS1390 is not set
910# CONFIG_RTC_DRV_MAX6902 is not set
911# CONFIG_RTC_DRV_R9701 is not set
912# CONFIG_RTC_DRV_RS5C348 is not set
913# CONFIG_RTC_DRV_DS3234 is not set
868 914
869# 915#
870# Platform RTC drivers 916# Platform RTC drivers
@@ -1062,12 +1108,20 @@ CONFIG_DEBUG_INFO=y
1062# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set 1108# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1063# CONFIG_FAULT_INJECTION is not set 1109# CONFIG_FAULT_INJECTION is not set
1064CONFIG_SYSCTL_SYSCALL_CHECK=y 1110CONFIG_SYSCTL_SYSCALL_CHECK=y
1111
1112#
1113# Tracers
1114#
1115# CONFIG_SCHED_TRACER is not set
1116# CONFIG_CONTEXT_SWITCH_TRACER is not set
1117# CONFIG_BOOT_TRACER is not set
1065# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 1118# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1066# CONFIG_SAMPLES is not set 1119# CONFIG_SAMPLES is not set
1067CONFIG_HAVE_ARCH_KGDB=y 1120CONFIG_HAVE_ARCH_KGDB=y
1068# CONFIG_KGDB is not set 1121# CONFIG_KGDB is not set
1069# CONFIG_DEBUG_STACKOVERFLOW is not set 1122# CONFIG_DEBUG_STACKOVERFLOW is not set
1070# CONFIG_DEBUG_STACK_USAGE is not set 1123# CONFIG_DEBUG_STACK_USAGE is not set
1124# CONFIG_KGDB_TESTCASE is not set
1071CONFIG_DEBUG_VERBOSE=y 1125CONFIG_DEBUG_VERBOSE=y
1072CONFIG_DEBUG_MMRS=y 1126CONFIG_DEBUG_MMRS=y
1073# CONFIG_DEBUG_HWERR is not set 1127# CONFIG_DEBUG_HWERR is not set
@@ -1100,6 +1154,7 @@ CONFIG_CRYPTO=y
1100# 1154#
1101# CONFIG_CRYPTO_FIPS is not set 1155# CONFIG_CRYPTO_FIPS is not set
1102# CONFIG_CRYPTO_MANAGER is not set 1156# CONFIG_CRYPTO_MANAGER is not set
1157# CONFIG_CRYPTO_MANAGER2 is not set
1103# CONFIG_CRYPTO_GF128MUL is not set 1158# CONFIG_CRYPTO_GF128MUL is not set
1104# CONFIG_CRYPTO_NULL is not set 1159# CONFIG_CRYPTO_NULL is not set
1105# CONFIG_CRYPTO_CRYPTD is not set 1160# CONFIG_CRYPTO_CRYPTD is not set
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 833128b39724..a50050f17706 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -327,8 +327,8 @@ CONFIG_BFIN_ICACHE=y
327CONFIG_BFIN_DCACHE=y 327CONFIG_BFIN_DCACHE=y
328# CONFIG_BFIN_DCACHE_BANKA is not set 328# CONFIG_BFIN_DCACHE_BANKA is not set
329# CONFIG_BFIN_ICACHE_LOCK is not set 329# CONFIG_BFIN_ICACHE_LOCK is not set
330# CONFIG_BFIN_WB is not set 330CONFIG_BFIN_WB=y
331CONFIG_BFIN_WT=y 331# CONFIG_BFIN_WT is not set
332# CONFIG_MPU is not set 332# CONFIG_MPU is not set
333 333
334# 334#
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 334c94b51c40..0a2a00d63887 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 9d733436e300..eb027587a355 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y
290CONFIG_BFIN_DCACHE=y 290CONFIG_BFIN_DCACHE=y
291# CONFIG_BFIN_DCACHE_BANKA is not set 291# CONFIG_BFIN_DCACHE_BANKA is not set
292# CONFIG_BFIN_ICACHE_LOCK is not set 292# CONFIG_BFIN_ICACHE_LOCK is not set
293# CONFIG_BFIN_WB is not set 293CONFIG_BFIN_WB=y
294CONFIG_BFIN_WT=y 294# CONFIG_BFIN_WT is not set
295# CONFIG_MPU is not set 295# CONFIG_MPU is not set
296 296
297# 297#
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index 4fb4108d3103..9e62b9f40eb1 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -298,8 +298,8 @@ CONFIG_BFIN_ICACHE=y
298CONFIG_BFIN_DCACHE=y 298CONFIG_BFIN_DCACHE=y
299# CONFIG_BFIN_DCACHE_BANKA is not set 299# CONFIG_BFIN_DCACHE_BANKA is not set
300# CONFIG_BFIN_ICACHE_LOCK is not set 300# CONFIG_BFIN_ICACHE_LOCK is not set
301# CONFIG_BFIN_WB is not set 301CONFIG_BFIN_WB=y
302CONFIG_BFIN_WT=y 302# CONFIG_BFIN_WT is not set
303# CONFIG_MPU is not set 303# CONFIG_MPU is not set
304 304
305# 305#
@@ -568,15 +568,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2
568# CONFIG_MTD_DOC2000 is not set 568# CONFIG_MTD_DOC2000 is not set
569# CONFIG_MTD_DOC2001 is not set 569# CONFIG_MTD_DOC2001 is not set
570# CONFIG_MTD_DOC2001PLUS is not set 570# CONFIG_MTD_DOC2001PLUS is not set
571CONFIG_MTD_NAND=m 571# CONFIG_MTD_NAND is not set
572# CONFIG_MTD_NAND_VERIFY_WRITE is not set
573# CONFIG_MTD_NAND_ECC_SMC is not set
574# CONFIG_MTD_NAND_MUSEUM_IDS is not set
575# CONFIG_MTD_NAND_BFIN is not set
576CONFIG_MTD_NAND_IDS=m
577# CONFIG_MTD_NAND_DISKONCHIP is not set
578# CONFIG_MTD_NAND_NANDSIM is not set
579CONFIG_MTD_NAND_PLATFORM=m
580# CONFIG_MTD_ONENAND is not set 572# CONFIG_MTD_ONENAND is not set
581 573
582# 574#
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig
index cb32f5624a1b..dd6ad6be1c87 100644
--- a/arch/blackfin/configs/BF538-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF538-EZKIT_defconfig
@@ -306,8 +306,8 @@ CONFIG_BFIN_ICACHE=y
306CONFIG_BFIN_DCACHE=y 306CONFIG_BFIN_DCACHE=y
307# CONFIG_BFIN_DCACHE_BANKA is not set 307# CONFIG_BFIN_DCACHE_BANKA is not set
308# CONFIG_BFIN_ICACHE_LOCK is not set 308# CONFIG_BFIN_ICACHE_LOCK is not set
309# CONFIG_BFIN_WB is not set 309CONFIG_BFIN_WB=y
310CONFIG_BFIN_WT=y 310# CONFIG_BFIN_WT is not set
311# CONFIG_MPU is not set 311# CONFIG_MPU is not set
312 312
313# 313#
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig
index 0f8697618aa5..6bc2fb1b2a70 100644
--- a/arch/blackfin/configs/BF548-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF548-EZKIT_defconfig
@@ -361,8 +361,8 @@ CONFIG_BFIN_ICACHE=y
361CONFIG_BFIN_DCACHE=y 361CONFIG_BFIN_DCACHE=y
362# CONFIG_BFIN_DCACHE_BANKA is not set 362# CONFIG_BFIN_DCACHE_BANKA is not set
363# CONFIG_BFIN_ICACHE_LOCK is not set 363# CONFIG_BFIN_ICACHE_LOCK is not set
364# CONFIG_BFIN_WB is not set 364CONFIG_BFIN_WB=y
365CONFIG_BFIN_WT=y 365# CONFIG_BFIN_WT is not set
366# CONFIG_BFIN_L2_CACHEABLE is not set 366# CONFIG_BFIN_L2_CACHEABLE is not set
367# CONFIG_MPU is not set 367# CONFIG_MPU is not set
368 368
@@ -680,7 +680,7 @@ CONFIG_SCSI=y
680CONFIG_SCSI_DMA=y 680CONFIG_SCSI_DMA=y
681# CONFIG_SCSI_TGT is not set 681# CONFIG_SCSI_TGT is not set
682# CONFIG_SCSI_NETLINK is not set 682# CONFIG_SCSI_NETLINK is not set
683CONFIG_SCSI_PROC_FS=y 683# CONFIG_SCSI_PROC_FS is not set
684 684
685# 685#
686# SCSI support type (disk, tape, CD-ROM) 686# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig
index 042c7adfccfa..69714fb3e608 100644
--- a/arch/blackfin/configs/BF561-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF561-EZKIT_defconfig
@@ -329,8 +329,8 @@ CONFIG_BFIN_ICACHE=y
329CONFIG_BFIN_DCACHE=y 329CONFIG_BFIN_DCACHE=y
330# CONFIG_BFIN_DCACHE_BANKA is not set 330# CONFIG_BFIN_DCACHE_BANKA is not set
331# CONFIG_BFIN_ICACHE_LOCK is not set 331# CONFIG_BFIN_ICACHE_LOCK is not set
332# CONFIG_BFIN_WB is not set 332CONFIG_BFIN_WB=y
333CONFIG_BFIN_WT=y 333# CONFIG_BFIN_WT is not set
334# CONFIG_BFIN_L2_CACHEABLE is not set 334# CONFIG_BFIN_L2_CACHEABLE is not set
335# CONFIG_MPU is not set 335# CONFIG_MPU is not set
336 336
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig
index 3a20e281d23c..017c6ea071b5 100644
--- a/arch/blackfin/configs/BlackStamp_defconfig
+++ b/arch/blackfin/configs/BlackStamp_defconfig
@@ -288,8 +288,8 @@ CONFIG_BFIN_ICACHE=y
288CONFIG_BFIN_DCACHE=y 288CONFIG_BFIN_DCACHE=y
289# CONFIG_BFIN_DCACHE_BANKA is not set 289# CONFIG_BFIN_DCACHE_BANKA is not set
290# CONFIG_BFIN_ICACHE_LOCK is not set 290# CONFIG_BFIN_ICACHE_LOCK is not set
291# CONFIG_BFIN_WB is not set 291CONFIG_BFIN_WB=y
292CONFIG_BFIN_WT=y 292# CONFIG_BFIN_WT is not set
293# CONFIG_MPU is not set 293# CONFIG_MPU is not set
294 294
295# 295#
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig
index 865ed85a5760..d880ef786770 100644
--- a/arch/blackfin/configs/CM-BF527_defconfig
+++ b/arch/blackfin/configs/CM-BF527_defconfig
@@ -332,8 +332,8 @@ CONFIG_BFIN_ICACHE=y
332CONFIG_BFIN_DCACHE=y 332CONFIG_BFIN_DCACHE=y
333# CONFIG_BFIN_DCACHE_BANKA is not set 333# CONFIG_BFIN_DCACHE_BANKA is not set
334# CONFIG_BFIN_ICACHE_LOCK is not set 334# CONFIG_BFIN_ICACHE_LOCK is not set
335# CONFIG_BFIN_WB is not set 335CONFIG_BFIN_WB=y
336CONFIG_BFIN_WT=y 336# CONFIG_BFIN_WT is not set
337# CONFIG_MPU is not set 337# CONFIG_MPU is not set
338 338
339# 339#
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig
index efe9741b1f14..f410430b4e3d 100644
--- a/arch/blackfin/configs/CM-BF548_defconfig
+++ b/arch/blackfin/configs/CM-BF548_defconfig
@@ -336,8 +336,8 @@ CONFIG_BFIN_ICACHE=y
336CONFIG_BFIN_DCACHE=y 336CONFIG_BFIN_DCACHE=y
337# CONFIG_BFIN_DCACHE_BANKA is not set 337# CONFIG_BFIN_DCACHE_BANKA is not set
338# CONFIG_BFIN_ICACHE_LOCK is not set 338# CONFIG_BFIN_ICACHE_LOCK is not set
339# CONFIG_BFIN_WB is not set 339CONFIG_BFIN_WB=y
340CONFIG_BFIN_WT=y 340# CONFIG_BFIN_WT is not set
341CONFIG_L1_MAX_PIECE=16 341CONFIG_L1_MAX_PIECE=16
342# CONFIG_MPU is not set 342# CONFIG_MPU is not set
343 343
@@ -595,7 +595,7 @@ CONFIG_SCSI=y
595CONFIG_SCSI_DMA=y 595CONFIG_SCSI_DMA=y
596# CONFIG_SCSI_TGT is not set 596# CONFIG_SCSI_TGT is not set
597# CONFIG_SCSI_NETLINK is not set 597# CONFIG_SCSI_NETLINK is not set
598CONFIG_SCSI_PROC_FS=y 598# CONFIG_SCSI_PROC_FS is not set
599 599
600# 600#
601# SCSI support type (disk, tape, CD-ROM) 601# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig
index eae83b5de92f..7db93874c987 100644
--- a/arch/blackfin/configs/IP0X_defconfig
+++ b/arch/blackfin/configs/IP0X_defconfig
@@ -612,7 +612,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
612CONFIG_SCSI=y 612CONFIG_SCSI=y
613# CONFIG_SCSI_TGT is not set 613# CONFIG_SCSI_TGT is not set
614# CONFIG_SCSI_NETLINK is not set 614# CONFIG_SCSI_NETLINK is not set
615CONFIG_SCSI_PROC_FS=y 615# CONFIG_SCSI_PROC_FS is not set
616 616
617# 617#
618# SCSI support type (disk, tape, CD-ROM) 618# SCSI support type (disk, tape, CD-ROM)
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig
index fa580affc9d6..a46529c6ade3 100644
--- a/arch/blackfin/configs/SRV1_defconfig
+++ b/arch/blackfin/configs/SRV1_defconfig
@@ -282,8 +282,8 @@ CONFIG_BFIN_ICACHE=y
282CONFIG_BFIN_DCACHE=y 282CONFIG_BFIN_DCACHE=y
283# CONFIG_BFIN_DCACHE_BANKA is not set 283# CONFIG_BFIN_DCACHE_BANKA is not set
284# CONFIG_BFIN_ICACHE_LOCK is not set 284# CONFIG_BFIN_ICACHE_LOCK is not set
285# CONFIG_BFIN_WB is not set 285CONFIG_BFIN_WB=y
286CONFIG_BFIN_WT=y 286# CONFIG_BFIN_WT is not set
287CONFIG_L1_MAX_PIECE=16 287CONFIG_L1_MAX_PIECE=16
288 288
289# 289#
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild
index 606ecfdcc962..09c31418cc08 100644
--- a/arch/blackfin/include/asm/Kbuild
+++ b/arch/blackfin/include/asm/Kbuild
@@ -1,3 +1,4 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2 2
3unifdef-y += bfin_sport.h
3unifdef-y += fixed_code.h 4unifdef-y += fixed_code.h
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index fe88a2c19213..65a651db5b07 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -1,30 +1,9 @@
1/* 1/*
2 * File: include/asm-blackfin/bfin_sport.h 2 * bfin_sport.h - userspace header for bfin sport driver
3 * Based on:
4 * Author: Roy Huang (roy.huang@analog.com)
5 * 3 *
6 * Created: Thu Aug. 24 2006 4 * Copyright 2004-2008 Analog Devices Inc.
7 * Description:
8 * 5 *
9 * Modified: 6 * Licensed under the GPL-2 or later.
10 * Copyright 2004-2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 7 */
29 8
30#ifndef __BFIN_SPORT_H__ 9#ifndef __BFIN_SPORT_H__
@@ -42,11 +21,10 @@
42#define NORM_FORMAT 0x0 21#define NORM_FORMAT 0x0
43#define ALAW_FORMAT 0x2 22#define ALAW_FORMAT 0x2
44#define ULAW_FORMAT 0x3 23#define ULAW_FORMAT 0x3
45struct sport_register;
46 24
47/* Function driver which use sport must initialize the structure */ 25/* Function driver which use sport must initialize the structure */
48struct sport_config { 26struct sport_config {
49 /*TDM (multichannels), I2S or other mode */ 27 /* TDM (multichannels), I2S or other mode */
50 unsigned int mode:3; 28 unsigned int mode:3;
51 29
52 /* if TDM mode is selected, channels must be set */ 30 /* if TDM mode is selected, channels must be set */
@@ -72,12 +50,18 @@ struct sport_config {
72 int serial_clk; 50 int serial_clk;
73 int fsync_clk; 51 int fsync_clk;
74 52
75 unsigned int data_format:2; /*Normal, u-law or a-law */ 53 unsigned int data_format:2; /* Normal, u-law or a-law */
76 54
77 int word_len; /* How length of the word in bits, 3-32 bits */ 55 int word_len; /* How length of the word in bits, 3-32 bits */
78 int dma_enabled; 56 int dma_enabled;
79}; 57};
80 58
59/* Userspace interface */
60#define SPORT_IOC_MAGIC 'P'
61#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
62
63#ifdef __KERNEL__
64
81struct sport_register { 65struct sport_register {
82 unsigned short tcr1; 66 unsigned short tcr1;
83 unsigned short reserved0; 67 unsigned short reserved0;
@@ -117,9 +101,6 @@ struct sport_register {
117 unsigned long mrcs3; 101 unsigned long mrcs3;
118}; 102};
119 103
120#define SPORT_IOC_MAGIC 'P'
121#define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config)
122
123struct sport_dev { 104struct sport_dev {
124 struct cdev cdev; /* Char device structure */ 105 struct cdev cdev; /* Char device structure */
125 106
@@ -149,6 +130,8 @@ struct sport_dev {
149 struct sport_config config; 130 struct sport_config config;
150}; 131};
151 132
133#endif
134
152#define SPORT_TCR1 0 135#define SPORT_TCR1 0
153#define SPORT_TCR2 1 136#define SPORT_TCR2 1
154#define SPORT_TCLKDIV 2 137#define SPORT_TCLKDIV 2
@@ -169,4 +152,4 @@ struct sport_dev {
169#define SPORT_MRCS2 22 152#define SPORT_MRCS2 22
170#define SPORT_MRCS3 23 153#define SPORT_MRCS3 23
171 154
172#endif /*__BFIN_SPORT_H__*/ 155#endif
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h
index 76f53d8b9a0d..343b56361ec9 100644
--- a/arch/blackfin/include/asm/ipipe.h
+++ b/arch/blackfin/include/asm/ipipe.h
@@ -35,9 +35,9 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/traps.h> 36#include <asm/traps.h>
37 37
38#define IPIPE_ARCH_STRING "1.8-00" 38#define IPIPE_ARCH_STRING "1.9-00"
39#define IPIPE_MAJOR_NUMBER 1 39#define IPIPE_MAJOR_NUMBER 1
40#define IPIPE_MINOR_NUMBER 8 40#define IPIPE_MINOR_NUMBER 9
41#define IPIPE_PATCH_NUMBER 0 41#define IPIPE_PATCH_NUMBER 0
42 42
43#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -83,9 +83,9 @@ struct ipipe_sysinfo {
83 "%2 = CYCLES2\n" \ 83 "%2 = CYCLES2\n" \
84 "CC = %2 == %0\n" \ 84 "CC = %2 == %0\n" \
85 "if ! CC jump 1b\n" \ 85 "if ! CC jump 1b\n" \
86 : "=r" (((unsigned long *)&t)[1]), \ 86 : "=d,a" (((unsigned long *)&t)[1]), \
87 "=r" (((unsigned long *)&t)[0]), \ 87 "=d,a" (((unsigned long *)&t)[0]), \
88 "=r" (__cy2) \ 88 "=d,a" (__cy2) \
89 : /*no input*/ : "CC"); \ 89 : /*no input*/ : "CC"); \
90 t; \ 90 t; \
91 }) 91 })
@@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd,
118 118
119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) 119#define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq))
120 120
121#define __ipipe_lock_root() \ 121static inline int __ipipe_check_tickdev(const char *devname)
122 set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 122{
123 return 1;
124}
123 125
124#define __ipipe_unlock_root() \ 126static inline void __ipipe_lock_root(void)
125 clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) 127{
128 set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
129}
130
131static inline void __ipipe_unlock_root(void)
132{
133 clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status));
134}
126 135
127void __ipipe_enable_pipeline(void); 136void __ipipe_enable_pipeline(void);
128 137
129#define __ipipe_hook_critical_ipi(ipd) do { } while (0) 138#define __ipipe_hook_critical_ipi(ipd) do { } while (0)
130 139
131#define __ipipe_sync_pipeline(syncmask) \ 140#define __ipipe_sync_pipeline ___ipipe_sync_pipeline
132 do { \ 141void ___ipipe_sync_pipeline(unsigned long syncmask);
133 struct ipipe_domain *ipd = ipipe_current_domain; \
134 if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \
135 __ipipe_sync_stage(syncmask); \
136 } while (0)
137 142
138void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); 143void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs);
139 144
140int __ipipe_get_irq_priority(unsigned irq); 145int __ipipe_get_irq_priority(unsigned irq);
141 146
142int __ipipe_get_irqthread_priority(unsigned irq);
143
144void __ipipe_stall_root_raw(void); 147void __ipipe_stall_root_raw(void);
145 148
146void __ipipe_unstall_root_raw(void); 149void __ipipe_unstall_root_raw(void);
147 150
148void __ipipe_serial_debug(const char *fmt, ...); 151void __ipipe_serial_debug(const char *fmt, ...);
149 152
153asmlinkage void __ipipe_call_irqtail(unsigned long addr);
154
150DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 155DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
151 156
152extern unsigned long __ipipe_core_clock; 157extern unsigned long __ipipe_core_clock;
@@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul)
162 167
163#define __ipipe_run_irqtail() /* Must be a macro */ \ 168#define __ipipe_run_irqtail() /* Must be a macro */ \
164 do { \ 169 do { \
165 asmlinkage void __ipipe_call_irqtail(void); \
166 unsigned long __pending; \ 170 unsigned long __pending; \
167 CSYNC(); \ 171 CSYNC(); \
168 __pending = bfin_read_IPEND(); \ 172 __pending = bfin_read_IPEND(); \
169 if (__pending & 0x8000) { \ 173 if (__pending & 0x8000) { \
170 __pending &= ~0x8010; \ 174 __pending &= ~0x8010; \
171 if (__pending && (__pending & (__pending - 1)) == 0) \ 175 if (__pending && (__pending & (__pending - 1)) == 0) \
172 __ipipe_call_irqtail(); \ 176 __ipipe_call_irqtail(__ipipe_irq_tail_hook); \
173 } \ 177 } \
174 } while (0) 178 } while (0)
175 179
176#define __ipipe_run_isr(ipd, irq) \ 180#define __ipipe_run_isr(ipd, irq) \
177 do { \ 181 do { \
178 if (ipd == ipipe_root_domain) { \ 182 if (ipd == ipipe_root_domain) { \
179 /* \ 183 local_irq_enable_hw(); \
180 * Note: the I-pipe implements a threaded interrupt model on \ 184 if (ipipe_virtual_irq_p(irq)) \
181 * this arch for Linux external IRQs. The interrupt handler we \
182 * call here only wakes up the associated IRQ thread. \
183 */ \
184 if (ipipe_virtual_irq_p(irq)) { \
185 /* No irqtail here; virtual interrupts have no effect \
186 on IPEND so there is no need for processing \
187 deferral. */ \
188 local_irq_enable_nohead(ipd); \
189 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ 185 ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
190 local_irq_disable_nohead(ipd); \ 186 else \
191 } else \
192 /* \
193 * No need to run the irqtail here either; \
194 * we can't be preempted by hw IRQs, so \
195 * non-Linux IRQs cannot stack over the short \
196 * thread wakeup code. Which in turn means \
197 * that no irqtail condition could be pending \
198 * for domains above Linux in the pipeline. \
199 */ \
200 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ 187 ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \
188 local_irq_disable_hw(); \
201 } else { \ 189 } else { \
202 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ 190 __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \
203 local_irq_enable_nohead(ipd); \ 191 local_irq_enable_nohead(ipd); \
@@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void);
217 205
218int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); 206int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
219 207
220#define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) 208#ifdef CONFIG_GENERIC_CLOCKEVENTS
221#define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) 209#define IRQ_SYSTMR IRQ_CORETMR
222 210#define IRQ_PRIOTMR IRQ_CORETMR
211#else
223#define IRQ_SYSTMR IRQ_TIMER0 212#define IRQ_SYSTMR IRQ_TIMER0
224#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 213#define IRQ_PRIOTMR CONFIG_IRQ_TIMER0
214#endif
225 215
226#if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) 216#ifdef CONFIG_BF561
227#define PRIO_GPIODEMUX(irq) CONFIG_PFA
228#elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537)
229#define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA
230#elif defined(CONFIG_BF52x)
231#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \
232 (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \
233 (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \
234 -1)
235#elif defined(CONFIG_BF561)
236#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \
237 (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \
238 (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \
239 -1)
240#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) 217#define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val)
241#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) 218#define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val)
242#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) 219#define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val)
243#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() 220#define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS()
244#elif defined(CONFIG_BF54x) 221#elif defined(CONFIG_BF54x)
245#define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \
246 (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \
247 (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \
248 (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \
249 -1)
250#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) 222#define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val)
251#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) 223#define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val)
252#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) 224#define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val)
253#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) 225#define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val)
254#else
255# error "no PRIO_GPIODEMUX() for this part"
256#endif 226#endif
257 227
258#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) 228#define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0)
@@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc);
275 245
276#endif /* !CONFIG_IPIPE */ 246#endif /* !CONFIG_IPIPE */
277 247
248#define ipipe_update_tick_evtdev(evtdev) do { } while (0)
249
278#endif /* !__ASM_BLACKFIN_IPIPE_H */ 250#endif /* !__ASM_BLACKFIN_IPIPE_H */
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h
index cb1025aeabcf..3e8acbd1a3be 100644
--- a/arch/blackfin/include/asm/ipipe_base.h
+++ b/arch/blackfin/include/asm/ipipe_base.h
@@ -1,5 +1,5 @@
1/* -*- linux-c -*- 1/* -*- linux-c -*-
2 * include/asm-blackfin/_baseipipe.h 2 * include/asm-blackfin/ipipe_base.h
3 * 3 *
4 * Copyright (C) 2007 Philippe Gerum. 4 * Copyright (C) 2007 Philippe Gerum.
5 * 5 *
@@ -27,8 +27,9 @@
27#define IPIPE_NR_XIRQS NR_IRQS 27#define IPIPE_NR_XIRQS NR_IRQS
28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ 28#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
29 29
30/* Blackfin-specific, global domain flags */ 30/* Blackfin-specific, per-cpu pipeline status */
31#define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ 31#define IPIPE_SYNCDEFER_FLAG 15
32#define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK)
32 33
33 /* Blackfin traps -- i.e. exception vector numbers */ 34 /* Blackfin traps -- i.e. exception vector numbers */
34#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ 35#define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */
@@ -48,11 +49,6 @@
48 49
49#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
50 51
51#include <linux/bitops.h>
52
53extern int test_bit(int nr, const void *addr);
54
55
56extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ 52extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */
57 53
58static inline void __ipipe_stall_root(void) 54static inline void __ipipe_stall_root(void)
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 3d977909ce7d..7645e85a5f6f 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags);
61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) 61#define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags))
62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) 62#define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x)
63 63
64#define local_save_flags(x) \ 64#define local_save_flags(x) \
65 do { \ 65 do { \
66 (x) = __ipipe_test_root() ? \ 66 (x) = __ipipe_test_root() ? \
67 __all_masked_irq_flags : bfin_irq_flags; \ 67 __all_masked_irq_flags : bfin_irq_flags; \
68 barrier(); \
68 } while (0) 69 } while (0)
69 70
70#define local_irq_save(x) \ 71#define local_irq_save(x) \
71 do { \ 72 do { \
72 (x) = __ipipe_test_and_stall_root(); \ 73 (x) = __ipipe_test_and_stall_root() ? \
74 __all_masked_irq_flags : bfin_irq_flags; \
75 barrier(); \
76 } while (0)
77
78static inline void local_irq_restore(unsigned long x)
79{
80 barrier();
81 __ipipe_restore_root(x == __all_masked_irq_flags);
82}
83
84#define local_irq_disable() \
85 do { \
86 __ipipe_stall_root(); \
87 barrier(); \
73 } while (0) 88 } while (0)
74 89
75#define local_irq_restore(x) __ipipe_restore_root(x) 90static inline void local_irq_enable(void)
76#define local_irq_disable() __ipipe_stall_root() 91{
77#define local_irq_enable() __ipipe_unstall_root() 92 barrier();
93 __ipipe_unstall_root();
94}
95
78#define irqs_disabled() __ipipe_test_root() 96#define irqs_disabled() __ipipe_test_root()
79 97
80#define local_save_flags_hw(x) \ 98#define local_save_flags_hw(x) \
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h
index e721ce55956c..2920087516f2 100644
--- a/arch/blackfin/include/asm/thread_info.h
+++ b/arch/blackfin/include/asm/thread_info.h
@@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void)
122#define TIF_MEMDIE 4 122#define TIF_MEMDIE 4
123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ 123#define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */
124#define TIF_FREEZE 6 /* is freezing for suspend */ 124#define TIF_FREEZE 6 /* is freezing for suspend */
125#define TIF_IRQ_SYNC 7 /* sync pipeline stage */
125 126
126/* as above, but as bit values */ 127/* as above, but as bit values */
127#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 128#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
@@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
130#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 131#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
131#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) 132#define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK)
132#define _TIF_FREEZE (1<<TIF_FREEZE) 133#define _TIF_FREEZE (1<<TIF_FREEZE)
134#define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC)
133 135
134#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ 136#define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */
135 137
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index 4a92a86824b7..fd4d4328a0f2 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -15,13 +15,15 @@ else
15 obj-y += time.o 15 obj-y += time.o
16endif 16endif
17 17
18CFLAGS_kgdb_test.o := -mlong-calls -O0
19
20obj-$(CONFIG_IPIPE) += ipipe.o 18obj-$(CONFIG_IPIPE) += ipipe.o
21obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o 19obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o
22obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o 20obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o
23obj-$(CONFIG_CPLB_INFO) += cplbinfo.o 21obj-$(CONFIG_CPLB_INFO) += cplbinfo.o
24obj-$(CONFIG_MODULES) += module.o 22obj-$(CONFIG_MODULES) += module.o
25obj-$(CONFIG_KGDB) += kgdb.o 23obj-$(CONFIG_KGDB) += kgdb.o
26obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o 24obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o
27obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 25obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
26
27# the kgdb test puts code into L2 and without linker
28# relaxation, we need to force long calls to/from it
29CFLAGS_kgdb_test.o := -mlong-calls -O0
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 0e28f7595733..d6c067782e63 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -53,9 +53,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
53 53
54 i_d = i_i = 0; 54 i_d = i_i = 0;
55 55
56#ifdef CONFIG_DEBUG_HUNT_FOR_ZERO
56 /* Set up the zero page. */ 57 /* Set up the zero page. */
57 d_tbl[i_d].addr = 0; 58 d_tbl[i_d].addr = 0;
58 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; 59 d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
60 i_tbl[i_i].addr = 0;
61 i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
62#endif
59 63
60 /* Cover kernel memory with 4M pages. */ 64 /* Cover kernel memory with 4M pages. */
61 addr = 0; 65 addr = 0;
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index 339be5a3ae6a..a5de8d45424c 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -35,14 +35,8 @@
35#include <asm/atomic.h> 35#include <asm/atomic.h>
36#include <asm/io.h> 36#include <asm/io.h>
37 37
38static int create_irq_threads;
39
40DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); 38DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
41 39
42static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask);
43
44static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count);
45
46asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); 40asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
47 41
48static void __ipipe_no_irqtail(void); 42static void __ipipe_no_irqtail(void);
@@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void)
93 */ 87 */
94void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) 88void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
95{ 89{
90 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
96 struct ipipe_domain *this_domain, *next_domain; 91 struct ipipe_domain *this_domain, *next_domain;
97 struct list_head *head, *pos; 92 struct list_head *head, *pos;
98 int m_ack, s = -1; 93 int m_ack, s = -1;
@@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
104 * interrupt. 99 * interrupt.
105 */ 100 */
106 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); 101 m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR);
107
108 this_domain = ipipe_current_domain; 102 this_domain = ipipe_current_domain;
109 103
110 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) 104 if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control)))
@@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
114 next_domain = list_entry(head, struct ipipe_domain, p_link); 108 next_domain = list_entry(head, struct ipipe_domain, p_link);
115 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { 109 if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
116 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) 110 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
117 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 111 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
118 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 112 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
119 s = __test_and_set_bit(IPIPE_STALL_FLAG, 113 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
120 &ipipe_root_cpudom_var(status));
121 __ipipe_dispatch_wired(next_domain, irq); 114 __ipipe_dispatch_wired(next_domain, irq);
122 goto finalize; 115 goto out;
123 return;
124 } 116 }
125 } 117 }
126 118
127 /* Ack the interrupt. */ 119 /* Ack the interrupt. */
128 120
129 pos = head; 121 pos = head;
130
131 while (pos != &__ipipe_pipeline) { 122 while (pos != &__ipipe_pipeline) {
132 next_domain = list_entry(pos, struct ipipe_domain, p_link); 123 next_domain = list_entry(pos, struct ipipe_domain, p_link);
133 /*
134 * For each domain handling the incoming IRQ, mark it
135 * as pending in its log.
136 */
137 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { 124 if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
138 /*
139 * Domains that handle this IRQ are polled for
140 * acknowledging it by decreasing priority
141 * order. The interrupt must be made pending
142 * _first_ in the domain's status flags before
143 * the PIC is unlocked.
144 */
145 __ipipe_set_irq_pending(next_domain, irq); 125 __ipipe_set_irq_pending(next_domain, irq);
146
147 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { 126 if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) {
148 next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); 127 next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq));
149 m_ack = 1; 128 m_ack = 1;
150 } 129 }
151 } 130 }
152
153 /*
154 * If the domain does not want the IRQ to be passed
155 * down the interrupt pipe, exit the loop now.
156 */
157 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) 131 if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
158 break; 132 break;
159
160 pos = next_domain->p_link.next; 133 pos = next_domain->p_link.next;
161 } 134 }
162 135
@@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs)
166 * immediately to the current domain if the interrupt has been 139 * immediately to the current domain if the interrupt has been
167 * marked as 'sticky'. This search does not go beyond the 140 * marked as 'sticky'. This search does not go beyond the
168 * current domain in the pipeline. We also enforce the 141 * current domain in the pipeline. We also enforce the
169 * additional root stage lock (blackfin-specific). */ 142 * additional root stage lock (blackfin-specific).
143 */
144 if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status))
145 s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status);
170 146
171 if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) 147 /*
172 s = __test_and_set_bit(IPIPE_STALL_FLAG, 148 * If the interrupt preempted the head domain, then do not
173 &ipipe_root_cpudom_var(status)); 149 * even try to walk the pipeline, unless an interrupt is
174finalize: 150 * pending for it.
151 */
152 if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) &&
153 ipipe_head_cpudom_var(irqpend_himask) == 0)
154 goto out;
175 155
176 __ipipe_walk_pipeline(head); 156 __ipipe_walk_pipeline(head);
177 157out:
178 if (!s) 158 if (!s)
179 __clear_bit(IPIPE_STALL_FLAG, 159 __clear_bit(IPIPE_STALL_FLAG, &p->status);
180 &ipipe_root_cpudom_var(status));
181} 160}
182 161
183int __ipipe_check_root(void) 162int __ipipe_check_root(void)
@@ -187,7 +166,7 @@ int __ipipe_check_root(void)
187 166
188void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 167void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
189{ 168{
190 struct irq_desc *desc = irq_desc + irq; 169 struct irq_desc *desc = irq_to_desc(irq);
191 int prio = desc->ic_prio; 170 int prio = desc->ic_prio;
192 171
193 desc->depth = 0; 172 desc->depth = 0;
@@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc);
199 178
200void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) 179void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq)
201{ 180{
202 struct irq_desc *desc = irq_desc + irq; 181 struct irq_desc *desc = irq_to_desc(irq);
203 int prio = desc->ic_prio; 182 int prio = desc->ic_prio;
204 183
205 if (ipd != &ipipe_root && 184 if (ipd != &ipipe_root &&
@@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs)
236{ 215{
237 unsigned long flags; 216 unsigned long flags;
238 217
239 /* We need to run the IRQ tail hook whenever we don't 218 /*
219 * We need to run the IRQ tail hook whenever we don't
240 * propagate a syscall to higher domains, because we know that 220 * propagate a syscall to higher domains, because we know that
241 * important operations might be pending there (e.g. Xenomai 221 * important operations might be pending there (e.g. Xenomai
242 * deferred rescheduling). */ 222 * deferred rescheduling).
223 */
243 224
244 if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { 225 if (regs->orig_p0 < NR_syscalls) {
245 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; 226 void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook;
246 hook(); 227 hook();
247 return 0; 228 if ((current->flags & PF_EVNOTIFY) == 0)
229 return 0;
248 } 230 }
249 231
250 /* 232 /*
@@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq)
312{ 294{
313 unsigned long flags; 295 unsigned long flags;
314 296
297#ifdef CONFIG_IPIPE_DEBUG
315 if (irq >= IPIPE_NR_IRQS || 298 if (irq >= IPIPE_NR_IRQS ||
316 (ipipe_virtual_irq_p(irq) 299 (ipipe_virtual_irq_p(irq)
317 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) 300 && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
318 return -EINVAL; 301 return -EINVAL;
302#endif
319 303
320 local_irq_save_hw(flags); 304 local_irq_save_hw(flags);
321
322 __ipipe_handle_irq(irq, NULL); 305 __ipipe_handle_irq(irq, NULL);
323
324 local_irq_restore_hw(flags); 306 local_irq_restore_hw(flags);
325 307
326 return 1; 308 return 1;
327} 309}
328 310
329/* Move Linux IRQ to threads. */ 311asmlinkage void __ipipe_sync_root(void)
330
331static int do_irqd(void *__desc)
332{ 312{
333 struct irq_desc *desc = __desc; 313 unsigned long flags;
334 unsigned irq = desc - irq_desc;
335 int thrprio = desc->thr_prio;
336 int thrmask = 1 << thrprio;
337 int cpu = smp_processor_id();
338 cpumask_t cpumask;
339
340 sigfillset(&current->blocked);
341 current->flags |= PF_NOFREEZE;
342 cpumask = cpumask_of_cpu(cpu);
343 set_cpus_allowed(current, cpumask);
344 ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio);
345
346 while (!kthread_should_stop()) {
347 local_irq_disable();
348 if (!(desc->status & IRQ_SCHEDULED)) {
349 set_current_state(TASK_INTERRUPTIBLE);
350resched:
351 local_irq_enable();
352 schedule();
353 local_irq_disable();
354 }
355 __set_current_state(TASK_RUNNING);
356 /*
357 * If higher priority interrupt servers are ready to
358 * run, reschedule immediately. We need this for the
359 * GPIO demux IRQ handler to unmask the interrupt line
360 * _last_, after all GPIO IRQs have run.
361 */
362 if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1)))
363 goto resched;
364 if (--per_cpu(pending_irq_count[thrprio], cpu) == 0)
365 per_cpu(pending_irqthread_mask, cpu) &= ~thrmask;
366 desc->status &= ~IRQ_SCHEDULED;
367 desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs));
368 local_irq_enable();
369 }
370 __set_current_state(TASK_RUNNING);
371 return 0;
372}
373 314
374static void kick_irqd(unsigned irq, void *cookie) 315 BUG_ON(irqs_disabled());
375{
376 struct irq_desc *desc = irq_desc + irq;
377 int thrprio = desc->thr_prio;
378 int thrmask = 1 << thrprio;
379 int cpu = smp_processor_id();
380
381 if (!(desc->status & IRQ_SCHEDULED)) {
382 desc->status |= IRQ_SCHEDULED;
383 per_cpu(pending_irqthread_mask, cpu) |= thrmask;
384 ++per_cpu(pending_irq_count[thrprio], cpu);
385 wake_up_process(desc->thread);
386 }
387}
388 316
389int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) 317 local_irq_save_hw(flags);
390{
391 if (desc->thread || !create_irq_threads)
392 return 0;
393
394 desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq);
395 if (desc->thread == NULL) {
396 printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq);
397 return -ENOMEM;
398 }
399 318
400 wake_up_process(desc->thread); 319 clear_thread_flag(TIF_IRQ_SYNC);
401 320
402 desc->thr_handler = ipipe_root_domain->irqs[irq].handler; 321 if (ipipe_root_cpudom_var(irqpend_himask) != 0)
403 ipipe_root_domain->irqs[irq].handler = &kick_irqd; 322 __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
404 323
405 return 0; 324 local_irq_restore_hw(flags);
406} 325}
407 326
408void __init ipipe_init_irq_threads(void) 327void ___ipipe_sync_pipeline(unsigned long syncmask)
409{ 328{
410 unsigned irq; 329 struct ipipe_domain *ipd = ipipe_current_domain;
411 struct irq_desc *desc;
412
413 create_irq_threads = 1;
414 330
415 for (irq = 0; irq < NR_IRQS; irq++) { 331 if (ipd == ipipe_root_domain) {
416 desc = irq_desc + irq; 332 if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)))
417 if (desc->action != NULL || 333 return;
418 (desc->status & IRQ_NOREQUEST) != 0)
419 ipipe_start_irq_thread(irq, desc);
420 } 334 }
335
336 __ipipe_sync_stage(syncmask);
421} 337}
422 338
423EXPORT_SYMBOL(show_stack); 339EXPORT_SYMBOL(show_stack);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 75724eee6494..7fd126564846 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -144,11 +144,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
144#endif 144#endif
145 generic_handle_irq(irq); 145 generic_handle_irq(irq);
146 146
147#ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ 147#ifndef CONFIG_IPIPE
148 /* If we're the only interrupt running (ignoring IRQ15 which is for 148 /*
149 syscalls), lower our priority to IRQ14 so that softirqs run at 149 * If we're the only interrupt running (ignoring IRQ15 which
150 that level. If there's another, lower-level interrupt, irq_exit 150 * is for syscalls), lower our priority to IRQ14 so that
151 will defer softirqs to that. */ 151 * softirqs run at that level. If there's another,
152 * lower-level interrupt, irq_exit will defer softirqs to
153 * that. If the interrupt pipeline is enabled, we are already
154 * running at IRQ14 priority, so we don't need this code.
155 */
152 CSYNC(); 156 CSYNC();
153 pending = bfin_read_IPEND() & ~0x8000; 157 pending = bfin_read_IPEND() & ~0x8000;
154 other_ints = pending & (pending - 1); 158 other_ints = pending & (pending - 1);
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c
index 3dba9c17304a..dbcf3e45cb0b 100644
--- a/arch/blackfin/kernel/kgdb_test.c
+++ b/arch/blackfin/kernel/kgdb_test.c
@@ -20,6 +20,7 @@
20static char cmdline[256]; 20static char cmdline[256];
21static unsigned long len; 21static unsigned long len;
22 22
23#ifndef CONFIG_SMP
23static int num1 __attribute__((l1_data)); 24static int num1 __attribute__((l1_data));
24 25
25void kgdb_l1_test(void) __attribute__((l1_text)); 26void kgdb_l1_test(void) __attribute__((l1_text));
@@ -32,6 +33,8 @@ void kgdb_l1_test(void)
32 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); 33 printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1);
33 return ; 34 return ;
34} 35}
36#endif
37
35#if L2_LENGTH 38#if L2_LENGTH
36 39
37static int num2 __attribute__((l2)); 40static int num2 __attribute__((l2));
@@ -59,10 +62,12 @@ int kgdb_test(char *name, int len, int count, int z)
59static int test_proc_output(char *buf) 62static int test_proc_output(char *buf)
60{ 63{
61 kgdb_test("hello world!", 12, 0x55, 0x10); 64 kgdb_test("hello world!", 12, 0x55, 0x10);
65#ifndef CONFIG_SMP
62 kgdb_l1_test(); 66 kgdb_l1_test();
63 #if L2_LENGTH 67#endif
68#if L2_LENGTH
64 kgdb_l2_test(); 69 kgdb_l2_test();
65 #endif 70#endif
66 71
67 return 0; 72 return 0;
68} 73}
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c
index 594e325b40e4..d76618db50df 100644
--- a/arch/blackfin/kernel/ptrace.c
+++ b/arch/blackfin/kernel/ptrace.c
@@ -45,6 +45,7 @@
45#include <asm/asm-offsets.h> 45#include <asm/asm-offsets.h>
46#include <asm/dma.h> 46#include <asm/dma.h>
47#include <asm/fixed_code.h> 47#include <asm/fixed_code.h>
48#include <asm/cacheflush.h>
48#include <asm/mem_map.h> 49#include <asm/mem_map.h>
49 50
50#define TEXT_OFFSET 0 51#define TEXT_OFFSET 0
@@ -240,7 +241,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
240 241
241 } else if (addr >= FIXED_CODE_START 242 } else if (addr >= FIXED_CODE_START
242 && addr + sizeof(tmp) <= FIXED_CODE_END) { 243 && addr + sizeof(tmp) <= FIXED_CODE_END) {
243 memcpy(&tmp, (const void *)(addr), sizeof(tmp)); 244 copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp));
244 copied = sizeof(tmp); 245 copied = sizeof(tmp);
245 246
246 } else 247 } else
@@ -320,7 +321,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
320 321
321 } else if (addr >= FIXED_CODE_START 322 } else if (addr >= FIXED_CODE_START
322 && addr + sizeof(data) <= FIXED_CODE_END) { 323 && addr + sizeof(data) <= FIXED_CODE_END) {
323 memcpy((void *)(addr), &data, sizeof(data)); 324 copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data));
324 copied = sizeof(data); 325 copied = sizeof(data);
325 326
326 } else 327 } else
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index e5c116230800..a58687bdee6a 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -889,6 +889,10 @@ void __init setup_arch(char **cmdline_p)
889 CPU, bfin_revid()); 889 CPU, bfin_revid());
890 } 890 }
891 891
892 /* We can't run on BF548-0.1 due to ANOMALY 05000448 */
893 if (bfin_cpuid() == 0x27de && bfin_revid() == 1)
894 panic("You can't run on this processor due to 05000448\n");
895
892 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); 896 printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
893 897
894 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", 898 printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
@@ -1141,12 +1145,12 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1141 icache_size = 0; 1145 icache_size = 0;
1142 1146
1143 seq_printf(m, "cache size\t: %d KB(L1 icache) " 1147 seq_printf(m, "cache size\t: %d KB(L1 icache) "
1144 "%d KB(L1 dcache-%s) %d KB(L2 cache)\n", 1148 "%d KB(L1 dcache%s) %d KB(L2 cache)\n",
1145 icache_size, dcache_size, 1149 icache_size, dcache_size,
1146#if defined CONFIG_BFIN_WB 1150#if defined CONFIG_BFIN_WB
1147 "wb" 1151 "-wb"
1148#elif defined CONFIG_BFIN_WT 1152#elif defined CONFIG_BFIN_WT
1149 "wt" 1153 "-wt"
1150#endif 1154#endif
1151 "", 0); 1155 "", 0);
1152 1156
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c
index 172b4c588467..1bbacfbd4c5d 100644
--- a/arch/blackfin/kernel/time.c
+++ b/arch/blackfin/kernel/time.c
@@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy)
134 134
135 write_seqlock(&xtime_lock); 135 write_seqlock(&xtime_lock);
136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) 136#if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE)
137/* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ 137 /*
138 * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is
139 * enabled.
140 */
138 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { 141 if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) {
139#endif 142#endif
140 do_timer(1); 143 do_timer(1);
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c
index 0e175342112e..41f2eacfef20 100644
--- a/arch/blackfin/mach-bf518/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf518/boards/ezbrd.c
@@ -113,7 +113,6 @@ static struct platform_device bfin_mac_device = {
113 .name = "bfin_mac", 113 .name = "bfin_mac",
114 .dev.platform_data = &bfin_mii_bus, 114 .dev.platform_data = &bfin_mii_bus,
115}; 115};
116#endif
117 116
118#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 117#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
119static struct dsa_platform_data ksz8893m_switch_data = { 118static struct dsa_platform_data ksz8893m_switch_data = {
@@ -132,6 +131,7 @@ static struct platform_device ksz8893m_switch_device = {
132 .dev.platform_data = &ksz8893m_switch_data, 131 .dev.platform_data = &ksz8893m_switch_data,
133}; 132};
134#endif 133#endif
134#endif
135 135
136#if defined(CONFIG_MTD_M25P80) \ 136#if defined(CONFIG_MTD_M25P80) \
137 || defined(CONFIG_MTD_M25P80_MODULE) 137 || defined(CONFIG_MTD_M25P80_MODULE)
@@ -171,6 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
171}; 171};
172#endif 172#endif
173 173
174#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
174#if defined(CONFIG_NET_DSA_KSZ8893M) \ 175#if defined(CONFIG_NET_DSA_KSZ8893M) \
175 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 176 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
176/* SPI SWITCH CHIP */ 177/* SPI SWITCH CHIP */
@@ -179,10 +180,11 @@ static struct bfin5xx_spi_chip spi_switch_info = {
179 .bits_per_word = 8, 180 .bits_per_word = 8,
180}; 181};
181#endif 182#endif
183#endif
182 184
183#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 185#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
184static struct bfin5xx_spi_chip spi_mmc_chip_info = { 186static struct bfin5xx_spi_chip mmc_spi_chip_info = {
185 .enable_dma = 1, 187 .enable_dma = 0,
186 .bits_per_word = 8, 188 .bits_per_word = 8,
187}; 189};
188#endif 190#endif
@@ -259,6 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
259 }, 261 },
260#endif 262#endif
261 263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
262#if defined(CONFIG_NET_DSA_KSZ8893M) \ 265#if defined(CONFIG_NET_DSA_KSZ8893M) \
263 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 266 || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
264 { 267 {
@@ -271,24 +274,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
271 .mode = SPI_MODE_3, 274 .mode = SPI_MODE_3,
272 }, 275 },
273#endif 276#endif
277#endif
274 278
275#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 279#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
276 { 280 {
277 .modalias = "spi_mmc_dummy", 281 .modalias = "mmc_spi",
278 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 282 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
279 .bus_num = 0, 283 .bus_num = 0,
280 .chip_select = 0, 284 .chip_select = 5,
281 .platform_data = NULL, 285 .controller_data = &mmc_spi_chip_info,
282 .controller_data = &spi_mmc_chip_info,
283 .mode = SPI_MODE_3,
284 },
285 {
286 .modalias = "spi_mmc",
287 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
288 .bus_num = 0,
289 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
290 .platform_data = NULL,
291 .controller_data = &spi_mmc_chip_info,
292 .mode = SPI_MODE_3, 286 .mode = SPI_MODE_3,
293 }, 287 },
294#endif 288#endif
@@ -630,11 +624,10 @@ static struct platform_device *stamp_devices[] __initdata = {
630#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 624#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
631 &bfin_mii_bus, 625 &bfin_mii_bus,
632 &bfin_mac_device, 626 &bfin_mac_device,
633#endif
634
635#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) 627#if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE)
636 &ksz8893m_switch_device, 628 &ksz8893m_switch_device,
637#endif 629#endif
630#endif
638 631
639#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 632#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
640 &bfin_spi0_device, 633 &bfin_spi0_device,
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index e5b4bef0edae..c847bb101076 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf518/anomaly.h 2 * File: include/asm-blackfin/mach-bf518/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - ???? 10 * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -19,6 +19,8 @@
19#define ANOMALY_05000122 (1) 19#define ANOMALY_05000122 (1)
20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
21#define ANOMALY_05000245 (1) 21#define ANOMALY_05000245 (1)
22/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
23#define ANOMALY_05000254 (1)
22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 (1) 25#define ANOMALY_05000265 (1)
24/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 26/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -53,6 +55,12 @@
53#define ANOMALY_05000443 (1) 55#define ANOMALY_05000443 (1)
54/* Incorrect L1 Instruction Bank B Memory Map Location */ 56/* Incorrect L1 Instruction Bank B Memory Map Location */
55#define ANOMALY_05000444 (1) 57#define ANOMALY_05000444 (1)
58/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
59#define ANOMALY_05000452 (1)
60/* PWM_TRIPB Signal Not Available on PG10 */
61#define ANOMALY_05000453 (1)
62/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
63#define ANOMALY_05000455 (1)
56 64
57/* Anomalies that don't exist on this proc */ 65/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0) 66#define ANOMALY_05000125 (0)
@@ -65,15 +73,20 @@
65#define ANOMALY_05000263 (0) 73#define ANOMALY_05000263 (0)
66#define ANOMALY_05000266 (0) 74#define ANOMALY_05000266 (0)
67#define ANOMALY_05000273 (0) 75#define ANOMALY_05000273 (0)
76#define ANOMALY_05000278 (0)
68#define ANOMALY_05000285 (0) 77#define ANOMALY_05000285 (0)
78#define ANOMALY_05000305 (0)
69#define ANOMALY_05000307 (0) 79#define ANOMALY_05000307 (0)
70#define ANOMALY_05000311 (0) 80#define ANOMALY_05000311 (0)
71#define ANOMALY_05000312 (0) 81#define ANOMALY_05000312 (0)
72#define ANOMALY_05000323 (0) 82#define ANOMALY_05000323 (0)
73#define ANOMALY_05000353 (0) 83#define ANOMALY_05000353 (0)
74#define ANOMALY_05000363 (0) 84#define ANOMALY_05000363 (0)
85#define ANOMALY_05000380 (0)
75#define ANOMALY_05000386 (0) 86#define ANOMALY_05000386 (0)
76#define ANOMALY_05000412 (0) 87#define ANOMALY_05000412 (0)
77#define ANOMALY_05000432 (0) 88#define ANOMALY_05000432 (0)
89#define ANOMALY_05000447 (0)
90#define ANOMALY_05000448 (0)
78 91
79#endif 92#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
index b50a63b975a2..e21c1c3e4ec7 100644
--- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c
index 856c097b5317..48e69eecdba4 100644
--- a/arch/blackfin/mach-bf527/boards/cm_bf527.c
+++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c
@@ -487,9 +487,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
487}; 487};
488#endif 488#endif
489 489
490#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 490#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
491static struct bfin5xx_spi_chip spi_mmc_chip_info = { 491static struct bfin5xx_spi_chip mmc_spi_chip_info = {
492 .enable_dma = 1, 492 .enable_dma = 0,
493 .bits_per_word = 8, 493 .bits_per_word = 8,
494}; 494};
495#endif 495#endif
@@ -585,23 +585,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
585 .controller_data = &ad9960_spi_chip_info, 585 .controller_data = &ad9960_spi_chip_info,
586 }, 586 },
587#endif 587#endif
588#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 588#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
589 { 589 {
590 .modalias = "spi_mmc_dummy", 590 .modalias = "mmc_spi",
591 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 591 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
592 .bus_num = 0,
593 .chip_select = 0,
594 .platform_data = NULL,
595 .controller_data = &spi_mmc_chip_info,
596 .mode = SPI_MODE_3,
597 },
598 {
599 .modalias = "spi_mmc",
600 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
601 .bus_num = 0, 592 .bus_num = 0,
602 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 593 .chip_select = 5,
603 .platform_data = NULL, 594 .controller_data = &mmc_spi_chip_info,
604 .controller_data = &spi_mmc_chip_info,
605 .mode = SPI_MODE_3, 595 .mode = SPI_MODE_3,
606 }, 596 },
607#endif 597#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c
index 83606fcdde27..7fe480e4ebe8 100644
--- a/arch/blackfin/mach-bf527/boards/ezbrd.c
+++ b/arch/blackfin/mach-bf527/boards/ezbrd.c
@@ -256,9 +256,9 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = {
256}; 256};
257#endif 257#endif
258 258
259#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 259#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
260static struct bfin5xx_spi_chip spi_mmc_chip_info = { 260static struct bfin5xx_spi_chip mmc_spi_chip_info = {
261 .enable_dma = 1, 261 .enable_dma = 0,
262 .bits_per_word = 8, 262 .bits_per_word = 8,
263}; 263};
264#endif 264#endif
@@ -366,23 +366,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
366 }, 366 },
367#endif 367#endif
368 368
369#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 369#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
370 { 370 {
371 .modalias = "spi_mmc_dummy", 371 .modalias = "mmc_spi",
372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 372 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
373 .bus_num = 0, 373 .bus_num = 0,
374 .chip_select = 0, 374 .chip_select = 5,
375 .platform_data = NULL, 375 .controller_data = &mmc_spi_chip_info,
376 .controller_data = &spi_mmc_chip_info,
377 .mode = SPI_MODE_3,
378 },
379 {
380 .modalias = "spi_mmc",
381 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
382 .bus_num = 0,
383 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
384 .platform_data = NULL,
385 .controller_data = &spi_mmc_chip_info,
386 .mode = SPI_MODE_3, 376 .mode = SPI_MODE_3,
387 }, 377 },
388#endif 378#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 035e8d835058..df6808d8a6ef 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf527/anomaly.h 2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -167,12 +167,16 @@
167#define ANOMALY_05000263 (0) 167#define ANOMALY_05000263 (0)
168#define ANOMALY_05000266 (0) 168#define ANOMALY_05000266 (0)
169#define ANOMALY_05000273 (0) 169#define ANOMALY_05000273 (0)
170#define ANOMALY_05000278 (0)
170#define ANOMALY_05000285 (0) 171#define ANOMALY_05000285 (0)
172#define ANOMALY_05000305 (0)
171#define ANOMALY_05000307 (0) 173#define ANOMALY_05000307 (0)
172#define ANOMALY_05000311 (0) 174#define ANOMALY_05000311 (0)
173#define ANOMALY_05000312 (0) 175#define ANOMALY_05000312 (0)
174#define ANOMALY_05000323 (0) 176#define ANOMALY_05000323 (0)
175#define ANOMALY_05000363 (0) 177#define ANOMALY_05000363 (0)
176#define ANOMALY_05000412 (0) 178#define ANOMALY_05000412 (0)
179#define ANOMALY_05000447 (0)
180#define ANOMALY_05000448 (0)
177 181
178#endif 182#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
index 75722d6008b0..e8c41fd842b5 100644
--- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig
index 308c98dc5aba..8d8b3e7321e6 100644
--- a/arch/blackfin/mach-bf533/boards/Kconfig
+++ b/arch/blackfin/mach-bf533/boards/Kconfig
@@ -38,9 +38,4 @@ config BFIN532_IP0X
38 help 38 help
39 Core support for IP04/IP04 open hardware IP-PBX. 39 Core support for IP04/IP04 open hardware IP-PBX.
40 40
41config GENERIC_BF533_BOARD
42 bool "Generic"
43 help
44 Generic or Custom board support.
45
46endchoice 41endchoice
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile
index 9afbe72b484f..ff1e832f80d2 100644
--- a/arch/blackfin/mach-bf533/boards/Makefile
+++ b/arch/blackfin/mach-bf533/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf533/boards/Makefile 2# arch/blackfin/mach-bf533/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN533_STAMP) += stamp.o 5obj-$(CONFIG_BFIN533_STAMP) += stamp.o
7obj-$(CONFIG_BFIN532_IP0X) += ip0x.o 6obj-$(CONFIG_BFIN532_IP0X) += ip0x.o
8obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o 7obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c
index 015c18f85e7f..0765872a8ada 100644
--- a/arch/blackfin/mach-bf533/boards/blackstamp.c
+++ b/arch/blackfin/mach-bf533/boards/blackstamp.c
@@ -101,9 +101,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
101}; 101};
102#endif 102#endif
103 103
104#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 104#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
105static struct bfin5xx_spi_chip spi_mmc_chip_info = { 105static struct bfin5xx_spi_chip mmc_spi_chip_info = {
106 .enable_dma = 1, 106 .enable_dma = 0,
107 .bits_per_word = 8, 107 .bits_per_word = 8,
108}; 108};
109#endif 109#endif
@@ -129,23 +129,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
129 }, 129 },
130#endif 130#endif
131 131
132#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 132#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
133 {
134 .modalias = "spi_mmc_dummy",
135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
136 .bus_num = 0,
137 .chip_select = 0,
138 .platform_data = NULL,
139 .controller_data = &spi_mmc_chip_info,
140 .mode = SPI_MODE_3,
141 },
142 { 133 {
143 .modalias = "spi_mmc", 134 .modalias = "mmc_spi",
144 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ 135 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0, 136 .bus_num = 0,
146 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 137 .chip_select = 5,
147 .platform_data = NULL, 138 .controller_data = &mmc_spi_chip_info,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3, 139 .mode = SPI_MODE_3,
150 }, 140 },
151#endif 141#endif
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c
index e7061c7e8c42..e8974878d8c2 100644
--- a/arch/blackfin/mach-bf533/boards/cm_bf533.c
+++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c
@@ -96,9 +96,9 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
96}; 96};
97#endif 97#endif
98 98
99#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 99#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
100static struct bfin5xx_spi_chip spi_mmc_chip_info = { 100static struct bfin5xx_spi_chip mmc_spi_chip_info = {
101 .enable_dma = 1, 101 .enable_dma = 0,
102 .bits_per_word = 8, 102 .bits_per_word = 8,
103}; 103};
104#endif 104#endif
@@ -138,23 +138,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
138 }, 138 },
139#endif 139#endif
140 140
141#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 141#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
142 {
143 .modalias = "spi_mmc_dummy",
144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
145 .bus_num = 0,
146 .chip_select = 0,
147 .platform_data = NULL,
148 .controller_data = &spi_mmc_chip_info,
149 .mode = SPI_MODE_3,
150 },
151 { 142 {
152 .modalias = "spi_mmc", 143 .modalias = "mmc_spi",
153 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 144 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
154 .bus_num = 0, 145 .bus_num = 0,
155 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 146 .chip_select = 5,
156 .platform_data = NULL, 147 .controller_data = &mmc_spi_chip_info,
157 .controller_data = &spi_mmc_chip_info,
158 .mode = SPI_MODE_3, 148 .mode = SPI_MODE_3,
159 }, 149 },
160#endif 150#endif
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c
deleted file mode 100644
index 986eeec53b1f..000000000000
--- a/arch/blackfin/mach-bf533/boards/generic_board.c
+++ /dev/null
@@ -1,126 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf533/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created: 2005
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35/*
36 * Name the Board for the /proc/cpuinfo
37 */
38const char bfin_board_name[] = "UNKNOWN BOARD";
39
40#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
41static struct platform_device rtc_device = {
42 .name = "rtc-bfin",
43 .id = -1,
44};
45#endif
46
47/*
48 * Driver needs to know address, irq and flag pin.
49 */
50#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
51static struct resource smc91x_resources[] = {
52 {
53 .start = 0x20300300,
54 .end = 0x20300300 + 16,
55 .flags = IORESOURCE_MEM,
56 }, {
57 .start = IRQ_PROG_INTB,
58 .end = IRQ_PROG_INTB,
59 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
60 }, {
61 .start = IRQ_PF7,
62 .end = IRQ_PF7,
63 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
64 },
65};
66
67static struct platform_device smc91x_device = {
68 .name = "smc91x",
69 .id = 0,
70 .num_resources = ARRAY_SIZE(smc91x_resources),
71 .resource = smc91x_resources,
72};
73#endif
74
75#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
76#ifdef CONFIG_BFIN_SIR0
77static struct resource bfin_sir0_resources[] = {
78 {
79 .start = 0xFFC00400,
80 .end = 0xFFC004FF,
81 .flags = IORESOURCE_MEM,
82 },
83 {
84 .start = IRQ_UART0_RX,
85 .end = IRQ_UART0_RX+1,
86 .flags = IORESOURCE_IRQ,
87 },
88 {
89 .start = CH_UART0_RX,
90 .end = CH_UART0_RX+1,
91 .flags = IORESOURCE_DMA,
92 },
93};
94
95static struct platform_device bfin_sir0_device = {
96 .name = "bfin_sir",
97 .id = 0,
98 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
99 .resource = bfin_sir0_resources,
100};
101#endif
102#endif
103
104static struct platform_device *generic_board_devices[] __initdata = {
105#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
106 &rtc_device,
107#endif
108
109#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
110 &smc91x_device,
111#endif
112
113#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
114#ifdef CONFIG_BFIN_SIR0
115 &bfin_sir0_device,
116#endif
117#endif
118};
119
120static int __init generic_board_init(void)
121{
122 printk(KERN_INFO "%s(): registering device resources\n", __func__);
123 return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices));
124}
125
126arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c
index e30b1b7d1442..f19b63378b12 100644
--- a/arch/blackfin/mach-bf533/boards/ip0x.c
+++ b/arch/blackfin/mach-bf533/boards/ip0x.c
@@ -127,8 +127,8 @@ static struct platform_device dm9000_device2 = {
127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) 127#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
128/* all SPI peripherals info goes here */ 128/* all SPI peripherals info goes here */
129 129
130#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 130#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
131static struct bfin5xx_spi_chip spi_mmc_chip_info = { 131static struct bfin5xx_spi_chip mmc_spi_chip_info = {
132/* 132/*
133 * CPOL (Clock Polarity) 133 * CPOL (Clock Polarity)
134 * 0 - Active high SCK 134 * 0 - Active high SCK
@@ -152,14 +152,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = {
152/* Notice: for blackfin, the speed_hz is the value of register 152/* Notice: for blackfin, the speed_hz is the value of register
153 * SPI_BAUD, not the real baudrate */ 153 * SPI_BAUD, not the real baudrate */
154static struct spi_board_info bfin_spi_board_info[] __initdata = { 154static struct spi_board_info bfin_spi_board_info[] __initdata = {
155#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 155#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
156 { 156 {
157 .modalias = "spi_mmc", 157 .modalias = "mmc_spi",
158 .max_speed_hz = 2, 158 .max_speed_hz = 2,
159 .bus_num = 1, 159 .bus_num = 1,
160 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 160 .chip_select = 5,
161 .platform_data = NULL, 161 .controller_data = &mmc_spi_chip_info,
162 .controller_data = &spi_mmc_chip_info,
163 }, 162 },
164#endif 163#endif
165}; 164};
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 0d3a03429fb9..1cf893e2e55b 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -160,7 +160,7 @@
160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
@@ -278,9 +278,12 @@
278#define ANOMALY_05000266 (0) 278#define ANOMALY_05000266 (0)
279#define ANOMALY_05000323 (0) 279#define ANOMALY_05000323 (0)
280#define ANOMALY_05000353 (1) 280#define ANOMALY_05000353 (1)
281#define ANOMALY_05000380 (0)
281#define ANOMALY_05000386 (1) 282#define ANOMALY_05000386 (1)
282#define ANOMALY_05000412 (0) 283#define ANOMALY_05000412 (0)
283#define ANOMALY_05000432 (0) 284#define ANOMALY_05000432 (0)
284#define ANOMALY_05000435 (0) 285#define ANOMALY_05000435 (0)
286#define ANOMALY_05000447 (0)
287#define ANOMALY_05000448 (0)
285 288
286#endif 289#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
index f3d9e495230c..5f517f53b0fd 100644
--- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig
index 42a57b0acb29..77c59da87e85 100644
--- a/arch/blackfin/mach-bf537/boards/Kconfig
+++ b/arch/blackfin/mach-bf537/boards/Kconfig
@@ -33,9 +33,4 @@ config CAMSIG_MINOTAUR
33 help 33 help
34 Board supply package for CSP Minotaur 34 Board supply package for CSP Minotaur
35 35
36config GENERIC_BF537_BOARD
37 bool "Generic"
38 help
39 Generic or Custom board support.
40
41endchoice 36endchoice
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile
index 7168cc14afd8..68b98a7af6a6 100644
--- a/arch/blackfin/mach-bf537/boards/Makefile
+++ b/arch/blackfin/mach-bf537/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf537/boards/Makefile 2# arch/blackfin/mach-bf537/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN537_STAMP) += stamp.o 5obj-$(CONFIG_BFIN537_STAMP) += stamp.o
7obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o 6obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o
8obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o 7obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c
index 9cd8fb2a30d3..41c75b9bfac0 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 1,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c
deleted file mode 100644
index da710fdc4569..000000000000
--- a/arch/blackfin/mach-bf537/boards/generic_board.c
+++ /dev/null
@@ -1,745 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf537/boards/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/boards/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2008 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/etherdevice.h>
33#include <linux/platform_device.h>
34#include <linux/mtd/mtd.h>
35#include <linux/mtd/partitions.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/flash.h>
38#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
39#include <linux/usb/isp1362.h>
40#endif
41#include <linux/irq.h>
42#include <linux/interrupt.h>
43#include <linux/usb/sl811.h>
44#include <asm/dma.h>
45#include <asm/bfin5xx_spi.h>
46#include <asm/reboot.h>
47#include <asm/portmux.h>
48#include <linux/spi/ad7877.h>
49
50/*
51 * Name the Board for the /proc/cpuinfo
52 */
53const char bfin_board_name[] = "UNKNOWN BOARD";
54
55/*
56 * Driver needs to know address, irq and flag pin.
57 */
58
59#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
60#include <linux/usb/isp1760.h>
61static struct resource bfin_isp1760_resources[] = {
62 [0] = {
63 .start = 0x203C0000,
64 .end = 0x203C0000 + 0x000fffff,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = {
68 .start = IRQ_PF7,
69 .end = IRQ_PF7,
70 .flags = IORESOURCE_IRQ,
71 },
72};
73
74static struct isp1760_platform_data isp1760_priv = {
75 .is_isp1761 = 0,
76 .port1_disable = 0,
77 .bus_width_16 = 1,
78 .port1_otg = 0,
79 .analog_oc = 0,
80 .dack_polarity_high = 0,
81 .dreq_polarity_high = 0,
82};
83
84static struct platform_device bfin_isp1760_device = {
85 .name = "isp1760-hcd",
86 .id = 0,
87 .dev = {
88 .platform_data = &isp1760_priv,
89 },
90 .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
91 .resource = bfin_isp1760_resources,
92};
93#endif
94
95#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
96static struct resource bfin_pcmcia_cf_resources[] = {
97 {
98 .start = 0x20310000, /* IO PORT */
99 .end = 0x20312000,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = 0x20311000, /* Attribute Memory */
103 .end = 0x20311FFF,
104 .flags = IORESOURCE_MEM,
105 }, {
106 .start = IRQ_PF4,
107 .end = IRQ_PF4,
108 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
109 }, {
110 .start = 6, /* Card Detect PF6 */
111 .end = 6,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device bfin_pcmcia_cf_device = {
117 .name = "bfin_cf_pcmcia",
118 .id = -1,
119 .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
120 .resource = bfin_pcmcia_cf_resources,
121};
122#endif
123
124#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
125static struct platform_device rtc_device = {
126 .name = "rtc-bfin",
127 .id = -1,
128};
129#endif
130
131#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
132static struct resource smc91x_resources[] = {
133 {
134 .name = "smc91x-regs",
135 .start = 0x20300300,
136 .end = 0x20300300 + 16,
137 .flags = IORESOURCE_MEM,
138 }, {
139
140 .start = IRQ_PF7,
141 .end = IRQ_PF7,
142 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
143 },
144};
145static struct platform_device smc91x_device = {
146 .name = "smc91x",
147 .id = 0,
148 .num_resources = ARRAY_SIZE(smc91x_resources),
149 .resource = smc91x_resources,
150};
151#endif
152
153#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
154static struct resource dm9000_resources[] = {
155 [0] = {
156 .start = 0x203FB800,
157 .end = 0x203FB800 + 1,
158 .flags = IORESOURCE_MEM,
159 },
160 [1] = {
161 .start = 0x203FB800 + 4,
162 .end = 0x203FB800 + 5,
163 .flags = IORESOURCE_MEM,
164 },
165 [2] = {
166 .start = IRQ_PF9,
167 .end = IRQ_PF9,
168 .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
169 },
170};
171
172static struct platform_device dm9000_device = {
173 .name = "dm9000",
174 .id = -1,
175 .num_resources = ARRAY_SIZE(dm9000_resources),
176 .resource = dm9000_resources,
177};
178#endif
179
180#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
181static struct resource sl811_hcd_resources[] = {
182 {
183 .start = 0x20340000,
184 .end = 0x20340000,
185 .flags = IORESOURCE_MEM,
186 }, {
187 .start = 0x20340004,
188 .end = 0x20340004,
189 .flags = IORESOURCE_MEM,
190 }, {
191 .start = CONFIG_USB_SL811_BFIN_IRQ,
192 .end = CONFIG_USB_SL811_BFIN_IRQ,
193 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
194 },
195};
196
197#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
198void sl811_port_power(struct device *dev, int is_on)
199{
200 gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS");
201 gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on);
202
203}
204#endif
205
206static struct sl811_platform_data sl811_priv = {
207 .potpg = 10,
208 .power = 250, /* == 500mA */
209#if defined(CONFIG_USB_SL811_BFIN_USE_VBUS)
210 .port_power = &sl811_port_power,
211#endif
212};
213
214static struct platform_device sl811_hcd_device = {
215 .name = "sl811-hcd",
216 .id = 0,
217 .dev = {
218 .platform_data = &sl811_priv,
219 },
220 .num_resources = ARRAY_SIZE(sl811_hcd_resources),
221 .resource = sl811_hcd_resources,
222};
223#endif
224
225#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
226static struct resource isp1362_hcd_resources[] = {
227 {
228 .start = 0x20360000,
229 .end = 0x20360000,
230 .flags = IORESOURCE_MEM,
231 }, {
232 .start = 0x20360004,
233 .end = 0x20360004,
234 .flags = IORESOURCE_MEM,
235 }, {
236 .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
237 .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ,
238 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
239 },
240};
241
242static struct isp1362_platform_data isp1362_priv = {
243 .sel15Kres = 1,
244 .clknotstop = 0,
245 .oc_enable = 0,
246 .int_act_high = 0,
247 .int_edge_triggered = 0,
248 .remote_wakeup_connected = 0,
249 .no_power_switching = 1,
250 .power_switching_mode = 0,
251};
252
253static struct platform_device isp1362_hcd_device = {
254 .name = "isp1362-hcd",
255 .id = 0,
256 .dev = {
257 .platform_data = &isp1362_priv,
258 },
259 .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
260 .resource = isp1362_hcd_resources,
261};
262#endif
263
264#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
265static struct platform_device bfin_mii_bus = {
266 .name = "bfin_mii_bus",
267};
268
269static struct platform_device bfin_mac_device = {
270 .name = "bfin_mac",
271 .dev.platform_data = &bfin_mii_bus,
272};
273#endif
274
275#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
276static struct resource net2272_bfin_resources[] = {
277 {
278 .start = 0x20300000,
279 .end = 0x20300000 + 0x100,
280 .flags = IORESOURCE_MEM,
281 }, {
282 .start = IRQ_PF7,
283 .end = IRQ_PF7,
284 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
285 },
286};
287
288static struct platform_device net2272_bfin_device = {
289 .name = "net2272",
290 .id = -1,
291 .num_resources = ARRAY_SIZE(net2272_bfin_resources),
292 .resource = net2272_bfin_resources,
293};
294#endif
295
296#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
297/* all SPI peripherals info goes here */
298
299#if defined(CONFIG_MTD_M25P80) \
300 || defined(CONFIG_MTD_M25P80_MODULE)
301static struct mtd_partition bfin_spi_flash_partitions[] = {
302 {
303 .name = "bootloader(spi)",
304 .size = 0x00020000,
305 .offset = 0,
306 .mask_flags = MTD_CAP_ROM
307 }, {
308 .name = "linux kernel(spi)",
309 .size = 0xe0000,
310 .offset = 0x20000
311 }, {
312 .name = "file system(spi)",
313 .size = 0x700000,
314 .offset = 0x00100000,
315 }
316};
317
318static struct flash_platform_data bfin_spi_flash_data = {
319 .name = "m25p80",
320 .parts = bfin_spi_flash_partitions,
321 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
322 .type = "m25p64",
323};
324
325/* SPI flash chip (m25p64) */
326static struct bfin5xx_spi_chip spi_flash_chip_info = {
327 .enable_dma = 0, /* use dma transfer with this chip*/
328 .bits_per_word = 8,
329};
330#endif
331
332#if defined(CONFIG_SPI_ADC_BF533) \
333 || defined(CONFIG_SPI_ADC_BF533_MODULE)
334/* SPI ADC chip */
335static struct bfin5xx_spi_chip spi_adc_chip_info = {
336 .enable_dma = 1, /* use dma transfer with this chip*/
337 .bits_per_word = 16,
338};
339#endif
340
341#if defined(CONFIG_SND_BLACKFIN_AD1836) \
342 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
343static struct bfin5xx_spi_chip ad1836_spi_chip_info = {
344 .enable_dma = 0,
345 .bits_per_word = 16,
346};
347#endif
348
349#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
350static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
351 .enable_dma = 0,
352 .bits_per_word = 16,
353};
354#endif
355
356#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
357static struct bfin5xx_spi_chip spi_mmc_chip_info = {
358 .enable_dma = 1,
359 .bits_per_word = 8,
360};
361#endif
362
363#if defined(CONFIG_PBX)
364static struct bfin5xx_spi_chip spi_si3xxx_chip_info = {
365 .ctl_reg = 0x4, /* send zero */
366 .enable_dma = 0,
367 .bits_per_word = 8,
368 .cs_change_per_word = 1,
369};
370#endif
371
372#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
373static struct bfin5xx_spi_chip spi_ad7877_chip_info = {
374 .enable_dma = 0,
375 .bits_per_word = 16,
376};
377
378static const struct ad7877_platform_data bfin_ad7877_ts_info = {
379 .model = 7877,
380 .vref_delay_usecs = 50, /* internal, no capacitor */
381 .x_plate_ohms = 419,
382 .y_plate_ohms = 486,
383 .pressure_max = 1000,
384 .pressure_min = 0,
385 .stopacq_polarity = 1,
386 .first_conversion_delay = 3,
387 .acquisition_time = 1,
388 .averaging = 1,
389 .pen_down_acc_interval = 1,
390};
391#endif
392
393static struct spi_board_info bfin_spi_board_info[] __initdata = {
394#if defined(CONFIG_MTD_M25P80) \
395 || defined(CONFIG_MTD_M25P80_MODULE)
396 {
397 /* the modalias must be the same as spi device driver name */
398 .modalias = "m25p80", /* Name of spi_driver for this device */
399 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
400 .bus_num = 0, /* Framework bus number */
401 .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
402 .platform_data = &bfin_spi_flash_data,
403 .controller_data = &spi_flash_chip_info,
404 .mode = SPI_MODE_3,
405 },
406#endif
407
408#if defined(CONFIG_SPI_ADC_BF533) \
409 || defined(CONFIG_SPI_ADC_BF533_MODULE)
410 {
411 .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */
412 .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */
413 .bus_num = 0, /* Framework bus number */
414 .chip_select = 1, /* Framework chip select. */
415 .platform_data = NULL, /* No spi_driver specific config */
416 .controller_data = &spi_adc_chip_info,
417 },
418#endif
419
420#if defined(CONFIG_SND_BLACKFIN_AD1836) \
421 || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE)
422 {
423 .modalias = "ad1836-spi",
424 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
425 .bus_num = 0,
426 .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT,
427 .controller_data = &ad1836_spi_chip_info,
428 },
429#endif
430#if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE)
431 {
432 .modalias = "ad9960-spi",
433 .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */
434 .bus_num = 0,
435 .chip_select = 1,
436 .controller_data = &ad9960_spi_chip_info,
437 },
438#endif
439#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE)
440 {
441 .modalias = "spi_mmc_dummy",
442 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
443 .bus_num = 0,
444 .chip_select = 0,
445 .platform_data = NULL,
446 .controller_data = &spi_mmc_chip_info,
447 .mode = SPI_MODE_3,
448 },
449 {
450 .modalias = "spi_mmc",
451 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
452 .bus_num = 0,
453 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
454 .platform_data = NULL,
455 .controller_data = &spi_mmc_chip_info,
456 .mode = SPI_MODE_3,
457 },
458#endif
459#if defined(CONFIG_PBX)
460 {
461 .modalias = "fxs-spi",
462 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
463 .bus_num = 0,
464 .chip_select = 8 - CONFIG_J11_JUMPER,
465 .controller_data = &spi_si3xxx_chip_info,
466 .mode = SPI_MODE_3,
467 },
468 {
469 .modalias = "fxo-spi",
470 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
471 .bus_num = 0,
472 .chip_select = 8 - CONFIG_J19_JUMPER,
473 .controller_data = &spi_si3xxx_chip_info,
474 .mode = SPI_MODE_3,
475 },
476#endif
477#if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
478 {
479 .modalias = "ad7877",
480 .platform_data = &bfin_ad7877_ts_info,
481 .irq = IRQ_PF6,
482 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */
483 .bus_num = 0,
484 .chip_select = 1,
485 .controller_data = &spi_ad7877_chip_info,
486 },
487#endif
488};
489
490/* SPI controller data */
491static struct bfin5xx_spi_master bfin_spi0_info = {
492 .num_chipselect = 8,
493 .enable_dma = 1, /* master has the ability to do dma transfer */
494 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
495};
496
497/* SPI (0) */
498static struct resource bfin_spi0_resource[] = {
499 [0] = {
500 .start = SPI0_REGBASE,
501 .end = SPI0_REGBASE + 0xFF,
502 .flags = IORESOURCE_MEM,
503 },
504 [1] = {
505 .start = CH_SPI,
506 .end = CH_SPI,
507 .flags = IORESOURCE_IRQ,
508 },
509};
510
511static struct platform_device bfin_spi0_device = {
512 .name = "bfin-spi",
513 .id = 0, /* Bus number */
514 .num_resources = ARRAY_SIZE(bfin_spi0_resource),
515 .resource = bfin_spi0_resource,
516 .dev = {
517 .platform_data = &bfin_spi0_info, /* Passed to driver */
518 },
519};
520#endif /* spi master and devices */
521
522#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
523static struct platform_device bfin_fb_device = {
524 .name = "bf537-lq035",
525};
526#endif
527
528#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
529static struct platform_device bfin_fb_adv7393_device = {
530 .name = "bfin-adv7393",
531};
532#endif
533
534#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
535static struct resource bfin_uart_resources[] = {
536 {
537 .start = 0xFFC00400,
538 .end = 0xFFC004FF,
539 .flags = IORESOURCE_MEM,
540 }, {
541 .start = 0xFFC02000,
542 .end = 0xFFC020FF,
543 .flags = IORESOURCE_MEM,
544 },
545};
546
547static struct platform_device bfin_uart_device = {
548 .name = "bfin-uart",
549 .id = 1,
550 .num_resources = ARRAY_SIZE(bfin_uart_resources),
551 .resource = bfin_uart_resources,
552};
553#endif
554
555#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
556#ifdef CONFIG_BFIN_SIR0
557static struct resource bfin_sir0_resources[] = {
558 {
559 .start = 0xFFC00400,
560 .end = 0xFFC004FF,
561 .flags = IORESOURCE_MEM,
562 },
563 {
564 .start = IRQ_UART0_RX,
565 .end = IRQ_UART0_RX+1,
566 .flags = IORESOURCE_IRQ,
567 },
568 {
569 .start = CH_UART0_RX,
570 .end = CH_UART0_RX+1,
571 .flags = IORESOURCE_DMA,
572 },
573};
574
575static struct platform_device bfin_sir0_device = {
576 .name = "bfin_sir",
577 .id = 0,
578 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
579 .resource = bfin_sir0_resources,
580};
581#endif
582#ifdef CONFIG_BFIN_SIR1
583static struct resource bfin_sir1_resources[] = {
584 {
585 .start = 0xFFC02000,
586 .end = 0xFFC020FF,
587 .flags = IORESOURCE_MEM,
588 },
589 {
590 .start = IRQ_UART1_RX,
591 .end = IRQ_UART1_RX+1,
592 .flags = IORESOURCE_IRQ,
593 },
594 {
595 .start = CH_UART1_RX,
596 .end = CH_UART1_RX+1,
597 .flags = IORESOURCE_DMA,
598 },
599};
600
601static struct platform_device bfin_sir1_device = {
602 .name = "bfin_sir",
603 .id = 1,
604 .num_resources = ARRAY_SIZE(bfin_sir1_resources),
605 .resource = bfin_sir1_resources,
606};
607#endif
608#endif
609
610#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
611static struct resource bfin_twi0_resource[] = {
612 [0] = {
613 .start = TWI0_REGBASE,
614 .end = TWI0_REGBASE + 0xFF,
615 .flags = IORESOURCE_MEM,
616 },
617 [1] = {
618 .start = IRQ_TWI,
619 .end = IRQ_TWI,
620 .flags = IORESOURCE_IRQ,
621 },
622};
623
624static struct platform_device i2c_bfin_twi_device = {
625 .name = "i2c-bfin-twi",
626 .id = 0,
627 .num_resources = ARRAY_SIZE(bfin_twi0_resource),
628 .resource = bfin_twi0_resource,
629};
630#endif
631
632#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
633static struct platform_device bfin_sport0_uart_device = {
634 .name = "bfin-sport-uart",
635 .id = 0,
636};
637
638static struct platform_device bfin_sport1_uart_device = {
639 .name = "bfin-sport-uart",
640 .id = 1,
641};
642#endif
643
644static struct platform_device *stamp_devices[] __initdata = {
645#if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE)
646 &bfin_pcmcia_cf_device,
647#endif
648
649#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
650 &rtc_device,
651#endif
652
653#if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE)
654 &sl811_hcd_device,
655#endif
656
657#if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
658 &isp1362_hcd_device,
659#endif
660
661#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
662 &smc91x_device,
663#endif
664
665#if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
666 &dm9000_device,
667#endif
668
669#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
670 &bfin_mii_bus,
671 &bfin_mac_device,
672#endif
673
674#if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE)
675 &net2272_bfin_device,
676#endif
677
678#if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
679 &bfin_isp1760_device,
680#endif
681
682#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
683 &bfin_spi0_device,
684#endif
685
686#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
687 &bfin_fb_device,
688#endif
689
690#if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE)
691 &bfin_fb_adv7393_device,
692#endif
693
694#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
695 &bfin_uart_device,
696#endif
697
698#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
699#ifdef CONFIG_BFIN_SIR0
700 &bfin_sir0_device,
701#endif
702#ifdef CONFIG_BFIN_SIR1
703 &bfin_sir1_device,
704#endif
705#endif
706
707#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
708 &i2c_bfin_twi_device,
709#endif
710
711#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
712 &bfin_sport0_uart_device,
713 &bfin_sport1_uart_device,
714#endif
715};
716
717static int __init generic_init(void)
718{
719 printk(KERN_INFO "%s(): registering device resources\n", __func__);
720 platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
721#if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
722 spi_register_board_info(bfin_spi_board_info,
723 ARRAY_SIZE(bfin_spi_board_info));
724#endif
725
726 return 0;
727}
728
729arch_initcall(generic_init);
730
731void native_machine_restart(char *cmd)
732{
733 /* workaround reboot hang when booting from SPI */
734 if ((bfin_read_SYSCR() & 0x7) == 0x3)
735 bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
736}
737
738#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
739void bfin_get_ether_addr(char *addr)
740{
741 random_ether_addr(addr);
742 printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__);
743}
744EXPORT_SYMBOL(bfin_get_ether_addr);
745#endif
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c
index db7d3a385e4b..3c159819e555 100644
--- a/arch/blackfin/mach-bf537/boards/minotaur.c
+++ b/arch/blackfin/mach-bf537/boards/minotaur.c
@@ -134,9 +134,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = {
134}; 134};
135#endif 135#endif
136 136
137#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 137#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
138static struct bfin5xx_spi_chip spi_mmc_chip_info = { 138static struct bfin5xx_spi_chip mmc_spi_chip_info = {
139 .enable_dma = 1, 139 .enable_dma = 0,
140 .bits_per_word = 8, 140 .bits_per_word = 8,
141}; 141};
142#endif 142#endif
@@ -156,23 +156,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
156 }, 156 },
157#endif 157#endif
158 158
159#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 159#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
160 { 160 {
161 .modalias = "spi_mmc_dummy", 161 .modalias = "mmc_spi",
162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 162 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
163 .bus_num = 0, 163 .bus_num = 0,
164 .chip_select = 0, 164 .chip_select = 5,
165 .platform_data = NULL, 165 .controller_data = &mmc_spi_chip_info,
166 .controller_data = &spi_mmc_chip_info,
167 .mode = SPI_MODE_3,
168 },
169 {
170 .modalias = "spi_mmc",
171 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */
172 .bus_num = 0,
173 .chip_select = CONFIG_SPI_MMC_CS_CHAN,
174 .platform_data = NULL,
175 .controller_data = &spi_mmc_chip_info,
176 .mode = SPI_MODE_3, 166 .mode = SPI_MODE_3,
177 }, 167 },
178#endif 168#endif
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c
index 590eb3a139b7..4e1de1e53f89 100644
--- a/arch/blackfin/mach-bf537/boards/pnav10.c
+++ b/arch/blackfin/mach-bf537/boards/pnav10.c
@@ -289,9 +289,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
289}; 289};
290#endif 290#endif
291 291
292#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 292#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
293static struct bfin5xx_spi_chip spi_mmc_chip_info = { 293static struct bfin5xx_spi_chip mmc_spi_chip_info = {
294 .enable_dma = 1, 294 .enable_dma = 0,
295 .bits_per_word = 8, 295 .bits_per_word = 8,
296}; 296};
297#endif 297#endif
@@ -364,23 +364,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
364 .controller_data = &ad9960_spi_chip_info, 364 .controller_data = &ad9960_spi_chip_info,
365 }, 365 },
366#endif 366#endif
367#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 367#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
368 {
369 .modalias = "spi_mmc_dummy",
370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
371 .bus_num = 0,
372 .chip_select = 7,
373 .platform_data = NULL,
374 .controller_data = &spi_mmc_chip_info,
375 .mode = SPI_MODE_3,
376 },
377 { 368 {
378 .modalias = "spi_mmc", 369 .modalias = "mmc_spi",
379 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 370 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
380 .bus_num = 0, 371 .bus_num = 0,
381 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 372 .chip_select = 5,
382 .platform_data = NULL, 373 .controller_data = &mmc_spi_chip_info,
383 .controller_data = &spi_mmc_chip_info,
384 .mode = SPI_MODE_3, 374 .mode = SPI_MODE_3,
385 }, 375 },
386#endif 376#endif
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
index 3f4f203a06ec..53ad10f3cd76 100644
--- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c
+++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c
@@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
108}; 108};
109#endif 109#endif
110 110
111#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 111#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
112static struct bfin5xx_spi_chip spi_mmc_chip_info = { 112static struct bfin5xx_spi_chip mmc_spi_chip_info = {
113 .enable_dma = 1, 113 .enable_dma = 0,
114 .bits_per_word = 8, 114 .bits_per_word = 8,
115}; 115};
116#endif 116#endif
@@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
160 }, 160 },
161#endif 161#endif
162 162
163#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 163#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
164 {
165 .modalias = "spi_mmc_dummy",
166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
167 .bus_num = 0,
168 .chip_select = 7,
169 .platform_data = NULL,
170 .controller_data = &spi_mmc_chip_info,
171 .mode = SPI_MODE_3,
172 },
173 { 164 {
174 .modalias = "spi_mmc", 165 .modalias = "mmc_spi",
175 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 166 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
176 .bus_num = 0, 167 .bus_num = 0,
177 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 168 .chip_select = 5,
178 .platform_data = NULL, 169 .controller_data = &mmc_spi_chip_info,
179 .controller_data = &spi_mmc_chip_info,
180 .mode = SPI_MODE_3, 170 .mode = SPI_MODE_3,
181 }, 171 },
182#endif 172#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 9cb39121d1cb..1bfd80c26c90 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -110,7 +110,7 @@
110#define ANOMALY_05000301 (1) 110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) 112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 113/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
@@ -168,9 +168,12 @@
168#define ANOMALY_05000323 (0) 168#define ANOMALY_05000323 (0)
169#define ANOMALY_05000353 (1) 169#define ANOMALY_05000353 (1)
170#define ANOMALY_05000363 (0) 170#define ANOMALY_05000363 (0)
171#define ANOMALY_05000380 (0)
171#define ANOMALY_05000386 (1) 172#define ANOMALY_05000386 (1)
172#define ANOMALY_05000412 (0) 173#define ANOMALY_05000412 (0)
173#define ANOMALY_05000432 (0) 174#define ANOMALY_05000432 (0)
174#define ANOMALY_05000435 (0) 175#define ANOMALY_05000435 (0)
176#define ANOMALY_05000447 (0)
177#define ANOMALY_05000448 (0)
175 178
176#endif 179#endif
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
index b3f87e1d16a2..9e34700844a2 100644
--- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index e130b4f8a05d..3a5699827363 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf538/anomaly.h 2 * File: include/asm-blackfin/mach-bf538/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -120,13 +120,17 @@
120#define ANOMALY_05000198 (0) 120#define ANOMALY_05000198 (0)
121#define ANOMALY_05000230 (0) 121#define ANOMALY_05000230 (0)
122#define ANOMALY_05000263 (0) 122#define ANOMALY_05000263 (0)
123#define ANOMALY_05000305 (0)
123#define ANOMALY_05000311 (0) 124#define ANOMALY_05000311 (0)
124#define ANOMALY_05000323 (0) 125#define ANOMALY_05000323 (0)
125#define ANOMALY_05000353 (1) 126#define ANOMALY_05000353 (1)
126#define ANOMALY_05000363 (0) 127#define ANOMALY_05000363 (0)
128#define ANOMALY_05000380 (0)
127#define ANOMALY_05000386 (1) 129#define ANOMALY_05000386 (1)
128#define ANOMALY_05000412 (0) 130#define ANOMALY_05000412 (0)
129#define ANOMALY_05000432 (0) 131#define ANOMALY_05000432 (0)
130#define ANOMALY_05000435 (0) 132#define ANOMALY_05000435 (0)
133#define ANOMALY_05000447 (0)
134#define ANOMALY_05000448 (0)
131 135
132#endif 136#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
index 40503b6b89a3..3c2811ebecdd 100644
--- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h
@@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART0_TX, 144 CH_UART0_TX,
145 CH_UART0_RX, 145 CH_UART0_RX,
146#endif 146#endif
147#ifdef CONFIG_BFIN_UART0_CTSRTS 147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 CONFIG_UART0_CTS_PIN, 148 CONFIG_UART0_CTS_PIN,
149 CONFIG_UART0_RTS_PIN, 149 CONFIG_UART0_RTS_PIN,
150#endif 150#endif
@@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
158 CH_UART1_TX, 158 CH_UART1_TX,
159 CH_UART1_RX, 159 CH_UART1_RX,
160#endif 160#endif
161#ifdef CONFIG_BFIN_UART1_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
162 CONFIG_UART1_CTS_PIN, 162 CONFIG_UART1_CTS_PIN,
163 CONFIG_UART1_RTS_PIN, 163 CONFIG_UART1_RTS_PIN,
164#endif 164#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index 23d03c52f4b4..882e40ccf0d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf548/anomaly.h 2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -91,8 +91,6 @@
91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ 92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) 93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
94/* Mobile DDR Operation Not Functional */
95#define ANOMALY_05000377 (1)
96/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 94/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
97#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 95#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
98/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 96/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
@@ -157,8 +155,22 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 155#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 156/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 157#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
158/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
159#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
160/* OTP Write Accesses Not Supported */
161#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 162/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1) 163#define ANOMALY_05000443 (1)
164/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
165#define ANOMALY_05000446 (1)
166/* UART IrDA Receiver Fails on Extended Bit Pulses */
167#define ANOMALY_05000447 (1)
168/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
169#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
170/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
171#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
172/* USB DMA Mode 1 Short Packet Data Corruption */
173#define ANOMALY_05000450 (1
162 174
163/* Anomalies that don't exist on this proc */ 175/* Anomalies that don't exist on this proc */
164#define ANOMALY_05000125 (0) 176#define ANOMALY_05000125 (0)
@@ -171,6 +183,8 @@
171#define ANOMALY_05000263 (0) 183#define ANOMALY_05000263 (0)
172#define ANOMALY_05000266 (0) 184#define ANOMALY_05000266 (0)
173#define ANOMALY_05000273 (0) 185#define ANOMALY_05000273 (0)
186#define ANOMALY_05000278 (0)
187#define ANOMALY_05000305 (0)
174#define ANOMALY_05000307 (0) 188#define ANOMALY_05000307 (0)
175#define ANOMALY_05000311 (0) 189#define ANOMALY_05000311 (0)
176#define ANOMALY_05000323 (0) 190#define ANOMALY_05000323 (0)
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
index e4cf35e7ab9f..c05e79cba257 100644
--- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h
@@ -63,7 +63,7 @@
63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) 63#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) 64#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
65 65
66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) 66#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS)
67# define CONFIG_SERIAL_BFIN_CTSRTS 67# define CONFIG_SERIAL_BFIN_CTSRTS
68 68
69# ifndef CONFIG_UART0_CTS_PIN 69# ifndef CONFIG_UART0_CTS_PIN
@@ -74,12 +74,12 @@
74# define CONFIG_UART0_RTS_PIN -1 74# define CONFIG_UART0_RTS_PIN -1
75# endif 75# endif
76 76
77# ifndef CONFIG_UART1_CTS_PIN 77# ifndef CONFIG_UART2_CTS_PIN
78# define CONFIG_UART1_CTS_PIN -1 78# define CONFIG_UART2_CTS_PIN -1
79# endif 79# endif
80 80
81# ifndef CONFIG_UART1_RTS_PIN 81# ifndef CONFIG_UART2_RTS_PIN
82# define CONFIG_UART1_RTS_PIN -1 82# define CONFIG_UART2_RTS_PIN -1
83# endif 83# endif
84#endif 84#endif
85 85
@@ -130,7 +130,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
130 CH_UART0_TX, 130 CH_UART0_TX,
131 CH_UART0_RX, 131 CH_UART0_RX,
132#endif 132#endif
133#ifdef CONFIG_BFIN_UART0_CTSRTS 133#ifdef CONFIG_SERIAL_BFIN_CTSRTS
134 CONFIG_UART0_CTS_PIN, 134 CONFIG_UART0_CTS_PIN,
135 CONFIG_UART0_RTS_PIN, 135 CONFIG_UART0_RTS_PIN,
136#endif 136#endif
@@ -144,6 +144,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
144 CH_UART1_TX, 144 CH_UART1_TX,
145 CH_UART1_RX, 145 CH_UART1_RX,
146#endif 146#endif
147#ifdef CONFIG_SERIAL_BFIN_CTSRTS
148 0,
149 0,
150#endif
147 }, 151 },
148#endif 152#endif
149#ifdef CONFIG_SERIAL_BFIN_UART2 153#ifdef CONFIG_SERIAL_BFIN_UART2
@@ -154,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
154 CH_UART2_TX, 158 CH_UART2_TX,
155 CH_UART2_RX, 159 CH_UART2_RX,
156#endif 160#endif
157#ifdef CONFIG_BFIN_UART2_CTSRTS 161#ifdef CONFIG_SERIAL_BFIN_CTSRTS
158 CONFIG_UART2_CTS_PIN, 162 CONFIG_UART2_CTS_PIN,
159 CONFIG_UART2_RTS_PIN, 163 CONFIG_UART2_RTS_PIN,
160#endif 164#endif
@@ -168,6 +172,10 @@ struct bfin_serial_res bfin_serial_resource[] = {
168 CH_UART3_TX, 172 CH_UART3_TX,
169 CH_UART3_RX, 173 CH_UART3_RX,
170#endif 174#endif
175#ifdef CONFIG_SERIAL_BFIN_CTSRTS
176 0,
177 0,
178#endif
171 }, 179 },
172#endif 180#endif
173}; 181};
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 60299a71e090..f194625f6821 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -123,8 +123,8 @@ Events (highest priority) EMU 0
123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ 123#define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */
124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ 124#define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */
125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ 125#define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */
126#define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ 126#define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */
127#define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ 127#define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */
128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ 128#define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */
129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ 129#define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */
130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ 130#define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */
@@ -361,8 +361,8 @@ Events (highest priority) EMU 0
361#define IRQ_UART2_ERR IRQ_UART2_ERROR 361#define IRQ_UART2_ERR IRQ_UART2_ERROR
362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR 362#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR 363#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
364#define IRQ_EPP1_ERR IRQ_EPP1_ERROR 364#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
365#define IRQ_EPP2_ERR IRQ_EPP2_ERROR 365#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
366#define IRQ_UART3_ERR IRQ_UART3_ERROR 366#define IRQ_UART3_ERR IRQ_UART3_ERROR
367#define IRQ_HOST_ERR IRQ_HOST_ERROR 367#define IRQ_HOST_ERR IRQ_HOST_ERROR
368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR 368#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig
index e41a67b1fb53..e4bc6d7c5a6a 100644
--- a/arch/blackfin/mach-bf561/boards/Kconfig
+++ b/arch/blackfin/mach-bf561/boards/Kconfig
@@ -19,9 +19,4 @@ config BFIN561_BLUETECHNIX_CM
19 help 19 help
20 CM-BF561 support for EVAL- and DEV-Board. 20 CM-BF561 support for EVAL- and DEV-Board.
21 21
22config GENERIC_BF561_BOARD
23 bool "Generic"
24 help
25 Generic or Custom board support.
26
27endchoice 22endchoice
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile
index 04add010b568..3a152559e957 100644
--- a/arch/blackfin/mach-bf561/boards/Makefile
+++ b/arch/blackfin/mach-bf561/boards/Makefile
@@ -2,7 +2,6 @@
2# arch/blackfin/mach-bf561/boards/Makefile 2# arch/blackfin/mach-bf561/boards/Makefile
3# 3#
4 4
5obj-$(CONFIG_GENERIC_BF561_BOARD) += generic_board.o
6obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o 5obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o
7obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o 6obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o
8obj-$(CONFIG_BFIN561_TEPLA) += tepla.o 7obj-$(CONFIG_BFIN561_TEPLA) += tepla.o
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c
index 6880d1ebfe60..f623c6b0719f 100644
--- a/arch/blackfin/mach-bf561/boards/cm_bf561.c
+++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c
@@ -105,9 +105,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = {
105}; 105};
106#endif 106#endif
107 107
108#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 108#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
109static struct bfin5xx_spi_chip spi_mmc_chip_info = { 109static struct bfin5xx_spi_chip mmc_spi_chip_info = {
110 .enable_dma = 1, 110 .enable_dma = 0,
111 .bits_per_word = 8, 111 .bits_per_word = 8,
112}; 112};
113#endif 113#endif
@@ -155,14 +155,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
155 .controller_data = &ad9960_spi_chip_info, 155 .controller_data = &ad9960_spi_chip_info,
156 }, 156 },
157#endif 157#endif
158#if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) 158#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
159 { 159 {
160 .modalias = "spi_mmc", 160 .modalias = "mmc_spi",
161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 161 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */
162 .bus_num = 0, 162 .bus_num = 0,
163 .chip_select = CONFIG_SPI_MMC_CS_CHAN, 163 .chip_select = 5,
164 .platform_data = NULL, 164 .controller_data = &mmc_spi_chip_info,
165 .controller_data = &spi_mmc_chip_info,
166 .mode = SPI_MODE_3, 165 .mode = SPI_MODE_3,
167 }, 166 },
168#endif 167#endif
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c
deleted file mode 100644
index 0ba366a0e696..000000000000
--- a/arch/blackfin/mach-bf561/boards/generic_board.c
+++ /dev/null
@@ -1,113 +0,0 @@
1/*
2 * File: arch/blackfin/mach-bf561/generic_board.c
3 * Based on: arch/blackfin/mach-bf533/ezkit.c
4 * Author: Aidan Williams <aidan@nicta.com.au>
5 *
6 * Created:
7 * Description:
8 *
9 * Modified:
10 * Copyright 2005 National ICT Australia (NICTA)
11 * Copyright 2004-2006 Analog Devices Inc.
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, see the file COPYING, or write
27 * to the Free Software Foundation, Inc.,
28 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 */
30
31#include <linux/device.h>
32#include <linux/platform_device.h>
33#include <linux/irq.h>
34
35const char bfin_board_name[] = "UNKNOWN BOARD";
36
37/*
38 * Driver needs to know address, irq and flag pin.
39 */
40#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
41static struct resource smc91x_resources[] = {
42 {
43 .start = 0x2C010300,
44 .end = 0x2C010300 + 16,
45 .flags = IORESOURCE_MEM,
46 }, {
47 .start = IRQ_PROG_INTB,
48 .end = IRQ_PROG_INTB,
49 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
50 }, {
51 .start = IRQ_PF9,
52 .end = IRQ_PF9,
53 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
54 },
55};
56
57static struct platform_device smc91x_device = {
58 .name = "smc91x",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(smc91x_resources),
61 .resource = smc91x_resources,
62};
63#endif
64
65#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
66#ifdef CONFIG_BFIN_SIR0
67static struct resource bfin_sir0_resources[] = {
68 {
69 .start = 0xFFC00400,
70 .end = 0xFFC004FF,
71 .flags = IORESOURCE_MEM,
72 },
73 {
74 .start = IRQ_UART0_RX,
75 .end = IRQ_UART0_RX+1,
76 .flags = IORESOURCE_IRQ,
77 },
78 {
79 .start = CH_UART0_RX,
80 .end = CH_UART0_RX+1,
81 .flags = IORESOURCE_DMA,
82 },
83};
84
85static struct platform_device bfin_sir0_device = {
86 .name = "bfin_sir",
87 .id = 0,
88 .num_resources = ARRAY_SIZE(bfin_sir0_resources),
89 .resource = bfin_sir0_resources,
90};
91#endif
92#endif
93
94static struct platform_device *generic_board_devices[] __initdata = {
95#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
96 &smc91x_device,
97#endif
98
99#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
100#ifdef CONFIG_BFIN_SIR0
101 &bfin_sir0_device,
102#endif
103#endif
104};
105
106static int __init generic_board_init(void)
107{
108 printk(KERN_INFO "%s(): registering device resources\n", __func__);
109 return platform_add_devices(generic_board_devices,
110 ARRAY_SIZE(generic_board_devices));
111}
112
113arch_initcall(generic_board_init);
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 1a9e17562821..d0b0b3506440 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf561/anomaly.h 2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -224,7 +224,7 @@
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
@@ -283,8 +283,11 @@
283#define ANOMALY_05000273 (0) 283#define ANOMALY_05000273 (0)
284#define ANOMALY_05000311 (0) 284#define ANOMALY_05000311 (0)
285#define ANOMALY_05000353 (1) 285#define ANOMALY_05000353 (1)
286#define ANOMALY_05000380 (0)
286#define ANOMALY_05000386 (1) 287#define ANOMALY_05000386 (1)
287#define ANOMALY_05000432 (0) 288#define ANOMALY_05000432 (0)
288#define ANOMALY_05000435 (0) 289#define ANOMALY_05000435 (0)
290#define ANOMALY_05000447 (0)
291#define ANOMALY_05000448 (0)
289 292
290#endif 293#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
index 043bfcf26c52..ca8c5f645209 100644
--- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
+++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h
@@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = {
134 CH_UART_TX, 134 CH_UART_TX,
135 CH_UART_RX, 135 CH_UART_RX,
136#endif 136#endif
137#ifdef CONFIG_BFIN_UART0_CTSRTS 137#ifdef CONFIG_SERIAL_BFIN_CTSRTS
138 CONFIG_UART0_CTS_PIN, 138 CONFIG_UART0_CTS_PIN,
139 CONFIG_UART0_RTS_PIN, 139 CONFIG_UART0_RTS_PIN,
140#endif 140#endif
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c
index 98133b968f7b..80d39b2f9db2 100644
--- a/arch/blackfin/mach-common/arch_checks.c
+++ b/arch/blackfin/mach-common/arch_checks.c
@@ -62,3 +62,12 @@
62#if (CONFIG_BOOT_LOAD & 0x3) 62#if (CONFIG_BOOT_LOAD & 0x3)
63# error "The kernel load address must be 4 byte aligned" 63# error "The kernel load address must be 4 byte aligned"
64#endif 64#endif
65
66/* The entire kernel must be able to make a 24bit pcrel call to start of L1 */
67#if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000
68# error "The kernel load address is too high; keep it below 10meg for safety"
69#endif
70
71#if ANOMALY_05000448
72# error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes.
73#endif
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S
index 3c98dacbf289..aa0648c6a9fe 100644
--- a/arch/blackfin/mach-common/cache.S
+++ b/arch/blackfin/mach-common/cache.S
@@ -66,11 +66,33 @@
66 66
67/* Invalidate all instruction cache lines assocoiated with this memory area */ 67/* Invalidate all instruction cache lines assocoiated with this memory area */
68ENTRY(_blackfin_icache_flush_range) 68ENTRY(_blackfin_icache_flush_range)
69/*
70 * Walkaround to avoid loading wrong instruction after invalidating icache
71 * and following sequence is met.
72 *
73 * 1) One instruction address is cached in the instruction cache.
74 * 2) This instruction in SDRAM is changed.
75 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
76 * 4) This instruction is executed again, but the old one is loaded.
77 */
78 P0 = R0;
79 IFLUSH[P0];
69 do_flush IFLUSH, , nop 80 do_flush IFLUSH, , nop
70ENDPROC(_blackfin_icache_flush_range) 81ENDPROC(_blackfin_icache_flush_range)
71 82
72/* Flush all cache lines assocoiated with this area of memory. */ 83/* Flush all cache lines assocoiated with this area of memory. */
73ENTRY(_blackfin_icache_dcache_flush_range) 84ENTRY(_blackfin_icache_dcache_flush_range)
85/*
86 * Walkaround to avoid loading wrong instruction after invalidating icache
87 * and following sequence is met.
88 *
89 * 1) One instruction address is cached in the instruction cache.
90 * 2) This instruction in SDRAM is changed.
91 * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range().
92 * 4) This instruction is executed again, but the old one is loaded.
93 */
94 P0 = R0;
95 IFLUSH[P0];
74 do_flush FLUSH, IFLUSH 96 do_flush FLUSH, IFLUSH
75ENDPROC(_blackfin_icache_dcache_flush_range) 97ENDPROC(_blackfin_icache_dcache_flush_range)
76 98
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 9dddb6f8cc85..35393651359b 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -17,7 +17,7 @@
17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ 17#define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */
18#define PLL_CTL_VAL \ 18#define PLL_CTL_VAL \
19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ 19 (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
20 (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) 20 (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000))
21 21
22__attribute__((l1_text)) 22__attribute__((l1_text))
23static void do_sync(void) 23static void do_sync(void)
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S
index 4da50bcd9300..8009a512fb11 100644
--- a/arch/blackfin/mach-common/dpmc_modes.S
+++ b/arch/blackfin/mach-common/dpmc_modes.S
@@ -376,10 +376,22 @@ ENTRY(_do_hibernate)
376#endif 376#endif
377 377
378#ifdef PINT0_ASSIGN 378#ifdef PINT0_ASSIGN
379 PM_SYS_PUSH(PINT0_MASK_SET)
380 PM_SYS_PUSH(PINT1_MASK_SET)
381 PM_SYS_PUSH(PINT2_MASK_SET)
382 PM_SYS_PUSH(PINT3_MASK_SET)
379 PM_SYS_PUSH(PINT0_ASSIGN) 383 PM_SYS_PUSH(PINT0_ASSIGN)
380 PM_SYS_PUSH(PINT1_ASSIGN) 384 PM_SYS_PUSH(PINT1_ASSIGN)
381 PM_SYS_PUSH(PINT2_ASSIGN) 385 PM_SYS_PUSH(PINT2_ASSIGN)
382 PM_SYS_PUSH(PINT3_ASSIGN) 386 PM_SYS_PUSH(PINT3_ASSIGN)
387 PM_SYS_PUSH(PINT0_INVERT_SET)
388 PM_SYS_PUSH(PINT1_INVERT_SET)
389 PM_SYS_PUSH(PINT2_INVERT_SET)
390 PM_SYS_PUSH(PINT3_INVERT_SET)
391 PM_SYS_PUSH(PINT0_EDGE_SET)
392 PM_SYS_PUSH(PINT1_EDGE_SET)
393 PM_SYS_PUSH(PINT2_EDGE_SET)
394 PM_SYS_PUSH(PINT3_EDGE_SET)
383#endif 395#endif
384 396
385 PM_SYS_PUSH(EBIU_AMBCTL0) 397 PM_SYS_PUSH(EBIU_AMBCTL0)
@@ -714,10 +726,22 @@ ENTRY(_do_hibernate)
714 PM_SYS_POP(EBIU_AMBCTL0) 726 PM_SYS_POP(EBIU_AMBCTL0)
715 727
716#ifdef PINT0_ASSIGN 728#ifdef PINT0_ASSIGN
729 PM_SYS_POP(PINT3_EDGE_SET)
730 PM_SYS_POP(PINT2_EDGE_SET)
731 PM_SYS_POP(PINT1_EDGE_SET)
732 PM_SYS_POP(PINT0_EDGE_SET)
733 PM_SYS_POP(PINT3_INVERT_SET)
734 PM_SYS_POP(PINT2_INVERT_SET)
735 PM_SYS_POP(PINT1_INVERT_SET)
736 PM_SYS_POP(PINT0_INVERT_SET)
717 PM_SYS_POP(PINT3_ASSIGN) 737 PM_SYS_POP(PINT3_ASSIGN)
718 PM_SYS_POP(PINT2_ASSIGN) 738 PM_SYS_POP(PINT2_ASSIGN)
719 PM_SYS_POP(PINT1_ASSIGN) 739 PM_SYS_POP(PINT1_ASSIGN)
720 PM_SYS_POP(PINT0_ASSIGN) 740 PM_SYS_POP(PINT0_ASSIGN)
741 PM_SYS_POP(PINT3_MASK_SET)
742 PM_SYS_POP(PINT2_MASK_SET)
743 PM_SYS_POP(PINT1_MASK_SET)
744 PM_SYS_POP(PINT0_MASK_SET)
721#endif 745#endif
722 746
723#ifdef SICA_IWR1 747#ifdef SICA_IWR1
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 88de053bbe8e..21e65a339a22 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -600,6 +600,19 @@ ENTRY(_system_call)
600 p2 = [p2]; 600 p2 = [p2];
601 601
602 [p2+(TASK_THREAD+THREAD_KSP)] = sp; 602 [p2+(TASK_THREAD+THREAD_KSP)] = sp;
603#ifdef CONFIG_IPIPE
604 r0 = sp;
605 SP += -12;
606 call ___ipipe_syscall_root;
607 SP += 12;
608 cc = r0 == 1;
609 if cc jump .Lsyscall_really_exit;
610 cc = r0 == -1;
611 if cc jump .Lresume_userspace;
612 r3 = [sp + PT_R3];
613 r4 = [sp + PT_R4];
614 p0 = [sp + PT_ORIG_P0];
615#endif /* CONFIG_IPIPE */
603 616
604 /* Check the System Call */ 617 /* Check the System Call */
605 r7 = __NR_syscall; 618 r7 = __NR_syscall;
@@ -654,6 +667,17 @@ ENTRY(_system_call)
654 r7 = r7 & r4; 667 r7 = r7 & r4;
655 668
656.Lsyscall_resched: 669.Lsyscall_resched:
670#ifdef CONFIG_IPIPE
671 cc = BITTST(r7, TIF_IRQ_SYNC);
672 if !cc jump .Lsyscall_no_irqsync;
673 [--sp] = reti;
674 r0 = [sp++];
675 SP += -12;
676 call ___ipipe_sync_root;
677 SP += 12;
678 jump .Lresume_userspace_1;
679.Lsyscall_no_irqsync:
680#endif
657 cc = BITTST(r7, TIF_NEED_RESCHED); 681 cc = BITTST(r7, TIF_NEED_RESCHED);
658 if !cc jump .Lsyscall_sigpending; 682 if !cc jump .Lsyscall_sigpending;
659 683
@@ -685,6 +709,10 @@ ENTRY(_system_call)
685.Lsyscall_really_exit: 709.Lsyscall_really_exit:
686 r5 = [sp + PT_RESERVED]; 710 r5 = [sp + PT_RESERVED];
687 rets = r5; 711 rets = r5;
712#ifdef CONFIG_IPIPE
713 [--sp] = reti;
714 r5 = [sp++];
715#endif /* CONFIG_IPIPE */
688 rts; 716 rts;
689ENDPROC(_system_call) 717ENDPROC(_system_call)
690 718
@@ -771,6 +799,15 @@ _new_old_task:
771ENDPROC(_resume) 799ENDPROC(_resume)
772 800
773ENTRY(_ret_from_exception) 801ENTRY(_ret_from_exception)
802#ifdef CONFIG_IPIPE
803 [--sp] = rets;
804 SP += -12;
805 call ___ipipe_check_root
806 SP += 12
807 rets = [sp++];
808 cc = r0 == 0;
809 if cc jump 4f; /* not on behalf of Linux, get out */
810#endif /* CONFIG_IPIPE */
774 p2.l = lo(IPEND); 811 p2.l = lo(IPEND);
775 p2.h = hi(IPEND); 812 p2.h = hi(IPEND);
776 813
@@ -827,6 +864,28 @@ ENTRY(_ret_from_exception)
827 rts; 864 rts;
828ENDPROC(_ret_from_exception) 865ENDPROC(_ret_from_exception)
829 866
867#ifdef CONFIG_IPIPE
868
869_sync_root_irqs:
870 [--sp] = reti; /* Reenable interrupts */
871 r0 = [sp++];
872 jump.l ___ipipe_sync_root
873
874_resume_kernel_from_int:
875 r0.l = _sync_root_irqs
876 r0.h = _sync_root_irqs
877 [--sp] = rets;
878 [--sp] = ( r7:4, p5:3 );
879 SP += -12;
880 call ___ipipe_call_irqtail
881 SP += 12;
882 ( r7:4, p5:3 ) = [sp++];
883 rets = [sp++];
884 rts
885#else
886#define _resume_kernel_from_int 2f
887#endif
888
830ENTRY(_return_from_int) 889ENTRY(_return_from_int)
831 /* If someone else already raised IRQ 15, do nothing. */ 890 /* If someone else already raised IRQ 15, do nothing. */
832 csync; 891 csync;
@@ -848,7 +907,7 @@ ENTRY(_return_from_int)
848 r1 = r0 - r1; 907 r1 = r0 - r1;
849 r2 = r0 & r1; 908 r2 = r0 & r1;
850 cc = r2 == 0; 909 cc = r2 == 0;
851 if !cc jump 2f; 910 if !cc jump _resume_kernel_from_int;
852 911
853 /* Lower the interrupt level to 15. */ 912 /* Lower the interrupt level to 15. */
854 p0.l = lo(EVT15); 913 p0.l = lo(EVT15);
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S
index 43c4eb9acb65..0069c2dd4625 100644
--- a/arch/blackfin/mach-common/interrupt.S
+++ b/arch/blackfin/mach-common/interrupt.S
@@ -235,6 +235,7 @@ ENDPROC(_evt_system_call)
235 235
236#ifdef CONFIG_IPIPE 236#ifdef CONFIG_IPIPE
237ENTRY(___ipipe_call_irqtail) 237ENTRY(___ipipe_call_irqtail)
238 p0 = r0;
238 r0.l = 1f; 239 r0.l = 1f;
239 r0.h = 1f; 240 r0.h = 1f;
240 reti = r0; 241 reti = r0;
@@ -242,9 +243,6 @@ ENTRY(___ipipe_call_irqtail)
2421: 2431:
243 [--sp] = rets; 244 [--sp] = rets;
244 [--sp] = ( r7:4, p5:3 ); 245 [--sp] = ( r7:4, p5:3 );
245 p0.l = ___ipipe_irq_tail_hook;
246 p0.h = ___ipipe_irq_tail_hook;
247 p0 = [p0];
248 sp += -12; 246 sp += -12;
249 call (p0); 247 call (p0);
250 sp += 12; 248 sp += 12;
@@ -259,7 +257,7 @@ ENTRY(___ipipe_call_irqtail)
259 p0.h = hi(EVT14); 257 p0.h = hi(EVT14);
260 [p0] = r0; 258 [p0] = r0;
261 csync; 259 csync;
262 r0 = 0x401f; 260 r0 = 0x401f (z);
263 sti r0; 261 sti r0;
264 raise 14; 262 raise 14;
265 [--sp] = reti; /* IRQs on. */ 263 [--sp] = reti; /* IRQs on. */
@@ -277,11 +275,7 @@ ENTRY(___ipipe_call_irqtail)
277 p0.h = _bfin_irq_flags; 275 p0.h = _bfin_irq_flags;
278 r0 = [p0]; 276 r0 = [p0];
279 sti r0; 277 sti r0;
280#if 0 /* FIXME: this actually raises scheduling latencies */
281 /* Reenable interrupts */
282 [--sp] = reti;
283 r0 = [sp++];
284#endif
285 rts; 278 rts;
286ENDPROC(___ipipe_call_irqtail) 279ENDPROC(___ipipe_call_irqtail)
280
287#endif /* CONFIG_IPIPE */ 281#endif /* CONFIG_IPIPE */
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 202494568c6c..a7d7b2dd4059 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -161,11 +161,15 @@ static void bfin_core_unmask_irq(unsigned int irq)
161 161
162static void bfin_internal_mask_irq(unsigned int irq) 162static void bfin_internal_mask_irq(unsigned int irq)
163{ 163{
164 unsigned long flags;
165
164#ifdef CONFIG_BF53x 166#ifdef CONFIG_BF53x
167 local_irq_save_hw(flags);
165 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & 168 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
166 ~(1 << SIC_SYSIRQ(irq))); 169 ~(1 << SIC_SYSIRQ(irq)));
167#else 170#else
168 unsigned mask_bank, mask_bit; 171 unsigned mask_bank, mask_bit;
172 local_irq_save_hw(flags);
169 mask_bank = SIC_SYSIRQ(irq) / 32; 173 mask_bank = SIC_SYSIRQ(irq) / 32;
170 mask_bit = SIC_SYSIRQ(irq) % 32; 174 mask_bit = SIC_SYSIRQ(irq) % 32;
171 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & 175 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
@@ -175,15 +179,20 @@ static void bfin_internal_mask_irq(unsigned int irq)
175 ~(1 << mask_bit)); 179 ~(1 << mask_bit));
176#endif 180#endif
177#endif 181#endif
182 local_irq_restore_hw(flags);
178} 183}
179 184
180static void bfin_internal_unmask_irq(unsigned int irq) 185static void bfin_internal_unmask_irq(unsigned int irq)
181{ 186{
187 unsigned long flags;
188
182#ifdef CONFIG_BF53x 189#ifdef CONFIG_BF53x
190 local_irq_save_hw(flags);
183 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 191 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
184 (1 << SIC_SYSIRQ(irq))); 192 (1 << SIC_SYSIRQ(irq)));
185#else 193#else
186 unsigned mask_bank, mask_bit; 194 unsigned mask_bank, mask_bit;
195 local_irq_save_hw(flags);
187 mask_bank = SIC_SYSIRQ(irq) / 32; 196 mask_bank = SIC_SYSIRQ(irq) / 32;
188 mask_bit = SIC_SYSIRQ(irq) % 32; 197 mask_bit = SIC_SYSIRQ(irq) % 32;
189 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | 198 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
@@ -193,6 +202,7 @@ static void bfin_internal_unmask_irq(unsigned int irq)
193 (1 << mask_bit)); 202 (1 << mask_bit));
194#endif 203#endif
195#endif 204#endif
205 local_irq_restore_hw(flags);
196} 206}
197 207
198#ifdef CONFIG_PM 208#ifdef CONFIG_PM
@@ -390,7 +400,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq,
390static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) 400static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
391{ 401{
392#ifdef CONFIG_IPIPE 402#ifdef CONFIG_IPIPE
393 _set_irq_handler(irq, handle_edge_irq); 403 _set_irq_handler(irq, handle_level_irq);
394#else 404#else
395 struct irq_desc *desc = irq_desc + irq; 405 struct irq_desc *desc = irq_desc + irq;
396 /* May not call generic set_irq_handler() due to spinlock 406 /* May not call generic set_irq_handler() due to spinlock
@@ -1055,13 +1065,18 @@ int __init init_arch_irq(void)
1055#endif 1065#endif
1056 default: 1066 default:
1057#ifdef CONFIG_IPIPE 1067#ifdef CONFIG_IPIPE
1058 /* 1068 /*
1059 * We want internal interrupt sources to be masked, because 1069 * We want internal interrupt sources to be
1060 * ISRs may trigger interrupts recursively (e.g. DMA), but 1070 * masked, because ISRs may trigger interrupts
1061 * interrupts are _not_ masked at CPU level. So let's handle 1071 * recursively (e.g. DMA), but interrupts are
1062 * them as level interrupts. 1072 * _not_ masked at CPU level. So let's handle
1063 */ 1073 * most of them as level interrupts, except
1064 set_irq_handler(irq, handle_level_irq); 1074 * the timer interrupt which is special.
1075 */
1076 if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR)
1077 set_irq_handler(irq, handle_simple_irq);
1078 else
1079 set_irq_handler(irq, handle_level_irq);
1065#else /* !CONFIG_IPIPE */ 1080#else /* !CONFIG_IPIPE */
1066 set_irq_handler(irq, handle_simple_irq); 1081 set_irq_handler(irq, handle_simple_irq);
1067#endif /* !CONFIG_IPIPE */ 1082#endif /* !CONFIG_IPIPE */
@@ -1123,9 +1138,8 @@ int __init init_arch_irq(void)
1123 1138
1124#ifdef CONFIG_IPIPE 1139#ifdef CONFIG_IPIPE
1125 for (irq = 0; irq < NR_IRQS; irq++) { 1140 for (irq = 0; irq < NR_IRQS; irq++) {
1126 struct irq_desc *desc = irq_desc + irq; 1141 struct irq_desc *desc = irq_to_desc(irq);
1127 desc->ic_prio = __ipipe_get_irq_priority(irq); 1142 desc->ic_prio = __ipipe_get_irq_priority(irq);
1128 desc->thr_prio = __ipipe_get_irqthread_priority(irq);
1129 } 1143 }
1130#endif /* CONFIG_IPIPE */ 1144#endif /* CONFIG_IPIPE */
1131 1145
@@ -1208,76 +1222,21 @@ int __ipipe_get_irq_priority(unsigned irq)
1208 return IVG15; 1222 return IVG15;
1209} 1223}
1210 1224
1211int __ipipe_get_irqthread_priority(unsigned irq)
1212{
1213 int ient, prio;
1214 int demux_irq;
1215
1216 /* The returned priority value is rescaled to [0..IVG13+1]
1217 * with 0 being the lowest effective priority level. */
1218
1219 if (irq <= IRQ_CORETMR)
1220 return IVG13 - irq + 1;
1221
1222 /* GPIO IRQs are given the priority of the demux
1223 * interrupt. */
1224 if (IS_GPIOIRQ(irq)) {
1225#if defined(CONFIG_BF54x)
1226 u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]);
1227 demux_irq = (bank == 0 ? IRQ_PINT0 :
1228 bank == 1 ? IRQ_PINT1 :
1229 bank == 2 ? IRQ_PINT2 :
1230 IRQ_PINT3);
1231#elif defined(CONFIG_BF561)
1232 demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA :
1233 irq >= IRQ_PF16 ? IRQ_PROG1_INTA :
1234 IRQ_PROG0_INTA);
1235#elif defined(CONFIG_BF52x)
1236 demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA :
1237 irq >= IRQ_PG0 ? IRQ_PORTG_INTA :
1238 IRQ_PORTF_INTA);
1239#else
1240 demux_irq = irq;
1241#endif
1242 return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1;
1243 }
1244
1245 /* The GPIO demux interrupt is given a lower priority
1246 * than the GPIO IRQs, so that its threaded handler
1247 * unmasks the interrupt line after the decoded IRQs
1248 * have been processed. */
1249 prio = PRIO_GPIODEMUX(irq);
1250 /* demux irq? */
1251 if (prio != -1)
1252 return IVG13 - prio;
1253
1254 for (ient = 0; ient < NR_PERI_INTS; ient++) {
1255 struct ivgx *ivg = ivg_table + ient;
1256 if (ivg->irqno == irq) {
1257 for (prio = 0; prio <= IVG13-IVG7; prio++) {
1258 if (ivg7_13[prio].ifirst <= ivg &&
1259 ivg7_13[prio].istop > ivg)
1260 return IVG7 - prio;
1261 }
1262 }
1263 }
1264
1265 return 0;
1266}
1267
1268/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ 1225/* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1269#ifdef CONFIG_DO_IRQ_L1 1226#ifdef CONFIG_DO_IRQ_L1
1270__attribute__((l1_text)) 1227__attribute__((l1_text))
1271#endif 1228#endif
1272asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) 1229asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1273{ 1230{
1231 struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1232 struct ipipe_domain *this_domain = ipipe_current_domain;
1274 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; 1233 struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
1275 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; 1234 struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
1276 int irq; 1235 int irq, s;
1277 1236
1278 if (likely(vec == EVT_IVTMR_P)) { 1237 if (likely(vec == EVT_IVTMR_P)) {
1279 irq = IRQ_CORETMR; 1238 irq = IRQ_CORETMR;
1280 goto handle_irq; 1239 goto core_tick;
1281 } 1240 }
1282 1241
1283 SSYNC(); 1242 SSYNC();
@@ -1319,24 +1278,39 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1319 irq = ivg->irqno; 1278 irq = ivg->irqno;
1320 1279
1321 if (irq == IRQ_SYSTMR) { 1280 if (irq == IRQ_SYSTMR) {
1281#ifdef CONFIG_GENERIC_CLOCKEVENTS
1282core_tick:
1283#else
1322 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ 1284 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1285#endif
1323 /* This is basically what we need from the register frame. */ 1286 /* This is basically what we need from the register frame. */
1324 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; 1287 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1325 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; 1288 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1326 if (!ipipe_root_domain_p) 1289 if (this_domain != ipipe_root_domain)
1327 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1328 else
1329 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; 1290 __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1291 else
1292 __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1330 } 1293 }
1331 1294
1332handle_irq: 1295#ifndef CONFIG_GENERIC_CLOCKEVENTS
1296core_tick:
1297#endif
1298 if (this_domain == ipipe_root_domain) {
1299 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1300 barrier();
1301 }
1333 1302
1334 ipipe_trace_irq_entry(irq); 1303 ipipe_trace_irq_entry(irq);
1335 __ipipe_handle_irq(irq, regs); 1304 __ipipe_handle_irq(irq, regs);
1336 ipipe_trace_irq_exit(irq); 1305 ipipe_trace_irq_exit(irq);
1337 1306
1338 if (ipipe_root_domain_p) 1307 if (this_domain == ipipe_root_domain) {
1339 return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); 1308 set_thread_flag(TIF_IRQ_SYNC);
1309 if (!s) {
1310 __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1311 return !test_bit(IPIPE_STALL_FLAG, &p->status);
1312 }
1313 }
1340 1314
1341 return 0; 1315 return 0;
1342} 1316}
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 77c992847094..93eab6146079 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -158,10 +158,14 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance)
158 kfree(msg); 158 kfree(msg);
159 break; 159 break;
160 case BFIN_IPI_CALL_FUNC: 160 case BFIN_IPI_CALL_FUNC:
161 spin_unlock(&msg_queue->lock);
161 ipi_call_function(cpu, msg); 162 ipi_call_function(cpu, msg);
163 spin_lock(&msg_queue->lock);
162 break; 164 break;
163 case BFIN_IPI_CPU_STOP: 165 case BFIN_IPI_CPU_STOP:
166 spin_unlock(&msg_queue->lock);
164 ipi_cpu_stop(cpu); 167 ipi_cpu_stop(cpu);
168 spin_lock(&msg_queue->lock);
165 kfree(msg); 169 kfree(msg);
166 break; 170 break;
167 default: 171 default:
@@ -457,7 +461,7 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end)
457 smp_flush_data.start = start; 461 smp_flush_data.start = start;
458 smp_flush_data.end = end; 462 smp_flush_data.end = end;
459 463
460 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) 464 if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0))
461 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); 465 printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n");
462} 466}
463EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); 467EXPORT_SYMBOL_GPL(smp_icache_flush_range_others);
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c
index d0532b72bba5..9c3629b9a689 100644
--- a/arch/blackfin/mm/init.c
+++ b/arch/blackfin/mm/init.c
@@ -104,7 +104,7 @@ void __init paging_init(void)
104 } 104 }
105} 105}
106 106
107asmlinkage void init_pda(void) 107asmlinkage void __init init_pda(void)
108{ 108{
109 unsigned int cpu = raw_smp_processor_id(); 109 unsigned int cpu = raw_smp_processor_id();
110 110
diff --git a/arch/frv/mm/dma-alloc.c b/arch/frv/mm/dma-alloc.c
index dc6522c464d4..44840e73e907 100644
--- a/arch/frv/mm/dma-alloc.c
+++ b/arch/frv/mm/dma-alloc.c
@@ -36,10 +36,10 @@
36#include <linux/vmalloc.h> 36#include <linux/vmalloc.h>
37#include <linux/init.h> 37#include <linux/init.h>
38#include <linux/pci.h> 38#include <linux/pci.h>
39#include <linux/hardirq.h>
39 40
40#include <asm/pgalloc.h> 41#include <asm/pgalloc.h>
41#include <asm/io.h> 42#include <asm/io.h>
42#include <asm/hardirq.h>
43#include <asm/mmu_context.h> 43#include <asm/mmu_context.h>
44#include <asm/pgtable.h> 44#include <asm/pgtable.h>
45#include <asm/mmu.h> 45#include <asm/mmu.h>
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 6183aeccecf1..153e727a6e8e 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -221,7 +221,11 @@ config IA64_HP_SIM
221 221
222config IA64_XEN_GUEST 222config IA64_XEN_GUEST
223 bool "Xen guest" 223 bool "Xen guest"
224 select SWIOTLB
224 depends on XEN 225 depends on XEN
226 help
227 Build a kernel that runs on Xen guest domain. At this moment only
228 16KB page size in supported.
225 229
226endchoice 230endchoice
227 231
@@ -479,8 +483,7 @@ config HOLES_IN_ZONE
479 default y if VIRTUAL_MEM_MAP 483 default y if VIRTUAL_MEM_MAP
480 484
481config HAVE_ARCH_EARLY_PFN_TO_NID 485config HAVE_ARCH_EARLY_PFN_TO_NID
482 def_bool y 486 def_bool NUMA && SPARSEMEM
483 depends on NEED_MULTIPLE_NODES
484 487
485config HAVE_ARCH_NODEDATA_EXTENSION 488config HAVE_ARCH_NODEDATA_EXTENSION
486 def_bool y 489 def_bool y
@@ -635,6 +638,17 @@ config DMAR
635 and include PCI device scope covered by these DMA 638 and include PCI device scope covered by these DMA
636 remapping devices. 639 remapping devices.
637 640
641config DMAR_DEFAULT_ON
642 def_bool y
643 prompt "Enable DMA Remapping Devices by default"
644 depends on DMAR
645 help
646 Selecting this option will enable a DMAR device at boot time if
647 one is found. If this option is not selected, DMAR support can
648 be enabled by passing intel_iommu=on to the kernel. It is
649 recommended you say N here while the DMAR code remains
650 experimental.
651
638endmenu 652endmenu
639 653
640endif 654endif
diff --git a/arch/ia64/configs/xen_domu_defconfig b/arch/ia64/configs/xen_domu_defconfig
new file mode 100644
index 000000000000..0bb0714dc19d
--- /dev/null
+++ b/arch/ia64/configs/xen_domu_defconfig
@@ -0,0 +1,1601 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc1
4# Fri Jan 16 11:49:59 2009
5#
6CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
7
8#
9# General setup
10#
11CONFIG_EXPERIMENTAL=y
12CONFIG_LOCK_KERNEL=y
13CONFIG_INIT_ENV_ARG_LIMIT=32
14CONFIG_LOCALVERSION=""
15CONFIG_LOCALVERSION_AUTO=y
16CONFIG_SWAP=y
17CONFIG_SYSVIPC=y
18CONFIG_SYSVIPC_SYSCTL=y
19CONFIG_POSIX_MQUEUE=y
20# CONFIG_BSD_PROCESS_ACCT is not set
21# CONFIG_TASKSTATS is not set
22# CONFIG_AUDIT is not set
23CONFIG_IKCONFIG=y
24CONFIG_IKCONFIG_PROC=y
25CONFIG_LOG_BUF_SHIFT=20
26CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y
27# CONFIG_GROUP_SCHED is not set
28
29#
30# Control Group support
31#
32# CONFIG_CGROUPS is not set
33CONFIG_SYSFS_DEPRECATED=y
34CONFIG_SYSFS_DEPRECATED_V2=y
35# CONFIG_RELAY is not set
36CONFIG_NAMESPACES=y
37# CONFIG_UTS_NS is not set
38# CONFIG_IPC_NS is not set
39# CONFIG_USER_NS is not set
40# CONFIG_PID_NS is not set
41CONFIG_BLK_DEV_INITRD=y
42CONFIG_INITRAMFS_SOURCE=""
43CONFIG_CC_OPTIMIZE_FOR_SIZE=y
44CONFIG_SYSCTL=y
45# CONFIG_EMBEDDED is not set
46CONFIG_SYSCTL_SYSCALL=y
47CONFIG_KALLSYMS=y
48CONFIG_KALLSYMS_ALL=y
49CONFIG_KALLSYMS_STRIP_GENERATED=y
50# CONFIG_KALLSYMS_EXTRA_PASS is not set
51CONFIG_HOTPLUG=y
52CONFIG_PRINTK=y
53CONFIG_BUG=y
54CONFIG_ELF_CORE=y
55CONFIG_COMPAT_BRK=y
56CONFIG_BASE_FULL=y
57CONFIG_FUTEX=y
58CONFIG_ANON_INODES=y
59CONFIG_EPOLL=y
60CONFIG_SIGNALFD=y
61CONFIG_TIMERFD=y
62CONFIG_EVENTFD=y
63CONFIG_SHMEM=y
64CONFIG_AIO=y
65CONFIG_VM_EVENT_COUNTERS=y
66CONFIG_PCI_QUIRKS=y
67CONFIG_SLUB_DEBUG=y
68# CONFIG_SLAB is not set
69CONFIG_SLUB=y
70# CONFIG_SLOB is not set
71# CONFIG_PROFILING is not set
72CONFIG_HAVE_OPROFILE=y
73# CONFIG_KPROBES is not set
74CONFIG_HAVE_KPROBES=y
75CONFIG_HAVE_KRETPROBES=y
76CONFIG_HAVE_ARCH_TRACEHOOK=y
77CONFIG_HAVE_DMA_ATTRS=y
78CONFIG_USE_GENERIC_SMP_HELPERS=y
79# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
80CONFIG_SLABINFO=y
81CONFIG_RT_MUTEXES=y
82CONFIG_BASE_SMALL=0
83CONFIG_MODULES=y
84# CONFIG_MODULE_FORCE_LOAD is not set
85CONFIG_MODULE_UNLOAD=y
86# CONFIG_MODULE_FORCE_UNLOAD is not set
87CONFIG_MODVERSIONS=y
88CONFIG_MODULE_SRCVERSION_ALL=y
89CONFIG_STOP_MACHINE=y
90CONFIG_BLOCK=y
91# CONFIG_BLK_DEV_IO_TRACE is not set
92# CONFIG_BLK_DEV_BSG is not set
93# CONFIG_BLK_DEV_INTEGRITY is not set
94
95#
96# IO Schedulers
97#
98CONFIG_IOSCHED_NOOP=y
99CONFIG_IOSCHED_AS=y
100CONFIG_IOSCHED_DEADLINE=y
101CONFIG_IOSCHED_CFQ=y
102CONFIG_DEFAULT_AS=y
103# CONFIG_DEFAULT_DEADLINE is not set
104# CONFIG_DEFAULT_CFQ is not set
105# CONFIG_DEFAULT_NOOP is not set
106CONFIG_DEFAULT_IOSCHED="anticipatory"
107CONFIG_CLASSIC_RCU=y
108# CONFIG_TREE_RCU is not set
109# CONFIG_PREEMPT_RCU is not set
110# CONFIG_TREE_RCU_TRACE is not set
111# CONFIG_PREEMPT_RCU_TRACE is not set
112CONFIG_FREEZER=y
113
114#
115# Processor type and features
116#
117CONFIG_IA64=y
118CONFIG_64BIT=y
119CONFIG_ZONE_DMA=y
120CONFIG_QUICKLIST=y
121CONFIG_MMU=y
122CONFIG_SWIOTLB=y
123CONFIG_IOMMU_HELPER=y
124CONFIG_RWSEM_XCHGADD_ALGORITHM=y
125CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y
126CONFIG_GENERIC_FIND_NEXT_BIT=y
127CONFIG_GENERIC_CALIBRATE_DELAY=y
128CONFIG_GENERIC_TIME=y
129CONFIG_GENERIC_TIME_VSYSCALL=y
130CONFIG_HAVE_SETUP_PER_CPU_AREA=y
131CONFIG_DMI=y
132CONFIG_EFI=y
133CONFIG_GENERIC_IOMAP=y
134CONFIG_SCHED_OMIT_FRAME_POINTER=y
135CONFIG_AUDIT_ARCH=y
136CONFIG_PARAVIRT_GUEST=y
137CONFIG_PARAVIRT=y
138CONFIG_XEN=y
139CONFIG_XEN_XENCOMM=y
140CONFIG_NO_IDLE_HZ=y
141# CONFIG_IA64_GENERIC is not set
142# CONFIG_IA64_DIG is not set
143# CONFIG_IA64_DIG_VTD is not set
144# CONFIG_IA64_HP_ZX1 is not set
145# CONFIG_IA64_HP_ZX1_SWIOTLB is not set
146# CONFIG_IA64_SGI_SN2 is not set
147# CONFIG_IA64_SGI_UV is not set
148# CONFIG_IA64_HP_SIM is not set
149CONFIG_IA64_XEN_GUEST=y
150# CONFIG_ITANIUM is not set
151CONFIG_MCKINLEY=y
152# CONFIG_IA64_PAGE_SIZE_4KB is not set
153# CONFIG_IA64_PAGE_SIZE_8KB is not set
154CONFIG_IA64_PAGE_SIZE_16KB=y
155# CONFIG_IA64_PAGE_SIZE_64KB is not set
156CONFIG_PGTABLE_3=y
157# CONFIG_PGTABLE_4 is not set
158CONFIG_HZ=250
159# CONFIG_HZ_100 is not set
160CONFIG_HZ_250=y
161# CONFIG_HZ_300 is not set
162# CONFIG_HZ_1000 is not set
163# CONFIG_SCHED_HRTICK is not set
164CONFIG_IA64_L1_CACHE_SHIFT=7
165CONFIG_IA64_CYCLONE=y
166CONFIG_IOSAPIC=y
167CONFIG_FORCE_MAX_ZONEORDER=17
168# CONFIG_VIRT_CPU_ACCOUNTING is not set
169CONFIG_SMP=y
170CONFIG_NR_CPUS=16
171CONFIG_HOTPLUG_CPU=y
172CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
173CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
174# CONFIG_SCHED_SMT is not set
175CONFIG_PERMIT_BSP_REMOVE=y
176CONFIG_FORCE_CPEI_RETARGET=y
177CONFIG_PREEMPT_NONE=y
178# CONFIG_PREEMPT_VOLUNTARY is not set
179# CONFIG_PREEMPT is not set
180CONFIG_SELECT_MEMORY_MODEL=y
181CONFIG_FLATMEM_MANUAL=y
182# CONFIG_DISCONTIGMEM_MANUAL is not set
183# CONFIG_SPARSEMEM_MANUAL is not set
184CONFIG_FLATMEM=y
185CONFIG_FLAT_NODE_MEM_MAP=y
186CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
187CONFIG_PAGEFLAGS_EXTENDED=y
188CONFIG_SPLIT_PTLOCK_CPUS=4
189CONFIG_MIGRATION=y
190CONFIG_PHYS_ADDR_T_64BIT=y
191CONFIG_ZONE_DMA_FLAG=1
192CONFIG_BOUNCE=y
193CONFIG_NR_QUICK=1
194CONFIG_VIRT_TO_BUS=y
195CONFIG_UNEVICTABLE_LRU=y
196CONFIG_ARCH_SELECT_MEMORY_MODEL=y
197CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
198CONFIG_ARCH_FLATMEM_ENABLE=y
199CONFIG_ARCH_SPARSEMEM_ENABLE=y
200CONFIG_ARCH_POPULATES_NODE_MAP=y
201CONFIG_VIRTUAL_MEM_MAP=y
202CONFIG_HOLES_IN_ZONE=y
203# CONFIG_IA32_SUPPORT is not set
204# CONFIG_COMPAT_FOR_U64_ALIGNMENT is not set
205CONFIG_IA64_MCA_RECOVERY=y
206CONFIG_PERFMON=y
207CONFIG_IA64_PALINFO=y
208# CONFIG_IA64_MC_ERR_INJECT is not set
209# CONFIG_IA64_ESI is not set
210# CONFIG_IA64_HP_AML_NFW is not set
211CONFIG_KEXEC=y
212# CONFIG_CRASH_DUMP is not set
213
214#
215# Firmware Drivers
216#
217# CONFIG_FIRMWARE_MEMMAP is not set
218CONFIG_EFI_VARS=y
219CONFIG_EFI_PCDP=y
220CONFIG_DMIID=y
221CONFIG_BINFMT_ELF=y
222# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
223# CONFIG_HAVE_AOUT is not set
224CONFIG_BINFMT_MISC=m
225
226#
227# Power management and ACPI options
228#
229CONFIG_PM=y
230# CONFIG_PM_DEBUG is not set
231CONFIG_PM_SLEEP=y
232CONFIG_SUSPEND=y
233CONFIG_SUSPEND_FREEZER=y
234CONFIG_ACPI=y
235CONFIG_ACPI_SLEEP=y
236CONFIG_ACPI_PROCFS=y
237CONFIG_ACPI_PROCFS_POWER=y
238CONFIG_ACPI_SYSFS_POWER=y
239CONFIG_ACPI_PROC_EVENT=y
240CONFIG_ACPI_BUTTON=m
241CONFIG_ACPI_FAN=m
242# CONFIG_ACPI_DOCK is not set
243CONFIG_ACPI_PROCESSOR=m
244CONFIG_ACPI_HOTPLUG_CPU=y
245CONFIG_ACPI_THERMAL=m
246# CONFIG_ACPI_CUSTOM_DSDT is not set
247CONFIG_ACPI_BLACKLIST_YEAR=0
248# CONFIG_ACPI_DEBUG is not set
249# CONFIG_ACPI_PCI_SLOT is not set
250CONFIG_ACPI_SYSTEM=y
251CONFIG_ACPI_CONTAINER=m
252
253#
254# CPU Frequency scaling
255#
256# CONFIG_CPU_FREQ is not set
257
258#
259# Bus options (PCI, PCMCIA)
260#
261CONFIG_PCI=y
262CONFIG_PCI_DOMAINS=y
263CONFIG_PCI_SYSCALL=y
264# CONFIG_PCIEPORTBUS is not set
265CONFIG_ARCH_SUPPORTS_MSI=y
266# CONFIG_PCI_MSI is not set
267CONFIG_PCI_LEGACY=y
268# CONFIG_PCI_DEBUG is not set
269# CONFIG_PCI_STUB is not set
270CONFIG_HOTPLUG_PCI=m
271# CONFIG_HOTPLUG_PCI_FAKE is not set
272CONFIG_HOTPLUG_PCI_ACPI=m
273# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
274# CONFIG_HOTPLUG_PCI_CPCI is not set
275# CONFIG_HOTPLUG_PCI_SHPC is not set
276# CONFIG_PCCARD is not set
277CONFIG_NET=y
278
279#
280# Networking options
281#
282# CONFIG_NET_NS is not set
283CONFIG_COMPAT_NET_DEV_OPS=y
284CONFIG_PACKET=y
285# CONFIG_PACKET_MMAP is not set
286CONFIG_UNIX=y
287CONFIG_XFRM=y
288# CONFIG_XFRM_USER is not set
289# CONFIG_XFRM_SUB_POLICY is not set
290# CONFIG_XFRM_MIGRATE is not set
291# CONFIG_XFRM_STATISTICS is not set
292# CONFIG_NET_KEY is not set
293CONFIG_INET=y
294CONFIG_IP_MULTICAST=y
295# CONFIG_IP_ADVANCED_ROUTER is not set
296CONFIG_IP_FIB_HASH=y
297# CONFIG_IP_PNP is not set
298# CONFIG_NET_IPIP is not set
299# CONFIG_NET_IPGRE is not set
300# CONFIG_IP_MROUTE is not set
301CONFIG_ARPD=y
302CONFIG_SYN_COOKIES=y
303# CONFIG_INET_AH is not set
304# CONFIG_INET_ESP is not set
305# CONFIG_INET_IPCOMP is not set
306# CONFIG_INET_XFRM_TUNNEL is not set
307# CONFIG_INET_TUNNEL is not set
308CONFIG_INET_XFRM_MODE_TRANSPORT=y
309CONFIG_INET_XFRM_MODE_TUNNEL=y
310CONFIG_INET_XFRM_MODE_BEET=y
311# CONFIG_INET_LRO is not set
312CONFIG_INET_DIAG=y
313CONFIG_INET_TCP_DIAG=y
314# CONFIG_TCP_CONG_ADVANCED is not set
315CONFIG_TCP_CONG_CUBIC=y
316CONFIG_DEFAULT_TCP_CONG="cubic"
317# CONFIG_TCP_MD5SIG is not set
318# CONFIG_IPV6 is not set
319# CONFIG_NETWORK_SECMARK is not set
320# CONFIG_NETFILTER is not set
321# CONFIG_IP_DCCP is not set
322# CONFIG_IP_SCTP is not set
323# CONFIG_TIPC is not set
324# CONFIG_ATM is not set
325# CONFIG_BRIDGE is not set
326# CONFIG_NET_DSA is not set
327# CONFIG_VLAN_8021Q is not set
328# CONFIG_DECNET is not set
329# CONFIG_LLC2 is not set
330# CONFIG_IPX is not set
331# CONFIG_ATALK is not set
332# CONFIG_X25 is not set
333# CONFIG_LAPB is not set
334# CONFIG_ECONET is not set
335# CONFIG_WAN_ROUTER is not set
336# CONFIG_NET_SCHED is not set
337# CONFIG_DCB is not set
338
339#
340# Network testing
341#
342# CONFIG_NET_PKTGEN is not set
343# CONFIG_HAMRADIO is not set
344# CONFIG_CAN is not set
345# CONFIG_IRDA is not set
346# CONFIG_BT is not set
347# CONFIG_AF_RXRPC is not set
348# CONFIG_PHONET is not set
349# CONFIG_WIRELESS is not set
350# CONFIG_WIMAX is not set
351# CONFIG_RFKILL is not set
352# CONFIG_NET_9P is not set
353
354#
355# Device Drivers
356#
357
358#
359# Generic Driver Options
360#
361CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
362CONFIG_STANDALONE=y
363CONFIG_PREVENT_FIRMWARE_BUILD=y
364CONFIG_FW_LOADER=y
365CONFIG_FIRMWARE_IN_KERNEL=y
366CONFIG_EXTRA_FIRMWARE=""
367# CONFIG_DEBUG_DRIVER is not set
368# CONFIG_DEBUG_DEVRES is not set
369# CONFIG_SYS_HYPERVISOR is not set
370# CONFIG_CONNECTOR is not set
371# CONFIG_MTD is not set
372# CONFIG_PARPORT is not set
373CONFIG_PNP=y
374CONFIG_PNP_DEBUG_MESSAGES=y
375
376#
377# Protocols
378#
379CONFIG_PNPACPI=y
380CONFIG_BLK_DEV=y
381# CONFIG_BLK_CPQ_DA is not set
382# CONFIG_BLK_CPQ_CISS_DA is not set
383# CONFIG_BLK_DEV_DAC960 is not set
384# CONFIG_BLK_DEV_UMEM is not set
385# CONFIG_BLK_DEV_COW_COMMON is not set
386CONFIG_BLK_DEV_LOOP=m
387CONFIG_BLK_DEV_CRYPTOLOOP=m
388CONFIG_BLK_DEV_NBD=m
389# CONFIG_BLK_DEV_SX8 is not set
390# CONFIG_BLK_DEV_UB is not set
391CONFIG_BLK_DEV_RAM=y
392CONFIG_BLK_DEV_RAM_COUNT=16
393CONFIG_BLK_DEV_RAM_SIZE=4096
394# CONFIG_BLK_DEV_XIP is not set
395# CONFIG_CDROM_PKTCDVD is not set
396# CONFIG_ATA_OVER_ETH is not set
397CONFIG_XEN_BLKDEV_FRONTEND=y
398# CONFIG_BLK_DEV_HD is not set
399CONFIG_MISC_DEVICES=y
400# CONFIG_PHANTOM is not set
401# CONFIG_EEPROM_93CX6 is not set
402# CONFIG_SGI_IOC4 is not set
403# CONFIG_TIFM_CORE is not set
404# CONFIG_ICS932S401 is not set
405# CONFIG_ENCLOSURE_SERVICES is not set
406# CONFIG_HP_ILO is not set
407# CONFIG_C2PORT is not set
408CONFIG_HAVE_IDE=y
409CONFIG_IDE=y
410
411#
412# Please see Documentation/ide/ide.txt for help/info on IDE drives
413#
414CONFIG_IDE_TIMINGS=y
415CONFIG_IDE_ATAPI=y
416# CONFIG_BLK_DEV_IDE_SATA is not set
417CONFIG_IDE_GD=y
418CONFIG_IDE_GD_ATA=y
419# CONFIG_IDE_GD_ATAPI is not set
420CONFIG_BLK_DEV_IDECD=y
421CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
422# CONFIG_BLK_DEV_IDETAPE is not set
423# CONFIG_BLK_DEV_IDEACPI is not set
424# CONFIG_IDE_TASK_IOCTL is not set
425CONFIG_IDE_PROC_FS=y
426
427#
428# IDE chipset support/bugfixes
429#
430# CONFIG_IDE_GENERIC is not set
431# CONFIG_BLK_DEV_PLATFORM is not set
432# CONFIG_BLK_DEV_IDEPNP is not set
433CONFIG_BLK_DEV_IDEDMA_SFF=y
434
435#
436# PCI IDE chipsets support
437#
438CONFIG_BLK_DEV_IDEPCI=y
439CONFIG_IDEPCI_PCIBUS_ORDER=y
440# CONFIG_BLK_DEV_OFFBOARD is not set
441CONFIG_BLK_DEV_GENERIC=y
442# CONFIG_BLK_DEV_OPTI621 is not set
443CONFIG_BLK_DEV_IDEDMA_PCI=y
444# CONFIG_BLK_DEV_AEC62XX is not set
445# CONFIG_BLK_DEV_ALI15X3 is not set
446# CONFIG_BLK_DEV_AMD74XX is not set
447CONFIG_BLK_DEV_CMD64X=y
448# CONFIG_BLK_DEV_TRIFLEX is not set
449# CONFIG_BLK_DEV_CS5520 is not set
450# CONFIG_BLK_DEV_CS5530 is not set
451# CONFIG_BLK_DEV_HPT366 is not set
452# CONFIG_BLK_DEV_JMICRON is not set
453# CONFIG_BLK_DEV_SC1200 is not set
454CONFIG_BLK_DEV_PIIX=y
455# CONFIG_BLK_DEV_IT8172 is not set
456# CONFIG_BLK_DEV_IT8213 is not set
457# CONFIG_BLK_DEV_IT821X is not set
458# CONFIG_BLK_DEV_NS87415 is not set
459# CONFIG_BLK_DEV_PDC202XX_OLD is not set
460# CONFIG_BLK_DEV_PDC202XX_NEW is not set
461# CONFIG_BLK_DEV_SVWKS is not set
462# CONFIG_BLK_DEV_SIIMAGE is not set
463# CONFIG_BLK_DEV_SLC90E66 is not set
464# CONFIG_BLK_DEV_TRM290 is not set
465# CONFIG_BLK_DEV_VIA82CXXX is not set
466# CONFIG_BLK_DEV_TC86C001 is not set
467CONFIG_BLK_DEV_IDEDMA=y
468
469#
470# SCSI device support
471#
472# CONFIG_RAID_ATTRS is not set
473CONFIG_SCSI=y
474CONFIG_SCSI_DMA=y
475# CONFIG_SCSI_TGT is not set
476CONFIG_SCSI_NETLINK=y
477CONFIG_SCSI_PROC_FS=y
478
479#
480# SCSI support type (disk, tape, CD-ROM)
481#
482CONFIG_BLK_DEV_SD=y
483CONFIG_CHR_DEV_ST=m
484# CONFIG_CHR_DEV_OSST is not set
485CONFIG_BLK_DEV_SR=m
486# CONFIG_BLK_DEV_SR_VENDOR is not set
487CONFIG_CHR_DEV_SG=m
488# CONFIG_CHR_DEV_SCH is not set
489
490#
491# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
492#
493# CONFIG_SCSI_MULTI_LUN is not set
494# CONFIG_SCSI_CONSTANTS is not set
495# CONFIG_SCSI_LOGGING is not set
496# CONFIG_SCSI_SCAN_ASYNC is not set
497CONFIG_SCSI_WAIT_SCAN=m
498
499#
500# SCSI Transports
501#
502CONFIG_SCSI_SPI_ATTRS=y
503CONFIG_SCSI_FC_ATTRS=y
504# CONFIG_SCSI_ISCSI_ATTRS is not set
505# CONFIG_SCSI_SAS_LIBSAS is not set
506# CONFIG_SCSI_SRP_ATTRS is not set
507CONFIG_SCSI_LOWLEVEL=y
508# CONFIG_ISCSI_TCP is not set
509# CONFIG_SCSI_CXGB3_ISCSI is not set
510# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
511# CONFIG_SCSI_3W_9XXX is not set
512# CONFIG_SCSI_ACARD is not set
513# CONFIG_SCSI_AACRAID is not set
514# CONFIG_SCSI_AIC7XXX is not set
515# CONFIG_SCSI_AIC7XXX_OLD is not set
516# CONFIG_SCSI_AIC79XX is not set
517# CONFIG_SCSI_AIC94XX is not set
518# CONFIG_SCSI_DPT_I2O is not set
519# CONFIG_SCSI_ADVANSYS is not set
520# CONFIG_SCSI_ARCMSR is not set
521# CONFIG_MEGARAID_NEWGEN is not set
522# CONFIG_MEGARAID_LEGACY is not set
523# CONFIG_MEGARAID_SAS is not set
524# CONFIG_SCSI_HPTIOP is not set
525# CONFIG_LIBFC is not set
526# CONFIG_FCOE is not set
527# CONFIG_SCSI_DMX3191D is not set
528# CONFIG_SCSI_FUTURE_DOMAIN is not set
529# CONFIG_SCSI_IPS is not set
530# CONFIG_SCSI_INITIO is not set
531# CONFIG_SCSI_INIA100 is not set
532# CONFIG_SCSI_MVSAS is not set
533# CONFIG_SCSI_STEX is not set
534CONFIG_SCSI_SYM53C8XX_2=y
535CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
536CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
537CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
538CONFIG_SCSI_SYM53C8XX_MMIO=y
539CONFIG_SCSI_QLOGIC_1280=y
540# CONFIG_SCSI_QLA_FC is not set
541# CONFIG_SCSI_QLA_ISCSI is not set
542# CONFIG_SCSI_LPFC is not set
543# CONFIG_SCSI_DC395x is not set
544# CONFIG_SCSI_DC390T is not set
545# CONFIG_SCSI_DEBUG is not set
546# CONFIG_SCSI_SRP is not set
547# CONFIG_SCSI_DH is not set
548# CONFIG_ATA is not set
549CONFIG_MD=y
550CONFIG_BLK_DEV_MD=m
551CONFIG_MD_LINEAR=m
552CONFIG_MD_RAID0=m
553CONFIG_MD_RAID1=m
554# CONFIG_MD_RAID10 is not set
555# CONFIG_MD_RAID456 is not set
556CONFIG_MD_MULTIPATH=m
557# CONFIG_MD_FAULTY is not set
558CONFIG_BLK_DEV_DM=m
559# CONFIG_DM_DEBUG is not set
560CONFIG_DM_CRYPT=m
561CONFIG_DM_SNAPSHOT=m
562CONFIG_DM_MIRROR=m
563CONFIG_DM_ZERO=m
564# CONFIG_DM_MULTIPATH is not set
565# CONFIG_DM_DELAY is not set
566# CONFIG_DM_UEVENT is not set
567CONFIG_FUSION=y
568CONFIG_FUSION_SPI=y
569CONFIG_FUSION_FC=y
570# CONFIG_FUSION_SAS is not set
571CONFIG_FUSION_MAX_SGE=128
572CONFIG_FUSION_CTL=y
573# CONFIG_FUSION_LOGGING is not set
574
575#
576# IEEE 1394 (FireWire) support
577#
578
579#
580# Enable only one of the two stacks, unless you know what you are doing
581#
582# CONFIG_FIREWIRE is not set
583# CONFIG_IEEE1394 is not set
584# CONFIG_I2O is not set
585CONFIG_NETDEVICES=y
586CONFIG_DUMMY=m
587# CONFIG_BONDING is not set
588# CONFIG_MACVLAN is not set
589# CONFIG_EQUALIZER is not set
590# CONFIG_TUN is not set
591# CONFIG_VETH is not set
592# CONFIG_NET_SB1000 is not set
593# CONFIG_ARCNET is not set
594CONFIG_PHYLIB=y
595
596#
597# MII PHY device drivers
598#
599# CONFIG_MARVELL_PHY is not set
600# CONFIG_DAVICOM_PHY is not set
601# CONFIG_QSEMI_PHY is not set
602# CONFIG_LXT_PHY is not set
603# CONFIG_CICADA_PHY is not set
604# CONFIG_VITESSE_PHY is not set
605# CONFIG_SMSC_PHY is not set
606# CONFIG_BROADCOM_PHY is not set
607# CONFIG_ICPLUS_PHY is not set
608# CONFIG_REALTEK_PHY is not set
609# CONFIG_NATIONAL_PHY is not set
610# CONFIG_STE10XP is not set
611# CONFIG_LSI_ET1011C_PHY is not set
612# CONFIG_FIXED_PHY is not set
613# CONFIG_MDIO_BITBANG is not set
614CONFIG_NET_ETHERNET=y
615CONFIG_MII=m
616# CONFIG_HAPPYMEAL is not set
617# CONFIG_SUNGEM is not set
618# CONFIG_CASSINI is not set
619# CONFIG_NET_VENDOR_3COM is not set
620CONFIG_NET_TULIP=y
621# CONFIG_DE2104X is not set
622CONFIG_TULIP=m
623# CONFIG_TULIP_MWI is not set
624# CONFIG_TULIP_MMIO is not set
625# CONFIG_TULIP_NAPI is not set
626# CONFIG_DE4X5 is not set
627# CONFIG_WINBOND_840 is not set
628# CONFIG_DM9102 is not set
629# CONFIG_ULI526X is not set
630# CONFIG_HP100 is not set
631# CONFIG_IBM_NEW_EMAC_ZMII is not set
632# CONFIG_IBM_NEW_EMAC_RGMII is not set
633# CONFIG_IBM_NEW_EMAC_TAH is not set
634# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
635# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
636# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
637# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
638CONFIG_NET_PCI=y
639# CONFIG_PCNET32 is not set
640# CONFIG_AMD8111_ETH is not set
641# CONFIG_ADAPTEC_STARFIRE is not set
642# CONFIG_B44 is not set
643# CONFIG_FORCEDETH is not set
644CONFIG_E100=m
645# CONFIG_FEALNX is not set
646# CONFIG_NATSEMI is not set
647# CONFIG_NE2K_PCI is not set
648# CONFIG_8139CP is not set
649# CONFIG_8139TOO is not set
650# CONFIG_R6040 is not set
651# CONFIG_SIS900 is not set
652# CONFIG_EPIC100 is not set
653# CONFIG_SMSC9420 is not set
654# CONFIG_SUNDANCE is not set
655# CONFIG_TLAN is not set
656# CONFIG_VIA_RHINE is not set
657# CONFIG_SC92031 is not set
658# CONFIG_ATL2 is not set
659CONFIG_NETDEV_1000=y
660# CONFIG_ACENIC is not set
661# CONFIG_DL2K is not set
662CONFIG_E1000=y
663# CONFIG_E1000E is not set
664# CONFIG_IP1000 is not set
665# CONFIG_IGB is not set
666# CONFIG_NS83820 is not set
667# CONFIG_HAMACHI is not set
668# CONFIG_YELLOWFIN is not set
669# CONFIG_R8169 is not set
670# CONFIG_SIS190 is not set
671# CONFIG_SKGE is not set
672# CONFIG_SKY2 is not set
673# CONFIG_VIA_VELOCITY is not set
674CONFIG_TIGON3=y
675# CONFIG_BNX2 is not set
676# CONFIG_QLA3XXX is not set
677# CONFIG_ATL1 is not set
678# CONFIG_ATL1E is not set
679# CONFIG_JME is not set
680CONFIG_NETDEV_10000=y
681# CONFIG_CHELSIO_T1 is not set
682CONFIG_CHELSIO_T3_DEPENDS=y
683# CONFIG_CHELSIO_T3 is not set
684# CONFIG_ENIC is not set
685# CONFIG_IXGBE is not set
686# CONFIG_IXGB is not set
687# CONFIG_S2IO is not set
688# CONFIG_MYRI10GE is not set
689# CONFIG_NETXEN_NIC is not set
690# CONFIG_NIU is not set
691# CONFIG_MLX4_EN is not set
692# CONFIG_MLX4_CORE is not set
693# CONFIG_TEHUTI is not set
694# CONFIG_BNX2X is not set
695# CONFIG_QLGE is not set
696# CONFIG_SFC is not set
697# CONFIG_TR is not set
698
699#
700# Wireless LAN
701#
702# CONFIG_WLAN_PRE80211 is not set
703# CONFIG_WLAN_80211 is not set
704# CONFIG_IWLWIFI_LEDS is not set
705
706#
707# Enable WiMAX (Networking options) to see the WiMAX drivers
708#
709
710#
711# USB Network Adapters
712#
713# CONFIG_USB_CATC is not set
714# CONFIG_USB_KAWETH is not set
715# CONFIG_USB_PEGASUS is not set
716# CONFIG_USB_RTL8150 is not set
717# CONFIG_USB_USBNET is not set
718# CONFIG_WAN is not set
719CONFIG_XEN_NETDEV_FRONTEND=y
720# CONFIG_FDDI is not set
721# CONFIG_HIPPI is not set
722# CONFIG_PPP is not set
723# CONFIG_SLIP is not set
724# CONFIG_NET_FC is not set
725CONFIG_NETCONSOLE=y
726# CONFIG_NETCONSOLE_DYNAMIC is not set
727CONFIG_NETPOLL=y
728# CONFIG_NETPOLL_TRAP is not set
729CONFIG_NET_POLL_CONTROLLER=y
730# CONFIG_ISDN is not set
731# CONFIG_PHONE is not set
732
733#
734# Input device support
735#
736CONFIG_INPUT=y
737# CONFIG_INPUT_FF_MEMLESS is not set
738# CONFIG_INPUT_POLLDEV is not set
739
740#
741# Userland interfaces
742#
743CONFIG_INPUT_MOUSEDEV=y
744CONFIG_INPUT_MOUSEDEV_PSAUX=y
745CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
746CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
747# CONFIG_INPUT_JOYDEV is not set
748# CONFIG_INPUT_EVDEV is not set
749# CONFIG_INPUT_EVBUG is not set
750
751#
752# Input Device Drivers
753#
754CONFIG_INPUT_KEYBOARD=y
755CONFIG_KEYBOARD_ATKBD=y
756# CONFIG_KEYBOARD_SUNKBD is not set
757# CONFIG_KEYBOARD_LKKBD is not set
758# CONFIG_KEYBOARD_XTKBD is not set
759# CONFIG_KEYBOARD_NEWTON is not set
760# CONFIG_KEYBOARD_STOWAWAY is not set
761CONFIG_INPUT_MOUSE=y
762CONFIG_MOUSE_PS2=y
763CONFIG_MOUSE_PS2_ALPS=y
764CONFIG_MOUSE_PS2_LOGIPS2PP=y
765CONFIG_MOUSE_PS2_SYNAPTICS=y
766CONFIG_MOUSE_PS2_LIFEBOOK=y
767CONFIG_MOUSE_PS2_TRACKPOINT=y
768# CONFIG_MOUSE_PS2_ELANTECH is not set
769# CONFIG_MOUSE_PS2_TOUCHKIT is not set
770# CONFIG_MOUSE_SERIAL is not set
771# CONFIG_MOUSE_APPLETOUCH is not set
772# CONFIG_MOUSE_BCM5974 is not set
773# CONFIG_MOUSE_VSXXXAA is not set
774# CONFIG_INPUT_JOYSTICK is not set
775# CONFIG_INPUT_TABLET is not set
776# CONFIG_INPUT_TOUCHSCREEN is not set
777# CONFIG_INPUT_MISC is not set
778
779#
780# Hardware I/O ports
781#
782CONFIG_SERIO=y
783CONFIG_SERIO_I8042=y
784# CONFIG_SERIO_SERPORT is not set
785# CONFIG_SERIO_PCIPS2 is not set
786CONFIG_SERIO_LIBPS2=y
787# CONFIG_SERIO_RAW is not set
788CONFIG_GAMEPORT=m
789# CONFIG_GAMEPORT_NS558 is not set
790# CONFIG_GAMEPORT_L4 is not set
791# CONFIG_GAMEPORT_EMU10K1 is not set
792# CONFIG_GAMEPORT_FM801 is not set
793
794#
795# Character devices
796#
797CONFIG_VT=y
798CONFIG_CONSOLE_TRANSLATIONS=y
799CONFIG_VT_CONSOLE=y
800CONFIG_HW_CONSOLE=y
801# CONFIG_VT_HW_CONSOLE_BINDING is not set
802CONFIG_DEVKMEM=y
803CONFIG_SERIAL_NONSTANDARD=y
804# CONFIG_COMPUTONE is not set
805# CONFIG_ROCKETPORT is not set
806# CONFIG_CYCLADES is not set
807# CONFIG_DIGIEPCA is not set
808# CONFIG_MOXA_INTELLIO is not set
809# CONFIG_MOXA_SMARTIO is not set
810# CONFIG_ISI is not set
811# CONFIG_SYNCLINKMP is not set
812# CONFIG_SYNCLINK_GT is not set
813# CONFIG_N_HDLC is not set
814# CONFIG_RISCOM8 is not set
815# CONFIG_SPECIALIX is not set
816# CONFIG_SX is not set
817# CONFIG_RIO is not set
818# CONFIG_STALDRV is not set
819# CONFIG_NOZOMI is not set
820
821#
822# Serial drivers
823#
824CONFIG_SERIAL_8250=y
825CONFIG_SERIAL_8250_CONSOLE=y
826CONFIG_SERIAL_8250_PCI=y
827CONFIG_SERIAL_8250_PNP=y
828CONFIG_SERIAL_8250_NR_UARTS=6
829CONFIG_SERIAL_8250_RUNTIME_UARTS=4
830CONFIG_SERIAL_8250_EXTENDED=y
831CONFIG_SERIAL_8250_SHARE_IRQ=y
832# CONFIG_SERIAL_8250_DETECT_IRQ is not set
833# CONFIG_SERIAL_8250_RSA is not set
834
835#
836# Non-8250 serial port support
837#
838CONFIG_SERIAL_CORE=y
839CONFIG_SERIAL_CORE_CONSOLE=y
840# CONFIG_SERIAL_JSM is not set
841CONFIG_UNIX98_PTYS=y
842# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
843CONFIG_LEGACY_PTYS=y
844CONFIG_LEGACY_PTY_COUNT=256
845CONFIG_HVC_DRIVER=y
846CONFIG_HVC_IRQ=y
847CONFIG_HVC_XEN=y
848# CONFIG_IPMI_HANDLER is not set
849# CONFIG_HW_RANDOM is not set
850CONFIG_EFI_RTC=y
851# CONFIG_R3964 is not set
852# CONFIG_APPLICOM is not set
853CONFIG_RAW_DRIVER=m
854CONFIG_MAX_RAW_DEVS=256
855CONFIG_HPET=y
856CONFIG_HPET_MMAP=y
857# CONFIG_HANGCHECK_TIMER is not set
858# CONFIG_TCG_TPM is not set
859CONFIG_DEVPORT=y
860CONFIG_I2C=m
861CONFIG_I2C_BOARDINFO=y
862# CONFIG_I2C_CHARDEV is not set
863CONFIG_I2C_HELPER_AUTO=y
864CONFIG_I2C_ALGOBIT=m
865
866#
867# I2C Hardware Bus support
868#
869
870#
871# PC SMBus host controller drivers
872#
873# CONFIG_I2C_ALI1535 is not set
874# CONFIG_I2C_ALI1563 is not set
875# CONFIG_I2C_ALI15X3 is not set
876# CONFIG_I2C_AMD756 is not set
877# CONFIG_I2C_AMD8111 is not set
878# CONFIG_I2C_I801 is not set
879# CONFIG_I2C_ISCH is not set
880# CONFIG_I2C_PIIX4 is not set
881# CONFIG_I2C_NFORCE2 is not set
882# CONFIG_I2C_SIS5595 is not set
883# CONFIG_I2C_SIS630 is not set
884# CONFIG_I2C_SIS96X is not set
885# CONFIG_I2C_VIA is not set
886# CONFIG_I2C_VIAPRO is not set
887
888#
889# I2C system bus drivers (mostly embedded / system-on-chip)
890#
891# CONFIG_I2C_OCORES is not set
892# CONFIG_I2C_SIMTEC is not set
893
894#
895# External I2C/SMBus adapter drivers
896#
897# CONFIG_I2C_PARPORT_LIGHT is not set
898# CONFIG_I2C_TAOS_EVM is not set
899# CONFIG_I2C_TINY_USB is not set
900
901#
902# Graphics adapter I2C/DDC channel drivers
903#
904# CONFIG_I2C_VOODOO3 is not set
905
906#
907# Other I2C/SMBus bus drivers
908#
909# CONFIG_I2C_PCA_PLATFORM is not set
910# CONFIG_I2C_STUB is not set
911
912#
913# Miscellaneous I2C Chip support
914#
915# CONFIG_DS1682 is not set
916# CONFIG_AT24 is not set
917# CONFIG_SENSORS_EEPROM is not set
918# CONFIG_SENSORS_PCF8574 is not set
919# CONFIG_PCF8575 is not set
920# CONFIG_SENSORS_PCA9539 is not set
921# CONFIG_SENSORS_PCF8591 is not set
922# CONFIG_SENSORS_MAX6875 is not set
923# CONFIG_SENSORS_TSL2550 is not set
924# CONFIG_I2C_DEBUG_CORE is not set
925# CONFIG_I2C_DEBUG_ALGO is not set
926# CONFIG_I2C_DEBUG_BUS is not set
927# CONFIG_I2C_DEBUG_CHIP is not set
928# CONFIG_SPI is not set
929# CONFIG_W1 is not set
930CONFIG_POWER_SUPPLY=y
931# CONFIG_POWER_SUPPLY_DEBUG is not set
932# CONFIG_PDA_POWER is not set
933# CONFIG_BATTERY_DS2760 is not set
934# CONFIG_BATTERY_BQ27x00 is not set
935CONFIG_HWMON=y
936# CONFIG_HWMON_VID is not set
937# CONFIG_SENSORS_AD7414 is not set
938# CONFIG_SENSORS_AD7418 is not set
939# CONFIG_SENSORS_ADM1021 is not set
940# CONFIG_SENSORS_ADM1025 is not set
941# CONFIG_SENSORS_ADM1026 is not set
942# CONFIG_SENSORS_ADM1029 is not set
943# CONFIG_SENSORS_ADM1031 is not set
944# CONFIG_SENSORS_ADM9240 is not set
945# CONFIG_SENSORS_ADT7462 is not set
946# CONFIG_SENSORS_ADT7470 is not set
947# CONFIG_SENSORS_ADT7473 is not set
948# CONFIG_SENSORS_ATXP1 is not set
949# CONFIG_SENSORS_DS1621 is not set
950# CONFIG_SENSORS_I5K_AMB is not set
951# CONFIG_SENSORS_F71805F is not set
952# CONFIG_SENSORS_F71882FG is not set
953# CONFIG_SENSORS_F75375S is not set
954# CONFIG_SENSORS_GL518SM is not set
955# CONFIG_SENSORS_GL520SM is not set
956# CONFIG_SENSORS_IT87 is not set
957# CONFIG_SENSORS_LM63 is not set
958# CONFIG_SENSORS_LM75 is not set
959# CONFIG_SENSORS_LM77 is not set
960# CONFIG_SENSORS_LM78 is not set
961# CONFIG_SENSORS_LM80 is not set
962# CONFIG_SENSORS_LM83 is not set
963# CONFIG_SENSORS_LM85 is not set
964# CONFIG_SENSORS_LM87 is not set
965# CONFIG_SENSORS_LM90 is not set
966# CONFIG_SENSORS_LM92 is not set
967# CONFIG_SENSORS_LM93 is not set
968# CONFIG_SENSORS_LTC4245 is not set
969# CONFIG_SENSORS_MAX1619 is not set
970# CONFIG_SENSORS_MAX6650 is not set
971# CONFIG_SENSORS_PC87360 is not set
972# CONFIG_SENSORS_PC87427 is not set
973# CONFIG_SENSORS_SIS5595 is not set
974# CONFIG_SENSORS_DME1737 is not set
975# CONFIG_SENSORS_SMSC47M1 is not set
976# CONFIG_SENSORS_SMSC47M192 is not set
977# CONFIG_SENSORS_SMSC47B397 is not set
978# CONFIG_SENSORS_ADS7828 is not set
979# CONFIG_SENSORS_THMC50 is not set
980# CONFIG_SENSORS_VIA686A is not set
981# CONFIG_SENSORS_VT1211 is not set
982# CONFIG_SENSORS_VT8231 is not set
983# CONFIG_SENSORS_W83781D is not set
984# CONFIG_SENSORS_W83791D is not set
985# CONFIG_SENSORS_W83792D is not set
986# CONFIG_SENSORS_W83793 is not set
987# CONFIG_SENSORS_W83L785TS is not set
988# CONFIG_SENSORS_W83L786NG is not set
989# CONFIG_SENSORS_W83627HF is not set
990# CONFIG_SENSORS_W83627EHF is not set
991# CONFIG_SENSORS_LIS3LV02D is not set
992# CONFIG_HWMON_DEBUG_CHIP is not set
993CONFIG_THERMAL=m
994# CONFIG_THERMAL_HWMON is not set
995# CONFIG_WATCHDOG is not set
996CONFIG_SSB_POSSIBLE=y
997
998#
999# Sonics Silicon Backplane
1000#
1001# CONFIG_SSB is not set
1002
1003#
1004# Multifunction device drivers
1005#
1006# CONFIG_MFD_CORE is not set
1007# CONFIG_MFD_SM501 is not set
1008# CONFIG_HTC_PASIC3 is not set
1009# CONFIG_MFD_TMIO is not set
1010# CONFIG_MFD_WM8400 is not set
1011# CONFIG_MFD_WM8350_I2C is not set
1012# CONFIG_MFD_PCF50633 is not set
1013# CONFIG_REGULATOR is not set
1014
1015#
1016# Multimedia devices
1017#
1018
1019#
1020# Multimedia core support
1021#
1022# CONFIG_VIDEO_DEV is not set
1023# CONFIG_DVB_CORE is not set
1024# CONFIG_VIDEO_MEDIA is not set
1025
1026#
1027# Multimedia drivers
1028#
1029CONFIG_DAB=y
1030# CONFIG_USB_DABUSB is not set
1031
1032#
1033# Graphics support
1034#
1035CONFIG_AGP=m
1036CONFIG_DRM=m
1037CONFIG_DRM_TDFX=m
1038CONFIG_DRM_R128=m
1039CONFIG_DRM_RADEON=m
1040CONFIG_DRM_MGA=m
1041CONFIG_DRM_SIS=m
1042# CONFIG_DRM_VIA is not set
1043# CONFIG_DRM_SAVAGE is not set
1044# CONFIG_VGASTATE is not set
1045# CONFIG_VIDEO_OUTPUT_CONTROL is not set
1046# CONFIG_FB is not set
1047# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1048
1049#
1050# Display device support
1051#
1052# CONFIG_DISPLAY_SUPPORT is not set
1053
1054#
1055# Console display driver support
1056#
1057CONFIG_VGA_CONSOLE=y
1058# CONFIG_VGACON_SOFT_SCROLLBACK is not set
1059CONFIG_DUMMY_CONSOLE=y
1060# CONFIG_SOUND is not set
1061CONFIG_HID_SUPPORT=y
1062CONFIG_HID=y
1063# CONFIG_HID_DEBUG is not set
1064# CONFIG_HIDRAW is not set
1065
1066#
1067# USB Input Devices
1068#
1069CONFIG_USB_HID=y
1070# CONFIG_HID_PID is not set
1071# CONFIG_USB_HIDDEV is not set
1072
1073#
1074# Special HID drivers
1075#
1076CONFIG_HID_COMPAT=y
1077CONFIG_HID_A4TECH=y
1078CONFIG_HID_APPLE=y
1079CONFIG_HID_BELKIN=y
1080CONFIG_HID_CHERRY=y
1081CONFIG_HID_CHICONY=y
1082CONFIG_HID_CYPRESS=y
1083CONFIG_HID_EZKEY=y
1084CONFIG_HID_GYRATION=y
1085CONFIG_HID_LOGITECH=y
1086# CONFIG_LOGITECH_FF is not set
1087# CONFIG_LOGIRUMBLEPAD2_FF is not set
1088CONFIG_HID_MICROSOFT=y
1089CONFIG_HID_MONTEREY=y
1090CONFIG_HID_NTRIG=y
1091CONFIG_HID_PANTHERLORD=y
1092# CONFIG_PANTHERLORD_FF is not set
1093CONFIG_HID_PETALYNX=y
1094CONFIG_HID_SAMSUNG=y
1095CONFIG_HID_SONY=y
1096CONFIG_HID_SUNPLUS=y
1097# CONFIG_GREENASIA_FF is not set
1098CONFIG_HID_TOPSEED=y
1099# CONFIG_THRUSTMASTER_FF is not set
1100# CONFIG_ZEROPLUS_FF is not set
1101CONFIG_USB_SUPPORT=y
1102CONFIG_USB_ARCH_HAS_HCD=y
1103CONFIG_USB_ARCH_HAS_OHCI=y
1104CONFIG_USB_ARCH_HAS_EHCI=y
1105CONFIG_USB=y
1106# CONFIG_USB_DEBUG is not set
1107# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1108
1109#
1110# Miscellaneous USB options
1111#
1112CONFIG_USB_DEVICEFS=y
1113CONFIG_USB_DEVICE_CLASS=y
1114# CONFIG_USB_DYNAMIC_MINORS is not set
1115# CONFIG_USB_SUSPEND is not set
1116# CONFIG_USB_OTG is not set
1117# CONFIG_USB_MON is not set
1118# CONFIG_USB_WUSB is not set
1119# CONFIG_USB_WUSB_CBAF is not set
1120
1121#
1122# USB Host Controller Drivers
1123#
1124# CONFIG_USB_C67X00_HCD is not set
1125CONFIG_USB_EHCI_HCD=m
1126# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
1127# CONFIG_USB_EHCI_TT_NEWSCHED is not set
1128# CONFIG_USB_OXU210HP_HCD is not set
1129# CONFIG_USB_ISP116X_HCD is not set
1130# CONFIG_USB_ISP1760_HCD is not set
1131CONFIG_USB_OHCI_HCD=m
1132# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1133# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1134CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1135CONFIG_USB_UHCI_HCD=y
1136# CONFIG_USB_SL811_HCD is not set
1137# CONFIG_USB_R8A66597_HCD is not set
1138# CONFIG_USB_WHCI_HCD is not set
1139# CONFIG_USB_HWA_HCD is not set
1140
1141#
1142# USB Device Class drivers
1143#
1144# CONFIG_USB_ACM is not set
1145# CONFIG_USB_PRINTER is not set
1146# CONFIG_USB_WDM is not set
1147# CONFIG_USB_TMC is not set
1148
1149#
1150# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
1151#
1152
1153#
1154# see USB_STORAGE Help for more information
1155#
1156CONFIG_USB_STORAGE=m
1157# CONFIG_USB_STORAGE_DEBUG is not set
1158# CONFIG_USB_STORAGE_DATAFAB is not set
1159# CONFIG_USB_STORAGE_FREECOM is not set
1160# CONFIG_USB_STORAGE_ISD200 is not set
1161# CONFIG_USB_STORAGE_USBAT is not set
1162# CONFIG_USB_STORAGE_SDDR09 is not set
1163# CONFIG_USB_STORAGE_SDDR55 is not set
1164# CONFIG_USB_STORAGE_JUMPSHOT is not set
1165# CONFIG_USB_STORAGE_ALAUDA is not set
1166# CONFIG_USB_STORAGE_ONETOUCH is not set
1167# CONFIG_USB_STORAGE_KARMA is not set
1168# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1169# CONFIG_USB_LIBUSUAL is not set
1170
1171#
1172# USB Imaging devices
1173#
1174# CONFIG_USB_MDC800 is not set
1175# CONFIG_USB_MICROTEK is not set
1176
1177#
1178# USB port drivers
1179#
1180# CONFIG_USB_SERIAL is not set
1181
1182#
1183# USB Miscellaneous drivers
1184#
1185# CONFIG_USB_EMI62 is not set
1186# CONFIG_USB_EMI26 is not set
1187# CONFIG_USB_ADUTUX is not set
1188# CONFIG_USB_SEVSEG is not set
1189# CONFIG_USB_RIO500 is not set
1190# CONFIG_USB_LEGOTOWER is not set
1191# CONFIG_USB_LCD is not set
1192# CONFIG_USB_BERRY_CHARGE is not set
1193# CONFIG_USB_LED is not set
1194# CONFIG_USB_CYPRESS_CY7C63 is not set
1195# CONFIG_USB_CYTHERM is not set
1196# CONFIG_USB_PHIDGET is not set
1197# CONFIG_USB_IDMOUSE is not set
1198# CONFIG_USB_FTDI_ELAN is not set
1199# CONFIG_USB_APPLEDISPLAY is not set
1200# CONFIG_USB_SISUSBVGA is not set
1201# CONFIG_USB_LD is not set
1202# CONFIG_USB_TRANCEVIBRATOR is not set
1203# CONFIG_USB_IOWARRIOR is not set
1204# CONFIG_USB_TEST is not set
1205# CONFIG_USB_ISIGHTFW is not set
1206# CONFIG_USB_VST is not set
1207# CONFIG_USB_GADGET is not set
1208
1209#
1210# OTG and related infrastructure
1211#
1212# CONFIG_UWB is not set
1213# CONFIG_MMC is not set
1214# CONFIG_MEMSTICK is not set
1215# CONFIG_NEW_LEDS is not set
1216# CONFIG_ACCESSIBILITY is not set
1217# CONFIG_INFINIBAND is not set
1218# CONFIG_RTC_CLASS is not set
1219# CONFIG_DMADEVICES is not set
1220# CONFIG_UIO is not set
1221CONFIG_XEN_BALLOON=y
1222CONFIG_XEN_SCRUB_PAGES=y
1223CONFIG_XENFS=y
1224CONFIG_XEN_COMPAT_XENFS=y
1225# CONFIG_STAGING is not set
1226# CONFIG_MSPEC is not set
1227
1228#
1229# File systems
1230#
1231CONFIG_EXT2_FS=y
1232CONFIG_EXT2_FS_XATTR=y
1233CONFIG_EXT2_FS_POSIX_ACL=y
1234CONFIG_EXT2_FS_SECURITY=y
1235# CONFIG_EXT2_FS_XIP is not set
1236CONFIG_EXT3_FS=y
1237CONFIG_EXT3_FS_XATTR=y
1238CONFIG_EXT3_FS_POSIX_ACL=y
1239CONFIG_EXT3_FS_SECURITY=y
1240# CONFIG_EXT4_FS is not set
1241CONFIG_JBD=y
1242CONFIG_FS_MBCACHE=y
1243CONFIG_REISERFS_FS=y
1244# CONFIG_REISERFS_CHECK is not set
1245# CONFIG_REISERFS_PROC_INFO is not set
1246CONFIG_REISERFS_FS_XATTR=y
1247CONFIG_REISERFS_FS_POSIX_ACL=y
1248CONFIG_REISERFS_FS_SECURITY=y
1249# CONFIG_JFS_FS is not set
1250CONFIG_FS_POSIX_ACL=y
1251CONFIG_FILE_LOCKING=y
1252CONFIG_XFS_FS=y
1253# CONFIG_XFS_QUOTA is not set
1254# CONFIG_XFS_POSIX_ACL is not set
1255# CONFIG_XFS_RT is not set
1256# CONFIG_XFS_DEBUG is not set
1257# CONFIG_GFS2_FS is not set
1258# CONFIG_OCFS2_FS is not set
1259# CONFIG_BTRFS_FS is not set
1260CONFIG_DNOTIFY=y
1261CONFIG_INOTIFY=y
1262CONFIG_INOTIFY_USER=y
1263# CONFIG_QUOTA is not set
1264CONFIG_AUTOFS_FS=y
1265CONFIG_AUTOFS4_FS=y
1266# CONFIG_FUSE_FS is not set
1267
1268#
1269# CD-ROM/DVD Filesystems
1270#
1271CONFIG_ISO9660_FS=m
1272CONFIG_JOLIET=y
1273# CONFIG_ZISOFS is not set
1274CONFIG_UDF_FS=m
1275CONFIG_UDF_NLS=y
1276
1277#
1278# DOS/FAT/NT Filesystems
1279#
1280CONFIG_FAT_FS=y
1281# CONFIG_MSDOS_FS is not set
1282CONFIG_VFAT_FS=y
1283CONFIG_FAT_DEFAULT_CODEPAGE=437
1284CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1285CONFIG_NTFS_FS=m
1286# CONFIG_NTFS_DEBUG is not set
1287# CONFIG_NTFS_RW is not set
1288
1289#
1290# Pseudo filesystems
1291#
1292CONFIG_PROC_FS=y
1293CONFIG_PROC_KCORE=y
1294CONFIG_PROC_SYSCTL=y
1295CONFIG_PROC_PAGE_MONITOR=y
1296CONFIG_SYSFS=y
1297CONFIG_TMPFS=y
1298# CONFIG_TMPFS_POSIX_ACL is not set
1299CONFIG_HUGETLBFS=y
1300CONFIG_HUGETLB_PAGE=y
1301# CONFIG_CONFIGFS_FS is not set
1302CONFIG_MISC_FILESYSTEMS=y
1303# CONFIG_ADFS_FS is not set
1304# CONFIG_AFFS_FS is not set
1305# CONFIG_HFS_FS is not set
1306# CONFIG_HFSPLUS_FS is not set
1307# CONFIG_BEFS_FS is not set
1308# CONFIG_BFS_FS is not set
1309# CONFIG_EFS_FS is not set
1310# CONFIG_CRAMFS is not set
1311# CONFIG_SQUASHFS is not set
1312# CONFIG_VXFS_FS is not set
1313# CONFIG_MINIX_FS is not set
1314# CONFIG_OMFS_FS is not set
1315# CONFIG_HPFS_FS is not set
1316# CONFIG_QNX4FS_FS is not set
1317# CONFIG_ROMFS_FS is not set
1318# CONFIG_SYSV_FS is not set
1319# CONFIG_UFS_FS is not set
1320CONFIG_NETWORK_FILESYSTEMS=y
1321CONFIG_NFS_FS=m
1322CONFIG_NFS_V3=y
1323# CONFIG_NFS_V3_ACL is not set
1324CONFIG_NFS_V4=y
1325CONFIG_NFSD=m
1326CONFIG_NFSD_V3=y
1327# CONFIG_NFSD_V3_ACL is not set
1328CONFIG_NFSD_V4=y
1329CONFIG_LOCKD=m
1330CONFIG_LOCKD_V4=y
1331CONFIG_EXPORTFS=m
1332CONFIG_NFS_COMMON=y
1333CONFIG_SUNRPC=m
1334CONFIG_SUNRPC_GSS=m
1335# CONFIG_SUNRPC_REGISTER_V4 is not set
1336CONFIG_RPCSEC_GSS_KRB5=m
1337# CONFIG_RPCSEC_GSS_SPKM3 is not set
1338CONFIG_SMB_FS=m
1339CONFIG_SMB_NLS_DEFAULT=y
1340CONFIG_SMB_NLS_REMOTE="cp437"
1341CONFIG_CIFS=m
1342# CONFIG_CIFS_STATS is not set
1343# CONFIG_CIFS_WEAK_PW_HASH is not set
1344# CONFIG_CIFS_XATTR is not set
1345# CONFIG_CIFS_DEBUG2 is not set
1346# CONFIG_CIFS_EXPERIMENTAL is not set
1347# CONFIG_NCP_FS is not set
1348# CONFIG_CODA_FS is not set
1349# CONFIG_AFS_FS is not set
1350
1351#
1352# Partition Types
1353#
1354CONFIG_PARTITION_ADVANCED=y
1355# CONFIG_ACORN_PARTITION is not set
1356# CONFIG_OSF_PARTITION is not set
1357# CONFIG_AMIGA_PARTITION is not set
1358# CONFIG_ATARI_PARTITION is not set
1359# CONFIG_MAC_PARTITION is not set
1360CONFIG_MSDOS_PARTITION=y
1361# CONFIG_BSD_DISKLABEL is not set
1362# CONFIG_MINIX_SUBPARTITION is not set
1363# CONFIG_SOLARIS_X86_PARTITION is not set
1364# CONFIG_UNIXWARE_DISKLABEL is not set
1365# CONFIG_LDM_PARTITION is not set
1366CONFIG_SGI_PARTITION=y
1367# CONFIG_ULTRIX_PARTITION is not set
1368# CONFIG_SUN_PARTITION is not set
1369# CONFIG_KARMA_PARTITION is not set
1370CONFIG_EFI_PARTITION=y
1371# CONFIG_SYSV68_PARTITION is not set
1372CONFIG_NLS=y
1373CONFIG_NLS_DEFAULT="iso8859-1"
1374CONFIG_NLS_CODEPAGE_437=y
1375CONFIG_NLS_CODEPAGE_737=m
1376CONFIG_NLS_CODEPAGE_775=m
1377CONFIG_NLS_CODEPAGE_850=m
1378CONFIG_NLS_CODEPAGE_852=m
1379CONFIG_NLS_CODEPAGE_855=m
1380CONFIG_NLS_CODEPAGE_857=m
1381CONFIG_NLS_CODEPAGE_860=m
1382CONFIG_NLS_CODEPAGE_861=m
1383CONFIG_NLS_CODEPAGE_862=m
1384CONFIG_NLS_CODEPAGE_863=m
1385CONFIG_NLS_CODEPAGE_864=m
1386CONFIG_NLS_CODEPAGE_865=m
1387CONFIG_NLS_CODEPAGE_866=m
1388CONFIG_NLS_CODEPAGE_869=m
1389CONFIG_NLS_CODEPAGE_936=m
1390CONFIG_NLS_CODEPAGE_950=m
1391CONFIG_NLS_CODEPAGE_932=m
1392CONFIG_NLS_CODEPAGE_949=m
1393CONFIG_NLS_CODEPAGE_874=m
1394CONFIG_NLS_ISO8859_8=m
1395CONFIG_NLS_CODEPAGE_1250=m
1396CONFIG_NLS_CODEPAGE_1251=m
1397# CONFIG_NLS_ASCII is not set
1398CONFIG_NLS_ISO8859_1=y
1399CONFIG_NLS_ISO8859_2=m
1400CONFIG_NLS_ISO8859_3=m
1401CONFIG_NLS_ISO8859_4=m
1402CONFIG_NLS_ISO8859_5=m
1403CONFIG_NLS_ISO8859_6=m
1404CONFIG_NLS_ISO8859_7=m
1405CONFIG_NLS_ISO8859_9=m
1406CONFIG_NLS_ISO8859_13=m
1407CONFIG_NLS_ISO8859_14=m
1408CONFIG_NLS_ISO8859_15=m
1409CONFIG_NLS_KOI8_R=m
1410CONFIG_NLS_KOI8_U=m
1411CONFIG_NLS_UTF8=m
1412# CONFIG_DLM is not set
1413
1414#
1415# Kernel hacking
1416#
1417# CONFIG_PRINTK_TIME is not set
1418CONFIG_ENABLE_WARN_DEPRECATED=y
1419CONFIG_ENABLE_MUST_CHECK=y
1420CONFIG_FRAME_WARN=2048
1421CONFIG_MAGIC_SYSRQ=y
1422# CONFIG_UNUSED_SYMBOLS is not set
1423# CONFIG_DEBUG_FS is not set
1424# CONFIG_HEADERS_CHECK is not set
1425CONFIG_DEBUG_KERNEL=y
1426# CONFIG_DEBUG_SHIRQ is not set
1427CONFIG_DETECT_SOFTLOCKUP=y
1428# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1429CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1430CONFIG_SCHED_DEBUG=y
1431# CONFIG_SCHEDSTATS is not set
1432# CONFIG_TIMER_STATS is not set
1433# CONFIG_DEBUG_OBJECTS is not set
1434# CONFIG_SLUB_DEBUG_ON is not set
1435# CONFIG_SLUB_STATS is not set
1436# CONFIG_DEBUG_RT_MUTEXES is not set
1437# CONFIG_RT_MUTEX_TESTER is not set
1438# CONFIG_DEBUG_SPINLOCK is not set
1439CONFIG_DEBUG_MUTEXES=y
1440# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1441# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1442# CONFIG_DEBUG_KOBJECT is not set
1443# CONFIG_DEBUG_INFO is not set
1444# CONFIG_DEBUG_VM is not set
1445# CONFIG_DEBUG_WRITECOUNT is not set
1446CONFIG_DEBUG_MEMORY_INIT=y
1447# CONFIG_DEBUG_LIST is not set
1448# CONFIG_DEBUG_SG is not set
1449# CONFIG_DEBUG_NOTIFIERS is not set
1450# CONFIG_BOOT_PRINTK_DELAY is not set
1451# CONFIG_RCU_TORTURE_TEST is not set
1452# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1453# CONFIG_BACKTRACE_SELF_TEST is not set
1454# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
1455# CONFIG_FAULT_INJECTION is not set
1456# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1457
1458#
1459# Tracers
1460#
1461# CONFIG_SCHED_TRACER is not set
1462# CONFIG_CONTEXT_SWITCH_TRACER is not set
1463# CONFIG_BOOT_TRACER is not set
1464# CONFIG_TRACE_BRANCH_PROFILING is not set
1465# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
1466# CONFIG_SAMPLES is not set
1467CONFIG_IA64_GRANULE_16MB=y
1468# CONFIG_IA64_GRANULE_64MB is not set
1469# CONFIG_IA64_PRINT_HAZARDS is not set
1470# CONFIG_DISABLE_VHPT is not set
1471# CONFIG_IA64_DEBUG_CMPXCHG is not set
1472# CONFIG_IA64_DEBUG_IRQ is not set
1473
1474#
1475# Security options
1476#
1477# CONFIG_KEYS is not set
1478# CONFIG_SECURITY is not set
1479# CONFIG_SECURITYFS is not set
1480# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1481CONFIG_CRYPTO=y
1482
1483#
1484# Crypto core or helper
1485#
1486# CONFIG_CRYPTO_FIPS is not set
1487CONFIG_CRYPTO_ALGAPI=y
1488CONFIG_CRYPTO_ALGAPI2=y
1489CONFIG_CRYPTO_AEAD2=y
1490CONFIG_CRYPTO_BLKCIPHER=m
1491CONFIG_CRYPTO_BLKCIPHER2=y
1492CONFIG_CRYPTO_HASH=y
1493CONFIG_CRYPTO_HASH2=y
1494CONFIG_CRYPTO_RNG2=y
1495CONFIG_CRYPTO_MANAGER=m
1496CONFIG_CRYPTO_MANAGER2=y
1497# CONFIG_CRYPTO_GF128MUL is not set
1498# CONFIG_CRYPTO_NULL is not set
1499# CONFIG_CRYPTO_CRYPTD is not set
1500# CONFIG_CRYPTO_AUTHENC is not set
1501# CONFIG_CRYPTO_TEST is not set
1502
1503#
1504# Authenticated Encryption with Associated Data
1505#
1506# CONFIG_CRYPTO_CCM is not set
1507# CONFIG_CRYPTO_GCM is not set
1508# CONFIG_CRYPTO_SEQIV is not set
1509
1510#
1511# Block modes
1512#
1513CONFIG_CRYPTO_CBC=m
1514# CONFIG_CRYPTO_CTR is not set
1515# CONFIG_CRYPTO_CTS is not set
1516CONFIG_CRYPTO_ECB=m
1517# CONFIG_CRYPTO_LRW is not set
1518CONFIG_CRYPTO_PCBC=m
1519# CONFIG_CRYPTO_XTS is not set
1520
1521#
1522# Hash modes
1523#
1524# CONFIG_CRYPTO_HMAC is not set
1525# CONFIG_CRYPTO_XCBC is not set
1526
1527#
1528# Digest
1529#
1530# CONFIG_CRYPTO_CRC32C is not set
1531# CONFIG_CRYPTO_MD4 is not set
1532CONFIG_CRYPTO_MD5=y
1533# CONFIG_CRYPTO_MICHAEL_MIC is not set
1534# CONFIG_CRYPTO_RMD128 is not set
1535# CONFIG_CRYPTO_RMD160 is not set
1536# CONFIG_CRYPTO_RMD256 is not set
1537# CONFIG_CRYPTO_RMD320 is not set
1538# CONFIG_CRYPTO_SHA1 is not set
1539# CONFIG_CRYPTO_SHA256 is not set
1540# CONFIG_CRYPTO_SHA512 is not set
1541# CONFIG_CRYPTO_TGR192 is not set
1542# CONFIG_CRYPTO_WP512 is not set
1543
1544#
1545# Ciphers
1546#
1547# CONFIG_CRYPTO_AES is not set
1548# CONFIG_CRYPTO_ANUBIS is not set
1549# CONFIG_CRYPTO_ARC4 is not set
1550# CONFIG_CRYPTO_BLOWFISH is not set
1551# CONFIG_CRYPTO_CAMELLIA is not set
1552# CONFIG_CRYPTO_CAST5 is not set
1553# CONFIG_CRYPTO_CAST6 is not set
1554CONFIG_CRYPTO_DES=m
1555# CONFIG_CRYPTO_FCRYPT is not set
1556# CONFIG_CRYPTO_KHAZAD is not set
1557# CONFIG_CRYPTO_SALSA20 is not set
1558# CONFIG_CRYPTO_SEED is not set
1559# CONFIG_CRYPTO_SERPENT is not set
1560# CONFIG_CRYPTO_TEA is not set
1561# CONFIG_CRYPTO_TWOFISH is not set
1562
1563#
1564# Compression
1565#
1566# CONFIG_CRYPTO_DEFLATE is not set
1567# CONFIG_CRYPTO_LZO is not set
1568
1569#
1570# Random Number Generation
1571#
1572# CONFIG_CRYPTO_ANSI_CPRNG is not set
1573CONFIG_CRYPTO_HW=y
1574# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1575CONFIG_HAVE_KVM=y
1576CONFIG_VIRTUALIZATION=y
1577# CONFIG_KVM is not set
1578# CONFIG_VIRTIO_PCI is not set
1579# CONFIG_VIRTIO_BALLOON is not set
1580
1581#
1582# Library routines
1583#
1584CONFIG_BITREVERSE=y
1585CONFIG_GENERIC_FIND_LAST_BIT=y
1586# CONFIG_CRC_CCITT is not set
1587# CONFIG_CRC16 is not set
1588# CONFIG_CRC_T10DIF is not set
1589CONFIG_CRC_ITU_T=m
1590CONFIG_CRC32=y
1591# CONFIG_CRC7 is not set
1592# CONFIG_LIBCRC32C is not set
1593CONFIG_PLIST=y
1594CONFIG_HAS_IOMEM=y
1595CONFIG_HAS_IOPORT=y
1596CONFIG_HAS_DMA=y
1597CONFIG_GENERIC_HARDIRQS=y
1598CONFIG_GENERIC_IRQ_PROBE=y
1599CONFIG_GENERIC_PENDING_IRQ=y
1600CONFIG_IRQ_PER_CPU=y
1601# CONFIG_IOMMU_API is not set
diff --git a/arch/ia64/include/asm/kvm.h b/arch/ia64/include/asm/kvm.h
index 68aa6da807c1..bfa86b6af7cd 100644
--- a/arch/ia64/include/asm/kvm.h
+++ b/arch/ia64/include/asm/kvm.h
@@ -25,6 +25,10 @@
25 25
26#include <linux/ioctl.h> 26#include <linux/ioctl.h>
27 27
28/* Select x86 specific features in <linux/kvm.h> */
29#define __KVM_HAVE_IOAPIC
30#define __KVM_HAVE_DEVICE_ASSIGNMENT
31
28/* Architectural interrupt line count. */ 32/* Architectural interrupt line count. */
29#define KVM_NR_INTERRUPTS 256 33#define KVM_NR_INTERRUPTS 256
30 34
diff --git a/arch/ia64/include/asm/mmzone.h b/arch/ia64/include/asm/mmzone.h
index 34efe88eb849..f2ca32069b3f 100644
--- a/arch/ia64/include/asm/mmzone.h
+++ b/arch/ia64/include/asm/mmzone.h
@@ -31,10 +31,6 @@ static inline int pfn_to_nid(unsigned long pfn)
31#endif 31#endif
32} 32}
33 33
34#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
35extern int early_pfn_to_nid(unsigned long pfn);
36#endif
37
38#ifdef CONFIG_IA64_DIG /* DIG systems are small */ 34#ifdef CONFIG_IA64_DIG /* DIG systems are small */
39# define MAX_PHYSNODE_ID 8 35# define MAX_PHYSNODE_ID 8
40# define NR_NODE_MEMBLKS (MAX_NUMNODES * 8) 36# define NR_NODE_MEMBLKS (MAX_NUMNODES * 8)
diff --git a/arch/ia64/include/asm/sn/bte.h b/arch/ia64/include/asm/sn/bte.h
index 5efecf06c9a4..96798d2da7c2 100644
--- a/arch/ia64/include/asm/sn/bte.h
+++ b/arch/ia64/include/asm/sn/bte.h
@@ -39,7 +39,7 @@
39/* BTE status register only supports 16 bits for length field */ 39/* BTE status register only supports 16 bits for length field */
40#define BTE_LEN_BITS (16) 40#define BTE_LEN_BITS (16)
41#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1) 41#define BTE_LEN_MASK ((1 << BTE_LEN_BITS) - 1)
42#define BTE_MAX_XFER ((1 << BTE_LEN_BITS) * L1_CACHE_BYTES) 42#define BTE_MAX_XFER (BTE_LEN_MASK << L1_CACHE_SHIFT)
43 43
44 44
45/* Define hardware */ 45/* Define hardware */
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 5cfd3d91001a..e13125058bed 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -507,7 +507,7 @@ static int iosapic_find_sharable_irq(unsigned long trigger, unsigned long pol)
507 if (trigger == IOSAPIC_EDGE) 507 if (trigger == IOSAPIC_EDGE)
508 return -EINVAL; 508 return -EINVAL;
509 509
510 for (i = 0; i <= NR_IRQS; i++) { 510 for (i = 0; i < NR_IRQS; i++) {
511 info = &iosapic_intr_info[i]; 511 info = &iosapic_intr_info[i];
512 if (info->trigger == trigger && info->polarity == pol && 512 if (info->trigger == trigger && info->polarity == pol &&
513 (info->dmode == IOSAPIC_FIXED || 513 (info->dmode == IOSAPIC_FIXED ||
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index 11463994a7d5..52290547c85b 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -736,14 +736,15 @@ int __cpu_disable(void)
736 return -EBUSY; 736 return -EBUSY;
737 } 737 }
738 738
739 cpu_clear(cpu, cpu_online_map);
740
739 if (migrate_platform_irqs(cpu)) { 741 if (migrate_platform_irqs(cpu)) {
740 cpu_set(cpu, cpu_online_map); 742 cpu_set(cpu, cpu_online_map);
741 return (-EBUSY); 743 return -EBUSY;
742 } 744 }
743 745
744 remove_siblinginfo(cpu); 746 remove_siblinginfo(cpu);
745 fixup_irqs(); 747 fixup_irqs();
746 cpu_clear(cpu, cpu_online_map);
747 local_flush_tlb_all(); 748 local_flush_tlb_all();
748 cpu_clear(cpu, cpu_callin_map); 749 cpu_clear(cpu, cpu_callin_map);
749 return 0; 750 return 0;
diff --git a/arch/ia64/kernel/unwind.c b/arch/ia64/kernel/unwind.c
index 67810b77d998..b6c0e63a0bf6 100644
--- a/arch/ia64/kernel/unwind.c
+++ b/arch/ia64/kernel/unwind.c
@@ -2149,7 +2149,7 @@ unw_remove_unwind_table (void *handle)
2149 2149
2150 /* next, remove hash table entries for this table */ 2150 /* next, remove hash table entries for this table */
2151 2151
2152 for (index = 0; index <= UNW_HASH_SIZE; ++index) { 2152 for (index = 0; index < UNW_HASH_SIZE; ++index) {
2153 tmp = unw.cache + unw.hash[index]; 2153 tmp = unw.cache + unw.hash[index];
2154 if (unw.hash[index] >= UNW_CACHE_SIZE 2154 if (unw.hash[index] >= UNW_CACHE_SIZE
2155 || tmp->ip < table->start || tmp->ip >= table->end) 2155 || tmp->ip < table->start || tmp->ip >= table->end)
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 4e586f6110aa..28f982045f29 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -1337,6 +1337,10 @@ static void kvm_release_vm_pages(struct kvm *kvm)
1337 } 1337 }
1338} 1338}
1339 1339
1340void kvm_arch_sync_events(struct kvm *kvm)
1341{
1342}
1343
1340void kvm_arch_destroy_vm(struct kvm *kvm) 1344void kvm_arch_destroy_vm(struct kvm *kvm)
1341{ 1345{
1342 kvm_iommu_unmap_guest(kvm); 1346 kvm_iommu_unmap_guest(kvm);
diff --git a/arch/ia64/kvm/process.c b/arch/ia64/kvm/process.c
index 552d07724207..230eae482f32 100644
--- a/arch/ia64/kvm/process.c
+++ b/arch/ia64/kvm/process.c
@@ -455,13 +455,18 @@ fpswa_ret_t vmm_fp_emulate(int fp_fault, void *bundle, unsigned long *ipsr,
455 if (!vmm_fpswa_interface) 455 if (!vmm_fpswa_interface)
456 return (fpswa_ret_t) {-1, 0, 0, 0}; 456 return (fpswa_ret_t) {-1, 0, 0, 0};
457 457
458 /*
459 * Just let fpswa driver to use hardware fp registers.
460 * No fp register is valid in memory.
461 */
462 memset(&fp_state, 0, sizeof(fp_state_t)); 458 memset(&fp_state, 0, sizeof(fp_state_t));
463 459
464 /* 460 /*
461 * compute fp_state. only FP registers f6 - f11 are used by the
462 * vmm, so set those bits in the mask and set the low volatile
463 * pointer to point to these registers.
464 */
465 fp_state.bitmask_low64 = 0xfc0; /* bit6..bit11 */
466
467 fp_state.fp_state_low_volatile = (fp_state_low_volatile_t *) &regs->f6;
468
469 /*
465 * unsigned long (*EFI_FPSWA) ( 470 * unsigned long (*EFI_FPSWA) (
466 * unsigned long trap_type, 471 * unsigned long trap_type,
467 * void *Bundle, 472 * void *Bundle,
@@ -545,10 +550,6 @@ void reflect_interruption(u64 ifa, u64 isr, u64 iim,
545 status = vmm_handle_fpu_swa(0, regs, isr); 550 status = vmm_handle_fpu_swa(0, regs, isr);
546 if (!status) 551 if (!status)
547 return ; 552 return ;
548 else if (-EAGAIN == status) {
549 vcpu_decrement_iip(vcpu);
550 return ;
551 }
552 break; 553 break;
553 } 554 }
554 555
diff --git a/arch/ia64/mm/numa.c b/arch/ia64/mm/numa.c
index b73bf1838e57..3efea7d0a351 100644
--- a/arch/ia64/mm/numa.c
+++ b/arch/ia64/mm/numa.c
@@ -58,7 +58,7 @@ paddr_to_nid(unsigned long paddr)
58 * SPARSEMEM to allocate the SPARSEMEM sectionmap on the NUMA node where 58 * SPARSEMEM to allocate the SPARSEMEM sectionmap on the NUMA node where
59 * the section resides. 59 * the section resides.
60 */ 60 */
61int early_pfn_to_nid(unsigned long pfn) 61int __meminit __early_pfn_to_nid(unsigned long pfn)
62{ 62{
63 int i, section = pfn >> PFN_SECTION_SHIFT, ssec, esec; 63 int i, section = pfn >> PFN_SECTION_SHIFT, ssec, esec;
64 64
@@ -70,7 +70,7 @@ int early_pfn_to_nid(unsigned long pfn)
70 return node_memblk[i].nid; 70 return node_memblk[i].nid;
71 } 71 }
72 72
73 return 0; 73 return -1;
74} 74}
75 75
76#ifdef CONFIG_MEMORY_HOTPLUG 76#ifdef CONFIG_MEMORY_HOTPLUG
diff --git a/arch/ia64/sn/kernel/bte.c b/arch/ia64/sn/kernel/bte.c
index 9456d4034024..c6d6b62db66c 100644
--- a/arch/ia64/sn/kernel/bte.c
+++ b/arch/ia64/sn/kernel/bte.c
@@ -97,9 +97,10 @@ bte_result_t bte_copy(u64 src, u64 dest, u64 len, u64 mode, void *notification)
97 return BTE_SUCCESS; 97 return BTE_SUCCESS;
98 } 98 }
99 99
100 BUG_ON((len & L1_CACHE_MASK) || 100 BUG_ON(len & L1_CACHE_MASK);
101 (src & L1_CACHE_MASK) || (dest & L1_CACHE_MASK)); 101 BUG_ON(src & L1_CACHE_MASK);
102 BUG_ON(!(len < ((BTE_LEN_MASK + 1) << L1_CACHE_SHIFT))); 102 BUG_ON(dest & L1_CACHE_MASK);
103 BUG_ON(len > BTE_MAX_XFER);
103 104
104 /* 105 /*
105 * Start with interface corresponding to cpu number 106 * Start with interface corresponding to cpu number
diff --git a/arch/ia64/sn/kernel/io_acpi_init.c b/arch/ia64/sn/kernel/io_acpi_init.c
index c5a214026a77..d0223abbbbd4 100644
--- a/arch/ia64/sn/kernel/io_acpi_init.c
+++ b/arch/ia64/sn/kernel/io_acpi_init.c
@@ -443,7 +443,7 @@ sn_acpi_slot_fixup(struct pci_dev *dev)
443 size = pci_resource_len(dev, PCI_ROM_RESOURCE); 443 size = pci_resource_len(dev, PCI_ROM_RESOURCE);
444 addr = ioremap(pcidev_info->pdi_pio_mapped_addr[PCI_ROM_RESOURCE], 444 addr = ioremap(pcidev_info->pdi_pio_mapped_addr[PCI_ROM_RESOURCE],
445 size); 445 size);
446 image_size = pci_get_rom_size(addr, size); 446 image_size = pci_get_rom_size(dev, addr, size);
447 dev->resource[PCI_ROM_RESOURCE].start = (unsigned long) addr; 447 dev->resource[PCI_ROM_RESOURCE].start = (unsigned long) addr;
448 dev->resource[PCI_ROM_RESOURCE].end = 448 dev->resource[PCI_ROM_RESOURCE].end =
449 (unsigned long) addr + image_size - 1; 449 (unsigned long) addr + image_size - 1;
diff --git a/arch/ia64/sn/kernel/io_init.c b/arch/ia64/sn/kernel/io_init.c
index 4e1801bad83a..e2eb2da60f96 100644
--- a/arch/ia64/sn/kernel/io_init.c
+++ b/arch/ia64/sn/kernel/io_init.c
@@ -269,7 +269,7 @@ sn_io_slot_fixup(struct pci_dev *dev)
269 269
270 rom = ioremap(pci_resource_start(dev, PCI_ROM_RESOURCE), 270 rom = ioremap(pci_resource_start(dev, PCI_ROM_RESOURCE),
271 size + 1); 271 size + 1);
272 image_size = pci_get_rom_size(rom, size + 1); 272 image_size = pci_get_rom_size(dev, rom, size + 1);
273 dev->resource[PCI_ROM_RESOURCE].end = 273 dev->resource[PCI_ROM_RESOURCE].end =
274 dev->resource[PCI_ROM_RESOURCE].start + 274 dev->resource[PCI_ROM_RESOURCE].start +
275 image_size - 1; 275 image_size - 1;
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
index e626e50a938a..060df4aa9916 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c
@@ -135,11 +135,10 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr,
135 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) 135 if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS)
136 pci_addr = IS_PIC_SOFT(pcibus_info) ? 136 pci_addr = IS_PIC_SOFT(pcibus_info) ?
137 PHYS_TO_DMA(paddr) : 137 PHYS_TO_DMA(paddr) :
138 PHYS_TO_TIODMA(paddr) | dma_attributes; 138 PHYS_TO_TIODMA(paddr);
139 else 139 else
140 pci_addr = IS_PIC_SOFT(pcibus_info) ? 140 pci_addr = paddr;
141 paddr : 141 pci_addr |= dma_attributes;
142 paddr | dma_attributes;
143 142
144 /* Handle Bus mode */ 143 /* Handle Bus mode */
145 if (IS_PCIX(pcibus_info)) 144 if (IS_PCIX(pcibus_info))
diff --git a/arch/ia64/xen/Kconfig b/arch/ia64/xen/Kconfig
index f1683a20275b..515e0826803a 100644
--- a/arch/ia64/xen/Kconfig
+++ b/arch/ia64/xen/Kconfig
@@ -8,8 +8,7 @@ config XEN
8 depends on PARAVIRT && MCKINLEY && IA64_PAGE_SIZE_16KB && EXPERIMENTAL 8 depends on PARAVIRT && MCKINLEY && IA64_PAGE_SIZE_16KB && EXPERIMENTAL
9 select XEN_XENCOMM 9 select XEN_XENCOMM
10 select NO_IDLE_HZ 10 select NO_IDLE_HZ
11 11 # followings are required to save/restore.
12 # those are required to save/restore.
13 select ARCH_SUSPEND_POSSIBLE 12 select ARCH_SUSPEND_POSSIBLE
14 select SUSPEND 13 select SUSPEND
15 select PM_SLEEP 14 select PM_SLEEP
diff --git a/arch/ia64/xen/xen_pv_ops.c b/arch/ia64/xen/xen_pv_ops.c
index 04cd12350455..936cff3c96e0 100644
--- a/arch/ia64/xen/xen_pv_ops.c
+++ b/arch/ia64/xen/xen_pv_ops.c
@@ -153,7 +153,7 @@ xen_post_smp_prepare_boot_cpu(void)
153 xen_setup_vcpu_info_placement(); 153 xen_setup_vcpu_info_placement();
154} 154}
155 155
156static const struct pv_init_ops xen_init_ops __initdata = { 156static const struct pv_init_ops xen_init_ops __initconst = {
157 .banner = xen_banner, 157 .banner = xen_banner,
158 158
159 .reserve_memory = xen_reserve_memory, 159 .reserve_memory = xen_reserve_memory,
@@ -337,7 +337,7 @@ xen_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
337 HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op); 337 HYPERVISOR_physdev_op(PHYSDEVOP_apic_write, &apic_op);
338} 338}
339 339
340static const struct pv_iosapic_ops xen_iosapic_ops __initdata = { 340static const struct pv_iosapic_ops xen_iosapic_ops __initconst = {
341 .pcat_compat_init = xen_pcat_compat_init, 341 .pcat_compat_init = xen_pcat_compat_init,
342 .__get_irq_chip = xen_iosapic_get_irq_chip, 342 .__get_irq_chip = xen_iosapic_get_irq_chip,
343 343
diff --git a/arch/m68k/atari/ataints.c b/arch/m68k/atari/ataints.c
index dba4afabb444..39478dd08e67 100644
--- a/arch/m68k/atari/ataints.c
+++ b/arch/m68k/atari/ataints.c
@@ -187,8 +187,8 @@ __asm__ (__ALIGN_STR "\n" \
187" jbra ret_from_interrupt\n" \ 187" jbra ret_from_interrupt\n" \
188 : : "i" (&kstat_cpu(0).irqs[n+8]), "i" (&irq_handler[n+8]), \ 188 : : "i" (&kstat_cpu(0).irqs[n+8]), "i" (&irq_handler[n+8]), \
189 "n" (PT_OFF_SR), "n" (n), \ 189 "n" (PT_OFF_SR), "n" (n), \
190 "i" (n & 8 ? (n & 16 ? &tt_mfp.int_mk_a : &mfp.int_mk_a) \ 190 "i" (n & 8 ? (n & 16 ? &tt_mfp.int_mk_a : &st_mfp.int_mk_a) \
191 : (n & 16 ? &tt_mfp.int_mk_b : &mfp.int_mk_b)), \ 191 : (n & 16 ? &tt_mfp.int_mk_b : &st_mfp.int_mk_b)), \
192 "m" (preempt_count()), "di" (HARDIRQ_OFFSET) \ 192 "m" (preempt_count()), "di" (HARDIRQ_OFFSET) \
193); \ 193); \
194 for (;;); /* fake noreturn */ \ 194 for (;;); /* fake noreturn */ \
@@ -366,14 +366,14 @@ void __init atari_init_IRQ(void)
366 /* Initialize the MFP(s) */ 366 /* Initialize the MFP(s) */
367 367
368#ifdef ATARI_USE_SOFTWARE_EOI 368#ifdef ATARI_USE_SOFTWARE_EOI
369 mfp.vec_adr = 0x48; /* Software EOI-Mode */ 369 st_mfp.vec_adr = 0x48; /* Software EOI-Mode */
370#else 370#else
371 mfp.vec_adr = 0x40; /* Automatic EOI-Mode */ 371 st_mfp.vec_adr = 0x40; /* Automatic EOI-Mode */
372#endif 372#endif
373 mfp.int_en_a = 0x00; /* turn off MFP-Ints */ 373 st_mfp.int_en_a = 0x00; /* turn off MFP-Ints */
374 mfp.int_en_b = 0x00; 374 st_mfp.int_en_b = 0x00;
375 mfp.int_mk_a = 0xff; /* no Masking */ 375 st_mfp.int_mk_a = 0xff; /* no Masking */
376 mfp.int_mk_b = 0xff; 376 st_mfp.int_mk_b = 0xff;
377 377
378 if (ATARIHW_PRESENT(TT_MFP)) { 378 if (ATARIHW_PRESENT(TT_MFP)) {
379#ifdef ATARI_USE_SOFTWARE_EOI 379#ifdef ATARI_USE_SOFTWARE_EOI
diff --git a/arch/m68k/atari/atakeyb.c b/arch/m68k/atari/atakeyb.c
index a5f33c059979..4add96d13b19 100644
--- a/arch/m68k/atari/atakeyb.c
+++ b/arch/m68k/atari/atakeyb.c
@@ -609,10 +609,10 @@ int atari_keyb_init(void)
609 ACIA_RHTID : 0); 609 ACIA_RHTID : 0);
610 610
611 /* make sure the interrupt line is up */ 611 /* make sure the interrupt line is up */
612 } while ((mfp.par_dt_reg & 0x10) == 0); 612 } while ((st_mfp.par_dt_reg & 0x10) == 0);
613 613
614 /* enable ACIA Interrupts */ 614 /* enable ACIA Interrupts */
615 mfp.active_edge &= ~0x10; 615 st_mfp.active_edge &= ~0x10;
616 atari_turnon_irq(IRQ_MFP_ACIA); 616 atari_turnon_irq(IRQ_MFP_ACIA);
617 617
618 ikbd_self_test = 1; 618 ikbd_self_test = 1;
diff --git a/arch/m68k/atari/config.c b/arch/m68k/atari/config.c
index 49c28cdbea5c..ae2d96e5d618 100644
--- a/arch/m68k/atari/config.c
+++ b/arch/m68k/atari/config.c
@@ -258,7 +258,7 @@ void __init config_atari(void)
258 printk("STND_SHIFTER "); 258 printk("STND_SHIFTER ");
259 } 259 }
260 } 260 }
261 if (hwreg_present(&mfp.par_dt_reg)) { 261 if (hwreg_present(&st_mfp.par_dt_reg)) {
262 ATARIHW_SET(ST_MFP); 262 ATARIHW_SET(ST_MFP);
263 printk("ST_MFP "); 263 printk("ST_MFP ");
264 } 264 }
diff --git a/arch/m68k/atari/debug.c b/arch/m68k/atari/debug.c
index 702b15ccfab7..28efdc33c1ae 100644
--- a/arch/m68k/atari/debug.c
+++ b/arch/m68k/atari/debug.c
@@ -34,9 +34,9 @@ static struct console atari_console_driver = {
34 34
35static inline void ata_mfp_out(char c) 35static inline void ata_mfp_out(char c)
36{ 36{
37 while (!(mfp.trn_stat & 0x80)) /* wait for tx buf empty */ 37 while (!(st_mfp.trn_stat & 0x80)) /* wait for tx buf empty */
38 barrier(); 38 barrier();
39 mfp.usart_dta = c; 39 st_mfp.usart_dta = c;
40} 40}
41 41
42static void atari_mfp_console_write(struct console *co, const char *str, 42static void atari_mfp_console_write(struct console *co, const char *str,
@@ -91,7 +91,7 @@ static int ata_par_out(char c)
91 /* This a some-seconds timeout in case no printer is connected */ 91 /* This a some-seconds timeout in case no printer is connected */
92 unsigned long i = loops_per_jiffy > 1 ? loops_per_jiffy : 10000000/HZ; 92 unsigned long i = loops_per_jiffy > 1 ? loops_per_jiffy : 10000000/HZ;
93 93
94 while ((mfp.par_dt_reg & 1) && --i) /* wait for BUSY == L */ 94 while ((st_mfp.par_dt_reg & 1) && --i) /* wait for BUSY == L */
95 ; 95 ;
96 if (!i) 96 if (!i)
97 return 0; 97 return 0;
@@ -131,9 +131,9 @@ static void atari_par_console_write(struct console *co, const char *str,
131#if 0 131#if 0
132int atari_mfp_console_wait_key(struct console *co) 132int atari_mfp_console_wait_key(struct console *co)
133{ 133{
134 while (!(mfp.rcv_stat & 0x80)) /* wait for rx buf filled */ 134 while (!(st_mfp.rcv_stat & 0x80)) /* wait for rx buf filled */
135 barrier(); 135 barrier();
136 return mfp.usart_dta; 136 return st_mfp.usart_dta;
137} 137}
138 138
139int atari_scc_console_wait_key(struct console *co) 139int atari_scc_console_wait_key(struct console *co)
@@ -175,12 +175,12 @@ static void __init atari_init_mfp_port(int cflag)
175 baud = B9600; /* use default 9600bps for non-implemented rates */ 175 baud = B9600; /* use default 9600bps for non-implemented rates */
176 baud -= B1200; /* baud_table[] starts at 1200bps */ 176 baud -= B1200; /* baud_table[] starts at 1200bps */
177 177
178 mfp.trn_stat &= ~0x01; /* disable TX */ 178 st_mfp.trn_stat &= ~0x01; /* disable TX */
179 mfp.usart_ctr = parity | csize | 0x88; /* 1:16 clk mode, 1 stop bit */ 179 st_mfp.usart_ctr = parity | csize | 0x88; /* 1:16 clk mode, 1 stop bit */
180 mfp.tim_ct_cd &= 0x70; /* stop timer D */ 180 st_mfp.tim_ct_cd &= 0x70; /* stop timer D */
181 mfp.tim_dt_d = baud_table[baud]; 181 st_mfp.tim_dt_d = baud_table[baud];
182 mfp.tim_ct_cd |= 0x01; /* start timer D, 1:4 */ 182 st_mfp.tim_ct_cd |= 0x01; /* start timer D, 1:4 */
183 mfp.trn_stat |= 0x01; /* enable TX */ 183 st_mfp.trn_stat |= 0x01; /* enable TX */
184} 184}
185 185
186#define SCC_WRITE(reg, val) \ 186#define SCC_WRITE(reg, val) \
diff --git a/arch/m68k/atari/time.c b/arch/m68k/atari/time.c
index d076ff8d1b39..a0531f34c617 100644
--- a/arch/m68k/atari/time.c
+++ b/arch/m68k/atari/time.c
@@ -27,9 +27,9 @@ void __init
27atari_sched_init(irq_handler_t timer_routine) 27atari_sched_init(irq_handler_t timer_routine)
28{ 28{
29 /* set Timer C data Register */ 29 /* set Timer C data Register */
30 mfp.tim_dt_c = INT_TICKS; 30 st_mfp.tim_dt_c = INT_TICKS;
31 /* start timer C, div = 1:100 */ 31 /* start timer C, div = 1:100 */
32 mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60; 32 st_mfp.tim_ct_cd = (st_mfp.tim_ct_cd & 15) | 0x60;
33 /* install interrupt service routine for MFP Timer C */ 33 /* install interrupt service routine for MFP Timer C */
34 if (request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW, 34 if (request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW,
35 "timer", timer_routine)) 35 "timer", timer_routine))
@@ -46,11 +46,11 @@ unsigned long atari_gettimeoffset (void)
46 unsigned long ticks, offset = 0; 46 unsigned long ticks, offset = 0;
47 47
48 /* read MFP timer C current value */ 48 /* read MFP timer C current value */
49 ticks = mfp.tim_dt_c; 49 ticks = st_mfp.tim_dt_c;
50 /* The probability of underflow is less than 2% */ 50 /* The probability of underflow is less than 2% */
51 if (ticks > INT_TICKS - INT_TICKS / 50) 51 if (ticks > INT_TICKS - INT_TICKS / 50)
52 /* Check for pending timer interrupt */ 52 /* Check for pending timer interrupt */
53 if (mfp.int_pn_b & (1 << 5)) 53 if (st_mfp.int_pn_b & (1 << 5))
54 offset = TICK_SIZE; 54 offset = TICK_SIZE;
55 55
56 ticks = INT_TICKS - ticks; 56 ticks = INT_TICKS - ticks;
diff --git a/arch/m68k/include/asm/atarihw.h b/arch/m68k/include/asm/atarihw.h
index 1412b4ab202f..a714e1aa072a 100644
--- a/arch/m68k/include/asm/atarihw.h
+++ b/arch/m68k/include/asm/atarihw.h
@@ -113,7 +113,7 @@ extern struct atari_hw_present atari_hw_present;
113 * of nops on various machines. Somebody claimed that the tstb takes 600 ns. 113 * of nops on various machines. Somebody claimed that the tstb takes 600 ns.
114 */ 114 */
115#define MFPDELAY() \ 115#define MFPDELAY() \
116 __asm__ __volatile__ ( "tstb %0" : : "m" (mfp.par_dt_reg) : "cc" ); 116 __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" );
117 117
118/* Do cache push/invalidate for DMA read/write. This function obeys the 118/* Do cache push/invalidate for DMA read/write. This function obeys the
119 * snooping on some machines (Medusa) and processors: The Medusa itself can 119 * snooping on some machines (Medusa) and processors: The Medusa itself can
@@ -565,7 +565,7 @@ struct MFP
565 u_char char_dummy23; 565 u_char char_dummy23;
566 u_char usart_dta; 566 u_char usart_dta;
567 }; 567 };
568# define mfp ((*(volatile struct MFP*)MFP_BAS)) 568# define st_mfp ((*(volatile struct MFP*)MFP_BAS))
569 569
570/* TT's second MFP */ 570/* TT's second MFP */
571 571
diff --git a/arch/m68k/include/asm/atariints.h b/arch/m68k/include/asm/atariints.h
index 5748e99f4e26..f597892e43a0 100644
--- a/arch/m68k/include/asm/atariints.h
+++ b/arch/m68k/include/asm/atariints.h
@@ -113,7 +113,7 @@ static inline int get_mfp_bit( unsigned irq, int type )
113{ unsigned char mask, *reg; 113{ unsigned char mask, *reg;
114 114
115 mask = 1 << (irq & 7); 115 mask = 1 << (irq & 7);
116 reg = (unsigned char *)&mfp.int_en_a + type*4 + 116 reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
117 ((irq & 8) >> 2) + (((irq-8) & 16) << 3); 117 ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
118 return( *reg & mask ); 118 return( *reg & mask );
119} 119}
@@ -123,7 +123,7 @@ static inline void set_mfp_bit( unsigned irq, int type )
123{ unsigned char mask, *reg; 123{ unsigned char mask, *reg;
124 124
125 mask = 1 << (irq & 7); 125 mask = 1 << (irq & 7);
126 reg = (unsigned char *)&mfp.int_en_a + type*4 + 126 reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
127 ((irq & 8) >> 2) + (((irq-8) & 16) << 3); 127 ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
128 __asm__ __volatile__ ( "orb %0,%1" 128 __asm__ __volatile__ ( "orb %0,%1"
129 : : "di" (mask), "m" (*reg) : "memory" ); 129 : : "di" (mask), "m" (*reg) : "memory" );
@@ -134,7 +134,7 @@ static inline void clear_mfp_bit( unsigned irq, int type )
134{ unsigned char mask, *reg; 134{ unsigned char mask, *reg;
135 135
136 mask = ~(1 << (irq & 7)); 136 mask = ~(1 << (irq & 7));
137 reg = (unsigned char *)&mfp.int_en_a + type*4 + 137 reg = (unsigned char *)&st_mfp.int_en_a + type*4 +
138 ((irq & 8) >> 2) + (((irq-8) & 16) << 3); 138 ((irq & 8) >> 2) + (((irq-8) & 16) << 3);
139 if (type == MFP_PENDING || type == MFP_SERVICE) 139 if (type == MFP_PENDING || type == MFP_SERVICE)
140 __asm__ __volatile__ ( "moveb %0,%1" 140 __asm__ __volatile__ ( "moveb %0,%1"
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index d01a5d2b7557..db902540bf2c 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -17,6 +17,7 @@
17#include <asm/coldfire.h> 17#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 18#include <asm/mcfsim.h>
19#include <asm/mcfdma.h> 19#include <asm/mcfdma.h>
20#include <asm/mcfuart.h>
20 21
21/***************************************************************************/ 22/***************************************************************************/
22 23
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index dfdb5c2ed8e6..44baeb225dc7 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -24,7 +24,6 @@
24#include <asm/coldfire.h> 24#include <asm/coldfire.h>
25#include <asm/mcfsim.h> 25#include <asm/mcfsim.h>
26#include <asm/mcfuart.h> 26#include <asm/mcfuart.h>
27#include <asm/mcfqspi.h>
28 27
29#ifdef CONFIG_MTD_PARTITIONS 28#ifdef CONFIG_MTD_PARTITIONS
30#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
@@ -33,233 +32,6 @@
33/***************************************************************************/ 32/***************************************************************************/
34 33
35void coldfire_reset(void); 34void coldfire_reset(void);
36static void coldfire_qspi_cs_control(u8 cs, u8 command);
37
38/***************************************************************************/
39
40#if defined(CONFIG_SPI)
41
42#if defined(CONFIG_WILDFIRE)
43#define SPI_NUM_CHIPSELECTS 0x02
44#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
45#define SPI_CS_MASK 0x18
46
47#define FLASH_BLOCKSIZE (1024*64)
48#define FLASH_NUMBLOCKS 16
49#define FLASH_TYPE "m25p80"
50
51#define M25P80_CS 0
52#define MMC_CS 1
53
54#ifdef CONFIG_MTD_PARTITIONS
55static struct mtd_partition stm25p_partitions[] = {
56 /* sflash */
57 [0] = {
58 .name = "stm25p80",
59 .offset = 0x00000000,
60 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
61 .mask_flags = 0
62 }
63};
64
65#endif
66
67#elif defined(CONFIG_WILDFIREMOD)
68
69#define SPI_NUM_CHIPSELECTS 0x08
70#define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */
71#define SPI_CS_MASK 0x78
72
73#define FLASH_BLOCKSIZE (1024*64)
74#define FLASH_NUMBLOCKS 64
75#define FLASH_TYPE "m25p32"
76/* Reserve 1M for the kernel parition */
77#define FLASH_KERNEL_SIZE (1024 * 1024)
78
79#define M25P80_CS 5
80#define MMC_CS 6
81
82#ifdef CONFIG_MTD_PARTITIONS
83static struct mtd_partition stm25p_partitions[] = {
84 /* sflash */
85 [0] = {
86 .name = "kernel",
87 .offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
88 .size = FLASH_KERNEL_SIZE,
89 .mask_flags = 0
90 },
91 [1] = {
92 .name = "image",
93 .offset = 0x00000000,
94 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE,
95 .mask_flags = 0
96 },
97 [2] = {
98 .name = "all",
99 .offset = 0x00000000,
100 .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS,
101 .mask_flags = 0
102 }
103};
104#endif
105
106#else
107#define SPI_NUM_CHIPSELECTS 0x04
108#define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */
109#endif
110
111#ifdef MMC_CS
112static struct coldfire_spi_chip flash_chip_info = {
113 .mode = SPI_MODE_0,
114 .bits_per_word = 16,
115 .del_cs_to_clk = 17,
116 .del_after_trans = 1,
117 .void_write_data = 0
118};
119
120static struct coldfire_spi_chip mmc_chip_info = {
121 .mode = SPI_MODE_0,
122 .bits_per_word = 16,
123 .del_cs_to_clk = 17,
124 .del_after_trans = 1,
125 .void_write_data = 0xFFFF
126};
127#endif
128
129#ifdef M25P80_CS
130static struct flash_platform_data stm25p80_platform_data = {
131 .name = "ST M25P80 SPI Flash chip",
132#ifdef CONFIG_MTD_PARTITIONS
133 .parts = stm25p_partitions,
134 .nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions),
135#endif
136 .type = FLASH_TYPE
137};
138#endif
139
140static struct spi_board_info spi_board_info[] __initdata = {
141#ifdef M25P80_CS
142 {
143 .modalias = "m25p80",
144 .max_speed_hz = 16000000,
145 .bus_num = 1,
146 .chip_select = M25P80_CS,
147 .platform_data = &stm25p80_platform_data,
148 .controller_data = &flash_chip_info
149 },
150#endif
151#ifdef MMC_CS
152 {
153 .modalias = "mmc_spi",
154 .max_speed_hz = 16000000,
155 .bus_num = 1,
156 .chip_select = MMC_CS,
157 .controller_data = &mmc_chip_info
158 }
159#endif
160};
161
162static struct coldfire_spi_master coldfire_master_info = {
163 .bus_num = 1,
164 .num_chipselect = SPI_NUM_CHIPSELECTS,
165 .irq_source = MCF5282_QSPI_IRQ_SOURCE,
166 .irq_vector = MCF5282_QSPI_IRQ_VECTOR,
167 .irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01),
168 .irq_lp = 0x2B, /* Level 5 and Priority 3 */
169 .par_val = SPI_PAR_VAL,
170 .cs_control = coldfire_qspi_cs_control,
171};
172
173static struct resource coldfire_spi_resources[] = {
174 [0] = {
175 .name = "qspi-par",
176 .start = MCF5282_QSPI_PAR,
177 .end = MCF5282_QSPI_PAR,
178 .flags = IORESOURCE_MEM
179 },
180
181 [1] = {
182 .name = "qspi-module",
183 .start = MCF5282_QSPI_QMR,
184 .end = MCF5282_QSPI_QMR + 0x18,
185 .flags = IORESOURCE_MEM
186 },
187
188 [2] = {
189 .name = "qspi-int-level",
190 .start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
191 .end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE,
192 .flags = IORESOURCE_MEM
193 },
194
195 [3] = {
196 .name = "qspi-int-mask",
197 .start = MCF5282_INTC0 + MCFINTC_IMRL,
198 .end = MCF5282_INTC0 + MCFINTC_IMRL,
199 .flags = IORESOURCE_MEM
200 }
201};
202
203static struct platform_device coldfire_spi = {
204 .name = "spi_coldfire",
205 .id = -1,
206 .resource = coldfire_spi_resources,
207 .num_resources = ARRAY_SIZE(coldfire_spi_resources),
208 .dev = {
209 .platform_data = &coldfire_master_info,
210 }
211};
212
213static void coldfire_qspi_cs_control(u8 cs, u8 command)
214{
215 u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK;
216
217#if defined(CONFIG_WILDFIRE)
218 u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK);
219#endif
220#if defined(CONFIG_WILDFIREMOD)
221 u8 cs_mask = (cs << 3) & SPI_CS_MASK;
222#endif
223
224 /*
225 * Don't do anything if the chip select is not
226 * one of the port qs pins.
227 */
228 if (command & QSPI_CS_INIT) {
229#if defined(CONFIG_WILDFIRE)
230 MCF5282_GPIO_DDRQS |= cs_bit;
231 MCF5282_GPIO_PQSPAR &= ~cs_bit;
232#endif
233
234#if defined(CONFIG_WILDFIREMOD)
235 MCF5282_GPIO_DDRQS |= SPI_CS_MASK;
236 MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK;
237#endif
238 }
239
240 if (command & QSPI_CS_ASSERT) {
241 MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK;
242 MCF5282_GPIO_PORTQS |= cs_mask;
243 } else if (command & QSPI_CS_DROP) {
244 MCF5282_GPIO_PORTQS |= SPI_CS_MASK;
245 }
246}
247
248static int __init spi_dev_init(void)
249{
250 int retval;
251
252 retval = platform_device_register(&coldfire_spi);
253 if (retval < 0)
254 return retval;
255
256 if (ARRAY_SIZE(spi_board_info))
257 retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
258
259 return retval;
260}
261
262#endif /* CONFIG_SPI */
263 35
264/***************************************************************************/ 36/***************************************************************************/
265 37
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 600eef3f3ac7..e61465a18c7e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR
603 select SYS_SUPPORTS_64BIT_KERNEL 603 select SYS_SUPPORTS_64BIT_KERNEL
604 select SYS_SUPPORTS_BIG_ENDIAN 604 select SYS_SUPPORTS_BIG_ENDIAN
605 select SYS_SUPPORTS_HIGHMEM 605 select SYS_SUPPORTS_HIGHMEM
606 select CPU_CAVIUM_OCTEON 606 select SYS_HAS_CPU_CAVIUM_OCTEON
607 help 607 help
608 The Octeon simulator is software performance model of the Cavium 608 The Octeon simulator is software performance model of the Cavium
609 Octeon Processor. It supports simulating Octeon processors on x86 609 Octeon Processor. It supports simulating Octeon processors on x86
@@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
618 select SYS_SUPPORTS_BIG_ENDIAN 618 select SYS_SUPPORTS_BIG_ENDIAN
619 select SYS_SUPPORTS_HIGHMEM 619 select SYS_SUPPORTS_HIGHMEM
620 select SYS_HAS_EARLY_PRINTK 620 select SYS_HAS_EARLY_PRINTK
621 select CPU_CAVIUM_OCTEON 621 select SYS_HAS_CPU_CAVIUM_OCTEON
622 select SWAP_IO_SPACE 622 select SWAP_IO_SPACE
623 help 623 help
624 This option supports all of the Octeon reference boards from Cavium 624 This option supports all of the Octeon reference boards from Cavium
@@ -1234,6 +1234,7 @@ config CPU_SB1
1234 1234
1235config CPU_CAVIUM_OCTEON 1235config CPU_CAVIUM_OCTEON
1236 bool "Cavium Octeon processor" 1236 bool "Cavium Octeon processor"
1237 depends on SYS_HAS_CPU_CAVIUM_OCTEON
1237 select IRQ_CPU 1238 select IRQ_CPU
1238 select IRQ_CPU_OCTEON 1239 select IRQ_CPU_OCTEON
1239 select CPU_HAS_PREFETCH 1240 select CPU_HAS_PREFETCH
@@ -1314,6 +1315,9 @@ config SYS_HAS_CPU_RM9000
1314config SYS_HAS_CPU_SB1 1315config SYS_HAS_CPU_SB1
1315 bool 1316 bool
1316 1317
1318config SYS_HAS_CPU_CAVIUM_OCTEON
1319 bool
1320
1317# 1321#
1318# CPU may reorder R->R, R->W, W->R, W->W 1322# CPU may reorder R->R, R->W, W->R, W->W
1319# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC 1323# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
@@ -1387,6 +1391,7 @@ config 32BIT
1387config 64BIT 1391config 64BIT
1388 bool "64-bit kernel" 1392 bool "64-bit kernel"
1389 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL 1393 depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
1394 select HAVE_SYSCALL_WRAPPERS
1390 help 1395 help
1391 Select this option if you want to build a 64-bit kernel. 1396 Select this option if you want to build a 64-bit kernel.
1392 1397
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 6fd441d16af5..f58d4ffb8945 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -118,7 +118,7 @@ void __init plat_time_init(void)
118 * setup counter 1 (RTC) to tick at full speed 118 * setup counter 1 (RTC) to tick at full speed
119 */ 119 */
120 t = 0xffffff; 120 t = 0xffffff;
121 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) 121 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t)
122 asm volatile ("nop"); 122 asm volatile ("nop");
123 if (!t) 123 if (!t)
124 goto cntr_err; 124 goto cntr_err;
@@ -127,7 +127,7 @@ void __init plat_time_init(void)
127 au_sync(); 127 au_sync();
128 128
129 t = 0xffffff; 129 t = 0xffffff;
130 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) 130 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
131 asm volatile ("nop"); 131 asm volatile ("nop");
132 if (!t) 132 if (!t)
133 goto cntr_err; 133 goto cntr_err;
@@ -135,7 +135,7 @@ void __init plat_time_init(void)
135 au_sync(); 135 au_sync();
136 136
137 t = 0xffffff; 137 t = 0xffffff;
138 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) 138 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t)
139 asm volatile ("nop"); 139 asm volatile ("nop");
140 if (!t) 140 if (!t)
141 goto cntr_err; 141 goto cntr_err;
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h
index ac5d541368e9..6c5b40905dd6 100644
--- a/arch/mips/include/asm/compat.h
+++ b/arch/mips/include/asm/compat.h
@@ -3,6 +3,8 @@
3/* 3/*
4 * Architecture specific compatibility types 4 * Architecture specific compatibility types
5 */ 5 */
6#include <linux/seccomp.h>
7#include <linux/thread_info.h>
6#include <linux/types.h> 8#include <linux/types.h>
7#include <asm/page.h> 9#include <asm/page.h>
8#include <asm/ptrace.h> 10#include <asm/ptrace.h>
@@ -218,4 +220,9 @@ struct compat_shmid64_ds {
218 compat_ulong_t __unused2; 220 compat_ulong_t __unused2;
219}; 221};
220 222
223static inline int is_compat_task(void)
224{
225 return test_thread_flag(TIF_32BIT);
226}
227
221#endif /* _ASM_COMPAT_H */ 228#endif /* _ASM_COMPAT_H */
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h
index 36ed44070256..a6772e9507f5 100644
--- a/arch/mips/include/asm/seccomp.h
+++ b/arch/mips/include/asm/seccomp.h
@@ -1,6 +1,5 @@
1#ifndef __ASM_SECCOMP_H 1#ifndef __ASM_SECCOMP_H
2 2
3#include <linux/thread_info.h>
4#include <linux/unistd.h> 3#include <linux/unistd.h>
5 4
6#define __NR_seccomp_read __NR_read 5#define __NR_seccomp_read __NR_read
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h
index 1a1f320c30d8..0884947ebe27 100644
--- a/arch/mips/include/asm/spinlock.h
+++ b/arch/mips/include/asm/spinlock.h
@@ -51,6 +51,7 @@ static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
51 51
52 return (((counters >> 14) - counters) & 0x1fff) > 1; 52 return (((counters >> 14) - counters) & 0x1fff) > 1;
53} 53}
54#define __raw_spin_is_contended __raw_spin_is_contended
54 55
55static inline void __raw_spin_lock(raw_spinlock_t *lock) 56static inline void __raw_spin_lock(raw_spinlock_t *lock)
56{ 57{
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a0ff2b66e22b..4b4007b3083a 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -111,7 +111,6 @@ int show_interrupts(struct seq_file *p, void *v)
111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
112#endif 112#endif
113 seq_printf(p, " %14s", irq_desc[i].chip->name); 113 seq_printf(p, " %14s", irq_desc[i].chip->name);
114 seq_printf(p, "-%-8s", irq_desc[i].name);
115 seq_printf(p, " %s", action->name); 114 seq_printf(p, " %s", action->name);
116 115
117 for (action=action->next; action; action = action->next) 116 for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index aa2c55e3b55f..2f8452b404c7 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -32,6 +32,7 @@
32#include <linux/module.h> 32#include <linux/module.h>
33#include <linux/binfmts.h> 33#include <linux/binfmts.h>
34#include <linux/security.h> 34#include <linux/security.h>
35#include <linux/syscalls.h>
35#include <linux/compat.h> 36#include <linux/compat.h>
36#include <linux/vfs.h> 37#include <linux/vfs.h>
37#include <linux/ipc.h> 38#include <linux/ipc.h>
@@ -63,9 +64,9 @@
63#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) 64#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL))
64#endif 65#endif
65 66
66asmlinkage unsigned long 67SYSCALL_DEFINE6(32_mmap2, unsigned long, addr, unsigned long, len,
67sys32_mmap2(unsigned long addr, unsigned long len, unsigned long prot, 68 unsigned long, prot, unsigned long, flags, unsigned long, fd,
68 unsigned long flags, unsigned long fd, unsigned long pgoff) 69 unsigned long, pgoff)
69{ 70{
70 struct file * file = NULL; 71 struct file * file = NULL;
71 unsigned long error; 72 unsigned long error;
@@ -121,21 +122,21 @@ struct rlimit32 {
121 int rlim_max; 122 int rlim_max;
122}; 123};
123 124
124asmlinkage long sys32_truncate64(const char __user * path, 125SYSCALL_DEFINE4(32_truncate64, const char __user *, path,
125 unsigned long __dummy, int a2, int a3) 126 unsigned long, __dummy, unsigned long, a2, unsigned long, a3)
126{ 127{
127 return sys_truncate(path, merge_64(a2, a3)); 128 return sys_truncate(path, merge_64(a2, a3));
128} 129}
129 130
130asmlinkage long sys32_ftruncate64(unsigned int fd, unsigned long __dummy, 131SYSCALL_DEFINE4(32_ftruncate64, unsigned long, fd, unsigned long, __dummy,
131 int a2, int a3) 132 unsigned long, a2, unsigned long, a3)
132{ 133{
133 return sys_ftruncate(fd, merge_64(a2, a3)); 134 return sys_ftruncate(fd, merge_64(a2, a3));
134} 135}
135 136
136asmlinkage int sys32_llseek(unsigned int fd, unsigned int offset_high, 137SYSCALL_DEFINE5(32_llseek, unsigned long, fd, unsigned long, offset_high,
137 unsigned int offset_low, loff_t __user * result, 138 unsigned long, offset_low, loff_t __user *, result,
138 unsigned int origin) 139 unsigned long, origin)
139{ 140{
140 return sys_llseek(fd, offset_high, offset_low, result, origin); 141 return sys_llseek(fd, offset_high, offset_low, result, origin);
141} 142}
@@ -144,20 +145,20 @@ asmlinkage int sys32_llseek(unsigned int fd, unsigned int offset_high,
144 lseek back to original location. They fail just like lseek does on 145 lseek back to original location. They fail just like lseek does on
145 non-seekable files. */ 146 non-seekable files. */
146 147
147asmlinkage ssize_t sys32_pread(unsigned int fd, char __user * buf, 148SYSCALL_DEFINE6(32_pread, unsigned long, fd, char __user *, buf, size_t, count,
148 size_t count, u32 unused, u64 a4, u64 a5) 149 unsigned long, unused, unsigned long, a4, unsigned long, a5)
149{ 150{
150 return sys_pread64(fd, buf, count, merge_64(a4, a5)); 151 return sys_pread64(fd, buf, count, merge_64(a4, a5));
151} 152}
152 153
153asmlinkage ssize_t sys32_pwrite(unsigned int fd, const char __user * buf, 154SYSCALL_DEFINE6(32_pwrite, unsigned int, fd, const char __user *, buf,
154 size_t count, u32 unused, u64 a4, u64 a5) 155 size_t, count, u32, unused, u64, a4, u64, a5)
155{ 156{
156 return sys_pwrite64(fd, buf, count, merge_64(a4, a5)); 157 return sys_pwrite64(fd, buf, count, merge_64(a4, a5));
157} 158}
158 159
159asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid, 160SYSCALL_DEFINE2(32_sched_rr_get_interval, compat_pid_t, pid,
160 struct compat_timespec __user *interval) 161 struct compat_timespec __user *, interval)
161{ 162{
162 struct timespec t; 163 struct timespec t;
163 int ret; 164 int ret;
@@ -174,8 +175,8 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
174 175
175#ifdef CONFIG_SYSVIPC 176#ifdef CONFIG_SYSVIPC
176 177
177asmlinkage long 178SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third,
178sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth) 179 unsigned long, ptr, unsigned long, fifth)
179{ 180{
180 int version, err; 181 int version, err;
181 182
@@ -233,8 +234,8 @@ sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
233 234
234#else 235#else
235 236
236asmlinkage long 237SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third,
237sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth) 238 u32, ptr, u32 fifth)
238{ 239{
239 return -ENOSYS; 240 return -ENOSYS;
240} 241}
@@ -242,7 +243,7 @@ sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
242#endif /* CONFIG_SYSVIPC */ 243#endif /* CONFIG_SYSVIPC */
243 244
244#ifdef CONFIG_MIPS32_N32 245#ifdef CONFIG_MIPS32_N32
245asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, u32 arg) 246SYSCALL_DEFINE4(n32_semctl, int, semid, int, semnum, int, cmd, u32, arg)
246{ 247{
247 /* compat_sys_semctl expects a pointer to union semun */ 248 /* compat_sys_semctl expects a pointer to union semun */
248 u32 __user *uptr = compat_alloc_user_space(sizeof(u32)); 249 u32 __user *uptr = compat_alloc_user_space(sizeof(u32));
@@ -251,13 +252,14 @@ asmlinkage long sysn32_semctl(int semid, int semnum, int cmd, u32 arg)
251 return compat_sys_semctl(semid, semnum, cmd, uptr); 252 return compat_sys_semctl(semid, semnum, cmd, uptr);
252} 253}
253 254
254asmlinkage long sysn32_msgsnd(int msqid, u32 msgp, unsigned msgsz, int msgflg) 255SYSCALL_DEFINE4(n32_msgsnd, int, msqid, u32, msgp, unsigned int, msgsz,
256 int, msgflg)
255{ 257{
256 return compat_sys_msgsnd(msqid, msgsz, msgflg, compat_ptr(msgp)); 258 return compat_sys_msgsnd(msqid, msgsz, msgflg, compat_ptr(msgp));
257} 259}
258 260
259asmlinkage long sysn32_msgrcv(int msqid, u32 msgp, size_t msgsz, int msgtyp, 261SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz,
260 int msgflg) 262 int, msgtyp, int, msgflg)
261{ 263{
262 return compat_sys_msgrcv(msqid, msgsz, msgtyp, msgflg, IPC_64, 264 return compat_sys_msgrcv(msqid, msgsz, msgtyp, msgflg, IPC_64,
263 compat_ptr(msgp)); 265 compat_ptr(msgp));
@@ -277,7 +279,7 @@ struct sysctl_args32
277 279
278#ifdef CONFIG_SYSCTL_SYSCALL 280#ifdef CONFIG_SYSCTL_SYSCALL
279 281
280asmlinkage long sys32_sysctl(struct sysctl_args32 __user *args) 282SYSCALL_DEFINE1(32_sysctl, struct sysctl_args32 __user *, args)
281{ 283{
282 struct sysctl_args32 tmp; 284 struct sysctl_args32 tmp;
283 int error; 285 int error;
@@ -316,9 +318,16 @@ asmlinkage long sys32_sysctl(struct sysctl_args32 __user *args)
316 return error; 318 return error;
317} 319}
318 320
321#else
322
323SYSCALL_DEFINE1(32_sysctl, struct sysctl_args32 __user *, args)
324{
325 return -ENOSYS;
326}
327
319#endif /* CONFIG_SYSCTL_SYSCALL */ 328#endif /* CONFIG_SYSCTL_SYSCALL */
320 329
321asmlinkage long sys32_newuname(struct new_utsname __user * name) 330SYSCALL_DEFINE1(32_newuname, struct new_utsname __user *, name)
322{ 331{
323 int ret = 0; 332 int ret = 0;
324 333
@@ -334,7 +343,7 @@ asmlinkage long sys32_newuname(struct new_utsname __user * name)
334 return ret; 343 return ret;
335} 344}
336 345
337asmlinkage int sys32_personality(unsigned long personality) 346SYSCALL_DEFINE1(32_personality, unsigned long, personality)
338{ 347{
339 int ret; 348 int ret;
340 personality &= 0xffffffff; 349 personality &= 0xffffffff;
@@ -357,7 +366,7 @@ struct ustat32 {
357 366
358extern asmlinkage long sys_ustat(dev_t dev, struct ustat __user * ubuf); 367extern asmlinkage long sys_ustat(dev_t dev, struct ustat __user * ubuf);
359 368
360asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32) 369SYSCALL_DEFINE2(32_ustat, dev_t, dev, struct ustat32 __user *, ubuf32)
361{ 370{
362 int err; 371 int err;
363 struct ustat tmp; 372 struct ustat tmp;
@@ -381,8 +390,8 @@ out:
381 return err; 390 return err;
382} 391}
383 392
384asmlinkage int sys32_sendfile(int out_fd, int in_fd, compat_off_t __user *offset, 393SYSCALL_DEFINE4(32_sendfile, long, out_fd, long, in_fd,
385 s32 count) 394 compat_off_t __user *, offset, s32, count)
386{ 395{
387 mm_segment_t old_fs = get_fs(); 396 mm_segment_t old_fs = get_fs();
388 int ret; 397 int ret;
diff --git a/arch/mips/kernel/scall32-o32.S b/arch/mips/kernel/scall32-o32.S
index 51d1ba415b90..9ab70c3b5be6 100644
--- a/arch/mips/kernel/scall32-o32.S
+++ b/arch/mips/kernel/scall32-o32.S
@@ -399,7 +399,7 @@ einval: li v0, -ENOSYS
399 sys sys_swapon 2 399 sys sys_swapon 2
400 sys sys_reboot 3 400 sys sys_reboot 3
401 sys sys_old_readdir 3 401 sys sys_old_readdir 3
402 sys old_mmap 6 /* 4090 */ 402 sys sys_mips_mmap 6 /* 4090 */
403 sys sys_munmap 2 403 sys sys_munmap 2
404 sys sys_truncate 2 404 sys sys_truncate 2
405 sys sys_ftruncate 2 405 sys sys_ftruncate 2
@@ -519,7 +519,7 @@ einval: li v0, -ENOSYS
519 sys sys_sendfile 4 519 sys sys_sendfile 4
520 sys sys_ni_syscall 0 520 sys sys_ni_syscall 0
521 sys sys_ni_syscall 0 521 sys sys_ni_syscall 0
522 sys sys_mmap2 6 /* 4210 */ 522 sys sys_mips_mmap2 6 /* 4210 */
523 sys sys_truncate64 4 523 sys sys_truncate64 4
524 sys sys_ftruncate64 4 524 sys sys_ftruncate64 4
525 sys sys_stat64 2 525 sys sys_stat64 2
diff --git a/arch/mips/kernel/scall64-64.S b/arch/mips/kernel/scall64-64.S
index a9e171618994..9b4698667154 100644
--- a/arch/mips/kernel/scall64-64.S
+++ b/arch/mips/kernel/scall64-64.S
@@ -207,7 +207,7 @@ sys_call_table:
207 PTR sys_newlstat 207 PTR sys_newlstat
208 PTR sys_poll 208 PTR sys_poll
209 PTR sys_lseek 209 PTR sys_lseek
210 PTR old_mmap 210 PTR sys_mips_mmap
211 PTR sys_mprotect /* 5010 */ 211 PTR sys_mprotect /* 5010 */
212 PTR sys_munmap 212 PTR sys_munmap
213 PTR sys_brk 213 PTR sys_brk
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 30f3b6317a83..7438e92f8a01 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -129,12 +129,12 @@ EXPORT(sysn32_call_table)
129 PTR sys_newlstat 129 PTR sys_newlstat
130 PTR sys_poll 130 PTR sys_poll
131 PTR sys_lseek 131 PTR sys_lseek
132 PTR old_mmap 132 PTR sys_mips_mmap
133 PTR sys_mprotect /* 6010 */ 133 PTR sys_mprotect /* 6010 */
134 PTR sys_munmap 134 PTR sys_munmap
135 PTR sys_brk 135 PTR sys_brk
136 PTR sys32_rt_sigaction 136 PTR sys_32_rt_sigaction
137 PTR sys32_rt_sigprocmask 137 PTR sys_32_rt_sigprocmask
138 PTR compat_sys_ioctl /* 6015 */ 138 PTR compat_sys_ioctl /* 6015 */
139 PTR sys_pread64 139 PTR sys_pread64
140 PTR sys_pwrite64 140 PTR sys_pwrite64
@@ -159,7 +159,7 @@ EXPORT(sysn32_call_table)
159 PTR compat_sys_setitimer 159 PTR compat_sys_setitimer
160 PTR sys_alarm 160 PTR sys_alarm
161 PTR sys_getpid 161 PTR sys_getpid
162 PTR sys32_sendfile 162 PTR sys_32_sendfile
163 PTR sys_socket /* 6040 */ 163 PTR sys_socket /* 6040 */
164 PTR sys_connect 164 PTR sys_connect
165 PTR sys_accept 165 PTR sys_accept
@@ -181,14 +181,14 @@ EXPORT(sysn32_call_table)
181 PTR sys_exit 181 PTR sys_exit
182 PTR compat_sys_wait4 182 PTR compat_sys_wait4
183 PTR sys_kill /* 6060 */ 183 PTR sys_kill /* 6060 */
184 PTR sys32_newuname 184 PTR sys_32_newuname
185 PTR sys_semget 185 PTR sys_semget
186 PTR sys_semop 186 PTR sys_semop
187 PTR sysn32_semctl 187 PTR sys_n32_semctl
188 PTR sys_shmdt /* 6065 */ 188 PTR sys_shmdt /* 6065 */
189 PTR sys_msgget 189 PTR sys_msgget
190 PTR sysn32_msgsnd 190 PTR sys_n32_msgsnd
191 PTR sysn32_msgrcv 191 PTR sys_n32_msgrcv
192 PTR compat_sys_msgctl 192 PTR compat_sys_msgctl
193 PTR compat_sys_fcntl /* 6070 */ 193 PTR compat_sys_fcntl /* 6070 */
194 PTR sys_flock 194 PTR sys_flock
@@ -245,15 +245,15 @@ EXPORT(sysn32_call_table)
245 PTR sys_getsid 245 PTR sys_getsid
246 PTR sys_capget 246 PTR sys_capget
247 PTR sys_capset 247 PTR sys_capset
248 PTR sys32_rt_sigpending /* 6125 */ 248 PTR sys_32_rt_sigpending /* 6125 */
249 PTR compat_sys_rt_sigtimedwait 249 PTR compat_sys_rt_sigtimedwait
250 PTR sys32_rt_sigqueueinfo 250 PTR sys_32_rt_sigqueueinfo
251 PTR sysn32_rt_sigsuspend 251 PTR sysn32_rt_sigsuspend
252 PTR sys32_sigaltstack 252 PTR sys32_sigaltstack
253 PTR compat_sys_utime /* 6130 */ 253 PTR compat_sys_utime /* 6130 */
254 PTR sys_mknod 254 PTR sys_mknod
255 PTR sys32_personality 255 PTR sys_32_personality
256 PTR sys32_ustat 256 PTR sys_32_ustat
257 PTR compat_sys_statfs 257 PTR compat_sys_statfs
258 PTR compat_sys_fstatfs /* 6135 */ 258 PTR compat_sys_fstatfs /* 6135 */
259 PTR sys_sysfs 259 PTR sys_sysfs
@@ -265,14 +265,14 @@ EXPORT(sysn32_call_table)
265 PTR sys_sched_getscheduler 265 PTR sys_sched_getscheduler
266 PTR sys_sched_get_priority_max 266 PTR sys_sched_get_priority_max
267 PTR sys_sched_get_priority_min 267 PTR sys_sched_get_priority_min
268 PTR sys32_sched_rr_get_interval /* 6145 */ 268 PTR sys_32_sched_rr_get_interval /* 6145 */
269 PTR sys_mlock 269 PTR sys_mlock
270 PTR sys_munlock 270 PTR sys_munlock
271 PTR sys_mlockall 271 PTR sys_mlockall
272 PTR sys_munlockall 272 PTR sys_munlockall
273 PTR sys_vhangup /* 6150 */ 273 PTR sys_vhangup /* 6150 */
274 PTR sys_pivot_root 274 PTR sys_pivot_root
275 PTR sys32_sysctl 275 PTR sys_32_sysctl
276 PTR sys_prctl 276 PTR sys_prctl
277 PTR compat_sys_adjtimex 277 PTR compat_sys_adjtimex
278 PTR compat_sys_setrlimit /* 6155 */ 278 PTR compat_sys_setrlimit /* 6155 */
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index fefef4af8595..b0fef4ff9827 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -265,12 +265,12 @@ sys_call_table:
265 PTR sys_olduname 265 PTR sys_olduname
266 PTR sys_umask /* 4060 */ 266 PTR sys_umask /* 4060 */
267 PTR sys_chroot 267 PTR sys_chroot
268 PTR sys32_ustat 268 PTR sys_32_ustat
269 PTR sys_dup2 269 PTR sys_dup2
270 PTR sys_getppid 270 PTR sys_getppid
271 PTR sys_getpgrp /* 4065 */ 271 PTR sys_getpgrp /* 4065 */
272 PTR sys_setsid 272 PTR sys_setsid
273 PTR sys32_sigaction 273 PTR sys_32_sigaction
274 PTR sys_sgetmask 274 PTR sys_sgetmask
275 PTR sys_ssetmask 275 PTR sys_ssetmask
276 PTR sys_setreuid /* 4070 */ 276 PTR sys_setreuid /* 4070 */
@@ -293,7 +293,7 @@ sys_call_table:
293 PTR sys_swapon 293 PTR sys_swapon
294 PTR sys_reboot 294 PTR sys_reboot
295 PTR compat_sys_old_readdir 295 PTR compat_sys_old_readdir
296 PTR old_mmap /* 4090 */ 296 PTR sys_mips_mmap /* 4090 */
297 PTR sys_munmap 297 PTR sys_munmap
298 PTR sys_truncate 298 PTR sys_truncate
299 PTR sys_ftruncate 299 PTR sys_ftruncate
@@ -320,12 +320,12 @@ sys_call_table:
320 PTR compat_sys_wait4 320 PTR compat_sys_wait4
321 PTR sys_swapoff /* 4115 */ 321 PTR sys_swapoff /* 4115 */
322 PTR compat_sys_sysinfo 322 PTR compat_sys_sysinfo
323 PTR sys32_ipc 323 PTR sys_32_ipc
324 PTR sys_fsync 324 PTR sys_fsync
325 PTR sys32_sigreturn 325 PTR sys32_sigreturn
326 PTR sys32_clone /* 4120 */ 326 PTR sys32_clone /* 4120 */
327 PTR sys_setdomainname 327 PTR sys_setdomainname
328 PTR sys32_newuname 328 PTR sys_32_newuname
329 PTR sys_ni_syscall /* sys_modify_ldt */ 329 PTR sys_ni_syscall /* sys_modify_ldt */
330 PTR compat_sys_adjtimex 330 PTR compat_sys_adjtimex
331 PTR sys_mprotect /* 4125 */ 331 PTR sys_mprotect /* 4125 */
@@ -339,11 +339,11 @@ sys_call_table:
339 PTR sys_fchdir 339 PTR sys_fchdir
340 PTR sys_bdflush 340 PTR sys_bdflush
341 PTR sys_sysfs /* 4135 */ 341 PTR sys_sysfs /* 4135 */
342 PTR sys32_personality 342 PTR sys_32_personality
343 PTR sys_ni_syscall /* for afs_syscall */ 343 PTR sys_ni_syscall /* for afs_syscall */
344 PTR sys_setfsuid 344 PTR sys_setfsuid
345 PTR sys_setfsgid 345 PTR sys_setfsgid
346 PTR sys32_llseek /* 4140 */ 346 PTR sys_32_llseek /* 4140 */
347 PTR compat_sys_getdents 347 PTR compat_sys_getdents
348 PTR compat_sys_select 348 PTR compat_sys_select
349 PTR sys_flock 349 PTR sys_flock
@@ -356,7 +356,7 @@ sys_call_table:
356 PTR sys_ni_syscall /* 4150 */ 356 PTR sys_ni_syscall /* 4150 */
357 PTR sys_getsid 357 PTR sys_getsid
358 PTR sys_fdatasync 358 PTR sys_fdatasync
359 PTR sys32_sysctl 359 PTR sys_32_sysctl
360 PTR sys_mlock 360 PTR sys_mlock
361 PTR sys_munlock /* 4155 */ 361 PTR sys_munlock /* 4155 */
362 PTR sys_mlockall 362 PTR sys_mlockall
@@ -368,7 +368,7 @@ sys_call_table:
368 PTR sys_sched_yield 368 PTR sys_sched_yield
369 PTR sys_sched_get_priority_max 369 PTR sys_sched_get_priority_max
370 PTR sys_sched_get_priority_min 370 PTR sys_sched_get_priority_min
371 PTR sys32_sched_rr_get_interval /* 4165 */ 371 PTR sys_32_sched_rr_get_interval /* 4165 */
372 PTR compat_sys_nanosleep 372 PTR compat_sys_nanosleep
373 PTR sys_mremap 373 PTR sys_mremap
374 PTR sys_accept 374 PTR sys_accept
@@ -397,25 +397,25 @@ sys_call_table:
397 PTR sys_getresgid 397 PTR sys_getresgid
398 PTR sys_prctl 398 PTR sys_prctl
399 PTR sys32_rt_sigreturn 399 PTR sys32_rt_sigreturn
400 PTR sys32_rt_sigaction 400 PTR sys_32_rt_sigaction
401 PTR sys32_rt_sigprocmask /* 4195 */ 401 PTR sys_32_rt_sigprocmask /* 4195 */
402 PTR sys32_rt_sigpending 402 PTR sys_32_rt_sigpending
403 PTR compat_sys_rt_sigtimedwait 403 PTR compat_sys_rt_sigtimedwait
404 PTR sys32_rt_sigqueueinfo 404 PTR sys_32_rt_sigqueueinfo
405 PTR sys32_rt_sigsuspend 405 PTR sys32_rt_sigsuspend
406 PTR sys32_pread /* 4200 */ 406 PTR sys_32_pread /* 4200 */
407 PTR sys32_pwrite 407 PTR sys_32_pwrite
408 PTR sys_chown 408 PTR sys_chown
409 PTR sys_getcwd 409 PTR sys_getcwd
410 PTR sys_capget 410 PTR sys_capget
411 PTR sys_capset /* 4205 */ 411 PTR sys_capset /* 4205 */
412 PTR sys32_sigaltstack 412 PTR sys32_sigaltstack
413 PTR sys32_sendfile 413 PTR sys_32_sendfile
414 PTR sys_ni_syscall 414 PTR sys_ni_syscall
415 PTR sys_ni_syscall 415 PTR sys_ni_syscall
416 PTR sys32_mmap2 /* 4210 */ 416 PTR sys_mips_mmap2 /* 4210 */
417 PTR sys32_truncate64 417 PTR sys_32_truncate64
418 PTR sys32_ftruncate64 418 PTR sys_32_ftruncate64
419 PTR sys_newstat 419 PTR sys_newstat
420 PTR sys_newlstat 420 PTR sys_newlstat
421 PTR sys_newfstat /* 4215 */ 421 PTR sys_newfstat /* 4215 */
@@ -481,7 +481,7 @@ sys_call_table:
481 PTR compat_sys_mq_notify /* 4275 */ 481 PTR compat_sys_mq_notify /* 4275 */
482 PTR compat_sys_mq_getsetattr 482 PTR compat_sys_mq_getsetattr
483 PTR sys_ni_syscall /* sys_vserver */ 483 PTR sys_ni_syscall /* sys_vserver */
484 PTR sys32_waitid 484 PTR sys_32_waitid
485 PTR sys_ni_syscall /* available, was setaltroot */ 485 PTR sys_ni_syscall /* available, was setaltroot */
486 PTR sys_add_key /* 4280 */ 486 PTR sys_add_key /* 4280 */
487 PTR sys_request_key 487 PTR sys_request_key
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index a4e106c56ab5..830c5ef9932b 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -19,6 +19,7 @@
19#include <linux/ptrace.h> 19#include <linux/ptrace.h>
20#include <linux/unistd.h> 20#include <linux/unistd.h>
21#include <linux/compiler.h> 21#include <linux/compiler.h>
22#include <linux/syscalls.h>
22#include <linux/uaccess.h> 23#include <linux/uaccess.h>
23 24
24#include <asm/abi.h> 25#include <asm/abi.h>
@@ -338,8 +339,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
338} 339}
339 340
340#ifdef CONFIG_TRAD_SIGNALS 341#ifdef CONFIG_TRAD_SIGNALS
341asmlinkage int sys_sigaction(int sig, const struct sigaction __user *act, 342SYSCALL_DEFINE3(sigaction, int, sig, const struct sigaction __user *, act,
342 struct sigaction __user *oact) 343 struct sigaction __user *, oact)
343{ 344{
344 struct k_sigaction new_ka, old_ka; 345 struct k_sigaction new_ka, old_ka;
345 int ret; 346 int ret;
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 652709b353ad..2e74075ac0ca 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -349,8 +349,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
349 return -ERESTARTNOHAND; 349 return -ERESTARTNOHAND;
350} 350}
351 351
352asmlinkage int sys32_sigaction(int sig, const struct sigaction32 __user *act, 352SYSCALL_DEFINE3(32_sigaction, long, sig, const struct sigaction32 __user *, act,
353 struct sigaction32 __user *oact) 353 struct sigaction32 __user *, oact)
354{ 354{
355 struct k_sigaction new_ka, old_ka; 355 struct k_sigaction new_ka, old_ka;
356 int ret; 356 int ret;
@@ -704,9 +704,9 @@ struct mips_abi mips_abi_32 = {
704 .restart = __NR_O32_restart_syscall 704 .restart = __NR_O32_restart_syscall
705}; 705};
706 706
707asmlinkage int sys32_rt_sigaction(int sig, const struct sigaction32 __user *act, 707SYSCALL_DEFINE4(32_rt_sigaction, int, sig,
708 struct sigaction32 __user *oact, 708 const struct sigaction32 __user *, act,
709 unsigned int sigsetsize) 709 struct sigaction32 __user *, oact, unsigned int, sigsetsize)
710{ 710{
711 struct k_sigaction new_sa, old_sa; 711 struct k_sigaction new_sa, old_sa;
712 int ret = -EINVAL; 712 int ret = -EINVAL;
@@ -748,8 +748,8 @@ out:
748 return ret; 748 return ret;
749} 749}
750 750
751asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set, 751SYSCALL_DEFINE4(32_rt_sigprocmask, int, how, compat_sigset_t __user *, set,
752 compat_sigset_t __user *oset, unsigned int sigsetsize) 752 compat_sigset_t __user *, oset, unsigned int, sigsetsize)
753{ 753{
754 sigset_t old_set, new_set; 754 sigset_t old_set, new_set;
755 int ret; 755 int ret;
@@ -770,8 +770,8 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set,
770 return ret; 770 return ret;
771} 771}
772 772
773asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset, 773SYSCALL_DEFINE2(32_rt_sigpending, compat_sigset_t __user *, uset,
774 unsigned int sigsetsize) 774 unsigned int, sigsetsize)
775{ 775{
776 int ret; 776 int ret;
777 sigset_t set; 777 sigset_t set;
@@ -787,7 +787,8 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset,
787 return ret; 787 return ret;
788} 788}
789 789
790asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *uinfo) 790SYSCALL_DEFINE3(32_rt_sigqueueinfo, int, pid, int, sig,
791 compat_siginfo_t __user *, uinfo)
791{ 792{
792 siginfo_t info; 793 siginfo_t info;
793 int ret; 794 int ret;
@@ -802,10 +803,9 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *
802 return ret; 803 return ret;
803} 804}
804 805
805asmlinkage long 806SYSCALL_DEFINE5(32_waitid, int, which, compat_pid_t, pid,
806sys32_waitid(int which, compat_pid_t pid, 807 compat_siginfo_t __user *, uinfo, int, options,
807 compat_siginfo_t __user *uinfo, int options, 808 struct compat_rusage __user *, uru)
808 struct compat_rusage __user *uru)
809{ 809{
810 siginfo_t info; 810 siginfo_t info;
811 struct rusage ru; 811 struct rusage ru;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 37970d9b2186..8cf384644040 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -152,9 +152,9 @@ out:
152 return error; 152 return error;
153} 153}
154 154
155asmlinkage unsigned long 155SYSCALL_DEFINE6(mips_mmap, unsigned long, addr, unsigned long, len,
156old_mmap(unsigned long addr, unsigned long len, int prot, 156 unsigned long, prot, unsigned long, flags, unsigned long,
157 int flags, int fd, off_t offset) 157 fd, off_t, offset)
158{ 158{
159 unsigned long result; 159 unsigned long result;
160 160
@@ -168,9 +168,9 @@ out:
168 return result; 168 return result;
169} 169}
170 170
171asmlinkage unsigned long 171SYSCALL_DEFINE6(mips_mmap2, unsigned long, addr, unsigned long, len,
172sys_mmap2(unsigned long addr, unsigned long len, unsigned long prot, 172 unsigned long, prot, unsigned long, flags, unsigned long, fd,
173 unsigned long flags, unsigned long fd, unsigned long pgoff) 173 unsigned long, pgoff)
174{ 174{
175 if (pgoff & (~PAGE_MASK >> 12)) 175 if (pgoff & (~PAGE_MASK >> 12))
176 return -EINVAL; 176 return -EINVAL;
@@ -240,7 +240,7 @@ out:
240/* 240/*
241 * Compacrapability ... 241 * Compacrapability ...
242 */ 242 */
243asmlinkage int sys_uname(struct old_utsname __user * name) 243SYSCALL_DEFINE1(uname, struct old_utsname __user *, name)
244{ 244{
245 if (name && !copy_to_user(name, utsname(), sizeof (*name))) 245 if (name && !copy_to_user(name, utsname(), sizeof (*name)))
246 return 0; 246 return 0;
@@ -250,7 +250,7 @@ asmlinkage int sys_uname(struct old_utsname __user * name)
250/* 250/*
251 * Compacrapability ... 251 * Compacrapability ...
252 */ 252 */
253asmlinkage int sys_olduname(struct oldold_utsname __user * name) 253SYSCALL_DEFINE1(olduname, struct oldold_utsname __user *, name)
254{ 254{
255 int error; 255 int error;
256 256
@@ -279,7 +279,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
279 return error; 279 return error;
280} 280}
281 281
282asmlinkage int sys_set_thread_area(unsigned long addr) 282SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
283{ 283{
284 struct thread_info *ti = task_thread_info(current); 284 struct thread_info *ti = task_thread_info(current);
285 285
@@ -290,7 +290,7 @@ asmlinkage int sys_set_thread_area(unsigned long addr)
290 return 0; 290 return 0;
291} 291}
292 292
293asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3) 293asmlinkage int _sys_sysmips(long cmd, long arg1, long arg2, long arg3)
294{ 294{
295 switch (cmd) { 295 switch (cmd) {
296 case MIPS_ATOMIC_SET: 296 case MIPS_ATOMIC_SET:
@@ -325,8 +325,8 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
325 * 325 *
326 * This is really horribly ugly. 326 * This is really horribly ugly.
327 */ 327 */
328asmlinkage int sys_ipc(unsigned int call, int first, int second, 328SYSCALL_DEFINE6(ipc, unsigned int, call, int, first, int, second,
329 unsigned long third, void __user *ptr, long fifth) 329 unsigned long, third, void __user *, ptr, long, fifth)
330{ 330{
331 int version, ret; 331 int version, ret;
332 332
@@ -411,7 +411,7 @@ asmlinkage int sys_ipc(unsigned int call, int first, int second,
411/* 411/*
412 * No implemented yet ... 412 * No implemented yet ...
413 */ 413 */
414asmlinkage int sys_cachectl(char *addr, int nbytes, int op) 414SYSCALL_DEFINE3(cachectl, char *, addr, int, nbytes, int, op)
415{ 415{
416 return -ENOSYS; 416 return -ENOSYS;
417} 417}
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 98ad0a82c29e..694d51f523d1 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -13,6 +13,7 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/sched.h> 15#include <linux/sched.h>
16#include <linux/syscalls.h>
16#include <linux/mm.h> 17#include <linux/mm.h>
17 18
18#include <asm/cacheflush.h> 19#include <asm/cacheflush.h>
@@ -58,8 +59,8 @@ EXPORT_SYMBOL(_dma_cache_wback_inv);
58 * We could optimize the case where the cache argument is not BCACHE but 59 * We could optimize the case where the cache argument is not BCACHE but
59 * that seems very atypical use ... 60 * that seems very atypical use ...
60 */ 61 */
61asmlinkage int sys_cacheflush(unsigned long addr, 62SYSCALL_DEFINE3(cacheflush, unsigned long, addr, unsigned long, bytes,
62 unsigned long bytes, unsigned int cache) 63 unsigned int, cache)
63{ 64{
64 if (bytes == 0) 65 if (bytes == 0)
65 return 0; 66 return 0;
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index 9a9f43358879..41d16822e616 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -7,6 +7,7 @@ mainmenu "Linux Kernel Configuration"
7 7
8config MN10300 8config MN10300
9 def_bool y 9 def_bool y
10 select HAVE_OPROFILE
10 11
11config AM33 12config AM33
12 def_bool y 13 def_bool y
diff --git a/arch/mn10300/unit-asb2305/pci.c b/arch/mn10300/unit-asb2305/pci.c
index 1a86425fec42..07dbbcda3b2e 100644
--- a/arch/mn10300/unit-asb2305/pci.c
+++ b/arch/mn10300/unit-asb2305/pci.c
@@ -173,7 +173,7 @@ static int pci_ampci_write_config_byte(struct pci_bus *bus, unsigned int devfn,
173 BRIDGEREGB(where) = value; 173 BRIDGEREGB(where) = value;
174 } else { 174 } else {
175 if (bus->number == 0 && 175 if (bus->number == 0 &&
176 (devfn == PCI_DEVFN(2, 0) && devfn == PCI_DEVFN(3, 0)) 176 (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(3, 0))
177 ) 177 )
178 __pcidebug("<= %02x", bus, devfn, where, value); 178 __pcidebug("<= %02x", bus, devfn, where, value);
179 CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where); 179 CONFIG_ADDRESS = CONFIG_CMD(bus, devfn, where);
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 909a89cab9ac..3ebf7ec0484c 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -191,7 +191,8 @@
191 interrupts = <37 0x8 36 0x8 35 0x8>; 191 interrupts = <37 0x8 36 0x8 35 0x8>;
192 interrupt-parent = <&ipic>; 192 interrupt-parent = <&ipic>;
193 tbi-handle = < &tbi0 >; 193 tbi-handle = < &tbi0 >;
194 phy-handle = < &phy1 >; 194 /* Vitesse 7385 isn't on the MDIO bus */
195 fixed-link = <1 1 1000 0 0>;
195 fsl,magic-packet; 196 fsl,magic-packet;
196 197
197 mdio@24520 { 198 mdio@24520 {
@@ -199,12 +200,6 @@
199 #size-cells = <0>; 200 #size-cells = <0>;
200 compatible = "fsl,gianfar-mdio"; 201 compatible = "fsl,gianfar-mdio";
201 reg = <0x24520 0x20>; 202 reg = <0x24520 0x20>;
202 phy1: ethernet-phy@1 {
203 interrupt-parent = <&ipic>;
204 interrupts = <19 0x8>;
205 reg = <0x1>;
206 device_type = "ethernet-phy";
207 };
208 phy4: ethernet-phy@4 { 203 phy4: ethernet-phy@4 {
209 interrupt-parent = <&ipic>; 204 interrupt-parent = <&ipic>;
210 interrupts = <20 0x8>; 205 interrupts = <20 0x8>;
@@ -219,6 +214,8 @@
219 }; 214 };
220 215
221 enet1: ethernet@25000 { 216 enet1: ethernet@25000 {
217 #address-cells = <1>;
218 #size-cells = <1>;
222 cell-index = <1>; 219 cell-index = <1>;
223 device_type = "network"; 220 device_type = "network";
224 model = "eTSEC"; 221 model = "eTSEC";
diff --git a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
index 9e47ae957e2e..409d017621a8 100644
--- a/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
+++ b/arch/powerpc/configs/83xx/mpc8313_rdb_defconfig
@@ -651,7 +651,7 @@ CONFIG_CICADA_PHY=y
651# CONFIG_NATIONAL_PHY is not set 651# CONFIG_NATIONAL_PHY is not set
652# CONFIG_STE10XP is not set 652# CONFIG_STE10XP is not set
653# CONFIG_LSI_ET1011C_PHY is not set 653# CONFIG_LSI_ET1011C_PHY is not set
654# CONFIG_FIXED_PHY is not set 654CONFIG_FIXED_PHY=y
655# CONFIG_MDIO_BITBANG is not set 655# CONFIG_MDIO_BITBANG is not set
656CONFIG_NET_ETHERNET=y 656CONFIG_NET_ETHERNET=y
657CONFIG_MII=y 657CONFIG_MII=y
diff --git a/arch/powerpc/include/asm/compat.h b/arch/powerpc/include/asm/compat.h
index d811a8cd7b58..4774c2f92232 100644
--- a/arch/powerpc/include/asm/compat.h
+++ b/arch/powerpc/include/asm/compat.h
@@ -210,5 +210,10 @@ struct compat_shmid64_ds {
210 compat_ulong_t __unused6; 210 compat_ulong_t __unused6;
211}; 211};
212 212
213static inline int is_compat_task(void)
214{
215 return test_thread_flag(TIF_32BIT);
216}
217
213#endif /* __KERNEL__ */ 218#endif /* __KERNEL__ */
214#endif /* _ASM_POWERPC_COMPAT_H */ 219#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/arch/powerpc/include/asm/pgtable-4k.h b/arch/powerpc/include/asm/pgtable-4k.h
index 6b18ba9d2d85..1dbca4e7de67 100644
--- a/arch/powerpc/include/asm/pgtable-4k.h
+++ b/arch/powerpc/include/asm/pgtable-4k.h
@@ -60,7 +60,7 @@
60/* It should be preserving the high 48 bits and then specifically */ 60/* It should be preserving the high 48 bits and then specifically */
61/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */ 61/* preserving _PAGE_SECONDARY | _PAGE_GROUP_IX */
62#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \ 62#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
63 _PAGE_HPTEFLAGS) 63 _PAGE_HPTEFLAGS | _PAGE_SPECIAL)
64 64
65/* Bits to mask out from a PMD to get to the PTE page */ 65/* Bits to mask out from a PMD to get to the PTE page */
66#define PMD_MASKED_BITS 0 66#define PMD_MASKED_BITS 0
diff --git a/arch/powerpc/include/asm/pgtable-64k.h b/arch/powerpc/include/asm/pgtable-64k.h
index 07b0d8f09cb6..7389003349a6 100644
--- a/arch/powerpc/include/asm/pgtable-64k.h
+++ b/arch/powerpc/include/asm/pgtable-64k.h
@@ -114,7 +114,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
114 * pgprot changes 114 * pgprot changes
115 */ 115 */
116#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \ 116#define _PAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | _PAGE_DIRTY | \
117 _PAGE_ACCESSED) 117 _PAGE_ACCESSED | _PAGE_SPECIAL)
118 118
119/* Bits to mask out from a PMD to get to the PTE page */ 119/* Bits to mask out from a PMD to get to the PTE page */
120#define PMD_MASKED_BITS 0x1ff 120#define PMD_MASKED_BITS 0x1ff
diff --git a/arch/powerpc/include/asm/pgtable-ppc32.h b/arch/powerpc/include/asm/pgtable-ppc32.h
index f69a4d977729..820b5f0a35ce 100644
--- a/arch/powerpc/include/asm/pgtable-ppc32.h
+++ b/arch/powerpc/include/asm/pgtable-ppc32.h
@@ -429,7 +429,8 @@ extern int icache_44x_need_flush;
429#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE() 429#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
430#endif 430#endif
431 431
432#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 432#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY | \
433 _PAGE_SPECIAL)
433 434
434 435
435#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \ 436#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
diff --git a/arch/powerpc/include/asm/seccomp.h b/arch/powerpc/include/asm/seccomp.h
index 853765eb1f65..00c1d9133cfe 100644
--- a/arch/powerpc/include/asm/seccomp.h
+++ b/arch/powerpc/include/asm/seccomp.h
@@ -1,10 +1,6 @@
1#ifndef _ASM_POWERPC_SECCOMP_H 1#ifndef _ASM_POWERPC_SECCOMP_H
2#define _ASM_POWERPC_SECCOMP_H 2#define _ASM_POWERPC_SECCOMP_H
3 3
4#ifdef __KERNEL__
5#include <linux/thread_info.h>
6#endif
7
8#include <linux/unistd.h> 4#include <linux/unistd.h>
9 5
10#define __NR_seccomp_read __NR_read 6#define __NR_seccomp_read __NR_read
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 5af4e9b2dbe2..73cb6a3229ae 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -367,27 +367,24 @@ static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
367static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg, 367static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
368 unsigned int flags) 368 unsigned int flags)
369{ 369{
370 char *ptr = (char *) &current->thread.TS_FPR(reg); 370 char *ptr0 = (char *) &current->thread.TS_FPR(reg);
371 int i, ret; 371 char *ptr1 = (char *) &current->thread.TS_FPR(reg+1);
372 int i, ret, sw = 0;
372 373
373 if (!(flags & F)) 374 if (!(flags & F))
374 return 0; 375 return 0;
375 if (reg & 1) 376 if (reg & 1)
376 return 0; /* invalid form: FRS/FRT must be even */ 377 return 0; /* invalid form: FRS/FRT must be even */
377 if (!(flags & SW)) { 378 if (flags & SW)
378 /* not byte-swapped - easy */ 379 sw = 7;
379 if (!(flags & ST)) 380 ret = 0;
380 ret = __copy_from_user(ptr, addr, 16); 381 for (i = 0; i < 8; ++i) {
381 else 382 if (!(flags & ST)) {
382 ret = __copy_to_user(addr, ptr, 16); 383 ret |= __get_user(ptr0[i^sw], addr + i);
383 } else { 384 ret |= __get_user(ptr1[i^sw], addr + i + 8);
384 /* each FPR value is byte-swapped separately */ 385 } else {
385 ret = 0; 386 ret |= __put_user(ptr0[i^sw], addr + i);
386 for (i = 0; i < 16; ++i) { 387 ret |= __put_user(ptr1[i^sw], addr + i + 8);
387 if (!(flags & ST))
388 ret |= __get_user(ptr[i^7], addr + i);
389 else
390 ret |= __put_user(ptr[i^7], addr + i);
391 } 388 }
392 } 389 }
393 if (ret) 390 if (ret)
@@ -646,11 +643,16 @@ static int emulate_vsx(unsigned char __user *addr, unsigned int reg,
646 unsigned int areg, struct pt_regs *regs, 643 unsigned int areg, struct pt_regs *regs,
647 unsigned int flags, unsigned int length) 644 unsigned int flags, unsigned int length)
648{ 645{
649 char *ptr = (char *) &current->thread.TS_FPR(reg); 646 char *ptr;
650 int ret = 0; 647 int ret = 0;
651 648
652 flush_vsx_to_thread(current); 649 flush_vsx_to_thread(current);
653 650
651 if (reg < 32)
652 ptr = (char *) &current->thread.TS_FPR(reg);
653 else
654 ptr = (char *) &current->thread.vr[reg - 32];
655
654 if (flags & ST) 656 if (flags & ST)
655 ret = __copy_to_user(addr, ptr, length); 657 ret = __copy_to_user(addr, ptr, length);
656 else { 658 else {
diff --git a/arch/powerpc/kernel/ftrace.c b/arch/powerpc/kernel/ftrace.c
index 5355244c99ff..60c60ccf5e3c 100644
--- a/arch/powerpc/kernel/ftrace.c
+++ b/arch/powerpc/kernel/ftrace.c
@@ -195,8 +195,9 @@ __ftrace_make_nop(struct module *mod,
195 return -EINVAL; 195 return -EINVAL;
196 } 196 }
197 197
198 offset = (unsigned)((unsigned short)jmp[0]) << 16 | 198 /* The bottom half is signed extended */
199 (unsigned)((unsigned short)jmp[1]); 199 offset = ((unsigned)((unsigned short)jmp[0]) << 16) +
200 (int)((short)jmp[1]);
200 201
201 DEBUGP(" %x ", offset); 202 DEBUGP(" %x ", offset);
202 203
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 19b12d2cbb4b..0f4181272311 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -561,8 +561,21 @@ int pci_mmap_legacy_page_range(struct pci_bus *bus,
561 (unsigned long long)(offset + size - 1)); 561 (unsigned long long)(offset + size - 1));
562 562
563 if (mmap_state == pci_mmap_mem) { 563 if (mmap_state == pci_mmap_mem) {
564 if ((offset + size) > hose->isa_mem_size) 564 /* Hack alert !
565 return -ENXIO; 565 *
566 * Because X is lame and can fail starting if it gets an error trying
567 * to mmap legacy_mem (instead of just moving on without legacy memory
568 * access) we fake it here by giving it anonymous memory, effectively
569 * behaving just like /dev/zero
570 */
571 if ((offset + size) > hose->isa_mem_size) {
572 printk(KERN_DEBUG
573 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
574 current->comm, current->pid, pci_domain_nr(bus), bus->number);
575 if (vma->vm_flags & VM_SHARED)
576 return shmem_zero_setup(vma);
577 return 0;
578 }
566 offset += hose->isa_mem_phys; 579 offset += hose->isa_mem_phys;
567 } else { 580 } else {
568 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE; 581 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2822c8ccfaaf..5f81256287f5 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -125,6 +125,10 @@ static void kvmppc_free_vcpus(struct kvm *kvm)
125 } 125 }
126} 126}
127 127
128void kvm_arch_sync_events(struct kvm *kvm)
129{
130}
131
128void kvm_arch_destroy_vm(struct kvm *kvm) 132void kvm_arch_destroy_vm(struct kvm *kvm)
129{ 133{
130 kvmppc_free_vcpus(kvm); 134 kvmppc_free_vcpus(kvm);
diff --git a/arch/powerpc/lib/copyuser_64.S b/arch/powerpc/lib/copyuser_64.S
index 70693a5c12a1..693b14a778fa 100644
--- a/arch/powerpc/lib/copyuser_64.S
+++ b/arch/powerpc/lib/copyuser_64.S
@@ -62,18 +62,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
6272: std r8,8(r3) 6272: std r8,8(r3)
63 beq+ 3f 63 beq+ 3f
64 addi r3,r3,16 64 addi r3,r3,16
6523: ld r9,8(r4)
66.Ldo_tail: 65.Ldo_tail:
67 bf cr7*4+1,1f 66 bf cr7*4+1,1f
68 rotldi r9,r9,32 6723: lwz r9,8(r4)
68 addi r4,r4,4
6973: stw r9,0(r3) 6973: stw r9,0(r3)
70 addi r3,r3,4 70 addi r3,r3,4
711: bf cr7*4+2,2f 711: bf cr7*4+2,2f
72 rotldi r9,r9,16 7244: lhz r9,8(r4)
73 addi r4,r4,2
7374: sth r9,0(r3) 7474: sth r9,0(r3)
74 addi r3,r3,2 75 addi r3,r3,2
752: bf cr7*4+3,3f 762: bf cr7*4+3,3f
76 rotldi r9,r9,8 7745: lbz r9,8(r4)
7775: stb r9,0(r3) 7875: stb r9,0(r3)
783: li r3,0 793: li r3,0
79 blr 80 blr
@@ -141,11 +142,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
1416: cmpwi cr1,r5,8 1426: cmpwi cr1,r5,8
142 addi r3,r3,32 143 addi r3,r3,32
143 sld r9,r9,r10 144 sld r9,r9,r10
144 ble cr1,.Ldo_tail 145 ble cr1,7f
14534: ld r0,8(r4) 14634: ld r0,8(r4)
146 srd r7,r0,r11 147 srd r7,r0,r11
147 or r9,r7,r9 148 or r9,r7,r9
148 b .Ldo_tail 1497:
150 bf cr7*4+1,1f
151 rotldi r9,r9,32
15294: stw r9,0(r3)
153 addi r3,r3,4
1541: bf cr7*4+2,2f
155 rotldi r9,r9,16
15695: sth r9,0(r3)
157 addi r3,r3,2
1582: bf cr7*4+3,3f
159 rotldi r9,r9,8
16096: stb r9,0(r3)
1613: li r3,0
162 blr
149 163
150.Ldst_unaligned: 164.Ldst_unaligned:
151 PPC_MTOCRF 0x01,r6 /* put #bytes to 8B bdry into cr7 */ 165 PPC_MTOCRF 0x01,r6 /* put #bytes to 8B bdry into cr7 */
@@ -218,7 +232,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
218121: 232121:
219132: 233132:
220 addi r3,r3,8 234 addi r3,r3,8
221123:
222134: 235134:
223135: 236135:
224138: 237138:
@@ -226,6 +239,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
226140: 239140:
227141: 240141:
228142: 241142:
242123:
243144:
244145:
229 245
230/* 246/*
231 * here we have had a fault on a load and r3 points to the first 247 * here we have had a fault on a load and r3 points to the first
@@ -309,6 +325,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
309187: 325187:
310188: 326188:
311189: 327189:
328194:
329195:
330196:
3121: 3311:
313 ld r6,-24(r1) 332 ld r6,-24(r1)
314 ld r5,-8(r1) 333 ld r5,-8(r1)
@@ -329,7 +348,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
329 .llong 72b,172b 348 .llong 72b,172b
330 .llong 23b,123b 349 .llong 23b,123b
331 .llong 73b,173b 350 .llong 73b,173b
351 .llong 44b,144b
332 .llong 74b,174b 352 .llong 74b,174b
353 .llong 45b,145b
333 .llong 75b,175b 354 .llong 75b,175b
334 .llong 24b,124b 355 .llong 24b,124b
335 .llong 25b,125b 356 .llong 25b,125b
@@ -347,6 +368,9 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
347 .llong 79b,179b 368 .llong 79b,179b
348 .llong 80b,180b 369 .llong 80b,180b
349 .llong 34b,134b 370 .llong 34b,134b
371 .llong 94b,194b
372 .llong 95b,195b
373 .llong 96b,196b
350 .llong 35b,135b 374 .llong 35b,135b
351 .llong 81b,181b 375 .llong 81b,181b
352 .llong 36b,136b 376 .llong 36b,136b
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index fe2d34e5332d..e178922b2c21 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -53,18 +53,19 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
533: std r8,8(r3) 533: std r8,8(r3)
54 beq 3f 54 beq 3f
55 addi r3,r3,16 55 addi r3,r3,16
56 ld r9,8(r4)
57.Ldo_tail: 56.Ldo_tail:
58 bf cr7*4+1,1f 57 bf cr7*4+1,1f
59 rotldi r9,r9,32 58 lwz r9,8(r4)
59 addi r4,r4,4
60 stw r9,0(r3) 60 stw r9,0(r3)
61 addi r3,r3,4 61 addi r3,r3,4
621: bf cr7*4+2,2f 621: bf cr7*4+2,2f
63 rotldi r9,r9,16 63 lhz r9,8(r4)
64 addi r4,r4,2
64 sth r9,0(r3) 65 sth r9,0(r3)
65 addi r3,r3,2 66 addi r3,r3,2
662: bf cr7*4+3,3f 672: bf cr7*4+3,3f
67 rotldi r9,r9,8 68 lbz r9,8(r4)
68 stb r9,0(r3) 69 stb r9,0(r3)
693: ld r3,48(r1) /* return dest pointer */ 703: ld r3,48(r1) /* return dest pointer */
70 blr 71 blr
@@ -133,11 +134,24 @@ END_FTR_SECTION_IFCLR(CPU_FTR_UNALIGNED_LD_STD)
133 cmpwi cr1,r5,8 134 cmpwi cr1,r5,8
134 addi r3,r3,32 135 addi r3,r3,32
135 sld r9,r9,r10 136 sld r9,r9,r10
136 ble cr1,.Ldo_tail 137 ble cr1,6f
137 ld r0,8(r4) 138 ld r0,8(r4)
138 srd r7,r0,r11 139 srd r7,r0,r11
139 or r9,r7,r9 140 or r9,r7,r9
140 b .Ldo_tail 1416:
142 bf cr7*4+1,1f
143 rotldi r9,r9,32
144 stw r9,0(r3)
145 addi r3,r3,4
1461: bf cr7*4+2,2f
147 rotldi r9,r9,16
148 sth r9,0(r3)
149 addi r3,r3,2
1502: bf cr7*4+3,3f
151 rotldi r9,r9,8
152 stb r9,0(r3)
1533: ld r3,48(r1) /* return dest pointer */
154 blr
141 155
142.Ldst_unaligned: 156.Ldst_unaligned:
143 PPC_MTOCRF 0x01,r6 # put #bytes to 8B bdry into cr7 157 PPC_MTOCRF 0x01,r6 # put #bytes to 8B bdry into cr7
diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 4aae0c387645..13b7d54f185b 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c
@@ -172,6 +172,8 @@ int __kprobes emulate_step(struct pt_regs *regs, unsigned int instr)
172 } 172 }
173 break; 173 break;
174 case 0x378: /* orx */ 174 case 0x378: /* orx */
175 if (instr & 1)
176 break;
175 rs = (instr >> 21) & 0x1f; 177 rs = (instr >> 21) & 0x1f;
176 rb = (instr >> 11) & 0x1f; 178 rb = (instr >> 11) & 0x1f;
177 if (rs == rb) { /* mr */ 179 if (rs == rb) { /* mr */
diff --git a/arch/powerpc/mm/fsl_booke_mmu.c b/arch/powerpc/mm/fsl_booke_mmu.c
index 1971e4ee3d6e..ea6e41e39d9f 100644
--- a/arch/powerpc/mm/fsl_booke_mmu.c
+++ b/arch/powerpc/mm/fsl_booke_mmu.c
@@ -73,7 +73,7 @@ extern unsigned int tlbcam_index;
73/* 73/*
74 * Return PA for this VA if it is mapped by a CAM, or 0 74 * Return PA for this VA if it is mapped by a CAM, or 0
75 */ 75 */
76unsigned long v_mapped_by_tlbcam(unsigned long va) 76phys_addr_t v_mapped_by_tlbcam(unsigned long va)
77{ 77{
78 int b; 78 int b;
79 for (b = 0; b < tlbcam_index; ++b) 79 for (b = 0; b < tlbcam_index; ++b)
@@ -85,7 +85,7 @@ unsigned long v_mapped_by_tlbcam(unsigned long va)
85/* 85/*
86 * Return VA for a given PA or 0 if not mapped 86 * Return VA for a given PA or 0 if not mapped
87 */ 87 */
88unsigned long p_mapped_by_tlbcam(unsigned long pa) 88unsigned long p_mapped_by_tlbcam(phys_addr_t pa)
89{ 89{
90 int b; 90 int b;
91 for (b = 0; b < tlbcam_index; ++b) 91 for (b = 0; b < tlbcam_index; ++b)
diff --git a/arch/powerpc/mm/hash_low_32.S b/arch/powerpc/mm/hash_low_32.S
index 67850ec9feb3..14af8cedab70 100644
--- a/arch/powerpc/mm/hash_low_32.S
+++ b/arch/powerpc/mm/hash_low_32.S
@@ -320,7 +320,7 @@ _GLOBAL(create_hpte)
320 and r8,r8,r0 /* writable if _RW & _DIRTY */ 320 and r8,r8,r0 /* writable if _RW & _DIRTY */
321 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */ 321 rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
322 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */ 322 rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
323 ori r8,r8,0xe14 /* clear out reserved bits and M */ 323 ori r8,r8,0xe04 /* clear out reserved bits */
324 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */ 324 andc r8,r5,r8 /* PP = user? (rw&dirty? 2: 3): 0 */
325BEGIN_FTR_SECTION 325BEGIN_FTR_SECTION
326 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */ 326 rlwinm r8,r8,0,~_PAGE_COHERENT /* clear M (coherence not required) */
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 7393bd76d698..5ac08b8ab654 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -19,6 +19,7 @@
19#include <linux/notifier.h> 19#include <linux/notifier.h>
20#include <linux/lmb.h> 20#include <linux/lmb.h>
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/pfn.h>
22#include <asm/sparsemem.h> 23#include <asm/sparsemem.h>
23#include <asm/prom.h> 24#include <asm/prom.h>
24#include <asm/system.h> 25#include <asm/system.h>
@@ -882,7 +883,7 @@ static void mark_reserved_regions_for_nid(int nid)
882 unsigned long physbase = lmb.reserved.region[i].base; 883 unsigned long physbase = lmb.reserved.region[i].base;
883 unsigned long size = lmb.reserved.region[i].size; 884 unsigned long size = lmb.reserved.region[i].size;
884 unsigned long start_pfn = physbase >> PAGE_SHIFT; 885 unsigned long start_pfn = physbase >> PAGE_SHIFT;
885 unsigned long end_pfn = ((physbase + size) >> PAGE_SHIFT); 886 unsigned long end_pfn = PFN_UP(physbase + size);
886 struct node_active_region node_ar; 887 struct node_active_region node_ar;
887 unsigned long node_end_pfn = node->node_start_pfn + 888 unsigned long node_end_pfn = node->node_start_pfn +
888 node->node_spanned_pages; 889 node->node_spanned_pages;
@@ -908,7 +909,7 @@ static void mark_reserved_regions_for_nid(int nid)
908 */ 909 */
909 if (end_pfn > node_ar.end_pfn) 910 if (end_pfn > node_ar.end_pfn)
910 reserve_size = (node_ar.end_pfn << PAGE_SHIFT) 911 reserve_size = (node_ar.end_pfn << PAGE_SHIFT)
911 - (start_pfn << PAGE_SHIFT); 912 - physbase;
912 /* 913 /*
913 * Only worry about *this* node, others may not 914 * Only worry about *this* node, others may not
914 * yet have valid NODE_DATA(). 915 * yet have valid NODE_DATA().
diff --git a/arch/powerpc/mm/pgtable_32.c b/arch/powerpc/mm/pgtable_32.c
index 22972cd83cc9..58bcaeba728d 100644
--- a/arch/powerpc/mm/pgtable_32.c
+++ b/arch/powerpc/mm/pgtable_32.c
@@ -61,8 +61,8 @@ void setbat(int index, unsigned long virt, phys_addr_t phys,
61 61
62#ifdef HAVE_TLBCAM 62#ifdef HAVE_TLBCAM
63extern unsigned int tlbcam_index; 63extern unsigned int tlbcam_index;
64extern unsigned long v_mapped_by_tlbcam(unsigned long va); 64extern phys_addr_t v_mapped_by_tlbcam(unsigned long va);
65extern unsigned long p_mapped_by_tlbcam(unsigned long pa); 65extern unsigned long p_mapped_by_tlbcam(phys_addr_t pa);
66#else /* !HAVE_TLBCAM */ 66#else /* !HAVE_TLBCAM */
67#define v_mapped_by_tlbcam(x) (0UL) 67#define v_mapped_by_tlbcam(x) (0UL)
68#define p_mapped_by_tlbcam(x) (0UL) 68#define p_mapped_by_tlbcam(x) (0UL)
diff --git a/arch/powerpc/oprofile/cell/spu_profiler.c b/arch/powerpc/oprofile/cell/spu_profiler.c
index 9305ddaac512..b129d007e7fe 100644
--- a/arch/powerpc/oprofile/cell/spu_profiler.c
+++ b/arch/powerpc/oprofile/cell/spu_profiler.c
@@ -16,6 +16,7 @@
16#include <linux/smp.h> 16#include <linux/smp.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <asm/cell-pmu.h> 18#include <asm/cell-pmu.h>
19#include <asm/time.h>
19#include "pr_util.h" 20#include "pr_util.h"
20 21
21#define SCALE_SHIFT 14 22#define SCALE_SHIFT 14
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 9876d7e072f4..ddf0bdc0fc8b 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -186,7 +186,7 @@ out_unmap_regs:
186 iounmap(priv->regs); 186 iounmap(priv->regs);
187out_free_bootmem: 187out_free_bootmem:
188 free_bootmem((unsigned long)priv, 188 free_bootmem((unsigned long)priv,
189 sizeof(sizeof(struct pq2ads_pci_pic))); 189 sizeof(struct pq2ads_pci_pic));
190 of_node_put(np); 190 of_node_put(np);
191out_unmap_irq: 191out_unmap_irq:
192 irq_dispose_mapping(irq); 192 irq_dispose_mapping(irq);
diff --git a/arch/powerpc/platforms/86xx/gef_sbc610.c b/arch/powerpc/platforms/86xx/gef_sbc610.c
index fb371f5ce132..d6b772ba3b8f 100644
--- a/arch/powerpc/platforms/86xx/gef_sbc610.c
+++ b/arch/powerpc/platforms/86xx/gef_sbc610.c
@@ -142,6 +142,10 @@ static void __init gef_sbc610_nec_fixup(struct pci_dev *pdev)
142{ 142{
143 unsigned int val; 143 unsigned int val;
144 144
145 /* Do not do the fixup on other platforms! */
146 if (!machine_is(gef_sbc610))
147 return;
148
145 printk(KERN_INFO "Running NEC uPD720101 Fixup\n"); 149 printk(KERN_INFO "Running NEC uPD720101 Fixup\n");
146 150
147 /* Ensure ports 1, 2, 3, 4 & 5 are enabled */ 151 /* Ensure ports 1, 2, 3, 4 & 5 are enabled */
diff --git a/arch/powerpc/platforms/ps3/mm.c b/arch/powerpc/platforms/ps3/mm.c
index 67de6bf3db3d..d281cc0bca71 100644
--- a/arch/powerpc/platforms/ps3/mm.c
+++ b/arch/powerpc/platforms/ps3/mm.c
@@ -328,7 +328,7 @@ static int __init ps3_mm_add_memory(void)
328 return result; 328 return result;
329} 329}
330 330
331core_initcall(ps3_mm_add_memory); 331device_initcall(ps3_mm_add_memory);
332 332
333/*============================================================================*/ 333/*============================================================================*/
334/* dma routines */ 334/* dma routines */
diff --git a/arch/powerpc/platforms/pseries/hotplug-memory.c b/arch/powerpc/platforms/pseries/hotplug-memory.c
index a623ad256e9e..9b21ee68ea50 100644
--- a/arch/powerpc/platforms/pseries/hotplug-memory.c
+++ b/arch/powerpc/platforms/pseries/hotplug-memory.c
@@ -14,6 +14,7 @@
14#include <asm/firmware.h> 14#include <asm/firmware.h>
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/pSeries_reconfig.h> 16#include <asm/pSeries_reconfig.h>
17#include <asm/sparsemem.h>
17 18
18static int pseries_remove_lmb(unsigned long base, unsigned int lmb_size) 19static int pseries_remove_lmb(unsigned long base, unsigned int lmb_size)
19{ 20{
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index b16ca3ed65d2..78f1f7cca0a0 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -165,7 +165,7 @@ static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type)
165 edibit = (14 - (src - CPM2_IRQ_EXT1)); 165 edibit = (14 - (src - CPM2_IRQ_EXT1));
166 else 166 else
167 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0) 167 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
168 edibit = (31 - (src - CPM2_IRQ_PORTC15)); 168 edibit = (31 - (CPM2_IRQ_PORTC0 - src));
169 else 169 else
170 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL; 170 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
171 171
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 88a983ece5c9..9a89cd3e80a2 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -890,7 +890,7 @@ unsigned int ipic_get_irq(void)
890 return irq_linear_revmap(primary_ipic->irqhost, irq); 890 return irq_linear_revmap(primary_ipic->irqhost, irq);
891} 891}
892 892
893#ifdef CONFIG_PM 893#ifdef CONFIG_SUSPEND
894static struct { 894static struct {
895 u32 sicfr; 895 u32 sicfr;
896 u32 siprr[2]; 896 u32 siprr[2];
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.c b/arch/powerpc/sysdev/ppc4xx_pci.c
index 77fae5f64f2e..5558d932b4d5 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.c
+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
@@ -204,6 +204,23 @@ static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
204{ 204{
205 u32 ma, pcila, pciha; 205 u32 ma, pcila, pciha;
206 206
207 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
208 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
209 * address are actually hard wired to a value that appears to depend
210 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
211 *
212 * The trick here is we just crop those top bits and ignore them when
213 * programming the chip. That means the device-tree has to be right
214 * for the specific part used (we don't print a warning if it's wrong
215 * but on the other hand, you'll crash quickly enough), but at least
216 * this code should work whatever the hard coded value is
217 */
218 plb_addr &= 0xffffffffull;
219
220 /* Note: Due to the above hack, the test below doesn't actually test
221 * if you address is above 4G, but it tests that address and
222 * (address + size) are both contained in the same 4G
223 */
207 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || 224 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
208 size < 0x1000 || (plb_addr & (size - 1)) != 0) { 225 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
209 printk(KERN_WARNING "%s: Resource out of range\n", 226 printk(KERN_WARNING "%s: Resource out of range\n",
diff --git a/arch/s390/crypto/aes_s390.c b/arch/s390/crypto/aes_s390.c
index c42cd898f68b..6118890c946d 100644
--- a/arch/s390/crypto/aes_s390.c
+++ b/arch/s390/crypto/aes_s390.c
@@ -556,7 +556,7 @@ static void __exit aes_s390_fini(void)
556module_init(aes_s390_init); 556module_init(aes_s390_init);
557module_exit(aes_s390_fini); 557module_exit(aes_s390_fini);
558 558
559MODULE_ALIAS("aes"); 559MODULE_ALIAS("aes-all");
560 560
561MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm"); 561MODULE_DESCRIPTION("Rijndael (AES) Cipher Algorithm");
562MODULE_LICENSE("GPL"); 562MODULE_LICENSE("GPL");
diff --git a/arch/s390/defconfig b/arch/s390/defconfig
index a0e748da9909..31e809c77790 100644
--- a/arch/s390/defconfig
+++ b/arch/s390/defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc6 3# Linux kernel version: 2.6.29-rc4
4# Thu Nov 27 11:00:49 2008 4# Wed Feb 11 10:07:16 2009
5# 5#
6CONFIG_SCHED_MC=y 6CONFIG_SCHED_MC=y
7CONFIG_MMU=y 7CONFIG_MMU=y
@@ -14,12 +14,14 @@ CONFIG_RWSEM_XCHGADD_ALGORITHM=y
14# CONFIG_ARCH_HAS_ILOG2_U64 is not set 14# CONFIG_ARCH_HAS_ILOG2_U64 is not set
15CONFIG_GENERIC_HWEIGHT=y 15CONFIG_GENERIC_HWEIGHT=y
16CONFIG_GENERIC_TIME=y 16CONFIG_GENERIC_TIME=y
17CONFIG_GENERIC_TIME_VSYSCALL=y
17CONFIG_GENERIC_CLOCKEVENTS=y 18CONFIG_GENERIC_CLOCKEVENTS=y
18CONFIG_GENERIC_BUG=y 19CONFIG_GENERIC_BUG=y
19CONFIG_NO_IOMEM=y 20CONFIG_NO_IOMEM=y
20CONFIG_NO_DMA=y 21CONFIG_NO_DMA=y
21CONFIG_GENERIC_LOCKBREAK=y 22CONFIG_GENERIC_LOCKBREAK=y
22CONFIG_PGSTE=y 23CONFIG_PGSTE=y
24CONFIG_VIRT_CPU_ACCOUNTING=y
23CONFIG_S390=y 25CONFIG_S390=y
24CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
25 27
@@ -39,20 +41,29 @@ CONFIG_POSIX_MQUEUE=y
39# CONFIG_TASKSTATS is not set 41# CONFIG_TASKSTATS is not set
40CONFIG_AUDIT=y 42CONFIG_AUDIT=y
41# CONFIG_AUDITSYSCALL is not set 43# CONFIG_AUDITSYSCALL is not set
44
45#
46# RCU Subsystem
47#
48CONFIG_CLASSIC_RCU=y
49# CONFIG_TREE_RCU is not set
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_TREE_RCU_TRACE is not set
52# CONFIG_PREEMPT_RCU_TRACE is not set
42CONFIG_IKCONFIG=y 53CONFIG_IKCONFIG=y
43CONFIG_IKCONFIG_PROC=y 54CONFIG_IKCONFIG_PROC=y
44CONFIG_LOG_BUF_SHIFT=17 55CONFIG_LOG_BUF_SHIFT=17
56CONFIG_GROUP_SCHED=y
57CONFIG_FAIR_GROUP_SCHED=y
58# CONFIG_RT_GROUP_SCHED is not set
59CONFIG_USER_SCHED=y
60# CONFIG_CGROUP_SCHED is not set
45CONFIG_CGROUPS=y 61CONFIG_CGROUPS=y
46# CONFIG_CGROUP_DEBUG is not set 62# CONFIG_CGROUP_DEBUG is not set
47CONFIG_CGROUP_NS=y 63CONFIG_CGROUP_NS=y
48# CONFIG_CGROUP_FREEZER is not set 64# CONFIG_CGROUP_FREEZER is not set
49# CONFIG_CGROUP_DEVICE is not set 65# CONFIG_CGROUP_DEVICE is not set
50# CONFIG_CPUSETS is not set 66# CONFIG_CPUSETS is not set
51CONFIG_GROUP_SCHED=y
52CONFIG_FAIR_GROUP_SCHED=y
53# CONFIG_RT_GROUP_SCHED is not set
54CONFIG_USER_SCHED=y
55# CONFIG_CGROUP_SCHED is not set
56# CONFIG_CGROUP_CPUACCT is not set 67# CONFIG_CGROUP_CPUACCT is not set
57# CONFIG_RESOURCE_COUNTERS is not set 68# CONFIG_RESOURCE_COUNTERS is not set
58CONFIG_SYSFS_DEPRECATED=y 69CONFIG_SYSFS_DEPRECATED=y
@@ -63,6 +74,7 @@ CONFIG_UTS_NS=y
63CONFIG_IPC_NS=y 74CONFIG_IPC_NS=y
64# CONFIG_USER_NS is not set 75# CONFIG_USER_NS is not set
65# CONFIG_PID_NS is not set 76# CONFIG_PID_NS is not set
77# CONFIG_NET_NS is not set
66CONFIG_BLK_DEV_INITRD=y 78CONFIG_BLK_DEV_INITRD=y
67CONFIG_INITRAMFS_SOURCE="" 79CONFIG_INITRAMFS_SOURCE=""
68# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 80# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
@@ -91,17 +103,17 @@ CONFIG_SLAB=y
91# CONFIG_SLUB is not set 103# CONFIG_SLUB is not set
92# CONFIG_SLOB is not set 104# CONFIG_SLOB is not set
93# CONFIG_PROFILING is not set 105# CONFIG_PROFILING is not set
94# CONFIG_MARKERS is not set
95CONFIG_HAVE_OPROFILE=y 106CONFIG_HAVE_OPROFILE=y
96CONFIG_KPROBES=y 107CONFIG_KPROBES=y
108CONFIG_HAVE_SYSCALL_WRAPPERS=y
97CONFIG_KRETPROBES=y 109CONFIG_KRETPROBES=y
98CONFIG_HAVE_KPROBES=y 110CONFIG_HAVE_KPROBES=y
99CONFIG_HAVE_KRETPROBES=y 111CONFIG_HAVE_KRETPROBES=y
100CONFIG_HAVE_ARCH_TRACEHOOK=y 112CONFIG_HAVE_ARCH_TRACEHOOK=y
113CONFIG_USE_GENERIC_SMP_HELPERS=y
101# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set 114# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
102CONFIG_SLABINFO=y 115CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 116CONFIG_RT_MUTEXES=y
104# CONFIG_TINY_SHMEM is not set
105CONFIG_BASE_SMALL=0 117CONFIG_BASE_SMALL=0
106CONFIG_MODULES=y 118CONFIG_MODULES=y
107# CONFIG_MODULE_FORCE_LOAD is not set 119# CONFIG_MODULE_FORCE_LOAD is not set
@@ -109,7 +121,7 @@ CONFIG_MODULE_UNLOAD=y
109# CONFIG_MODULE_FORCE_UNLOAD is not set 121# CONFIG_MODULE_FORCE_UNLOAD is not set
110CONFIG_MODVERSIONS=y 122CONFIG_MODVERSIONS=y
111# CONFIG_MODULE_SRCVERSION_ALL is not set 123# CONFIG_MODULE_SRCVERSION_ALL is not set
112CONFIG_KMOD=y 124CONFIG_INIT_ALL_POSSIBLE=y
113CONFIG_STOP_MACHINE=y 125CONFIG_STOP_MACHINE=y
114CONFIG_BLOCK=y 126CONFIG_BLOCK=y
115# CONFIG_BLK_DEV_IO_TRACE is not set 127# CONFIG_BLK_DEV_IO_TRACE is not set
@@ -130,7 +142,6 @@ CONFIG_DEFAULT_DEADLINE=y
130# CONFIG_DEFAULT_NOOP is not set 142# CONFIG_DEFAULT_NOOP is not set
131CONFIG_DEFAULT_IOSCHED="deadline" 143CONFIG_DEFAULT_IOSCHED="deadline"
132CONFIG_PREEMPT_NOTIFIERS=y 144CONFIG_PREEMPT_NOTIFIERS=y
133CONFIG_CLASSIC_RCU=y
134# CONFIG_FREEZER is not set 145# CONFIG_FREEZER is not set
135 146
136# 147#
@@ -161,6 +172,7 @@ CONFIG_S390_EXEC_PROTECT=y
161CONFIG_MARCH_Z900=y 172CONFIG_MARCH_Z900=y
162# CONFIG_MARCH_Z990 is not set 173# CONFIG_MARCH_Z990 is not set
163# CONFIG_MARCH_Z9_109 is not set 174# CONFIG_MARCH_Z9_109 is not set
175# CONFIG_MARCH_Z10 is not set
164CONFIG_PACK_STACK=y 176CONFIG_PACK_STACK=y
165# CONFIG_SMALL_STACK is not set 177# CONFIG_SMALL_STACK is not set
166CONFIG_CHECK_STACK=y 178CONFIG_CHECK_STACK=y
@@ -174,7 +186,6 @@ CONFIG_ARCH_POPULATES_NODE_MAP=y
174# CONFIG_PREEMPT_NONE is not set 186# CONFIG_PREEMPT_NONE is not set
175# CONFIG_PREEMPT_VOLUNTARY is not set 187# CONFIG_PREEMPT_VOLUNTARY is not set
176CONFIG_PREEMPT=y 188CONFIG_PREEMPT=y
177# CONFIG_PREEMPT_RCU is not set
178CONFIG_ARCH_SPARSEMEM_ENABLE=y 189CONFIG_ARCH_SPARSEMEM_ENABLE=y
179CONFIG_ARCH_SPARSEMEM_DEFAULT=y 190CONFIG_ARCH_SPARSEMEM_DEFAULT=y
180CONFIG_ARCH_SELECT_MEMORY_MODEL=y 191CONFIG_ARCH_SELECT_MEMORY_MODEL=y
@@ -195,7 +206,6 @@ CONFIG_MEMORY_HOTREMOVE=y
195CONFIG_PAGEFLAGS_EXTENDED=y 206CONFIG_PAGEFLAGS_EXTENDED=y
196CONFIG_SPLIT_PTLOCK_CPUS=4 207CONFIG_SPLIT_PTLOCK_CPUS=4
197CONFIG_MIGRATION=y 208CONFIG_MIGRATION=y
198CONFIG_RESOURCES_64BIT=y
199CONFIG_PHYS_ADDR_T_64BIT=y 209CONFIG_PHYS_ADDR_T_64BIT=y
200CONFIG_ZONE_DMA_FLAG=1 210CONFIG_ZONE_DMA_FLAG=1
201CONFIG_BOUNCE=y 211CONFIG_BOUNCE=y
@@ -207,7 +217,6 @@ CONFIG_UNEVICTABLE_LRU=y
207# 217#
208CONFIG_MACHCHK_WARNING=y 218CONFIG_MACHCHK_WARNING=y
209CONFIG_QDIO=y 219CONFIG_QDIO=y
210# CONFIG_QDIO_DEBUG is not set
211CONFIG_CHSC_SCH=m 220CONFIG_CHSC_SCH=m
212 221
213# 222#
@@ -227,15 +236,13 @@ CONFIG_PFAULT=y
227# CONFIG_SHARED_KERNEL is not set 236# CONFIG_SHARED_KERNEL is not set
228# CONFIG_CMM is not set 237# CONFIG_CMM is not set
229# CONFIG_PAGE_STATES is not set 238# CONFIG_PAGE_STATES is not set
230CONFIG_VIRT_TIMER=y
231CONFIG_VIRT_CPU_ACCOUNTING=y
232# CONFIG_APPLDATA_BASE is not set 239# CONFIG_APPLDATA_BASE is not set
233CONFIG_HZ_100=y 240CONFIG_HZ_100=y
234# CONFIG_HZ_250 is not set 241# CONFIG_HZ_250 is not set
235# CONFIG_HZ_300 is not set 242# CONFIG_HZ_300 is not set
236# CONFIG_HZ_1000 is not set 243# CONFIG_HZ_1000 is not set
237CONFIG_HZ=100 244CONFIG_HZ=100
238# CONFIG_SCHED_HRTICK is not set 245CONFIG_SCHED_HRTICK=y
239CONFIG_S390_HYPFS_FS=y 246CONFIG_S390_HYPFS_FS=y
240CONFIG_KEXEC=y 247CONFIG_KEXEC=y
241# CONFIG_ZFCPDUMP is not set 248# CONFIG_ZFCPDUMP is not set
@@ -245,6 +252,7 @@ CONFIG_NET=y
245# 252#
246# Networking options 253# Networking options
247# 254#
255CONFIG_COMPAT_NET_DEV_OPS=y
248CONFIG_PACKET=y 256CONFIG_PACKET=y
249# CONFIG_PACKET_MMAP is not set 257# CONFIG_PACKET_MMAP is not set
250CONFIG_UNIX=y 258CONFIG_UNIX=y
@@ -383,6 +391,7 @@ CONFIG_NET_SCH_TBF=m
383CONFIG_NET_SCH_GRED=m 391CONFIG_NET_SCH_GRED=m
384CONFIG_NET_SCH_DSMARK=m 392CONFIG_NET_SCH_DSMARK=m
385# CONFIG_NET_SCH_NETEM is not set 393# CONFIG_NET_SCH_NETEM is not set
394# CONFIG_NET_SCH_DRR is not set
386# CONFIG_NET_SCH_INGRESS is not set 395# CONFIG_NET_SCH_INGRESS is not set
387 396
388# 397#
@@ -400,6 +409,7 @@ CONFIG_CLS_U32_MARK=y
400CONFIG_NET_CLS_RSVP=m 409CONFIG_NET_CLS_RSVP=m
401CONFIG_NET_CLS_RSVP6=m 410CONFIG_NET_CLS_RSVP6=m
402CONFIG_NET_CLS_FLOW=m 411CONFIG_NET_CLS_FLOW=m
412# CONFIG_NET_CLS_CGROUP is not set
403# CONFIG_NET_EMATCH is not set 413# CONFIG_NET_EMATCH is not set
404CONFIG_NET_CLS_ACT=y 414CONFIG_NET_CLS_ACT=y
405CONFIG_NET_ACT_POLICE=y 415CONFIG_NET_ACT_POLICE=y
@@ -411,6 +421,7 @@ CONFIG_NET_ACT_NAT=m
411# CONFIG_NET_ACT_SKBEDIT is not set 421# CONFIG_NET_ACT_SKBEDIT is not set
412# CONFIG_NET_CLS_IND is not set 422# CONFIG_NET_CLS_IND is not set
413CONFIG_NET_SCH_FIFO=y 423CONFIG_NET_SCH_FIFO=y
424# CONFIG_DCB is not set
414 425
415# 426#
416# Network testing 427# Network testing
@@ -428,6 +439,7 @@ CONFIG_CAN_VCAN=m
428# CONFIG_CAN_DEBUG_DEVICES is not set 439# CONFIG_CAN_DEBUG_DEVICES is not set
429# CONFIG_AF_RXRPC is not set 440# CONFIG_AF_RXRPC is not set
430# CONFIG_PHONET is not set 441# CONFIG_PHONET is not set
442# CONFIG_WIMAX is not set
431# CONFIG_RFKILL is not set 443# CONFIG_RFKILL is not set
432# CONFIG_NET_9P is not set 444# CONFIG_NET_9P is not set
433# CONFIG_PCMCIA is not set 445# CONFIG_PCMCIA is not set
@@ -475,11 +487,15 @@ CONFIG_DASD_DIAG=y
475CONFIG_DASD_EER=y 487CONFIG_DASD_EER=y
476CONFIG_VIRTIO_BLK=m 488CONFIG_VIRTIO_BLK=m
477CONFIG_MISC_DEVICES=y 489CONFIG_MISC_DEVICES=y
478# CONFIG_EEPROM_93CX6 is not set
479# CONFIG_ENCLOSURE_SERVICES is not set 490# CONFIG_ENCLOSURE_SERVICES is not set
480# CONFIG_C2PORT is not set 491# CONFIG_C2PORT is not set
481 492
482# 493#
494# EEPROM support
495#
496# CONFIG_EEPROM_93CX6 is not set
497
498#
483# SCSI device support 499# SCSI device support
484# 500#
485# CONFIG_RAID_ATTRS is not set 501# CONFIG_RAID_ATTRS is not set
@@ -520,6 +536,7 @@ CONFIG_SCSI_FC_ATTRS=y
520# CONFIG_SCSI_SRP_ATTRS is not set 536# CONFIG_SCSI_SRP_ATTRS is not set
521CONFIG_SCSI_LOWLEVEL=y 537CONFIG_SCSI_LOWLEVEL=y
522# CONFIG_ISCSI_TCP is not set 538# CONFIG_ISCSI_TCP is not set
539# CONFIG_LIBFC is not set
523# CONFIG_SCSI_DEBUG is not set 540# CONFIG_SCSI_DEBUG is not set
524CONFIG_ZFCP=y 541CONFIG_ZFCP=y
525CONFIG_SCSI_DH=m 542CONFIG_SCSI_DH=m
@@ -566,6 +583,10 @@ CONFIG_NET_ETHERNET=y
566CONFIG_NETDEV_1000=y 583CONFIG_NETDEV_1000=y
567CONFIG_NETDEV_10000=y 584CONFIG_NETDEV_10000=y
568# CONFIG_TR is not set 585# CONFIG_TR is not set
586
587#
588# Enable WiMAX (Networking options) to see the WiMAX drivers
589#
569# CONFIG_WAN is not set 590# CONFIG_WAN is not set
570 591
571# 592#
@@ -593,9 +614,11 @@ CONFIG_VIRTIO_NET=m
593# 614#
594CONFIG_DEVKMEM=y 615CONFIG_DEVKMEM=y
595CONFIG_UNIX98_PTYS=y 616CONFIG_UNIX98_PTYS=y
617# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
596CONFIG_LEGACY_PTYS=y 618CONFIG_LEGACY_PTYS=y
597CONFIG_LEGACY_PTY_COUNT=256 619CONFIG_LEGACY_PTY_COUNT=256
598CONFIG_HVC_DRIVER=y 620CONFIG_HVC_DRIVER=y
621CONFIG_HVC_IUCV=y
599CONFIG_VIRTIO_CONSOLE=y 622CONFIG_VIRTIO_CONSOLE=y
600CONFIG_HW_RANDOM=m 623CONFIG_HW_RANDOM=m
601CONFIG_HW_RANDOM_VIRTIO=m 624CONFIG_HW_RANDOM_VIRTIO=m
@@ -645,7 +668,6 @@ CONFIG_S390_VMUR=m
645# CONFIG_NEW_LEDS is not set 668# CONFIG_NEW_LEDS is not set
646CONFIG_ACCESSIBILITY=y 669CONFIG_ACCESSIBILITY=y
647# CONFIG_STAGING is not set 670# CONFIG_STAGING is not set
648CONFIG_STAGING_EXCLUDE_BUILD=y
649 671
650# 672#
651# File systems 673# File systems
@@ -668,6 +690,7 @@ CONFIG_FILE_LOCKING=y
668# CONFIG_XFS_FS is not set 690# CONFIG_XFS_FS is not set
669# CONFIG_GFS2_FS is not set 691# CONFIG_GFS2_FS is not set
670# CONFIG_OCFS2_FS is not set 692# CONFIG_OCFS2_FS is not set
693# CONFIG_BTRFS_FS is not set
671CONFIG_DNOTIFY=y 694CONFIG_DNOTIFY=y
672CONFIG_INOTIFY=y 695CONFIG_INOTIFY=y
673CONFIG_INOTIFY_USER=y 696CONFIG_INOTIFY_USER=y
@@ -703,10 +726,7 @@ CONFIG_TMPFS_POSIX_ACL=y
703# CONFIG_HUGETLBFS is not set 726# CONFIG_HUGETLBFS is not set
704# CONFIG_HUGETLB_PAGE is not set 727# CONFIG_HUGETLB_PAGE is not set
705CONFIG_CONFIGFS_FS=m 728CONFIG_CONFIGFS_FS=m
706 729CONFIG_MISC_FILESYSTEMS=y
707#
708# Miscellaneous filesystems
709#
710# CONFIG_ADFS_FS is not set 730# CONFIG_ADFS_FS is not set
711# CONFIG_AFFS_FS is not set 731# CONFIG_AFFS_FS is not set
712# CONFIG_HFS_FS is not set 732# CONFIG_HFS_FS is not set
@@ -715,6 +735,7 @@ CONFIG_CONFIGFS_FS=m
715# CONFIG_BFS_FS is not set 735# CONFIG_BFS_FS is not set
716# CONFIG_EFS_FS is not set 736# CONFIG_EFS_FS is not set
717# CONFIG_CRAMFS is not set 737# CONFIG_CRAMFS is not set
738# CONFIG_SQUASHFS is not set
718# CONFIG_VXFS_FS is not set 739# CONFIG_VXFS_FS is not set
719# CONFIG_MINIX_FS is not set 740# CONFIG_MINIX_FS is not set
720# CONFIG_OMFS_FS is not set 741# CONFIG_OMFS_FS is not set
@@ -808,6 +829,7 @@ CONFIG_DEBUG_BUGVERBOSE=y
808CONFIG_DEBUG_MEMORY_INIT=y 829CONFIG_DEBUG_MEMORY_INIT=y
809# CONFIG_DEBUG_LIST is not set 830# CONFIG_DEBUG_LIST is not set
810# CONFIG_DEBUG_SG is not set 831# CONFIG_DEBUG_SG is not set
832# CONFIG_DEBUG_NOTIFIERS is not set
811# CONFIG_FRAME_POINTER is not set 833# CONFIG_FRAME_POINTER is not set
812# CONFIG_RCU_TORTURE_TEST is not set 834# CONFIG_RCU_TORTURE_TEST is not set
813# CONFIG_RCU_CPU_STALL_DETECTOR is not set 835# CONFIG_RCU_CPU_STALL_DETECTOR is not set
@@ -818,15 +840,19 @@ CONFIG_DEBUG_MEMORY_INIT=y
818# CONFIG_FAULT_INJECTION is not set 840# CONFIG_FAULT_INJECTION is not set
819# CONFIG_LATENCYTOP is not set 841# CONFIG_LATENCYTOP is not set
820CONFIG_SYSCTL_SYSCALL_CHECK=y 842CONFIG_SYSCTL_SYSCALL_CHECK=y
843CONFIG_HAVE_FUNCTION_TRACER=y
821 844
822# 845#
823# Tracers 846# Tracers
824# 847#
848# CONFIG_FUNCTION_TRACER is not set
825# CONFIG_IRQSOFF_TRACER is not set 849# CONFIG_IRQSOFF_TRACER is not set
826# CONFIG_PREEMPT_TRACER is not set 850# CONFIG_PREEMPT_TRACER is not set
827# CONFIG_SCHED_TRACER is not set 851# CONFIG_SCHED_TRACER is not set
828# CONFIG_CONTEXT_SWITCH_TRACER is not set 852# CONFIG_CONTEXT_SWITCH_TRACER is not set
829# CONFIG_BOOT_TRACER is not set 853# CONFIG_BOOT_TRACER is not set
854# CONFIG_TRACE_BRANCH_PROFILING is not set
855# CONFIG_STACK_TRACER is not set
830# CONFIG_DYNAMIC_PRINTK_DEBUG is not set 856# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
831CONFIG_SAMPLES=y 857CONFIG_SAMPLES=y
832# CONFIG_SAMPLE_KOBJECT is not set 858# CONFIG_SAMPLE_KOBJECT is not set
@@ -847,11 +873,17 @@ CONFIG_CRYPTO=y
847# 873#
848CONFIG_CRYPTO_FIPS=y 874CONFIG_CRYPTO_FIPS=y
849CONFIG_CRYPTO_ALGAPI=y 875CONFIG_CRYPTO_ALGAPI=y
850CONFIG_CRYPTO_AEAD=y 876CONFIG_CRYPTO_ALGAPI2=y
877CONFIG_CRYPTO_AEAD=m
878CONFIG_CRYPTO_AEAD2=y
851CONFIG_CRYPTO_BLKCIPHER=y 879CONFIG_CRYPTO_BLKCIPHER=y
852CONFIG_CRYPTO_HASH=y 880CONFIG_CRYPTO_BLKCIPHER2=y
853CONFIG_CRYPTO_RNG=y 881CONFIG_CRYPTO_HASH=m
882CONFIG_CRYPTO_HASH2=y
883CONFIG_CRYPTO_RNG=m
884CONFIG_CRYPTO_RNG2=y
854CONFIG_CRYPTO_MANAGER=y 885CONFIG_CRYPTO_MANAGER=y
886CONFIG_CRYPTO_MANAGER2=y
855CONFIG_CRYPTO_GF128MUL=m 887CONFIG_CRYPTO_GF128MUL=m
856# CONFIG_CRYPTO_NULL is not set 888# CONFIG_CRYPTO_NULL is not set
857# CONFIG_CRYPTO_CRYPTD is not set 889# CONFIG_CRYPTO_CRYPTD is not set
@@ -885,7 +917,7 @@ CONFIG_CRYPTO_HMAC=m
885# 917#
886# Digest 918# Digest
887# 919#
888# CONFIG_CRYPTO_CRC32C is not set 920CONFIG_CRYPTO_CRC32C=m
889# CONFIG_CRYPTO_MD4 is not set 921# CONFIG_CRYPTO_MD4 is not set
890CONFIG_CRYPTO_MD5=m 922CONFIG_CRYPTO_MD5=m
891# CONFIG_CRYPTO_MICHAEL_MIC is not set 923# CONFIG_CRYPTO_MICHAEL_MIC is not set
@@ -942,6 +974,7 @@ CONFIG_S390_PRNG=m
942# Library routines 974# Library routines
943# 975#
944CONFIG_BITREVERSE=m 976CONFIG_BITREVERSE=m
977CONFIG_GENERIC_FIND_LAST_BIT=y
945# CONFIG_CRC_CCITT is not set 978# CONFIG_CRC_CCITT is not set
946# CONFIG_CRC16 is not set 979# CONFIG_CRC16 is not set
947CONFIG_CRC_T10DIF=y 980CONFIG_CRC_T10DIF=y
diff --git a/arch/s390/include/asm/cputime.h b/arch/s390/include/asm/cputime.h
index 521726430afa..95b0f7db3c69 100644
--- a/arch/s390/include/asm/cputime.h
+++ b/arch/s390/include/asm/cputime.h
@@ -145,7 +145,7 @@ cputime_to_timeval(const cputime_t cputime, struct timeval *value)
145 value->tv_usec = rp.subreg.even / 4096; 145 value->tv_usec = rp.subreg.even / 4096;
146 value->tv_sec = rp.subreg.odd; 146 value->tv_sec = rp.subreg.odd;
147#else 147#else
148 value->tv_usec = cputime % 4096000000ULL; 148 value->tv_usec = (cputime % 4096000000ULL) / 4096;
149 value->tv_sec = cputime / 4096000000ULL; 149 value->tv_sec = cputime / 4096000000ULL;
150#endif 150#endif
151} 151}
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index ffdef5fe8587..f3720defdd16 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -384,8 +384,8 @@ struct _lowcore
384 __u32 panic_magic; /* 0xe00 */ 384 __u32 panic_magic; /* 0xe00 */
385 385
386 /* Per cpu primary space access list */ 386 /* Per cpu primary space access list */
387 __u8 pad_0xe04[0xe3c-0xe04]; /* 0xe04 */ 387 __u8 pad_0xe04[0xe38-0xe04]; /* 0xe04 */
388 __u32 vdso_per_cpu_data; /* 0xe3c */ 388 __u64 vdso_per_cpu_data; /* 0xe38 */
389 __u32 paste[16]; /* 0xe40 */ 389 __u32 paste[16]; /* 0xe40 */
390 390
391 __u8 pad13[0x11b8-0xe80]; /* 0xe80 */ 391 __u8 pad13[0x11b8-0xe80]; /* 0xe80 */
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index 2bd9faeb3919..e8bd6ac22c99 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -43,6 +43,8 @@ struct mem_chunk {
43 43
44extern struct mem_chunk memory_chunk[]; 44extern struct mem_chunk memory_chunk[];
45extern unsigned long real_memory_size; 45extern unsigned long real_memory_size;
46extern int memory_end_set;
47extern unsigned long memory_end;
46 48
47void detect_memory_layout(struct mem_chunk chunk[]); 49void detect_memory_layout(struct mem_chunk chunk[]);
48 50
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index e7c5bfb7c755..026a37a94fc9 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -95,6 +95,7 @@ asmlinkage void do_softirq(void)
95 local_irq_restore(flags); 95 local_irq_restore(flags);
96} 96}
97 97
98#ifdef CONFIG_PROC_FS
98void init_irq_proc(void) 99void init_irq_proc(void)
99{ 100{
100 struct proc_dir_entry *root_irq_dir; 101 struct proc_dir_entry *root_irq_dir;
@@ -102,3 +103,4 @@ void init_irq_proc(void)
102 root_irq_dir = proc_mkdir("irq", NULL); 103 root_irq_dir = proc_mkdir("irq", NULL);
103 create_prof_cpu_mask(root_irq_dir); 104 create_prof_cpu_mask(root_irq_dir);
104} 105}
106#endif
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index d825f4950e4e..c5cfb6185eac 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -82,7 +82,9 @@ char elf_platform[ELF_PLATFORM_SIZE];
82 82
83struct mem_chunk __initdata memory_chunk[MEMORY_CHUNKS]; 83struct mem_chunk __initdata memory_chunk[MEMORY_CHUNKS];
84volatile int __cpu_logical_map[NR_CPUS]; /* logical cpu to cpu address */ 84volatile int __cpu_logical_map[NR_CPUS]; /* logical cpu to cpu address */
85static unsigned long __initdata memory_end; 85
86int __initdata memory_end_set;
87unsigned long __initdata memory_end;
86 88
87/* 89/*
88 * This is set up by the setup-routine at boot-time 90 * This is set up by the setup-routine at boot-time
@@ -281,6 +283,7 @@ void (*pm_power_off)(void) = machine_power_off;
281static int __init early_parse_mem(char *p) 283static int __init early_parse_mem(char *p)
282{ 284{
283 memory_end = memparse(p, &p); 285 memory_end = memparse(p, &p);
286 memory_end_set = 1;
284 return 0; 287 return 0;
285} 288}
286early_param("mem", early_parse_mem); 289early_param("mem", early_parse_mem);
@@ -508,8 +511,10 @@ static void __init setup_memory_end(void)
508 int i; 511 int i;
509 512
510#if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_ZFCPDUMP_MODULE) 513#if defined(CONFIG_ZFCPDUMP) || defined(CONFIG_ZFCPDUMP_MODULE)
511 if (ipl_info.type == IPL_TYPE_FCP_DUMP) 514 if (ipl_info.type == IPL_TYPE_FCP_DUMP) {
512 memory_end = ZFCPDUMP_HSA_SIZE; 515 memory_end = ZFCPDUMP_HSA_SIZE;
516 memory_end_set = 1;
517 }
513#endif 518#endif
514 memory_size = 0; 519 memory_size = 0;
515 memory_end &= PAGE_MASK; 520 memory_end &= PAGE_MASK;
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index be8497186b96..0d33893e1e89 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -212,6 +212,10 @@ static void kvm_free_vcpus(struct kvm *kvm)
212 } 212 }
213} 213}
214 214
215void kvm_arch_sync_events(struct kvm *kvm)
216{
217}
218
215void kvm_arch_destroy_vm(struct kvm *kvm) 219void kvm_arch_destroy_vm(struct kvm *kvm)
216{ 220{
217 kvm_free_vcpus(kvm); 221 kvm_free_vcpus(kvm);
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index 7c35787d29b4..15b6d450fbf0 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -22,7 +22,7 @@
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
24#include <linux/spi/spi_gpio.h> 24#include <linux/spi/spi_gpio.h>
25#include <media/ov772x.h> 25#include <media/soc_camera.h>
26#include <media/soc_camera_platform.h> 26#include <media/soc_camera_platform.h>
27#include <media/sh_mobile_ceu.h> 27#include <media/sh_mobile_ceu.h>
28#include <video/sh_mobile_lcdc.h> 28#include <video/sh_mobile_lcdc.h>
@@ -224,7 +224,6 @@ static void camera_power(int val)
224} 224}
225 225
226#ifdef CONFIG_I2C 226#ifdef CONFIG_I2C
227/* support for the old ncm03j camera */
228static unsigned char camera_ncm03j_magic[] = 227static unsigned char camera_ncm03j_magic[] =
229{ 228{
230 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8, 229 0x87, 0x00, 0x88, 0x08, 0x89, 0x01, 0x8A, 0xE8,
@@ -245,23 +244,6 @@ static unsigned char camera_ncm03j_magic[] =
245 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F, 244 0x63, 0xD4, 0x64, 0xEA, 0xD6, 0x0F,
246}; 245};
247 246
248static int camera_probe(void)
249{
250 struct i2c_adapter *a = i2c_get_adapter(0);
251 struct i2c_msg msg;
252 int ret;
253
254 camera_power(1);
255 msg.addr = 0x6e;
256 msg.buf = camera_ncm03j_magic;
257 msg.len = 2;
258 msg.flags = 0;
259 ret = i2c_transfer(a, &msg, 1);
260 camera_power(0);
261
262 return ret;
263}
264
265static int camera_set_capture(struct soc_camera_platform_info *info, 247static int camera_set_capture(struct soc_camera_platform_info *info,
266 int enable) 248 int enable)
267{ 249{
@@ -313,35 +295,8 @@ static struct platform_device camera_device = {
313 .platform_data = &camera_info, 295 .platform_data = &camera_info,
314 }, 296 },
315}; 297};
316
317static int __init camera_setup(void)
318{
319 if (camera_probe() > 0)
320 platform_device_register(&camera_device);
321
322 return 0;
323}
324late_initcall(camera_setup);
325
326#endif /* CONFIG_I2C */ 298#endif /* CONFIG_I2C */
327 299
328static int ov7725_power(struct device *dev, int mode)
329{
330 camera_power(0);
331 if (mode)
332 camera_power(1);
333
334 return 0;
335}
336
337static struct ov772x_camera_info ov7725_info = {
338 .buswidth = SOCAM_DATAWIDTH_8,
339 .flags = OV772X_FLAG_VFLIP | OV772X_FLAG_HFLIP,
340 .link = {
341 .power = ov7725_power,
342 },
343};
344
345static struct sh_mobile_ceu_info sh_mobile_ceu_info = { 300static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
346 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH | 301 .flags = SOCAM_PCLK_SAMPLE_RISING | SOCAM_HSYNC_ACTIVE_HIGH |
347 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8, 302 SOCAM_VSYNC_ACTIVE_HIGH | SOCAM_MASTER | SOCAM_DATAWIDTH_8,
@@ -392,6 +347,9 @@ static struct platform_device *ap325rxa_devices[] __initdata = {
392 &ap325rxa_nor_flash_device, 347 &ap325rxa_nor_flash_device,
393 &lcdc_device, 348 &lcdc_device,
394 &ceu_device, 349 &ceu_device,
350#ifdef CONFIG_I2C
351 &camera_device,
352#endif
395 &nand_flash_device, 353 &nand_flash_device,
396 &sdcard_cn3_device, 354 &sdcard_cn3_device,
397}; 355};
@@ -400,10 +358,6 @@ static struct i2c_board_info __initdata ap325rxa_i2c_devices[] = {
400 { 358 {
401 I2C_BOARD_INFO("pcf8563", 0x51), 359 I2C_BOARD_INFO("pcf8563", 0x51),
402 }, 360 },
403 {
404 I2C_BOARD_INFO("ov772x", 0x21),
405 .platform_data = &ov7725_info,
406 },
407}; 361};
408 362
409static struct spi_board_info ap325rxa_spi_devices[] = { 363static struct spi_board_info ap325rxa_spi_devices[] = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 020a96fe961a..4a5e59732334 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -18,8 +18,8 @@
18#include <asm/freq.h> 18#include <asm/freq.h>
19#include <asm/io.h> 19#include <asm/io.h>
20 20
21const static int pll1rate[]={1,2,3,4,6,8}; 21static const int pll1rate[]={1,2,3,4,6,8};
22const static int pfc_divisors[]={1,2,3,4,6,8,12}; 22static const int pfc_divisors[]={1,2,3,4,6,8,12};
23#define ifc_divisors pfc_divisors 23#define ifc_divisors pfc_divisors
24 24
25#if (CONFIG_SH_CLK_MD == 0) 25#if (CONFIG_SH_CLK_MD == 0)
diff --git a/arch/sparc/include/asm/compat.h b/arch/sparc/include/asm/compat.h
index f260b58f5ce9..0e706257918f 100644
--- a/arch/sparc/include/asm/compat.h
+++ b/arch/sparc/include/asm/compat.h
@@ -240,4 +240,9 @@ struct compat_shmid64_ds {
240 unsigned int __unused2; 240 unsigned int __unused2;
241}; 241};
242 242
243static inline int is_compat_task(void)
244{
245 return test_thread_flag(TIF_32BIT);
246}
247
243#endif /* _ASM_SPARC64_COMPAT_H */ 248#endif /* _ASM_SPARC64_COMPAT_H */
diff --git a/arch/sparc/include/asm/seccomp.h b/arch/sparc/include/asm/seccomp.h
index 7fcd9968192b..adca1bce41d4 100644
--- a/arch/sparc/include/asm/seccomp.h
+++ b/arch/sparc/include/asm/seccomp.h
@@ -1,11 +1,5 @@
1#ifndef _ASM_SECCOMP_H 1#ifndef _ASM_SECCOMP_H
2 2
3#include <linux/thread_info.h> /* already defines TIF_32BIT */
4
5#ifndef TIF_32BIT
6#error "unexpected TIF_32BIT on sparc64"
7#endif
8
9#include <linux/unistd.h> 3#include <linux/unistd.h>
10 4
11#define __NR_seccomp_read __NR_read 5#define __NR_seccomp_read __NR_read
diff --git a/arch/sparc/kernel/chmc.c b/arch/sparc/kernel/chmc.c
index 3b9f4d6e14a9..e1a9598e2a4d 100644
--- a/arch/sparc/kernel/chmc.c
+++ b/arch/sparc/kernel/chmc.c
@@ -306,6 +306,7 @@ static int jbusmc_print_dimm(int syndrome_code,
306 buf[1] = '?'; 306 buf[1] = '?';
307 buf[2] = '?'; 307 buf[2] = '?';
308 buf[3] = '\0'; 308 buf[3] = '\0';
309 return 0;
309 } 310 }
310 p = dp->controller; 311 p = dp->controller;
311 prop = &p->layout; 312 prop = &p->layout;
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 8ffee714f932..a46c3a21e26d 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -891,10 +891,35 @@ prom_tba: .xword 0
891tlb_type: .word 0 /* Must NOT end up in BSS */ 891tlb_type: .word 0 /* Must NOT end up in BSS */
892 .section ".fixup",#alloc,#execinstr 892 .section ".fixup",#alloc,#execinstr
893 893
894 .globl __ret_efault, __retl_efault 894 .globl __ret_efault, __retl_efault, __ret_one, __retl_one
895__ret_efault: 895ENTRY(__ret_efault)
896 ret 896 ret
897 restore %g0, -EFAULT, %o0 897 restore %g0, -EFAULT, %o0
898__retl_efault: 898ENDPROC(__ret_efault)
899
900ENTRY(__retl_efault)
899 retl 901 retl
900 mov -EFAULT, %o0 902 mov -EFAULT, %o0
903ENDPROC(__retl_efault)
904
905ENTRY(__retl_one)
906 retl
907 mov 1, %o0
908ENDPROC(__retl_one)
909
910ENTRY(__ret_one_asi)
911 wr %g0, ASI_AIUS, %asi
912 ret
913 restore %g0, 1, %o0
914ENDPROC(__ret_one_asi)
915
916ENTRY(__retl_one_asi)
917 wr %g0, ASI_AIUS, %asi
918 retl
919 mov 1, %o0
920ENDPROC(__retl_one_asi)
921
922ENTRY(__retl_o1)
923 retl
924 mov %o1, %o0
925ENDPROC(__retl_o1)
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c
index 09f088ed4a64..f3577223c863 100644
--- a/arch/sparc/kernel/nmi.c
+++ b/arch/sparc/kernel/nmi.c
@@ -70,6 +70,7 @@ static void die_nmi(const char *str, struct pt_regs *regs, int do_panic)
70 printk(" on CPU%d, ip %08lx, registers:\n", 70 printk(" on CPU%d, ip %08lx, registers:\n",
71 smp_processor_id(), regs->tpc); 71 smp_processor_id(), regs->tpc);
72 show_regs(regs); 72 show_regs(regs);
73 dump_stack();
73 74
74 bust_spinlocks(0); 75 bust_spinlocks(0);
75 76
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index 92e0dda141a4..1ae8cdd7e703 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -133,11 +133,16 @@ int __init pcr_arch_init(void)
133 133
134 case cheetah: 134 case cheetah:
135 case cheetah_plus: 135 case cheetah_plus:
136 case spitfire:
137 pcr_ops = &direct_pcr_ops; 136 pcr_ops = &direct_pcr_ops;
138 pcr_enable = PCR_SUN4U_ENABLE; 137 pcr_enable = PCR_SUN4U_ENABLE;
139 break; 138 break;
140 139
140 case spitfire:
141 /* UltraSPARC-I/II and derivatives lack a profile
142 * counter overflow interrupt so we can't make use of
143 * their hardware currently.
144 */
145 /* fallthrough */
141 default: 146 default:
142 err = -ENODEV; 147 err = -ENODEV;
143 goto out_unregister; 148 goto out_unregister;
diff --git a/arch/sparc/lib/GENbzero.S b/arch/sparc/lib/GENbzero.S
index 6a4f956a2f7a..8e7a843ddd88 100644
--- a/arch/sparc/lib/GENbzero.S
+++ b/arch/sparc/lib/GENbzero.S
@@ -6,13 +6,9 @@
6 6
7#define EX_ST(x,y) \ 7#define EX_ST(x,y) \
898: x,y; \ 898: x,y; \
9 .section .fixup; \
10 .align 4; \
1199: retl; \
12 mov %o1, %o0; \
13 .section __ex_table,"a";\ 9 .section __ex_table,"a";\
14 .align 4; \ 10 .align 4; \
15 .word 98b, 99b; \ 11 .word 98b, __retl_o1; \
16 .text; \ 12 .text; \
17 .align 4; 13 .align 4;
18 14
diff --git a/arch/sparc/lib/GENcopy_from_user.S b/arch/sparc/lib/GENcopy_from_user.S
index 2b9df99e87f9..b7d0bd6b1406 100644
--- a/arch/sparc/lib/GENcopy_from_user.S
+++ b/arch/sparc/lib/GENcopy_from_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_LD(x) \ 6#define EX_LD(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
@@ -27,7 +23,7 @@
27#define PREAMBLE \ 23#define PREAMBLE \
28 rd %asi, %g1; \ 24 rd %asi, %g1; \
29 cmp %g1, ASI_AIUS; \ 25 cmp %g1, ASI_AIUS; \
30 bne,pn %icc, memcpy_user_stub; \ 26 bne,pn %icc, ___copy_in_user; \
31 nop 27 nop
32#endif 28#endif
33 29
diff --git a/arch/sparc/lib/GENcopy_to_user.S b/arch/sparc/lib/GENcopy_to_user.S
index bb3f7084daf9..780550e1afc7 100644
--- a/arch/sparc/lib/GENcopy_to_user.S
+++ b/arch/sparc/lib/GENcopy_to_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_ST(x) \ 6#define EX_ST(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
@@ -31,7 +27,7 @@
31#define PREAMBLE \ 27#define PREAMBLE \
32 rd %asi, %g1; \ 28 rd %asi, %g1; \
33 cmp %g1, ASI_AIUS; \ 29 cmp %g1, ASI_AIUS; \
34 bne,pn %icc, memcpy_user_stub; \ 30 bne,pn %icc, ___copy_in_user; \
35 nop 31 nop
36#endif 32#endif
37 33
diff --git a/arch/sparc/lib/NG2copy_from_user.S b/arch/sparc/lib/NG2copy_from_user.S
index c77ef5f22102..119ccb9a54f4 100644
--- a/arch/sparc/lib/NG2copy_from_user.S
+++ b/arch/sparc/lib/NG2copy_from_user.S
@@ -5,14 +5,9 @@
5 5
6#define EX_LD(x) \ 6#define EX_LD(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: wr %g0, ASI_AIUS, %asi;\
11 retl; \
12 mov 1, %o0; \
13 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
14 .align 4; \ 9 .align 4; \
15 .word 98b, 99b; \ 10 .word 98b, __retl_one_asi;\
16 .text; \ 11 .text; \
17 .align 4; 12 .align 4;
18 13
@@ -33,7 +28,7 @@
33#define PREAMBLE \ 28#define PREAMBLE \
34 rd %asi, %g1; \ 29 rd %asi, %g1; \
35 cmp %g1, ASI_AIUS; \ 30 cmp %g1, ASI_AIUS; \
36 bne,pn %icc, memcpy_user_stub; \ 31 bne,pn %icc, ___copy_in_user; \
37 nop 32 nop
38#endif 33#endif
39 34
diff --git a/arch/sparc/lib/NG2copy_to_user.S b/arch/sparc/lib/NG2copy_to_user.S
index 4bd4093acbbd..7fe1ccefd9d0 100644
--- a/arch/sparc/lib/NG2copy_to_user.S
+++ b/arch/sparc/lib/NG2copy_to_user.S
@@ -5,14 +5,9 @@
5 5
6#define EX_ST(x) \ 6#define EX_ST(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: wr %g0, ASI_AIUS, %asi;\
11 retl; \
12 mov 1, %o0; \
13 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
14 .align 4; \ 9 .align 4; \
15 .word 98b, 99b; \ 10 .word 98b, __retl_one_asi;\
16 .text; \ 11 .text; \
17 .align 4; 12 .align 4;
18 13
@@ -42,7 +37,7 @@
42#define PREAMBLE \ 37#define PREAMBLE \
43 rd %asi, %g1; \ 38 rd %asi, %g1; \
44 cmp %g1, ASI_AIUS; \ 39 cmp %g1, ASI_AIUS; \
45 bne,pn %icc, memcpy_user_stub; \ 40 bne,pn %icc, ___copy_in_user; \
46 nop 41 nop
47#endif 42#endif
48 43
diff --git a/arch/sparc/lib/NGbzero.S b/arch/sparc/lib/NGbzero.S
index 814d5f7a45e1..beab29bf419b 100644
--- a/arch/sparc/lib/NGbzero.S
+++ b/arch/sparc/lib/NGbzero.S
@@ -6,13 +6,9 @@
6 6
7#define EX_ST(x,y) \ 7#define EX_ST(x,y) \
898: x,y; \ 898: x,y; \
9 .section .fixup; \
10 .align 4; \
1199: retl; \
12 mov %o1, %o0; \
13 .section __ex_table,"a";\ 9 .section __ex_table,"a";\
14 .align 4; \ 10 .align 4; \
15 .word 98b, 99b; \ 11 .word 98b, __retl_o1; \
16 .text; \ 12 .text; \
17 .align 4; 13 .align 4;
18 14
diff --git a/arch/sparc/lib/NGcopy_from_user.S b/arch/sparc/lib/NGcopy_from_user.S
index e7f433f71b42..5d1e4d1ac21e 100644
--- a/arch/sparc/lib/NGcopy_from_user.S
+++ b/arch/sparc/lib/NGcopy_from_user.S
@@ -5,14 +5,9 @@
5 5
6#define EX_LD(x) \ 6#define EX_LD(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: wr %g0, ASI_AIUS, %asi;\
11 ret; \
12 restore %g0, 1, %o0; \
13 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
14 .align 4; \ 9 .align 4; \
15 .word 98b, 99b; \ 10 .word 98b, __ret_one_asi;\
16 .text; \ 11 .text; \
17 .align 4; 12 .align 4;
18 13
@@ -30,7 +25,7 @@
30#define PREAMBLE \ 25#define PREAMBLE \
31 rd %asi, %g1; \ 26 rd %asi, %g1; \
32 cmp %g1, ASI_AIUS; \ 27 cmp %g1, ASI_AIUS; \
33 bne,pn %icc, memcpy_user_stub; \ 28 bne,pn %icc, ___copy_in_user; \
34 nop 29 nop
35#endif 30#endif
36 31
diff --git a/arch/sparc/lib/NGcopy_to_user.S b/arch/sparc/lib/NGcopy_to_user.S
index 6ea01c5532a0..ff630dcb273c 100644
--- a/arch/sparc/lib/NGcopy_to_user.S
+++ b/arch/sparc/lib/NGcopy_to_user.S
@@ -5,14 +5,9 @@
5 5
6#define EX_ST(x) \ 6#define EX_ST(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: wr %g0, ASI_AIUS, %asi;\
11 ret; \
12 restore %g0, 1, %o0; \
13 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
14 .align 4; \ 9 .align 4; \
15 .word 98b, 99b; \ 10 .word 98b, __ret_one_asi;\
16 .text; \ 11 .text; \
17 .align 4; 12 .align 4;
18 13
@@ -33,7 +28,7 @@
33#define PREAMBLE \ 28#define PREAMBLE \
34 rd %asi, %g1; \ 29 rd %asi, %g1; \
35 cmp %g1, ASI_AIUS; \ 30 cmp %g1, ASI_AIUS; \
36 bne,pn %icc, memcpy_user_stub; \ 31 bne,pn %icc, ___copy_in_user; \
37 nop 32 nop
38#endif 33#endif
39 34
diff --git a/arch/sparc/lib/U1copy_from_user.S b/arch/sparc/lib/U1copy_from_user.S
index 3192b0bf4fab..a6ae2ea04bf5 100644
--- a/arch/sparc/lib/U1copy_from_user.S
+++ b/arch/sparc/lib/U1copy_from_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_LD(x) \ 6#define EX_LD(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
@@ -27,7 +23,7 @@
27#define PREAMBLE \ 23#define PREAMBLE \
28 rd %asi, %g1; \ 24 rd %asi, %g1; \
29 cmp %g1, ASI_AIUS; \ 25 cmp %g1, ASI_AIUS; \
30 bne,pn %icc, memcpy_user_stub; \ 26 bne,pn %icc, ___copy_in_user; \
31 nop; \ 27 nop; \
32 28
33#include "U1memcpy.S" 29#include "U1memcpy.S"
diff --git a/arch/sparc/lib/U1copy_to_user.S b/arch/sparc/lib/U1copy_to_user.S
index d1210ffb0b82..f4b970eeb485 100644
--- a/arch/sparc/lib/U1copy_to_user.S
+++ b/arch/sparc/lib/U1copy_to_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_ST(x) \ 6#define EX_ST(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
@@ -27,7 +23,7 @@
27#define PREAMBLE \ 23#define PREAMBLE \
28 rd %asi, %g1; \ 24 rd %asi, %g1; \
29 cmp %g1, ASI_AIUS; \ 25 cmp %g1, ASI_AIUS; \
30 bne,pn %icc, memcpy_user_stub; \ 26 bne,pn %icc, ___copy_in_user; \
31 nop; \ 27 nop; \
32 28
33#include "U1memcpy.S" 29#include "U1memcpy.S"
diff --git a/arch/sparc/lib/U3copy_from_user.S b/arch/sparc/lib/U3copy_from_user.S
index f5bfc8d9d216..b1acd1331c33 100644
--- a/arch/sparc/lib/U3copy_from_user.S
+++ b/arch/sparc/lib/U3copy_from_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_LD(x) \ 6#define EX_LD(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
diff --git a/arch/sparc/lib/U3copy_to_user.S b/arch/sparc/lib/U3copy_to_user.S
index 2334f111bb0c..ef1e493afdfa 100644
--- a/arch/sparc/lib/U3copy_to_user.S
+++ b/arch/sparc/lib/U3copy_to_user.S
@@ -5,13 +5,9 @@
5 5
6#define EX_ST(x) \ 6#define EX_ST(x) \
798: x; \ 798: x; \
8 .section .fixup; \
9 .align 4; \
1099: retl; \
11 mov 1, %o0; \
12 .section __ex_table,"a";\ 8 .section __ex_table,"a";\
13 .align 4; \ 9 .align 4; \
14 .word 98b, 99b; \ 10 .word 98b, __retl_one; \
15 .text; \ 11 .text; \
16 .align 4; 12 .align 4;
17 13
@@ -27,7 +23,7 @@
27#define PREAMBLE \ 23#define PREAMBLE \
28 rd %asi, %g1; \ 24 rd %asi, %g1; \
29 cmp %g1, ASI_AIUS; \ 25 cmp %g1, ASI_AIUS; \
30 bne,pn %icc, memcpy_user_stub; \ 26 bne,pn %icc, ___copy_in_user; \
31 nop; \ 27 nop; \
32 28
33#include "U3memcpy.S" 29#include "U3memcpy.S"
diff --git a/arch/sparc/lib/bzero.S b/arch/sparc/lib/bzero.S
index c7bbae8c590f..b6557297440f 100644
--- a/arch/sparc/lib/bzero.S
+++ b/arch/sparc/lib/bzero.S
@@ -88,13 +88,9 @@ __bzero_done:
88 88
89#define EX_ST(x,y) \ 89#define EX_ST(x,y) \
9098: x,y; \ 9098: x,y; \
91 .section .fixup; \
92 .align 4; \
9399: retl; \
94 mov %o1, %o0; \
95 .section __ex_table,"a";\ 91 .section __ex_table,"a";\
96 .align 4; \ 92 .align 4; \
97 .word 98b, 99b; \ 93 .word 98b, __retl_o1; \
98 .text; \ 94 .text; \
99 .align 4; 95 .align 4;
100 96
diff --git a/arch/sparc/lib/copy_in_user.S b/arch/sparc/lib/copy_in_user.S
index 650af3f21f78..302c0e60dc2c 100644
--- a/arch/sparc/lib/copy_in_user.S
+++ b/arch/sparc/lib/copy_in_user.S
@@ -3,19 +3,16 @@
3 * Copyright (C) 1999, 2000, 2004 David S. Miller (davem@redhat.com) 3 * Copyright (C) 1999, 2000, 2004 David S. Miller (davem@redhat.com)
4 */ 4 */
5 5
6#include <linux/linkage.h>
6#include <asm/asi.h> 7#include <asm/asi.h>
7 8
8#define XCC xcc 9#define XCC xcc
9 10
10#define EX(x,y) \ 11#define EX(x,y) \
1198: x,y; \ 1298: x,y; \
12 .section .fixup; \
13 .align 4; \
1499: retl; \
15 mov 1, %o0; \
16 .section __ex_table,"a";\ 13 .section __ex_table,"a";\
17 .align 4; \ 14 .align 4; \
18 .word 98b, 99b; \ 15 .word 98b, __retl_one; \
19 .text; \ 16 .text; \
20 .align 4; 17 .align 4;
21 18
@@ -31,18 +28,7 @@
31 * to copy register windows around during thread cloning. 28 * to copy register windows around during thread cloning.
32 */ 29 */
33 30
34 .globl ___copy_in_user 31ENTRY(___copy_in_user) /* %o0=dst, %o1=src, %o2=len */
35 .type ___copy_in_user,#function
36___copy_in_user: /* %o0=dst, %o1=src, %o2=len */
37 /* Writing to %asi is _expensive_ so we hardcode it.
38 * Reading %asi to check for KERNEL_DS is comparatively
39 * cheap.
40 */
41 rd %asi, %g1
42 cmp %g1, ASI_AIUS
43 bne,pn %icc, memcpy_user_stub
44 nop
45
46 cmp %o2, 0 32 cmp %o2, 0
47 be,pn %XCC, 85f 33 be,pn %XCC, 85f
48 or %o0, %o1, %o3 34 or %o0, %o1, %o3
@@ -53,22 +39,24 @@ ___copy_in_user: /* %o0=dst, %o1=src, %o2=len */
53 /* 16 < len <= 64 */ 39 /* 16 < len <= 64 */
54 andcc %o3, 0x7, %g0 40 andcc %o3, 0x7, %g0
55 bne,pn %XCC, 90f 41 bne,pn %XCC, 90f
56 sub %o0, %o1, %o3 42 nop
57 43
58 andn %o2, 0x7, %o4 44 andn %o2, 0x7, %o4
59 and %o2, 0x7, %o2 45 and %o2, 0x7, %o2
601: subcc %o4, 0x8, %o4 461: subcc %o4, 0x8, %o4
61 EX(ldxa [%o1] %asi, %o5) 47 EX(ldxa [%o1] %asi, %o5)
62 EX(stxa %o5, [%o1 + %o3] ASI_AIUS) 48 EX(stxa %o5, [%o0] %asi)
49 add %o1, 0x8, %o1
63 bgu,pt %XCC, 1b 50 bgu,pt %XCC, 1b
64 add %o1, 0x8, %o1 51 add %o0, 0x8, %o0
65 andcc %o2, 0x4, %g0 52 andcc %o2, 0x4, %g0
66 be,pt %XCC, 1f 53 be,pt %XCC, 1f
67 nop 54 nop
68 sub %o2, 0x4, %o2 55 sub %o2, 0x4, %o2
69 EX(lduwa [%o1] %asi, %o5) 56 EX(lduwa [%o1] %asi, %o5)
70 EX(stwa %o5, [%o1 + %o3] ASI_AIUS) 57 EX(stwa %o5, [%o0] %asi)
71 add %o1, 0x4, %o1 58 add %o1, 0x4, %o1
59 add %o0, 0x4, %o0
721: cmp %o2, 0 601: cmp %o2, 0
73 be,pt %XCC, 85f 61 be,pt %XCC, 85f
74 nop 62 nop
@@ -78,14 +66,15 @@ ___copy_in_user: /* %o0=dst, %o1=src, %o2=len */
7880: /* 0 < len <= 16 */ 6680: /* 0 < len <= 16 */
79 andcc %o3, 0x3, %g0 67 andcc %o3, 0x3, %g0
80 bne,pn %XCC, 90f 68 bne,pn %XCC, 90f
81 sub %o0, %o1, %o3 69 nop
82 70
8382: 7182:
84 subcc %o2, 4, %o2 72 subcc %o2, 4, %o2
85 EX(lduwa [%o1] %asi, %g1) 73 EX(lduwa [%o1] %asi, %g1)
86 EX(stwa %g1, [%o1 + %o3] ASI_AIUS) 74 EX(stwa %g1, [%o0] %asi)
75 add %o1, 4, %o1
87 bgu,pt %XCC, 82b 76 bgu,pt %XCC, 82b
88 add %o1, 4, %o1 77 add %o0, 4, %o0
89 78
9085: retl 7985: retl
91 clr %o0 80 clr %o0
@@ -94,26 +83,10 @@ ___copy_in_user: /* %o0=dst, %o1=src, %o2=len */
9490: 8390:
95 subcc %o2, 1, %o2 84 subcc %o2, 1, %o2
96 EX(lduba [%o1] %asi, %g1) 85 EX(lduba [%o1] %asi, %g1)
97 EX(stba %g1, [%o1 + %o3] ASI_AIUS) 86 EX(stba %g1, [%o0] %asi)
87 add %o1, 1, %o1
98 bgu,pt %XCC, 90b 88 bgu,pt %XCC, 90b
99 add %o1, 1, %o1 89 add %o0, 1, %o0
100 retl 90 retl
101 clr %o0 91 clr %o0
102 92ENDPROC(___copy_in_user)
103 .size ___copy_in_user, .-___copy_in_user
104
105 /* Act like copy_{to,in}_user(), ie. return zero instead
106 * of original destination pointer. This is invoked when
107 * copy_{to,in}_user() finds that %asi is kernel space.
108 */
109 .globl memcpy_user_stub
110 .type memcpy_user_stub,#function
111memcpy_user_stub:
112 save %sp, -192, %sp
113 mov %i0, %o0
114 mov %i1, %o1
115 call memcpy
116 mov %i2, %o2
117 ret
118 restore %g0, %g0, %o0
119 .size memcpy_user_stub, .-memcpy_user_stub
diff --git a/arch/um/drivers/vde_user.c b/arch/um/drivers/vde_user.c
index 56533db25343..c5c43253e6ce 100644
--- a/arch/um/drivers/vde_user.c
+++ b/arch/um/drivers/vde_user.c
@@ -78,7 +78,7 @@ void vde_init_libstuff(struct vde_data *vpri, struct vde_init *init)
78{ 78{
79 struct vde_open_args *args; 79 struct vde_open_args *args;
80 80
81 vpri->args = kmalloc(sizeof(struct vde_open_args), UM_GFP_KERNEL); 81 vpri->args = uml_kmalloc(sizeof(struct vde_open_args), UM_GFP_KERNEL);
82 if (vpri->args == NULL) { 82 if (vpri->args == NULL) {
83 printk(UM_KERN_ERR "vde_init_libstuff - vde_open_args " 83 printk(UM_KERN_ERR "vde_init_libstuff - vde_open_args "
84 "allocation failed"); 84 "allocation failed");
@@ -91,8 +91,8 @@ void vde_init_libstuff(struct vde_data *vpri, struct vde_init *init)
91 args->group = init->group; 91 args->group = init->group;
92 args->mode = init->mode ? init->mode : 0700; 92 args->mode = init->mode ? init->mode : 0700;
93 93
94 args->port ? printk(UM_KERN_INFO "port %d", args->port) : 94 args->port ? printk("port %d", args->port) :
95 printk(UM_KERN_INFO "undefined port"); 95 printk("undefined port");
96} 96}
97 97
98int vde_user_read(void *conn, void *buf, int len) 98int vde_user_read(void *conn, void *buf, int len)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 73f7fe8fd4d1..bc2fbadff9f9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1802,6 +1802,17 @@ config DMAR
1802 and include PCI device scope covered by these DMA 1802 and include PCI device scope covered by these DMA
1803 remapping devices. 1803 remapping devices.
1804 1804
1805config DMAR_DEFAULT_ON
1806 def_bool y
1807 prompt "Enable DMA Remapping Devices by default"
1808 depends on DMAR
1809 help
1810 Selecting this option will enable a DMAR device at boot time if
1811 one is found. If this option is not selected, DMAR support can
1812 be enabled by passing intel_iommu=on to the kernel. It is
1813 recommended you say N here while the DMAR code remains
1814 experimental.
1815
1805config DMAR_GFX_WA 1816config DMAR_GFX_WA
1806 def_bool y 1817 def_bool y
1807 prompt "Support for Graphics workaround" 1818 prompt "Support for Graphics workaround"
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8078955845ae..c98d52e82966 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -167,9 +167,9 @@ config MK7
167config MK8 167config MK8
168 bool "Opteron/Athlon64/Hammer/K8" 168 bool "Opteron/Athlon64/Hammer/K8"
169 help 169 help
170 Select this for an AMD Opteron or Athlon64 Hammer-family processor. Enables 170 Select this for an AMD Opteron or Athlon64 Hammer-family processor.
171 use of some extended instructions, and passes appropriate optimization 171 Enables use of some extended instructions, and passes appropriate
172 flags to GCC. 172 optimization flags to GCC.
173 173
174config MCRUSOE 174config MCRUSOE
175 bool "Crusoe" 175 bool "Crusoe"
@@ -256,9 +256,11 @@ config MPSC
256config MCORE2 256config MCORE2
257 bool "Core 2/newer Xeon" 257 bool "Core 2/newer Xeon"
258 help 258 help
259 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and 53xx) 259
260 CPUs. You can distinguish newer from older Xeons by the CPU family 260 Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
261 in /proc/cpuinfo. Newer ones have 6 and older ones 15 (not a typo) 261 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
262 family in /proc/cpuinfo. Newer ones have 6 and older ones 15
263 (not a typo)
262 264
263config GENERIC_CPU 265config GENERIC_CPU
264 bool "Generic-x86-64" 266 bool "Generic-x86-64"
@@ -320,14 +322,14 @@ config X86_PPRO_FENCE
320 bool "PentiumPro memory ordering errata workaround" 322 bool "PentiumPro memory ordering errata workaround"
321 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1 323 depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
322 help 324 help
323 Old PentiumPro multiprocessor systems had errata that could cause memory 325 Old PentiumPro multiprocessor systems had errata that could cause
324 operations to violate the x86 ordering standard in rare cases. Enabling this 326 memory operations to violate the x86 ordering standard in rare cases.
325 option will attempt to work around some (but not all) occurances of 327 Enabling this option will attempt to work around some (but not all)
326 this problem, at the cost of much heavier spinlock and memory barrier 328 occurances of this problem, at the cost of much heavier spinlock and
327 operations. 329 memory barrier operations.
328 330
329 If unsure, say n here. Even distro kernels should think twice before enabling 331 If unsure, say n here. Even distro kernels should think twice before
330 this: there are few systems, and an unlikely bug. 332 enabling this: there are few systems, and an unlikely bug.
331 333
332config X86_F00F_BUG 334config X86_F00F_BUG
333 def_bool y 335 def_bool y
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 10d6cc3fd052..e1983fa025d2 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -174,28 +174,8 @@ config IOMMU_LEAK
174 Add a simple leak tracer to the IOMMU code. This is useful when you 174 Add a simple leak tracer to the IOMMU code. This is useful when you
175 are debugging a buggy device driver that leaks IOMMU mappings. 175 are debugging a buggy device driver that leaks IOMMU mappings.
176 176
177config MMIOTRACE 177config HAVE_MMIOTRACE_SUPPORT
178 bool "Memory mapped IO tracing" 178 def_bool y
179 depends on DEBUG_KERNEL && PCI
180 select TRACING
181 help
182 Mmiotrace traces Memory Mapped I/O access and is meant for
183 debugging and reverse engineering. It is called from the ioremap
184 implementation and works via page faults. Tracing is disabled by
185 default and can be enabled at run-time.
186
187 See Documentation/tracers/mmiotrace.txt.
188 If you are not helping to develop drivers, say N.
189
190config MMIOTRACE_TEST
191 tristate "Test module for mmiotrace"
192 depends on MMIOTRACE && m
193 help
194 This is a dumb module for testing mmiotrace. It is very dangerous
195 as it will write garbage to IO memory starting at a given address.
196 However, it should be safe to use on e.g. unused portion of VRAM.
197
198 Say N, unless you absolutely know what you are doing.
199 179
200# 180#
201# IO delay types: 181# IO delay types:
diff --git a/arch/x86/include/asm/a.out-core.h b/arch/x86/include/asm/a.out-core.h
index 37822206083e..3c601f8224be 100644
--- a/arch/x86/include/asm/a.out-core.h
+++ b/arch/x86/include/asm/a.out-core.h
@@ -23,8 +23,6 @@
23 */ 23 */
24static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump) 24static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
25{ 25{
26 u16 gs;
27
28/* changed the size calculations - should hopefully work better. lbt */ 26/* changed the size calculations - should hopefully work better. lbt */
29 dump->magic = CMAGIC; 27 dump->magic = CMAGIC;
30 dump->start_code = 0; 28 dump->start_code = 0;
@@ -57,7 +55,7 @@ static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
57 dump->regs.ds = (u16)regs->ds; 55 dump->regs.ds = (u16)regs->ds;
58 dump->regs.es = (u16)regs->es; 56 dump->regs.es = (u16)regs->es;
59 dump->regs.fs = (u16)regs->fs; 57 dump->regs.fs = (u16)regs->fs;
60 savesegment(gs, gs); 58 savesegment(gs, dump->regs.gs);
61 dump->regs.orig_ax = regs->orig_ax; 59 dump->regs.orig_ax = regs->orig_ax;
62 dump->regs.ip = regs->ip; 60 dump->regs.ip = regs->ip;
63 dump->regs.cs = (u16)regs->cs; 61 dump->regs.cs = (u16)regs->cs;
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index ea408dcba513..7301e60dc4a8 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -93,6 +93,7 @@
93#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */ 93#define X86_FEATURE_XTOPOLOGY (3*32+22) /* cpu topology enum extensions */
94#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */ 94#define X86_FEATURE_TSC_RELIABLE (3*32+23) /* TSC is known to be reliable */
95#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */ 95#define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
96#define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
96 97
97/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ 98/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
98#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */ 99#define X86_FEATURE_XMM3 (4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h
index ca5ffb2856b6..edc90f23e708 100644
--- a/arch/x86/include/asm/efi.h
+++ b/arch/x86/include/asm/efi.h
@@ -37,8 +37,6 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...);
37 37
38#else /* !CONFIG_X86_32 */ 38#else /* !CONFIG_X86_32 */
39 39
40#define MAX_EFI_IO_PAGES 100
41
42extern u64 efi_call0(void *fp); 40extern u64 efi_call0(void *fp);
43extern u64 efi_call1(void *fp, u64 arg1); 41extern u64 efi_call1(void *fp, u64 arg1);
44extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); 42extern u64 efi_call2(void *fp, u64 arg1, u64 arg2);
diff --git a/arch/x86/include/asm/fixmap_64.h b/arch/x86/include/asm/fixmap_64.h
index 00a30ab9b1a5..8be740977db8 100644
--- a/arch/x86/include/asm/fixmap_64.h
+++ b/arch/x86/include/asm/fixmap_64.h
@@ -16,7 +16,6 @@
16#include <asm/apicdef.h> 16#include <asm/apicdef.h>
17#include <asm/page.h> 17#include <asm/page.h>
18#include <asm/vsyscall.h> 18#include <asm/vsyscall.h>
19#include <asm/efi.h>
20 19
21/* 20/*
22 * Here we define all the compile-time 'special' virtual 21 * Here we define all the compile-time 'special' virtual
@@ -43,9 +42,6 @@ enum fixed_addresses {
43 FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ 42 FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */
44 FIX_IO_APIC_BASE_0, 43 FIX_IO_APIC_BASE_0,
45 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, 44 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
46 FIX_EFI_IO_MAP_LAST_PAGE,
47 FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE
48 + MAX_EFI_IO_PAGES - 1,
49#ifdef CONFIG_PARAVIRT 45#ifdef CONFIG_PARAVIRT
50 FIX_PARAVIRT_BOOTMAP, 46 FIX_PARAVIRT_BOOTMAP,
51#endif 47#endif
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 48f0004db8c9..71c9e5183982 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -172,7 +172,13 @@ static inline void __save_init_fpu(struct task_struct *tsk)
172 172
173#else /* CONFIG_X86_32 */ 173#else /* CONFIG_X86_32 */
174 174
175extern void finit(void); 175#ifdef CONFIG_MATH_EMULATION
176extern void finit_task(struct task_struct *tsk);
177#else
178static inline void finit_task(struct task_struct *tsk)
179{
180}
181#endif
176 182
177static inline void tolerant_fwait(void) 183static inline void tolerant_fwait(void)
178{ 184{
diff --git a/arch/x86/include/asm/iomap.h b/arch/x86/include/asm/iomap.h
index c1f06289b14b..86af26091d6c 100644
--- a/arch/x86/include/asm/iomap.h
+++ b/arch/x86/include/asm/iomap.h
@@ -23,6 +23,9 @@
23#include <asm/pgtable.h> 23#include <asm/pgtable.h>
24#include <asm/tlbflush.h> 24#include <asm/tlbflush.h>
25 25
26int
27is_io_mapping_possible(resource_size_t base, unsigned long size);
28
26void * 29void *
27iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot); 30iomap_atomic_prot_pfn(unsigned long pfn, enum km_type type, pgprot_t prot);
28 31
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h
index d2e3bf3608af..886c9402ec45 100644
--- a/arch/x86/include/asm/kvm.h
+++ b/arch/x86/include/asm/kvm.h
@@ -9,6 +9,13 @@
9#include <linux/types.h> 9#include <linux/types.h>
10#include <linux/ioctl.h> 10#include <linux/ioctl.h>
11 11
12/* Select x86 specific features in <linux/kvm.h> */
13#define __KVM_HAVE_PIT
14#define __KVM_HAVE_IOAPIC
15#define __KVM_HAVE_DEVICE_ASSIGNMENT
16#define __KVM_HAVE_MSI
17#define __KVM_HAVE_USER_NMI
18
12/* Architectural interrupt line count. */ 19/* Architectural interrupt line count. */
13#define KVM_NR_INTERRUPTS 256 20#define KVM_NR_INTERRUPTS 256
14 21
diff --git a/arch/x86/include/asm/math_emu.h b/arch/x86/include/asm/math_emu.h
index 5a65b107ad58..031f6266f425 100644
--- a/arch/x86/include/asm/math_emu.h
+++ b/arch/x86/include/asm/math_emu.h
@@ -1,31 +1,18 @@
1#ifndef _ASM_X86_MATH_EMU_H 1#ifndef _ASM_X86_MATH_EMU_H
2#define _ASM_X86_MATH_EMU_H 2#define _ASM_X86_MATH_EMU_H
3 3
4#include <asm/ptrace.h>
5#include <asm/vm86.h>
6
4/* This structure matches the layout of the data saved to the stack 7/* This structure matches the layout of the data saved to the stack
5 following a device-not-present interrupt, part of it saved 8 following a device-not-present interrupt, part of it saved
6 automatically by the 80386/80486. 9 automatically by the 80386/80486.
7 */ 10 */
8struct info { 11struct math_emu_info {
9 long ___orig_eip; 12 long ___orig_eip;
10 long ___ebx; 13 union {
11 long ___ecx; 14 struct pt_regs *regs;
12 long ___edx; 15 struct kernel_vm86_regs *vm86;
13 long ___esi; 16 };
14 long ___edi;
15 long ___ebp;
16 long ___eax;
17 long ___ds;
18 long ___es;
19 long ___fs;
20 long ___orig_eax;
21 long ___eip;
22 long ___cs;
23 long ___eflags;
24 long ___esp;
25 long ___ss;
26 long ___vm86_es; /* This and the following only in vm86 mode */
27 long ___vm86_ds;
28 long ___vm86_fs;
29 long ___vm86_gs;
30}; 17};
31#endif /* _ASM_X86_MATH_EMU_H */ 18#endif /* _ASM_X86_MATH_EMU_H */
diff --git a/arch/x86/include/asm/mmzone_32.h b/arch/x86/include/asm/mmzone_32.h
index 07f1af494ca5..105fb90a0635 100644
--- a/arch/x86/include/asm/mmzone_32.h
+++ b/arch/x86/include/asm/mmzone_32.h
@@ -32,8 +32,6 @@ static inline void get_memcfg_numa(void)
32 get_memcfg_numa_flat(); 32 get_memcfg_numa_flat();
33} 33}
34 34
35extern int early_pfn_to_nid(unsigned long pfn);
36
37extern void resume_map_numa_kva(pgd_t *pgd); 35extern void resume_map_numa_kva(pgd_t *pgd);
38 36
39#else /* !CONFIG_NUMA */ 37#else /* !CONFIG_NUMA */
diff --git a/arch/x86/include/asm/mmzone_64.h b/arch/x86/include/asm/mmzone_64.h
index a5b3817d4b9e..a29f48c2a322 100644
--- a/arch/x86/include/asm/mmzone_64.h
+++ b/arch/x86/include/asm/mmzone_64.h
@@ -40,8 +40,6 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
40#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \ 40#define node_end_pfn(nid) (NODE_DATA(nid)->node_start_pfn + \
41 NODE_DATA(nid)->node_spanned_pages) 41 NODE_DATA(nid)->node_spanned_pages)
42 42
43extern int early_pfn_to_nid(unsigned long pfn);
44
45#ifdef CONFIG_NUMA_EMU 43#ifdef CONFIG_NUMA_EMU
46#define FAKE_NODE_MIN_SIZE (64 * 1024 * 1024) 44#define FAKE_NODE_MIN_SIZE (64 * 1024 * 1024)
47#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL)) 45#define FAKE_NODE_MIN_HASH_MASK (~(FAKE_NODE_MIN_SIZE - 1UL))
diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h
index 62d14ce3cd00..bd22f2a3713f 100644
--- a/arch/x86/include/asm/mpspec.h
+++ b/arch/x86/include/asm/mpspec.h
@@ -60,6 +60,7 @@ extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
60 u32 gsi); 60 u32 gsi);
61extern void mp_config_acpi_legacy_irqs(void); 61extern void mp_config_acpi_legacy_irqs(void);
62extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); 62extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
63extern int acpi_probe_gsi(void);
63#ifdef CONFIG_X86_IO_APIC 64#ifdef CONFIG_X86_IO_APIC
64extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin, 65extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
65 u32 gsi, int triggering, int polarity); 66 u32 gsi, int triggering, int polarity);
@@ -71,6 +72,11 @@ mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
71 return 0; 72 return 0;
72} 73}
73#endif 74#endif
75#else /* !CONFIG_ACPI: */
76static inline int acpi_probe_gsi(void)
77{
78 return 0;
79}
74#endif /* CONFIG_ACPI */ 80#endif /* CONFIG_ACPI */
75 81
76#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 82#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
diff --git a/arch/x86/include/asm/page.h b/arch/x86/include/asm/page.h
index e9873a2e8695..776579119a00 100644
--- a/arch/x86/include/asm/page.h
+++ b/arch/x86/include/asm/page.h
@@ -57,7 +57,6 @@ typedef struct { pgdval_t pgd; } pgd_t;
57typedef struct { pgprotval_t pgprot; } pgprot_t; 57typedef struct { pgprotval_t pgprot; } pgprot_t;
58 58
59extern int page_is_ram(unsigned long pagenr); 59extern int page_is_ram(unsigned long pagenr);
60extern int pagerange_is_ram(unsigned long start, unsigned long end);
61extern int devmem_is_allowed(unsigned long pagenr); 60extern int devmem_is_allowed(unsigned long pagenr);
62extern void map_devmem(unsigned long pfn, unsigned long size, 61extern void map_devmem(unsigned long pfn, unsigned long size,
63 pgprot_t vma_prot); 62 pgprot_t vma_prot);
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index ba3e2ff6aedc..e299287e8e33 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -1352,14 +1352,7 @@ static inline void arch_leave_lazy_cpu_mode(void)
1352 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave); 1352 PVOP_VCALL0(pv_cpu_ops.lazy_mode.leave);
1353} 1353}
1354 1354
1355static inline void arch_flush_lazy_cpu_mode(void) 1355void arch_flush_lazy_cpu_mode(void);
1356{
1357 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU)) {
1358 arch_leave_lazy_cpu_mode();
1359 arch_enter_lazy_cpu_mode();
1360 }
1361}
1362
1363 1356
1364#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE 1357#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
1365static inline void arch_enter_lazy_mmu_mode(void) 1358static inline void arch_enter_lazy_mmu_mode(void)
@@ -1372,13 +1365,7 @@ static inline void arch_leave_lazy_mmu_mode(void)
1372 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave); 1365 PVOP_VCALL0(pv_mmu_ops.lazy_mode.leave);
1373} 1366}
1374 1367
1375static inline void arch_flush_lazy_mmu_mode(void) 1368void arch_flush_lazy_mmu_mode(void);
1376{
1377 if (unlikely(paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU)) {
1378 arch_leave_lazy_mmu_mode();
1379 arch_enter_lazy_mmu_mode();
1380 }
1381}
1382 1369
1383static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, 1370static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
1384 unsigned long phys, pgprot_t flags) 1371 unsigned long phys, pgprot_t flags)
@@ -1402,6 +1389,7 @@ static inline int __raw_spin_is_contended(struct raw_spinlock *lock)
1402{ 1389{
1403 return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock); 1390 return PVOP_CALL1(int, pv_lock_ops.spin_is_contended, lock);
1404} 1391}
1392#define __raw_spin_is_contended __raw_spin_is_contended
1405 1393
1406static __always_inline void __raw_spin_lock(struct raw_spinlock *lock) 1394static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
1407{ 1395{
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 06bbcbd66e9c..4f5af8447d54 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -302,16 +302,30 @@ static inline pte_t pte_mkspecial(pte_t pte)
302 302
303extern pteval_t __supported_pte_mask; 303extern pteval_t __supported_pte_mask;
304 304
305/*
306 * Mask out unsupported bits in a present pgprot. Non-present pgprots
307 * can use those bits for other purposes, so leave them be.
308 */
309static inline pgprotval_t massage_pgprot(pgprot_t pgprot)
310{
311 pgprotval_t protval = pgprot_val(pgprot);
312
313 if (protval & _PAGE_PRESENT)
314 protval &= __supported_pte_mask;
315
316 return protval;
317}
318
305static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot) 319static inline pte_t pfn_pte(unsigned long page_nr, pgprot_t pgprot)
306{ 320{
307 return __pte((((phys_addr_t)page_nr << PAGE_SHIFT) | 321 return __pte(((phys_addr_t)page_nr << PAGE_SHIFT) |
308 pgprot_val(pgprot)) & __supported_pte_mask); 322 massage_pgprot(pgprot));
309} 323}
310 324
311static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) 325static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
312{ 326{
313 return __pmd((((phys_addr_t)page_nr << PAGE_SHIFT) | 327 return __pmd(((phys_addr_t)page_nr << PAGE_SHIFT) |
314 pgprot_val(pgprot)) & __supported_pte_mask); 328 massage_pgprot(pgprot));
315} 329}
316 330
317static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 331static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
@@ -323,7 +337,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
323 * the newprot (if present): 337 * the newprot (if present):
324 */ 338 */
325 val &= _PAGE_CHG_MASK; 339 val &= _PAGE_CHG_MASK;
326 val |= pgprot_val(newprot) & (~_PAGE_CHG_MASK) & __supported_pte_mask; 340 val |= massage_pgprot(newprot) & ~_PAGE_CHG_MASK;
327 341
328 return __pte(val); 342 return __pte(val);
329} 343}
@@ -339,7 +353,7 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
339 353
340#define pte_pgprot(x) __pgprot(pte_flags(x) & PTE_FLAGS_MASK) 354#define pte_pgprot(x) __pgprot(pte_flags(x) & PTE_FLAGS_MASK)
341 355
342#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) 356#define canon_pgprot(p) __pgprot(massage_pgprot(p))
343 357
344static inline int is_new_memtype_allowed(unsigned long flags, 358static inline int is_new_memtype_allowed(unsigned long flags,
345 unsigned long new_flags) 359 unsigned long new_flags)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 091cd8855f2e..3bfd5235a9eb 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -353,7 +353,7 @@ struct i387_soft_struct {
353 u8 no_update; 353 u8 no_update;
354 u8 rm; 354 u8 rm;
355 u8 alimit; 355 u8 alimit;
356 struct info *info; 356 struct math_emu_info *info;
357 u32 entry_eip; 357 u32 entry_eip;
358}; 358};
359 359
diff --git a/arch/x86/include/asm/seccomp_32.h b/arch/x86/include/asm/seccomp_32.h
index a6ad87b352c4..b811d6f5780c 100644
--- a/arch/x86/include/asm/seccomp_32.h
+++ b/arch/x86/include/asm/seccomp_32.h
@@ -1,12 +1,6 @@
1#ifndef _ASM_X86_SECCOMP_32_H 1#ifndef _ASM_X86_SECCOMP_32_H
2#define _ASM_X86_SECCOMP_32_H 2#define _ASM_X86_SECCOMP_32_H
3 3
4#include <linux/thread_info.h>
5
6#ifdef TIF_32BIT
7#error "unexpected TIF_32BIT on i386"
8#endif
9
10#include <linux/unistd.h> 4#include <linux/unistd.h>
11 5
12#define __NR_seccomp_read __NR_read 6#define __NR_seccomp_read __NR_read
diff --git a/arch/x86/include/asm/seccomp_64.h b/arch/x86/include/asm/seccomp_64.h
index 4171bb794e9e..84ec1bd161a5 100644
--- a/arch/x86/include/asm/seccomp_64.h
+++ b/arch/x86/include/asm/seccomp_64.h
@@ -1,14 +1,6 @@
1#ifndef _ASM_X86_SECCOMP_64_H 1#ifndef _ASM_X86_SECCOMP_64_H
2#define _ASM_X86_SECCOMP_64_H 2#define _ASM_X86_SECCOMP_64_H
3 3
4#include <linux/thread_info.h>
5
6#ifdef TIF_32BIT
7#error "unexpected TIF_32BIT on x86_64"
8#else
9#define TIF_32BIT TIF_IA32
10#endif
11
12#include <linux/unistd.h> 4#include <linux/unistd.h>
13#include <asm/ia32_unistd.h> 5#include <asm/ia32_unistd.h>
14 6
diff --git a/arch/x86/include/asm/spinlock.h b/arch/x86/include/asm/spinlock.h
index d17c91981da2..8247e94ac6b1 100644
--- a/arch/x86/include/asm/spinlock.h
+++ b/arch/x86/include/asm/spinlock.h
@@ -245,6 +245,7 @@ static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
245{ 245{
246 return __ticket_spin_is_contended(lock); 246 return __ticket_spin_is_contended(lock);
247} 247}
248#define __raw_spin_is_contended __raw_spin_is_contended
248 249
249static __always_inline void __raw_spin_lock(raw_spinlock_t *lock) 250static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
250{ 251{
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index 2ee0a3bceedf..cf3bb053da0b 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -41,7 +41,7 @@ dotraplinkage void do_int3(struct pt_regs *, long);
41dotraplinkage void do_overflow(struct pt_regs *, long); 41dotraplinkage void do_overflow(struct pt_regs *, long);
42dotraplinkage void do_bounds(struct pt_regs *, long); 42dotraplinkage void do_bounds(struct pt_regs *, long);
43dotraplinkage void do_invalid_op(struct pt_regs *, long); 43dotraplinkage void do_invalid_op(struct pt_regs *, long);
44dotraplinkage void do_device_not_available(struct pt_regs *, long); 44dotraplinkage void do_device_not_available(struct pt_regs);
45dotraplinkage void do_coprocessor_segment_overrun(struct pt_regs *, long); 45dotraplinkage void do_coprocessor_segment_overrun(struct pt_regs *, long);
46dotraplinkage void do_invalid_TSS(struct pt_regs *, long); 46dotraplinkage void do_invalid_TSS(struct pt_regs *, long);
47dotraplinkage void do_segment_not_present(struct pt_regs *, long); 47dotraplinkage void do_segment_not_present(struct pt_regs *, long);
@@ -77,7 +77,7 @@ extern int panic_on_unrecovered_nmi;
77extern int kstack_depth_to_print; 77extern int kstack_depth_to_print;
78 78
79void math_error(void __user *); 79void math_error(void __user *);
80asmlinkage void math_emulate(long); 80void math_emulate(struct math_emu_info *);
81#ifdef CONFIG_X86_32 81#ifdef CONFIG_X86_32
82unsigned long patch_espfix_desc(unsigned long, unsigned long); 82unsigned long patch_espfix_desc(unsigned long, unsigned long);
83#else 83#else
diff --git a/arch/x86/include/asm/xen/page.h b/arch/x86/include/asm/xen/page.h
index 7ef617ef1df3..4bd990ee43df 100644
--- a/arch/x86/include/asm/xen/page.h
+++ b/arch/x86/include/asm/xen/page.h
@@ -137,7 +137,7 @@ static inline pte_t mfn_pte(unsigned long page_nr, pgprot_t pgprot)
137 pte_t pte; 137 pte_t pte;
138 138
139 pte.pte = ((phys_addr_t)page_nr << PAGE_SHIFT) | 139 pte.pte = ((phys_addr_t)page_nr << PAGE_SHIFT) |
140 (pgprot_val(pgprot) & __supported_pte_mask); 140 massage_pgprot(pgprot);
141 141
142 return pte; 142 return pte;
143} 143}
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index d37593c2f438..7678f10c4568 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -973,6 +973,29 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
973 nr_ioapics++; 973 nr_ioapics++;
974} 974}
975 975
976int __init acpi_probe_gsi(void)
977{
978 int idx;
979 int gsi;
980 int max_gsi = 0;
981
982 if (acpi_disabled)
983 return 0;
984
985 if (!acpi_ioapic)
986 return 0;
987
988 max_gsi = 0;
989 for (idx = 0; idx < nr_ioapics; idx++) {
990 gsi = mp_ioapic_routing[idx].gsi_end;
991
992 if (gsi > max_gsi)
993 max_gsi = gsi;
994 }
995
996 return max_gsi + 1;
997}
998
976static void assign_to_mp_irq(struct mp_config_intsrc *m, 999static void assign_to_mp_irq(struct mp_config_intsrc *m,
977 struct mp_config_intsrc *mp_irq) 1000 struct mp_config_intsrc *mp_irq)
978{ 1001{
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 707c1f6f95fa..a60c1f3bcb87 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -156,11 +156,11 @@ static int __init acpi_sleep_setup(char *str)
156#ifdef CONFIG_HIBERNATION 156#ifdef CONFIG_HIBERNATION
157 if (strncmp(str, "s4_nohwsig", 10) == 0) 157 if (strncmp(str, "s4_nohwsig", 10) == 0)
158 acpi_no_s4_hw_signature(); 158 acpi_no_s4_hw_signature();
159 if (strncmp(str, "s4_nonvs", 8) == 0)
160 acpi_s4_no_nvs();
159#endif 161#endif
160 if (strncmp(str, "old_ordering", 12) == 0) 162 if (strncmp(str, "old_ordering", 12) == 0)
161 acpi_old_suspend_ordering(); 163 acpi_old_suspend_ordering();
162 if (strncmp(str, "s4_nonvs", 8) == 0)
163 acpi_s4_no_nvs();
164 str = strchr(str, ','); 164 str = strchr(str, ',');
165 if (str != NULL) 165 if (str != NULL)
166 str += strspn(str, ", \t"); 166 str += strspn(str, ", \t");
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index bcc293423a70..96258d9dc974 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -13,7 +13,6 @@
13 * Hooray, we are in Long 64-bit mode (but still running in low memory) 13 * Hooray, we are in Long 64-bit mode (but still running in low memory)
14 */ 14 */
15ENTRY(wakeup_long64) 15ENTRY(wakeup_long64)
16wakeup_long64:
17 movq saved_magic, %rax 16 movq saved_magic, %rax
18 movq $0x123456789abcdef0, %rdx 17 movq $0x123456789abcdef0, %rdx
19 cmpq %rdx, %rax 18 cmpq %rdx, %rax
@@ -34,16 +33,12 @@ wakeup_long64:
34 33
35 movq saved_rip, %rax 34 movq saved_rip, %rax
36 jmp *%rax 35 jmp *%rax
36ENDPROC(wakeup_long64)
37 37
38bogus_64_magic: 38bogus_64_magic:
39 jmp bogus_64_magic 39 jmp bogus_64_magic
40 40
41 .align 2 41ENTRY(do_suspend_lowlevel)
42 .p2align 4,,15
43.globl do_suspend_lowlevel
44 .type do_suspend_lowlevel,@function
45do_suspend_lowlevel:
46.LFB5:
47 subq $8, %rsp 42 subq $8, %rsp
48 xorl %eax, %eax 43 xorl %eax, %eax
49 call save_processor_state 44 call save_processor_state
@@ -67,7 +62,7 @@ do_suspend_lowlevel:
67 pushfq 62 pushfq
68 popq pt_regs_flags(%rax) 63 popq pt_regs_flags(%rax)
69 64
70 movq $.L97, saved_rip(%rip) 65 movq $resume_point, saved_rip(%rip)
71 66
72 movq %rsp, saved_rsp 67 movq %rsp, saved_rsp
73 movq %rbp, saved_rbp 68 movq %rbp, saved_rbp
@@ -78,14 +73,12 @@ do_suspend_lowlevel:
78 addq $8, %rsp 73 addq $8, %rsp
79 movl $3, %edi 74 movl $3, %edi
80 xorl %eax, %eax 75 xorl %eax, %eax
81 jmp acpi_enter_sleep_state 76 call acpi_enter_sleep_state
82.L97: 77 /* in case something went wrong, restore the machine status and go on */
83 .p2align 4,,7 78 jmp resume_point
84.L99:
85 .align 4
86 movl $24, %eax
87 movw %ax, %ds
88 79
80 .align 4
81resume_point:
89 /* We don't restore %rax, it must be 0 anyway */ 82 /* We don't restore %rax, it must be 0 anyway */
90 movq $saved_context, %rax 83 movq $saved_context, %rax
91 movq saved_context_cr4(%rax), %rbx 84 movq saved_context_cr4(%rax), %rbx
@@ -117,12 +110,9 @@ do_suspend_lowlevel:
117 xorl %eax, %eax 110 xorl %eax, %eax
118 addq $8, %rsp 111 addq $8, %rsp
119 jmp restore_processor_state 112 jmp restore_processor_state
120.LFE5: 113ENDPROC(do_suspend_lowlevel)
121.Lfe5: 114
122 .size do_suspend_lowlevel, .Lfe5-do_suspend_lowlevel
123
124.data 115.data
125ALIGN
126ENTRY(saved_rbp) .quad 0 116ENTRY(saved_rbp) .quad 0
127ENTRY(saved_rsi) .quad 0 117ENTRY(saved_rsi) .quad 0
128ENTRY(saved_rdi) .quad 0 118ENTRY(saved_rdi) .quad 0
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index 115449f869ee..570f36e44e59 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -862,7 +862,7 @@ void clear_local_APIC(void)
862 } 862 }
863 863
864 /* lets not touch this if we didn't frob it */ 864 /* lets not touch this if we didn't frob it */
865#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL) 865#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
866 if (maxlvt >= 5) { 866 if (maxlvt >= 5) {
867 v = apic_read(APIC_LVTTHMR); 867 v = apic_read(APIC_LVTTHMR);
868 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 868 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 98807bb095ad..266ec6c18b6c 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -1192,6 +1192,7 @@ static int suspend(int vetoable)
1192 device_suspend(PMSG_SUSPEND); 1192 device_suspend(PMSG_SUSPEND);
1193 local_irq_disable(); 1193 local_irq_disable();
1194 device_power_down(PMSG_SUSPEND); 1194 device_power_down(PMSG_SUSPEND);
1195 sysdev_suspend(PMSG_SUSPEND);
1195 1196
1196 local_irq_enable(); 1197 local_irq_enable();
1197 1198
@@ -1208,6 +1209,7 @@ static int suspend(int vetoable)
1208 if (err != APM_SUCCESS) 1209 if (err != APM_SUCCESS)
1209 apm_error("suspend", err); 1210 apm_error("suspend", err);
1210 err = (err == APM_SUCCESS) ? 0 : -EIO; 1211 err = (err == APM_SUCCESS) ? 0 : -EIO;
1212 sysdev_resume();
1211 device_power_up(PMSG_RESUME); 1213 device_power_up(PMSG_RESUME);
1212 local_irq_enable(); 1214 local_irq_enable();
1213 device_resume(PMSG_RESUME); 1215 device_resume(PMSG_RESUME);
@@ -1228,6 +1230,7 @@ static void standby(void)
1228 1230
1229 local_irq_disable(); 1231 local_irq_disable();
1230 device_power_down(PMSG_SUSPEND); 1232 device_power_down(PMSG_SUSPEND);
1233 sysdev_suspend(PMSG_SUSPEND);
1231 local_irq_enable(); 1234 local_irq_enable();
1232 1235
1233 err = set_system_power_state(APM_STATE_STANDBY); 1236 err = set_system_power_state(APM_STATE_STANDBY);
@@ -1235,6 +1238,7 @@ static void standby(void)
1235 apm_error("standby", err); 1238 apm_error("standby", err);
1236 1239
1237 local_irq_disable(); 1240 local_irq_disable();
1241 sysdev_resume();
1238 device_power_up(PMSG_RESUME); 1242 device_power_up(PMSG_RESUME);
1239 local_irq_enable(); 1243 local_irq_enable();
1240} 1244}
diff --git a/arch/x86/kernel/cpu/cpufreq/Kconfig b/arch/x86/kernel/cpu/cpufreq/Kconfig
index efae3b22a0ff..65792c2cc462 100644
--- a/arch/x86/kernel/cpu/cpufreq/Kconfig
+++ b/arch/x86/kernel/cpu/cpufreq/Kconfig
@@ -245,17 +245,6 @@ config X86_E_POWERSAVER
245 245
246comment "shared options" 246comment "shared options"
247 247
248config X86_ACPI_CPUFREQ_PROC_INTF
249 bool "/proc/acpi/processor/../performance interface (deprecated)"
250 depends on PROC_FS
251 depends on X86_ACPI_CPUFREQ || X86_POWERNOW_K7_ACPI || X86_POWERNOW_K8_ACPI
252 help
253 This enables the deprecated /proc/acpi/processor/../performance
254 interface. While it is helpful for debugging, the generic,
255 cross-architecture cpufreq interfaces should be used.
256
257 If in doubt, say N.
258
259config X86_SPEEDSTEP_LIB 248config X86_SPEEDSTEP_LIB
260 tristate 249 tristate
261 default (X86_SPEEDSTEP_ICH || X86_SPEEDSTEP_SMI || X86_P4_CLOCKMOD) 250 default (X86_SPEEDSTEP_ICH || X86_SPEEDSTEP_SMI || X86_P4_CLOCKMOD)
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
index b585e04cbc9e..3178c3acd97e 100644
--- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
+++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c
@@ -277,7 +277,6 @@ static struct cpufreq_driver p4clockmod_driver = {
277 .name = "p4-clockmod", 277 .name = "p4-clockmod",
278 .owner = THIS_MODULE, 278 .owner = THIS_MODULE,
279 .attr = p4clockmod_attr, 279 .attr = p4clockmod_attr,
280 .hide_interface = 1,
281}; 280};
282 281
283 282
diff --git a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
index 5c28b37dea11..6428aa17b40e 100644
--- a/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
+++ b/arch/x86/kernel/cpu/cpufreq/powernow-k8.c
@@ -939,10 +939,25 @@ static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data)
939 free_cpumask_var(data->acpi_data.shared_cpu_map); 939 free_cpumask_var(data->acpi_data.shared_cpu_map);
940} 940}
941 941
942static int get_transition_latency(struct powernow_k8_data *data)
943{
944 int max_latency = 0;
945 int i;
946 for (i = 0; i < data->acpi_data.state_count; i++) {
947 int cur_latency = data->acpi_data.states[i].transition_latency
948 + data->acpi_data.states[i].bus_master_latency;
949 if (cur_latency > max_latency)
950 max_latency = cur_latency;
951 }
952 /* value in usecs, needs to be in nanoseconds */
953 return 1000 * max_latency;
954}
955
942#else 956#else
943static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) { return -ENODEV; } 957static int powernow_k8_cpu_init_acpi(struct powernow_k8_data *data) { return -ENODEV; }
944static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) { return; } 958static void powernow_k8_cpu_exit_acpi(struct powernow_k8_data *data) { return; }
945static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) { return; } 959static void powernow_k8_acpi_pst_values(struct powernow_k8_data *data, unsigned int index) { return; }
960static int get_transition_latency(struct powernow_k8_data *data) { return 0; }
946#endif /* CONFIG_X86_POWERNOW_K8_ACPI */ 961#endif /* CONFIG_X86_POWERNOW_K8_ACPI */
947 962
948/* Take a frequency, and issue the fid/vid transition command */ 963/* Take a frequency, and issue the fid/vid transition command */
@@ -1142,8 +1157,7 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1142 data->cpu = pol->cpu; 1157 data->cpu = pol->cpu;
1143 data->currpstate = HW_PSTATE_INVALID; 1158 data->currpstate = HW_PSTATE_INVALID;
1144 1159
1145 rc = powernow_k8_cpu_init_acpi(data); 1160 if (powernow_k8_cpu_init_acpi(data)) {
1146 if (rc) {
1147 /* 1161 /*
1148 * Use the PSB BIOS structure. This is only availabe on 1162 * Use the PSB BIOS structure. This is only availabe on
1149 * an UP version, and is deprecated by AMD. 1163 * an UP version, and is deprecated by AMD.
@@ -1161,19 +1175,28 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1161 "ACPI maintainers and complain to your BIOS " 1175 "ACPI maintainers and complain to your BIOS "
1162 "vendor.\n"); 1176 "vendor.\n");
1163#endif 1177#endif
1164 goto err_out; 1178 kfree(data);
1179 return -ENODEV;
1165 } 1180 }
1166 if (pol->cpu != 0) { 1181 if (pol->cpu != 0) {
1167 printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for " 1182 printk(KERN_ERR FW_BUG PFX "No ACPI _PSS objects for "
1168 "CPU other than CPU0. Complain to your BIOS " 1183 "CPU other than CPU0. Complain to your BIOS "
1169 "vendor.\n"); 1184 "vendor.\n");
1170 goto err_out; 1185 kfree(data);
1186 return -ENODEV;
1171 } 1187 }
1172 rc = find_psb_table(data); 1188 rc = find_psb_table(data);
1173 if (rc) { 1189 if (rc) {
1174 goto err_out; 1190 kfree(data);
1191 return -ENODEV;
1175 } 1192 }
1176 } 1193 /* Take a crude guess here.
1194 * That guess was in microseconds, so multiply with 1000 */
1195 pol->cpuinfo.transition_latency = (
1196 ((data->rvo + 8) * data->vstable * VST_UNITS_20US) +
1197 ((1 << data->irt) * 30)) * 1000;
1198 } else /* ACPI _PSS objects available */
1199 pol->cpuinfo.transition_latency = get_transition_latency(data);
1177 1200
1178 /* only run on specific CPU from here on */ 1201 /* only run on specific CPU from here on */
1179 oldmask = current->cpus_allowed; 1202 oldmask = current->cpus_allowed;
@@ -1204,11 +1227,6 @@ static int __cpuinit powernowk8_cpu_init(struct cpufreq_policy *pol)
1204 cpumask_copy(pol->cpus, &per_cpu(cpu_core_map, pol->cpu)); 1227 cpumask_copy(pol->cpus, &per_cpu(cpu_core_map, pol->cpu));
1205 data->available_cores = pol->cpus; 1228 data->available_cores = pol->cpus;
1206 1229
1207 /* Take a crude guess here.
1208 * That guess was in microseconds, so multiply with 1000 */
1209 pol->cpuinfo.transition_latency = (((data->rvo + 8) * data->vstable * VST_UNITS_20US)
1210 + (3 * (1 << data->irt) * 10)) * 1000;
1211
1212 if (cpu_family == CPU_HW_PSTATE) 1230 if (cpu_family == CPU_HW_PSTATE)
1213 pol->cur = find_khz_freq_from_pstate(data->powernow_table, data->currpstate); 1231 pol->cur = find_khz_freq_from_pstate(data->powernow_table, data->currpstate);
1214 else 1232 else
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 430e5c38a544..24ff26a38ade 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -291,6 +291,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
291 ds_init_intel(c); 291 ds_init_intel(c);
292 } 292 }
293 293
294 if (c->x86 == 6 && c->x86_model == 29 && cpu_has_clflush)
295 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
296
294#ifdef CONFIG_X86_64 297#ifdef CONFIG_X86_64
295 if (c->x86 == 15) 298 if (c->x86 == 15)
296 c->x86_cache_alignment = c->x86_clflush_size * 2; 299 c->x86_cache_alignment = c->x86_clflush_size * 2;
diff --git a/arch/x86/kernel/cpu/mcheck/mce_64.c b/arch/x86/kernel/cpu/mcheck/mce_64.c
index 1c838032fd37..fe79985ce0f2 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_64.c
@@ -295,11 +295,11 @@ void do_machine_check(struct pt_regs * regs, long error_code)
295 * If we know that the error was in user space, send a 295 * If we know that the error was in user space, send a
296 * SIGBUS. Otherwise, panic if tolerance is low. 296 * SIGBUS. Otherwise, panic if tolerance is low.
297 * 297 *
298 * do_exit() takes an awful lot of locks and has a slight 298 * force_sig() takes an awful lot of locks and has a slight
299 * risk of deadlocking. 299 * risk of deadlocking.
300 */ 300 */
301 if (user_space) { 301 if (user_space) {
302 do_exit(SIGBUS); 302 force_sig(SIGBUS, current);
303 } else if (panic_on_oops || tolerant < 2) { 303 } else if (panic_on_oops || tolerant < 2) {
304 mce_panic("Uncorrected machine check", 304 mce_panic("Uncorrected machine check",
305 &panicm, mcestart); 305 &panicm, mcestart);
@@ -490,7 +490,7 @@ static void __cpuinit mce_cpu_quirks(struct cpuinfo_x86 *c)
490 490
491} 491}
492 492
493static void __cpuinit mce_cpu_features(struct cpuinfo_x86 *c) 493static void mce_cpu_features(struct cpuinfo_x86 *c)
494{ 494{
495 switch (c->x86_vendor) { 495 switch (c->x86_vendor) {
496 case X86_VENDOR_INTEL: 496 case X86_VENDOR_INTEL:
@@ -734,6 +734,7 @@ __setup("mce=", mcheck_enable);
734static int mce_resume(struct sys_device *dev) 734static int mce_resume(struct sys_device *dev)
735{ 735{
736 mce_init(NULL); 736 mce_init(NULL);
737 mce_cpu_features(&current_cpu_data);
737 return 0; 738 return 0;
738} 739}
739 740
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
index 8ae8c4ff094d..f2ee0ae29bd6 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd_64.c
@@ -121,7 +121,7 @@ static long threshold_restart_bank(void *_tr)
121} 121}
122 122
123/* cpu init entry point, called from mce.c with preempt off */ 123/* cpu init entry point, called from mce.c with preempt off */
124void __cpuinit mce_amd_feature_init(struct cpuinfo_x86 *c) 124void mce_amd_feature_init(struct cpuinfo_x86 *c)
125{ 125{
126 unsigned int bank, block; 126 unsigned int bank, block;
127 unsigned int cpu = smp_processor_id(); 127 unsigned int cpu = smp_processor_id();
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
index 4b48f251fd39..f44c36624360 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel_64.c
@@ -30,7 +30,7 @@ asmlinkage void smp_thermal_interrupt(void)
30 irq_exit(); 30 irq_exit();
31} 31}
32 32
33static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c) 33static void intel_init_thermal(struct cpuinfo_x86 *c)
34{ 34{
35 u32 l, h; 35 u32 l, h;
36 int tm2 = 0; 36 int tm2 = 0;
@@ -84,7 +84,7 @@ static void __cpuinit intel_init_thermal(struct cpuinfo_x86 *c)
84 return; 84 return;
85} 85}
86 86
87void __cpuinit mce_intel_feature_init(struct cpuinfo_x86 *c) 87void mce_intel_feature_init(struct cpuinfo_x86 *c)
88{ 88{
89 intel_init_thermal(c); 89 intel_init_thermal(c);
90} 90}
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index 169a120587be..87b67e3a765a 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -729,7 +729,7 @@ struct pebs_tracer *ds_request_pebs(struct task_struct *task,
729 729
730 spin_unlock_irqrestore(&ds_lock, irq); 730 spin_unlock_irqrestore(&ds_lock, irq);
731 731
732 ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_bts); 732 ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_pebs);
733 ds_resume_pebs(tracer); 733 ds_resume_pebs(tracer);
734 734
735 return tracer; 735 return tracer;
@@ -1029,5 +1029,4 @@ void ds_copy_thread(struct task_struct *tsk, struct task_struct *father)
1029 1029
1030void ds_exit_thread(struct task_struct *tsk) 1030void ds_exit_thread(struct task_struct *tsk)
1031{ 1031{
1032 WARN_ON(tsk->thread.ds_ctx);
1033} 1032}
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c
index 1119d247fe11..eb1ef3b67dd5 100644
--- a/arch/x86/kernel/efi.c
+++ b/arch/x86/kernel/efi.c
@@ -467,7 +467,7 @@ void __init efi_enter_virtual_mode(void)
467 efi_memory_desc_t *md; 467 efi_memory_desc_t *md;
468 efi_status_t status; 468 efi_status_t status;
469 unsigned long size; 469 unsigned long size;
470 u64 end, systab, addr, npages; 470 u64 end, systab, addr, npages, end_pfn;
471 void *p, *va; 471 void *p, *va;
472 472
473 efi.systab = NULL; 473 efi.systab = NULL;
@@ -479,7 +479,10 @@ void __init efi_enter_virtual_mode(void)
479 size = md->num_pages << EFI_PAGE_SHIFT; 479 size = md->num_pages << EFI_PAGE_SHIFT;
480 end = md->phys_addr + size; 480 end = md->phys_addr + size;
481 481
482 if (PFN_UP(end) <= max_low_pfn_mapped) 482 end_pfn = PFN_UP(end);
483 if (end_pfn <= max_low_pfn_mapped
484 || (end_pfn > (1UL << (32 - PAGE_SHIFT))
485 && end_pfn <= max_pfn_mapped))
483 va = __va(md->phys_addr); 486 va = __va(md->phys_addr);
484 else 487 else
485 va = efi_ioremap(md->phys_addr, size); 488 va = efi_ioremap(md->phys_addr, size);
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/kernel/efi_64.c
index 652c5287215f..cb783b92c50c 100644
--- a/arch/x86/kernel/efi_64.c
+++ b/arch/x86/kernel/efi_64.c
@@ -99,24 +99,11 @@ void __init efi_call_phys_epilog(void)
99 99
100void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size) 100void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size)
101{ 101{
102 static unsigned pages_mapped __initdata; 102 unsigned long last_map_pfn;
103 unsigned i, pages;
104 unsigned long offset;
105 103
106 pages = PFN_UP(phys_addr + size) - PFN_DOWN(phys_addr); 104 last_map_pfn = init_memory_mapping(phys_addr, phys_addr + size);
107 offset = phys_addr & ~PAGE_MASK; 105 if ((last_map_pfn << PAGE_SHIFT) < phys_addr + size)
108 phys_addr &= PAGE_MASK;
109
110 if (pages_mapped + pages > MAX_EFI_IO_PAGES)
111 return NULL; 106 return NULL;
112 107
113 for (i = 0; i < pages; i++) { 108 return (void __iomem *)__va(phys_addr);
114 __set_fixmap(FIX_EFI_IO_MAP_FIRST_PAGE - pages_mapped,
115 phys_addr, PAGE_KERNEL);
116 phys_addr += PAGE_SIZE;
117 pages_mapped++;
118 }
119
120 return (void __iomem *)__fix_to_virt(FIX_EFI_IO_MAP_FIRST_PAGE - \
121 (pages_mapped - pages)) + offset;
122} 109}
diff --git a/arch/x86/kernel/ftrace.c b/arch/x86/kernel/ftrace.c
index 1b43086b097a..231bdd3c5b1c 100644
--- a/arch/x86/kernel/ftrace.c
+++ b/arch/x86/kernel/ftrace.c
@@ -488,20 +488,21 @@ void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr)
488 * ignore such a protection. 488 * ignore such a protection.
489 */ 489 */
490 asm volatile( 490 asm volatile(
491 "1: " _ASM_MOV " (%[parent_old]), %[old]\n" 491 "1: " _ASM_MOV " (%[parent]), %[old]\n"
492 "2: " _ASM_MOV " %[return_hooker], (%[parent_replaced])\n" 492 "2: " _ASM_MOV " %[return_hooker], (%[parent])\n"
493 " movl $0, %[faulted]\n" 493 " movl $0, %[faulted]\n"
494 "3:\n"
494 495
495 ".section .fixup, \"ax\"\n" 496 ".section .fixup, \"ax\"\n"
496 "3: movl $1, %[faulted]\n" 497 "4: movl $1, %[faulted]\n"
498 " jmp 3b\n"
497 ".previous\n" 499 ".previous\n"
498 500
499 _ASM_EXTABLE(1b, 3b) 501 _ASM_EXTABLE(1b, 4b)
500 _ASM_EXTABLE(2b, 3b) 502 _ASM_EXTABLE(2b, 4b)
501 503
502 : [parent_replaced] "=r" (parent), [old] "=r" (old), 504 : [old] "=r" (old), [faulted] "=r" (faulted)
503 [faulted] "=r" (faulted) 505 : [parent] "r" (parent), [return_hooker] "r" (return_hooker)
504 : [parent_old] "0" (parent), [return_hooker] "r" (return_hooker)
505 : "memory" 506 : "memory"
506 ); 507 );
507 508
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 64d5ad0b8add..a00545fe5cdd 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -269,6 +269,8 @@ static void hpet_set_mode(enum clock_event_mode mode,
269 now = hpet_readl(HPET_COUNTER); 269 now = hpet_readl(HPET_COUNTER);
270 cmp = now + (unsigned long) delta; 270 cmp = now + (unsigned long) delta;
271 cfg = hpet_readl(HPET_Tn_CFG(timer)); 271 cfg = hpet_readl(HPET_Tn_CFG(timer));
272 /* Make sure we use edge triggered interrupts */
273 cfg &= ~HPET_TN_LEVEL;
272 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | 274 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
273 HPET_TN_SETVAL | HPET_TN_32BIT; 275 HPET_TN_SETVAL | HPET_TN_32BIT;
274 hpet_writel(cfg, HPET_Tn_CFG(timer)); 276 hpet_writel(cfg, HPET_Tn_CFG(timer));
@@ -897,7 +899,7 @@ static unsigned long hpet_rtc_flags;
897static int hpet_prev_update_sec; 899static int hpet_prev_update_sec;
898static struct rtc_time hpet_alarm_time; 900static struct rtc_time hpet_alarm_time;
899static unsigned long hpet_pie_count; 901static unsigned long hpet_pie_count;
900static unsigned long hpet_t1_cmp; 902static u32 hpet_t1_cmp;
901static unsigned long hpet_default_delta; 903static unsigned long hpet_default_delta;
902static unsigned long hpet_pie_delta; 904static unsigned long hpet_pie_delta;
903static unsigned long hpet_pie_limit; 905static unsigned long hpet_pie_limit;
@@ -905,6 +907,14 @@ static unsigned long hpet_pie_limit;
905static rtc_irq_handler irq_handler; 907static rtc_irq_handler irq_handler;
906 908
907/* 909/*
910 * Check that the hpet counter c1 is ahead of the c2
911 */
912static inline int hpet_cnt_ahead(u32 c1, u32 c2)
913{
914 return (s32)(c2 - c1) < 0;
915}
916
917/*
908 * Registers a IRQ handler. 918 * Registers a IRQ handler.
909 */ 919 */
910int hpet_register_irq_handler(rtc_irq_handler handler) 920int hpet_register_irq_handler(rtc_irq_handler handler)
@@ -1075,7 +1085,7 @@ static void hpet_rtc_timer_reinit(void)
1075 hpet_t1_cmp += delta; 1085 hpet_t1_cmp += delta;
1076 hpet_writel(hpet_t1_cmp, HPET_T1_CMP); 1086 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1077 lost_ints++; 1087 lost_ints++;
1078 } while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0); 1088 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1079 1089
1080 if (lost_ints) { 1090 if (lost_ints) {
1081 if (hpet_rtc_flags & RTC_PIE) 1091 if (hpet_rtc_flags & RTC_PIE)
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index b0f61f0dcd0a..f2f8540a7f3d 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -136,7 +136,7 @@ int init_fpu(struct task_struct *tsk)
136#ifdef CONFIG_X86_32 136#ifdef CONFIG_X86_32
137 if (!HAVE_HWFP) { 137 if (!HAVE_HWFP) {
138 memset(tsk->thread.xstate, 0, xstate_size); 138 memset(tsk->thread.xstate, 0, xstate_size);
139 finit(); 139 finit_task(tsk);
140 set_stopped_child_used_math(tsk); 140 set_stopped_child_used_math(tsk);
141 return 0; 141 return 0;
142 } 142 }
diff --git a/arch/x86/kernel/i8237.c b/arch/x86/kernel/i8237.c
index dbd6c1d1b638..b42ca694dc68 100644
--- a/arch/x86/kernel/i8237.c
+++ b/arch/x86/kernel/i8237.c
@@ -28,10 +28,10 @@ static int i8237A_resume(struct sys_device *dev)
28 28
29 flags = claim_dma_lock(); 29 flags = claim_dma_lock();
30 30
31 dma_outb(DMA1_RESET_REG, 0); 31 dma_outb(0, DMA1_RESET_REG);
32 dma_outb(DMA2_RESET_REG, 0); 32 dma_outb(0, DMA2_RESET_REG);
33 33
34 for (i = 0;i < 8;i++) { 34 for (i = 0; i < 8; i++) {
35 set_dma_addr(i, 0x000000); 35 set_dma_addr(i, 0x000000);
36 /* DMA count is a bit weird so this is not 0 */ 36 /* DMA count is a bit weird so this is not 0 */
37 set_dma_count(i, 1); 37 set_dma_count(i, 1);
@@ -51,14 +51,14 @@ static int i8237A_suspend(struct sys_device *dev, pm_message_t state)
51} 51}
52 52
53static struct sysdev_class i8237_sysdev_class = { 53static struct sysdev_class i8237_sysdev_class = {
54 .name = "i8237", 54 .name = "i8237",
55 .suspend = i8237A_suspend, 55 .suspend = i8237A_suspend,
56 .resume = i8237A_resume, 56 .resume = i8237A_resume,
57}; 57};
58 58
59static struct sys_device device_i8237A = { 59static struct sys_device device_i8237A = {
60 .id = 0, 60 .id = 0,
61 .cls = &i8237_sysdev_class, 61 .cls = &i8237_sysdev_class,
62}; 62};
63 63
64static int __init i8237A_init_sysfs(void) 64static int __init i8237A_init_sysfs(void)
@@ -68,5 +68,4 @@ static int __init i8237A_init_sysfs(void)
68 error = sysdev_register(&device_i8237A); 68 error = sysdev_register(&device_i8237A);
69 return error; 69 return error;
70} 70}
71
72device_initcall(i8237A_init_sysfs); 71device_initcall(i8237A_init_sysfs);
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c
index 9b0c480c383b..bc7ac4da90d7 100644
--- a/arch/x86/kernel/io_apic.c
+++ b/arch/x86/kernel/io_apic.c
@@ -3841,14 +3841,24 @@ int __init io_apic_get_redir_entries (int ioapic)
3841 3841
3842void __init probe_nr_irqs_gsi(void) 3842void __init probe_nr_irqs_gsi(void)
3843{ 3843{
3844 int idx;
3845 int nr = 0; 3844 int nr = 0;
3846 3845
3847 for (idx = 0; idx < nr_ioapics; idx++) 3846 nr = acpi_probe_gsi();
3848 nr += io_apic_get_redir_entries(idx) + 1; 3847 if (nr > nr_irqs_gsi) {
3849
3850 if (nr > nr_irqs_gsi)
3851 nr_irqs_gsi = nr; 3848 nr_irqs_gsi = nr;
3849 } else {
3850 /* for acpi=off or acpi is not compiled in */
3851 int idx;
3852
3853 nr = 0;
3854 for (idx = 0; idx < nr_ioapics; idx++)
3855 nr += io_apic_get_redir_entries(idx) + 1;
3856
3857 if (nr > nr_irqs_gsi)
3858 nr_irqs_gsi = nr;
3859 }
3860
3861 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3852} 3862}
3853 3863
3854/* -------------------------------------------------------------------------- 3864/* --------------------------------------------------------------------------
diff --git a/arch/x86/kernel/olpc.c b/arch/x86/kernel/olpc.c
index 7a13fac63a1f..4006c522adc7 100644
--- a/arch/x86/kernel/olpc.c
+++ b/arch/x86/kernel/olpc.c
@@ -203,7 +203,7 @@ static void __init platform_detect(void)
203static void __init platform_detect(void) 203static void __init platform_detect(void)
204{ 204{
205 /* stopgap until OFW support is added to the kernel */ 205 /* stopgap until OFW support is added to the kernel */
206 olpc_platform_info.boardrev = 0xc2; 206 olpc_platform_info.boardrev = olpc_board(0xc2);
207} 207}
208#endif 208#endif
209 209
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index e4c8fb608873..c6520a4e85d4 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -268,6 +268,32 @@ enum paravirt_lazy_mode paravirt_get_lazy_mode(void)
268 return __get_cpu_var(paravirt_lazy_mode); 268 return __get_cpu_var(paravirt_lazy_mode);
269} 269}
270 270
271void arch_flush_lazy_mmu_mode(void)
272{
273 preempt_disable();
274
275 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_MMU) {
276 WARN_ON(preempt_count() == 1);
277 arch_leave_lazy_mmu_mode();
278 arch_enter_lazy_mmu_mode();
279 }
280
281 preempt_enable();
282}
283
284void arch_flush_lazy_cpu_mode(void)
285{
286 preempt_disable();
287
288 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) {
289 WARN_ON(preempt_count() == 1);
290 arch_leave_lazy_cpu_mode();
291 arch_enter_lazy_cpu_mode();
292 }
293
294 preempt_enable();
295}
296
271struct pv_info pv_info = { 297struct pv_info pv_info = {
272 .name = "bare hardware", 298 .name = "bare hardware",
273 .paravirt_enabled = 0, 299 .paravirt_enabled = 0,
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index e68bb9e30864..6d12f7e37f8c 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -180,6 +180,9 @@ void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
180 180
181 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1); 181 trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
182 if (!need_resched()) { 182 if (!need_resched()) {
183 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
184 clflush((void *)&current_thread_info()->flags);
185
183 __monitor((void *)&current_thread_info()->flags, 0, 0); 186 __monitor((void *)&current_thread_info()->flags, 0, 0);
184 smp_mb(); 187 smp_mb();
185 if (!need_resched()) 188 if (!need_resched())
@@ -194,6 +197,9 @@ static void mwait_idle(void)
194 struct power_trace it; 197 struct power_trace it;
195 if (!need_resched()) { 198 if (!need_resched()) {
196 trace_power_start(&it, POWER_CSTATE, 1); 199 trace_power_start(&it, POWER_CSTATE, 1);
200 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
201 clflush((void *)&current_thread_info()->flags);
202
197 __monitor((void *)&current_thread_info()->flags, 0, 0); 203 __monitor((void *)&current_thread_info()->flags, 0, 0);
198 smp_mb(); 204 smp_mb();
199 if (!need_resched()) 205 if (!need_resched())
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index a546f55c77b4..bd4da2af08ae 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -104,9 +104,6 @@ void cpu_idle(void)
104 check_pgt_cache(); 104 check_pgt_cache();
105 rmb(); 105 rmb();
106 106
107 if (rcu_pending(cpu))
108 rcu_check_callbacks(cpu, 0);
109
110 if (cpu_is_offline(cpu)) 107 if (cpu_is_offline(cpu))
111 play_dead(); 108 play_dead();
112 109
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 416fb9282f4f..85b4cb5c1980 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -40,6 +40,7 @@
40#include <linux/uaccess.h> 40#include <linux/uaccess.h>
41#include <linux/io.h> 41#include <linux/io.h>
42#include <linux/ftrace.h> 42#include <linux/ftrace.h>
43#include <linux/dmi.h>
43 44
44#include <asm/pgtable.h> 45#include <asm/pgtable.h>
45#include <asm/system.h> 46#include <asm/system.h>
@@ -151,14 +152,18 @@ void __show_regs(struct pt_regs *regs, int all)
151 unsigned long d0, d1, d2, d3, d6, d7; 152 unsigned long d0, d1, d2, d3, d6, d7;
152 unsigned int fsindex, gsindex; 153 unsigned int fsindex, gsindex;
153 unsigned int ds, cs, es; 154 unsigned int ds, cs, es;
155 const char *board;
154 156
155 printk("\n"); 157 printk("\n");
156 print_modules(); 158 print_modules();
157 printk(KERN_INFO "Pid: %d, comm: %.20s %s %s %.*s\n", 159 board = dmi_get_system_info(DMI_PRODUCT_NAME);
160 if (!board)
161 board = "";
162 printk(KERN_INFO "Pid: %d, comm: %.20s %s %s %.*s %s\n",
158 current->pid, current->comm, print_tainted(), 163 current->pid, current->comm, print_tainted(),
159 init_utsname()->release, 164 init_utsname()->release,
160 (int)strcspn(init_utsname()->version, " "), 165 (int)strcspn(init_utsname()->version, " "),
161 init_utsname()->version); 166 init_utsname()->version, board);
162 printk(KERN_INFO "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip); 167 printk(KERN_INFO "RIP: %04lx:[<%016lx>] ", regs->cs & 0xffff, regs->ip);
163 printk_address(regs->ip, 1); 168 printk_address(regs->ip, 1);
164 printk(KERN_INFO "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss, 169 printk(KERN_INFO "RSP: %04lx:%016lx EFLAGS: %08lx\n", regs->ss,
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index 0a5df5f82fb9..06ca07f6ad86 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -810,12 +810,16 @@ static void ptrace_bts_untrace(struct task_struct *child)
810 810
811static void ptrace_bts_detach(struct task_struct *child) 811static void ptrace_bts_detach(struct task_struct *child)
812{ 812{
813 if (unlikely(child->bts)) { 813 /*
814 ds_release_bts(child->bts); 814 * Ptrace_detach() races with ptrace_untrace() in case
815 child->bts = NULL; 815 * the child dies and is reaped by another thread.
816 816 *
817 ptrace_bts_free_buffer(child); 817 * We only do the memory accounting at this point and
818 } 818 * leave the buffer deallocation and the bts tracer
819 * release to ptrace_bts_untrace() which will be called
820 * later on with tasklist_lock held.
821 */
822 release_locked_buffer(child->bts_buffer, child->bts_size);
819} 823}
820#else 824#else
821static inline void ptrace_bts_fork(struct task_struct *tsk) {} 825static inline void ptrace_bts_fork(struct task_struct *tsk) {}
@@ -1384,7 +1388,7 @@ void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
1384#ifdef CONFIG_X86_32 1388#ifdef CONFIG_X86_32
1385# define IS_IA32 1 1389# define IS_IA32 1
1386#elif defined CONFIG_IA32_EMULATION 1390#elif defined CONFIG_IA32_EMULATION
1387# define IS_IA32 test_thread_flag(TIF_IA32) 1391# define IS_IA32 is_compat_task()
1388#else 1392#else
1389# define IS_IA32 0 1393# define IS_IA32 0
1390#endif 1394#endif
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c
index 2b46eb41643b..4526b3a75ed2 100644
--- a/arch/x86/kernel/reboot.c
+++ b/arch/x86/kernel/reboot.c
@@ -217,6 +217,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = {
217 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), 217 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"),
218 }, 218 },
219 }, 219 },
220 { /* Handle problems with rebooting on Dell XPS710 */
221 .callback = set_bios_reboot,
222 .ident = "Dell XPS710",
223 .matches = {
224 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
225 DMI_MATCH(DMI_PRODUCT_NAME, "Dell XPS710"),
226 },
227 },
220 { } 228 { }
221}; 229};
222 230
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index ae0d8042cf69..6a8811a69324 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -607,7 +607,7 @@ struct x86_quirks *x86_quirks __initdata = &default_x86_quirks;
607static int __init dmi_low_memory_corruption(const struct dmi_system_id *d) 607static int __init dmi_low_memory_corruption(const struct dmi_system_id *d)
608{ 608{
609 printk(KERN_NOTICE 609 printk(KERN_NOTICE
610 "%s detected: BIOS may corrupt low RAM, working it around.\n", 610 "%s detected: BIOS may corrupt low RAM, working around it.\n",
611 d->ident); 611 d->ident);
612 612
613 e820_update_range(0, 0x10000, E820_RAM, E820_RESERVED); 613 e820_update_range(0, 0x10000, E820_RAM, E820_RESERVED);
@@ -770,6 +770,9 @@ void __init setup_arch(char **cmdline_p)
770 770
771 finish_e820_parsing(); 771 finish_e820_parsing();
772 772
773 if (efi_enabled)
774 efi_init();
775
773 dmi_scan_machine(); 776 dmi_scan_machine();
774 777
775 dmi_check_system(bad_bios_dmi_table); 778 dmi_check_system(bad_bios_dmi_table);
@@ -789,8 +792,6 @@ void __init setup_arch(char **cmdline_p)
789 insert_resource(&iomem_resource, &data_resource); 792 insert_resource(&iomem_resource, &data_resource);
790 insert_resource(&iomem_resource, &bss_resource); 793 insert_resource(&iomem_resource, &bss_resource);
791 794
792 if (efi_enabled)
793 efi_init();
794 795
795#ifdef CONFIG_X86_32 796#ifdef CONFIG_X86_32
796 if (ppro_with_ram_bug()) { 797 if (ppro_with_ram_bug()) {
diff --git a/arch/x86/kernel/time_64.c b/arch/x86/kernel/time_64.c
index e6e695acd725..241ec3923f61 100644
--- a/arch/x86/kernel/time_64.c
+++ b/arch/x86/kernel/time_64.c
@@ -115,7 +115,7 @@ unsigned long __init calibrate_cpu(void)
115 115
116static struct irqaction irq0 = { 116static struct irqaction irq0 = {
117 .handler = timer_interrupt, 117 .handler = timer_interrupt,
118 .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING, 118 .flags = IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING | IRQF_TIMER,
119 .mask = CPU_MASK_NONE, 119 .mask = CPU_MASK_NONE,
120 .name = "timer" 120 .name = "timer"
121}; 121};
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 98c2d055284b..a9e7548e1790 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -99,6 +99,12 @@ static inline void preempt_conditional_sti(struct pt_regs *regs)
99 local_irq_enable(); 99 local_irq_enable();
100} 100}
101 101
102static inline void conditional_cli(struct pt_regs *regs)
103{
104 if (regs->flags & X86_EFLAGS_IF)
105 local_irq_disable();
106}
107
102static inline void preempt_conditional_cli(struct pt_regs *regs) 108static inline void preempt_conditional_cli(struct pt_regs *regs)
103{ 109{
104 if (regs->flags & X86_EFLAGS_IF) 110 if (regs->flags & X86_EFLAGS_IF)
@@ -626,8 +632,10 @@ clear_dr7:
626 632
627#ifdef CONFIG_X86_32 633#ifdef CONFIG_X86_32
628debug_vm86: 634debug_vm86:
635 /* reenable preemption: handle_vm86_trap() might sleep */
636 dec_preempt_count();
629 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1); 637 handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1);
630 preempt_conditional_cli(regs); 638 conditional_cli(regs);
631 return; 639 return;
632#endif 640#endif
633 641
@@ -896,7 +904,7 @@ asmlinkage void math_state_restore(void)
896EXPORT_SYMBOL_GPL(math_state_restore); 904EXPORT_SYMBOL_GPL(math_state_restore);
897 905
898#ifndef CONFIG_MATH_EMULATION 906#ifndef CONFIG_MATH_EMULATION
899asmlinkage void math_emulate(long arg) 907void math_emulate(struct math_emu_info *info)
900{ 908{
901 printk(KERN_EMERG 909 printk(KERN_EMERG
902 "math-emulation not enabled and no coprocessor found.\n"); 910 "math-emulation not enabled and no coprocessor found.\n");
@@ -906,16 +914,19 @@ asmlinkage void math_emulate(long arg)
906} 914}
907#endif /* CONFIG_MATH_EMULATION */ 915#endif /* CONFIG_MATH_EMULATION */
908 916
909dotraplinkage void __kprobes 917dotraplinkage void __kprobes do_device_not_available(struct pt_regs regs)
910do_device_not_available(struct pt_regs *regs, long error)
911{ 918{
912#ifdef CONFIG_X86_32 919#ifdef CONFIG_X86_32
913 if (read_cr0() & X86_CR0_EM) { 920 if (read_cr0() & X86_CR0_EM) {
914 conditional_sti(regs); 921 struct math_emu_info info = { };
915 math_emulate(0); 922
923 conditional_sti(&regs);
924
925 info.regs = &regs;
926 math_emulate(&info);
916 } else { 927 } else {
917 math_state_restore(); /* interrupts still off */ 928 math_state_restore(); /* interrupts still off */
918 conditional_sti(regs); 929 conditional_sti(&regs);
919 } 930 }
920#else 931#else
921 math_state_restore(); 932 math_state_restore();
diff --git a/arch/x86/kernel/vmi_32.c b/arch/x86/kernel/vmi_32.c
index 1d3302cc2ddf..bef58b4982db 100644
--- a/arch/x86/kernel/vmi_32.c
+++ b/arch/x86/kernel/vmi_32.c
@@ -321,6 +321,16 @@ static void vmi_release_pmd(unsigned long pfn)
321} 321}
322 322
323/* 323/*
324 * We use the pgd_free hook for releasing the pgd page:
325 */
326static void vmi_pgd_free(struct mm_struct *mm, pgd_t *pgd)
327{
328 unsigned long pfn = __pa(pgd) >> PAGE_SHIFT;
329
330 vmi_ops.release_page(pfn, VMI_PAGE_L2);
331}
332
333/*
324 * Helper macros for MMU update flags. We can defer updates until a flush 334 * Helper macros for MMU update flags. We can defer updates until a flush
325 * or page invalidation only if the update is to the current address space 335 * or page invalidation only if the update is to the current address space
326 * (otherwise, there is no flush). We must check against init_mm, since 336 * (otherwise, there is no flush). We must check against init_mm, since
@@ -762,6 +772,7 @@ static inline int __init activate_vmi(void)
762 if (vmi_ops.release_page) { 772 if (vmi_ops.release_page) {
763 pv_mmu_ops.release_pte = vmi_release_pte; 773 pv_mmu_ops.release_pte = vmi_release_pte;
764 pv_mmu_ops.release_pmd = vmi_release_pmd; 774 pv_mmu_ops.release_pmd = vmi_release_pmd;
775 pv_mmu_ops.pgd_free = vmi_pgd_free;
765 } 776 }
766 777
767 /* Set linear is needed in all cases */ 778 /* Set linear is needed in all cases */
diff --git a/arch/x86/kernel/vmiclock_32.c b/arch/x86/kernel/vmiclock_32.c
index c4c1f9e09402..e5b088fffa40 100644
--- a/arch/x86/kernel/vmiclock_32.c
+++ b/arch/x86/kernel/vmiclock_32.c
@@ -202,7 +202,7 @@ static irqreturn_t vmi_timer_interrupt(int irq, void *dev_id)
202static struct irqaction vmi_clock_action = { 202static struct irqaction vmi_clock_action = {
203 .name = "vmi-timer", 203 .name = "vmi-timer",
204 .handler = vmi_timer_interrupt, 204 .handler = vmi_timer_interrupt,
205 .flags = IRQF_DISABLED | IRQF_NOBALANCING, 205 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_TIMER,
206 .mask = CPU_MASK_ALL, 206 .mask = CPU_MASK_ALL,
207}; 207};
208 208
@@ -283,10 +283,13 @@ void __devinit vmi_time_ap_init(void)
283#endif 283#endif
284 284
285/** vmi clocksource */ 285/** vmi clocksource */
286static struct clocksource clocksource_vmi;
286 287
287static cycle_t read_real_cycles(void) 288static cycle_t read_real_cycles(void)
288{ 289{
289 return vmi_timer_ops.get_cycle_counter(VMI_CYCLES_REAL); 290 cycle_t ret = (cycle_t)vmi_timer_ops.get_cycle_counter(VMI_CYCLES_REAL);
291 return ret >= clocksource_vmi.cycle_last ?
292 ret : clocksource_vmi.cycle_last;
290} 293}
291 294
292static struct clocksource clocksource_vmi = { 295static struct clocksource clocksource_vmi = {
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index e665d1c623ca..72bd275a9b5c 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -207,7 +207,7 @@ static int __pit_timer_fn(struct kvm_kpit_state *ps)
207 hrtimer_add_expires_ns(&pt->timer, pt->period); 207 hrtimer_add_expires_ns(&pt->timer, pt->period);
208 pt->scheduled = hrtimer_get_expires_ns(&pt->timer); 208 pt->scheduled = hrtimer_get_expires_ns(&pt->timer);
209 if (pt->period) 209 if (pt->period)
210 ps->channels[0].count_load_time = hrtimer_get_expires(&pt->timer); 210 ps->channels[0].count_load_time = ktime_get();
211 211
212 return (pt->period == 0 ? 0 : 1); 212 return (pt->period == 0 ? 0 : 1);
213} 213}
diff --git a/arch/x86/kvm/irq.c b/arch/x86/kvm/irq.c
index c019b8edcdb7..cf17ed52f6fb 100644
--- a/arch/x86/kvm/irq.c
+++ b/arch/x86/kvm/irq.c
@@ -87,13 +87,6 @@ void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu)
87} 87}
88EXPORT_SYMBOL_GPL(kvm_inject_pending_timer_irqs); 88EXPORT_SYMBOL_GPL(kvm_inject_pending_timer_irqs);
89 89
90void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
91{
92 kvm_apic_timer_intr_post(vcpu, vec);
93 /* TODO: PIT, RTC etc. */
94}
95EXPORT_SYMBOL_GPL(kvm_timer_intr_post);
96
97void __kvm_migrate_timers(struct kvm_vcpu *vcpu) 90void __kvm_migrate_timers(struct kvm_vcpu *vcpu)
98{ 91{
99 __kvm_migrate_apic_timer(vcpu); 92 __kvm_migrate_apic_timer(vcpu);
diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h
index 2bf32a03ceec..82579ee538d0 100644
--- a/arch/x86/kvm/irq.h
+++ b/arch/x86/kvm/irq.h
@@ -89,7 +89,6 @@ static inline int irqchip_in_kernel(struct kvm *kvm)
89 89
90void kvm_pic_reset(struct kvm_kpic_state *s); 90void kvm_pic_reset(struct kvm_kpic_state *s);
91 91
92void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
93void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu); 92void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
94void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu); 93void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
95void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu); 94void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index afac68c0815c..f0b67f2cdd69 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -35,6 +35,12 @@
35#include "kvm_cache_regs.h" 35#include "kvm_cache_regs.h"
36#include "irq.h" 36#include "irq.h"
37 37
38#ifndef CONFIG_X86_64
39#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
40#else
41#define mod_64(x, y) ((x) % (y))
42#endif
43
38#define PRId64 "d" 44#define PRId64 "d"
39#define PRIx64 "llx" 45#define PRIx64 "llx"
40#define PRIu64 "u" 46#define PRIu64 "u"
@@ -511,52 +517,22 @@ static void apic_send_ipi(struct kvm_lapic *apic)
511 517
512static u32 apic_get_tmcct(struct kvm_lapic *apic) 518static u32 apic_get_tmcct(struct kvm_lapic *apic)
513{ 519{
514 u64 counter_passed; 520 ktime_t remaining;
515 ktime_t passed, now; 521 s64 ns;
516 u32 tmcct; 522 u32 tmcct;
517 523
518 ASSERT(apic != NULL); 524 ASSERT(apic != NULL);
519 525
520 now = apic->timer.dev.base->get_time();
521 tmcct = apic_get_reg(apic, APIC_TMICT);
522
523 /* if initial count is 0, current count should also be 0 */ 526 /* if initial count is 0, current count should also be 0 */
524 if (tmcct == 0) 527 if (apic_get_reg(apic, APIC_TMICT) == 0)
525 return 0; 528 return 0;
526 529
527 if (unlikely(ktime_to_ns(now) <= 530 remaining = hrtimer_expires_remaining(&apic->timer.dev);
528 ktime_to_ns(apic->timer.last_update))) { 531 if (ktime_to_ns(remaining) < 0)
529 /* Wrap around */ 532 remaining = ktime_set(0, 0);
530 passed = ktime_add(( { 533
531 (ktime_t) { 534 ns = mod_64(ktime_to_ns(remaining), apic->timer.period);
532 .tv64 = KTIME_MAX - 535 tmcct = div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
533 (apic->timer.last_update).tv64}; }
534 ), now);
535 apic_debug("time elapsed\n");
536 } else
537 passed = ktime_sub(now, apic->timer.last_update);
538
539 counter_passed = div64_u64(ktime_to_ns(passed),
540 (APIC_BUS_CYCLE_NS * apic->timer.divide_count));
541
542 if (counter_passed > tmcct) {
543 if (unlikely(!apic_lvtt_period(apic))) {
544 /* one-shot timers stick at 0 until reset */
545 tmcct = 0;
546 } else {
547 /*
548 * periodic timers reset to APIC_TMICT when they
549 * hit 0. The while loop simulates this happening N
550 * times. (counter_passed %= tmcct) would also work,
551 * but might be slower or not work on 32-bit??
552 */
553 while (counter_passed > tmcct)
554 counter_passed -= tmcct;
555 tmcct -= counter_passed;
556 }
557 } else {
558 tmcct -= counter_passed;
559 }
560 536
561 return tmcct; 537 return tmcct;
562} 538}
@@ -653,8 +629,6 @@ static void start_apic_timer(struct kvm_lapic *apic)
653{ 629{
654 ktime_t now = apic->timer.dev.base->get_time(); 630 ktime_t now = apic->timer.dev.base->get_time();
655 631
656 apic->timer.last_update = now;
657
658 apic->timer.period = apic_get_reg(apic, APIC_TMICT) * 632 apic->timer.period = apic_get_reg(apic, APIC_TMICT) *
659 APIC_BUS_CYCLE_NS * apic->timer.divide_count; 633 APIC_BUS_CYCLE_NS * apic->timer.divide_count;
660 atomic_set(&apic->timer.pending, 0); 634 atomic_set(&apic->timer.pending, 0);
@@ -1110,16 +1084,6 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1110 } 1084 }
1111} 1085}
1112 1086
1113void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec)
1114{
1115 struct kvm_lapic *apic = vcpu->arch.apic;
1116
1117 if (apic && apic_lvt_vector(apic, APIC_LVTT) == vec)
1118 apic->timer.last_update = ktime_add_ns(
1119 apic->timer.last_update,
1120 apic->timer.period);
1121}
1122
1123int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) 1087int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1124{ 1088{
1125 int vector = kvm_apic_has_interrupt(vcpu); 1089 int vector = kvm_apic_has_interrupt(vcpu);
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 81858881287e..45ab6ee71209 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -12,7 +12,6 @@ struct kvm_lapic {
12 atomic_t pending; 12 atomic_t pending;
13 s64 period; /* unit: ns */ 13 s64 period; /* unit: ns */
14 u32 divide_count; 14 u32 divide_count;
15 ktime_t last_update;
16 struct hrtimer dev; 15 struct hrtimer dev;
17 } timer; 16 } timer;
18 struct kvm_vcpu *vcpu; 17 struct kvm_vcpu *vcpu;
@@ -42,7 +41,6 @@ void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
42void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu); 41void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
43int kvm_lapic_enabled(struct kvm_vcpu *vcpu); 42int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
44int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu); 43int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
45void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
46 44
47void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr); 45void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
48void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu); 46void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 83f11c7474a1..2d4477c71473 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -1698,8 +1698,13 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
1698 if (largepage) 1698 if (largepage)
1699 spte |= PT_PAGE_SIZE_MASK; 1699 spte |= PT_PAGE_SIZE_MASK;
1700 if (mt_mask) { 1700 if (mt_mask) {
1701 mt_mask = get_memory_type(vcpu, gfn) << 1701 if (!kvm_is_mmio_pfn(pfn)) {
1702 kvm_x86_ops->get_mt_mask_shift(); 1702 mt_mask = get_memory_type(vcpu, gfn) <<
1703 kvm_x86_ops->get_mt_mask_shift();
1704 mt_mask |= VMX_EPT_IGMT_BIT;
1705 } else
1706 mt_mask = MTRR_TYPE_UNCACHABLE <<
1707 kvm_x86_ops->get_mt_mask_shift();
1703 spte |= mt_mask; 1708 spte |= mt_mask;
1704 } 1709 }
1705 1710
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 1452851ae258..a9e769e4e251 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1600,7 +1600,6 @@ static void svm_intr_assist(struct kvm_vcpu *vcpu)
1600 /* Okay, we can deliver the interrupt: grab it and update PIC state. */ 1600 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1601 intr_vector = kvm_cpu_get_interrupt(vcpu); 1601 intr_vector = kvm_cpu_get_interrupt(vcpu);
1602 svm_inject_irq(svm, intr_vector); 1602 svm_inject_irq(svm, intr_vector);
1603 kvm_timer_intr_post(vcpu, intr_vector);
1604out: 1603out:
1605 update_cr8_intercept(vcpu); 1604 update_cr8_intercept(vcpu);
1606} 1605}
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 6259d7467648..7611af576829 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -903,6 +903,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
903 data = vmcs_readl(GUEST_SYSENTER_ESP); 903 data = vmcs_readl(GUEST_SYSENTER_ESP);
904 break; 904 break;
905 default: 905 default:
906 vmx_load_host_state(to_vmx(vcpu));
906 msr = find_msr_entry(to_vmx(vcpu), msr_index); 907 msr = find_msr_entry(to_vmx(vcpu), msr_index);
907 if (msr) { 908 if (msr) {
908 data = msr->data; 909 data = msr->data;
@@ -3285,7 +3286,6 @@ static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3285 } 3286 }
3286 if (vcpu->arch.interrupt.pending) { 3287 if (vcpu->arch.interrupt.pending) {
3287 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); 3288 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3288 kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr);
3289 if (kvm_cpu_has_interrupt(vcpu)) 3289 if (kvm_cpu_has_interrupt(vcpu))
3290 enable_irq_window(vcpu); 3290 enable_irq_window(vcpu);
3291 } 3291 }
@@ -3687,8 +3687,7 @@ static int __init vmx_init(void)
3687 if (vm_need_ept()) { 3687 if (vm_need_ept()) {
3688 bypass_guest_pf = 0; 3688 bypass_guest_pf = 0;
3689 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | 3689 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3690 VMX_EPT_WRITABLE_MASK | 3690 VMX_EPT_WRITABLE_MASK);
3691 VMX_EPT_IGMT_BIT);
3692 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, 3691 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3693 VMX_EPT_EXECUTABLE_MASK, 3692 VMX_EPT_EXECUTABLE_MASK,
3694 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); 3693 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index cc17546a2406..758b7a155ae9 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -967,7 +967,6 @@ int kvm_dev_ioctl_check_extension(long ext)
967 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL: 967 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
968 case KVM_CAP_SET_TSS_ADDR: 968 case KVM_CAP_SET_TSS_ADDR:
969 case KVM_CAP_EXT_CPUID: 969 case KVM_CAP_EXT_CPUID:
970 case KVM_CAP_CLOCKSOURCE:
971 case KVM_CAP_PIT: 970 case KVM_CAP_PIT:
972 case KVM_CAP_NOP_IO_DELAY: 971 case KVM_CAP_NOP_IO_DELAY:
973 case KVM_CAP_MP_STATE: 972 case KVM_CAP_MP_STATE:
@@ -992,6 +991,9 @@ int kvm_dev_ioctl_check_extension(long ext)
992 case KVM_CAP_IOMMU: 991 case KVM_CAP_IOMMU:
993 r = iommu_found(); 992 r = iommu_found();
994 break; 993 break;
994 case KVM_CAP_CLOCKSOURCE:
995 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
996 break;
995 default: 997 default:
996 r = 0; 998 r = 0;
997 break; 999 break;
@@ -4127,9 +4129,13 @@ static void kvm_free_vcpus(struct kvm *kvm)
4127 4129
4128} 4130}
4129 4131
4130void kvm_arch_destroy_vm(struct kvm *kvm) 4132void kvm_arch_sync_events(struct kvm *kvm)
4131{ 4133{
4132 kvm_free_all_assigned_devices(kvm); 4134 kvm_free_all_assigned_devices(kvm);
4135}
4136
4137void kvm_arch_destroy_vm(struct kvm *kvm)
4138{
4133 kvm_iommu_unmap_guest(kvm); 4139 kvm_iommu_unmap_guest(kvm);
4134 kvm_free_pit(kvm); 4140 kvm_free_pit(kvm);
4135 kfree(kvm->arch.vpic); 4141 kfree(kvm->arch.vpic);
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c
index 92f1c6f3e19d..960a8d9c049c 100644
--- a/arch/x86/lguest/boot.c
+++ b/arch/x86/lguest/boot.c
@@ -343,6 +343,11 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx,
343 * flush_tlb_user() for both user and kernel mappings unless 343 * flush_tlb_user() for both user and kernel mappings unless
344 * the Page Global Enable (PGE) feature bit is set. */ 344 * the Page Global Enable (PGE) feature bit is set. */
345 *dx |= 0x00002000; 345 *dx |= 0x00002000;
346 /* We also lie, and say we're family id 5. 6 or greater
347 * leads to a rdmsr in early_init_intel which we can't handle.
348 * Family ID is returned as bits 8-12 in ax. */
349 *ax &= 0xFFFFF0FF;
350 *ax |= 0x00000500;
346 break; 351 break;
347 case 0x80000000: 352 case 0x80000000:
348 /* Futureproof this a little: if they ask how much extended 353 /* Futureproof this a little: if they ask how much extended
@@ -589,19 +594,21 @@ static void __init lguest_init_IRQ(void)
589 /* Some systems map "vectors" to interrupts weirdly. Lguest has 594 /* Some systems map "vectors" to interrupts weirdly. Lguest has
590 * a straightforward 1 to 1 mapping, so force that here. */ 595 * a straightforward 1 to 1 mapping, so force that here. */
591 __get_cpu_var(vector_irq)[vector] = i; 596 __get_cpu_var(vector_irq)[vector] = i;
592 if (vector != SYSCALL_VECTOR) { 597 if (vector != SYSCALL_VECTOR)
593 set_intr_gate(vector, 598 set_intr_gate(vector, interrupt[i]);
594 interrupt[vector-FIRST_EXTERNAL_VECTOR]);
595 set_irq_chip_and_handler_name(i, &lguest_irq_controller,
596 handle_level_irq,
597 "level");
598 }
599 } 599 }
600 /* This call is required to set up for 4k stacks, where we have 600 /* This call is required to set up for 4k stacks, where we have
601 * separate stacks for hard and soft interrupts. */ 601 * separate stacks for hard and soft interrupts. */
602 irq_ctx_init(smp_processor_id()); 602 irq_ctx_init(smp_processor_id());
603} 603}
604 604
605void lguest_setup_irq(unsigned int irq)
606{
607 irq_to_desc_alloc_cpu(irq, 0);
608 set_irq_chip_and_handler_name(irq, &lguest_irq_controller,
609 handle_level_irq, "level");
610}
611
605/* 612/*
606 * Time. 613 * Time.
607 * 614 *
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c
index a265a7c63190..50b591871128 100644
--- a/arch/x86/mach-default/setup.c
+++ b/arch/x86/mach-default/setup.c
@@ -96,7 +96,7 @@ void __init trap_init_hook(void)
96 96
97static struct irqaction irq0 = { 97static struct irqaction irq0 = {
98 .handler = timer_interrupt, 98 .handler = timer_interrupt,
99 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL, 99 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
100 .mask = CPU_MASK_NONE, 100 .mask = CPU_MASK_NONE,
101 .name = "timer" 101 .name = "timer"
102}; 102};
diff --git a/arch/x86/mach-voyager/setup.c b/arch/x86/mach-voyager/setup.c
index d914a7996a66..8e5118371f0f 100644
--- a/arch/x86/mach-voyager/setup.c
+++ b/arch/x86/mach-voyager/setup.c
@@ -56,7 +56,7 @@ void __init trap_init_hook(void)
56 56
57static struct irqaction irq0 = { 57static struct irqaction irq0 = {
58 .handler = timer_interrupt, 58 .handler = timer_interrupt,
59 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL, 59 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL | IRQF_TIMER,
60 .mask = CPU_MASK_NONE, 60 .mask = CPU_MASK_NONE,
61 .name = "timer" 61 .name = "timer"
62}; 62};
diff --git a/arch/x86/mach-voyager/voyager_smp.c b/arch/x86/mach-voyager/voyager_smp.c
index 7ffcdeec4631..b9cc84a2a4fc 100644
--- a/arch/x86/mach-voyager/voyager_smp.c
+++ b/arch/x86/mach-voyager/voyager_smp.c
@@ -65,7 +65,7 @@ static volatile unsigned long smp_invalidate_needed;
65 65
66/* Bitmask of CPUs present in the system - exported by i386_syms.c, used 66/* Bitmask of CPUs present in the system - exported by i386_syms.c, used
67 * by scheduler but indexed physically */ 67 * by scheduler but indexed physically */
68cpumask_t phys_cpu_present_map = CPU_MASK_NONE; 68static cpumask_t voyager_phys_cpu_present_map = CPU_MASK_NONE;
69 69
70/* The internal functions */ 70/* The internal functions */
71static void send_CPI(__u32 cpuset, __u8 cpi); 71static void send_CPI(__u32 cpuset, __u8 cpi);
@@ -366,19 +366,19 @@ void __init find_smp_config(void)
366 /* set up everything for just this CPU, we can alter 366 /* set up everything for just this CPU, we can alter
367 * this as we start the other CPUs later */ 367 * this as we start the other CPUs later */
368 /* now get the CPU disposition from the extended CMOS */ 368 /* now get the CPU disposition from the extended CMOS */
369 cpus_addr(phys_cpu_present_map)[0] = 369 cpus_addr(voyager_phys_cpu_present_map)[0] =
370 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK); 370 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK);
371 cpus_addr(phys_cpu_present_map)[0] |= 371 cpus_addr(voyager_phys_cpu_present_map)[0] |=
372 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8; 372 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 1) << 8;
373 cpus_addr(phys_cpu_present_map)[0] |= 373 cpus_addr(voyager_phys_cpu_present_map)[0] |=
374 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 374 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
375 2) << 16; 375 2) << 16;
376 cpus_addr(phys_cpu_present_map)[0] |= 376 cpus_addr(voyager_phys_cpu_present_map)[0] |=
377 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK + 377 voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK +
378 3) << 24; 378 3) << 24;
379 init_cpu_possible(&phys_cpu_present_map); 379 init_cpu_possible(&voyager_phys_cpu_present_map);
380 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", 380 printk("VOYAGER SMP: voyager_phys_cpu_present_map = 0x%lx\n",
381 cpus_addr(phys_cpu_present_map)[0]); 381 cpus_addr(voyager_phys_cpu_present_map)[0]);
382 /* Here we set up the VIC to enable SMP */ 382 /* Here we set up the VIC to enable SMP */
383 /* enable the CPIs by writing the base vector to their register */ 383 /* enable the CPIs by writing the base vector to their register */
384 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER); 384 outb(VIC_DEFAULT_CPI_BASE, VIC_CPI_BASE_REGISTER);
@@ -628,15 +628,15 @@ void __init smp_boot_cpus(void)
628 /* now that the cat has probed the Voyager System Bus, sanity 628 /* now that the cat has probed the Voyager System Bus, sanity
629 * check the cpu map */ 629 * check the cpu map */
630 if (((voyager_quad_processors | voyager_extended_vic_processors) 630 if (((voyager_quad_processors | voyager_extended_vic_processors)
631 & cpus_addr(phys_cpu_present_map)[0]) != 631 & cpus_addr(voyager_phys_cpu_present_map)[0]) !=
632 cpus_addr(phys_cpu_present_map)[0]) { 632 cpus_addr(voyager_phys_cpu_present_map)[0]) {
633 /* should panic */ 633 /* should panic */
634 printk("\n\n***WARNING*** " 634 printk("\n\n***WARNING*** "
635 "Sanity check of CPU present map FAILED\n"); 635 "Sanity check of CPU present map FAILED\n");
636 } 636 }
637 } else if (voyager_level == 4) 637 } else if (voyager_level == 4)
638 voyager_extended_vic_processors = 638 voyager_extended_vic_processors =
639 cpus_addr(phys_cpu_present_map)[0]; 639 cpus_addr(voyager_phys_cpu_present_map)[0];
640 640
641 /* this sets up the idle task to run on the current cpu */ 641 /* this sets up the idle task to run on the current cpu */
642 voyager_extended_cpus = 1; 642 voyager_extended_cpus = 1;
@@ -670,7 +670,7 @@ void __init smp_boot_cpus(void)
670 /* loop over all the extended VIC CPUs and boot them. The 670 /* loop over all the extended VIC CPUs and boot them. The
671 * Quad CPUs must be bootstrapped by their extended VIC cpu */ 671 * Quad CPUs must be bootstrapped by their extended VIC cpu */
672 for (i = 0; i < nr_cpu_ids; i++) { 672 for (i = 0; i < nr_cpu_ids; i++) {
673 if (i == boot_cpu_id || !cpu_isset(i, phys_cpu_present_map)) 673 if (i == boot_cpu_id || !cpu_isset(i, voyager_phys_cpu_present_map))
674 continue; 674 continue;
675 do_boot_cpu(i); 675 do_boot_cpu(i);
676 /* This udelay seems to be needed for the Quad boots 676 /* This udelay seems to be needed for the Quad boots
diff --git a/arch/x86/math-emu/fpu_aux.c b/arch/x86/math-emu/fpu_aux.c
index 491e737ce547..aa0987088774 100644
--- a/arch/x86/math-emu/fpu_aux.c
+++ b/arch/x86/math-emu/fpu_aux.c
@@ -30,20 +30,29 @@ static void fclex(void)
30} 30}
31 31
32/* Needs to be externally visible */ 32/* Needs to be externally visible */
33void finit(void) 33void finit_task(struct task_struct *tsk)
34{ 34{
35 control_word = 0x037f; 35 struct i387_soft_struct *soft = &tsk->thread.xstate->soft;
36 partial_status = 0; 36 struct address *oaddr, *iaddr;
37 top = 0; /* We don't keep top in the status word internally. */ 37 soft->cwd = 0x037f;
38 fpu_tag_word = 0xffff; 38 soft->swd = 0;
39 soft->ftop = 0; /* We don't keep top in the status word internally. */
40 soft->twd = 0xffff;
39 /* The behaviour is different from that detailed in 41 /* The behaviour is different from that detailed in
40 Section 15.1.6 of the Intel manual */ 42 Section 15.1.6 of the Intel manual */
41 operand_address.offset = 0; 43 oaddr = (struct address *)&soft->foo;
42 operand_address.selector = 0; 44 oaddr->offset = 0;
43 instruction_address.offset = 0; 45 oaddr->selector = 0;
44 instruction_address.selector = 0; 46 iaddr = (struct address *)&soft->fip;
45 instruction_address.opcode = 0; 47 iaddr->offset = 0;
46 no_ip_update = 1; 48 iaddr->selector = 0;
49 iaddr->opcode = 0;
50 soft->no_update = 1;
51}
52
53void finit(void)
54{
55 finit_task(current);
47} 56}
48 57
49/* 58/*
diff --git a/arch/x86/math-emu/fpu_entry.c b/arch/x86/math-emu/fpu_entry.c
index c7b06feb139b..5d87f586f8d7 100644
--- a/arch/x86/math-emu/fpu_entry.c
+++ b/arch/x86/math-emu/fpu_entry.c
@@ -131,7 +131,7 @@ u_char emulating = 0;
131static int valid_prefix(u_char *Byte, u_char __user ** fpu_eip, 131static int valid_prefix(u_char *Byte, u_char __user ** fpu_eip,
132 overrides * override); 132 overrides * override);
133 133
134asmlinkage void math_emulate(long arg) 134void math_emulate(struct math_emu_info *info)
135{ 135{
136 u_char FPU_modrm, byte1; 136 u_char FPU_modrm, byte1;
137 unsigned short code; 137 unsigned short code;
@@ -161,7 +161,7 @@ asmlinkage void math_emulate(long arg)
161 RE_ENTRANT_CHECK_ON; 161 RE_ENTRANT_CHECK_ON;
162#endif /* RE_ENTRANT_CHECKING */ 162#endif /* RE_ENTRANT_CHECKING */
163 163
164 SETUP_DATA_AREA(arg); 164 FPU_info = info;
165 165
166 FPU_ORIG_EIP = FPU_EIP; 166 FPU_ORIG_EIP = FPU_EIP;
167 167
@@ -659,7 +659,7 @@ static int valid_prefix(u_char *Byte, u_char __user **fpu_eip,
659 } 659 }
660} 660}
661 661
662void math_abort(struct info *info, unsigned int signal) 662void math_abort(struct math_emu_info *info, unsigned int signal)
663{ 663{
664 FPU_EIP = FPU_ORIG_EIP; 664 FPU_EIP = FPU_ORIG_EIP;
665 current->thread.trap_no = 16; 665 current->thread.trap_no = 16;
diff --git a/arch/x86/math-emu/fpu_proto.h b/arch/x86/math-emu/fpu_proto.h
index aa49b6a0d850..9779df436b7d 100644
--- a/arch/x86/math-emu/fpu_proto.h
+++ b/arch/x86/math-emu/fpu_proto.h
@@ -51,8 +51,8 @@ extern void ffreep(void);
51extern void fst_i_(void); 51extern void fst_i_(void);
52extern void fstp_i(void); 52extern void fstp_i(void);
53/* fpu_entry.c */ 53/* fpu_entry.c */
54asmlinkage extern void math_emulate(long arg); 54extern void math_emulate(struct math_emu_info *info);
55extern void math_abort(struct info *info, unsigned int signal); 55extern void math_abort(struct math_emu_info *info, unsigned int signal);
56/* fpu_etc.c */ 56/* fpu_etc.c */
57extern void FPU_etc(void); 57extern void FPU_etc(void);
58/* fpu_tags.c */ 58/* fpu_tags.c */
diff --git a/arch/x86/math-emu/fpu_system.h b/arch/x86/math-emu/fpu_system.h
index 13488fa153e0..50fa0ec2c8a5 100644
--- a/arch/x86/math-emu/fpu_system.h
+++ b/arch/x86/math-emu/fpu_system.h
@@ -16,10 +16,6 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/mm.h> 17#include <linux/mm.h>
18 18
19/* This sets the pointer FPU_info to point to the argument part
20 of the stack frame of math_emulate() */
21#define SETUP_DATA_AREA(arg) FPU_info = (struct info *) &arg
22
23/* s is always from a cpu register, and the cpu does bounds checking 19/* s is always from a cpu register, and the cpu does bounds checking
24 * during register load --> no further bounds checks needed */ 20 * during register load --> no further bounds checks needed */
25#define LDT_DESCRIPTOR(s) (((struct desc_struct *)current->mm->context.ldt)[(s) >> 3]) 21#define LDT_DESCRIPTOR(s) (((struct desc_struct *)current->mm->context.ldt)[(s) >> 3])
@@ -38,12 +34,12 @@
38#define I387 (current->thread.xstate) 34#define I387 (current->thread.xstate)
39#define FPU_info (I387->soft.info) 35#define FPU_info (I387->soft.info)
40 36
41#define FPU_CS (*(unsigned short *) &(FPU_info->___cs)) 37#define FPU_CS (*(unsigned short *) &(FPU_info->regs->cs))
42#define FPU_SS (*(unsigned short *) &(FPU_info->___ss)) 38#define FPU_SS (*(unsigned short *) &(FPU_info->regs->ss))
43#define FPU_DS (*(unsigned short *) &(FPU_info->___ds)) 39#define FPU_DS (*(unsigned short *) &(FPU_info->regs->ds))
44#define FPU_EAX (FPU_info->___eax) 40#define FPU_EAX (FPU_info->regs->ax)
45#define FPU_EFLAGS (FPU_info->___eflags) 41#define FPU_EFLAGS (FPU_info->regs->flags)
46#define FPU_EIP (FPU_info->___eip) 42#define FPU_EIP (FPU_info->regs->ip)
47#define FPU_ORIG_EIP (FPU_info->___orig_eip) 43#define FPU_ORIG_EIP (FPU_info->___orig_eip)
48 44
49#define FPU_lookahead (I387->soft.lookahead) 45#define FPU_lookahead (I387->soft.lookahead)
diff --git a/arch/x86/math-emu/get_address.c b/arch/x86/math-emu/get_address.c
index d701e2b39e44..420b3b6e3915 100644
--- a/arch/x86/math-emu/get_address.c
+++ b/arch/x86/math-emu/get_address.c
@@ -29,46 +29,43 @@
29#define FPU_WRITE_BIT 0x10 29#define FPU_WRITE_BIT 0x10
30 30
31static int reg_offset[] = { 31static int reg_offset[] = {
32 offsetof(struct info, ___eax), 32 offsetof(struct pt_regs, ax),
33 offsetof(struct info, ___ecx), 33 offsetof(struct pt_regs, cx),
34 offsetof(struct info, ___edx), 34 offsetof(struct pt_regs, dx),
35 offsetof(struct info, ___ebx), 35 offsetof(struct pt_regs, bx),
36 offsetof(struct info, ___esp), 36 offsetof(struct pt_regs, sp),
37 offsetof(struct info, ___ebp), 37 offsetof(struct pt_regs, bp),
38 offsetof(struct info, ___esi), 38 offsetof(struct pt_regs, si),
39 offsetof(struct info, ___edi) 39 offsetof(struct pt_regs, di)
40}; 40};
41 41
42#define REG_(x) (*(long *)(reg_offset[(x)]+(u_char *) FPU_info)) 42#define REG_(x) (*(long *)(reg_offset[(x)] + (u_char *)FPU_info->regs))
43 43
44static int reg_offset_vm86[] = { 44static int reg_offset_vm86[] = {
45 offsetof(struct info, ___cs), 45 offsetof(struct pt_regs, cs),
46 offsetof(struct info, ___vm86_ds), 46 offsetof(struct kernel_vm86_regs, ds),
47 offsetof(struct info, ___vm86_es), 47 offsetof(struct kernel_vm86_regs, es),
48 offsetof(struct info, ___vm86_fs), 48 offsetof(struct kernel_vm86_regs, fs),
49 offsetof(struct info, ___vm86_gs), 49 offsetof(struct kernel_vm86_regs, gs),
50 offsetof(struct info, ___ss), 50 offsetof(struct pt_regs, ss),
51 offsetof(struct info, ___vm86_ds) 51 offsetof(struct kernel_vm86_regs, ds)
52}; 52};
53 53
54#define VM86_REG_(x) (*(unsigned short *) \ 54#define VM86_REG_(x) (*(unsigned short *) \
55 (reg_offset_vm86[((unsigned)x)]+(u_char *) FPU_info)) 55 (reg_offset_vm86[((unsigned)x)] + (u_char *)FPU_info->regs))
56
57/* This dummy, gs is not saved on the stack. */
58#define ___GS ___ds
59 56
60static int reg_offset_pm[] = { 57static int reg_offset_pm[] = {
61 offsetof(struct info, ___cs), 58 offsetof(struct pt_regs, cs),
62 offsetof(struct info, ___ds), 59 offsetof(struct pt_regs, ds),
63 offsetof(struct info, ___es), 60 offsetof(struct pt_regs, es),
64 offsetof(struct info, ___fs), 61 offsetof(struct pt_regs, fs),
65 offsetof(struct info, ___GS), 62 offsetof(struct pt_regs, ds), /* dummy, not saved on stack */
66 offsetof(struct info, ___ss), 63 offsetof(struct pt_regs, ss),
67 offsetof(struct info, ___ds) 64 offsetof(struct pt_regs, ds)
68}; 65};
69 66
70#define PM_REG_(x) (*(unsigned short *) \ 67#define PM_REG_(x) (*(unsigned short *) \
71 (reg_offset_pm[((unsigned)x)]+(u_char *) FPU_info)) 68 (reg_offset_pm[((unsigned)x)] + (u_char *)FPU_info->regs))
72 69
73/* Decode the SIB byte. This function assumes mod != 0 */ 70/* Decode the SIB byte. This function assumes mod != 0 */
74static int sib(int mod, unsigned long *fpu_eip) 71static int sib(int mod, unsigned long *fpu_eip)
@@ -349,34 +346,34 @@ void __user *FPU_get_address_16(u_char FPU_modrm, unsigned long *fpu_eip,
349 } 346 }
350 switch (rm) { 347 switch (rm) {
351 case 0: 348 case 0:
352 address += FPU_info->___ebx + FPU_info->___esi; 349 address += FPU_info->regs->bx + FPU_info->regs->si;
353 break; 350 break;
354 case 1: 351 case 1:
355 address += FPU_info->___ebx + FPU_info->___edi; 352 address += FPU_info->regs->bx + FPU_info->regs->di;
356 break; 353 break;
357 case 2: 354 case 2:
358 address += FPU_info->___ebp + FPU_info->___esi; 355 address += FPU_info->regs->bp + FPU_info->regs->si;
359 if (addr_modes.override.segment == PREFIX_DEFAULT) 356 if (addr_modes.override.segment == PREFIX_DEFAULT)
360 addr_modes.override.segment = PREFIX_SS_; 357 addr_modes.override.segment = PREFIX_SS_;
361 break; 358 break;
362 case 3: 359 case 3:
363 address += FPU_info->___ebp + FPU_info->___edi; 360 address += FPU_info->regs->bp + FPU_info->regs->di;
364 if (addr_modes.override.segment == PREFIX_DEFAULT) 361 if (addr_modes.override.segment == PREFIX_DEFAULT)
365 addr_modes.override.segment = PREFIX_SS_; 362 addr_modes.override.segment = PREFIX_SS_;
366 break; 363 break;
367 case 4: 364 case 4:
368 address += FPU_info->___esi; 365 address += FPU_info->regs->si;
369 break; 366 break;
370 case 5: 367 case 5:
371 address += FPU_info->___edi; 368 address += FPU_info->regs->di;
372 break; 369 break;
373 case 6: 370 case 6:
374 address += FPU_info->___ebp; 371 address += FPU_info->regs->bp;
375 if (addr_modes.override.segment == PREFIX_DEFAULT) 372 if (addr_modes.override.segment == PREFIX_DEFAULT)
376 addr_modes.override.segment = PREFIX_SS_; 373 addr_modes.override.segment = PREFIX_SS_;
377 break; 374 break;
378 case 7: 375 case 7:
379 address += FPU_info->___ebx; 376 address += FPU_info->regs->bx;
380 break; 377 break;
381 } 378 }
382 379
diff --git a/arch/x86/mm/init_64.c b/arch/x86/mm/init_64.c
index e6d36b490250..b1352250096e 100644
--- a/arch/x86/mm/init_64.c
+++ b/arch/x86/mm/init_64.c
@@ -714,6 +714,8 @@ unsigned long __init_refok init_memory_mapping(unsigned long start,
714 pos = start_pfn << PAGE_SHIFT; 714 pos = start_pfn << PAGE_SHIFT;
715 end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT) 715 end_pfn = ((pos + (PMD_SIZE - 1)) >> PMD_SHIFT)
716 << (PMD_SHIFT - PAGE_SHIFT); 716 << (PMD_SHIFT - PAGE_SHIFT);
717 if (end_pfn > (end >> PAGE_SHIFT))
718 end_pfn = end >> PAGE_SHIFT;
717 if (start_pfn < end_pfn) { 719 if (start_pfn < end_pfn) {
718 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0); 720 nr_range = save_mr(mr, nr_range, start_pfn, end_pfn, 0);
719 pos = end_pfn << PAGE_SHIFT; 721 pos = end_pfn << PAGE_SHIFT;
diff --git a/arch/x86/mm/iomap_32.c b/arch/x86/mm/iomap_32.c
index ca53224fc56c..04102d42ff42 100644
--- a/arch/x86/mm/iomap_32.c
+++ b/arch/x86/mm/iomap_32.c
@@ -20,6 +20,17 @@
20#include <asm/pat.h> 20#include <asm/pat.h>
21#include <linux/module.h> 21#include <linux/module.h>
22 22
23int is_io_mapping_possible(resource_size_t base, unsigned long size)
24{
25#ifndef CONFIG_X86_PAE
26 /* There is no way to map greater than 1 << 32 address without PAE */
27 if (base + size > 0x100000000ULL)
28 return 0;
29#endif
30 return 1;
31}
32EXPORT_SYMBOL_GPL(is_io_mapping_possible);
33
23/* Map 'pfn' using fixed map 'type' and protections 'prot' 34/* Map 'pfn' using fixed map 'type' and protections 'prot'
24 */ 35 */
25void * 36void *
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index af750ab973b6..f45d5e29a72e 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -134,25 +134,6 @@ int page_is_ram(unsigned long pagenr)
134 return 0; 134 return 0;
135} 135}
136 136
137int pagerange_is_ram(unsigned long start, unsigned long end)
138{
139 int ram_page = 0, not_rampage = 0;
140 unsigned long page_nr;
141
142 for (page_nr = (start >> PAGE_SHIFT); page_nr < (end >> PAGE_SHIFT);
143 ++page_nr) {
144 if (page_is_ram(page_nr))
145 ram_page = 1;
146 else
147 not_rampage = 1;
148
149 if (ram_page == not_rampage)
150 return -1;
151 }
152
153 return ram_page;
154}
155
156/* 137/*
157 * Fix up the linear direct mapping of the kernel to avoid cache attribute 138 * Fix up the linear direct mapping of the kernel to avoid cache attribute
158 * conflicts. 139 * conflicts.
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c
index 93d82038af4b..6a518dd08a36 100644
--- a/arch/x86/mm/kmmio.c
+++ b/arch/x86/mm/kmmio.c
@@ -32,11 +32,14 @@ struct kmmio_fault_page {
32 struct list_head list; 32 struct list_head list;
33 struct kmmio_fault_page *release_next; 33 struct kmmio_fault_page *release_next;
34 unsigned long page; /* location of the fault page */ 34 unsigned long page; /* location of the fault page */
35 bool old_presence; /* page presence prior to arming */
36 bool armed;
35 37
36 /* 38 /*
37 * Number of times this page has been registered as a part 39 * Number of times this page has been registered as a part
38 * of a probe. If zero, page is disarmed and this may be freed. 40 * of a probe. If zero, page is disarmed and this may be freed.
39 * Used only by writers (RCU). 41 * Used only by writers (RCU) and post_kmmio_handler().
42 * Protected by kmmio_lock, when linked into kmmio_page_table.
40 */ 43 */
41 int count; 44 int count;
42}; 45};
@@ -105,57 +108,85 @@ static struct kmmio_fault_page *get_kmmio_fault_page(unsigned long page)
105 return NULL; 108 return NULL;
106} 109}
107 110
108static void set_page_present(unsigned long addr, bool present, 111static void set_pmd_presence(pmd_t *pmd, bool present, bool *old)
109 unsigned int *pglevel) 112{
113 pmdval_t v = pmd_val(*pmd);
114 *old = !!(v & _PAGE_PRESENT);
115 v &= ~_PAGE_PRESENT;
116 if (present)
117 v |= _PAGE_PRESENT;
118 set_pmd(pmd, __pmd(v));
119}
120
121static void set_pte_presence(pte_t *pte, bool present, bool *old)
122{
123 pteval_t v = pte_val(*pte);
124 *old = !!(v & _PAGE_PRESENT);
125 v &= ~_PAGE_PRESENT;
126 if (present)
127 v |= _PAGE_PRESENT;
128 set_pte_atomic(pte, __pte(v));
129}
130
131static int set_page_presence(unsigned long addr, bool present, bool *old)
110{ 132{
111 pteval_t pteval;
112 pmdval_t pmdval;
113 unsigned int level; 133 unsigned int level;
114 pmd_t *pmd;
115 pte_t *pte = lookup_address(addr, &level); 134 pte_t *pte = lookup_address(addr, &level);
116 135
117 if (!pte) { 136 if (!pte) {
118 pr_err("kmmio: no pte for page 0x%08lx\n", addr); 137 pr_err("kmmio: no pte for page 0x%08lx\n", addr);
119 return; 138 return -1;
120 } 139 }
121 140
122 if (pglevel)
123 *pglevel = level;
124
125 switch (level) { 141 switch (level) {
126 case PG_LEVEL_2M: 142 case PG_LEVEL_2M:
127 pmd = (pmd_t *)pte; 143 set_pmd_presence((pmd_t *)pte, present, old);
128 pmdval = pmd_val(*pmd) & ~_PAGE_PRESENT;
129 if (present)
130 pmdval |= _PAGE_PRESENT;
131 set_pmd(pmd, __pmd(pmdval));
132 break; 144 break;
133
134 case PG_LEVEL_4K: 145 case PG_LEVEL_4K:
135 pteval = pte_val(*pte) & ~_PAGE_PRESENT; 146 set_pte_presence(pte, present, old);
136 if (present)
137 pteval |= _PAGE_PRESENT;
138 set_pte_atomic(pte, __pte(pteval));
139 break; 147 break;
140
141 default: 148 default:
142 pr_err("kmmio: unexpected page level 0x%x.\n", level); 149 pr_err("kmmio: unexpected page level 0x%x.\n", level);
143 return; 150 return -1;
144 } 151 }
145 152
146 __flush_tlb_one(addr); 153 __flush_tlb_one(addr);
154 return 0;
147} 155}
148 156
149/** Mark the given page as not present. Access to it will trigger a fault. */ 157/*
150static void arm_kmmio_fault_page(unsigned long page, unsigned int *pglevel) 158 * Mark the given page as not present. Access to it will trigger a fault.
159 *
160 * Struct kmmio_fault_page is protected by RCU and kmmio_lock, but the
161 * protection is ignored here. RCU read lock is assumed held, so the struct
162 * will not disappear unexpectedly. Furthermore, the caller must guarantee,
163 * that double arming the same virtual address (page) cannot occur.
164 *
165 * Double disarming on the other hand is allowed, and may occur when a fault
166 * and mmiotrace shutdown happen simultaneously.
167 */
168static int arm_kmmio_fault_page(struct kmmio_fault_page *f)
151{ 169{
152 set_page_present(page & PAGE_MASK, false, pglevel); 170 int ret;
171 WARN_ONCE(f->armed, KERN_ERR "kmmio page already armed.\n");
172 if (f->armed) {
173 pr_warning("kmmio double-arm: page 0x%08lx, ref %d, old %d\n",
174 f->page, f->count, f->old_presence);
175 }
176 ret = set_page_presence(f->page, false, &f->old_presence);
177 WARN_ONCE(ret < 0, KERN_ERR "kmmio arming 0x%08lx failed.\n", f->page);
178 f->armed = true;
179 return ret;
153} 180}
154 181
155/** Mark the given page as present. */ 182/** Restore the given page to saved presence state. */
156static void disarm_kmmio_fault_page(unsigned long page, unsigned int *pglevel) 183static void disarm_kmmio_fault_page(struct kmmio_fault_page *f)
157{ 184{
158 set_page_present(page & PAGE_MASK, true, pglevel); 185 bool tmp;
186 int ret = set_page_presence(f->page, f->old_presence, &tmp);
187 WARN_ONCE(ret < 0,
188 KERN_ERR "kmmio disarming 0x%08lx failed.\n", f->page);
189 f->armed = false;
159} 190}
160 191
161/* 192/*
@@ -202,28 +233,32 @@ int kmmio_handler(struct pt_regs *regs, unsigned long addr)
202 233
203 ctx = &get_cpu_var(kmmio_ctx); 234 ctx = &get_cpu_var(kmmio_ctx);
204 if (ctx->active) { 235 if (ctx->active) {
205 disarm_kmmio_fault_page(faultpage->page, NULL);
206 if (addr == ctx->addr) { 236 if (addr == ctx->addr) {
207 /* 237 /*
208 * On SMP we sometimes get recursive probe hits on the 238 * A second fault on the same page means some other
209 * same address. Context is already saved, fall out. 239 * condition needs handling by do_page_fault(), the
240 * page really not being present is the most common.
210 */ 241 */
211 pr_debug("kmmio: duplicate probe hit on CPU %d, for " 242 pr_debug("kmmio: secondary hit for 0x%08lx CPU %d.\n",
212 "address 0x%08lx.\n", 243 addr, smp_processor_id());
213 smp_processor_id(), addr); 244
214 ret = 1; 245 if (!faultpage->old_presence)
215 goto no_kmmio_ctx; 246 pr_info("kmmio: unexpected secondary hit for "
216 } 247 "address 0x%08lx on CPU %d.\n", addr,
217 /* 248 smp_processor_id());
218 * Prevent overwriting already in-flight context. 249 } else {
219 * This should not happen, let's hope disarming at least 250 /*
220 * prevents a panic. 251 * Prevent overwriting already in-flight context.
221 */ 252 * This should not happen, let's hope disarming at
222 pr_emerg("kmmio: recursive probe hit on CPU %d, " 253 * least prevents a panic.
254 */
255 pr_emerg("kmmio: recursive probe hit on CPU %d, "
223 "for address 0x%08lx. Ignoring.\n", 256 "for address 0x%08lx. Ignoring.\n",
224 smp_processor_id(), addr); 257 smp_processor_id(), addr);
225 pr_emerg("kmmio: previous hit was at 0x%08lx.\n", 258 pr_emerg("kmmio: previous hit was at 0x%08lx.\n",
226 ctx->addr); 259 ctx->addr);
260 disarm_kmmio_fault_page(faultpage);
261 }
227 goto no_kmmio_ctx; 262 goto no_kmmio_ctx;
228 } 263 }
229 ctx->active++; 264 ctx->active++;
@@ -244,7 +279,7 @@ int kmmio_handler(struct pt_regs *regs, unsigned long addr)
244 regs->flags &= ~X86_EFLAGS_IF; 279 regs->flags &= ~X86_EFLAGS_IF;
245 280
246 /* Now we set present bit in PTE and single step. */ 281 /* Now we set present bit in PTE and single step. */
247 disarm_kmmio_fault_page(ctx->fpage->page, NULL); 282 disarm_kmmio_fault_page(ctx->fpage);
248 283
249 /* 284 /*
250 * If another cpu accesses the same page while we are stepping, 285 * If another cpu accesses the same page while we are stepping,
@@ -275,7 +310,7 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
275 struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx); 310 struct kmmio_context *ctx = &get_cpu_var(kmmio_ctx);
276 311
277 if (!ctx->active) { 312 if (!ctx->active) {
278 pr_debug("kmmio: spurious debug trap on CPU %d.\n", 313 pr_warning("kmmio: spurious debug trap on CPU %d.\n",
279 smp_processor_id()); 314 smp_processor_id());
280 goto out; 315 goto out;
281 } 316 }
@@ -283,7 +318,11 @@ static int post_kmmio_handler(unsigned long condition, struct pt_regs *regs)
283 if (ctx->probe && ctx->probe->post_handler) 318 if (ctx->probe && ctx->probe->post_handler)
284 ctx->probe->post_handler(ctx->probe, condition, regs); 319 ctx->probe->post_handler(ctx->probe, condition, regs);
285 320
286 arm_kmmio_fault_page(ctx->fpage->page, NULL); 321 /* Prevent racing against release_kmmio_fault_page(). */
322 spin_lock(&kmmio_lock);
323 if (ctx->fpage->count)
324 arm_kmmio_fault_page(ctx->fpage);
325 spin_unlock(&kmmio_lock);
287 326
288 regs->flags &= ~X86_EFLAGS_TF; 327 regs->flags &= ~X86_EFLAGS_TF;
289 regs->flags |= ctx->saved_flags; 328 regs->flags |= ctx->saved_flags;
@@ -315,20 +354,24 @@ static int add_kmmio_fault_page(unsigned long page)
315 f = get_kmmio_fault_page(page); 354 f = get_kmmio_fault_page(page);
316 if (f) { 355 if (f) {
317 if (!f->count) 356 if (!f->count)
318 arm_kmmio_fault_page(f->page, NULL); 357 arm_kmmio_fault_page(f);
319 f->count++; 358 f->count++;
320 return 0; 359 return 0;
321 } 360 }
322 361
323 f = kmalloc(sizeof(*f), GFP_ATOMIC); 362 f = kzalloc(sizeof(*f), GFP_ATOMIC);
324 if (!f) 363 if (!f)
325 return -1; 364 return -1;
326 365
327 f->count = 1; 366 f->count = 1;
328 f->page = page; 367 f->page = page;
329 list_add_rcu(&f->list, kmmio_page_list(f->page));
330 368
331 arm_kmmio_fault_page(f->page, NULL); 369 if (arm_kmmio_fault_page(f)) {
370 kfree(f);
371 return -1;
372 }
373
374 list_add_rcu(&f->list, kmmio_page_list(f->page));
332 375
333 return 0; 376 return 0;
334} 377}
@@ -347,7 +390,7 @@ static void release_kmmio_fault_page(unsigned long page,
347 f->count--; 390 f->count--;
348 BUG_ON(f->count < 0); 391 BUG_ON(f->count < 0);
349 if (!f->count) { 392 if (!f->count) {
350 disarm_kmmio_fault_page(f->page, NULL); 393 disarm_kmmio_fault_page(f);
351 f->release_next = *release_list; 394 f->release_next = *release_list;
352 *release_list = f; 395 *release_list = f;
353 } 396 }
@@ -408,23 +451,24 @@ static void rcu_free_kmmio_fault_pages(struct rcu_head *head)
408 451
409static void remove_kmmio_fault_pages(struct rcu_head *head) 452static void remove_kmmio_fault_pages(struct rcu_head *head)
410{ 453{
411 struct kmmio_delayed_release *dr = container_of( 454 struct kmmio_delayed_release *dr =
412 head, 455 container_of(head, struct kmmio_delayed_release, rcu);
413 struct kmmio_delayed_release,
414 rcu);
415 struct kmmio_fault_page *p = dr->release_list; 456 struct kmmio_fault_page *p = dr->release_list;
416 struct kmmio_fault_page **prevp = &dr->release_list; 457 struct kmmio_fault_page **prevp = &dr->release_list;
417 unsigned long flags; 458 unsigned long flags;
459
418 spin_lock_irqsave(&kmmio_lock, flags); 460 spin_lock_irqsave(&kmmio_lock, flags);
419 while (p) { 461 while (p) {
420 if (!p->count) 462 if (!p->count) {
421 list_del_rcu(&p->list); 463 list_del_rcu(&p->list);
422 else 464 prevp = &p->release_next;
465 } else {
423 *prevp = p->release_next; 466 *prevp = p->release_next;
424 prevp = &p->release_next; 467 }
425 p = p->release_next; 468 p = p->release_next;
426 } 469 }
427 spin_unlock_irqrestore(&kmmio_lock, flags); 470 spin_unlock_irqrestore(&kmmio_lock, flags);
471
428 /* This is the real RCU destroy call. */ 472 /* This is the real RCU destroy call. */
429 call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages); 473 call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages);
430} 474}
diff --git a/arch/x86/mm/numa_64.c b/arch/x86/mm/numa_64.c
index 71a14f89f89e..f3516da035d1 100644
--- a/arch/x86/mm/numa_64.c
+++ b/arch/x86/mm/numa_64.c
@@ -145,7 +145,7 @@ int __init compute_hash_shift(struct bootnode *nodes, int numnodes,
145 return shift; 145 return shift;
146} 146}
147 147
148int early_pfn_to_nid(unsigned long pfn) 148int __meminit __early_pfn_to_nid(unsigned long pfn)
149{ 149{
150 return phys_to_nid(pfn << PAGE_SHIFT); 150 return phys_to_nid(pfn << PAGE_SHIFT);
151} 151}
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c
index 84ba74820ad6..7be47d1a97e4 100644
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -508,18 +508,13 @@ static int split_large_page(pte_t *kpte, unsigned long address)
508#endif 508#endif
509 509
510 /* 510 /*
511 * Install the new, split up pagetable. Important details here: 511 * Install the new, split up pagetable.
512 * 512 *
513 * On Intel the NX bit of all levels must be cleared to make a 513 * We use the standard kernel pagetable protections for the new
514 * page executable. See section 4.13.2 of Intel 64 and IA-32 514 * pagetable protections, the actual ptes set above control the
515 * Architectures Software Developer's Manual). 515 * primary protection behavior:
516 *
517 * Mark the entry present. The current mapping might be
518 * set to not present, which we preserved above.
519 */ 516 */
520 ref_prot = pte_pgprot(pte_mkexec(pte_clrhuge(*kpte))); 517 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
521 pgprot_val(ref_prot) |= _PAGE_PRESENT;
522 __set_pmd_pte(kpte, address, mk_pte(base, ref_prot));
523 base = NULL; 518 base = NULL;
524 519
525out_unlock: 520out_unlock:
@@ -575,7 +570,6 @@ static int __change_page_attr(struct cpa_data *cpa, int primary)
575 address = cpa->vaddr[cpa->curpage]; 570 address = cpa->vaddr[cpa->curpage];
576 else 571 else
577 address = *cpa->vaddr; 572 address = *cpa->vaddr;
578
579repeat: 573repeat:
580 kpte = lookup_address(address, &level); 574 kpte = lookup_address(address, &level);
581 if (!kpte) 575 if (!kpte)
@@ -812,6 +806,13 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
812 806
813 vm_unmap_aliases(); 807 vm_unmap_aliases();
814 808
809 /*
810 * If we're called with lazy mmu updates enabled, the
811 * in-memory pte state may be stale. Flush pending updates to
812 * bring them up to date.
813 */
814 arch_flush_lazy_mmu_mode();
815
815 cpa.vaddr = addr; 816 cpa.vaddr = addr;
816 cpa.numpages = numpages; 817 cpa.numpages = numpages;
817 cpa.mask_set = mask_set; 818 cpa.mask_set = mask_set;
@@ -854,6 +855,13 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
854 } else 855 } else
855 cpa_flush_all(cache); 856 cpa_flush_all(cache);
856 857
858 /*
859 * If we've been called with lazy mmu updates enabled, then
860 * make sure that everything gets flushed out before we
861 * return.
862 */
863 arch_flush_lazy_mmu_mode();
864
857out: 865out:
858 return ret; 866 return ret;
859} 867}
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 7b61036427df..e0ab173b6974 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -11,6 +11,7 @@
11#include <linux/bootmem.h> 11#include <linux/bootmem.h>
12#include <linux/debugfs.h> 12#include <linux/debugfs.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/module.h>
14#include <linux/gfp.h> 15#include <linux/gfp.h>
15#include <linux/mm.h> 16#include <linux/mm.h>
16#include <linux/fs.h> 17#include <linux/fs.h>
@@ -211,6 +212,33 @@ chk_conflict(struct memtype *new, struct memtype *entry, unsigned long *type)
211static struct memtype *cached_entry; 212static struct memtype *cached_entry;
212static u64 cached_start; 213static u64 cached_start;
213 214
215static int pat_pagerange_is_ram(unsigned long start, unsigned long end)
216{
217 int ram_page = 0, not_rampage = 0;
218 unsigned long page_nr;
219
220 for (page_nr = (start >> PAGE_SHIFT); page_nr < (end >> PAGE_SHIFT);
221 ++page_nr) {
222 /*
223 * For legacy reasons, physical address range in the legacy ISA
224 * region is tracked as non-RAM. This will allow users of
225 * /dev/mem to map portions of legacy ISA region, even when
226 * some of those portions are listed(or not even listed) with
227 * different e820 types(RAM/reserved/..)
228 */
229 if (page_nr >= (ISA_END_ADDRESS >> PAGE_SHIFT) &&
230 page_is_ram(page_nr))
231 ram_page = 1;
232 else
233 not_rampage = 1;
234
235 if (ram_page == not_rampage)
236 return -1;
237 }
238
239 return ram_page;
240}
241
214/* 242/*
215 * For RAM pages, mark the pages as non WB memory type using 243 * For RAM pages, mark the pages as non WB memory type using
216 * PageNonWB (PG_arch_1). We allow only one set_memory_uc() or 244 * PageNonWB (PG_arch_1). We allow only one set_memory_uc() or
@@ -336,20 +364,12 @@ int reserve_memtype(u64 start, u64 end, unsigned long req_type,
336 if (new_type) 364 if (new_type)
337 *new_type = actual_type; 365 *new_type = actual_type;
338 366
339 /* 367 is_range_ram = pat_pagerange_is_ram(start, end);
340 * For legacy reasons, some parts of the physical address range in the 368 if (is_range_ram == 1)
341 * legacy 1MB region is treated as non-RAM (even when listed as RAM in 369 return reserve_ram_pages_type(start, end, req_type,
342 * the e820 tables). So we will track the memory attributes of this 370 new_type);
343 * legacy 1MB region using the linear memtype_list always. 371 else if (is_range_ram < 0)
344 */ 372 return -EINVAL;
345 if (end >= ISA_END_ADDRESS) {
346 is_range_ram = pagerange_is_ram(start, end);
347 if (is_range_ram == 1)
348 return reserve_ram_pages_type(start, end, req_type,
349 new_type);
350 else if (is_range_ram < 0)
351 return -EINVAL;
352 }
353 373
354 new = kmalloc(sizeof(struct memtype), GFP_KERNEL); 374 new = kmalloc(sizeof(struct memtype), GFP_KERNEL);
355 if (!new) 375 if (!new)
@@ -446,19 +466,11 @@ int free_memtype(u64 start, u64 end)
446 if (is_ISA_range(start, end - 1)) 466 if (is_ISA_range(start, end - 1))
447 return 0; 467 return 0;
448 468
449 /* 469 is_range_ram = pat_pagerange_is_ram(start, end);
450 * For legacy reasons, some parts of the physical address range in the 470 if (is_range_ram == 1)
451 * legacy 1MB region is treated as non-RAM (even when listed as RAM in 471 return free_ram_pages_type(start, end);
452 * the e820 tables). So we will track the memory attributes of this 472 else if (is_range_ram < 0)
453 * legacy 1MB region using the linear memtype_list always. 473 return -EINVAL;
454 */
455 if (end >= ISA_END_ADDRESS) {
456 is_range_ram = pagerange_is_ram(start, end);
457 if (is_range_ram == 1)
458 return free_ram_pages_type(start, end);
459 else if (is_range_ram < 0)
460 return -EINVAL;
461 }
462 474
463 spin_lock(&memtype_lock); 475 spin_lock(&memtype_lock);
464 list_for_each_entry(entry, &memtype_list, nd) { 476 list_for_each_entry(entry, &memtype_list, nd) {
@@ -626,17 +638,13 @@ static int reserve_pfn_range(u64 paddr, unsigned long size, pgprot_t *vma_prot,
626 unsigned long flags; 638 unsigned long flags;
627 unsigned long want_flags = (pgprot_val(*vma_prot) & _PAGE_CACHE_MASK); 639 unsigned long want_flags = (pgprot_val(*vma_prot) & _PAGE_CACHE_MASK);
628 640
629 is_ram = pagerange_is_ram(paddr, paddr + size); 641 is_ram = pat_pagerange_is_ram(paddr, paddr + size);
630 642
631 if (is_ram != 0) { 643 /*
632 /* 644 * reserve_pfn_range() doesn't support RAM pages.
633 * For mapping RAM pages, drivers need to call 645 */
634 * set_memory_[uc|wc|wb] directly, for reserve and free, before 646 if (is_ram != 0)
635 * setting up the PTE. 647 return -EINVAL;
636 */
637 WARN_ON_ONCE(1);
638 return 0;
639 }
640 648
641 ret = reserve_memtype(paddr, paddr + size, want_flags, &flags); 649 ret = reserve_memtype(paddr, paddr + size, want_flags, &flags);
642 if (ret) 650 if (ret)
@@ -693,7 +701,7 @@ static void free_pfn_range(u64 paddr, unsigned long size)
693{ 701{
694 int is_ram; 702 int is_ram;
695 703
696 is_ram = pagerange_is_ram(paddr, paddr + size); 704 is_ram = pat_pagerange_is_ram(paddr, paddr + size);
697 if (is_ram == 0) 705 if (is_ram == 0)
698 free_memtype(paddr, paddr + size); 706 free_memtype(paddr, paddr + size);
699} 707}
@@ -861,6 +869,7 @@ pgprot_t pgprot_writecombine(pgprot_t prot)
861 else 869 else
862 return pgprot_noncached(prot); 870 return pgprot_noncached(prot);
863} 871}
872EXPORT_SYMBOL_GPL(pgprot_writecombine);
864 873
865#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT) 874#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_X86_PAT)
866 875
diff --git a/arch/x86/mm/testmmiotrace.c b/arch/x86/mm/testmmiotrace.c
index ab50a8d7402c..427fd1b56df5 100644
--- a/arch/x86/mm/testmmiotrace.c
+++ b/arch/x86/mm/testmmiotrace.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Written by Pekka Paalanen, 2008 <pq@iki.fi> 2 * Written by Pekka Paalanen, 2008-2009 <pq@iki.fi>
3 */ 3 */
4#include <linux/module.h> 4#include <linux/module.h>
5#include <linux/io.h> 5#include <linux/io.h>
@@ -9,35 +9,74 @@
9 9
10static unsigned long mmio_address; 10static unsigned long mmio_address;
11module_param(mmio_address, ulong, 0); 11module_param(mmio_address, ulong, 0);
12MODULE_PARM_DESC(mmio_address, "Start address of the mapping of 16 kB."); 12MODULE_PARM_DESC(mmio_address, " Start address of the mapping of 16 kB "
13 "(or 8 MB if read_far is non-zero).");
14
15static unsigned long read_far = 0x400100;
16module_param(read_far, ulong, 0);
17MODULE_PARM_DESC(read_far, " Offset of a 32-bit read within 8 MB "
18 "(default: 0x400100).");
19
20static unsigned v16(unsigned i)
21{
22 return i * 12 + 7;
23}
24
25static unsigned v32(unsigned i)
26{
27 return i * 212371 + 13;
28}
13 29
14static void do_write_test(void __iomem *p) 30static void do_write_test(void __iomem *p)
15{ 31{
16 unsigned int i; 32 unsigned int i;
33 pr_info(MODULE_NAME ": write test.\n");
17 mmiotrace_printk("Write test.\n"); 34 mmiotrace_printk("Write test.\n");
35
18 for (i = 0; i < 256; i++) 36 for (i = 0; i < 256; i++)
19 iowrite8(i, p + i); 37 iowrite8(i, p + i);
38
20 for (i = 1024; i < (5 * 1024); i += 2) 39 for (i = 1024; i < (5 * 1024); i += 2)
21 iowrite16(i * 12 + 7, p + i); 40 iowrite16(v16(i), p + i);
41
22 for (i = (5 * 1024); i < (16 * 1024); i += 4) 42 for (i = (5 * 1024); i < (16 * 1024); i += 4)
23 iowrite32(i * 212371 + 13, p + i); 43 iowrite32(v32(i), p + i);
24} 44}
25 45
26static void do_read_test(void __iomem *p) 46static void do_read_test(void __iomem *p)
27{ 47{
28 unsigned int i; 48 unsigned int i;
49 unsigned errs[3] = { 0 };
50 pr_info(MODULE_NAME ": read test.\n");
29 mmiotrace_printk("Read test.\n"); 51 mmiotrace_printk("Read test.\n");
52
30 for (i = 0; i < 256; i++) 53 for (i = 0; i < 256; i++)
31 ioread8(p + i); 54 if (ioread8(p + i) != i)
55 ++errs[0];
56
32 for (i = 1024; i < (5 * 1024); i += 2) 57 for (i = 1024; i < (5 * 1024); i += 2)
33 ioread16(p + i); 58 if (ioread16(p + i) != v16(i))
59 ++errs[1];
60
34 for (i = (5 * 1024); i < (16 * 1024); i += 4) 61 for (i = (5 * 1024); i < (16 * 1024); i += 4)
35 ioread32(p + i); 62 if (ioread32(p + i) != v32(i))
63 ++errs[2];
64
65 mmiotrace_printk("Read errors: 8-bit %d, 16-bit %d, 32-bit %d.\n",
66 errs[0], errs[1], errs[2]);
36} 67}
37 68
38static void do_test(void) 69static void do_read_far_test(void __iomem *p)
39{ 70{
40 void __iomem *p = ioremap_nocache(mmio_address, 0x4000); 71 pr_info(MODULE_NAME ": read far test.\n");
72 mmiotrace_printk("Read far test.\n");
73
74 ioread32(p + read_far);
75}
76
77static void do_test(unsigned long size)
78{
79 void __iomem *p = ioremap_nocache(mmio_address, size);
41 if (!p) { 80 if (!p) {
42 pr_err(MODULE_NAME ": could not ioremap, aborting.\n"); 81 pr_err(MODULE_NAME ": could not ioremap, aborting.\n");
43 return; 82 return;
@@ -45,11 +84,15 @@ static void do_test(void)
45 mmiotrace_printk("ioremap returned %p.\n", p); 84 mmiotrace_printk("ioremap returned %p.\n", p);
46 do_write_test(p); 85 do_write_test(p);
47 do_read_test(p); 86 do_read_test(p);
87 if (read_far && read_far < size - 4)
88 do_read_far_test(p);
48 iounmap(p); 89 iounmap(p);
49} 90}
50 91
51static int __init init(void) 92static int __init init(void)
52{ 93{
94 unsigned long size = (read_far) ? (8 << 20) : (16 << 10);
95
53 if (mmio_address == 0) { 96 if (mmio_address == 0) {
54 pr_err(MODULE_NAME ": you have to use the module argument " 97 pr_err(MODULE_NAME ": you have to use the module argument "
55 "mmio_address.\n"); 98 "mmio_address.\n");
@@ -58,10 +101,11 @@ static int __init init(void)
58 return -ENXIO; 101 return -ENXIO;
59 } 102 }
60 103
61 pr_warning(MODULE_NAME ": WARNING: mapping 16 kB @ 0x%08lx " 104 pr_warning(MODULE_NAME ": WARNING: mapping %lu kB @ 0x%08lx in PCI "
62 "in PCI address space, and writing " 105 "address space, and writing 16 kB of rubbish in there.\n",
63 "rubbish in there.\n", mmio_address); 106 size >> 10, mmio_address);
64 do_test(); 107 do_test(size);
108 pr_info(MODULE_NAME ": All done.\n");
65 return 0; 109 return 0;
66} 110}
67 111
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index e9f80c744cf3..10131fbdaada 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -78,8 +78,18 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs)
78 if (cpu_has_arch_perfmon) { 78 if (cpu_has_arch_perfmon) {
79 union cpuid10_eax eax; 79 union cpuid10_eax eax;
80 eax.full = cpuid_eax(0xa); 80 eax.full = cpuid_eax(0xa);
81 if (counter_width < eax.split.bit_width) 81
82 counter_width = eax.split.bit_width; 82 /*
83 * For Core2 (family 6, model 15), don't reset the
84 * counter width:
85 */
86 if (!(eax.split.version_id == 0 &&
87 current_cpu_data.x86 == 6 &&
88 current_cpu_data.x86_model == 15)) {
89
90 if (counter_width < eax.split.bit_width)
91 counter_width = eax.split.bit_width;
92 }
83 } 93 }
84 94
85 /* clear all counters */ 95 /* clear all counters */
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index bea215230b20..b58e96338149 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1672,6 +1672,9 @@ asmlinkage void __init xen_start_kernel(void)
1672 possible map and a non-dummy shared_info. */ 1672 possible map and a non-dummy shared_info. */
1673 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0]; 1673 per_cpu(xen_vcpu, 0) = &HYPERVISOR_shared_info->vcpu_info[0];
1674 1674
1675 local_irq_disable();
1676 early_boot_irqs_off();
1677
1675 xen_raw_console_write("mapping kernel into physical memory\n"); 1678 xen_raw_console_write("mapping kernel into physical memory\n");
1676 pgd = xen_setup_kernel_pagetable(pgd, xen_start_info->nr_pages); 1679 pgd = xen_setup_kernel_pagetable(pgd, xen_start_info->nr_pages);
1677 1680
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 6c873dceb177..981200830432 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -103,9 +103,6 @@ config MATH_EMULATION
103 help 103 help
104 Can we use information of configuration file? 104 Can we use information of configuration file?
105 105
106config HIGHMEM
107 bool "High memory support"
108
109endmenu 106endmenu
110 107
111menu "Platform options" 108menu "Platform options"
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 9606d2bd1dd9..4ec1633c2941 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -44,6 +44,8 @@
44#include <asm/setup.h> 44#include <asm/setup.h>
45#include <asm/param.h> 45#include <asm/param.h>
46 46
47#include <platform/hardware.h>
48
47#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 49#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
48struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; 50struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
49#endif 51#endif
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index c7a021d9f696..c44f830b6c7a 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -30,6 +30,7 @@
30#include <linux/stringify.h> 30#include <linux/stringify.h>
31#include <linux/kallsyms.h> 31#include <linux/kallsyms.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
33#include <linux/hardirq.h>
33 34
34#include <asm/ptrace.h> 35#include <asm/ptrace.h>
35#include <asm/timex.h> 36#include <asm/timex.h>
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index 33f366be323f..bdd860d93f72 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/hardirq.h>
17#include <asm/mmu_context.h> 18#include <asm/mmu_context.h>
18#include <asm/cacheflush.h> 19#include <asm/cacheflush.h>
19#include <asm/hardirq.h> 20#include <asm/hardirq.h>
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c
index efed8897bef3..25d46c84eb08 100644
--- a/arch/xtensa/platforms/iss/console.c
+++ b/arch/xtensa/platforms/iss/console.c
@@ -140,16 +140,14 @@ static void rs_poll(unsigned long priv)
140} 140}
141 141
142 142
143static void rs_put_char(struct tty_struct *tty, unsigned char ch) 143static int rs_put_char(struct tty_struct *tty, unsigned char ch)
144{ 144{
145 char buf[2]; 145 char buf[2];
146 146
147 if (!tty)
148 return;
149
150 buf[0] = ch; 147 buf[0] = ch;
151 buf[1] = '\0'; /* Is this NULL necessary? */ 148 buf[1] = '\0'; /* Is this NULL necessary? */
152 __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0); 149 __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0);
150 return 1;
153} 151}
154 152
155static void rs_flush_chars(struct tty_struct *tty) 153static void rs_flush_chars(struct tty_struct *tty)