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-rw-r--r--arch/powerpc/boot/Makefile4
-rw-r--r--arch/powerpc/boot/dts/media5200.dts318
-rw-r--r--arch/powerpc/platforms/52xx/Kconfig5
-rw-r--r--arch/powerpc/platforms/52xx/Makefile1
-rw-r--r--arch/powerpc/platforms/52xx/media5200.c273
5 files changed, 600 insertions, 1 deletions
diff --git a/arch/powerpc/boot/Makefile b/arch/powerpc/boot/Makefile
index e84df338ea29..8244813bc5a6 100644
--- a/arch/powerpc/boot/Makefile
+++ b/arch/powerpc/boot/Makefile
@@ -235,7 +235,9 @@ image-$(CONFIG_PPC_ADDER875) += cuImage.adder875-uboot \
235 dtbImage.adder875-redboot 235 dtbImage.adder875-redboot
236 236
237# Board ports in arch/powerpc/platform/52xx/Kconfig 237# Board ports in arch/powerpc/platform/52xx/Kconfig
238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 cuImage.lite5200b 238image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200 lite5200.dtb
239image-$(CONFIG_PPC_LITE5200) += cuImage.lite5200b lite5200b.dtb
240image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200 media5200.dtb
239 241
240# Board ports in arch/powerpc/platform/82xx/Kconfig 242# Board ports in arch/powerpc/platform/82xx/Kconfig
241image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads 243image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
diff --git a/arch/powerpc/boot/dts/media5200.dts b/arch/powerpc/boot/dts/media5200.dts
new file mode 100644
index 000000000000..e297d8b41875
--- /dev/null
+++ b/arch/powerpc/boot/dts/media5200.dts
@@ -0,0 +1,318 @@
1/*
2 * Freescale Media5200 board Device Tree Source
3 *
4 * Copyright 2009 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 * Steven Cavanagh <scavanagh@secretlab.ca>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14/dts-v1/;
15
16/ {
17 model = "fsl,media5200";
18 compatible = "fsl,media5200";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 interrupt-parent = <&mpc5200_pic>;
22
23 aliases {
24 console = &console;
25 ethernet0 = &eth0;
26 };
27
28 chosen {
29 linux,stdout-path = &console;
30 };
31
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
35
36 PowerPC,5200@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <32>;
40 i-cache-line-size = <32>;
41 d-cache-size = <0x4000>; // L1, 16K
42 i-cache-size = <0x4000>; // L1, 16K
43 timebase-frequency = <33000000>; // 33 MHz, these were configured by U-Boot
44 bus-frequency = <132000000>; // 132 MHz
45 clock-frequency = <396000000>; // 396 MHz
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x00000000 0x08000000>; // 128MB RAM
52 };
53
54 soc@f0000000 {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "fsl,mpc5200b-immr";
58 ranges = <0 0xf0000000 0x0000c000>;
59 reg = <0xf0000000 0x00000100>;
60 bus-frequency = <132000000>;// 132 MHz
61 system-frequency = <0>; // from bootloader
62
63 cdm@200 {
64 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
65 reg = <0x200 0x38>;
66 };
67
68 mpc5200_pic: interrupt-controller@500 {
69 // 5200 interrupts are encoded into two levels;
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
73 reg = <0x500 0x80>;
74 };
75
76 timer@600 { // General Purpose Timer
77 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78 reg = <0x600 0x10>;
79 interrupts = <1 9 0>;
80 fsl,has-wdt;
81 };
82
83 timer@610 { // General Purpose Timer
84 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
85 reg = <0x610 0x10>;
86 interrupts = <1 10 0>;
87 };
88
89 timer@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 reg = <0x620 0x10>;
92 interrupts = <1 11 0>;
93 };
94
95 timer@630 { // General Purpose Timer
96 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
97 reg = <0x630 0x10>;
98 interrupts = <1 12 0>;
99 };
100
101 timer@640 { // General Purpose Timer
102 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
103 reg = <0x640 0x10>;
104 interrupts = <1 13 0>;
105 };
106
107 timer@650 { // General Purpose Timer
108 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
109 reg = <0x650 0x10>;
110 interrupts = <1 14 0>;
111 };
112
113 timer@660 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 reg = <0x660 0x10>;
116 interrupts = <1 15 0>;
117 };
118
119 timer@670 { // General Purpose Timer
120 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
121 reg = <0x670 0x10>;
122 interrupts = <1 16 0>;
123 };
124
125 rtc@800 { // Real time clock
126 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
127 reg = <0x800 0x100>;
128 interrupts = <1 5 0 1 6 0>;
129 };
130
131 can@900 {
132 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
133 interrupts = <2 17 0>;
134 reg = <0x900 0x80>;
135 };
136
137 can@980 {
138 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan";
139 interrupts = <2 18 0>;
140 reg = <0x980 0x80>;
141 };
142
143 gpio_simple: gpio@b00 {
144 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
145 reg = <0xb00 0x40>;
146 interrupts = <1 7 0>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 gpio_wkup: gpio@c00 {
152 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153 reg = <0xc00 0x40>;
154 interrupts = <1 8 0 0 3 0>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158
159 spi@f00 {
160 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
161 reg = <0xf00 0x20>;
162 interrupts = <2 13 0 2 14 0>;
163 };
164
165 usb@1000 {
166 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
167 reg = <0x1000 0x100>;
168 interrupts = <2 6 0>;
169 };
170
171 dma-controller@1200 {
172 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
173 reg = <0x1200 0x80>;
174 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
175 3 4 0 3 5 0 3 6 0 3 7 0
176 3 8 0 3 9 0 3 10 0 3 11 0
177 3 12 0 3 13 0 3 14 0 3 15 0>;
178 };
179
180 xlb@1f00 {
181 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
182 reg = <0x1f00 0x100>;
183 };
184
185 // PSC6 in uart mode
186 console: serial@2c00 { // PSC6
187 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
188 cell-index = <5>;
189 port-number = <0>; // Logical port assignment
190 reg = <0x2c00 0x100>;
191 interrupts = <2 4 0>;
192 };
193
194 eth0: ethernet@3000 {
195 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
196 reg = <0x3000 0x400>;
197 local-mac-address = [ 00 00 00 00 00 00 ];
198 interrupts = <2 5 0>;
199 phy-handle = <&phy0>;
200 };
201
202 mdio@3000 {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio";
206 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
207 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
208
209 phy0: ethernet-phy@0 {
210 reg = <0>;
211 };
212 };
213
214 ata@3a00 {
215 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
216 reg = <0x3a00 0x100>;
217 interrupts = <2 7 0>;
218 };
219
220 i2c@3d00 {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
224 reg = <0x3d00 0x40>;
225 interrupts = <2 15 0>;
226 fsl5200-clocking;
227 };
228
229 i2c@3d40 {
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
233 reg = <0x3d40 0x40>;
234 interrupts = <2 16 0>;
235 fsl5200-clocking;
236 };
237
238 sram@8000 {
239 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
240 reg = <0x8000 0x4000>;
241 };
242 };
243
244 pci@f0000d00 {
245 #interrupt-cells = <1>;
246 #size-cells = <2>;
247 #address-cells = <3>;
248 device_type = "pci";
249 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
250 reg = <0xf0000d00 0x100>;
251 interrupt-map-mask = <0xf800 0 0 7>;
252 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
253 0xc000 0 0 2 &media5200_fpga 0 3
254 0xc000 0 0 3 &media5200_fpga 0 4
255 0xc000 0 0 4 &media5200_fpga 0 5
256
257 0xc800 0 0 1 &media5200_fpga 0 3 // 2nd slot
258 0xc800 0 0 2 &media5200_fpga 0 4
259 0xc800 0 0 3 &media5200_fpga 0 5
260 0xc800 0 0 4 &media5200_fpga 0 2
261
262 0xd000 0 0 1 &media5200_fpga 0 4 // miniPCI
263 0xd000 0 0 2 &media5200_fpga 0 5
264
265 0xe000 0 0 1 &media5200_fpga 0 5 // CoralIP
266 >;
267 clock-frequency = <0>; // From boot loader
268 interrupts = <2 8 0 2 9 0 2 10 0>;
269 interrupt-parent = <&mpc5200_pic>;
270 bus-range = <0 0>;
271 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
272 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
273 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
274 };
275
276 localbus {
277 compatible = "fsl,mpc5200b-lpb","simple-bus";
278 #address-cells = <2>;
279 #size-cells = <1>;
280
281 ranges = < 0 0 0xfc000000 0x02000000
282 1 0 0xfe000000 0x02000000
283 2 0 0xf0010000 0x00010000
284 3 0 0xf0020000 0x00010000 >;
285
286 flash@0,0 {
287 compatible = "amd,am29lv28ml", "cfi-flash";
288 reg = <0 0x0 0x2000000>; // 32 MB
289 bank-width = <4>; // Width in bytes of the flash bank
290 device-width = <2>; // Two devices on each bank
291 };
292
293 flash@1,0 {
294 compatible = "amd,am29lv28ml", "cfi-flash";
295 reg = <1 0 0x2000000>; // 32 MB
296 bank-width = <4>; // Width in bytes of the flash bank
297 device-width = <2>; // Two devices on each bank
298 };
299
300 media5200_fpga: fpga@2,0 {
301 compatible = "fsl,media5200-fpga";
302 interrupt-controller;
303 #interrupt-cells = <2>; // 0:bank 1:id; no type field
304 reg = <2 0 0x10000>;
305
306 interrupt-parent = <&mpc5200_pic>;
307 interrupts = <0 0 3 // IRQ bank 0
308 1 1 3>; // IRQ bank 1
309 };
310
311 uart@3,0 {
312 compatible = "ti,tl16c752bpt";
313 reg = <3 0 0x10000>;
314 interrupt-parent = <&media5200_fpga>;
315 interrupts = <0 0 0 1>; // 2 irqs
316 };
317 };
318};
diff --git a/arch/powerpc/platforms/52xx/Kconfig b/arch/powerpc/platforms/52xx/Kconfig
index 696a5ee4962d..c01db1316b01 100644
--- a/arch/powerpc/platforms/52xx/Kconfig
+++ b/arch/powerpc/platforms/52xx/Kconfig
@@ -35,6 +35,11 @@ config PPC_LITE5200
35 depends on PPC_MPC52xx 35 depends on PPC_MPC52xx
36 select DEFAULT_UIMAGE 36 select DEFAULT_UIMAGE
37 37
38config PPC_MEDIA5200
39 bool "Freescale Media5200 Eval Board"
40 depends on PPC_MPC52xx
41 select DEFAULT_UIMAGE
42
38config PPC_MPC5200_BUGFIX 43config PPC_MPC5200_BUGFIX
39 bool "MPC5200 (L25R) bugfix support" 44 bool "MPC5200 (L25R) bugfix support"
40 depends on PPC_MPC52xx 45 depends on PPC_MPC52xx
diff --git a/arch/powerpc/platforms/52xx/Makefile b/arch/powerpc/platforms/52xx/Makefile
index d6ade3d5f199..bfd4f52cf3dd 100644
--- a/arch/powerpc/platforms/52xx/Makefile
+++ b/arch/powerpc/platforms/52xx/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI) += mpc52xx_pci.o
7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o 7obj-$(CONFIG_PPC_MPC5200_SIMPLE) += mpc5200_simple.o
8obj-$(CONFIG_PPC_EFIKA) += efika.o 8obj-$(CONFIG_PPC_EFIKA) += efika.o
9obj-$(CONFIG_PPC_LITE5200) += lite5200.o 9obj-$(CONFIG_PPC_LITE5200) += lite5200.o
10obj-$(CONFIG_PPC_MEDIA5200) += media5200.o
10 11
11obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o 12obj-$(CONFIG_PM) += mpc52xx_sleep.o mpc52xx_pm.o
12ifeq ($(CONFIG_PPC_LITE5200),y) 13ifeq ($(CONFIG_PPC_LITE5200),y)
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
new file mode 100644
index 000000000000..68e4f1696d14
--- /dev/null
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -0,0 +1,273 @@
1/*
2 * Support for 'media5200-platform' compatible boards.
3 *
4 * Copyright (C) 2008 Secret Lab Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Description:
12 * This code implements support for the Freescape Media5200 platform
13 * (built around the MPC5200 SoC).
14 *
15 * Notable characteristic of the Media5200 is the presence of an FPGA
16 * that has all external IRQ lines routed through it. This file implements
17 * a cascaded interrupt controller driver which attaches itself to the
18 * Virtual IRQ subsystem after the primary mpc5200 interrupt controller
19 * is initialized.
20 *
21 */
22
23#undef DEBUG
24
25#include <linux/irq.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <asm/time.h>
29#include <asm/prom.h>
30#include <asm/machdep.h>
31#include <asm/mpc52xx.h>
32
33static struct of_device_id mpc5200_gpio_ids[] __initdata = {
34 { .compatible = "fsl,mpc5200-gpio", },
35 { .compatible = "mpc5200-gpio", },
36 {}
37};
38
39/* FPGA register set */
40#define MEDIA5200_IRQ_ENABLE (0x40c)
41#define MEDIA5200_IRQ_STATUS (0x410)
42#define MEDIA5200_NUM_IRQS (6)
43#define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS)
44
45struct media5200_irq {
46 void __iomem *regs;
47 spinlock_t lock;
48 struct irq_host *irqhost;
49};
50struct media5200_irq media5200_irq;
51
52static void media5200_irq_unmask(unsigned int virq)
53{
54 unsigned long flags;
55 u32 val;
56
57 spin_lock_irqsave(&media5200_irq.lock, flags);
58 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
59 val |= 1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq);
60 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
61 spin_unlock_irqrestore(&media5200_irq.lock, flags);
62}
63
64static void media5200_irq_mask(unsigned int virq)
65{
66 unsigned long flags;
67 u32 val;
68
69 spin_lock_irqsave(&media5200_irq.lock, flags);
70 val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
71 val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irq_map[virq].hwirq));
72 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val);
73 spin_unlock_irqrestore(&media5200_irq.lock, flags);
74}
75
76static struct irq_chip media5200_irq_chip = {
77 .typename = "Media5200 FPGA",
78 .unmask = media5200_irq_unmask,
79 .mask = media5200_irq_mask,
80 .mask_ack = media5200_irq_mask,
81};
82
83void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
84{
85 int sub_virq, val;
86 u32 status, enable;
87
88 /* Mask off the cascaded IRQ */
89 spin_lock(&desc->lock);
90 desc->chip->mask(virq);
91 spin_unlock(&desc->lock);
92
93 /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs
94 * are pending. 'ffs()' is 1 based */
95 status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE);
96 enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
97 val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
98 if (val) {
99 sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
100 /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
101 * __func__, virq, status, enable, val - 1, sub_virq);
102 */
103 generic_handle_irq(sub_virq);
104 }
105
106 /* Processing done; can reenable the cascade now */
107 spin_lock(&desc->lock);
108 desc->chip->ack(virq);
109 if (!(desc->status & IRQ_DISABLED))
110 desc->chip->unmask(virq);
111 spin_unlock(&desc->lock);
112}
113
114static int media5200_irq_map(struct irq_host *h, unsigned int virq,
115 irq_hw_number_t hw)
116{
117 struct irq_desc *desc = get_irq_desc(virq);
118
119 pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
120 set_irq_chip_data(virq, &media5200_irq);
121 set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
122 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
123 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
124 desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
125
126 return 0;
127}
128
129static int media5200_irq_xlate(struct irq_host *h, struct device_node *ct,
130 u32 *intspec, unsigned int intsize,
131 irq_hw_number_t *out_hwirq,
132 unsigned int *out_flags)
133{
134 if (intsize != 2)
135 return -1;
136
137 pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]);
138 *out_hwirq = intspec[1];
139 *out_flags = IRQ_TYPE_NONE;
140 return 0;
141}
142
143static struct irq_host_ops media5200_irq_ops = {
144 .map = media5200_irq_map,
145 .xlate = media5200_irq_xlate,
146};
147
148/*
149 * Setup Media5200 IRQ mapping
150 */
151static void __init media5200_init_irq(void)
152{
153 struct device_node *fpga_np;
154 int cascade_virq;
155
156 /* First setup the regular MPC5200 interrupt controller */
157 mpc52xx_init_irq();
158
159 /* Now find the FPGA IRQ */
160 fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga");
161 if (!fpga_np)
162 goto out;
163 pr_debug("%s: found fpga node: %s\n", __func__, fpga_np->full_name);
164
165 media5200_irq.regs = of_iomap(fpga_np, 0);
166 if (!media5200_irq.regs)
167 goto out;
168 pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs);
169
170 cascade_virq = irq_of_parse_and_map(fpga_np, 0);
171 if (!cascade_virq)
172 goto out;
173 pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq);
174
175 /* Disable all FPGA IRQs */
176 out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0);
177
178 spin_lock_init(&media5200_irq.lock);
179
180 media5200_irq.irqhost = irq_alloc_host(fpga_np, IRQ_HOST_MAP_LINEAR,
181 MEDIA5200_NUM_IRQS,
182 &media5200_irq_ops, -1);
183 if (!media5200_irq.irqhost)
184 goto out;
185 pr_debug("%s: allocated irqhost\n", __func__);
186
187 media5200_irq.irqhost->host_data = &media5200_irq;
188
189 set_irq_data(cascade_virq, &media5200_irq);
190 set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
191
192 return;
193
194 out:
195 pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n");
196}
197
198/*
199 * Setup the architecture
200 */
201static void __init media5200_setup_arch(void)
202{
203
204 struct device_node *np;
205 struct mpc52xx_gpio __iomem *gpio;
206 u32 port_config;
207
208 if (ppc_md.progress)
209 ppc_md.progress("media5200_setup_arch()", 0);
210
211 /* Map important registers from the internal memory map */
212 mpc52xx_map_common_devices();
213
214 /* Some mpc5200 & mpc5200b related configuration */
215 mpc5200_setup_xlb_arbiter();
216
217 mpc52xx_setup_pci();
218
219 np = of_find_matching_node(NULL, mpc5200_gpio_ids);
220 gpio = of_iomap(np, 0);
221 of_node_put(np);
222 if (!gpio) {
223 printk(KERN_ERR "%s() failed. expect abnormal behavior\n",
224 __func__);
225 return;
226 }
227
228 /* Set port config */
229 port_config = in_be32(&gpio->port_config);
230
231 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */
232 port_config |= 0x01000000;
233
234 out_be32(&gpio->port_config, port_config);
235
236 /* Unmap zone */
237 iounmap(gpio);
238
239}
240
241/* list of the supported boards */
242static char *board[] __initdata = {
243 "fsl,media5200",
244 NULL
245};
246
247/*
248 * Called very early, MMU is off, device-tree isn't unflattened
249 */
250static int __init media5200_probe(void)
251{
252 unsigned long node = of_get_flat_dt_root();
253 int i = 0;
254
255 while (board[i]) {
256 if (of_flat_dt_is_compatible(node, board[i]))
257 break;
258 i++;
259 }
260
261 return (board[i] != NULL);
262}
263
264define_machine(media5200_platform) {
265 .name = "media5200-platform",
266 .probe = media5200_probe,
267 .setup_arch = media5200_setup_arch,
268 .init = mpc52xx_declare_of_platform_devices,
269 .init_IRQ = media5200_init_irq,
270 .get_irq = mpc52xx_get_irq,
271 .restart = mpc52xx_restart,
272 .calibrate_decr = generic_calibrate_decr,
273};
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 10:29:52 -0500