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-rw-r--r--arch/powerpc/boot/dts/mpc8548cds.dts124
1 files changed, 89 insertions, 35 deletions
diff --git a/arch/powerpc/boot/dts/mpc8548cds.dts b/arch/powerpc/boot/dts/mpc8548cds.dts
index 4770a5b96838..d215d21fff42 100644
--- a/arch/powerpc/boot/dts/mpc8548cds.dts
+++ b/arch/powerpc/boot/dts/mpc8548cds.dts
@@ -44,8 +44,14 @@
44 #size-cells = <1>; 44 #size-cells = <1>;
45 #interrupt-cells = <2>; 45 #interrupt-cells = <2>;
46 device_type = "soc"; 46 device_type = "soc";
47 ranges = <0 e0000000 00100000>; 47 ranges = <00001000 e0001000 000ff000
48 reg = <e0000000 00100000>; // CCSRBAR 1M 48 80000000 80000000 10000000
49 e2000000 e2000000 00800000
50 90000000 90000000 10000000
51 e2800000 e2800000 00800000
52 a0000000 a0000000 20000000
53 e3000000 e3000000 01000000>;
54 reg = <e0000000 00001000>; // CCSRBAR
49 bus-frequency = <0>; 55 bus-frequency = <0>;
50 56
51 memory-controller@2000 { 57 memory-controller@2000 {
@@ -162,8 +168,8 @@
162 serial@4500 { 168 serial@4500 {
163 device_type = "serial"; 169 device_type = "serial";
164 compatible = "ns16550"; 170 compatible = "ns16550";
165 reg = <4500 100>; // reg base, size 171 reg = <4500 100>; // reg base, size
166 clock-frequency = <0>; // should we fill in in uboot? 172 clock-frequency = <0>; // should we fill in in uboot?
167 interrupts = <2a 2>; 173 interrupts = <2a 2>;
168 interrupt-parent = <&mpic>; 174 interrupt-parent = <&mpic>;
169 }; 175 };
@@ -172,7 +178,7 @@
172 device_type = "serial"; 178 device_type = "serial";
173 compatible = "ns16550"; 179 compatible = "ns16550";
174 reg = <4600 100>; // reg base, size 180 reg = <4600 100>; // reg base, size
175 clock-frequency = <0>; // should we fill in in uboot? 181 clock-frequency = <0>; // should we fill in in uboot?
176 interrupts = <2a 2>; 182 interrupts = <2a 2>;
177 interrupt-parent = <&mpic>; 183 interrupt-parent = <&mpic>;
178 }; 184 };
@@ -183,8 +189,8 @@
183 fsl,has-rstcr; 189 fsl,has-rstcr;
184 }; 190 };
185 191
186 pci1: pci@8000 { 192 pci@8000 {
187 interrupt-map-mask = <1f800 0 0 7>; 193 interrupt-map-mask = <f800 0 0 7>;
188 interrupt-map = < 194 interrupt-map = <
189 /* IDSEL 0x4 (PCIX Slot 2) */ 195 /* IDSEL 0x4 (PCIX Slot 2) */
190 02000 0 0 1 &mpic 0 1 196 02000 0 0 1 &mpic 0 1
@@ -244,19 +250,7 @@
244 0E000 0 0 1 &mpic 0 1 250 0E000 0 0 1 &mpic 0 1
245 0E000 0 0 2 &mpic 1 1 251 0E000 0 0 2 &mpic 1 1
246 0E000 0 0 3 &mpic 2 1 252 0E000 0 0 3 &mpic 2 1
247 0E000 0 0 4 &mpic 3 1 253 0E000 0 0 4 &mpic 3 1>;
248
249 /* bus 1 , idsel 0x2 Tsi310 bridge secondary */
250 11000 0 0 1 &mpic 2 1
251 11000 0 0 2 &mpic 3 1
252 11000 0 0 3 &mpic 0 1
253 11000 0 0 4 &mpic 1 1
254
255 /* VIA chip */
256 12000 0 0 1 &mpic 0 1
257 12000 0 0 2 &mpic 1 1
258 12000 0 0 3 &mpic 2 1
259 12000 0 0 4 &mpic 3 1>;
260 254
261 interrupt-parent = <&mpic>; 255 interrupt-parent = <&mpic>;
262 interrupts = <18 2>; 256 interrupts = <18 2>;
@@ -271,18 +265,78 @@
271 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci"; 265 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
272 device_type = "pci"; 266 device_type = "pci";
273 267
274 i8259@4 { 268 pci_bridge@1c {
275 clock-frequency = <0>; 269 interrupt-map-mask = <f800 0 0 7>;
276 interrupt-controller; 270 interrupt-map = <
277 device_type = "interrupt-controller"; 271
278 reg = <12000 0 0 0 1>; 272 /* IDSEL 0x00 (PrPMC Site) */
279 #address-cells = <0>; 273 0000 0 0 1 &mpic 0 1
280 #interrupt-cells = <2>; 274 0000 0 0 2 &mpic 1 1
281 built-in; 275 0000 0 0 3 &mpic 2 1
282 compatible = "chrp,iic"; 276 0000 0 0 4 &mpic 3 1
283 big-endian; 277
284 interrupts = <1>; 278 /* IDSEL 0x04 (VIA chip) */
285 interrupt-parent = <&pci1>; 279 2000 0 0 1 &mpic 0 1
280 2000 0 0 2 &mpic 1 1
281 2000 0 0 3 &mpic 2 1
282 2000 0 0 4 &mpic 3 1
283
284 /* IDSEL 0x05 (8139) */
285 2800 0 0 1 &mpic 1 1
286
287 /* IDSEL 0x06 (Slot 6) */
288 3000 0 0 1 &mpic 2 1
289 3000 0 0 2 &mpic 3 1
290 3000 0 0 3 &mpic 0 1
291 3000 0 0 4 &mpic 1 1
292
293 /* IDESL 0x07 (Slot 7) */
294 3800 0 0 1 &mpic 3 1
295 3800 0 0 2 &mpic 0 1
296 3800 0 0 3 &mpic 1 1
297 3800 0 0 4 &mpic 2 1>;
298
299 reg = <e000 0 0 0 0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 ranges = <02000000 0 80000000
304 02000000 0 80000000
305 0 20000000
306 01000000 0 00000000
307 01000000 0 00000000
308 0 00080000>;
309 clock-frequency = <1fca055>;
310
311 isa@4 {
312 device_type = "isa";
313 #interrupt-cells = <2>;
314 #size-cells = <1>;
315 #address-cells = <2>;
316 reg = <2000 0 0 0 0>;
317 ranges = <1 0 01000000 0 0 00001000>;
318 interrupt-parent = <&i8259>;
319
320 i8259: interrupt-controller@20 {
321 clock-frequency = <0>;
322 interrupt-controller;
323 device_type = "interrupt-controller";
324 reg = <1 20 2
325 1 a0 2
326 1 4d0 2>;
327 #address-cells = <0>;
328 #interrupt-cells = <2>;
329 built-in;
330 compatible = "chrp,iic";
331 interrupts = <0 1>;
332 interrupt-parent = <&mpic>;
333 };
334
335 rtc@70 {
336 compatible = "pnpPNP,b00";
337 reg = <1 70 2>;
338 };
339 };
286 }; 340 };
287 }; 341 };
288 342
@@ -292,9 +346,9 @@
292 346
293 /* IDSEL 0x15 */ 347 /* IDSEL 0x15 */
294 a800 0 0 1 &mpic b 1 348 a800 0 0 1 &mpic b 1
295 a800 0 0 2 &mpic b 1 349 a800 0 0 2 &mpic 1 1
296 a800 0 0 3 &mpic b 1 350 a800 0 0 3 &mpic 2 1
297 a800 0 0 4 &mpic b 1>; 351 a800 0 0 4 &mpic 3 1>;
298 352
299 interrupt-parent = <&mpic>; 353 interrupt-parent = <&mpic>;
300 interrupts = <19 2>; 354 interrupts = <19 2>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-24 18:28:42 -0500