5 files changed, 0 insertions, 66 deletions

diff --git a/arch/i386/kernel/smpboot.c b/arch/i386/kernel/smpboot.c
index 88baed1e7e83..0b2954534b8e 100644
--- a/arch/i386/kernel/smpboot.c
+++ b/arch/i386/kernel/smpboot.c
@@ -941,17 +941,6 @@ exit:
 }
 #endif
 
-static void smp_tune_scheduling(void)
-{
-        if (cpu_khz) {
-                /* cache size in kB */
-                long cachesize = boot_cpu_data.x86_cache_size;
-
-                if (cachesize > 0)
-                        max_cache_size = cachesize * 1024;
-        }
-}
-
 /*
  * Cycle through the processors sending APIC IPIs to boot each.
  */
@@ -980,7 +969,6 @@ static void __init smp_boot_cpus(unsigned int max_cpus)
         x86_cpu_to_apicid[0] = boot_cpu_physical_apicid;
 
         current_thread_info()->cpu = 0;
-        smp_tune_scheduling();
 
         set_cpu_sibling_map(0);
 
diff --git a/arch/ia64/kernel/setup.c b/arch/ia64/kernel/setup.c
index eaa6a24bc0b6..188fb73c6845 100644
--- a/arch/ia64/kernel/setup.c
+++ b/arch/ia64/kernel/setup.c
@@ -805,7 +805,6 @@ static void __cpuinit
 get_max_cacheline_size (void)
 {
         unsigned long line_size, max = 1;
-        unsigned int cache_size = 0;
         u64 l, levels, unique_caches;
         pal_cache_config_info_t cci;
         s64 status;
@@ -835,8 +834,6 @@ get_max_cacheline_size (void)
                 line_size = 1 << cci.pcci_line_size;
                 if (line_size > max)
                         max = line_size;
-                if (cache_size < cci.pcci_cache_size)
-                        cache_size = cci.pcci_cache_size;
                 if (!cci.pcci_unified) {
                         status = ia64_pal_cache_config_info(l,
                                                     /* cache_type (instruction)= */ 1,
@@ -853,9 +850,6 @@ get_max_cacheline_size (void)
                         ia64_i_cache_stride_shift = cci.pcci_stride;
         }
   out:
-#ifdef CONFIG_SMP
-        max_cache_size = max(max_cache_size, cache_size);
-#endif
         if (max > ia64_max_cacheline_size)
                 ia64_max_cacheline_size = max;
 }
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 67edfa7ed93a..a1b017f2dbb3 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -51,16 +51,6 @@ int __cpu_logical_map[NR_CPUS];		/* Map logical to physical */
 EXPORT_SYMBOL(phys_cpu_present_map);
 EXPORT_SYMBOL(cpu_online_map);
 
-/* This happens early in bootup, can't really do it better */
-static void smp_tune_scheduling (void)
-{
-        struct cache_desc *cd = &current_cpu_data.scache;
-        unsigned long cachesize = cd->linesz * cd->sets * cd->ways;
-
-        if (cachesize > max_cache_size)
-                max_cache_size = cachesize;
-}
-
 extern void __init calibrate_delay(void);
 extern ATTRIB_NORET void cpu_idle(void);
 
@@ -228,7 +218,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
 {
         init_new_context(current, &init_mm);
         current_thread_info()->cpu = 0;
-        smp_tune_scheduling();
         plat_prepare_cpus(max_cpus);
 #ifndef CONFIG_HOTPLUG_CPU
         cpu_present_map = cpu_possible_map;
diff --git a/arch/sparc/kernel/smp.c b/arch/sparc/kernel/smp.c
index 4d9ad59031bb..4fea3ac7bff0 100644
--- a/arch/sparc/kernel/smp.c
+++ b/arch/sparc/kernel/smp.c
@@ -68,16 +68,6 @@ void __cpuinit smp_store_cpu_info(int id)
         cpu_data(id).prom_node = cpu_node;
         cpu_data(id).mid = cpu_get_hwmid(cpu_node);
 
-        /* this is required to tune the scheduler correctly */
-        /* is it possible to have CPUs with different cache sizes? */
-        if (id == boot_cpu_id) {
-                int cache_line,cache_nlines;
-                cache_line = 0x20;
-                cache_line = prom_getintdefault(cpu_node, "ecache-line-size", cache_line);
-                cache_nlines = 0x8000;
-                cache_nlines = prom_getintdefault(cpu_node, "ecache-nlines", cache_nlines);
-                max_cache_size = cache_line * cache_nlines;
-        }
         if (cpu_data(id).mid < 0)
                 panic("No MID found for CPU%d at node 0x%08d", id, cpu_node);
 }
diff --git a/arch/sparc64/kernel/smp.c b/arch/sparc64/kernel/smp.c
index 4dcd7d0b60f2..40e40f968d61 100644
--- a/arch/sparc64/kernel/smp.c
+++ b/arch/sparc64/kernel/smp.c
@@ -1163,32 +1163,6 @@ int setup_profiling_timer(unsigned int multiplier)
         return -EINVAL;
 }
 
-static void __init smp_tune_scheduling(void)
-{
-        unsigned int smallest = ~0U;
-        int i;
-
-        for (i = 0; i < NR_CPUS; i++) {
-                unsigned int val = cpu_data(i).ecache_size;
-
-                if (val && val < smallest)
-                        smallest = val;
-        }
-
-        /* Any value less than 256K is nonsense.  */
-        if (smallest < (256U * 1024U))
-                smallest = 256 * 1024;
-
-        max_cache_size = smallest;
-
-        if (smallest < 1U * 1024U * 1024U)
-                printk(KERN_INFO "Using max_cache_size of %uKB\n",
-                       smallest / 1024U);
-        else
-                printk(KERN_INFO "Using max_cache_size of %uMB\n",
-                       smallest / 1024U / 1024U);
-}
-
 /* Constrain the number of cpus to max_cpus.  */
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
@@ -1206,7 +1180,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         }
 
         cpu_data(boot_cpu_id).udelay_val = loops_per_jiffy;
-        smp_tune_scheduling();
 }
 
 void __devinit smp_prepare_boot_cpu(void)