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-rw-r--r--arch/powerpc/platforms/cell/setup.c4
-rw-r--r--arch/powerpc/platforms/cell/spu_base.c5
-rw-r--r--arch/powerpc/platforms/cell/spu_priv1_mmio.c104
-rw-r--r--arch/powerpc/platforms/cell/spufs/hw_ops.c1
-rw-r--r--arch/powerpc/platforms/cell/spufs/switch.c1
5 files changed, 74 insertions, 41 deletions
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index eb8ab9bbf744..3d1831d331e5 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -49,6 +49,7 @@
49#include <asm/ppc-pci.h> 49#include <asm/ppc-pci.h>
50#include <asm/irq.h> 50#include <asm/irq.h>
51#include <asm/spu.h> 51#include <asm/spu.h>
52#include <asm/spu_priv1.h>
52 53
53#include "interrupt.h" 54#include "interrupt.h"
54#include "iommu.h" 55#include "iommu.h"
@@ -83,6 +84,9 @@ static void __init cell_setup_arch(void)
83{ 84{
84 ppc_md.init_IRQ = iic_init_IRQ; 85 ppc_md.init_IRQ = iic_init_IRQ;
85 ppc_md.get_irq = iic_get_irq; 86 ppc_md.get_irq = iic_get_irq;
87#ifdef CONFIG_SPU_BASE
88 spu_priv1_ops = &spu_priv1_mmio_ops;
89#endif
86 90
87 cbe_regs_init(); 91 cbe_regs_init();
88 92
diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c
index eb367dd89a7d..c3bb7299c4b5 100644
--- a/arch/powerpc/platforms/cell/spu_base.c
+++ b/arch/powerpc/platforms/cell/spu_base.c
@@ -34,10 +34,15 @@
34#include <asm/prom.h> 34#include <asm/prom.h>
35#include <linux/mutex.h> 35#include <linux/mutex.h>
36#include <asm/spu.h> 36#include <asm/spu.h>
37#include <asm/spu_priv1.h>
37#include <asm/mmu_context.h> 38#include <asm/mmu_context.h>
38 39
39#include "interrupt.h" 40#include "interrupt.h"
40 41
42const struct spu_priv1_ops *spu_priv1_ops;
43
44EXPORT_SYMBOL_GPL(spu_priv1_ops);
45
41static int __spu_trap_invalid_dma(struct spu *spu) 46static int __spu_trap_invalid_dma(struct spu *spu)
42{ 47{
43 pr_debug("%s\n", __FUNCTION__); 48 pr_debug("%s\n", __FUNCTION__);
diff --git a/arch/powerpc/platforms/cell/spu_priv1_mmio.c b/arch/powerpc/platforms/cell/spu_priv1_mmio.c
index b2656421c7b5..abe8a84925d2 100644
--- a/arch/powerpc/platforms/cell/spu_priv1_mmio.c
+++ b/arch/powerpc/platforms/cell/spu_priv1_mmio.c
@@ -1,133 +1,155 @@
1/* 1/*
2 * access to SPU privileged registers 2 * spu hypervisor abstraction for direct hardware access.
3 *
4 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
5 * Copyright 2006 Sony Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3 */ 19 */
20
4#include <linux/module.h> 21#include <linux/module.h>
5 22
6#include <asm/io.h> 23#include <asm/io.h>
7#include <asm/spu.h> 24#include <asm/spu.h>
25#include <asm/spu_priv1.h>
8 26
9void spu_int_mask_and(struct spu *spu, int class, u64 mask) 27static void int_mask_and(struct spu *spu, int class, u64 mask)
10{ 28{
11 u64 old_mask; 29 u64 old_mask;
12 30
13 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); 31 old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
14 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); 32 out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
15} 33}
16EXPORT_SYMBOL_GPL(spu_int_mask_and);
17 34
18void spu_int_mask_or(struct spu *spu, int class, u64 mask) 35static void int_mask_or(struct spu *spu, int class, u64 mask)
19{ 36{
20 u64 old_mask; 37 u64 old_mask;
21 38
22 old_mask = in_be64(&spu->priv1->int_mask_RW[class]); 39 old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
23 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); 40 out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
24} 41}
25EXPORT_SYMBOL_GPL(spu_int_mask_or);
26 42
27void spu_int_mask_set(struct spu *spu, int class, u64 mask) 43static void int_mask_set(struct spu *spu, int class, u64 mask)
28{ 44{
29 out_be64(&spu->priv1->int_mask_RW[class], mask); 45 out_be64(&spu->priv1->int_mask_RW[class], mask);
30} 46}
31EXPORT_SYMBOL_GPL(spu_int_mask_set);
32 47
33u64 spu_int_mask_get(struct spu *spu, int class) 48static u64 int_mask_get(struct spu *spu, int class)
34{ 49{
35 return in_be64(&spu->priv1->int_mask_RW[class]); 50 return in_be64(&spu->priv1->int_mask_RW[class]);
36} 51}
37EXPORT_SYMBOL_GPL(spu_int_mask_get);
38 52
39void spu_int_stat_clear(struct spu *spu, int class, u64 stat) 53static void int_stat_clear(struct spu *spu, int class, u64 stat)
40{ 54{
41 out_be64(&spu->priv1->int_stat_RW[class], stat); 55 out_be64(&spu->priv1->int_stat_RW[class], stat);
42} 56}
43EXPORT_SYMBOL_GPL(spu_int_stat_clear);
44 57
45u64 spu_int_stat_get(struct spu *spu, int class) 58static u64 int_stat_get(struct spu *spu, int class)
46{ 59{
47 return in_be64(&spu->priv1->int_stat_RW[class]); 60 return in_be64(&spu->priv1->int_stat_RW[class]);
48} 61}
49EXPORT_SYMBOL_GPL(spu_int_stat_get);
50 62
51void spu_int_route_set(struct spu *spu, u64 route) 63static void int_route_set(struct spu *spu, u64 route)
52{ 64{
53 out_be64(&spu->priv1->int_route_RW, route); 65 out_be64(&spu->priv1->int_route_RW, route);
54} 66}
55EXPORT_SYMBOL_GPL(spu_int_route_set);
56 67
57u64 spu_mfc_dar_get(struct spu *spu) 68static u64 mfc_dar_get(struct spu *spu)
58{ 69{
59 return in_be64(&spu->priv1->mfc_dar_RW); 70 return in_be64(&spu->priv1->mfc_dar_RW);
60} 71}
61EXPORT_SYMBOL_GPL(spu_mfc_dar_get);
62 72
63u64 spu_mfc_dsisr_get(struct spu *spu) 73static u64 mfc_dsisr_get(struct spu *spu)
64{ 74{
65 return in_be64(&spu->priv1->mfc_dsisr_RW); 75 return in_be64(&spu->priv1->mfc_dsisr_RW);
66} 76}
67EXPORT_SYMBOL_GPL(spu_mfc_dsisr_get);
68 77
69void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr) 78static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
70{ 79{
71 out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); 80 out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
72} 81}
73EXPORT_SYMBOL_GPL(spu_mfc_dsisr_set);
74 82
75void spu_mfc_sdr_set(struct spu *spu, u64 sdr) 83static void mfc_sdr_set(struct spu *spu, u64 sdr)
76{ 84{
77 out_be64(&spu->priv1->mfc_sdr_RW, sdr); 85 out_be64(&spu->priv1->mfc_sdr_RW, sdr);
78} 86}
79EXPORT_SYMBOL_GPL(spu_mfc_sdr_set);
80 87
81void spu_mfc_sr1_set(struct spu *spu, u64 sr1) 88static void mfc_sr1_set(struct spu *spu, u64 sr1)
82{ 89{
83 out_be64(&spu->priv1->mfc_sr1_RW, sr1); 90 out_be64(&spu->priv1->mfc_sr1_RW, sr1);
84} 91}
85EXPORT_SYMBOL_GPL(spu_mfc_sr1_set);
86 92
87u64 spu_mfc_sr1_get(struct spu *spu) 93static u64 mfc_sr1_get(struct spu *spu)
88{ 94{
89 return in_be64(&spu->priv1->mfc_sr1_RW); 95 return in_be64(&spu->priv1->mfc_sr1_RW);
90} 96}
91EXPORT_SYMBOL_GPL(spu_mfc_sr1_get);
92 97
93void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id) 98static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
94{ 99{
95 out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); 100 out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
96} 101}
97EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_set);
98 102
99u64 spu_mfc_tclass_id_get(struct spu *spu) 103static u64 mfc_tclass_id_get(struct spu *spu)
100{ 104{
101 return in_be64(&spu->priv1->mfc_tclass_id_RW); 105 return in_be64(&spu->priv1->mfc_tclass_id_RW);
102} 106}
103EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_get);
104 107
105void spu_tlb_invalidate(struct spu *spu) 108static void tlb_invalidate(struct spu *spu)
106{ 109{
107 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); 110 out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
108} 111}
109EXPORT_SYMBOL_GPL(spu_tlb_invalidate);
110 112
111void spu_resource_allocation_groupID_set(struct spu *spu, u64 id) 113static void resource_allocation_groupID_set(struct spu *spu, u64 id)
112{ 114{
113 out_be64(&spu->priv1->resource_allocation_groupID_RW, id); 115 out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
114} 116}
115EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_set);
116 117
117u64 spu_resource_allocation_groupID_get(struct spu *spu) 118static u64 resource_allocation_groupID_get(struct spu *spu)
118{ 119{
119 return in_be64(&spu->priv1->resource_allocation_groupID_RW); 120 return in_be64(&spu->priv1->resource_allocation_groupID_RW);
120} 121}
121EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_get);
122 122
123void spu_resource_allocation_enable_set(struct spu *spu, u64 enable) 123static void resource_allocation_enable_set(struct spu *spu, u64 enable)
124{ 124{
125 out_be64(&spu->priv1->resource_allocation_enable_RW, enable); 125 out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
126} 126}
127EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_set);
128 127
129u64 spu_resource_allocation_enable_get(struct spu *spu) 128static u64 resource_allocation_enable_get(struct spu *spu)
130{ 129{
131 return in_be64(&spu->priv1->resource_allocation_enable_RW); 130 return in_be64(&spu->priv1->resource_allocation_enable_RW);
132} 131}
133EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_get); 132
133const struct spu_priv1_ops spu_priv1_mmio_ops =
134{
135 .int_mask_and = int_mask_and,
136 .int_mask_or = int_mask_or,
137 .int_mask_set = int_mask_set,
138 .int_mask_get = int_mask_get,
139 .int_stat_clear = int_stat_clear,
140 .int_stat_get = int_stat_get,
141 .int_route_set = int_route_set,
142 .mfc_dar_get = mfc_dar_get,
143 .mfc_dsisr_get = mfc_dsisr_get,
144 .mfc_dsisr_set = mfc_dsisr_set,
145 .mfc_sdr_set = mfc_sdr_set,
146 .mfc_sr1_set = mfc_sr1_set,
147 .mfc_sr1_get = mfc_sr1_get,
148 .mfc_tclass_id_set = mfc_tclass_id_set,
149 .mfc_tclass_id_get = mfc_tclass_id_get,
150 .tlb_invalidate = tlb_invalidate,
151 .resource_allocation_groupID_set = resource_allocation_groupID_set,
152 .resource_allocation_groupID_get = resource_allocation_groupID_get,
153 .resource_allocation_enable_set = resource_allocation_enable_set,
154 .resource_allocation_enable_get = resource_allocation_enable_get,
155};
diff --git a/arch/powerpc/platforms/cell/spufs/hw_ops.c b/arch/powerpc/platforms/cell/spufs/hw_ops.c
index a13a8b5a014d..ede2cac46b6d 100644
--- a/arch/powerpc/platforms/cell/spufs/hw_ops.c
+++ b/arch/powerpc/platforms/cell/spufs/hw_ops.c
@@ -32,6 +32,7 @@
32 32
33#include <asm/io.h> 33#include <asm/io.h>
34#include <asm/spu.h> 34#include <asm/spu.h>
35#include <asm/spu_priv1.h>
35#include <asm/spu_csa.h> 36#include <asm/spu_csa.h>
36#include <asm/mmu_context.h> 37#include <asm/mmu_context.h>
37#include "spufs.h" 38#include "spufs.h"
diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c
index 85bea06e798b..2dae062a9aec 100644
--- a/arch/powerpc/platforms/cell/spufs/switch.c
+++ b/arch/powerpc/platforms/cell/spufs/switch.c
@@ -46,6 +46,7 @@
46 46
47#include <asm/io.h> 47#include <asm/io.h>
48#include <asm/spu.h> 48#include <asm/spu.h>
49#include <asm/spu_priv1.h>
49#include <asm/spu_csa.h> 50#include <asm/spu_csa.h>
50#include <asm/mmu_context.h> 51#include <asm/mmu_context.h>
51 52