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-rw-r--r--arch/i386/kernel/head.S14
-rw-r--r--arch/i386/kernel/hpet.c2
-rw-r--r--arch/i386/kernel/irq.c5
-rw-r--r--arch/i386/kernel/setup.c32
-rw-r--r--arch/i386/kernel/traps.c27
-rw-r--r--arch/i386/pci/common.c5
-rw-r--r--arch/i386/pci/mmconfig.c34
-rw-r--r--arch/i386/pci/pci.h3
-rw-r--r--arch/ia64/Kconfig4
-rw-r--r--arch/ia64/kernel/topology.c6
-rw-r--r--arch/ia64/sn/kernel/xpc_channel.c4
-rw-r--r--arch/ia64/sn/kernel/xpc_main.c28
-rw-r--r--arch/ia64/sn/kernel/xpc_partition.c24
-rw-r--r--arch/powerpc/Kconfig20
-rw-r--r--arch/powerpc/boot/dts/mpc7448hpc2.dts190
-rw-r--r--arch/powerpc/boot/dts/mpc8349emds.dts328
-rw-r--r--arch/powerpc/configs/mpc834x_mds_defconfig (renamed from arch/powerpc/configs/mpc834x_sys_defconfig)0
-rw-r--r--arch/powerpc/kernel/fpu.S5
-rw-r--r--arch/powerpc/kernel/irq.c84
-rw-r--r--arch/powerpc/kernel/pci_64.c11
-rw-r--r--arch/powerpc/kernel/ppc_ksyms.c4
-rw-r--r--arch/powerpc/kernel/prom_init.c10
-rw-r--r--arch/powerpc/kernel/prom_parse.c17
-rw-r--r--arch/powerpc/kernel/smp-tbsync.c5
-rw-r--r--arch/powerpc/kernel/time.c25
-rw-r--r--arch/powerpc/lib/memcpy_64.S11
-rw-r--r--arch/powerpc/mm/44x_mmu.c4
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_itx.c49
-rw-r--r--arch/powerpc/platforms/83xx/mpc834x_sys.c56
-rw-r--r--arch/powerpc/platforms/83xx/mpc83xx.h1
-rw-r--r--arch/powerpc/platforms/83xx/pci.c9
-rw-r--r--arch/powerpc/platforms/86xx/mpc86xx_hpcn.c26
-rw-r--r--arch/powerpc/platforms/86xx/pci.c3
-rw-r--r--arch/powerpc/platforms/embedded6xx/Kconfig1
-rw-r--r--arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c2
-rw-r--r--arch/powerpc/platforms/powermac/pic.c6
-rw-r--r--arch/powerpc/sysdev/Makefile4
-rw-r--r--arch/powerpc/sysdev/ipic.c303
-rw-r--r--arch/powerpc/sysdev/ipic.h23
-rw-r--r--arch/powerpc/sysdev/mpic.c223
-rw-r--r--arch/ppc/kernel/smp-tbsync.c7
-rw-r--r--arch/ppc/syslib/Makefile2
-rw-r--r--arch/ppc/syslib/ipic.c646
-rw-r--r--arch/ppc/syslib/ipic.h47
-rw-r--r--arch/s390/lib/uaccess.S33
-rw-r--r--arch/s390/lib/uaccess64.S35
-rw-r--r--arch/sparc64/mm/generic.c2
-rw-r--r--arch/x86_64/defconfig66
-rw-r--r--arch/x86_64/ia32/ia32_binfmt.c57
-rw-r--r--arch/x86_64/kernel/e820.c35
-rw-r--r--arch/x86_64/kernel/entry.S3
-rw-r--r--arch/x86_64/kernel/head.S1
-rw-r--r--arch/x86_64/kernel/init_task.c5
-rw-r--r--arch/x86_64/kernel/setup.c6
-rw-r--r--arch/x86_64/kernel/setup64.c3
-rw-r--r--arch/x86_64/kernel/traps.c30
-rw-r--r--arch/x86_64/pci/mmconfig.c34
-rw-r--r--arch/xtensa/kernel/ptrace.c2
58 files changed, 2019 insertions, 603 deletions
diff --git a/arch/i386/kernel/head.S b/arch/i386/kernel/head.S
index eb79aa2fa8bb..a6b8bd89aa27 100644
--- a/arch/i386/kernel/head.S
+++ b/arch/i386/kernel/head.S
@@ -317,20 +317,14 @@ is386: movl $2,%ecx # set MP
317 movl %eax,%gs 317 movl %eax,%gs
318 lldt %ax 318 lldt %ax
319 cld # gcc2 wants the direction flag cleared at all times 319 cld # gcc2 wants the direction flag cleared at all times
320 pushl %eax # fake return address
320#ifdef CONFIG_SMP 321#ifdef CONFIG_SMP
321 movb ready, %cl 322 movb ready, %cl
322 movb $1, ready 323 movb $1, ready
323 cmpb $0,%cl 324 cmpb $0,%cl # the first CPU calls start_kernel
324 je 1f # the first CPU calls start_kernel 325 jne initialize_secondary # all other CPUs call initialize_secondary
325 # all other CPUs call initialize_secondary
326 call initialize_secondary
327 jmp L6
3281:
329#endif /* CONFIG_SMP */ 326#endif /* CONFIG_SMP */
330 call start_kernel 327 jmp start_kernel
331L6:
332 jmp L6 # main should never return here, but
333 # just in case, we know what happens.
334 328
335/* 329/*
336 * We depend on ET to be correct. This checks for 287/387. 330 * We depend on ET to be correct. This checks for 287/387.
diff --git a/arch/i386/kernel/hpet.c b/arch/i386/kernel/hpet.c
index c6737c35815d..17647a530b2f 100644
--- a/arch/i386/kernel/hpet.c
+++ b/arch/i386/kernel/hpet.c
@@ -35,7 +35,7 @@ static int __init init_hpet_clocksource(void)
35 void __iomem* hpet_base; 35 void __iomem* hpet_base;
36 u64 tmp; 36 u64 tmp;
37 37
38 if (!hpet_address) 38 if (!is_hpet_enabled())
39 return -ENODEV; 39 return -ENODEV;
40 40
41 /* calculate the hpet address: */ 41 /* calculate the hpet address: */
diff --git a/arch/i386/kernel/irq.c b/arch/i386/kernel/irq.c
index 6cb529f60dcc..5fe547cd8f9f 100644
--- a/arch/i386/kernel/irq.c
+++ b/arch/i386/kernel/irq.c
@@ -82,10 +82,6 @@ fastcall unsigned int do_IRQ(struct pt_regs *regs)
82 } 82 }
83#endif 83#endif
84 84
85 if (!irq_desc[irq].handle_irq) {
86 __do_IRQ(irq, regs);
87 goto out_exit;
88 }
89#ifdef CONFIG_4KSTACKS 85#ifdef CONFIG_4KSTACKS
90 86
91 curctx = (union irq_ctx *) current_thread_info(); 87 curctx = (union irq_ctx *) current_thread_info();
@@ -125,7 +121,6 @@ fastcall unsigned int do_IRQ(struct pt_regs *regs)
125#endif 121#endif
126 __do_IRQ(irq, regs); 122 __do_IRQ(irq, regs);
127 123
128out_exit:
129 irq_exit(); 124 irq_exit();
130 125
131 return 1; 126 return 1;
diff --git a/arch/i386/kernel/setup.c b/arch/i386/kernel/setup.c
index f1682206d304..345ffb7d904d 100644
--- a/arch/i386/kernel/setup.c
+++ b/arch/i386/kernel/setup.c
@@ -956,38 +956,6 @@ efi_memory_present_wrapper(unsigned long start, unsigned long end, void *arg)
956 return 0; 956 return 0;
957} 957}
958 958
959 /*
960 * This function checks if the entire range <start,end> is mapped with type.
961 *
962 * Note: this function only works correct if the e820 table is sorted and
963 * not-overlapping, which is the case
964 */
965int __init
966e820_all_mapped(unsigned long s, unsigned long e, unsigned type)
967{
968 u64 start = s;
969 u64 end = e;
970 int i;
971 for (i = 0; i < e820.nr_map; i++) {
972 struct e820entry *ei = &e820.map[i];
973 if (type && ei->type != type)
974 continue;
975 /* is the region (part) in overlap with the current region ?*/
976 if (ei->addr >= end || ei->addr + ei->size <= start)
977 continue;
978 /* if the region is at the beginning of <start,end> we move
979 * start to the end of the region since it's ok until there
980 */
981 if (ei->addr <= start)
982 start = ei->addr + ei->size;
983 /* if start is now at or beyond end, we're done, full
984 * coverage */
985 if (start >= end)
986 return 1; /* we're done */
987 }
988 return 0;
989}
990
991/* 959/*
992 * Find the highest page frame number we have available 960 * Find the highest page frame number we have available
993 */ 961 */
diff --git a/arch/i386/kernel/traps.c b/arch/i386/kernel/traps.c
index 82e0fd02af1c..7e9edafffd8a 100644
--- a/arch/i386/kernel/traps.c
+++ b/arch/i386/kernel/traps.c
@@ -92,7 +92,11 @@ asmlinkage void spurious_interrupt_bug(void);
92asmlinkage void machine_check(void); 92asmlinkage void machine_check(void);
93 93
94static int kstack_depth_to_print = 24; 94static int kstack_depth_to_print = 24;
95#ifdef CONFIG_STACK_UNWIND
95static int call_trace = 1; 96static int call_trace = 1;
97#else
98#define call_trace (-1)
99#endif
96ATOMIC_NOTIFIER_HEAD(i386die_chain); 100ATOMIC_NOTIFIER_HEAD(i386die_chain);
97 101
98int register_die_notifier(struct notifier_block *nb) 102int register_die_notifier(struct notifier_block *nb)
@@ -187,22 +191,21 @@ static void show_trace_log_lvl(struct task_struct *task, struct pt_regs *regs,
187 if (unwind_init_blocked(&info, task) == 0) 191 if (unwind_init_blocked(&info, task) == 0)
188 unw_ret = show_trace_unwind(&info, log_lvl); 192 unw_ret = show_trace_unwind(&info, log_lvl);
189 } 193 }
190 if (unw_ret > 0 && !arch_unw_user_mode(&info)) { 194 if (unw_ret > 0) {
191#ifdef CONFIG_STACK_UNWIND 195 if (call_trace == 1 && !arch_unw_user_mode(&info)) {
192 print_symbol("DWARF2 unwinder stuck at %s\n", 196 print_symbol("DWARF2 unwinder stuck at %s\n",
193 UNW_PC(&info)); 197 UNW_PC(&info));
194 if (call_trace == 1) { 198 if (UNW_SP(&info) >= PAGE_OFFSET) {
195 printk("Leftover inexact backtrace:\n"); 199 printk("Leftover inexact backtrace:\n");
196 if (UNW_SP(&info))
197 stack = (void *)UNW_SP(&info); 200 stack = (void *)UNW_SP(&info);
198 } else if (call_trace > 1) 201 } else
202 printk("Full inexact backtrace again:\n");
203 } else if (call_trace >= 1)
199 return; 204 return;
200 else 205 else
201 printk("Full inexact backtrace again:\n"); 206 printk("Full inexact backtrace again:\n");
202#else 207 } else
203 printk("Inexact backtrace:\n"); 208 printk("Inexact backtrace:\n");
204#endif
205 }
206 } 209 }
207 210
208 if (task == current) { 211 if (task == current) {
@@ -1241,6 +1244,7 @@ static int __init kstack_setup(char *s)
1241} 1244}
1242__setup("kstack=", kstack_setup); 1245__setup("kstack=", kstack_setup);
1243 1246
1247#ifdef CONFIG_STACK_UNWIND
1244static int __init call_trace_setup(char *s) 1248static int __init call_trace_setup(char *s)
1245{ 1249{
1246 if (strcmp(s, "old") == 0) 1250 if (strcmp(s, "old") == 0)
@@ -1254,3 +1258,4 @@ static int __init call_trace_setup(char *s)
1254 return 1; 1258 return 1;
1255} 1259}
1256__setup("call_trace=", call_trace_setup); 1260__setup("call_trace=", call_trace_setup);
1261#endif
diff --git a/arch/i386/pci/common.c b/arch/i386/pci/common.c
index 0a362e3aeac5..1220dd828ce3 100644
--- a/arch/i386/pci/common.c
+++ b/arch/i386/pci/common.c
@@ -237,6 +237,11 @@ char * __devinit pcibios_setup(char *str)
237 pci_probe &= ~PCI_PROBE_MMCONF; 237 pci_probe &= ~PCI_PROBE_MMCONF;
238 return NULL; 238 return NULL;
239 } 239 }
240 /* override DMI blacklist */
241 else if (!strcmp(str, "mmconf")) {
242 pci_probe |= PCI_PROBE_MMCONF_FORCE;
243 return NULL;
244 }
240#endif 245#endif
241 else if (!strcmp(str, "noacpi")) { 246 else if (!strcmp(str, "noacpi")) {
242 acpi_noirq_set(); 247 acpi_noirq_set();
diff --git a/arch/i386/pci/mmconfig.c b/arch/i386/pci/mmconfig.c
index 972180f738d9..ef5a2faa7d82 100644
--- a/arch/i386/pci/mmconfig.c
+++ b/arch/i386/pci/mmconfig.c
@@ -12,6 +12,7 @@
12#include <linux/pci.h> 12#include <linux/pci.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/acpi.h> 14#include <linux/acpi.h>
15#include <linux/dmi.h>
15#include <asm/e820.h> 16#include <asm/e820.h>
16#include "pci.h" 17#include "pci.h"
17 18
@@ -187,9 +188,31 @@ static __init void unreachable_devices(void)
187 } 188 }
188} 189}
189 190
191static int disable_mcfg(struct dmi_system_id *d)
192{
193 printk("PCI: %s detected. Disabling MCFG.\n", d->ident);
194 pci_probe &= ~PCI_PROBE_MMCONF;
195 return 0;
196}
197
198static struct dmi_system_id __initdata dmi_bad_mcfg[] = {
199 /* Has broken MCFG table that makes the system hang when used */
200 {
201 .callback = disable_mcfg,
202 .ident = "Intel D3C5105 SDV",
203 .matches = {
204 DMI_MATCH(DMI_BIOS_VENDOR, "Intel"),
205 DMI_MATCH(DMI_BOARD_NAME, "D26928"),
206 },
207 },
208 {}
209};
210
190void __init pci_mmcfg_init(void) 211void __init pci_mmcfg_init(void)
191{ 212{
192 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 213 dmi_check_system(dmi_bad_mcfg);
214
215 if ((pci_probe & (PCI_PROBE_MMCONF_FORCE|PCI_PROBE_MMCONF)) == 0)
193 return; 216 return;
194 217
195 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg); 218 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
@@ -198,15 +221,6 @@ void __init pci_mmcfg_init(void)
198 (pci_mmcfg_config[0].base_address == 0)) 221 (pci_mmcfg_config[0].base_address == 0))
199 return; 222 return;
200 223
201 if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
202 pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
203 E820_RESERVED)) {
204 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
205 pci_mmcfg_config[0].base_address);
206 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
207 return;
208 }
209
210 printk(KERN_INFO "PCI: Using MMCONFIG\n"); 224 printk(KERN_INFO "PCI: Using MMCONFIG\n");
211 raw_pci_ops = &pci_mmcfg; 225 raw_pci_ops = &pci_mmcfg;
212 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; 226 pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
diff --git a/arch/i386/pci/pci.h b/arch/i386/pci/pci.h
index bf4e79335388..49a849b3a241 100644
--- a/arch/i386/pci/pci.h
+++ b/arch/i386/pci/pci.h
@@ -16,7 +16,8 @@
16#define PCI_PROBE_CONF1 0x0002 16#define PCI_PROBE_CONF1 0x0002
17#define PCI_PROBE_CONF2 0x0004 17#define PCI_PROBE_CONF2 0x0004
18#define PCI_PROBE_MMCONF 0x0008 18#define PCI_PROBE_MMCONF 0x0008
19#define PCI_PROBE_MASK 0x000f 19#define PCI_PROBE_MMCONF_FORCE 0x0010
20#define PCI_PROBE_MASK 0x00ff
20 21
21#define PCI_NO_SORT 0x0100 22#define PCI_NO_SORT 0x0100
22#define PCI_BIOS_SORT 0x0200 23#define PCI_BIOS_SORT 0x0200
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index 47de9ee6bcd6..674de8943478 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -258,7 +258,7 @@ config NR_CPUS
258 int "Maximum number of CPUs (2-1024)" 258 int "Maximum number of CPUs (2-1024)"
259 range 2 1024 259 range 2 1024
260 depends on SMP 260 depends on SMP
261 default "64" 261 default "1024"
262 help 262 help
263 You should set this to the number of CPUs in your system, but 263 You should set this to the number of CPUs in your system, but
264 keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but 264 keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but
@@ -354,7 +354,7 @@ config NUMA
354config NODES_SHIFT 354config NODES_SHIFT
355 int "Max num nodes shift(3-10)" 355 int "Max num nodes shift(3-10)"
356 range 3 10 356 range 3 10
357 default "8" 357 default "10"
358 depends on NEED_MULTIPLE_NODES 358 depends on NEED_MULTIPLE_NODES
359 help 359 help
360 This option specifies the maximum number of nodes in your SSI system. 360 This option specifies the maximum number of nodes in your SSI system.
diff --git a/arch/ia64/kernel/topology.c b/arch/ia64/kernel/topology.c
index d24fa393b182..f648c610b10c 100644
--- a/arch/ia64/kernel/topology.c
+++ b/arch/ia64/kernel/topology.c
@@ -67,10 +67,8 @@ static int __init topology_init(void)
67#endif 67#endif
68 68
69 sysfs_cpus = kzalloc(sizeof(struct ia64_cpu) * NR_CPUS, GFP_KERNEL); 69 sysfs_cpus = kzalloc(sizeof(struct ia64_cpu) * NR_CPUS, GFP_KERNEL);
70 if (!sysfs_cpus) { 70 if (!sysfs_cpus)
71 err = -ENOMEM; 71 panic("kzalloc in topology_init failed - NR_CPUS too big?");
72 goto out;
73 }
74 72
75 for_each_present_cpu(i) { 73 for_each_present_cpu(i) {
76 if((err = arch_register_cpu(i))) 74 if((err = arch_register_cpu(i)))
diff --git a/arch/ia64/sn/kernel/xpc_channel.c b/arch/ia64/sn/kernel/xpc_channel.c
index c2f69f7942af..1f3540826e68 100644
--- a/arch/ia64/sn/kernel/xpc_channel.c
+++ b/arch/ia64/sn/kernel/xpc_channel.c
@@ -279,8 +279,8 @@ xpc_pull_remote_cachelines(struct xpc_partition *part, void *dst,
279 return part->reason; 279 return part->reason;
280 } 280 }
281 281
282 bte_ret = xp_bte_copy((u64) src, (u64) ia64_tpa((u64) dst), 282 bte_ret = xp_bte_copy((u64) src, (u64) dst, (u64) cnt,
283 (u64) cnt, (BTE_NORMAL | BTE_WACQUIRE), NULL); 283 (BTE_NORMAL | BTE_WACQUIRE), NULL);
284 if (bte_ret == BTE_SUCCESS) { 284 if (bte_ret == BTE_SUCCESS) {
285 return xpcSuccess; 285 return xpcSuccess;
286 } 286 }
diff --git a/arch/ia64/sn/kernel/xpc_main.c b/arch/ia64/sn/kernel/xpc_main.c
index 5e8e59efb347..4d026f9dd98b 100644
--- a/arch/ia64/sn/kernel/xpc_main.c
+++ b/arch/ia64/sn/kernel/xpc_main.c
@@ -1052,6 +1052,8 @@ xpc_do_exit(enum xpc_retval reason)
1052 if (xpc_sysctl) { 1052 if (xpc_sysctl) {
1053 unregister_sysctl_table(xpc_sysctl); 1053 unregister_sysctl_table(xpc_sysctl);
1054 } 1054 }
1055
1056 kfree(xpc_remote_copy_buffer_base);
1055} 1057}
1056 1058
1057 1059
@@ -1212,24 +1214,20 @@ xpc_init(void)
1212 partid_t partid; 1214 partid_t partid;
1213 struct xpc_partition *part; 1215 struct xpc_partition *part;
1214 pid_t pid; 1216 pid_t pid;
1217 size_t buf_size;
1215 1218
1216 1219
1217 if (!ia64_platform_is("sn2")) { 1220 if (!ia64_platform_is("sn2")) {
1218 return -ENODEV; 1221 return -ENODEV;
1219 } 1222 }
1220 1223
1221 /* 1224
1222 * xpc_remote_copy_buffer is used as a temporary buffer for bte_copy'ng 1225 buf_size = max(XPC_RP_VARS_SIZE,
1223 * various portions of a partition's reserved page. Its size is based 1226 XPC_RP_HEADER_SIZE + XP_NASID_MASK_BYTES);
1224 * on the size of the reserved page header and part_nasids mask. So we 1227 xpc_remote_copy_buffer = xpc_kmalloc_cacheline_aligned(buf_size,
1225 * need to ensure that the other items will fit as well. 1228 GFP_KERNEL, &xpc_remote_copy_buffer_base);
1226 */ 1229 if (xpc_remote_copy_buffer == NULL)
1227 if (XPC_RP_VARS_SIZE > XPC_RP_HEADER_SIZE + XP_NASID_MASK_BYTES) { 1230 return -ENOMEM;
1228 dev_err(xpc_part, "xpc_remote_copy_buffer is not big enough\n");
1229 return -EPERM;
1230 }
1231 DBUG_ON((u64) xpc_remote_copy_buffer !=
1232 L1_CACHE_ALIGN((u64) xpc_remote_copy_buffer));
1233 1231
1234 snprintf(xpc_part->bus_id, BUS_ID_SIZE, "part"); 1232 snprintf(xpc_part->bus_id, BUS_ID_SIZE, "part");
1235 snprintf(xpc_chan->bus_id, BUS_ID_SIZE, "chan"); 1233 snprintf(xpc_chan->bus_id, BUS_ID_SIZE, "chan");
@@ -1293,6 +1291,8 @@ xpc_init(void)
1293 if (xpc_sysctl) { 1291 if (xpc_sysctl) {
1294 unregister_sysctl_table(xpc_sysctl); 1292 unregister_sysctl_table(xpc_sysctl);
1295 } 1293 }
1294
1295 kfree(xpc_remote_copy_buffer_base);
1296 return -EBUSY; 1296 return -EBUSY;
1297 } 1297 }
1298 1298
@@ -1311,6 +1311,8 @@ xpc_init(void)
1311 if (xpc_sysctl) { 1311 if (xpc_sysctl) {
1312 unregister_sysctl_table(xpc_sysctl); 1312 unregister_sysctl_table(xpc_sysctl);
1313 } 1313 }
1314
1315 kfree(xpc_remote_copy_buffer_base);
1314 return -EBUSY; 1316 return -EBUSY;
1315 } 1317 }
1316 1318
@@ -1362,6 +1364,8 @@ xpc_init(void)
1362 if (xpc_sysctl) { 1364 if (xpc_sysctl) {
1363 unregister_sysctl_table(xpc_sysctl); 1365 unregister_sysctl_table(xpc_sysctl);
1364 } 1366 }
1367
1368 kfree(xpc_remote_copy_buffer_base);
1365 return -EBUSY; 1369 return -EBUSY;
1366 } 1370 }
1367 1371
diff --git a/arch/ia64/sn/kernel/xpc_partition.c b/arch/ia64/sn/kernel/xpc_partition.c
index 2a89cfce4954..57c723f5cba4 100644
--- a/arch/ia64/sn/kernel/xpc_partition.c
+++ b/arch/ia64/sn/kernel/xpc_partition.c
@@ -71,19 +71,15 @@ struct xpc_partition xpc_partitions[XP_MAX_PARTITIONS + 1];
71 * Generic buffer used to store a local copy of portions of a remote 71 * Generic buffer used to store a local copy of portions of a remote
72 * partition's reserved page (either its header and part_nasids mask, 72 * partition's reserved page (either its header and part_nasids mask,
73 * or its vars). 73 * or its vars).
74 *
75 * xpc_discovery runs only once and is a seperate thread that is
76 * very likely going to be processing in parallel with receiving
77 * interrupts.
78 */ 74 */
79char ____cacheline_aligned xpc_remote_copy_buffer[XPC_RP_HEADER_SIZE + 75char *xpc_remote_copy_buffer;
80 XP_NASID_MASK_BYTES]; 76void *xpc_remote_copy_buffer_base;
81 77
82 78
83/* 79/*
84 * Guarantee that the kmalloc'd memory is cacheline aligned. 80 * Guarantee that the kmalloc'd memory is cacheline aligned.
85 */ 81 */
86static void * 82void *
87xpc_kmalloc_cacheline_aligned(size_t size, gfp_t flags, void **base) 83xpc_kmalloc_cacheline_aligned(size_t size, gfp_t flags, void **base)
88{ 84{
89 /* see if kmalloc will give us cachline aligned memory by default */ 85 /* see if kmalloc will give us cachline aligned memory by default */
@@ -148,7 +144,7 @@ xpc_get_rsvd_page_pa(int nasid)
148 } 144 }
149 } 145 }
150 146
151 bte_res = xp_bte_copy(rp_pa, ia64_tpa(buf), buf_len, 147 bte_res = xp_bte_copy(rp_pa, buf, buf_len,
152 (BTE_NOTIFY | BTE_WACQUIRE), NULL); 148 (BTE_NOTIFY | BTE_WACQUIRE), NULL);
153 if (bte_res != BTE_SUCCESS) { 149 if (bte_res != BTE_SUCCESS) {
154 dev_dbg(xpc_part, "xp_bte_copy failed %i\n", bte_res); 150 dev_dbg(xpc_part, "xp_bte_copy failed %i\n", bte_res);
@@ -447,7 +443,7 @@ xpc_check_remote_hb(void)
447 443
448 /* pull the remote_hb cache line */ 444 /* pull the remote_hb cache line */
449 bres = xp_bte_copy(part->remote_vars_pa, 445 bres = xp_bte_copy(part->remote_vars_pa,
450 ia64_tpa((u64) remote_vars), 446 (u64) remote_vars,
451 XPC_RP_VARS_SIZE, 447 XPC_RP_VARS_SIZE,
452 (BTE_NOTIFY | BTE_WACQUIRE), NULL); 448 (BTE_NOTIFY | BTE_WACQUIRE), NULL);
453 if (bres != BTE_SUCCESS) { 449 if (bres != BTE_SUCCESS) {
@@ -498,8 +494,7 @@ xpc_get_remote_rp(int nasid, u64 *discovered_nasids,
498 494
499 495
500 /* pull over the reserved page header and part_nasids mask */ 496 /* pull over the reserved page header and part_nasids mask */
501 497 bres = xp_bte_copy(*remote_rp_pa, (u64) remote_rp,
502 bres = xp_bte_copy(*remote_rp_pa, ia64_tpa((u64) remote_rp),
503 XPC_RP_HEADER_SIZE + xp_nasid_mask_bytes, 498 XPC_RP_HEADER_SIZE + xp_nasid_mask_bytes,
504 (BTE_NOTIFY | BTE_WACQUIRE), NULL); 499 (BTE_NOTIFY | BTE_WACQUIRE), NULL);
505 if (bres != BTE_SUCCESS) { 500 if (bres != BTE_SUCCESS) {
@@ -554,11 +549,8 @@ xpc_get_remote_vars(u64 remote_vars_pa, struct xpc_vars *remote_vars)
554 return xpcVarsNotSet; 549 return xpcVarsNotSet;
555 } 550 }
556 551
557
558 /* pull over the cross partition variables */ 552 /* pull over the cross partition variables */
559 553 bres = xp_bte_copy(remote_vars_pa, (u64) remote_vars, XPC_RP_VARS_SIZE,
560 bres = xp_bte_copy(remote_vars_pa, ia64_tpa((u64) remote_vars),
561 XPC_RP_VARS_SIZE,
562 (BTE_NOTIFY | BTE_WACQUIRE), NULL); 554 (BTE_NOTIFY | BTE_WACQUIRE), NULL);
563 if (bres != BTE_SUCCESS) { 555 if (bres != BTE_SUCCESS) {
564 return xpc_map_bte_errors(bres); 556 return xpc_map_bte_errors(bres);
@@ -1239,7 +1231,7 @@ xpc_initiate_partid_to_nasids(partid_t partid, void *nasid_mask)
1239 1231
1240 part_nasid_pa = (u64) XPC_RP_PART_NASIDS(part->remote_rp_pa); 1232 part_nasid_pa = (u64) XPC_RP_PART_NASIDS(part->remote_rp_pa);
1241 1233
1242 bte_res = xp_bte_copy(part_nasid_pa, ia64_tpa((u64) nasid_mask), 1234 bte_res = xp_bte_copy(part_nasid_pa, (u64) nasid_mask,
1243 xp_nasid_mask_bytes, (BTE_NOTIFY | BTE_WACQUIRE), NULL); 1235 xp_nasid_mask_bytes, (BTE_NOTIFY | BTE_WACQUIRE), NULL);
1244 1236
1245 return xpc_map_bte_errors(bte_res); 1237 return xpc_map_bte_errors(bte_res);
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index abb325eb8f75..4d4b6fb156e1 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -354,6 +354,7 @@ endchoice
354config PPC_PSERIES 354config PPC_PSERIES
355 depends on PPC_MULTIPLATFORM && PPC64 355 depends on PPC_MULTIPLATFORM && PPC64
356 bool "IBM pSeries & new (POWER5-based) iSeries" 356 bool "IBM pSeries & new (POWER5-based) iSeries"
357 select MPIC
357 select PPC_I8259 358 select PPC_I8259
358 select PPC_RTAS 359 select PPC_RTAS
359 select RTAS_ERROR_LOGGING 360 select RTAS_ERROR_LOGGING
@@ -363,6 +364,7 @@ config PPC_PSERIES
363config PPC_CHRP 364config PPC_CHRP
364 bool "Common Hardware Reference Platform (CHRP) based machines" 365 bool "Common Hardware Reference Platform (CHRP) based machines"
365 depends on PPC_MULTIPLATFORM && PPC32 366 depends on PPC_MULTIPLATFORM && PPC32
367 select MPIC
366 select PPC_I8259 368 select PPC_I8259
367 select PPC_INDIRECT_PCI 369 select PPC_INDIRECT_PCI
368 select PPC_RTAS 370 select PPC_RTAS
@@ -373,6 +375,7 @@ config PPC_CHRP
373config PPC_PMAC 375config PPC_PMAC
374 bool "Apple PowerMac based machines" 376 bool "Apple PowerMac based machines"
375 depends on PPC_MULTIPLATFORM 377 depends on PPC_MULTIPLATFORM
378 select MPIC
376 select PPC_INDIRECT_PCI if PPC32 379 select PPC_INDIRECT_PCI if PPC32
377 select PPC_MPC106 if PPC32 380 select PPC_MPC106 if PPC32
378 default y 381 default y
@@ -380,6 +383,7 @@ config PPC_PMAC
380config PPC_PMAC64 383config PPC_PMAC64
381 bool 384 bool
382 depends on PPC_PMAC && POWER4 385 depends on PPC_PMAC && POWER4
386 select MPIC
383 select U3_DART 387 select U3_DART
384 select MPIC_BROKEN_U3 388 select MPIC_BROKEN_U3
385 select GENERIC_TBSYNC 389 select GENERIC_TBSYNC
@@ -389,6 +393,7 @@ config PPC_PMAC64
389config PPC_PREP 393config PPC_PREP
390 bool "PowerPC Reference Platform (PReP) based machines" 394 bool "PowerPC Reference Platform (PReP) based machines"
391 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN 395 depends on PPC_MULTIPLATFORM && PPC32 && BROKEN
396 select MPIC
392 select PPC_I8259 397 select PPC_I8259
393 select PPC_INDIRECT_PCI 398 select PPC_INDIRECT_PCI
394 select PPC_UDBG_16550 399 select PPC_UDBG_16550
@@ -397,6 +402,7 @@ config PPC_PREP
397config PPC_MAPLE 402config PPC_MAPLE
398 depends on PPC_MULTIPLATFORM && PPC64 403 depends on PPC_MULTIPLATFORM && PPC64
399 bool "Maple 970FX Evaluation Board" 404 bool "Maple 970FX Evaluation Board"
405 select MPIC
400 select U3_DART 406 select U3_DART
401 select MPIC_BROKEN_U3 407 select MPIC_BROKEN_U3
402 select GENERIC_TBSYNC 408 select GENERIC_TBSYNC
@@ -439,12 +445,6 @@ config U3_DART
439 depends on PPC_MULTIPLATFORM && PPC64 445 depends on PPC_MULTIPLATFORM && PPC64
440 default n 446 default n
441 447
442config MPIC
443 depends on PPC_PSERIES || PPC_PMAC || PPC_MAPLE || PPC_CHRP \
444 || MPC7448HPC2
445 bool
446 default y
447
448config PPC_RTAS 448config PPC_RTAS
449 bool 449 bool
450 default n 450 default n
@@ -812,6 +812,14 @@ config GENERIC_ISA_DMA
812 depends on PPC64 || POWER4 || 6xx && !CPM2 812 depends on PPC64 || POWER4 || 6xx && !CPM2
813 default y 813 default y
814 814
815config MPIC
816 bool
817 default n
818
819config MPIC_WEIRD
820 bool
821 default n
822
815config PPC_I8259 823config PPC_I8259
816 bool 824 bool
817 default n 825 default n
diff --git a/arch/powerpc/boot/dts/mpc7448hpc2.dts b/arch/powerpc/boot/dts/mpc7448hpc2.dts
new file mode 100644
index 000000000000..d7b985e6bd2f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc7448hpc2.dts
@@ -0,0 +1,190 @@
1/*
2 * MPC7448HPC2 (Taiga) board Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * 2006 Roy Zang <Roy Zang at freescale.com>.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13
14/ {
15 model = "mpc7448hpc2";
16 compatible = "mpc74xx";
17 #address-cells = <1>;
18 #size-cells = <1>;
19 linux,phandle = <100>;
20
21 cpus {
22 #cpus = <1>;
23 #address-cells = <1>;
24 #size-cells =<0>;
25 linux,phandle = <200>;
26
27 PowerPC,7448@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K bytes
33 i-cache-size = <8000>; // L1, 32K bytes
34 timebase-frequency = <0>; // 33 MHz, from uboot
35 clock-frequency = <0>; // From U-Boot
36 bus-frequency = <0>; // From U-Boot
37 32-bit;
38 linux,phandle = <201>;
39 linux,boot-cpu;
40 };
41 };
42
43 memory {
44 device_type = "memory";
45 linux,phandle = <300>;
46 reg = <00000000 20000000 // DDR2 512M at 0
47 >;
48 };
49
50 tsi108@c0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "tsi-bridge";
55 ranges = <00000000 c0000000 00010000>;
56 reg = <c0000000 00010000>;
57 bus-frequency = <0>;
58
59 i2c@7000 {
60 interrupt-parent = <7400>;
61 interrupts = <E 0>;
62 reg = <7000 400>;
63 device_type = "i2c";
64 compatible = "tsi-i2c";
65 };
66
67 mdio@6000 {
68 device_type = "mdio";
69 compatible = "tsi-ethernet";
70
71 ethernet-phy@6000 {
72 linux,phandle = <6000>;
73 interrupt-parent = <7400>;
74 interrupts = <2 1>;
75 reg = <6000 50>;
76 phy-id = <8>;
77 device_type = "ethernet-phy";
78 };
79
80 ethernet-phy@6400 {
81 linux,phandle = <6400>;
82 interrupt-parent = <7400>;
83 interrupts = <2 1>;
84 reg = <6000 50>;
85 phy-id = <9>;
86 device_type = "ethernet-phy";
87 };
88
89 };
90
91 ethernet@6200 {
92 #size-cells = <0>;
93 device_type = "network";
94 model = "TSI-ETH";
95 compatible = "tsi-ethernet";
96 reg = <6000 200>;
97 address = [ 00 06 D2 00 00 01 ];
98 interrupts = <10 2>;
99 interrupt-parent = <7400>;
100 phy-handle = <6000>;
101 };
102
103 ethernet@6600 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 device_type = "network";
107 model = "TSI-ETH";
108 compatible = "tsi-ethernet";
109 reg = <6400 200>;
110 address = [ 00 06 D2 00 00 02 ];
111 interrupts = <11 2>;
112 interrupt-parent = <7400>;
113 phy-handle = <6400>;
114 };
115
116 serial@7808 {
117 device_type = "serial";
118 compatible = "ns16550";
119 reg = <7808 200>;
120 clock-frequency = <3f6b5a00>;
121 interrupts = <c 0>;
122 interrupt-parent = <7400>;
123 };
124
125 serial@7c08 {
126 device_type = "serial";
127 compatible = "ns16550";
128 reg = <7c08 200>;
129 clock-frequency = <3f6b5a00>;
130 interrupts = <d 0>;
131 interrupt-parent = <7400>;
132 };
133
134 pic@7400 {
135 linux,phandle = <7400>;
136 clock-frequency = <0>;
137 interrupt-controller;
138 #address-cells = <0>;
139 #interrupt-cells = <2>;
140 reg = <7400 400>;
141 built-in;
142 compatible = "chrp,open-pic";
143 device_type = "open-pic";
144 big-endian;
145 };
146 pci@1000 {
147 compatible = "tsi10x";
148 device_type = "pci";
149 linux,phandle = <1000>;
150 #interrupt-cells = <1>;
151 #size-cells = <2>;
152 #address-cells = <3>;
153 reg = <1000 1000>;
154 bus-range = <0 0>;
155 ranges = <02000000 0 e0000000 e0000000 0 1A000000
156 01000000 0 00000000 fa000000 0 00010000>;
157 clock-frequency = <7f28154>;
158 interrupt-parent = <7400>;
159 interrupts = <17 2>;
160 interrupt-map-mask = <f800 0 0 7>;
161 interrupt-map = <
162
163 /* IDSEL 0x11 */
164 0800 0 0 1 7400 24 0
165 0800 0 0 2 7400 25 0
166 0800 0 0 3 7400 26 0
167 0800 0 0 4 7400 27 0
168
169 /* IDSEL 0x12 */
170 1000 0 0 1 7400 25 0
171 1000 0 0 2 7400 26 0
172 1000 0 0 3 7400 27 0
173 1000 0 0 4 7400 24 0
174
175 /* IDSEL 0x13 */
176 1800 0 0 1 7400 26 0
177 1800 0 0 2 7400 27 0
178 1800 0 0 3 7400 24 0
179 1800 0 0 4 7400 25 0
180
181 /* IDSEL 0x14 */
182 2000 0 0 1 7400 27 0
183 2000 0 0 2 7400 24 0
184 2000 0 0 3 7400 25 0
185 2000 0 0 4 7400 26 0
186 >;
187 };
188 };
189
190};
diff --git a/arch/powerpc/boot/dts/mpc8349emds.dts b/arch/powerpc/boot/dts/mpc8349emds.dts
new file mode 100644
index 000000000000..12f5dbf3055f
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8349emds.dts
@@ -0,0 +1,328 @@
1/*
2 * MPC8349E MDS Device Tree Source
3 *
4 * Copyright 2005, 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12/ {
13 model = "MPC8349EMDS";
14 compatible = "MPC834xMDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
17
18 cpus {
19 #cpus = <1>;
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 PowerPC,8349@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // from bootloader
31 bus-frequency = <0>; // from bootloader
32 clock-frequency = <0>; // from bootloader
33 32-bit;
34 };
35 };
36
37 memory {
38 device_type = "memory";
39 reg = <00000000 10000000>; // 256MB at 0
40 };
41
42 soc8349@e0000000 {
43 #address-cells = <1>;
44 #size-cells = <1>;
45 #interrupt-cells = <2>;
46 device_type = "soc";
47 ranges = <0 e0000000 00100000>;
48 reg = <e0000000 00000200>;
49 bus-frequency = <0>;
50
51 wdt@200 {
52 device_type = "watchdog";
53 compatible = "mpc83xx_wdt";
54 reg = <200 100>;
55 };
56
57 i2c@3000 {
58 device_type = "i2c";
59 compatible = "fsl-i2c";
60 reg = <3000 100>;
61 interrupts = <e 8>;
62 interrupt-parent = <700>;
63 dfsrr;
64 };
65
66 i2c@3100 {
67 device_type = "i2c";
68 compatible = "fsl-i2c";
69 reg = <3100 100>;
70 interrupts = <f 8>;
71 interrupt-parent = <700>;
72 dfsrr;
73 };
74
75 spi@7000 {
76 device_type = "spi";
77 compatible = "mpc83xx_spi";
78 reg = <7000 1000>;
79 interrupts = <10 8>;
80 interrupt-parent = <700>;
81 mode = <0>;
82 };
83
84 /* phy type (ULPI or SERIAL) are only types supportted for MPH */
85 /* port = 0 or 1 */
86 usb@22000 {
87 device_type = "usb";
88 compatible = "fsl-usb2-mph";
89 reg = <22000 1000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 interrupt-parent = <700>;
93 interrupts = <27 2>;
94 phy_type = "ulpi";
95 port1;
96 };
97 /* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
98 usb@23000 {
99 device_type = "usb";
100 compatible = "fsl-usb2-dr";
101 reg = <23000 1000>;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 interrupt-parent = <700>;
105 interrupts = <26 2>;
106 phy_type = "ulpi";
107 };
108
109 mdio@24520 {
110 device_type = "mdio";
111 compatible = "gianfar";
112 reg = <24520 20>;
113 #address-cells = <1>;
114 #size-cells = <0>;
115 linux,phandle = <24520>;
116 ethernet-phy@0 {
117 linux,phandle = <2452000>;
118 interrupt-parent = <700>;
119 interrupts = <11 2>;
120 reg = <0>;
121 device_type = "ethernet-phy";
122 };
123 ethernet-phy@1 {
124 linux,phandle = <2452001>;
125 interrupt-parent = <700>;
126 interrupts = <12 2>;
127 reg = <1>;
128 device_type = "ethernet-phy";
129 };
130 };
131
132 ethernet@24000 {
133 device_type = "network";
134 model = "TSEC";
135 compatible = "gianfar";
136 reg = <24000 1000>;
137 address = [ 00 00 00 00 00 00 ];
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <20 8 21 8 22 8>;
140 interrupt-parent = <700>;
141 phy-handle = <2452000>;
142 };
143
144 ethernet@25000 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 device_type = "network";
148 model = "TSEC";
149 compatible = "gianfar";
150 reg = <25000 1000>;
151 address = [ 00 00 00 00 00 00 ];
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <23 8 24 8 25 8>;
154 interrupt-parent = <700>;
155 phy-handle = <2452001>;
156 };
157
158 serial@4500 {
159 device_type = "serial";
160 compatible = "ns16550";
161 reg = <4500 100>;
162 clock-frequency = <0>;
163 interrupts = <9 8>;
164 interrupt-parent = <700>;
165 };
166
167 serial@4600 {
168 device_type = "serial";
169 compatible = "ns16550";
170 reg = <4600 100>;
171 clock-frequency = <0>;
172 interrupts = <a 8>;
173 interrupt-parent = <700>;
174 };
175
176 pci@8500 {
177 interrupt-map-mask = <f800 0 0 7>;
178 interrupt-map = <
179
180 /* IDSEL 0x11 */
181 8800 0 0 1 700 14 8
182 8800 0 0 2 700 15 8
183 8800 0 0 3 700 16 8
184 8800 0 0 4 700 17 8
185
186 /* IDSEL 0x12 */
187 9000 0 0 1 700 16 8
188 9000 0 0 2 700 17 8
189 9000 0 0 3 700 14 8
190 9000 0 0 4 700 15 8
191
192 /* IDSEL 0x13 */
193 9800 0 0 1 700 17 8
194 9800 0 0 2 700 14 8
195 9800 0 0 3 700 15 8
196 9800 0 0 4 700 16 8
197
198 /* IDSEL 0x15 */
199 a800 0 0 1 700 14 8
200 a800 0 0 2 700 15 8
201 a800 0 0 3 700 16 8
202 a800 0 0 4 700 17 8
203
204 /* IDSEL 0x16 */
205 b000 0 0 1 700 17 8
206 b000 0 0 2 700 14 8
207 b000 0 0 3 700 15 8
208 b000 0 0 4 700 16 8
209
210 /* IDSEL 0x17 */
211 b800 0 0 1 700 16 8
212 b800 0 0 2 700 17 8
213 b800 0 0 3 700 14 8
214 b800 0 0 4 700 15 8
215
216 /* IDSEL 0x18 */
217 b000 0 0 1 700 15 8
218 b000 0 0 2 700 16 8
219 b000 0 0 3 700 17 8
220 b000 0 0 4 700 14 8>;
221 interrupt-parent = <700>;
222 interrupts = <42 8>;
223 bus-range = <0 0>;
224 ranges = <02000000 0 a0000000 a0000000 0 10000000
225 42000000 0 80000000 80000000 0 10000000
226 01000000 0 00000000 e2000000 0 00100000>;
227 clock-frequency = <3f940aa>;
228 #interrupt-cells = <1>;
229 #size-cells = <2>;
230 #address-cells = <3>;
231 reg = <8500 100>;
232 compatible = "83xx";
233 device_type = "pci";
234 };
235
236 pci@8600 {
237 interrupt-map-mask = <f800 0 0 7>;
238 interrupt-map = <
239
240 /* IDSEL 0x11 */
241 8800 0 0 1 700 14 8
242 8800 0 0 2 700 15 8
243 8800 0 0 3 700 16 8
244 8800 0 0 4 700 17 8
245
246 /* IDSEL 0x12 */
247 9000 0 0 1 700 16 8
248 9000 0 0 2 700 17 8
249 9000 0 0 3 700 14 8
250 9000 0 0 4 700 15 8
251
252 /* IDSEL 0x13 */
253 9800 0 0 1 700 17 8
254 9800 0 0 2 700 14 8
255 9800 0 0 3 700 15 8
256 9800 0 0 4 700 16 8
257
258 /* IDSEL 0x15 */
259 a800 0 0 1 700 14 8
260 a800 0 0 2 700 15 8
261 a800 0 0 3 700 16 8
262 a800 0 0 4 700 17 8
263
264 /* IDSEL 0x16 */
265 b000 0 0 1 700 17 8
266 b000 0 0 2 700 14 8
267 b000 0 0 3 700 15 8
268 b000 0 0 4 700 16 8
269
270 /* IDSEL 0x17 */
271 b800 0 0 1 700 16 8
272 b800 0 0 2 700 17 8
273 b800 0 0 3 700 14 8
274 b800 0 0 4 700 15 8
275
276 /* IDSEL 0x18 */
277 b000 0 0 1 700 15 8
278 b000 0 0 2 700 16 8
279 b000 0 0 3 700 17 8
280 b000 0 0 4 700 14 8>;
281 interrupt-parent = <700>;
282 interrupts = <42 8>;
283 bus-range = <0 0>;
284 ranges = <02000000 0 b0000000 b0000000 0 10000000
285 42000000 0 90000000 90000000 0 10000000
286 01000000 0 00000000 e2100000 0 00100000>;
287 clock-frequency = <3f940aa>;
288 #interrupt-cells = <1>;
289 #size-cells = <2>;
290 #address-cells = <3>;
291 reg = <8600 100>;
292 compatible = "83xx";
293 device_type = "pci";
294 };
295
296 /* May need to remove if on a part without crypto engine */
297 crypto@30000 {
298 device_type = "crypto";
299 model = "SEC2";
300 compatible = "talitos";
301 reg = <30000 10000>;
302 interrupts = <b 8>;
303 interrupt-parent = <700>;
304 num-channels = <4>;
305 channel-fifo-len = <18>;
306 exec-units-mask = <0000007e>;
307 /* desc mask is for rev2.0,
308 * we need runtime fixup for >2.0 */
309 descriptor-types-mask = <01010ebf>;
310 };
311
312 /* IPIC
313 * interrupts cell = <intr #, sense>
314 * sense values match linux IORESOURCE_IRQ_* defines:
315 * sense == 8: Level, low assertion
316 * sense == 2: Edge, high-to-low change
317 */
318 pic@700 {
319 linux,phandle = <700>;
320 interrupt-controller;
321 #address-cells = <0>;
322 #interrupt-cells = <2>;
323 reg = <700 100>;
324 built-in;
325 device_type = "ipic";
326 };
327 };
328};
diff --git a/arch/powerpc/configs/mpc834x_sys_defconfig b/arch/powerpc/configs/mpc834x_mds_defconfig
index 5078b0441d61..5078b0441d61 100644
--- a/arch/powerpc/configs/mpc834x_sys_defconfig
+++ b/arch/powerpc/configs/mpc834x_mds_defconfig
diff --git a/arch/powerpc/kernel/fpu.S b/arch/powerpc/kernel/fpu.S
index 7e2c9fe44ac1..821e152e093c 100644
--- a/arch/powerpc/kernel/fpu.S
+++ b/arch/powerpc/kernel/fpu.S
@@ -2,6 +2,11 @@
2 * FPU support code, moved here from head.S so that it can be used 2 * FPU support code, moved here from head.S so that it can be used
3 * by chips which use other head-whatever.S files. 3 * by chips which use other head-whatever.S files.
4 * 4 *
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9 *
5 * This program is free software; you can redistribute it and/or 10 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 11 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 12 * as published by the Free Software Foundation; either version
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 7ee685433319..12c5971d6565 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -322,7 +322,8 @@ EXPORT_SYMBOL(do_softirq);
322 322
323static LIST_HEAD(irq_hosts); 323static LIST_HEAD(irq_hosts);
324static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED; 324static spinlock_t irq_big_lock = SPIN_LOCK_UNLOCKED;
325 325static DEFINE_PER_CPU(unsigned int, irq_radix_reader);
326static unsigned int irq_radix_writer;
326struct irq_map_entry irq_map[NR_IRQS]; 327struct irq_map_entry irq_map[NR_IRQS];
327static unsigned int irq_virq_count = NR_IRQS; 328static unsigned int irq_virq_count = NR_IRQS;
328static struct irq_host *irq_default_host; 329static struct irq_host *irq_default_host;
@@ -455,6 +456,58 @@ void irq_set_virq_count(unsigned int count)
455 irq_virq_count = count; 456 irq_virq_count = count;
456} 457}
457 458
459/* radix tree not lockless safe ! we use a brlock-type mecanism
460 * for now, until we can use a lockless radix tree
461 */
462static void irq_radix_wrlock(unsigned long *flags)
463{
464 unsigned int cpu, ok;
465
466 spin_lock_irqsave(&irq_big_lock, *flags);
467 irq_radix_writer = 1;
468 smp_mb();
469 do {
470 barrier();
471 ok = 1;
472 for_each_possible_cpu(cpu) {
473 if (per_cpu(irq_radix_reader, cpu)) {
474 ok = 0;
475 break;
476 }
477 }
478 if (!ok)
479 cpu_relax();
480 } while(!ok);
481}
482
483static void irq_radix_wrunlock(unsigned long flags)
484{
485 smp_wmb();
486 irq_radix_writer = 0;
487 spin_unlock_irqrestore(&irq_big_lock, flags);
488}
489
490static void irq_radix_rdlock(unsigned long *flags)
491{
492 local_irq_save(*flags);
493 __get_cpu_var(irq_radix_reader) = 1;
494 smp_mb();
495 if (likely(irq_radix_writer == 0))
496 return;
497 __get_cpu_var(irq_radix_reader) = 0;
498 smp_wmb();
499 spin_lock(&irq_big_lock);
500 __get_cpu_var(irq_radix_reader) = 1;
501 spin_unlock(&irq_big_lock);
502}
503
504static void irq_radix_rdunlock(unsigned long flags)
505{
506 __get_cpu_var(irq_radix_reader) = 0;
507 local_irq_restore(flags);
508}
509
510
458unsigned int irq_create_mapping(struct irq_host *host, 511unsigned int irq_create_mapping(struct irq_host *host,
459 irq_hw_number_t hwirq) 512 irq_hw_number_t hwirq)
460{ 513{
@@ -604,13 +657,9 @@ void irq_dispose_mapping(unsigned int virq)
604 /* Check if radix tree allocated yet */ 657 /* Check if radix tree allocated yet */
605 if (host->revmap_data.tree.gfp_mask == 0) 658 if (host->revmap_data.tree.gfp_mask == 0)
606 break; 659 break;
607 /* XXX radix tree not safe ! remove lock whem it becomes safe 660 irq_radix_wrlock(&flags);
608 * and use some RCU sync to make sure everything is ok before we
609 * can re-use that map entry
610 */
611 spin_lock_irqsave(&irq_big_lock, flags);
612 radix_tree_delete(&host->revmap_data.tree, hwirq); 661 radix_tree_delete(&host->revmap_data.tree, hwirq);
613 spin_unlock_irqrestore(&irq_big_lock, flags); 662 irq_radix_wrunlock(flags);
614 break; 663 break;
615 } 664 }
616 665
@@ -677,25 +726,24 @@ unsigned int irq_radix_revmap(struct irq_host *host,
677 if (tree->gfp_mask == 0) 726 if (tree->gfp_mask == 0)
678 return irq_find_mapping(host, hwirq); 727 return irq_find_mapping(host, hwirq);
679 728
680 /* XXX Current radix trees are NOT SMP safe !!! Remove that lock
681 * when that is fixed (when Nick's patch gets in
682 */
683 spin_lock_irqsave(&irq_big_lock, flags);
684
685 /* Now try to resolve */ 729 /* Now try to resolve */
730 irq_radix_rdlock(&flags);
686 ptr = radix_tree_lookup(tree, hwirq); 731 ptr = radix_tree_lookup(tree, hwirq);
732 irq_radix_rdunlock(flags);
733
687 /* Found it, return */ 734 /* Found it, return */
688 if (ptr) { 735 if (ptr) {
689 virq = ptr - irq_map; 736 virq = ptr - irq_map;
690 goto bail; 737 return virq;
691 } 738 }
692 739
693 /* If not there, try to insert it */ 740 /* If not there, try to insert it */
694 virq = irq_find_mapping(host, hwirq); 741 virq = irq_find_mapping(host, hwirq);
695 if (virq != NO_IRQ) 742 if (virq != NO_IRQ) {
743 irq_radix_wrlock(&flags);
696 radix_tree_insert(tree, hwirq, &irq_map[virq]); 744 radix_tree_insert(tree, hwirq, &irq_map[virq]);
697 bail: 745 irq_radix_wrunlock(flags);
698 spin_unlock_irqrestore(&irq_big_lock, flags); 746 }
699 return virq; 747 return virq;
700} 748}
701 749
@@ -806,12 +854,12 @@ static int irq_late_init(void)
806 struct irq_host *h; 854 struct irq_host *h;
807 unsigned long flags; 855 unsigned long flags;
808 856
809 spin_lock_irqsave(&irq_big_lock, flags); 857 irq_radix_wrlock(&flags);
810 list_for_each_entry(h, &irq_hosts, link) { 858 list_for_each_entry(h, &irq_hosts, link) {
811 if (h->revmap_type == IRQ_HOST_MAP_TREE) 859 if (h->revmap_type == IRQ_HOST_MAP_TREE)
812 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC); 860 INIT_RADIX_TREE(&h->revmap_data.tree, GFP_ATOMIC);
813 } 861 }
814 spin_unlock_irqrestore(&irq_big_lock, flags); 862 irq_radix_wrunlock(flags);
815 863
816 return 0; 864 return 0;
817} 865}
diff --git a/arch/powerpc/kernel/pci_64.c b/arch/powerpc/kernel/pci_64.c
index 2fce7738e9e2..138134c8c17d 100644
--- a/arch/powerpc/kernel/pci_64.c
+++ b/arch/powerpc/kernel/pci_64.c
@@ -1289,6 +1289,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1289 1289
1290 DBG("Try to map irq for %s...\n", pci_name(pci_dev)); 1290 DBG("Try to map irq for %s...\n", pci_name(pci_dev));
1291 1291
1292#ifdef DEBUG
1293 memset(&oirq, 0xff, sizeof(oirq));
1294#endif
1292 /* Try to get a mapping from the device-tree */ 1295 /* Try to get a mapping from the device-tree */
1293 if (of_irq_map_pci(pci_dev, &oirq)) { 1296 if (of_irq_map_pci(pci_dev, &oirq)) {
1294 u8 line, pin; 1297 u8 line, pin;
@@ -1314,8 +1317,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1314 if (virq != NO_IRQ) 1317 if (virq != NO_IRQ)
1315 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW); 1318 set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
1316 } else { 1319 } else {
1317 DBG(" -> got one, spec %d cells (0x%08x...) on %s\n", 1320 DBG(" -> got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
1318 oirq.size, oirq.specifier[0], oirq.controller->full_name); 1321 oirq.size, oirq.specifier[0], oirq.specifier[1],
1322 oirq.controller->full_name);
1319 1323
1320 virq = irq_create_of_mapping(oirq.controller, oirq.specifier, 1324 virq = irq_create_of_mapping(oirq.controller, oirq.specifier,
1321 oirq.size); 1325 oirq.size);
@@ -1324,6 +1328,9 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
1324 DBG(" -> failed to map !\n"); 1328 DBG(" -> failed to map !\n");
1325 return -1; 1329 return -1;
1326 } 1330 }
1331
1332 DBG(" -> mapped to linux irq %d\n", virq);
1333
1327 pci_dev->irq = virq; 1334 pci_dev->irq = virq;
1328 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq); 1335 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, virq);
1329 1336
diff --git a/arch/powerpc/kernel/ppc_ksyms.c b/arch/powerpc/kernel/ppc_ksyms.c
index f6a05f090b25..39d3bfcabcd2 100644
--- a/arch/powerpc/kernel/ppc_ksyms.c
+++ b/arch/powerpc/kernel/ppc_ksyms.c
@@ -126,10 +126,6 @@ EXPORT_SYMBOL(pci_bus_mem_base_phys);
126EXPORT_SYMBOL(pci_bus_to_hose); 126EXPORT_SYMBOL(pci_bus_to_hose);
127#endif /* CONFIG_PCI */ 127#endif /* CONFIG_PCI */
128 128
129#ifdef CONFIG_NOT_COHERENT_CACHE
130EXPORT_SYMBOL(flush_dcache_all);
131#endif
132
133EXPORT_SYMBOL(start_thread); 129EXPORT_SYMBOL(start_thread);
134EXPORT_SYMBOL(kernel_thread); 130EXPORT_SYMBOL(kernel_thread);
135 131
diff --git a/arch/powerpc/kernel/prom_init.c b/arch/powerpc/kernel/prom_init.c
index 462bced40c12..4394e545f9f7 100644
--- a/arch/powerpc/kernel/prom_init.c
+++ b/arch/powerpc/kernel/prom_init.c
@@ -646,13 +646,13 @@ static unsigned char ibm_architecture_vec[] = {
646 5 - 1, /* 5 option vectors */ 646 5 - 1, /* 5 option vectors */
647 647
648 /* option vector 1: processor architectures supported */ 648 /* option vector 1: processor architectures supported */
649 3 - 1, /* length */ 649 3 - 2, /* length */
650 0, /* don't ignore, don't halt */ 650 0, /* don't ignore, don't halt */
651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 | 651 OV1_PPC_2_00 | OV1_PPC_2_01 | OV1_PPC_2_02 | OV1_PPC_2_03 |
652 OV1_PPC_2_04 | OV1_PPC_2_05, 652 OV1_PPC_2_04 | OV1_PPC_2_05,
653 653
654 /* option vector 2: Open Firmware options supported */ 654 /* option vector 2: Open Firmware options supported */
655 34 - 1, /* length */ 655 34 - 2, /* length */
656 OV2_REAL_MODE, 656 OV2_REAL_MODE,
657 0, 0, 657 0, 0,
658 W(0xffffffff), /* real_base */ 658 W(0xffffffff), /* real_base */
@@ -666,16 +666,16 @@ static unsigned char ibm_architecture_vec[] = {
666 48, /* max log_2(hash table size) */ 666 48, /* max log_2(hash table size) */
667 667
668 /* option vector 3: processor options supported */ 668 /* option vector 3: processor options supported */
669 3 - 1, /* length */ 669 3 - 2, /* length */
670 0, /* don't ignore, don't halt */ 670 0, /* don't ignore, don't halt */
671 OV3_FP | OV3_VMX, 671 OV3_FP | OV3_VMX,
672 672
673 /* option vector 4: IBM PAPR implementation */ 673 /* option vector 4: IBM PAPR implementation */
674 2 - 1, /* length */ 674 2 - 2, /* length */
675 0, /* don't halt */ 675 0, /* don't halt */
676 676
677 /* option vector 5: PAPR/OF options */ 677 /* option vector 5: PAPR/OF options */
678 3 - 1, /* length */ 678 3 - 2, /* length */
679 0, /* don't ignore, don't halt */ 679 0, /* don't ignore, don't halt */
680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES, 680 OV5_LPAR | OV5_SPLPAR | OV5_LARGE_PAGES,
681}; 681};
diff --git a/arch/powerpc/kernel/prom_parse.c b/arch/powerpc/kernel/prom_parse.c
index 11052c212ad5..a10825a5dfe6 100644
--- a/arch/powerpc/kernel/prom_parse.c
+++ b/arch/powerpc/kernel/prom_parse.c
@@ -639,14 +639,17 @@ void of_irq_map_init(unsigned int flags)
639 639
640} 640}
641 641
642int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr, 642int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 ointsize,
643 struct of_irq *out_irq) 643 u32 *addr, struct of_irq *out_irq)
644{ 644{
645 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL; 645 struct device_node *ipar, *tnode, *old = NULL, *newpar = NULL;
646 u32 *tmp, *imap, *imask; 646 u32 *tmp, *imap, *imask;
647 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0; 647 u32 intsize = 1, addrsize, newintsize = 0, newaddrsize = 0;
648 int imaplen, match, i; 648 int imaplen, match, i;
649 649
650 DBG("of_irq_map_raw: par=%s,intspec=[0x%08x 0x%08x...],ointsize=%d\n",
651 parent->full_name, intspec[0], intspec[1], ointsize);
652
650 ipar = of_node_get(parent); 653 ipar = of_node_get(parent);
651 654
652 /* First get the #interrupt-cells property of the current cursor 655 /* First get the #interrupt-cells property of the current cursor
@@ -670,6 +673,9 @@ int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
670 673
671 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize); 674 DBG("of_irq_map_raw: ipar=%s, size=%d\n", ipar->full_name, intsize);
672 675
676 if (ointsize != intsize)
677 return -EINVAL;
678
673 /* Look for this #address-cells. We have to implement the old linux 679 /* Look for this #address-cells. We have to implement the old linux
674 * trick of looking for the parent here as some device-trees rely on it 680 * trick of looking for the parent here as some device-trees rely on it
675 */ 681 */
@@ -875,12 +881,15 @@ int of_irq_map_one(struct device_node *device, int index, struct of_irq *out_irq
875 } 881 }
876 intsize = *tmp; 882 intsize = *tmp;
877 883
884 DBG(" intsize=%d intlen=%d\n", intsize, intlen);
885
878 /* Check index */ 886 /* Check index */
879 if ((index + 1) * intsize > intlen) 887 if ((index + 1) * intsize > intlen)
880 return -EINVAL; 888 return -EINVAL;
881 889
882 /* Get new specifier and map it */ 890 /* Get new specifier and map it */
883 res = of_irq_map_raw(p, intspec + index * intsize, addr, out_irq); 891 res = of_irq_map_raw(p, intspec + index * intsize, intsize,
892 addr, out_irq);
884 of_node_put(p); 893 of_node_put(p);
885 return res; 894 return res;
886} 895}
@@ -965,7 +974,7 @@ int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq)
965 laddr[0] = (pdev->bus->number << 16) 974 laddr[0] = (pdev->bus->number << 16)
966 | (pdev->devfn << 8); 975 | (pdev->devfn << 8);
967 laddr[1] = laddr[2] = 0; 976 laddr[1] = laddr[2] = 0;
968 return of_irq_map_raw(ppnode, &lspec, laddr, out_irq); 977 return of_irq_map_raw(ppnode, &lspec, 1, laddr, out_irq);
969} 978}
970EXPORT_SYMBOL_GPL(of_irq_map_pci); 979EXPORT_SYMBOL_GPL(of_irq_map_pci);
971#endif /* CONFIG_PCI */ 980#endif /* CONFIG_PCI */
diff --git a/arch/powerpc/kernel/smp-tbsync.c b/arch/powerpc/kernel/smp-tbsync.c
index f19e2e0e61e7..de59c6c31a5b 100644
--- a/arch/powerpc/kernel/smp-tbsync.c
+++ b/arch/powerpc/kernel/smp-tbsync.c
@@ -45,8 +45,9 @@ void __devinit smp_generic_take_timebase(void)
45{ 45{
46 int cmd; 46 int cmd;
47 u64 tb; 47 u64 tb;
48 unsigned long flags;
48 49
49 local_irq_disable(); 50 local_irq_save(flags);
50 while (!running) 51 while (!running)
51 barrier(); 52 barrier();
52 rmb(); 53 rmb();
@@ -70,7 +71,7 @@ void __devinit smp_generic_take_timebase(void)
70 set_tb(tb >> 32, tb & 0xfffffffful); 71 set_tb(tb >> 32, tb & 0xfffffffful);
71 enter_contest(tbsync->mark, -1); 72 enter_contest(tbsync->mark, -1);
72 } 73 }
73 local_irq_enable(); 74 local_irq_restore(flags);
74} 75}
75 76
76static int __devinit start_contest(int cmd, long offset, int num) 77static int __devinit start_contest(int cmd, long offset, int num)
diff --git a/arch/powerpc/kernel/time.c b/arch/powerpc/kernel/time.c
index 18e59e43d2b3..a124499e65d9 100644
--- a/arch/powerpc/kernel/time.c
+++ b/arch/powerpc/kernel/time.c
@@ -125,15 +125,8 @@ static long timezone_offset;
125unsigned long ppc_proc_freq; 125unsigned long ppc_proc_freq;
126unsigned long ppc_tb_freq; 126unsigned long ppc_tb_freq;
127 127
128u64 tb_last_jiffy __cacheline_aligned_in_smp; 128static u64 tb_last_jiffy __cacheline_aligned_in_smp;
129unsigned long tb_last_stamp; 129static DEFINE_PER_CPU(u64, last_jiffy);
130
131/*
132 * Note that on ppc32 this only stores the bottom 32 bits of
133 * the timebase value, but that's enough to tell when a jiffy
134 * has passed.
135 */
136DEFINE_PER_CPU(unsigned long, last_jiffy);
137 130
138#ifdef CONFIG_VIRT_CPU_ACCOUNTING 131#ifdef CONFIG_VIRT_CPU_ACCOUNTING
139/* 132/*
@@ -458,7 +451,7 @@ void do_gettimeofday(struct timeval *tv)
458 do { 451 do {
459 seq = read_seqbegin_irqsave(&xtime_lock, flags); 452 seq = read_seqbegin_irqsave(&xtime_lock, flags);
460 sec = xtime.tv_sec; 453 sec = xtime.tv_sec;
461 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_stamp); 454 nsec = xtime.tv_nsec + tb_ticks_since(tb_last_jiffy);
462 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags)); 455 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
463 usec = nsec / 1000; 456 usec = nsec / 1000;
464 while (usec >= 1000000) { 457 while (usec >= 1000000) {
@@ -700,7 +693,6 @@ void timer_interrupt(struct pt_regs * regs)
700 tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy; 693 tb_next_jiffy = tb_last_jiffy + tb_ticks_per_jiffy;
701 if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) { 694 if (per_cpu(last_jiffy, cpu) >= tb_next_jiffy) {
702 tb_last_jiffy = tb_next_jiffy; 695 tb_last_jiffy = tb_next_jiffy;
703 tb_last_stamp = per_cpu(last_jiffy, cpu);
704 do_timer(regs); 696 do_timer(regs);
705 timer_recalc_offset(tb_last_jiffy); 697 timer_recalc_offset(tb_last_jiffy);
706 timer_check_rtc(); 698 timer_check_rtc();
@@ -749,7 +741,7 @@ void __init smp_space_timers(unsigned int max_cpus)
749 int i; 741 int i;
750 unsigned long half = tb_ticks_per_jiffy / 2; 742 unsigned long half = tb_ticks_per_jiffy / 2;
751 unsigned long offset = tb_ticks_per_jiffy / max_cpus; 743 unsigned long offset = tb_ticks_per_jiffy / max_cpus;
752 unsigned long previous_tb = per_cpu(last_jiffy, boot_cpuid); 744 u64 previous_tb = per_cpu(last_jiffy, boot_cpuid);
753 745
754 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */ 746 /* make sure tb > per_cpu(last_jiffy, cpu) for all cpus always */
755 previous_tb -= tb_ticks_per_jiffy; 747 previous_tb -= tb_ticks_per_jiffy;
@@ -830,7 +822,7 @@ int do_settimeofday(struct timespec *tv)
830 * and therefore the (jiffies - wall_jiffies) computation 822 * and therefore the (jiffies - wall_jiffies) computation
831 * has been removed. 823 * has been removed.
832 */ 824 */
833 tb_delta = tb_ticks_since(tb_last_stamp); 825 tb_delta = tb_ticks_since(tb_last_jiffy);
834 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */ 826 tb_delta = mulhdu(tb_delta, do_gtod.varp->tb_to_xs); /* in xsec */
835 new_nsec -= SCALE_XSEC(tb_delta, 1000000000); 827 new_nsec -= SCALE_XSEC(tb_delta, 1000000000);
836 828
@@ -950,8 +942,7 @@ void __init time_init(void)
950 if (__USE_RTC()) { 942 if (__USE_RTC()) {
951 /* 601 processor: dec counts down by 128 every 128ns */ 943 /* 601 processor: dec counts down by 128 every 128ns */
952 ppc_tb_freq = 1000000000; 944 ppc_tb_freq = 1000000000;
953 tb_last_stamp = get_rtcl(); 945 tb_last_jiffy = get_rtcl();
954 tb_last_jiffy = tb_last_stamp;
955 } else { 946 } else {
956 /* Normal PowerPC with timebase register */ 947 /* Normal PowerPC with timebase register */
957 ppc_md.calibrate_decr(); 948 ppc_md.calibrate_decr();
@@ -959,7 +950,7 @@ void __init time_init(void)
959 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000); 950 ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
960 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n", 951 printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n",
961 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000); 952 ppc_proc_freq / 1000000, ppc_proc_freq % 1000000);
962 tb_last_stamp = tb_last_jiffy = get_tb(); 953 tb_last_jiffy = get_tb();
963 } 954 }
964 955
965 tb_ticks_per_jiffy = ppc_tb_freq / HZ; 956 tb_ticks_per_jiffy = ppc_tb_freq / HZ;
@@ -1036,7 +1027,7 @@ void __init time_init(void)
1036 do_gtod.varp = &do_gtod.vars[0]; 1027 do_gtod.varp = &do_gtod.vars[0];
1037 do_gtod.var_idx = 0; 1028 do_gtod.var_idx = 0;
1038 do_gtod.varp->tb_orig_stamp = tb_last_jiffy; 1029 do_gtod.varp->tb_orig_stamp = tb_last_jiffy;
1039 __get_cpu_var(last_jiffy) = tb_last_stamp; 1030 __get_cpu_var(last_jiffy) = tb_last_jiffy;
1040 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC; 1031 do_gtod.varp->stamp_xsec = (u64) xtime.tv_sec * XSEC_PER_SEC;
1041 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec; 1032 do_gtod.tb_ticks_per_sec = tb_ticks_per_sec;
1042 do_gtod.varp->tb_to_xs = tb_to_xs; 1033 do_gtod.varp->tb_to_xs = tb_to_xs;
diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S
index fd66acfd3e3e..7173ba98f427 100644
--- a/arch/powerpc/lib/memcpy_64.S
+++ b/arch/powerpc/lib/memcpy_64.S
@@ -11,6 +11,7 @@
11 11
12 .align 7 12 .align 7
13_GLOBAL(memcpy) 13_GLOBAL(memcpy)
14 std r3,48(r1) /* save destination pointer for return value */
14 mtcrf 0x01,r5 15 mtcrf 0x01,r5
15 cmpldi cr1,r5,16 16 cmpldi cr1,r5,16
16 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry 17 neg r6,r3 # LS 3 bits = # bytes to 8-byte dest bdry
@@ -38,7 +39,7 @@ _GLOBAL(memcpy)
38 stdu r9,16(r3) 39 stdu r9,16(r3)
39 bdnz 1b 40 bdnz 1b
403: std r8,8(r3) 413: std r8,8(r3)
41 beqlr 42 beq 3f
42 addi r3,r3,16 43 addi r3,r3,16
43 ld r9,8(r4) 44 ld r9,8(r4)
44.Ldo_tail: 45.Ldo_tail:
@@ -53,7 +54,8 @@ _GLOBAL(memcpy)
532: bf cr7*4+3,3f 542: bf cr7*4+3,3f
54 rotldi r9,r9,8 55 rotldi r9,r9,8
55 stb r9,0(r3) 56 stb r9,0(r3)
563: blr 573: ld r3,48(r1) /* return dest pointer */
58 blr
57 59
58.Lsrc_unaligned: 60.Lsrc_unaligned:
59 srdi r6,r5,3 61 srdi r6,r5,3
@@ -115,7 +117,7 @@ _GLOBAL(memcpy)
1155: srd r12,r9,r11 1175: srd r12,r9,r11
116 or r12,r8,r12 118 or r12,r8,r12
117 std r12,24(r3) 119 std r12,24(r3)
118 beqlr 120 beq 4f
119 cmpwi cr1,r5,8 121 cmpwi cr1,r5,8
120 addi r3,r3,32 122 addi r3,r3,32
121 sld r9,r9,r10 123 sld r9,r9,r10
@@ -167,4 +169,5 @@ _GLOBAL(memcpy)
1673: bf cr7*4+3,4f 1693: bf cr7*4+3,4f
168 lbz r0,0(r4) 170 lbz r0,0(r4)
169 stb r0,0(r3) 171 stb r0,0(r3)
1704: blr 1724: ld r3,48(r1) /* return dest pointer */
173 blr
diff --git a/arch/powerpc/mm/44x_mmu.c b/arch/powerpc/mm/44x_mmu.c
index 376829ed2211..0a0a0487b334 100644
--- a/arch/powerpc/mm/44x_mmu.c
+++ b/arch/powerpc/mm/44x_mmu.c
@@ -103,7 +103,7 @@ unsigned long __init mmu_mapin_ram(void)
103 103
104 /* Determine number of entries necessary to cover lowmem */ 104 /* Determine number of entries necessary to cover lowmem */
105 pinned_tlbs = (unsigned int) 105 pinned_tlbs = (unsigned int)
106 (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT); 106 (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
107 107
108 /* Write upper watermark to save location */ 108 /* Write upper watermark to save location */
109 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs; 109 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
@@ -111,7 +111,7 @@ unsigned long __init mmu_mapin_ram(void)
111 /* If necessary, set additional pinned TLBs */ 111 /* If necessary, set additional pinned TLBs */
112 if (pinned_tlbs > 1) 112 if (pinned_tlbs > 1)
113 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { 113 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
114 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE; 114 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
115 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); 115 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
116 } 116 }
117 117
diff --git a/arch/powerpc/platforms/83xx/mpc834x_itx.c b/arch/powerpc/platforms/83xx/mpc834x_itx.c
index b46305645d38..cf3967a66fb5 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_itx.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_itx.c
@@ -46,26 +46,6 @@ unsigned long isa_io_base = 0;
46unsigned long isa_mem_base = 0; 46unsigned long isa_mem_base = 0;
47#endif 47#endif
48 48
49#ifdef CONFIG_PCI
50static int
51mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
52{
53 static char pci_irq_table[][4] =
54 /*
55 * PCI IDSEL/INTPIN->INTLINE
56 * A B C D
57 */
58 {
59 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x0e */
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x0f */
61 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x10 */
62 };
63
64 const long min_idsel = 0x0e, max_idsel = 0x10, irqs_per_slot = 4;
65 return PCI_IRQ_TABLE_LOOKUP;
66}
67#endif /* CONFIG_PCI */
68
69/* ************************************************************************ 49/* ************************************************************************
70 * 50 *
71 * Setup the architecture 51 * Setup the architecture
@@ -92,8 +72,6 @@ static void __init mpc834x_itx_setup_arch(void)
92 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 72 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
93 add_bridge(np); 73 add_bridge(np);
94 74
95 ppc_md.pci_swizzle = common_swizzle;
96 ppc_md.pci_map_irq = mpc83xx_map_irq;
97 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 75 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
98#endif 76#endif
99 77
@@ -106,25 +84,13 @@ static void __init mpc834x_itx_setup_arch(void)
106 84
107void __init mpc834x_itx_init_IRQ(void) 85void __init mpc834x_itx_init_IRQ(void)
108{ 86{
109 u8 senses[8] = { 87 struct device_node *np;
110 0, /* EXT 0 */ 88
111 IRQ_SENSE_LEVEL, /* EXT 1 */ 89 np = of_find_node_by_type(NULL, "ipic");
112 IRQ_SENSE_LEVEL, /* EXT 2 */ 90 if (!np)
113 0, /* EXT 3 */ 91 return;
114#ifdef CONFIG_PCI
115 IRQ_SENSE_LEVEL, /* EXT 4 */
116 IRQ_SENSE_LEVEL, /* EXT 5 */
117 IRQ_SENSE_LEVEL, /* EXT 6 */
118 IRQ_SENSE_LEVEL, /* EXT 7 */
119#else
120 0, /* EXT 4 */
121 0, /* EXT 5 */
122 0, /* EXT 6 */
123 0, /* EXT 7 */
124#endif
125 };
126 92
127 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 93 ipic_init(np, 0);
128 94
129 /* Initialize the default interrupt mapping priorities, 95 /* Initialize the default interrupt mapping priorities,
130 * in case the boot rom changed something on us. 96 * in case the boot rom changed something on us.
@@ -153,4 +119,7 @@ define_machine(mpc834x_itx) {
153 .time_init = mpc83xx_time_init, 119 .time_init = mpc83xx_time_init,
154 .calibrate_decr = generic_calibrate_decr, 120 .calibrate_decr = generic_calibrate_decr,
155 .progress = udbg_progress, 121 .progress = udbg_progress,
122#ifdef CONFIG_PCI
123 .pcibios_fixup = mpc83xx_pcibios_fixup,
124#endif
156}; 125};
diff --git a/arch/powerpc/platforms/83xx/mpc834x_sys.c b/arch/powerpc/platforms/83xx/mpc834x_sys.c
index 3e1c16eb4a63..32df239d1c48 100644
--- a/arch/powerpc/platforms/83xx/mpc834x_sys.c
+++ b/arch/powerpc/platforms/83xx/mpc834x_sys.c
@@ -43,33 +43,6 @@ unsigned long isa_io_base = 0;
43unsigned long isa_mem_base = 0; 43unsigned long isa_mem_base = 0;
44#endif 44#endif
45 45
46#ifdef CONFIG_PCI
47static int
48mpc83xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
49{
50 static char pci_irq_table[][4] =
51 /*
52 * PCI IDSEL/INTPIN->INTLINE
53 * A B C D
54 */
55 {
56 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x11 */
57 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x12 */
58 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x13 */
59 {0, 0, 0, 0},
60 {PIRQA, PIRQB, PIRQC, PIRQD}, /* idsel 0x15 */
61 {PIRQD, PIRQA, PIRQB, PIRQC}, /* idsel 0x16 */
62 {PIRQC, PIRQD, PIRQA, PIRQB}, /* idsel 0x17 */
63 {PIRQB, PIRQC, PIRQD, PIRQA}, /* idsel 0x18 */
64 {0, 0, 0, 0}, /* idsel 0x19 */
65 {0, 0, 0, 0}, /* idsel 0x20 */
66 };
67
68 const long min_idsel = 0x11, max_idsel = 0x20, irqs_per_slot = 4;
69 return PCI_IRQ_TABLE_LOOKUP;
70}
71#endif /* CONFIG_PCI */
72
73/* ************************************************************************ 46/* ************************************************************************
74 * 47 *
75 * Setup the architecture 48 * Setup the architecture
@@ -96,8 +69,6 @@ static void __init mpc834x_sys_setup_arch(void)
96 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) 69 for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
97 add_bridge(np); 70 add_bridge(np);
98 71
99 ppc_md.pci_swizzle = common_swizzle;
100 ppc_md.pci_map_irq = mpc83xx_map_irq;
101 ppc_md.pci_exclude_device = mpc83xx_exclude_device; 72 ppc_md.pci_exclude_device = mpc83xx_exclude_device;
102#endif 73#endif
103 74
@@ -110,25 +81,13 @@ static void __init mpc834x_sys_setup_arch(void)
110 81
111void __init mpc834x_sys_init_IRQ(void) 82void __init mpc834x_sys_init_IRQ(void)
112{ 83{
113 u8 senses[8] = { 84 struct device_node *np;
114 0, /* EXT 0 */ 85
115 IRQ_SENSE_LEVEL, /* EXT 1 */ 86 np = of_find_node_by_type(NULL, "ipic");
116 IRQ_SENSE_LEVEL, /* EXT 2 */ 87 if (!np)
117 0, /* EXT 3 */ 88 return;
118#ifdef CONFIG_PCI
119 IRQ_SENSE_LEVEL, /* EXT 4 */
120 IRQ_SENSE_LEVEL, /* EXT 5 */
121 IRQ_SENSE_LEVEL, /* EXT 6 */
122 IRQ_SENSE_LEVEL, /* EXT 7 */
123#else
124 0, /* EXT 4 */
125 0, /* EXT 5 */
126 0, /* EXT 6 */
127 0, /* EXT 7 */
128#endif
129 };
130 89
131 ipic_init(get_immrbase() + 0x00700, 0, 0, senses, 8); 90 ipic_init(np, 0);
132 91
133 /* Initialize the default interrupt mapping priorities, 92 /* Initialize the default interrupt mapping priorities,
134 * in case the boot rom changed something on us. 93 * in case the boot rom changed something on us.
@@ -178,4 +137,7 @@ define_machine(mpc834x_sys) {
178 .time_init = mpc83xx_time_init, 137 .time_init = mpc83xx_time_init,
179 .calibrate_decr = generic_calibrate_decr, 138 .calibrate_decr = generic_calibrate_decr,
180 .progress = udbg_progress, 139 .progress = udbg_progress,
140#ifdef CONFIG_PCI
141 .pcibios_fixup = mpc83xx_pcibios_fixup,
142#endif
181}; 143};
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 01cae106912b..2c82bca9bfbb 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -11,6 +11,7 @@
11 11
12extern int add_bridge(struct device_node *dev); 12extern int add_bridge(struct device_node *dev);
13extern int mpc83xx_exclude_device(u_char bus, u_char devfn); 13extern int mpc83xx_exclude_device(u_char bus, u_char devfn);
14extern void mpc83xx_pcibios_fixup(void);
14extern void mpc83xx_restart(char *cmd); 15extern void mpc83xx_restart(char *cmd);
15extern long mpc83xx_time_init(void); 16extern long mpc83xx_time_init(void);
16 17
diff --git a/arch/powerpc/platforms/83xx/pci.c b/arch/powerpc/platforms/83xx/pci.c
index 3b5e563c279f..5d84a9ccd103 100644
--- a/arch/powerpc/platforms/83xx/pci.c
+++ b/arch/powerpc/platforms/83xx/pci.c
@@ -45,6 +45,15 @@ int mpc83xx_exclude_device(u_char bus, u_char devfn)
45 return PCIBIOS_SUCCESSFUL; 45 return PCIBIOS_SUCCESSFUL;
46} 46}
47 47
48void __init mpc83xx_pcibios_fixup(void)
49{
50 struct pci_dev *dev = NULL;
51
52 /* map all the PCI irqs */
53 for_each_pci_dev(dev)
54 pci_read_irq_line(dev);
55}
56
48int __init add_bridge(struct device_node *dev) 57int __init add_bridge(struct device_node *dev)
49{ 58{
50 int len; 59 int len;
diff --git a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
index 146da3001c67..0b1b52168bb7 100644
--- a/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
+++ b/arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
@@ -52,6 +52,7 @@ unsigned long pci_dram_offset = 0;
52#endif 52#endif
53 53
54 54
55#ifdef CONFIG_PCI
55static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc, 56static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
56 struct pt_regs *regs) 57 struct pt_regs *regs)
57{ 58{
@@ -60,40 +61,43 @@ static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc,
60 generic_handle_irq(cascade_irq, regs); 61 generic_handle_irq(cascade_irq, regs);
61 desc->chip->eoi(irq); 62 desc->chip->eoi(irq);
62} 63}
64#endif /* CONFIG_PCI */
63 65
64void __init 66void __init
65mpc86xx_hpcn_init_irq(void) 67mpc86xx_hpcn_init_irq(void)
66{ 68{
67 struct mpic *mpic1; 69 struct mpic *mpic1;
68 struct device_node *np, *cascade_node = NULL; 70 struct device_node *np;
71 struct resource res;
72#ifdef CONFIG_PCI
73 struct device_node *cascade_node = NULL;
69 int cascade_irq; 74 int cascade_irq;
70 phys_addr_t openpic_paddr; 75#endif
71 76
77 /* Determine PIC address. */
72 np = of_find_node_by_type(NULL, "open-pic"); 78 np = of_find_node_by_type(NULL, "open-pic");
73 if (np == NULL) 79 if (np == NULL)
74 return; 80 return;
75 81 of_address_to_resource(np, 0, &res);
76 /* Determine the Physical Address of the OpenPIC regs */
77 openpic_paddr = get_immrbase() + MPC86xx_OPENPIC_OFFSET;
78 82
79 /* Alloc mpic structure and per isu has 16 INT entries. */ 83 /* Alloc mpic structure and per isu has 16 INT entries. */
80 mpic1 = mpic_alloc(np, openpic_paddr, 84 mpic1 = mpic_alloc(np, res.start,
81 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, 85 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
82 16, NR_IRQS - 4, 86 16, NR_IRQS - 4,
83 " MPIC "); 87 " MPIC ");
84 BUG_ON(mpic1 == NULL); 88 BUG_ON(mpic1 == NULL);
85 89
86 mpic_assign_isu(mpic1, 0, openpic_paddr + 0x10000); 90 mpic_assign_isu(mpic1, 0, res.start + 0x10000);
87 91
88 /* 48 Internal Interrupts */ 92 /* 48 Internal Interrupts */
89 mpic_assign_isu(mpic1, 1, openpic_paddr + 0x10200); 93 mpic_assign_isu(mpic1, 1, res.start + 0x10200);
90 mpic_assign_isu(mpic1, 2, openpic_paddr + 0x10400); 94 mpic_assign_isu(mpic1, 2, res.start + 0x10400);
91 mpic_assign_isu(mpic1, 3, openpic_paddr + 0x10600); 95 mpic_assign_isu(mpic1, 3, res.start + 0x10600);
92 96
93 /* 16 External interrupts 97 /* 16 External interrupts
94 * Moving them from [0 - 15] to [64 - 79] 98 * Moving them from [0 - 15] to [64 - 79]
95 */ 99 */
96 mpic_assign_isu(mpic1, 4, openpic_paddr + 0x10000); 100 mpic_assign_isu(mpic1, 4, res.start + 0x10000);
97 101
98 mpic_init(mpic1); 102 mpic_init(mpic1);
99 103
diff --git a/arch/powerpc/platforms/86xx/pci.c b/arch/powerpc/platforms/86xx/pci.c
index bc5139043112..a8c8f0a44055 100644
--- a/arch/powerpc/platforms/86xx/pci.c
+++ b/arch/powerpc/platforms/86xx/pci.c
@@ -188,7 +188,8 @@ int __init add_bridge(struct device_node *dev)
188 188
189 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " 189 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
190 "Firmware bus number: %d->%d\n", 190 "Firmware bus number: %d->%d\n",
191 rsrc.start, hose->first_busno, hose->last_busno); 191 (unsigned long) rsrc.start,
192 hose->first_busno, hose->last_busno);
192 193
193 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 194 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
194 hose, hose->cfg_addr, hose->cfg_data); 195 hose, hose->cfg_addr, hose->cfg_data);
diff --git a/arch/powerpc/platforms/embedded6xx/Kconfig b/arch/powerpc/platforms/embedded6xx/Kconfig
index ba07a9a7c039..234a861870a8 100644
--- a/arch/powerpc/platforms/embedded6xx/Kconfig
+++ b/arch/powerpc/platforms/embedded6xx/Kconfig
@@ -80,6 +80,7 @@ config MPC7448HPC2
80 select DEFAULT_UIMAGE 80 select DEFAULT_UIMAGE
81 select PPC_UDBG_16550 81 select PPC_UDBG_16550
82 select MPIC 82 select MPIC
83 select MPIC_WEIRD
83 help 84 help
84 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga) 85 Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
85 platform 86 platform
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index ed00ed2455dd..5d393eb94935 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -215,7 +215,7 @@ static void __init mpc7448_hpc2_init_IRQ(void)
215 215
216 mpic = mpic_alloc(tsi_pic, mpic_paddr, 216 mpic = mpic_alloc(tsi_pic, mpic_paddr,
217 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET | 217 MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
218 MPIC_SPV_EOI | MPIC_MOD_ID(MPIC_ID_TSI108), 218 MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
219 0, /* num_sources used */ 219 0, /* num_sources used */
220 0, /* num_sources used */ 220 0, /* num_sources used */
221 "Tsi108_PIC"); 221 "Tsi108_PIC");
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 060789e31c67..39f7ddb554ea 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -87,8 +87,8 @@ static void __pmac_retrigger(unsigned int irq_nr)
87static void pmac_mask_and_ack_irq(unsigned int virq) 87static void pmac_mask_and_ack_irq(unsigned int virq)
88{ 88{
89 unsigned int src = irq_map[virq].hwirq; 89 unsigned int src = irq_map[virq].hwirq;
90 unsigned long bit = 1UL << (virq & 0x1f); 90 unsigned long bit = 1UL << (src & 0x1f);
91 int i = virq >> 5; 91 int i = src >> 5;
92 unsigned long flags; 92 unsigned long flags;
93 93
94 spin_lock_irqsave(&pmac_pic_lock, flags); 94 spin_lock_irqsave(&pmac_pic_lock, flags);
@@ -175,7 +175,7 @@ static void pmac_mask_irq(unsigned int virq)
175 175
176 spin_lock_irqsave(&pmac_pic_lock, flags); 176 spin_lock_irqsave(&pmac_pic_lock, flags);
177 __clear_bit(src, ppc_cached_irq_mask); 177 __clear_bit(src, ppc_cached_irq_mask);
178 __pmac_set_irq_mask(src, 0); 178 __pmac_set_irq_mask(src, 1);
179 spin_unlock_irqrestore(&pmac_pic_lock, flags); 179 spin_unlock_irqrestore(&pmac_pic_lock, flags);
180} 180}
181 181
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index cebfae242602..e5e999ea891a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -9,11 +9,11 @@ obj-$(CONFIG_BOOKE) += dcr.o
9obj-$(CONFIG_40x) += dcr.o 9obj-$(CONFIG_40x) += dcr.o
10obj-$(CONFIG_U3_DART) += dart_iommu.o 10obj-$(CONFIG_U3_DART) += dart_iommu.o
11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o 11obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
12obj-$(CONFIG_PPC_83xx) += ipic.o
13obj-$(CONFIG_FSL_SOC) += fsl_soc.o 12obj-$(CONFIG_FSL_SOC) += fsl_soc.o
14obj-$(CONFIG_PPC_TODC) += todc.o 13obj-$(CONFIG_PPC_TODC) += todc.o
15obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o 14obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
16 15
17ifeq ($(CONFIG_PPC_MERGE),y) 16ifeq ($(CONFIG_PPC_MERGE),y)
18obj-$(CONFIG_PPC_I8259) += i8259.o 17obj-$(CONFIG_PPC_I8259) += i8259.o
19 endif 18obj-$(CONFIG_PPC_83xx) += ipic.o
19endif
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 46801f5ec03f..70e707785d49 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -19,15 +19,18 @@
19#include <linux/sched.h> 19#include <linux/sched.h>
20#include <linux/signal.h> 20#include <linux/signal.h>
21#include <linux/sysdev.h> 21#include <linux/sysdev.h>
22#include <linux/device.h>
23#include <linux/bootmem.h>
24#include <linux/spinlock.h>
22#include <asm/irq.h> 25#include <asm/irq.h>
23#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/prom.h>
24#include <asm/ipic.h> 28#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26 29
27#include "ipic.h" 30#include "ipic.h"
28 31
29static struct ipic p_ipic;
30static struct ipic * primary_ipic; 32static struct ipic * primary_ipic;
33static DEFINE_SPINLOCK(ipic_lock);
31 34
32static struct ipic_info ipic_info[] = { 35static struct ipic_info ipic_info[] = {
33 [9] = { 36 [9] = {
@@ -373,74 +376,220 @@ static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32
373 out_be32(base + (reg >> 2), value); 376 out_be32(base + (reg >> 2), value);
374} 377}
375 378
376static inline struct ipic * ipic_from_irq(unsigned int irq) 379static inline struct ipic * ipic_from_irq(unsigned int virq)
377{ 380{
378 return primary_ipic; 381 return primary_ipic;
379} 382}
380 383
381static void ipic_enable_irq(unsigned int irq) 384#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
385
386static void ipic_unmask_irq(unsigned int virq)
382{ 387{
383 struct ipic *ipic = ipic_from_irq(irq); 388 struct ipic *ipic = ipic_from_irq(virq);
384 unsigned int src = irq - ipic->irq_offset; 389 unsigned int src = ipic_irq_to_hw(virq);
390 unsigned long flags;
385 u32 temp; 391 u32 temp;
386 392
393 spin_lock_irqsave(&ipic_lock, flags);
394
387 temp = ipic_read(ipic->regs, ipic_info[src].mask); 395 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit)); 396 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp); 397 ipic_write(ipic->regs, ipic_info[src].mask, temp);
398
399 spin_unlock_irqrestore(&ipic_lock, flags);
390} 400}
391 401
392static void ipic_disable_irq(unsigned int irq) 402static void ipic_mask_irq(unsigned int virq)
393{ 403{
394 struct ipic *ipic = ipic_from_irq(irq); 404 struct ipic *ipic = ipic_from_irq(virq);
395 unsigned int src = irq - ipic->irq_offset; 405 unsigned int src = ipic_irq_to_hw(virq);
406 unsigned long flags;
396 u32 temp; 407 u32 temp;
397 408
409 spin_lock_irqsave(&ipic_lock, flags);
410
398 temp = ipic_read(ipic->regs, ipic_info[src].mask); 411 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit)); 412 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp); 413 ipic_write(ipic->regs, ipic_info[src].mask, temp);
414
415 spin_unlock_irqrestore(&ipic_lock, flags);
401} 416}
402 417
403static void ipic_disable_irq_and_ack(unsigned int irq) 418static void ipic_ack_irq(unsigned int virq)
404{ 419{
405 struct ipic *ipic = ipic_from_irq(irq); 420 struct ipic *ipic = ipic_from_irq(virq);
406 unsigned int src = irq - ipic->irq_offset; 421 unsigned int src = ipic_irq_to_hw(virq);
422 unsigned long flags;
407 u32 temp; 423 u32 temp;
408 424
409 ipic_disable_irq(irq); 425 spin_lock_irqsave(&ipic_lock, flags);
410 426
411 temp = ipic_read(ipic->regs, ipic_info[src].pend); 427 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit)); 428 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp); 429 ipic_write(ipic->regs, ipic_info[src].pend, temp);
430
431 spin_unlock_irqrestore(&ipic_lock, flags);
414} 432}
415 433
416static void ipic_end_irq(unsigned int irq) 434static void ipic_mask_irq_and_ack(unsigned int virq)
417{ 435{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 436 struct ipic *ipic = ipic_from_irq(virq);
419 ipic_enable_irq(irq); 437 unsigned int src = ipic_irq_to_hw(virq);
438 unsigned long flags;
439 u32 temp;
440
441 spin_lock_irqsave(&ipic_lock, flags);
442
443 temp = ipic_read(ipic->regs, ipic_info[src].mask);
444 temp &= ~(1 << (31 - ipic_info[src].bit));
445 ipic_write(ipic->regs, ipic_info[src].mask, temp);
446
447 temp = ipic_read(ipic->regs, ipic_info[src].pend);
448 temp |= (1 << (31 - ipic_info[src].bit));
449 ipic_write(ipic->regs, ipic_info[src].pend, temp);
450
451 spin_unlock_irqrestore(&ipic_lock, flags);
420} 452}
421 453
422struct hw_interrupt_type ipic = { 454static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
423 .typename = " IPIC ", 455{
424 .enable = ipic_enable_irq, 456 struct ipic *ipic = ipic_from_irq(virq);
425 .disable = ipic_disable_irq, 457 unsigned int src = ipic_irq_to_hw(virq);
426 .ack = ipic_disable_irq_and_ack, 458 struct irq_desc *desc = get_irq_desc(virq);
427 .end = ipic_end_irq, 459 unsigned int vold, vnew, edibit;
460
461 if (flow_type == IRQ_TYPE_NONE)
462 flow_type = IRQ_TYPE_LEVEL_LOW;
463
464 /* ipic supports only low assertion and high-to-low change senses
465 */
466 if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
467 printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
468 flow_type);
469 return -EINVAL;
470 }
471
472 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
473 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
474 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
475 desc->status |= IRQ_LEVEL;
476 set_irq_handler(virq, handle_level_irq);
477 } else {
478 set_irq_handler(virq, handle_edge_irq);
479 }
480
481 /* only EXT IRQ senses are programmable on ipic
482 * internal IRQ senses are LEVEL_LOW
483 */
484 if (src == IPIC_IRQ_EXT0)
485 edibit = 15;
486 else
487 if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
488 edibit = (14 - (src - IPIC_IRQ_EXT1));
489 else
490 return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
491
492 vold = ipic_read(ipic->regs, IPIC_SECNR);
493 if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
494 vnew = vold | (1 << edibit);
495 } else {
496 vnew = vold & ~(1 << edibit);
497 }
498 if (vold != vnew)
499 ipic_write(ipic->regs, IPIC_SECNR, vnew);
500 return 0;
501}
502
503static struct irq_chip ipic_irq_chip = {
504 .typename = " IPIC ",
505 .unmask = ipic_unmask_irq,
506 .mask = ipic_mask_irq,
507 .mask_ack = ipic_mask_irq_and_ack,
508 .ack = ipic_ack_irq,
509 .set_type = ipic_set_irq_type,
510};
511
512static int ipic_host_match(struct irq_host *h, struct device_node *node)
513{
514 struct ipic *ipic = h->host_data;
515
516 /* Exact match, unless ipic node is NULL */
517 return ipic->of_node == NULL || ipic->of_node == node;
518}
519
520static int ipic_host_map(struct irq_host *h, unsigned int virq,
521 irq_hw_number_t hw)
522{
523 struct ipic *ipic = h->host_data;
524 struct irq_chip *chip;
525
526 /* Default chip */
527 chip = &ipic->hc_irq;
528
529 set_irq_chip_data(virq, ipic);
530 set_irq_chip_and_handler(virq, chip, handle_level_irq);
531
532 /* Set default irq type */
533 set_irq_type(virq, IRQ_TYPE_NONE);
534
535 return 0;
536}
537
538static int ipic_host_xlate(struct irq_host *h, struct device_node *ct,
539 u32 *intspec, unsigned int intsize,
540 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
541
542{
543 /* interrupt sense values coming from the device tree equal either
544 * LEVEL_LOW (low assertion) or EDGE_FALLING (high-to-low change)
545 */
546 *out_hwirq = intspec[0];
547 if (intsize > 1)
548 *out_flags = intspec[1];
549 else
550 *out_flags = IRQ_TYPE_NONE;
551 return 0;
552}
553
554static struct irq_host_ops ipic_host_ops = {
555 .match = ipic_host_match,
556 .map = ipic_host_map,
557 .xlate = ipic_host_xlate,
428}; 558};
429 559
430void __init ipic_init(phys_addr_t phys_addr, 560void __init ipic_init(struct device_node *node,
431 unsigned int flags, 561 unsigned int flags)
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{ 562{
436 u32 i, temp = 0; 563 struct ipic *ipic;
564 struct resource res;
565 u32 temp = 0, ret;
566
567 ipic = alloc_bootmem(sizeof(struct ipic));
568 if (ipic == NULL)
569 return;
570
571 memset(ipic, 0, sizeof(struct ipic));
572 ipic->of_node = node ? of_node_get(node) : NULL;
573
574 ipic->irqhost = irq_alloc_host(IRQ_HOST_MAP_LINEAR,
575 NR_IPIC_INTS,
576 &ipic_host_ops, 0);
577 if (ipic->irqhost == NULL) {
578 of_node_put(node);
579 return;
580 }
581
582 ret = of_address_to_resource(node, 0, &res);
583 if (ret)
584 return;
437 585
438 primary_ipic = &p_ipic; 586 ipic->regs = ioremap(res.start, res.end - res.start + 1);
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440 587
441 primary_ipic->irq_offset = irq_offset; 588 ipic->irqhost->host_data = ipic;
589 ipic->hc_irq = ipic_irq_chip;
442 590
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0); 591 /* init hw */
592 ipic_write(ipic->regs, IPIC_SICNR, 0x0);
444 593
445 /* default priority scheme is grouped. If spread mode is required 594 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */ 595 * configure SICFR accordingly */
@@ -453,49 +602,35 @@ void __init ipic_init(phys_addr_t phys_addr,
453 if (flags & IPIC_SPREADMODE_MIX_B) 602 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB; 603 temp |= SICFR_MPSB;
455 604
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp); 605 ipic_write(ipic->regs, IPIC_SICNR, temp);
457 606
458 /* handle MCP route */ 607 /* handle MCP route */
459 temp = 0; 608 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT) 609 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR; 610 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp); 611 ipic_write(ipic->regs, IPIC_SERCR, temp);
463 612
464 /* handle routing of IRQ0 to MCP */ 613 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR); 614 temp = ipic_read(ipic->regs, IPIC_SEMSR);
466 615
467 if (flags & IPIC_IRQ0_MCP) 616 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0; 617 temp |= SEMSR_SIRQ0;
469 else 618 else
470 temp &= ~SEMSR_SIRQ0; 619 temp &= ~SEMSR_SIRQ0;
471 620
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp); 621 ipic_write(ipic->regs, IPIC_SEMSR, temp);
473 622
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) { 623 primary_ipic = ipic;
475 irq_desc[i+irq_offset].chip = &ipic; 624 irq_set_default_host(primary_ipic->irqhost);
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478 625
479 temp = 0; 626 printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
480 for (i = 0 ; i < senses_count ; i++) { 627 primary_ipic->regs);
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493} 628}
494 629
495int ipic_set_priority(unsigned int irq, unsigned int priority) 630int ipic_set_priority(unsigned int virq, unsigned int priority)
496{ 631{
497 struct ipic *ipic = ipic_from_irq(irq); 632 struct ipic *ipic = ipic_from_irq(virq);
498 unsigned int src = irq - ipic->irq_offset; 633 unsigned int src = ipic_irq_to_hw(virq);
499 u32 temp; 634 u32 temp;
500 635
501 if (priority > 7) 636 if (priority > 7)
@@ -520,10 +655,10 @@ int ipic_set_priority(unsigned int irq, unsigned int priority)
520 return 0; 655 return 0;
521} 656}
522 657
523void ipic_set_highest_priority(unsigned int irq) 658void ipic_set_highest_priority(unsigned int virq)
524{ 659{
525 struct ipic *ipic = ipic_from_irq(irq); 660 struct ipic *ipic = ipic_from_irq(virq);
526 unsigned int src = irq - ipic->irq_offset; 661 unsigned int src = ipic_irq_to_hw(virq);
527 u32 temp; 662 u32 temp;
528 663
529 temp = ipic_read(ipic->regs, IPIC_SICFR); 664 temp = ipic_read(ipic->regs, IPIC_SICFR);
@@ -537,37 +672,10 @@ void ipic_set_highest_priority(unsigned int irq)
537 672
538void ipic_set_default_priority(void) 673void ipic_set_default_priority(void)
539{ 674{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0); 675 ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_SIPRR_A_DEFAULT);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1); 676 ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_SIPRR_D_DEFAULT);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2); 677 ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_SMPRR_A_DEFAULT);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3); 678 ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_SMPRR_B_DEFAULT);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571} 679}
572 680
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq) 681void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
@@ -600,17 +708,20 @@ void ipic_clear_mcp_status(u32 mask)
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask); 708 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601} 709}
602 710
603/* Return an interrupt vector or -1 if no interrupt is pending. */ 711/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs) 712unsigned int ipic_get_irq(struct pt_regs *regs)
605{ 713{
606 int irq; 714 int irq;
607 715
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f; 716 BUG_ON(primary_ipic == NULL);
717
718#define IPIC_SIVCR_VECTOR_MASK 0x7f
719 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
609 720
610 if (irq == 0) /* 0 --> no irq is pending */ 721 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1; 722 return NO_IRQ;
612 723
613 return irq; 724 return irq_linear_revmap(primary_ipic->irqhost, irq);
614} 725}
615 726
616static struct sysdev_class ipic_sysclass = { 727static struct sysdev_class ipic_sysclass = {
diff --git a/arch/powerpc/sysdev/ipic.h b/arch/powerpc/sysdev/ipic.h
index a60c9d18bb7f..c28e589877eb 100644
--- a/arch/powerpc/sysdev/ipic.h
+++ b/arch/powerpc/sysdev/ipic.h
@@ -15,7 +15,18 @@
15 15
16#include <asm/ipic.h> 16#include <asm/ipic.h>
17 17
18#define MPC83xx_IPIC_SIZE (0x00100) 18#define NR_IPIC_INTS 128
19
20/* External IRQS */
21#define IPIC_IRQ_EXT0 48
22#define IPIC_IRQ_EXT1 17
23#define IPIC_IRQ_EXT7 23
24
25/* Default Priority Registers */
26#define IPIC_SIPRR_A_DEFAULT 0x05309770
27#define IPIC_SIPRR_D_DEFAULT 0x05309770
28#define IPIC_SMPRR_A_DEFAULT 0x05309770
29#define IPIC_SMPRR_B_DEFAULT 0x05309770
19 30
20/* System Global Interrupt Configuration Register */ 31/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000 32#define SICFR_IPSA 0x00010000
@@ -31,7 +42,15 @@
31 42
32struct ipic { 43struct ipic {
33 volatile u32 __iomem *regs; 44 volatile u32 __iomem *regs;
34 unsigned int irq_offset; 45
46 /* The remapper for this IPIC */
47 struct irq_host *irqhost;
48
49 /* The "linux" controller struct */
50 struct irq_chip hc_irq;
51
52 /* The device node of the interrupt controller */
53 struct device_node *of_node;
35}; 54};
36 55
37struct ipic_info { 56struct ipic_info {
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 6e0281afa6c3..b604926401f5 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -54,6 +54,94 @@ static DEFINE_SPINLOCK(mpic_lock);
54#endif 54#endif
55#endif 55#endif
56 56
57#ifdef CONFIG_MPIC_WEIRD
58static u32 mpic_infos[][MPIC_IDX_END] = {
59 [0] = { /* Original OpenPIC compatible MPIC */
60 MPIC_GREG_BASE,
61 MPIC_GREG_FEATURE_0,
62 MPIC_GREG_GLOBAL_CONF_0,
63 MPIC_GREG_VENDOR_ID,
64 MPIC_GREG_IPI_VECTOR_PRI_0,
65 MPIC_GREG_IPI_STRIDE,
66 MPIC_GREG_SPURIOUS,
67 MPIC_GREG_TIMER_FREQ,
68
69 MPIC_TIMER_BASE,
70 MPIC_TIMER_STRIDE,
71 MPIC_TIMER_CURRENT_CNT,
72 MPIC_TIMER_BASE_CNT,
73 MPIC_TIMER_VECTOR_PRI,
74 MPIC_TIMER_DESTINATION,
75
76 MPIC_CPU_BASE,
77 MPIC_CPU_STRIDE,
78 MPIC_CPU_IPI_DISPATCH_0,
79 MPIC_CPU_IPI_DISPATCH_STRIDE,
80 MPIC_CPU_CURRENT_TASK_PRI,
81 MPIC_CPU_WHOAMI,
82 MPIC_CPU_INTACK,
83 MPIC_CPU_EOI,
84
85 MPIC_IRQ_BASE,
86 MPIC_IRQ_STRIDE,
87 MPIC_IRQ_VECTOR_PRI,
88 MPIC_VECPRI_VECTOR_MASK,
89 MPIC_VECPRI_POLARITY_POSITIVE,
90 MPIC_VECPRI_POLARITY_NEGATIVE,
91 MPIC_VECPRI_SENSE_LEVEL,
92 MPIC_VECPRI_SENSE_EDGE,
93 MPIC_VECPRI_POLARITY_MASK,
94 MPIC_VECPRI_SENSE_MASK,
95 MPIC_IRQ_DESTINATION
96 },
97 [1] = { /* Tsi108/109 PIC */
98 TSI108_GREG_BASE,
99 TSI108_GREG_FEATURE_0,
100 TSI108_GREG_GLOBAL_CONF_0,
101 TSI108_GREG_VENDOR_ID,
102 TSI108_GREG_IPI_VECTOR_PRI_0,
103 TSI108_GREG_IPI_STRIDE,
104 TSI108_GREG_SPURIOUS,
105 TSI108_GREG_TIMER_FREQ,
106
107 TSI108_TIMER_BASE,
108 TSI108_TIMER_STRIDE,
109 TSI108_TIMER_CURRENT_CNT,
110 TSI108_TIMER_BASE_CNT,
111 TSI108_TIMER_VECTOR_PRI,
112 TSI108_TIMER_DESTINATION,
113
114 TSI108_CPU_BASE,
115 TSI108_CPU_STRIDE,
116 TSI108_CPU_IPI_DISPATCH_0,
117 TSI108_CPU_IPI_DISPATCH_STRIDE,
118 TSI108_CPU_CURRENT_TASK_PRI,
119 TSI108_CPU_WHOAMI,
120 TSI108_CPU_INTACK,
121 TSI108_CPU_EOI,
122
123 TSI108_IRQ_BASE,
124 TSI108_IRQ_STRIDE,
125 TSI108_IRQ_VECTOR_PRI,
126 TSI108_VECPRI_VECTOR_MASK,
127 TSI108_VECPRI_POLARITY_POSITIVE,
128 TSI108_VECPRI_POLARITY_NEGATIVE,
129 TSI108_VECPRI_SENSE_LEVEL,
130 TSI108_VECPRI_SENSE_EDGE,
131 TSI108_VECPRI_POLARITY_MASK,
132 TSI108_VECPRI_SENSE_MASK,
133 TSI108_IRQ_DESTINATION
134 },
135};
136
137#define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
138
139#else /* CONFIG_MPIC_WEIRD */
140
141#define MPIC_INFO(name) MPIC_##name
142
143#endif /* CONFIG_MPIC_WEIRD */
144
57/* 145/*
58 * Register accessor functions 146 * Register accessor functions
59 */ 147 */
@@ -80,7 +168,8 @@ static inline void _mpic_write(unsigned int be, volatile u32 __iomem *base,
80static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi) 168static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
81{ 169{
82 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0; 170 unsigned int be = (mpic->flags & MPIC_BIG_ENDIAN) != 0;
83 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 171 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
172 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
84 173
85 if (mpic->flags & MPIC_BROKEN_IPI) 174 if (mpic->flags & MPIC_BROKEN_IPI)
86 be = !be; 175 be = !be;
@@ -89,7 +178,8 @@ static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
89 178
90static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value) 179static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
91{ 180{
92 unsigned int offset = MPIC_GREG_IPI_VECTOR_PRI_0 + (ipi * 0x10); 181 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
182 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
93 183
94 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value); 184 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->gregs, offset, value);
95} 185}
@@ -120,7 +210,7 @@ static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigne
120 unsigned int idx = src_no & mpic->isu_mask; 210 unsigned int idx = src_no & mpic->isu_mask;
121 211
122 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 212 return _mpic_read(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
123 reg + (idx * MPIC_IRQ_STRIDE)); 213 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
124} 214}
125 215
126static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no, 216static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
@@ -130,7 +220,7 @@ static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
130 unsigned int idx = src_no & mpic->isu_mask; 220 unsigned int idx = src_no & mpic->isu_mask;
131 221
132 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu], 222 _mpic_write(mpic->flags & MPIC_BIG_ENDIAN, mpic->isus[isu],
133 reg + (idx * MPIC_IRQ_STRIDE), value); 223 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
134} 224}
135 225
136#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r)) 226#define mpic_read(b,r) _mpic_read(mpic->flags & MPIC_BIG_ENDIAN,(b),(r))
@@ -156,8 +246,8 @@ static void __init mpic_test_broken_ipi(struct mpic *mpic)
156{ 246{
157 u32 r; 247 u32 r;
158 248
159 mpic_write(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0, MPIC_VECPRI_MASK); 249 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
160 r = mpic_read(mpic->gregs, MPIC_GREG_IPI_VECTOR_PRI_0); 250 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
161 251
162 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) { 252 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
163 printk(KERN_INFO "mpic: Detected reversed IPI registers\n"); 253 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
@@ -394,8 +484,8 @@ static inline struct mpic * mpic_from_irq(unsigned int irq)
394/* Send an EOI */ 484/* Send an EOI */
395static inline void mpic_eoi(struct mpic *mpic) 485static inline void mpic_eoi(struct mpic *mpic)
396{ 486{
397 mpic_cpu_write(MPIC_CPU_EOI, 0); 487 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
398 (void)mpic_cpu_read(MPIC_CPU_WHOAMI); 488 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
399} 489}
400 490
401#ifdef CONFIG_SMP 491#ifdef CONFIG_SMP
@@ -419,8 +509,8 @@ static void mpic_unmask_irq(unsigned int irq)
419 509
420 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 510 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
421 511
422 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 512 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
423 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & 513 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
424 ~MPIC_VECPRI_MASK); 514 ~MPIC_VECPRI_MASK);
425 /* make sure mask gets to controller before we return to user */ 515 /* make sure mask gets to controller before we return to user */
426 do { 516 do {
@@ -428,7 +518,7 @@ static void mpic_unmask_irq(unsigned int irq)
428 printk(KERN_ERR "mpic_enable_irq timeout\n"); 518 printk(KERN_ERR "mpic_enable_irq timeout\n");
429 break; 519 break;
430 } 520 }
431 } while(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK); 521 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
432} 522}
433 523
434static void mpic_mask_irq(unsigned int irq) 524static void mpic_mask_irq(unsigned int irq)
@@ -439,8 +529,8 @@ static void mpic_mask_irq(unsigned int irq)
439 529
440 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 530 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
441 531
442 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 532 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
443 mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) | 533 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
444 MPIC_VECPRI_MASK); 534 MPIC_VECPRI_MASK);
445 535
446 /* make sure mask gets to controller before we return to user */ 536 /* make sure mask gets to controller before we return to user */
@@ -449,7 +539,7 @@ static void mpic_mask_irq(unsigned int irq)
449 printk(KERN_ERR "mpic_enable_irq timeout\n"); 539 printk(KERN_ERR "mpic_enable_irq timeout\n");
450 break; 540 break;
451 } 541 }
452 } while(!(mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) & MPIC_VECPRI_MASK)); 542 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
453} 543}
454 544
455static void mpic_end_irq(unsigned int irq) 545static void mpic_end_irq(unsigned int irq)
@@ -560,24 +650,28 @@ static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
560 650
561 cpus_and(tmp, cpumask, cpu_online_map); 651 cpus_and(tmp, cpumask, cpu_online_map);
562 652
563 mpic_irq_write(src, MPIC_IRQ_DESTINATION, 653 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
564 mpic_physmask(cpus_addr(tmp)[0])); 654 mpic_physmask(cpus_addr(tmp)[0]));
565} 655}
566 656
567static unsigned int mpic_type_to_vecpri(unsigned int type) 657static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
568{ 658{
569 /* Now convert sense value */ 659 /* Now convert sense value */
570 switch(type & IRQ_TYPE_SENSE_MASK) { 660 switch(type & IRQ_TYPE_SENSE_MASK) {
571 case IRQ_TYPE_EDGE_RISING: 661 case IRQ_TYPE_EDGE_RISING:
572 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_POSITIVE; 662 return MPIC_INFO(VECPRI_SENSE_EDGE) |
663 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
573 case IRQ_TYPE_EDGE_FALLING: 664 case IRQ_TYPE_EDGE_FALLING:
574 case IRQ_TYPE_EDGE_BOTH: 665 case IRQ_TYPE_EDGE_BOTH:
575 return MPIC_VECPRI_SENSE_EDGE | MPIC_VECPRI_POLARITY_NEGATIVE; 666 return MPIC_INFO(VECPRI_SENSE_EDGE) |
667 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
576 case IRQ_TYPE_LEVEL_HIGH: 668 case IRQ_TYPE_LEVEL_HIGH:
577 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_POSITIVE; 669 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
670 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
578 case IRQ_TYPE_LEVEL_LOW: 671 case IRQ_TYPE_LEVEL_LOW:
579 default: 672 default:
580 return MPIC_VECPRI_SENSE_LEVEL | MPIC_VECPRI_POLARITY_NEGATIVE; 673 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
674 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
581 } 675 }
582} 676}
583 677
@@ -609,13 +703,14 @@ static int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
609 vecpri = MPIC_VECPRI_POLARITY_POSITIVE | 703 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
610 MPIC_VECPRI_SENSE_EDGE; 704 MPIC_VECPRI_SENSE_EDGE;
611 else 705 else
612 vecpri = mpic_type_to_vecpri(flow_type); 706 vecpri = mpic_type_to_vecpri(mpic, flow_type);
613 707
614 vold = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 708 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
615 vnew = vold & ~(MPIC_VECPRI_POLARITY_MASK | MPIC_VECPRI_SENSE_MASK); 709 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
710 MPIC_INFO(VECPRI_SENSE_MASK));
616 vnew |= vecpri; 711 vnew |= vecpri;
617 if (vold != vnew) 712 if (vold != vnew)
618 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, vnew); 713 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
619 714
620 return 0; 715 return 0;
621} 716}
@@ -798,17 +893,22 @@ struct mpic * __init mpic_alloc(struct device_node *node,
798 mpic->irq_count = irq_count; 893 mpic->irq_count = irq_count;
799 mpic->num_sources = 0; /* so far */ 894 mpic->num_sources = 0; /* so far */
800 895
896#ifdef CONFIG_MPIC_WEIRD
897 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
898#endif
899
801 /* Map the global registers */ 900 /* Map the global registers */
802 mpic->gregs = ioremap(phys_addr + MPIC_GREG_BASE, 0x1000); 901 mpic->gregs = ioremap(phys_addr + MPIC_INFO(GREG_BASE), 0x1000);
803 mpic->tmregs = mpic->gregs + ((MPIC_TIMER_BASE - MPIC_GREG_BASE) >> 2); 902 mpic->tmregs = mpic->gregs +
903 ((MPIC_INFO(TIMER_BASE) - MPIC_INFO(GREG_BASE)) >> 2);
804 BUG_ON(mpic->gregs == NULL); 904 BUG_ON(mpic->gregs == NULL);
805 905
806 /* Reset */ 906 /* Reset */
807 if (flags & MPIC_WANTS_RESET) { 907 if (flags & MPIC_WANTS_RESET) {
808 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 908 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
809 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 909 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
810 | MPIC_GREG_GCONF_RESET); 910 | MPIC_GREG_GCONF_RESET);
811 while( mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 911 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
812 & MPIC_GREG_GCONF_RESET) 912 & MPIC_GREG_GCONF_RESET)
813 mb(); 913 mb();
814 } 914 }
@@ -817,7 +917,7 @@ struct mpic * __init mpic_alloc(struct device_node *node,
817 * MPICs, num sources as well. On ISU MPICs, sources are counted 917 * MPICs, num sources as well. On ISU MPICs, sources are counted
818 * as ISUs are added 918 * as ISUs are added
819 */ 919 */
820 reg = mpic_read(mpic->gregs, MPIC_GREG_FEATURE_0); 920 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
821 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK) 921 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
822 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1; 922 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
823 if (isu_size == 0) 923 if (isu_size == 0)
@@ -826,16 +926,16 @@ struct mpic * __init mpic_alloc(struct device_node *node,
826 926
827 /* Map the per-CPU registers */ 927 /* Map the per-CPU registers */
828 for (i = 0; i < mpic->num_cpus; i++) { 928 for (i = 0; i < mpic->num_cpus; i++) {
829 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_CPU_BASE + 929 mpic->cpuregs[i] = ioremap(phys_addr + MPIC_INFO(CPU_BASE) +
830 i * MPIC_CPU_STRIDE, 0x1000); 930 i * MPIC_INFO(CPU_STRIDE), 0x1000);
831 BUG_ON(mpic->cpuregs[i] == NULL); 931 BUG_ON(mpic->cpuregs[i] == NULL);
832 } 932 }
833 933
834 /* Initialize main ISU if none provided */ 934 /* Initialize main ISU if none provided */
835 if (mpic->isu_size == 0) { 935 if (mpic->isu_size == 0) {
836 mpic->isu_size = mpic->num_sources; 936 mpic->isu_size = mpic->num_sources;
837 mpic->isus[0] = ioremap(phys_addr + MPIC_IRQ_BASE, 937 mpic->isus[0] = ioremap(phys_addr + MPIC_INFO(IRQ_BASE),
838 MPIC_IRQ_STRIDE * mpic->isu_size); 938 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
839 BUG_ON(mpic->isus[0] == NULL); 939 BUG_ON(mpic->isus[0] == NULL);
840 } 940 }
841 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1); 941 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
@@ -879,7 +979,8 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
879 979
880 BUG_ON(isu_num >= MPIC_MAX_ISU); 980 BUG_ON(isu_num >= MPIC_MAX_ISU);
881 981
882 mpic->isus[isu_num] = ioremap(phys_addr, MPIC_IRQ_STRIDE * mpic->isu_size); 982 mpic->isus[isu_num] = ioremap(phys_addr,
983 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
883 if ((isu_first + mpic->isu_size) > mpic->num_sources) 984 if ((isu_first + mpic->isu_size) > mpic->num_sources)
884 mpic->num_sources = isu_first + mpic->isu_size; 985 mpic->num_sources = isu_first + mpic->isu_size;
885} 986}
@@ -904,14 +1005,16 @@ void __init mpic_init(struct mpic *mpic)
904 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources); 1005 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
905 1006
906 /* Set current processor priority to max */ 1007 /* Set current processor priority to max */
907 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1008 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
908 1009
909 /* Initialize timers: just disable them all */ 1010 /* Initialize timers: just disable them all */
910 for (i = 0; i < 4; i++) { 1011 for (i = 0; i < 4; i++) {
911 mpic_write(mpic->tmregs, 1012 mpic_write(mpic->tmregs,
912 i * MPIC_TIMER_STRIDE + MPIC_TIMER_DESTINATION, 0); 1013 i * MPIC_INFO(TIMER_STRIDE) +
1014 MPIC_INFO(TIMER_DESTINATION), 0);
913 mpic_write(mpic->tmregs, 1015 mpic_write(mpic->tmregs,
914 i * MPIC_TIMER_STRIDE + MPIC_TIMER_VECTOR_PRI, 1016 i * MPIC_INFO(TIMER_STRIDE) +
1017 MPIC_INFO(TIMER_VECTOR_PRI),
915 MPIC_VECPRI_MASK | 1018 MPIC_VECPRI_MASK |
916 (MPIC_VEC_TIMER_0 + i)); 1019 (MPIC_VEC_TIMER_0 + i));
917 } 1020 }
@@ -940,21 +1043,22 @@ void __init mpic_init(struct mpic *mpic)
940 (8 << MPIC_VECPRI_PRIORITY_SHIFT); 1043 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
941 1044
942 /* init hw */ 1045 /* init hw */
943 mpic_irq_write(i, MPIC_IRQ_VECTOR_PRI, vecpri); 1046 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
944 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1047 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
945 1 << hard_smp_processor_id()); 1048 1 << hard_smp_processor_id());
946 } 1049 }
947 1050
948 /* Init spurrious vector */ 1051 /* Init spurrious vector */
949 mpic_write(mpic->gregs, MPIC_GREG_SPURIOUS, MPIC_VEC_SPURRIOUS); 1052 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), MPIC_VEC_SPURRIOUS);
950 1053
951 /* Disable 8259 passthrough */ 1054 /* Disable 8259 passthrough, if supported */
952 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0, 1055 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
953 mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_0) 1056 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
954 | MPIC_GREG_GCONF_8259_PTHROU_DIS); 1057 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1058 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
955 1059
956 /* Set current processor priority to 0 */ 1060 /* Set current processor priority to 0 */
957 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1061 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
958} 1062}
959 1063
960void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio) 1064void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
@@ -997,9 +1101,9 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
997 mpic_ipi_write(src - MPIC_VEC_IPI_0, 1101 mpic_ipi_write(src - MPIC_VEC_IPI_0,
998 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1102 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
999 } else { 1103 } else {
1000 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI) 1104 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1001 & ~MPIC_VECPRI_PRIORITY_MASK; 1105 & ~MPIC_VECPRI_PRIORITY_MASK;
1002 mpic_irq_write(src, MPIC_IRQ_VECTOR_PRI, 1106 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1003 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT)); 1107 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1004 } 1108 }
1005 spin_unlock_irqrestore(&mpic_lock, flags); 1109 spin_unlock_irqrestore(&mpic_lock, flags);
@@ -1017,7 +1121,7 @@ unsigned int mpic_irq_get_priority(unsigned int irq)
1017 if (is_ipi) 1121 if (is_ipi)
1018 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0); 1122 reg = mpic_ipi_read(src = MPIC_VEC_IPI_0);
1019 else 1123 else
1020 reg = mpic_irq_read(src, MPIC_IRQ_VECTOR_PRI); 1124 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1021 spin_unlock_irqrestore(&mpic_lock, flags); 1125 spin_unlock_irqrestore(&mpic_lock, flags);
1022 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT; 1126 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1023} 1127}
@@ -1043,12 +1147,12 @@ void mpic_setup_this_cpu(void)
1043 */ 1147 */
1044 if (distribute_irqs) { 1148 if (distribute_irqs) {
1045 for (i = 0; i < mpic->num_sources ; i++) 1149 for (i = 0; i < mpic->num_sources ; i++)
1046 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1150 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1047 mpic_irq_read(i, MPIC_IRQ_DESTINATION) | msk); 1151 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1048 } 1152 }
1049 1153
1050 /* Set current processor priority to 0 */ 1154 /* Set current processor priority to 0 */
1051 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0); 1155 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1052 1156
1053 spin_unlock_irqrestore(&mpic_lock, flags); 1157 spin_unlock_irqrestore(&mpic_lock, flags);
1054#endif /* CONFIG_SMP */ 1158#endif /* CONFIG_SMP */
@@ -1058,7 +1162,7 @@ int mpic_cpu_get_priority(void)
1058{ 1162{
1059 struct mpic *mpic = mpic_primary; 1163 struct mpic *mpic = mpic_primary;
1060 1164
1061 return mpic_cpu_read(MPIC_CPU_CURRENT_TASK_PRI); 1165 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1062} 1166}
1063 1167
1064void mpic_cpu_set_priority(int prio) 1168void mpic_cpu_set_priority(int prio)
@@ -1066,7 +1170,7 @@ void mpic_cpu_set_priority(int prio)
1066 struct mpic *mpic = mpic_primary; 1170 struct mpic *mpic = mpic_primary;
1067 1171
1068 prio &= MPIC_CPU_TASKPRI_MASK; 1172 prio &= MPIC_CPU_TASKPRI_MASK;
1069 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, prio); 1173 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1070} 1174}
1071 1175
1072/* 1176/*
@@ -1088,11 +1192,11 @@ void mpic_teardown_this_cpu(int secondary)
1088 1192
1089 /* let the mpic know we don't want intrs. */ 1193 /* let the mpic know we don't want intrs. */
1090 for (i = 0; i < mpic->num_sources ; i++) 1194 for (i = 0; i < mpic->num_sources ; i++)
1091 mpic_irq_write(i, MPIC_IRQ_DESTINATION, 1195 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1092 mpic_irq_read(i, MPIC_IRQ_DESTINATION) & ~msk); 1196 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1093 1197
1094 /* Set current processor priority to max */ 1198 /* Set current processor priority to max */
1095 mpic_cpu_write(MPIC_CPU_CURRENT_TASK_PRI, 0xf); 1199 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1096 1200
1097 spin_unlock_irqrestore(&mpic_lock, flags); 1201 spin_unlock_irqrestore(&mpic_lock, flags);
1098} 1202}
@@ -1108,7 +1212,8 @@ void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1108 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no); 1212 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1109#endif 1213#endif
1110 1214
1111 mpic_cpu_write(MPIC_CPU_IPI_DISPATCH_0 + ipi_no * 0x10, 1215 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1216 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1112 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0])); 1217 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1113} 1218}
1114 1219
@@ -1116,7 +1221,7 @@ unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs)
1116{ 1221{
1117 u32 src; 1222 u32 src;
1118 1223
1119 src = mpic_cpu_read(MPIC_CPU_INTACK) & MPIC_VECPRI_VECTOR_MASK; 1224 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1120#ifdef DEBUG_LOW 1225#ifdef DEBUG_LOW
1121 DBG("%s: get_one_irq(): %d\n", mpic->name, src); 1226 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1122#endif 1227#endif
diff --git a/arch/ppc/kernel/smp-tbsync.c b/arch/ppc/kernel/smp-tbsync.c
index 1576758debaf..d0cf3f86931d 100644
--- a/arch/ppc/kernel/smp-tbsync.c
+++ b/arch/ppc/kernel/smp-tbsync.c
@@ -47,8 +47,9 @@ void __devinit
47smp_generic_take_timebase( void ) 47smp_generic_take_timebase( void )
48{ 48{
49 int cmd, tbl, tbu; 49 int cmd, tbl, tbu;
50 unsigned long flags;
50 51
51 local_irq_disable(); 52 local_irq_save(flags);
52 while( !running ) 53 while( !running )
53 ; 54 ;
54 rmb(); 55 rmb();
@@ -64,7 +65,7 @@ smp_generic_take_timebase( void )
64 tbu = tbsync->tbu; 65 tbu = tbsync->tbu;
65 tbsync->ack = 0; 66 tbsync->ack = 0;
66 if( cmd == kExit ) 67 if( cmd == kExit )
67 return; 68 break;
68 69
69 if( cmd == kSetAndTest ) { 70 if( cmd == kSetAndTest ) {
70 while( tbsync->handshake ) 71 while( tbsync->handshake )
@@ -77,7 +78,7 @@ smp_generic_take_timebase( void )
77 } 78 }
78 enter_contest( tbsync->mark, -1 ); 79 enter_contest( tbsync->mark, -1 );
79 } 80 }
80 local_irq_enable(); 81 local_irq_restore(flags);
81} 82}
82 83
83static int __devinit 84static int __devinit
diff --git a/arch/ppc/syslib/Makefile b/arch/ppc/syslib/Makefile
index 2497bbc07e76..dca23f2ef851 100644
--- a/arch/ppc/syslib/Makefile
+++ b/arch/ppc/syslib/Makefile
@@ -93,7 +93,7 @@ obj-$(CONFIG_PCI) += pci_auto.o
93endif 93endif
94obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o 94obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
95obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \ 95obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
96 mpc83xx_sys.o mpc83xx_devices.o 96 mpc83xx_sys.o mpc83xx_devices.o ipic.o
97ifeq ($(CONFIG_83xx),y) 97ifeq ($(CONFIG_83xx),y)
98obj-$(CONFIG_PCI) += pci_auto.o 98obj-$(CONFIG_PCI) += pci_auto.o
99endif 99endif
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c
new file mode 100644
index 000000000000..46801f5ec03f
--- /dev/null
+++ b/arch/ppc/syslib/ipic.c
@@ -0,0 +1,646 @@
1/*
2 * include/asm-ppc/ipic.c
3 *
4 * IPIC routines implementations.
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/errno.h>
16#include <linux/reboot.h>
17#include <linux/slab.h>
18#include <linux/stddef.h>
19#include <linux/sched.h>
20#include <linux/signal.h>
21#include <linux/sysdev.h>
22#include <asm/irq.h>
23#include <asm/io.h>
24#include <asm/ipic.h>
25#include <asm/mpc83xx.h>
26
27#include "ipic.h"
28
29static struct ipic p_ipic;
30static struct ipic * primary_ipic;
31
32static struct ipic_info ipic_info[] = {
33 [9] = {
34 .pend = IPIC_SIPNR_H,
35 .mask = IPIC_SIMSR_H,
36 .prio = IPIC_SIPRR_D,
37 .force = IPIC_SIFCR_H,
38 .bit = 24,
39 .prio_mask = 0,
40 },
41 [10] = {
42 .pend = IPIC_SIPNR_H,
43 .mask = IPIC_SIMSR_H,
44 .prio = IPIC_SIPRR_D,
45 .force = IPIC_SIFCR_H,
46 .bit = 25,
47 .prio_mask = 1,
48 },
49 [11] = {
50 .pend = IPIC_SIPNR_H,
51 .mask = IPIC_SIMSR_H,
52 .prio = IPIC_SIPRR_D,
53 .force = IPIC_SIFCR_H,
54 .bit = 26,
55 .prio_mask = 2,
56 },
57 [14] = {
58 .pend = IPIC_SIPNR_H,
59 .mask = IPIC_SIMSR_H,
60 .prio = IPIC_SIPRR_D,
61 .force = IPIC_SIFCR_H,
62 .bit = 29,
63 .prio_mask = 5,
64 },
65 [15] = {
66 .pend = IPIC_SIPNR_H,
67 .mask = IPIC_SIMSR_H,
68 .prio = IPIC_SIPRR_D,
69 .force = IPIC_SIFCR_H,
70 .bit = 30,
71 .prio_mask = 6,
72 },
73 [16] = {
74 .pend = IPIC_SIPNR_H,
75 .mask = IPIC_SIMSR_H,
76 .prio = IPIC_SIPRR_D,
77 .force = IPIC_SIFCR_H,
78 .bit = 31,
79 .prio_mask = 7,
80 },
81 [17] = {
82 .pend = IPIC_SEPNR,
83 .mask = IPIC_SEMSR,
84 .prio = IPIC_SMPRR_A,
85 .force = IPIC_SEFCR,
86 .bit = 1,
87 .prio_mask = 5,
88 },
89 [18] = {
90 .pend = IPIC_SEPNR,
91 .mask = IPIC_SEMSR,
92 .prio = IPIC_SMPRR_A,
93 .force = IPIC_SEFCR,
94 .bit = 2,
95 .prio_mask = 6,
96 },
97 [19] = {
98 .pend = IPIC_SEPNR,
99 .mask = IPIC_SEMSR,
100 .prio = IPIC_SMPRR_A,
101 .force = IPIC_SEFCR,
102 .bit = 3,
103 .prio_mask = 7,
104 },
105 [20] = {
106 .pend = IPIC_SEPNR,
107 .mask = IPIC_SEMSR,
108 .prio = IPIC_SMPRR_B,
109 .force = IPIC_SEFCR,
110 .bit = 4,
111 .prio_mask = 4,
112 },
113 [21] = {
114 .pend = IPIC_SEPNR,
115 .mask = IPIC_SEMSR,
116 .prio = IPIC_SMPRR_B,
117 .force = IPIC_SEFCR,
118 .bit = 5,
119 .prio_mask = 5,
120 },
121 [22] = {
122 .pend = IPIC_SEPNR,
123 .mask = IPIC_SEMSR,
124 .prio = IPIC_SMPRR_B,
125 .force = IPIC_SEFCR,
126 .bit = 6,
127 .prio_mask = 6,
128 },
129 [23] = {
130 .pend = IPIC_SEPNR,
131 .mask = IPIC_SEMSR,
132 .prio = IPIC_SMPRR_B,
133 .force = IPIC_SEFCR,
134 .bit = 7,
135 .prio_mask = 7,
136 },
137 [32] = {
138 .pend = IPIC_SIPNR_H,
139 .mask = IPIC_SIMSR_H,
140 .prio = IPIC_SIPRR_A,
141 .force = IPIC_SIFCR_H,
142 .bit = 0,
143 .prio_mask = 0,
144 },
145 [33] = {
146 .pend = IPIC_SIPNR_H,
147 .mask = IPIC_SIMSR_H,
148 .prio = IPIC_SIPRR_A,
149 .force = IPIC_SIFCR_H,
150 .bit = 1,
151 .prio_mask = 1,
152 },
153 [34] = {
154 .pend = IPIC_SIPNR_H,
155 .mask = IPIC_SIMSR_H,
156 .prio = IPIC_SIPRR_A,
157 .force = IPIC_SIFCR_H,
158 .bit = 2,
159 .prio_mask = 2,
160 },
161 [35] = {
162 .pend = IPIC_SIPNR_H,
163 .mask = IPIC_SIMSR_H,
164 .prio = IPIC_SIPRR_A,
165 .force = IPIC_SIFCR_H,
166 .bit = 3,
167 .prio_mask = 3,
168 },
169 [36] = {
170 .pend = IPIC_SIPNR_H,
171 .mask = IPIC_SIMSR_H,
172 .prio = IPIC_SIPRR_A,
173 .force = IPIC_SIFCR_H,
174 .bit = 4,
175 .prio_mask = 4,
176 },
177 [37] = {
178 .pend = IPIC_SIPNR_H,
179 .mask = IPIC_SIMSR_H,
180 .prio = IPIC_SIPRR_A,
181 .force = IPIC_SIFCR_H,
182 .bit = 5,
183 .prio_mask = 5,
184 },
185 [38] = {
186 .pend = IPIC_SIPNR_H,
187 .mask = IPIC_SIMSR_H,
188 .prio = IPIC_SIPRR_A,
189 .force = IPIC_SIFCR_H,
190 .bit = 6,
191 .prio_mask = 6,
192 },
193 [39] = {
194 .pend = IPIC_SIPNR_H,
195 .mask = IPIC_SIMSR_H,
196 .prio = IPIC_SIPRR_A,
197 .force = IPIC_SIFCR_H,
198 .bit = 7,
199 .prio_mask = 7,
200 },
201 [48] = {
202 .pend = IPIC_SEPNR,
203 .mask = IPIC_SEMSR,
204 .prio = IPIC_SMPRR_A,
205 .force = IPIC_SEFCR,
206 .bit = 0,
207 .prio_mask = 4,
208 },
209 [64] = {
210 .pend = IPIC_SIPNR_H,
211 .mask = IPIC_SIMSR_L,
212 .prio = IPIC_SMPRR_A,
213 .force = IPIC_SIFCR_L,
214 .bit = 0,
215 .prio_mask = 0,
216 },
217 [65] = {
218 .pend = IPIC_SIPNR_H,
219 .mask = IPIC_SIMSR_L,
220 .prio = IPIC_SMPRR_A,
221 .force = IPIC_SIFCR_L,
222 .bit = 1,
223 .prio_mask = 1,
224 },
225 [66] = {
226 .pend = IPIC_SIPNR_H,
227 .mask = IPIC_SIMSR_L,
228 .prio = IPIC_SMPRR_A,
229 .force = IPIC_SIFCR_L,
230 .bit = 2,
231 .prio_mask = 2,
232 },
233 [67] = {
234 .pend = IPIC_SIPNR_H,
235 .mask = IPIC_SIMSR_L,
236 .prio = IPIC_SMPRR_A,
237 .force = IPIC_SIFCR_L,
238 .bit = 3,
239 .prio_mask = 3,
240 },
241 [68] = {
242 .pend = IPIC_SIPNR_H,
243 .mask = IPIC_SIMSR_L,
244 .prio = IPIC_SMPRR_B,
245 .force = IPIC_SIFCR_L,
246 .bit = 4,
247 .prio_mask = 0,
248 },
249 [69] = {
250 .pend = IPIC_SIPNR_H,
251 .mask = IPIC_SIMSR_L,
252 .prio = IPIC_SMPRR_B,
253 .force = IPIC_SIFCR_L,
254 .bit = 5,
255 .prio_mask = 1,
256 },
257 [70] = {
258 .pend = IPIC_SIPNR_H,
259 .mask = IPIC_SIMSR_L,
260 .prio = IPIC_SMPRR_B,
261 .force = IPIC_SIFCR_L,
262 .bit = 6,
263 .prio_mask = 2,
264 },
265 [71] = {
266 .pend = IPIC_SIPNR_H,
267 .mask = IPIC_SIMSR_L,
268 .prio = IPIC_SMPRR_B,
269 .force = IPIC_SIFCR_L,
270 .bit = 7,
271 .prio_mask = 3,
272 },
273 [72] = {
274 .pend = IPIC_SIPNR_H,
275 .mask = IPIC_SIMSR_L,
276 .prio = 0,
277 .force = IPIC_SIFCR_L,
278 .bit = 8,
279 },
280 [73] = {
281 .pend = IPIC_SIPNR_H,
282 .mask = IPIC_SIMSR_L,
283 .prio = 0,
284 .force = IPIC_SIFCR_L,
285 .bit = 9,
286 },
287 [74] = {
288 .pend = IPIC_SIPNR_H,
289 .mask = IPIC_SIMSR_L,
290 .prio = 0,
291 .force = IPIC_SIFCR_L,
292 .bit = 10,
293 },
294 [75] = {
295 .pend = IPIC_SIPNR_H,
296 .mask = IPIC_SIMSR_L,
297 .prio = 0,
298 .force = IPIC_SIFCR_L,
299 .bit = 11,
300 },
301 [76] = {
302 .pend = IPIC_SIPNR_H,
303 .mask = IPIC_SIMSR_L,
304 .prio = 0,
305 .force = IPIC_SIFCR_L,
306 .bit = 12,
307 },
308 [77] = {
309 .pend = IPIC_SIPNR_H,
310 .mask = IPIC_SIMSR_L,
311 .prio = 0,
312 .force = IPIC_SIFCR_L,
313 .bit = 13,
314 },
315 [78] = {
316 .pend = IPIC_SIPNR_H,
317 .mask = IPIC_SIMSR_L,
318 .prio = 0,
319 .force = IPIC_SIFCR_L,
320 .bit = 14,
321 },
322 [79] = {
323 .pend = IPIC_SIPNR_H,
324 .mask = IPIC_SIMSR_L,
325 .prio = 0,
326 .force = IPIC_SIFCR_L,
327 .bit = 15,
328 },
329 [80] = {
330 .pend = IPIC_SIPNR_H,
331 .mask = IPIC_SIMSR_L,
332 .prio = 0,
333 .force = IPIC_SIFCR_L,
334 .bit = 16,
335 },
336 [84] = {
337 .pend = IPIC_SIPNR_H,
338 .mask = IPIC_SIMSR_L,
339 .prio = 0,
340 .force = IPIC_SIFCR_L,
341 .bit = 20,
342 },
343 [85] = {
344 .pend = IPIC_SIPNR_H,
345 .mask = IPIC_SIMSR_L,
346 .prio = 0,
347 .force = IPIC_SIFCR_L,
348 .bit = 21,
349 },
350 [90] = {
351 .pend = IPIC_SIPNR_H,
352 .mask = IPIC_SIMSR_L,
353 .prio = 0,
354 .force = IPIC_SIFCR_L,
355 .bit = 26,
356 },
357 [91] = {
358 .pend = IPIC_SIPNR_H,
359 .mask = IPIC_SIMSR_L,
360 .prio = 0,
361 .force = IPIC_SIFCR_L,
362 .bit = 27,
363 },
364};
365
366static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
367{
368 return in_be32(base + (reg >> 2));
369}
370
371static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
372{
373 out_be32(base + (reg >> 2), value);
374}
375
376static inline struct ipic * ipic_from_irq(unsigned int irq)
377{
378 return primary_ipic;
379}
380
381static void ipic_enable_irq(unsigned int irq)
382{
383 struct ipic *ipic = ipic_from_irq(irq);
384 unsigned int src = irq - ipic->irq_offset;
385 u32 temp;
386
387 temp = ipic_read(ipic->regs, ipic_info[src].mask);
388 temp |= (1 << (31 - ipic_info[src].bit));
389 ipic_write(ipic->regs, ipic_info[src].mask, temp);
390}
391
392static void ipic_disable_irq(unsigned int irq)
393{
394 struct ipic *ipic = ipic_from_irq(irq);
395 unsigned int src = irq - ipic->irq_offset;
396 u32 temp;
397
398 temp = ipic_read(ipic->regs, ipic_info[src].mask);
399 temp &= ~(1 << (31 - ipic_info[src].bit));
400 ipic_write(ipic->regs, ipic_info[src].mask, temp);
401}
402
403static void ipic_disable_irq_and_ack(unsigned int irq)
404{
405 struct ipic *ipic = ipic_from_irq(irq);
406 unsigned int src = irq - ipic->irq_offset;
407 u32 temp;
408
409 ipic_disable_irq(irq);
410
411 temp = ipic_read(ipic->regs, ipic_info[src].pend);
412 temp |= (1 << (31 - ipic_info[src].bit));
413 ipic_write(ipic->regs, ipic_info[src].pend, temp);
414}
415
416static void ipic_end_irq(unsigned int irq)
417{
418 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
419 ipic_enable_irq(irq);
420}
421
422struct hw_interrupt_type ipic = {
423 .typename = " IPIC ",
424 .enable = ipic_enable_irq,
425 .disable = ipic_disable_irq,
426 .ack = ipic_disable_irq_and_ack,
427 .end = ipic_end_irq,
428};
429
430void __init ipic_init(phys_addr_t phys_addr,
431 unsigned int flags,
432 unsigned int irq_offset,
433 unsigned char *senses,
434 unsigned int senses_count)
435{
436 u32 i, temp = 0;
437
438 primary_ipic = &p_ipic;
439 primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
440
441 primary_ipic->irq_offset = irq_offset;
442
443 ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
444
445 /* default priority scheme is grouped. If spread mode is required
446 * configure SICFR accordingly */
447 if (flags & IPIC_SPREADMODE_GRP_A)
448 temp |= SICFR_IPSA;
449 if (flags & IPIC_SPREADMODE_GRP_D)
450 temp |= SICFR_IPSD;
451 if (flags & IPIC_SPREADMODE_MIX_A)
452 temp |= SICFR_MPSA;
453 if (flags & IPIC_SPREADMODE_MIX_B)
454 temp |= SICFR_MPSB;
455
456 ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
457
458 /* handle MCP route */
459 temp = 0;
460 if (flags & IPIC_DISABLE_MCP_OUT)
461 temp = SERCR_MCPR;
462 ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
463
464 /* handle routing of IRQ0 to MCP */
465 temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
466
467 if (flags & IPIC_IRQ0_MCP)
468 temp |= SEMSR_SIRQ0;
469 else
470 temp &= ~SEMSR_SIRQ0;
471
472 ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
473
474 for (i = 0 ; i < NR_IPIC_INTS ; i++) {
475 irq_desc[i+irq_offset].chip = &ipic;
476 irq_desc[i+irq_offset].status = IRQ_LEVEL;
477 }
478
479 temp = 0;
480 for (i = 0 ; i < senses_count ; i++) {
481 if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
482 temp |= 1 << (15 - i);
483 if (i != 0)
484 irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
485 else
486 irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
487 }
488 }
489 ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
490
491 printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
492 senses_count, primary_ipic->regs);
493}
494
495int ipic_set_priority(unsigned int irq, unsigned int priority)
496{
497 struct ipic *ipic = ipic_from_irq(irq);
498 unsigned int src = irq - ipic->irq_offset;
499 u32 temp;
500
501 if (priority > 7)
502 return -EINVAL;
503 if (src > 127)
504 return -EINVAL;
505 if (ipic_info[src].prio == 0)
506 return -EINVAL;
507
508 temp = ipic_read(ipic->regs, ipic_info[src].prio);
509
510 if (priority < 4) {
511 temp &= ~(0x7 << (20 + (3 - priority) * 3));
512 temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
513 } else {
514 temp &= ~(0x7 << (4 + (7 - priority) * 3));
515 temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
516 }
517
518 ipic_write(ipic->regs, ipic_info[src].prio, temp);
519
520 return 0;
521}
522
523void ipic_set_highest_priority(unsigned int irq)
524{
525 struct ipic *ipic = ipic_from_irq(irq);
526 unsigned int src = irq - ipic->irq_offset;
527 u32 temp;
528
529 temp = ipic_read(ipic->regs, IPIC_SICFR);
530
531 /* clear and set HPI */
532 temp &= 0x7f000000;
533 temp |= (src & 0x7f) << 24;
534
535 ipic_write(ipic->regs, IPIC_SICFR, temp);
536}
537
538void ipic_set_default_priority(void)
539{
540 ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
541 ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
542 ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
543 ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
544 ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
545 ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
546 ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
547 ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
548
549 ipic_set_priority(MPC83xx_IRQ_UART1, 0);
550 ipic_set_priority(MPC83xx_IRQ_UART2, 1);
551 ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
552 ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
553 ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
554 ipic_set_priority(MPC83xx_IRQ_SPI, 7);
555 ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
556 ipic_set_priority(MPC83xx_IRQ_PIT, 1);
557 ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
558 ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
559 ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
560 ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
561 ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
562 ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
563 ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
564 ipic_set_priority(MPC83xx_IRQ_MU, 1);
565 ipic_set_priority(MPC83xx_IRQ_SBA, 2);
566 ipic_set_priority(MPC83xx_IRQ_DMA, 3);
567 ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
568 ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
569 ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
570 ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
571}
572
573void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
574{
575 struct ipic *ipic = primary_ipic;
576 u32 temp;
577
578 temp = ipic_read(ipic->regs, IPIC_SERMR);
579 temp |= (1 << (31 - mcp_irq));
580 ipic_write(ipic->regs, IPIC_SERMR, temp);
581}
582
583void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
584{
585 struct ipic *ipic = primary_ipic;
586 u32 temp;
587
588 temp = ipic_read(ipic->regs, IPIC_SERMR);
589 temp &= (1 << (31 - mcp_irq));
590 ipic_write(ipic->regs, IPIC_SERMR, temp);
591}
592
593u32 ipic_get_mcp_status(void)
594{
595 return ipic_read(primary_ipic->regs, IPIC_SERMR);
596}
597
598void ipic_clear_mcp_status(u32 mask)
599{
600 ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
601}
602
603/* Return an interrupt vector or -1 if no interrupt is pending. */
604int ipic_get_irq(struct pt_regs *regs)
605{
606 int irq;
607
608 irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
609
610 if (irq == 0) /* 0 --> no irq is pending */
611 irq = -1;
612
613 return irq;
614}
615
616static struct sysdev_class ipic_sysclass = {
617 set_kset_name("ipic"),
618};
619
620static struct sys_device device_ipic = {
621 .id = 0,
622 .cls = &ipic_sysclass,
623};
624
625static int __init init_ipic_sysfs(void)
626{
627 int rc;
628
629 if (!primary_ipic->regs)
630 return -ENODEV;
631 printk(KERN_DEBUG "Registering ipic with sysfs...\n");
632
633 rc = sysdev_class_register(&ipic_sysclass);
634 if (rc) {
635 printk(KERN_ERR "Failed registering ipic sys class\n");
636 return -ENODEV;
637 }
638 rc = sysdev_register(&device_ipic);
639 if (rc) {
640 printk(KERN_ERR "Failed registering ipic sys device\n");
641 return -ENODEV;
642 }
643 return 0;
644}
645
646subsys_initcall(init_ipic_sysfs);
diff --git a/arch/ppc/syslib/ipic.h b/arch/ppc/syslib/ipic.h
new file mode 100644
index 000000000000..a60c9d18bb7f
--- /dev/null
+++ b/arch/ppc/syslib/ipic.h
@@ -0,0 +1,47 @@
1/*
2 * IPIC private definitions and structure.
3 *
4 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
5 *
6 * Copyright 2005 Freescale Semiconductor, Inc
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#ifndef __IPIC_H__
14#define __IPIC_H__
15
16#include <asm/ipic.h>
17
18#define MPC83xx_IPIC_SIZE (0x00100)
19
20/* System Global Interrupt Configuration Register */
21#define SICFR_IPSA 0x00010000
22#define SICFR_IPSD 0x00080000
23#define SICFR_MPSA 0x00200000
24#define SICFR_MPSB 0x00400000
25
26/* System External Interrupt Mask Register */
27#define SEMSR_SIRQ0 0x00008000
28
29/* System Error Control Register */
30#define SERCR_MCPR 0x00000001
31
32struct ipic {
33 volatile u32 __iomem *regs;
34 unsigned int irq_offset;
35};
36
37struct ipic_info {
38 u8 pend; /* pending register offset from base */
39 u8 mask; /* mask register offset from base */
40 u8 prio; /* priority register offset from base */
41 u8 force; /* force register offset from base */
42 u8 bit; /* register bit position (as per doc)
43 bit mask = 1 << (31 - bit) */
44 u8 prio_mask; /* priority mask value */
45};
46
47#endif /* __IPIC_H__ */
diff --git a/arch/s390/lib/uaccess.S b/arch/s390/lib/uaccess.S
index 5d59e2625048..837275284d9f 100644
--- a/arch/s390/lib/uaccess.S
+++ b/arch/s390/lib/uaccess.S
@@ -88,30 +88,31 @@ __copy_to_user_asm:
88 .globl __copy_in_user_asm 88 .globl __copy_in_user_asm
89 # %r2 = from, %r3 = n, %r4 = to 89 # %r2 = from, %r3 = n, %r4 = to
90__copy_in_user_asm: 90__copy_in_user_asm:
91 ahi %r3,-1
92 jo 6f
91 sacf 256 93 sacf 256
92 bras 1,1f 94 bras %r1,4f
93 mvc 0(1,%r4),0(%r2) 950: ahi %r3,257
940: mvc 0(256,%r4),0(%r2) 961: mvc 0(1,%r4),0(%r2)
95 la %r2,256(%r2)
96 la %r4,256(%r4)
971: ahi %r3,-256
98 jnm 0b
992: ex %r3,0(%r1)
100 sacf 0
101 slr %r2,%r2
102 br 14
1033: mvc 0(1,%r4),0(%r2)
104 la %r2,1(%r2) 97 la %r2,1(%r2)
105 la %r4,1(%r4) 98 la %r4,1(%r4)
106 ahi %r3,-1 99 ahi %r3,-1
100 jnz 1b
1012: lr %r2,%r3
102 br %r14
1033: mvc 0(256,%r4),0(%r2)
104 la %r2,256(%r2)
105 la %r4,256(%r4)
1064: ahi %r3,-256
107 jnm 3b 107 jnm 3b
1084: lr %r2,%r3 1085: ex %r3,4(%r1)
109 sacf 0 109 sacf 0
1106: slr %r2,%r2
110 br %r14 111 br %r14
111 .section __ex_table,"a" 112 .section __ex_table,"a"
112 .long 0b,3b 113 .long 1b,2b
113 .long 2b,3b 114 .long 3b,0b
114 .long 3b,4b 115 .long 5b,0b
115 .previous 116 .previous
116 117
117 .align 4 118 .align 4
diff --git a/arch/s390/lib/uaccess64.S b/arch/s390/lib/uaccess64.S
index 19b41a33c230..1f755be22f92 100644
--- a/arch/s390/lib/uaccess64.S
+++ b/arch/s390/lib/uaccess64.S
@@ -88,30 +88,31 @@ __copy_to_user_asm:
88 .globl __copy_in_user_asm 88 .globl __copy_in_user_asm
89 # %r2 = from, %r3 = n, %r4 = to 89 # %r2 = from, %r3 = n, %r4 = to
90__copy_in_user_asm: 90__copy_in_user_asm:
91 aghi %r3,-1
92 jo 6f
91 sacf 256 93 sacf 256
92 bras 1,1f 94 bras %r1,4f
93 mvc 0(1,%r4),0(%r2) 950: aghi %r3,257
940: mvc 0(256,%r4),0(%r2) 961: mvc 0(1,%r4),0(%r2)
95 la %r2,256(%r2)
96 la %r4,256(%r4)
971: aghi %r3,-256
98 jnm 0b
992: ex %r3,0(%r1)
100 sacf 0
101 slgr %r2,%r2
102 br 14
1033: mvc 0(1,%r4),0(%r2)
104 la %r2,1(%r2) 97 la %r2,1(%r2)
105 la %r4,1(%r4) 98 la %r4,1(%r4)
106 aghi %r3,-1 99 aghi %r3,-1
100 jnz 1b
1012: lgr %r2,%r3
102 br %r14
1033: mvc 0(256,%r4),0(%r2)
104 la %r2,256(%r2)
105 la %r4,256(%r4)
1064: aghi %r3,-256
107 jnm 3b 107 jnm 3b
1084: lgr %r2,%r3 1085: ex %r3,4(%r1)
109 sacf 0 109 sacf 0
110 br %r14 1106: slgr %r2,%r2
111 br 14
111 .section __ex_table,"a" 112 .section __ex_table,"a"
112 .quad 0b,3b 113 .quad 1b,2b
113 .quad 2b,3b 114 .quad 3b,0b
114 .quad 3b,4b 115 .quad 5b,0b
115 .previous 116 .previous
116 117
117 .align 4 118 .align 4
diff --git a/arch/sparc64/mm/generic.c b/arch/sparc64/mm/generic.c
index 8cb06205d265..af9d81db0b38 100644
--- a/arch/sparc64/mm/generic.c
+++ b/arch/sparc64/mm/generic.c
@@ -69,6 +69,8 @@ static inline void io_remap_pte_range(struct mm_struct *mm, pte_t * pte,
69 } else 69 } else
70 offset += PAGE_SIZE; 70 offset += PAGE_SIZE;
71 71
72 if (pte_write(entry))
73 entry = pte_mkdirty(entry);
72 do { 74 do {
73 BUG_ON(!pte_none(*pte)); 75 BUG_ON(!pte_none(*pte));
74 set_pte_at(mm, address, pte, entry); 76 set_pte_at(mm, address, pte, entry);
diff --git a/arch/x86_64/defconfig b/arch/x86_64/defconfig
index 840d5d93d5cc..5fb970715941 100644
--- a/arch/x86_64/defconfig
+++ b/arch/x86_64/defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.18-rc2 3# Linux kernel version: 2.6.18-rc4
4# Tue Jul 18 17:13:20 2006 4# Thu Aug 24 21:05:55 2006
5# 5#
6CONFIG_X86_64=y 6CONFIG_X86_64=y
7CONFIG_64BIT=y 7CONFIG_64BIT=y
@@ -201,7 +201,7 @@ CONFIG_ACPI_THERMAL=y
201CONFIG_ACPI_NUMA=y 201CONFIG_ACPI_NUMA=y
202# CONFIG_ACPI_ASUS is not set 202# CONFIG_ACPI_ASUS is not set
203# CONFIG_ACPI_IBM is not set 203# CONFIG_ACPI_IBM is not set
204CONFIG_ACPI_TOSHIBA=y 204# CONFIG_ACPI_TOSHIBA is not set
205CONFIG_ACPI_BLACKLIST_YEAR=0 205CONFIG_ACPI_BLACKLIST_YEAR=0
206# CONFIG_ACPI_DEBUG is not set 206# CONFIG_ACPI_DEBUG is not set
207CONFIG_ACPI_EC=y 207CONFIG_ACPI_EC=y
@@ -216,7 +216,7 @@ CONFIG_ACPI_CONTAINER=y
216# 216#
217CONFIG_CPU_FREQ=y 217CONFIG_CPU_FREQ=y
218CONFIG_CPU_FREQ_TABLE=y 218CONFIG_CPU_FREQ_TABLE=y
219# CONFIG_CPU_FREQ_DEBUG is not set 219CONFIG_CPU_FREQ_DEBUG=y
220CONFIG_CPU_FREQ_STAT=y 220CONFIG_CPU_FREQ_STAT=y
221# CONFIG_CPU_FREQ_STAT_DETAILS is not set 221# CONFIG_CPU_FREQ_STAT_DETAILS is not set
222CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y 222CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
@@ -495,8 +495,9 @@ CONFIG_SCSI=y
495CONFIG_BLK_DEV_SD=y 495CONFIG_BLK_DEV_SD=y
496# CONFIG_CHR_DEV_ST is not set 496# CONFIG_CHR_DEV_ST is not set
497# CONFIG_CHR_DEV_OSST is not set 497# CONFIG_CHR_DEV_OSST is not set
498# CONFIG_BLK_DEV_SR is not set 498CONFIG_BLK_DEV_SR=y
499# CONFIG_CHR_DEV_SG is not set 499# CONFIG_BLK_DEV_SR_VENDOR is not set
500CONFIG_CHR_DEV_SG=y
500# CONFIG_CHR_DEV_SCH is not set 501# CONFIG_CHR_DEV_SCH is not set
501 502
502# 503#
@@ -512,7 +513,7 @@ CONFIG_SCSI_CONSTANTS=y
512CONFIG_SCSI_SPI_ATTRS=y 513CONFIG_SCSI_SPI_ATTRS=y
513CONFIG_SCSI_FC_ATTRS=y 514CONFIG_SCSI_FC_ATTRS=y
514# CONFIG_SCSI_ISCSI_ATTRS is not set 515# CONFIG_SCSI_ISCSI_ATTRS is not set
515# CONFIG_SCSI_SAS_ATTRS is not set 516CONFIG_SCSI_SAS_ATTRS=y
516 517
517# 518#
518# SCSI low-level drivers 519# SCSI low-level drivers
@@ -538,7 +539,7 @@ CONFIG_MEGARAID_MAILBOX=y
538CONFIG_MEGARAID_SAS=y 539CONFIG_MEGARAID_SAS=y
539CONFIG_SCSI_SATA=y 540CONFIG_SCSI_SATA=y
540CONFIG_SCSI_SATA_AHCI=y 541CONFIG_SCSI_SATA_AHCI=y
541# CONFIG_SCSI_SATA_SVW is not set 542CONFIG_SCSI_SATA_SVW=y
542CONFIG_SCSI_ATA_PIIX=y 543CONFIG_SCSI_ATA_PIIX=y
543# CONFIG_SCSI_SATA_MV is not set 544# CONFIG_SCSI_SATA_MV is not set
544CONFIG_SCSI_SATA_NV=y 545CONFIG_SCSI_SATA_NV=y
@@ -589,7 +590,7 @@ CONFIG_BLK_DEV_DM=y
589CONFIG_FUSION=y 590CONFIG_FUSION=y
590CONFIG_FUSION_SPI=y 591CONFIG_FUSION_SPI=y
591# CONFIG_FUSION_FC is not set 592# CONFIG_FUSION_FC is not set
592# CONFIG_FUSION_SAS is not set 593CONFIG_FUSION_SAS=y
593CONFIG_FUSION_MAX_SGE=128 594CONFIG_FUSION_MAX_SGE=128
594# CONFIG_FUSION_CTL is not set 595# CONFIG_FUSION_CTL is not set
595 596
@@ -675,7 +676,7 @@ CONFIG_NET_PCI=y
675# CONFIG_PCNET32 is not set 676# CONFIG_PCNET32 is not set
676# CONFIG_AMD8111_ETH is not set 677# CONFIG_AMD8111_ETH is not set
677# CONFIG_ADAPTEC_STARFIRE is not set 678# CONFIG_ADAPTEC_STARFIRE is not set
678# CONFIG_B44 is not set 679CONFIG_B44=y
679CONFIG_FORCEDETH=y 680CONFIG_FORCEDETH=y
680# CONFIG_DGRS is not set 681# CONFIG_DGRS is not set
681# CONFIG_EEPRO100 is not set 682# CONFIG_EEPRO100 is not set
@@ -712,7 +713,7 @@ CONFIG_E1000=y
712# CONFIG_SK98LIN is not set 713# CONFIG_SK98LIN is not set
713# CONFIG_VIA_VELOCITY is not set 714# CONFIG_VIA_VELOCITY is not set
714CONFIG_TIGON3=y 715CONFIG_TIGON3=y
715# CONFIG_BNX2 is not set 716CONFIG_BNX2=y
716 717
717# 718#
718# Ethernet (10000 Mbit) 719# Ethernet (10000 Mbit)
@@ -842,44 +843,7 @@ CONFIG_LEGACY_PTY_COUNT=256
842# 843#
843# Watchdog Cards 844# Watchdog Cards
844# 845#
845CONFIG_WATCHDOG=y 846# CONFIG_WATCHDOG is not set
846# CONFIG_WATCHDOG_NOWAYOUT is not set
847
848#
849# Watchdog Device Drivers
850#
851CONFIG_SOFT_WATCHDOG=y
852# CONFIG_ACQUIRE_WDT is not set
853# CONFIG_ADVANTECH_WDT is not set
854# CONFIG_ALIM1535_WDT is not set
855# CONFIG_ALIM7101_WDT is not set
856# CONFIG_SC520_WDT is not set
857# CONFIG_EUROTECH_WDT is not set
858# CONFIG_IB700_WDT is not set
859# CONFIG_IBMASR is not set
860# CONFIG_WAFER_WDT is not set
861# CONFIG_I6300ESB_WDT is not set
862# CONFIG_I8XX_TCO is not set
863# CONFIG_SC1200_WDT is not set
864# CONFIG_60XX_WDT is not set
865# CONFIG_SBC8360_WDT is not set
866# CONFIG_CPU5_WDT is not set
867# CONFIG_W83627HF_WDT is not set
868# CONFIG_W83877F_WDT is not set
869# CONFIG_W83977F_WDT is not set
870# CONFIG_MACHZ_WDT is not set
871# CONFIG_SBC_EPX_C3_WATCHDOG is not set
872
873#
874# PCI-based Watchdog Cards
875#
876# CONFIG_PCIPCWATCHDOG is not set
877# CONFIG_WDTPCI is not set
878
879#
880# USB-based Watchdog Cards
881#
882# CONFIG_USBPCWATCHDOG is not set
883CONFIG_HW_RANDOM=y 847CONFIG_HW_RANDOM=y
884CONFIG_HW_RANDOM_INTEL=y 848CONFIG_HW_RANDOM_INTEL=y
885CONFIG_HW_RANDOM_AMD=y 849CONFIG_HW_RANDOM_AMD=y
@@ -1056,6 +1020,7 @@ CONFIG_VGACON_SOFT_SCROLLBACK=y
1056CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=256 1020CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=256
1057CONFIG_VIDEO_SELECT=y 1021CONFIG_VIDEO_SELECT=y
1058CONFIG_DUMMY_CONSOLE=y 1022CONFIG_DUMMY_CONSOLE=y
1023# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1059 1024
1060# 1025#
1061# Sound 1026# Sound
@@ -1301,7 +1266,7 @@ CONFIG_INOTIFY=y
1301CONFIG_INOTIFY_USER=y 1266CONFIG_INOTIFY_USER=y
1302# CONFIG_QUOTA is not set 1267# CONFIG_QUOTA is not set
1303CONFIG_DNOTIFY=y 1268CONFIG_DNOTIFY=y
1304CONFIG_AUTOFS_FS=y 1269# CONFIG_AUTOFS_FS is not set
1305CONFIG_AUTOFS4_FS=y 1270CONFIG_AUTOFS4_FS=y
1306# CONFIG_FUSE_FS is not set 1271# CONFIG_FUSE_FS is not set
1307 1272
@@ -1494,4 +1459,5 @@ CONFIG_DEBUG_STACKOVERFLOW=y
1494# CONFIG_CRC16 is not set 1459# CONFIG_CRC16 is not set
1495CONFIG_CRC32=y 1460CONFIG_CRC32=y
1496# CONFIG_LIBCRC32C is not set 1461# CONFIG_LIBCRC32C is not set
1462CONFIG_ZLIB_INFLATE=y
1497CONFIG_PLIST=y 1463CONFIG_PLIST=y
diff --git a/arch/x86_64/ia32/ia32_binfmt.c b/arch/x86_64/ia32/ia32_binfmt.c
index a9dc0f3b5b51..2fd5a67fd435 100644
--- a/arch/x86_64/ia32/ia32_binfmt.c
+++ b/arch/x86_64/ia32/ia32_binfmt.c
@@ -73,39 +73,44 @@ typedef elf_greg_t elf_gregset_t[ELF_NGREG];
73 * Dumping its extra ELF program headers includes all the other information 73 * Dumping its extra ELF program headers includes all the other information
74 * a debugger needs to easily find how the vsyscall DSO was being used. 74 * a debugger needs to easily find how the vsyscall DSO was being used.
75 */ 75 */
76#define ELF_CORE_EXTRA_PHDRS (VSYSCALL32_EHDR->e_phnum) 76#define ELF_CORE_EXTRA_PHDRS (find_vma(current->mm, VSYSCALL32_BASE) ? \
77 (VSYSCALL32_EHDR->e_phnum) : 0)
77#define ELF_CORE_WRITE_EXTRA_PHDRS \ 78#define ELF_CORE_WRITE_EXTRA_PHDRS \
78do { \ 79do { \
79 const struct elf32_phdr *const vsyscall_phdrs = \ 80 if (find_vma(current->mm, VSYSCALL32_BASE)) { \
80 (const struct elf32_phdr *) (VSYSCALL32_BASE \ 81 const struct elf32_phdr *const vsyscall_phdrs = \
81 + VSYSCALL32_EHDR->e_phoff); \ 82 (const struct elf32_phdr *) (VSYSCALL32_BASE \
82 int i; \ 83 + VSYSCALL32_EHDR->e_phoff);\
83 Elf32_Off ofs = 0; \ 84 int i; \
84 for (i = 0; i < VSYSCALL32_EHDR->e_phnum; ++i) { \ 85 Elf32_Off ofs = 0; \
85 struct elf32_phdr phdr = vsyscall_phdrs[i]; \ 86 for (i = 0; i < VSYSCALL32_EHDR->e_phnum; ++i) { \
86 if (phdr.p_type == PT_LOAD) { \ 87 struct elf32_phdr phdr = vsyscall_phdrs[i]; \
87 BUG_ON(ofs != 0); \ 88 if (phdr.p_type == PT_LOAD) { \
88 ofs = phdr.p_offset = offset; \ 89 BUG_ON(ofs != 0); \
89 phdr.p_memsz = PAGE_ALIGN(phdr.p_memsz); \ 90 ofs = phdr.p_offset = offset; \
90 phdr.p_filesz = phdr.p_memsz; \ 91 phdr.p_memsz = PAGE_ALIGN(phdr.p_memsz); \
91 offset += phdr.p_filesz; \ 92 phdr.p_filesz = phdr.p_memsz; \
93 offset += phdr.p_filesz; \
94 } \
95 else \
96 phdr.p_offset += ofs; \
97 phdr.p_paddr = 0; /* match other core phdrs */ \
98 DUMP_WRITE(&phdr, sizeof(phdr)); \
92 } \ 99 } \
93 else \
94 phdr.p_offset += ofs; \
95 phdr.p_paddr = 0; /* match other core phdrs */ \
96 DUMP_WRITE(&phdr, sizeof(phdr)); \
97 } \ 100 } \
98} while (0) 101} while (0)
99#define ELF_CORE_WRITE_EXTRA_DATA \ 102#define ELF_CORE_WRITE_EXTRA_DATA \
100do { \ 103do { \
101 const struct elf32_phdr *const vsyscall_phdrs = \ 104 if (find_vma(current->mm, VSYSCALL32_BASE)) { \
102 (const struct elf32_phdr *) (VSYSCALL32_BASE \ 105 const struct elf32_phdr *const vsyscall_phdrs = \
103 + VSYSCALL32_EHDR->e_phoff); \ 106 (const struct elf32_phdr *) (VSYSCALL32_BASE \
104 int i; \ 107 + VSYSCALL32_EHDR->e_phoff); \
105 for (i = 0; i < VSYSCALL32_EHDR->e_phnum; ++i) { \ 108 int i; \
106 if (vsyscall_phdrs[i].p_type == PT_LOAD) \ 109 for (i = 0; i < VSYSCALL32_EHDR->e_phnum; ++i) { \
107 DUMP_WRITE((void *) (u64) vsyscall_phdrs[i].p_vaddr, \ 110 if (vsyscall_phdrs[i].p_type == PT_LOAD) \
108 PAGE_ALIGN(vsyscall_phdrs[i].p_memsz)); \ 111 DUMP_WRITE((void *) (u64) vsyscall_phdrs[i].p_vaddr,\
112 PAGE_ALIGN(vsyscall_phdrs[i].p_memsz)); \
113 } \
109 } \ 114 } \
110} while (0) 115} while (0)
111 116
diff --git a/arch/x86_64/kernel/e820.c b/arch/x86_64/kernel/e820.c
index e56c2adf57a4..764bf23c7103 100644
--- a/arch/x86_64/kernel/e820.c
+++ b/arch/x86_64/kernel/e820.c
@@ -71,7 +71,11 @@ static inline int bad_addr(unsigned long *addrp, unsigned long size)
71#endif 71#endif
72 /* kernel code + 640k memory hole (later should not be needed, but 72 /* kernel code + 640k memory hole (later should not be needed, but
73 be paranoid for now) */ 73 be paranoid for now) */
74 if (last >= 640*1024 && addr < __pa_symbol(&_end)) { 74 if (last >= 640*1024 && addr < 1024*1024) {
75 *addrp = 1024*1024;
76 return 1;
77 }
78 if (last >= __pa_symbol(&_text) && last < __pa_symbol(&_end)) {
75 *addrp = __pa_symbol(&_end); 79 *addrp = __pa_symbol(&_end);
76 return 1; 80 return 1;
77 } 81 }
@@ -104,35 +108,6 @@ e820_any_mapped(unsigned long start, unsigned long end, unsigned type)
104 return 0; 108 return 0;
105} 109}
106 110
107/*
108 * This function checks if the entire range <start,end> is mapped with type.
109 *
110 * Note: this function only works correct if the e820 table is sorted and
111 * not-overlapping, which is the case
112 */
113int __init e820_all_mapped(unsigned long start, unsigned long end, unsigned type)
114{
115 int i;
116 for (i = 0; i < e820.nr_map; i++) {
117 struct e820entry *ei = &e820.map[i];
118 if (type && ei->type != type)
119 continue;
120 /* is the region (part) in overlap with the current region ?*/
121 if (ei->addr >= end || ei->addr + ei->size <= start)
122 continue;
123
124 /* if the region is at the beginning of <start,end> we move
125 * start to the end of the region since it's ok until there
126 */
127 if (ei->addr <= start)
128 start = ei->addr + ei->size;
129 /* if start is now at or beyond end, we're done, full coverage */
130 if (start >= end)
131 return 1; /* we're done */
132 }
133 return 0;
134}
135
136/* 111/*
137 * Find a free area in a specific range. 112 * Find a free area in a specific range.
138 */ 113 */
diff --git a/arch/x86_64/kernel/entry.S b/arch/x86_64/kernel/entry.S
index 6f810424df44..aa8d8939abc1 100644
--- a/arch/x86_64/kernel/entry.S
+++ b/arch/x86_64/kernel/entry.S
@@ -973,6 +973,8 @@ ENTRY(kernel_thread)
973ENDPROC(kernel_thread) 973ENDPROC(kernel_thread)
974 974
975child_rip: 975child_rip:
976 pushq $0 # fake return address
977 CFI_STARTPROC
976 /* 978 /*
977 * Here we are in the child and the registers are set as they were 979 * Here we are in the child and the registers are set as they were
978 * at kernel_thread() invocation in the parent. 980 * at kernel_thread() invocation in the parent.
@@ -983,6 +985,7 @@ child_rip:
983 # exit 985 # exit
984 xorl %edi, %edi 986 xorl %edi, %edi
985 call do_exit 987 call do_exit
988 CFI_ENDPROC
986ENDPROC(child_rip) 989ENDPROC(child_rip)
987 990
988/* 991/*
diff --git a/arch/x86_64/kernel/head.S b/arch/x86_64/kernel/head.S
index 6df05e6034fa..c9739ca81d06 100644
--- a/arch/x86_64/kernel/head.S
+++ b/arch/x86_64/kernel/head.S
@@ -191,6 +191,7 @@ startup_64:
191 * jump 191 * jump
192 */ 192 */
193 movq initial_code(%rip),%rax 193 movq initial_code(%rip),%rax
194 pushq $0 # fake return address
194 jmp *%rax 195 jmp *%rax
195 196
196 /* SMP bootup changes these two */ 197 /* SMP bootup changes these two */
diff --git a/arch/x86_64/kernel/init_task.c b/arch/x86_64/kernel/init_task.c
index ce31d904d601..3dc5854ba21e 100644
--- a/arch/x86_64/kernel/init_task.c
+++ b/arch/x86_64/kernel/init_task.c
@@ -46,4 +46,9 @@ EXPORT_SYMBOL(init_task);
46 */ 46 */
47DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS; 47DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;
48 48
49/* Copies of the original ist values from the tss are only accessed during
50 * debugging, no special alignment required.
51 */
52DEFINE_PER_CPU(struct orig_ist, orig_ist);
53
49#define ALIGN_TO_4K __attribute__((section(".data.init_task"))) 54#define ALIGN_TO_4K __attribute__((section(".data.init_task")))
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 8a099ff1f8bc..34afad704824 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -521,8 +521,6 @@ static void discover_ebda(void)
521 521
522void __init setup_arch(char **cmdline_p) 522void __init setup_arch(char **cmdline_p)
523{ 523{
524 unsigned long kernel_end;
525
526 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV); 524 ROOT_DEV = old_decode_dev(ORIG_ROOT_DEV);
527 screen_info = SCREEN_INFO; 525 screen_info = SCREEN_INFO;
528 edid_info = EDID_INFO; 526 edid_info = EDID_INFO;
@@ -596,8 +594,8 @@ void __init setup_arch(char **cmdline_p)
596 (table_end - table_start) << PAGE_SHIFT); 594 (table_end - table_start) << PAGE_SHIFT);
597 595
598 /* reserve kernel */ 596 /* reserve kernel */
599 kernel_end = round_up(__pa_symbol(&_end),PAGE_SIZE); 597 reserve_bootmem_generic(__pa_symbol(&_text),
600 reserve_bootmem_generic(HIGH_MEMORY, kernel_end - HIGH_MEMORY); 598 __pa_symbol(&_end) - __pa_symbol(&_text));
601 599
602 /* 600 /*
603 * reserve physical page 0 - it's a special BIOS page on many boxes, 601 * reserve physical page 0 - it's a special BIOS page on many boxes,
diff --git a/arch/x86_64/kernel/setup64.c b/arch/x86_64/kernel/setup64.c
index 6fe58a634b5f..417de564456e 100644
--- a/arch/x86_64/kernel/setup64.c
+++ b/arch/x86_64/kernel/setup64.c
@@ -189,6 +189,7 @@ void __cpuinit cpu_init (void)
189{ 189{
190 int cpu = stack_smp_processor_id(); 190 int cpu = stack_smp_processor_id();
191 struct tss_struct *t = &per_cpu(init_tss, cpu); 191 struct tss_struct *t = &per_cpu(init_tss, cpu);
192 struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
192 unsigned long v; 193 unsigned long v;
193 char *estacks = NULL; 194 char *estacks = NULL;
194 struct task_struct *me; 195 struct task_struct *me;
@@ -256,7 +257,7 @@ void __cpuinit cpu_init (void)
256 estacks += EXCEPTION_STKSZ; 257 estacks += EXCEPTION_STKSZ;
257 break; 258 break;
258 } 259 }
259 t->ist[v] = (unsigned long)estacks; 260 orig_ist->ist[v] = t->ist[v] = (unsigned long)estacks;
260 } 261 }
261 262
262 t->io_bitmap_base = offsetof(struct tss_struct, io_bitmap); 263 t->io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
diff --git a/arch/x86_64/kernel/traps.c b/arch/x86_64/kernel/traps.c
index 14052f089814..b1249774d1e8 100644
--- a/arch/x86_64/kernel/traps.c
+++ b/arch/x86_64/kernel/traps.c
@@ -107,7 +107,11 @@ static inline void preempt_conditional_cli(struct pt_regs *regs)
107} 107}
108 108
109static int kstack_depth_to_print = 12; 109static int kstack_depth_to_print = 12;
110#ifdef CONFIG_STACK_UNWIND
110static int call_trace = 1; 111static int call_trace = 1;
112#else
113#define call_trace (-1)
114#endif
111 115
112#ifdef CONFIG_KALLSYMS 116#ifdef CONFIG_KALLSYMS
113# include <linux/kallsyms.h> 117# include <linux/kallsyms.h>
@@ -174,7 +178,7 @@ static unsigned long *in_exception_stack(unsigned cpu, unsigned long stack,
174 break; 178 break;
175#endif 179#endif
176 default: 180 default:
177 end = per_cpu(init_tss, cpu).ist[k]; 181 end = per_cpu(orig_ist, cpu).ist[k];
178 break; 182 break;
179 } 183 }
180 /* 184 /*
@@ -274,21 +278,21 @@ void show_trace(struct task_struct *tsk, struct pt_regs *regs, unsigned long * s
274 if (unwind_init_blocked(&info, tsk) == 0) 278 if (unwind_init_blocked(&info, tsk) == 0)
275 unw_ret = show_trace_unwind(&info, NULL); 279 unw_ret = show_trace_unwind(&info, NULL);
276 } 280 }
277 if (unw_ret > 0 && !arch_unw_user_mode(&info)) { 281 if (unw_ret > 0) {
278#ifdef CONFIG_STACK_UNWIND 282 if (call_trace == 1 && !arch_unw_user_mode(&info)) {
279 unsigned long rip = info.regs.rip; 283 print_symbol("DWARF2 unwinder stuck at %s\n",
280 print_symbol("DWARF2 unwinder stuck at %s\n", rip); 284 UNW_PC(&info));
281 if (call_trace == 1) { 285 if ((long)UNW_SP(&info) < 0) {
282 printk("Leftover inexact backtrace:\n"); 286 printk("Leftover inexact backtrace:\n");
283 stack = (unsigned long *)info.regs.rsp; 287 stack = (unsigned long *)UNW_SP(&info);
284 } else if (call_trace > 1) 288 } else
289 printk("Full inexact backtrace again:\n");
290 } else if (call_trace >= 1)
285 return; 291 return;
286 else 292 else
287 printk("Full inexact backtrace again:\n"); 293 printk("Full inexact backtrace again:\n");
288#else 294 } else
289 printk("Inexact backtrace:\n"); 295 printk("Inexact backtrace:\n");
290#endif
291 }
292 } 296 }
293 297
294 /* 298 /*
@@ -1120,6 +1124,7 @@ static int __init kstack_setup(char *s)
1120} 1124}
1121__setup("kstack=", kstack_setup); 1125__setup("kstack=", kstack_setup);
1122 1126
1127#ifdef CONFIG_STACK_UNWIND
1123static int __init call_trace_setup(char *s) 1128static int __init call_trace_setup(char *s)
1124{ 1129{
1125 if (strcmp(s, "old") == 0) 1130 if (strcmp(s, "old") == 0)
@@ -1133,3 +1138,4 @@ static int __init call_trace_setup(char *s)
1133 return 1; 1138 return 1;
1134} 1139}
1135__setup("call_trace=", call_trace_setup); 1140__setup("call_trace=", call_trace_setup);
1141#endif
diff --git a/arch/x86_64/pci/mmconfig.c b/arch/x86_64/pci/mmconfig.c
index 3c55c76c6fd5..2d48a7941d48 100644
--- a/arch/x86_64/pci/mmconfig.c
+++ b/arch/x86_64/pci/mmconfig.c
@@ -9,6 +9,7 @@
9#include <linux/init.h> 9#include <linux/init.h>
10#include <linux/acpi.h> 10#include <linux/acpi.h>
11#include <linux/bitmap.h> 11#include <linux/bitmap.h>
12#include <linux/dmi.h>
12#include <asm/e820.h> 13#include <asm/e820.h>
13 14
14#include "pci.h" 15#include "pci.h"
@@ -164,11 +165,33 @@ static __init void unreachable_devices(void)
164 } 165 }
165} 166}
166 167
168static int disable_mcfg(struct dmi_system_id *d)
169{
170 printk("PCI: %s detected. Disabling MCFG.\n", d->ident);
171 pci_probe &= ~PCI_PROBE_MMCONF;
172 return 0;
173}
174
175static struct dmi_system_id __initdata dmi_bad_mcfg[] = {
176 /* Has broken MCFG table that makes the system hang when used */
177 {
178 .callback = disable_mcfg,
179 .ident = "Intel D3C5105 SDV",
180 .matches = {
181 DMI_MATCH(DMI_BIOS_VENDOR, "Intel"),
182 DMI_MATCH(DMI_BOARD_NAME, "D26928"),
183 },
184 },
185 {}
186};
187
167void __init pci_mmcfg_init(void) 188void __init pci_mmcfg_init(void)
168{ 189{
169 int i; 190 int i;
170 191
171 if ((pci_probe & PCI_PROBE_MMCONF) == 0) 192 dmi_check_system(dmi_bad_mcfg);
193
194 if ((pci_probe & (PCI_PROBE_MMCONF|PCI_PROBE_MMCONF_FORCE)) == 0)
172 return; 195 return;
173 196
174 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg); 197 acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
@@ -177,15 +200,6 @@ void __init pci_mmcfg_init(void)
177 (pci_mmcfg_config[0].base_address == 0)) 200 (pci_mmcfg_config[0].base_address == 0))
178 return; 201 return;
179 202
180 if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
181 pci_mmcfg_config[0].base_address + MMCONFIG_APER_MIN,
182 E820_RESERVED)) {
183 printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %x is not E820-reserved\n",
184 pci_mmcfg_config[0].base_address);
185 printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
186 return;
187 }
188
189 /* RED-PEN i386 doesn't do _nocache right now */ 203 /* RED-PEN i386 doesn't do _nocache right now */
190 pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL); 204 pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) * pci_mmcfg_config_num, GFP_KERNEL);
191 if (pci_mmcfg_virt == NULL) { 205 if (pci_mmcfg_virt == NULL) {
diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c
index 5064d9383963..9aea23cc0dc5 100644
--- a/arch/xtensa/kernel/ptrace.c
+++ b/arch/xtensa/kernel/ptrace.c
@@ -212,7 +212,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
212 */ 212 */
213 case PTRACE_KILL: 213 case PTRACE_KILL:
214 ret = 0; 214 ret = 0;
215 if (child->state == EXIT_ZOMBIE) /* already dead */ 215 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
216 break; 216 break;
217 child->exit_code = SIGKILL; 217 child->exit_code = SIGKILL;
218 child->ptrace &= ~PT_SINGLESTEP; 218 child->ptrace &= ~PT_SINGLESTEP;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 11:23:20 -0500