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-rw-r--r--arch/powerpc/Kconfig29
-rw-r--r--arch/powerpc/Makefile1
-rw-r--r--arch/powerpc/configs/mpc8540_ads_defconfig721
-rw-r--r--arch/powerpc/kernel/head_booke.h363
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig74
-rw-r--r--arch/powerpc/platforms/85xx/Makefile5
-rw-r--r--arch/powerpc/platforms/85xx/mpc8540_ads.h60
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.c31
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx.h17
-rw-r--r--arch/powerpc/platforms/85xx/mpc85xx_ads.c208
-rw-r--r--arch/powerpc/platforms/Makefile2
-rw-r--r--arch/ppc/8xx_io/commproc.c6
-rw-r--r--arch/ppc/mm/44x_mmu.c4
-rw-r--r--arch/ppc/syslib/m8xx_setup.c63
-rw-r--r--arch/ppc/syslib/m8xx_wdt.c3
15 files changed, 1501 insertions, 86 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index df338c5cc910..fb0dcb994b84 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -83,6 +83,12 @@ config GENERIC_TBSYNC
83 default y if PPC32 && SMP 83 default y if PPC32 && SMP
84 default n 84 default n
85 85
86config DEFAULT_UIMAGE
87 bool
88 help
89 Used to allow a board to specify it wants a uImage built by default
90 default n
91
86menu "Processor support" 92menu "Processor support"
87choice 93choice
88 prompt "Processor Type" 94 prompt "Processor Type"
@@ -121,6 +127,12 @@ config PPC_83xx
121 select 83xx 127 select 83xx
122 select PPC_FPU 128 select PPC_FPU
123 129
130config PPC_85xx
131 bool "Freescale 85xx"
132 select E500
133 select FSL_SOC
134 select 85xx
135
124config 40x 136config 40x
125 bool "AMCC 40x" 137 bool "AMCC 40x"
126 138
@@ -133,8 +145,6 @@ config 8xx
133config E200 145config E200
134 bool "Freescale e200" 146 bool "Freescale e200"
135 147
136config E500
137 bool "Freescale e500"
138endchoice 148endchoice
139 149
140config POWER4_ONLY 150config POWER4_ONLY
@@ -162,6 +172,13 @@ config 6xx
162config 83xx 172config 83xx
163 bool 173 bool
164 174
175# this is temp to handle compat with arch=ppc
176config 85xx
177 bool
178
179config E500
180 bool
181
165config PPC_FPU 182config PPC_FPU
166 bool 183 bool
167 default y if PPC64 184 default y if PPC64
@@ -211,6 +228,7 @@ config ALTIVEC
211config SPE 228config SPE
212 bool "SPE Support" 229 bool "SPE Support"
213 depends on E200 || E500 230 depends on E200 || E500
231 default y
214 ---help--- 232 ---help---
215 This option enables kernel support for the Signal Processing 233 This option enables kernel support for the Signal Processing
216 Extensions (SPE) to the PowerPC processor. The kernel currently 234 Extensions (SPE) to the PowerPC processor. The kernel currently
@@ -728,13 +746,12 @@ config GENERIC_ISA_DMA
728 746
729config PPC_I8259 747config PPC_I8259
730 bool 748 bool
731 default y if 85xx
732 default n 749 default n
733 750
734config PPC_INDIRECT_PCI 751config PPC_INDIRECT_PCI
735 bool 752 bool
736 depends on PCI 753 depends on PCI
737 default y if 40x || 44x || 85xx 754 default y if 40x || 44x
738 default n 755 default n
739 756
740config EISA 757config EISA
@@ -751,8 +768,8 @@ config MCA
751 bool 768 bool
752 769
753config PCI 770config PCI
754 bool "PCI support" if 40x || CPM2 || PPC_83xx || 85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES) 771 bool "PCI support" if 40x || CPM2 || PPC_83xx || PPC_85xx || PPC_MPC52xx || (EMBEDDED && PPC_ISERIES)
755 default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !85xx 772 default y if !40x && !CPM2 && !8xx && !APUS && !PPC_83xx && !PPC_85xx
756 default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS 773 default PCI_PERMEDIA if !4xx && !CPM2 && !8xx && APUS
757 default PCI_QSPAN if !4xx && !CPM2 && 8xx 774 default PCI_QSPAN if !4xx && !CPM2 && 8xx
758 help 775 help
diff --git a/arch/powerpc/Makefile b/arch/powerpc/Makefile
index 44dd82b791d1..15fc3e98ac5c 100644
--- a/arch/powerpc/Makefile
+++ b/arch/powerpc/Makefile
@@ -142,6 +142,7 @@ drivers-$(CONFIG_OPROFILE) += arch/powerpc/oprofile/
142# Default to zImage, override when needed 142# Default to zImage, override when needed
143defaultimage-y := zImage 143defaultimage-y := zImage
144defaultimage-$(CONFIG_PPC_ISERIES) := vmlinux 144defaultimage-$(CONFIG_PPC_ISERIES) := vmlinux
145defaultimage-$(CONFIG_DEFAULT_UIMAGE) := uImage
145KBUILD_IMAGE := $(defaultimage-y) 146KBUILD_IMAGE := $(defaultimage-y)
146all: $(KBUILD_IMAGE) 147all: $(KBUILD_IMAGE)
147 148
diff --git a/arch/powerpc/configs/mpc8540_ads_defconfig b/arch/powerpc/configs/mpc8540_ads_defconfig
new file mode 100644
index 000000000000..2a8290ee15c6
--- /dev/null
+++ b/arch/powerpc/configs/mpc8540_ads_defconfig
@@ -0,0 +1,721 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version:
4# Sat Jan 14 15:57:54 2006
5#
6# CONFIG_PPC64 is not set
7CONFIG_PPC32=y
8CONFIG_PPC_MERGE=y
9CONFIG_MMU=y
10CONFIG_GENERIC_HARDIRQS=y
11CONFIG_RWSEM_XCHGADD_ALGORITHM=y
12CONFIG_GENERIC_CALIBRATE_DELAY=y
13CONFIG_PPC=y
14CONFIG_EARLY_PRINTK=y
15CONFIG_GENERIC_NVRAM=y
16CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
17CONFIG_ARCH_MAY_HAVE_PC_FDC=y
18CONFIG_PPC_OF=y
19CONFIG_PPC_UDBG_16550=y
20# CONFIG_GENERIC_TBSYNC is not set
21
22#
23# Processor support
24#
25# CONFIG_CLASSIC32 is not set
26# CONFIG_PPC_52xx is not set
27# CONFIG_PPC_82xx is not set
28# CONFIG_PPC_83xx is not set
29CONFIG_PPC_85xx=y
30# CONFIG_40x is not set
31# CONFIG_44x is not set
32# CONFIG_8xx is not set
33# CONFIG_E200 is not set
34CONFIG_85xx=y
35CONFIG_E500=y
36CONFIG_BOOKE=y
37CONFIG_FSL_BOOKE=y
38# CONFIG_PHYS_64BIT is not set
39CONFIG_SPE=y
40
41#
42# Code maturity level options
43#
44CONFIG_EXPERIMENTAL=y
45CONFIG_CLEAN_COMPILE=y
46CONFIG_BROKEN_ON_SMP=y
47CONFIG_INIT_ENV_ARG_LIMIT=32
48
49#
50# General setup
51#
52CONFIG_LOCALVERSION=""
53CONFIG_LOCALVERSION_AUTO=y
54CONFIG_SWAP=y
55CONFIG_SYSVIPC=y
56# CONFIG_POSIX_MQUEUE is not set
57# CONFIG_BSD_PROCESS_ACCT is not set
58CONFIG_SYSCTL=y
59# CONFIG_AUDIT is not set
60# CONFIG_IKCONFIG is not set
61CONFIG_INITRAMFS_SOURCE=""
62# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
63CONFIG_EMBEDDED=y
64CONFIG_KALLSYMS=y
65# CONFIG_KALLSYMS_ALL is not set
66# CONFIG_KALLSYMS_EXTRA_PASS is not set
67CONFIG_HOTPLUG=y
68CONFIG_PRINTK=y
69CONFIG_BUG=y
70CONFIG_ELF_CORE=y
71CONFIG_BASE_FULL=y
72CONFIG_FUTEX=y
73CONFIG_EPOLL=y
74CONFIG_SHMEM=y
75CONFIG_CC_ALIGN_FUNCTIONS=0
76CONFIG_CC_ALIGN_LABELS=0
77CONFIG_CC_ALIGN_LOOPS=0
78CONFIG_CC_ALIGN_JUMPS=0
79CONFIG_SLAB=y
80# CONFIG_TINY_SHMEM is not set
81CONFIG_BASE_SMALL=0
82# CONFIG_SLOB is not set
83
84#
85# Loadable module support
86#
87# CONFIG_MODULES is not set
88
89#
90# Block layer
91#
92# CONFIG_LBD is not set
93
94#
95# IO Schedulers
96#
97CONFIG_IOSCHED_NOOP=y
98CONFIG_IOSCHED_AS=y
99CONFIG_IOSCHED_DEADLINE=y
100CONFIG_IOSCHED_CFQ=y
101CONFIG_DEFAULT_AS=y
102# CONFIG_DEFAULT_DEADLINE is not set
103# CONFIG_DEFAULT_CFQ is not set
104# CONFIG_DEFAULT_NOOP is not set
105CONFIG_DEFAULT_IOSCHED="anticipatory"
106CONFIG_MPIC=y
107# CONFIG_WANT_EARLY_SERIAL is not set
108
109#
110# Platform support
111#
112CONFIG_MPC8540_ADS=y
113CONFIG_MPC8540=y
114CONFIG_PPC_INDIRECT_PCI_BE=y
115
116#
117# Kernel options
118#
119# CONFIG_HIGHMEM is not set
120# CONFIG_HZ_100 is not set
121CONFIG_HZ_250=y
122# CONFIG_HZ_1000 is not set
123CONFIG_HZ=250
124CONFIG_PREEMPT_NONE=y
125# CONFIG_PREEMPT_VOLUNTARY is not set
126# CONFIG_PREEMPT is not set
127CONFIG_BINFMT_ELF=y
128CONFIG_BINFMT_MISC=y
129CONFIG_MATH_EMULATION=y
130CONFIG_ARCH_FLATMEM_ENABLE=y
131CONFIG_SELECT_MEMORY_MODEL=y
132CONFIG_FLATMEM_MANUAL=y
133# CONFIG_DISCONTIGMEM_MANUAL is not set
134# CONFIG_SPARSEMEM_MANUAL is not set
135CONFIG_FLATMEM=y
136CONFIG_FLAT_NODE_MEM_MAP=y
137# CONFIG_SPARSEMEM_STATIC is not set
138CONFIG_SPLIT_PTLOCK_CPUS=4
139CONFIG_PROC_DEVICETREE=y
140# CONFIG_CMDLINE_BOOL is not set
141# CONFIG_PM is not set
142# CONFIG_SOFTWARE_SUSPEND is not set
143# CONFIG_SECCOMP is not set
144CONFIG_ISA_DMA_API=y
145
146#
147# Bus options
148#
149# CONFIG_PPC_I8259 is not set
150CONFIG_PPC_INDIRECT_PCI=y
151CONFIG_FSL_SOC=y
152# CONFIG_PCI is not set
153# CONFIG_PCI_DOMAINS is not set
154
155#
156# PCCARD (PCMCIA/CardBus) support
157#
158# CONFIG_PCCARD is not set
159
160#
161# PCI Hotplug Support
162#
163
164#
165# Advanced setup
166#
167# CONFIG_ADVANCED_OPTIONS is not set
168
169#
170# Default settings for advanced configuration options are used
171#
172CONFIG_HIGHMEM_START=0xfe000000
173CONFIG_LOWMEM_SIZE=0x30000000
174CONFIG_KERNEL_START=0xc0000000
175CONFIG_TASK_SIZE=0x80000000
176CONFIG_BOOT_LOAD=0x00800000
177
178#
179# Networking
180#
181CONFIG_NET=y
182
183#
184# Networking options
185#
186CONFIG_PACKET=y
187# CONFIG_PACKET_MMAP is not set
188CONFIG_UNIX=y
189# CONFIG_NET_KEY is not set
190CONFIG_INET=y
191CONFIG_IP_MULTICAST=y
192# CONFIG_IP_ADVANCED_ROUTER is not set
193CONFIG_IP_FIB_HASH=y
194CONFIG_IP_PNP=y
195CONFIG_IP_PNP_DHCP=y
196CONFIG_IP_PNP_BOOTP=y
197# CONFIG_IP_PNP_RARP is not set
198# CONFIG_NET_IPIP is not set
199# CONFIG_NET_IPGRE is not set
200# CONFIG_IP_MROUTE is not set
201# CONFIG_ARPD is not set
202CONFIG_SYN_COOKIES=y
203# CONFIG_INET_AH is not set
204# CONFIG_INET_ESP is not set
205# CONFIG_INET_IPCOMP is not set
206# CONFIG_INET_TUNNEL is not set
207CONFIG_INET_DIAG=y
208CONFIG_INET_TCP_DIAG=y
209# CONFIG_TCP_CONG_ADVANCED is not set
210CONFIG_TCP_CONG_BIC=y
211# CONFIG_IPV6 is not set
212# CONFIG_NETFILTER is not set
213
214#
215# DCCP Configuration (EXPERIMENTAL)
216#
217# CONFIG_IP_DCCP is not set
218
219#
220# SCTP Configuration (EXPERIMENTAL)
221#
222# CONFIG_IP_SCTP is not set
223# CONFIG_ATM is not set
224# CONFIG_BRIDGE is not set
225# CONFIG_VLAN_8021Q is not set
226# CONFIG_DECNET is not set
227# CONFIG_LLC2 is not set
228# CONFIG_IPX is not set
229# CONFIG_ATALK is not set
230# CONFIG_X25 is not set
231# CONFIG_LAPB is not set
232
233#
234# TIPC Configuration (EXPERIMENTAL)
235#
236# CONFIG_TIPC is not set
237# CONFIG_NET_DIVERT is not set
238# CONFIG_ECONET is not set
239# CONFIG_WAN_ROUTER is not set
240
241#
242# QoS and/or fair queueing
243#
244# CONFIG_NET_SCHED is not set
245
246#
247# Network testing
248#
249# CONFIG_NET_PKTGEN is not set
250# CONFIG_HAMRADIO is not set
251# CONFIG_IRDA is not set
252# CONFIG_BT is not set
253# CONFIG_IEEE80211 is not set
254
255#
256# Device Drivers
257#
258
259#
260# Generic Driver Options
261#
262CONFIG_STANDALONE=y
263CONFIG_PREVENT_FIRMWARE_BUILD=y
264# CONFIG_FW_LOADER is not set
265# CONFIG_DEBUG_DRIVER is not set
266
267#
268# Connector - unified userspace <-> kernelspace linker
269#
270# CONFIG_CONNECTOR is not set
271
272#
273# Memory Technology Devices (MTD)
274#
275# CONFIG_MTD is not set
276
277#
278# Parallel port support
279#
280# CONFIG_PARPORT is not set
281
282#
283# Plug and Play support
284#
285
286#
287# Block devices
288#
289# CONFIG_BLK_DEV_FD is not set
290# CONFIG_BLK_DEV_COW_COMMON is not set
291CONFIG_BLK_DEV_LOOP=y
292# CONFIG_BLK_DEV_CRYPTOLOOP is not set
293# CONFIG_BLK_DEV_NBD is not set
294CONFIG_BLK_DEV_RAM=y
295CONFIG_BLK_DEV_RAM_COUNT=16
296CONFIG_BLK_DEV_RAM_SIZE=32768
297CONFIG_BLK_DEV_INITRD=y
298# CONFIG_CDROM_PKTCDVD is not set
299# CONFIG_ATA_OVER_ETH is not set
300
301#
302# ATA/ATAPI/MFM/RLL support
303#
304# CONFIG_IDE is not set
305
306#
307# SCSI device support
308#
309# CONFIG_RAID_ATTRS is not set
310# CONFIG_SCSI is not set
311
312#
313# Multi-device support (RAID and LVM)
314#
315# CONFIG_MD is not set
316
317#
318# Fusion MPT device support
319#
320# CONFIG_FUSION is not set
321
322#
323# IEEE 1394 (FireWire) support
324#
325
326#
327# I2O device support
328#
329
330#
331# Macintosh device drivers
332#
333# CONFIG_WINDFARM is not set
334
335#
336# Network device support
337#
338CONFIG_NETDEVICES=y
339# CONFIG_DUMMY is not set
340# CONFIG_BONDING is not set
341# CONFIG_EQUALIZER is not set
342# CONFIG_TUN is not set
343
344#
345# PHY device support
346#
347CONFIG_PHYLIB=y
348
349#
350# MII PHY device drivers
351#
352# CONFIG_MARVELL_PHY is not set
353# CONFIG_DAVICOM_PHY is not set
354# CONFIG_QSEMI_PHY is not set
355# CONFIG_LXT_PHY is not set
356# CONFIG_CICADA_PHY is not set
357
358#
359# Ethernet (10 or 100Mbit)
360#
361CONFIG_NET_ETHERNET=y
362CONFIG_MII=y
363
364#
365# Ethernet (1000 Mbit)
366#
367CONFIG_GIANFAR=y
368CONFIG_GFAR_NAPI=y
369
370#
371# Ethernet (10000 Mbit)
372#
373
374#
375# Token Ring devices
376#
377
378#
379# Wireless LAN (non-hamradio)
380#
381# CONFIG_NET_RADIO is not set
382
383#
384# Wan interfaces
385#
386# CONFIG_WAN is not set
387# CONFIG_PPP is not set
388# CONFIG_SLIP is not set
389# CONFIG_SHAPER is not set
390# CONFIG_NETCONSOLE is not set
391# CONFIG_NETPOLL is not set
392# CONFIG_NET_POLL_CONTROLLER is not set
393
394#
395# ISDN subsystem
396#
397# CONFIG_ISDN is not set
398
399#
400# Telephony Support
401#
402# CONFIG_PHONE is not set
403
404#
405# Input device support
406#
407CONFIG_INPUT=y
408
409#
410# Userland interfaces
411#
412# CONFIG_INPUT_MOUSEDEV is not set
413# CONFIG_INPUT_JOYDEV is not set
414# CONFIG_INPUT_TSDEV is not set
415# CONFIG_INPUT_EVDEV is not set
416# CONFIG_INPUT_EVBUG is not set
417
418#
419# Input Device Drivers
420#
421# CONFIG_INPUT_KEYBOARD is not set
422# CONFIG_INPUT_MOUSE is not set
423# CONFIG_INPUT_JOYSTICK is not set
424# CONFIG_INPUT_TOUCHSCREEN is not set
425# CONFIG_INPUT_MISC is not set
426
427#
428# Hardware I/O ports
429#
430# CONFIG_SERIO is not set
431# CONFIG_GAMEPORT is not set
432
433#
434# Character devices
435#
436# CONFIG_VT is not set
437# CONFIG_SERIAL_NONSTANDARD is not set
438
439#
440# Serial drivers
441#
442CONFIG_SERIAL_8250=y
443CONFIG_SERIAL_8250_CONSOLE=y
444CONFIG_SERIAL_8250_NR_UARTS=4
445CONFIG_SERIAL_8250_RUNTIME_UARTS=4
446# CONFIG_SERIAL_8250_EXTENDED is not set
447
448#
449# Non-8250 serial port support
450#
451CONFIG_SERIAL_CORE=y
452CONFIG_SERIAL_CORE_CONSOLE=y
453CONFIG_UNIX98_PTYS=y
454CONFIG_LEGACY_PTYS=y
455CONFIG_LEGACY_PTY_COUNT=256
456
457#
458# IPMI
459#
460# CONFIG_IPMI_HANDLER is not set
461
462#
463# Watchdog Cards
464#
465# CONFIG_WATCHDOG is not set
466# CONFIG_NVRAM is not set
467CONFIG_GEN_RTC=y
468# CONFIG_GEN_RTC_X is not set
469# CONFIG_DTLK is not set
470# CONFIG_R3964 is not set
471
472#
473# Ftape, the floppy tape device driver
474#
475# CONFIG_AGP is not set
476# CONFIG_RAW_DRIVER is not set
477
478#
479# TPM devices
480#
481# CONFIG_TCG_TPM is not set
482# CONFIG_TELCLOCK is not set
483
484#
485# I2C support
486#
487# CONFIG_I2C is not set
488
489#
490# Dallas's 1-wire bus
491#
492# CONFIG_W1 is not set
493
494#
495# Hardware Monitoring support
496#
497CONFIG_HWMON=y
498# CONFIG_HWMON_VID is not set
499# CONFIG_HWMON_DEBUG_CHIP is not set
500
501#
502# Misc devices
503#
504
505#
506# Multimedia Capabilities Port drivers
507#
508
509#
510# Multimedia devices
511#
512# CONFIG_VIDEO_DEV is not set
513
514#
515# Digital Video Broadcasting Devices
516#
517# CONFIG_DVB is not set
518
519#
520# Graphics support
521#
522# CONFIG_FB is not set
523
524#
525# Sound
526#
527# CONFIG_SOUND is not set
528
529#
530# USB support
531#
532# CONFIG_USB_ARCH_HAS_HCD is not set
533# CONFIG_USB_ARCH_HAS_OHCI is not set
534
535#
536# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
537#
538
539#
540# USB Gadget Support
541#
542# CONFIG_USB_GADGET is not set
543
544#
545# MMC/SD Card support
546#
547# CONFIG_MMC is not set
548
549#
550# InfiniBand support
551#
552
553#
554# SN Devices
555#
556
557#
558# File systems
559#
560CONFIG_EXT2_FS=y
561# CONFIG_EXT2_FS_XATTR is not set
562# CONFIG_EXT2_FS_XIP is not set
563CONFIG_EXT3_FS=y
564CONFIG_EXT3_FS_XATTR=y
565# CONFIG_EXT3_FS_POSIX_ACL is not set
566# CONFIG_EXT3_FS_SECURITY is not set
567CONFIG_JBD=y
568# CONFIG_JBD_DEBUG is not set
569CONFIG_FS_MBCACHE=y
570# CONFIG_REISERFS_FS is not set
571# CONFIG_JFS_FS is not set
572# CONFIG_FS_POSIX_ACL is not set
573# CONFIG_XFS_FS is not set
574# CONFIG_OCFS2_FS is not set
575# CONFIG_MINIX_FS is not set
576# CONFIG_ROMFS_FS is not set
577CONFIG_INOTIFY=y
578# CONFIG_QUOTA is not set
579CONFIG_DNOTIFY=y
580# CONFIG_AUTOFS_FS is not set
581# CONFIG_AUTOFS4_FS is not set
582# CONFIG_FUSE_FS is not set
583
584#
585# CD-ROM/DVD Filesystems
586#
587# CONFIG_ISO9660_FS is not set
588# CONFIG_UDF_FS is not set
589
590#
591# DOS/FAT/NT Filesystems
592#
593# CONFIG_MSDOS_FS is not set
594# CONFIG_VFAT_FS is not set
595# CONFIG_NTFS_FS is not set
596
597#
598# Pseudo filesystems
599#
600CONFIG_PROC_FS=y
601CONFIG_PROC_KCORE=y
602CONFIG_SYSFS=y
603CONFIG_TMPFS=y
604# CONFIG_HUGETLB_PAGE is not set
605CONFIG_RAMFS=y
606# CONFIG_RELAYFS_FS is not set
607# CONFIG_CONFIGFS_FS is not set
608
609#
610# Miscellaneous filesystems
611#
612# CONFIG_ADFS_FS is not set
613# CONFIG_AFFS_FS is not set
614# CONFIG_HFS_FS is not set
615# CONFIG_HFSPLUS_FS is not set
616# CONFIG_BEFS_FS is not set
617# CONFIG_BFS_FS is not set
618# CONFIG_EFS_FS is not set
619# CONFIG_CRAMFS is not set
620# CONFIG_VXFS_FS is not set
621# CONFIG_HPFS_FS is not set
622# CONFIG_QNX4FS_FS is not set
623# CONFIG_SYSV_FS is not set
624# CONFIG_UFS_FS is not set
625
626#
627# Network File Systems
628#
629CONFIG_NFS_FS=y
630# CONFIG_NFS_V3 is not set
631# CONFIG_NFS_V4 is not set
632# CONFIG_NFS_DIRECTIO is not set
633# CONFIG_NFSD is not set
634CONFIG_ROOT_NFS=y
635CONFIG_LOCKD=y
636CONFIG_NFS_COMMON=y
637CONFIG_SUNRPC=y
638# CONFIG_RPCSEC_GSS_KRB5 is not set
639# CONFIG_RPCSEC_GSS_SPKM3 is not set
640# CONFIG_SMB_FS is not set
641# CONFIG_CIFS is not set
642# CONFIG_NCP_FS is not set
643# CONFIG_CODA_FS is not set
644# CONFIG_AFS_FS is not set
645# CONFIG_9P_FS is not set
646
647#
648# Partition Types
649#
650CONFIG_PARTITION_ADVANCED=y
651# CONFIG_ACORN_PARTITION is not set
652# CONFIG_OSF_PARTITION is not set
653# CONFIG_AMIGA_PARTITION is not set
654# CONFIG_ATARI_PARTITION is not set
655# CONFIG_MAC_PARTITION is not set
656# CONFIG_MSDOS_PARTITION is not set
657# CONFIG_LDM_PARTITION is not set
658# CONFIG_SGI_PARTITION is not set
659# CONFIG_ULTRIX_PARTITION is not set
660# CONFIG_SUN_PARTITION is not set
661# CONFIG_EFI_PARTITION is not set
662
663#
664# Native Language Support
665#
666# CONFIG_NLS is not set
667
668#
669# Library routines
670#
671# CONFIG_CRC_CCITT is not set
672# CONFIG_CRC16 is not set
673CONFIG_CRC32=y
674# CONFIG_LIBCRC32C is not set
675
676#
677# Instrumentation Support
678#
679# CONFIG_PROFILING is not set
680
681#
682# Kernel hacking
683#
684# CONFIG_PRINTK_TIME is not set
685# CONFIG_MAGIC_SYSRQ is not set
686CONFIG_DEBUG_KERNEL=y
687CONFIG_LOG_BUF_SHIFT=14
688CONFIG_DETECT_SOFTLOCKUP=y
689# CONFIG_SCHEDSTATS is not set
690# CONFIG_DEBUG_SLAB is not set
691CONFIG_DEBUG_MUTEXES=y
692# CONFIG_DEBUG_SPINLOCK is not set
693# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
694# CONFIG_DEBUG_KOBJECT is not set
695# CONFIG_DEBUG_INFO is not set
696# CONFIG_DEBUG_FS is not set
697# CONFIG_DEBUG_VM is not set
698# CONFIG_RCU_TORTURE_TEST is not set
699# CONFIG_DEBUGGER is not set
700# CONFIG_BDI_SWITCH is not set
701# CONFIG_BOOTX_TEXT is not set
702# CONFIG_PPC_EARLY_DEBUG_LPAR is not set
703# CONFIG_PPC_EARLY_DEBUG_G5 is not set
704# CONFIG_PPC_EARLY_DEBUG_RTAS is not set
705# CONFIG_PPC_EARLY_DEBUG_MAPLE is not set
706# CONFIG_PPC_EARLY_DEBUG_ISERIES is not set
707
708#
709# Security options
710#
711# CONFIG_KEYS is not set
712# CONFIG_SECURITY is not set
713
714#
715# Cryptographic options
716#
717# CONFIG_CRYPTO is not set
718
719#
720# Hardware crypto devices
721#
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
new file mode 100644
index 000000000000..5827c27e0b59
--- /dev/null
+++ b/arch/powerpc/kernel/head_booke.h
@@ -0,0 +1,363 @@
1#ifndef __HEAD_BOOKE_H__
2#define __HEAD_BOOKE_H__
3
4/*
5 * Macros used for common Book-e exception handling
6 */
7
8#define SET_IVOR(vector_number, vector_label) \
9 li r26,vector_label@l; \
10 mtspr SPRN_IVOR##vector_number,r26; \
11 sync
12
13#define NORMAL_EXCEPTION_PROLOG \
14 mtspr SPRN_SPRG0,r10; /* save two registers to work with */\
15 mtspr SPRN_SPRG1,r11; \
16 mtspr SPRN_SPRG4W,r1; \
17 mfcr r10; /* save CR in r10 for now */\
18 mfspr r11,SPRN_SRR1; /* check whether user or kernel */\
19 andi. r11,r11,MSR_PR; \
20 beq 1f; \
21 mfspr r1,SPRN_SPRG3; /* if from user, start at top of */\
22 lwz r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack */\
23 addi r1,r1,THREAD_SIZE; \
241: subi r1,r1,INT_FRAME_SIZE; /* Allocate an exception frame */\
25 mr r11,r1; \
26 stw r10,_CCR(r11); /* save various registers */\
27 stw r12,GPR12(r11); \
28 stw r9,GPR9(r11); \
29 mfspr r10,SPRN_SPRG0; \
30 stw r10,GPR10(r11); \
31 mfspr r12,SPRN_SPRG1; \
32 stw r12,GPR11(r11); \
33 mflr r10; \
34 stw r10,_LINK(r11); \
35 mfspr r10,SPRN_SPRG4R; \
36 mfspr r12,SPRN_SRR0; \
37 stw r10,GPR1(r11); \
38 mfspr r9,SPRN_SRR1; \
39 stw r10,0(r11); \
40 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
41 stw r0,GPR0(r11); \
42 SAVE_4GPRS(3, r11); \
43 SAVE_2GPRS(7, r11)
44
45/* To handle the additional exception priority levels on 40x and Book-E
46 * processors we allocate a 4k stack per additional priority level. The various
47 * head_xxx.S files allocate space (exception_stack_top) for each priority's
48 * stack times the number of CPUs
49 *
50 * On 40x critical is the only additional level
51 * On 44x/e500 we have critical and machine check
52 * On e200 we have critical and debug (machine check occurs via critical)
53 *
54 * Additionally we reserve a SPRG for each priority level so we can free up a
55 * GPR to use as the base for indirect access to the exception stacks. This
56 * is necessary since the MMU is always on, for Book-E parts, and the stacks
57 * are offset from KERNELBASE.
58 *
59 */
60#define BOOKE_EXCEPTION_STACK_SIZE (8192)
61
62/* CRIT_SPRG only used in critical exception handling */
63#define CRIT_SPRG SPRN_SPRG2
64/* MCHECK_SPRG only used in machine check exception handling */
65#define MCHECK_SPRG SPRN_SPRG6W
66
67#define MCHECK_STACK_TOP (exception_stack_top - 4096)
68#define CRIT_STACK_TOP (exception_stack_top)
69
70/* only on e200 for now */
71#define DEBUG_STACK_TOP (exception_stack_top - 4096)
72#define DEBUG_SPRG SPRN_SPRG6W
73
74#ifdef CONFIG_SMP
75#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
76 mfspr r8,SPRN_PIR; \
77 mulli r8,r8,BOOKE_EXCEPTION_STACK_SIZE; \
78 neg r8,r8; \
79 addis r8,r8,level##_STACK_TOP@ha; \
80 addi r8,r8,level##_STACK_TOP@l
81#else
82#define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
83 lis r8,level##_STACK_TOP@h; \
84 ori r8,r8,level##_STACK_TOP@l
85#endif
86
87/*
88 * Exception prolog for critical/machine check exceptions. This is a
89 * little different from the normal exception prolog above since a
90 * critical/machine check exception can potentially occur at any point
91 * during normal exception processing. Thus we cannot use the same SPRG
92 * registers as the normal prolog above. Instead we use a portion of the
93 * critical/machine check exception stack at low physical addresses.
94 */
95#define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, exc_level_srr0, exc_level_srr1) \
96 mtspr exc_level##_SPRG,r8; \
97 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
98 stw r10,GPR10-INT_FRAME_SIZE(r8); \
99 stw r11,GPR11-INT_FRAME_SIZE(r8); \
100 mfcr r10; /* save CR in r10 for now */\
101 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
102 andi. r11,r11,MSR_PR; \
103 mr r11,r8; \
104 mfspr r8,exc_level##_SPRG; \
105 beq 1f; \
106 /* COMING FROM USER MODE */ \
107 mfspr r11,SPRN_SPRG3; /* if from user, start at top of */\
108 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
109 addi r11,r11,THREAD_SIZE; \
1101: subi r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame */\
111 stw r10,_CCR(r11); /* save various registers */\
112 stw r12,GPR12(r11); \
113 stw r9,GPR9(r11); \
114 mflr r10; \
115 stw r10,_LINK(r11); \
116 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
117 stw r12,_DEAR(r11); /* since they may have had stuff */\
118 mfspr r9,SPRN_ESR; /* in them at the point where the */\
119 stw r9,_ESR(r11); /* exception was taken */\
120 mfspr r12,exc_level_srr0; \
121 stw r1,GPR1(r11); \
122 mfspr r9,exc_level_srr1; \
123 stw r1,0(r11); \
124 mr r1,r11; \
125 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
126 stw r0,GPR0(r11); \
127 SAVE_4GPRS(3, r11); \
128 SAVE_2GPRS(7, r11)
129
130#define CRITICAL_EXCEPTION_PROLOG \
131 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1)
132#define DEBUG_EXCEPTION_PROLOG \
133 EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1)
134#define MCHECK_EXCEPTION_PROLOG \
135 EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1)
136
137/*
138 * Exception vectors.
139 */
140#define START_EXCEPTION(label) \
141 .align 5; \
142label:
143
144#define FINISH_EXCEPTION(func) \
145 bl transfer_to_handler_full; \
146 .long func; \
147 .long ret_from_except_full
148
149#define EXCEPTION(n, label, hdlr, xfer) \
150 START_EXCEPTION(label); \
151 NORMAL_EXCEPTION_PROLOG; \
152 addi r3,r1,STACK_FRAME_OVERHEAD; \
153 xfer(n, hdlr)
154
155#define CRITICAL_EXCEPTION(n, label, hdlr) \
156 START_EXCEPTION(label); \
157 CRITICAL_EXCEPTION_PROLOG; \
158 addi r3,r1,STACK_FRAME_OVERHEAD; \
159 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
160 NOCOPY, crit_transfer_to_handler, \
161 ret_from_crit_exc)
162
163#define MCHECK_EXCEPTION(n, label, hdlr) \
164 START_EXCEPTION(label); \
165 MCHECK_EXCEPTION_PROLOG; \
166 mfspr r5,SPRN_ESR; \
167 stw r5,_ESR(r11); \
168 addi r3,r1,STACK_FRAME_OVERHEAD; \
169 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
170 NOCOPY, mcheck_transfer_to_handler, \
171 ret_from_mcheck_exc)
172
173#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
174 li r10,trap; \
175 stw r10,_TRAP(r11); \
176 lis r10,msr@h; \
177 ori r10,r10,msr@l; \
178 copyee(r10, r9); \
179 bl tfer; \
180 .long hdlr; \
181 .long ret
182
183#define COPY_EE(d, s) rlwimi d,s,0,16,16
184#define NOCOPY(d, s)
185
186#define EXC_XFER_STD(n, hdlr) \
187 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
188 ret_from_except_full)
189
190#define EXC_XFER_LITE(n, hdlr) \
191 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
192 ret_from_except)
193
194#define EXC_XFER_EE(n, hdlr) \
195 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
196 ret_from_except_full)
197
198#define EXC_XFER_EE_LITE(n, hdlr) \
199 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
200 ret_from_except)
201
202/* Check for a single step debug exception while in an exception
203 * handler before state has been saved. This is to catch the case
204 * where an instruction that we are trying to single step causes
205 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
206 * the exception handler generates a single step debug exception.
207 *
208 * If we get a debug trap on the first instruction of an exception handler,
209 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
210 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
211 * The exception handler was handling a non-critical interrupt, so it will
212 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
213 * the MSR_DE bit set.
214 */
215#ifdef CONFIG_E200
216#define DEBUG_EXCEPTION \
217 START_EXCEPTION(Debug); \
218 DEBUG_EXCEPTION_PROLOG; \
219 \
220 /* \
221 * If there is a single step or branch-taken exception in an \
222 * exception entry sequence, it was probably meant to apply to \
223 * the code where the exception occurred (since exception entry \
224 * doesn't turn off DE automatically). We simulate the effect \
225 * of turning off DE on entry to an exception handler by turning \
226 * off DE in the CSRR1 value and clearing the debug status. \
227 */ \
228 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
229 andis. r10,r10,DBSR_IC@h; \
230 beq+ 2f; \
231 \
232 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
233 ori r10,r10,KERNELBASE@l; \
234 cmplw r12,r10; \
235 blt+ 2f; /* addr below exception vectors */ \
236 \
237 lis r10,Debug@h; \
238 ori r10,r10,Debug@l; \
239 cmplw r12,r10; \
240 bgt+ 2f; /* addr above exception vectors */ \
241 \
242 /* here it looks like we got an inappropriate debug exception. */ \
2431: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
244 lis r10,DBSR_IC@h; /* clear the IC event */ \
245 mtspr SPRN_DBSR,r10; \
246 /* restore state and get out */ \
247 lwz r10,_CCR(r11); \
248 lwz r0,GPR0(r11); \
249 lwz r1,GPR1(r11); \
250 mtcrf 0x80,r10; \
251 mtspr SPRN_DSRR0,r12; \
252 mtspr SPRN_DSRR1,r9; \
253 lwz r9,GPR9(r11); \
254 lwz r12,GPR12(r11); \
255 mtspr DEBUG_SPRG,r8; \
256 BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \
257 lwz r10,GPR10-INT_FRAME_SIZE(r8); \
258 lwz r11,GPR11-INT_FRAME_SIZE(r8); \
259 mfspr r8,DEBUG_SPRG; \
260 \
261 RFDI; \
262 b .; \
263 \
264 /* continue normal handling for a critical exception... */ \
2652: mfspr r4,SPRN_DBSR; \
266 addi r3,r1,STACK_FRAME_OVERHEAD; \
267 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
268#else
269#define DEBUG_EXCEPTION \
270 START_EXCEPTION(Debug); \
271 CRITICAL_EXCEPTION_PROLOG; \
272 \
273 /* \
274 * If there is a single step or branch-taken exception in an \
275 * exception entry sequence, it was probably meant to apply to \
276 * the code where the exception occurred (since exception entry \
277 * doesn't turn off DE automatically). We simulate the effect \
278 * of turning off DE on entry to an exception handler by turning \
279 * off DE in the CSRR1 value and clearing the debug status. \
280 */ \
281 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
282 andis. r10,r10,DBSR_IC@h; \
283 beq+ 2f; \
284 \
285 lis r10,KERNELBASE@h; /* check if exception in vectors */ \
286 ori r10,r10,KERNELBASE@l; \
287 cmplw r12,r10; \
288 blt+ 2f; /* addr below exception vectors */ \
289 \
290 lis r10,Debug@h; \
291 ori r10,r10,Debug@l; \
292 cmplw r12,r10; \
293 bgt+ 2f; /* addr above exception vectors */ \
294 \
295 /* here it looks like we got an inappropriate debug exception. */ \
2961: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
297 lis r10,DBSR_IC@h; /* clear the IC event */ \
298 mtspr SPRN_DBSR,r10; \
299 /* restore state and get out */ \
300 lwz r10,_CCR(r11); \
301 lwz r0,GPR0(r11); \
302 lwz r1,GPR1(r11); \
303 mtcrf 0x80,r10; \
304 mtspr SPRN_CSRR0,r12; \
305 mtspr SPRN_CSRR1,r9; \
306 lwz r9,GPR9(r11); \
307 lwz r12,GPR12(r11); \
308 mtspr CRIT_SPRG,r8; \
309 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
310 lwz r10,GPR10-INT_FRAME_SIZE(r8); \
311 lwz r11,GPR11-INT_FRAME_SIZE(r8); \
312 mfspr r8,CRIT_SPRG; \
313 \
314 rfci; \
315 b .; \
316 \
317 /* continue normal handling for a critical exception... */ \
3182: mfspr r4,SPRN_DBSR; \
319 addi r3,r1,STACK_FRAME_OVERHEAD; \
320 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
321#endif
322
323#define INSTRUCTION_STORAGE_EXCEPTION \
324 START_EXCEPTION(InstructionStorage) \
325 NORMAL_EXCEPTION_PROLOG; \
326 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
327 stw r5,_ESR(r11); \
328 mr r4,r12; /* Pass SRR0 as arg2 */ \
329 li r5,0; /* Pass zero as arg3 */ \
330 EXC_XFER_EE_LITE(0x0400, handle_page_fault)
331
332#define ALIGNMENT_EXCEPTION \
333 START_EXCEPTION(Alignment) \
334 NORMAL_EXCEPTION_PROLOG; \
335 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
336 stw r4,_DEAR(r11); \
337 addi r3,r1,STACK_FRAME_OVERHEAD; \
338 EXC_XFER_EE(0x0600, alignment_exception)
339
340#define PROGRAM_EXCEPTION \
341 START_EXCEPTION(Program) \
342 NORMAL_EXCEPTION_PROLOG; \
343 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
344 stw r4,_ESR(r11); \
345 addi r3,r1,STACK_FRAME_OVERHEAD; \
346 EXC_XFER_STD(0x0700, program_check_exception)
347
348#define DECREMENTER_EXCEPTION \
349 START_EXCEPTION(Decrementer) \
350 NORMAL_EXCEPTION_PROLOG; \
351 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
352 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
353 addi r3,r1,STACK_FRAME_OVERHEAD; \
354 EXC_XFER_LITE(0x0900, timer_interrupt)
355
356#define FP_UNAVAILABLE_EXCEPTION \
357 START_EXCEPTION(FloatingPointUnavailable) \
358 NORMAL_EXCEPTION_PROLOG; \
359 bne load_up_fpu; /* if from user, just load it up */ \
360 addi r3,r1,STACK_FRAME_OVERHEAD; \
361 EXC_XFER_EE_LITE(0x800, KernelFP)
362
363#endif /* __HEAD_BOOKE_H__ */
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index c5bc2821d991..d3d0ff745e84 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -1,86 +1,30 @@
1config 85xx 1menu "Platform support"
2 bool 2 depends on PPC_85xx
3 depends on E500
4 default y
5
6config PPC_INDIRECT_PCI_BE
7 bool
8 depends on 85xx
9 default y
10
11menu "Freescale 85xx options"
12 depends on E500
13 3
14choice 4choice
15 prompt "Machine Type" 5 prompt "Machine Type"
16 depends on 85xx
17 default MPC8540_ADS 6 default MPC8540_ADS
18 7
19config MPC8540_ADS 8config MPC8540_ADS
20 bool "Freescale MPC8540 ADS" 9 bool "Freescale MPC8540 ADS"
21 help 10 help
22 This option enables support for the MPC 8540 ADS evaluation board. 11 This option enables support for the MPC 8540 ADS board
23
24config MPC8548_CDS
25 bool "Freescale MPC8548 CDS"
26 help
27 This option enablese support for the MPC8548 CDS evaluation board.
28
29config MPC8555_CDS
30 bool "Freescale MPC8555 CDS"
31 help
32 This option enablese support for the MPC8555 CDS evaluation board.
33
34config MPC8560_ADS
35 bool "Freescale MPC8560 ADS"
36 help
37 This option enables support for the MPC 8560 ADS evaluation board.
38
39config SBC8560
40 bool "WindRiver PowerQUICC III SBC8560"
41 help
42 This option enables support for the WindRiver PowerQUICC III
43 SBC8560 board.
44
45config STX_GP3
46 bool "Silicon Turnkey Express GP3"
47 help
48 This option enables support for the Silicon Turnkey Express GP3
49 board.
50 12
51endchoice 13endchoice
52 14
53# It's often necessary to know the specific 85xx processor type.
54# Fortunately, it is implied (so far) from the board type, so we
55# don't need to ask more redundant questions.
56config MPC8540 15config MPC8540
57 bool 16 bool
58 depends on MPC8540_ADS 17 select PPC_UDBG_16550
59 default y 18 select PPC_INDIRECT_PCI
60 19 default y if MPC8540_ADS
61config MPC8548
62 bool
63 depends on MPC8548_CDS
64 default y
65 20
66config MPC8555 21config PPC_INDIRECT_PCI_BE
67 bool
68 depends on MPC8555_CDS
69 default y
70
71config MPC8560
72 bool 22 bool
73 depends on SBC8560 || MPC8560_ADS || STX_GP3 23 depends on PPC_85xx
74 default y
75
76config 85xx_PCI2
77 bool "Supprt for 2nd PCI host controller"
78 depends on MPC8555_CDS
79 default y 24 default y
80 25
81config PPC_GEN550 26config MPIC
82 bool 27 bool
83 depends on MPC8540 || SBC8560 || MPC8555
84 default y 28 default y
85 29
86endmenu 30endmenu
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 6407197ffd89..b443206e61af 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -1 +1,4 @@
1# empty makefile so make clean works 1#
2# Makefile for the PowerPC 85xx linux kernel.
3#
4obj-$(CONFIG_PPC_85xx) += mpc85xx.o mpc85xx_ads.o
diff --git a/arch/powerpc/platforms/85xx/mpc8540_ads.h b/arch/powerpc/platforms/85xx/mpc8540_ads.h
new file mode 100644
index 000000000000..47609c97e01e
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc8540_ads.h
@@ -0,0 +1,60 @@
1/*
2 * arch/ppc/platforms/85xx/mpc8540_ads.h
3 *
4 * MPC8540ADS board definitions
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2004 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17#ifndef __MACH_MPC8540ADS_H__
18#define __MACH_MPC8540ADS_H__
19
20#include <linux/config.h>
21#include <linux/initrd.h>
22
23#define BOARD_CCSRBAR ((uint)0xe0000000)
24#define BCSR_ADDR ((uint)0xf8000000)
25#define BCSR_SIZE ((uint)(32 * 1024))
26
27/* PCI interrupt controller */
28#define PIRQA MPC85xx_IRQ_EXT1
29#define PIRQB MPC85xx_IRQ_EXT2
30#define PIRQC MPC85xx_IRQ_EXT3
31#define PIRQD MPC85xx_IRQ_EXT4
32
33#define MPC85XX_PCI1_LOWER_IO 0x00000000
34#define MPC85XX_PCI1_UPPER_IO 0x00ffffff
35
36#define MPC85XX_PCI1_LOWER_MEM 0x80000000
37#define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
38
39#define MPC85XX_PCI1_IO_BASE 0xe2000000
40#define MPC85XX_PCI1_MEM_OFFSET 0x00000000
41
42#define MPC85XX_PCI1_IO_SIZE 0x01000000
43
44/* PCI config */
45#define PCI1_CFG_ADDR_OFFSET (0x8000)
46#define PCI1_CFG_DATA_OFFSET (0x8004)
47
48#define PCI2_CFG_ADDR_OFFSET (0x9000)
49#define PCI2_CFG_DATA_OFFSET (0x9004)
50
51/* Additional register for PCI-X configuration */
52#define PCIX_NEXT_CAP 0x60
53#define PCIX_CAP_ID 0x61
54#define PCIX_COMMAND 0x62
55#define PCIX_STATUS 0x64
56
57/* Offset of CPM register space */
58#define CPM_MAP_ADDR (CCSRBAR + MPC85xx_CPM_OFFSET)
59
60#endif /* __MACH_MPC8540ADS_H__ */
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.c b/arch/powerpc/platforms/85xx/mpc85xx.c
new file mode 100644
index 000000000000..82510385d88a
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx.c
@@ -0,0 +1,31 @@
1/*
2 * MPC85xx generic code.
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/irq.h>
14#include <linux/module.h>
15#include <asm/irq.h>
16
17extern void abort(void);
18
19void
20mpc85xx_restart(char *cmd)
21{
22 local_irq_disable();
23 abort();
24}
25
26/* For now this is a pass through */
27phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
28{
29 return addr;
30};
31EXPORT_SYMBOL(fixup_bigphys_addr);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
new file mode 100644
index 000000000000..be75abb2a283
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -0,0 +1,17 @@
1/*
2 * arch/ppc/platforms/85xx/mpc85xx.h
3 *
4 * MPC85xx soc definitions/function decls
5 *
6 * Maintainer: Kumar Gala <kumar.gala@freescale.com>
7 *
8 * Copyright 2005 Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16
17extern void mpc85xx_restart(char *);
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
new file mode 100644
index 000000000000..41191e9aa528
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -0,0 +1,208 @@
1/*
2 * MPC85xx setup and early boot code plus other random bits.
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2005 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/config.h>
15#include <linux/stddef.h>
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/errno.h>
19#include <linux/reboot.h>
20#include <linux/pci.h>
21#include <linux/kdev_t.h>
22#include <linux/major.h>
23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/irq.h>
26#include <linux/seq_file.h>
27#include <linux/root_dev.h>
28#include <linux/serial.h>
29#include <linux/tty.h> /* for linux/serial_core.h */
30#include <linux/serial_core.h>
31#include <linux/initrd.h>
32#include <linux/module.h>
33#include <linux/fsl_devices.h>
34#include <linux/serial_core.h>
35#include <linux/serial_8250.h>
36
37#include <asm/system.h>
38#include <asm/pgtable.h>
39#include <asm/page.h>
40#include <asm/atomic.h>
41#include <asm/time.h>
42#include <asm/io.h>
43#include <asm/machdep.h>
44#include <asm/bootinfo.h>
45#include <asm/pci-bridge.h>
46#include <asm/mpc85xx.h>
47#include <asm/irq.h>
48#include <asm/immap_85xx.h>
49#include <asm/prom.h>
50#include <asm/mpic.h>
51#include <mm/mmu_decl.h>
52#include <asm/udbg.h>
53
54#include <sysdev/fsl_soc.h>
55#include "mpc85xx.h"
56
57#ifndef CONFIG_PCI
58unsigned long isa_io_base = 0;
59unsigned long isa_mem_base = 0;
60#endif
61
62
63/*
64 * Internal interrupts are all Level Sensitive, and Positive Polarity
65 *
66 * Note: Likely, this table and the following function should be
67 * obtained and derived from the OF Device Tree.
68 */
69static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
70 MPC85XX_INTERNAL_IRQ_SENSES,
71 0x0, /* External 0: */
72#if defined(CONFIG_PCI)
73 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 1: PCI slot 0 */
74 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 2: PCI slot 1 */
75 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 3: PCI slot 2 */
76 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Ext 4: PCI slot 3 */
77#else
78 0x0, /* External 1: */
79 0x0, /* External 2: */
80 0x0, /* External 3: */
81 0x0, /* External 4: */
82#endif
83 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
84 0x0, /* External 6: */
85 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 7: PHY */
86 0x0, /* External 8: */
87 0x0, /* External 9: */
88 0x0, /* External 10: */
89 0x0, /* External 11: */
90};
91
92
93void __init mpc85xx_ads_pic_init(void)
94{
95 struct mpic *mpic1;
96 phys_addr_t OpenPIC_PAddr;
97
98 /* Determine the Physical Address of the OpenPIC regs */
99 OpenPIC_PAddr = get_immrbase() + MPC85xx_OPENPIC_OFFSET;
100
101 mpic1 = mpic_alloc(OpenPIC_PAddr,
102 MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
103 4, MPC85xx_OPENPIC_IRQ_OFFSET, 0, 250,
104 mpc85xx_ads_openpic_initsenses,
105 sizeof(mpc85xx_ads_openpic_initsenses), " OpenPIC ");
106 BUG_ON(mpic1 == NULL);
107 mpic_assign_isu(mpic1, 0, OpenPIC_PAddr + 0x10200);
108 mpic_assign_isu(mpic1, 1, OpenPIC_PAddr + 0x10280);
109 mpic_assign_isu(mpic1, 2, OpenPIC_PAddr + 0x10300);
110 mpic_assign_isu(mpic1, 3, OpenPIC_PAddr + 0x10380);
111 mpic_assign_isu(mpic1, 4, OpenPIC_PAddr + 0x10400);
112 mpic_assign_isu(mpic1, 5, OpenPIC_PAddr + 0x10480);
113 mpic_assign_isu(mpic1, 6, OpenPIC_PAddr + 0x10500);
114 mpic_assign_isu(mpic1, 7, OpenPIC_PAddr + 0x10580);
115
116 /* dummy mappings to get to 48 */
117 mpic_assign_isu(mpic1, 8, OpenPIC_PAddr + 0x10600);
118 mpic_assign_isu(mpic1, 9, OpenPIC_PAddr + 0x10680);
119 mpic_assign_isu(mpic1, 10, OpenPIC_PAddr + 0x10700);
120 mpic_assign_isu(mpic1, 11, OpenPIC_PAddr + 0x10780);
121
122 /* External ints */
123 mpic_assign_isu(mpic1, 12, OpenPIC_PAddr + 0x10000);
124 mpic_assign_isu(mpic1, 13, OpenPIC_PAddr + 0x10080);
125 mpic_assign_isu(mpic1, 14, OpenPIC_PAddr + 0x10100);
126 mpic_init(mpic1);
127}
128
129
130/*
131 * Setup the architecture
132 */
133static void __init
134mpc85xx_ads_setup_arch(void)
135{
136 struct device_node *cpu;
137
138 if (ppc_md.progress)
139 ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
140
141 cpu = of_find_node_by_type(NULL, "cpu");
142 if (cpu != 0) {
143 unsigned int *fp;
144
145 fp = (int *)get_property(cpu, "clock-frequency", NULL);
146 if (fp != 0)
147 loops_per_jiffy = *fp / HZ;
148 else
149 loops_per_jiffy = 50000000 / HZ;
150 of_node_put(cpu);
151 }
152
153#ifdef CONFIG_ROOT_NFS
154 ROOT_DEV = Root_NFS;
155#else
156 ROOT_DEV = Root_HDA1;
157#endif
158}
159
160
161void
162mpc85xx_ads_show_cpuinfo(struct seq_file *m)
163{
164 uint pvid, svid, phid1;
165 uint memsize = total_memory;
166
167 pvid = mfspr(SPRN_PVR);
168 svid = mfspr(SPRN_SVR);
169
170 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
171 seq_printf(m, "Machine\t\t: mpc85xx\n");
172 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
173 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
174
175 /* Display cpu Pll setting */
176 phid1 = mfspr(SPRN_HID1);
177 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
178
179 /* Display the amount of memory */
180 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
181}
182
183
184void __init
185platform_init(void)
186{
187 ppc_md.setup_arch = mpc85xx_ads_setup_arch;
188 ppc_md.show_cpuinfo = mpc85xx_ads_show_cpuinfo;
189
190 ppc_md.init_IRQ = mpc85xx_ads_pic_init;
191 ppc_md.get_irq = mpic_get_irq;
192
193 ppc_md.restart = mpc85xx_restart;
194 ppc_md.power_off = NULL;
195 ppc_md.halt = NULL;
196
197 ppc_md.time_init = NULL;
198 ppc_md.set_rtc_time = NULL;
199 ppc_md.get_rtc_time = NULL;
200 ppc_md.calibrate_decr = generic_calibrate_decr;
201
202 ppc_md.progress = udbg_progress;
203
204 if (ppc_md.progress)
205 ppc_md.progress("mpc85xx_ads platform_init(): exit", 0);
206}
207
208
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 04073fd987ec..c4f6b0d2d140 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -8,7 +8,7 @@ endif
8obj-$(CONFIG_PPC_CHRP) += chrp/ 8obj-$(CONFIG_PPC_CHRP) += chrp/
9obj-$(CONFIG_4xx) += 4xx/ 9obj-$(CONFIG_4xx) += 4xx/
10obj-$(CONFIG_PPC_83xx) += 83xx/ 10obj-$(CONFIG_PPC_83xx) += 83xx/
11obj-$(CONFIG_85xx) += 85xx/ 11obj-$(CONFIG_PPC_85xx) += 85xx/
12obj-$(CONFIG_PPC_PSERIES) += pseries/ 12obj-$(CONFIG_PPC_PSERIES) += pseries/
13obj-$(CONFIG_PPC_ISERIES) += iseries/ 13obj-$(CONFIG_PPC_ISERIES) += iseries/
14obj-$(CONFIG_PPC_MAPLE) += maple/ 14obj-$(CONFIG_PPC_MAPLE) += maple/
diff --git a/arch/ppc/8xx_io/commproc.c b/arch/ppc/8xx_io/commproc.c
index 579cd40258b9..12b84ca51327 100644
--- a/arch/ppc/8xx_io/commproc.c
+++ b/arch/ppc/8xx_io/commproc.c
@@ -73,7 +73,7 @@ cpm_mask_irq(unsigned int irq)
73{ 73{
74 int cpm_vec = irq - CPM_IRQ_OFFSET; 74 int cpm_vec = irq - CPM_IRQ_OFFSET;
75 75
76 out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) & ~(1 << cpm_vec)); 76 clrbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
77} 77}
78 78
79static void 79static void
@@ -81,7 +81,7 @@ cpm_unmask_irq(unsigned int irq)
81{ 81{
82 int cpm_vec = irq - CPM_IRQ_OFFSET; 82 int cpm_vec = irq - CPM_IRQ_OFFSET;
83 83
84 out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr) | (1 << cpm_vec)); 84 setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cimr, (1 << cpm_vec));
85} 85}
86 86
87static void 87static void
@@ -198,7 +198,7 @@ cpm_interrupt_init(void)
198 if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction)) 198 if (setup_irq(CPM_IRQ_OFFSET + CPMVEC_ERROR, &cpm_error_irqaction))
199 panic("Could not allocate CPM error IRQ!"); 199 panic("Could not allocate CPM error IRQ!");
200 200
201 out_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, in_be32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr) | CICR_IEN); 201 setbits32(&((immap_t *)IMAP_ADDR)->im_cpic.cpic_cicr, CICR_IEN);
202} 202}
203 203
204/* 204/*
diff --git a/arch/ppc/mm/44x_mmu.c b/arch/ppc/mm/44x_mmu.c
index 3d79ce281b67..e0152a9b26e6 100644
--- a/arch/ppc/mm/44x_mmu.c
+++ b/arch/ppc/mm/44x_mmu.c
@@ -104,7 +104,7 @@ unsigned long __init mmu_mapin_ram(void)
104 104
105 /* Determine number of entries necessary to cover lowmem */ 105 /* Determine number of entries necessary to cover lowmem */
106 pinned_tlbs = (unsigned int) 106 pinned_tlbs = (unsigned int)
107 (_ALIGN(total_lowmem, PPC44x_PIN_SIZE) >> PPC44x_PIN_SHIFT); 107 (_ALIGN(total_lowmem, PPC_PIN_SIZE) >> PPC44x_PIN_SHIFT);
108 108
109 /* Write upper watermark to save location */ 109 /* Write upper watermark to save location */
110 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs; 110 tlb_44x_hwater = PPC44x_LOW_SLOT - pinned_tlbs;
@@ -112,7 +112,7 @@ unsigned long __init mmu_mapin_ram(void)
112 /* If necessary, set additional pinned TLBs */ 112 /* If necessary, set additional pinned TLBs */
113 if (pinned_tlbs > 1) 113 if (pinned_tlbs > 1)
114 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) { 114 for (i = (PPC44x_LOW_SLOT-(pinned_tlbs-1)); i < PPC44x_LOW_SLOT; i++) {
115 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC44x_PIN_SIZE; 115 unsigned int phys_addr = (PPC44x_LOW_SLOT-i) * PPC_PIN_SIZE;
116 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr); 116 ppc44x_pin_tlb(i, phys_addr+PAGE_OFFSET, phys_addr);
117 } 117 }
118 118
diff --git a/arch/ppc/syslib/m8xx_setup.c b/arch/ppc/syslib/m8xx_setup.c
index 688616de3cde..cdb73a23a538 100644
--- a/arch/ppc/syslib/m8xx_setup.c
+++ b/arch/ppc/syslib/m8xx_setup.c
@@ -34,6 +34,13 @@
34#include <linux/seq_file.h> 34#include <linux/seq_file.h>
35#include <linux/root_dev.h> 35#include <linux/root_dev.h>
36 36
37#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
38#include <linux/mtd/partitions.h>
39#include <linux/mtd/physmap.h>
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/map.h>
42#endif
43
37#include <asm/mmu.h> 44#include <asm/mmu.h>
38#include <asm/reg.h> 45#include <asm/reg.h>
39#include <asm/residual.h> 46#include <asm/residual.h>
@@ -49,6 +56,34 @@
49 56
50#include "ppc8xx_pic.h" 57#include "ppc8xx_pic.h"
51 58
59#ifdef CONFIG_MTD_PHYSMAP
60#define MPC8xxADS_BANK_WIDTH 4
61#endif
62
63#define MPC8xxADS_U_BOOT_SIZE 0x80000
64#define MPC8xxADS_FREE_AREA_OFFSET MPC8xxADS_U_BOOT_SIZE
65
66#if defined(CONFIG_MTD_PARTITIONS)
67 /*
68 NOTE: bank width and interleave relative to the installed flash
69 should have been chosen within MTD_CFI_GEOMETRY options.
70 */
71static struct mtd_partition mpc8xxads_partitions[] = {
72 {
73 .name = "bootloader",
74 .size = MPC8xxADS_U_BOOT_SIZE,
75 .offset = 0,
76 .mask_flags = MTD_WRITEABLE, /* force read-only */
77 }, {
78 .name = "User FS",
79 .offset = MPC8xxADS_FREE_AREA_OFFSET
80 }
81};
82
83#define mpc8xxads_part_num (sizeof (mpc8xxads_partitions) / sizeof (mpc8xxads_partitions[0]))
84
85#endif
86
52static int m8xx_set_rtc_time(unsigned long time); 87static int m8xx_set_rtc_time(unsigned long time);
53static unsigned long m8xx_get_rtc_time(void); 88static unsigned long m8xx_get_rtc_time(void);
54void m8xx_calibrate_decr(void); 89void m8xx_calibrate_decr(void);
@@ -71,6 +106,10 @@ board_init(void)
71void __init 106void __init
72m8xx_setup_arch(void) 107m8xx_setup_arch(void)
73{ 108{
109#if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
110 bd_t *binfo = (bd_t *)__res;
111#endif
112
74 /* Reset the Communication Processor Module. 113 /* Reset the Communication Processor Module.
75 */ 114 */
76 m8xx_cpm_reset(); 115 m8xx_cpm_reset();
@@ -106,6 +145,17 @@ m8xx_setup_arch(void)
106 } 145 }
107#endif 146#endif
108#endif 147#endif
148
149#if defined (CONFIG_MPC86XADS) || defined (CONFIG_MPC885ADS)
150#if defined(CONFIG_MTD_PHYSMAP)
151 physmap_configure(binfo->bi_flashstart, binfo->bi_flashsize,
152 MPC8xxADS_BANK_WIDTH, NULL);
153#ifdef CONFIG_MTD_PARTITIONS
154 physmap_set_partitions(mpc8xxads_partitions, mpc8xxads_part_num);
155#endif /* CONFIG_MTD_PARTITIONS */
156#endif /* CONFIG_MTD_PHYSMAP */
157#endif
158
109 board_init(); 159 board_init();
110} 160}
111 161
@@ -140,9 +190,11 @@ void __init __attribute__ ((weak))
140init_internal_rtc(void) 190init_internal_rtc(void)
141{ 191{
142 /* Disable the RTC one second and alarm interrupts. */ 192 /* Disable the RTC one second and alarm interrupts. */
143 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) & ~(RTCSC_SIE | RTCSC_ALE)); 193 clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
194
144 /* Enable the RTC */ 195 /* Enable the RTC */
145 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, in_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc) | (RTCSC_RTF | RTCSC_RTE)); 196 setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
197
146} 198}
147 199
148/* The decrementer counts at the system (internal) clock frequency divided by 200/* The decrementer counts at the system (internal) clock frequency divided by
@@ -159,8 +211,7 @@ void __init m8xx_calibrate_decr(void)
159 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY); 211 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
160 212
161 /* Force all 8xx processors to use divide by 16 processor clock. */ 213 /* Force all 8xx processors to use divide by 16 processor clock. */
162 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 214 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
163 in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr)|0x02000000);
164 /* Processor frequency is MHz. 215 /* Processor frequency is MHz.
165 * The value 'fp' is the number of decrementer ticks per second. 216 * The value 'fp' is the number of decrementer ticks per second.
166 */ 217 */
@@ -239,8 +290,8 @@ m8xx_restart(char *cmd)
239 __volatile__ unsigned char dummy; 290 __volatile__ unsigned char dummy;
240 291
241 local_irq_disable(); 292 local_irq_disable();
242 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, in_be32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr) | 0x00000080);
243 293
294 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
244 /* Clear the ME bit in MSR to cause checkstop on machine check 295 /* Clear the ME bit in MSR to cause checkstop on machine check
245 */ 296 */
246 mtmsr(mfmsr() & ~0x1000); 297 mtmsr(mfmsr() & ~0x1000);
@@ -310,8 +361,8 @@ m8xx_init_IRQ(void)
310 i8259_init(0); 361 i8259_init(0);
311 362
312 /* The i8259 cascade interrupt must be level sensitive. */ 363 /* The i8259 cascade interrupt must be level sensitive. */
313 out_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, in_be32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel & ~(0x80000000 >> ISA_BRIDGE_INT)));
314 364
365 clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
315 if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction)) 366 if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
316 enable_irq(ISA_BRIDGE_INT); 367 enable_irq(ISA_BRIDGE_INT);
317#endif /* CONFIG_PCI */ 368#endif /* CONFIG_PCI */
diff --git a/arch/ppc/syslib/m8xx_wdt.c b/arch/ppc/syslib/m8xx_wdt.c
index df6c9557b86a..ac11d7bab443 100644
--- a/arch/ppc/syslib/m8xx_wdt.c
+++ b/arch/ppc/syslib/m8xx_wdt.c
@@ -41,8 +41,7 @@ static irqreturn_t m8xx_wdt_interrupt(int irq, void *dev, struct pt_regs *regs)
41 41
42 m8xx_wdt_reset(); 42 m8xx_wdt_reset();
43 43
44 out_be16(&imap->im_sit.sit_piscr, in_be16(&imap->im_sit.sit_piscr) | PISCR_PS); /* clear irq */ 44 setbits16(&imap->im_sit.sit_piscr, PISCR_PS);
45
46 return IRQ_HANDLED; 45 return IRQ_HANDLED;
47} 46}
48 47
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 06:37:44 -0500