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-rw-r--r--arch/blackfin/mach-bf518/include/mach/anomaly.h13
-rw-r--r--arch/blackfin/mach-bf527/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf533/include/mach/anomaly.h4
-rw-r--r--arch/blackfin/mach-bf537/include/mach/anomaly.h4
-rw-r--r--arch/blackfin/mach-bf538/include/mach/anomaly.h3
-rw-r--r--arch/blackfin/mach-bf548/include/mach/anomaly.h21
-rw-r--r--arch/blackfin/mach-bf561/include/mach/anomaly.h4
7 files changed, 38 insertions, 14 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 6e1670072829..143a29dfe870 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf518/anomaly.h 2 * File: include/asm-blackfin/mach-bf518/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - ???? 10 * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -19,6 +19,8 @@
19#define ANOMALY_05000122 (1) 19#define ANOMALY_05000122 (1)
20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ 20/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
21#define ANOMALY_05000245 (1) 21#define ANOMALY_05000245 (1)
22/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
23#define ANOMALY_05000254 (1)
22/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ 24/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
23#define ANOMALY_05000265 (1) 25#define ANOMALY_05000265 (1)
24/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ 26/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
@@ -53,6 +55,12 @@
53#define ANOMALY_05000443 (1) 55#define ANOMALY_05000443 (1)
54/* Incorrect L1 Instruction Bank B Memory Map Location */ 56/* Incorrect L1 Instruction Bank B Memory Map Location */
55#define ANOMALY_05000444 (1) 57#define ANOMALY_05000444 (1)
58/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
59#define ANOMALY_05000452 (1)
60/* PWM_TRIPB Signal Not Available on PG10 */
61#define ANOMALY_05000453 (1)
62/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
63#define ANOMALY_05000455 (1)
56 64
57/* Anomalies that don't exist on this proc */ 65/* Anomalies that don't exist on this proc */
58#define ANOMALY_05000125 (0) 66#define ANOMALY_05000125 (0)
@@ -67,6 +75,7 @@
67#define ANOMALY_05000273 (0) 75#define ANOMALY_05000273 (0)
68#define ANOMALY_05000278 (0) 76#define ANOMALY_05000278 (0)
69#define ANOMALY_05000285 (0) 77#define ANOMALY_05000285 (0)
78#define ANOMALY_05000305 (0)
70#define ANOMALY_05000307 (0) 79#define ANOMALY_05000307 (0)
71#define ANOMALY_05000311 (0) 80#define ANOMALY_05000311 (0)
72#define ANOMALY_05000312 (0) 81#define ANOMALY_05000312 (0)
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index fdc87839af60..4ffccb6de52d 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf527/anomaly.h 2 * File: include/asm-blackfin/mach-bf527/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -169,6 +169,7 @@
169#define ANOMALY_05000273 (0) 169#define ANOMALY_05000273 (0)
170#define ANOMALY_05000278 (0) 170#define ANOMALY_05000278 (0)
171#define ANOMALY_05000285 (0) 171#define ANOMALY_05000285 (0)
172#define ANOMALY_05000305 (0)
172#define ANOMALY_05000307 (0) 173#define ANOMALY_05000307 (0)
173#define ANOMALY_05000311 (0) 174#define ANOMALY_05000311 (0)
174#define ANOMALY_05000312 (0) 175#define ANOMALY_05000312 (0)
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 657dd1820a93..9e838f851720 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf533/anomaly.h 2 * File: include/asm-blackfin/mach-bf533/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -160,7 +160,7 @@
160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6) 160#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 161/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5) 162#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
163/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 163/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 164#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ 165/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) 166#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index fe1ae4c75cd6..438b43ffd41e 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -110,7 +110,7 @@
110#define ANOMALY_05000301 (1) 110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ 111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3) 112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 113/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3) 114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3) 116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 56ea454709ca..f4ece1cfca43 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf538/anomaly.h 2 * File: include/asm-blackfin/mach-bf538/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -120,6 +120,7 @@
120#define ANOMALY_05000198 (0) 120#define ANOMALY_05000198 (0)
121#define ANOMALY_05000230 (0) 121#define ANOMALY_05000230 (0)
122#define ANOMALY_05000263 (0) 122#define ANOMALY_05000263 (0)
123#define ANOMALY_05000305 (0)
123#define ANOMALY_05000311 (0) 124#define ANOMALY_05000311 (0)
124#define ANOMALY_05000323 (0) 125#define ANOMALY_05000323 (0)
125#define ANOMALY_05000353 (1) 126#define ANOMALY_05000353 (1)
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index d9d10a73c1dc..882e40ccf0d1 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -2,12 +2,12 @@
2 * File: include/asm-blackfin/mach-bf548/anomaly.h 2 * File: include/asm-blackfin/mach-bf548/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
9/* This file shoule be up to date with: 9/* This file shoule be up to date with:
10 * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List 10 * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
11 */ 11 */
12 12
13#ifndef _MACH_ANOMALY_H_ 13#ifndef _MACH_ANOMALY_H_
@@ -91,8 +91,6 @@
91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2) 91#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */ 92/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1) 93#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
94/* Mobile DDR Operation Not Functional */
95#define ANOMALY_05000377 (1)
96/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ 94/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
97#define ANOMALY_05000378 (__SILICON_REVISION__ < 2) 95#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
98/* 16-Bit NAND FLASH Boot Mode Is Not Functional */ 96/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
@@ -157,8 +155,22 @@
157#define ANOMALY_05000429 (__SILICON_REVISION__ < 2) 155#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
158/* Software System Reset Corrupts PLL_LOCKCNT Register */ 156/* Software System Reset Corrupts PLL_LOCKCNT Register */
159#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) 157#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
158/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
159#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
160/* OTP Write Accesses Not Supported */
161#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
160/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ 162/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
161#define ANOMALY_05000443 (1) 163#define ANOMALY_05000443 (1)
164/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
165#define ANOMALY_05000446 (1)
166/* UART IrDA Receiver Fails on Extended Bit Pulses */
167#define ANOMALY_05000447 (1)
168/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
169#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
170/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
171#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
172/* USB DMA Mode 1 Short Packet Data Corruption */
173#define ANOMALY_05000450 (1
162 174
163/* Anomalies that don't exist on this proc */ 175/* Anomalies that don't exist on this proc */
164#define ANOMALY_05000125 (0) 176#define ANOMALY_05000125 (0)
@@ -172,6 +184,7 @@
172#define ANOMALY_05000266 (0) 184#define ANOMALY_05000266 (0)
173#define ANOMALY_05000273 (0) 185#define ANOMALY_05000273 (0)
174#define ANOMALY_05000278 (0) 186#define ANOMALY_05000278 (0)
187#define ANOMALY_05000305 (0)
175#define ANOMALY_05000307 (0) 188#define ANOMALY_05000307 (0)
176#define ANOMALY_05000311 (0) 189#define ANOMALY_05000311 (0)
177#define ANOMALY_05000323 (0) 190#define ANOMALY_05000323 (0)
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 24d3a2264e44..d78bc6b49e61 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -2,7 +2,7 @@
2 * File: include/asm-blackfin/mach-bf561/anomaly.h 2 * File: include/asm-blackfin/mach-bf561/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/ 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 * 4 *
5 * Copyright (C) 2004-2008 Analog Devices Inc. 5 * Copyright (C) 2004-2009 Analog Devices Inc.
6 * Licensed under the GPL-2 or later. 6 * Licensed under the GPL-2 or later.
7 */ 7 */
8 8
@@ -224,7 +224,7 @@
224#define ANOMALY_05000301 (1) 224#define ANOMALY_05000301 (1)
225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ 225/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
226#define ANOMALY_05000302 (1) 226#define ANOMALY_05000302 (1)
227/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ 227/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5) 228#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
229/* SCKELOW Bit Does Not Maintain State Through Hibernate */ 229/* SCKELOW Bit Does Not Maintain State Through Hibernate */
230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5) 230#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 04:19:44 -0500