diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mm/proc-xscale.S | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S index 861b35947280..2d3823ec3153 100644 --- a/arch/arm/mm/proc-xscale.S +++ b/arch/arm/mm/proc-xscale.S | |||
@@ -241,7 +241,15 @@ ENTRY(xscale_flush_user_cache_range) | |||
241 | * it also trashes the mini I-cache used by JTAG debuggers. | 241 | * it also trashes the mini I-cache used by JTAG debuggers. |
242 | */ | 242 | */ |
243 | ENTRY(xscale_coherent_kern_range) | 243 | ENTRY(xscale_coherent_kern_range) |
244 | /* FALLTHROUGH */ | 244 | bic r0, r0, #CACHELINESIZE - 1 |
245 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
246 | add r0, r0, #CACHELINESIZE | ||
247 | cmp r0, r1 | ||
248 | blo 1b | ||
249 | mov r0, #0 | ||
250 | mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB | ||
251 | mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer | ||
252 | mov pc, lr | ||
245 | 253 | ||
246 | /* | 254 | /* |
247 | * coherent_user_range(start, end) | 255 | * coherent_user_range(start, end) |
@@ -252,18 +260,16 @@ ENTRY(xscale_coherent_kern_range) | |||
252 | * | 260 | * |
253 | * - start - virtual start address | 261 | * - start - virtual start address |
254 | * - end - virtual end address | 262 | * - end - virtual end address |
255 | * | ||
256 | * Note: single I-cache line invalidation isn't used here since | ||
257 | * it also trashes the mini I-cache used by JTAG debuggers. | ||
258 | */ | 263 | */ |
259 | ENTRY(xscale_coherent_user_range) | 264 | ENTRY(xscale_coherent_user_range) |
260 | bic r0, r0, #CACHELINESIZE - 1 | 265 | bic r0, r0, #CACHELINESIZE - 1 |
261 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | 266 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
267 | mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry | ||
262 | add r0, r0, #CACHELINESIZE | 268 | add r0, r0, #CACHELINESIZE |
263 | cmp r0, r1 | 269 | cmp r0, r1 |
264 | blo 1b | 270 | blo 1b |
265 | mov r0, #0 | 271 | mov r0, #0 |
266 | mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB | 272 | mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB |
267 | mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer | 273 | mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
268 | mov pc, lr | 274 | mov pc, lr |
269 | 275 | ||