diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/ppc/Kconfig | 17 | ||||
-rw-r--r-- | arch/ppc/Makefile | 3 | ||||
-rw-r--r-- | arch/ppc/kernel/Makefile | 2 | ||||
-rw-r--r-- | arch/ppc/kernel/cputable.c | 25 | ||||
-rw-r--r-- | arch/ppc/kernel/entry.S | 9 | ||||
-rw-r--r-- | arch/ppc/kernel/head_booke.h | 64 | ||||
-rw-r--r-- | arch/ppc/kernel/head_fsl_booke.S | 51 | ||||
-rw-r--r-- | arch/ppc/kernel/misc.S | 8 | ||||
-rw-r--r-- | arch/ppc/kernel/perfmon.c | 2 | ||||
-rw-r--r-- | arch/ppc/kernel/traps.c | 24 | ||||
-rw-r--r-- | arch/ppc/mm/fsl_booke_mmu.c | 2 |
11 files changed, 192 insertions, 15 deletions
diff --git a/arch/ppc/Kconfig b/arch/ppc/Kconfig index 848f43970a4b..979590a9baf9 100644 --- a/arch/ppc/Kconfig +++ b/arch/ppc/Kconfig | |||
@@ -88,6 +88,9 @@ config 8xx | |||
88 | depends on BROKEN | 88 | depends on BROKEN |
89 | bool "8xx" | 89 | bool "8xx" |
90 | 90 | ||
91 | config E200 | ||
92 | bool "e200" | ||
93 | |||
91 | config E500 | 94 | config E500 |
92 | bool "e500" | 95 | bool "e500" |
93 | 96 | ||
@@ -98,12 +101,12 @@ config PPC_FPU | |||
98 | 101 | ||
99 | config BOOKE | 102 | config BOOKE |
100 | bool | 103 | bool |
101 | depends on E500 | 104 | depends on E200 || E500 |
102 | default y | 105 | default y |
103 | 106 | ||
104 | config FSL_BOOKE | 107 | config FSL_BOOKE |
105 | bool | 108 | bool |
106 | depends on E500 | 109 | depends on E200 || E500 |
107 | default y | 110 | default y |
108 | 111 | ||
109 | config PTE_64BIT | 112 | config PTE_64BIT |
@@ -141,16 +144,16 @@ config ALTIVEC | |||
141 | 144 | ||
142 | config SPE | 145 | config SPE |
143 | bool "SPE Support" | 146 | bool "SPE Support" |
144 | depends on E500 | 147 | depends on E200 || E500 |
145 | ---help--- | 148 | ---help--- |
146 | This option enables kernel support for the Signal Processing | 149 | This option enables kernel support for the Signal Processing |
147 | Extensions (SPE) to the PowerPC processor. The kernel currently | 150 | Extensions (SPE) to the PowerPC processor. The kernel currently |
148 | supports saving and restoring SPE registers, and turning on the | 151 | supports saving and restoring SPE registers, and turning on the |
149 | 'spe enable' bit so user processes can execute SPE instructions. | 152 | 'spe enable' bit so user processes can execute SPE instructions. |
150 | 153 | ||
151 | This option is only usefully if you have a processor that supports | 154 | This option is only useful if you have a processor that supports |
152 | SPE (e500, otherwise known as 85xx series), but does not have any | 155 | SPE (e500, otherwise known as 85xx series), but does not have any |
153 | affect on a non-spe cpu (it does, however add code to the kernel). | 156 | effect on a non-spe cpu (it does, however add code to the kernel). |
154 | 157 | ||
155 | If in doubt, say Y here. | 158 | If in doubt, say Y here. |
156 | 159 | ||
@@ -200,7 +203,7 @@ config TAU_AVERAGE | |||
200 | 203 | ||
201 | config MATH_EMULATION | 204 | config MATH_EMULATION |
202 | bool "Math emulation" | 205 | bool "Math emulation" |
203 | depends on 4xx || 8xx || E500 | 206 | depends on 4xx || 8xx || E200 || E500 |
204 | ---help--- | 207 | ---help--- |
205 | Some PowerPC chips designed for embedded applications do not have | 208 | Some PowerPC chips designed for embedded applications do not have |
206 | a floating-point unit and therefore do not implement the | 209 | a floating-point unit and therefore do not implement the |
@@ -254,7 +257,7 @@ config PPC_STD_MMU | |||
254 | 257 | ||
255 | config NOT_COHERENT_CACHE | 258 | config NOT_COHERENT_CACHE |
256 | bool | 259 | bool |
257 | depends on 4xx || 8xx | 260 | depends on 4xx || 8xx || E200 |
258 | default y | 261 | default y |
259 | 262 | ||
260 | endmenu | 263 | endmenu |
diff --git a/arch/ppc/Makefile b/arch/ppc/Makefile index 0432a25b4735..f9b0d778dd82 100644 --- a/arch/ppc/Makefile +++ b/arch/ppc/Makefile | |||
@@ -29,7 +29,7 @@ CPP = $(CC) -E $(CFLAGS) | |||
29 | 29 | ||
30 | CHECKFLAGS += -D__powerpc__ | 30 | CHECKFLAGS += -D__powerpc__ |
31 | 31 | ||
32 | ifndef CONFIG_E500 | 32 | ifndef CONFIG_FSL_BOOKE |
33 | CFLAGS += -mstring | 33 | CFLAGS += -mstring |
34 | endif | 34 | endif |
35 | 35 | ||
@@ -38,6 +38,7 @@ cpu-as-$(CONFIG_4xx) += -Wa,-m405 | |||
38 | cpu-as-$(CONFIG_6xx) += -Wa,-maltivec | 38 | cpu-as-$(CONFIG_6xx) += -Wa,-maltivec |
39 | cpu-as-$(CONFIG_POWER4) += -Wa,-maltivec | 39 | cpu-as-$(CONFIG_POWER4) += -Wa,-maltivec |
40 | cpu-as-$(CONFIG_E500) += -Wa,-me500 | 40 | cpu-as-$(CONFIG_E500) += -Wa,-me500 |
41 | cpu-as-$(CONFIG_E200) += -Wa,-me200 | ||
41 | 42 | ||
42 | AFLAGS += $(cpu-as-y) | 43 | AFLAGS += $(cpu-as-y) |
43 | CFLAGS += $(cpu-as-y) | 44 | CFLAGS += $(cpu-as-y) |
diff --git a/arch/ppc/kernel/Makefile b/arch/ppc/kernel/Makefile index b284451802c9..8276c0b551d2 100644 --- a/arch/ppc/kernel/Makefile +++ b/arch/ppc/kernel/Makefile | |||
@@ -26,7 +26,9 @@ obj-$(CONFIG_KGDB) += ppc-stub.o | |||
26 | obj-$(CONFIG_SMP) += smp.o smp-tbsync.o | 26 | obj-$(CONFIG_SMP) += smp.o smp-tbsync.o |
27 | obj-$(CONFIG_TAU) += temp.o | 27 | obj-$(CONFIG_TAU) += temp.o |
28 | obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o | 28 | obj-$(CONFIG_ALTIVEC) += vecemu.o vector.o |
29 | ifndef CONFIG_E200 | ||
29 | obj-$(CONFIG_FSL_BOOKE) += perfmon_fsl_booke.o | 30 | obj-$(CONFIG_FSL_BOOKE) += perfmon_fsl_booke.o |
31 | endif | ||
30 | 32 | ||
31 | ifndef CONFIG_MATH_EMULATION | 33 | ifndef CONFIG_MATH_EMULATION |
32 | obj-$(CONFIG_8xx) += softemu8xx.o | 34 | obj-$(CONFIG_8xx) += softemu8xx.o |
diff --git a/arch/ppc/kernel/cputable.c b/arch/ppc/kernel/cputable.c index 01c226008dbf..50936cda0af9 100644 --- a/arch/ppc/kernel/cputable.c +++ b/arch/ppc/kernel/cputable.c | |||
@@ -903,7 +903,30 @@ struct cpu_spec cpu_specs[] = { | |||
903 | .dcache_bsize = 32, | 903 | .dcache_bsize = 32, |
904 | }, | 904 | }, |
905 | #endif /* CONFIG_44x */ | 905 | #endif /* CONFIG_44x */ |
906 | #ifdef CONFIG_E500 | 906 | #ifdef CONFIG_FSL_BOOKE |
907 | { /* e200z5 */ | ||
908 | .pvr_mask = 0xfff00000, | ||
909 | .pvr_value = 0x81000000, | ||
910 | .cpu_name = "e200z5", | ||
911 | /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ | ||
912 | .cpu_features = CPU_FTR_USE_TB, | ||
913 | .cpu_user_features = PPC_FEATURE_32 | | ||
914 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE | | ||
915 | PPC_FEATURE_UNIFIED_CACHE, | ||
916 | .dcache_bsize = 32, | ||
917 | }, | ||
918 | { /* e200z6 */ | ||
919 | .pvr_mask = 0xfff00000, | ||
920 | .pvr_value = 0x81100000, | ||
921 | .cpu_name = "e200z6", | ||
922 | /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */ | ||
923 | .cpu_features = CPU_FTR_USE_TB, | ||
924 | .cpu_user_features = PPC_FEATURE_32 | | ||
925 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP | | ||
926 | PPC_FEATURE_HAS_EFP_SINGLE | | ||
927 | PPC_FEATURE_UNIFIED_CACHE, | ||
928 | .dcache_bsize = 32, | ||
929 | }, | ||
907 | { /* e500 */ | 930 | { /* e500 */ |
908 | .pvr_mask = 0xffff0000, | 931 | .pvr_mask = 0xffff0000, |
909 | .pvr_value = 0x80200000, | 932 | .pvr_value = 0x80200000, |
diff --git a/arch/ppc/kernel/entry.S b/arch/ppc/kernel/entry.S index 8377b6ca26da..d4df68629cc6 100644 --- a/arch/ppc/kernel/entry.S +++ b/arch/ppc/kernel/entry.S | |||
@@ -60,6 +60,11 @@ mcheck_transfer_to_handler: | |||
60 | TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK) | 60 | TRANSFER_TO_HANDLER_EXC_LEVEL(MCHECK) |
61 | b transfer_to_handler_full | 61 | b transfer_to_handler_full |
62 | 62 | ||
63 | .globl debug_transfer_to_handler | ||
64 | debug_transfer_to_handler: | ||
65 | TRANSFER_TO_HANDLER_EXC_LEVEL(DEBUG) | ||
66 | b transfer_to_handler_full | ||
67 | |||
63 | .globl crit_transfer_to_handler | 68 | .globl crit_transfer_to_handler |
64 | crit_transfer_to_handler: | 69 | crit_transfer_to_handler: |
65 | TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT) | 70 | TRANSFER_TO_HANDLER_EXC_LEVEL(CRIT) |
@@ -835,6 +840,10 @@ ret_from_crit_exc: | |||
835 | RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) | 840 | RET_FROM_EXC_LEVEL(SPRN_CSRR0, SPRN_CSRR1, RFCI) |
836 | 841 | ||
837 | #ifdef CONFIG_BOOKE | 842 | #ifdef CONFIG_BOOKE |
843 | .globl ret_from_debug_exc | ||
844 | ret_from_debug_exc: | ||
845 | RET_FROM_EXC_LEVEL(SPRN_DSRR0, SPRN_DSRR1, RFDI) | ||
846 | |||
838 | .globl ret_from_mcheck_exc | 847 | .globl ret_from_mcheck_exc |
839 | ret_from_mcheck_exc: | 848 | ret_from_mcheck_exc: |
840 | RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI) | 849 | RET_FROM_EXC_LEVEL(SPRN_MCSRR0, SPRN_MCSRR1, RFMCI) |
diff --git a/arch/ppc/kernel/head_booke.h b/arch/ppc/kernel/head_booke.h index 9c50f9d2657c..9342acf12e72 100644 --- a/arch/ppc/kernel/head_booke.h +++ b/arch/ppc/kernel/head_booke.h | |||
@@ -49,6 +49,7 @@ | |||
49 | * | 49 | * |
50 | * On 40x critical is the only additional level | 50 | * On 40x critical is the only additional level |
51 | * On 44x/e500 we have critical and machine check | 51 | * On 44x/e500 we have critical and machine check |
52 | * On e200 we have critical and debug (machine check occurs via critical) | ||
52 | * | 53 | * |
53 | * Additionally we reserve a SPRG for each priority level so we can free up a | 54 | * Additionally we reserve a SPRG for each priority level so we can free up a |
54 | * GPR to use as the base for indirect access to the exception stacks. This | 55 | * GPR to use as the base for indirect access to the exception stacks. This |
@@ -60,12 +61,16 @@ | |||
60 | 61 | ||
61 | /* CRIT_SPRG only used in critical exception handling */ | 62 | /* CRIT_SPRG only used in critical exception handling */ |
62 | #define CRIT_SPRG SPRN_SPRG2 | 63 | #define CRIT_SPRG SPRN_SPRG2 |
63 | /* MCHECK_SPRG only used in critical exception handling */ | 64 | /* MCHECK_SPRG only used in machine check exception handling */ |
64 | #define MCHECK_SPRG SPRN_SPRG6W | 65 | #define MCHECK_SPRG SPRN_SPRG6W |
65 | 66 | ||
66 | #define MCHECK_STACK_TOP (exception_stack_top - 4096) | 67 | #define MCHECK_STACK_TOP (exception_stack_top - 4096) |
67 | #define CRIT_STACK_TOP (exception_stack_top) | 68 | #define CRIT_STACK_TOP (exception_stack_top) |
68 | 69 | ||
70 | /* only on e200 for now */ | ||
71 | #define DEBUG_STACK_TOP (exception_stack_top - 4096) | ||
72 | #define DEBUG_SPRG SPRN_SPRG6W | ||
73 | |||
69 | #ifdef CONFIG_SMP | 74 | #ifdef CONFIG_SMP |
70 | #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ | 75 | #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \ |
71 | mfspr r8,SPRN_PIR; \ | 76 | mfspr r8,SPRN_PIR; \ |
@@ -124,6 +129,8 @@ | |||
124 | 129 | ||
125 | #define CRITICAL_EXCEPTION_PROLOG \ | 130 | #define CRITICAL_EXCEPTION_PROLOG \ |
126 | EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) | 131 | EXC_LEVEL_EXCEPTION_PROLOG(CRIT, SPRN_CSRR0, SPRN_CSRR1) |
132 | #define DEBUG_EXCEPTION_PROLOG \ | ||
133 | EXC_LEVEL_EXCEPTION_PROLOG(DEBUG, SPRN_DSRR0, SPRN_DSRR1) | ||
127 | #define MCHECK_EXCEPTION_PROLOG \ | 134 | #define MCHECK_EXCEPTION_PROLOG \ |
128 | EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1) | 135 | EXC_LEVEL_EXCEPTION_PROLOG(MCHECK, SPRN_MCSRR0, SPRN_MCSRR1) |
129 | 136 | ||
@@ -205,6 +212,60 @@ label: | |||
205 | * save (and later restore) the MSR via SPRN_CSRR1, which will still have | 212 | * save (and later restore) the MSR via SPRN_CSRR1, which will still have |
206 | * the MSR_DE bit set. | 213 | * the MSR_DE bit set. |
207 | */ | 214 | */ |
215 | #ifdef CONFIG_E200 | ||
216 | #define DEBUG_EXCEPTION \ | ||
217 | START_EXCEPTION(Debug); \ | ||
218 | DEBUG_EXCEPTION_PROLOG; \ | ||
219 | \ | ||
220 | /* \ | ||
221 | * If there is a single step or branch-taken exception in an \ | ||
222 | * exception entry sequence, it was probably meant to apply to \ | ||
223 | * the code where the exception occurred (since exception entry \ | ||
224 | * doesn't turn off DE automatically). We simulate the effect \ | ||
225 | * of turning off DE on entry to an exception handler by turning \ | ||
226 | * off DE in the CSRR1 value and clearing the debug status. \ | ||
227 | */ \ | ||
228 | mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \ | ||
229 | andis. r10,r10,DBSR_IC@h; \ | ||
230 | beq+ 2f; \ | ||
231 | \ | ||
232 | lis r10,KERNELBASE@h; /* check if exception in vectors */ \ | ||
233 | ori r10,r10,KERNELBASE@l; \ | ||
234 | cmplw r12,r10; \ | ||
235 | blt+ 2f; /* addr below exception vectors */ \ | ||
236 | \ | ||
237 | lis r10,Debug@h; \ | ||
238 | ori r10,r10,Debug@l; \ | ||
239 | cmplw r12,r10; \ | ||
240 | bgt+ 2f; /* addr above exception vectors */ \ | ||
241 | \ | ||
242 | /* here it looks like we got an inappropriate debug exception. */ \ | ||
243 | 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \ | ||
244 | lis r10,DBSR_IC@h; /* clear the IC event */ \ | ||
245 | mtspr SPRN_DBSR,r10; \ | ||
246 | /* restore state and get out */ \ | ||
247 | lwz r10,_CCR(r11); \ | ||
248 | lwz r0,GPR0(r11); \ | ||
249 | lwz r1,GPR1(r11); \ | ||
250 | mtcrf 0x80,r10; \ | ||
251 | mtspr SPRN_DSRR0,r12; \ | ||
252 | mtspr SPRN_DSRR1,r9; \ | ||
253 | lwz r9,GPR9(r11); \ | ||
254 | lwz r12,GPR12(r11); \ | ||
255 | mtspr DEBUG_SPRG,r8; \ | ||
256 | BOOKE_LOAD_EXC_LEVEL_STACK(DEBUG); /* r8 points to the debug stack */ \ | ||
257 | lwz r10,GPR10-INT_FRAME_SIZE(r8); \ | ||
258 | lwz r11,GPR11-INT_FRAME_SIZE(r8); \ | ||
259 | mfspr r8,DEBUG_SPRG; \ | ||
260 | \ | ||
261 | RFDI; \ | ||
262 | b .; \ | ||
263 | \ | ||
264 | /* continue normal handling for a critical exception... */ \ | ||
265 | 2: mfspr r4,SPRN_DBSR; \ | ||
266 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | ||
267 | EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc) | ||
268 | #else | ||
208 | #define DEBUG_EXCEPTION \ | 269 | #define DEBUG_EXCEPTION \ |
209 | START_EXCEPTION(Debug); \ | 270 | START_EXCEPTION(Debug); \ |
210 | CRITICAL_EXCEPTION_PROLOG; \ | 271 | CRITICAL_EXCEPTION_PROLOG; \ |
@@ -257,6 +318,7 @@ label: | |||
257 | 2: mfspr r4,SPRN_DBSR; \ | 318 | 2: mfspr r4,SPRN_DBSR; \ |
258 | addi r3,r1,STACK_FRAME_OVERHEAD; \ | 319 | addi r3,r1,STACK_FRAME_OVERHEAD; \ |
259 | EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) | 320 | EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc) |
321 | #endif | ||
260 | 322 | ||
261 | #define INSTRUCTION_STORAGE_EXCEPTION \ | 323 | #define INSTRUCTION_STORAGE_EXCEPTION \ |
262 | START_EXCEPTION(InstructionStorage) \ | 324 | START_EXCEPTION(InstructionStorage) \ |
diff --git a/arch/ppc/kernel/head_fsl_booke.S b/arch/ppc/kernel/head_fsl_booke.S index ce36e88ba627..eb804b7a3cb2 100644 --- a/arch/ppc/kernel/head_fsl_booke.S +++ b/arch/ppc/kernel/head_fsl_booke.S | |||
@@ -102,6 +102,7 @@ invstr: mflr r6 /* Make it accessible */ | |||
102 | or r7,r7,r4 | 102 | or r7,r7,r4 |
103 | mtspr SPRN_MAS6,r7 | 103 | mtspr SPRN_MAS6,r7 |
104 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ | 104 | tlbsx 0,r6 /* search MSR[IS], SPID=PID0 */ |
105 | #ifndef CONFIG_E200 | ||
105 | mfspr r7,SPRN_MAS1 | 106 | mfspr r7,SPRN_MAS1 |
106 | andis. r7,r7,MAS1_VALID@h | 107 | andis. r7,r7,MAS1_VALID@h |
107 | bne match_TLB | 108 | bne match_TLB |
@@ -118,6 +119,7 @@ invstr: mflr r6 /* Make it accessible */ | |||
118 | or r7,r7,r4 | 119 | or r7,r7,r4 |
119 | mtspr SPRN_MAS6,r7 | 120 | mtspr SPRN_MAS6,r7 |
120 | tlbsx 0,r6 /* Fall through, we had to match */ | 121 | tlbsx 0,r6 /* Fall through, we had to match */ |
122 | #endif | ||
121 | match_TLB: | 123 | match_TLB: |
122 | mfspr r7,SPRN_MAS0 | 124 | mfspr r7,SPRN_MAS0 |
123 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ | 125 | rlwinm r3,r7,16,20,31 /* Extract MAS0(Entry) */ |
@@ -196,8 +198,10 @@ skpinv: addi r6,r6,1 /* Increment */ | |||
196 | /* 4. Clear out PIDs & Search info */ | 198 | /* 4. Clear out PIDs & Search info */ |
197 | li r6,0 | 199 | li r6,0 |
198 | mtspr SPRN_PID0,r6 | 200 | mtspr SPRN_PID0,r6 |
201 | #ifndef CONFIG_E200 | ||
199 | mtspr SPRN_PID1,r6 | 202 | mtspr SPRN_PID1,r6 |
200 | mtspr SPRN_PID2,r6 | 203 | mtspr SPRN_PID2,r6 |
204 | #endif | ||
201 | mtspr SPRN_MAS6,r6 | 205 | mtspr SPRN_MAS6,r6 |
202 | 206 | ||
203 | /* 5. Invalidate mapping we started in */ | 207 | /* 5. Invalidate mapping we started in */ |
@@ -277,7 +281,9 @@ skpinv: addi r6,r6,1 /* Increment */ | |||
277 | SET_IVOR(32, SPEUnavailable); | 281 | SET_IVOR(32, SPEUnavailable); |
278 | SET_IVOR(33, SPEFloatingPointData); | 282 | SET_IVOR(33, SPEFloatingPointData); |
279 | SET_IVOR(34, SPEFloatingPointRound); | 283 | SET_IVOR(34, SPEFloatingPointRound); |
284 | #ifndef CONFIG_E200 | ||
280 | SET_IVOR(35, PerformanceMonitor); | 285 | SET_IVOR(35, PerformanceMonitor); |
286 | #endif | ||
281 | 287 | ||
282 | /* Establish the interrupt vector base */ | 288 | /* Establish the interrupt vector base */ |
283 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ | 289 | lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */ |
@@ -285,6 +291,9 @@ skpinv: addi r6,r6,1 /* Increment */ | |||
285 | 291 | ||
286 | /* Setup the defaults for TLB entries */ | 292 | /* Setup the defaults for TLB entries */ |
287 | li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l | 293 | li r2,(MAS4_TSIZED(BOOKE_PAGESZ_4K))@l |
294 | #ifdef CONFIG_E200 | ||
295 | oris r2,r2,MAS4_TLBSELD(1)@h | ||
296 | #endif | ||
288 | mtspr SPRN_MAS4, r2 | 297 | mtspr SPRN_MAS4, r2 |
289 | 298 | ||
290 | #if 0 | 299 | #if 0 |
@@ -293,6 +302,12 @@ skpinv: addi r6,r6,1 /* Increment */ | |||
293 | oris r2,r2,HID0_DOZE@h | 302 | oris r2,r2,HID0_DOZE@h |
294 | mtspr SPRN_HID0, r2 | 303 | mtspr SPRN_HID0, r2 |
295 | #endif | 304 | #endif |
305 | #ifdef CONFIG_E200 | ||
306 | /* enable dedicated debug exception handling resources (Debug APU) */ | ||
307 | mfspr r2,SPRN_HID0 | ||
308 | ori r2,r2,HID0_DAPUEN@l | ||
309 | mtspr SPRN_HID0,r2 | ||
310 | #endif | ||
296 | 311 | ||
297 | #if !defined(CONFIG_BDI_SWITCH) | 312 | #if !defined(CONFIG_BDI_SWITCH) |
298 | /* | 313 | /* |
@@ -414,7 +429,12 @@ interrupt_base: | |||
414 | CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) | 429 | CRITICAL_EXCEPTION(0x0100, CriticalInput, UnknownException) |
415 | 430 | ||
416 | /* Machine Check Interrupt */ | 431 | /* Machine Check Interrupt */ |
432 | #ifdef CONFIG_E200 | ||
433 | /* no RFMCI, MCSRRs on E200 */ | ||
434 | CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException) | ||
435 | #else | ||
417 | MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) | 436 | MCHECK_EXCEPTION(0x0200, MachineCheck, MachineCheckException) |
437 | #endif | ||
418 | 438 | ||
419 | /* Data Storage Interrupt */ | 439 | /* Data Storage Interrupt */ |
420 | START_EXCEPTION(DataStorage) | 440 | START_EXCEPTION(DataStorage) |
@@ -520,8 +540,13 @@ interrupt_base: | |||
520 | #ifdef CONFIG_PPC_FPU | 540 | #ifdef CONFIG_PPC_FPU |
521 | FP_UNAVAILABLE_EXCEPTION | 541 | FP_UNAVAILABLE_EXCEPTION |
522 | #else | 542 | #else |
543 | #ifdef CONFIG_E200 | ||
544 | /* E200 treats 'normal' floating point instructions as FP Unavail exception */ | ||
545 | EXCEPTION(0x0800, FloatingPointUnavailable, ProgramCheckException, EXC_XFER_EE) | ||
546 | #else | ||
523 | EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) | 547 | EXCEPTION(0x0800, FloatingPointUnavailable, UnknownException, EXC_XFER_EE) |
524 | #endif | 548 | #endif |
549 | #endif | ||
525 | 550 | ||
526 | /* System Call Interrupt */ | 551 | /* System Call Interrupt */ |
527 | START_EXCEPTION(SystemCall) | 552 | START_EXCEPTION(SystemCall) |
@@ -691,6 +716,7 @@ interrupt_base: | |||
691 | /* | 716 | /* |
692 | * Local functions | 717 | * Local functions |
693 | */ | 718 | */ |
719 | |||
694 | /* | 720 | /* |
695 | * Data TLB exceptions will bail out to this point | 721 | * Data TLB exceptions will bail out to this point |
696 | * if they can't resolve the lightweight TLB fault. | 722 | * if they can't resolve the lightweight TLB fault. |
@@ -761,6 +787,31 @@ END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) | |||
761 | 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ | 787 | 2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ |
762 | mtspr SPRN_MAS3, r11 | 788 | mtspr SPRN_MAS3, r11 |
763 | #endif | 789 | #endif |
790 | #ifdef CONFIG_E200 | ||
791 | /* Round robin TLB1 entries assignment */ | ||
792 | mfspr r12, SPRN_MAS0 | ||
793 | |||
794 | /* Extract TLB1CFG(NENTRY) */ | ||
795 | mfspr r11, SPRN_TLB1CFG | ||
796 | andi. r11, r11, 0xfff | ||
797 | |||
798 | /* Extract MAS0(NV) */ | ||
799 | andi. r13, r12, 0xfff | ||
800 | addi r13, r13, 1 | ||
801 | cmpw 0, r13, r11 | ||
802 | addi r12, r12, 1 | ||
803 | |||
804 | /* check if we need to wrap */ | ||
805 | blt 7f | ||
806 | |||
807 | /* wrap back to first free tlbcam entry */ | ||
808 | lis r13, tlbcam_index@ha | ||
809 | lwz r13, tlbcam_index@l(r13) | ||
810 | rlwimi r12, r13, 0, 20, 31 | ||
811 | 7: | ||
812 | mtspr SPRN_MAS0,r12 | ||
813 | #endif /* CONFIG_E200 */ | ||
814 | |||
764 | tlbwe | 815 | tlbwe |
765 | 816 | ||
766 | /* Done...restore registers and get out of here. */ | 817 | /* Done...restore registers and get out of here. */ |
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index 7329ef177a18..a3132f8e799c 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S | |||
@@ -593,6 +593,14 @@ _GLOBAL(flush_instruction_cache) | |||
593 | iccci 0,r3 | 593 | iccci 0,r3 |
594 | #endif | 594 | #endif |
595 | #elif CONFIG_FSL_BOOKE | 595 | #elif CONFIG_FSL_BOOKE |
596 | BEGIN_FTR_SECTION | ||
597 | mfspr r3,SPRN_L1CSR0 | ||
598 | ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC | ||
599 | /* msync; isync recommended here */ | ||
600 | mtspr SPRN_L1CSR0,r3 | ||
601 | isync | ||
602 | blr | ||
603 | END_FTR_SECTION_IFCLR(CPU_FTR_SPLIT_ID_CACHE) | ||
596 | mfspr r3,SPRN_L1CSR1 | 604 | mfspr r3,SPRN_L1CSR1 |
597 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR | 605 | ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR |
598 | mtspr SPRN_L1CSR1,r3 | 606 | mtspr SPRN_L1CSR1,r3 |
diff --git a/arch/ppc/kernel/perfmon.c b/arch/ppc/kernel/perfmon.c index 918f6b252e45..fa1dad96b830 100644 --- a/arch/ppc/kernel/perfmon.c +++ b/arch/ppc/kernel/perfmon.c | |||
@@ -36,7 +36,7 @@ | |||
36 | /* A lock to regulate grabbing the interrupt */ | 36 | /* A lock to regulate grabbing the interrupt */ |
37 | DEFINE_SPINLOCK(perfmon_lock); | 37 | DEFINE_SPINLOCK(perfmon_lock); |
38 | 38 | ||
39 | #ifdef CONFIG_FSL_BOOKE | 39 | #if defined (CONFIG_FSL_BOOKE) && !defined (CONFIG_E200) |
40 | static void dummy_perf(struct pt_regs *regs) | 40 | static void dummy_perf(struct pt_regs *regs) |
41 | { | 41 | { |
42 | unsigned int pmgc0 = mfpmr(PMRN_PMGC0); | 42 | unsigned int pmgc0 = mfpmr(PMRN_PMGC0); |
diff --git a/arch/ppc/kernel/traps.c b/arch/ppc/kernel/traps.c index 2ca8ecfeefd9..9e6ae5696650 100644 --- a/arch/ppc/kernel/traps.c +++ b/arch/ppc/kernel/traps.c | |||
@@ -173,13 +173,13 @@ static inline int check_io_access(struct pt_regs *regs) | |||
173 | /* On 4xx, the reason for the machine check or program exception | 173 | /* On 4xx, the reason for the machine check or program exception |
174 | is in the ESR. */ | 174 | is in the ESR. */ |
175 | #define get_reason(regs) ((regs)->dsisr) | 175 | #define get_reason(regs) ((regs)->dsisr) |
176 | #ifndef CONFIG_E500 | 176 | #ifndef CONFIG_FSL_BOOKE |
177 | #define get_mc_reason(regs) ((regs)->dsisr) | 177 | #define get_mc_reason(regs) ((regs)->dsisr) |
178 | #else | 178 | #else |
179 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) | 179 | #define get_mc_reason(regs) (mfspr(SPRN_MCSR)) |
180 | #endif | 180 | #endif |
181 | #define REASON_FP ESR_FP | 181 | #define REASON_FP ESR_FP |
182 | #define REASON_ILLEGAL ESR_PIL | 182 | #define REASON_ILLEGAL (ESR_PIL | ESR_PUO) |
183 | #define REASON_PRIVILEGED ESR_PPR | 183 | #define REASON_PRIVILEGED ESR_PPR |
184 | #define REASON_TRAP ESR_PTR | 184 | #define REASON_TRAP ESR_PTR |
185 | 185 | ||
@@ -302,7 +302,25 @@ void MachineCheckException(struct pt_regs *regs) | |||
302 | printk("Bus - Instruction Parity Error\n"); | 302 | printk("Bus - Instruction Parity Error\n"); |
303 | if (reason & MCSR_BUS_RPERR) | 303 | if (reason & MCSR_BUS_RPERR) |
304 | printk("Bus - Read Parity Error\n"); | 304 | printk("Bus - Read Parity Error\n"); |
305 | #else /* !CONFIG_4xx && !CONFIG_E500 */ | 305 | #elif defined (CONFIG_E200) |
306 | printk("Machine check in kernel mode.\n"); | ||
307 | printk("Caused by (from MCSR=%lx): ", reason); | ||
308 | |||
309 | if (reason & MCSR_MCP) | ||
310 | printk("Machine Check Signal\n"); | ||
311 | if (reason & MCSR_CP_PERR) | ||
312 | printk("Cache Push Parity Error\n"); | ||
313 | if (reason & MCSR_CPERR) | ||
314 | printk("Cache Parity Error\n"); | ||
315 | if (reason & MCSR_EXCP_ERR) | ||
316 | printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n"); | ||
317 | if (reason & MCSR_BUS_IRERR) | ||
318 | printk("Bus - Read Bus Error on instruction fetch\n"); | ||
319 | if (reason & MCSR_BUS_DRERR) | ||
320 | printk("Bus - Read Bus Error on data load\n"); | ||
321 | if (reason & MCSR_BUS_WRERR) | ||
322 | printk("Bus - Write Bus Error on buffered store or cache line push\n"); | ||
323 | #else /* !CONFIG_4xx && !CONFIG_E500 && !CONFIG_E200 */ | ||
306 | printk("Machine check in kernel mode.\n"); | 324 | printk("Machine check in kernel mode.\n"); |
307 | printk("Caused by (from SRR1=%lx): ", reason); | 325 | printk("Caused by (from SRR1=%lx): ", reason); |
308 | switch (reason & 0x601F0000) { | 326 | switch (reason & 0x601F0000) { |
diff --git a/arch/ppc/mm/fsl_booke_mmu.c b/arch/ppc/mm/fsl_booke_mmu.c index e07990efa046..9fa884de5c7c 100644 --- a/arch/ppc/mm/fsl_booke_mmu.c +++ b/arch/ppc/mm/fsl_booke_mmu.c | |||
@@ -126,7 +126,7 @@ void settlbcam(int index, unsigned long virt, phys_addr_t phys, | |||
126 | flags |= _PAGE_COHERENT; | 126 | flags |= _PAGE_COHERENT; |
127 | #endif | 127 | #endif |
128 | 128 | ||
129 | TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index); | 129 | TLBCAM[index].MAS0 = MAS0_TLBSEL(1) | MAS0_ESEL(index) | MAS0_NV(index+1); |
130 | TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); | 130 | TLBCAM[index].MAS1 = MAS1_VALID | MAS1_IPROT | MAS1_TSIZE(tsize) | MAS1_TID(pid); |
131 | TLBCAM[index].MAS2 = virt & PAGE_MASK; | 131 | TLBCAM[index].MAS2 = virt & PAGE_MASK; |
132 | 132 | ||