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-rw-r--r--arch/sparc/include/asm/spitfire.h4
-rw-r--r--arch/sparc/kernel/Makefile2
-rw-r--r--arch/sparc/kernel/cpu.c (renamed from arch/sparc/kernel/cpu_32.c)91
-rw-r--r--arch/sparc/kernel/cpu_64.c167
4 files changed, 95 insertions, 169 deletions
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index 985ea7e31992..f0d0c40c44da 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -6,6 +6,8 @@
6#ifndef _SPARC64_SPITFIRE_H 6#ifndef _SPARC64_SPITFIRE_H
7#define _SPARC64_SPITFIRE_H 7#define _SPARC64_SPITFIRE_H
8 8
9#ifdef CONFIG_SPARC64
10
9#include <asm/asi.h> 11#include <asm/asi.h>
10 12
11/* The following register addresses are accessible via ASI_DMMU 13/* The following register addresses are accessible via ASI_DMMU
@@ -338,5 +340,5 @@ static inline void cheetah_put_itlb_data(int entry, unsigned long data)
338} 340}
339 341
340#endif /* !(__ASSEMBLY__) */ 342#endif /* !(__ASSEMBLY__) */
341 343#endif /* CONFIG_SPARC64 */
342#endif /* !(_SPARC64_SPITFIRE_H) */ 344#endif /* !(_SPARC64_SPITFIRE_H) */
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 04c74d00f832..0ba314b7f111 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -27,7 +27,7 @@ obj-y += sys_sparc_$(BITS).o
27obj-$(CONFIG_SPARC32) += systbls_32.o 27obj-$(CONFIG_SPARC32) += systbls_32.o
28obj-y += time_$(BITS).o 28obj-y += time_$(BITS).o
29obj-$(CONFIG_SPARC32) += windows.o 29obj-$(CONFIG_SPARC32) += windows.o
30obj-y += cpu_$(BITS).o 30obj-y += cpu.o
31obj-$(CONFIG_SPARC32) += devices.o 31obj-$(CONFIG_SPARC32) += devices.o
32obj-$(CONFIG_SPARC32) += tadpole.o 32obj-$(CONFIG_SPARC32) += tadpole.o
33obj-$(CONFIG_SPARC32) += tick14.o 33obj-$(CONFIG_SPARC32) += tick14.o
diff --git a/arch/sparc/kernel/cpu_32.c b/arch/sparc/kernel/cpu.c
index 60528227e591..6c2da2420f76 100644
--- a/arch/sparc/kernel/cpu_32.c
+++ b/arch/sparc/kernel/cpu.c
@@ -8,6 +8,8 @@
8#include <linux/init.h> 8#include <linux/init.h>
9#include <linux/smp.h> 9#include <linux/smp.h>
10#include <linux/threads.h> 10#include <linux/threads.h>
11
12#include <asm/spitfire.h>
11#include <asm/oplib.h> 13#include <asm/oplib.h>
12#include <asm/page.h> 14#include <asm/page.h>
13#include <asm/head.h> 15#include <asm/head.h>
@@ -176,6 +178,52 @@ static const struct manufacturer_info __initconst manufacturer_info[] = {
176 FPU(3, "Fujitsu or Weitek on-chip FPU"), 178 FPU(3, "Fujitsu or Weitek on-chip FPU"),
177 FPU(-1, NULL) 179 FPU(-1, NULL)
178 } 180 }
181},{
182 0x17,
183 .cpu_info = {
184 CPU(0x10, "TI UltraSparc I (SpitFire)"),
185 CPU(0x11, "TI UltraSparc II (BlackBird)"),
186 CPU(0x12, "TI UltraSparc IIi (Sabre)"),
187 CPU(0x13, "TI UltraSparc IIe (Hummingbird)"),
188 CPU(-1, NULL)
189 },
190 .fpu_info = {
191 FPU(0x10, "UltraSparc I integrated FPU"),
192 FPU(0x11, "UltraSparc II integrated FPU"),
193 FPU(0x12, "UltraSparc IIi integrated FPU"),
194 FPU(0x13, "UltraSparc IIe integrated FPU"),
195 FPU(-1, NULL)
196 }
197},{
198 0x22,
199 .cpu_info = {
200 CPU(0x10, "TI UltraSparc I (SpitFire)"),
201 CPU(-1, NULL)
202 },
203 .fpu_info = {
204 FPU(0x10, "UltraSparc I integrated FPU"),
205 FPU(-1, NULL)
206 }
207},{
208 0x3e,
209 .cpu_info = {
210 CPU(0x14, "TI UltraSparc III (Cheetah)"),
211 CPU(0x15, "TI UltraSparc III+ (Cheetah+)"),
212 CPU(0x16, "TI UltraSparc IIIi (Jalapeno)"),
213 CPU(0x18, "TI UltraSparc IV (Jaguar)"),
214 CPU(0x19, "TI UltraSparc IV+ (Panther)"),
215 CPU(0x22, "TI UltraSparc IIIi+ (Serrano)"),
216 CPU(-1, NULL)
217 },
218 .fpu_info = {
219 FPU(0x14, "UltraSparc III integrated FPU"),
220 FPU(0x15, "UltraSparc III+ integrated FPU"),
221 FPU(0x16, "UltraSparc IIIi integrated FPU"),
222 FPU(0x18, "UltraSparc IV integrated FPU"),
223 FPU(0x19, "UltraSparc IV+ integrated FPU"),
224 FPU(0x22, "UltraSparc IIIi+ integrated FPU"),
225 FPU(-1, NULL)
226 }
179}}; 227}};
180 228
181/* In order to get the fpu type correct, you need to take the IDPROM's 229/* In order to get the fpu type correct, you need to take the IDPROM's
@@ -230,6 +278,7 @@ static void set_cpu_and_fpu(int psr_impl, int psr_vers, int fpu_vers)
230 } 278 }
231} 279}
232 280
281#ifdef CONFIG_SPARC32
233void __cpuinit cpu_probe(void) 282void __cpuinit cpu_probe(void)
234{ 283{
235 int psr_impl, psr_vers, fpu_vers; 284 int psr_impl, psr_vers, fpu_vers;
@@ -245,3 +294,45 @@ void __cpuinit cpu_probe(void)
245 294
246 set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers); 295 set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
247} 296}
297#else
298static void __init sun4v_cpu_probe(void)
299{
300 switch (sun4v_chip_type) {
301 case SUN4V_CHIP_NIAGARA1:
302 sparc_cpu_type = "UltraSparc T1 (Niagara)";
303 sparc_fpu_type = "UltraSparc T1 integrated FPU";
304 break;
305
306 case SUN4V_CHIP_NIAGARA2:
307 sparc_cpu_type = "UltraSparc T2 (Niagara2)";
308 sparc_fpu_type = "UltraSparc T2 integrated FPU";
309 break;
310
311 default:
312 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
313 prom_cpu_compatible);
314 sparc_cpu_type = "Unknown SUN4V CPU";
315 sparc_fpu_type = "Unknown SUN4V FPU";
316 break;
317 }
318}
319
320static int __init cpu_type_probe(void)
321{
322 if (tlb_type == hypervisor) {
323 sun4v_cpu_probe();
324 } else {
325 unsigned long ver;
326 int manuf, impl;
327
328 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
329
330 manuf = ((ver >> 48) & 0xffff);
331 impl = ((ver >> 32) & 0xffff);
332 set_cpu_and_fpu(manuf, impl, impl);
333 }
334 return 0;
335}
336
337arch_initcall(cpu_type_probe);
338#endif
diff --git a/arch/sparc/kernel/cpu_64.c b/arch/sparc/kernel/cpu_64.c
deleted file mode 100644
index 4a81ed744477..000000000000
--- a/arch/sparc/kernel/cpu_64.c
+++ /dev/null
@@ -1,167 +0,0 @@
1/* cpu.c: Dinky routines to look for the kind of Sparc cpu
2 * we are on.
3 *
4 * Copyright (C) 1996, 2007, 2008 David S. Miller (davem@davemloft.net)
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/sched.h>
10#include <linux/smp.h>
11#include <asm/asi.h>
12#include <asm/system.h>
13#include <asm/fpumacro.h>
14#include <asm/cpudata.h>
15#include <asm/spitfire.h>
16#include <asm/oplib.h>
17
18#include "entry.h"
19#include "kernel.h"
20
21DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
22
23struct cpu_chip_info {
24 unsigned short manuf;
25 unsigned short impl;
26 const char *cpu_name;
27 const char *fp_name;
28};
29
30static const struct cpu_chip_info cpu_chips[] = {
31 {
32 .manuf = 0x17,
33 .impl = 0x10,
34 .cpu_name = "TI UltraSparc I (SpitFire)",
35 .fp_name = "UltraSparc I integrated FPU",
36 },
37 {
38 .manuf = 0x22,
39 .impl = 0x10,
40 .cpu_name = "TI UltraSparc I (SpitFire)",
41 .fp_name = "UltraSparc I integrated FPU",
42 },
43 {
44 .manuf = 0x17,
45 .impl = 0x11,
46 .cpu_name = "TI UltraSparc II (BlackBird)",
47 .fp_name = "UltraSparc II integrated FPU",
48 },
49 {
50 .manuf = 0x17,
51 .impl = 0x12,
52 .cpu_name = "TI UltraSparc IIi (Sabre)",
53 .fp_name = "UltraSparc IIi integrated FPU",
54 },
55 {
56 .manuf = 0x17,
57 .impl = 0x13,
58 .cpu_name = "TI UltraSparc IIe (Hummingbird)",
59 .fp_name = "UltraSparc IIe integrated FPU",
60 },
61 {
62 .manuf = 0x3e,
63 .impl = 0x14,
64 .cpu_name = "TI UltraSparc III (Cheetah)",
65 .fp_name = "UltraSparc III integrated FPU",
66 },
67 {
68 .manuf = 0x3e,
69 .impl = 0x15,
70 .cpu_name = "TI UltraSparc III+ (Cheetah+)",
71 .fp_name = "UltraSparc III+ integrated FPU",
72 },
73 {
74 .manuf = 0x3e,
75 .impl = 0x16,
76 .cpu_name = "TI UltraSparc IIIi (Jalapeno)",
77 .fp_name = "UltraSparc IIIi integrated FPU",
78 },
79 {
80 .manuf = 0x3e,
81 .impl = 0x18,
82 .cpu_name = "TI UltraSparc IV (Jaguar)",
83 .fp_name = "UltraSparc IV integrated FPU",
84 },
85 {
86 .manuf = 0x3e,
87 .impl = 0x19,
88 .cpu_name = "TI UltraSparc IV+ (Panther)",
89 .fp_name = "UltraSparc IV+ integrated FPU",
90 },
91 {
92 .manuf = 0x3e,
93 .impl = 0x22,
94 .cpu_name = "TI UltraSparc IIIi+ (Serrano)",
95 .fp_name = "UltraSparc IIIi+ integrated FPU",
96 },
97};
98
99#define NSPARCCHIPS ARRAY_SIZE(linux_sparc_chips)
100
101const char *sparc_cpu_type;
102const char *sparc_fpu_type;
103
104static void __init sun4v_cpu_probe(void)
105{
106 switch (sun4v_chip_type) {
107 case SUN4V_CHIP_NIAGARA1:
108 sparc_cpu_type = "UltraSparc T1 (Niagara)";
109 sparc_fpu_type = "UltraSparc T1 integrated FPU";
110 break;
111
112 case SUN4V_CHIP_NIAGARA2:
113 sparc_cpu_type = "UltraSparc T2 (Niagara2)";
114 sparc_fpu_type = "UltraSparc T2 integrated FPU";
115 break;
116
117 default:
118 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
119 prom_cpu_compatible);
120 sparc_cpu_type = "Unknown SUN4V CPU";
121 sparc_fpu_type = "Unknown SUN4V FPU";
122 break;
123 }
124}
125
126static const struct cpu_chip_info * __init find_cpu_chip(unsigned short manuf,
127 unsigned short impl)
128{
129 int i;
130
131 for (i = 0; i < ARRAY_SIZE(cpu_chips); i++) {
132 const struct cpu_chip_info *p = &cpu_chips[i];
133
134 if (p->manuf == manuf && p->impl == impl)
135 return p;
136 }
137 return NULL;
138}
139
140static int __init cpu_type_probe(void)
141{
142 if (tlb_type == hypervisor) {
143 sun4v_cpu_probe();
144 } else {
145 unsigned long ver, manuf, impl;
146 const struct cpu_chip_info *p;
147
148 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
149
150 manuf = ((ver >> 48) & 0xffff);
151 impl = ((ver >> 32) & 0xffff);
152
153 p = find_cpu_chip(manuf, impl);
154 if (p) {
155 sparc_cpu_type = p->cpu_name;
156 sparc_fpu_type = p->fp_name;
157 } else {
158 printk(KERN_ERR "CPU: Unknown chip, manuf[%lx] impl[%lx]\n",
159 manuf, impl);
160 sparc_cpu_type = "Unknown CPU";
161 sparc_fpu_type = "Unknown FPU";
162 }
163 }
164 return 0;
165}
166
167arch_initcall(cpu_type_probe);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-15 15:59:52 -0500