11 files changed, 243 insertions, 261 deletions

diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 07a56ff61494..4a2af55e134b 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -31,8 +31,3 @@ head-y			:= head.o
 obj-$(CONFIG_DEBUG_LL)  += debug.o
 
 extra-y := $(head-y) init_task.o vmlinux.lds
-
-# Spell out some dependencies that aren't automatically figured out
-$(obj)/entry-armv.o:    $(obj)/entry-header.S include/asm-arm/constants.h
-$(obj)/entry-common.o:  $(obj)/entry-header.S include/asm-arm/constants.h \
-                        $(obj)/calls.S
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 99d43259ff89..c1ff4d1f1bfd 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -64,6 +64,26 @@ int main(void)
   DEFINE(TI_VFPSTATE,           offsetof(struct thread_info, vfpstate));
   DEFINE(TI_IWMMXT_STATE,       (offsetof(struct thread_info, fpstate)+4)&~7);
   BLANK();
+  DEFINE(S_R0,                  offsetof(struct pt_regs, ARM_r0));
+  DEFINE(S_R1,                  offsetof(struct pt_regs, ARM_r1));
+  DEFINE(S_R2,                  offsetof(struct pt_regs, ARM_r2));
+  DEFINE(S_R3,                  offsetof(struct pt_regs, ARM_r3));
+  DEFINE(S_R4,                  offsetof(struct pt_regs, ARM_r4));
+  DEFINE(S_R5,                  offsetof(struct pt_regs, ARM_r5));
+  DEFINE(S_R6,                  offsetof(struct pt_regs, ARM_r6));
+  DEFINE(S_R7,                  offsetof(struct pt_regs, ARM_r7));
+  DEFINE(S_R8,                  offsetof(struct pt_regs, ARM_r8));
+  DEFINE(S_R9,                  offsetof(struct pt_regs, ARM_r9));
+  DEFINE(S_R10,                 offsetof(struct pt_regs, ARM_r10));
+  DEFINE(S_FP,                  offsetof(struct pt_regs, ARM_fp));
+  DEFINE(S_IP,                  offsetof(struct pt_regs, ARM_ip));
+  DEFINE(S_SP,                  offsetof(struct pt_regs, ARM_sp));
+  DEFINE(S_LR,                  offsetof(struct pt_regs, ARM_lr));
+  DEFINE(S_PC,                  offsetof(struct pt_regs, ARM_pc));
+  DEFINE(S_PSR,                 offsetof(struct pt_regs, ARM_cpsr));
+  DEFINE(S_OLD_R0,              offsetof(struct pt_regs, ARM_ORIG_r0));
+  DEFINE(S_FRAME_SIZE,          sizeof(struct pt_regs));
+  BLANK();
 #if __LINUX_ARM_ARCH__ >= 6
   DEFINE(MM_CONTEXT_ID,         offsetof(struct mm_struct, context.id));
   BLANK();
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb27c317d94b..2a5c3fe09a95 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -14,12 +14,12 @@
  *  it to save wrong values...  Be aware!
  */
 #include <linux/config.h>
-#include <linux/init.h>
 
-#include <asm/thread_info.h>
 #include <asm/glue.h>
-#include <asm/ptrace.h>
 #include <asm/vfpmacros.h>
+#include <asm/hardware.h>               @ should be moved into entry-macro.S
+#include <asm/arch/irqs.h>              @ should be moved into entry-macro.S
+#include <asm/arch/entry-macro.S>
 
 #include "entry-header.S"
 
@@ -118,7 +118,7 @@ __dabt_svc:
         @
         @ IRQs off again before pulling preserved data off the stack
         @
-        disable_irq r0
+        disable_irq
 
         @
         @ restore SPSR and restart the instruction
@@ -198,7 +198,7 @@ __und_svc:
         @
         @ IRQs off again before pulling preserved data off the stack
         @
-1:      disable_irq r0
+1:      disable_irq
 
         @
         @ restore SPSR and restart the instruction
@@ -232,7 +232,7 @@ __pabt_svc:
         @
         @ IRQs off again before pulling preserved data off the stack
         @
-        disable_irq r0
+        disable_irq
 
         @
         @ restore SPSR and restart the instruction
@@ -316,7 +316,7 @@ __dabt_usr:
         @
         @ IRQs on, then call the main handler
         @
-        enable_irq r2
+        enable_irq
         mov     r2, sp
         adr     lr, ret_from_exception
         b       do_DataAbort
@@ -418,7 +418,7 @@ call_fpe:
         movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
         bcs     iwmmxt_task_enable
 #endif
-        enable_irq r7
+        enable_irq
         add     pc, pc, r8, lsr #6
         mov     r0, r0
 
@@ -472,7 +472,7 @@ fpundefinstr:
 __pabt_usr:
         usr_entry abt
 
-        enable_irq r0                           @ Enable interrupts
+        enable_irq                              @ Enable interrupts
         mov     r0, r2                          @ address (pc)
         mov     r1, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
@@ -522,8 +522,9 @@ ENTRY(__switch_to)
 /*
  * Vector stubs.
  *
- * This code is copied to 0x200 or 0xffff0200 so we can use branches in the
- * vectors, rather than ldr's.
+ * This code is copied to 0xffff0200 so we can use branches in the
+ * vectors, rather than ldr's.  Note that this code must not
+ * exceed 0x300 bytes.
  *
  * Common stub entry macro:
  *   Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
@@ -544,7 +545,7 @@ vector_\name:
         @
         mrs     r13, cpsr
         bic     r13, r13, #MODE_MASK
-        orr     r13, r13, #MODE_SVC
+        orr     r13, r13, #SVC_MODE
         msr     spsr_cxsf, r13                  @ switch to SVC_32 mode
 
         and     lr, lr, #15
@@ -552,6 +553,7 @@ vector_\name:
         movs    pc, lr                          @ Changes mode and branches
         .endm
 
+        .globl  __stubs_start
 __stubs_start:
 /*
  * Interrupt dispatcher
@@ -686,37 +688,24 @@ vector_addrexcptn:
 .LCsabt:
         .word   __temp_abt
 
+        .globl  __stubs_end
 __stubs_end:
 
-        .equ    __real_stubs_start, .LCvectors + 0x200
+        .equ    stubs_offset, __vectors_start + 0x200 - __stubs_start
 
-.LCvectors:
+        .globl  __vectors_start
+__vectors_start:
         swi     SYS_ERROR0
-        b       __real_stubs_start + (vector_und - __stubs_start)
-        ldr     pc, __real_stubs_start + (.LCvswi - __stubs_start)
-        b       __real_stubs_start + (vector_pabt - __stubs_start)
-        b       __real_stubs_start + (vector_dabt - __stubs_start)
-        b       __real_stubs_start + (vector_addrexcptn - __stubs_start)
-        b       __real_stubs_start + (vector_irq - __stubs_start)
-        b       __real_stubs_start + (vector_fiq - __stubs_start)
-
-ENTRY(__trap_init)
-        stmfd   sp!, {r4 - r6, lr}
-
-        mov     r0, #0xff000000
-        orr     r0, r0, #0x00ff0000             @ high vectors position
-        adr     r1, .LCvectors                  @ set up the vectors
-        ldmia   r1, {r1, r2, r3, r4, r5, r6, ip, lr}
-        stmia   r0, {r1, r2, r3, r4, r5, r6, ip, lr}
-
-        add     r2, r0, #0x200
-        adr     r0, __stubs_start               @ copy stubs to 0x200
-        adr     r1, __stubs_end
-1:      ldr     r3, [r0], #4
-        str     r3, [r2], #4
-        cmp     r0, r1
-        blt     1b
-        LOADREGS(fd, sp!, {r4 - r6, pc})
+        b       vector_und + stubs_offset
+        ldr     pc, .LCvswi + stubs_offset
+        b       vector_pabt + stubs_offset
+        b       vector_dabt + stubs_offset
+        b       vector_addrexcptn + stubs_offset
+        b       vector_irq + stubs_offset
+        b       vector_fiq + stubs_offset
+
+        .globl  __vectors_end
+__vectors_end:
 
         .data
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 53a7e0dea44d..3f8d0e3aefab 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -9,19 +9,10 @@
  */
 #include <linux/config.h>
 
-#include <asm/thread_info.h>
-#include <asm/ptrace.h>
 #include <asm/unistd.h>
 
 #include "entry-header.S"
 
-/* 
- * We rely on the fact that R0 is at the bottom of the stack (due to
- * slow/fast restore user regs).
- */
-#if S_R0 != 0
-#error "Please fix"
-#endif
 
         .align  5
 /*
@@ -30,11 +21,19 @@
  * stack.
  */
 ret_fast_syscall:
-        disable_irq r1                          @ disable interrupts
+        disable_irq                             @ disable interrupts
         ldr     r1, [tsk, #TI_FLAGS]
         tst     r1, #_TIF_WORK_MASK
         bne     fast_work_pending
-        fast_restore_user_regs
+
+        @ fast_restore_user_regs
+        ldr     r1, [sp, #S_OFF + S_PSR]        @ get calling cpsr
+        ldr     lr, [sp, #S_OFF + S_PC]!        @ get pc
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
+        mov     r0, r0
+        add     sp, sp, #S_FRAME_SIZE - S_PC
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
 
 /*
  * Ok, we need to do extra processing, enter the slow path.
@@ -49,7 +48,7 @@ work_pending:
         mov     r0, sp                          @ 'regs'
         mov     r2, why                         @ 'syscall'
         bl      do_notify_resume
-        disable_irq r1                          @ disable interrupts
+        disable_irq                             @ disable interrupts
         b       no_work_pending
 
 work_resched:
@@ -59,12 +58,19 @@ work_resched:
  */
 ENTRY(ret_to_user)
 ret_slow_syscall:
-        disable_irq r1                          @ disable interrupts
+        disable_irq                             @ disable interrupts
         ldr     r1, [tsk, #TI_FLAGS]
         tst     r1, #_TIF_WORK_MASK
         bne     work_pending
 no_work_pending:
-        slow_restore_user_regs
+        @ slow_restore_user_regs
+        ldr     r1, [sp, #S_PSR]                @ get calling cpsr
+        ldr     lr, [sp, #S_PC]!                @ get pc
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        ldmdb   sp, {r0 - lr}^                  @ get calling r1 - lr
+        mov     r0, r0
+        add     sp, sp, #S_FRAME_SIZE - S_PC
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
 
 /*
  * This is how we return from a fork.
@@ -116,9 +122,26 @@ ENTRY(ret_from_fork)
 
         .align  5
 ENTRY(vector_swi)
-        save_user_regs
+        sub     sp, sp, #S_FRAME_SIZE
+        stmia   sp, {r0 - r12}                  @ Calling r0 - r12
+        add     r8, sp, #S_PC
+        stmdb   r8, {sp, lr}^                   @ Calling sp, lr
+        mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
+        str     lr, [sp, #S_PC]                 @ Save calling PC
+        str     r8, [sp, #S_PSR]                @ Save CPSR
+        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
         zero_fp
-        get_scno
+
+        /*
+         * Get the system call number.
+         */
+#ifdef CONFIG_ARM_THUMB
+        tst     r8, #PSR_T_BIT                  @ this is SPSR from save_user_regs
+        addne   scno, r7, #__NR_SYSCALL_BASE    @ put OS number in
+        ldreq   scno, [lr, #-4]
+#else
+        ldr     scno, [lr, #-4]                 @ get SWI instruction
+#endif
         arm710_bug_check scno, ip
 
 #ifdef CONFIG_ALIGNMENT_TRAP
@@ -126,14 +149,14 @@ ENTRY(vector_swi)
         ldr     ip, [ip]
         mcr     p15, 0, ip, c1, c0              @ update control register
 #endif
-        enable_irq ip
+        enable_irq
 
         str     r4, [sp, #-S_OFF]!              @ push fifth arg
 
         get_thread_info tsk
         ldr     ip, [tsk, #TI_FLAGS]            @ check for syscall tracing
         bic     scno, scno, #0xff000000         @ mask off SWI op-code
-        eor     scno, scno, #OS_NUMBER << 20    @ check OS number
+        eor     scno, scno, #__NR_SYSCALL_BASE  @ check OS number
         adr     tbl, sys_call_table             @ load syscall table pointer
         tst     ip, #_TIF_SYSCALL_TRACE         @ are we tracing syscalls?
         bne     __sys_trace
@@ -144,8 +167,8 @@ ENTRY(vector_swi)
 
         add     r1, sp, #S_OFF
 2:      mov     why, #0                         @ no longer a real syscall
-        cmp     scno, #ARMSWI_OFFSET
-        eor     r0, scno, #OS_NUMBER << 20      @ put OS number back
+        cmp     scno, #(__ARM_NR_BASE - __NR_SYSCALL_BASE)
+        eor     r0, scno, #__NR_SYSCALL_BASE    @ put OS number back
         bcs     arm_syscall     
         b       sys_ni_syscall                  @ not private func
 
@@ -190,7 +213,7 @@ ENTRY(sys_call_table)
 @ r5 = syscall table
                 .type   sys_syscall, #function
 sys_syscall:
-                eor     scno, r0, #OS_NUMBER << 20
+                eor     scno, r0, #__NR_SYSCALL_BASE
                 cmp     scno, #__NR_syscall - __NR_SYSCALL_BASE
                 cmpne   scno, #NR_syscalls      @ check range
                 stmloia sp, {r5, r6}            @ shuffle args
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 4039d8c120b5..a3d40a0e2b04 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -1,24 +1,11 @@
-#include <linux/config.h> /* for CONFIG_ARCH_xxxx */
+#include <linux/config.h>
+#include <linux/init.h>
 #include <linux/linkage.h>
 
 #include <asm/assembler.h>
 #include <asm/constants.h>
 #include <asm/errno.h>
-#include <asm/hardware.h>
-#include <asm/arch/irqs.h>
-#include <asm/arch/entry-macro.S>
-
-#ifndef MODE_SVC
-#define MODE_SVC 0x13
-#endif
-
-        .macro  zero_fp
-#ifdef CONFIG_FRAME_POINTER
-        mov     fp, #0
-#endif
-        .endm
-
-        .text
+#include <asm/thread_info.h>
 
 @ Bad Abort numbers
 @ -----------------
@@ -29,113 +16,44 @@
 #define BAD_IRQ         3
 #define BAD_UNDEFINSTR  4
 
-#define PT_TRACESYS     0x00000002
-
-@ OS version number used in SWIs
-@  RISC OS is 0
-@  RISC iX is 8
 @
-#define OS_NUMBER       9
-#define ARMSWI_OFFSET   0x000f0000
-
+@ Most of the stack format comes from struct pt_regs, but with
+@ the addition of 8 bytes for storing syscall args 5 and 6.
 @
-@ Stack format (ensured by USER_* and SVC_*)
-@
-#define S_FRAME_SIZE    72
-#define S_OLD_R0        68
-#define S_PSR           64
-
-#define S_PC            60
-#define S_LR            56
-#define S_SP            52
-#define S_IP            48
-#define S_FP            44
-#define S_R10           40
-#define S_R9            36
-#define S_R8            32
-#define S_R7            28
-#define S_R6            24
-#define S_R5            20
-#define S_R4            16
-#define S_R3            12
-#define S_R2            8
-#define S_R1            4
-#define S_R0            0
 #define S_OFF           8
 
-        .macro  set_cpsr_c, reg, mode
-        msr     cpsr_c, \mode
+/* 
+ * The SWI code relies on the fact that R0 is at the bottom of the stack
+ * (due to slow/fast restore user regs).
+ */
+#if S_R0 != 0
+#error "Please fix"
+#endif
+
+        .macro  zero_fp
+#ifdef CONFIG_FRAME_POINTER
+        mov     fp, #0
+#endif
         .endm
 
 #if __LINUX_ARM_ARCH__ >= 6
-        .macro  disable_irq, temp
+        .macro  disable_irq
         cpsid   i
         .endm
 
-        .macro  enable_irq, temp
+        .macro  enable_irq
         cpsie   i
         .endm
 #else
-        .macro  disable_irq, temp
-        set_cpsr_c \temp, #PSR_I_BIT | MODE_SVC
+        .macro  disable_irq
+        msr     cpsr_c, #PSR_I_BIT | SVC_MODE
         .endm
 
-        .macro  enable_irq, temp
-        set_cpsr_c \temp, #MODE_SVC
+        .macro  enable_irq
+        msr     cpsr_c, #SVC_MODE
         .endm
 #endif
 
-        .macro  save_user_regs
-        sub     sp, sp, #S_FRAME_SIZE
-        stmia   sp, {r0 - r12}                  @ Calling r0 - r12
-        add     r8, sp, #S_PC
-        stmdb   r8, {sp, lr}^                   @ Calling sp, lr
-        mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
-        str     lr, [sp, #S_PC]                 @ Save calling PC
-        str     r8, [sp, #S_PSR]                @ Save CPSR
-        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
-        .endm
-
-        .macro  restore_user_regs
-        ldr     r1, [sp, #S_PSR]                @ Get calling cpsr
-        disable_irq ip                          @ disable IRQs
-        ldr     lr, [sp, #S_PC]!                @ Get PC
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r0 - lr}^                  @ Get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
-        .endm
-
-/*
- * Must be called with IRQs already disabled.
- */
-        .macro  fast_restore_user_regs
-        ldr     r1, [sp, #S_OFF + S_PSR]        @ get calling cpsr
-        ldr     lr, [sp, #S_OFF + S_PC]!        @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
-        .endm
-
-/*
- * Must be called with IRQs already disabled.
- */
-        .macro  slow_restore_user_regs
-        ldr     r1, [sp, #S_PSR]                @ get calling cpsr
-        ldr     lr, [sp, #S_PC]!                @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r0 - lr}^                  @ get calling r1 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
-        .endm
-
-        .macro  mask_pc, rd, rm
-        .endm
-
         .macro  get_thread_info, rd
         mov     \rd, sp, lsr #13
         mov     \rd, \rd, lsl #13
@@ -165,18 +83,3 @@ scno	.req	r7		@ syscall number
 tbl     .req    r8              @ syscall table pointer
 why     .req    r8              @ Linux syscall (!= 0)
 tsk     .req    r9              @ current thread_info
-
-/*
- * Get the system call number.
- */
-        .macro  get_scno
-#ifdef CONFIG_ARM_THUMB
-        tst     r8, #PSR_T_BIT          @ this is SPSR from save_user_regs
-        addne   scno, r7, #OS_NUMBER << 20 @ put OS number in
-        ldreq   scno, [lr, #-4]
-
-#else
-        mask_pc lr, lr
-        ldr     scno, [lr, #-4]         @ get SWI instruction
-#endif
-        .endm
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 6e31718f6008..0078aeb85737 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -578,9 +578,16 @@ EXPORT_SYMBOL(abort);
 
 void __init trap_init(void)
 {
-        extern void __trap_init(void);
+        extern char __stubs_start[], __stubs_end[];
+        extern char __vectors_start[], __vectors_end[];
 
-        __trap_init();
+        /*
+         * Copy the vectors and stubs (in entry-armv.S) into the
+         * vector page, mapped at 0xffff0000, and ensure these are
+         * visible to the instruction stream.
+         */
+        memcpy((void *)0xffff0000, __vectors_start, __vectors_end - __vectors_start);
+        memcpy((void *)0xffff0200, __stubs_start, __stubs_end - __stubs_start);
         flush_icache_range(0xffff0000, 0xffff0000 + PAGE_SIZE);
         modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
 }
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 16cad2c2497c..5786ccad938c 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -18,6 +18,11 @@
 
 #include <asm/arch/pxa-regs.h>
 
+#ifdef CONFIG_PXA27x                    // workaround for Errata 50
+#define MDREFR_KDIV     0x200a4000      // all banks
+#define CCCR_SLEEP      0x00000107      // L=7 2N=2 A=0 PPDIS=0 CPDIS=0
+#endif
+
                 .text
 
 /*
@@ -28,7 +33,9 @@
 
 ENTRY(pxa_cpu_suspend)
 
+#ifndef CONFIG_IWMMXT
         mra     r2, r3, acc0
+#endif
         stmfd   sp!, {r2 - r12, lr}             @ save registers on stack
 
         @ get coprocessor registers
@@ -61,14 +68,23 @@ ENTRY(pxa_cpu_suspend)
         @ prepare value for sleep mode
         mov     r1, #3                          @ sleep mode
 
-        @ prepare to put SDRAM into self-refresh manually
+        @ prepare pointer to physical address 0 (virtual mapping in generic.c)
+        mov     r2, #UNCACHED_PHYS_0
+
+        @ prepare SDRAM refresh settings
         ldr     r4, =MDREFR
         ldr     r5, [r4]
+
+        @ enable SDRAM self-refresh mode
         orr     r5, r5, #MDREFR_SLFRSH
 
-        @ prepare pointer to physical address 0 (virtual mapping in generic.c)
-        mov     r2, #UNCACHED_PHYS_0
+#ifdef CONFIG_PXA27x
+        @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
+        ldr     r6, =MDREFR_KDIV
+        orr     r5, r5, r6
+#endif
 
+#ifdef CONFIG_PXA25x
         @ Intel PXA255 Specification Update notes problems
         @ about suspending with PXBus operating above 133MHz
         @ (see Errata 31, GPIO output signals, ... unpredictable in sleep
@@ -100,6 +116,18 @@ ENTRY(pxa_cpu_suspend)
         mov     r0, #0
         mcr     p14, 0, r0, c6, c0, 0
         orr     r0, r0, #2                      @ initiate change bit
+#endif
+#ifdef CONFIG_PXA27x
+        @ Intel PXA270 Specification Update notes problems sleeping
+        @ with core operating above 91 MHz
+        @ (see Errata 50, ...processor does not exit from sleep...)
+
+        ldr     r6, =CCCR
+        ldr     r8, [r6]                @ keep original value for resume
+
+        ldr     r7, =CCCR_SLEEP         @ prepare CCCR sleep value
+        mov     r0, #0x2                @ prepare value for CLKCFG
+#endif
 
         @ align execution to a cache line
         b       1f
@@ -111,6 +139,7 @@ ENTRY(pxa_cpu_suspend)
         @ All needed values are now in registers.
         @ These last instructions should be in cache
 
+#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
         @ initiate the frequency change...
         str     r7, [r6]
         mcr     p14, 0, r0, c6, c0, 0
@@ -118,14 +147,27 @@ ENTRY(pxa_cpu_suspend)
         @ restore the original cpu speed value for resume
         str     r8, [r6]
 
-        @ put SDRAM into self-refresh
-        str     r5, [r4]
+        @ need 6 13-MHz cycles before changing PWRMODE
+        @ just set frequency to 91-MHz... 6*91/13 = 42
+
+        mov     r0, #42
+10:     subs    r0, r0, #1
+        bne     10b
+#endif
+
+        @ Do not reorder...
+        @ Intel PXA270 Specification Update notes problems performing
+        @ external accesses after SDRAM is put in self-refresh mode
+        @ (see Errata 39 ...hangs when entering self-refresh mode)
 
         @ force address lines low by reading at physical address 0
         ldr     r3, [r2]
 
+        @ put SDRAM into self-refresh
+        str     r5, [r4]
+
         @ enter sleep mode
-        mcr     p14, 0, r1, c7, c0, 0
+        mcr     p14, 0, r1, c7, c0, 0           @ PWRMODE
 
 20:     b       20b                             @ loop waiting for sleep
 
@@ -188,7 +230,9 @@ resume_after_mmu:
         bl      cpu_xscale_proc_init
 #endif
         ldmfd   sp!, {r2, r3}
+#ifndef CONFIG_IWMMXT
         mar     acc0, r2, r3
+#endif
         ldmfd   sp!, {r4 - r12, pc}             @ return to caller
 
 
diff --git a/arch/ppc64/kernel/rtas_flash.c b/arch/ppc64/kernel/rtas_flash.c
index 3213837282ca..923e2e201a70 100644
--- a/arch/ppc64/kernel/rtas_flash.c
+++ b/arch/ppc64/kernel/rtas_flash.c
@@ -218,7 +218,7 @@ static void get_flash_status_msg(int status, char *buf)
 }
 
 /* Reading the proc file will show status (not the firmware contents) */
-static ssize_t rtas_flash_read(struct file *file, char *buf,
+static ssize_t rtas_flash_read(struct file *file, char __user *buf,
                                size_t count, loff_t *ppos)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
@@ -256,7 +256,7 @@ static ssize_t rtas_flash_read(struct file *file, char *buf,
  * count is.  If the system is low on memory it will be just as well
  * that we fail....
  */
-static ssize_t rtas_flash_write(struct file *file, const char *buffer,
+static ssize_t rtas_flash_write(struct file *file, const char __user *buffer,
                                 size_t count, loff_t *off)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
@@ -356,7 +356,7 @@ static void manage_flash(struct rtas_manage_flash_t *args_buf)
         args_buf->status = rc;
 }
 
-static ssize_t manage_flash_read(struct file *file, char *buf,
+static ssize_t manage_flash_read(struct file *file, char __user *buf,
                                size_t count, loff_t *ppos)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
@@ -386,7 +386,7 @@ static ssize_t manage_flash_read(struct file *file, char *buf,
         return msglen;
 }
 
-static ssize_t manage_flash_write(struct file *file, const char *buf,
+static ssize_t manage_flash_write(struct file *file, const char __user *buf,
                                 size_t count, loff_t *off)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
@@ -466,7 +466,7 @@ static int get_validate_flash_msg(struct rtas_validate_flash_t *args_buf,
         return n;
 }
 
-static ssize_t validate_flash_read(struct file *file, char *buf,
+static ssize_t validate_flash_read(struct file *file, char __user *buf,
                                size_t count, loff_t *ppos)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
@@ -494,7 +494,7 @@ static ssize_t validate_flash_read(struct file *file, char *buf,
         return msglen;
 }
 
-static ssize_t validate_flash_write(struct file *file, const char *buf,
+static ssize_t validate_flash_write(struct file *file, const char __user *buf,
                                     size_t count, loff_t *off)
 {
         struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
diff --git a/arch/ppc64/kernel/scanlog.c b/arch/ppc64/kernel/scanlog.c
index 189b81a41987..4d70736619c7 100644
--- a/arch/ppc64/kernel/scanlog.c
+++ b/arch/ppc64/kernel/scanlog.c
@@ -43,7 +43,7 @@ static int scanlog_debug;
 static unsigned int ibm_scan_log_dump;                  /* RTAS token */
 static struct proc_dir_entry *proc_ppc64_scan_log_dump; /* The proc file */
 
-static ssize_t scanlog_read(struct file *file, char *buf,
+static ssize_t scanlog_read(struct file *file, char __user *buf,
                             size_t count, loff_t *ppos)
 {
         struct inode * inode = file->f_dentry->d_inode;
@@ -129,7 +129,7 @@ static ssize_t scanlog_read(struct file *file, char *buf,
         /*NOTREACHED*/
 }
 
-static ssize_t scanlog_write(struct file * file, const char * buf,
+static ssize_t scanlog_write(struct file * file, const char __user * buf,
                              size_t count, loff_t *ppos)
 {
         char stkbuf[20];
diff --git a/arch/ppc64/xmon/ppc-opc.c b/arch/ppc64/xmon/ppc-opc.c
index 1e4e7e319970..5ee8fc32f824 100644
--- a/arch/ppc64/xmon/ppc-opc.c
+++ b/arch/ppc64/xmon/ppc-opc.c
@@ -20,6 +20,7 @@
    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
    02111-1307, USA.  */
 
+#include <linux/stddef.h>
 #include "nonstdio.h"
 #include "ppc.h"
 
@@ -110,12 +111,12 @@ const struct powerpc_operand powerpc_operands[] =
   /* The zero index is used to indicate the end of the list of
      operands.  */
 #define UNUSED 0
-  { 0, 0, 0, 0, 0 },
+  { 0, 0, NULL, NULL, 0 },
 
   /* The BA field in an XL form instruction.  */
 #define BA UNUSED + 1
 #define BA_MASK (0x1f << 16)
-  { 5, 16, 0, 0, PPC_OPERAND_CR },
+  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
 
   /* The BA field in an XL form instruction when it must be the same
      as the BT field in the same instruction.  */
@@ -125,7 +126,7 @@ const struct powerpc_operand powerpc_operands[] =
   /* The BB field in an XL form instruction.  */
 #define BB BAT + 1
 #define BB_MASK (0x1f << 11)
-  { 5, 11, 0, 0, PPC_OPERAND_CR },
+  { 5, 11, NULL, NULL, PPC_OPERAND_CR },
 
   /* The BB field in an XL form instruction when it must be the same
      as the BA field in the same instruction.  */
@@ -168,21 +169,21 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The BF field in an X or XL form instruction.  */
 #define BF BDPA + 1
-  { 3, 23, 0, 0, PPC_OPERAND_CR },
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
 
   /* An optional BF field.  This is used for comparison instructions,
      in which an omitted BF field is taken as zero.  */
 #define OBF BF + 1
-  { 3, 23, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 
   /* The BFA field in an X or XL form instruction.  */
 #define BFA OBF + 1
-  { 3, 18, 0, 0, PPC_OPERAND_CR },
+  { 3, 18, NULL, NULL, PPC_OPERAND_CR },
 
   /* The BI field in a B form or XL form instruction.  */
 #define BI BFA + 1
 #define BI_MASK (0x1f << 16)
-  { 5, 16, 0, 0, PPC_OPERAND_CR },
+  { 5, 16, NULL, NULL, PPC_OPERAND_CR },
 
   /* The BO field in a B form instruction.  Certain values are
      illegal.  */
@@ -197,36 +198,36 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The BT field in an X or XL form instruction.  */
 #define BT BOE + 1
-  { 5, 21, 0, 0, PPC_OPERAND_CR },
+  { 5, 21, NULL, NULL, PPC_OPERAND_CR },
 
   /* The condition register number portion of the BI field in a B form
      or XL form instruction.  This is used for the extended
      conditional branch mnemonics, which set the lower two bits of the
      BI field.  This field is optional.  */
 #define CR BT + 1
-  { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
+  { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
 
   /* The CRB field in an X form instruction.  */
 #define CRB CR + 1
-  { 5, 6, 0, 0, 0 },
+  { 5, 6, NULL, NULL, 0 },
 
   /* The CRFD field in an X form instruction.  */
 #define CRFD CRB + 1
-  { 3, 23, 0, 0, PPC_OPERAND_CR },
+  { 3, 23, NULL, NULL, PPC_OPERAND_CR },
 
   /* The CRFS field in an X form instruction.  */
 #define CRFS CRFD + 1
-  { 3, 0, 0, 0, PPC_OPERAND_CR },
+  { 3, 0, NULL, NULL, PPC_OPERAND_CR },
 
   /* The CT field in an X form instruction.  */
 #define CT CRFS + 1
-  { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+  { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The D field in a D form instruction.  This is a displacement off
      a register, and implies that the next operand is a register in
      parentheses.  */
 #define D CT + 1
-  { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
+  { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
 
   /* The DE field in a DE form instruction.  This is like D, but is 12
      bits only.  */
@@ -252,40 +253,40 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The E field in a wrteei instruction.  */
 #define E DS + 1
-  { 1, 15, 0, 0, 0 },
+  { 1, 15, NULL, NULL, 0 },
 
   /* The FL1 field in a POWER SC form instruction.  */
 #define FL1 E + 1
-  { 4, 12, 0, 0, 0 },
+  { 4, 12, NULL, NULL, 0 },
 
   /* The FL2 field in a POWER SC form instruction.  */
 #define FL2 FL1 + 1
-  { 3, 2, 0, 0, 0 },
+  { 3, 2, NULL, NULL, 0 },
 
   /* The FLM field in an XFL form instruction.  */
 #define FLM FL2 + 1
-  { 8, 17, 0, 0, 0 },
+  { 8, 17, NULL, NULL, 0 },
 
   /* The FRA field in an X or A form instruction.  */
 #define FRA FLM + 1
 #define FRA_MASK (0x1f << 16)
-  { 5, 16, 0, 0, PPC_OPERAND_FPR },
+  { 5, 16, NULL, NULL, PPC_OPERAND_FPR },
 
   /* The FRB field in an X or A form instruction.  */
 #define FRB FRA + 1
 #define FRB_MASK (0x1f << 11)
-  { 5, 11, 0, 0, PPC_OPERAND_FPR },
+  { 5, 11, NULL, NULL, PPC_OPERAND_FPR },
 
   /* The FRC field in an A form instruction.  */
 #define FRC FRB + 1
 #define FRC_MASK (0x1f << 6)
-  { 5, 6, 0, 0, PPC_OPERAND_FPR },
+  { 5, 6, NULL, NULL, PPC_OPERAND_FPR },
 
   /* The FRS field in an X form instruction or the FRT field in a D, X
      or A form instruction.  */
 #define FRS FRC + 1
 #define FRT FRS
-  { 5, 21, 0, 0, PPC_OPERAND_FPR },
+  { 5, 21, NULL, NULL, PPC_OPERAND_FPR },
 
   /* The FXM field in an XFX instruction.  */
 #define FXM FRS + 1
@@ -298,11 +299,11 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The L field in a D or X form instruction.  */
 #define L FXM4 + 1
-  { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+  { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The LEV field in a POWER SC form instruction.  */
 #define LEV L + 1
-  { 7, 5, 0, 0, 0 },
+  { 7, 5, NULL, NULL, 0 },
 
   /* The LI field in an I form instruction.  The lower two bits are
      forced to zero.  */
@@ -316,24 +317,24 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The LS field in an X (sync) form instruction.  */
 #define LS LIA + 1
-  { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL },
+  { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
   /* The MB field in an M form instruction.  */
 #define MB LS + 1
 #define MB_MASK (0x1f << 6)
-  { 5, 6, 0, 0, 0 },
+  { 5, 6, NULL, NULL, 0 },
 
   /* The ME field in an M form instruction.  */
 #define ME MB + 1
 #define ME_MASK (0x1f << 1)
-  { 5, 1, 0, 0, 0 },
+  { 5, 1, NULL, NULL, 0 },
 
   /* The MB and ME fields in an M form instruction expressed a single
      operand which is a bitmask indicating which bits to select.  This
      is a two operand form using PPC_OPERAND_NEXT.  See the
      description in opcode/ppc.h for what this means.  */
 #define MBE ME + 1
-  { 5, 6, 0, 0, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
+  { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
   { 32, 0, insert_mbe, extract_mbe, 0 },
 
   /* The MB or ME field in an MD or MDS form instruction.  The high
@@ -345,7 +346,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The MO field in an mbar instruction.  */
 #define MO MB6 + 1
-  { 5, 21, 0, 0, 0 },
+  { 5, 21, NULL, NULL, 0 },
 
   /* The NB field in an X form instruction.  The value 32 is stored as
      0.  */
@@ -361,34 +362,34 @@ const struct powerpc_operand powerpc_operands[] =
   /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
 #define RA NSI + 1
 #define RA_MASK (0x1f << 16)
-  { 5, 16, 0, 0, PPC_OPERAND_GPR },
+  { 5, 16, NULL, NULL, PPC_OPERAND_GPR },
 
   /* The RA field in the DQ form lq instruction, which has special
      value restrictions.  */
 #define RAQ RA + 1
-  { 5, 16, insert_raq, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR },
 
   /* The RA field in a D or X form instruction which is an updating
      load, which means that the RA field may not be zero and may not
      equal the RT field.  */
 #define RAL RAQ + 1
-  { 5, 16, insert_ral, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR },
 
   /* The RA field in an lmw instruction, which has special value
      restrictions.  */
 #define RAM RAL + 1
-  { 5, 16, insert_ram, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR },
 
   /* The RA field in a D or X form instruction which is an updating
      store or an updating floating point load, which means that the RA
      field may not be zero.  */
 #define RAS RAM + 1
-  { 5, 16, insert_ras, 0, PPC_OPERAND_GPR },
+  { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR },
 
   /* The RB field in an X, XO, M, or MDS form instruction.  */
 #define RB RAS + 1
 #define RB_MASK (0x1f << 11)
-  { 5, 11, 0, 0, PPC_OPERAND_GPR },
+  { 5, 11, NULL, NULL, PPC_OPERAND_GPR },
 
   /* The RB field in an X form instruction when it must be the same as
      the RS field in the instruction.  This is used for extended
@@ -402,22 +403,22 @@ const struct powerpc_operand powerpc_operands[] =
 #define RS RBS + 1
 #define RT RS
 #define RT_MASK (0x1f << 21)
-  { 5, 21, 0, 0, PPC_OPERAND_GPR },
+  { 5, 21, NULL, NULL, PPC_OPERAND_GPR },
 
   /* The RS field of the DS form stq instruction, which has special
      value restrictions.  */
 #define RSQ RS + 1
-  { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR },
 
   /* The RT field of the DQ form lq instruction, which has special
      value restrictions.  */
 #define RTQ RSQ + 1
-  { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR },
+  { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR },
 
   /* The SH field in an X or M form instruction.  */
 #define SH RTQ + 1
 #define SH_MASK (0x1f << 11)
-  { 5, 11, 0, 0, 0 },
+  { 5, 11, NULL, NULL, 0 },
 
   /* The SH field in an MD form instruction.  This is split.  */
 #define SH6 SH + 1
@@ -426,12 +427,12 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The SI field in a D form instruction.  */
 #define SI SH6 + 1
-  { 16, 0, 0, 0, PPC_OPERAND_SIGNED },
+  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED },
 
   /* The SI field in a D form instruction when we accept a wide range
      of positive values.  */
 #define SISIGNOPT SI + 1
-  { 16, 0, 0, 0, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
+  { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },
 
   /* The SPR field in an XFX form instruction.  This is flipped--the
      lower 5 bits are stored in the upper 5 and vice- versa.  */
@@ -443,25 +444,25 @@ const struct powerpc_operand powerpc_operands[] =
   /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
 #define SPRBAT SPR + 1
 #define SPRBAT_MASK (0x3 << 17)
-  { 2, 17, 0, 0, 0 },
+  { 2, 17, NULL, NULL, 0 },
 
   /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
 #define SPRG SPRBAT + 1
 #define SPRG_MASK (0x3 << 16)
-  { 2, 16, 0, 0, 0 },
+  { 2, 16, NULL, NULL, 0 },
 
   /* The SR field in an X form instruction.  */
 #define SR SPRG + 1
-  { 4, 16, 0, 0, 0 },
+  { 4, 16, NULL, NULL, 0 },
 
   /* The STRM field in an X AltiVec form instruction.  */
 #define STRM SR + 1
 #define STRM_MASK (0x3 << 21)
-  { 2, 21, 0, 0, 0 },
+  { 2, 21, NULL, NULL, 0 },
 
   /* The SV field in a POWER SC form instruction.  */
 #define SV STRM + 1
-  { 14, 2, 0, 0, 0 },
+  { 14, 2, NULL, NULL, 0 },
 
   /* The TBR field in an XFX form instruction.  This is like the SPR
      field, but it is optional.  */
@@ -471,52 +472,52 @@ const struct powerpc_operand powerpc_operands[] =
   /* The TO field in a D or X form instruction.  */
 #define TO TBR + 1
 #define TO_MASK (0x1f << 21)
-  { 5, 21, 0, 0, 0 },
+  { 5, 21, NULL, NULL, 0 },
 
   /* The U field in an X form instruction.  */
 #define U TO + 1
-  { 4, 12, 0, 0, 0 },
+  { 4, 12, NULL, NULL, 0 },
 
   /* The UI field in a D form instruction.  */
 #define UI U + 1
-  { 16, 0, 0, 0, 0 },
+  { 16, 0, NULL, NULL, 0 },
 
   /* The VA field in a VA, VX or VXR form instruction.  */
 #define VA UI + 1
 #define VA_MASK (0x1f << 16)
-  { 5, 16, 0, 0, PPC_OPERAND_VR },
+  { 5, 16, NULL, NULL, PPC_OPERAND_VR },
 
   /* The VB field in a VA, VX or VXR form instruction.  */
 #define VB VA + 1
 #define VB_MASK (0x1f << 11)
-  { 5, 11, 0, 0, PPC_OPERAND_VR },
+  { 5, 11, NULL, NULL, PPC_OPERAND_VR },
 
   /* The VC field in a VA form instruction.  */
 #define VC VB + 1
 #define VC_MASK (0x1f << 6)
-  { 5, 6, 0, 0, PPC_OPERAND_VR },
+  { 5, 6, NULL, NULL, PPC_OPERAND_VR },
 
   /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
 #define VD VC + 1
 #define VS VD
 #define VD_MASK (0x1f << 21)
-  { 5, 21, 0, 0, PPC_OPERAND_VR },
+  { 5, 21, NULL, NULL, PPC_OPERAND_VR },
 
   /* The SIMM field in a VX form instruction.  */
 #define SIMM VD + 1
-  { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
+  { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED},
 
   /* The UIMM field in a VX form instruction.  */
 #define UIMM SIMM + 1
-  { 5, 16, 0, 0, 0 },
+  { 5, 16, NULL, NULL, 0 },
 
   /* The SHB field in a VA form instruction.  */
 #define SHB UIMM + 1
-  { 4, 6, 0, 0, 0 },
+  { 4, 6, NULL, NULL, 0 },
 
   /* The other UIMM field in a EVX form instruction.  */
 #define EVUIMM SHB + 1
-  { 5, 11, 0, 0, 0 },
+  { 5, 11, NULL, NULL, 0 },
 
   /* The other UIMM field in a half word EVX form instruction.  */
 #define EVUIMM_2 EVUIMM + 1
@@ -533,11 +534,11 @@ const struct powerpc_operand powerpc_operands[] =
   /* The WS field.  */
 #define WS EVUIMM_8 + 1
 #define WS_MASK (0x7 << 11)
-  { 3, 11, 0, 0, 0 },
+  { 3, 11, NULL, NULL, 0 },
 
   /* The L field in an mtmsrd instruction */
 #define MTMSRD_L WS + 1
-  { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
+  { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
 
 };
 
diff --git a/arch/x86_64/kernel/signal.c b/arch/x86_64/kernel/signal.c
index 7760224cdfe3..d439ced150c6 100644
--- a/arch/x86_64/kernel/signal.c
+++ b/arch/x86_64/kernel/signal.c
@@ -83,7 +83,7 @@ sys_sigaltstack(const stack_t __user *uss, stack_t __user *uoss,
 
 struct rt_sigframe
 {
-        char *pretcode;
+        char __user *pretcode;
         struct ucontext uc;
         struct siginfo info;
 };