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-rw-r--r--arch/arm/mach-tcc8k/Makefile2
-rw-r--r--arch/arm/mach-tcc8k/common.h1
-rw-r--r--arch/arm/mach-tcc8k/irq.c111
-rw-r--r--arch/arm/plat-tcc/include/mach/irqs.h83
4 files changed, 196 insertions, 1 deletions
diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
index 805d850919eb..53bc2f58549b 100644
--- a/arch/arm/mach-tcc8k/Makefile
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -3,4 +3,4 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y += clock.o 6obj-y += clock.o irq.o
diff --git a/arch/arm/mach-tcc8k/common.h b/arch/arm/mach-tcc8k/common.h
index e2c902c1639c..e539548e58d2 100644
--- a/arch/arm/mach-tcc8k/common.h
+++ b/arch/arm/mach-tcc8k/common.h
@@ -2,5 +2,6 @@
2#define MACH_TCC8K_COMMON_H 2#define MACH_TCC8K_COMMON_H
3 3
4extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq); 4extern void tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq);
5extern void tcc8k_init_irq(void);
5 6
6#endif 7#endif
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
new file mode 100644
index 000000000000..34575c4963f0
--- /dev/null
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -0,0 +1,111 @@
1/*
2 * Copyright (C) Telechips, Inc.
3 * Copyright (C) 2009-2010 Hans J. Koch <hjk@linutronix.de>
4 *
5 * Licensed under the terms of the GNU GPL version 2.
6 */
7
8#include <linux/init.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11
12#include <asm/irq.h>
13#include <asm/mach/irq.h>
14
15#include <mach/tcc8k-regs.h>
16#include <mach/irqs.h>
17
18#include "common.h"
19
20/* Disable IRQ */
21static void tcc8000_mask_ack_irq0(unsigned int irq)
22{
23 PIC0_IEN &= ~(1 << irq);
24 PIC0_CREQ |= (1 << irq);
25}
26
27static void tcc8000_mask_ack_irq1(unsigned int irq)
28{
29 PIC1_IEN &= ~(1 << (irq - 32));
30 PIC1_CREQ |= (1 << (irq - 32));
31}
32
33static void tcc8000_mask_irq0(unsigned int irq)
34{
35 PIC0_IEN &= ~(1 << irq);
36}
37
38static void tcc8000_mask_irq1(unsigned int irq)
39{
40 PIC1_IEN &= ~(1 << (irq - 32));
41}
42
43static void tcc8000_ack_irq0(unsigned int irq)
44{
45 PIC0_CREQ |= (1 << irq);
46}
47
48static void tcc8000_ack_irq1(unsigned int irq)
49{
50 PIC1_CREQ |= (1 << (irq - 32));
51}
52
53/* Enable IRQ */
54static void tcc8000_unmask_irq0(unsigned int irq)
55{
56 PIC0_IEN |= (1 << irq);
57 PIC0_INTOEN |= (1 << irq);
58}
59
60static void tcc8000_unmask_irq1(unsigned int irq)
61{
62 PIC1_IEN |= (1 << (irq - 32));
63 PIC1_INTOEN |= (1 << (irq - 32));
64}
65
66static struct irq_chip tcc8000_irq_chip0 = {
67 .name = "tcc_irq0",
68 .mask = tcc8000_mask_irq0,
69 .ack = tcc8000_ack_irq0,
70 .mask_ack = tcc8000_mask_ack_irq0,
71 .unmask = tcc8000_unmask_irq0,
72};
73
74static struct irq_chip tcc8000_irq_chip1 = {
75 .name = "tcc_irq1",
76 .mask = tcc8000_mask_irq1,
77 .ack = tcc8000_ack_irq1,
78 .mask_ack = tcc8000_mask_ack_irq1,
79 .unmask = tcc8000_unmask_irq1,
80};
81
82void __init tcc8k_init_irq(void)
83{
84 int irqno;
85
86 /* Mask and clear all interrupts */
87 PIC0_IEN = 0x00000000;
88 PIC0_CREQ = 0xffffffff;
89 PIC1_IEN = 0x00000000;
90 PIC1_CREQ = 0xffffffff;
91
92 PIC0_MEN0 = 0x00000003;
93 PIC1_MEN1 = 0x00000003;
94 PIC1_MEN = 0x00000003;
95
96 /* let all IRQs be level triggered */
97 PIC0_TMODE = 0xffffffff;
98 PIC1_TMODE = 0xffffffff;
99 /* all IRQs are IRQs (not FIQs) */
100 PIC0_IRQSEL = 0xffffffff;
101 PIC1_IRQSEL = 0xffffffff;
102
103 for (irqno = 0; irqno < NR_IRQS; irqno++) {
104 if (irqno < 32)
105 set_irq_chip(irqno, &tcc8000_irq_chip0);
106 else
107 set_irq_chip(irqno, &tcc8000_irq_chip1);
108 set_irq_handler(irqno, handle_level_irq);
109 set_irq_flags(irqno, IRQF_VALID);
110 }
111}
diff --git a/arch/arm/plat-tcc/include/mach/irqs.h b/arch/arm/plat-tcc/include/mach/irqs.h
new file mode 100644
index 000000000000..da863894d498
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/irqs.h
@@ -0,0 +1,83 @@
1/*
2 * IRQ definitions for TCC8xxx
3 *
4 * Copyright (C) 2008-2009 Telechips
5 * Copyright (C) 2009 Hans J. Koch <hjk@linutronix.de>
6 *
7 * Licensed under the terms of the GPL v2.
8 *
9 */
10
11#ifndef __ASM_ARCH_TCC_IRQS_H
12#define __ASM_ARCH_TCC_IRQS_H
13
14#define NR_IRQS 64
15
16/* PIC0 interrupts */
17#define INT_ADMA1 0
18#define INT_BDMA 1
19#define INT_ADMA0 2
20#define INT_GDMA1 3
21#define INT_I2S0RX 4
22#define INT_I2S0TX 5
23#define INT_TC 6
24#define INT_UART0 7
25#define INT_USBD 8
26#define INT_SPI0TX 9
27#define INT_UDMA 10
28#define INT_LIRQ 11
29#define INT_GDMA2 12
30#define INT_GDMA0 13
31#define INT_TC32 14
32#define INT_LCD 15
33#define INT_ADC 16
34#define INT_I2C 17
35#define INT_RTCP 18
36#define INT_RTCA 19
37#define INT_NFC 20
38#define INT_SD0 21
39#define INT_GSB0 22
40#define INT_PK 23
41#define INT_USBH0 24
42#define INT_USBH1 25
43#define INT_G2D 26
44#define INT_ECC 27
45#define INT_SPI0RX 28
46#define INT_UART1 29
47#define INT_MSCL 30
48#define INT_GSB1 31
49/* PIC1 interrupts */
50#define INT_E0 32
51#define INT_E1 33
52#define INT_E2 34
53#define INT_E3 35
54#define INT_E4 36
55#define INT_E5 37
56#define INT_E6 38
57#define INT_E7 39
58#define INT_UART2 40
59#define INT_UART3 41
60#define INT_SPI1TX 42
61#define INT_SPI1RX 43
62#define INT_GSB2 44
63#define INT_SPDIF 45
64#define INT_CDIF 46
65#define INT_VBON 47
66#define INT_VBOFF 48
67#define INT_SD1 49
68#define INT_UART4 50
69#define INT_GDMA3 51
70#define INT_I2S1RX 52
71#define INT_I2S1TX 53
72#define INT_CAN0 54
73#define INT_CAN1 55
74#define INT_GSB3 56
75#define INT_KRST 57
76#define INT_UNUSED 58
77#define INT_SD0D3 59
78#define INT_SD1D3 60
79#define INT_GPS0 61
80#define INT_GPS1 62
81#define INT_GPS2 63
82
83#endif /* ASM_ARCH_TCC_IRQS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 12:59:44 -0500