aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c81
-rw-r--r--arch/arm/mach-msm/devices-msm7x00.c3
-rw-r--r--arch/arm/mach-msm/devices-msm7x30.c3
-rw-r--r--arch/arm/mach-msm/devices-qsd8x50.c199
-rw-r--r--arch/arm/mach-msm/gpiomux-8x50.c23
-rw-r--r--arch/arm/mach-msm/include/mach/mmc.h11
-rw-r--r--arch/arm/mach-msm/include/mach/msm_iomap-8x50.h8
7 files changed, 321 insertions, 7 deletions
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 3edc4de7e542..b464d48da7c0 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -1,4 +1,4 @@
1/* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -21,6 +21,7 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/usb/msm_hsusb.h> 23#include <linux/usb/msm_hsusb.h>
24#include <linux/err.h>
24 25
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
@@ -31,6 +32,8 @@
31#include <mach/irqs.h> 32#include <mach/irqs.h>
32#include <mach/sirc.h> 33#include <mach/sirc.h>
33#include <mach/gpio.h> 34#include <mach/gpio.h>
35#include <mach/vreg.h>
36#include <mach/mmc.h>
34 37
35#include "devices.h" 38#include "devices.h"
36 39
@@ -95,6 +98,81 @@ static struct platform_device *devices[] __initdata = {
95 &msm_device_hsusb_host, 98 &msm_device_hsusb_host,
96}; 99};
97 100
101static struct msm_mmc_gpio sdc1_gpio_cfg[] = {
102 {51, "sdc1_dat_3"},
103 {52, "sdc1_dat_2"},
104 {53, "sdc1_dat_1"},
105 {54, "sdc1_dat_0"},
106 {55, "sdc1_cmd"},
107 {56, "sdc1_clk"}
108};
109
110static struct vreg *vreg_mmc;
111static unsigned long vreg_sts;
112
113static uint32_t msm_sdcc_setup_power(struct device *dv, unsigned int vdd)
114{
115 int rc = 0;
116 struct platform_device *pdev;
117
118 pdev = container_of(dv, struct platform_device, dev);
119
120 if (vdd == 0) {
121 if (!vreg_sts)
122 return 0;
123
124 clear_bit(pdev->id, &vreg_sts);
125
126 if (!vreg_sts) {
127 rc = vreg_disable(vreg_mmc);
128 if (rc)
129 pr_err("vreg_mmc disable failed for slot "
130 "%d: %d\n", pdev->id, rc);
131 }
132 return 0;
133 }
134
135 if (!vreg_sts) {
136 rc = vreg_set_level(vreg_mmc, 2900);
137 if (rc)
138 pr_err("vreg_mmc set level failed for slot %d: %d\n",
139 pdev->id, rc);
140 rc = vreg_enable(vreg_mmc);
141 if (rc)
142 pr_err("vreg_mmc enable failed for slot %d: %d\n",
143 pdev->id, rc);
144 }
145 set_bit(pdev->id, &vreg_sts);
146 return 0;
147}
148
149static struct msm_mmc_gpio_data sdc1_gpio = {
150 .gpio = sdc1_gpio_cfg,
151 .size = ARRAY_SIZE(sdc1_gpio_cfg),
152};
153
154static struct msm_mmc_platform_data qsd8x50_sdc1_data = {
155 .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
156 .translate_vdd = msm_sdcc_setup_power,
157 .gpio_data = &sdc1_gpio,
158};
159
160static void __init qsd8x50_init_mmc(void)
161{
162 if (machine_is_qsd8x50_ffa() || machine_is_qsd8x50a_ffa())
163 vreg_mmc = vreg_get(NULL, "gp6");
164 else
165 vreg_mmc = vreg_get(NULL, "gp5");
166
167 if (IS_ERR(vreg_mmc)) {
168 pr_err("vreg get for vreg_mmc failed (%ld)\n",
169 PTR_ERR(vreg_mmc));
170 return;
171 }
172
173 msm_add_sdcc(1, &qsd8x50_sdc1_data, 0, 0);
174}
175
98static void __init qsd8x50_map_io(void) 176static void __init qsd8x50_map_io(void)
99{ 177{
100 msm_map_qsd8x50_io(); 178 msm_map_qsd8x50_io();
@@ -113,6 +191,7 @@ static void __init qsd8x50_init(void)
113 msm_device_hsusb.dev.parent = &msm_device_otg.dev; 191 msm_device_hsusb.dev.parent = &msm_device_otg.dev;
114 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev; 192 msm_device_hsusb_host.dev.parent = &msm_device_otg.dev;
115 platform_add_devices(devices, ARRAY_SIZE(devices)); 193 platform_add_devices(devices, ARRAY_SIZE(devices));
194 qsd8x50_init_mmc();
116} 195}
117 196
118MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") 197MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index 0a47678143f6..ed62806559e7 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -39,6 +39,7 @@ static struct resource resources_uart1[] = {
39 .start = MSM_UART1_PHYS, 39 .start = MSM_UART1_PHYS,
40 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1, 40 .end = MSM_UART1_PHYS + MSM_UART1_SIZE - 1,
41 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
42 .name = "uart_resource"
42 }, 43 },
43}; 44};
44 45
@@ -52,6 +53,7 @@ static struct resource resources_uart2[] = {
52 .start = MSM_UART2_PHYS, 53 .start = MSM_UART2_PHYS,
53 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, 54 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
54 .flags = IORESOURCE_MEM, 55 .flags = IORESOURCE_MEM,
56 .name = "uart_resource"
55 }, 57 },
56}; 58};
57 59
@@ -65,6 +67,7 @@ static struct resource resources_uart3[] = {
65 .start = MSM_UART3_PHYS, 67 .start = MSM_UART3_PHYS,
66 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, 68 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
67 .flags = IORESOURCE_MEM, 69 .flags = IORESOURCE_MEM,
70 .name = "uart_resource"
68 }, 71 },
69}; 72};
70 73
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 8bd730792ff0..cd4343bcf730 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2008 Google, Inc. 2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -42,6 +42,7 @@ static struct resource resources_uart2[] = {
42 .start = MSM_UART2_PHYS, 42 .start = MSM_UART2_PHYS,
43 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1, 43 .end = MSM_UART2_PHYS + MSM_UART2_SIZE - 1,
44 .flags = IORESOURCE_MEM, 44 .flags = IORESOURCE_MEM,
45 .name = "uart_resource"
45 }, 46 },
46}; 47};
47 48
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4cbf89dda733..bd545f9e8c29 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * Copyright (C) 2008 Google, Inc. 2 * Copyright (C) 2008 Google, Inc.
3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * 4 *
5 * This software is licensed under the terms of the GNU General Public 5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and 6 * License version 2, as published by the Free Software Foundation, and
@@ -39,6 +39,7 @@ static struct resource resources_uart3[] = {
39 .start = MSM_UART3_PHYS, 39 .start = MSM_UART3_PHYS,
40 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1, 40 .end = MSM_UART3_PHYS + MSM_UART3_SIZE - 1,
41 .flags = IORESOURCE_MEM, 41 .flags = IORESOURCE_MEM,
42 .name = "uart_resource"
42 }, 43 },
43}; 44};
44 45
@@ -125,6 +126,194 @@ struct platform_device msm_device_hsusb_host = {
125 }, 126 },
126}; 127};
127 128
129static struct resource resources_sdc1[] = {
130 {
131 .start = MSM_SDC1_PHYS,
132 .end = MSM_SDC1_PHYS + MSM_SDC1_SIZE - 1,
133 .flags = IORESOURCE_MEM,
134 },
135 {
136 .start = INT_SDC1_0,
137 .end = INT_SDC1_0,
138 .flags = IORESOURCE_IRQ,
139 .name = "cmd_irq",
140 },
141 {
142 .start = INT_SDC1_1,
143 .end = INT_SDC1_1,
144 .flags = IORESOURCE_IRQ,
145 .name = "pio_irq",
146 },
147 {
148 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
149 .name = "status_irq"
150 },
151 {
152 .start = 8,
153 .end = 8,
154 .flags = IORESOURCE_DMA,
155 },
156};
157
158static struct resource resources_sdc2[] = {
159 {
160 .start = MSM_SDC2_PHYS,
161 .end = MSM_SDC2_PHYS + MSM_SDC2_SIZE - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 {
165 .start = INT_SDC2_0,
166 .end = INT_SDC2_0,
167 .flags = IORESOURCE_IRQ,
168 .name = "cmd_irq",
169 },
170 {
171 .start = INT_SDC2_1,
172 .end = INT_SDC2_1,
173 .flags = IORESOURCE_IRQ,
174 .name = "pio_irq",
175 },
176 {
177 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
178 .name = "status_irq"
179 },
180 {
181 .start = 8,
182 .end = 8,
183 .flags = IORESOURCE_DMA,
184 },
185};
186
187static struct resource resources_sdc3[] = {
188 {
189 .start = MSM_SDC3_PHYS,
190 .end = MSM_SDC3_PHYS + MSM_SDC3_SIZE - 1,
191 .flags = IORESOURCE_MEM,
192 },
193 {
194 .start = INT_SDC3_0,
195 .end = INT_SDC3_0,
196 .flags = IORESOURCE_IRQ,
197 .name = "cmd_irq",
198 },
199 {
200 .start = INT_SDC3_1,
201 .end = INT_SDC3_1,
202 .flags = IORESOURCE_IRQ,
203 .name = "pio_irq",
204 },
205 {
206 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
207 .name = "status_irq"
208 },
209 {
210 .start = 8,
211 .end = 8,
212 .flags = IORESOURCE_DMA,
213 },
214};
215
216static struct resource resources_sdc4[] = {
217 {
218 .start = MSM_SDC4_PHYS,
219 .end = MSM_SDC4_PHYS + MSM_SDC4_SIZE - 1,
220 .flags = IORESOURCE_MEM,
221 },
222 {
223 .start = INT_SDC4_0,
224 .end = INT_SDC4_0,
225 .flags = IORESOURCE_IRQ,
226 .name = "cmd_irq",
227 },
228 {
229 .start = INT_SDC4_1,
230 .end = INT_SDC4_1,
231 .flags = IORESOURCE_IRQ,
232 .name = "pio_irq",
233 },
234 {
235 .flags = IORESOURCE_IRQ | IORESOURCE_DISABLED,
236 .name = "status_irq"
237 },
238 {
239 .start = 8,
240 .end = 8,
241 .flags = IORESOURCE_DMA,
242 },
243};
244
245struct platform_device msm_device_sdc1 = {
246 .name = "msm_sdcc",
247 .id = 1,
248 .num_resources = ARRAY_SIZE(resources_sdc1),
249 .resource = resources_sdc1,
250 .dev = {
251 .coherent_dma_mask = 0xffffffff,
252 },
253};
254
255struct platform_device msm_device_sdc2 = {
256 .name = "msm_sdcc",
257 .id = 2,
258 .num_resources = ARRAY_SIZE(resources_sdc2),
259 .resource = resources_sdc2,
260 .dev = {
261 .coherent_dma_mask = 0xffffffff,
262 },
263};
264
265struct platform_device msm_device_sdc3 = {
266 .name = "msm_sdcc",
267 .id = 3,
268 .num_resources = ARRAY_SIZE(resources_sdc3),
269 .resource = resources_sdc3,
270 .dev = {
271 .coherent_dma_mask = 0xffffffff,
272 },
273};
274
275struct platform_device msm_device_sdc4 = {
276 .name = "msm_sdcc",
277 .id = 4,
278 .num_resources = ARRAY_SIZE(resources_sdc4),
279 .resource = resources_sdc4,
280 .dev = {
281 .coherent_dma_mask = 0xffffffff,
282 },
283};
284
285static struct platform_device *msm_sdcc_devices[] __initdata = {
286 &msm_device_sdc1,
287 &msm_device_sdc2,
288 &msm_device_sdc3,
289 &msm_device_sdc4,
290};
291
292int __init msm_add_sdcc(unsigned int controller,
293 struct msm_mmc_platform_data *plat,
294 unsigned int stat_irq, unsigned long stat_irq_flags)
295{
296 struct platform_device *pdev;
297 struct resource *res;
298
299 if (controller < 1 || controller > 4)
300 return -EINVAL;
301
302 pdev = msm_sdcc_devices[controller-1];
303 pdev->dev.platform_data = plat;
304
305 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "status_irq");
306 if (!res)
307 return -EINVAL;
308 else if (stat_irq) {
309 res->start = res->end = stat_irq;
310 res->flags &= ~IORESOURCE_DISABLED;
311 res->flags |= stat_irq_flags;
312 }
313
314 return platform_device_register(pdev);
315}
316
128struct clk msm_clocks_8x50[] = { 317struct clk msm_clocks_8x50[] = {
129 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0), 318 CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
130 CLK_PCOM("ce_clk", CE_CLK, NULL, 0), 319 CLK_PCOM("ce_clk", CE_CLK, NULL, 0),
@@ -147,6 +336,14 @@ struct clk msm_clocks_8x50[] = {
147 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN), 336 CLK_PCOM("pbus_clk", PBUS_CLK, NULL, CLK_MIN),
148 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0), 337 CLK_PCOM("pcm_clk", PCM_CLK, NULL, 0),
149 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF), 338 CLK_PCOM("sdac_clk", SDAC_CLK, NULL, OFF),
339 CLK_PCOM("sdc_clk", SDC1_CLK, &msm_device_sdc1.dev, OFF),
340 CLK_PCOM("sdc_pclk", SDC1_P_CLK, &msm_device_sdc1.dev, OFF),
341 CLK_PCOM("sdc_clk", SDC2_CLK, &msm_device_sdc2.dev, OFF),
342 CLK_PCOM("sdc_pclk", SDC2_P_CLK, &msm_device_sdc2.dev, OFF),
343 CLK_PCOM("sdc_clk", SDC3_CLK, &msm_device_sdc3.dev, OFF),
344 CLK_PCOM("sdc_pclk", SDC3_P_CLK, &msm_device_sdc3.dev, OFF),
345 CLK_PCOM("sdc_clk", SDC4_CLK, &msm_device_sdc4.dev, OFF),
346 CLK_PCOM("sdc_pclk", SDC4_P_CLK, &msm_device_sdc4.dev, OFF),
150 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0), 347 CLK_PCOM("spi_clk", SPI_CLK, NULL, 0),
151 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0), 348 CLK_PCOM("tsif_clk", TSIF_CLK, NULL, 0),
152 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0), 349 CLK_PCOM("tsif_ref_clk", TSIF_REF_CLK, NULL, 0),
diff --git a/arch/arm/mach-msm/gpiomux-8x50.c b/arch/arm/mach-msm/gpiomux-8x50.c
index 4406e0f4ae95..f7a4ea593c95 100644
--- a/arch/arm/mach-msm/gpiomux-8x50.c
+++ b/arch/arm/mach-msm/gpiomux-8x50.c
@@ -16,6 +16,19 @@
16 */ 16 */
17#include "gpiomux.h" 17#include "gpiomux.h"
18 18
19#if defined(CONFIG_MMC_MSM) || defined(CONFIG_MMC_MSM_MODULE)
20 #define SDCC_DAT_0_3_CMD_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_UP\
21 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
22 #define SDCC_CLK_ACTV_CFG (GPIOMUX_VALID | GPIOMUX_PULL_NONE\
23 | GPIOMUX_FUNC_1 | GPIOMUX_DRV_8MA)
24#else
25 #define SDCC_DAT_0_3_CMD_ACTV_CFG 0
26 #define SDCC_CLK_ACTV_CFG 0
27#endif
28
29#define SDC1_SUSPEND_CONFIG (GPIOMUX_VALID | GPIOMUX_PULL_DOWN\
30 | GPIOMUX_FUNC_GPIO | GPIOMUX_DRV_2MA)
31
19struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = { 32struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
20 [86] = { /* UART3 RX */ 33 [86] = { /* UART3 RX */
21 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | 34 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
@@ -25,4 +38,14 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
25 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN | 38 .suspended = GPIOMUX_DRV_2MA | GPIOMUX_PULL_DOWN |
26 GPIOMUX_FUNC_1 | GPIOMUX_VALID, 39 GPIOMUX_FUNC_1 | GPIOMUX_VALID,
27 }, 40 },
41 /* SDC1 data[3:0] & CMD */
42 [51 ... 55] = {
43 .active = SDCC_DAT_0_3_CMD_ACTV_CFG,
44 .suspended = SDC1_SUSPEND_CONFIG
45 },
46 /* SDC1 CLK */
47 [56] = {
48 .active = SDCC_CLK_ACTV_CFG,
49 .suspended = SDC1_SUSPEND_CONFIG
50 },
28}; 51};
diff --git a/arch/arm/mach-msm/include/mach/mmc.h b/arch/arm/mach-msm/include/mach/mmc.h
index d54b6b086cff..5631b51cec46 100644
--- a/arch/arm/mach-msm/include/mach/mmc.h
+++ b/arch/arm/mach-msm/include/mach/mmc.h
@@ -15,12 +15,23 @@ struct embedded_sdio_data {
15 int num_funcs; 15 int num_funcs;
16}; 16};
17 17
18struct msm_mmc_gpio {
19 unsigned no;
20 const char *name;
21};
22
23struct msm_mmc_gpio_data {
24 struct msm_mmc_gpio *gpio;
25 u8 size;
26};
27
18struct msm_mmc_platform_data { 28struct msm_mmc_platform_data {
19 unsigned int ocr_mask; /* available voltages */ 29 unsigned int ocr_mask; /* available voltages */
20 u32 (*translate_vdd)(struct device *, unsigned int); 30 u32 (*translate_vdd)(struct device *, unsigned int);
21 unsigned int (*status)(struct device *); 31 unsigned int (*status)(struct device *);
22 struct embedded_sdio_data *embedded_sdio; 32 struct embedded_sdio_data *embedded_sdio;
23 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id); 33 int (*register_status_notify)(void (*callback)(int card_present, void *dev_id), void *dev_id);
34 struct msm_mmc_gpio_data *gpio_data;
24}; 35};
25 36
26#endif 37#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
index cf1c2df1d953..d4143201999f 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x50.h
@@ -124,16 +124,16 @@
124#define MSM_UART2DM_PHYS 0xA0900000 124#define MSM_UART2DM_PHYS 0xA0900000
125 125
126 126
127#define MSM_SDC1_PHYS 0xA0400000 127#define MSM_SDC1_PHYS 0xA0300000
128#define MSM_SDC1_SIZE SZ_4K 128#define MSM_SDC1_SIZE SZ_4K
129 129
130#define MSM_SDC2_PHYS 0xA0500000 130#define MSM_SDC2_PHYS 0xA0400000
131#define MSM_SDC2_SIZE SZ_4K 131#define MSM_SDC2_SIZE SZ_4K
132 132
133#define MSM_SDC3_PHYS 0xA0600000 133#define MSM_SDC3_PHYS 0xA0500000
134#define MSM_SDC3_SIZE SZ_4K 134#define MSM_SDC3_SIZE SZ_4K
135 135
136#define MSM_SDC4_PHYS 0xA0700000 136#define MSM_SDC4_PHYS 0xA0600000
137#define MSM_SDC4_SIZE SZ_4K 137#define MSM_SDC4_SIZE SZ_4K
138 138
139#endif 139#endif