231 files changed, 9464 insertions, 5353 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0f3417065d13..fac58916adec 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -14,6 +14,7 @@ config ARM
         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
+        select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
         select HAVE_GENERIC_DMA_COHERENT
         select HAVE_KERNEL_GZIP
         select HAVE_KERNEL_LZO
@@ -805,6 +806,7 @@ config ARCH_U8500
         select GENERIC_CLOCKEVENTS
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_CPUFREQ
         help
           Support for ST-Ericsson's Ux500 architecture
 
@@ -1009,8 +1011,8 @@ source arch/arm/mm/Kconfig
 
 config IWMMXT
         bool "Enable iWMMXt support"
-        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
-        default y if PXA27x || PXA3xx || ARCH_MMP
+        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
+        default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
         help
           Enable support for iWMMXt context switching at run time if
           running on a CPU that supports it.
@@ -1215,10 +1217,11 @@ config SMP
         depends on EXPERIMENTAL
         depends on GENERIC_CLOCKEVENTS
         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
-                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+                 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+                 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+                 ARCH_MSM_SCORPIONMP
         select USE_GENERIC_SMP_HELPERS
-        select HAVE_ARM_SCU
+        select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
         help
           This enables support for systems with more than one CPU. If you have
           a system with only one CPU, like most personal computers, say N. If
@@ -1293,6 +1296,7 @@ config NR_CPUS
 config HOTPLUG_CPU
         bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
         depends on SMP && HOTPLUG && EXPERIMENTAL
+        depends on !ARCH_MSM
         help
           Say Y here to experiment with turning CPUs off and on.  CPUs
           can be controlled through /sys/devices/system/cpu.
@@ -1301,7 +1305,7 @@ config LOCAL_TIMERS
         bool "Use local timer interrupts"
         depends on SMP
         default y
-        select HAVE_ARM_TWD
+        select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
         help
           Enable support for local timers on SMP platforms, rather then the
           legacy IPI broadcast method.  Local timers allows the system
@@ -1321,7 +1325,7 @@ config HZ
 
 config THUMB2_KERNEL
         bool "Compile the kernel in Thumb-2 mode"
-        depends on CPU_V7 && EXPERIMENTAL
+        depends on CPU_V7 && !CPU_V6 && EXPERIMENTAL
         select AEABI
         select ARM_ASM_UNIFIED
         help
@@ -1769,7 +1773,7 @@ comment "At least one emulation must be selected"
 
 config FPE_NWFPE
         bool "NWFPE math emulation"
-        depends on !AEABI || OABI_COMPAT
+        depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
         ---help---
           Say Y to include the NWFPE floating point emulator in the kernel.
           This is necessary to run most binaries. Linux does not currently
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 2fd0b99afc4b..eac62085f5b2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -23,7 +23,7 @@ config STRICT_DEVMEM
 config FRAME_POINTER
         bool
         depends on !THUMB2_KERNEL
-        default y if !ARM_UNWIND
+        default y if !ARM_UNWIND || FUNCTION_GRAPH_TRACER
         help
           If you say N here, the resulting kernel will be slightly smaller and
           faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled,
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 4d8ae9d67abe..f389b2704d82 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -20,8 +20,8 @@ struct arch_hw_breakpoint_ctrl {
 struct arch_hw_breakpoint {
         u32     address;
         u32     trigger;
-        struct perf_event *suspended_wp;
-        struct arch_hw_breakpoint_ctrl ctrl;
+        struct  arch_hw_breakpoint_ctrl step_ctrl;
+        struct  arch_hw_breakpoint_ctrl ctrl;
 };
 
 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 1120f18a6b17..ec4327a4653d 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -63,6 +63,11 @@
 #include <asm/outercache.h>
 
 #define __exception     __attribute__((section(".exception.text")))
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#define __exception_irq_entry   __irq_entry
+#else
+#define __exception_irq_entry   __exception
+#endif
 
 struct thread_info;
 struct task_struct;
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 491960bf4260..124475afb007 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -15,13 +15,32 @@ struct undef_hook {
 void register_undef_hook(struct undef_hook *hook);
 void unregister_undef_hook(struct undef_hook *hook);
 
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+static inline int __in_irqentry_text(unsigned long ptr)
+{
+        extern char __irqentry_text_start[];
+        extern char __irqentry_text_end[];
+
+        return ptr >= (unsigned long)&__irqentry_text_start &&
+               ptr < (unsigned long)&__irqentry_text_end;
+}
+#else
+static inline int __in_irqentry_text(unsigned long ptr)
+{
+        return 0;
+}
+#endif
+
 static inline int in_exception_text(unsigned long ptr)
 {
         extern char __exception_text_start[];
         extern char __exception_text_end[];
+        int in;
+
+        in = ptr >= (unsigned long)&__exception_text_start &&
+             ptr < (unsigned long)&__exception_text_end;
 
-        return ptr >= (unsigned long)&__exception_text_start &&
-               ptr < (unsigned long)&__exception_text_end;
+        return in ? : __in_irqentry_text(ptr);
 }
 
 extern void __init early_trap_init(void);
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 5b9b268f4fbb..c73abe4b7e72 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -5,7 +5,7 @@
 CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
 AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
 
-ifdef CONFIG_DYNAMIC_FTRACE
+ifdef CONFIG_FUNCTION_TRACER
 CFLAGS_REMOVE_ftrace.o = -pg
 endif
 
@@ -33,6 +33,7 @@ obj-$(CONFIG_SMP)		+= smp.o
 obj-$(CONFIG_HAVE_ARM_SCU)      += smp_scu.o
 obj-$(CONFIG_HAVE_ARM_TWD)      += smp_twd.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
+obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
 obj-$(CONFIG_KEXEC)             += machine_kexec.o relocate_kernel.o
 obj-$(CONFIG_KPROBES)           += kprobes.o kprobes-decode.o
 obj-$(CONFIG_ATAGS_PROC)        += atags.o
@@ -50,6 +51,7 @@ AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
 obj-$(CONFIG_CPU_XSCALE)        += xscale-cp0.o
 obj-$(CONFIG_CPU_XSC3)          += xscale-cp0.o
 obj-$(CONFIG_CPU_MOHAWK)        += xscale-cp0.o
+obj-$(CONFIG_CPU_PJ4)           += pj4-cp0.o
 obj-$(CONFIG_IWMMXT)            += iwmmxt.o
 obj-$(CONFIG_CPU_HAS_PMU)       += pmu.o
 obj-$(CONFIG_HW_PERF_EVENTS)    += perf_event.o
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bb96a7d4bbf5..36199ffc4cc2 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -198,6 +198,7 @@ __dabt_svc:
         @
         @ set desired IRQ state, then call main handler
         @
+        debug_entry r1
         msr     cpsr_c, r9
         mov     r2, sp
         bl      do_DataAbort
@@ -324,6 +325,7 @@ __pabt_svc:
 #else
         bl      CPU_PABORT_HANDLER
 #endif
+        debug_entry r1
         msr     cpsr_c, r9                      @ Maybe enable interrupts
         mov     r2, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
@@ -439,6 +441,7 @@ __dabt_usr:
         @
         @ IRQs on, then call the main handler
         @
+        debug_entry r1
         enable_irq
         mov     r2, sp
         adr     lr, BSYM(ret_from_exception)
@@ -703,6 +706,7 @@ __pabt_usr:
 #else
         bl      CPU_PABORT_HANDLER
 #endif
+        debug_entry r1
         enable_irq                              @ Enable interrupts
         mov     r2, sp                          @ regs
         bl      do_PrefetchAbort                @ call abort handler
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8bfa98757cd2..aae802ee12f8 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -141,98 +141,170 @@ ENDPROC(ret_from_fork)
 #endif
 #endif
 
-#ifdef CONFIG_DYNAMIC_FTRACE
-ENTRY(__gnu_mcount_nc)
-        mov     ip, lr
-        ldmia   sp!, {lr}
-        mov     pc, ip
-ENDPROC(__gnu_mcount_nc)
+.macro __mcount suffix
+        mcount_enter
+        ldr     r0, =ftrace_trace_function
+        ldr     r2, [r0]
+        adr     r0, .Lftrace_stub
+        cmp     r0, r2
+        bne     1f
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        ldr     r1, =ftrace_graph_return
+        ldr     r2, [r1]
+        cmp     r0, r2
+        bne     ftrace_graph_caller\suffix
+
+        ldr     r1, =ftrace_graph_entry
+        ldr     r2, [r1]
+        ldr     r0, =ftrace_graph_entry_stub
+        cmp     r0, r2
+        bne     ftrace_graph_caller\suffix
+#endif
 
-ENTRY(ftrace_caller)
-        stmdb   sp!, {r0-r3, lr}
-        mov     r0, lr
+        mcount_exit
+
+1:      mcount_get_lr   r1                      @ lr of instrumented func
+        mov     r0, lr                          @ instrumented function
+        sub     r0, r0, #MCOUNT_INSN_SIZE
+        adr     lr, BSYM(2f)
+        mov     pc, r2
+2:      mcount_exit
+.endm
+
+.macro __ftrace_caller suffix
+        mcount_enter
+
+        mcount_get_lr   r1                      @ lr of instrumented func
+        mov     r0, lr                          @ instrumented function
         sub     r0, r0, #MCOUNT_INSN_SIZE
-        ldr     r1, [sp, #20]
 
-        .global ftrace_call
-ftrace_call:
+        .globl ftrace_call\suffix
+ftrace_call\suffix:
         bl      ftrace_stub
-        ldmia   sp!, {r0-r3, ip, lr}
-        mov     pc, ip
-ENDPROC(ftrace_caller)
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl ftrace_graph_call\suffix
+ftrace_graph_call\suffix:
+        mov     r0, r0
+#endif
+
+        mcount_exit
+.endm
+
+.macro __ftrace_graph_caller
+        sub     r0, fp, #4              @ &lr of instrumented routine (&parent)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        @ called from __ftrace_caller, saved in mcount_enter
+        ldr     r1, [sp, #16]           @ instrumented routine (func)
+#else
+        @ called from __mcount, untouched in lr
+        mov     r1, lr                  @ instrumented routine (func)
+#endif
+        sub     r1, r1, #MCOUNT_INSN_SIZE
+        mov     r2, fp                  @ frame pointer
+        bl      prepare_ftrace_return
+        mcount_exit
+.endm
 
 #ifdef CONFIG_OLD_MCOUNT
+/*
+ * mcount
+ */
+
+.macro mcount_enter
+        stmdb   sp!, {r0-r3, lr}
+.endm
+
+.macro mcount_get_lr reg
+        ldr     \reg, [fp, #-4]
+.endm
+
+.macro mcount_exit
+        ldr     lr, [fp, #-4]
+        ldmia   sp!, {r0-r3, pc}
+.endm
+
 ENTRY(mcount)
+#ifdef CONFIG_DYNAMIC_FTRACE
         stmdb   sp!, {lr}
         ldr     lr, [fp, #-4]
         ldmia   sp!, {pc}
+#else
+        __mcount _old
+#endif
 ENDPROC(mcount)
 
+#ifdef CONFIG_DYNAMIC_FTRACE
 ENTRY(ftrace_caller_old)
-        stmdb   sp!, {r0-r3, lr}
-        ldr     r1, [fp, #-4]
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-
-        .globl ftrace_call_old
-ftrace_call_old:
-        bl      ftrace_stub
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
+        __ftrace_caller _old
 ENDPROC(ftrace_caller_old)
 #endif
 
-#else
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(ftrace_graph_caller_old)
+        __ftrace_graph_caller
+ENDPROC(ftrace_graph_caller_old)
+#endif
 
-ENTRY(__gnu_mcount_nc)
+.purgem mcount_enter
+.purgem mcount_get_lr
+.purgem mcount_exit
+#endif
+
+/*
+ * __gnu_mcount_nc
+ */
+
+.macro mcount_enter
         stmdb   sp!, {r0-r3, lr}
-        ldr     r0, =ftrace_trace_function
-        ldr     r2, [r0]
-        adr     r0, .Lftrace_stub
-        cmp     r0, r2
-        bne     gnu_trace
+.endm
+
+.macro mcount_get_lr reg
+        ldr     \reg, [sp, #20]
+.endm
+
+.macro mcount_exit
         ldmia   sp!, {r0-r3, ip, lr}
         mov     pc, ip
+.endm
 
-gnu_trace:
-        ldr     r1, [sp, #20]                   @ lr of instrumented routine
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-        adr     lr, BSYM(1f)
-        mov     pc, r2
-1:
-        ldmia   sp!, {r0-r3, ip, lr}
+ENTRY(__gnu_mcount_nc)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        mov     ip, lr
+        ldmia   sp!, {lr}
         mov     pc, ip
+#else
+        __mcount
+#endif
 ENDPROC(__gnu_mcount_nc)
 
-#ifdef CONFIG_OLD_MCOUNT
-/*
- * This is under an ifdef in order to force link-time errors for people trying
- * to build with !FRAME_POINTER with a GCC which doesn't use the new-style
- * mcount.
- */
-ENTRY(mcount)
-        stmdb   sp!, {r0-r3, lr}
-        ldr     r0, =ftrace_trace_function
-        ldr     r2, [r0]
-        adr     r0, ftrace_stub
-        cmp     r0, r2
-        bne     trace
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
+#ifdef CONFIG_DYNAMIC_FTRACE
+ENTRY(ftrace_caller)
+        __ftrace_caller
+ENDPROC(ftrace_caller)
+#endif
 
-trace:
-        ldr     r1, [fp, #-4]                   @ lr of instrumented routine
-        mov     r0, lr
-        sub     r0, r0, #MCOUNT_INSN_SIZE
-        mov     lr, pc
-        mov     pc, r2
-        ldr     lr, [fp, #-4]                   @ restore lr
-        ldmia   sp!, {r0-r3, pc}
-ENDPROC(mcount)
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+ENTRY(ftrace_graph_caller)
+        __ftrace_graph_caller
+ENDPROC(ftrace_graph_caller)
 #endif
 
-#endif /* CONFIG_DYNAMIC_FTRACE */
+.purgem mcount_enter
+.purgem mcount_get_lr
+.purgem mcount_exit
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl return_to_handler
+return_to_handler:
+        stmdb   sp!, {r0-r3}
+        mov     r0, fp                  @ frame pointer
+        bl      ftrace_return_to_handler
+        mov     lr, r0                  @ r0 has real ret addr
+        ldmia   sp!, {r0-r3}
+        mov     pc, lr
+#endif
 
 ENTRY(ftrace_stub)
 .Lftrace_stub:
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index d93f976fb389..ae9464900168 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -165,6 +165,25 @@
         .endm
 #endif  /* !CONFIG_THUMB2_KERNEL */
 
+        @
+        @ Debug exceptions are taken as prefetch or data aborts.
+        @ We must disable preemption during the handler so that
+        @ we can access the debug registers safely.
+        @
+        .macro  debug_entry, fsr
+#if defined(CONFIG_HAVE_HW_BREAKPOINT) && defined(CONFIG_PREEMPT)
+        ldr     r4, =0x40f              @ mask out fsr.fs
+        and     r5, r4, \fsr
+        cmp     r5, #2                  @ debug exception
+        bne     1f
+        get_thread_info r10
+        ldr     r6, [r10, #TI_PREEMPT]  @ get preempt count
+        add     r11, r6, #1             @ increment it
+        str     r11, [r10, #TI_PREEMPT]
+1:
+#endif
+        .endm
+
 /*
  * These are the registers used in the syscall handler, and allow us to
  * have in theory up to 7 arguments to a function - r0 to r6.
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index 971ac8c36ea7..c0062ad1e847 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -24,6 +24,7 @@
 #define NOP             0xe8bd4000      /* pop {lr} */
 #endif
 
+#ifdef CONFIG_DYNAMIC_FTRACE
 #ifdef CONFIG_OLD_MCOUNT
 #define OLD_MCOUNT_ADDR ((unsigned long) mcount)
 #define OLD_FTRACE_ADDR ((unsigned long) ftrace_caller_old)
@@ -59,9 +60,9 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
 }
 #endif
 
-/* construct a branch (BL) instruction to addr */
 #ifdef CONFIG_THUMB2_KERNEL
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr,
+                                       bool link)
 {
         unsigned long s, j1, j2, i1, i2, imm10, imm11;
         unsigned long first, second;
@@ -83,15 +84,22 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
         j2 = (!i2) ^ s;
 
         first = 0xf000 | (s << 10) | imm10;
-        second = 0xd000 | (j1 << 13) | (j2 << 11) | imm11;
+        second = 0x9000 | (j1 << 13) | (j2 << 11) | imm11;
+        if (link)
+                second |= 1 << 14;
 
         return (second << 16) | first;
 }
 #else
-static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+static unsigned long ftrace_gen_branch(unsigned long pc, unsigned long addr,
+                                       bool link)
 {
+        unsigned long opcode = 0xea000000;
         long offset;
 
+        if (link)
+                opcode |= 1 << 24;
+
         offset = (long)addr - (long)(pc + 8);
         if (unlikely(offset < -33554432 || offset > 33554428)) {
                 /* Can't generate branches that far (from ARM ARM). Ftrace
@@ -103,10 +111,15 @@ static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
 
         offset = (offset >> 2) & 0x00ffffff;
 
-        return 0xeb000000 | offset;
+        return opcode | offset;
 }
 #endif
 
+static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
+{
+        return ftrace_gen_branch(pc, addr, true);
+}
+
 static int ftrace_modify_code(unsigned long pc, unsigned long old,
                               unsigned long new)
 {
@@ -193,3 +206,83 @@ int __init ftrace_dyn_arch_init(void *data)
 
         return 0;
 }
+#endif /* CONFIG_DYNAMIC_FTRACE */
+
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+void prepare_ftrace_return(unsigned long *parent, unsigned long self_addr,
+                           unsigned long frame_pointer)
+{
+        unsigned long return_hooker = (unsigned long) &return_to_handler;
+        struct ftrace_graph_ent trace;
+        unsigned long old;
+        int err;
+
+        if (unlikely(atomic_read(&current->tracing_graph_pause)))
+                return;
+
+        old = *parent;
+        *parent = return_hooker;
+
+        err = ftrace_push_return_trace(old, self_addr, &trace.depth,
+                                       frame_pointer);
+        if (err == -EBUSY) {
+                *parent = old;
+                return;
+        }
+
+        trace.func = self_addr;
+
+        /* Only trace if the calling function expects to */
+        if (!ftrace_graph_entry(&trace)) {
+                current->curr_ret_stack--;
+                *parent = old;
+        }
+}
+
+#ifdef CONFIG_DYNAMIC_FTRACE
+extern unsigned long ftrace_graph_call;
+extern unsigned long ftrace_graph_call_old;
+extern void ftrace_graph_caller_old(void);
+
+static int __ftrace_modify_caller(unsigned long *callsite,
+                                  void (*func) (void), bool enable)
+{
+        unsigned long caller_fn = (unsigned long) func;
+        unsigned long pc = (unsigned long) callsite;
+        unsigned long branch = ftrace_gen_branch(pc, caller_fn, false);
+        unsigned long nop = 0xe1a00000; /* mov r0, r0 */
+        unsigned long old = enable ? nop : branch;
+        unsigned long new = enable ? branch : nop;
+
+        return ftrace_modify_code(pc, old, new);
+}
+
+static int ftrace_modify_graph_caller(bool enable)
+{
+        int ret;
+
+        ret = __ftrace_modify_caller(&ftrace_graph_call,
+                                     ftrace_graph_caller,
+                                     enable);
+
+#ifdef CONFIG_OLD_MCOUNT
+        if (!ret)
+                ret = __ftrace_modify_caller(&ftrace_graph_call_old,
+                                             ftrace_graph_caller_old,
+                                             enable);
+#endif
+
+        return ret;
+}
+
+int ftrace_enable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_graph_caller(true);
+}
+
+int ftrace_disable_ftrace_graph_caller(void)
+{
+        return ftrace_modify_graph_caller(false);
+}
+#endif /* CONFIG_DYNAMIC_FTRACE */
+#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 21e3a4ab3b8c..c9f3f0467570 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -24,6 +24,7 @@
 #define pr_fmt(fmt) "hw-breakpoint: " fmt
 
 #include <linux/errno.h>
+#include <linux/hardirq.h>
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/smp.h>
@@ -44,6 +45,7 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
 
 /* Number of BRP/WRP registers on this CPU. */
 static int core_num_brps;
+static int core_num_reserved_brps;
 static int core_num_wrps;
 
 /* Debug architecture version. */
@@ -52,87 +54,6 @@ static u8 debug_arch;
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
 
-/* Determine number of BRP registers available. */
-static int get_num_brps(void)
-{
-        u32 didr;
-        ARM_DBG_READ(c0, 0, didr);
-        return ((didr >> 24) & 0xf) + 1;
-}
-
-/* Determine number of WRP registers available. */
-static int get_num_wrps(void)
-{
-        /*
-         * FIXME: When a watchpoint fires, the only way to work out which
-         * watchpoint it was is by disassembling the faulting instruction
-         * and working out the address of the memory access.
-         *
-         * Furthermore, we can only do this if the watchpoint was precise
-         * since imprecise watchpoints prevent us from calculating register
-         * based addresses.
-         *
-         * For the time being, we only report 1 watchpoint register so we
-         * always know which watchpoint fired. In the future we can either
-         * add a disassembler and address generation emulator, or we can
-         * insert a check to see if the DFAR is set on watchpoint exception
-         * entry [the ARM ARM states that the DFAR is UNKNOWN, but
-         * experience shows that it is set on some implementations].
-         */
-
-#if 0
-        u32 didr, wrps;
-        ARM_DBG_READ(c0, 0, didr);
-        return ((didr >> 28) & 0xf) + 1;
-#endif
-
-        return 1;
-}
-
-int hw_breakpoint_slots(int type)
-{
-        /*
-         * We can be called early, so don't rely on
-         * our static variables being initialised.
-         */
-        switch (type) {
-        case TYPE_INST:
-                return get_num_brps();
-        case TYPE_DATA:
-                return get_num_wrps();
-        default:
-                pr_warning("unknown slot type: %d\n", type);
-                return 0;
-        }
-}
-
-/* Determine debug architecture. */
-static u8 get_debug_arch(void)
-{
-        u32 didr;
-
-        /* Do we implement the extended CPUID interface? */
-        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
-                pr_warning("CPUID feature registers not supported. "
-                                "Assuming v6 debug is present.\n");
-                return ARM_DEBUG_ARCH_V6;
-        }
-
-        ARM_DBG_READ(c0, 0, didr);
-        return (didr >> 16) & 0xf;
-}
-
-/* Does this core support mismatch breakpoints? */
-static int core_has_mismatch_bps(void)
-{
-        return debug_arch >= ARM_DEBUG_ARCH_V7_ECP14 && core_num_brps > 1;
-}
-
-u8 arch_get_debug_arch(void)
-{
-        return debug_arch;
-}
-
 #define READ_WB_REG_CASE(OP2, M, VAL)           \
         case ((OP2 << 4) + M):                  \
                 ARM_DBG_READ(c ## M, OP2, VAL); \
@@ -210,6 +131,94 @@ static void write_wb_reg(int n, u32 val)
         isb();
 }
 
+/* Determine debug architecture. */
+static u8 get_debug_arch(void)
+{
+        u32 didr;
+
+        /* Do we implement the extended CPUID interface? */
+        if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
+                pr_warning("CPUID feature registers not supported. "
+                                "Assuming v6 debug is present.\n");
+                return ARM_DEBUG_ARCH_V6;
+        }
+
+        ARM_DBG_READ(c0, 0, didr);
+        return (didr >> 16) & 0xf;
+}
+
+u8 arch_get_debug_arch(void)
+{
+        return debug_arch;
+}
+
+/* Determine number of BRP register available. */
+static int get_num_brp_resources(void)
+{
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        return ((didr >> 24) & 0xf) + 1;
+}
+
+/* Does this core support mismatch breakpoints? */
+static int core_has_mismatch_brps(void)
+{
+        return (get_debug_arch() >= ARM_DEBUG_ARCH_V7_ECP14 &&
+                get_num_brp_resources() > 1);
+}
+
+/* Determine number of usable WRPs available. */
+static int get_num_wrps(void)
+{
+        /*
+         * FIXME: When a watchpoint fires, the only way to work out which
+         * watchpoint it was is by disassembling the faulting instruction
+         * and working out the address of the memory access.
+         *
+         * Furthermore, we can only do this if the watchpoint was precise
+         * since imprecise watchpoints prevent us from calculating register
+         * based addresses.
+         *
+         * Providing we have more than 1 breakpoint register, we only report
+         * a single watchpoint register for the time being. This way, we always
+         * know which watchpoint fired. In the future we can either add a
+         * disassembler and address generation emulator, or we can insert a
+         * check to see if the DFAR is set on watchpoint exception entry
+         * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
+         * that it is set on some implementations].
+         */
+
+#if 0
+        int wrps;
+        u32 didr;
+        ARM_DBG_READ(c0, 0, didr);
+        wrps = ((didr >> 28) & 0xf) + 1;
+#endif
+        int wrps = 1;
+
+        if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
+                wrps = get_num_brp_resources() - 1;
+
+        return wrps;
+}
+
+/* We reserve one breakpoint for each watchpoint. */
+static int get_num_reserved_brps(void)
+{
+        if (core_has_mismatch_brps())
+                return get_num_wrps();
+        return 0;
+}
+
+/* Determine number of usable BRPs available. */
+static int get_num_brps(void)
+{
+        int brps = get_num_brp_resources();
+        if (core_has_mismatch_brps())
+                brps -= get_num_reserved_brps();
+        return brps;
+}
+
 /*
  * In order to access the breakpoint/watchpoint control registers,
  * we must be running in debug monitor mode. Unfortunately, we can
@@ -230,8 +239,12 @@ static int enable_monitor_mode(void)
                 goto out;
         }
 
+        /* If monitor mode is already enabled, just return. */
+        if (dscr & ARM_DSCR_MDBGEN)
+                goto out;
+
         /* Write to the corresponding DSCR. */
-        switch (debug_arch) {
+        switch (get_debug_arch()) {
         case ARM_DEBUG_ARCH_V6:
         case ARM_DEBUG_ARCH_V6_1:
                 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
@@ -246,15 +259,30 @@ static int enable_monitor_mode(void)
 
         /* Check that the write made it through. */
         ARM_DBG_READ(c1, 0, dscr);
-        if (WARN_ONCE(!(dscr & ARM_DSCR_MDBGEN),
-                                "failed to enable monitor mode.")) {
+        if (!(dscr & ARM_DSCR_MDBGEN))
                 ret = -EPERM;
-        }
 
 out:
         return ret;
 }
 
+int hw_breakpoint_slots(int type)
+{
+        /*
+         * We can be called early, so don't rely on
+         * our static variables being initialised.
+         */
+        switch (type) {
+        case TYPE_INST:
+                return get_num_brps();
+        case TYPE_DATA:
+                return get_num_wrps();
+        default:
+                pr_warning("unknown slot type: %d\n", type);
+                return 0;
+        }
+}
+
 /*
  * Check if 8-bit byte-address select is available.
  * This clobbers WRP 0.
@@ -268,9 +296,6 @@ static u8 get_max_wp_len(void)
         if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
                 goto out;
 
-        if (enable_monitor_mode())
-                goto out;
-
         memset(&ctrl, 0, sizeof(ctrl));
         ctrl.len = ARM_BREAKPOINT_LEN_8;
         ctrl_reg = encode_ctrl_reg(ctrl);
@@ -290,23 +315,6 @@ u8 arch_get_max_wp_len(void)
 }
 
 /*
- * Handler for reactivating a suspended watchpoint when the single
- * step `mismatch' breakpoint is triggered.
- */
-static void wp_single_step_handler(struct perf_event *bp, int unused,
-                                   struct perf_sample_data *data,
-                                   struct pt_regs *regs)
-{
-        perf_event_enable(counter_arch_bp(bp)->suspended_wp);
-        unregister_hw_breakpoint(bp);
-}
-
-static int bp_is_single_step(struct perf_event *bp)
-{
-        return bp->overflow_handler == wp_single_step_handler;
-}
-
-/*
  * Install a perf counter breakpoint.
  */
 int arch_install_hw_breakpoint(struct perf_event *bp)
@@ -314,30 +322,41 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
         struct perf_event **slot, **slots;
         int i, max_slots, ctrl_base, val_base, ret = 0;
+        u32 addr, ctrl;
 
         /* Ensure that we are in monitor mode and halting mode is disabled. */
         ret = enable_monitor_mode();
         if (ret)
                 goto out;
 
+        addr = info->address;
+        ctrl = encode_ctrl_reg(info->ctrl) | 0x1;
+
         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
                 /* Breakpoint */
                 ctrl_base = ARM_BASE_BCR;
                 val_base = ARM_BASE_BVR;
-                slots = __get_cpu_var(bp_on_reg);
-                max_slots = core_num_brps - 1;
-
-                if (bp_is_single_step(bp)) {
-                        info->ctrl.mismatch = 1;
-                        i = max_slots;
-                        slots[i] = bp;
-                        goto setup;
+                slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps;
+                if (info->step_ctrl.enabled) {
+                        /* Override the breakpoint data with the step data. */
+                        addr = info->trigger & ~0x3;
+                        ctrl = encode_ctrl_reg(info->step_ctrl);
                 }
         } else {
                 /* Watchpoint */
-                ctrl_base = ARM_BASE_WCR;
-                val_base = ARM_BASE_WVR;
-                slots = __get_cpu_var(wp_on_reg);
+                if (info->step_ctrl.enabled) {
+                        /* Install into the reserved breakpoint region. */
+                        ctrl_base = ARM_BASE_BCR + core_num_brps;
+                        val_base = ARM_BASE_BVR + core_num_brps;
+                        /* Override the watchpoint data with the step data. */
+                        addr = info->trigger & ~0x3;
+                        ctrl = encode_ctrl_reg(info->step_ctrl);
+                } else {
+                        ctrl_base = ARM_BASE_WCR;
+                        val_base = ARM_BASE_WVR;
+                }
+                slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
 
@@ -355,12 +374,11 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
                 goto out;
         }
 
-setup:
         /* Setup the address register. */
-        write_wb_reg(val_base + i, info->address);
+        write_wb_reg(val_base + i, addr);
 
         /* Setup the control register. */
-        write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl) | 0x1);
+        write_wb_reg(ctrl_base + i, ctrl);
 
 out:
         return ret;
@@ -375,18 +393,15 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
                 /* Breakpoint */
                 base = ARM_BASE_BCR;
-                slots = __get_cpu_var(bp_on_reg);
-                max_slots = core_num_brps - 1;
-
-                if (bp_is_single_step(bp)) {
-                        i = max_slots;
-                        slots[i] = NULL;
-                        goto reset;
-                }
+                slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+                max_slots = core_num_brps;
         } else {
                 /* Watchpoint */
-                base = ARM_BASE_WCR;
-                slots = __get_cpu_var(wp_on_reg);
+                if (info->step_ctrl.enabled)
+                        base = ARM_BASE_BCR + core_num_brps;
+                else
+                        base = ARM_BASE_WCR;
+                slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
                 max_slots = core_num_wrps;
         }
 
@@ -403,7 +418,6 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
         if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
                 return;
 
-reset:
         /* Reset the control register. */
         write_wb_reg(base + i, 0);
 }
@@ -537,12 +551,23 @@ static int arch_build_bp_info(struct perf_event *bp)
                 return -EINVAL;
         }
 
+        /*
+         * Breakpoints must be of length 2 (thumb) or 4 (ARM) bytes.
+         * Watchpoints can be of length 1, 2, 4 or 8 bytes if supported
+         * by the hardware and must be aligned to the appropriate number of
+         * bytes.
+         */
+        if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE &&
+            info->ctrl.len != ARM_BREAKPOINT_LEN_2 &&
+            info->ctrl.len != ARM_BREAKPOINT_LEN_4)
+                return -EINVAL;
+
         /* Address */
         info->address = bp->attr.bp_addr;
 
         /* Privilege */
         info->ctrl.privilege = ARM_BREAKPOINT_USER;
-        if (arch_check_bp_in_kernelspace(bp) && !bp_is_single_step(bp))
+        if (arch_check_bp_in_kernelspace(bp))
                 info->ctrl.privilege |= ARM_BREAKPOINT_PRIV;
 
         /* Enabled? */
@@ -561,7 +586,7 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
 {
         struct arch_hw_breakpoint *info = counter_arch_bp(bp);
         int ret = 0;
-        u32 bytelen, max_len, offset, alignment_mask = 0x3;
+        u32 offset, alignment_mask = 0x3;
 
         /* Build the arch_hw_breakpoint. */
         ret = arch_build_bp_info(bp);
@@ -571,84 +596,85 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
         /* Check address alignment. */
         if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
                 alignment_mask = 0x7;
-        if (info->address & alignment_mask) {
-                /*
-                 * Try to fix the alignment. This may result in a length
-                 * that is too large, so we must check for that.
-                 */
-                bytelen = get_hbp_len(info->ctrl.len);
-                max_len = info->ctrl.type == ARM_BREAKPOINT_EXECUTE ? 4 :
-                                max_watchpoint_len;
-
-                if (max_len >= 8)
-                        offset = info->address & 0x7;
-                else
-                        offset = info->address & 0x3;
-
-                if (bytelen > (1 << ((max_len - (offset + 1)) >> 1))) {
-                        ret = -EFBIG;
-                        goto out;
-                }
-
-                info->ctrl.len <<= offset;
-                info->address &= ~offset;
-
-                pr_debug("breakpoint alignment fixup: length = 0x%x, "
-                        "address = 0x%x\n", info->ctrl.len, info->address);
+        offset = info->address & alignment_mask;
+        switch (offset) {
+        case 0:
+                /* Aligned */
+                break;
+        case 1:
+                /* Allow single byte watchpoint. */
+                if (info->ctrl.len == ARM_BREAKPOINT_LEN_1)
+                        break;
+        case 2:
+                /* Allow halfword watchpoints and breakpoints. */
+                if (info->ctrl.len == ARM_BREAKPOINT_LEN_2)
+                        break;
+        default:
+                ret = -EINVAL;
+                goto out;
         }
 
+        info->address &= ~alignment_mask;
+        info->ctrl.len <<= offset;
+
         /*
          * Currently we rely on an overflow handler to take
          * care of single-stepping the breakpoint when it fires.
          * In the case of userspace breakpoints on a core with V7 debug,
-         * we can use the mismatch feature as a poor-man's hardware single-step.
+         * we can use the mismatch feature as a poor-man's hardware
+         * single-step, but this only works for per-task breakpoints.
          */
         if (WARN_ONCE(!bp->overflow_handler &&
-                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_bps()),
+                (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps()
+                 || !bp->hw.bp_target),
                         "overflow handler required but none found")) {
                 ret = -EINVAL;
-                goto out;
         }
 out:
         return ret;
 }
 
-static void update_mismatch_flag(int idx, int flag)
+/*
+ * Enable/disable single-stepping over the breakpoint bp at address addr.
+ */
+static void enable_single_step(struct perf_event *bp, u32 addr)
 {
-        struct perf_event *bp = __get_cpu_var(bp_on_reg[idx]);
-        struct arch_hw_breakpoint *info;
-
-        if (bp == NULL)
-                return;
+        struct arch_hw_breakpoint *info = counter_arch_bp(bp);
 
-        info = counter_arch_bp(bp);
+        arch_uninstall_hw_breakpoint(bp);
+        info->step_ctrl.mismatch  = 1;
+        info->step_ctrl.len       = ARM_BREAKPOINT_LEN_4;
+        info->step_ctrl.type      = ARM_BREAKPOINT_EXECUTE;
+        info->step_ctrl.privilege = info->ctrl.privilege;
+        info->step_ctrl.enabled   = 1;
+        info->trigger             = addr;
+        arch_install_hw_breakpoint(bp);
+}
 
-        /* Update the mismatch field to enter/exit `single-step' mode */
-        if (!bp->overflow_handler && info->ctrl.mismatch != flag) {
-                info->ctrl.mismatch = flag;
-                write_wb_reg(ARM_BASE_BCR + idx, encode_ctrl_reg(info->ctrl) | 0x1);
-        }
+static void disable_single_step(struct perf_event *bp)
+{
+        arch_uninstall_hw_breakpoint(bp);
+        counter_arch_bp(bp)->step_ctrl.enabled = 0;
+        arch_install_hw_breakpoint(bp);
 }
 
 static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
 {
         int i;
-        struct perf_event *bp, **slots = __get_cpu_var(wp_on_reg);
+        struct perf_event *wp, **slots;
         struct arch_hw_breakpoint *info;
-        struct perf_event_attr attr;
+
+        slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
 
         /* Without a disassembler, we can only handle 1 watchpoint. */
         BUG_ON(core_num_wrps > 1);
 
-        hw_breakpoint_init(&attr);
-        attr.bp_addr    = regs->ARM_pc & ~0x3;
-        attr.bp_len     = HW_BREAKPOINT_LEN_4;
-        attr.bp_type    = HW_BREAKPOINT_X;
-
         for (i = 0; i < core_num_wrps; ++i) {
                 rcu_read_lock();
 
-                if (slots[i] == NULL) {
+                wp = slots[i];
+
+                if (wp == NULL) {
                         rcu_read_unlock();
                         continue;
                 }
@@ -658,24 +684,51 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
                  * single watchpoint, we can set the trigger to the lowest
                  * possible faulting address.
                  */
-                info = counter_arch_bp(slots[i]);
-                info->trigger = slots[i]->attr.bp_addr;
+                info = counter_arch_bp(wp);
+                info->trigger = wp->attr.bp_addr;
                 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
-                perf_bp_event(slots[i], regs);
+                perf_bp_event(wp, regs);
 
                 /*
                  * If no overflow handler is present, insert a temporary
                  * mismatch breakpoint so we can single-step over the
                  * watchpoint trigger.
                  */
-                if (!slots[i]->overflow_handler) {
-                        bp = register_user_hw_breakpoint(&attr,
-                                                         wp_single_step_handler,
-                                                         current);
-                        counter_arch_bp(bp)->suspended_wp = slots[i];
-                        perf_event_disable(slots[i]);
-                }
+                if (!wp->overflow_handler)
+                        enable_single_step(wp, instruction_pointer(regs));
+
+                rcu_read_unlock();
+        }
+}
 
+static void watchpoint_single_step_handler(unsigned long pc)
+{
+        int i;
+        struct perf_event *wp, **slots;
+        struct arch_hw_breakpoint *info;
+
+        slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
+
+        for (i = 0; i < core_num_reserved_brps; ++i) {
+                rcu_read_lock();
+
+                wp = slots[i];
+
+                if (wp == NULL)
+                        goto unlock;
+
+                info = counter_arch_bp(wp);
+                if (!info->step_ctrl.enabled)
+                        goto unlock;
+
+                /*
+                 * Restore the original watchpoint if we've completed the
+                 * single-step.
+                 */
+                if (info->trigger != pc)
+                        disable_single_step(wp);
+
+unlock:
                 rcu_read_unlock();
         }
 }
@@ -683,62 +736,69 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
 static void breakpoint_handler(unsigned long unknown, struct pt_regs *regs)
 {
         int i;
-        int mismatch;
         u32 ctrl_reg, val, addr;
-        struct perf_event *bp, **slots = __get_cpu_var(bp_on_reg);
+        struct perf_event *bp, **slots;
         struct arch_hw_breakpoint *info;
         struct arch_hw_breakpoint_ctrl ctrl;
 
+        slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
+
         /* The exception entry code places the amended lr in the PC. */
         addr = regs->ARM_pc;
 
+        /* Check the currently installed breakpoints first. */
         for (i = 0; i < core_num_brps; ++i) {
                 rcu_read_lock();
 
                 bp = slots[i];
 
-                if (bp == NULL) {
-                        rcu_read_unlock();
-                        continue;
-                }
+                if (bp == NULL)
+                        goto unlock;
 
-                mismatch = 0;
+                info = counter_arch_bp(bp);
 
                 /* Check if the breakpoint value matches. */
                 val = read_wb_reg(ARM_BASE_BVR + i);
                 if (val != (addr & ~0x3))
-                        goto unlock;
+                        goto mismatch;
 
                 /* Possible match, check the byte address select to confirm. */
                 ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
                 decode_ctrl_reg(ctrl_reg, &ctrl);
                 if ((1 << (addr & 0x3)) & ctrl.len) {
-                        mismatch = 1;
-                        info = counter_arch_bp(bp);
                         info->trigger = addr;
-                }
-
-unlock:
-                if ((mismatch && !info->ctrl.mismatch) || bp_is_single_step(bp)) {
                         pr_debug("breakpoint fired: address = 0x%x\n", addr);
                         perf_bp_event(bp, regs);
+                        if (!bp->overflow_handler)
+                                enable_single_step(bp, addr);
+                        goto unlock;
                 }
 
-                update_mismatch_flag(i, mismatch);
+mismatch:
+                /* If we're stepping a breakpoint, it can now be restored. */
+                if (info->step_ctrl.enabled)
+                        disable_single_step(bp);
+unlock:
                 rcu_read_unlock();
         }
+
+        /* Handle any pending watchpoint single-step breakpoints. */
+        watchpoint_single_step_handler(addr);
 }
 
 /*
  * Called from either the Data Abort Handler [watchpoint] or the
- * Prefetch Abort Handler [breakpoint].
+ * Prefetch Abort Handler [breakpoint] with preemption disabled.
  */
 static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                                  struct pt_regs *regs)
 {
-        int ret = 1; /* Unhandled fault. */
+        int ret = 0;
         u32 dscr;
 
+        /* We must be called with preemption disabled. */
+        WARN_ON(preemptible());
+
         /* We only handle watchpoints and hardware breakpoints. */
         ARM_DBG_READ(c1, 0, dscr);
 
@@ -753,25 +813,47 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
                 watchpoint_handler(addr, regs);
                 break;
         default:
-                goto out;
+                ret = 1; /* Unhandled fault. */
         }
 
-        ret = 0;
-out:
+        /*
+         * Re-enable preemption after it was disabled in the
+         * low-level exception handling code.
+         */
+        preempt_enable();
+
         return ret;
 }
 
 /*
  * One-time initialisation.
  */
-static void __init reset_ctrl_regs(void *unused)
+static void reset_ctrl_regs(void *unused)
 {
         int i;
 
+        /*
+         * v7 debug contains save and restore registers so that debug state
+         * can be maintained across low-power modes without leaving
+         * the debug logic powered up. It is IMPLEMENTATION DEFINED whether
+         * we can write to the debug registers out of reset, so we must
+         * unlock the OS Lock Access Register to avoid taking undefined
+         * instruction exceptions later on.
+         */
+        if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
+                /*
+                 * Unconditionally clear the lock by writing a value
+                 * other than 0xC5ACCE55 to the access register.
+                 */
+                asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
+                isb();
+        }
+
         if (enable_monitor_mode())
                 return;
 
-        for (i = 0; i < core_num_brps; ++i) {
+        /* We must also reset any reserved registers. */
+        for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) {
                 write_wb_reg(ARM_BASE_BCR + i, 0UL);
                 write_wb_reg(ARM_BASE_BVR + i, 0UL);
         }
@@ -782,45 +864,57 @@ static void __init reset_ctrl_regs(void *unused)
         }
 }
 
+static int __cpuinit dbg_reset_notify(struct notifier_block *self,
+                                      unsigned long action, void *cpu)
+{
+        if (action == CPU_ONLINE)
+                smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata dbg_reset_nb = {
+        .notifier_call = dbg_reset_notify,
+};
+
 static int __init arch_hw_breakpoint_init(void)
 {
-        int ret = 0;
         u32 dscr;
 
         debug_arch = get_debug_arch();
 
         if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
                 pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
-                ret = -ENODEV;
-                goto out;
+                return 0;
         }
 
         /* Determine how many BRPs/WRPs are available. */
         core_num_brps = get_num_brps();
+        core_num_reserved_brps = get_num_reserved_brps();
         core_num_wrps = get_num_wrps();
 
         pr_info("found %d breakpoint and %d watchpoint registers.\n",
-                        core_num_brps, core_num_wrps);
+                core_num_brps + core_num_reserved_brps, core_num_wrps);
 
-        if (core_has_mismatch_bps())
-                pr_info("1 breakpoint reserved for watchpoint single-step.\n");
+        if (core_num_reserved_brps)
+                pr_info("%d breakpoint(s) reserved for watchpoint "
+                                "single-step.\n", core_num_reserved_brps);
 
         ARM_DBG_READ(c1, 0, dscr);
         if (dscr & ARM_DSCR_HDBGEN) {
                 pr_warning("halting debug mode enabled. Assuming maximum "
                                 "watchpoint size of 4 bytes.");
         } else {
-                /* Work out the maximum supported watchpoint length. */
-                max_watchpoint_len = get_max_wp_len();
-                pr_info("maximum watchpoint size is %u bytes.\n",
-                                max_watchpoint_len);
-
                 /*
                  * Reset the breakpoint resources. We assume that a halting
                  * debugger will leave the world in a nice state for us.
                  */
                 smp_call_function(reset_ctrl_regs, NULL, 1);
                 reset_ctrl_regs(NULL);
+
+                /* Work out the maximum supported watchpoint length. */
+                max_watchpoint_len = get_max_wp_len();
+                pr_info("maximum watchpoint size is %u bytes.\n",
+                                max_watchpoint_len);
         }
 
         /* Register debug fault handler. */
@@ -829,8 +923,9 @@ static int __init arch_hw_breakpoint_init(void)
         hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, TRAP_HWBKPT,
                         "breakpoint debug exception");
 
-out:
-        return ret;
+        /* Register hotplug notifier. */
+        register_cpu_notifier(&dbg_reset_nb);
+        return 0;
 }
 arch_initcall(arch_hw_breakpoint_init);
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 36ad3be4692a..6d616333340f 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -35,6 +35,7 @@
 #include <linux/list.h>
 #include <linux/kallsyms.h>
 #include <linux/proc_fs.h>
+#include <linux/ftrace.h>
 
 #include <asm/system.h>
 #include <asm/mach/irq.h>
@@ -105,7 +106,8 @@ unlock:
  * come via this function.  Instead, they should provide their
  * own 'handler'
  */
-asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+asmlinkage void __exception_irq_entry
+asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
 
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index b63b528f22a6..7fa3bb0d2397 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -19,6 +19,14 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 
+#if defined(CONFIG_CPU_PJ4)
+#define PJ4(code...)            code
+#define XSC(code...)
+#else
+#define PJ4(code...)
+#define XSC(code...)            code
+#endif
+
 #define MMX_WR0                 (0x00)
 #define MMX_WR1                 (0x08)
 #define MMX_WR2                 (0x10)
@@ -58,11 +66,17 @@
 
 ENTRY(iwmmxt_task_enable)
 
-        mrc     p15, 0, r2, c15, c1, 0
-        tst     r2, #0x3                        @ CP0 and CP1 accessible?
+        XSC(mrc p15, 0, r2, c15, c1, 0)
+        PJ4(mrc p15, 0, r2, c1, c0, 2)
+        @ CP0 and CP1 accessible?
+        XSC(tst r2, #0x3)
+        PJ4(tst r2, #0xf)
         movne   pc, lr                          @ if so no business here
-        orr     r2, r2, #0x3                    @ enable access to CP0 and CP1
-        mcr     p15, 0, r2, c15, c1, 0
+        @ enable access to CP0 and CP1
+        XSC(orr r2, r2, #0x3)
+        XSC(mcr p15, 0, r2, c15, c1, 0)
+        PJ4(orr r2, r2, #0xf)
+        PJ4(mcr p15, 0, r2, c1, c0, 2)
 
         ldr     r3, =concan_owner
         add     r0, r10, #TI_IWMMXT_STATE       @ get task Concan save area
@@ -179,17 +193,26 @@ ENTRY(iwmmxt_task_disable)
         teqne   r1, r2                          @ or specified one?
         bne     1f                              @ no: quit
 
-        mrc     p15, 0, r4, c15, c1, 0
-        orr     r4, r4, #0x3                    @ enable access to CP0 and CP1
-        mcr     p15, 0, r4, c15, c1, 0
+        @ enable access to CP0 and CP1
+        XSC(mrc p15, 0, r4, c15, c1, 0)
+        XSC(orr r4, r4, #0xf)
+        XSC(mcr p15, 0, r4, c15, c1, 0)
+        PJ4(mrc p15, 0, r4, c1, c0, 2)
+        PJ4(orr r4, r4, #0x3)
+        PJ4(mcr p15, 0, r4, c1, c0, 2)
+
         mov     r0, #0                          @ nothing to load
         str     r0, [r3]                        @ no more current owner
         mrc     p15, 0, r2, c2, c0, 0
         mov     r2, r2                          @ cpwait
         bl      concan_save
 
-        bic     r4, r4, #0x3                    @ disable access to CP0 and CP1
-        mcr     p15, 0, r4, c15, c1, 0
+        @ disable access to CP0 and CP1
+        XSC(bic r4, r4, #0x3)
+        XSC(mcr p15, 0, r4, c15, c1, 0)
+        PJ4(bic r4, r4, #0xf)
+        PJ4(mcr p15, 0, r4, c1, c0, 2)
+
         mrc     p15, 0, r2, c2, c0, 0
         mov     r2, r2                          @ cpwait
 
@@ -277,8 +300,11 @@ ENTRY(iwmmxt_task_restore)
  */
 ENTRY(iwmmxt_task_switch)
 
-        mrc     p15, 0, r1, c15, c1, 0
-        tst     r1, #0x3                        @ CP0 and CP1 accessible?
+        XSC(mrc p15, 0, r1, c15, c1, 0)
+        PJ4(mrc p15, 0, r1, c1, c0, 2)
+        @ CP0 and CP1 accessible?
+        XSC(tst r1, #0x3)
+        PJ4(tst r1, #0xf)
         bne     1f                              @ yes: block them for next task
 
         ldr     r2, =concan_owner
@@ -287,8 +313,11 @@ ENTRY(iwmmxt_task_switch)
         teq     r2, r3                          @ next task owns it?
         movne   pc, lr                          @ no: leave Concan disabled
 
-1:      eor     r1, r1, #3                      @ flip Concan access
-        mcr     p15, 0, r1, c15, c1, 0
+1:      @ flip Conan access
+        XSC(eor r1, r1, #0x3)
+        XSC(mcr p15, 0, r1, c15, c1, 0)
+        PJ4(eor r1, r1, #0xf)
+        PJ4(mcr p15, 0, r1, c1, c0, 2)
 
         mrc     p15, 0, r1, c2, c0, 0
         sub     pc, lr, r1, lsr #32             @ cpwait and return
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 07a50357492a..624e2a5de2b3 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -4,9 +4,7 @@
  * ARM performance counter support.
  *
  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
- *
- * ARMv7 support: Jean Pihet <jpihet@mvista.com>
- * 2010 (c) MontaVista Software, LLC.
+ * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
  *
  * This code is based on the sparc64 perf event code, which is in turn based
  * on the x86 code. Callchain code is based on the ARM OProfile backtrace
@@ -34,7 +32,7 @@ static struct platform_device *pmu_device;
  * Hardware lock to serialize accesses to PMU registers. Needed for the
  * read/modify/write sequences.
  */
-DEFINE_SPINLOCK(pmu_lock);
+static DEFINE_RAW_SPINLOCK(pmu_lock);
 
 /*
  * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
@@ -67,31 +65,25 @@ struct cpu_hw_events {
          */
         unsigned long           active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
 };
-DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
-
-/* PMU names. */
-static const char *arm_pmu_names[] = {
-        [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
-        [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
-        [ARM_PERF_PMU_ID_V6]      = "v6",
-        [ARM_PERF_PMU_ID_V6MP]    = "v6mpcore",
-        [ARM_PERF_PMU_ID_CA8]     = "ARMv7 Cortex-A8",
-        [ARM_PERF_PMU_ID_CA9]     = "ARMv7 Cortex-A9",
-};
+static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
 
 struct arm_pmu {
         enum arm_perf_pmu_ids id;
+        const char      *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
         void            (*enable)(struct hw_perf_event *evt, int idx);
         void            (*disable)(struct hw_perf_event *evt, int idx);
-        int             (*event_map)(int evt);
-        u64             (*raw_event)(u64);
         int             (*get_event_idx)(struct cpu_hw_events *cpuc,
                                          struct hw_perf_event *hwc);
         u32             (*read_counter)(int idx);
         void            (*write_counter)(int idx, u32 val);
         void            (*start)(void);
         void            (*stop)(void);
+        const unsigned  (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+                                    [PERF_COUNT_HW_CACHE_OP_MAX]
+                                    [PERF_COUNT_HW_CACHE_RESULT_MAX];
+        const unsigned  (*event_map)[PERF_COUNT_HW_MAX];
+        u32             raw_event_mask;
         int             num_events;
         u64             max_period;
 };
@@ -136,10 +128,6 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
 
 #define CACHE_OP_UNSUPPORTED            0xFFFF
 
-static unsigned armpmu_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                     [PERF_COUNT_HW_CACHE_OP_MAX]
-                                     [PERF_COUNT_HW_CACHE_RESULT_MAX];
-
 static int
 armpmu_map_cache_event(u64 config)
 {
@@ -157,7 +145,7 @@ armpmu_map_cache_event(u64 config)
         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
                 return -EINVAL;
 
-        ret = (int)armpmu_perf_cache_map[cache_type][cache_op][cache_result];
+        ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
 
         if (ret == CACHE_OP_UNSUPPORTED)
                 return -ENOENT;
@@ -166,6 +154,19 @@ armpmu_map_cache_event(u64 config)
 }
 
 static int
+armpmu_map_event(u64 config)
+{
+        int mapping = (*armpmu->event_map)[config];
+        return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
+}
+
+static int
+armpmu_map_raw_event(u64 config)
+{
+        return (int)(config & armpmu->raw_event_mask);
+}
+
+static int
 armpmu_event_set_period(struct perf_event *event,
                         struct hw_perf_event *hwc,
                         int idx)
@@ -458,11 +459,11 @@ __hw_perf_event_init(struct perf_event *event)
 
         /* Decode the generic type into an ARM event identifier. */
         if (PERF_TYPE_HARDWARE == event->attr.type) {
-                mapping = armpmu->event_map(event->attr.config);
+                mapping = armpmu_map_event(event->attr.config);
         } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
                 mapping = armpmu_map_cache_event(event->attr.config);
         } else if (PERF_TYPE_RAW == event->attr.type) {
-                mapping = armpmu->raw_event(event->attr.config);
+                mapping = armpmu_map_raw_event(event->attr.config);
         } else {
                 pr_debug("event type %x not supported\n", event->attr.type);
                 return -EOPNOTSUPP;
@@ -603,2366 +604,10 @@ static struct pmu pmu = {
         .read           = armpmu_read,
 };
 
-/*
- * ARMv6 Performance counter handling code.
- *
- * ARMv6 has 2 configurable performance counters and a single cycle counter.
- * They all share a single reset bit but can be written to zero so we can use
- * that for a reset.
- *
- * The counters can't be individually enabled or disabled so when we remove
- * one event and replace it with another we could get spurious counts from the
- * wrong event. However, we can take advantage of the fact that the
- * performance counters can export events to the event bus, and the event bus
- * itself can be monitored. This requires that we *don't* export the events to
- * the event bus. The procedure for disabling a configurable counter is:
- *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
- *        effectively stops the counter from counting.
- *      - disable the counter's interrupt generation (each counter has it's
- *        own interrupt enable bit).
- * Once stopped, the counter value can be written as 0 to reset.
- *
- * To enable a counter:
- *      - enable the counter's interrupt generation.
- *      - set the new event type.
- *
- * Note: the dedicated cycle counter only counts cycles and can't be
- * enabled/disabled independently of the others. When we want to disable the
- * cycle counter, we have to just disable the interrupt reporting and start
- * ignoring that counter. When re-enabling, we have to reset the value and
- * enable the interrupt.
- */
-
-enum armv6_perf_types {
-        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
-        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
-        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
-        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
-        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
-        ARMV6_PERFCTR_BR_EXEC               = 0x5,
-        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
-        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
-        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
-        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
-        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
-        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
-        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
-        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
-        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
-        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
-        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
-        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
-        ARMV6_PERFCTR_NOP                   = 0x20,
-};
-
-enum armv6_counters {
-        ARMV6_CYCLE_COUNTER = 1,
-        ARMV6_COUNTER0,
-        ARMV6_COUNTER1,
-};
-
-/*
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * The ARM performance counters can count micro DTLB misses,
-                 * micro ITLB misses and main TLB misses. There isn't an event
-                 * for TLB misses, so use the micro misses here and if users
-                 * want the main TLB misses they can use a raw counter.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-enum armv6mpcore_perf_types {
-        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
-        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
-        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
-        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
-        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
-        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
-        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
-        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
-        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
-        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
-        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
-        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
-        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
-        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
-        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
-        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
-        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
-        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
-        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
-        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
-};
-
-/*
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                        [PERF_COUNT_HW_CACHE_OP_MAX]
-                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  =
-                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
-                        [C(RESULT_MISS)]    =
-                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  =
-                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
-                        [C(RESULT_MISS)]    =
-                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * The ARM performance counters can count micro DTLB misses,
-                 * micro ITLB misses and main TLB misses. There isn't an event
-                 * for TLB misses, so use the micro misses here and if users
-                 * want the main TLB misses they can use a raw counter.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-static inline unsigned long
-armv6_pmcr_read(void)
-{
-        u32 val;
-        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
-        return val;
-}
-
-static inline void
-armv6_pmcr_write(unsigned long val)
-{
-        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
-}
-
-#define ARMV6_PMCR_ENABLE               (1 << 0)
-#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
-#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
-#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
-#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
-#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
-#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
-#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
-#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
-#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
-#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
-#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
-#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
-#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
-
-#define ARMV6_PMCR_OVERFLOWED_MASK \
-        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
-         ARMV6_PMCR_CCOUNT_OVERFLOW)
-
-static inline int
-armv6_pmcr_has_overflowed(unsigned long pmcr)
-{
-        return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
-}
-
-static inline int
-armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
-                                  enum armv6_counters counter)
-{
-        int ret = 0;
-
-        if (ARMV6_CYCLE_COUNTER == counter)
-                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
-        else if (ARMV6_COUNTER0 == counter)
-                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
-        else if (ARMV6_COUNTER1 == counter)
-                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-
-        return ret;
-}
-
-static inline u32
-armv6pmu_read_counter(int counter)
-{
-        unsigned long value = 0;
-
-        if (ARMV6_CYCLE_COUNTER == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
-        else if (ARMV6_COUNTER0 == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
-        else if (ARMV6_COUNTER1 == counter)
-                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-
-        return value;
-}
-
-static inline void
-armv6pmu_write_counter(int counter,
-                       u32 value)
-{
-        if (ARMV6_CYCLE_COUNTER == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
-        else if (ARMV6_COUNTER0 == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
-        else if (ARMV6_COUNTER1 == counter)
-                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
-        else
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-}
-
-void
-armv6pmu_enable_event(struct hw_perf_event *hwc,
-                      int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = 0;
-                evt     = ARMV6_PMCR_CCOUNT_IEN;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
-                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
-                          ARMV6_PMCR_COUNT0_IEN;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
-                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
-                          ARMV6_PMCR_COUNT1_IEN;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Mask out the current event and set the counter to count the event
-         * that we're interested in.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static irqreturn_t
-armv6pmu_handle_irq(int irq_num,
-                    void *dev)
-{
-        unsigned long pmcr = armv6_pmcr_read();
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        if (!armv6_pmcr_has_overflowed(pmcr))
-                return IRQ_NONE;
-
-        regs = get_irq_regs();
-
-        /*
-         * The interrupts are cleared by writing the overflow flags back to
-         * the control register. All of the other bits don't have any effect
-         * if they are rewritten, so write the whole value back.
-         */
-        armv6_pmcr_write(pmcr);
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                /*
-                 * We have a single interrupt for all counters. Check that
-                 * each counter has overflowed before we process it.
-                 */
-                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        /*
-         * Handle the pending perf events.
-         *
-         * Note: this call *must* be run with interrupts disabled. For
-         * platforms that can have the PMU interrupts raised as an NMI, this
-         * will not work.
-         */
-        irq_work_run();
-
-        return IRQ_HANDLED;
-}
-
-static void
-armv6pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val |= ARMV6_PMCR_ENABLE;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-void
-armv6pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~ARMV6_PMCR_ENABLE;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline int
-armv6pmu_event_map(int config)
-{
-        int mapping = armv6_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static inline int
-armv6mpcore_pmu_event_map(int config)
-{
-        int mapping = armv6mpcore_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64
-armv6pmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-static int
-armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                       struct hw_perf_event *event)
-{
-        /* Always place a cycle counter into the cycle counter. */
-        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
-                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return ARMV6_CYCLE_COUNTER;
-        } else {
-                /*
-                 * For anything other than a cycle counter, try and use
-                 * counter0 and counter1.
-                 */
-                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
-                        return ARMV6_COUNTER1;
-                }
-
-                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
-                        return ARMV6_COUNTER0;
-                }
-
-                /* The counters are all in use. */
-                return -EAGAIN;
-        }
-}
-
-static void
-armv6pmu_disable_event(struct hw_perf_event *hwc,
-                       int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = ARMV6_PMCR_CCOUNT_IEN;
-                evt     = 0;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
-                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
-                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Mask out the current event and set the counter to count the number
-         * of ETM bus signal assertion cycles. The external reporting should
-         * be disabled and so this should never increment.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
-                              int idx)
-{
-        unsigned long val, mask, flags, evt = 0;
-
-        if (ARMV6_CYCLE_COUNTER == idx) {
-                mask    = ARMV6_PMCR_CCOUNT_IEN;
-        } else if (ARMV6_COUNTER0 == idx) {
-                mask    = ARMV6_PMCR_COUNT0_IEN;
-        } else if (ARMV6_COUNTER1 == idx) {
-                mask    = ARMV6_PMCR_COUNT1_IEN;
-        } else {
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        /*
-         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
-         * simply disable the interrupt reporting.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = armv6_pmcr_read();
-        val &= ~mask;
-        val |= evt;
-        armv6_pmcr_write(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static const struct arm_pmu armv6pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6,
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6pmu_disable_event,
-        .event_map              = armv6pmu_event_map,
-        .raw_event              = armv6pmu_raw_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-/*
- * ARMv6mpcore is almost identical to single core ARMv6 with the exception
- * that some of the events have different enumerations and that there is no
- * *hack* to stop the programmable counters. To stop the counters we simply
- * disable the interrupt reporting and update the event. When unthrottling we
- * reset the period and enable the interrupt reporting.
- */
-static const struct arm_pmu armv6mpcore_pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6MP,
-        .handle_irq             = armv6pmu_handle_irq,
-        .enable                 = armv6pmu_enable_event,
-        .disable                = armv6mpcore_pmu_disable_event,
-        .event_map              = armv6mpcore_pmu_event_map,
-        .raw_event              = armv6pmu_raw_event,
-        .read_counter           = armv6pmu_read_counter,
-        .write_counter          = armv6pmu_write_counter,
-        .get_event_idx          = armv6pmu_get_event_idx,
-        .start                  = armv6pmu_start,
-        .stop                   = armv6pmu_stop,
-        .num_events             = 3,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-/*
- * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
- *
- * Copied from ARMv6 code, with the low level code inspired
- *  by the ARMv7 Oprofile code.
- *
- * Cortex-A8 has up to 4 configurable performance counters and
- *  a single cycle counter.
- * Cortex-A9 has up to 31 configurable performance counters and
- *  a single cycle counter.
- *
- * All counters can be enabled/disabled and IRQ masked separately. The cycle
- *  counter and all 4 performance counters together can be reset separately.
- */
-
-/* Common ARMv7 event types */
-enum armv7_perf_types {
-        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
-        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
-        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
-        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
-        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
-        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
-        ARMV7_PERFCTR_DREAD                     = 0x06,
-        ARMV7_PERFCTR_DWRITE                    = 0x07,
-
-        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
-        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
-        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
-        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
-         * It counts:
-         *  - all branch instructions,
-         *  - instructions that explicitly write the PC,
-         *  - exception generating instructions.
-         */
-        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
-        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
-        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
-        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
-
-        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
-
-        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
-};
-
-/* ARMv7 Cortex-A8 specific event types */
-enum armv7_a8_perf_types {
-        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
-
-        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
-
-        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
-        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
-        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
-        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
-        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
-        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
-        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
-        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
-        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
-        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
-        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
-        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
-        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
-        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
-        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
-        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
-        ARMV7_PERFCTR_L1_INST                   = 0x50,
-        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
-        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
-        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
-        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
-        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
-        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
-        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
-        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
-        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
-        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
-
-        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
-        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
-        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
-};
-
-/* ARMv7 Cortex-A9 specific event types */
-enum armv7_a9_perf_types {
-        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
-        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
-        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
-
-        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
-        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
-
-        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
-        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
-        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
-        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
-        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
-        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
-        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
-        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
-        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
-
-        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
-
-        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
-        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
-        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
-        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
-        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
-
-        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
-        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
-        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
-        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
-        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
-        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
-        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
-
-        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
-        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
-
-        ARMV7_PERFCTR_ISB_INST                  = 0x90,
-        ARMV7_PERFCTR_DSB_INST                  = 0x91,
-        ARMV7_PERFCTR_DMB_INST                  = 0x92,
-        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
-
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
-        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
-        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
-        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
-        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
-        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
-};
-
-/*
- * Cortex-A8 HW events mapping
- *
- * The hardware events that we support. We do support cache operations but
- * we have harvard caches and no way to combine instruction and data
- * accesses/misses in hardware.
- */
-static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
-};
-
-static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * Only ITLB misses and DTLB refills are supported.
-                 * If users want the DTLB refills misses a raw counter
-                 * must be used.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-/*
- * Cortex-A9 HW events mapping
- */
-static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
-        [PERF_COUNT_HW_INSTRUCTIONS]        =
-                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
-        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
-};
-
-static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                          [PERF_COUNT_HW_CACHE_OP_MAX]
-                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                /*
-                 * The performance counters don't differentiate between read
-                 * and write accesses/misses so this isn't strictly correct,
-                 * but it's the best we can do. Writes and reads get
-                 * combined.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                /*
-                 * Only ITLB misses and DTLB refills are supported.
-                 * If users want the DTLB refills misses a raw counter
-                 * must be used.
-                 */
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
-                        [C(RESULT_MISS)]
-                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-/*
- * Perf Events counters
- */
-enum armv7_counters {
-        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
-        ARMV7_COUNTER0                  = 2,    /* First event counter */
-};
-
-/*
- * The cycle counter is ARMV7_CYCLE_COUNTER.
- * The first event counter is ARMV7_COUNTER0.
- * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
- */
-#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
-
-/*
- * ARMv7 low level PMNC access
- */
-
-/*
- * Per-CPU PMNC: config reg
- */
-#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
-#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
-#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
-#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
-#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
-#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
-#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
-#define ARMV7_PMNC_N_MASK       0x1f
-#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
-
-/*
- * Available counters
- */
-#define ARMV7_CNT0              0       /* First event counter */
-#define ARMV7_CCNT              31      /* Cycle counter */
-
-/* Perf Event to low level counters mapping */
-#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
-
-/*
- * CNTENS: counters enable reg
- */
-#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * CNTENC: counters disable reg
- */
-#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENS: counters overflow interrupt enable reg
- */
-#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
-
-/*
- * INTENC: counters overflow interrupt disable reg
- */
-#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
-
-/*
- * EVTSEL: Event selection reg
- */
-#define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
-
-/*
- * SELECT: Counter selection reg
- */
-#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
-
-/*
- * FLAG: counters overflow flag status reg
- */
-#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
-#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
-#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
-#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
-
-static inline unsigned long armv7_pmnc_read(void)
-{
-        u32 val;
-        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
-        return val;
-}
-
-static inline void armv7_pmnc_write(unsigned long val)
-{
-        val &= ARMV7_PMNC_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
-}
-
-static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
-{
-        return pmnc & ARMV7_OVERFLOWED_MASK;
-}
-
-static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
-                                        enum armv7_counters counter)
-{
-        int ret = 0;
-
-        if (counter == ARMV7_CYCLE_COUNTER)
-                ret = pmnc & ARMV7_FLAG_C;
-        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
-                ret = pmnc & ARMV7_FLAG_P(counter);
-        else
-                pr_err("CPU%u checking wrong counter %d overflow status\n",
-                        smp_processor_id(), counter);
-
-        return ret;
-}
-
-static inline int armv7_pmnc_select_counter(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
-                pr_err("CPU%u selecting wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7pmu_read_counter(int idx)
-{
-        unsigned long value = 0;
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
-                                     : "=r" (value));
-        } else
-                pr_err("CPU%u reading wrong counter %d\n",
-                        smp_processor_id(), idx);
-
-        return value;
-}
-
-static inline void armv7pmu_write_counter(int idx, u32 value)
-{
-        if (idx == ARMV7_CYCLE_COUNTER)
-                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
-        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
-                if (armv7_pmnc_select_counter(idx) == idx)
-                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
-                                     : : "r" (value));
-        } else
-                pr_err("CPU%u writing wrong counter %d\n",
-                        smp_processor_id(), idx);
-}
-
-static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
-{
-        if (armv7_pmnc_select_counter(idx) == idx) {
-                val &= ARMV7_EVTSEL_MASK;
-                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
-        }
-}
-
-static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENS_C;
-        else
-                val = ARMV7_CNTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
-{
-        u32 val;
-
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_CNTENC_C;
-        else
-                val = ARMV7_CNTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u enabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENS_C;
-        else
-                val = ARMV7_INTENS_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
-{
-        u32 val;
-
-        if ((idx != ARMV7_CYCLE_COUNTER) &&
-            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
-                pr_err("CPU%u disabling wrong PMNC counter"
-                        " interrupt enable %d\n", smp_processor_id(), idx);
-                return -1;
-        }
-
-        if (idx == ARMV7_CYCLE_COUNTER)
-                val = ARMV7_INTENC_C;
-        else
-                val = ARMV7_INTENC_P(idx);
-
-        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
-
-        return idx;
-}
-
-static inline u32 armv7_pmnc_getreset_flags(void)
-{
-        u32 val;
-
-        /* Read */
-        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
-
-        /* Write to clear flags */
-        val &= ARMV7_FLAG_MASK;
-        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
-
-        return val;
-}
-
-#ifdef DEBUG
-static void armv7_pmnc_dump_regs(void)
-{
-        u32 val;
-        unsigned int cnt;
-
-        printk(KERN_INFO "PMNC registers dump:\n");
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
-        printk(KERN_INFO "PMNC  =0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
-        printk(KERN_INFO "CNTENS=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
-        printk(KERN_INFO "INTENS=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
-        printk(KERN_INFO "FLAGS =0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
-        printk(KERN_INFO "SELECT=0x%08x\n", val);
-
-        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
-        printk(KERN_INFO "CCNT  =0x%08x\n", val);
-
-        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
-                armv7_pmnc_select_counter(cnt);
-                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
-                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
-                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
-                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
-        }
-}
-#endif
-
-void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags;
-
-        /*
-         * Enable counter and interrupt, and set the counter to count
-         * the event that we're interested in.
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-
-        /*
-         * Disable counter
-         */
-        armv7_pmnc_disable_counter(idx);
-
-        /*
-         * Set event (if destined for PMNx counters)
-         * We don't need to set the event if it's a cycle count
-         */
-        if (idx != ARMV7_CYCLE_COUNTER)
-                armv7_pmnc_write_evtsel(idx, hwc->config_base);
-
-        /*
-         * Enable interrupt for this counter
-         */
-        armv7_pmnc_enable_intens(idx);
-
-        /*
-         * Enable counter
-         */
-        armv7_pmnc_enable_counter(idx);
-
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags;
-
-        /*
-         * Disable counter and interrupt
-         */
-        spin_lock_irqsave(&pmu_lock, flags);
-
-        /*
-         * Disable counter
-         */
-        armv7_pmnc_disable_counter(idx);
-
-        /*
-         * Disable interrupt for this counter
-         */
-        armv7_pmnc_disable_intens(idx);
-
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /*
-         * Get and reset the IRQ flags
-         */
-        pmnc = armv7_pmnc_getreset_flags();
-
-        /*
-         * Did an overflow occur?
-         */
-        if (!armv7_pmnc_has_overflowed(pmnc))
-                return IRQ_NONE;
-
-        /*
-         * Handle the counter(s) overflow(s)
-         */
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                /*
-                 * We have a single interrupt for all counters. Check that
-                 * each counter has overflowed before we process it.
-                 */
-                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        /*
-         * Handle the pending perf events.
-         *
-         * Note: this call *must* be run with interrupts disabled. For
-         * platforms that can have the PMU interrupts raised as an NMI, this
-         * will not work.
-         */
-        irq_work_run();
-
-        return IRQ_HANDLED;
-}
-
-static void armv7pmu_start(void)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        /* Enable all counters */
-        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void armv7pmu_stop(void)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        /* Disable all counters */
-        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline int armv7_a8_pmu_event_map(int config)
-{
-        int mapping = armv7_a8_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static inline int armv7_a9_pmu_event_map(int config)
-{
-        int mapping = armv7_a9_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64 armv7pmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                                  struct hw_perf_event *event)
-{
-        int idx;
-
-        /* Always place a cycle counter into the cycle counter. */
-        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
-                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return ARMV7_CYCLE_COUNTER;
-        } else {
-                /*
-                 * For anything other than a cycle counter, try and use
-                 * the events counters
-                 */
-                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
-                        if (!test_and_set_bit(idx, cpuc->used_mask))
-                                return idx;
-                }
-
-                /* The counters are all in use. */
-                return -EAGAIN;
-        }
-}
-
-static struct arm_pmu armv7pmu = {
-        .handle_irq             = armv7pmu_handle_irq,
-        .enable                 = armv7pmu_enable_event,
-        .disable                = armv7pmu_disable_event,
-        .raw_event              = armv7pmu_raw_event,
-        .read_counter           = armv7pmu_read_counter,
-        .write_counter          = armv7pmu_write_counter,
-        .get_event_idx          = armv7pmu_get_event_idx,
-        .start                  = armv7pmu_start,
-        .stop                   = armv7pmu_stop,
-        .max_period             = (1LLU << 32) - 1,
-};
-
-static u32 __init armv7_reset_read_pmnc(void)
-{
-        u32 nb_cnt;
-
-        /* Initialize & Reset PMNC: C and P bits */
-        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
-
-        /* Read the nb of CNTx counters supported from PMNC */
-        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
-
-        /* Add the CPU cycles counter and return */
-        return nb_cnt + 1;
-}
-
-/*
- * ARMv5 [xscale] Performance counter handling code.
- *
- * Based on xscale OProfile code.
- *
- * There are two variants of the xscale PMU that we support:
- *      - xscale1pmu: 2 event counters and a cycle counter
- *      - xscale2pmu: 4 event counters and a cycle counter
- * The two variants share event definitions, but have different
- * PMU structures.
- */
-
-enum xscale_perf_types {
-        XSCALE_PERFCTR_ICACHE_MISS              = 0x00,
-        XSCALE_PERFCTR_ICACHE_NO_DELIVER        = 0x01,
-        XSCALE_PERFCTR_DATA_STALL               = 0x02,
-        XSCALE_PERFCTR_ITLB_MISS                = 0x03,
-        XSCALE_PERFCTR_DTLB_MISS                = 0x04,
-        XSCALE_PERFCTR_BRANCH                   = 0x05,
-        XSCALE_PERFCTR_BRANCH_MISS              = 0x06,
-        XSCALE_PERFCTR_INSTRUCTION              = 0x07,
-        XSCALE_PERFCTR_DCACHE_FULL_STALL        = 0x08,
-        XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
-        XSCALE_PERFCTR_DCACHE_ACCESS            = 0x0A,
-        XSCALE_PERFCTR_DCACHE_MISS              = 0x0B,
-        XSCALE_PERFCTR_DCACHE_WRITE_BACK        = 0x0C,
-        XSCALE_PERFCTR_PC_CHANGED               = 0x0D,
-        XSCALE_PERFCTR_BCU_REQUEST              = 0x10,
-        XSCALE_PERFCTR_BCU_FULL                 = 0x11,
-        XSCALE_PERFCTR_BCU_DRAIN                = 0x12,
-        XSCALE_PERFCTR_BCU_ECC_NO_ELOG          = 0x14,
-        XSCALE_PERFCTR_BCU_1_BIT_ERR            = 0x15,
-        XSCALE_PERFCTR_RMW                      = 0x16,
-        /* XSCALE_PERFCTR_CCNT is not hardware defined */
-        XSCALE_PERFCTR_CCNT                     = 0xFE,
-        XSCALE_PERFCTR_UNUSED                   = 0xFF,
-};
-
-enum xscale_counters {
-        XSCALE_CYCLE_COUNTER    = 1,
-        XSCALE_COUNTER0,
-        XSCALE_COUNTER1,
-        XSCALE_COUNTER2,
-        XSCALE_COUNTER3,
-};
-
-static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
-        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
-        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
-        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
-        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
-        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
-        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
-};
-
-static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
-                                           [PERF_COUNT_HW_CACHE_OP_MAX]
-                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
-        [C(L1D)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(L1I)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(LL)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(DTLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(ITLB)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-        [C(BPU)] = {
-                [C(OP_READ)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_WRITE)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-                [C(OP_PREFETCH)] = {
-                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
-                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
-                },
-        },
-};
-
-#define XSCALE_PMU_ENABLE       0x001
-#define XSCALE_PMN_RESET        0x002
-#define XSCALE_CCNT_RESET       0x004
-#define XSCALE_PMU_RESET        (CCNT_RESET | PMN_RESET)
-#define XSCALE_PMU_CNT64        0x008
-
-static inline int
-xscalepmu_event_map(int config)
-{
-        int mapping = xscale_perf_map[config];
-        if (HW_OP_UNSUPPORTED == mapping)
-                mapping = -EOPNOTSUPP;
-        return mapping;
-}
-
-static u64
-xscalepmu_raw_event(u64 config)
-{
-        return config & 0xff;
-}
-
-#define XSCALE1_OVERFLOWED_MASK 0x700
-#define XSCALE1_CCOUNT_OVERFLOW 0x400
-#define XSCALE1_COUNT0_OVERFLOW 0x100
-#define XSCALE1_COUNT1_OVERFLOW 0x200
-#define XSCALE1_CCOUNT_INT_EN   0x040
-#define XSCALE1_COUNT0_INT_EN   0x010
-#define XSCALE1_COUNT1_INT_EN   0x020
-#define XSCALE1_COUNT0_EVT_SHFT 12
-#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
-#define XSCALE1_COUNT1_EVT_SHFT 20
-#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
-
-static inline u32
-xscale1pmu_read_pmnc(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale1pmu_write_pmnc(u32 val)
-{
-        /* upper 4bits and 7, 11 are write-as-0 */
-        val &= 0xffff77f;
-        asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
-}
-
-static inline int
-xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
-                                        enum xscale_counters counter)
-{
-        int ret = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
-                break;
-        case XSCALE_COUNTER0:
-                ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
-                break;
-        case XSCALE_COUNTER1:
-                ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-        }
-
-        return ret;
-}
-
-static irqreturn_t
-xscale1pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /*
-         * NOTE: there's an A stepping erratum that states if an overflow
-         *       bit already exists and another occurs, the previous
-         *       Overflow bit gets cleared. There's no workaround.
-         *       Fixed in B stepping or later.
-         */
-        pmnc = xscale1pmu_read_pmnc();
-
-        /*
-         * Write the value back to clear the overflow flags. Overflow
-         * flags remain in pmnc for use below. We also disable the PMU
-         * while we process the interrupt.
-         */
-        xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
-
-        if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
-                return IRQ_NONE;
-
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        irq_work_run();
-
-        /*
-         * Re-enable the PMU.
-         */
-        pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(pmnc);
-
-        return IRQ_HANDLED;
-}
-
-static void
-xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                mask = 0;
-                evt = XSCALE1_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                mask = XSCALE1_COUNT0_EVT_MASK;
-                evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
-                        XSCALE1_COUNT0_INT_EN;
-                break;
-        case XSCALE_COUNTER1:
-                mask = XSCALE1_COUNT1_EVT_MASK;
-                evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
-                        XSCALE1_COUNT1_INT_EN;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~mask;
-        val |= evt;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long val, mask, evt, flags;
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                mask = XSCALE1_CCOUNT_INT_EN;
-                evt = 0;
-                break;
-        case XSCALE_COUNTER0:
-                mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
-                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
-                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~mask;
-        val |= evt;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static int
-xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                        struct hw_perf_event *event)
-{
-        if (XSCALE_PERFCTR_CCNT == event->config_base) {
-                if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
-                        return -EAGAIN;
-
-                return XSCALE_CYCLE_COUNTER;
-        } else {
-                if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
-                        return XSCALE_COUNTER1;
-                }
-
-                if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
-                        return XSCALE_COUNTER0;
-                }
-
-                return -EAGAIN;
-        }
-}
-
-static void
-xscale1pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val |= XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale1pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale1pmu_read_pmnc();
-        val &= ~XSCALE_PMU_ENABLE;
-        xscale1pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline u32
-xscale1pmu_read_counter(int counter)
-{
-        u32 val = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
-                break;
-        }
-
-        return val;
-}
-
-static inline void
-xscale1pmu_write_counter(int counter, u32 val)
-{
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
-                break;
-        }
-}
-
-static const struct arm_pmu xscale1pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE1,
-        .handle_irq     = xscale1pmu_handle_irq,
-        .enable         = xscale1pmu_enable_event,
-        .disable        = xscale1pmu_disable_event,
-        .event_map      = xscalepmu_event_map,
-        .raw_event      = xscalepmu_raw_event,
-        .read_counter   = xscale1pmu_read_counter,
-        .write_counter  = xscale1pmu_write_counter,
-        .get_event_idx  = xscale1pmu_get_event_idx,
-        .start          = xscale1pmu_start,
-        .stop           = xscale1pmu_stop,
-        .num_events     = 3,
-        .max_period     = (1LLU << 32) - 1,
-};
-
-#define XSCALE2_OVERFLOWED_MASK 0x01f
-#define XSCALE2_CCOUNT_OVERFLOW 0x001
-#define XSCALE2_COUNT0_OVERFLOW 0x002
-#define XSCALE2_COUNT1_OVERFLOW 0x004
-#define XSCALE2_COUNT2_OVERFLOW 0x008
-#define XSCALE2_COUNT3_OVERFLOW 0x010
-#define XSCALE2_CCOUNT_INT_EN   0x001
-#define XSCALE2_COUNT0_INT_EN   0x002
-#define XSCALE2_COUNT1_INT_EN   0x004
-#define XSCALE2_COUNT2_INT_EN   0x008
-#define XSCALE2_COUNT3_INT_EN   0x010
-#define XSCALE2_COUNT0_EVT_SHFT 0
-#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
-#define XSCALE2_COUNT1_EVT_SHFT 8
-#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
-#define XSCALE2_COUNT2_EVT_SHFT 16
-#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
-#define XSCALE2_COUNT3_EVT_SHFT 24
-#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
-
-static inline u32
-xscale2pmu_read_pmnc(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
-        /* bits 1-2 and 4-23 are read-unpredictable */
-        return val & 0xff000009;
-}
-
-static inline void
-xscale2pmu_write_pmnc(u32 val)
-{
-        /* bits 4-23 are write-as-0, 24-31 are write ignored */
-        val &= 0xf;
-        asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
-}
-
-static inline u32
-xscale2pmu_read_overflow_flags(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale2pmu_write_overflow_flags(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
-}
-
-static inline u32
-xscale2pmu_read_event_select(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
-        return val;
-}
-
-static inline void
-xscale2pmu_write_event_select(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
-}
-
-static inline u32
-xscale2pmu_read_int_enable(void)
-{
-        u32 val;
-        asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
-        return val;
-}
-
-static void
-xscale2pmu_write_int_enable(u32 val)
-{
-        asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
-}
-
-static inline int
-xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
-                                        enum xscale_counters counter)
-{
-        int ret = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
-                break;
-        case XSCALE_COUNTER0:
-                ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
-                break;
-        case XSCALE_COUNTER1:
-                ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
-                break;
-        case XSCALE_COUNTER2:
-                ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
-                break;
-        case XSCALE_COUNTER3:
-                ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
-        }
-
-        return ret;
-}
-
-static irqreturn_t
-xscale2pmu_handle_irq(int irq_num, void *dev)
-{
-        unsigned long pmnc, of_flags;
-        struct perf_sample_data data;
-        struct cpu_hw_events *cpuc;
-        struct pt_regs *regs;
-        int idx;
-
-        /* Disable the PMU. */
-        pmnc = xscale2pmu_read_pmnc();
-        xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
-
-        /* Check the overflow flag register. */
-        of_flags = xscale2pmu_read_overflow_flags();
-        if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
-                return IRQ_NONE;
-
-        /* Clear the overflow bits. */
-        xscale2pmu_write_overflow_flags(of_flags);
-
-        regs = get_irq_regs();
-
-        perf_sample_data_init(&data, 0);
-
-        cpuc = &__get_cpu_var(cpu_hw_events);
-        for (idx = 0; idx <= armpmu->num_events; ++idx) {
-                struct perf_event *event = cpuc->events[idx];
-                struct hw_perf_event *hwc;
-
-                if (!test_bit(idx, cpuc->active_mask))
-                        continue;
-
-                if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
-                        continue;
-
-                hwc = &event->hw;
-                armpmu_event_update(event, hwc, idx);
-                data.period = event->hw.last_period;
-                if (!armpmu_event_set_period(event, hwc, idx))
-                        continue;
-
-                if (perf_event_overflow(event, 0, &data, regs))
-                        armpmu->disable(hwc, idx);
-        }
-
-        irq_work_run();
-
-        /*
-         * Re-enable the PMU.
-         */
-        pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(pmnc);
-
-        return IRQ_HANDLED;
-}
-
-static void
-xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags, ien, evtsel;
-
-        ien = xscale2pmu_read_int_enable();
-        evtsel = xscale2pmu_read_event_select();
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                ien |= XSCALE2_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                ien |= XSCALE2_COUNT0_INT_EN;
-                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                ien |= XSCALE2_COUNT1_INT_EN;
-                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER2:
-                ien |= XSCALE2_COUNT2_INT_EN;
-                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER3:
-                ien |= XSCALE2_COUNT3_INT_EN;
-                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
-                evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        xscale2pmu_write_event_select(evtsel);
-        xscale2pmu_write_int_enable(ien);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
-{
-        unsigned long flags, ien, evtsel;
-
-        ien = xscale2pmu_read_int_enable();
-        evtsel = xscale2pmu_read_event_select();
-
-        switch (idx) {
-        case XSCALE_CYCLE_COUNTER:
-                ien &= ~XSCALE2_CCOUNT_INT_EN;
-                break;
-        case XSCALE_COUNTER0:
-                ien &= ~XSCALE2_COUNT0_INT_EN;
-                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER1:
-                ien &= ~XSCALE2_COUNT1_INT_EN;
-                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER2:
-                ien &= ~XSCALE2_COUNT2_INT_EN;
-                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
-                break;
-        case XSCALE_COUNTER3:
-                ien &= ~XSCALE2_COUNT3_INT_EN;
-                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
-                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
-                break;
-        default:
-                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
-                return;
-        }
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        xscale2pmu_write_event_select(evtsel);
-        xscale2pmu_write_int_enable(ien);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static int
-xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
-                        struct hw_perf_event *event)
-{
-        int idx = xscale1pmu_get_event_idx(cpuc, event);
-        if (idx >= 0)
-                goto out;
-
-        if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
-                idx = XSCALE_COUNTER3;
-        else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
-                idx = XSCALE_COUNTER2;
-out:
-        return idx;
-}
-
-static void
-xscale2pmu_start(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
-        val |= XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static void
-xscale2pmu_stop(void)
-{
-        unsigned long flags, val;
-
-        spin_lock_irqsave(&pmu_lock, flags);
-        val = xscale2pmu_read_pmnc();
-        val &= ~XSCALE_PMU_ENABLE;
-        xscale2pmu_write_pmnc(val);
-        spin_unlock_irqrestore(&pmu_lock, flags);
-}
-
-static inline u32
-xscale2pmu_read_counter(int counter)
-{
-        u32 val = 0;
-
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER2:
-                asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
-                break;
-        case XSCALE_COUNTER3:
-                asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
-                break;
-        }
-
-        return val;
-}
-
-static inline void
-xscale2pmu_write_counter(int counter, u32 val)
-{
-        switch (counter) {
-        case XSCALE_CYCLE_COUNTER:
-                asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER0:
-                asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER1:
-                asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER2:
-                asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
-                break;
-        case XSCALE_COUNTER3:
-                asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
-                break;
-        }
-}
-
-static const struct arm_pmu xscale2pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE2,
-        .handle_irq     = xscale2pmu_handle_irq,
-        .enable         = xscale2pmu_enable_event,
-        .disable        = xscale2pmu_disable_event,
-        .event_map      = xscalepmu_event_map,
-        .raw_event      = xscalepmu_raw_event,
-        .read_counter   = xscale2pmu_read_counter,
-        .write_counter  = xscale2pmu_write_counter,
-        .get_event_idx  = xscale2pmu_get_event_idx,
-        .start          = xscale2pmu_start,
-        .stop           = xscale2pmu_stop,
-        .num_events     = 5,
-        .max_period     = (1LLU << 32) - 1,
-};
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
 
 static int __init
 init_hw_perf_events(void)
@@ -2977,37 +622,16 @@ init_hw_perf_events(void)
                 case 0xB360:    /* ARM1136 */
                 case 0xB560:    /* ARM1156 */
                 case 0xB760:    /* ARM1176 */
-                        armpmu = &armv6pmu;
-                        memcpy(armpmu_perf_cache_map, armv6_perf_cache_map,
-                                        sizeof(armv6_perf_cache_map));
+                        armpmu = armv6pmu_init();
                         break;
                 case 0xB020:    /* ARM11mpcore */
-                        armpmu = &armv6mpcore_pmu;
-                        memcpy(armpmu_perf_cache_map,
-                               armv6mpcore_perf_cache_map,
-                               sizeof(armv6mpcore_perf_cache_map));
+                        armpmu = armv6mpcore_pmu_init();
                         break;
                 case 0xC080:    /* Cortex-A8 */
-                        armv7pmu.id = ARM_PERF_PMU_ID_CA8;
-                        memcpy(armpmu_perf_cache_map, armv7_a8_perf_cache_map,
-                                sizeof(armv7_a8_perf_cache_map));
-                        armv7pmu.event_map = armv7_a8_pmu_event_map;
-                        armpmu = &armv7pmu;
-
-                        /* Reset PMNC and read the nb of CNTx counters
-                            supported */
-                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        armpmu = armv7_a8_pmu_init();
                         break;
                 case 0xC090:    /* Cortex-A9 */
-                        armv7pmu.id = ARM_PERF_PMU_ID_CA9;
-                        memcpy(armpmu_perf_cache_map, armv7_a9_perf_cache_map,
-                                sizeof(armv7_a9_perf_cache_map));
-                        armv7pmu.event_map = armv7_a9_pmu_event_map;
-                        armpmu = &armv7pmu;
-
-                        /* Reset PMNC and read the nb of CNTx counters
-                            supported */
-                        armv7pmu.num_events = armv7_reset_read_pmnc();
+                        armpmu = armv7_a9_pmu_init();
                         break;
                 }
         /* Intel CPUs [xscale]. */
@@ -3015,21 +639,17 @@ init_hw_perf_events(void)
                 part_number = (cpuid >> 13) & 0x7;
                 switch (part_number) {
                 case 1:
-                        armpmu = &xscale1pmu;
-                        memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
-                                        sizeof(xscale_perf_cache_map));
+                        armpmu = xscale1pmu_init();
                         break;
                 case 2:
-                        armpmu = &xscale2pmu;
-                        memcpy(armpmu_perf_cache_map, xscale_perf_cache_map,
-                                        sizeof(xscale_perf_cache_map));
+                        armpmu = xscale2pmu_init();
                         break;
                 }
         }
 
         if (armpmu) {
                 pr_info("enabled with %s PMU driver, %d counters available\n",
-                                arm_pmu_names[armpmu->id], armpmu->num_events);
+                        armpmu->name, armpmu->num_events);
         } else {
                 pr_info("no hardware support available\n");
         }
@@ -3053,17 +673,17 @@ arch_initcall(init_hw_perf_events);
  * This code has been adapted from the ARM OProfile support.
  */
 struct frame_tail {
-        struct frame_tail   *fp;
-        unsigned long       sp;
-        unsigned long       lr;
+        struct frame_tail __user *fp;
+        unsigned long sp;
+        unsigned long lr;
 } __attribute__((packed));
 
 /*
  * Get the return address for a single stackframe and return a pointer to the
  * next frame tail.
  */
-static struct frame_tail *
-user_backtrace(struct frame_tail *tail,
+static struct frame_tail __user *
+user_backtrace(struct frame_tail __user *tail,
                struct perf_callchain_entry *entry)
 {
         struct frame_tail buftail;
@@ -3089,10 +709,10 @@ user_backtrace(struct frame_tail *tail,
 void
 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
 {
-        struct frame_tail *tail;
+        struct frame_tail __user *tail;
 
 
-        tail = (struct frame_tail *)regs->ARM_fp - 1;
+        tail = (struct frame_tail __user *)regs->ARM_fp - 1;
 
         while (tail && !((unsigned long)tail & 0x3))
                 tail = user_backtrace(tail, entry);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
new file mode 100644
index 000000000000..c058bfc8532b
--- /dev/null
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -0,0 +1,672 @@
+/*
+ * ARMv6 Performance counter handling code.
+ *
+ * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
+ *
+ * ARMv6 has 2 configurable performance counters and a single cycle counter.
+ * They all share a single reset bit but can be written to zero so we can use
+ * that for a reset.
+ *
+ * The counters can't be individually enabled or disabled so when we remove
+ * one event and replace it with another we could get spurious counts from the
+ * wrong event. However, we can take advantage of the fact that the
+ * performance counters can export events to the event bus, and the event bus
+ * itself can be monitored. This requires that we *don't* export the events to
+ * the event bus. The procedure for disabling a configurable counter is:
+ *      - change the counter to count the ETMEXTOUT[0] signal (0x20). This
+ *        effectively stops the counter from counting.
+ *      - disable the counter's interrupt generation (each counter has it's
+ *        own interrupt enable bit).
+ * Once stopped, the counter value can be written as 0 to reset.
+ *
+ * To enable a counter:
+ *      - enable the counter's interrupt generation.
+ *      - set the new event type.
+ *
+ * Note: the dedicated cycle counter only counts cycles and can't be
+ * enabled/disabled independently of the others. When we want to disable the
+ * cycle counter, we have to just disable the interrupt reporting and start
+ * ignoring that counter. When re-enabling, we have to reset the value and
+ * enable the interrupt.
+ */
+
+#ifdef CONFIG_CPU_V6
+enum armv6_perf_types {
+        ARMV6_PERFCTR_ICACHE_MISS           = 0x0,
+        ARMV6_PERFCTR_IBUF_STALL            = 0x1,
+        ARMV6_PERFCTR_DDEP_STALL            = 0x2,
+        ARMV6_PERFCTR_ITLB_MISS             = 0x3,
+        ARMV6_PERFCTR_DTLB_MISS             = 0x4,
+        ARMV6_PERFCTR_BR_EXEC               = 0x5,
+        ARMV6_PERFCTR_BR_MISPREDICT         = 0x6,
+        ARMV6_PERFCTR_INSTR_EXEC            = 0x7,
+        ARMV6_PERFCTR_DCACHE_HIT            = 0x9,
+        ARMV6_PERFCTR_DCACHE_ACCESS         = 0xA,
+        ARMV6_PERFCTR_DCACHE_MISS           = 0xB,
+        ARMV6_PERFCTR_DCACHE_WBACK          = 0xC,
+        ARMV6_PERFCTR_SW_PC_CHANGE          = 0xD,
+        ARMV6_PERFCTR_MAIN_TLB_MISS         = 0xF,
+        ARMV6_PERFCTR_EXPL_D_ACCESS         = 0x10,
+        ARMV6_PERFCTR_LSU_FULL_STALL        = 0x11,
+        ARMV6_PERFCTR_WBUF_DRAINED          = 0x12,
+        ARMV6_PERFCTR_CPU_CYCLES            = 0xFF,
+        ARMV6_PERFCTR_NOP                   = 0x20,
+};
+
+enum armv6_counters {
+        ARMV6_CYCLE_COUNTER = 1,
+        ARMV6_COUNTER0,
+        ARMV6_COUNTER1,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV6_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV6_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+enum armv6mpcore_perf_types {
+        ARMV6MPCORE_PERFCTR_ICACHE_MISS     = 0x0,
+        ARMV6MPCORE_PERFCTR_IBUF_STALL      = 0x1,
+        ARMV6MPCORE_PERFCTR_DDEP_STALL      = 0x2,
+        ARMV6MPCORE_PERFCTR_ITLB_MISS       = 0x3,
+        ARMV6MPCORE_PERFCTR_DTLB_MISS       = 0x4,
+        ARMV6MPCORE_PERFCTR_BR_EXEC         = 0x5,
+        ARMV6MPCORE_PERFCTR_BR_NOTPREDICT   = 0x6,
+        ARMV6MPCORE_PERFCTR_BR_MISPREDICT   = 0x7,
+        ARMV6MPCORE_PERFCTR_INSTR_EXEC      = 0x8,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
+        ARMV6MPCORE_PERFCTR_DCACHE_RDMISS   = 0xB,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
+        ARMV6MPCORE_PERFCTR_DCACHE_WRMISS   = 0xD,
+        ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
+        ARMV6MPCORE_PERFCTR_SW_PC_CHANGE    = 0xF,
+        ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS   = 0x10,
+        ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
+        ARMV6MPCORE_PERFCTR_LSU_FULL_STALL  = 0x12,
+        ARMV6MPCORE_PERFCTR_WBUF_DRAINED    = 0x13,
+        ARMV6MPCORE_PERFCTR_CPU_CYCLES      = 0xFF,
+};
+
+/*
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                        [PERF_COUNT_HW_CACHE_OP_MAX]
+                                        [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
+                        [C(RESULT_MISS)]    =
+                                ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * The ARM performance counters can count micro DTLB misses,
+                 * micro ITLB misses and main TLB misses. There isn't an event
+                 * for TLB misses, so use the micro misses here and if users
+                 * want the main TLB misses they can use a raw counter.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = ARMV6MPCORE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]  = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]    = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+static inline unsigned long
+armv6_pmcr_read(void)
+{
+        u32 val;
+        asm volatile("mrc   p15, 0, %0, c15, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void
+armv6_pmcr_write(unsigned long val)
+{
+        asm volatile("mcr   p15, 0, %0, c15, c12, 0" : : "r"(val));
+}
+
+#define ARMV6_PMCR_ENABLE               (1 << 0)
+#define ARMV6_PMCR_CTR01_RESET          (1 << 1)
+#define ARMV6_PMCR_CCOUNT_RESET         (1 << 2)
+#define ARMV6_PMCR_CCOUNT_DIV           (1 << 3)
+#define ARMV6_PMCR_COUNT0_IEN           (1 << 4)
+#define ARMV6_PMCR_COUNT1_IEN           (1 << 5)
+#define ARMV6_PMCR_CCOUNT_IEN           (1 << 6)
+#define ARMV6_PMCR_COUNT0_OVERFLOW      (1 << 8)
+#define ARMV6_PMCR_COUNT1_OVERFLOW      (1 << 9)
+#define ARMV6_PMCR_CCOUNT_OVERFLOW      (1 << 10)
+#define ARMV6_PMCR_EVT_COUNT0_SHIFT     20
+#define ARMV6_PMCR_EVT_COUNT0_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
+#define ARMV6_PMCR_EVT_COUNT1_SHIFT     12
+#define ARMV6_PMCR_EVT_COUNT1_MASK      (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
+
+#define ARMV6_PMCR_OVERFLOWED_MASK \
+        (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
+         ARMV6_PMCR_CCOUNT_OVERFLOW)
+
+static inline int
+armv6_pmcr_has_overflowed(unsigned long pmcr)
+{
+        return pmcr & ARMV6_PMCR_OVERFLOWED_MASK;
+}
+
+static inline int
+armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
+                                  enum armv6_counters counter)
+{
+        int ret = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
+        else if (ARMV6_COUNTER0 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
+        else if (ARMV6_COUNTER1 == counter)
+                ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return ret;
+}
+
+static inline u32
+armv6pmu_read_counter(int counter)
+{
+        unsigned long value = 0;
+
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 1" : "=r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 2" : "=r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mrc   p15, 0, %0, c15, c12, 3" : "=r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+
+        return value;
+}
+
+static inline void
+armv6pmu_write_counter(int counter,
+                       u32 value)
+{
+        if (ARMV6_CYCLE_COUNTER == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 1" : : "r"(value));
+        else if (ARMV6_COUNTER0 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 2" : : "r"(value));
+        else if (ARMV6_COUNTER1 == counter)
+                asm volatile("mcr   p15, 0, %0, c15, c12, 3" : : "r"(value));
+        else
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+}
+
+static void
+armv6pmu_enable_event(struct hw_perf_event *hwc,
+                      int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = 0;
+                evt     = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
+                          ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
+                          ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the event
+         * that we're interested in.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t
+armv6pmu_handle_irq(int irq_num,
+                    void *dev)
+{
+        unsigned long pmcr = armv6_pmcr_read();
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        if (!armv6_pmcr_has_overflowed(pmcr))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        /*
+         * The interrupts are cleared by writing the overflow flags back to
+         * the control register. All of the other bits don't have any effect
+         * if they are rewritten, so write the whole value back.
+         */
+        armv6_pmcr_write(pmcr);
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
+         * will not work.
+         */
+        irq_work_run();
+
+        return IRQ_HANDLED;
+}
+
+static void
+armv6pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val |= ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~ARMV6_PMCR_ENABLE;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                       struct hw_perf_event *event)
+{
+        /* Always place a cycle counter into the cycle counter. */
+        if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
+                if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV6_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * counter0 and counter1.
+                 */
+                if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask))
+                        return ARMV6_COUNTER1;
+
+                if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask))
+                        return ARMV6_COUNTER0;
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static void
+armv6pmu_disable_event(struct hw_perf_event *hwc,
+                       int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+                evt     = 0;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
+                evt     = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Mask out the current event and set the counter to count the number
+         * of ETM bus signal assertion cycles. The external reporting should
+         * be disabled and so this should never increment.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
+                              int idx)
+{
+        unsigned long val, mask, flags, evt = 0;
+
+        if (ARMV6_CYCLE_COUNTER == idx) {
+                mask    = ARMV6_PMCR_CCOUNT_IEN;
+        } else if (ARMV6_COUNTER0 == idx) {
+                mask    = ARMV6_PMCR_COUNT0_IEN;
+        } else if (ARMV6_COUNTER1 == idx) {
+                mask    = ARMV6_PMCR_COUNT1_IEN;
+        } else {
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        /*
+         * Unlike UP ARMv6, we don't have a way of stopping the counters. We
+         * simply disable the interrupt reporting.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = armv6_pmcr_read();
+        val &= ~mask;
+        val |= evt;
+        armv6_pmcr_write(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static const struct arm_pmu armv6pmu = {
+        .id                     = ARM_PERF_PMU_ID_V6,
+        .name                   = "v6",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6pmu_disable_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .cache_map              = &armv6_perf_cache_map,
+        .event_map              = &armv6_perf_map,
+        .raw_event_mask         = 0xFF,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init armv6pmu_init(void)
+{
+        return &armv6pmu;
+}
+
+/*
+ * ARMv6mpcore is almost identical to single core ARMv6 with the exception
+ * that some of the events have different enumerations and that there is no
+ * *hack* to stop the programmable counters. To stop the counters we simply
+ * disable the interrupt reporting and update the event. When unthrottling we
+ * reset the period and enable the interrupt reporting.
+ */
+static const struct arm_pmu armv6mpcore_pmu = {
+        .id                     = ARM_PERF_PMU_ID_V6MP,
+        .name                   = "v6mpcore",
+        .handle_irq             = armv6pmu_handle_irq,
+        .enable                 = armv6pmu_enable_event,
+        .disable                = armv6mpcore_pmu_disable_event,
+        .read_counter           = armv6pmu_read_counter,
+        .write_counter          = armv6pmu_write_counter,
+        .get_event_idx          = armv6pmu_get_event_idx,
+        .start                  = armv6pmu_start,
+        .stop                   = armv6pmu_stop,
+        .cache_map              = &armv6mpcore_perf_cache_map,
+        .event_map              = &armv6mpcore_perf_map,
+        .raw_event_mask         = 0xFF,
+        .num_events             = 3,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+{
+        return &armv6mpcore_pmu;
+}
+#else
+static const struct arm_pmu *__init armv6pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init armv6mpcore_pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_V6 */
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
new file mode 100644
index 000000000000..2e1402556fa0
--- /dev/null
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -0,0 +1,906 @@
+/*
+ * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
+ *
+ * ARMv7 support: Jean Pihet <jpihet@mvista.com>
+ * 2010 (c) MontaVista Software, LLC.
+ *
+ * Copied from ARMv6 code, with the low level code inspired
+ *  by the ARMv7 Oprofile code.
+ *
+ * Cortex-A8 has up to 4 configurable performance counters and
+ *  a single cycle counter.
+ * Cortex-A9 has up to 31 configurable performance counters and
+ *  a single cycle counter.
+ *
+ * All counters can be enabled/disabled and IRQ masked separately. The cycle
+ *  counter and all 4 performance counters together can be reset separately.
+ */
+
+#ifdef CONFIG_CPU_V7
+/* Common ARMv7 event types */
+enum armv7_perf_types {
+        ARMV7_PERFCTR_PMNC_SW_INCR              = 0x00,
+        ARMV7_PERFCTR_IFETCH_MISS               = 0x01,
+        ARMV7_PERFCTR_ITLB_MISS                 = 0x02,
+        ARMV7_PERFCTR_DCACHE_REFILL             = 0x03,
+        ARMV7_PERFCTR_DCACHE_ACCESS             = 0x04,
+        ARMV7_PERFCTR_DTLB_REFILL               = 0x05,
+        ARMV7_PERFCTR_DREAD                     = 0x06,
+        ARMV7_PERFCTR_DWRITE                    = 0x07,
+
+        ARMV7_PERFCTR_EXC_TAKEN                 = 0x09,
+        ARMV7_PERFCTR_EXC_EXECUTED              = 0x0A,
+        ARMV7_PERFCTR_CID_WRITE                 = 0x0B,
+        /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
+         * It counts:
+         *  - all branch instructions,
+         *  - instructions that explicitly write the PC,
+         *  - exception generating instructions.
+         */
+        ARMV7_PERFCTR_PC_WRITE                  = 0x0C,
+        ARMV7_PERFCTR_PC_IMM_BRANCH             = 0x0D,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS          = 0x0F,
+        ARMV7_PERFCTR_PC_BRANCH_MIS_PRED        = 0x10,
+        ARMV7_PERFCTR_CLOCK_CYCLES              = 0x11,
+
+        ARMV7_PERFCTR_PC_BRANCH_MIS_USED        = 0x12,
+
+        ARMV7_PERFCTR_CPU_CYCLES                = 0xFF
+};
+
+/* ARMv7 Cortex-A8 specific event types */
+enum armv7_a8_perf_types {
+        ARMV7_PERFCTR_INSTR_EXECUTED            = 0x08,
+
+        ARMV7_PERFCTR_PC_PROC_RETURN            = 0x0E,
+
+        ARMV7_PERFCTR_WRITE_BUFFER_FULL         = 0x40,
+        ARMV7_PERFCTR_L2_STORE_MERGED           = 0x41,
+        ARMV7_PERFCTR_L2_STORE_BUFF             = 0x42,
+        ARMV7_PERFCTR_L2_ACCESS                 = 0x43,
+        ARMV7_PERFCTR_L2_CACH_MISS              = 0x44,
+        ARMV7_PERFCTR_AXI_READ_CYCLES           = 0x45,
+        ARMV7_PERFCTR_AXI_WRITE_CYCLES          = 0x46,
+        ARMV7_PERFCTR_MEMORY_REPLAY             = 0x47,
+        ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY   = 0x48,
+        ARMV7_PERFCTR_L1_DATA_MISS              = 0x49,
+        ARMV7_PERFCTR_L1_INST_MISS              = 0x4A,
+        ARMV7_PERFCTR_L1_DATA_COLORING          = 0x4B,
+        ARMV7_PERFCTR_L1_NEON_DATA              = 0x4C,
+        ARMV7_PERFCTR_L1_NEON_CACH_DATA         = 0x4D,
+        ARMV7_PERFCTR_L2_NEON                   = 0x4E,
+        ARMV7_PERFCTR_L2_NEON_HIT               = 0x4F,
+        ARMV7_PERFCTR_L1_INST                   = 0x50,
+        ARMV7_PERFCTR_PC_RETURN_MIS_PRED        = 0x51,
+        ARMV7_PERFCTR_PC_BRANCH_FAILED          = 0x52,
+        ARMV7_PERFCTR_PC_BRANCH_TAKEN           = 0x53,
+        ARMV7_PERFCTR_PC_BRANCH_EXECUTED        = 0x54,
+        ARMV7_PERFCTR_OP_EXECUTED               = 0x55,
+        ARMV7_PERFCTR_CYCLES_INST_STALL         = 0x56,
+        ARMV7_PERFCTR_CYCLES_INST               = 0x57,
+        ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL    = 0x58,
+        ARMV7_PERFCTR_CYCLES_NEON_INST_STALL    = 0x59,
+        ARMV7_PERFCTR_NEON_CYCLES               = 0x5A,
+
+        ARMV7_PERFCTR_PMU0_EVENTS               = 0x70,
+        ARMV7_PERFCTR_PMU1_EVENTS               = 0x71,
+        ARMV7_PERFCTR_PMU_EVENTS                = 0x72,
+};
+
+/* ARMv7 Cortex-A9 specific event types */
+enum armv7_a9_perf_types {
+        ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC     = 0x40,
+        ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC     = 0x41,
+        ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC       = 0x42,
+
+        ARMV7_PERFCTR_COHERENT_LINE_MISS        = 0x50,
+        ARMV7_PERFCTR_COHERENT_LINE_HIT         = 0x51,
+
+        ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES   = 0x60,
+        ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES   = 0x61,
+        ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
+        ARMV7_PERFCTR_STREX_EXECUTED_PASSED     = 0x63,
+        ARMV7_PERFCTR_STREX_EXECUTED_FAILED     = 0x64,
+        ARMV7_PERFCTR_DATA_EVICTION             = 0x65,
+        ARMV7_PERFCTR_ISSUE_STAGE_NO_INST       = 0x66,
+        ARMV7_PERFCTR_ISSUE_STAGE_EMPTY         = 0x67,
+        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE  = 0x68,
+
+        ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
+
+        ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST   = 0x70,
+        ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
+        ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST  = 0x72,
+        ARMV7_PERFCTR_FP_EXECUTED_INST          = 0x73,
+        ARMV7_PERFCTR_NEON_EXECUTED_INST        = 0x74,
+
+        ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
+        ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES  = 0x81,
+        ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES        = 0x82,
+        ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES        = 0x83,
+        ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES  = 0x84,
+        ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES  = 0x85,
+        ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES      = 0x86,
+
+        ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES  = 0x8A,
+        ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
+
+        ARMV7_PERFCTR_ISB_INST                  = 0x90,
+        ARMV7_PERFCTR_DSB_INST                  = 0x91,
+        ARMV7_PERFCTR_DMB_INST                  = 0x92,
+        ARMV7_PERFCTR_EXT_INTERRUPTS            = 0x93,
+
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED     = 0xA0,
+        ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED       = 0xA1,
+        ARMV7_PERFCTR_PLE_FIFO_FLUSH            = 0xA2,
+        ARMV7_PERFCTR_PLE_RQST_COMPLETED        = 0xA3,
+        ARMV7_PERFCTR_PLE_FIFO_OVERFLOW         = 0xA4,
+        ARMV7_PERFCTR_PLE_RQST_PROG             = 0xA5
+};
+
+/*
+ * Cortex-A8 HW events mapping
+ *
+ * The hardware events that we support. We do support cache operations but
+ * we have harvard caches and no way to combine instruction and data
+ * accesses/misses in hardware.
+ */
+static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = ARMV7_PERFCTR_INSTR_EXECUTED,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L1_INST,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L1_INST_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_L2_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_L2_CACH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Cortex-A9 HW events mapping
+ */
+static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = ARMV7_PERFCTR_CPU_CYCLES,
+        [PERF_COUNT_HW_INSTRUCTIONS]        =
+                                        ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = ARMV7_PERFCTR_COHERENT_LINE_HIT,
+        [PERF_COUNT_HW_CACHE_MISSES]        = ARMV7_PERFCTR_COHERENT_LINE_MISS,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+        [PERF_COUNT_HW_BUS_CYCLES]          = ARMV7_PERFCTR_CLOCK_CYCLES,
+};
+
+static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                          [PERF_COUNT_HW_CACHE_OP_MAX]
+                                          [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                /*
+                 * The performance counters don't differentiate between read
+                 * and write accesses/misses so this isn't strictly correct,
+                 * but it's the best we can do. Writes and reads get
+                 * combined.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DCACHE_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_IFETCH_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                /*
+                 * Only ITLB misses and DTLB refills are supported.
+                 * If users want the DTLB refills misses a raw counter
+                 * must be used.
+                 */
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_DTLB_REFILL,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = ARMV7_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = ARMV7_PERFCTR_PC_WRITE,
+                        [C(RESULT_MISS)]
+                                        = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+/*
+ * Perf Events counters
+ */
+enum armv7_counters {
+        ARMV7_CYCLE_COUNTER             = 1,    /* Cycle counter */
+        ARMV7_COUNTER0                  = 2,    /* First event counter */
+};
+
+/*
+ * The cycle counter is ARMV7_CYCLE_COUNTER.
+ * The first event counter is ARMV7_COUNTER0.
+ * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
+ */
+#define ARMV7_COUNTER_LAST      (ARMV7_COUNTER0 + armpmu->num_events - 1)
+
+/*
+ * ARMv7 low level PMNC access
+ */
+
+/*
+ * Per-CPU PMNC: config reg
+ */
+#define ARMV7_PMNC_E            (1 << 0) /* Enable all counters */
+#define ARMV7_PMNC_P            (1 << 1) /* Reset all counters */
+#define ARMV7_PMNC_C            (1 << 2) /* Cycle counter reset */
+#define ARMV7_PMNC_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV7_PMNC_X            (1 << 4) /* Export to ETM */
+#define ARMV7_PMNC_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
+#define ARMV7_PMNC_N_SHIFT      11       /* Number of counters supported */
+#define ARMV7_PMNC_N_MASK       0x1f
+#define ARMV7_PMNC_MASK         0x3f     /* Mask for writable bits */
+
+/*
+ * Available counters
+ */
+#define ARMV7_CNT0              0       /* First event counter */
+#define ARMV7_CCNT              31      /* Cycle counter */
+
+/* Perf Event to low level counters mapping */
+#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
+
+/*
+ * CNTENS: counters enable reg
+ */
+#define ARMV7_CNTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * CNTENC: counters disable reg
+ */
+#define ARMV7_CNTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_CNTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENS: counters overflow interrupt enable reg
+ */
+#define ARMV7_INTENS_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENS_C          (1 << ARMV7_CCNT)
+
+/*
+ * INTENC: counters overflow interrupt disable reg
+ */
+#define ARMV7_INTENC_P(idx)     (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_INTENC_C          (1 << ARMV7_CCNT)
+
+/*
+ * EVTSEL: Event selection reg
+ */
+#define ARMV7_EVTSEL_MASK       0xff            /* Mask for writable bits */
+
+/*
+ * SELECT: Counter selection reg
+ */
+#define ARMV7_SELECT_MASK       0x1f            /* Mask for writable bits */
+
+/*
+ * FLAG: counters overflow flag status reg
+ */
+#define ARMV7_FLAG_P(idx)       (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
+#define ARMV7_FLAG_C            (1 << ARMV7_CCNT)
+#define ARMV7_FLAG_MASK         0xffffffff      /* Mask for writable bits */
+#define ARMV7_OVERFLOWED_MASK   ARMV7_FLAG_MASK
+
+static inline unsigned long armv7_pmnc_read(void)
+{
+        u32 val;
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
+        return val;
+}
+
+static inline void armv7_pmnc_write(unsigned long val)
+{
+        val &= ARMV7_PMNC_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
+}
+
+static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
+{
+        return pmnc & ARMV7_OVERFLOWED_MASK;
+}
+
+static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum armv7_counters counter)
+{
+        int ret = 0;
+
+        if (counter == ARMV7_CYCLE_COUNTER)
+                ret = pmnc & ARMV7_FLAG_C;
+        else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
+                ret = pmnc & ARMV7_FLAG_P(counter);
+        else
+                pr_err("CPU%u checking wrong counter %d overflow status\n",
+                        smp_processor_id(), counter);
+
+        return ret;
+}
+
+static inline int armv7_pmnc_select_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
+                pr_err("CPU%u selecting wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7pmu_read_counter(int idx)
+{
+        unsigned long value = 0;
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mrc p15, 0, %0, c9, c13, 2"
+                                     : "=r" (value));
+        } else
+                pr_err("CPU%u reading wrong counter %d\n",
+                        smp_processor_id(), idx);
+
+        return value;
+}
+
+static inline void armv7pmu_write_counter(int idx, u32 value)
+{
+        if (idx == ARMV7_CYCLE_COUNTER)
+                asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
+        else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
+                if (armv7_pmnc_select_counter(idx) == idx)
+                        asm volatile("mcr p15, 0, %0, c9, c13, 2"
+                                     : : "r" (value));
+        } else
+                pr_err("CPU%u writing wrong counter %d\n",
+                        smp_processor_id(), idx);
+}
+
+static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
+{
+        if (armv7_pmnc_select_counter(idx) == idx) {
+                val &= ARMV7_EVTSEL_MASK;
+                asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
+        }
+}
+
+static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENS_C;
+        else
+                val = ARMV7_CNTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
+{
+        u32 val;
+
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_CNTENC_C;
+        else
+                val = ARMV7_CNTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u enabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENS_C;
+        else
+                val = ARMV7_INTENS_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
+{
+        u32 val;
+
+        if ((idx != ARMV7_CYCLE_COUNTER) &&
+            ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
+                pr_err("CPU%u disabling wrong PMNC counter"
+                        " interrupt enable %d\n", smp_processor_id(), idx);
+                return -1;
+        }
+
+        if (idx == ARMV7_CYCLE_COUNTER)
+                val = ARMV7_INTENC_C;
+        else
+                val = ARMV7_INTENC_P(idx);
+
+        asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
+
+        return idx;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+        u32 val;
+
+        /* Read */
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+        /* Write to clear flags */
+        val &= ARMV7_FLAG_MASK;
+        asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+        return val;
+}
+
+#ifdef DEBUG
+static void armv7_pmnc_dump_regs(void)
+{
+        u32 val;
+        unsigned int cnt;
+
+        printk(KERN_INFO "PMNC registers dump:\n");
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+        printk(KERN_INFO "PMNC  =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
+        printk(KERN_INFO "CNTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
+        printk(KERN_INFO "INTENS=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+        printk(KERN_INFO "FLAGS =0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
+        printk(KERN_INFO "SELECT=0x%08x\n", val);
+
+        asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+        printk(KERN_INFO "CCNT  =0x%08x\n", val);
+
+        for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
+                armv7_pmnc_select_counter(cnt);
+                asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] count =0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+                asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
+                printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
+                        cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
+        }
+}
+#endif
+
+static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Enable counter and interrupt, and set the counter to count
+         * the event that we're interested in.
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Set event (if destined for PMNx counters)
+         * We don't need to set the event if it's a cycle count
+         */
+        if (idx != ARMV7_CYCLE_COUNTER)
+                armv7_pmnc_write_evtsel(idx, hwc->config_base);
+
+        /*
+         * Enable interrupt for this counter
+         */
+        armv7_pmnc_enable_intens(idx);
+
+        /*
+         * Enable counter
+         */
+        armv7_pmnc_enable_counter(idx);
+
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags;
+
+        /*
+         * Disable counter and interrupt
+         */
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+
+        /*
+         * Disable counter
+         */
+        armv7_pmnc_disable_counter(idx);
+
+        /*
+         * Disable interrupt for this counter
+         */
+        armv7_pmnc_disable_intens(idx);
+
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * Get and reset the IRQ flags
+         */
+        pmnc = armv7_pmnc_getreset_flags();
+
+        /*
+         * Did an overflow occur?
+         */
+        if (!armv7_pmnc_has_overflowed(pmnc))
+                return IRQ_NONE;
+
+        /*
+         * Handle the counter(s) overflow(s)
+         */
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                /*
+                 * We have a single interrupt for all counters. Check that
+                 * each counter has overflowed before we process it.
+                 */
+                if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        /*
+         * Handle the pending perf events.
+         *
+         * Note: this call *must* be run with interrupts disabled. For
+         * platforms that can have the PMU interrupts raised as an NMI, this
+         * will not work.
+         */
+        irq_work_run();
+
+        return IRQ_HANDLED;
+}
+
+static void armv7pmu_start(void)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        /* Enable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void armv7pmu_stop(void)
+{
+        unsigned long flags;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        /* Disable all counters */
+        armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                                  struct hw_perf_event *event)
+{
+        int idx;
+
+        /* Always place a cycle counter into the cycle counter. */
+        if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
+                if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return ARMV7_CYCLE_COUNTER;
+        } else {
+                /*
+                 * For anything other than a cycle counter, try and use
+                 * the events counters
+                 */
+                for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
+                        if (!test_and_set_bit(idx, cpuc->used_mask))
+                                return idx;
+                }
+
+                /* The counters are all in use. */
+                return -EAGAIN;
+        }
+}
+
+static struct arm_pmu armv7pmu = {
+        .handle_irq             = armv7pmu_handle_irq,
+        .enable                 = armv7pmu_enable_event,
+        .disable                = armv7pmu_disable_event,
+        .read_counter           = armv7pmu_read_counter,
+        .write_counter          = armv7pmu_write_counter,
+        .get_event_idx          = armv7pmu_get_event_idx,
+        .start                  = armv7pmu_start,
+        .stop                   = armv7pmu_stop,
+        .raw_event_mask         = 0xFF,
+        .max_period             = (1LLU << 32) - 1,
+};
+
+static u32 __init armv7_reset_read_pmnc(void)
+{
+        u32 nb_cnt;
+
+        /* Initialize & Reset PMNC: C and P bits */
+        armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
+
+        /* Read the nb of CNTx counters supported from PMNC */
+        nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
+
+        /* Add the CPU cycles counter and return */
+        return nb_cnt + 1;
+}
+
+static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+{
+        armv7pmu.id             = ARM_PERF_PMU_ID_CA8;
+        armv7pmu.name           = "ARMv7 Cortex-A8";
+        armv7pmu.cache_map      = &armv7_a8_perf_cache_map;
+        armv7pmu.event_map      = &armv7_a8_perf_map;
+        armv7pmu.num_events     = armv7_reset_read_pmnc();
+        return &armv7pmu;
+}
+
+static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+{
+        armv7pmu.id             = ARM_PERF_PMU_ID_CA9;
+        armv7pmu.name           = "ARMv7 Cortex-A9";
+        armv7pmu.cache_map      = &armv7_a9_perf_cache_map;
+        armv7pmu.event_map      = &armv7_a9_perf_map;
+        armv7pmu.num_events     = armv7_reset_read_pmnc();
+        return &armv7pmu;
+}
+#else
+static const struct arm_pmu *__init armv7_a8_pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init armv7_a9_pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_V7 */
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
new file mode 100644
index 000000000000..28cd3b025bc3
--- /dev/null
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -0,0 +1,807 @@
+/*
+ * ARMv5 [xscale] Performance counter handling code.
+ *
+ * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com>
+ *
+ * Based on the previous xscale OProfile code.
+ *
+ * There are two variants of the xscale PMU that we support:
+ *      - xscale1pmu: 2 event counters and a cycle counter
+ *      - xscale2pmu: 4 event counters and a cycle counter
+ * The two variants share event definitions, but have different
+ * PMU structures.
+ */
+
+#ifdef CONFIG_CPU_XSCALE
+enum xscale_perf_types {
+        XSCALE_PERFCTR_ICACHE_MISS              = 0x00,
+        XSCALE_PERFCTR_ICACHE_NO_DELIVER        = 0x01,
+        XSCALE_PERFCTR_DATA_STALL               = 0x02,
+        XSCALE_PERFCTR_ITLB_MISS                = 0x03,
+        XSCALE_PERFCTR_DTLB_MISS                = 0x04,
+        XSCALE_PERFCTR_BRANCH                   = 0x05,
+        XSCALE_PERFCTR_BRANCH_MISS              = 0x06,
+        XSCALE_PERFCTR_INSTRUCTION              = 0x07,
+        XSCALE_PERFCTR_DCACHE_FULL_STALL        = 0x08,
+        XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
+        XSCALE_PERFCTR_DCACHE_ACCESS            = 0x0A,
+        XSCALE_PERFCTR_DCACHE_MISS              = 0x0B,
+        XSCALE_PERFCTR_DCACHE_WRITE_BACK        = 0x0C,
+        XSCALE_PERFCTR_PC_CHANGED               = 0x0D,
+        XSCALE_PERFCTR_BCU_REQUEST              = 0x10,
+        XSCALE_PERFCTR_BCU_FULL                 = 0x11,
+        XSCALE_PERFCTR_BCU_DRAIN                = 0x12,
+        XSCALE_PERFCTR_BCU_ECC_NO_ELOG          = 0x14,
+        XSCALE_PERFCTR_BCU_1_BIT_ERR            = 0x15,
+        XSCALE_PERFCTR_RMW                      = 0x16,
+        /* XSCALE_PERFCTR_CCNT is not hardware defined */
+        XSCALE_PERFCTR_CCNT                     = 0xFE,
+        XSCALE_PERFCTR_UNUSED                   = 0xFF,
+};
+
+enum xscale_counters {
+        XSCALE_CYCLE_COUNTER    = 1,
+        XSCALE_COUNTER0,
+        XSCALE_COUNTER1,
+        XSCALE_COUNTER2,
+        XSCALE_COUNTER3,
+};
+
+static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
+        [PERF_COUNT_HW_CPU_CYCLES]          = XSCALE_PERFCTR_CCNT,
+        [PERF_COUNT_HW_INSTRUCTIONS]        = XSCALE_PERFCTR_INSTRUCTION,
+        [PERF_COUNT_HW_CACHE_REFERENCES]    = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_CACHE_MISSES]        = HW_OP_UNSUPPORTED,
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
+        [PERF_COUNT_HW_BRANCH_MISSES]       = XSCALE_PERFCTR_BRANCH_MISS,
+        [PERF_COUNT_HW_BUS_CYCLES]          = HW_OP_UNSUPPORTED,
+};
+
+static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+                                           [PERF_COUNT_HW_CACHE_OP_MAX]
+                                           [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+        [C(L1D)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = XSCALE_PERFCTR_DCACHE_ACCESS,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DCACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(L1I)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ICACHE_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(LL)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(DTLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_DTLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(ITLB)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = XSCALE_PERFCTR_ITLB_MISS,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+        [C(BPU)] = {
+                [C(OP_READ)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_WRITE)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+                [C(OP_PREFETCH)] = {
+                        [C(RESULT_ACCESS)]      = CACHE_OP_UNSUPPORTED,
+                        [C(RESULT_MISS)]        = CACHE_OP_UNSUPPORTED,
+                },
+        },
+};
+
+#define XSCALE_PMU_ENABLE       0x001
+#define XSCALE_PMN_RESET        0x002
+#define XSCALE_CCNT_RESET       0x004
+#define XSCALE_PMU_RESET        (CCNT_RESET | PMN_RESET)
+#define XSCALE_PMU_CNT64        0x008
+
+#define XSCALE1_OVERFLOWED_MASK 0x700
+#define XSCALE1_CCOUNT_OVERFLOW 0x400
+#define XSCALE1_COUNT0_OVERFLOW 0x100
+#define XSCALE1_COUNT1_OVERFLOW 0x200
+#define XSCALE1_CCOUNT_INT_EN   0x040
+#define XSCALE1_COUNT0_INT_EN   0x010
+#define XSCALE1_COUNT1_INT_EN   0x020
+#define XSCALE1_COUNT0_EVT_SHFT 12
+#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
+#define XSCALE1_COUNT1_EVT_SHFT 20
+#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
+
+static inline u32
+xscale1pmu_read_pmnc(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale1pmu_write_pmnc(u32 val)
+{
+        /* upper 4bits and 7, 11 are write-as-0 */
+        val &= 0xffff77f;
+        asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
+}
+
+static inline int
+xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
+                                        enum xscale_counters counter)
+{
+        int ret = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
+                break;
+        case XSCALE_COUNTER0:
+                ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
+                break;
+        case XSCALE_COUNTER1:
+                ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+        }
+
+        return ret;
+}
+
+static irqreturn_t
+xscale1pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /*
+         * NOTE: there's an A stepping erratum that states if an overflow
+         *       bit already exists and another occurs, the previous
+         *       Overflow bit gets cleared. There's no workaround.
+         *       Fixed in B stepping or later.
+         */
+        pmnc = xscale1pmu_read_pmnc();
+
+        /*
+         * Write the value back to clear the overflow flags. Overflow
+         * flags remain in pmnc for use below. We also disable the PMU
+         * while we process the interrupt.
+         */
+        xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
+
+        if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
+                return IRQ_NONE;
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        irq_work_run();
+
+        /*
+         * Re-enable the PMU.
+         */
+        pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(pmnc);
+
+        return IRQ_HANDLED;
+}
+
+static void
+xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                mask = 0;
+                evt = XSCALE1_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                mask = XSCALE1_COUNT0_EVT_MASK;
+                evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
+                        XSCALE1_COUNT0_INT_EN;
+                break;
+        case XSCALE_COUNTER1:
+                mask = XSCALE1_COUNT1_EVT_MASK;
+                evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
+                        XSCALE1_COUNT1_INT_EN;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~mask;
+        val |= evt;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long val, mask, evt, flags;
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                mask = XSCALE1_CCOUNT_INT_EN;
+                evt = 0;
+                break;
+        case XSCALE_COUNTER0:
+                mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
+                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
+                evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~mask;
+        val |= evt;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *event)
+{
+        if (XSCALE_PERFCTR_CCNT == event->config_base) {
+                if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
+                        return -EAGAIN;
+
+                return XSCALE_CYCLE_COUNTER;
+        } else {
+                if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask))
+                        return XSCALE_COUNTER1;
+
+                if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask))
+                        return XSCALE_COUNTER0;
+
+                return -EAGAIN;
+        }
+}
+
+static void
+xscale1pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val |= XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale1pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale1pmu_read_pmnc();
+        val &= ~XSCALE_PMU_ENABLE;
+        xscale1pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline u32
+xscale1pmu_read_counter(int counter)
+{
+        u32 val = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
+                break;
+        }
+
+        return val;
+}
+
+static inline void
+xscale1pmu_write_counter(int counter, u32 val)
+{
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
+                break;
+        }
+}
+
+static const struct arm_pmu xscale1pmu = {
+        .id             = ARM_PERF_PMU_ID_XSCALE1,
+        .name           = "xscale1",
+        .handle_irq     = xscale1pmu_handle_irq,
+        .enable         = xscale1pmu_enable_event,
+        .disable        = xscale1pmu_disable_event,
+        .read_counter   = xscale1pmu_read_counter,
+        .write_counter  = xscale1pmu_write_counter,
+        .get_event_idx  = xscale1pmu_get_event_idx,
+        .start          = xscale1pmu_start,
+        .stop           = xscale1pmu_stop,
+        .cache_map      = &xscale_perf_cache_map,
+        .event_map      = &xscale_perf_map,
+        .raw_event_mask = 0xFF,
+        .num_events     = 3,
+        .max_period     = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init xscale1pmu_init(void)
+{
+        return &xscale1pmu;
+}
+
+#define XSCALE2_OVERFLOWED_MASK 0x01f
+#define XSCALE2_CCOUNT_OVERFLOW 0x001
+#define XSCALE2_COUNT0_OVERFLOW 0x002
+#define XSCALE2_COUNT1_OVERFLOW 0x004
+#define XSCALE2_COUNT2_OVERFLOW 0x008
+#define XSCALE2_COUNT3_OVERFLOW 0x010
+#define XSCALE2_CCOUNT_INT_EN   0x001
+#define XSCALE2_COUNT0_INT_EN   0x002
+#define XSCALE2_COUNT1_INT_EN   0x004
+#define XSCALE2_COUNT2_INT_EN   0x008
+#define XSCALE2_COUNT3_INT_EN   0x010
+#define XSCALE2_COUNT0_EVT_SHFT 0
+#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
+#define XSCALE2_COUNT1_EVT_SHFT 8
+#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
+#define XSCALE2_COUNT2_EVT_SHFT 16
+#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
+#define XSCALE2_COUNT3_EVT_SHFT 24
+#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
+
+static inline u32
+xscale2pmu_read_pmnc(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
+        /* bits 1-2 and 4-23 are read-unpredictable */
+        return val & 0xff000009;
+}
+
+static inline void
+xscale2pmu_write_pmnc(u32 val)
+{
+        /* bits 4-23 are write-as-0, 24-31 are write ignored */
+        val &= 0xf;
+        asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
+}
+
+static inline u32
+xscale2pmu_read_overflow_flags(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale2pmu_write_overflow_flags(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
+}
+
+static inline u32
+xscale2pmu_read_event_select(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
+        return val;
+}
+
+static inline void
+xscale2pmu_write_event_select(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
+}
+
+static inline u32
+xscale2pmu_read_int_enable(void)
+{
+        u32 val;
+        asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
+        return val;
+}
+
+static void
+xscale2pmu_write_int_enable(u32 val)
+{
+        asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
+}
+
+static inline int
+xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
+                                        enum xscale_counters counter)
+{
+        int ret = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
+                break;
+        case XSCALE_COUNTER0:
+                ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
+                break;
+        case XSCALE_COUNTER1:
+                ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
+                break;
+        case XSCALE_COUNTER2:
+                ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
+                break;
+        case XSCALE_COUNTER3:
+                ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", counter);
+        }
+
+        return ret;
+}
+
+static irqreturn_t
+xscale2pmu_handle_irq(int irq_num, void *dev)
+{
+        unsigned long pmnc, of_flags;
+        struct perf_sample_data data;
+        struct cpu_hw_events *cpuc;
+        struct pt_regs *regs;
+        int idx;
+
+        /* Disable the PMU. */
+        pmnc = xscale2pmu_read_pmnc();
+        xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
+
+        /* Check the overflow flag register. */
+        of_flags = xscale2pmu_read_overflow_flags();
+        if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
+                return IRQ_NONE;
+
+        /* Clear the overflow bits. */
+        xscale2pmu_write_overflow_flags(of_flags);
+
+        regs = get_irq_regs();
+
+        perf_sample_data_init(&data, 0);
+
+        cpuc = &__get_cpu_var(cpu_hw_events);
+        for (idx = 0; idx <= armpmu->num_events; ++idx) {
+                struct perf_event *event = cpuc->events[idx];
+                struct hw_perf_event *hwc;
+
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+
+                if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
+                        continue;
+
+                hwc = &event->hw;
+                armpmu_event_update(event, hwc, idx);
+                data.period = event->hw.last_period;
+                if (!armpmu_event_set_period(event, hwc, idx))
+                        continue;
+
+                if (perf_event_overflow(event, 0, &data, regs))
+                        armpmu->disable(hwc, idx);
+        }
+
+        irq_work_run();
+
+        /*
+         * Re-enable the PMU.
+         */
+        pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(pmnc);
+
+        return IRQ_HANDLED;
+}
+
+static void
+xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags, ien, evtsel;
+
+        ien = xscale2pmu_read_int_enable();
+        evtsel = xscale2pmu_read_event_select();
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                ien |= XSCALE2_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                ien |= XSCALE2_COUNT0_INT_EN;
+                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                ien |= XSCALE2_COUNT1_INT_EN;
+                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER2:
+                ien |= XSCALE2_COUNT2_INT_EN;
+                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER3:
+                ien |= XSCALE2_COUNT3_INT_EN;
+                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
+                evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        xscale2pmu_write_event_select(evtsel);
+        xscale2pmu_write_int_enable(ien);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
+{
+        unsigned long flags, ien, evtsel;
+
+        ien = xscale2pmu_read_int_enable();
+        evtsel = xscale2pmu_read_event_select();
+
+        switch (idx) {
+        case XSCALE_CYCLE_COUNTER:
+                ien &= ~XSCALE2_CCOUNT_INT_EN;
+                break;
+        case XSCALE_COUNTER0:
+                ien &= ~XSCALE2_COUNT0_INT_EN;
+                evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER1:
+                ien &= ~XSCALE2_COUNT1_INT_EN;
+                evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER2:
+                ien &= ~XSCALE2_COUNT2_INT_EN;
+                evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
+                break;
+        case XSCALE_COUNTER3:
+                ien &= ~XSCALE2_COUNT3_INT_EN;
+                evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
+                evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
+                break;
+        default:
+                WARN_ONCE(1, "invalid counter number (%d)\n", idx);
+                return;
+        }
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        xscale2pmu_write_event_select(evtsel);
+        xscale2pmu_write_int_enable(ien);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static int
+xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
+                        struct hw_perf_event *event)
+{
+        int idx = xscale1pmu_get_event_idx(cpuc, event);
+        if (idx >= 0)
+                goto out;
+
+        if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
+                idx = XSCALE_COUNTER3;
+        else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
+                idx = XSCALE_COUNTER2;
+out:
+        return idx;
+}
+
+static void
+xscale2pmu_start(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
+        val |= XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static void
+xscale2pmu_stop(void)
+{
+        unsigned long flags, val;
+
+        raw_spin_lock_irqsave(&pmu_lock, flags);
+        val = xscale2pmu_read_pmnc();
+        val &= ~XSCALE_PMU_ENABLE;
+        xscale2pmu_write_pmnc(val);
+        raw_spin_unlock_irqrestore(&pmu_lock, flags);
+}
+
+static inline u32
+xscale2pmu_read_counter(int counter)
+{
+        u32 val = 0;
+
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER2:
+                asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
+                break;
+        case XSCALE_COUNTER3:
+                asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
+                break;
+        }
+
+        return val;
+}
+
+static inline void
+xscale2pmu_write_counter(int counter, u32 val)
+{
+        switch (counter) {
+        case XSCALE_CYCLE_COUNTER:
+                asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER0:
+                asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER1:
+                asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER2:
+                asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
+                break;
+        case XSCALE_COUNTER3:
+                asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
+                break;
+        }
+}
+
+static const struct arm_pmu xscale2pmu = {
+        .id             = ARM_PERF_PMU_ID_XSCALE2,
+        .name           = "xscale2",
+        .handle_irq     = xscale2pmu_handle_irq,
+        .enable         = xscale2pmu_enable_event,
+        .disable        = xscale2pmu_disable_event,
+        .read_counter   = xscale2pmu_read_counter,
+        .write_counter  = xscale2pmu_write_counter,
+        .get_event_idx  = xscale2pmu_get_event_idx,
+        .start          = xscale2pmu_start,
+        .stop           = xscale2pmu_stop,
+        .cache_map      = &xscale_perf_cache_map,
+        .event_map      = &xscale_perf_map,
+        .raw_event_mask = 0xFF,
+        .num_events     = 5,
+        .max_period     = (1LLU << 32) - 1,
+};
+
+static const struct arm_pmu *__init xscale2pmu_init(void)
+{
+        return &xscale2pmu;
+}
+#else
+static const struct arm_pmu *__init xscale1pmu_init(void)
+{
+        return NULL;
+}
+
+static const struct arm_pmu *__init xscale2pmu_init(void)
+{
+        return NULL;
+}
+#endif  /* CONFIG_CPU_XSCALE */
diff --git a/arch/arm/kernel/pj4-cp0.c b/arch/arm/kernel/pj4-cp0.c
new file mode 100644
index 000000000000..a4b1b0748fd3
--- /dev/null
+++ b/arch/arm/kernel/pj4-cp0.c
@@ -0,0 +1,94 @@
+/*
+ * linux/arch/arm/kernel/pj4-cp0.c
+ *
+ * PJ4 iWMMXt coprocessor context switching and handling
+ *
+ * Copyright (c) 2010 Marvell International Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <asm/thread_notify.h>
+
+static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
+{
+        struct thread_info *thread = t;
+
+        switch (cmd) {
+        case THREAD_NOTIFY_FLUSH:
+                /*
+                 * flush_thread() zeroes thread->fpstate, so no need
+                 * to do anything here.
+                 *
+                 * FALLTHROUGH: Ensure we don't try to overwrite our newly
+                 * initialised state information on the first fault.
+                 */
+
+        case THREAD_NOTIFY_EXIT:
+                iwmmxt_task_release(thread);
+                break;
+
+        case THREAD_NOTIFY_SWITCH:
+                iwmmxt_task_switch(thread);
+                break;
+        }
+
+        return NOTIFY_DONE;
+}
+
+static struct notifier_block iwmmxt_notifier_block = {
+        .notifier_call  = iwmmxt_do,
+};
+
+
+static u32 __init pj4_cp_access_read(void)
+{
+        u32 value;
+
+        __asm__ __volatile__ (
+                "mrc    p15, 0, %0, c1, c0, 2\n\t"
+                : "=r" (value));
+        return value;
+}
+
+static void __init pj4_cp_access_write(u32 value)
+{
+        u32 temp;
+
+        __asm__ __volatile__ (
+                "mcr    p15, 0, %1, c1, c0, 2\n\t"
+                "mrc    p15, 0, %0, c1, c0, 2\n\t"
+                "mov    %0, %0\n\t"
+                "sub    pc, pc, #4\n\t"
+                : "=r" (temp) : "r" (value));
+}
+
+
+/*
+ * Disable CP0/CP1 on boot, and let call_fpe() and the iWMMXt lazy
+ * switch code handle iWMMXt context switching.
+ */
+static int __init pj4_cp0_init(void)
+{
+        u32 cp_access;
+
+        cp_access = pj4_cp_access_read() & ~0xf;
+        pj4_cp_access_write(cp_access);
+
+        printk(KERN_INFO "PJ4 iWMMXt coprocessor enabled.\n");
+        elf_hwcap |= HWCAP_IWMMXT;
+        thread_register_notifier(&iwmmxt_notifier_block);
+
+        return 0;
+}
+
+late_initcall(pj4_cp0_init);
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3e97483abcf0..19c6816db61e 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -1060,8 +1060,8 @@ static int ptrace_sethbpregs(struct task_struct *tsk, long num,
                         goto out;
 
                 if ((gen_type & implied_type) != gen_type) {
-                                ret = -EINVAL;
-                                goto out;
+                        ret = -EINVAL;
+                        goto out;
                 }
 
                 attr.bp_len     = gen_len;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 8c1959590252..bbca89872c18 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -16,6 +16,7 @@
 #include <linux/cache.h>
 #include <linux/profile.h>
 #include <linux/errno.h>
+#include <linux/ftrace.h>
 #include <linux/mm.h>
 #include <linux/err.h>
 #include <linux/cpu.h>
@@ -457,7 +458,7 @@ static void ipi_timer(void)
 }
 
 #ifdef CONFIG_LOCAL_TIMERS
-asmlinkage void __exception do_local_timer(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
 {
         struct pt_regs *old_regs = set_irq_regs(regs);
         int cpu = smp_processor_id();
@@ -544,7 +545,7 @@ static void ipi_cpu_stop(unsigned int cpu)
  *
  *  Bit 0 - Inter-processor function call
  */
-asmlinkage void __exception do_IPI(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry do_IPI(struct pt_regs *regs)
 {
         unsigned int cpu = smp_processor_id();
         struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index cead8893b46b..897c1a8f1694 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -101,6 +101,7 @@ SECTIONS
                         __exception_text_start = .;
                         *(.exception.text)
                         __exception_text_end = .;
+                        IRQENTRY_TEXT
                         TEXT_TEXT
                         SCHED_TEXT
                         LOCK_TEXT
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 90fe9ab8591d..08e5c8759502 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -17,6 +17,7 @@
 #include <linux/kernel.h>
 #include <linux/compiler.h>
 #include <linux/io.h>
+#include <linux/dma-mapping.h>
 #include <linux/serial_core.h>
 #include <linux/serial_8250.h>
 #include <linux/platform_device.h>
@@ -108,10 +109,63 @@ static void __init cns3420_early_serial_setup(void)
 }
 
 /*
+ * USB
+ */
+static struct resource cns3xxx_usb_ehci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_USB_BASE,
+                .end   = CNS3XXX_USB_BASE + SZ_16M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_USB_EHCI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ehci_device = {
+        .name          = "cns3xxx-ehci",
+        .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
+        .resource      = cns3xxx_usb_ehci_resources,
+        .dev           = {
+                .dma_mask          = &cns3xxx_usb_ehci_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+static struct resource cns3xxx_usb_ohci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_USB_OHCI_BASE,
+                .end   = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_USB_OHCI,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_usb_ohci_device = {
+        .name          = "cns3xxx-ohci",
+        .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
+        .resource      = cns3xxx_usb_ohci_resources,
+        .dev           = {
+                .dma_mask          = &cns3xxx_usb_ohci_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+};
+
+/*
  * Initialization
  */
 static struct platform_device *cns3420_pdevs[] __initdata = {
         &cns3420_nor_pdev,
+        &cns3xxx_usb_ehci_device,
+        &cns3xxx_usb_ohci_device,
 };
 
 static void __init cns3420_init(void)
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index 6b33ec11346e..73898a7835d3 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -17,7 +17,5 @@ extern struct sys_timer cns3xxx_timer;
 void __init cns3xxx_map_io(void);
 void __init cns3xxx_init_irq(void);
 void cns3xxx_power_off(void);
-void cns3xxx_pwr_power_up(unsigned int block);
-void cns3xxx_pwr_power_down(unsigned int block);
 
 #endif /* __CNS3XXX_CORE_H */
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 50b4d31c27c0..79d1fb02c23f 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
+#include <mach/pm.h>
 #include "core.h"
 #include "devices.h"
 
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 6dbce13771ca..191c8e57f289 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -165,7 +165,6 @@
 #define CNS3XXX_USBOTG_BASE_VIRT                0xFFF15000
 
 #define CNS3XXX_USB_BASE                        0x82000000      /* USB Host Control */
-#define CNS3XXX_USB_BASE_VIRT                   0xFFF16000
 
 #define CNS3XXX_SATA2_BASE                      0x83000000      /* SATA */
 #define CNS3XXX_SATA2_SIZE                      SZ_16M
@@ -184,7 +183,6 @@
 #define CNS3XXX_2DG_BASE_VIRT                   0xFFF1B000
 
 #define CNS3XXX_USB_OHCI_BASE                   0x88000000      /* USB OHCI */
-#define CNS3XXX_USB_OHCI_BASE_VIRT              0xFFF1C000
 
 #define CNS3XXX_L2C_BASE                        0x92000000      /* L2 Cache Control */
 #define CNS3XXX_L2C_BASE_VIRT                   0xFFF27000
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h
new file mode 100644
index 000000000000..6eae7f764d1d
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/pm.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2000 Deep Blue Solutions Ltd
+ * Copyright 2004 ARM Limited
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_PM_H
+#define __CNS3XXX_PM_H
+
+#include <asm/atomic.h>
+
+void cns3xxx_pwr_clk_en(unsigned int block);
+void cns3xxx_pwr_clk_dis(unsigned int block);
+void cns3xxx_pwr_power_up(unsigned int block);
+void cns3xxx_pwr_power_down(unsigned int block);
+
+extern atomic_t usb_pwr_ref;
+
+#endif /* __CNS3XXX_PM_H */
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 38e44706feab..5e579552aa54 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,10 +6,14 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/init.h>
+#include <linux/module.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <asm/atomic.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
+#include <mach/pm.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
@@ -18,6 +22,16 @@ void cns3xxx_pwr_clk_en(unsigned int block)
         reg |= (block & PM_CLK_GATE_REG_MASK);
         __raw_writel(reg, PM_CLK_GATE_REG);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_clk_en);
+
+void cns3xxx_pwr_clk_dis(unsigned int block)
+{
+        u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+        reg &= ~(block & PM_CLK_GATE_REG_MASK);
+        __raw_writel(reg, PM_CLK_GATE_REG);
+}
+EXPORT_SYMBOL(cns3xxx_pwr_clk_dis);
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
@@ -29,6 +43,7 @@ void cns3xxx_pwr_power_up(unsigned int block)
         /* Wait for 300us for the PLL output clock locked. */
         udelay(300);
 };
+EXPORT_SYMBOL(cns3xxx_pwr_power_up);
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
@@ -38,6 +53,7 @@ void cns3xxx_pwr_power_down(unsigned int block)
         reg |= (block & CNS3XXX_PWR_PLL_ALL);
         __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
+EXPORT_SYMBOL(cns3xxx_pwr_power_down);
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
@@ -51,11 +67,13 @@ static void cns3xxx_pwr_soft_rst_force(unsigned int block)
                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
         } else {
                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
+                __raw_writel(reg, PM_SOFT_RST_REG);
                 reg |= (block & PM_SOFT_RST_REG_MASK);
         }
 
         __raw_writel(reg, PM_SOFT_RST_REG);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst_force);
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
 {
@@ -69,6 +87,7 @@ void cns3xxx_pwr_soft_rst(unsigned int block)
         }
         cns3xxx_pwr_soft_rst_force(block);
 }
+EXPORT_SYMBOL(cns3xxx_pwr_soft_rst);
 
 void arch_reset(char mode, const char *cmd)
 {
@@ -99,3 +118,7 @@ int cns3xxx_cpu_clock(void)
 
         return cpu;
 }
+EXPORT_SYMBOL(cns3xxx_cpu_clock);
+
+atomic_t usb_pwr_ref = ATOMIC_INIT(0);
+EXPORT_SYMBOL(usb_pwr_ref);
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index b77b860b36d7..32f147998cd9 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -61,6 +61,8 @@ config MACH_DAVINCI_EVM
         bool "TI DM644x EVM"
         default ARCH_DAVINCI_DM644x
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify the whether the board used
           for development is a DM644x EVM
@@ -68,6 +70,8 @@ config MACH_DAVINCI_EVM
 config MACH_SFFSDR
         bool "Lyrtech SFFSDR"
         depends on ARCH_DAVINCI_DM644x
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the Lyrtech Small Form Factor
           Software Defined Radio (SFFSDR) board.
@@ -99,6 +103,8 @@ config MACH_DAVINCI_DM6467_EVM
         default ARCH_DAVINCI_DM646x
         depends on ARCH_DAVINCI_DM646x
         select MACH_DAVINCI_DM6467TEVM
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify the whether the board used
           for development is a DM6467 EVM
@@ -110,6 +116,8 @@ config MACH_DAVINCI_DM365_EVM
         bool "TI DM365 EVM"
         default ARCH_DAVINCI_DM365
         depends on ARCH_DAVINCI_DM365
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Configure this option to specify whether the board used
           for development is a DM365 EVM
@@ -119,6 +127,8 @@ config MACH_DAVINCI_DA830_EVM
         default ARCH_DAVINCI_DA830
         depends on ARCH_DAVINCI_DA830
         select GPIO_PCF857X
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module.
 
@@ -148,7 +158,6 @@ config MACH_DAVINCI_DA850_EVM
         bool "TI DA850/OMAP-L138/AM18x Reference Platform"
         default ARCH_DAVINCI_DA850
         depends on ARCH_DAVINCI_DA850
-        select GPIO_PCA953X
         help
           Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module.
 
@@ -178,6 +187,12 @@ config DA850_UI_RMII
 
 endchoice
 
+config GPIO_PCA953X
+        default MACH_DAVINCI_DA850_EVM
+
+config KEYBOARD_GPIO_POLLED
+        default MACH_DAVINCI_DA850_EVM
+
 config MACH_TNETV107X
         bool "TI TNETV107X Reference Platform"
         default ARCH_DAVINCI_TNETV107X
@@ -188,6 +203,8 @@ config MACH_TNETV107X
 config MACH_MITYOMAPL138
         bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
         depends on ARCH_DAVINCI_DA850
+        select MISC_DEVICES
+        select EEPROM_AT24
         help
           Say Y here to select the Critical Link MityDSP-L138/MityARM-1808
           System on Module.  Information on this SoM may be found at
diff --git a/arch/arm/mach-davinci/aemif.c b/arch/arm/mach-davinci/aemif.c
index 9c3f500fc12f..1ce70a91f2e9 100644
--- a/arch/arm/mach-davinci/aemif.c
+++ b/arch/arm/mach-davinci/aemif.c
@@ -90,7 +90,7 @@ int davinci_aemif_setup_timing(struct davinci_aemif_timing *t,
                                         void __iomem *base, unsigned cs)
 {
         unsigned set, val;
-        unsigned ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
+        int ta, rhold, rstrobe, rsetup, whold, wstrobe, wsetup;
         unsigned offset = A1CR_OFFSET + cs * 4;
         struct clk *aemif_clk;
         unsigned long clkrate;
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index c6e11c682e4c..b01fb2ab944a 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -17,8 +17,10 @@
 #include <linux/i2c.h>
 #include <linux/i2c/at24.h>
 #include <linux/i2c/pca953x.h>
+#include <linux/input.h>
 #include <linux/mfd/tps6507x.h>
 #include <linux/gpio.h>
+#include <linux/gpio_keys.h>
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
@@ -266,34 +268,115 @@ static inline void da850_evm_setup_emac_rmii(int rmii_sel)
         struct davinci_soc_info *soc_info = &davinci_soc_info;
 
         soc_info->emac_pdata->rmii_en = 1;
-        gpio_set_value(rmii_sel, 0);
+        gpio_set_value_cansleep(rmii_sel, 0);
 }
 #else
 static inline void da850_evm_setup_emac_rmii(int rmii_sel) { }
 #endif
 
+
+#define DA850_KEYS_DEBOUNCE_MS  10
+/*
+ * At 200ms polling interval it is possible to miss an
+ * event by tapping very lightly on the push button but most
+ * pushes do result in an event; longer intervals require the
+ * user to hold the button whereas shorter intervals require
+ * more CPU time for polling.
+ */
+#define DA850_GPIO_KEYS_POLL_MS 200
+
+enum da850_evm_ui_exp_pins {
+        DA850_EVM_UI_EXP_SEL_C = 5,
+        DA850_EVM_UI_EXP_SEL_B,
+        DA850_EVM_UI_EXP_SEL_A,
+        DA850_EVM_UI_EXP_PB8,
+        DA850_EVM_UI_EXP_PB7,
+        DA850_EVM_UI_EXP_PB6,
+        DA850_EVM_UI_EXP_PB5,
+        DA850_EVM_UI_EXP_PB4,
+        DA850_EVM_UI_EXP_PB3,
+        DA850_EVM_UI_EXP_PB2,
+        DA850_EVM_UI_EXP_PB1,
+};
+
+static const char const *da850_evm_ui_exp[] = {
+        [DA850_EVM_UI_EXP_SEL_C]        = "sel_c",
+        [DA850_EVM_UI_EXP_SEL_B]        = "sel_b",
+        [DA850_EVM_UI_EXP_SEL_A]        = "sel_a",
+        [DA850_EVM_UI_EXP_PB8]          = "pb8",
+        [DA850_EVM_UI_EXP_PB7]          = "pb7",
+        [DA850_EVM_UI_EXP_PB6]          = "pb6",
+        [DA850_EVM_UI_EXP_PB5]          = "pb5",
+        [DA850_EVM_UI_EXP_PB4]          = "pb4",
+        [DA850_EVM_UI_EXP_PB3]          = "pb3",
+        [DA850_EVM_UI_EXP_PB2]          = "pb2",
+        [DA850_EVM_UI_EXP_PB1]          = "pb1",
+};
+
+#define DA850_N_UI_PB           8
+
+static struct gpio_keys_button da850_evm_ui_keys[] = {
+        [0 ... DA850_N_UI_PB - 1] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = {
+        .buttons = da850_evm_ui_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_ui_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_ui_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 0,
+        .dev = {
+                .platform_data = &da850_evm_ui_keys_pdata
+        },
+};
+
+static void da850_evm_ui_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        for (i = 0; i < DA850_N_UI_PB; i++) {
+                button = &da850_evm_ui_keys[i];
+                button->code = KEY_F8 - i;
+                button->desc = (char *)
+                                da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i];
+                button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i;
+        }
+}
+
 static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
                                                 unsigned ngpio, void *c)
 {
         int sel_a, sel_b, sel_c, ret;
 
-        sel_a = gpio + 7;
-        sel_b = gpio + 6;
-        sel_c = gpio + 5;
+        sel_a = gpio + DA850_EVM_UI_EXP_SEL_A;
+        sel_b = gpio + DA850_EVM_UI_EXP_SEL_B;
+        sel_c = gpio + DA850_EVM_UI_EXP_SEL_C;
 
-        ret = gpio_request(sel_a, "sel_a");
+        ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_a);
                 goto exp_setup_sela_fail;
         }
 
-        ret = gpio_request(sel_b, "sel_b");
+        ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_b);
                 goto exp_setup_selb_fail;
         }
 
-        ret = gpio_request(sel_c, "sel_c");
+        ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]);
         if (ret) {
                 pr_warning("Cannot open UI expander pin %d\n", sel_c);
                 goto exp_setup_selc_fail;
@@ -304,6 +387,13 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
         gpio_direction_output(sel_b, 1);
         gpio_direction_output(sel_c, 1);
 
+        da850_evm_ui_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_ui_keys_device);
+        if (ret) {
+                pr_warning("Could not register UI GPIO expander push-buttons");
+                goto exp_setup_keys_fail;
+        }
+
         ui_card_detected = 1;
         pr_info("DA850/OMAP-L138 EVM UI card detected\n");
 
@@ -313,6 +403,8 @@ static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio,
 
         return 0;
 
+exp_setup_keys_fail:
+        gpio_free(sel_c);
 exp_setup_selc_fail:
         gpio_free(sel_b);
 exp_setup_selb_fail:
@@ -324,14 +416,192 @@ exp_setup_sela_fail:
 static int da850_evm_ui_expander_teardown(struct i2c_client *client,
                                         unsigned gpio, unsigned ngpio, void *c)
 {
+        platform_device_unregister(&da850_evm_ui_keys_device);
+
         /* deselect all functionalities */
-        gpio_set_value(gpio + 5, 1);
-        gpio_set_value(gpio + 6, 1);
-        gpio_set_value(gpio + 7, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1);
+        gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1);
+
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B);
+        gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A);
+
+        return 0;
+}
+
+/* assign the baseboard expander's GPIOs after the UI board's */
+#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp)
+#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS)
+
+enum da850_evm_bb_exp_pins {
+        DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0,
+        DA850_EVM_BB_EXP_SW_RST,
+        DA850_EVM_BB_EXP_TP_23,
+        DA850_EVM_BB_EXP_TP_22,
+        DA850_EVM_BB_EXP_TP_21,
+        DA850_EVM_BB_EXP_USER_PB1,
+        DA850_EVM_BB_EXP_USER_LED2,
+        DA850_EVM_BB_EXP_USER_LED1,
+        DA850_EVM_BB_EXP_USER_SW1,
+        DA850_EVM_BB_EXP_USER_SW2,
+        DA850_EVM_BB_EXP_USER_SW3,
+        DA850_EVM_BB_EXP_USER_SW4,
+        DA850_EVM_BB_EXP_USER_SW5,
+        DA850_EVM_BB_EXP_USER_SW6,
+        DA850_EVM_BB_EXP_USER_SW7,
+        DA850_EVM_BB_EXP_USER_SW8
+};
+
+static const char const *da850_evm_bb_exp[] = {
+        [DA850_EVM_BB_EXP_DEEP_SLEEP_EN]        = "deep_sleep_en",
+        [DA850_EVM_BB_EXP_SW_RST]               = "sw_rst",
+        [DA850_EVM_BB_EXP_TP_23]                = "tp_23",
+        [DA850_EVM_BB_EXP_TP_22]                = "tp_22",
+        [DA850_EVM_BB_EXP_TP_21]                = "tp_21",
+        [DA850_EVM_BB_EXP_USER_PB1]             = "user_pb1",
+        [DA850_EVM_BB_EXP_USER_LED2]            = "user_led2",
+        [DA850_EVM_BB_EXP_USER_LED1]            = "user_led1",
+        [DA850_EVM_BB_EXP_USER_SW1]             = "user_sw1",
+        [DA850_EVM_BB_EXP_USER_SW2]             = "user_sw2",
+        [DA850_EVM_BB_EXP_USER_SW3]             = "user_sw3",
+        [DA850_EVM_BB_EXP_USER_SW4]             = "user_sw4",
+        [DA850_EVM_BB_EXP_USER_SW5]             = "user_sw5",
+        [DA850_EVM_BB_EXP_USER_SW6]             = "user_sw6",
+        [DA850_EVM_BB_EXP_USER_SW7]             = "user_sw7",
+        [DA850_EVM_BB_EXP_USER_SW8]             = "user_sw8",
+};
+
+#define DA850_N_BB_USER_SW      8
+
+static struct gpio_keys_button da850_evm_bb_keys[] = {
+        [0] = {
+                .type                   = EV_KEY,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = KEY_PROG1,
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+        [1 ... DA850_N_BB_USER_SW] = {
+                .type                   = EV_SW,
+                .active_low             = 1,
+                .wakeup                 = 0,
+                .debounce_interval      = DA850_KEYS_DEBOUNCE_MS,
+                .code                   = -1, /* assigned at runtime */
+                .desc                   = NULL, /* assigned at runtime */
+                .gpio                   = -1, /* assigned at runtime */
+        },
+};
+
+static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = {
+        .buttons = da850_evm_bb_keys,
+        .nbuttons = ARRAY_SIZE(da850_evm_bb_keys),
+        .poll_interval = DA850_GPIO_KEYS_POLL_MS,
+};
+
+static struct platform_device da850_evm_bb_keys_device = {
+        .name = "gpio-keys-polled",
+        .id = 1,
+        .dev = {
+                .platform_data = &da850_evm_bb_keys_pdata
+        },
+};
+
+static void da850_evm_bb_keys_init(unsigned gpio)
+{
+        int i;
+        struct gpio_keys_button *button;
+
+        button = &da850_evm_bb_keys[0];
+        button->desc = (char *)
+                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1];
+        button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1;
+
+        for (i = 0; i < DA850_N_BB_USER_SW; i++) {
+                button = &da850_evm_bb_keys[i + 1];
+                button->code = SW_LID + i;
+                button->desc = (char *)
+                                da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i];
+                button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i;
+        }
+}
 
-        gpio_free(gpio + 5);
-        gpio_free(gpio + 6);
-        gpio_free(gpio + 7);
+#define DA850_N_BB_USER_LED     2
+
+static struct gpio_led da850_evm_bb_leds[] = {
+        [0 ... DA850_N_BB_USER_LED - 1] = {
+                .active_low = 1,
+                .gpio = -1, /* assigned at runtime */
+                .name = NULL, /* assigned at runtime */
+        },
+};
+
+static struct gpio_led_platform_data da850_evm_bb_leds_pdata = {
+        .leds = da850_evm_bb_leds,
+        .num_leds = ARRAY_SIZE(da850_evm_bb_leds),
+};
+
+static struct platform_device da850_evm_bb_leds_device = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev = {
+                .platform_data = &da850_evm_bb_leds_pdata
+        }
+};
+
+static void da850_evm_bb_leds_init(unsigned gpio)
+{
+        int i;
+        struct gpio_led *led;
+
+        for (i = 0; i < DA850_N_BB_USER_LED; i++) {
+                led = &da850_evm_bb_leds[i];
+
+                led->gpio = gpio + DA850_EVM_BB_EXP_USER_LED2 + i;
+                led->name =
+                        da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_LED2 + i];
+        }
+}
+
+static int da850_evm_bb_expander_setup(struct i2c_client *client,
+                                                unsigned gpio, unsigned ngpio,
+                                                void *c)
+{
+        int ret;
+
+        /*
+         * Register the switches and pushbutton on the baseboard as a gpio-keys
+         * device.
+         */
+        da850_evm_bb_keys_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_keys_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander keys");
+                goto io_exp_setup_sw_fail;
+        }
+
+        da850_evm_bb_leds_init(gpio);
+        ret = platform_device_register(&da850_evm_bb_leds_device);
+        if (ret) {
+                pr_warning("Could not register baseboard GPIO expander LEDS");
+                goto io_exp_setup_leds_fail;
+        }
+
+        return 0;
+
+io_exp_setup_leds_fail:
+        platform_device_unregister(&da850_evm_bb_keys_device);
+io_exp_setup_sw_fail:
+        return ret;
+}
+
+static int da850_evm_bb_expander_teardown(struct i2c_client *client,
+                                        unsigned gpio, unsigned ngpio, void *c)
+{
+        platform_device_unregister(&da850_evm_bb_leds_device);
+        platform_device_unregister(&da850_evm_bb_keys_device);
 
         return 0;
 }
@@ -340,6 +610,14 @@ static struct pca953x_platform_data da850_evm_ui_expander_info = {
         .gpio_base      = DAVINCI_N_GPIO,
         .setup          = da850_evm_ui_expander_setup,
         .teardown       = da850_evm_ui_expander_teardown,
+        .names          = da850_evm_ui_exp,
+};
+
+static struct pca953x_platform_data da850_evm_bb_expander_info = {
+        .gpio_base      = DA850_BB_EXPANDER_GPIO_BASE,
+        .setup          = da850_evm_bb_expander_setup,
+        .teardown       = da850_evm_bb_expander_teardown,
+        .names          = da850_evm_bb_exp,
 };
 
 static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
@@ -350,6 +628,10 @@ static struct i2c_board_info __initdata da850_evm_i2c_devices[] = {
                 I2C_BOARD_INFO("tca6416", 0x20),
                 .platform_data = &da850_evm_ui_expander_info,
         },
+        {
+                I2C_BOARD_INFO("tca6416", 0x21),
+                .platform_data = &da850_evm_bb_expander_info,
+        },
 };
 
 static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
@@ -540,7 +822,7 @@ static struct regulator_init_data tps65070_regulator_data[] = {
         {
                 .constraints = {
                         .min_uV = 950000,
-                        .max_uV = 1320000,
+                        .max_uV = 1350000,
                         .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE |
                                 REGULATOR_CHANGE_STATUS),
                         .boot_on = 1,
@@ -591,7 +873,7 @@ static struct tps6507x_board tps_board = {
         .tps6507x_ts_init_data = &tps6507x_touchscreen_data,
 };
 
-static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
+static struct i2c_board_info __initdata da850_evm_tps65070_info[] = {
         {
                 I2C_BOARD_INFO("tps6507x", 0x48),
                 .platform_data = &tps_board,
@@ -600,8 +882,8 @@ static struct i2c_board_info __initdata da850evm_tps65070_info[] = {
 
 static int __init pmic_tps65070_init(void)
 {
-        return i2c_register_board_info(1, da850evm_tps65070_info,
-                                        ARRAY_SIZE(da850evm_tps65070_info));
+        return i2c_register_board_info(1, da850_evm_tps65070_info,
+                                        ARRAY_SIZE(da850_evm_tps65070_info));
 }
 
 static const short da850_evm_lcdc_pins[] = {
@@ -736,6 +1018,27 @@ static struct edma_rsv_info *da850_edma_rsv[2] = {
         &da850_edma_cc1_rsv,
 };
 
+#ifdef CONFIG_CPU_FREQ
+static __init int da850_evm_init_cpufreq(void)
+{
+        switch (system_rev & 0xF) {
+        case 3:
+                da850_max_speed = 456000;
+                break;
+        case 2:
+                da850_max_speed = 408000;
+                break;
+        case 1:
+                da850_max_speed = 372000;
+                break;
+        }
+
+        return da850_register_cpufreq("pll0_sysclk3");
+}
+#else
+static __init int da850_evm_init_cpufreq(void) { return 0; }
+#endif
+
 static __init void da850_evm_init(void)
 {
         int ret;
@@ -836,7 +1139,7 @@ static __init void da850_evm_init(void)
         if (ret)
                 pr_warning("da850_evm_init: rtc setup failed: %d\n", ret);
 
-        ret = da850_register_cpufreq("pll0_sysclk3");
+        ret = da850_evm_init_cpufreq();
         if (ret)
                 pr_warning("da850_evm_init: cpufreq registration failed: %d\n",
                                 ret);
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 01ba080433db..e4e3af179f02 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -336,7 +336,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
                 ratio--;
         }
 
-        if (ratio > PLLDIV_RATIO_MASK)
+        if (ratio > pll->div_ratio_mask)
                 return -EINVAL;
 
         do {
@@ -344,7 +344,7 @@ int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate)
         } while (v & PLLSTAT_GOSTAT);
 
         v = __raw_readl(pll->base + clk->div_reg);
-        v &= ~PLLDIV_RATIO_MASK;
+        v &= ~pll->div_ratio_mask;
         v |= ratio | PLLDIV_EN;
         __raw_writel(v, pll->base + clk->div_reg);
 
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 63916b902760..78b5ae29ae40 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -830,8 +830,7 @@ static void da850_set_async3_src(int pllnum)
  * According to the TRM, minimum PLLM results in maximum power savings.
  * The OPP definitions below should keep the PLLM as low as possible.
  *
- * The output of the PLLM must be between 400 to 600 MHz.
- * This rules out prediv of anything but divide-by-one for 24Mhz OSC input.
+ * The output of the PLLM must be between 300 to 600 MHz.
  */
 struct da850_opp {
         unsigned int    freq;   /* in KHz */
@@ -842,6 +841,33 @@ struct da850_opp {
         unsigned int    cvdd_max; /* in uV */
 };
 
+static const struct da850_opp da850_opp_456 = {
+        .freq           = 456000,
+        .prediv         = 1,
+        .mult           = 19,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_408 = {
+        .freq           = 408000,
+        .prediv         = 1,
+        .mult           = 17,
+        .postdiv        = 1,
+        .cvdd_min       = 1300000,
+        .cvdd_max       = 1350000,
+};
+
+static const struct da850_opp da850_opp_372 = {
+        .freq           = 372000,
+        .prediv         = 2,
+        .mult           = 31,
+        .postdiv        = 1,
+        .cvdd_min       = 1200000,
+        .cvdd_max       = 1320000,
+};
+
 static const struct da850_opp da850_opp_300 = {
         .freq           = 300000,
         .prediv         = 1,
@@ -876,6 +902,9 @@ static const struct da850_opp da850_opp_96 = {
         }
 
 static struct cpufreq_frequency_table da850_freq_table[] = {
+        OPP(456),
+        OPP(408),
+        OPP(372),
         OPP(300),
         OPP(200),
         OPP(96),
@@ -886,6 +915,19 @@ static struct cpufreq_frequency_table da850_freq_table[] = {
 };
 
 #ifdef CONFIG_REGULATOR
+static int da850_set_voltage(unsigned int index);
+static int da850_regulator_init(void);
+#endif
+
+static struct davinci_cpufreq_config cpufreq_info = {
+        .freq_table = da850_freq_table,
+#ifdef CONFIG_REGULATOR
+        .init = da850_regulator_init,
+        .set_voltage = da850_set_voltage,
+#endif
+};
+
+#ifdef CONFIG_REGULATOR
 static struct regulator *cvdd;
 
 static int da850_set_voltage(unsigned int index)
@@ -895,7 +937,7 @@ static int da850_set_voltage(unsigned int index)
         if (!cvdd)
                 return -ENODEV;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
 
         return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max);
 }
@@ -912,14 +954,6 @@ static int da850_regulator_init(void)
 }
 #endif
 
-static struct davinci_cpufreq_config cpufreq_info = {
-        .freq_table = &da850_freq_table[0],
-#ifdef CONFIG_REGULATOR
-        .init = da850_regulator_init,
-        .set_voltage = da850_set_voltage,
-#endif
-};
-
 static struct platform_device da850_cpufreq_device = {
         .name                   = "cpufreq-davinci",
         .dev = {
@@ -928,12 +962,22 @@ static struct platform_device da850_cpufreq_device = {
         .id = -1,
 };
 
+unsigned int da850_max_speed = 300000;
+
 int __init da850_register_cpufreq(char *async_clk)
 {
+        int i;
+
         /* cpufreq driver can help keep an "async" clock constant */
         if (async_clk)
                 clk_add_alias("async", da850_cpufreq_device.name,
                                                         async_clk, NULL);
+        for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) {
+                if (da850_freq_table[i].frequency <= da850_max_speed) {
+                        cpufreq_info.freq_table = &da850_freq_table[i];
+                        break;
+                }
+        }
 
         return platform_device_register(&da850_cpufreq_device);
 }
@@ -942,17 +986,18 @@ static int da850_round_armrate(struct clk *clk, unsigned long rate)
 {
         int i, ret = 0, diff;
         unsigned int best = (unsigned int) -1;
+        struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
 
         rate /= 1000; /* convert to kHz */
 
-        for (i = 0; da850_freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
-                diff = da850_freq_table[i].frequency - rate;
+        for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+                diff = table[i].frequency - rate;
                 if (diff < 0)
                         diff = -diff;
 
                 if (diff < best) {
                         best = diff;
-                        ret = da850_freq_table[i].frequency;
+                        ret = table[i].frequency;
                 }
         }
 
@@ -973,7 +1018,7 @@ static int da850_set_pll0rate(struct clk *clk, unsigned long index)
         struct pll_data *pll = clk->pll_data;
         int ret;
 
-        opp = (struct da850_opp *) da850_freq_table[index].index;
+        opp = (struct da850_opp *) cpufreq_info.freq_table[index].index;
         prediv = opp->prediv;
         mult = opp->mult;
         postdiv = opp->postdiv;
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index c9a86d8130d1..85503debda51 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -344,7 +344,20 @@ static struct platform_device tsc_device = {
 
 void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
 {
-        int i;
+        int i, error;
+        struct clk *tsc_clk;
+
+        /*
+         * The reset defaults for tnetv107x tsc clock divider is set too high.
+         * This forces the clock down to a range that allows the ADC to
+         * complete sample conversion in time.
+         */
+        tsc_clk = clk_get(NULL, "sys_tsc_clk");
+        if (tsc_clk) {
+                error = clk_set_rate(tsc_clk, 5000000);
+                WARN_ON(error < 0);
+                clk_put(tsc_clk);
+        }
 
         platform_device_register(&edma_device);
         platform_device_register(&tnetv107x_wdt_device);
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 4247b3f53b33..e7f952066527 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -28,6 +28,13 @@ extern void __iomem *da8xx_syscfg0_base;
 extern void __iomem *da8xx_syscfg1_base;
 
 /*
+ * If the DA850/OMAP-L138/AM18x SoC on board is of a higher speed grade
+ * (than the regular 300Mhz variant), the board code should set this up
+ * with the supported speed before calling da850_register_cpufreq().
+ */
+extern unsigned int da850_max_speed;
+
+/*
  * The cp_intc interrupt controller for the da8xx isn't in the same
  * chunk of physical memory space as the other registers (like it is
  * on the davincis) so it needs to be mapped separately.  It will be
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index 1b15dbd0a77b..a41580400701 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -83,21 +83,16 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 pdctl1 = __raw_readl(psc_base + PDCTL1);
                 pdctl1 |= 0x100;
                 __raw_writel(pdctl1, psc_base + PDCTL1);
-
-                do {
-                        ptstat = __raw_readl(psc_base +
-                                               PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         } else {
                 ptcmd = 1 << domain;
                 __raw_writel(ptcmd, psc_base + PTCMD);
-
-                do {
-                        ptstat = __raw_readl(psc_base + PTSTAT);
-                } while (!(((ptstat >> domain) & 1) == 0));
         }
 
         do {
+                ptstat = __raw_readl(psc_base + PTSTAT);
+        } while (!(((ptstat >> domain) & 1) == 0));
+
+        do {
                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
         } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
 
diff --git a/arch/arm/mach-davinci/time.c b/arch/arm/mach-davinci/time.c
index 0f21c36e65dd..5d1eea026635 100644
--- a/arch/arm/mach-davinci/time.c
+++ b/arch/arm/mach-davinci/time.c
@@ -272,15 +272,36 @@ static cycle_t read_cycles(struct clocksource *cs)
         return (cycles_t)timer32_read(t);
 }
 
+/*
+ * Kernel assumes that sched_clock can be called early but may not have
+ * things ready yet.
+ */
+static cycle_t read_dummy(struct clocksource *cs)
+{
+        return 0;
+}
+
+
 static struct clocksource clocksource_davinci = {
         .rating         = 300,
-        .read           = read_cycles,
+        .read           = read_dummy,
         .mask           = CLOCKSOURCE_MASK(32),
         .shift          = 24,
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
 /*
+ * Overwrite weak default sched_clock with something more precise
+ */
+unsigned long long notrace sched_clock(void)
+{
+        const cycle_t cyc = clocksource_davinci.read(&clocksource_davinci);
+
+        return clocksource_cyc2ns(cyc, clocksource_davinci.mult,
+                                clocksource_davinci.shift);
+}
+
+/*
  * clockevent
  */
 static int davinci_set_next_event(unsigned long cycles,
@@ -377,6 +398,7 @@ static void __init davinci_timer_init(void)
         davinci_clock_tick_rate = clk_get_rate(timer_clk);
 
         /* setup clocksource */
+        clocksource_davinci.read = read_cycles;
         clocksource_davinci.name = id_to_name[clocksource_id];
         clocksource_davinci.mult =
                 clocksource_khz2mult(davinci_clock_tick_rate/1000,
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index daeae06430b9..6fcdecec8d8c 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -131,12 +131,13 @@ define_pll_clk(tdm, 1, 0x0ff, 0x200);
 define_pll_clk(eth, 2, 0x0ff, 0x400);
 
 /* Level 2 - divided outputs from the PLLs */
-#define define_pll_div_clk(pll, cname, div)             \
-        static struct clk pll##_##cname##_clk = {       \
-                .name           = #pll "_" #cname "_clk",\
-                .parent         = &pll_##pll##_clk,     \
-                .flags          = CLK_PLL,              \
-                .div_reg        = PLLDIV##div,          \
+#define define_pll_div_clk(pll, cname, div)                     \
+        static struct clk pll##_##cname##_clk = {               \
+                .name           = #pll "_" #cname "_clk",       \
+                .parent         = &pll_##pll##_clk,             \
+                .flags          = CLK_PLL,                      \
+                .div_reg        = PLLDIV##div,                  \
+                .set_rate       = davinci_set_sysclk_rate,      \
         }
 
 define_pll_div_clk(sys, arm1176,        1);
@@ -192,6 +193,7 @@ lpsc_clk_enabled(system,	sys_half_clk,	SYSTEM);
 lpsc_clk_enabled(ddr2_vrst,     sys_ddr_clk,    DDR2_EMIF1_VRST);
 lpsc_clk_enabled(ddr2_vctl_rst, sys_ddr_clk,    DDR2_EMIF2_VCTL_RST);
 lpsc_clk_enabled(wdt_arm,       sys_half_clk,   WDT_ARM);
+lpsc_clk_enabled(timer1,        sys_half_clk,   TIMER1);
 
 lpsc_clk(mbx_lite,      sys_arm1176_clk,        MBX_LITE);
 lpsc_clk(ethss,         eth_125mhz_clk,         ETHSS);
@@ -205,16 +207,15 @@ lpsc_clk(mdio,		sys_half_clk,		MDIO);
 lpsc_clk(sdio0,         sys_half_clk,           SDIO0);
 lpsc_clk(sdio1,         sys_half_clk,           SDIO1);
 lpsc_clk(timer0,        sys_half_clk,           TIMER0);
-lpsc_clk(timer1,        sys_half_clk,           TIMER1);
 lpsc_clk(wdt_dsp,       sys_half_clk,           WDT_DSP);
 lpsc_clk(ssp,           sys_half_clk,           SSP);
 lpsc_clk(tdm0,          tdm_0_clk,              TDM0);
 lpsc_clk(tdm1,          tdm_1_clk,              TDM1);
 lpsc_clk(vlynq,         sys_vlynq_ref_clk,      VLYNQ);
 lpsc_clk(mcdma,         sys_half_clk,           MCDMA);
-lpsc_clk(usb0,          sys_half_clk,           USB0);
-lpsc_clk(usb1,          sys_half_clk,           USB1);
 lpsc_clk(usbss,         sys_half_clk,           USBSS);
+lpsc_clk(usb0,          clk_usbss,              USB0);
+lpsc_clk(usb1,          clk_usbss,              USB1);
 lpsc_clk(ethss_rgmii,   eth_250mhz_clk,         ETHSS_RGMII);
 lpsc_clk(imcop,         sys_dsp_clk,            IMCOP);
 lpsc_clk(spare,         sys_half_clk,           SPARE);
@@ -281,7 +282,9 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_tdm0",             &clk_tdm0),
         CLK(NULL,               "clk_vlynq",            &clk_vlynq),
         CLK(NULL,               "clk_mcdma",            &clk_mcdma),
+        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_usb0",             &clk_usb0),
+        CLK(NULL,               "clk_usb1",             &clk_usb1),
         CLK(NULL,               "clk_tdm1",             &clk_tdm1),
         CLK(NULL,               "clk_debugss",          &clk_debugss),
         CLK(NULL,               "clk_ethss_rgmii",      &clk_ethss_rgmii),
@@ -289,8 +292,6 @@ static struct clk_lookup clks[] = {
         CLK(NULL,               "clk_imcop",            &clk_imcop),
         CLK(NULL,               "clk_spare",            &clk_spare),
         CLK("davinci_mmc.1",    NULL,                   &clk_sdio1),
-        CLK(NULL,               "clk_usb1",             &clk_usb1),
-        CLK(NULL,               "clk_usbss",            &clk_usbss),
         CLK(NULL,               "clk_ddr2_vrst",        &clk_ddr2_vrst),
         CLK(NULL,               "clk_ddr2_vctl_rst",    &clk_ddr2_vctl_rst),
         CLK(NULL,               NULL,                   NULL),
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index 3b9a32ace909..a4ed3900912a 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -9,6 +9,12 @@ config MACH_DOVE_DB
           Say 'Y' here if you want your kernel to support the
           Marvell DB-MV88AP510 Development Board.
 
+ config MACH_CM_A510
+        bool "CompuLab CM-A510 Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          CompuLab CM-A510 Board.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 7ab3be53f642..fa0f01856060 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,3 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o
+obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
 
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
+obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
new file mode 100644
index 000000000000..96e0e94e5fa9
--- /dev/null
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -0,0 +1,95 @@
+/*
+ * arch/arm/mach-dove/cm-a510.c
+ *
+ * Copyright (C) 2010 CompuLab, Ltd.
+ * Konstantin Sinyuk <kostyas@compulab.co.il>
+ *
+ * Based on Marvell DB-MV88AP510-BP Development Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/dove.h>
+
+#include "common.h"
+
+static struct mv643xx_eth_platform_data cm_a510_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static struct mv_sata_platform_data cm_a510_sata_data = {
+        .n_ports        = 1,
+};
+
+/*
+ * SPI Devices:
+ * SPI0: 1M Flash Winbond w25q32bv
+ */
+static const struct flash_platform_data cm_a510_spi_flash_data = {
+        .type           = "w25q32bv",
+};
+
+static struct spi_board_info __initdata cm_a510_spi_flash_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &cm_a510_spi_flash_data,
+                .irq            = -1,
+                .max_speed_hz   = 20000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+        },
+};
+
+static int __init cm_a510_pci_init(void)
+{
+        if (machine_is_cm_a510())
+                dove_pcie_init(1, 1);
+
+        return 0;
+}
+
+subsys_initcall(cm_a510_pci_init);
+
+/* Board Init */
+static void __init cm_a510_init(void)
+{
+        /*
+         * Basic Dove setup. Needs to be called early.
+         */
+        dove_init();
+
+        dove_ge00_init(&cm_a510_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_sata_init(&cm_a510_sata_data);
+        dove_sdio0_init();
+        dove_sdio1_init();
+        dove_spi0_init();
+        dove_spi1_init();
+        dove_uart0_init();
+        dove_uart1_init();
+        dove_i2c_init();
+        spi_register_board_info(cm_a510_spi_flash_info,
+                                ARRAY_SIZE(cm_a510_spi_flash_info));
+}
+
+MACHINE_START(CM_A510, "Compulab CM-A510 Board")
+        .boot_params    = 0x00000100,
+        .init_machine   = cm_a510_init,
+        .map_io         = dove_map_io,
+        .init_irq       = dove_init_irq,
+        .timer          = &dove_timer,
+MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index f6a08397f046..27b414578f2e 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -131,14 +131,21 @@
 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
 #define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_VIRT_BASE + 0x40)
-
+#define  DOVE_SPI_GPIO_SEL              (1 << 5)
+#define  DOVE_UART1_GPIO_SEL            (1 << 4)
+#define  DOVE_AU1_GPIO_SEL              (1 << 3)
+#define  DOVE_CAM_GPIO_SEL              (1 << 2)
+#define  DOVE_SD1_GPIO_SEL              (1 << 1)
+#define  DOVE_SD0_GPIO_SEL              (1 << 0)
 
 /* Power Management */
 #define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 
 /* Real Time Clock */
 #define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 0ee70ff39e11..340bb7af529d 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -14,12 +14,14 @@
 #include <plat/gpio.h>
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 
-#define GPIO_MAX        64
+#define GPIO_MAX        72
 
 #define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
 #define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
 
-#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO : GPIO_BASE_HI)
+#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO :            \
+                                 ((pin < 64) ? GPIO_BASE_HI :           \
+                                  DOVE_GPIO2_VIRT_BASE))
 
 #define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
 #define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
new file mode 100644
index 000000000000..71db2bdf2f28
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.c
@@ -0,0 +1,212 @@
+/*
+ * arch/arm/mach-dove/mpp.c
+ *
+ * MPP functions for Marvell Dove SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/dove.h>
+
+#include "mpp.h"
+
+#define MPP_NR_REGS 4
+#define MPP_CTRL(i)     ((i) == 3 ?                             \
+                         DOVE_MPP_CTRL4_VIRT_BASE :             \
+                         DOVE_MPP_VIRT_BASE + (i) * 4)
+#define PMU_SIG_REGS 2
+#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
+
+struct dove_mpp_grp {
+        int start;
+        int end;
+};
+
+static struct dove_mpp_grp dove_mpp_grp[] = {
+        [MPP_24_39] = {
+                .start  = 24,
+                .end    = 39,
+        },
+        [MPP_40_45] = {
+                .start  = 40,
+                .end    = 45,
+        },
+        [MPP_46_51] = {
+                .start  = 40,
+                .end    = 45,
+        },
+        [MPP_58_61] = {
+                .start  = 58,
+                .end    = 61,
+        },
+        [MPP_62_63] = {
+                .start  = 62,
+                .end    = 63,
+        },
+};
+
+static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
+{
+        int i;
+
+        for (i = start; i <= end; i++)
+                orion_gpio_set_valid(i, gpio_mode);
+}
+
+static void dove_mpp_dump_regs(void)
+{
+#ifdef DEBUG
+        int i;
+
+        pr_debug("MPP_CTRL regs:");
+        for (i = 0; i < MPP_NR_REGS; i++)
+                printk(" %08x", readl(MPP_CTRL(i)));
+        printk("\n");
+
+        pr_debug("PMU_SIG_CTRL regs:");
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                printk(" %08x", readl(PMU_SIG_CTRL(i)));
+        printk("\n");
+
+        pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
+        pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
+#endif
+}
+
+static void dove_mpp_cfg_nfc(int sel)
+{
+        u32 mpp_gen_cfg = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        mpp_gen_cfg &= ~0x1;
+        mpp_gen_cfg |= sel;
+        writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE);
+
+        dove_mpp_gpio_mode(64, 71, GPIO_OUTPUT_OK);
+}
+
+static void dove_mpp_cfg_au1(int sel)
+{
+        u32 mpp_ctrl4           = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        mpp_ctrl4 &= ~(DOVE_AU1_GPIO_SEL);
+        ssp_ctrl1 &= ~(DOVE_SSP_ON_AU1);
+        mpp_gen_ctrl &= ~(DOVE_AU1_SPDIFO_GPIO_EN);
+        global_cfg_2 &= ~(DOVE_TWSI_OPTION3_GPIO);
+
+        if (!sel || sel == 0x2)
+                dove_mpp_gpio_mode(52, 57, 0);
+        else
+                dove_mpp_gpio_mode(52, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
+
+        if (sel & 0x1) {
+                global_cfg_2 |= DOVE_TWSI_OPTION3_GPIO;
+                dove_mpp_gpio_mode(56, 57, 0);
+        }
+        if (sel & 0x2) {
+                mpp_gen_ctrl |= DOVE_AU1_SPDIFO_GPIO_EN;
+                dove_mpp_gpio_mode(57, 57, GPIO_OUTPUT_OK | GPIO_INPUT_OK);
+        }
+        if (sel & 0x4) {
+                ssp_ctrl1 |= DOVE_SSP_ON_AU1;
+                dove_mpp_gpio_mode(52, 55, 0);
+        }
+        if (sel & 0x8)
+                mpp_ctrl4 |= DOVE_AU1_GPIO_SEL;
+
+        writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
+        writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1);
+        writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE);
+        writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
+}
+
+static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
+{
+        int start = dove_mpp_grp[num].start;
+        int end = dove_mpp_grp[num].end;
+        int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+
+        *mpp_ctrl &= ~(0x1 << num);
+        *mpp_ctrl |= sel << num;
+
+        dove_mpp_gpio_mode(start, end, gpio_mode);
+}
+
+void __init dove_mpp_conf(unsigned int *mpp_list)
+{
+        u32 mpp_ctrl[MPP_NR_REGS];
+        u32 pmu_mpp_ctrl = 0;
+        u32 pmu_sig_ctrl[PMU_SIG_REGS];
+        int i;
+
+        /* Initialize gpiolib. */
+        orion_gpio_init();
+
+        for (i = 0; i < MPP_NR_REGS; i++)
+                mpp_ctrl[i] = readl(MPP_CTRL(i));
+
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
+
+        pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        dove_mpp_dump_regs();
+
+        for ( ; *mpp_list != MPP_END; mpp_list++) {
+                unsigned int num = MPP_NUM(*mpp_list);
+                unsigned int sel = MPP_SEL(*mpp_list);
+                int shift, gpio_mode;
+
+                if (num > MPP_MAX) {
+                        pr_err("dove: invalid MPP number (%u)\n", num);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_NFC_MASK) {
+                        dove_mpp_cfg_nfc(sel);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_AU1_MASK) {
+                        dove_mpp_cfg_au1(sel);
+                        continue;
+                }
+
+                if (*mpp_list & MPP_GRP_MASK) {
+                        dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
+                        continue;
+                }
+
+                shift = (num & 7) << 2;
+                if (*mpp_list & MPP_PMU_MASK) {
+                        pmu_mpp_ctrl |= (0x1 << num);
+                        pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
+                        pmu_sig_ctrl[num / 8] |= 0xf << shift;
+                        gpio_mode = 0;
+                } else {
+                        mpp_ctrl[num / 8] &= ~(0xf << shift);
+                        mpp_ctrl[num / 8] |= sel << shift;
+                        gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
+                }
+
+                orion_gpio_set_valid(num, gpio_mode);
+        }
+
+        for (i = 0; i < MPP_NR_REGS; i++)
+                writel(mpp_ctrl[i], MPP_CTRL(i));
+
+        for (i = 0; i < PMU_SIG_REGS; i++)
+                writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
+
+        writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
+
+        dove_mpp_dump_regs();
+}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
new file mode 100644
index 000000000000..2a43ce413b15
--- /dev/null
+++ b/arch/arm/mach-dove/mpp.h
@@ -0,0 +1,220 @@
+#ifndef __ARCH_DOVE_MPP_CODED_H
+#define __ARCH_DOVE_MPP_CODED_H
+
+#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) (      \
+/* MPP/group number */          ((_num) & 0xff) |               \
+/* MPP select value */          (((_mode) & 0xf) << 8) |        \
+/* MPP PMU */                   ((!!(_pmu)) << 12) |            \
+/* group flag */                ((!!(_grp)) << 13) |            \
+/* AU1 flag */                  ((!!(_au1)) << 14) |            \
+/* NFCE flag */                 ((!!(_nfc)) << 15))
+
+#define MPP_MAX 71
+
+#define MPP_NUM(x)    ((x) & 0xff)
+#define MPP_SEL(x)    (((x) >> 8) & 0xf)
+
+#define MPP_PMU_MASK            MPP(0, 0x0, 1, 0, 0, 0)
+#define MPP_GRP_MASK            MPP(0, 0x0, 0, 1, 0, 0)
+#define MPP_AU1_MASK            MPP(0, 0x0, 0, 0, 1, 0)
+#define MPP_NFC_MASK            MPP(0, 0x0, 0, 0, 0, 1)
+
+#define MPP_END                 MPP(0xff, 0xf, 1, 1, 1, 1)
+
+#define MPP_PMU_DRIVE_0         0x1
+#define MPP_PMU_DRIVE_1         0x2
+#define MPP_PMU_SDI             0x3
+#define MPP_PMU_CPU_PWRDWN      0x4
+#define MPP_PMU_STBY_PWRDWN     0x5
+#define MPP_PMU_CORE_PWR_GOOD   0x8
+#define MPP_PMU_BAT_FAULT       0xa
+#define MPP_PMU_EXT0_WU         0xb
+#define MPP_PMU_EXT1_WU         0xc
+#define MPP_PMU_EXT2_WU         0xd
+#define MPP_PMU_BLINK           0xe
+#define MPP_PMU(_num, _mode)    MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
+
+#define MPP_PIN(_num, _mode)    MPP((_num), (_mode), 0, 0, 0, 0)
+#define MPP_GRP(_grp, _mode)    MPP((_grp), (_mode), 0, 1, 0, 0)
+#define MPP_GRP_AU1(_mode)      MPP(0, (_mode), 0, 0, 1, 0)
+#define MPP_GRP_NFC(_mode)      MPP(0, (_mode), 0, 0, 0, 1)
+
+#define MPP0_GPIO0              MPP_PIN(0, 0x0)
+#define MPP0_UA2_RTSn           MPP_PIN(0, 0x2)
+#define MPP0_SDIO0_CD           MPP_PIN(0, 0x3)
+#define MPP0_LCD0_PWM           MPP_PIN(0, 0xf)
+
+#define MPP1_GPIO1              MPP_PIN(1, 0x0)
+#define MPP1_UA2_CTSn           MPP_PIN(1, 0x2)
+#define MPP1_SDIO0_WP           MPP_PIN(1, 0x3)
+#define MPP1_LCD1_PWM           MPP_PIN(1, 0xf)
+
+#define MPP2_GPIO2              MPP_PIN(2, 0x0)
+#define MPP2_SATA_PRESENT       MPP_PIN(2, 0x1)
+#define MPP2_UA2_TXD            MPP_PIN(2, 0x2)
+#define MPP2_SDIO0_BUS_POWER    MPP_PIN(2, 0x3)
+#define MPP2_UA_RTSn1           MPP_PIN(2, 0x4)
+
+#define MPP3_GPIO3              MPP_PIN(3, 0x0)
+#define MPP3_SATA_ACT           MPP_PIN(3, 0x1)
+#define MPP3_UA2_RXD            MPP_PIN(3, 0x2)
+#define MPP3_SDIO0_LED_CTRL     MPP_PIN(3, 0x3)
+#define MPP3_UA_CTSn1           MPP_PIN(3, 0x4)
+#define MPP3_SPI_LCD_CS1        MPP_PIN(3, 0xf)
+
+#define MPP4_GPIO4              MPP_PIN(4, 0x0)
+#define MPP4_UA3_RTSn           MPP_PIN(4, 0x2)
+#define MPP4_SDIO1_CD           MPP_PIN(4, 0x3)
+#define MPP4_SPI_1_MISO         MPP_PIN(4, 0x4)
+
+#define MPP5_GPIO5              MPP_PIN(5, 0x0)
+#define MPP5_UA3_CTSn           MPP_PIN(5, 0x2)
+#define MPP5_SDIO1_WP           MPP_PIN(5, 0x3)
+#define MPP5_SPI_1_CS           MPP_PIN(5, 0x4)
+
+#define MPP6_GPIO6              MPP_PIN(6, 0x0)
+#define MPP6_UA3_TXD            MPP_PIN(6, 0x2)
+#define MPP6_SDIO1_BUS_POWER    MPP_PIN(6, 0x3)
+#define MPP6_SPI_1_MOSI         MPP_PIN(6, 0x4)
+
+#define MPP7_GPIO7              MPP_PIN(7, 0x0)
+#define MPP7_UA3_RXD            MPP_PIN(7, 0x2)
+#define MPP7_SDIO1_LED_CTRL     MPP_PIN(7, 0x3)
+#define MPP7_SPI_1_SCK          MPP_PIN(7, 0x4)
+
+#define MPP8_GPIO8              MPP_PIN(8, 0x0)
+#define MPP8_WD_RST_OUT         MPP_PIN(8, 0x1)
+
+#define MPP9_GPIO9              MPP_PIN(9, 0x0)
+#define MPP9_PEX1_CLKREQn       MPP_PIN(9, 0x5)
+
+#define MPP10_GPIO10            MPP_PIN(10, 0x0)
+#define MPP10_SSP_SCLK          MPP_PIN(10, 0x5)
+
+#define MPP11_GPIO11            MPP_PIN(11, 0x0)
+#define MPP11_SATA_PRESENT      MPP_PIN(11, 0x1)
+#define MPP11_SATA_ACT          MPP_PIN(11, 0x2)
+#define MPP11_SDIO0_LED_CTRL    MPP_PIN(11, 0x3)
+#define MPP11_SDIO1_LED_CTRL    MPP_PIN(11, 0x4)
+#define MPP11_PEX0_CLKREQn      MPP_PIN(11, 0x5)
+
+#define MPP12_GPIO12            MPP_PIN(12, 0x0)
+#define MPP12_SATA_ACT          MPP_PIN(12, 0x1)
+#define MPP12_UA2_RTSn          MPP_PIN(12, 0x2)
+#define MPP12_AD0_I2S_EXT_MCLK  MPP_PIN(12, 0x3)
+#define MPP12_SDIO1_CD          MPP_PIN(12, 0x4)
+
+#define MPP13_GPIO13            MPP_PIN(13, 0x0)
+#define MPP13_UA2_CTSn          MPP_PIN(13, 0x2)
+#define MPP13_AD1_I2S_EXT_MCLK  MPP_PIN(13, 0x3)
+#define MPP13_SDIO1WP           MPP_PIN(13, 0x4)
+#define MPP13_SSP_EXTCLK        MPP_PIN(13, 0x5)
+
+#define MPP14_GPIO14            MPP_PIN(14, 0x0)
+#define MPP14_UA2_TXD           MPP_PIN(14, 0x2)
+#define MPP14_SDIO1_BUS_POWER   MPP_PIN(14, 0x4)
+#define MPP14_SSP_RXD           MPP_PIN(14, 0x5)
+
+#define MPP15_GPIO15            MPP_PIN(15, 0x0)
+#define MPP15_UA2_RXD           MPP_PIN(15, 0x2)
+#define MPP15_SDIO1_LED_CTRL    MPP_PIN(15, 0x4)
+#define MPP15_SSP_SFRM          MPP_PIN(15, 0x5)
+
+#define MPP16_GPIO16            MPP_PIN(16, 0x0)
+#define MPP16_UA3_RTSn          MPP_PIN(16, 0x2)
+#define MPP16_SDIO0_CD          MPP_PIN(16, 0x3)
+#define MPP16_SPI_LCD_CS1       MPP_PIN(16, 0x4)
+#define MPP16_AC97_SDATA_IN1    MPP_PIN(16, 0x5)
+
+#define MPP17_GPIO17            MPP_PIN(17, 0x0)
+#define MPP17_AC97_SYSCLK_OUT   MPP_PIN(17, 0x1)
+#define MPP17_UA3_CTSn          MPP_PIN(17, 0x2)
+#define MPP17_SDIO0_WP          MPP_PIN(17, 0x3)
+#define MPP17_TW_SDA2           MPP_PIN(17, 0x4)
+#define MPP17_AC97_SDATA_IN2    MPP_PIN(17, 0x5)
+
+#define MPP18_GPIO18            MPP_PIN(18, 0x0)
+#define MPP18_UA3_TXD           MPP_PIN(18, 0x2)
+#define MPP18_SDIO0_BUS_POWER   MPP_PIN(18, 0x3)
+#define MPP18_LCD0_PWM          MPP_PIN(18, 0x4)
+#define MPP18_AC_SDATA_IN3      MPP_PIN(18, 0x5)
+
+#define MPP19_GPIO19            MPP_PIN(19, 0x0)
+#define MPP19_UA3_RXD           MPP_PIN(19, 0x2)
+#define MPP19_SDIO0_LED_CTRL    MPP_PIN(19, 0x3)
+#define MPP19_TW_SCK2           MPP_PIN(19, 0x4)
+
+#define MPP20_GPIO20            MPP_PIN(20, 0x0)
+#define MPP20_AC97_SYSCLK_OUT   MPP_PIN(20, 0x1)
+#define MPP20_SPI_LCD_MISO      MPP_PIN(20, 0x2)
+#define MPP20_SDIO1_CD          MPP_PIN(20, 0x3)
+#define MPP20_SDIO0_CD          MPP_PIN(20, 0x5)
+#define MPP20_SPI_1_MISO        MPP_PIN(20, 0x6)
+
+#define MPP21_GPIO21            MPP_PIN(21, 0x0)
+#define MPP21_UA1_RTSn          MPP_PIN(21, 0x1)
+#define MPP21_SPI_LCD_CS0       MPP_PIN(21, 0x2)
+#define MPP21_SDIO1_WP          MPP_PIN(21, 0x3)
+#define MPP21_SSP_SFRM          MPP_PIN(21, 0x4)
+#define MPP21_SDIO0_WP          MPP_PIN(21, 0x5)
+#define MPP21_SPI_1_CS          MPP_PIN(21, 0x6)
+
+#define MPP22_GPIO22            MPP_PIN(22, 0x0)
+#define MPP22_UA1_CTSn          MPP_PIN(22, 0x1)
+#define MPP22_SPI_LCD_MOSI      MPP_PIN(22, 0x2)
+#define MPP22_SDIO1_BUS_POWER   MPP_PIN(22, 0x3)
+#define MPP22_SSP_TXD           MPP_PIN(22, 0x4)
+#define MPP22_SDIO0_BUS_POWER   MPP_PIN(22, 0x5)
+#define MPP22_SPI_1_MOSI        MPP_PIN(22, 0x6)
+
+#define MPP23_GPIO23            MPP_PIN(23, 0x0)
+#define MPP23_SPI_LCD_SCK       MPP_PIN(23, 0x2)
+#define MPP23_SDIO1_LED_CTRL    MPP_PIN(23, 0x3)
+#define MPP23_SSP_SCLK          MPP_PIN(23, 0x4)
+#define MPP23_SDIO0_LED_CTRL    MPP_PIN(23, 0x5)
+#define MPP23_SPI_1_SCK         MPP_PIN(23, 0x6)
+
+/* for MPP groups _num is a group index */
+enum dove_mpp_grp_idx {
+        MPP_24_39 = 2,
+        MPP_40_45 = 0,
+        MPP_46_51 = 1,
+        MPP_58_61 = 5,
+        MPP_62_63 = 4,
+};
+
+#define MPP24_39_GPIO           MPP_GRP(MPP_24_39, 0x1)
+#define MPP24_39_CAM            MPP_GRP(MPP_24_39, 0x0)
+
+#define MPP40_45_GPIO           MPP_GRP(MPP_40_45, 0x1)
+#define MPP40_45_SD0            MPP_GRP(MPP_40_45, 0x0)
+
+#define MPP46_51_GPIO           MPP_GRP(MPP_46_51, 0x1)
+#define MPP46_51_SD1            MPP_GRP(MPP_46_51, 0x0)
+
+#define MPP58_61_GPIO           MPP_GRP(MPP_58_61, 0x1)
+#define MPP58_61_SPI            MPP_GRP(MPP_58_61, 0x0)
+
+#define MPP62_63_GPIO           MPP_GRP(MPP_62_63, 0x1)
+#define MPP62_63_UA1            MPP_GRP(MPP_62_63, 0x0)
+
+/* The MPP[64:71] control differs from other groups */
+#define MPP64_71_GPO            MPP_GRP_NFC(0x1)
+#define MPP64_71_NFC            MPP_GRP_NFC(0x0)
+
+/*
+ * The MPP[52:57] functionality is encoded by 4 bits in different
+ * registers. The _num field in this case encodes those bits in
+ * correspodence with Table 135 of 88AP510 Functional specification
+ */
+#define MPP52_57_AU1            MPP_GRP_AU1(0x0)
+#define MPP52_57_AU1_GPIO57     MPP_GRP_AU1(0x2)
+#define MPP52_57_GPIO           MPP_GRP_AU1(0xa)
+#define MPP52_57_TW_GPIO        MPP_GRP_AU1(0xb)
+#define MPP52_57_AU1_SSP        MPP_GRP_AU1(0xc)
+#define MPP52_57_SSP_GPIO       MPP_GRP_AU1(0xe)
+#define MPP52_57_SSP_TW         MPP_GRP_AU1(0xf)
+
+void dove_mpp_conf(unsigned int *mpp_list);
+
+#endif  /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 34106335c728..7fc603b46891 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -45,18 +45,18 @@ config MACH_GURUPLUG
           Marvell GuruPlug Reference Board.
 
 config MACH_TS219
-        bool "QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS"
+        bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          QNAP TS-110, TS-119, TS-210, TS-219 and TS-219P Turbo NAS
-          devices.
+          QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+          TS-219P+ Turbo NAS devices.
 
 config MACH_TS41X
-        bool "QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS"
+        bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
         help
           Say 'Y' here if you want your kernel to support the
-          QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
-          devices.
+          QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
+          NAS devices.
 
 config MACH_DOCKSTAR
         bool "Seagate FreeAgent DockStar"
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 6710bd7773b8..dc999c4c5806 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -80,15 +80,19 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
         MPP14_UART1_RXD,        /* PIC controller */
-        MPP15_GPIO,             /* USB Copy button */
-        MPP16_GPIO,             /* Reset button */
+        MPP15_GPIO,             /* USB Copy button (on devices with 88F6281) */
+        MPP16_GPIO,             /* Reset button (on devices with 88F6281) */
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP37_GPIO,             /* Reset button (on devices with 88F6282) */
+        MPP43_GPIO,             /* USB Copy button (on devices with 88F6282) */
         MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
         0
 };
 
 static void __init qnap_ts219_init(void)
 {
+        u32 dev, rev;
+
         /*
          * Basic setup. Needs to be called early.
          */
@@ -100,6 +104,14 @@ static void __init qnap_ts219_init(void)
         qnap_tsx1x_register_flash();
         kirkwood_i2c_init();
         i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6282_DEV_ID) {
+                qnap_ts219_buttons[0].gpio = 43; /* USB Copy button */
+                qnap_ts219_buttons[1].gpio = 37; /* Reset button */
+                qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+        }
+
         kirkwood_ge00_init(&qnap_ts219_ge00_data);
         kirkwood_sata_init(&qnap_ts219_sata_data);
         kirkwood_ehci_init();
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 3587a281d993..9a44029915e2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -119,6 +119,8 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
 
 static void __init qnap_ts41x_init(void)
 {
+        u32 dev, rev;
+
         /*
          * Basic setup. Needs to be called early.
          */
@@ -130,8 +132,15 @@ static void __init qnap_ts41x_init(void)
         qnap_tsx1x_register_flash();
         kirkwood_i2c_init();
         i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
+
+        kirkwood_pcie_id(&dev, &rev);
+        if (dev == MV88F6282_DEV_ID) {
+                qnap_ts41x_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+                qnap_ts41x_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+        }
         kirkwood_ge00_init(&qnap_ts41x_ge00_data);
         kirkwood_ge01_init(&qnap_ts41x_ge01_data);
+
         kirkwood_sata_init(&qnap_ts41x_sata_data);
         kirkwood_ehci_init();
         platform_device_register(&qnap_ts41x_button_device);
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 0711d3b620ad..67793a690272 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -37,25 +37,38 @@ config MACH_TTC_DKB
           Say 'Y' here if you want to support the Marvell PXA910-based
           TTC_DKB Development Board.
 
+config MACH_BROWNSTONE
+        bool "Marvell's Brownstone Development Platform"
+        depends on !CPU_MOHAWK
+        select CPU_MMP2
+        help
+          Say 'Y' here if you want to support the Marvell MMP2-based
+          Brown Development Platform.
+          MMP2-based board can't be co-existed with PXA168-based &
+          PXA910-based development board. Since MMP2 is compatible to
+          ARMv7 architecture.
+
 config MACH_FLINT
         bool "Marvell's Flint Development Platform"
+        depends on !CPU_MOHAWK
         select CPU_MMP2
         help
           Say 'Y' here if you want to support the Marvell MMP2-based
           Flint Development Platform.
           MMP2-based board can't be co-existed with PXA168-based &
           PXA910-based development board. Since MMP2 is compatible to
-          ARMv6 architecture.
+          ARMv7 architecture.
 
 config MACH_MARVELL_JASPER
         bool "Marvell's Jasper Development Platform"
+        depends on !CPU_MOHAWK
         select CPU_MMP2
         help
           Say 'Y' here if you want to support the Marvell MMP2-base
           Jasper Development Platform.
           MMP2-based board can't be co-existed with PXA168-based &
           PXA910-based development board. Since MMP2 is compatible to
-          ARMv6 architecture.
+          ARMv7 architecture.
 
 config MACH_TETON_BGA
         bool "Marvell's PXA168 Teton BGA Development Board"
@@ -80,8 +93,7 @@ config CPU_PXA910
 
 config CPU_MMP2
         bool
-        select CPU_V6
-        select CPU_32v6K
+        select CPU_PJ4
         help
-          Select code specific to MMP2. MMP2 is ARMv6 compatible.
+          Select code specific to MMP2. MMP2 is ARMv7 compatible.
 endif
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 751cdbf733c8..5c68382141af 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_MACH_ZYLONITE2)	+= aspenite.o
 obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
 obj-$(CONFIG_MACH_TTC_DKB)      += ttc_dkb.o
+obj-$(CONFIG_MACH_BROWNSTONE)   += brownstone.o
 obj-$(CONFIG_MACH_FLINT)        += flint.o
 obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
 obj-$(CONFIG_MACH_TETON_BGA)    += teton_bga.o
diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c
new file mode 100644
index 000000000000..7bb78fd5a2a6
--- /dev/null
+++ b/arch/arm/mach-mmp/brownstone.c
@@ -0,0 +1,204 @@
+/*
+ *  linux/arch/arm/mach-mmp/brownstone.c
+ *
+ *  Support for the Marvell Brownstone Development Platform.
+ *
+ *  Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/max8649.h>
+#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8925.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/addr-map.h>
+#include <mach/mfp-mmp2.h>
+#include <mach/mmp2.h>
+#include <mach/irqs.h>
+
+#include "common.h"
+
+#define BROWNSTONE_NR_IRQS      (IRQ_BOARD_START + 40)
+
+#define GPIO_5V_ENABLE          (89)
+
+static unsigned long brownstone_pin_config[] __initdata = {
+        /* UART1 */
+        GPIO29_UART1_RXD,
+        GPIO30_UART1_TXD,
+
+        /* UART3 */
+        GPIO51_UART3_RXD,
+        GPIO52_UART3_TXD,
+
+        /* DFI */
+        GPIO168_DFI_D0,
+        GPIO167_DFI_D1,
+        GPIO166_DFI_D2,
+        GPIO165_DFI_D3,
+        GPIO107_DFI_D4,
+        GPIO106_DFI_D5,
+        GPIO105_DFI_D6,
+        GPIO104_DFI_D7,
+        GPIO111_DFI_D8,
+        GPIO164_DFI_D9,
+        GPIO163_DFI_D10,
+        GPIO162_DFI_D11,
+        GPIO161_DFI_D12,
+        GPIO110_DFI_D13,
+        GPIO109_DFI_D14,
+        GPIO108_DFI_D15,
+        GPIO143_ND_nCS0,
+        GPIO144_ND_nCS1,
+        GPIO147_ND_nWE,
+        GPIO148_ND_nRE,
+        GPIO150_ND_ALE,
+        GPIO149_ND_CLE,
+        GPIO112_ND_RDY0,
+        GPIO160_ND_RDY1,
+
+        /* PMIC */
+        PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
+
+        /* MMC0 */
+        GPIO131_MMC1_DAT3 | MFP_PULL_HIGH,
+        GPIO132_MMC1_DAT2 | MFP_PULL_HIGH,
+        GPIO133_MMC1_DAT1 | MFP_PULL_HIGH,
+        GPIO134_MMC1_DAT0 | MFP_PULL_HIGH,
+        GPIO136_MMC1_CMD | MFP_PULL_HIGH,
+        GPIO139_MMC1_CLK,
+        GPIO140_MMC1_CD | MFP_PULL_LOW,
+        GPIO141_MMC1_WP | MFP_PULL_LOW,
+
+        /* MMC1 */
+        GPIO37_MMC2_DAT3 | MFP_PULL_HIGH,
+        GPIO38_MMC2_DAT2 | MFP_PULL_HIGH,
+        GPIO39_MMC2_DAT1 | MFP_PULL_HIGH,
+        GPIO40_MMC2_DAT0 | MFP_PULL_HIGH,
+        GPIO41_MMC2_CMD | MFP_PULL_HIGH,
+        GPIO42_MMC2_CLK,
+
+        /* MMC2 */
+        GPIO165_MMC3_DAT7 | MFP_PULL_HIGH,
+        GPIO162_MMC3_DAT6 | MFP_PULL_HIGH,
+        GPIO166_MMC3_DAT5 | MFP_PULL_HIGH,
+        GPIO163_MMC3_DAT4 | MFP_PULL_HIGH,
+        GPIO167_MMC3_DAT3 | MFP_PULL_HIGH,
+        GPIO164_MMC3_DAT2 | MFP_PULL_HIGH,
+        GPIO168_MMC3_DAT1 | MFP_PULL_HIGH,
+        GPIO111_MMC3_DAT0 | MFP_PULL_HIGH,
+        GPIO112_MMC3_CMD | MFP_PULL_HIGH,
+        GPIO151_MMC3_CLK,
+
+        /* 5V regulator */
+        GPIO89_GPIO,
+};
+
+static struct regulator_consumer_supply max8649_supply[] = {
+        REGULATOR_SUPPLY("vcc_core", NULL),
+};
+
+static struct regulator_init_data max8649_init_data = {
+        .constraints    = {
+                .name           = "vcc_core range",
+                .min_uV         = 1150000,
+                .max_uV         = 1280000,
+                .always_on      = 1,
+                .boot_on        = 1,
+                .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &max8649_supply[0],
+};
+
+static struct max8649_platform_data brownstone_max8649_info = {
+        .mode           = 2,    /* VID1 = 1, VID0 = 0 */
+        .extclk         = 0,
+        .ramp_timing    = MAX8649_RAMP_32MV,
+        .regulator      = &max8649_init_data,
+};
+
+static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = {
+        REGULATOR_SUPPLY("v_5vp", NULL),
+};
+
+static struct regulator_init_data brownstone_v_5vp_data = {
+        .constraints    = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(brownstone_v_5vp_supplies),
+        .consumer_supplies      = brownstone_v_5vp_supplies,
+};
+
+static struct fixed_voltage_config brownstone_v_5vp = {
+        .supply_name            = "v_5vp",
+        .microvolts             = 5000000,
+        .gpio                   = GPIO_5V_ENABLE,
+        .enable_high            = 1,
+        .enabled_at_boot        = 1,
+        .init_data              = &brownstone_v_5vp_data,
+};
+
+static struct platform_device brownstone_v_5vp_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &brownstone_v_5vp,
+        },
+};
+
+static struct max8925_platform_data brownstone_max8925_info = {
+        .irq_base               = IRQ_BOARD_START,
+};
+
+static struct i2c_board_info brownstone_twsi1_info[] = {
+        [0] = {
+                .type           = "max8649",
+                .addr           = 0x60,
+                .platform_data  = &brownstone_max8649_info,
+        },
+        [1] = {
+                .type           = "max8925",
+                .addr           = 0x3c,
+                .irq            = IRQ_MMP2_PMIC,
+                .platform_data  = &brownstone_max8925_info,
+        },
+};
+
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
+        .max_speed      = 25000000,
+};
+
+static void __init brownstone_init(void)
+{
+        mfp_config(ARRAY_AND_SIZE(brownstone_pin_config));
+
+        /* on-chip devices */
+        mmp2_add_uart(1);
+        mmp2_add_uart(3);
+        mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info));
+        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
+
+        /* enable 5v regulator */
+        platform_device_register(&brownstone_v_5vp_device);
+}
+
+MACHINE_START(BROWNSTONE, "Brownstone Development Platform")
+        /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */
+        .map_io         = mmp_map_io,
+        .nr_irqs        = BROWNSTONE_NR_IRQS,
+        .init_irq       = mmp2_init_irq,
+        .timer          = &mmp2_timer,
+        .init_machine   = brownstone_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c
index bdeb6db4d49a..c4fd806b15b4 100644
--- a/arch/arm/mach-mmp/flint.c
+++ b/arch/arm/mach-mmp/flint.c
@@ -47,7 +47,7 @@ static unsigned long flint_pin_config[] __initdata = {
         GPIO113_SMC_RDY,
 
         /*Ethernet*/
-        GPIO155_GPIO155,
+        GPIO155_GPIO,
 
         /* DFI */
         GPIO168_DFI_D0,
diff --git a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
index 761c2dacc079..117e30366087 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-mmp2.h
@@ -9,175 +9,175 @@
 #define MFP_DRIVE_FAST          (0x8 << 13)
 
 /* GPIO */
-#define GPIO0_GPIO0             MFP_CFG(GPIO0, AF0)
-#define GPIO1_GPIO1             MFP_CFG(GPIO1, AF0)
-#define GPIO2_GPIO2             MFP_CFG(GPIO2, AF0)
-#define GPIO3_GPIO3             MFP_CFG(GPIO3, AF0)
-#define GPIO4_GPIO4             MFP_CFG(GPIO4, AF0)
-#define GPIO5_GPIO5             MFP_CFG(GPIO5, AF0)
-#define GPIO6_GPIO6             MFP_CFG(GPIO6, AF0)
-#define GPIO7_GPIO7             MFP_CFG(GPIO7, AF0)
-#define GPIO8_GPIO8             MFP_CFG(GPIO8, AF0)
-#define GPIO9_GPIO9             MFP_CFG(GPIO9, AF0)
-#define GPIO10_GPIO10           MFP_CFG(GPIO10, AF0)
-#define GPIO11_GPIO11           MFP_CFG(GPIO11, AF0)
-#define GPIO12_GPIO12           MFP_CFG(GPIO12, AF0)
-#define GPIO13_GPIO13           MFP_CFG(GPIO13, AF0)
-#define GPIO14_GPIO14           MFP_CFG(GPIO14, AF0)
-#define GPIO15_GPIO15           MFP_CFG(GPIO15, AF0)
-#define GPIO16_GPIO16           MFP_CFG(GPIO16, AF0)
-#define GPIO17_GPIO17           MFP_CFG(GPIO17, AF0)
-#define GPIO18_GPIO18           MFP_CFG(GPIO18, AF0)
-#define GPIO19_GPIO19           MFP_CFG(GPIO19, AF0)
-#define GPIO20_GPIO20           MFP_CFG(GPIO20, AF0)
-#define GPIO21_GPIO21           MFP_CFG(GPIO21, AF0)
-#define GPIO22_GPIO22           MFP_CFG(GPIO22, AF0)
-#define GPIO23_GPIO23           MFP_CFG(GPIO23, AF0)
-#define GPIO24_GPIO24           MFP_CFG(GPIO24, AF0)
-#define GPIO25_GPIO25           MFP_CFG(GPIO25, AF0)
-#define GPIO26_GPIO26           MFP_CFG(GPIO26, AF0)
-#define GPIO27_GPIO27           MFP_CFG(GPIO27, AF0)
-#define GPIO28_GPIO28           MFP_CFG(GPIO28, AF0)
-#define GPIO29_GPIO29           MFP_CFG(GPIO29, AF0)
-#define GPIO30_GPIO30           MFP_CFG(GPIO30, AF0)
-#define GPIO31_GPIO31           MFP_CFG(GPIO31, AF0)
-#define GPIO32_GPIO32           MFP_CFG(GPIO32, AF0)
-#define GPIO33_GPIO33           MFP_CFG(GPIO33, AF0)
-#define GPIO34_GPIO34           MFP_CFG(GPIO34, AF0)
-#define GPIO35_GPIO35           MFP_CFG(GPIO35, AF0)
-#define GPIO36_GPIO36           MFP_CFG(GPIO36, AF0)
-#define GPIO37_GPIO37           MFP_CFG(GPIO37, AF0)
-#define GPIO38_GPIO38           MFP_CFG(GPIO38, AF0)
-#define GPIO39_GPIO39           MFP_CFG(GPIO39, AF0)
-#define GPIO40_GPIO40           MFP_CFG(GPIO40, AF0)
-#define GPIO41_GPIO41           MFP_CFG(GPIO41, AF0)
-#define GPIO42_GPIO42           MFP_CFG(GPIO42, AF0)
-#define GPIO43_GPIO43           MFP_CFG(GPIO43, AF0)
-#define GPIO44_GPIO44           MFP_CFG(GPIO44, AF0)
-#define GPIO45_GPIO45           MFP_CFG(GPIO45, AF0)
-#define GPIO46_GPIO46           MFP_CFG(GPIO46, AF0)
-#define GPIO47_GPIO47           MFP_CFG(GPIO47, AF0)
-#define GPIO48_GPIO48           MFP_CFG(GPIO48, AF0)
-#define GPIO49_GPIO49           MFP_CFG(GPIO49, AF0)
-#define GPIO50_GPIO50           MFP_CFG(GPIO50, AF0)
-#define GPIO51_GPIO51           MFP_CFG(GPIO51, AF0)
-#define GPIO52_GPIO52           MFP_CFG(GPIO52, AF0)
-#define GPIO53_GPIO53           MFP_CFG(GPIO53, AF0)
-#define GPIO54_GPIO54           MFP_CFG(GPIO54, AF0)
-#define GPIO55_GPIO55           MFP_CFG(GPIO55, AF0)
-#define GPIO56_GPIO56           MFP_CFG(GPIO56, AF0)
-#define GPIO57_GPIO57           MFP_CFG(GPIO57, AF0)
-#define GPIO58_GPIO58           MFP_CFG(GPIO58, AF0)
-#define GPIO59_GPIO59           MFP_CFG(GPIO59, AF0)
-#define GPIO60_GPIO60           MFP_CFG(GPIO60, AF0)
-#define GPIO61_GPIO61           MFP_CFG(GPIO61, AF0)
-#define GPIO62_GPIO62           MFP_CFG(GPIO62, AF0)
-#define GPIO63_GPIO63           MFP_CFG(GPIO63, AF0)
-#define GPIO64_GPIO64           MFP_CFG(GPIO64, AF0)
-#define GPIO65_GPIO65           MFP_CFG(GPIO65, AF0)
-#define GPIO66_GPIO66           MFP_CFG(GPIO66, AF0)
-#define GPIO67_GPIO67           MFP_CFG(GPIO67, AF0)
-#define GPIO68_GPIO68           MFP_CFG(GPIO68, AF0)
-#define GPIO69_GPIO69           MFP_CFG(GPIO69, AF0)
-#define GPIO70_GPIO70           MFP_CFG(GPIO70, AF0)
-#define GPIO71_GPIO71           MFP_CFG(GPIO71, AF0)
-#define GPIO72_GPIO72           MFP_CFG(GPIO72, AF0)
-#define GPIO73_GPIO73           MFP_CFG(GPIO73, AF0)
-#define GPIO74_GPIO74           MFP_CFG(GPIO74, AF0)
-#define GPIO75_GPIO75           MFP_CFG(GPIO75, AF0)
-#define GPIO76_GPIO76           MFP_CFG(GPIO76, AF0)
-#define GPIO77_GPIO77           MFP_CFG(GPIO77, AF0)
-#define GPIO78_GPIO78           MFP_CFG(GPIO78, AF0)
-#define GPIO79_GPIO79           MFP_CFG(GPIO79, AF0)
-#define GPIO80_GPIO80           MFP_CFG(GPIO80, AF0)
-#define GPIO81_GPIO81           MFP_CFG(GPIO81, AF0)
-#define GPIO82_GPIO82           MFP_CFG(GPIO82, AF0)
-#define GPIO83_GPIO83           MFP_CFG(GPIO83, AF0)
-#define GPIO84_GPIO84           MFP_CFG(GPIO84, AF0)
-#define GPIO85_GPIO85           MFP_CFG(GPIO85, AF0)
-#define GPIO86_GPIO86           MFP_CFG(GPIO86, AF0)
-#define GPIO87_GPIO87           MFP_CFG(GPIO87, AF0)
-#define GPIO88_GPIO88           MFP_CFG(GPIO88, AF0)
-#define GPIO89_GPIO89           MFP_CFG(GPIO89, AF0)
-#define GPIO90_GPIO90           MFP_CFG(GPIO90, AF0)
-#define GPIO91_GPIO91           MFP_CFG(GPIO91, AF0)
-#define GPIO92_GPIO92           MFP_CFG(GPIO92, AF0)
-#define GPIO93_GPIO93           MFP_CFG(GPIO93, AF0)
-#define GPIO94_GPIO94           MFP_CFG(GPIO94, AF0)
-#define GPIO95_GPIO95           MFP_CFG(GPIO95, AF0)
-#define GPIO96_GPIO96           MFP_CFG(GPIO96, AF0)
-#define GPIO97_GPIO97           MFP_CFG(GPIO97, AF0)
-#define GPIO98_GPIO98           MFP_CFG(GPIO98, AF0)
-#define GPIO99_GPIO99           MFP_CFG(GPIO99, AF0)
-#define GPIO100_GPIO100         MFP_CFG(GPIO100, AF0)
-#define GPIO101_GPIO101         MFP_CFG(GPIO101, AF0)
-#define GPIO102_GPIO102         MFP_CFG(GPIO102, AF1)
-#define GPIO103_GPIO103         MFP_CFG(GPIO103, AF1)
-#define GPIO104_GPIO104         MFP_CFG(GPIO104, AF1)
-#define GPIO105_GPIO105         MFP_CFG(GPIO105, AF1)
-#define GPIO106_GPIO106         MFP_CFG(GPIO106, AF1)
-#define GPIO107_GPIO107         MFP_CFG(GPIO107, AF1)
-#define GPIO108_GPIO108         MFP_CFG(GPIO108, AF1)
-#define GPIO109_GPIO109         MFP_CFG(GPIO109, AF1)
-#define GPIO110_GPIO110         MFP_CFG(GPIO110, AF1)
-#define GPIO111_GPIO111         MFP_CFG(GPIO111, AF1)
-#define GPIO112_GPIO112         MFP_CFG(GPIO112, AF1)
-#define GPIO113_GPIO113         MFP_CFG(GPIO113, AF1)
-#define GPIO114_GPIO114         MFP_CFG(GPIO114, AF0)
-#define GPIO115_GPIO115         MFP_CFG(GPIO115, AF0)
-#define GPIO116_GPIO116         MFP_CFG(GPIO116, AF0)
-#define GPIO117_GPIO117         MFP_CFG(GPIO117, AF0)
-#define GPIO118_GPIO118         MFP_CFG(GPIO118, AF0)
-#define GPIO119_GPIO119         MFP_CFG(GPIO119, AF0)
-#define GPIO120_GPIO120         MFP_CFG(GPIO120, AF0)
-#define GPIO121_GPIO121         MFP_CFG(GPIO121, AF0)
-#define GPIO122_GPIO122         MFP_CFG(GPIO122, AF0)
-#define GPIO123_GPIO123         MFP_CFG(GPIO123, AF0)
-#define GPIO124_GPIO124         MFP_CFG(GPIO124, AF0)
-#define GPIO125_GPIO125         MFP_CFG(GPIO125, AF0)
-#define GPIO126_GPIO126         MFP_CFG(GPIO126, AF0)
-#define GPIO127_GPIO127         MFP_CFG(GPIO127, AF0)
-#define GPIO128_GPIO128         MFP_CFG(GPIO128, AF0)
-#define GPIO129_GPIO129         MFP_CFG(GPIO129, AF0)
-#define GPIO130_GPIO130         MFP_CFG(GPIO130, AF0)
-#define GPIO131_GPIO131         MFP_CFG(GPIO131, AF0)
-#define GPIO132_GPIO132         MFP_CFG(GPIO132, AF0)
-#define GPIO133_GPIO133         MFP_CFG(GPIO133, AF0)
-#define GPIO134_GPIO134         MFP_CFG(GPIO134, AF0)
-#define GPIO135_GPIO135         MFP_CFG(GPIO135, AF0)
-#define GPIO136_GPIO136         MFP_CFG(GPIO136, AF0)
-#define GPIO137_GPIO137         MFP_CFG(GPIO137, AF0)
-#define GPIO138_GPIO138         MFP_CFG(GPIO138, AF0)
-#define GPIO139_GPIO139         MFP_CFG(GPIO139, AF0)
-#define GPIO140_GPIO140         MFP_CFG(GPIO140, AF0)
-#define GPIO141_GPIO141         MFP_CFG(GPIO141, AF0)
-#define GPIO142_GPIO142         MFP_CFG(GPIO142, AF1)
-#define GPIO143_GPIO143         MFP_CFG(GPIO143, AF1)
-#define GPIO144_GPIO144         MFP_CFG(GPIO144, AF1)
-#define GPIO145_GPIO145         MFP_CFG(GPIO145, AF1)
-#define GPIO146_GPIO146         MFP_CFG(GPIO146, AF1)
-#define GPIO147_GPIO147         MFP_CFG(GPIO147, AF1)
-#define GPIO148_GPIO148         MFP_CFG(GPIO148, AF1)
-#define GPIO149_GPIO149         MFP_CFG(GPIO149, AF1)
-#define GPIO150_GPIO150         MFP_CFG(GPIO150, AF1)
-#define GPIO151_GPIO151         MFP_CFG(GPIO151, AF1)
-#define GPIO152_GPIO152         MFP_CFG(GPIO152, AF1)
-#define GPIO153_GPIO153         MFP_CFG(GPIO153, AF1)
-#define GPIO154_GPIO154         MFP_CFG(GPIO154, AF1)
-#define GPIO155_GPIO155         MFP_CFG(GPIO155, AF1)
-#define GPIO156_GPIO156         MFP_CFG(GPIO156, AF1)
-#define GPIO157_GPIO157         MFP_CFG(GPIO157, AF1)
-#define GPIO158_GPIO158         MFP_CFG(GPIO158, AF1)
-#define GPIO159_GPIO159         MFP_CFG(GPIO159, AF1)
-#define GPIO160_GPIO160         MFP_CFG(GPIO160, AF1)
-#define GPIO161_GPIO161         MFP_CFG(GPIO161, AF1)
-#define GPIO162_GPIO162         MFP_CFG(GPIO162, AF1)
-#define GPIO163_GPIO163         MFP_CFG(GPIO163, AF1)
-#define GPIO164_GPIO164         MFP_CFG(GPIO164, AF1)
-#define GPIO165_GPIO165         MFP_CFG(GPIO165, AF1)
-#define GPIO166_GPIO166         MFP_CFG(GPIO166, AF1)
-#define GPIO167_GPIO167         MFP_CFG(GPIO167, AF1)
-#define GPIO168_GPIO168         MFP_CFG(GPIO168, AF1)
+#define GPIO0_GPIO      MFP_CFG(GPIO0, AF0)
+#define GPIO1_GPIO      MFP_CFG(GPIO1, AF0)
+#define GPIO2_GPIO      MFP_CFG(GPIO2, AF0)
+#define GPIO3_GPIO      MFP_CFG(GPIO3, AF0)
+#define GPIO4_GPIO      MFP_CFG(GPIO4, AF0)
+#define GPIO5_GPIO      MFP_CFG(GPIO5, AF0)
+#define GPIO6_GPIO      MFP_CFG(GPIO6, AF0)
+#define GPIO7_GPIO      MFP_CFG(GPIO7, AF0)
+#define GPIO8_GPIO      MFP_CFG(GPIO8, AF0)
+#define GPIO9_GPIO      MFP_CFG(GPIO9, AF0)
+#define GPIO10_GPIO     MFP_CFG(GPIO10, AF0)
+#define GPIO11_GPIO     MFP_CFG(GPIO11, AF0)
+#define GPIO12_GPIO     MFP_CFG(GPIO12, AF0)
+#define GPIO13_GPIO     MFP_CFG(GPIO13, AF0)
+#define GPIO14_GPIO     MFP_CFG(GPIO14, AF0)
+#define GPIO15_GPIO     MFP_CFG(GPIO15, AF0)
+#define GPIO16_GPIO     MFP_CFG(GPIO16, AF0)
+#define GPIO17_GPIO     MFP_CFG(GPIO17, AF0)
+#define GPIO18_GPIO     MFP_CFG(GPIO18, AF0)
+#define GPIO19_GPIO     MFP_CFG(GPIO19, AF0)
+#define GPIO20_GPIO     MFP_CFG(GPIO20, AF0)
+#define GPIO21_GPIO     MFP_CFG(GPIO21, AF0)
+#define GPIO22_GPIO     MFP_CFG(GPIO22, AF0)
+#define GPIO23_GPIO     MFP_CFG(GPIO23, AF0)
+#define GPIO24_GPIO     MFP_CFG(GPIO24, AF0)
+#define GPIO25_GPIO     MFP_CFG(GPIO25, AF0)
+#define GPIO26_GPIO     MFP_CFG(GPIO26, AF0)
+#define GPIO27_GPIO     MFP_CFG(GPIO27, AF0)
+#define GPIO28_GPIO     MFP_CFG(GPIO28, AF0)
+#define GPIO29_GPIO     MFP_CFG(GPIO29, AF0)
+#define GPIO30_GPIO     MFP_CFG(GPIO30, AF0)
+#define GPIO31_GPIO     MFP_CFG(GPIO31, AF0)
+#define GPIO32_GPIO     MFP_CFG(GPIO32, AF0)
+#define GPIO33_GPIO     MFP_CFG(GPIO33, AF0)
+#define GPIO34_GPIO     MFP_CFG(GPIO34, AF0)
+#define GPIO35_GPIO     MFP_CFG(GPIO35, AF0)
+#define GPIO36_GPIO     MFP_CFG(GPIO36, AF0)
+#define GPIO37_GPIO     MFP_CFG(GPIO37, AF0)
+#define GPIO38_GPIO     MFP_CFG(GPIO38, AF0)
+#define GPIO39_GPIO     MFP_CFG(GPIO39, AF0)
+#define GPIO40_GPIO     MFP_CFG(GPIO40, AF0)
+#define GPIO41_GPIO     MFP_CFG(GPIO41, AF0)
+#define GPIO42_GPIO     MFP_CFG(GPIO42, AF0)
+#define GPIO43_GPIO     MFP_CFG(GPIO43, AF0)
+#define GPIO44_GPIO     MFP_CFG(GPIO44, AF0)
+#define GPIO45_GPIO     MFP_CFG(GPIO45, AF0)
+#define GPIO46_GPIO     MFP_CFG(GPIO46, AF0)
+#define GPIO47_GPIO     MFP_CFG(GPIO47, AF0)
+#define GPIO48_GPIO     MFP_CFG(GPIO48, AF0)
+#define GPIO49_GPIO     MFP_CFG(GPIO49, AF0)
+#define GPIO50_GPIO     MFP_CFG(GPIO50, AF0)
+#define GPIO51_GPIO     MFP_CFG(GPIO51, AF0)
+#define GPIO52_GPIO     MFP_CFG(GPIO52, AF0)
+#define GPIO53_GPIO     MFP_CFG(GPIO53, AF0)
+#define GPIO54_GPIO     MFP_CFG(GPIO54, AF0)
+#define GPIO55_GPIO     MFP_CFG(GPIO55, AF0)
+#define GPIO56_GPIO     MFP_CFG(GPIO56, AF0)
+#define GPIO57_GPIO     MFP_CFG(GPIO57, AF0)
+#define GPIO58_GPIO     MFP_CFG(GPIO58, AF0)
+#define GPIO59_GPIO     MFP_CFG(GPIO59, AF0)
+#define GPIO60_GPIO     MFP_CFG(GPIO60, AF0)
+#define GPIO61_GPIO     MFP_CFG(GPIO61, AF0)
+#define GPIO62_GPIO     MFP_CFG(GPIO62, AF0)
+#define GPIO63_GPIO     MFP_CFG(GPIO63, AF0)
+#define GPIO64_GPIO     MFP_CFG(GPIO64, AF0)
+#define GPIO65_GPIO     MFP_CFG(GPIO65, AF0)
+#define GPIO66_GPIO     MFP_CFG(GPIO66, AF0)
+#define GPIO67_GPIO     MFP_CFG(GPIO67, AF0)
+#define GPIO68_GPIO     MFP_CFG(GPIO68, AF0)
+#define GPIO69_GPIO     MFP_CFG(GPIO69, AF0)
+#define GPIO70_GPIO     MFP_CFG(GPIO70, AF0)
+#define GPIO71_GPIO     MFP_CFG(GPIO71, AF0)
+#define GPIO72_GPIO     MFP_CFG(GPIO72, AF0)
+#define GPIO73_GPIO     MFP_CFG(GPIO73, AF0)
+#define GPIO74_GPIO     MFP_CFG(GPIO74, AF0)
+#define GPIO75_GPIO     MFP_CFG(GPIO75, AF0)
+#define GPIO76_GPIO     MFP_CFG(GPIO76, AF0)
+#define GPIO77_GPIO     MFP_CFG(GPIO77, AF0)
+#define GPIO78_GPIO     MFP_CFG(GPIO78, AF0)
+#define GPIO79_GPIO     MFP_CFG(GPIO79, AF0)
+#define GPIO80_GPIO     MFP_CFG(GPIO80, AF0)
+#define GPIO81_GPIO     MFP_CFG(GPIO81, AF0)
+#define GPIO82_GPIO     MFP_CFG(GPIO82, AF0)
+#define GPIO83_GPIO     MFP_CFG(GPIO83, AF0)
+#define GPIO84_GPIO     MFP_CFG(GPIO84, AF0)
+#define GPIO85_GPIO     MFP_CFG(GPIO85, AF0)
+#define GPIO86_GPIO     MFP_CFG(GPIO86, AF0)
+#define GPIO87_GPIO     MFP_CFG(GPIO87, AF0)
+#define GPIO88_GPIO     MFP_CFG(GPIO88, AF0)
+#define GPIO89_GPIO     MFP_CFG(GPIO89, AF0)
+#define GPIO90_GPIO     MFP_CFG(GPIO90, AF0)
+#define GPIO91_GPIO     MFP_CFG(GPIO91, AF0)
+#define GPIO92_GPIO     MFP_CFG(GPIO92, AF0)
+#define GPIO93_GPIO     MFP_CFG(GPIO93, AF0)
+#define GPIO94_GPIO     MFP_CFG(GPIO94, AF0)
+#define GPIO95_GPIO     MFP_CFG(GPIO95, AF0)
+#define GPIO96_GPIO     MFP_CFG(GPIO96, AF0)
+#define GPIO97_GPIO     MFP_CFG(GPIO97, AF0)
+#define GPIO98_GPIO     MFP_CFG(GPIO98, AF0)
+#define GPIO99_GPIO     MFP_CFG(GPIO99, AF0)
+#define GPIO100_GPIO    MFP_CFG(GPIO100, AF0)
+#define GPIO101_GPIO    MFP_CFG(GPIO101, AF0)
+#define GPIO102_GPIO    MFP_CFG(GPIO102, AF1)
+#define GPIO103_GPIO    MFP_CFG(GPIO103, AF1)
+#define GPIO104_GPIO    MFP_CFG(GPIO104, AF1)
+#define GPIO105_GPIO    MFP_CFG(GPIO105, AF1)
+#define GPIO106_GPIO    MFP_CFG(GPIO106, AF1)
+#define GPIO107_GPIO    MFP_CFG(GPIO107, AF1)
+#define GPIO108_GPIO    MFP_CFG(GPIO108, AF1)
+#define GPIO109_GPIO    MFP_CFG(GPIO109, AF1)
+#define GPIO110_GPIO    MFP_CFG(GPIO110, AF1)
+#define GPIO111_GPIO    MFP_CFG(GPIO111, AF1)
+#define GPIO112_GPIO    MFP_CFG(GPIO112, AF1)
+#define GPIO113_GPIO    MFP_CFG(GPIO113, AF1)
+#define GPIO114_GPIO    MFP_CFG(GPIO114, AF0)
+#define GPIO115_GPIO    MFP_CFG(GPIO115, AF0)
+#define GPIO116_GPIO    MFP_CFG(GPIO116, AF0)
+#define GPIO117_GPIO    MFP_CFG(GPIO117, AF0)
+#define GPIO118_GPIO    MFP_CFG(GPIO118, AF0)
+#define GPIO119_GPIO    MFP_CFG(GPIO119, AF0)
+#define GPIO120_GPIO    MFP_CFG(GPIO120, AF0)
+#define GPIO121_GPIO    MFP_CFG(GPIO121, AF0)
+#define GPIO122_GPIO    MFP_CFG(GPIO122, AF0)
+#define GPIO123_GPIO    MFP_CFG(GPIO123, AF0)
+#define GPIO124_GPIO    MFP_CFG(GPIO124, AF0)
+#define GPIO125_GPIO    MFP_CFG(GPIO125, AF0)
+#define GPIO126_GPIO    MFP_CFG(GPIO126, AF0)
+#define GPIO127_GPIO    MFP_CFG(GPIO127, AF0)
+#define GPIO128_GPIO    MFP_CFG(GPIO128, AF0)
+#define GPIO129_GPIO    MFP_CFG(GPIO129, AF0)
+#define GPIO130_GPIO    MFP_CFG(GPIO130, AF0)
+#define GPIO131_GPIO    MFP_CFG(GPIO131, AF0)
+#define GPIO132_GPIO    MFP_CFG(GPIO132, AF0)
+#define GPIO133_GPIO    MFP_CFG(GPIO133, AF0)
+#define GPIO134_GPIO    MFP_CFG(GPIO134, AF0)
+#define GPIO135_GPIO    MFP_CFG(GPIO135, AF0)
+#define GPIO136_GPIO    MFP_CFG(GPIO136, AF0)
+#define GPIO137_GPIO    MFP_CFG(GPIO137, AF0)
+#define GPIO138_GPIO    MFP_CFG(GPIO138, AF0)
+#define GPIO139_GPIO    MFP_CFG(GPIO139, AF0)
+#define GPIO140_GPIO    MFP_CFG(GPIO140, AF0)
+#define GPIO141_GPIO    MFP_CFG(GPIO141, AF0)
+#define GPIO142_GPIO    MFP_CFG(GPIO142, AF1)
+#define GPIO143_GPIO    MFP_CFG(GPIO143, AF1)
+#define GPIO144_GPIO    MFP_CFG(GPIO144, AF1)
+#define GPIO145_GPIO    MFP_CFG(GPIO145, AF1)
+#define GPIO146_GPIO    MFP_CFG(GPIO146, AF1)
+#define GPIO147_GPIO    MFP_CFG(GPIO147, AF1)
+#define GPIO148_GPIO    MFP_CFG(GPIO148, AF1)
+#define GPIO149_GPIO    MFP_CFG(GPIO149, AF1)
+#define GPIO150_GPIO    MFP_CFG(GPIO150, AF1)
+#define GPIO151_GPIO    MFP_CFG(GPIO151, AF1)
+#define GPIO152_GPIO    MFP_CFG(GPIO152, AF1)
+#define GPIO153_GPIO    MFP_CFG(GPIO153, AF1)
+#define GPIO154_GPIO    MFP_CFG(GPIO154, AF1)
+#define GPIO155_GPIO    MFP_CFG(GPIO155, AF1)
+#define GPIO156_GPIO    MFP_CFG(GPIO156, AF1)
+#define GPIO157_GPIO    MFP_CFG(GPIO157, AF1)
+#define GPIO158_GPIO    MFP_CFG(GPIO158, AF1)
+#define GPIO159_GPIO    MFP_CFG(GPIO159, AF1)
+#define GPIO160_GPIO    MFP_CFG(GPIO160, AF1)
+#define GPIO161_GPIO    MFP_CFG(GPIO161, AF1)
+#define GPIO162_GPIO    MFP_CFG(GPIO162, AF1)
+#define GPIO163_GPIO    MFP_CFG(GPIO163, AF1)
+#define GPIO164_GPIO    MFP_CFG(GPIO164, AF1)
+#define GPIO165_GPIO    MFP_CFG(GPIO165, AF1)
+#define GPIO166_GPIO    MFP_CFG(GPIO166, AF1)
+#define GPIO167_GPIO    MFP_CFG(GPIO167, AF1)
+#define GPIO168_GPIO    MFP_CFG(GPIO168, AF1)
 
 /* DFI */
 #define GPIO108_DFI_D15         MFP_CFG(GPIO108, AF0)
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h b/arch/arm/mach-mmp/include/mach/mmp2.h
index dbba6e8a60c4..4aec493640b4 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -1,6 +1,8 @@
 #ifndef __ASM_MACH_MMP2_H
 #define __ASM_MACH_MMP2_H
 
+#include <plat/sdhci.h>
+
 struct sys_timer;
 
 extern struct sys_timer mmp2_timer;
@@ -22,6 +24,10 @@ extern struct pxa_device_desc mmp2_device_twsi3;
 extern struct pxa_device_desc mmp2_device_twsi4;
 extern struct pxa_device_desc mmp2_device_twsi5;
 extern struct pxa_device_desc mmp2_device_twsi6;
+extern struct pxa_device_desc mmp2_device_sdh0;
+extern struct pxa_device_desc mmp2_device_sdh1;
+extern struct pxa_device_desc mmp2_device_sdh2;
+extern struct pxa_device_desc mmp2_device_sdh3;
 
 static inline int mmp2_add_uart(int id)
 {
@@ -63,5 +69,21 @@ static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data,
         return pxa_register_device(d, data, sizeof(*data));
 }
 
+static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data)
+{
+        struct pxa_device_desc *d = NULL;
+
+        switch (id) {
+        case 0: d = &mmp2_device_sdh0; break;
+        case 1: d = &mmp2_device_sdh1; break;
+        case 2: d = &mmp2_device_sdh2; break;
+        case 3: d = &mmp2_device_sdh3; break;
+        default:
+                return -EINVAL;
+        }
+
+        return pxa_register_device(d, data, sizeof(*data));
+}
+
 #endif /* __ASM_MACH_MMP2_H */
 
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index ac4702357a6e..f7011ef70bf5 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -27,6 +27,8 @@
 #define APMU_DMA        APMU_REG(0x064)
 #define APMU_GEU        APMU_REG(0x068)
 #define APMU_BUS        APMU_REG(0x06c)
+#define APMU_SDH2       APMU_REG(0x0e8)
+#define APMU_SDH3       APMU_REG(0x0ec)
 
 #define APMU_FNCLK_EN   (1 << 4)
 #define APMU_AXICLK_EN  (1 << 3)
diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index 2a684fa50773..24172a0aad59 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -67,6 +67,36 @@ static unsigned long jasper_pin_config[] __initdata = {
 
         /* PMIC */
         PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
+
+        /* MMC1 */
+        GPIO131_MMC1_DAT3,
+        GPIO132_MMC1_DAT2,
+        GPIO133_MMC1_DAT1,
+        GPIO134_MMC1_DAT0,
+        GPIO136_MMC1_CMD,
+        GPIO139_MMC1_CLK,
+        GPIO140_MMC1_CD,
+        GPIO141_MMC1_WP,
+
+        /* MMC2 */
+        GPIO37_MMC2_DAT3,
+        GPIO38_MMC2_DAT2,
+        GPIO39_MMC2_DAT1,
+        GPIO40_MMC2_DAT0,
+        GPIO41_MMC2_CMD,
+        GPIO42_MMC2_CLK,
+
+        /* MMC3 */
+        GPIO165_MMC3_DAT7,
+        GPIO162_MMC3_DAT6,
+        GPIO166_MMC3_DAT5,
+        GPIO163_MMC3_DAT4,
+        GPIO167_MMC3_DAT3,
+        GPIO164_MMC3_DAT2,
+        GPIO168_MMC3_DAT1,
+        GPIO111_MMC3_DAT0,
+        GPIO112_MMC3_CMD,
+        GPIO151_MMC3_CLK,
 };
 
 static struct regulator_consumer_supply max8649_supply[] = {
@@ -123,6 +153,10 @@ static struct i2c_board_info jasper_twsi1_info[] = {
         },
 };
 
+static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = {
+        .max_speed      = 25000000,
+};
+
 static void __init jasper_init(void)
 {
         mfp_config(ARRAY_AND_SIZE(jasper_pin_config));
@@ -131,6 +165,7 @@ static void __init jasper_init(void)
         mmp2_add_uart(1);
         mmp2_add_uart(3);
         mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));
+        mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */
 
         regulator_has_full_constraints();
 }
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index daf3993349f8..8e6c3ac7f7c1 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -115,6 +115,29 @@ void __init mmp2_init_irq(void)
         mmp2_init_gpio();
 }
 
+static void sdhc_clk_enable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst |= clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+        uint32_t clk_rst;
+
+        clk_rst  =  __raw_readl(clk->clk_rst);
+        clk_rst &= ~clk->enable_val;
+        __raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+        .enable         = sdhc_clk_enable,
+        .disable        = sdhc_clk_disable,
+};
+
 /* APB peripheral clocks */
 static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
 static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
@@ -126,9 +149,12 @@ static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
 static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
 static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
 static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(rtc, MMP2_RTC, 0, 32768);
 
 static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
 
 static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
@@ -142,6 +168,10 @@ static struct clk_lookup mmp2_clkregs[] = {
         INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
         INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_sdh0, "sdhci-pxa.0", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh1, "sdhci-pxa.1", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh2, "sdhci-pxa.2", "PXA-SDHCLK"),
+        INIT_CLKREG(&clk_sdh3, "sdhci-pxa.3", "PXA-SDHCLK"),
 };
 
 static int __init mmp2_init(void)
@@ -192,4 +222,8 @@ MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70);
 MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70);
 MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70);
 MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29);
+MMP2_DEVICE(sdh0, "sdhci-pxa", 0, MMC, 0xd4280000, 0x120);
+MMP2_DEVICE(sdh1, "sdhci-pxa", 1, MMC2, 0xd4280800, 0x120);
+MMP2_DEVICE(sdh2, "sdhci-pxa", 2, MMC3, 0xd4281000, 0x120);
+MMP2_DEVICE(sdh3, "sdhci-pxa", 3, MMC4, 0xd4281800, 0x120);
 
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69bef3c..8f92ccd26edf 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -111,6 +111,7 @@ static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
 
 static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
 
 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
@@ -123,6 +124,7 @@ static struct clk_lookup pxa910_clkregs[] = {
         INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
         INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
         INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+        INIT_CLKREG(&clk_u2o, "pxa-u2o", "U2OCLK"),
 };
 
 static int __init pxa910_init(void)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index dbbcfeb919db..31e5fd63ec9a 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -49,6 +49,8 @@ endchoice
 
 config MSM_SOC_REV_A
         bool
+config  ARCH_MSM_SCORPIONMP
+        bool
 
 config  ARCH_MSM_ARM11
         bool
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 788bdace1304..3eff39921d4d 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -65,7 +65,7 @@
  */
 #define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
 #define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1700)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
 
 #define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 86c9b2102952..9db9203667df 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -216,7 +216,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {
                 .name           = "wl1271",
                 .mmc            = 3,
-                .caps           = MMC_CAP_4_BIT_DATA,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
                 .gpio_wp        = -EINVAL,
                 .gpio_cd        = -EINVAL,
                 .nonremovable   = true,
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 40562ddd3ee4..a1939b1e6f82 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -297,7 +297,7 @@ static int __init _omap2_init_reprogram_sdrc(void)
                 return 0;
 
         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
-        if (!dpll3_m2_ck)
+        if (IS_ERR(dpll3_m2_ck))
                 return -EINVAL;
 
         rate = clk_get_rate(dpll3_m2_ck);
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 5e81517a7af2..a8afb610c7d8 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -161,6 +161,23 @@ void omap2_pm_dump(int mode, int resume, unsigned int us)
                 printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
 }
 
+void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
+{
+        u32 tick_rate, cycles;
+
+        if (!seconds && !milliseconds)
+                return;
+
+        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
+        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
+        omap_dm_timer_stop(gptimer_wakeup);
+        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
+
+        pr_info("PM: Resume timer in %u.%03u secs"
+                " (%d ticks at %d ticks/sec.)\n",
+                seconds, milliseconds, cycles, tick_rate);
+}
+
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
@@ -354,23 +371,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev)
         pwrdm->timer = t;
 }
 
-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
-        u32 tick_rate, cycles;
-
-        if (!seconds && !milliseconds)
-                return;
-
-        tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
-        cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
-        omap_dm_timer_stop(gptimer_wakeup);
-        omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
-        pr_info("PM: Resume timer in %u.%03u secs"
-                " (%d ticks at %d ticks/sec.)\n",
-                seconds, milliseconds, cycles, tick_rate);
-}
-
 static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user)
 {
         struct seq_file *s = (struct seq_file *)user;
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index c85923e56b85..aaeea49b9bdd 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,19 @@
 #include <plat/powerdomain.h>
 #include <plat/clockdomain.h>
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
+
 static void (*omap2_sram_idle)(void);
 static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
                                   void __iomem *sdrc_power);
@@ -120,8 +133,9 @@ static void omap2_enter_full_retention(void)
                 goto no_sleep;
 
         /* Block console output in case it is on one of the OMAP UARTs */
-        if (try_acquire_console_sem())
-                goto no_sleep;
+        if (!is_suspending())
+                if (try_acquire_console_sem())
+                        goto no_sleep;
 
         omap_uart_prepare_idle(0);
         omap_uart_prepare_idle(1);
@@ -136,7 +150,8 @@ static void omap2_enter_full_retention(void)
         omap_uart_resume_idle(1);
         omap_uart_resume_idle(0);
 
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 
 no_sleep:
         if (omap2_pm_debug) {
@@ -284,6 +299,12 @@ out:
         local_irq_enable();
 }
 
+static int omap2_pm_begin(suspend_state_t state)
+{
+        suspend_state = state;
+        return 0;
+}
+
 static int omap2_pm_prepare(void)
 {
         /* We cannot sleep in idle until we have resumed */
@@ -333,10 +354,17 @@ static void omap2_pm_finish(void)
         enable_hlt();
 }
 
+static void omap2_pm_end(void)
+{
+        suspend_state = PM_SUSPEND_ON;
+}
+
 static struct platform_suspend_ops omap_pm_ops = {
+        .begin          = omap2_pm_begin,
         .prepare        = omap2_pm_prepare,
         .enter          = omap2_pm_enter,
         .finish         = omap2_pm_finish,
+        .end            = omap2_pm_end,
         .valid          = suspend_valid_only_mem,
 };
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 0ec8a04b7473..648b8c50d024 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,6 +50,19 @@
 #include "sdrc.h"
 #include "control.h"
 
+#ifdef CONFIG_SUSPEND
+static suspend_state_t suspend_state = PM_SUSPEND_ON;
+static inline bool is_suspending(void)
+{
+        return (suspend_state != PM_SUSPEND_ON);
+}
+#else
+static inline bool is_suspending(void)
+{
+        return false;
+}
+#endif
+
 /* Scratchpad offsets */
 #define OMAP343X_TABLE_ADDRESS_OFFSET      0xc4
 #define OMAP343X_TABLE_VALUE_OFFSET        0xc0
@@ -387,10 +400,11 @@ void omap_sram_idle(void)
         }
 
         /* Block console output in case it is on one of the OMAP UARTs */
-        if (per_next_state < PWRDM_POWER_ON ||
-            core_next_state < PWRDM_POWER_ON)
-                if (try_acquire_console_sem())
-                        goto console_still_active;
+        if (!is_suspending())
+                if (per_next_state < PWRDM_POWER_ON ||
+                    core_next_state < PWRDM_POWER_ON)
+                        if (try_acquire_console_sem())
+                                goto console_still_active;
 
         /* PER */
         if (per_next_state < PWRDM_POWER_ON) {
@@ -470,7 +484,8 @@ void omap_sram_idle(void)
                 omap_uart_resume_idle(3);
         }
 
-        release_console_sem();
+        if (!is_suspending())
+                release_console_sem();
 
 console_still_active:
         /* Disable IO-PAD and IO-CHAIN wakeup */
@@ -514,8 +529,6 @@ out:
 }
 
 #ifdef CONFIG_SUSPEND
-static suspend_state_t suspend_state;
-
 static int omap3_pm_prepare(void)
 {
         disable_hlt();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 298a22a754e2..f81acee4738d 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -243,13 +243,14 @@
 #define OMAP24XX_EN_GPT1_MASK                           (1 << 0)
 
 /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */
-#define OMAP24XX_ST_GPIOS_SHIFT                         (1 << 2)
-#define OMAP24XX_ST_GPIOS_MASK                          2
-#define OMAP24XX_ST_GPT1_SHIFT                          (1 << 0)
-#define OMAP24XX_ST_GPT1_MASK                           0
+#define OMAP24XX_ST_GPIOS_SHIFT                         2
+#define OMAP24XX_ST_GPIOS_MASK                          (1 << 2)
+#define OMAP24XX_ST_GPT1_SHIFT                          0
+#define OMAP24XX_ST_GPT1_MASK                           (1 << 0)
 
 /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */
-#define OMAP2430_ST_MDM_SHIFT                           (1 << 0)
+#define OMAP2430_ST_MDM_SHIFT                           0
+#define OMAP2430_ST_MDM_MASK                            (1 << 0)
 
 
 /* 3430 register bits shared between CM & PRM registers */
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index c897e03e413d..6604fc6ca58a 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -51,6 +51,13 @@ config MACH_LINKSTATION_PRO
           Buffalo Linkstation Pro/Live platform. Both v1 and
           v2 devices are supported.
 
+config MACH_LINKSTATION_LSCHL
+        bool "Buffalo Linkstation Live v3 (LS-CHL)"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          Buffalo Linkstation Live v3 (LS-CHL) platform.
+
 config MACH_LINKSTATION_MINI
         bool "Buffalo Linkstation Mini"
         select I2C_BOARDINFO
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index eb6eabcb41e4..7f18cdacd487 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_WNR854T)	+= wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
 obj-$(CONFIG_MACH_RD88F6183AP_GE)       += rd88f6183ap-ge-setup.o
+obj-$(CONFIG_MACH_LINKSTATION_LSCHL)    += ls-chl-setup.o
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
new file mode 100644
index 000000000000..20a9b66cbafa
--- /dev/null
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -0,0 +1,327 @@
+/*
+ * arch/arm/mach-orion5x/ls-chl-setup.c
+ *
+ * Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/gpio-fan.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/system.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+
+/*****************************************************************************
+ * Linkstation LS-CHL Info
+ ****************************************************************************/
+
+/*
+ * 256K NOR flash Device bus boot chip select
+ */
+
+#define LSCHL_NOR_BOOT_BASE     0xf4000000
+#define LSCHL_NOR_BOOT_SIZE     SZ_256K
+
+/*****************************************************************************
+ * 256KB NOR Flash on BOOT Device
+ ****************************************************************************/
+
+static struct physmap_flash_data lschl_nor_flash_data = {
+        .width = 1,
+};
+
+static struct resource lschl_nor_flash_resource = {
+        .flags  = IORESOURCE_MEM,
+        .start  = LSCHL_NOR_BOOT_BASE,
+        .end    = LSCHL_NOR_BOOT_BASE + LSCHL_NOR_BOOT_SIZE - 1,
+};
+
+static struct platform_device lschl_nor_flash = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data  = &lschl_nor_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &lschl_nor_flash_resource,
+};
+
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+
+static struct mv643xx_eth_platform_data lschl_eth_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR(8),
+};
+
+/*****************************************************************************
+ * RTC 5C372a on I2C bus
+ ****************************************************************************/
+
+static struct i2c_board_info __initdata lschl_i2c_rtc = {
+        I2C_BOARD_INFO("rs5c372a", 0x32),
+};
+
+/*****************************************************************************
+ * LEDs attached to GPIO
+ ****************************************************************************/
+
+#define LSCHL_GPIO_LED_ALARM    2
+#define LSCHL_GPIO_LED_INFO     3
+#define LSCHL_GPIO_LED_FUNC     17
+#define LSCHL_GPIO_LED_PWR      0
+
+static struct gpio_led lschl_led_pins[] = {
+        {
+                .name = "alarm:red",
+                .gpio = LSCHL_GPIO_LED_ALARM,
+                .active_low = 1,
+        }, {
+                .name = "info:amber",
+                .gpio = LSCHL_GPIO_LED_INFO,
+                .active_low = 1,
+        }, {
+                .name = "func:blue:top",
+                .gpio = LSCHL_GPIO_LED_FUNC,
+                .active_low = 1,
+        }, {
+                .name = "power:blue:bottom",
+                .gpio = LSCHL_GPIO_LED_PWR,
+        },
+};
+
+static struct gpio_led_platform_data lschl_led_data = {
+        .leds = lschl_led_pins,
+        .num_leds = ARRAY_SIZE(lschl_led_pins),
+};
+
+static struct platform_device lschl_leds = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &lschl_led_data,
+        },
+};
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data lschl_sata_data = {
+        .n_ports = 2,
+};
+
+/*****************************************************************************
+ * LS-CHL specific power off method: reboot
+ ****************************************************************************/
+/*
+ * On the LS-CHL, the shutdown process is following:
+ * - Userland monitors key events until the power switch goes to off position
+ * - The board reboots
+ * - U-boot starts and goes into an idle mode waiting for the user
+ *   to move the switch to ON position
+ *
+ */
+
+static void lschl_power_off(void)
+{
+        arm_machine_restart('h', NULL);
+}
+
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+#define LSCHL_GPIO_USB_POWER    9
+#define LSCHL_GPIO_AUTO_POWER   17
+#define LSCHL_GPIO_POWER        18
+
+/****************************************************************************
+ * GPIO Attached Keys
+ ****************************************************************************/
+#define LSCHL_GPIO_KEY_FUNC             15
+#define LSCHL_GPIO_KEY_POWER            8
+#define LSCHL_GPIO_KEY_AUTOPOWER        10
+#define LSCHL_SW_POWER          0x00
+#define LSCHL_SW_AUTOPOWER      0x01
+#define LSCHL_SW_FUNC           0x02
+
+static struct gpio_keys_button lschl_buttons[] = {
+        {
+                .type = EV_SW,
+                .code = LSCHL_SW_POWER,
+                .gpio = LSCHL_GPIO_KEY_POWER,
+                .desc = "Power-on Switch",
+                .active_low = 1,
+        }, {
+                .type = EV_SW,
+                .code = LSCHL_SW_AUTOPOWER,
+                .gpio = LSCHL_GPIO_KEY_AUTOPOWER,
+                .desc = "Power-auto Switch",
+                .active_low = 1,
+        }, {
+                .type = EV_SW,
+                .code = LSCHL_SW_FUNC,
+                .gpio = LSCHL_GPIO_KEY_FUNC,
+                .desc = "Function Switch",
+                .active_low = 1,
+        },
+};
+
+static struct gpio_keys_platform_data lschl_button_data = {
+        .buttons = lschl_buttons,
+        .nbuttons = ARRAY_SIZE(lschl_buttons),
+};
+
+static struct platform_device lschl_button_device = {
+        .name = "gpio-keys",
+        .id = -1,
+        .num_resources = 0,
+        .dev = {
+                .platform_data = &lschl_button_data,
+        },
+};
+
+#define LSCHL_GPIO_HDD_POWER    1
+
+/****************************************************************************
+ * GPIO Fan
+ ****************************************************************************/
+
+#define LSCHL_GPIO_FAN_LOW      16
+#define LSCHL_GPIO_FAN_HIGH     14
+#define LSCHL_GPIO_FAN_LOCK     6
+
+static struct gpio_fan_alarm lschl_alarm = {
+        .gpio = LSCHL_GPIO_FAN_LOCK,
+};
+
+static struct gpio_fan_speed lschl_speeds[] = {
+        {
+                .rpm = 0,
+                .ctrl_val = 3,
+        }, {
+                .rpm = 1500,
+                .ctrl_val = 2,
+        }, {
+                .rpm = 3250,
+                .ctrl_val = 1,
+        }, {
+                .rpm = 5000,
+                .ctrl_val = 0,
+        },
+};
+
+static int lschl_gpio_list[] = {
+        LSCHL_GPIO_FAN_HIGH, LSCHL_GPIO_FAN_LOW,
+};
+
+static struct gpio_fan_platform_data lschl_fan_data = {
+        .num_ctrl = ARRAY_SIZE(lschl_gpio_list),
+        .ctrl = lschl_gpio_list,
+        .alarm = &lschl_alarm,
+        .num_speed = ARRAY_SIZE(lschl_speeds),
+        .speed = lschl_speeds,
+};
+
+static struct platform_device lschl_fan_device = {
+        .name = "gpio-fan",
+        .id = -1,
+        .num_resources = 0,
+        .dev = {
+                .platform_data = &lschl_fan_data,
+        },
+};
+
+/****************************************************************************
+ * GPIO Data
+ ****************************************************************************/
+
+static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO }, /* LED POWER */
+        {  1, MPP_GPIO }, /* HDD POWER */
+        {  2, MPP_GPIO }, /* LED ALARM */
+        {  3, MPP_GPIO }, /* LED INFO */
+        {  4, MPP_UNUSED },
+        {  5, MPP_UNUSED },
+        {  6, MPP_GPIO }, /* FAN LOCK */
+        {  7, MPP_GPIO }, /* SW INIT */
+        {  8, MPP_GPIO }, /* SW POWER */
+        {  9, MPP_GPIO }, /* USB POWER */
+        { 10, MPP_GPIO }, /* SW AUTO POWER */
+        { 11, MPP_UNUSED },
+        { 12, MPP_UNUSED },
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO }, /* FAN HIGH */
+        { 15, MPP_GPIO }, /* SW FUNC */
+        { 16, MPP_GPIO }, /* FAN LOW */
+        { 17, MPP_GPIO }, /* LED FUNC */
+        { 18, MPP_UNUSED },
+        { 19, MPP_UNUSED },
+        { -1 },
+};
+
+static void __init lschl_init(void)
+{
+        /*
+         * Setup basic Orion functions. Needs to be called early.
+         */
+        orion5x_init();
+
+        orion5x_mpp_conf(lschl_mpp_modes);
+
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&lschl_eth_data);
+        orion5x_i2c_init();
+        orion5x_sata_init(&lschl_sata_data);
+        orion5x_uart0_init();
+        orion5x_xor_init();
+
+        orion5x_setup_dev_boot_win(LSCHL_NOR_BOOT_BASE,
+                                   LSCHL_NOR_BOOT_SIZE);
+        platform_device_register(&lschl_nor_flash);
+
+        platform_device_register(&lschl_leds);
+
+        platform_device_register(&lschl_button_device);
+
+        platform_device_register(&lschl_fan_device);
+
+        i2c_register_board_info(0, &lschl_i2c_rtc, 1);
+
+        /* usb power on */
+        gpio_set_value(LSCHL_GPIO_USB_POWER, 1);
+
+        /* register power-off method */
+        pm_power_off = lschl_power_off;
+
+        pr_info("%s: finished\n", __func__);
+}
+
+MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
+        /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
+        .boot_params    = 0x00000100,
+        .init_machine   = lschl_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index dd235ecc9d6c..1df6db6a136e 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -50,6 +50,10 @@ config MACH_SAAR
         select PXA3xx
         select CPU_PXA930
 
+config MACH_SAARB
+        bool "PXA955 Handheld Platform (aka SAARB)"
+        select CPU_PXA955
+
 comment "Third Party Dev Platforms (sorted by vendor name)"
 
 config ARCH_PXA_IDP
@@ -232,10 +236,6 @@ config MACH_COLIBRI
         bool "Toradex Colibri PXA270"
         select PXA27x
 
-config MACH_COLIBRI_PXA270_EVALBOARD
-        bool "Toradex Colibri Evaluation Carrier Board support (PXA270)"
-        depends on MACH_COLIBRI
-
 config MACH_COLIBRI_PXA270_INCOME
         bool "Income s.r.o. PXA270 SBC"
         depends on MACH_COLIBRI
@@ -253,6 +253,10 @@ config MACH_COLIBRI320
         select PXA3xx
         select CPU_PXA320
 
+config MACH_COLIBRI_EVALBOARD
+        bool "Toradex Colibri Evaluation Carrier Board support"
+        depends on MACH_COLIBRI || MACH_COLIBRI300 || MACH_COLIBRI320
+
 config MACH_VPAC270
         bool "Voipac PXA270"
         select PXA27x
@@ -651,11 +655,17 @@ config CPU_PXA935
         help
           PXA935 (codename Tavor-P65)
 
-config CPU_PXA950
+config PXA95x
         bool
-        select CPU_PXA930
+        select CPU_PJ4
+        help
+          Select code specific to PXA95x variants
+
+config CPU_PXA955
+        bool
+        select PXA95x
         help
-          PXA950 (codename Tavor-PV2)
+          PXA950 (codename MG1)
 
 config PXA_SHARP_C7xx
         bool
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index e2f89c2c6f49..cc39d17b2e07 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -16,9 +16,10 @@ endif
 # Generic drivers that other drivers may depend upon
 
 # SoC-specific code
-obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o pxa2xx.o pxa25x.o
-obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o pxa2xx.o pxa27x.o
-obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
+obj-$(CONFIG_PXA25x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa25x.o
+obj-$(CONFIG_PXA27x)            += mfp-pxa2xx.o clock-pxa2xx.o pxa2xx.o pxa27x.o
+obj-$(CONFIG_PXA3xx)            += mfp-pxa3xx.o clock-pxa3xx.o pxa3xx.o smemc.o pxa3xx-ulpi.o
+obj-$(CONFIG_PXA95x)            += mfp-pxa3xx.o clock-pxa3xx.o pxa95x.o smemc.o
 obj-$(CONFIG_CPU_PXA300)        += pxa300.o
 obj-$(CONFIG_CPU_PXA320)        += pxa320.o
 obj-$(CONFIG_CPU_PXA930)        += pxa930.o
@@ -34,6 +35,7 @@ obj-$(CONFIG_MACH_LITTLETON)	+= littleton.o
 obj-$(CONFIG_MACH_TAVOREVB)     += tavorevb.o
 obj-$(CONFIG_MACH_TAVOREVB3)    += tavorevb3.o
 obj-$(CONFIG_MACH_SAAR)         += saar.o
+obj-$(CONFIG_MACH_SAARB)        += saarb.o
 
 # 3rd Party Dev Platforms
 obj-$(CONFIG_ARCH_PXA_IDP)      += idp.o
@@ -60,7 +62,7 @@ obj-$(CONFIG_MACH_LOGICPD_PXA270)	+= lpd270.o
 obj-$(CONFIG_MACH_PCM027)               += pcm027.o
 obj-$(CONFIG_MACH_PCM990_BASEBOARD)     += pcm990-baseboard.o
 obj-$(CONFIG_MACH_COLIBRI)                      += colibri-pxa270.o
-obj-$(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD)     += colibri-pxa270-evalboard.o
+obj-$(CONFIG_MACH_COLIBRI_EVALBOARD)    += colibri-evalboard.o
 obj-$(CONFIG_MACH_COLIBRI_PXA270_INCOME)        += colibri-pxa270-income.o
 obj-$(CONFIG_MACH_COLIBRI300)   += colibri-pxa3xx.o colibri-pxa300.o
 obj-$(CONFIG_MACH_COLIBRI320)   += colibri-pxa3xx.o colibri-pxa320.o
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 21e188901935..ccb2d0cebcc3 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -567,27 +567,29 @@ static inline void balloon3_i2c_init(void) {}
  * NAND
  ******************************************************************************/
 #if defined(CONFIG_MTD_NAND_PLATFORM)||defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
-static uint16_t balloon3_ctl =
-        BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
-        BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
-        BALLOON3_NAND_CONTROL_FLWP;
-
 static void balloon3_nand_cmd_ctl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 {
         struct nand_chip *this = mtd->priv;
+        uint8_t balloon3_ctl_set = 0, balloon3_ctl_clr = 0;
 
         if (ctrl & NAND_CTRL_CHANGE) {
                 if (ctrl & NAND_CLE)
-                        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCLE;
+                        balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLCLE;
                 else
-                        balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLCLE;
+                        balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLCLE;
 
                 if (ctrl & NAND_ALE)
-                        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLALE;
+                        balloon3_ctl_set |= BALLOON3_NAND_CONTROL_FLALE;
                 else
-                        balloon3_ctl &= ~BALLOON3_NAND_CONTROL_FLALE;
-
-                __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+                        balloon3_ctl_clr |= BALLOON3_NAND_CONTROL_FLALE;
+
+                if (balloon3_ctl_clr)
+                        __raw_writel(balloon3_ctl_clr,
+                                BALLOON3_NAND_CONTROL_REG);
+                if (balloon3_ctl_set)
+                        __raw_writel(balloon3_ctl_set,
+                                BALLOON3_NAND_CONTROL_REG |
+                                BALLOON3_FPGA_SETnCLR);
         }
 
         if (cmd != NAND_CMD_NONE)
@@ -599,28 +601,33 @@ static void balloon3_nand_select_chip(struct mtd_info *mtd, int chip)
         if (chip < 0 || chip > 3)
                 return;
 
-        balloon3_ctl |= BALLOON3_NAND_CONTROL_FLCE0 |
-                        BALLOON3_NAND_CONTROL_FLCE1 |
-                        BALLOON3_NAND_CONTROL_FLCE2 |
-                        BALLOON3_NAND_CONTROL_FLCE3;
+        /* Assert all nCE lines */
+        __raw_writew(
+                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
+                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3,
+                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
 
         /* Deassert correct nCE line */
-        balloon3_ctl &= ~(BALLOON3_NAND_CONTROL_FLCE0 << chip);
+        __raw_writew(BALLOON3_NAND_CONTROL_FLCE0 << chip,
+                BALLOON3_NAND_CONTROL_REG);
+}
 
-        __raw_writew(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+static int balloon3_nand_dev_ready(struct mtd_info *mtd)
+{
+        return __raw_readl(BALLOON3_NAND_STAT_REG) & BALLOON3_NAND_STAT_RNB;
 }
 
 static int balloon3_nand_probe(struct platform_device *pdev)
 {
-        void __iomem *temp_map;
         uint16_t ver;
         int ret;
 
-        __raw_writew(BALLOON3_NAND_CONTROL2_16BIT, BALLOON3_NAND_CONTROL2_REG);
+        __raw_writew(BALLOON3_NAND_CONTROL2_16BIT,
+                BALLOON3_NAND_CONTROL2_REG | BALLOON3_FPGA_SETnCLR);
 
         ver = __raw_readw(BALLOON3_FPGA_VER);
-        if (ver > 0x0201)
-                pr_warn("The FPGA code, version 0x%04x, is newer than rel-0.3. "
+        if (ver < 0x4f08)
+                pr_warn("The FPGA code, version 0x%04x, is too old. "
                         "NAND support might be broken in this version!", ver);
 
         /* Power up the NAND chips */
@@ -635,7 +642,11 @@ static int balloon3_nand_probe(struct platform_device *pdev)
         gpio_set_value(BALLOON3_GPIO_RUN_NAND, 1);
 
         /* Deassert all nCE lines and write protect line */
-        __raw_writel(balloon3_ctl, BALLOON3_NAND_CONTROL_REG);
+        __raw_writel(
+                BALLOON3_NAND_CONTROL_FLCE0 | BALLOON3_NAND_CONTROL_FLCE1 |
+                BALLOON3_NAND_CONTROL_FLCE2 | BALLOON3_NAND_CONTROL_FLCE3 |
+                BALLOON3_NAND_CONTROL_FLWP,
+                BALLOON3_NAND_CONTROL_REG | BALLOON3_FPGA_SETnCLR);
         return 0;
 
 err2:
@@ -677,7 +688,7 @@ struct platform_nand_data balloon3_nand_pdata = {
         },
         .ctrl = {
                 .hwcontrol      = 0,
-                .dev_ready      = 0,
+                .dev_ready      = balloon3_nand_dev_ready,
                 .select_chip    = balloon3_nand_select_chip,
                 .cmd_ctrl       = balloon3_nand_cmd_ctl,
                 .probe          = balloon3_nand_probe,
@@ -802,7 +813,7 @@ static struct map_desc balloon3_io_desc[] __initdata = {
 
 static void __init balloon3_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(balloon3_io_desc, ARRAY_SIZE(balloon3_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 4bd7a3cda48c..4284513f396a 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -149,7 +149,7 @@ static void __init capc7117_init(void)
 MACHINE_START(CAPC7117,
               "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa3xx_map_io,
         .init_irq = pxa3xx_init_irq,
         .timer = &pxa_timer,
         .init_machine = capc7117_init
diff --git a/arch/arm/mach-pxa/clock-pxa2xx.c b/arch/arm/mach-pxa/clock-pxa2xx.c
new file mode 100644
index 000000000000..1ce090448493
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa2xx.c
@@ -0,0 +1,64 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa2xx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/sysdev.h>
+
+#include <mach/pxa2xx-regs.h>
+
+#include "clock.h"
+
+void clk_pxa2xx_cken_enable(struct clk *clk)
+{
+        CKEN |= 1 << clk->cken;
+}
+
+void clk_pxa2xx_cken_disable(struct clk *clk)
+{
+        CKEN &= ~(1 << clk->cken);
+}
+
+const struct clkops clk_pxa2xx_cken_ops = {
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
+};
+
+#ifdef CONFIG_PM
+static uint32_t saved_cken;
+
+static int pxa2xx_clock_suspend(struct sys_device *d, pm_message_t state)
+{
+        saved_cken = CKEN;
+        return 0;
+}
+
+static int pxa2xx_clock_resume(struct sys_device *d)
+{
+        CKEN = saved_cken;
+        return 0;
+}
+#else
+#define pxa2xx_clock_suspend    NULL
+#define pxa2xx_clock_resume     NULL
+#endif
+
+struct sysdev_class pxa2xx_clock_sysclass = {
+        .name           = "pxa2xx-clock",
+        .suspend        = pxa2xx_clock_suspend,
+        .resume         = pxa2xx_clock_resume,
+};
+
+static int __init pxa2xx_clock_init(void)
+{
+        if (cpu_is_pxa2xx())
+                return sysdev_class_register(&pxa2xx_clock_sysclass);
+        return 0;
+}
+postcore_initcall(pxa2xx_clock_init);
diff --git a/arch/arm/mach-pxa/clock-pxa3xx.c b/arch/arm/mach-pxa/clock-pxa3xx.c
new file mode 100644
index 000000000000..1b08a34ab234
--- /dev/null
+++ b/arch/arm/mach-pxa/clock-pxa3xx.c
@@ -0,0 +1,218 @@
+/*
+ * linux/arch/arm/mach-pxa/clock-pxa3xx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <mach/smemc.h>
+#include <mach/pxa3xx-regs.h>
+
+#include "clock.h"
+
+/* Crystal clock: 13MHz */
+#define BASE_CLK        13000000
+
+/* Ring Oscillator Clock: 60MHz */
+#define RO_CLK          60000000
+
+#define ACCR_D0CS       (1 << 26)
+#define ACCR_PCCE       (1 << 11)
+
+/* crystal frequency to HSIO bus frequency multiplier (HSS) */
+static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
+
+/*
+ * Get the clock frequency as reflected by CCSR and the turbo flag.
+ * We assume these values have been applied via a fcs.
+ * If info is not 0 we also display the current settings.
+ */
+unsigned int pxa3xx_get_clk_frequency_khz(int info)
+{
+        unsigned long acsr, xclkcfg;
+        unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
+
+        /* Read XCLKCFG register turbo bit */
+        __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
+        t = xclkcfg & 0x1;
+
+        acsr = ACSR;
+
+        xl  = acsr & 0x1f;
+        xn  = (acsr >> 8) & 0x7;
+        hss = (acsr >> 14) & 0x3;
+
+        XL = xl * BASE_CLK;
+        XN = xn * XL;
+
+        ro = acsr & ACCR_D0CS;
+
+        CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
+        HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        if (info) {
+                pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
+                        RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
+                        (ro) ? "" : "in");
+                pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
+                        XL / 1000000, (XL % 1000000) / 10000, xl);
+                pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
+                        XN / 1000000, (XN % 1000000) / 10000, xn,
+                        (t) ? "" : "in");
+                pr_info("HSIO bus clock: %d.%02dMHz\n",
+                        HSS / 1000000, (HSS % 1000000) / 10000);
+        }
+
+        return CLK / 1000;
+}
+
+/*
+ * Return the current AC97 clock frequency.
+ */
+static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
+{
+        unsigned long rate = 312000000;
+        unsigned long ac97_div;
+
+        ac97_div = AC97_DIV;
+
+        /* This may loose precision for some rates but won't for the
+         * standard 24.576MHz.
+         */
+        rate /= (ac97_div >> 12) & 0x7fff;
+        rate *= (ac97_div & 0xfff);
+
+        return rate;
+}
+
+/*
+ * Return the current HSIO bus clock frequency
+ */
+static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
+{
+        unsigned long acsr;
+        unsigned int hss, hsio_clk;
+
+        acsr = ACSR;
+
+        hss = (acsr >> 14) & 0x3;
+        hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
+
+        return hsio_clk;
+}
+
+/* crystal frequency to static memory controller multiplier (SMCFS) */
+static unsigned int smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
+static unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
+
+static unsigned long clk_pxa3xx_smemc_getrate(struct clk *clk)
+{
+        unsigned long acsr = ACSR;
+        unsigned long memclkcfg = __raw_readl(MEMCLKCFG);
+        unsigned int smcfs = (acsr >> 23) & 0x7;
+
+        return BASE_CLK * smcfs_mult[(acsr >> 23) & 0x7] /
+                        df_clkdiv[(memclkcfg >> 16) & 0x3];
+}
+
+void clk_pxa3xx_cken_enable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        if (clk->cken < 32)
+                CKENA |= mask;
+        else
+                CKENB |= mask;
+}
+
+void clk_pxa3xx_cken_disable(struct clk *clk)
+{
+        unsigned long mask = 1ul << (clk->cken & 0x1f);
+
+        if (clk->cken < 32)
+                CKENA &= ~mask;
+        else
+                CKENB &= ~mask;
+}
+
+const struct clkops clk_pxa3xx_cken_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+};
+
+const struct clkops clk_pxa3xx_hsio_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_hsio_getrate,
+};
+
+const struct clkops clk_pxa3xx_ac97_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_ac97_getrate,
+};
+
+const struct clkops clk_pxa3xx_smemc_ops = {
+        .enable         = clk_pxa3xx_cken_enable,
+        .disable        = clk_pxa3xx_cken_disable,
+        .getrate        = clk_pxa3xx_smemc_getrate,
+};
+
+static void clk_pout_enable(struct clk *clk)
+{
+        OSCC |= OSCC_PEN;
+}
+
+static void clk_pout_disable(struct clk *clk)
+{
+        OSCC &= ~OSCC_PEN;
+}
+
+const struct clkops clk_pxa3xx_pout_ops = {
+        .enable         = clk_pout_enable,
+        .disable        = clk_pout_disable,
+};
+
+#ifdef CONFIG_PM
+static uint32_t cken[2];
+static uint32_t accr;
+
+static int pxa3xx_clock_suspend(struct sys_device *d, pm_message_t state)
+{
+        cken[0] = CKENA;
+        cken[1] = CKENB;
+        accr = ACCR;
+        return 0;
+}
+
+static int pxa3xx_clock_resume(struct sys_device *d)
+{
+        ACCR = accr;
+        CKENA = cken[0];
+        CKENB = cken[1];
+        return 0;
+}
+#else
+#define pxa3xx_clock_suspend    NULL
+#define pxa3xx_clock_resume     NULL
+#endif
+
+struct sysdev_class pxa3xx_clock_sysclass = {
+        .name           = "pxa3xx-clock",
+        .suspend        = pxa3xx_clock_suspend,
+        .resume         = pxa3xx_clock_resume,
+};
+
+static int __init pxa3xx_clock_init(void)
+{
+        if (cpu_is_pxa3xx() || cpu_is_pxa95x())
+                return sysdev_class_register(&pxa3xx_clock_sysclass);
+        return 0;
+}
+postcore_initcall(pxa3xx_clock_init);
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index abba0089a2ae..8184fe2d71c3 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -3,21 +3,12 @@
  */
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
 #include <linux/clk.h>
 #include <linux/spinlock.h>
-#include <linux/platform_device.h>
 #include <linux/delay.h>
 
 #include <asm/clkdev.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/hardware.h>
 
-#include "devices.h"
-#include "generic.h"
 #include "clock.h"
 
 static DEFINE_SPINLOCK(clocks_lock);
@@ -63,18 +54,19 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
 
-
-void clk_cken_enable(struct clk *clk)
+void clk_dummy_enable(struct clk *clk)
 {
-        CKEN |= 1 << clk->cken;
 }
 
-void clk_cken_disable(struct clk *clk)
+void clk_dummy_disable(struct clk *clk)
 {
-        CKEN &= ~(1 << clk->cken);
 }
 
-const struct clkops clk_cken_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
+const struct clkops clk_dummy_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+};
+
+struct clk clk_dummy = {
+        .ops            = &clk_dummy_ops,
 };
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index d8488742b807..6e949944f2ec 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -1,3 +1,4 @@
+#include <linux/sysdev.h>
 #include <asm/clkdev.h>
 
 struct clkops {
@@ -14,6 +15,12 @@ struct clk {
         unsigned int            enabled;
 };
 
+void clk_dummy_enable(struct clk *);
+void clk_dummy_disable(struct clk *);
+
+extern const struct clkops clk_dummy_ops;
+extern struct clk clk_dummy;
+
 #define INIT_CLKREG(_clk,_devname,_conname)             \
         {                                               \
                 .clk            = _clk,                 \
@@ -21,14 +28,6 @@ struct clk {
                 .con_id         = _conname,             \
         }
 
-#define DEFINE_CKEN(_name, _cken, _rate, _delay)        \
-struct clk clk_##_name = {                              \
-                .ops    = &clk_cken_ops,                \
-                .rate   = _rate,                        \
-                .cken   = CKEN_##_cken,                 \
-                .delay  = _delay,                       \
-        }
-
 #define DEFINE_CK(_name, _cken, _ops)                   \
 struct clk clk_##_name = {                              \
                 .ops    = _ops,                         \
@@ -42,28 +41,38 @@ struct clk clk_##_name = {				\
                 .delay  = _delay,                       \
         }
 
-extern const struct clkops clk_cken_ops;
-
-void clk_cken_enable(struct clk *clk);
-void clk_cken_disable(struct clk *clk);
-
-#ifdef CONFIG_PXA3xx
-#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
+#define DEFINE_PXA2_CKEN(_name, _cken, _rate, _delay)   \
 struct clk clk_##_name = {                              \
-                .ops    = &clk_pxa3xx_cken_ops,         \
+                .ops    = &clk_pxa2xx_cken_ops,         \
                 .rate   = _rate,                        \
                 .cken   = CKEN_##_cken,                 \
                 .delay  = _delay,                       \
         }
 
-#define DEFINE_PXA3_CK(_name, _cken, _ops)              \
+extern const struct clkops clk_pxa2xx_cken_ops;
+
+void clk_pxa2xx_cken_enable(struct clk *clk);
+void clk_pxa2xx_cken_disable(struct clk *clk);
+
+extern struct sysdev_class pxa2xx_clock_sysclass;
+
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+#define DEFINE_PXA3_CKEN(_name, _cken, _rate, _delay)   \
 struct clk clk_##_name = {                              \
-                .ops    = _ops,                         \
+                .ops    = &clk_pxa3xx_cken_ops,         \
+                .rate   = _rate,                        \
                 .cken   = CKEN_##_cken,                 \
+                .delay  = _delay,                       \
         }
 
 extern const struct clkops clk_pxa3xx_cken_ops;
+extern const struct clkops clk_pxa3xx_hsio_ops;
+extern const struct clkops clk_pxa3xx_ac97_ops;
+extern const struct clkops clk_pxa3xx_pout_ops;
+extern const struct clkops clk_pxa3xx_smemc_ops;
+
 extern void clk_pxa3xx_cken_enable(struct clk *);
 extern void clk_pxa3xx_cken_disable(struct clk *);
-#endif
 
+extern struct sysdev_class pxa3xx_clock_sysclass;
+#endif
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index d34b99febeb9..b734d8468168 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -24,6 +24,7 @@
 #include <mach/pxa2xx-regs.h>
 #include <mach/audio.h>
 #include <mach/pxafb.h>
+#include <mach/smemc.h>
 
 #include <asm/hardware/it8152.h>
 
@@ -392,9 +393,9 @@ static int cmx2xx_suspend(struct sys_device *dev, pm_message_t state)
         cmx2xx_pci_suspend();
 
         /* save MSC registers */
-        sleep_save_msc[0] = MSC0;
-        sleep_save_msc[1] = MSC1;
-        sleep_save_msc[2] = MSC2;
+        sleep_save_msc[0] = __raw_readl(MSC0);
+        sleep_save_msc[1] = __raw_readl(MSC1);
+        sleep_save_msc[2] = __raw_readl(MSC2);
 
         /* setup power saving mode registers */
         PCFR = 0x0;
@@ -416,9 +417,9 @@ static int cmx2xx_resume(struct sys_device *dev)
         cmx2xx_pci_resume();
 
         /* restore MSC registers */
-        MSC0 = sleep_save_msc[0];
-        MSC1 = sleep_save_msc[1];
-        MSC2 = sleep_save_msc[2];
+        __raw_writel(sleep_save_msc[0], MSC0);
+        __raw_writel(sleep_save_msc[1], MSC1);
+        __raw_writel(sleep_save_msc[2], MSC2);
 
         return 0;
 }
@@ -498,7 +499,12 @@ static struct map_desc cmx2xx_io_desc[] __initdata = {
 
 static void __init cmx2xx_map_io(void)
 {
-        pxa_map_io();
+        if (cpu_is_pxa25x())
+                pxa25x_map_io();
+
+        if (cpu_is_pxa27x())
+                pxa27x_map_io();
+
         iotable_init(cmx2xx_io_desc, ARRAY_SIZE(cmx2xx_io_desc));
 
         it8152_base_address = CMX2XX_IT8152_VIRT;
@@ -506,7 +512,11 @@ static void __init cmx2xx_map_io(void)
 #else
 static void __init cmx2xx_map_io(void)
 {
-        pxa_map_io();
+        if (cpu_is_pxa25x())
+                pxa25x_map_io();
+
+        if (cpu_is_pxa27x())
+                pxa27x_map_io();
 }
 #endif
 
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 922b1075b9de..7984268508b6 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -857,7 +857,7 @@ static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag *tags,
 
 MACHINE_START(CM_X300, "CM-X300 module")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = cm_x300_init,
diff --git a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c b/arch/arm/mach-pxa/colibri-evalboard.c
index 0f3b632c3b14..6b2c800a1133 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-evalboard.c
+++ b/arch/arm/mach-pxa/colibri-evalboard.c
@@ -1,7 +1,7 @@
 /*
- *  linux/arch/arm/mach-pxa/colibri-pxa270-evalboard.c
+ *  linux/arch/arm/mach-pxa/colibri-evalboard.c
  *
- *  Support for Toradex PXA270 based Colibri Evaluation Carrier Board
+ *  Support for Toradex Colibri Evaluation Carrier Board
  *  Daniel Mack <daniel@caiaq.de>
  *  Marek Vasut <marek.vasut@gmail.com>
  *
@@ -19,6 +19,7 @@
 #include <asm/mach-types.h>
 #include <mach/hardware.h>
 #include <asm/mach/arch.h>
+#include <linux/i2c.h>
 
 #include <mach/pxa27x.h>
 #include <mach/colibri.h>
@@ -26,86 +27,95 @@
 #include <mach/ohci.h>
 #include <mach/pxa27x-udc.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 
 /******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-        GPIO0_GPIO,     /* SD detect */
-
-        /* FFUART */
-        GPIO39_FFUART_TXD,
-        GPIO34_FFUART_RXD,
-
-        /* UHC */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-        GPIO119_USBH2_PWR,
-        GPIO120_USBH2_PEN,
-};
-
-/******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static struct pxamci_platform_data colibri_pxa270_mci_platform_data = {
+static struct pxamci_platform_data colibri_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_power             = -1,
-        .gpio_card_detect       = GPIO0_COLIBRI_PXA270_SD_DETECT,
         .gpio_card_ro           = -1,
         .detect_delay_ms        = 200,
 };
 
-static void __init colibri_pxa270_mmc_init(void)
+static void __init colibri_mmc_init(void)
 {
-        pxa_set_mci_info(&colibri_pxa270_mci_platform_data);
+        if (machine_is_colibri())       /* PXA270 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO0_COLIBRI_PXA270_SD_DETECT;
+        if (machine_is_colibri300())    /* PXA300 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO39_COLIBRI_PXA300_SD_DETECT;
+        else                            /* PXA320 Colibri */
+                colibri_mci_platform_data.gpio_card_detect =
+                        GPIO28_COLIBRI_PXA320_SD_DETECT;
+
+        pxa_set_mci_info(&colibri_mci_platform_data);
 }
 #else
-static inline void colibri_pxa270_mmc_init(void) {}
+static inline void colibri_mmc_init(void) {}
 #endif
 
 /******************************************************************************
  * USB Host
  ******************************************************************************/
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static int colibri_pxa270_ohci_init(struct device *dev)
+static int colibri_ohci_init(struct device *dev)
 {
         UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
         return 0;
 }
 
-static struct pxaohci_platform_data colibri_pxa270_ohci_info = {
+static struct pxaohci_platform_data colibri_ohci_info = {
         .port_mode      = PMM_PERPORT_MODE,
-        .flags          = ENABLE_PORT1 | ENABLE_PORT2 |
+        .flags          = ENABLE_PORT1 |
                           POWER_CONTROL_LOW | POWER_SENSE_LOW,
-        .init           = colibri_pxa270_ohci_init,
+        .init           = colibri_ohci_init,
 };
 
-static void __init colibri_pxa270_uhc_init(void)
+static void __init colibri_uhc_init(void)
 {
-        pxa_set_ohci_info(&colibri_pxa270_ohci_info);
+        /* Colibri PXA270 has two usb ports, TBA for 320 */
+        if (machine_is_colibri())
+                colibri_ohci_info.flags |= ENABLE_PORT2;
+
+        pxa_set_ohci_info(&colibri_ohci_info);
 }
 #else
-static inline void colibri_pxa270_uhc_init(void) {}
+static inline void colibri_uhc_init(void) {}
 #endif
 
-void __init colibri_pxa270_evalboard_init(void)
+/******************************************************************************
+ * I2C RTC
+ ******************************************************************************/
+#if defined(CONFIG_RTC_DRV_DS1307) || defined(CONFIG_RTC_DRV_DS1307_MODULE)
+static struct i2c_board_info __initdata colibri_i2c_devs[] = {
+        {
+                I2C_BOARD_INFO("m41t00", 0x68),
+        },
+};
+
+static void __init colibri_rtc_init(void)
+{
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(colibri_i2c_devs));
+}
+#else
+static inline void colibri_rtc_init(void) {}
+#endif
+
+void __init colibri_evalboard_init(void)
 {
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_evalboard_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        colibri_pxa270_mmc_init();
-        colibri_pxa270_uhc_init();
+        colibri_mmc_init();
+        colibri_uhc_init();
+        colibri_rtc_init();
 }
-
diff --git a/arch/arm/mach-pxa/colibri-pxa270-income.c b/arch/arm/mach-pxa/colibri-pxa270-income.c
index 37f0f3ed7c61..07b62a096f17 100644
--- a/arch/arm/mach-pxa/colibri-pxa270-income.c
+++ b/arch/arm/mach-pxa/colibri-pxa270-income.c
@@ -46,52 +46,6 @@
 #define GPIO113_INCOME_TS_IRQ   (113)
 
 /******************************************************************************
- * Pin configuration
- ******************************************************************************/
-static mfp_cfg_t income_pin_config[] __initdata = {
-        /* MMC */
-        GPIO32_MMC_CLK,
-        GPIO92_MMC_DAT_0,
-        GPIO109_MMC_DAT_1,
-        GPIO110_MMC_DAT_2,
-        GPIO111_MMC_DAT_3,
-        GPIO112_MMC_CMD,
-        GPIO0_GPIO,     /* SD detect */
-        GPIO1_GPIO,     /* SD read-only */
-
-        /* FFUART */
-        GPIO39_FFUART_TXD,
-        GPIO34_FFUART_RXD,
-
-        /* BFUART */
-        GPIO42_BTUART_RXD,
-        GPIO43_BTUART_TXD,
-        GPIO45_BTUART_RTS,
-
-        /* STUART */
-        GPIO46_STUART_RXD,
-        GPIO47_STUART_TXD,
-
-        /* UHC */
-        GPIO88_USBH1_PWR,
-        GPIO89_USBH1_PEN,
-
-        /* LCD */
-        GPIOxx_LCD_TFT_16BPP,
-
-        /* PWM */
-        GPIO16_PWM0_OUT,
-
-        /* I2C */
-        GPIO117_I2C_SCL,
-        GPIO118_I2C_SDA,
-
-        /* LED */
-        GPIO54_GPIO,    /* LED A */
-        GPIO55_GPIO,    /* LED B */
-};
-
-/******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
 #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
@@ -257,7 +211,6 @@ static inline void income_pwm_init(void) {}
 
 void __init colibri_pxa270_income_boardinit(void)
 {
-        pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index bc045100ec15..6fc5d328ba7f 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -33,6 +33,103 @@
 #include "generic.h"
 
 /******************************************************************************
+ * Evaluation board MFP
+ ******************************************************************************/
+#ifdef   CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO0_GPIO,     /* SD detect */
+
+        /* FFUART */
+        GPIO39_FFUART_TXD,
+        GPIO34_FFUART_RXD,
+
+        /* UHC */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+        GPIO119_USBH2_PWR,
+        GPIO120_USBH2_PEN,
+
+        /* PCMCIA */
+        GPIO85_nPCE_1,
+        GPIO54_nPCE_2,
+        GPIO55_nPREG,
+        GPIO50_nPIOR,
+        GPIO51_nPIOW,
+        GPIO49_nPWE,
+        GPIO48_nPOE,
+        GPIO57_nIOIS16,
+        GPIO56_nPWAIT,
+        GPIO104_PSKTSEL,
+        GPIO53_GPIO,    /* RESET */
+        GPIO83_GPIO,    /* BVD1 */
+        GPIO82_GPIO,    /* BVD2 */
+        GPIO1_GPIO,     /* READY */
+        GPIO84_GPIO,    /* DETECT */
+        GPIO107_GPIO,   /* PPEN */
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+};
+#else
+static mfp_cfg_t colibri_pxa270_evalboard_pin_config[] __initdata = {};
+#endif
+
+#ifdef  CONFIG_MACH_COLIBRI_PXA270_INCOME
+static mfp_cfg_t income_pin_config[] __initdata = {
+        /* MMC */
+        GPIO32_MMC_CLK,
+        GPIO92_MMC_DAT_0,
+        GPIO109_MMC_DAT_1,
+        GPIO110_MMC_DAT_2,
+        GPIO111_MMC_DAT_3,
+        GPIO112_MMC_CMD,
+        GPIO0_GPIO,     /* SD detect */
+        GPIO1_GPIO,     /* SD read-only */
+
+        /* FFUART */
+        GPIO39_FFUART_TXD,
+        GPIO34_FFUART_RXD,
+
+        /* BFUART */
+        GPIO42_BTUART_RXD,
+        GPIO43_BTUART_TXD,
+        GPIO45_BTUART_RTS,
+
+        /* STUART */
+        GPIO46_STUART_RXD,
+        GPIO47_STUART_TXD,
+
+        /* UHC */
+        GPIO88_USBH1_PWR,
+        GPIO89_USBH1_PEN,
+
+        /* LCD */
+        GPIOxx_LCD_TFT_16BPP,
+
+        /* PWM */
+        GPIO16_PWM0_OUT,
+
+        /* I2C */
+        GPIO117_I2C_SCL,
+        GPIO118_I2C_SDA,
+
+        /* LED */
+        GPIO54_GPIO,    /* LED A */
+        GPIO55_GPIO,    /* LED B */
+};
+#else
+static mfp_cfg_t income_pin_config[] __initdata = {};
+#endif
+
+/******************************************************************************
  * Pin configuration
  ******************************************************************************/
 static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = {
@@ -184,10 +281,13 @@ static void __init colibri_pxa270_init(void)
         colibri_pxa270_tsc_init();
 
         switch (colibri_pxa270_baseboard) {
-        case COLIBRI_PXA270_EVALBOARD:
-                colibri_pxa270_evalboard_init();
+        case COLIBRI_EVALBOARD:
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(
+                        colibri_pxa270_evalboard_pin_config));
+                colibri_evalboard_init();
                 break;
         case COLIBRI_PXA270_INCOME:
+                pxa2xx_mfp_config(ARRAY_AND_SIZE(income_pin_config));
                 colibri_pxa270_income_boardinit();
                 break;
         default:
@@ -209,7 +309,7 @@ static void __init colibri_pxa270_income_init(void)
 MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa270_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -217,7 +317,7 @@ MACHINE_END
 MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
         .boot_params    = 0xa0000100,
         .init_machine   = colibri_pxa270_income_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index a70b256591e6..fddb16d07eb0 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -31,9 +31,38 @@
 #include "generic.h"
 #include "devices.h"
 
+
+#ifdef CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO7_MMC1_CLK,
+        GPIO14_MMC1_CMD,
+        GPIO3_MMC1_DAT0,
+        GPIO4_MMC1_DAT1,
+        GPIO5_MMC1_DAT2,
+        GPIO6_MMC1_DAT3,
+        GPIO39_GPIO,    /* SD detect */
+
+        /* UHC */
+        GPIO0_2_USBH_PEN,
+        GPIO1_2_USBH_PWR,
+        GPIO77_USB_P3_1,
+        GPIO78_USB_P3_2,
+        GPIO79_USB_P3_3,
+        GPIO80_USB_P3_4,
+        GPIO81_USB_P3_5,
+        GPIO82_USB_P3_6,
+
+        /* I2C */
+        GPIO21_I2C_SCL,
+        GPIO22_I2C_SDA,
+};
+#else
+static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {};
+#endif
+
 #if defined(CONFIG_AX88796)
 #define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO26_GPIO)
-
 /*
  * Asix AX88796 Ethernet
  */
@@ -80,35 +109,6 @@ static void __init colibri_pxa300_init_eth(void)
 static inline void __init colibri_pxa300_init_eth(void) {}
 #endif /* CONFIG_AX88796 */
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = {
-        GPIO0_2_USBH_PEN,
-        GPIO1_2_USBH_PWR,
-};
-
-static struct pxaohci_platform_data colibri_pxa300_ohci_info = {
-        .port_mode      = PMM_GLOBAL_MODE,
-        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-void __init colibri_pxa300_init_ohci(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config));
-        pxa_set_ohci_info(&colibri_pxa300_ohci_info);
-}
-#else
-static inline void colibri_pxa300_init_ohci(void) {}
-#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
-
-static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = {
-        GPIO7_MMC1_CLK,
-        GPIO14_MMC1_CMD,
-        GPIO3_MMC1_DAT0,
-        GPIO4_MMC1_DAT1,
-        GPIO5_MMC1_DAT2,
-        GPIO6_MMC1_DAT3,
-};
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = {
         GPIO54_LCD_LDD_0,
@@ -171,24 +171,21 @@ static inline void colibri_pxa310_init_ac97(void) {}
 
 void __init colibri_pxa300_init(void)
 {
-        pxa_set_ffuart_info(NULL);
-        pxa_set_btuart_info(NULL);
-        pxa_set_stuart_info(NULL);
-
         colibri_pxa300_init_eth();
-        colibri_pxa300_init_ohci();
         colibri_pxa3xx_init_nand();
         colibri_pxa300_init_lcd();
         colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO));
         colibri_pxa310_init_ac97();
-        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config),
-                                mfp_to_gpio(MFP_PIN_GPIO13));
+
+        /* Evalboard init */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_evalboard_pin_config));
+        colibri_evalboard_init();
 }
 
 MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa300_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ca5f29e2e9cd..ff9ff5f4fc47 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -35,9 +35,72 @@
 #include "generic.h"
 #include "devices.h"
 
+#ifdef  CONFIG_MACH_COLIBRI_EVALBOARD
+static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {
+        /* MMC */
+        GPIO22_MMC1_CLK,
+        GPIO23_MMC1_CMD,
+        GPIO18_MMC1_DAT0,
+        GPIO19_MMC1_DAT1,
+        GPIO20_MMC1_DAT2,
+        GPIO21_MMC1_DAT3,
+        GPIO28_GPIO,    /* SD detect */
+
+        /* UART 1 configuration (may be set by bootloader) */
+        GPIO99_UART1_CTS,
+        GPIO104_UART1_RTS,
+        GPIO97_UART1_RXD,
+        GPIO98_UART1_TXD,
+        GPIO101_UART1_DTR,
+        GPIO103_UART1_DSR,
+        GPIO100_UART1_DCD,
+        GPIO102_UART1_RI,
+
+        /* UART 2 configuration */
+        GPIO109_UART2_CTS,
+        GPIO112_UART2_RTS,
+        GPIO110_UART2_RXD,
+        GPIO111_UART2_TXD,
+
+        /* UART 3 configuration */
+        GPIO30_UART3_RXD,
+        GPIO31_UART3_TXD,
+
+        /* UHC */
+        GPIO2_2_USBH_PEN,
+        GPIO3_2_USBH_PWR,
+
+        /* I2C */
+        GPIO32_I2C_SCL,
+        GPIO33_I2C_SDA,
+
+        /* PCMCIA */
+        MFP_CFG(GPIO59, AF7),   /* PRST ; AF7 to tristate */
+        MFP_CFG(GPIO61, AF7),   /* PCE1 ; AF7 to tristate */
+        MFP_CFG(GPIO60, AF7),   /* PCE2 ; AF7 to tristate */
+        MFP_CFG(GPIO62, AF7),   /* PCD ; AF7 to tristate */
+        MFP_CFG(GPIO56, AF7),   /* PSKTSEL ; AF7 to tristate */
+        GPIO27_GPIO,            /* RDnWR ; input/tristate */
+        GPIO50_GPIO,            /* PREG ; input/tristate */
+        GPIO2_RDY,
+        GPIO5_NPIOR,
+        GPIO6_NPIOW,
+        GPIO7_NPIOS16,
+        GPIO8_NPWAIT,
+        GPIO29_GPIO,            /* PRDY (READY GPIO) */
+        GPIO57_GPIO,            /* PPEN (POWER GPIO) */
+        GPIO81_GPIO,            /* PCD (DETECT GPIO) */
+        GPIO77_GPIO,            /* PRST (RESET GPIO) */
+        GPIO53_GPIO,            /* PBVD1 */
+        GPIO79_GPIO,            /* PBVD2 */
+        GPIO54_GPIO,            /* POE */
+};
+#else
+static mfp_cfg_t colibri_pxa320_evalboard_pin_config[] __initdata = {};
+#endif
+
 #if defined(CONFIG_AX88796)
 #define COLIBRI_ETH_IRQ_GPIO    mfp_to_gpio(GPIO36_GPIO)
-
 /*
  * Asix AX88796 Ethernet
  */
@@ -84,26 +147,6 @@ static void __init colibri_pxa320_init_eth(void)
 static inline void __init colibri_pxa320_init_eth(void) {}
 #endif /* CONFIG_AX88796 */
 
-#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = {
-        GPIO2_2_USBH_PEN,
-        GPIO3_2_USBH_PWR,
-};
-
-static struct pxaohci_platform_data colibri_pxa320_ohci_info = {
-        .port_mode      = PMM_GLOBAL_MODE,
-        .flags          = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW,
-};
-
-void __init colibri_pxa320_init_ohci(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config));
-        pxa_set_ohci_info(&colibri_pxa320_ohci_info);
-}
-#else
-static inline void colibri_pxa320_init_ohci(void) {}
-#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
-
 #if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
 static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
         .gpio_vbus              = mfp_to_gpio(MFP_PIN_GPIO96),
@@ -140,15 +183,6 @@ static void __init colibri_pxa320_init_udc(void)
 static inline void colibri_pxa320_init_udc(void) {}
 #endif
 
-static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
-        GPIO22_MMC1_CLK,
-        GPIO23_MMC1_CMD,
-        GPIO18_MMC1_DAT0,
-        GPIO19_MMC1_DAT1,
-        GPIO20_MMC1_DAT2,
-        GPIO21_MMC1_DAT3
-};
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = {
         GPIO6_2_LCD_LDD_0,
@@ -205,59 +239,24 @@ static inline void __init colibri_pxa320_init_ac97(void)
 static inline void colibri_pxa320_init_ac97(void) {}
 #endif
 
-/*
- * The following configuration is verified to work with the Toradex Orchid
- * carrier board
- */
-static mfp_cfg_t colibri_pxa320_uart_pin_config[] __initdata = {
-        /* UART 1 configuration (may be set by bootloader) */
-        GPIO99_UART1_CTS,
-        GPIO104_UART1_RTS,
-        GPIO97_UART1_RXD,
-        GPIO98_UART1_TXD,
-        GPIO101_UART1_DTR,
-        GPIO103_UART1_DSR,
-        GPIO100_UART1_DCD,
-        GPIO102_UART1_RI,
-
-        /* UART 2 configuration */
-        GPIO109_UART2_CTS,
-        GPIO112_UART2_RTS,
-        GPIO110_UART2_RXD,
-        GPIO111_UART2_TXD,
-
-        /* UART 3 configuration */
-        GPIO30_UART3_RXD,
-        GPIO31_UART3_TXD,
-};
-
-static void __init colibri_pxa320_init_uart(void)
-{
-        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_uart_pin_config));
-}
-
 void __init colibri_pxa320_init(void)
 {
-        pxa_set_ffuart_info(NULL);
-        pxa_set_btuart_info(NULL);
-        pxa_set_stuart_info(NULL);
-
         colibri_pxa320_init_eth();
-        colibri_pxa320_init_ohci();
         colibri_pxa3xx_init_nand();
         colibri_pxa320_init_lcd();
         colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO));
         colibri_pxa320_init_ac97();
-        colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
-                                mfp_to_gpio(MFP_PIN_GPIO28));
-        colibri_pxa320_init_uart();
         colibri_pxa320_init_udc();
+
+        /* Evalboard init */
+        pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_evalboard_pin_config));
+        colibri_evalboard_init();
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
         .boot_params    = COLIBRI_SDRAM_BASE + 0x100,
         .init_machine   = colibri_pxa320_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 199afa2ae303..96b2d9fbfef0 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -64,55 +64,6 @@ void __init colibri_pxa3xx_init_eth(struct ax_plat_data *plat_data)
 }
 #endif
 
-#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
-static int mmc_detect_pin;
-
-static int colibri_pxa3xx_mci_init(struct device *dev,
-                                   irq_handler_t colibri_mmc_detect_int,
-                                   void *data)
-{
-        int ret;
-
-        ret = gpio_request(mmc_detect_pin, "mmc card detect");
-        if (ret)
-                return ret;
-
-        gpio_direction_input(mmc_detect_pin);
-        ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int,
-                          IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
-                          "MMC card detect", data);
-        if (ret) {
-                gpio_free(mmc_detect_pin);
-                return ret;
-        }
-
-        return 0;
-}
-
-static void colibri_pxa3xx_mci_exit(struct device *dev, void *data)
-{
-        free_irq(mmc_detect_pin, data);
-        gpio_free(gpio_to_irq(mmc_detect_pin));
-}
-
-static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = {
-        .detect_delay_ms        = 200,
-        .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
-        .init                   = colibri_pxa3xx_mci_init,
-        .exit                   = colibri_pxa3xx_mci_exit,
-        .gpio_card_detect       = -1,
-        .gpio_card_ro           = -1,
-        .gpio_power             = -1,
-};
-
-void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin)
-{
-        pxa3xx_mfp_config(pins, len);
-        mmc_detect_pin = detect_pin;
-        pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data);
-}
-#endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */
-
 #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static int lcd_bl_pin;
 
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 821229acabe6..9f3e5af0a0db 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -721,7 +721,7 @@ static void __init fixup_corgi(struct machine_desc *desc,
 #ifdef CONFIG_MACH_CORGI
 MACHINE_START(CORGI, "SHARP Corgi")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
@@ -731,7 +731,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_SHEPHERD
 MACHINE_START(SHEPHERD, "SHARP Shepherd")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
@@ -741,7 +741,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_HUSKY
 MACHINE_START(HUSKY, "SHARP Husky")
         .fixup          = fixup_corgi,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = corgi_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 58093d9e07be..6a7aeab42f6c 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -38,8 +38,10 @@
 #include <linux/cpufreq.h>
 #include <linux/err.h>
 #include <linux/regulator/consumer.h>
+#include <linux/io.h>
 
 #include <mach/pxa2xx-regs.h>
+#include <mach/smemc.h>
 
 #ifdef DEBUG
 static unsigned int freq_debug;
@@ -242,7 +244,7 @@ static void pxa27x_guess_max_freq(void)
 
 static void init_sdram_rows(void)
 {
-        uint32_t mdcnfg = MDCNFG;
+        uint32_t mdcnfg = __raw_readl(MDCNFG);
         unsigned int drac2 = 0, drac0 = 0;
 
         if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
@@ -331,8 +333,8 @@ static int pxa_set_target(struct cpufreq_policy *policy,
          * we need to preset the smaller DRI before the change.  If we're
          * speeding up we need to set the larger DRI value after the change.
          */
-        preset_mdrefr = postset_mdrefr = MDREFR;
-        if ((MDREFR & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
+        preset_mdrefr = postset_mdrefr = __raw_readl(MDREFR);
+        if ((preset_mdrefr & MDREFR_DRI_MASK) > mdrefr_dri(new_freq_mem)) {
                 preset_mdrefr = (preset_mdrefr & ~MDREFR_DRI_MASK);
                 preset_mdrefr |= mdrefr_dri(new_freq_mem);
         }
@@ -370,7 +372,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
 3:              nop                                                     \n\
           "
                      : "=&r" (unused)
-                     : "r" (&MDREFR), "r" (cclkcfg),
+                     : "r" (MDREFR), "r" (cclkcfg),
                        "r" (preset_mdrefr), "r" (postset_mdrefr)
                      : "r4", "r5");
         local_irq_restore(flags);
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 57cacaff194d..a305424a967d 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -27,6 +27,7 @@
 #include <mach/ohci.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -255,9 +256,9 @@ static struct platform_device *devices[] __initdata = {
 static void __init csb726_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config));
-/*      MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */
-/*      MSC2 = 0x06697ff4; *//* none/SM501 */
-        MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */
+/*      __raw_writel(0x7ffc3ffc, MSC1); *//* LAN9215/EXP_CS */
+/*      __raw_writel(0x06697ff4, MSC2); *//* none/SM501 */
+        __raw_writel((__raw_readl(MSC2) & ~0xffff) | 0x7ff4, MSC2); /* SM501 */
 
         pxa_set_ffuart_info(NULL);
         pxa_set_btuart_info(NULL);
@@ -273,7 +274,7 @@ static void __init csb726_init(void)
 
 MACHINE_START(CSB726, "Cogent CSB726")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = csb726_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index aaa1166df964..022c2fa4af04 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -342,27 +342,6 @@ struct platform_device pxa27x_device_i2c_power = {
 };
 #endif
 
-#ifdef CONFIG_PXA3xx
-static struct resource pxa3xx_resources_i2c_power[] = {
-        {
-                .start  = 0x40f500c0,
-                .end    = 0x40f500d3,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = IRQ_PWRI2C,
-                .end    = IRQ_PWRI2C,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device pxa3xx_device_i2c_power = {
-        .name           = "pxa3xx-pwri2c",
-        .id             = 1,
-        .resource       = pxa3xx_resources_i2c_power,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
-};
-#endif
-
 static struct resource pxai2s_resources[] = {
         {
                 .start  = 0x40400000,
@@ -633,30 +612,35 @@ struct platform_device pxa25x_device_assp = {
 #endif /* CONFIG_PXA25x */
 
 #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
-
-static struct resource pxa27x_resource_keypad[] = {
+static struct resource pxa27x_resource_camera[] = {
         [0] = {
-                .start  = 0x41500000,
-                .end    = 0x4150004c,
+                .start  = 0x50000000,
+                .end    = 0x50000fff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = IRQ_KEYPAD,
-                .end    = IRQ_KEYPAD,
+                .start  = IRQ_CAMERA,
+                .end    = IRQ_CAMERA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
 
-struct platform_device pxa27x_device_keypad = {
-        .name           = "pxa27x-keypad",
-        .id             = -1,
-        .resource       = pxa27x_resource_keypad,
-        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
+
+static struct platform_device pxa27x_device_camera = {
+        .name           = "pxa27x-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask               = &pxa27x_dma_mask_camera,
+                .coherent_dma_mask      = 0xffffffff,
+        },
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
+        .resource       = pxa27x_resource_camera,
 };
 
-void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
 {
-        pxa_register_device(&pxa27x_device_keypad, info);
+        pxa_register_device(&pxa27x_device_camera, info);
 }
 
 static u64 pxa27x_ohci_dma_mask = DMA_BIT_MASK(32);
@@ -689,6 +673,33 @@ void __init pxa_set_ohci_info(struct pxaohci_platform_data *info)
 {
         pxa_register_device(&pxa27x_device_ohci, info);
 }
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+
+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+static struct resource pxa27x_resource_keypad[] = {
+        [0] = {
+                .start  = 0x41500000,
+                .end    = 0x4150004c,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_KEYPAD,
+                .end    = IRQ_KEYPAD,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa27x_device_keypad = {
+        .name           = "pxa27x-keypad",
+        .id             = -1,
+        .resource       = pxa27x_resource_keypad,
+        .num_resources  = ARRAY_SIZE(pxa27x_resource_keypad),
+};
+
+void __init pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info)
+{
+        pxa_register_device(&pxa27x_device_keypad, info);
+}
 
 static u64 pxa27x_ssp1_dma_mask = DMA_BIT_MASK(32);
 
@@ -833,79 +844,9 @@ struct platform_device pxa27x_device_pwm1 = {
         .resource       = pxa27x_resource_pwm1,
         .num_resources  = ARRAY_SIZE(pxa27x_resource_pwm1),
 };
-
-static struct resource pxa27x_resource_camera[] = {
-        [0] = {
-                .start  = 0x50000000,
-                .end    = 0x50000fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CAMERA,
-                .end    = IRQ_CAMERA,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 pxa27x_dma_mask_camera = DMA_BIT_MASK(32);
-
-static struct platform_device pxa27x_device_camera = {
-        .name           = "pxa27x-camera",
-        .id             = 0, /* This is used to put cameras on this interface */
-        .dev            = {
-                .dma_mask               = &pxa27x_dma_mask_camera,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(pxa27x_resource_camera),
-        .resource       = pxa27x_resource_camera,
-};
-
-void __init pxa_set_camera_info(struct pxacamera_platform_data *info)
-{
-        pxa_register_device(&pxa27x_device_camera, info);
-}
-#endif /* CONFIG_PXA27x || CONFIG_PXA3xx */
+#endif /* CONFIG_PXA27x || CONFIG_PXA3xx || CONFIG_PXA95x*/
 
 #ifdef CONFIG_PXA3xx
-static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
-
-static struct resource pxa3xx_resource_ssp4[] = {
-        [0] = {
-                .start  = 0x41a00000,
-                .end    = 0x41a0003f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_SSP4,
-                .end    = IRQ_SSP4,
-                .flags  = IORESOURCE_IRQ,
-        },
-        [2] = {
-                /* DRCMR for RX */
-                .start  = 2,
-                .end    = 2,
-                .flags  = IORESOURCE_DMA,
-        },
-        [3] = {
-                /* DRCMR for TX */
-                .start  = 3,
-                .end    = 3,
-                .flags  = IORESOURCE_DMA,
-        },
-};
-
-struct platform_device pxa3xx_device_ssp4 = {
-        /* PXA3xx SSP is basically equivalent to PXA27x */
-        .name           = "pxa27x-ssp",
-        .id             = 3,
-        .dev            = {
-                .dma_mask = &pxa3xx_ssp4_dma_mask,
-                .coherent_dma_mask = DMA_BIT_MASK(32),
-        },
-        .resource       = pxa3xx_resource_ssp4,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
-};
-
 static struct resource pxa3xx_resources_mci2[] = {
         [0] = {
                 .start  = 0x42000000,
@@ -984,6 +925,54 @@ void __init pxa3xx_set_mci3_info(struct pxamci_platform_data *info)
         pxa_register_device(&pxa3xx_device_mci3, info);
 }
 
+static struct resource pxa3xx_resources_gcu[] = {
+        {
+                .start  = 0x54000000,
+                .end    = 0x54000fff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_GCU,
+                .end    = IRQ_GCU,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device pxa3xx_device_gcu = {
+        .name           = "pxa3xx-gcu",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resources_gcu),
+        .resource       = pxa3xx_resources_gcu,
+        .dev            = {
+                .dma_mask = &pxa3xx_gcu_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
+
+#endif /* CONFIG_PXA3xx */
+
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x)
+static struct resource pxa3xx_resources_i2c_power[] = {
+        {
+                .start  = 0x40f500c0,
+                .end    = 0x40f500d3,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_PWRI2C,
+                .end    = IRQ_PWRI2C,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device pxa3xx_device_i2c_power = {
+        .name           = "pxa3xx-pwri2c",
+        .id             = 1,
+        .resource       = pxa3xx_resources_i2c_power,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resources_i2c_power),
+};
+
 static struct resource pxa3xx_resources_nand[] = {
         [0] = {
                 .start  = 0x43100000,
@@ -1027,33 +1016,45 @@ void __init pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info)
         pxa_register_device(&pxa3xx_device_nand, info);
 }
 
-static struct resource pxa3xx_resources_gcu[] = {
-        {
-                .start  = 0x54000000,
-                .end    = 0x54000fff,
+static u64 pxa3xx_ssp4_dma_mask = DMA_BIT_MASK(32);
+
+static struct resource pxa3xx_resource_ssp4[] = {
+        [0] = {
+                .start  = 0x41a00000,
+                .end    = 0x41a0003f,
                 .flags  = IORESOURCE_MEM,
         },
-        {
-                .start  = IRQ_GCU,
-                .end    = IRQ_GCU,
+        [1] = {
+                .start  = IRQ_SSP4,
+                .end    = IRQ_SSP4,
                 .flags  = IORESOURCE_IRQ,
         },
+        [2] = {
+                /* DRCMR for RX */
+                .start  = 2,
+                .end    = 2,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                /* DRCMR for TX */
+                .start  = 3,
+                .end    = 3,
+                .flags  = IORESOURCE_DMA,
+        },
 };
 
-static u64 pxa3xx_gcu_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device pxa3xx_device_gcu = {
-        .name           = "pxa3xx-gcu",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(pxa3xx_resources_gcu),
-        .resource       = pxa3xx_resources_gcu,
+struct platform_device pxa3xx_device_ssp4 = {
+        /* PXA3xx SSP is basically equivalent to PXA27x */
+        .name           = "pxa27x-ssp",
+        .id             = 3,
         .dev            = {
-                .dma_mask = &pxa3xx_gcu_dmamask,
-                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &pxa3xx_ssp4_dma_mask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
         },
+        .resource       = pxa3xx_resource_ssp4,
+        .num_resources  = ARRAY_SIZE(pxa3xx_resource_ssp4),
 };
-
-#endif /* CONFIG_PXA3xx */
+#endif /* CONFIG_PXA3xx || CONFIG_PXA95x */
 
 /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1.
  * See comment in arch/arm/mach-pxa/ssp.c::ssp_probe() */
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index ed0dbfdb22ed..4cefd1d18afd 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1300,7 +1300,7 @@ static void __init em_x270_init(void)
 
 MACHINE_START(EM_X270, "Compulab EM-X270")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
@@ -1308,7 +1308,7 @@ MACHINE_END
 
 MACHINE_START(EXEDA, "Compulab eXeda")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = em_x270_init,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index b25690ccadc4..edca0a043293 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -181,7 +181,7 @@ static void __init e330_init(void)
 MACHINE_START(E330, "Toshiba e330")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -230,7 +230,7 @@ static void __init e350_init(void)
 MACHINE_START(E350, "Toshiba e350")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -352,7 +352,7 @@ static void __init e400_init(void)
 MACHINE_START(E400, "Toshiba e400")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -540,7 +540,7 @@ static void __init e740_init(void)
 MACHINE_START(E740, "Toshiba e740")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -731,7 +731,7 @@ static void __init e750_init(void)
 MACHINE_START(E750, "Toshiba e750")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
@@ -926,7 +926,7 @@ static void __init e800_init(void)
 MACHINE_START(E800, "Toshiba e800")
         /* Maintainer: Ian Molton (spyro@f2s.com) */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = ESERIES_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .fixup          = eseries_fixup,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 142c711f4cda..87cec0abe5b0 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -798,7 +798,7 @@ static void __init a780_init(void)
 
 MACHINE_START(EZX_A780, "Motorola EZX A780")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -863,7 +863,7 @@ static void __init e680_init(void)
 
 MACHINE_START(EZX_E680, "Motorola EZX E680")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -928,7 +928,7 @@ static void __init a1200_init(void)
 
 MACHINE_START(EZX_A1200, "Motorola EZX A1200")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1118,7 +1118,7 @@ static void __init a910_init(void)
 
 MACHINE_START(EZX_A910, "Motorola EZX A910")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1183,7 +1183,7 @@ static void __init e6_init(void)
 
 MACHINE_START(EZX_E6, "Motorola EZX E6")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -1222,7 +1222,7 @@ static void __init e2_init(void)
 
 MACHINE_START(EZX_E2, "Motorola EZX E2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .nr_irqs        = EZX_NR_IRQS,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 6451e9c3a93f..d6e15f71fc09 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -28,6 +28,8 @@
 
 #include <mach/reset.h>
 #include <mach/gpio.h>
+#include <mach/smemc.h>
+#include <mach/pxa3xx-regs.h>
 
 #include "generic.h"
 
@@ -35,9 +37,10 @@ void clear_reset_status(unsigned int mask)
 {
         if (cpu_is_pxa2xx())
                 pxa2xx_clear_reset_status(mask);
-
-        if (cpu_is_pxa3xx())
-                pxa3xx_clear_reset_status(mask);
+        else {
+                /* RESET_STATUS_* has a 1:1 mapping with ARSR */
+                ARSR = mask;
+        }
 }
 
 unsigned long get_clock_tick_rate(void)
@@ -71,47 +74,17 @@ unsigned int get_clk_frequency_khz(int info)
 EXPORT_SYMBOL(get_clk_frequency_khz);
 
 /*
- * Return the current memory clock frequency in units of 10kHz
- */
-unsigned int get_memclk_frequency_10khz(void)
-{
-        if (cpu_is_pxa25x())
-                return pxa25x_get_memclk_frequency_10khz();
-        else if (cpu_is_pxa27x())
-                return pxa27x_get_memclk_frequency_10khz();
-        return 0;
-}
-EXPORT_SYMBOL(get_memclk_frequency_10khz);
-
-/*
  * Intel PXA2xx internal register mapping.
  *
- * Note 1: not all PXA2xx variants implement all those addresses.
- *
- * Note 2: virtual 0xfffe0000-0xffffffff is reserved for the vector table
- *         and cache flush area.
+ * Note: virtual 0xfffe0000-0xffffffff is reserved for the vector table
+ *       and cache flush area.
  */
-static struct map_desc standard_io_desc[] __initdata = {
+static struct map_desc common_io_desc[] __initdata = {
         {       /* Devs */
                 .virtual        =  0xf2000000,
                 .pfn            = __phys_to_pfn(0x40000000),
                 .length         = 0x02000000,
                 .type           = MT_DEVICE
-        }, {    /* Mem Ctl */
-                .virtual        =  0xf6000000,
-                .pfn            = __phys_to_pfn(0x48000000),
-                .length         = 0x00200000,
-                .type           = MT_DEVICE
-        }, {    /* Camera */
-                .virtual        =  0xfa000000,
-                .pfn            = __phys_to_pfn(0x50000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
-        }, {    /* IMem ctl */
-                .virtual        =  0xfe000000,
-                .pfn            = __phys_to_pfn(0x58000000),
-                .length         = 0x00100000,
-                .type           = MT_DEVICE
         }, {    /* UNCACHED_PHYS_0 */
                 .virtual        = 0xff000000,
                 .pfn            = __phys_to_pfn(0x00000000),
@@ -122,6 +95,5 @@ static struct map_desc standard_io_desc[] __initdata = {
 
 void __init pxa_map_io(void)
 {
-        iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
-        get_clk_frequency_khz(1);
+        iotable_init(ARRAY_AND_SIZE(common_io_desc));
 }
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 4b1ad2769ed7..6205dc9a2b9d 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -20,7 +20,12 @@ extern void __init pxa26x_init_irq(void);
 #endif
 extern void __init pxa27x_init_irq(void);
 extern void __init pxa3xx_init_irq(void);
+extern void __init pxa95x_init_irq(void);
+
 extern void __init pxa_map_io(void);
+extern void __init pxa25x_map_io(void);
+extern void __init pxa27x_map_io(void);
+extern void __init pxa3xx_map_io(void);
 
 extern unsigned int get_clk_frequency_khz(int info);
 
@@ -32,18 +37,14 @@ extern unsigned int get_clk_frequency_khz(int info);
 
 #ifdef CONFIG_PXA25x
 extern unsigned pxa25x_get_clk_frequency_khz(int);
-extern unsigned pxa25x_get_memclk_frequency_10khz(void);
 #else
 #define pxa25x_get_clk_frequency_khz(x)         (0)
-#define pxa25x_get_memclk_frequency_10khz()     (0)
 #endif
 
 #ifdef CONFIG_PXA27x
 extern unsigned pxa27x_get_clk_frequency_khz(int);
-extern unsigned pxa27x_get_memclk_frequency_10khz(void);
 #else
 #define pxa27x_get_clk_frequency_khz(x)         (0)
-#define pxa27x_get_memclk_frequency_10khz()     (0)
 #endif
 
 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
@@ -54,10 +55,8 @@ static inline void pxa2xx_clear_reset_status(unsigned int mask) {}
 
 #ifdef CONFIG_PXA3xx
 extern unsigned pxa3xx_get_clk_frequency_khz(int);
-extern void pxa3xx_clear_reset_status(unsigned int);
 #else
 #define pxa3xx_get_clk_frequency_khz(x)         (0)
-static inline void pxa3xx_clear_reset_status(unsigned int mask) {}
 #endif
 
 extern struct sysdev_class pxa_irq_sysclass;
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 1e2a9a13aec1..6fd319ea5284 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -225,7 +225,7 @@ static void __init gumstix_init(void)
 
 MACHINE_START(GUMSTIX, "Gumstix")
         .boot_params    = 0xa0000100, /* match u-boot bi_boot_params */
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = gumstix_init,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 7057a1f46db4..657db469de1f 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -32,6 +32,7 @@
 #include <mach/pxa25x.h>
 #include <mach/h5000.h>
 #include <mach/udc.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -172,11 +173,11 @@ static unsigned long h5000_pin_config[] __initdata = {
 
 static void fix_msc(void)
 {
-        MSC0 = 0x129c24f2;
-        MSC1 = 0x7ff424fa;
-        MSC2 = 0x7ff47ff4;
+        __raw_writel(0x129c24f2, MSC0);
+        __raw_writel(0x7ff424fa, MSC1);
+        __raw_writel(0x7ff47ff4, MSC2);
 
-        MDREFR |= 0x02080000;
+        __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR);
 }
 
 /*
@@ -202,7 +203,7 @@ static void __init h5000_init(void)
 
 MACHINE_START(H5400, "HP iPAQ H5000")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .timer = &pxa_timer,
         .init_machine = h5000_init,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index 01b7f07ebad2..e8603eba54bd 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -160,7 +160,7 @@ static void __init himalaya_init(void)
 
 MACHINE_START(HIMALAYA, "HTC Himalaya")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa25x_map_io,
         .init_irq = pxa25x_init_irq,
         .init_machine = himalaya_init,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 76d93a25bab6..cacb21b7014d 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -871,7 +871,7 @@ static void __init hx4700_init(void)
 
 MACHINE_START(H4700, "HP iPAQ HX4700")
         .boot_params  = 0xa0000100,
-        .map_io       = pxa_map_io,
+        .map_io       = pxa27x_map_io,
         .nr_irqs      = HX4700_NR_IRQS,
         .init_irq     = pxa27x_init_irq,
         .init_machine = hx4700_init,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index d51ee3d25e70..ac6ee12e400e 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -192,7 +192,7 @@ static void __init icontrol_init(void)
 
 MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = icontrol_init
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index e773dceeabc6..dd40e4a9291c 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -187,7 +187,7 @@ static struct map_desc idp_io_desc[] __initdata = {
 
 static void __init idp_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
         iotable_init(idp_io_desc, ARRAY_SIZE(idp_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/include/mach/addr-map.h b/arch/arm/mach-pxa/include/mach/addr-map.h
new file mode 100644
index 000000000000..f4c03659168c
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/addr-map.h
@@ -0,0 +1,48 @@
+#ifndef __ASM_MACH_ADDR_MAP_H
+#define __ASM_MACH_ADDR_MAP_H
+
+/*
+ * Chip Selects
+ */
+#define PXA_CS0_PHYS            0x00000000
+#define PXA_CS1_PHYS            0x04000000
+#define PXA_CS2_PHYS            0x08000000
+#define PXA_CS3_PHYS            0x0C000000
+#define PXA_CS4_PHYS            0x10000000
+#define PXA_CS5_PHYS            0x14000000
+
+#define PXA300_CS0_PHYS         0x00000000      /* PXA300/PXA310 _only_ */
+#define PXA300_CS1_PHYS         0x30000000      /* PXA300/PXA310 _only_ */
+#define PXA3xx_CS2_PHYS         0x10000000
+#define PXA3xx_CS3_PHYS         0x14000000
+
+/*
+ * Peripheral Bus
+ */
+#define PERIPH_PHYS             0x40000000
+#define PERIPH_VIRT             0xf2000000
+#define PERIPH_SIZE             0x02000000
+
+/*
+ * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x)
+ */
+#define PXA2XX_SMEMC_PHYS       0x48000000
+#define PXA3XX_SMEMC_PHYS       0x4a000000
+#define SMEMC_VIRT              0xf6000000
+#define SMEMC_SIZE              0x00100000
+
+/*
+ * Dynamic Memory Controller (only on PXA3xx)
+ */
+#define DMEMC_PHYS              0x48100000
+#define DMEMC_VIRT              0xf6100000
+#define DMEMC_SIZE              0x00100000
+
+/*
+ * Internal Memory Controller (PXA27x and later)
+ */
+#define IMEMC_PHYS              0x58000000
+#define IMEMC_VIRT              0xfe000000
+#define IMEMC_SIZE              0x00100000
+
+#endif /* __ASM_MACH_ADDR_MAP_H */
diff --git a/arch/arm/mach-pxa/include/mach/balloon3.h b/arch/arm/mach-pxa/include/mach/balloon3.h
index 561562b4360b..7074e76146c9 100644
--- a/arch/arm/mach-pxa/include/mach/balloon3.h
+++ b/arch/arm/mach-pxa/include/mach/balloon3.h
@@ -26,6 +26,8 @@ enum balloon3_features {
 #define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
 #define BALLOON3_FPGA_LENGTH    0x01000000
 
+#define BALLOON3_FPGA_SETnCLR           (0x1000)
+
 /* FPGA / CPLD registers for CF socket */
 #define BALLOON3_CF_STATUS_REG          (BALLOON3_FPGA_VIRT + 0x00e00008)
 #define BALLOON3_CF_CONTROL_REG         (BALLOON3_FPGA_VIRT + 0x00e00008)
@@ -35,7 +37,7 @@ enum balloon3_features {
 #define BALLOON3_NAND_BASE              (PXA_CS4_PHYS + 0x00e00000)
 #define BALLOON3_NAND_IO_REG            (BALLOON3_FPGA_VIRT + 0x00e00000)
 #define BALLOON3_NAND_CONTROL2_REG      (BALLOON3_FPGA_VIRT + 0x00e00010)
-#define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00010)
+#define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00014)
 #define BALLOON3_NAND_CONTROL_REG       (BALLOON3_FPGA_VIRT + 0x00e00014)
 
 /* fpga/cpld interrupt control register */
@@ -174,7 +176,7 @@ enum balloon3_features {
 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 
-#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 4)
+#define BALLOON3_NR_IRQS        (IRQ_BOARD_START + 16)
 
 extern int balloon3_has(enum balloon3_features feature);
 
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h
index 58dada11054f..388a96f1ef93 100644
--- a/arch/arm/mach-pxa/include/mach/colibri.h
+++ b/arch/arm/mach-pxa/include/mach/colibri.h
@@ -9,14 +9,14 @@
  */
 
 enum {
-        COLIBRI_PXA270_EVALBOARD = 0,
+        COLIBRI_EVALBOARD = 0,
         COLIBRI_PXA270_INCOME,
 };
 
-#if defined(CONFIG_MACH_COLIBRI_PXA270_EVALBOARD)
-extern void colibri_pxa270_evalboard_init(void);
+#if defined(CONFIG_MACH_COLIBRI_EVALBOARD)
+extern void colibri_evalboard_init(void);
 #else
-static inline void colibri_pxa270_evalboard_init(void) {}
+static inline void colibri_evalboard_init(void) {}
 #endif
 
 #if defined(CONFIG_MACH_COLIBRI_PXA270_INCOME)
@@ -59,5 +59,11 @@ static inline void colibri_pxa3xx_init_nand(void) {}
 #define GPIO0_COLIBRI_PXA270_SD_DETECT  0
 #define GPIO113_COLIBRI_PXA270_TS_IRQ   113
 
+/* GPIO definitions for Colibri PXA300/310 */
+#define GPIO39_COLIBRI_PXA300_SD_DETECT 39
+
+/* GPIO definitions for Colibri PXA320 */
+#define GPIO28_COLIBRI_PXA320_SD_DETECT 28
+
 #endif /* _COLIBRI_H_ */
 
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 814f1458a06a..6957ba56025b 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -13,6 +13,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
 
+#include <mach/addr-map.h>
+
 /*
  * Workarounds for at least 2 errata so far require this.
  * The mapping is set in mach-pxa/generic.c.
@@ -193,14 +195,15 @@
 #define __cpu_is_pxa935(id)     (0)
 #endif
 
-#ifdef CONFIG_CPU_PXA950
-#define __cpu_is_pxa950(id)                             \
-        ({                                              \
+#ifdef CONFIG_CPU_PXA955
+#define __cpu_is_pxa955(id)                             \
+        ({                                              \
                 unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x697;                           \
-         })
+                _id == 0x581 || _id == 0xc08            \
+                        || _id == 0xb76;                \
+        })
 #else
-#define __cpu_is_pxa950(id)     (0)
+#define __cpu_is_pxa955(id)     (0)
 #endif
 
 #define cpu_is_pxa210()                                 \
@@ -253,16 +256,15 @@
                 __cpu_is_pxa935(read_cpuid_id());       \
          })
 
-#define cpu_is_pxa950()                                 \
+#define cpu_is_pxa955()                                 \
         ({                                              \
-                __cpu_is_pxa950(read_cpuid_id());       \
-         })
+                __cpu_is_pxa955(read_cpuid_id());       \
+        })
 
 
 /*
  * CPUID Core Generation Bit
  * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
- * == 0x3 for pxa300/pxa310/pxa320
  */
 #if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
 #define __cpu_is_pxa2xx(id)                             \
@@ -277,8 +279,10 @@
 #ifdef CONFIG_PXA3xx
 #define __cpu_is_pxa3xx(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 13 & 0x7;    \
-                _id == 0x3;                             \
+                __cpu_is_pxa300(id)                     \
+                        || __cpu_is_pxa310(id)          \
+                        || __cpu_is_pxa320(id)          \
+                        || __cpu_is_pxa93x(id);         \
          })
 #else
 #define __cpu_is_pxa3xx(id)     (0)
@@ -287,13 +291,22 @@
 #if defined(CONFIG_CPU_PXA930) || defined(CONFIG_CPU_PXA935)
 #define __cpu_is_pxa93x(id)                             \
         ({                                              \
-                unsigned int _id = (id) >> 4 & 0xfff;   \
-                _id == 0x683 || _id == 0x693;           \
+                __cpu_is_pxa930(id)                     \
+                        || __cpu_is_pxa935(id);         \
          })
 #else
 #define __cpu_is_pxa93x(id)     (0)
 #endif
 
+#ifdef CONFIG_PXA95x
+#define __cpu_is_pxa95x(id)                             \
+        ({                                              \
+                __cpu_is_pxa955(id);                    \
+        })
+#else
+#define __cpu_is_pxa95x(id)     (0)
+#endif
+
 #define cpu_is_pxa2xx()                                 \
         ({                                              \
                 __cpu_is_pxa2xx(read_cpuid_id());       \
@@ -308,6 +321,12 @@
         ({                                              \
                 __cpu_is_pxa93x(read_cpuid_id());       \
          })
+
+#define cpu_is_pxa95x()                                 \
+        ({                                              \
+                __cpu_is_pxa95x(read_cpuid_id());       \
+        })
+
 /*
  * return current memory and LCD clock frequency in units of 10kHz
  */
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index d372caa75dc7..a4285fc00878 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -21,16 +21,14 @@
 
 #define PXA_IRQ(x)      (PXA_ISA_IRQ_NUM + (x))
 
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
 #define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
-#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
-#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
+#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI,PXA27x) */
+#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI,PXA27x) */
 #define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
-#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
+#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt (PXA27x) */
+#define IRQ_ACIPC0      PXA_IRQ(5)      /* AP-CP Communication (PXA930) */
 #define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
-#endif
-
 #define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
 #define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
 #define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
@@ -38,7 +36,8 @@
 #define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
 #define IRQ_USB         PXA_IRQ(11)     /* USB Service */
 #define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
-#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
+#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt (PXA27x) */
+#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request (PXA3xx) */
 #define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
 #define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
 #define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
@@ -47,6 +46,7 @@
 #define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
 #define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
 #define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
+#define IRQ_ACIPC2      PXA_IRQ(19)     /* AP-CP Communication (PXA930) */
 #define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
 #define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
 #define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
@@ -60,19 +60,17 @@
 #define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
 #define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
 
-#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
 #define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
 #define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
-#endif
-
-#ifdef CONFIG_PXA3xx
-#define IRQ_SSP4        PXA_IRQ(13)     /* SSP4 service request */
 #define IRQ_CIR         PXA_IRQ(34)     /* Consumer IR */
 #define IRQ_COMM_WDT    PXA_IRQ(35)     /* Comm WDT interrupt */
 #define IRQ_TSI         PXA_IRQ(36)     /* Touch Screen Interface (PXA320) */
+#define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
 #define IRQ_USIM2       PXA_IRQ(38)     /* USIM2 Controller */
-#define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller */
+#define IRQ_GCU         PXA_IRQ(39)     /* Graphics Controller (PXA3xx) */
+#define IRQ_ACIPC1      PXA_IRQ(40)     /* AP-CP Communication (PXA930) */
 #define IRQ_MMC2        PXA_IRQ(41)     /* MMC2 Controller */
+#define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball (PXA930) */
 #define IRQ_1WIRE       PXA_IRQ(44)     /* 1-Wire Controller */
 #define IRQ_NAND        PXA_IRQ(45)     /* NAND Controller */
 #define IRQ_USB2        PXA_IRQ(46)     /* USB 2.0 Device Controller */
@@ -80,30 +78,14 @@
 #define IRQ_WAKEUP1     PXA_IRQ(50)     /* EXT_WAKEUP1 */
 #define IRQ_DMEMC       PXA_IRQ(51)     /* Dynamic Memory Controller */
 #define IRQ_MMC3        PXA_IRQ(55)     /* MMC3 Controller (PXA310) */
-#endif
 
-#ifdef CONFIG_CPU_PXA935
 #define IRQ_U2O         PXA_IRQ(64)     /* USB OTG 2.0 Controller (PXA935) */
 #define IRQ_U2H         PXA_IRQ(65)     /* USB Host 2.0 Controller (PXA935) */
-
-#define IRQ_MMC3_PXA935 PXA_IRQ(72)     /* MMC3 Controller (PXA935) */
-#define IRQ_MMC4_PXA935 PXA_IRQ(73)     /* MMC4 Controller (PXA935) */
-#define IRQ_MMC5_PXA935 PXA_IRQ(74)     /* MMC5 Controller (PXA935) */
-
+#define IRQ_PXA935_MMC0 PXA_IRQ(72)     /* MMC0 Controller (PXA935) */
+#define IRQ_PXA935_MMC1 PXA_IRQ(73)     /* MMC1 Controller (PXA935) */
+#define IRQ_PXA935_MMC2 PXA_IRQ(74)     /* MMC2 Controller (PXA935) */
+#define IRQ_PXA955_MMC3 PXA_IRQ(75)     /* MMC3 Controller (PXA955) */
 #define IRQ_U2P         PXA_IRQ(93)     /* USB PHY D+/D- Lines (PXA935) */
-#endif
-
-#ifdef CONFIG_CPU_PXA930
-#define IRQ_ENHROT      PXA_IRQ(37)     /* Enhanced Rotary (PXA930) */
-#define IRQ_ACIPC0      PXA_IRQ(5)
-#define IRQ_ACIPC1      PXA_IRQ(40)
-#define IRQ_ACIPC2      PXA_IRQ(19)
-#define IRQ_TRKBALL     PXA_IRQ(43)     /* Track Ball */
-#endif
-
-#ifdef CONFIG_CPU_PXA950
-#define IRQ_GC500       PXA_IRQ(70)     /* Graphics Controller (PXA950) */
-#endif
 
 #define PXA_GPIO_IRQ_BASE       PXA_IRQ(96)
 #define PXA_GPIO_IRQ_NUM        (192)
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
index 4fcddd9cab76..ee6ced1cea7f 100644
--- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
@@ -17,72 +17,6 @@
 #include <mach/hardware.h>
 
 /*
- * PXA Chip selects
- */
-
-#define PXA_CS0_PHYS    0x00000000
-#define PXA_CS1_PHYS    0x04000000
-#define PXA_CS2_PHYS    0x08000000
-#define PXA_CS3_PHYS    0x0C000000
-#define PXA_CS4_PHYS    0x10000000
-#define PXA_CS5_PHYS    0x14000000
-
-/*
- * Memory controller
- */
-
-#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
-#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
-#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
-#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
-#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
-#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
-#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
-#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
-#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
-#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
-#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
-#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
-#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
-#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
-#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
-#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
-#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
-
-/*
- * More handy macros for PCMCIA
- *
- * Arg is socket number
- */
-#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
-#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
-#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
-
-/* MECR register defines */
-#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
-#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
-
-#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
-#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
-#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
-#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
-
-#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
-#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
-#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
-#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
-#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
-#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
-#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
-#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
-#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
-#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
-#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
-#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
-#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
-#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
-
-/*
  * Power Manager
  */
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
index e91d63cfe811..e4fb4668c26e 100644
--- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
@@ -16,15 +16,6 @@
 #include <mach/hardware.h>
 
 /*
- * Static Chip Selects
- */
-
-#define PXA300_CS0_PHYS         (0x00000000)    /* PXA300/PXA310 _only_ */
-#define PXA300_CS1_PHYS         (0x30000000)    /* PXA300/PXA310 _only_ */
-#define PXA3xx_CS2_PHYS         (0x10000000)
-#define PXA3xx_CS3_PHYS         (0x14000000)
-
-/*
  * Oscillator Configuration Register (OSCC)
  */
 #define OSCC           __REG(0x41350000)  /* Oscillator Configuration Register */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
index 68464ce1c1ea..662288eb6f95 100644
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ b/arch/arm/mach-pxa/include/mach/regs-intc.h
@@ -27,8 +27,4 @@
 #define ICFP3           __REG(0x40D0013C)  /* Interrupt Controller FIQ Pending Register 3 */
 #define ICPR3           __REG(0x40D00140)  /* Interrupt Controller Pending Register 3 */
 
-#define IPR(x)          __REG(0x40D0001C + (x < 32 ? (x << 2)           \
-                                : (x < 64 ? (0x94 + ((x - 32) << 2))    \
-                                : (0x128 + ((x - 64) << 2)))))
-
 #endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/include/mach/smemc.h b/arch/arm/mach-pxa/include/mach/smemc.h
new file mode 100644
index 000000000000..654adc90c9a0
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/smemc.h
@@ -0,0 +1,74 @@
+/*
+ * Static memory controller register definitions for PXA CPUs
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __SMEMC_REGS_H
+#define __SMEMC_REGS_H
+
+#define PXA2XX_SMEMC_BASE       0x48000000
+#define PXA3XX_SMEMC_BASE       0x4a000000
+#define SMEMC_VIRT              0xf6000000
+
+#define MDCNFG          (SMEMC_VIRT + 0x00)  /* SDRAM Configuration Register 0 */
+#define MDREFR          (SMEMC_VIRT + 0x04)  /* SDRAM Refresh Control Register */
+#define MSC0            (SMEMC_VIRT + 0x08)  /* Static Memory Control Register 0 */
+#define MSC1            (SMEMC_VIRT + 0x0C)  /* Static Memory Control Register 1 */
+#define MSC2            (SMEMC_VIRT + 0x10)  /* Static Memory Control Register 2 */
+#define MECR            (SMEMC_VIRT + 0x14)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR           (SMEMC_VIRT + 0x18)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG          (SMEMC_VIRT + 0x1C)  /* Synchronous Static Memory Control Register */
+#define SXMRS           (SMEMC_VIRT + 0x24)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0          (SMEMC_VIRT + 0x28)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1          (SMEMC_VIRT + 0x2C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0          (SMEMC_VIRT + 0x30)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1          (SMEMC_VIRT + 0x34)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0           (SMEMC_VIRT + 0x38)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1           (SMEMC_VIRT + 0x3C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS           (SMEMC_VIRT + 0x40)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF        (SMEMC_VIRT + 0x44)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+#define MEMCLKCFG       (SMEMC_VIRT + 0x68)  /* Clock Configuration */
+#define CSADRCFG0       (SMEMC_VIRT + 0x80)  /* Address Configuration Register for CS0 */
+#define CSADRCFG1       (SMEMC_VIRT + 0x84)  /* Address Configuration Register for CS1 */
+#define CSADRCFG2       (SMEMC_VIRT + 0x88)  /* Address Configuration Register for CS2 */
+#define CSADRCFG3       (SMEMC_VIRT + 0x8C)  /* Address Configuration Register for CS3 */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)        (SMEMC_VIRT + 0x28 + ((s)<<2))  /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s)        (SMEMC_VIRT + 0x30 + ((s)<<2))  /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s)         (SMEMC_VIRT + 0x38 + ((s)<<2))  /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDCNFG_DE0      (1 << 0)        /* SDRAM Bank 0 Enable */
+#define MDCNFG_DE1      (1 << 1)        /* SDRAM Bank 1 Enable */
+#define MDCNFG_DE2      (1 << 16)       /* SDRAM Bank 2 Enable */
+#define MDCNFG_DE3      (1 << 17)       /* SDRAM Bank 3 Enable */
+
+#define MDREFR_K0DB4    (1 << 29)       /* SDCLK0 Divide by 4 Control/Status */
+#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
+
+#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 1beb40f692fc..54e91c9e71c8 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -16,20 +16,31 @@
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
+#include <linux/irq.h>
 
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
+#include <mach/irqs.h>
 #include <mach/gpio.h>
-#include <mach/regs-intc.h>
 
 #include "generic.h"
 
-#define MAX_INTERNAL_IRQS       128
+#define IRQ_BASE                (void __iomem *)io_p2v(0x40d00000)
+
+#define ICIP                    (0x000)
+#define ICMR                    (0x004)
+#define ICLR                    (0x008)
+#define ICFR                    (0x00c)
+#define ICPR                    (0x010)
+#define ICCR                    (0x014)
+#define ICHP                    (0x018)
+#define IPR(i)                  (((i) < 32) ? (0x01c + ((i) << 2)) :            \
+                                ((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) :      \
+                                      (0x144 + (((i) - 64) << 2)))
+#define IPR_VALID               (1 << 31)
+#define IRQ_BIT(n)              (((n) - PXA_IRQ(0)) & 0x1f)
 
-#define IRQ_BIT(n)      (((n) - PXA_IRQ(0)) & 0x1f)
-#define _ICMR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICMR2 : &ICMR))
-#define _ICLR(n)        (*((((n) - PXA_IRQ(0)) & ~0x1f) ? &ICLR2 : &ICLR))
+#define MAX_INTERNAL_IRQS       128
 
 /*
  * This is for peripheral IRQs internal to the PXA chip.
@@ -37,14 +48,27 @@
 
 static int pxa_internal_irq_nr;
 
+static inline int cpu_has_ipr(void)
+{
+        return !cpu_is_pxa25x();
+}
+
 static void pxa_mask_irq(unsigned int irq)
 {
-        _ICMR(irq) &= ~(1 << IRQ_BIT(irq));
+        void __iomem *base = get_irq_chip_data(irq);
+        uint32_t icmr = __raw_readl(base + ICMR);
+
+        icmr &= ~(1 << IRQ_BIT(irq));
+        __raw_writel(icmr, base + ICMR);
 }
 
 static void pxa_unmask_irq(unsigned int irq)
 {
-        _ICMR(irq) |= 1 << IRQ_BIT(irq);
+        void __iomem *base = get_irq_chip_data(irq);
+        uint32_t icmr = __raw_readl(base + ICMR);
+
+        icmr |= 1 << IRQ_BIT(irq);
+        __raw_writel(icmr, base + ICMR);
 }
 
 static struct irq_chip pxa_internal_irq_chip = {
@@ -86,12 +110,16 @@ static void pxa_ack_low_gpio(unsigned int irq)
 
 static void pxa_mask_low_gpio(unsigned int irq)
 {
-        ICMR &= ~(1 << (irq - PXA_IRQ(0)));
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        desc->chip->mask(irq);
 }
 
 static void pxa_unmask_low_gpio(unsigned int irq)
 {
-        ICMR |= 1 << (irq - PXA_IRQ(0));
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        desc->chip->unmask(irq);
 }
 
 static struct irq_chip pxa_low_gpio_chip = {
@@ -120,33 +148,45 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
         pxa_low_gpio_chip.set_wake = fn;
 }
 
+static inline void __iomem *irq_base(int i)
+{
+        static unsigned long phys_base[] = {
+                0x40d00000,
+                0x40d0009c,
+                0x40d00130,
+        };
+
+        return (void __iomem *)io_p2v(phys_base[i >> 5]);
+}
+
 void __init pxa_init_irq(int irq_nr, set_wake_t fn)
 {
-        int irq, i;
+        int irq, i, n;
 
         BUG_ON(irq_nr > MAX_INTERNAL_IRQS);
 
         pxa_internal_irq_nr = irq_nr;
 
-        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) {
-                _ICMR(irq) = 0; /* disable all IRQs */
-                _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */
-        }
-
-        /* initialize interrupt priority */
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
-                for (i = 0; i < irq_nr; i++)
-                        IPR(i) = i | (1 << 31);
+        for (n = 0; n < irq_nr; n += 32) {
+                void __iomem *base = irq_base(n);
+
+                __raw_writel(0, base + ICMR);   /* disable all IRQs */
+                __raw_writel(0, base + ICLR);   /* all IRQs are IRQ, not FIQ */
+                for (i = n; (i < (n + 32)) && (i < irq_nr); i++) {
+                        /* initialize interrupt priority */
+                        if (cpu_has_ipr())
+                                __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
+
+                        irq = PXA_IRQ(i);
+                        set_irq_chip(irq, &pxa_internal_irq_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID);
+                }
         }
 
         /* only unmasked interrupts kick us out of idle */
-        ICCR = 1;
-
-        for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) {
-                set_irq_chip(irq, &pxa_internal_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID);
-        }
+        __raw_writel(1, irq_base(0) + ICCR);
 
         pxa_internal_irq_chip.set_wake = fn;
         pxa_init_low_gpio_irq(fn);
@@ -158,16 +198,18 @@ static unsigned long saved_ipr[MAX_INTERNAL_IRQS];
 
 static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 {
-        int i, irq = PXA_IRQ(0);
+        int i;
 
-        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
-                saved_icmr[i] = _ICMR(irq);
-                _ICMR(irq) = 0;
+        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+                void __iomem *base = irq_base(i);
+
+                saved_icmr[i] = __raw_readl(base + ICMR);
+                __raw_writel(0, base + ICMR);
         }
 
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
+        if (cpu_has_ipr()) {
                 for (i = 0; i < pxa_internal_irq_nr; i++)
-                        saved_ipr[i] = IPR(i);
+                        saved_ipr[i] = __raw_readl(IRQ_BASE + IPR(i));
         }
 
         return 0;
@@ -175,19 +217,20 @@ static int pxa_irq_suspend(struct sys_device *dev, pm_message_t state)
 
 static int pxa_irq_resume(struct sys_device *dev)
 {
-        int i, irq = PXA_IRQ(0);
+        int i;
 
-        if (cpu_is_pxa27x() || cpu_is_pxa3xx()) {
-                for (i = 0; i < pxa_internal_irq_nr; i++)
-                        IPR(i) = saved_ipr[i];
-        }
+        for (i = 0; i < pxa_internal_irq_nr; i += 32) {
+                void __iomem *base = irq_base(i);
 
-        for (i = 0; irq < PXA_IRQ(pxa_internal_irq_nr); i++, irq += 32) {
-                _ICMR(irq) = saved_icmr[i];
-                _ICLR(irq) = 0;
+                __raw_writel(saved_icmr[i], base + ICMR);
+                __raw_writel(0, base + ICLR);
         }
 
-        ICCR = 1;
+        if (!cpu_is_pxa25x())
+                for (i = 0; i < pxa_internal_irq_nr; i++)
+                        __raw_writel(saved_ipr[i], IRQ_BASE + IPR(i));
+
+        __raw_writel(1, IRQ_BASE + ICCR);
         return 0;
 }
 #else
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 41aa89e35772..719c260597e7 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -438,7 +438,7 @@ static void __init littleton_init(void)
 
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = LITTLETON_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 623af0232a54..8ab62a677807 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -46,6 +46,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -463,7 +464,7 @@ static void __init lpd270_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        lpd270_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
+        lpd270_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         lpd270_flash_data[1].width = 4;
 
         /*
@@ -495,7 +496,7 @@ static struct map_desc lpd270_io_desc[] __initdata = {
 
 static void __init lpd270_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(lpd270_io_desc, ARRAY_SIZE(lpd270_io_desc));
 
         /* for use I SRAM as framebuffer.  */
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 1499493cd070..d3375486c8cd 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -50,6 +50,7 @@
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
 #include <mach/pm.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "clock.h"
@@ -525,7 +526,7 @@ static void __init lubbock_init(void)
         pxa_set_ac97_info(NULL);
 
         lubbock_flash_data[0].width = lubbock_flash_data[1].width =
-                (BOOT_DEF & 1) ? 2 : 4;
+                (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         /* Compensate for the nROMBT switch which swaps the flash banks */
         printk(KERN_NOTICE "Lubbock configured to boot from %s (bank %d)\n",
                flashboot?"Flash":"ROM", flashboot);
@@ -549,7 +550,7 @@ static struct map_desc lubbock_io_desc[] __initdata = {
 
 static void __init lubbock_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
         iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
 
         PCFR |= PCFR_OPDE;
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 90663760307a..41198f0dc3ac 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -765,7 +765,7 @@ static void __init magician_init(void)
 
 MACHINE_START(MAGICIAN, "HTC Magician")
         .boot_params = 0xa0000100,
-        .map_io = pxa_map_io,
+        .map_io = pxa27x_map_io,
         .nr_irqs = MAGICIAN_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .init_machine = magician_init,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index a980a5c93e49..740c03590e3b 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -51,6 +51,7 @@
 #include <mach/irda.h>
 #include <mach/ohci.h>
 #include <plat/pxa27x_keypad.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -565,7 +566,7 @@ static void __init mainstone_init(void)
         pxa_set_btuart_info(NULL);
         pxa_set_stuart_info(NULL);
 
-        mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
+        mst_flash_data[0].width = (__raw_readl(BOOT_DEF) & 1) ? 2 : 4;
         mst_flash_data[1].width = 4;
 
         /* Compensate for SW7 which swaps the flash banks */
@@ -614,7 +615,7 @@ static struct map_desc mainstone_io_desc[] __initdata = {
 
 static void __init mainstone_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 
         /*      for use I SRAM as framebuffer.  */
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index f5fb915e1315..faafea3542fb 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -819,7 +819,7 @@ static void mioa701_machine_exit(void)
 
 MACHINE_START(MIOA701, "MIO A701")
         .boot_params    = 0xa0000100,
-        .map_io         = &pxa_map_io,
+        .map_io         = &pxa27x_map_io,
         .init_irq       = &pxa27x_init_irq,
         .init_machine   = mioa701_machine_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 116167aaba68..59cce78aebd1 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -94,7 +94,7 @@ static void __init mp900c_init(void)
 MACHINE_START(NEC_MP900, "MobilePro900/C")
         .boot_params    = 0xa0220100,
         .timer          = &pxa_timer,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = mp900c_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index ce092c521e6d..a6f898cbfac9 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -313,7 +313,7 @@ static struct map_desc palmld_io_desc[] __initdata = {
 
 static void __init palmld_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 862da812cd10..df4d7d009fbb 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -203,7 +203,7 @@ static void __init palmt5_init(void)
 
 MACHINE_START(PALMT5, "Palm Tungsten|T5")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = palmt5_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 2131d5860919..a09a2374697b 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -25,6 +25,7 @@
 #include <linux/power_supply.h>
 #include <linux/gpio_keys.h>
 #include <linux/mtd/physmap.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -116,6 +117,7 @@ static unsigned long palmtc_pin_config[] __initdata = {
 /******************************************************************************
  * SD/MMC card controller
  ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 static struct pxamci_platform_data palmtc_mci_platform_data = {
         .ocr_mask               = MMC_VDD_32_33 | MMC_VDD_33_34,
         .gpio_power             = GPIO_NR_PALMTC_SD_POWER,
@@ -124,9 +126,18 @@ static struct pxamci_platform_data palmtc_mci_platform_data = {
         .detect_delay_ms        = 200,
 };
 
+static void __init palmtc_mmc_init(void)
+{
+        pxa_set_mci_info(&palmtc_mci_platform_data);
+}
+#else
+static inline void palmtc_mmc_init(void) {}
+#endif
+
 /******************************************************************************
  * GPIO keys
  ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 static struct gpio_keys_button palmtc_pxa_buttons[] = {
         {KEY_F8, GPIO_NR_PALMTC_HOTSYNC_BUTTON, 1, "HotSync Button", EV_KEY, 1},
 };
@@ -144,9 +155,18 @@ static struct platform_device palmtc_pxa_keys = {
         },
 };
 
+static void __init palmtc_keys_init(void)
+{
+        platform_device_register(&palmtc_pxa_keys);
+}
+#else
+static inline void palmtc_keys_init(void) {}
+#endif
+
 /******************************************************************************
  * Backlight
  ******************************************************************************/
+#if defined(CONFIG_BACKLIGHT_PWM) || defined(CONFIG_BACKLIGHT_PWM_MODULE)
 static int palmtc_backlight_init(struct device *dev)
 {
         int ret;
@@ -196,17 +216,35 @@ static struct platform_device palmtc_backlight = {
         },
 };
 
+static void __init palmtc_pwm_init(void)
+{
+        platform_device_register(&palmtc_backlight);
+}
+#else
+static inline void palmtc_pwm_init(void) {}
+#endif
+
 /******************************************************************************
  * IrDA
  ******************************************************************************/
+#if defined(CONFIG_IRDA) || defined(CONFIG_IRDA_MODULE)
 static struct pxaficp_platform_data palmtc_ficp_platform_data = {
         .gpio_pwdown            = GPIO_NR_PALMTC_IR_DISABLE,
         .transceiver_cap        = IR_SIRMODE | IR_OFF,
 };
 
+static void __init palmtc_irda_init(void)
+{
+        pxa_set_ficp_info(&palmtc_ficp_platform_data);
+}
+#else
+static inline void palmtc_irda_init(void) {}
+#endif
+
 /******************************************************************************
  * Keyboard
  ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 static const uint32_t palmtc_matrix_keys[] = {
         KEY(0, 0, KEY_F1),
         KEY(0, 1, KEY_X),
@@ -290,27 +328,103 @@ static struct platform_device palmtc_keyboard = {
                 .platform_data = &palmtc_keypad_platform_data,
         },
 };
+static void __init palmtc_mkp_init(void)
+{
+        platform_device_register(&palmtc_keyboard);
+}
+#else
+static inline void palmtc_mkp_init(void) {}
+#endif
 
 /******************************************************************************
  * UDC
  ******************************************************************************/
-static struct pxa2xx_udc_mach_info palmtc_udc_info __initdata = {
+#if defined(CONFIG_USB_GADGET_PXA25X)||defined(CONFIG_USB_GADGET_PXA25X_MODULE)
+static struct gpio_vbus_mach_info palmtc_udc_info = {
         .gpio_vbus              = GPIO_NR_PALMTC_USB_DETECT_N,
         .gpio_vbus_inverted     = 1,
         .gpio_pullup            = GPIO_NR_PALMTC_USB_POWER,
 };
 
+static struct platform_device palmtc_gpio_vbus = {
+        .name   = "gpio-vbus",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmtc_udc_info,
+        },
+};
+
+static void __init palmtc_udc_init(void)
+{
+        platform_device_register(&palmtc_gpio_vbus);
+};
+#else
+static inline void palmtc_udc_init(void) {}
+#endif
+
 /******************************************************************************
  * Touchscreen / Battery / GPIO-extender
  ******************************************************************************/
-static struct platform_device palmtc_ucb1400_core = {
+#if     defined(CONFIG_TOUCHSCREEN_UCB1400) || \
+        defined(CONFIG_TOUCHSCREEN_UCB1400_MODULE)
+static struct platform_device palmtc_ucb1400_device = {
         .name   = "ucb1400_core",
         .id     = -1,
 };
 
+static void __init palmtc_ts_init(void)
+{
+        pxa_set_ac97_info(NULL);
+        platform_device_register(&palmtc_ucb1400_device);
+}
+#else
+static inline void palmtc_ts_init(void) {}
+#endif
+
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+struct gpio_led palmtc_gpio_leds[] = {
+{
+        .name                   = "palmtc:green:user",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMTC_LED_POWER,
+        .active_low             = 1,
+}, {
+        .name                   = "palmtc:vibra:vibra",
+        .default_trigger        = "none",
+        .gpio                   = GPIO_NR_PALMTC_VIBRA_POWER,
+        .active_low             = 1,
+}
+
+};
+
+static struct gpio_led_platform_data palmtc_gpio_led_info = {
+        .leds           = palmtc_gpio_leds,
+        .num_leds       = ARRAY_SIZE(palmtc_gpio_leds),
+};
+
+static struct platform_device palmtc_leds = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &palmtc_gpio_led_info,
+        }
+};
+
+static void __init palmtc_leds_init(void)
+{
+        platform_device_register(&palmtc_leds);
+}
+#else
+static inline void palmtc_leds_init(void) {}
+#endif
+
 /******************************************************************************
  * NOR Flash
  ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
 static struct resource palmtc_flash_resource = {
         .start  = PXA_CS0_PHYS,
         .end    = PXA_CS0_PHYS + SZ_16M - 1,
@@ -356,24 +470,33 @@ static struct platform_device palmtc_flash = {
         },
 };
 
+static void __init palmtc_nor_init(void)
+{
+        platform_device_register(&palmtc_flash);
+}
+#else
+static inline void palmtc_nor_init(void) {}
+#endif
+
 /******************************************************************************
  * Framebuffer
  ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
 static struct pxafb_mode_info palmtc_lcd_modes[] = {
-{
-        .pixclock       = 115384,
-        .xres           = 320,
-        .yres           = 320,
-        .bpp            = 16,
-
-        .left_margin    = 27,
-        .right_margin   = 7,
-        .upper_margin   = 7,
-        .lower_margin   = 8,
-
-        .hsync_len      = 6,
-        .vsync_len      = 1,
-},
+        {
+                .pixclock       = 115384,
+                .xres           = 320,
+                .yres           = 320,
+                .bpp            = 16,
+
+                .left_margin    = 27,
+                .right_margin   = 7,
+                .upper_margin   = 7,
+                .lower_margin   = 8,
+
+                .hsync_len      = 6,
+                .vsync_len      = 1,
+        },
 };
 
 static struct pxafb_mach_info palmtc_lcd_screen = {
@@ -382,17 +505,17 @@ static struct pxafb_mach_info palmtc_lcd_screen = {
         .lcd_conn               = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
 };
 
+static void __init palmtc_lcd_init(void)
+{
+        set_pxa_fb_info(&palmtc_lcd_screen);
+}
+#else
+static inline void palmtc_lcd_init(void) {}
+#endif
+
 /******************************************************************************
  * Machine init
  ******************************************************************************/
-static struct platform_device *devices[] __initdata = {
-        &palmtc_backlight,
-        &palmtc_ucb1400_core,
-        &palmtc_keyboard,
-        &palmtc_pxa_keys,
-        &palmtc_flash,
-};
-
 static void __init palmtc_init(void)
 {
         pxa2xx_mfp_config(ARRAY_AND_SIZE(palmtc_pin_config));
@@ -402,18 +525,21 @@ static void __init palmtc_init(void)
         pxa_set_stuart_info(NULL);
         pxa_set_hwuart_info(NULL);
 
-        set_pxa_fb_info(&palmtc_lcd_screen);
-        pxa_set_mci_info(&palmtc_mci_platform_data);
-        pxa_set_udc_info(&palmtc_udc_info);
-        pxa_set_ac97_info(NULL);
-        pxa_set_ficp_info(&palmtc_ficp_platform_data);
-
-        platform_add_devices(devices, ARRAY_SIZE(devices));
+        palmtc_mmc_init();
+        palmtc_keys_init();
+        palmtc_pwm_init();
+        palmtc_irda_init();
+        palmtc_mkp_init();
+        palmtc_udc_init();
+        palmtc_ts_init();
+        palmtc_nor_init();
+        palmtc_lcd_init();
+        palmtc_leds_init();
 };
 
 MACHINE_START(PALMTC, "Palm Tungsten|C")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmtc_init
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index a9dae7bc35d9..3f25014a136c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -374,7 +374,7 @@ static void __init palmte2_init(void)
 
 MACHINE_START(PALMTE2, "Palm Tungsten|E2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmte2_init
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 00e2d7ba84ed..8aadad55fbe4 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -442,7 +442,7 @@ static void __init centro_init(void)
 
 MACHINE_START(TREO680, "Palm Treo 680")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
@@ -451,7 +451,7 @@ MACHINE_END
 
 MACHINE_START(CENTRO, "Palm Centro 685")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .reserve        = treo_reserve,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index d2060a1d1d68..595f002066cc 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -241,7 +241,8 @@ static inline void palmtx_keys_init(void) {}
 /******************************************************************************
  * NAND Flash
  ******************************************************************************/
-#if defined(CONFIG_MTD_NAND_GPIO) || defined(CONFIG_MTD_NAND_GPIO_MODULE)
+#if defined(CONFIG_MTD_NAND_PLATFORM) || \
+        defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 static void palmtx_nand_cmd_ctl(struct mtd_info *mtd, int cmd,
                                  unsigned int ctrl)
 {
@@ -333,7 +334,7 @@ static struct map_desc palmtx_io_desc[] __initdata = {
 
 static void __init palmtx_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(palmtx_io_desc, ARRAY_SIZE(palmtx_io_desc));
 }
 
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index af6203fbca9c..7bf4017326e3 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -280,7 +280,7 @@ static void __init palmz72_init(void)
 
 MACHINE_START(PALMZ72, "Palm Zire72")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = palmz72_init
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index c77e8f30a439..8547c9abc40a 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -244,7 +244,7 @@ static void __init pcm027_init(void)
 
 static void __init pcm027_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
 
         /* initialize sleep mode regs (wake-up sources, etc) */
         PGSR0 = 0x01308000;
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 93a191c889df..8451790cb48d 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -466,7 +466,7 @@ static void __init fixup_poodle(struct machine_desc *desc,
 
 MACHINE_START(POODLE, "SHARP Poodle")
         .fixup          = fixup_poodle,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = POODLE_NR_IRQS,       /* 4 for LoCoMo */
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index de53f2e4aa39..3f5241c84894 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -23,6 +23,7 @@
 #include <linux/suspend.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
@@ -30,6 +31,7 @@
 #include <mach/reset.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -90,23 +92,21 @@ unsigned int pxa25x_get_clk_frequency_khz(int info)
         return (turbo & 1) ? (N/1000) : (M/1000);
 }
 
-/*
- * Return the current memory clock frequency in units of 10kHz
- */
-unsigned int pxa25x_get_memclk_frequency_10khz(void)
+static unsigned long clk_pxa25x_mem_getrate(struct clk *clk)
 {
-        return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
+        return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK;
 }
 
-static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
-{
-        return pxa25x_get_memclk_frequency_10khz() * 10000;
-}
+static const struct clkops clk_pxa25x_mem_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+        .getrate        = clk_pxa25x_mem_getrate,
+};
 
 static const struct clkops clk_pxa25x_lcd_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
-        .getrate        = clk_pxa25x_lcd_getrate,
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
+        .getrate        = clk_pxa25x_mem_getrate,
 };
 
 static unsigned long gpio12_config_32k[] = {
@@ -160,31 +160,30 @@ static const struct clkops clk_pxa25x_gpio11_ops = {
  * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
  * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
  */
-static DEFINE_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
-
-static struct clk_lookup pxa25x_hwuart_clkreg =
-        INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
 
 /*
  * PXA 2xx clock declarations.
  */
+static DEFINE_PXA2_CKEN(pxa25x_hwuart, HWUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_stuart, STUART, 14745600, 1);
+static DEFINE_PXA2_CKEN(pxa25x_usb, USB, 47923000, 5);
+static DEFINE_PXA2_CKEN(pxa25x_mmc, MMC, 19169000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_i2c, I2C, 31949000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ssp, SSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_assp, ASSP, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ac97, AC97, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa25x_i2s, I2S, 14745600, 0);
+static DEFINE_PXA2_CKEN(pxa25x_ficp, FICP, 47923000, 0);
+
 static DEFINE_CK(pxa25x_lcd, LCD, &clk_pxa25x_lcd_ops);
-static DEFINE_CKEN(pxa25x_ffuart, FFUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_btuart, BTUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_stuart, STUART, 14745600, 1);
-static DEFINE_CKEN(pxa25x_usb, USB, 47923000, 5);
 static DEFINE_CLK(pxa25x_gpio11, &clk_pxa25x_gpio11_ops, 3686400, 0);
 static DEFINE_CLK(pxa25x_gpio12, &clk_pxa25x_gpio12_ops, 32768, 0);
-static DEFINE_CKEN(pxa25x_mmc, MMC, 19169000, 0);
-static DEFINE_CKEN(pxa25x_i2c, I2C, 31949000, 0);
-static DEFINE_CKEN(pxa25x_ssp, SSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_nssp, NSSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_assp, ASSP, 3686400, 0);
-static DEFINE_CKEN(pxa25x_pwm0, PWM0, 3686400, 0);
-static DEFINE_CKEN(pxa25x_pwm1, PWM1, 3686400, 0);
-static DEFINE_CKEN(pxa25x_ac97, AC97, 24576000, 0);
-static DEFINE_CKEN(pxa25x_i2s, I2S, 14745600, 0);
-static DEFINE_CKEN(pxa25x_ficp, FICP, 47923000, 0);
+static DEFINE_CLK(pxa25x_mem, &clk_pxa25x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_lcd, "pxa2xx-fb", NULL),
@@ -205,8 +204,12 @@ static struct clk_lookup pxa25x_clkregs[] = {
         INIT_CLKREG(&clk_pxa25x_ac97, NULL, "AC97CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
         INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
+        INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
 };
 
+static struct clk_lookup pxa25x_hwuart_clkreg =
+        INIT_CLKREG(&clk_pxa25x_hwuart, "pxa2xx-uart.3", NULL);
+
 #ifdef CONFIG_PM
 
 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
@@ -219,20 +222,17 @@ static struct clk_lookup pxa25x_clkregs[] = {
  */
 enum {
         SLEEP_SAVE_PSTR,
-        SLEEP_SAVE_CKEN,
         SLEEP_SAVE_COUNT
 };
 
 
 static void pxa25x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(CKEN);
         SAVE(PSTR);
 }
 
 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        RESTORE(CKEN);
         RESTORE(PSTR);
 }
 
@@ -320,6 +320,22 @@ void __init pxa26x_init_irq(void)
 }
 #endif
 
+static struct map_desc pxa25x_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        },
+};
+
+void __init pxa25x_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc));
+        pxa25x_get_clk_frequency_khz(1);
+}
+
 static struct platform_device *pxa25x_devices[] __initdata = {
         &pxa25x_device_udc,
         &pxa_device_pmu,
@@ -339,7 +355,9 @@ static struct sys_device pxa25x_sysdev[] = {
                 .cls    = &pxa2xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa2xx_clock_sysclass,
+        }
 };
 
 static int __init pxa25x_init(void)
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index d1fbf29d561c..b2130b7a7b52 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -17,7 +17,9 @@
 #include <linux/suspend.h>
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
+#include <linux/io.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
@@ -27,6 +29,8 @@
 #include <mach/ohci.h>
 #include <mach/pm.h>
 #include <mach/dma.h>
+#include <mach/smemc.h>
+
 #include <plat/i2c.h>
 
 #include "generic.h"
@@ -107,10 +111,9 @@ unsigned int pxa27x_get_clk_frequency_khz(int info)
 }
 
 /*
- * Return the current mem clock frequency in units of 10kHz as
- * reflected by CCCR[A], B, and L
+ * Return the current mem clock frequency as reflected by CCCR[A], B, and L
  */
-unsigned int pxa27x_get_memclk_frequency_10khz(void)
+static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
 {
         unsigned long ccsr, clkcfg;
         unsigned int l, L, m, M;
@@ -129,9 +132,15 @@ unsigned int pxa27x_get_memclk_frequency_10khz(void)
         L = l * BASE_CLK;
         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 
-        return (M / 10000);
+        return M;
 }
 
+static const struct clkops clk_pxa27x_mem_ops = {
+        .enable         = clk_dummy_enable,
+        .disable        = clk_dummy_disable,
+        .getrate        = clk_pxa27x_mem_getrate,
+};
+
 /*
  * Return the current LCD clock frequency in units of 10kHz as
  */
@@ -157,36 +166,38 @@ static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 }
 
 static const struct clkops clk_pxa27x_lcd_ops = {
-        .enable         = clk_cken_enable,
-        .disable        = clk_cken_disable,
+        .enable         = clk_pxa2xx_cken_enable,
+        .disable        = clk_pxa2xx_cken_disable,
         .getrate        = clk_pxa27x_lcd_getrate,
 };
 
+static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
+static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
+static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
+static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
+static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
+
 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
-static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
-static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
-static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
-static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
-static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
-static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
-static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
-static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
-static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
-static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
-static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
-static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
-static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
-static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
-static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
-static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
-static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
-static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
-static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
+static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
 
 static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
@@ -215,6 +226,7 @@ static struct clk_lookup pxa27x_clkregs[] = {
         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
+        INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -246,7 +258,6 @@ int __init pxa27x_set_pwrmode(unsigned int mode)
  */
 enum {
         SLEEP_SAVE_PSTR,
-        SLEEP_SAVE_CKEN,
         SLEEP_SAVE_MDREFR,
         SLEEP_SAVE_PCFR,
         SLEEP_SAVE_COUNT
@@ -254,21 +265,19 @@ enum {
 
 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 {
-        SAVE(MDREFR);
+        sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
         SAVE(PCFR);
 
-        SAVE(CKEN);
         SAVE(PSTR);
 }
 
 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 {
-        RESTORE(MDREFR);
+        __raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
         RESTORE(PCFR);
 
         PSSR = PSSR_RDH | PSSR_PH;
 
-        RESTORE(CKEN);
         RESTORE(PSTR);
 }
 
@@ -370,6 +379,27 @@ void __init pxa27x_init_irq(void)
         pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake);
 }
 
+static struct map_desc pxa27x_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA2XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        }, {    /* IMem ctl */
+                .virtual        =  0xfe000000,
+                .pfn            = __phys_to_pfn(0x58000000),
+                .length         = 0x00100000,
+                .type           = MT_DEVICE
+        },
+};
+
+void __init pxa27x_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
+        pxa27x_get_clk_frequency_khz(1);
+}
+
 /*
  * device registration specific to PXA27x.
  */
@@ -405,7 +435,9 @@ static struct sys_device pxa27x_sysdev[] = {
                 .cls    = &pxa2xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa2xx_clock_sysclass,
+        }
 };
 
 static int __init pxa27x_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index d1c747cdacf8..e14818f5d950 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/gpio.h>
 #include <mach/pxa3xx-regs.h>
@@ -30,193 +31,16 @@
 #include <mach/pm.h>
 #include <mach/dma.h>
 #include <mach/regs-intc.h>
+#include <mach/smemc.h>
 #include <plat/i2c.h>
 
 #include "generic.h"
 #include "devices.h"
 #include "clock.h"
 
-/* Crystal clock: 13MHz */
-#define BASE_CLK        13000000
-
-/* Ring Oscillator Clock: 60MHz */
-#define RO_CLK          60000000
-
-#define ACCR_D0CS       (1 << 26)
-#define ACCR_PCCE       (1 << 11)
-
 #define PECR_IE(n)      ((1 << ((n) * 2)) << 28)
 #define PECR_IS(n)      ((1 << ((n) * 2)) << 29)
 
-/* crystal frequency to static memory controller multiplier (SMCFS) */
-static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
-
-/* crystal frequency to HSIO bus frequency multiplier (HSS) */
-static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
-
-/*
- * Get the clock frequency as reflected by CCSR and the turbo flag.
- * We assume these values have been applied via a fcs.
- * If info is not 0 we also display the current settings.
- */
-unsigned int pxa3xx_get_clk_frequency_khz(int info)
-{
-        unsigned long acsr, xclkcfg;
-        unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
-
-        /* Read XCLKCFG register turbo bit */
-        __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
-        t = xclkcfg & 0x1;
-
-        acsr = ACSR;
-
-        xl  = acsr & 0x1f;
-        xn  = (acsr >> 8) & 0x7;
-        hss = (acsr >> 14) & 0x3;
-
-        XL = xl * BASE_CLK;
-        XN = xn * XL;
-
-        ro = acsr & ACCR_D0CS;
-
-        CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
-        HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
-
-        if (info) {
-                pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
-                        RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
-                        (ro) ? "" : "in");
-                pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
-                        XL / 1000000, (XL % 1000000) / 10000, xl);
-                pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
-                        XN / 1000000, (XN % 1000000) / 10000, xn,
-                        (t) ? "" : "in");
-                pr_info("HSIO bus clock: %d.%02dMHz\n",
-                        HSS / 1000000, (HSS % 1000000) / 10000);
-        }
-
-        return CLK / 1000;
-}
-
-void pxa3xx_clear_reset_status(unsigned int mask)
-{
-        /* RESET_STATUS_* has a 1:1 mapping with ARSR */
-        ARSR = mask;
-}
-
-/*
- * Return the current AC97 clock frequency.
- */
-static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
-{
-        unsigned long rate = 312000000;
-        unsigned long ac97_div;
-
-        ac97_div = AC97_DIV;
-
-        /* This may loose precision for some rates but won't for the
-         * standard 24.576MHz.
-         */
-        rate /= (ac97_div >> 12) & 0x7fff;
-        rate *= (ac97_div & 0xfff);
-
-        return rate;
-}
-
-/*
- * Return the current HSIO bus clock frequency
- */
-static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
-{
-        unsigned long acsr;
-        unsigned int hss, hsio_clk;
-
-        acsr = ACSR;
-
-        hss = (acsr >> 14) & 0x3;
-        hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
-
-        return hsio_clk;
-}
-
-void clk_pxa3xx_cken_enable(struct clk *clk)
-{
-        unsigned long mask = 1ul << (clk->cken & 0x1f);
-
-        if (clk->cken < 32)
-                CKENA |= mask;
-        else
-                CKENB |= mask;
-}
-
-void clk_pxa3xx_cken_disable(struct clk *clk)
-{
-        unsigned long mask = 1ul << (clk->cken & 0x1f);
-
-        if (clk->cken < 32)
-                CKENA &= ~mask;
-        else
-                CKENB &= ~mask;
-}
-
-const struct clkops clk_pxa3xx_cken_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-};
-
-static const struct clkops clk_pxa3xx_hsio_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-        .getrate        = clk_pxa3xx_hsio_getrate,
-};
-
-static const struct clkops clk_pxa3xx_ac97_ops = {
-        .enable         = clk_pxa3xx_cken_enable,
-        .disable        = clk_pxa3xx_cken_disable,
-        .getrate        = clk_pxa3xx_ac97_getrate,
-};
-
-static void clk_pout_enable(struct clk *clk)
-{
-        OSCC |= OSCC_PEN;
-}
-
-static void clk_pout_disable(struct clk *clk)
-{
-        OSCC &= ~OSCC_PEN;
-}
-
-static const struct clkops clk_pout_ops = {
-        .enable         = clk_pout_enable,
-        .disable        = clk_pout_disable,
-};
-
-static void clk_dummy_enable(struct clk *clk)
-{
-}
-
-static void clk_dummy_disable(struct clk *clk)
-{
-}
-
-static const struct clkops clk_dummy_ops = {
-        .enable         = clk_dummy_enable,
-        .disable        = clk_dummy_disable,
-};
-
-static struct clk clk_pxa3xx_pout = {
-        .ops            = &clk_pout_ops,
-        .rate           = 13000000,
-        .delay          = 70,
-};
-
-static struct clk clk_dummy = {
-        .ops            = &clk_dummy_ops,
-};
-
-static DEFINE_PXA3_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
-static DEFINE_PXA3_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
-static DEFINE_PXA3_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
 static DEFINE_PXA3_CKEN(pxa3xx_ffuart, FFUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_btuart, BTUART, 14857000, 1);
 static DEFINE_PXA3_CKEN(pxa3xx_stuart, STUART, 14857000, 1);
@@ -234,6 +58,12 @@ static DEFINE_PXA3_CKEN(pxa3xx_pwm1, PWM1, 13000000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc1, MMC1, 19500000, 0);
 static DEFINE_PXA3_CKEN(pxa3xx_mmc2, MMC2, 19500000, 0);
 
+static DEFINE_CK(pxa3xx_lcd, LCD, &clk_pxa3xx_hsio_ops);
+static DEFINE_CK(pxa3xx_smemc, SMC, &clk_pxa3xx_smemc_ops);
+static DEFINE_CK(pxa3xx_camera, CAMERA, &clk_pxa3xx_hsio_ops);
+static DEFINE_CK(pxa3xx_ac97, AC97, &clk_pxa3xx_ac97_ops);
+static DEFINE_CLK(pxa3xx_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
+
 static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
         /* Power I2C clock is always on */
@@ -258,6 +88,7 @@ static struct clk_lookup pxa3xx_clkregs[] = {
         INIT_CLKREG(&clk_pxa3xx_pwm1, "pxa27x-pwm.1", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc1, "pxa2xx-mci.0", NULL),
         INIT_CLKREG(&clk_pxa3xx_mmc2, "pxa2xx-mci.1", NULL),
+        INIT_CLKREG(&clk_pxa3xx_smemc, "pxa2xx-pcmcia", NULL),
 };
 
 #ifdef CONFIG_PM
@@ -268,30 +99,6 @@ static struct clk_lookup pxa3xx_clkregs[] = {
 static void __iomem *sram;
 static unsigned long wakeup_src;
 
-#define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
-#define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
-
-enum {  SLEEP_SAVE_CKENA,
-        SLEEP_SAVE_CKENB,
-        SLEEP_SAVE_ACCR,
-
-        SLEEP_SAVE_COUNT,
-};
-
-static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
-{
-        SAVE(CKENA);
-        SAVE(CKENB);
-        SAVE(ACCR);
-}
-
-static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
-{
-        RESTORE(ACCR);
-        RESTORE(CKENA);
-        RESTORE(CKENB);
-}
-
 /*
  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
  * memory controller has to be reinitialised, so we place some code
@@ -390,9 +197,6 @@ static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 }
 
 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
-        .save_count     = SLEEP_SAVE_COUNT,
-        .save           = pxa3xx_cpu_pm_save,
-        .restore        = pxa3xx_cpu_pm_restore,
         .valid          = pxa3xx_cpu_pm_valid,
         .enter          = pxa3xx_cpu_pm_enter,
 };
@@ -580,6 +384,22 @@ void __init pxa3xx_init_irq(void)
         pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
 }
 
+static struct map_desc pxa3xx_io_desc[] __initdata = {
+        {       /* Mem Ctl */
+                .virtual        = SMEMC_VIRT,
+                .pfn            = __phys_to_pfn(PXA3XX_SMEMC_BASE),
+                .length         = 0x00200000,
+                .type           = MT_DEVICE
+        }
+};
+
+void __init pxa3xx_map_io(void)
+{
+        pxa_map_io();
+        iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
+        pxa3xx_get_clk_frequency_khz(1);
+}
+
 /*
  * device registration specific to PXA3xx.
  */
@@ -615,7 +435,9 @@ static struct sys_device pxa3xx_sysdev[] = {
                 .cls    = &pxa3xx_mfp_sysclass,
         }, {
                 .cls    = &pxa_gpio_sysclass,
-        },
+        }, {
+                .cls    = &pxa3xx_clock_sysclass,
+        }
 };
 
 static int __init pxa3xx_init(void)
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c
index 7d29dd3af79d..8aeacf908784 100644
--- a/arch/arm/mach-pxa/pxa930.c
+++ b/arch/arm/mach-pxa/pxa930.c
@@ -192,7 +192,7 @@ static struct mfp_addr_map pxa935_mfp_addr_map[] __initdata = {
 
 static int __init pxa930_init(void)
 {
-        if (cpu_is_pxa930() || cpu_is_pxa935() || cpu_is_pxa950()) {
+        if (cpu_is_pxa93x()) {
                 mfp_init_base(io_p2v(MFPR_BASE));
                 mfp_init_addr(pxa930_mfp_addr_map);
         }
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
new file mode 100644
index 000000000000..437980f72710
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -0,0 +1,308 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa95x.c
+ *
+ * code specific to PXA95x aka MGx
+ *
+ * Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/pxa930.h>
+#include <mach/reset.h>
+#include <mach/pm.h>
+#include <mach/dma.h>
+#include <mach/regs-intc.h>
+#include <plat/i2c.h>
+
+#include "generic.h"
+#include "devices.h"
+#include "clock.h"
+
+static struct mfp_addr_map pxa95x_mfp_addr_map[] __initdata = {
+
+        MFP_ADDR(GPIO0, 0x02e0),
+        MFP_ADDR(GPIO1, 0x02dc),
+        MFP_ADDR(GPIO2, 0x02e8),
+        MFP_ADDR(GPIO3, 0x02d8),
+        MFP_ADDR(GPIO4, 0x02e4),
+        MFP_ADDR(GPIO5, 0x02ec),
+        MFP_ADDR(GPIO6, 0x02f8),
+        MFP_ADDR(GPIO7, 0x02fc),
+        MFP_ADDR(GPIO8, 0x0300),
+        MFP_ADDR(GPIO9, 0x02d4),
+        MFP_ADDR(GPIO10, 0x02f4),
+        MFP_ADDR(GPIO11, 0x02f0),
+        MFP_ADDR(GPIO12, 0x0304),
+        MFP_ADDR(GPIO13, 0x0310),
+        MFP_ADDR(GPIO14, 0x0308),
+        MFP_ADDR(GPIO15, 0x030c),
+        MFP_ADDR(GPIO16, 0x04e8),
+        MFP_ADDR(GPIO17, 0x04f4),
+        MFP_ADDR(GPIO18, 0x04f8),
+        MFP_ADDR(GPIO19, 0x04fc),
+        MFP_ADDR(GPIO20, 0x0518),
+        MFP_ADDR(GPIO21, 0x051c),
+        MFP_ADDR(GPIO22, 0x04ec),
+        MFP_ADDR(GPIO23, 0x0500),
+        MFP_ADDR(GPIO24, 0x04f0),
+        MFP_ADDR(GPIO25, 0x0504),
+        MFP_ADDR(GPIO26, 0x0510),
+        MFP_ADDR(GPIO27, 0x0514),
+        MFP_ADDR(GPIO28, 0x0520),
+        MFP_ADDR(GPIO29, 0x0600),
+        MFP_ADDR(GPIO30, 0x0618),
+        MFP_ADDR(GPIO31, 0x0610),
+        MFP_ADDR(GPIO32, 0x060c),
+        MFP_ADDR(GPIO33, 0x061c),
+        MFP_ADDR(GPIO34, 0x0620),
+        MFP_ADDR(GPIO35, 0x0628),
+        MFP_ADDR(GPIO36, 0x062c),
+        MFP_ADDR(GPIO37, 0x0630),
+        MFP_ADDR(GPIO38, 0x0634),
+        MFP_ADDR(GPIO39, 0x0638),
+        MFP_ADDR(GPIO40, 0x063c),
+        MFP_ADDR(GPIO41, 0x0614),
+        MFP_ADDR(GPIO42, 0x0624),
+        MFP_ADDR(GPIO43, 0x0608),
+        MFP_ADDR(GPIO44, 0x0604),
+        MFP_ADDR(GPIO45, 0x050c),
+        MFP_ADDR(GPIO46, 0x0508),
+        MFP_ADDR(GPIO47, 0x02bc),
+        MFP_ADDR(GPIO48, 0x02b4),
+        MFP_ADDR(GPIO49, 0x02b8),
+        MFP_ADDR(GPIO50, 0x02c8),
+        MFP_ADDR(GPIO51, 0x02c0),
+        MFP_ADDR(GPIO52, 0x02c4),
+        MFP_ADDR(GPIO53, 0x02d0),
+        MFP_ADDR(GPIO54, 0x02cc),
+        MFP_ADDR(GPIO55, 0x029c),
+        MFP_ADDR(GPIO56, 0x02a0),
+        MFP_ADDR(GPIO57, 0x0294),
+        MFP_ADDR(GPIO58, 0x0298),
+        MFP_ADDR(GPIO59, 0x02a4),
+        MFP_ADDR(GPIO60, 0x02a8),
+        MFP_ADDR(GPIO61, 0x02b0),
+        MFP_ADDR(GPIO62, 0x02ac),
+        MFP_ADDR(GPIO63, 0x0640),
+        MFP_ADDR(GPIO64, 0x065c),
+        MFP_ADDR(GPIO65, 0x0648),
+        MFP_ADDR(GPIO66, 0x0644),
+        MFP_ADDR(GPIO67, 0x0674),
+        MFP_ADDR(GPIO68, 0x0658),
+        MFP_ADDR(GPIO69, 0x0654),
+        MFP_ADDR(GPIO70, 0x0660),
+        MFP_ADDR(GPIO71, 0x0668),
+        MFP_ADDR(GPIO72, 0x0664),
+        MFP_ADDR(GPIO73, 0x0650),
+        MFP_ADDR(GPIO74, 0x066c),
+        MFP_ADDR(GPIO75, 0x064c),
+        MFP_ADDR(GPIO76, 0x0670),
+        MFP_ADDR(GPIO77, 0x0678),
+        MFP_ADDR(GPIO78, 0x067c),
+        MFP_ADDR(GPIO79, 0x0694),
+        MFP_ADDR(GPIO80, 0x069c),
+        MFP_ADDR(GPIO81, 0x06a0),
+        MFP_ADDR(GPIO82, 0x06a4),
+        MFP_ADDR(GPIO83, 0x0698),
+        MFP_ADDR(GPIO84, 0x06bc),
+        MFP_ADDR(GPIO85, 0x06b4),
+        MFP_ADDR(GPIO86, 0x06b0),
+        MFP_ADDR(GPIO87, 0x06c0),
+        MFP_ADDR(GPIO88, 0x06c4),
+        MFP_ADDR(GPIO89, 0x06ac),
+        MFP_ADDR(GPIO90, 0x0680),
+        MFP_ADDR(GPIO91, 0x0684),
+        MFP_ADDR(GPIO92, 0x0688),
+        MFP_ADDR(GPIO93, 0x0690),
+        MFP_ADDR(GPIO94, 0x068c),
+        MFP_ADDR(GPIO95, 0x06a8),
+        MFP_ADDR(GPIO96, 0x06b8),
+        MFP_ADDR(GPIO97, 0x0410),
+        MFP_ADDR(GPIO98, 0x0418),
+        MFP_ADDR(GPIO99, 0x041c),
+        MFP_ADDR(GPIO100, 0x0414),
+        MFP_ADDR(GPIO101, 0x0408),
+        MFP_ADDR(GPIO102, 0x0324),
+        MFP_ADDR(GPIO103, 0x040c),
+        MFP_ADDR(GPIO104, 0x0400),
+        MFP_ADDR(GPIO105, 0x0328),
+        MFP_ADDR(GPIO106, 0x0404),
+
+        MFP_ADDR(GPIO159, 0x0524),
+        MFP_ADDR(GPIO163, 0x0534),
+        MFP_ADDR(GPIO167, 0x0544),
+        MFP_ADDR(GPIO168, 0x0548),
+        MFP_ADDR(GPIO169, 0x054c),
+        MFP_ADDR(GPIO170, 0x0550),
+        MFP_ADDR(GPIO171, 0x0554),
+        MFP_ADDR(GPIO172, 0x0558),
+        MFP_ADDR(GPIO173, 0x055c),
+
+        MFP_ADDR(nXCVREN, 0x0204),
+        MFP_ADDR(DF_CLE_nOE, 0x020c),
+        MFP_ADDR(DF_nADV1_ALE, 0x0218),
+        MFP_ADDR(DF_SCLK_E, 0x0214),
+        MFP_ADDR(DF_SCLK_S, 0x0210),
+        MFP_ADDR(nBE0, 0x021c),
+        MFP_ADDR(nBE1, 0x0220),
+        MFP_ADDR(DF_nADV2_ALE, 0x0224),
+        MFP_ADDR(DF_INT_RnB, 0x0228),
+        MFP_ADDR(DF_nCS0, 0x022c),
+        MFP_ADDR(DF_nCS1, 0x0230),
+        MFP_ADDR(nLUA, 0x0254),
+        MFP_ADDR(nLLA, 0x0258),
+        MFP_ADDR(DF_nWE, 0x0234),
+        MFP_ADDR(DF_nRE_nOE, 0x0238),
+        MFP_ADDR(DF_ADDR0, 0x024c),
+        MFP_ADDR(DF_ADDR1, 0x0250),
+        MFP_ADDR(DF_ADDR2, 0x025c),
+        MFP_ADDR(DF_ADDR3, 0x0260),
+        MFP_ADDR(DF_IO0, 0x023c),
+        MFP_ADDR(DF_IO1, 0x0240),
+        MFP_ADDR(DF_IO2, 0x0244),
+        MFP_ADDR(DF_IO3, 0x0248),
+        MFP_ADDR(DF_IO4, 0x0264),
+        MFP_ADDR(DF_IO5, 0x0268),
+        MFP_ADDR(DF_IO6, 0x026c),
+        MFP_ADDR(DF_IO7, 0x0270),
+        MFP_ADDR(DF_IO8, 0x0274),
+        MFP_ADDR(DF_IO9, 0x0278),
+        MFP_ADDR(DF_IO10, 0x027c),
+        MFP_ADDR(DF_IO11, 0x0280),
+        MFP_ADDR(DF_IO12, 0x0284),
+        MFP_ADDR(DF_IO13, 0x0288),
+        MFP_ADDR(DF_IO14, 0x028c),
+        MFP_ADDR(DF_IO15, 0x0290),
+
+        MFP_ADDR(GSIM_UIO, 0x0314),
+        MFP_ADDR(GSIM_UCLK, 0x0318),
+        MFP_ADDR(GSIM_UDET, 0x031c),
+        MFP_ADDR(GSIM_nURST, 0x0320),
+
+        MFP_ADDR(PMIC_INT, 0x06c8),
+
+        MFP_ADDR(RDY, 0x0200),
+
+        MFP_ADDR_END,
+};
+
+static DEFINE_CK(pxa95x_lcd, LCD, &clk_pxa3xx_hsio_ops);
+static DEFINE_CLK(pxa95x_pout, &clk_pxa3xx_pout_ops, 13000000, 70);
+static DEFINE_PXA3_CKEN(pxa95x_ffuart, FFUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_btuart, BTUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_stuart, STUART, 14857000, 1);
+static DEFINE_PXA3_CKEN(pxa95x_i2c, I2C, 32842000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_keypad, KEYPAD, 32768, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp1, SSP1, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp2, SSP2, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp3, SSP3, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_ssp4, SSP4, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_pwm0, PWM0, 13000000, 0);
+static DEFINE_PXA3_CKEN(pxa95x_pwm1, PWM1, 13000000, 0);
+
+static struct clk_lookup pxa95x_clkregs[] = {
+        INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
+        /* Power I2C clock is always on */
+        INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
+        INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-uart.2", NULL),
+        INIT_CLKREG(&clk_pxa95x_stuart, "pxa2xx-ir", "UARTCLK"),
+        INIT_CLKREG(&clk_pxa95x_i2c, "pxa2xx-i2c.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_keypad, "pxa27x-keypad", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp1, "pxa27x-ssp.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp2, "pxa27x-ssp.1", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp3, "pxa27x-ssp.2", NULL),
+        INIT_CLKREG(&clk_pxa95x_ssp4, "pxa27x-ssp.3", NULL),
+        INIT_CLKREG(&clk_pxa95x_pwm0, "pxa27x-pwm.0", NULL),
+        INIT_CLKREG(&clk_pxa95x_pwm1, "pxa27x-pwm.1", NULL),
+};
+
+void __init pxa95x_init_irq(void)
+{
+        pxa_init_irq(96, NULL);
+        pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL);
+}
+
+/*
+ * device registration specific to PXA93x.
+ */
+
+void __init pxa95x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
+{
+        pxa_register_device(&pxa3xx_device_i2c_power, info);
+}
+
+static struct platform_device *devices[] __initdata = {
+        &sa1100_device_rtc,
+        &pxa_device_rtc,
+        &pxa27x_device_ssp1,
+        &pxa27x_device_ssp2,
+        &pxa27x_device_ssp3,
+        &pxa3xx_device_ssp4,
+        &pxa27x_device_pwm0,
+        &pxa27x_device_pwm1,
+};
+
+static struct sys_device pxa95x_sysdev[] = {
+        {
+                .cls    = &pxa_irq_sysclass,
+        }, {
+                .cls    = &pxa_gpio_sysclass,
+        }, {
+                .cls    = &pxa3xx_clock_sysclass,
+        }
+};
+
+static int __init pxa95x_init(void)
+{
+        int ret = 0, i;
+
+        if (cpu_is_pxa95x()) {
+                mfp_init_base(io_p2v(MFPR_BASE));
+                mfp_init_addr(pxa95x_mfp_addr_map);
+
+                reset_status = ARSR;
+
+                /*
+                 * clear RDH bit every time after reset
+                 *
+                 * Note: the last 3 bits DxS are write-1-to-clear so carefully
+                 * preserve them here in case they will be referenced later
+                 */
+                ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
+
+                clkdev_add_table(pxa95x_clkregs, ARRAY_SIZE(pxa95x_clkregs));
+
+                if ((ret = pxa_init_dma(IRQ_DMA, 32)))
+                        return ret;
+
+                for (i = 0; i < ARRAY_SIZE(pxa95x_sysdev); i++) {
+                        ret = sysdev_register(&pxa95x_sysdev[i]);
+                        if (ret)
+                                pr_err("failed to register sysdev[%d]\n", i);
+                }
+
+                ret = platform_add_devices(devices, ARRAY_SIZE(devices));
+        }
+
+        return ret;
+}
+
+postcore_initcall(pxa95x_init);
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 4121d03ea2c3..8361151be054 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -588,6 +588,9 @@ static struct pxafb_mach_info raumfeld_sharp_lcd_info = {
         .num_modes      = 1,
         .video_mem_size = 0x400000,
         .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL,
+#ifdef CONFIG_PXA3XX_GCU
+        .acceleration_enabled = 1,
+#endif
 };
 
 static void __init raumfeld_lcd_init(void)
@@ -616,6 +619,8 @@ static void __init raumfeld_lcd_init(void)
                 pr_warning("Unable to request GPIO_DISPLAY_ENABLE\n");
         else
                 gpio_direction_output(GPIO_DISPLAY_ENABLE, 1);
+
+        platform_device_register(&pxa3xx_device_gcu);
 }
 
 /**
@@ -1085,7 +1090,7 @@ static void __init raumfeld_speaker_init(void)
 MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_controller_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -1095,7 +1100,7 @@ MACHINE_END
 MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_connector_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
@@ -1105,7 +1110,7 @@ MACHINE_END
 MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
         .boot_params    = RAUMFELD_SDRAM_BASE + 0x100,
         .init_machine   = raumfeld_speaker_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index ffa50e633ee6..c1ca8cb467fc 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -597,7 +597,7 @@ static void __init saar_init(void)
 MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = saar_init,
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
new file mode 100644
index 000000000000..e497922f761a
--- /dev/null
+++ b/arch/arm/mach-pxa/saarb.c
@@ -0,0 +1,114 @@
+/*
+ *  linux/arch/arm/mach-pxa/saarb.c
+ *
+ *  Support for the Marvell Handheld Platform (aka SAARB)
+ *
+ *  Copyright (C) 2007-2010 Marvell International Ltd.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/mfd/88pm860x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/mfp.h>
+#include <mach/mfp-pxa930.h>
+#include <mach/gpio.h>
+
+#include <plat/i2c.h>
+
+#include "generic.h"
+
+#define SAARB_NR_IRQS   (IRQ_BOARD_START + 40)
+
+static struct pm860x_touch_pdata saarb_touch = {
+        .gpadc_prebias  = 1,
+        .slot_cycle     = 1,
+        .tsi_prebias    = 6,
+        .pen_prebias    = 16,
+        .pen_prechg     = 2,
+        .res_x          = 300,
+};
+
+static struct pm860x_backlight_pdata saarb_backlight[] = {
+        {
+                .id     = PM8606_ID_BACKLIGHT,
+                .iset   = PM8606_WLED_CURRENT(24),
+                .flags  = PM8606_BACKLIGHT1,
+        },
+        {},
+};
+
+static struct pm860x_led_pdata saarb_led[] = {
+        {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED1_BLUE,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_RED,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_GREEN,
+        }, {
+                .id     = PM8606_ID_LED,
+                .iset   = PM8606_LED_CURRENT(12),
+                .flags  = PM8606_LED2_BLUE,
+        },
+};
+
+static struct pm860x_platform_data saarb_pm8607_info = {
+        .touch          = &saarb_touch,
+        .backlight      = &saarb_backlight[0],
+        .led            = &saarb_led[0],
+        .companion_addr = 0x10,
+        .irq_mode       = 0,
+        .irq_base       = IRQ_BOARD_START,
+
+        .i2c_port       = GI2C_PORT,
+};
+
+static struct i2c_board_info saarb_i2c_info[] = {
+        {
+                .type           = "88PM860x",
+                .addr           = 0x34,
+                .platform_data  = &saarb_pm8607_info,
+                .irq            = gpio_to_irq(mfp_to_gpio(MFP_PIN_GPIO83)),
+        },
+};
+
+static void __init saarb_init(void)
+{
+        pxa_set_ffuart_info(NULL);
+        pxa_set_i2c_info(NULL);
+        i2c_register_board_info(0, ARRAY_AND_SIZE(saarb_i2c_info));
+}
+
+MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
+        .boot_params    = 0xa0000100,
+        .map_io         = pxa_map_io,
+        .nr_irqs        = SAARB_NR_IRQS,
+        .init_irq       = pxa95x_init_irq,
+        .timer          = &pxa_timer,
+        .init_machine   = saarb_init,
+MACHINE_END
+
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 52c30b01a671..2f5b08aeb52e 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -14,7 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <mach/hardware.h>
-
+#include <mach/smemc.h>
 #include <mach/pxa2xx-regs.h>
 
 #define MDREFR_KDIV     0x200a4000      // all banks
diff --git a/arch/arm/mach-pxa/smemc.c b/arch/arm/mach-pxa/smemc.c
index d6f6904132a6..232b7316ec08 100644
--- a/arch/arm/mach-pxa/smemc.c
+++ b/arch/arm/mach-pxa/smemc.c
@@ -9,50 +9,37 @@
 #include <linux/sysdev.h>
 
 #include <mach/hardware.h>
-
-#define SMEMC_PHYS_BASE (0x4A000000)
-#define SMEMC_PHYS_SIZE (0x90)
-
-#define MSC0            (0x08)  /* Static Memory Controller Register 0 */
-#define MSC1            (0x0C)  /* Static Memory Controller Register 1 */
-#define SXCNFG          (0x1C)  /* Synchronous Static Memory Control Register */
-#define MEMCLKCFG       (0x68)  /* Clock Configuration */
-#define CSADRCFG0       (0x80)  /* Address Configuration Register for CS0 */
-#define CSADRCFG1       (0x84)  /* Address Configuration Register for CS1 */
-#define CSADRCFG2       (0x88)  /* Address Configuration Register for CS2 */
-#define CSADRCFG3       (0x8C)  /* Address Configuration Register for CS3 */
+#include <mach/smemc.h>
 
 #ifdef CONFIG_PM
-static void __iomem *smemc_mmio_base;
-
 static unsigned long msc[2];
 static unsigned long sxcnfg, memclkcfg;
 static unsigned long csadrcfg[4];
 
 static int pxa3xx_smemc_suspend(struct sys_device *dev, pm_message_t state)
 {
-        msc[0] = __raw_readl(smemc_mmio_base + MSC0);
-        msc[1] = __raw_readl(smemc_mmio_base + MSC1);
-        sxcnfg = __raw_readl(smemc_mmio_base + SXCNFG);
-        memclkcfg = __raw_readl(smemc_mmio_base + MEMCLKCFG);
-        csadrcfg[0] = __raw_readl(smemc_mmio_base + CSADRCFG0);
-        csadrcfg[1] = __raw_readl(smemc_mmio_base + CSADRCFG1);
-        csadrcfg[2] = __raw_readl(smemc_mmio_base + CSADRCFG2);
-        csadrcfg[3] = __raw_readl(smemc_mmio_base + CSADRCFG3);
+        msc[0] = __raw_readl(MSC0);
+        msc[1] = __raw_readl(MSC1);
+        sxcnfg = __raw_readl(SXCNFG);
+        memclkcfg = __raw_readl(MEMCLKCFG);
+        csadrcfg[0] = __raw_readl(CSADRCFG0);
+        csadrcfg[1] = __raw_readl(CSADRCFG1);
+        csadrcfg[2] = __raw_readl(CSADRCFG2);
+        csadrcfg[3] = __raw_readl(CSADRCFG3);
 
         return 0;
 }
 
 static int pxa3xx_smemc_resume(struct sys_device *dev)
 {
-        __raw_writel(msc[0], smemc_mmio_base + MSC0);
-        __raw_writel(msc[1], smemc_mmio_base + MSC1);
-        __raw_writel(sxcnfg, smemc_mmio_base + SXCNFG);
-        __raw_writel(memclkcfg, smemc_mmio_base + MEMCLKCFG);
-        __raw_writel(csadrcfg[0], smemc_mmio_base + CSADRCFG0);
-        __raw_writel(csadrcfg[1], smemc_mmio_base + CSADRCFG1);
-        __raw_writel(csadrcfg[2], smemc_mmio_base + CSADRCFG2);
-        __raw_writel(csadrcfg[3], smemc_mmio_base + CSADRCFG3);
+        __raw_writel(msc[0], MSC0);
+        __raw_writel(msc[1], MSC1);
+        __raw_writel(sxcnfg, SXCNFG);
+        __raw_writel(memclkcfg, MEMCLKCFG);
+        __raw_writel(csadrcfg[0], CSADRCFG0);
+        __raw_writel(csadrcfg[1], CSADRCFG1);
+        __raw_writel(csadrcfg[2], CSADRCFG2);
+        __raw_writel(csadrcfg[3], CSADRCFG3);
 
         return 0;
 }
@@ -73,10 +60,6 @@ static int __init smemc_init(void)
         int ret = 0;
 
         if (cpu_is_pxa3xx()) {
-                smemc_mmio_base = ioremap(SMEMC_PHYS_BASE, SMEMC_PHYS_SIZE);
-                if (smemc_mmio_base == NULL)
-                        return -ENODEV;
-
                 ret = sysdev_class_register(&smemc_sysclass);
                 if (ret)
                         return ret;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index f736119f1ebf..0499a69e7673 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -27,6 +27,7 @@
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
 #include <linux/regulator/machine.h>
+#include <linux/io.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -44,6 +45,7 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 #include <mach/sharpsl_pm.h>
+#include <mach/smemc.h>
 
 #include <plat/i2c.h>
 
@@ -929,9 +931,10 @@ static void spitz_poweroff(void)
 
 static void spitz_restart(char mode, const char *cmd)
 {
+        uint32_t msc0 = __raw_readl(MSC0);
         /* Bootloader magic for a reboot */
-        if ((MSC0 & 0xffff0000) == 0x7ff00000)
-                MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
+        if ((msc0 & 0xffff0000) == 0x7ff00000)
+                __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
 
         spitz_poweroff();
 }
@@ -980,7 +983,7 @@ static void __init spitz_fixup(struct machine_desc *desc,
 #ifdef CONFIG_MACH_SPITZ
 MACHINE_START(SPITZ, "SHARP Spitz")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
@@ -990,7 +993,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_BORZOI
 MACHINE_START(BORZOI, "SHARP Borzoi")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
@@ -1000,7 +1003,7 @@ MACHINE_END
 #ifdef CONFIG_MACH_AKITA
 MACHINE_START(AKITA, "SHARP Akita")
         .fixup          = spitz_fixup,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .init_machine   = spitz_init,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 738adc1773fd..3498a1423943 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -48,6 +48,7 @@
 #include <mach/udc.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/pxa27x-udc.h>
+#include <mach/smemc.h>
 
 #include <linux/spi/spi.h>
 #include <linux/mfd/da903x.h>
@@ -976,7 +977,7 @@ static void __init stargate2_init(void)
 {
         /* This is probably a board specific hack as this must be set
            prior to connecting the MFP stuff up. */
-        MECR &= ~MECR_NOS;
+        __raw_writel(__raw_readl(MECR) & ~MECR_NOS, MECR);
 
         pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
 
@@ -998,7 +999,7 @@ static void __init stargate2_init(void)
 
 #ifdef CONFIG_MACH_INTELMOTE2
 MACHINE_START(INTELMOTE2, "IMOTE 2")
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = imote2_init,
@@ -1008,7 +1009,7 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_STARGATE2
 MACHINE_START(STARGATE2, "Stargate 2")
-        .map_io = pxa_map_io,
+        .map_io = pxa27x_map_io,
         .nr_irqs = STARGATE_NR_IRQS,
         .init_irq = pxa27x_init_irq,
         .timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 2ea7545273ad..9cecf8366db8 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -490,7 +490,7 @@ static void __init tavorevb_init(void)
 MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
         /* Maintainer: Eric Miao <eric.miao@marvell.com> */
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = tavorevb_init,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index dc3011697bbf..70191a9450eb 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -127,7 +127,7 @@ static void __init evb3_init(void)
 
 MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = TAVOREVB3_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 0ee1df49606d..57d61ee9b226 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -46,6 +46,7 @@
 #include <mach/tosa_bt.h>
 #include <mach/pxa2xx_spi.h>
 #include <mach/audio.h>
+#include <mach/smemc.h>
 
 #include <asm/mach/arch.h>
 #include <mach/tosa.h>
@@ -893,9 +894,11 @@ static void tosa_poweroff(void)
 
 static void tosa_restart(char mode, const char *cmd)
 {
+        uint32_t msc0 = __raw_readl(MSC0);
+
         /* Bootloader magic for a reboot */
-        if((MSC0 & 0xffff0000) == 0x7ff00000)
-                MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
+        if((msc0 & 0xffff0000) == 0x7ff00000)
+                __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0);
 
         tosa_poweroff();
 }
@@ -953,7 +956,7 @@ static void __init fixup_tosa(struct machine_desc *desc,
 
 MACHINE_START(TOSA, "SHARP Tosa")
         .fixup          = fixup_tosa,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .nr_irqs        = TOSA_NR_IRQS,
         .init_irq       = pxa25x_init_irq,
         .init_machine   = tosa_init,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 565d062f51d5..43fc9ca14594 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -47,6 +47,7 @@
 #include <mach/mmc.h>
 #include <mach/irda.h>
 #include <mach/ohci.h>
+#include <mach/smemc.h>
 #include <plat/i2c.h>
 
 #include "generic.h"
@@ -539,10 +540,10 @@ static void __init trizeps4_init(void)
 
 static void __init trizeps4_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
         iotable_init(trizeps4_io_desc, ARRAY_SIZE(trizeps4_io_desc));
 
-        if ((MSC0 & 0x8) && (BOOT_DEF & 0x1)) {
+        if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) {
                 /* if flash is 16 bit wide its a Trizeps4 WL */
                 __machine_arch_type = MACH_TYPE_TRIZEPS4WL;
                 trizeps4_flash_data[0].width = 2;
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 438fc9a5ed59..de69b203afa7 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -983,7 +983,7 @@ static struct map_desc viper_io_desc[] __initdata = {
 
 static void __init viper_map_io(void)
 {
-        pxa_map_io();
+        pxa25x_map_io();
 
         iotable_init(viper_io_desc, ARRAY_SIZE(viper_io_desc));
 
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index f45ac0961778..b9b579715ff6 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -719,7 +719,7 @@ static void __init vpac270_init(void)
 
 MACHINE_START(VPAC270, "Voipac PXA270")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = vpac270_init
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 3260ce73d327..51c0281c6e0a 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -31,6 +31,7 @@
 #include <mach/hardware.h>
 #include <mach/pxa2xx-regs.h>
 #include <mach/mfp-pxa25x.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -172,9 +173,9 @@ static void __init xcep_init(void)
 
         /* See Intel XScale Developer's Guide for details */
         /* Set RDF and RDN to appropriate values (chip select 3 (smc91x)) */
-        MSC1 = (MSC1 & 0xffff) | 0xD5540000;
+        __raw_writel((__raw_readl(MSC1) & 0xffff) | 0xD5540000, MSC1);
         /* Set RDF and RDN to appropriate values (chip select 5 (fpga)) */
-        MSC2 = (MSC2 & 0xffff) | 0x72A00000;
+        __raw_writel((__raw_readl(MSC2) & 0xffff) | 0x72A00000, MSC2);
 
         platform_add_devices(ARRAY_AND_SIZE(devices));
         pxa_set_i2c_info(&xcep_i2c_platform_data);
@@ -183,7 +184,7 @@ static void __init xcep_init(void)
 MACHINE_START(XCEP, "Iskratel XCEP")
         .boot_params    = 0xa0000100,
         .init_machine   = xcep_init,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa25x_map_io,
         .init_irq       = pxa25x_init_irq,
         .timer          = &pxa_timer,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index fefde9848d82..527c2a1ed310 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -704,7 +704,7 @@ static void __init z2_init(void)
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa27x_map_io,
         .init_irq       = pxa27x_init_irq,
         .timer          = &pxa_timer,
         .init_machine   = z2_init,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index dea46a2d089b..c87f2b35ee05 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -47,6 +47,7 @@
 #include <mach/audio.h>
 #include <mach/arcom-pcmcia.h>
 #include <mach/zeus.h>
+#include <mach/smemc.h>
 
 #include "generic.h"
 
@@ -823,13 +824,16 @@ static mfp_cfg_t zeus_pin_config[] __initdata = {
 static void __init zeus_init(void)
 {
         u16 dm9000_msc = DM9K_MSC_VALUE;
+        u32 msc0, msc1;
 
         system_rev = __raw_readw(ZEUS_CPLD_VERSION);
         pr_info("Zeus CPLD V%dI%d\n", (system_rev & 0xf0) >> 4, (system_rev & 0x0f));
 
         /* Fix timings for dm9000s (CS1/CS2)*/
-        MSC0 = (MSC0 & 0xffff) | (dm9000_msc << 16);
-        MSC1 = (MSC1 & 0xffff0000) | dm9000_msc;
+        msc0 = __raw_readl(MSC0) & 0x0000ffff | (dm9000_msc << 16);
+        msc1 = __raw_readl(MSC1) & 0xffff0000 | dm9000_msc;
+        __raw_writel(msc0, MSC0);
+        __raw_writel(msc1, MSC1);
 
         pm_power_off = zeus_power_off;
         zeus_setup_apm();
@@ -883,7 +887,7 @@ static struct map_desc zeus_io_desc[] __initdata = {
 
 static void __init zeus_map_io(void)
 {
-        pxa_map_io();
+        pxa27x_map_io();
 
         iotable_init(zeus_io_desc, ARRAY_SIZE(zeus_io_desc));
 
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 702f7a68e87d..a4c784aab764 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -423,7 +423,7 @@ static void __init zylonite_init(void)
 
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
         .boot_params    = 0xa0000100,
-        .map_io         = pxa_map_io,
+        .map_io         = pxa3xx_map_io,
         .nr_irqs        = ZYLONITE_NR_IRQS,
         .init_irq       = pxa3xx_init_irq,
         .timer          = &pxa_timer,
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index cef6a65637bd..fa2e5bffbb8e 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -16,7 +16,7 @@ config CPU_S3C2412
 config CPU_S3C2412_ONLY
         bool
         depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
-                   !CPU_2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
+                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
                    !CPU_S3C2443 && CPU_S3C2412
         default y if CPU_S3C2412
 
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 87b9c9f003bd..27b3e7c9d613 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -35,9 +35,12 @@ menu "S3C2416 Machines"
 config MACH_SMDK2416
         bool "SMDK2416"
         select CPU_S3C2416
+        select MACH_SMDK
         select S3C_DEV_FB
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC1
+        select S3C_DEV_NAND
+        select S3C_DEV_USB_HOST
         select S3C2416_PM if PM
         help
           Say Y here if you are using an SMDK2416
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index ff024a6c0f85..a0cb2581894f 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -18,6 +18,7 @@ config CPU_S3C2440
 config CPU_S3C2442
         bool
         select CPU_ARM920T
+        select S3C_GPIO_PULL_DOWN
         select S3C2410_CLOCK
         select S3C2410_GPIO
         select S3C2410_PM if PM
@@ -178,6 +179,9 @@ config MACH_MINI2440
         bool "MINI2440 development board"
         select CPU_S3C2440
         select EEPROM_AT24
+        select NEW_LEDS
+        select LEDS_CLASS
+        select LEDS_TRIGGER
         select LEDS_TRIGGER_BACKLIGHT
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c
index d50f3ae6173d..f7663f731ea0 100644
--- a/arch/arm/mach-s3c2440/s3c2440.c
+++ b/arch/arm/mach-s3c2440/s3c2440.c
@@ -46,9 +46,6 @@ int __init s3c2440_init(void)
 {
         printk("S3C2440: Initialising architecture\n");
 
-        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
-        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
-
         /* change irq for watchdog */
 
         s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
@@ -58,3 +55,11 @@ int __init s3c2440_init(void)
 
         return sysdev_register(&s3c2440_sysdev);
 }
+
+void __init s3c2440_map_io(void)
+{
+        s3c244x_map_io();
+
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up;
+}
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 188ad1e57dc0..ecf813546554 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -32,6 +32,7 @@
 #include <linux/interrupt.h>
 #include <linux/ioport.h>
 #include <linux/mutex.h>
+#include <linux/gpio.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 
@@ -43,6 +44,11 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
+#include <plat/s3c244x.h>
+
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+#include <plat/gpio-cfg-helpers.h>
 
 /* S3C2442 extended clock support */
 
@@ -163,3 +169,11 @@ int __init s3c2442_init(void)
 
         return sysdev_register(&s3c2442_sysdev);
 }
+
+void __init s3c2442_map_io(void)
+{
+        s3c244x_map_io();
+
+        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down;
+        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down;
+}
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig
index 4fef723126fa..31babec90cec 100644
--- a/arch/arm/mach-s3c2443/Kconfig
+++ b/arch/arm/mach-s3c2443/Kconfig
@@ -5,6 +5,7 @@
 config CPU_S3C2443
         bool
         depends on ARCH_S3C2410
+        select CPU_ARM920T
         select S3C2443_DMA if S3C2410_DMA
         select CPU_LLSERIAL_S3C2440
         select SAMSUNG_CLKSRC
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 9e27a84433cb..12052e8e064c 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -2,14 +2,16 @@
 # Makefile for the linux kernel, U8500 machine.
 #
 
-obj-y                           := clock.o cpu.o devices.o
-obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o devices-db5500.o
+obj-y                           := clock.o cpu.o devices.o devices-common.o
+obj-$(CONFIG_UX500_SOC_DB5500)  += cpu-db5500.o dma-db5500.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o devices-db8500.o prcmu.o
-obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o board-mop500-sdi.o
-obj-$(CONFIG_MACH_U5500)        += board-u5500.o
+obj-$(CONFIG_MACH_U8500_MOP)    += board-mop500.o board-mop500-sdi.o \
+                                board-mop500-keypads.o
+obj-$(CONFIG_MACH_U5500)        += board-u5500.o board-u5500-sdi.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)      += localtimer.o
 obj-$(CONFIG_REGULATOR_AB8500)  += board-mop500-regulators.o
-obj-$(CONFIG_U5500_MODEM_IRQ)   += modem_irq.o
-obj-$(CONFIG_U5500_MBOX)        += mbox.o
+obj-$(CONFIG_U5500_MODEM_IRQ)   += modem-irq-db5500.o
+obj-$(CONFIG_U5500_MBOX)        += mbox-db5500.o
+obj-$(CONFIG_CPU_FREQ)          += cpufreq.o
diff --git a/arch/arm/mach-ux500/board-mop500-keypads.c b/arch/arm/mach-ux500/board-mop500-keypads.c
new file mode 100644
index 000000000000..70318c354d32
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-keypads.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Keypad layouts for various boards
+ */
+
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/mfd/tc3589x.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <plat/pincfg.h>
+#include <plat/ske.h>
+
+#include <mach/devices.h>
+#include <mach/hardware.h>
+
+#include "devices-db8500.h"
+#include "board-mop500.h"
+
+/* STMPE/SKE keypad use this key layout */
+static const unsigned int mop500_keymap[] = {
+        KEY(2, 5, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(3, 5, KEY_VOLUMEDOWN),
+        KEY(1, 3, KEY_3),
+        KEY(5, 2, KEY_RIGHT),
+        KEY(5, 0, KEY_9),
+
+        KEY(0, 5, KEY_MENU),
+        KEY(7, 6, KEY_ENTER),
+        KEY(4, 5, KEY_0),
+        KEY(6, 7, KEY_2),
+        KEY(3, 4, KEY_UP),
+        KEY(3, 3, KEY_DOWN),
+
+        KEY(6, 4, KEY_SEND),
+        KEY(6, 2, KEY_BACK),
+        KEY(4, 2, KEY_VOLUMEUP),
+        KEY(5, 5, KEY_1),
+        KEY(4, 3, KEY_LEFT),
+        KEY(3, 2, KEY_7),
+};
+
+static const struct matrix_keymap_data mop500_keymap_data = {
+        .keymap         = mop500_keymap,
+        .keymap_size    = ARRAY_SIZE(mop500_keymap),
+};
+
+/*
+ * Nomadik SKE keypad
+ */
+#define ROW_PIN_I0      164
+#define ROW_PIN_I1      163
+#define ROW_PIN_I2      162
+#define ROW_PIN_I3      161
+#define ROW_PIN_I4      156
+#define ROW_PIN_I5      155
+#define ROW_PIN_I6      154
+#define ROW_PIN_I7      153
+#define COL_PIN_O0      168
+#define COL_PIN_O1      167
+#define COL_PIN_O2      166
+#define COL_PIN_O3      165
+#define COL_PIN_O4      160
+#define COL_PIN_O5      159
+#define COL_PIN_O6      158
+#define COL_PIN_O7      157
+
+#define SKE_KPD_MAX_ROWS        8
+#define SKE_KPD_MAX_COLS        8
+
+static int ske_kp_rows[] = {
+        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
+        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
+};
+
+/*
+ * ske_set_gpio_row: request and set gpio rows
+ */
+static int ske_set_gpio_row(int gpio)
+{
+        int ret;
+
+        ret = gpio_request(gpio, "ske-kp");
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio request failed\n");
+                return ret;
+        }
+
+        ret = gpio_direction_output(gpio, 1);
+        if (ret < 0) {
+                pr_err("ske_set_gpio_row: gpio direction failed\n");
+                gpio_free(gpio);
+        }
+
+        return ret;
+}
+
+/*
+ * ske_kp_init - enable the gpio configuration
+ */
+static int ske_kp_init(void)
+{
+        int ret, i;
+
+        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
+                ret = ske_set_gpio_row(ske_kp_rows[i]);
+                if (ret < 0) {
+                        pr_err("ske_kp_init: failed init\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static struct ske_keypad_platform_data ske_keypad_board = {
+        .init           = ske_kp_init,
+        .keymap_data    = &mop500_keymap_data,
+        .no_autorepeat  = true,
+        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
+        .kcol           = SKE_KPD_MAX_COLS,
+        .debounce_ms    = 40,                   /* in millisecs */
+};
+
+/*
+ * STMPE1601
+ */
+static struct stmpe_keypad_platform_data stmpe1601_keypad_data = {
+        .debounce_ms    = 64,
+        .scan_count     = 8,
+        .no_autorepeat  = true,
+        .keymap_data    = &mop500_keymap_data,
+};
+
+static struct stmpe_platform_data stmpe1601_data = {
+        .id             = 1,
+        .blocks         = STMPE_BLOCK_KEYPAD,
+        .irq_trigger    = IRQF_TRIGGER_FALLING,
+        .irq_base       = MOP500_STMPE1601_IRQ(0),
+        .keypad         = &stmpe1601_keypad_data,
+        .autosleep      = true,
+        .autosleep_timeout = 1024,
+};
+
+static struct i2c_board_info mop500_i2c0_devices_stuib[] = {
+        {
+                I2C_BOARD_INFO("stmpe1601", 0x40),
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .platform_data = &stmpe1601_data,
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+/*
+ * TC35893
+ */
+
+static const unsigned int uib_keymap[] = {
+        KEY(3, 1, KEY_END),
+        KEY(4, 1, KEY_POWER),
+        KEY(6, 4, KEY_VOLUMEDOWN),
+        KEY(4, 2, KEY_EMAIL),
+        KEY(3, 3, KEY_RIGHT),
+        KEY(2, 5, KEY_BACKSPACE),
+
+        KEY(6, 7, KEY_MENU),
+        KEY(5, 0, KEY_ENTER),
+        KEY(4, 3, KEY_0),
+        KEY(3, 4, KEY_DOT),
+        KEY(5, 2, KEY_UP),
+        KEY(3, 5, KEY_DOWN),
+
+        KEY(4, 5, KEY_SEND),
+        KEY(0, 5, KEY_BACK),
+        KEY(6, 2, KEY_VOLUMEUP),
+        KEY(1, 3, KEY_SPACE),
+        KEY(7, 6, KEY_LEFT),
+        KEY(5, 5, KEY_SEARCH),
+};
+
+static struct matrix_keymap_data uib_keymap_data = {
+        .keymap         = uib_keymap,
+        .keymap_size    = ARRAY_SIZE(uib_keymap),
+};
+
+static struct tc3589x_keypad_platform_data tc35893_data = {
+        .krow = TC_KPD_ROWS,
+        .kcol = TC_KPD_COLUMNS,
+        .debounce_period = TC_KPD_DEBOUNCE_PERIOD,
+        .settle_time = TC_KPD_SETTLE_TIME,
+        .irqtype = IRQF_TRIGGER_FALLING,
+        .enable_wakeup = true,
+        .keymap_data    = &uib_keymap_data,
+        .no_autorepeat  = true,
+};
+
+static struct tc3589x_platform_data tc3589x_keypad_data = {
+        .block = TC3589x_BLOCK_KEYPAD,
+        .keypad = &tc35893_data,
+        .irq_base = MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct i2c_board_info mop500_i2c0_devices_uib[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x44),
+                .platform_data = &tc3589x_keypad_data,
+                .irq = NOMADIK_GPIO_TO_IRQ(218),
+                .flags = I2C_CLIENT_WAKE,
+        },
+};
+
+void mop500_keypad_init(void)
+{
+        db8500_add_ske_keypad(&ske_keypad_board);
+
+        i2c_register_board_info(0, mop500_i2c0_devices_stuib,
+                        ARRAY_SIZE(mop500_i2c0_devices_stuib));
+
+        i2c_register_board_info(0, mop500_i2c0_devices_uib,
+                        ARRAY_SIZE(mop500_i2c0_devices_uib));
+
+}
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index bac995665b58..4b996676594e 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -16,10 +16,24 @@
 #include <mach/devices.h>
 #include <mach/hardware.h>
 
+#include "devices-db8500.h"
 #include "pins-db8500.h"
 #include "board-mop500.h"
 
 static pin_cfg_t mop500_sdi_pins[] = {
+        /* SDI0 (MicroSD slot) */
+        GPIO18_MC0_CMDDIR,
+        GPIO19_MC0_DAT0DIR,
+        GPIO20_MC0_DAT2DIR,
+        GPIO21_MC0_DAT31DIR,
+        GPIO22_MC0_FBCLK,
+        GPIO23_MC0_CLK,
+        GPIO24_MC0_CMD,
+        GPIO25_MC0_DAT0,
+        GPIO26_MC0_DAT1,
+        GPIO27_MC0_DAT2,
+        GPIO28_MC0_DAT3,
+
         /* SDI4 (on-board eMMC) */
         GPIO197_MC4_DAT3,
         GPIO198_MC4_DAT2,
@@ -50,6 +64,55 @@ static pin_cfg_t mop500_sdi2_pins[] = {
 };
 
 /*
+ * SDI 0 (MicroSD slot)
+ */
+
+/* MMCIPOWER bits */
+#define MCI_DATA2DIREN          (1 << 2)
+#define MCI_CMDDIREN            (1 << 3)
+#define MCI_DATA0DIREN          (1 << 4)
+#define MCI_DATA31DIREN         (1 << 5)
+#define MCI_FBCLKEN             (1 << 7)
+
+static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
+                                   unsigned char power_mode)
+{
+        if (power_mode == MMC_POWER_UP)
+                gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
+        else if (power_mode == MMC_POWER_OFF)
+                gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
+
+        return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
+               MCI_DATA2DIREN | MCI_DATA31DIREN;
+}
+
+static struct mmci_platform_data mop500_sdi0_data = {
+        .vdd_handler    = mop500_sdi0_vdd_handler,
+        .ocr_mask       = MMC_VDD_29_30,
+        .f_max          = 100000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA,
+        .gpio_cd        = GPIO_SDMMC_CD,
+        .gpio_wp        = -1,
+};
+
+void mop500_sdi_tc35892_init(void)
+{
+        int ret;
+
+        ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN");
+        if (!ret)
+                ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL,
+                                   "GPIO_SDMMC_1V8_3V_SEL");
+        if (ret)
+                return;
+
+        gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 1);
+        gpio_direction_output(GPIO_SDMMC_EN, 0);
+
+        db8500_add_sdi0(&mop500_sdi0_data);
+}
+
+/*
  * SDI 2 (POP eMMC, not on DB8500ed)
  */
 
@@ -74,18 +137,24 @@ static struct mmci_platform_data mop500_sdi4_data = {
         .gpio_wp        = -1,
 };
 
-void mop500_sdi_init(void)
+void __init mop500_sdi_init(void)
 {
         nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
 
-        u8500_sdi2_device.dev.platform_data = &mop500_sdi2_data;
-        u8500_sdi4_device.dev.platform_data = &mop500_sdi4_data;
+        /*
+         * sdi0 will finally be added when the TC35892 initializes and calls
+         * mop500_sdi_tc35892_init() above.
+         */
 
+        /* PoP:ed eMMC */
         if (!cpu_is_u8500ed()) {
                 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
-                amba_device_register(&u8500_sdi2_device, &iomem_resource);
+                /* POP eMMC on v1.0 has problems with high speed */
+                if (!cpu_is_u8500v10())
+                        mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
+                db8500_add_sdi2(&mop500_sdi2_data);
         }
 
         /* On-board eMMC */
-        amba_device_register(&u8500_sdi4_device, &iomem_resource);
+        db8500_add_sdi4(&mop500_sdi4_data);
 }
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index cac83a694880..a1c9ea1a66df 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -13,25 +13,26 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
 #include <linux/mfd/ab8500.h>
-#include <linux/input/matrix_keypad.h>
+#include <linux/mfd/tc3589x.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
 #include <plat/pincfg.h>
 #include <plat/i2c.h>
-#include <plat/ske.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
 #include <mach/irqs.h>
 
+#include "devices-db8500.h"
 #include "pins-db8500.h"
 #include "board-mop500.h"
 
@@ -69,22 +70,12 @@ static pin_cfg_t mop500_pins[] = {
         GPIO166_KP_O2,
         GPIO167_KP_O1,
         GPIO168_KP_O0,
-};
 
-static void ab4500_spi_cs_control(u32 command)
-{
-        /* set the FRM signal, which is CS  - TODO */
-}
+        /* GPIO_EXP_INT */
+        GPIO217_GPIO,
 
-struct pl022_config_chip ab4500_chip_info = {
-        .com_mode = INTERRUPT_TRANSFER,
-        .iface = SSP_INTERFACE_MOTOROLA_SPI,
-        /* we can act as master only */
-        .hierarchy = SSP_MASTER,
-        .slave_tx_disable = 0,
-        .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
-        .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
-        .cs_control = ab4500_spi_cs_control,
+        /* STMPE1601 IRQ */
+        GPIO218_GPIO    | PIN_INPUT_PULLUP,
 };
 
 static struct ab8500_platform_data ab8500_platdata = {
@@ -93,9 +84,9 @@ static struct ab8500_platform_data ab8500_platdata = {
 
 static struct resource ab8500_resources[] = {
         [0] = {
-                .start = IRQ_AB8500,
-                .end = IRQ_AB8500,
-                .flags = IORESOURCE_IRQ
+                .start  = IRQ_DB8500_AB8500,
+                .end    = IRQ_DB8500_AB8500,
+                .flags  = IORESOURCE_IRQ
         }
 };
 
@@ -109,19 +100,6 @@ struct platform_device ab8500_device = {
         .resource = ab8500_resources,
 };
 
-static struct spi_board_info ab8500_spi_devices[] = {
-        {
-                .modalias = "ab8500-spi",
-                .controller_data = &ab4500_chip_info,
-                .platform_data = &ab8500_platdata,
-                .max_speed_hz = 12000000,
-                .bus_num = 0,
-                .chip_select = 0,
-                .mode = SPI_MODE_3,
-                .irq = IRQ_DB8500_AB8500,
-        },
-};
-
 static struct pl022_ssp_controller ssp0_platform_data = {
         .bus_id = 0,
         /* pl022 not yet supports dma */
@@ -132,6 +110,34 @@ static struct pl022_ssp_controller ssp0_platform_data = {
         .num_chipselect = 5,
 };
 
+/*
+ * TC35892
+ */
+
+static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
+{
+        mop500_sdi_tc35892_init();
+}
+
+static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
+        .gpio_base      = MOP500_EGPIO(0),
+        .setup          = mop500_tc35892_init,
+};
+
+static struct tc3589x_platform_data mop500_tc35892_data = {
+        .block          = TC3589x_BLOCK_GPIO,
+        .gpio           = &mop500_tc35892_gpio_data,
+        .irq_base       = MOP500_EGPIO_IRQ_BASE,
+};
+
+static struct i2c_board_info mop500_i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("tc3589x", 0x42),
+                .irq            = NOMADIK_GPIO_TO_IRQ(217),
+                .platform_data  = &mop500_tc35892_data,
+        },
+};
+
 #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
         /*                              \
@@ -161,159 +167,49 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
 
-static struct amba_device *amba_devs[] __initdata = {
-        &ux500_uart0_device,
-        &ux500_uart1_device,
-        &ux500_uart2_device,
-        &u8500_ssp0_device,
-};
-
-static const unsigned int ux500_keymap[] = {
-        KEY(2, 5, KEY_END),
-        KEY(4, 1, KEY_POWER),
-        KEY(3, 5, KEY_VOLUMEDOWN),
-        KEY(1, 3, KEY_3),
-        KEY(5, 2, KEY_RIGHT),
-        KEY(5, 0, KEY_9),
-
-        KEY(0, 5, KEY_MENU),
-        KEY(7, 6, KEY_ENTER),
-        KEY(4, 5, KEY_0),
-        KEY(6, 7, KEY_2),
-        KEY(3, 4, KEY_UP),
-        KEY(3, 3, KEY_DOWN),
-
-        KEY(6, 4, KEY_SEND),
-        KEY(6, 2, KEY_BACK),
-        KEY(4, 2, KEY_VOLUMEUP),
-        KEY(5, 5, KEY_1),
-        KEY(4, 3, KEY_LEFT),
-        KEY(3, 2, KEY_7),
-};
-
-static const struct matrix_keymap_data ux500_keymap_data = {
-        .keymap         = ux500_keymap,
-        .keymap_size    = ARRAY_SIZE(ux500_keymap),
-};
+static void __init mop500_i2c_init(void)
+{
+        db8500_add_i2c0(&u8500_i2c0_data);
+        db8500_add_i2c1(&u8500_i2c1_data);
+        db8500_add_i2c2(&u8500_i2c2_data);
+        db8500_add_i2c3(&u8500_i2c3_data);
+}
 
-/*
- * Nomadik SKE keypad
- */
-#define ROW_PIN_I0      164
-#define ROW_PIN_I1      163
-#define ROW_PIN_I2      162
-#define ROW_PIN_I3      161
-#define ROW_PIN_I4      156
-#define ROW_PIN_I5      155
-#define ROW_PIN_I6      154
-#define ROW_PIN_I7      153
-#define COL_PIN_O0      168
-#define COL_PIN_O1      167
-#define COL_PIN_O2      166
-#define COL_PIN_O3      165
-#define COL_PIN_O4      160
-#define COL_PIN_O5      159
-#define COL_PIN_O6      158
-#define COL_PIN_O7      157
-
-#define SKE_KPD_MAX_ROWS        8
-#define SKE_KPD_MAX_COLS        8
-
-static int ske_kp_rows[] = {
-        ROW_PIN_I0, ROW_PIN_I1, ROW_PIN_I2, ROW_PIN_I3,
-        ROW_PIN_I4, ROW_PIN_I5, ROW_PIN_I6, ROW_PIN_I7,
+/* add any platform devices here - TODO */
+static struct platform_device *platform_devs[] __initdata = {
 };
 
-/*
- * ske_set_gpio_row: request and set gpio rows
- */
-static int ske_set_gpio_row(int gpio)
+static void __init mop500_spi_init(void)
 {
-        int ret;
-
-        ret = gpio_request(gpio, "ske-kp");
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio request failed\n");
-                return ret;
-        }
-
-        ret = gpio_direction_output(gpio, 1);
-        if (ret < 0) {
-                pr_err("ske_set_gpio_row: gpio direction failed\n");
-                gpio_free(gpio);
-        }
-
-        return ret;
+        db8500_add_ssp0(&ssp0_platform_data);
 }
 
-/*
- * ske_kp_init - enable the gpio configuration
- */
-static int ske_kp_init(void)
+static void __init mop500_uart_init(void)
 {
-        int ret, i;
-
-        for (i = 0; i < SKE_KPD_MAX_ROWS; i++) {
-                ret = ske_set_gpio_row(ske_kp_rows[i]);
-                if (ret < 0) {
-                        pr_err("ske_kp_init: failed init\n");
-                        return ret;
-                }
-        }
-
-        return 0;
+        db8500_add_uart0();
+        db8500_add_uart1();
+        db8500_add_uart2();
 }
 
-static struct ske_keypad_platform_data ske_keypad_board = {
-        .init           = ske_kp_init,
-        .keymap_data    = &ux500_keymap_data,
-        .no_autorepeat  = true,
-        .krow           = SKE_KPD_MAX_ROWS,     /* 8x8 matrix */
-        .kcol           = SKE_KPD_MAX_COLS,
-        .debounce_ms    = 40,                   /* in millsecs */
-};
-
-
-
-/* add any platform devices here - TODO */
-static struct platform_device *platform_devs[] __initdata = {
-        &u8500_i2c0_device,
-        &ux500_i2c1_device,
-        &ux500_i2c2_device,
-        &ux500_i2c3_device,
-        &ux500_ske_keypad_device,
-};
-
 static void __init u8500_init_machine(void)
 {
-        int i;
-
         u8500_init_devices();
 
         nmk_config_pins(mop500_pins, ARRAY_SIZE(mop500_pins));
 
-        u8500_i2c0_device.dev.platform_data = &u8500_i2c0_data;
-        ux500_i2c1_device.dev.platform_data = &u8500_i2c1_data;
-        ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
-        ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data;
-        ux500_ske_keypad_device.dev.platform_data = &ske_keypad_board;
-
-        u8500_ssp0_device.dev.platform_data = &ssp0_platform_data;
-
-        /* Register the active AMBA devices on this board */
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
-
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
+        mop500_i2c_init();
         mop500_sdi_init();
+        mop500_spi_init();
+        mop500_uart_init();
+
+        mop500_keypad_init();
+
+        platform_device_register(&ab8500_device);
 
-        /* If HW is early drop (ED) or V1.0 then use SPI to access AB8500 */
-        if (cpu_is_u8500ed() || cpu_is_u8500v10())
-                spi_register_board_info(ab8500_spi_devices,
-                        ARRAY_SIZE(ab8500_spi_devices));
-        else /* If HW is v.1.1 or later use I2C to access AB8500 */
-                platform_device_register(&ab8500_device);
+        i2c_register_board_info(0, mop500_i2c0_devices,
+                                ARRAY_SIZE(mop500_i2c0_devices));
 }
 
 MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 2d240322fa6f..3104ae2a02c2 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,15 @@
 #ifndef __BOARD_MOP500_H
 #define __BOARD_MOP500_H
 
+#define MOP500_EGPIO(x)                 (NOMADIK_NR_GPIO + (x))
+
+/* GPIOs on the TC35892 expander */
+#define GPIO_SDMMC_CD                   MOP500_EGPIO(3)
+#define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
+#define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
+
 extern void mop500_sdi_init(void);
+extern void mop500_sdi_tc35892_init(void);
+extern void mop500_keypad_init(void);
 
 #endif
diff --git a/arch/arm/mach-ux500/board-u5500-sdi.c b/arch/arm/mach-ux500/board-u5500-sdi.c
new file mode 100644
index 000000000000..54712acc0394
--- /dev/null
+++ b/arch/arm/mach-ux500/board-u5500-sdi.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Hanumath Prasad <ulf.hansson@stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/amba/mmci.h>
+#include <linux/mmc/host.h>
+#include <linux/gpio.h>
+
+#include <plat/pincfg.h>
+#include <mach/db5500-regs.h>
+#include <plat/ste_dma40.h>
+
+#include "pins-db5500.h"
+#include "devices-db5500.h"
+#include "ste-dma40-db5500.h"
+
+static pin_cfg_t u5500_sdi_pins[] = {
+        /* SDI0 (POP eMMC) */
+        GPIO5_MC0_DAT0          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO6_MC0_DAT1          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO7_MC0_DAT2          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO8_MC0_DAT3          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO9_MC0_DAT4          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO10_MC0_DAT5         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO11_MC0_DAT6         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO12_MC0_DAT7         | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO13_MC0_CMD          | PIN_DIR_INPUT | PIN_PULL_UP,
+        GPIO14_MC0_CLK          | PIN_DIR_OUTPUT | PIN_VAL_LOW,
+};
+
+static struct mmci_platform_data u5500_sdi0_data = {
+        .ocr_mask       = MMC_VDD_165_195,
+        .f_max          = 50000000,
+        .capabilities   = MMC_CAP_4_BIT_DATA |
+                                MMC_CAP_8_BIT_DATA |
+                                MMC_CAP_MMC_HIGHSPEED,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
+};
+
+void __init u5500_sdi_init(void)
+{
+        nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
+
+        db5500_add_sdi0(&u5500_sdi0_data);
+}
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 1ca094a45e71..39d370c1f3b4 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -9,6 +9,7 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/gpio.h>
+#include <linux/irq.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
@@ -17,20 +18,24 @@
 #include <mach/devices.h>
 #include <mach/setup.h>
 
-static struct amba_device *amba_board_devs[] __initdata = {
-        &ux500_uart0_device,
-        &ux500_uart1_device,
-        &ux500_uart2_device,
-};
+#include "devices-db5500.h"
+
+static void __init u5500_uart_init(void)
+{
+        db5500_add_uart0();
+        db5500_add_uart1();
+        db5500_add_uart2();
+}
 
 static void __init u5500_init_machine(void)
 {
         u5500_init_devices();
 
-        amba_add_devices(amba_board_devs, ARRAY_SIZE(amba_board_devs));
+        u5500_sdi_init();
+        u5500_uart_init();
 }
 
-MACHINE_START(U8500, "ST-Ericsson U5500 Platform")
+MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
         .boot_params    = 0x00000100,
         .map_io         = u5500_map_io,
         .init_irq       = ux500_init_irq,
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 1675047daf20..912d1cc18c57 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -20,6 +20,12 @@
 #include <mach/hardware.h>
 #include "clock.h"
 
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/uaccess.h>      /* for copy_from_user */
+static LIST_HEAD(clk_list);
+#endif
+
 #define PRCC_PCKEN              0x00
 #define PRCC_PCKDIS             0x04
 #define PRCC_KCKEN              0x08
@@ -133,7 +139,7 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
 {
         void __iomem *addr = __io_address(UX500_PRCMU_BASE)
                 + PRCM_TCR;
-        u32 tcr = readl(addr);
+        u32 tcr;
         int mtu = (int) clk->data;
         /*
          * One of these is selected eventually
@@ -144,6 +150,14 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
         unsigned long mturate;
         unsigned long retclk;
 
+        /*
+         * On a startup, always conifgure the TCR to the doze mode;
+         * bootloaders do it for us. Do this in the kernel too.
+         */
+        writel(PRCM_TCR_DOZE_MODE, addr);
+
+        tcr = readl(addr);
+
         /* Get the rate from the parent as a default */
         if (clk->parent_periph)
                 mturate = clk_get_rate(clk->parent_periph);
@@ -153,45 +167,6 @@ static unsigned long clk_mtu_get_rate(struct clk *clk)
                 /* We need to be connected SOMEWHERE */
                 BUG();
 
-        /*
-         * Are we in doze mode?
-         * In this mode the parent peripheral or the fixed 32768 Hz
-         * clock is fed into the block.
-         */
-        if (!(tcr & PRCM_TCR_DOZE_MODE)) {
-                /*
-                 * Here we're using the clock input from the APE ULP
-                 * clock domain. But first: are the timers stopped?
-                 */
-                if (tcr & PRCM_TCR_STOPPED) {
-                        clk32k = 0;
-                        mturate = 0;
-                } else {
-                        /* Else default mode: 0 and 2.4 MHz */
-                        clk32k = 0;
-                        if (cpu_is_u5500())
-                                /* DB5500 divides by 8 */
-                                mturate /= 8;
-                        else if (cpu_is_u8500ed()) {
-                                /*
-                                 * This clocking setting must not be used
-                                 * in the ED chip, it is simply not
-                                 * connected anywhere!
-                                 */
-                                mturate = 0;
-                                BUG();
-                        } else
-                                /*
-                                 * In this mode the ulp38m4 clock is divided
-                                 * by a factor 16, on the DB8500 typically
-                                 * 38400000 / 16 ~ 2.4 MHz.
-                                 * TODO: Replace the constant with a reference
-                                 * to the ULP source once this is modeled.
-                                 */
-                                mturate = 38400000 / 16;
-                }
-        }
-
         /* Return the clock selected for this MTU */
         if (tcr & (1 << mtu))
                 retclk = clk32k;
@@ -317,6 +292,7 @@ static struct clkops clk_prcc_ops = {
 };
 
 static struct clk clk_32khz = {
+        .name =  "clk_32khz",
         .rate = 32000,
 };
 
@@ -366,94 +342,96 @@ static DEFINE_PRCMU_CLK(uiccclk,	0x4, 1, UICCCLK); /* v1 */
  */
 
 /* Peripheral Cluster #1 */
-static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, i2c4,         10, 9, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, gpio0,        9, -1, NULL);
-static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
-static DEFINE_PRCC_CLK(1, spi3_ed,      7,  7, NULL);
-static DEFINE_PRCC_CLK(1, spi3_v1,      7, -1, NULL);
-static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, slimbus0,     8,  8, &clk_slimclk);
+static DEFINE_PRCC_CLK(1, spi3_ed,      7,  7, NULL);
+static DEFINE_PRCC_CLK(1, spi3_v1,      7, -1, NULL);
+static DEFINE_PRCC_CLK(1, i2c2,         6,  6, &clk_i2cclk);
 static DEFINE_PRCC_CLK(1, sdi0,         5,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(1, msp1_ed,      4,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, msp1_v1,      4,  4, &clk_msp1clk);
-static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
-static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, msp1_ed,      4,  4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, msp1_v1,      4,  4, &clk_msp1clk);
+static DEFINE_PRCC_CLK(1, msp0,         3,  3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(1, i2c1,         2,  2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(1, uart1,        1,  1, &clk_uartclk);
+static DEFINE_PRCC_CLK(1, uart0,        0,  0, &clk_uartclk);
 
 /* Peripheral Cluster #2 */
 
 static DEFINE_PRCC_CLK(2, gpio1_ed,     12, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_ed,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_ed,     10, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi0_ed,       9, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_ed,       8,  6, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_ed,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_ed,       6,  4, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_ed,       4,  2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, ssitx_ed,     11, -1, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_ed,     10, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi0_ed,       9, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_ed,       8,  6, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_ed,       7,  5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_ed,       6,  4, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_ed,       4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_ed,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_ed,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(2, spi1_ed,       2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_ed,       1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_ed,       0,  0, &clk_i2cclk);
 
 static DEFINE_PRCC_CLK(2, gpio1_v1,     11, -1, NULL);
-static DEFINE_PRCC_CLK(2, ssitx_v1,     10,  7, NULL);
-static DEFINE_PRCC_CLK(2, ssirx_v1,      9,  6, NULL);
-static DEFINE_PRCC_CLK(2, spi0_v1,       8, -1, NULL);
-static DEFINE_PRCC_CLK(2, sdi3_v1,       7,  5, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, sdi1_v1,       6,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(2, msp2_v1,       5,  3, &clk_msp02clk);
-static DEFINE_PRCC_CLK(2, sdi4_v1,       4,  2, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, ssitx_v1,     10,  7, NULL);
+static DEFINE_PRCC_CLK(2, ssirx_v1,      9,  6, NULL);
+static DEFINE_PRCC_CLK(2, spi0_v1,       8, -1, NULL);
+static DEFINE_PRCC_CLK(2, sdi3_v1,       7,  5, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, sdi1_v1,       6,  4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(2, msp2_v1,       5,  3, &clk_msp02clk);
+static DEFINE_PRCC_CLK(2, sdi4_v1,       4,  2, &clk_sdmmcclk);
 static DEFINE_PRCC_CLK(2, pwl_v1,        3,  1, NULL);
-static DEFINE_PRCC_CLK(2, spi1_v1,       2, -1, NULL);
-static DEFINE_PRCC_CLK(2, spi2_v1,       1, -1, NULL);
-static DEFINE_PRCC_CLK(2, i2c3_v1,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(2, spi1_v1,       2, -1, NULL);
+static DEFINE_PRCC_CLK(2, spi2_v1,       1, -1, NULL);
+static DEFINE_PRCC_CLK(2, i2c3_v1,       0,  0, &clk_i2cclk);
 
 /* Peripheral Cluster #3 */
-static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
-static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
-static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
-static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
-static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_ed,      2,  2, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp0_ed,      1,  1, &clk_i2cclk);
-static DEFINE_PRCC_CLK(3, ssp1_v1,      2,  2, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, ssp0_v1,      1,  1, &clk_sspclk);
-static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
+static DEFINE_PRCC_CLK(3, gpio2,        8, -1, NULL);
+static DEFINE_PRCC_CLK(3, sdi5,         7,  7, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, uart2,        6,  6, &clk_uartclk);
+static DEFINE_PRCC_CLK(3, ske,          5,  5, &clk_32khz);
+static DEFINE_PRCC_CLK(3, sdi2,         4,  4, &clk_sdmmcclk);
+static DEFINE_PRCC_CLK(3, i2c0,         3,  3, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_ed,      2,  2, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp0_ed,      1,  1, &clk_i2cclk);
+static DEFINE_PRCC_CLK(3, ssp1_v1,      2,  2, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, ssp0_v1,      1,  1, &clk_sspclk);
+static DEFINE_PRCC_CLK(3, fsmc,         0, -1, NULL);
 
 /* Peripheral Cluster #4 is in the always on domain */
 
 /* Peripheral Cluster #5 */
-static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
-static DEFINE_PRCC_CLK(5, usb_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(5, usb_v1,       0,  0, NULL);
+static DEFINE_PRCC_CLK(5, gpio3,        1, -1, NULL);
+static DEFINE_PRCC_CLK(5, usb_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(5, usb_v1,       0,  0, NULL);
 
 /* Peripheral Cluster #6 */
 
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(6, cfgreg_v1,    6,  6, NULL);
-static DEFINE_PRCC_CLK(6, dmc_ed,       6,  6, NULL);
-static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
-static DEFINE_PRCC_CLK(6, unipro_v1,    4,  1, &clk_uniproclk);
-static DEFINE_PRCC_CLK(6, cryp1_ed,     4, -1, NULL);
-static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
-static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
-static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
-static DEFINE_PRCC_CLK(6, rng_ed,       0,  0, &clk_i2cclk);
-static DEFINE_PRCC_CLK(6, rng_v1,       0,  0, &clk_rngclk);
+static DEFINE_PRCC_CLK(6, cfgreg_v1,    6,  6, NULL);
+static DEFINE_PRCC_CLK(6, dmc_ed,       6,  6, NULL);
+static DEFINE_PRCC_CLK(6, hash1,        5, -1, NULL);
+static DEFINE_PRCC_CLK(6, unipro_v1,    4,  1, &clk_uniproclk);
+static DEFINE_PRCC_CLK(6, cryp1_ed,     4, -1, NULL);
+static DEFINE_PRCC_CLK(6, pka,          3, -1, NULL);
+static DEFINE_PRCC_CLK(6, hash0,        2, -1, NULL);
+static DEFINE_PRCC_CLK(6, cryp0,        1, -1, NULL);
+static DEFINE_PRCC_CLK(6, rng_ed,       0,  0, &clk_i2cclk);
+static DEFINE_PRCC_CLK(6, rng_v1,       0,  0, &clk_rngclk);
 
 /* Peripheral Cluster #7 */
 
-static DEFINE_PRCC_CLK(7, tzpc0_ed,     4, -1, NULL);
+static DEFINE_PRCC_CLK(7, tzpc0_ed,     4, -1, NULL);
 /* MTU ID in data */
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
 static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
-static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
-static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
+static DEFINE_PRCC_CLK(7, wdg_ed,       1, -1, NULL);
+static DEFINE_PRCC_CLK(7, cfgreg_ed,    0, -1, NULL);
 
-static struct clk clk_dummy_apb_pclk;
+static struct clk clk_dummy_apb_pclk = {
+        .name = "apb_pclk",
+};
 
 static struct clk_lookup u8500_common_clks[] = {
         CLK(dummy_apb_pclk, NULL,       "apb_pclk"),
@@ -554,7 +532,7 @@ static struct clk_lookup u8500_ed_clks[] = {
 
 static struct clk_lookup u8500_v1_clks[] = {
         /* Peripheral Cluster #1 */
-        CLK(i2c4,       "nmk-i2c.4",    NULL),
+        CLK(i2c4,       "nmk-i2c.4",    NULL),
         CLK(spi3_v1,    "spi3",         NULL),
         CLK(msp1_v1,    "msp1",         NULL),
 
@@ -599,6 +577,183 @@ static struct clk_lookup u8500_v1_clks[] = {
         CLK(uiccclk,    "uicc",         NULL),
 };
 
+#ifdef CONFIG_DEBUG_FS
+/*
+ *      debugfs support to trace clock tree hierarchy and attributes with
+ *      powerdebug
+ */
+static struct dentry *clk_debugfs_root;
+
+void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
+{
+        while (num--) {
+                /* Check that the clock has not been already registered */
+                if (!(cl->clk->list.prev != cl->clk->list.next))
+                        list_add_tail(&cl->clk->list, &clk_list);
+
+                cl++;
+        }
+}
+
+static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
+                                                  size_t size, loff_t *off)
+{
+        struct clk *clk = file->f_dentry->d_inode->i_private;
+        char cusecount[128];
+        unsigned int len;
+
+        len = sprintf(cusecount, "%u\n", clk->enabled);
+        return simple_read_from_buffer(buf, size, off, cusecount, len);
+}
+
+static ssize_t rate_dbg_read(struct file *file, char __user *buf,
+                                          size_t size, loff_t *off)
+{
+        struct clk *clk = file->f_dentry->d_inode->i_private;
+        char crate[128];
+        unsigned int rate;
+        unsigned int len;
+
+        rate = clk_get_rate(clk);
+        len = sprintf(crate, "%u\n", rate);
+        return simple_read_from_buffer(buf, size, off, crate, len);
+}
+
+static const struct file_operations usecount_fops = {
+        .read = usecount_dbg_read,
+};
+
+static const struct file_operations set_rate_fops = {
+        .read = rate_dbg_read,
+};
+
+static struct dentry *clk_debugfs_register_dir(struct clk *c,
+                                                struct dentry *p_dentry)
+{
+        struct dentry *d, *clk_d, *child, *child_tmp;
+        char s[255];
+        char *p = s;
+
+        if (c->name == NULL)
+                p += sprintf(p, "BUG");
+        else
+                p += sprintf(p, "%s", c->name);
+
+        clk_d = debugfs_create_dir(s, p_dentry);
+        if (!clk_d)
+                return NULL;
+
+        d = debugfs_create_file("usecount", S_IRUGO,
+                                clk_d, c, &usecount_fops);
+        if (!d)
+                goto err_out;
+        d = debugfs_create_file("rate", S_IRUGO,
+                                clk_d, c, &set_rate_fops);
+        if (!d)
+                goto err_out;
+        /*
+         * TODO : not currently available in ux500
+         * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
+         * if (!d)
+         *      goto err_out;
+         */
+
+        return clk_d;
+
+err_out:
+        d = clk_d;
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(clk_d);
+        return NULL;
+}
+
+static void clk_debugfs_remove_dir(struct dentry *cdentry)
+{
+        struct dentry *d, *child, *child_tmp;
+
+        d = cdentry;
+        list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+                debugfs_remove(child);
+        debugfs_remove(cdentry);
+        return ;
+}
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+        struct clk *pa = c->parent_periph;
+        struct clk *bpa = c->parent_cluster;
+
+        if (!(bpa && !pa)) {
+                c->dent = clk_debugfs_register_dir(c,
+                                pa ? pa->dent : clk_debugfs_root);
+                if (!c->dent)
+                        return -ENOMEM;
+        }
+
+        if (bpa) {
+                c->dent_bus = clk_debugfs_register_dir(c,
+                                bpa->dent_bus ? bpa->dent_bus : bpa->dent);
+                if ((!c->dent_bus) &&  (c->dent)) {
+                        clk_debugfs_remove_dir(c->dent);
+                        c->dent = NULL;
+                        return -ENOMEM;
+                }
+        }
+        return 0;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+        int err;
+        struct clk *pa = c->parent_periph;
+        struct clk *bpa = c->parent_cluster;
+
+        if (pa && (!pa->dent && !pa->dent_bus)) {
+                err = clk_debugfs_register(pa);
+                if (err)
+                        return err;
+        }
+
+        if (bpa && (!bpa->dent && !bpa->dent_bus)) {
+                err = clk_debugfs_register(bpa);
+                if (err)
+                        return err;
+        }
+
+        if ((!c->dent) && (!c->dent_bus)) {
+                err = clk_debugfs_register_one(c);
+                if (err)
+                        return err;
+        }
+        return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+        struct clk *c;
+        struct dentry *d;
+        int err;
+
+        d = debugfs_create_dir("clock", NULL);
+        if (!d)
+                return -ENOMEM;
+        clk_debugfs_root = d;
+
+        list_for_each_entry(c, &clk_list, list) {
+                err = clk_debugfs_register(c);
+                if (err)
+                        goto err_out;
+        }
+        return 0;
+err_out:
+        debugfs_remove_recursive(clk_debugfs_root);
+        return err;
+}
+
+late_initcall(clk_debugfs_init);
+#endif /* defined(CONFIG_DEBUG_FS) */
+
 int __init clk_init(void)
 {
         if (cpu_is_u8500ed()) {
@@ -609,7 +764,8 @@ int __init clk_init(void)
                 /* Clock tree for U5500 not implemented yet */
                 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
                 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
-                clk_per6clk.rate = 26000000;
+                clk_uartclk.rate = 36360000;
+                clk_sdmmcclk.rate = 99900000;
         }
 
         clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
@@ -618,5 +774,12 @@ int __init clk_init(void)
         else
                 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
 
+#ifdef CONFIG_DEBUG_FS
+        clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
+        if (cpu_is_u8500ed())
+                clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
+        else
+                clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
+#endif
         return 0;
 }
diff --git a/arch/arm/mach-ux500/clock.h b/arch/arm/mach-ux500/clock.h
index a05802501527..074490705229 100644
--- a/arch/arm/mach-ux500/clock.h
+++ b/arch/arm/mach-ux500/clock.h
@@ -90,6 +90,10 @@ struct clk {
 
         struct clk              *parent_cluster;
         struct clk              *parent_periph;
+#if defined(CONFIG_DEBUG_FS)
+        struct dentry           *dent;          /* For visible tree hierarchy */
+        struct dentry           *dent_bus;      /* For visible tree hierarchy */
+#endif
 };
 
 #define DEFINE_PRCMU_CLK(_name, _cg_off, _cg_bit, _reg)         \
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index 2f87075e9d6f..acc841e48de4 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -8,14 +8,19 @@
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/map.h>
 
+#include <plat/gpio.h>
+
 #include <mach/hardware.h>
 #include <mach/devices.h>
 #include <mach/setup.h>
 #include <mach/irqs.h>
 
+#include "devices-db5500.h"
+
 static struct map_desc u5500_io_desc[] __initdata = {
         __IO_DEV_DESC(U5500_GPIO0_BASE, SZ_4K),
         __IO_DEV_DESC(U5500_GPIO1_BASE, SZ_4K),
@@ -110,19 +115,32 @@ static struct platform_device mbox2_device = {
 };
 
 static struct platform_device *u5500_platform_devs[] __initdata = {
-        &u5500_gpio_devs[0],
-        &u5500_gpio_devs[1],
-        &u5500_gpio_devs[2],
-        &u5500_gpio_devs[3],
-        &u5500_gpio_devs[4],
-        &u5500_gpio_devs[5],
-        &u5500_gpio_devs[6],
-        &u5500_gpio_devs[7],
         &mbox0_device,
         &mbox1_device,
         &mbox2_device,
 };
 
+static resource_size_t __initdata db5500_gpio_base[] = {
+        U5500_GPIOBANK0_BASE,
+        U5500_GPIOBANK1_BASE,
+        U5500_GPIOBANK2_BASE,
+        U5500_GPIOBANK3_BASE,
+        U5500_GPIOBANK4_BASE,
+        U5500_GPIOBANK5_BASE,
+        U5500_GPIOBANK6_BASE,
+        U5500_GPIOBANK7_BASE,
+};
+
+static void __init db5500_add_gpios(void)
+{
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
+
+        dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base),
+                         IRQ_DB5500_GPIO0, &pdata);
+}
+
 void __init u5500_map_io(void)
 {
         ux500_map_io();
@@ -132,7 +150,9 @@ void __init u5500_map_io(void)
 
 void __init u5500_init_devices(void)
 {
-        ux500_init_devices();
+        db5500_add_gpios();
+        db5500_dma_init();
+        db5500_add_rtc();
 
         platform_add_devices(u5500_platform_devs,
                              ARRAY_SIZE(u5500_platform_devs));
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 4acab7544b3c..c0f34a404c53 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -22,23 +22,15 @@
 #include <mach/setup.h>
 #include <mach/devices.h>
 
+#include "devices-db8500.h"
+
 static struct platform_device *platform_devs[] __initdata = {
-        &u8500_gpio_devs[0],
-        &u8500_gpio_devs[1],
-        &u8500_gpio_devs[2],
-        &u8500_gpio_devs[3],
-        &u8500_gpio_devs[4],
-        &u8500_gpio_devs[5],
-        &u8500_gpio_devs[6],
-        &u8500_gpio_devs[7],
-        &u8500_gpio_devs[8],
         &u8500_dma40_device,
 };
 
 /* minimum static i/o mapping required to boot U8500 platforms */
 static struct map_desc u8500_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_PRCMU_BASE, SZ_4K),
-        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO0_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO1_BASE, SZ_4K),
         __IO_DEV_DESC(U8500_GPIO2_BASE, SZ_4K),
@@ -46,13 +38,18 @@ static struct map_desc u8500_io_desc[] __initdata = {
         __MEM_DEV_DESC(U8500_BOOT_ROM_BASE, SZ_1M),
 };
 
-static struct map_desc u8500ed_io_desc[] __initdata = {
+static struct map_desc u8500_ed_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_MTU0_BASE_ED, SZ_4K),
         __IO_DEV_DESC(U8500_CLKRST7_BASE_ED, SZ_8K),
 };
 
-static struct map_desc u8500v1_io_desc[] __initdata = {
+static struct map_desc u8500_v1_io_desc[] __initdata = {
         __IO_DEV_DESC(U8500_MTU0_BASE, SZ_4K),
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE_V1, SZ_4K),
+};
+
+static struct map_desc u8500_v2_io_desc[] __initdata = {
+        __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K),
 };
 
 /*
@@ -125,14 +122,38 @@ void __init u8500_map_io(void)
         iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
 
         if (cpu_is_u8500ed())
-                iotable_init(u8500ed_io_desc, ARRAY_SIZE(u8500ed_io_desc));
-        else
-                iotable_init(u8500v1_io_desc, ARRAY_SIZE(u8500v1_io_desc));
+                iotable_init(u8500_ed_io_desc, ARRAY_SIZE(u8500_ed_io_desc));
+        else if (cpu_is_u8500v1())
+                iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
+        else if (cpu_is_u8500v2())
+                iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
 
         /* Read out the ASIC ID as early as we can */
         get_db8500_asic_id();
 }
 
+static resource_size_t __initdata db8500_gpio_base[] = {
+        U8500_GPIOBANK0_BASE,
+        U8500_GPIOBANK1_BASE,
+        U8500_GPIOBANK2_BASE,
+        U8500_GPIOBANK3_BASE,
+        U8500_GPIOBANK4_BASE,
+        U8500_GPIOBANK5_BASE,
+        U8500_GPIOBANK6_BASE,
+        U8500_GPIOBANK7_BASE,
+        U8500_GPIOBANK8_BASE,
+};
+
+static void __init db8500_add_gpios(void)
+{
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
+
+        dbx500_add_gpios(ARRAY_AND_SIZE(db8500_gpio_base),
+                         IRQ_DB8500_GPIO0, &pdata);
+}
+
 /*
  * This function is called from the board init
  */
@@ -152,12 +173,13 @@ void __init u8500_init_devices(void)
         else
                 pr_warning("ASIC: UNKNOWN SILICON VERSION!\n");
 
-        ux500_init_devices();
-
         if (cpu_is_u8500ed())
                 dma40_u8500ed_fixup();
 
-        /* Register the platform devices */
+        db8500_add_rtc();
+        db8500_add_gpios();
+
+        platform_device_register_simple("cpufreq-u8500", -1, NULL, 0);
         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
         return ;
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 608a1372b172..a3700bc374d3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -6,7 +6,6 @@
  */
 
 #include <linux/platform_device.h>
-#include <linux/amba/bus.h>
 #include <linux/io.h>
 #include <linux/clk.h>
 
@@ -20,6 +19,7 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 #include <mach/devices.h>
+#include <mach/prcmu.h>
 
 #include "clock.h"
 
@@ -45,20 +45,11 @@ static struct map_desc ux500_io_desc[] __initdata = {
         __IO_DEV_DESC(UX500_BACKUPRAM0_BASE, SZ_8K),
 };
 
-static struct amba_device *ux500_amba_devs[] __initdata = {
-        &ux500_pl031_device,
-};
-
 void __init ux500_map_io(void)
 {
         iotable_init(ux500_io_desc, ARRAY_SIZE(ux500_io_desc));
 }
 
-void __init ux500_init_devices(void)
-{
-        amba_add_devices(ux500_amba_devs, ARRAY_SIZE(ux500_amba_devs));
-}
-
 void __init ux500_init_irq(void)
 {
         gic_dist_init(0, __io_address(UX500_GIC_DIST_BASE), 29);
@@ -68,6 +59,8 @@ void __init ux500_init_irq(void)
          * Init clocks here so that they are available for system timer
          * initialization.
          */
+        if (cpu_is_u8500())
+                prcmu_early_init();
         clk_init();
 }
 
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
new file mode 100644
index 000000000000..5c5b747f134d
--- /dev/null
+++ b/arch/arm/mach-ux500/cpufreq.c
@@ -0,0 +1,211 @@
+/*
+ * CPU frequency scaling for u8500
+ * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
+ *
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Martin Persson <martin.persson@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+
+#include <mach/hardware.h>
+#include <mach/prcmu.h>
+#include <mach/prcmu-defs.h>
+
+#define DRIVER_NAME "cpufreq-u8500"
+#define CPUFREQ_NAME "u8500"
+
+static struct device *dev;
+
+static struct cpufreq_frequency_table freq_table[] = {
+        [0] = {
+                .index = 0,
+                .frequency = 200000,
+        },
+        [1] = {
+                .index = 1,
+                .frequency = 300000,
+        },
+        [2] = {
+                .index = 2,
+                .frequency = 600000,
+        },
+        [3] = {
+                /* Used for CPU_OPP_MAX, if available */
+                .index = 3,
+                .frequency = CPUFREQ_TABLE_END,
+        },
+        [4] = {
+                .index = 4,
+                .frequency = CPUFREQ_TABLE_END,
+        },
+};
+
+static enum prcmu_cpu_opp index2opp[] = {
+        CPU_OPP_EXT_CLK,
+        CPU_OPP_50,
+        CPU_OPP_100,
+        CPU_OPP_MAX
+};
+
+static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+        return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static int u8500_cpufreq_target(struct cpufreq_policy *policy,
+                                unsigned int target_freq,
+                                unsigned int relation)
+{
+        struct cpufreq_freqs freqs;
+        unsigned int index;
+        int ret = 0;
+
+        /*
+         * Ensure desired rate is within allowed range.  Some govenors
+         * (ondemand) will just pass target_freq=0 to get the minimum.
+         */
+        if (target_freq < policy->cpuinfo.min_freq)
+                target_freq = policy->cpuinfo.min_freq;
+        if (target_freq > policy->cpuinfo.max_freq)
+                target_freq = policy->cpuinfo.max_freq;
+
+        ret = cpufreq_frequency_table_target(policy, freq_table,
+                                             target_freq, relation, &index);
+        if (ret < 0) {
+                dev_err(dev, "Could not look up next frequency\n");
+                return ret;
+        }
+
+        freqs.old = policy->cur;
+        freqs.new = freq_table[index].frequency;
+        freqs.cpu = policy->cpu;
+
+        if (freqs.old == freqs.new) {
+                dev_dbg(dev, "Current and target frequencies are equal\n");
+                return 0;
+        }
+
+        dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
+        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+        ret = prcmu_set_cpu_opp(index2opp[index]);
+        if (ret < 0) {
+                dev_err(dev, "Failed to set OPP level\n");
+                return ret;
+        }
+
+        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+        return ret;
+}
+
+static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
+{
+        int i;
+
+        for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
+                ;
+        return freq_table[i].frequency;
+}
+
+static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
+{
+        int res;
+
+        BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
+
+        if (cpu_is_u8500v2()) {
+                freq_table[1].frequency = 400000;
+                freq_table[2].frequency = 800000;
+                if (prcmu_has_arm_maxopp())
+                        freq_table[3].frequency = 1000000;
+        }
+
+        /* get policy fields based on the table */
+        res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+        if (!res)
+                cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+        else {
+                dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
+                return res;
+        }
+
+        policy->min = policy->cpuinfo.min_freq;
+        policy->max = policy->cpuinfo.max_freq;
+        policy->cur = u8500_cpufreq_getspeed(policy->cpu);
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+        /*
+         * FIXME : Need to take time measurement across the target()
+         *         function with no/some/all drivers in the notification
+         *         list.
+         */
+        policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
+
+        /* policy sharing between dual CPUs */
+        cpumask_copy(policy->cpus, &cpu_present_map);
+
+        policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+
+        return res;
+}
+
+static struct freq_attr *u8500_cpufreq_attr[] = {
+        &cpufreq_freq_attr_scaling_available_freqs,
+        NULL,
+};
+static int u8500_cpu_exit(struct cpufreq_policy *policy)
+{
+        cpufreq_frequency_table_put_attr(policy->cpu);
+        return 0;
+}
+
+static struct cpufreq_driver u8500_driver = {
+        .owner = THIS_MODULE,
+        .flags = CPUFREQ_STICKY,
+        .verify = u8500_cpufreq_verify_speed,
+        .target = u8500_cpufreq_target,
+        .get = u8500_cpufreq_getspeed,
+        .init = u8500_cpu_init,
+        .exit = u8500_cpu_exit,
+        .name = CPUFREQ_NAME,
+        .attr = u8500_cpufreq_attr,
+};
+
+static int __init u8500_cpufreq_probe(struct platform_device *pdev)
+{
+        dev = &pdev->dev;
+        return cpufreq_register_driver(&u8500_driver);
+}
+
+static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
+{
+        return cpufreq_unregister_driver(&u8500_driver);
+}
+
+static struct platform_driver u8500_cpufreq_driver = {
+        .driver = {
+                .name    = DRIVER_NAME,
+                .owner   = THIS_MODULE,
+        },
+        .remove = __exit_p(u8500_cpufreq_remove),
+};
+
+static int __init u8500_cpufreq_init(void)
+{
+        return platform_driver_probe(&u8500_cpufreq_driver,
+                                     &u8500_cpufreq_probe);
+}
+
+device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/devices-common.c b/arch/arm/mach-ux500/devices-common.c
new file mode 100644
index 000000000000..fe69f5fac1bb
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-common.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+
+#include <plat/gpio.h>
+
+#include <mach/hardware.h>
+
+#include "devices-common.h"
+
+struct amba_device *
+dbx500_add_amba_device(const char *name, resource_size_t base,
+                       int irq, void *pdata, unsigned int periphid)
+{
+        struct amba_device *dev;
+        int ret;
+
+        dev = kzalloc(sizeof *dev, GFP_KERNEL);
+        if (!dev)
+                return ERR_PTR(-ENOMEM);
+
+        dev->dev.init_name = name;
+
+        dev->res.start = base;
+        dev->res.end = base + SZ_4K - 1;
+        dev->res.flags = IORESOURCE_MEM;
+
+        dev->dma_mask = DMA_BIT_MASK(32);
+        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+        dev->irq[0] = irq;
+        dev->irq[1] = NO_IRQ;
+
+        dev->periphid = periphid;
+
+        dev->dev.platform_data = pdata;
+
+        ret = amba_device_register(dev, &iomem_resource);
+        if (ret) {
+                kfree(dev);
+                return ERR_PTR(ret);
+        }
+
+        return dev;
+}
+
+static struct platform_device *
+dbx500_add_platform_device(const char *name, int id, void *pdata,
+                           struct resource *res, int resnum)
+{
+        struct platform_device *dev;
+        int ret;
+
+        dev = platform_device_alloc(name, id);
+        if (!dev)
+                return ERR_PTR(-ENOMEM);
+
+        dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+        dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
+
+        ret = platform_device_add_resources(dev, res, resnum);
+        if (ret)
+                goto out_free;
+
+        dev->dev.platform_data = pdata;
+
+        ret = platform_device_add(dev);
+        if (ret)
+                goto out_free;
+
+        return dev;
+
+out_free:
+        platform_device_put(dev);
+        return ERR_PTR(ret);
+}
+
+struct platform_device *
+dbx500_add_platform_device_4k1irq(const char *name, int id,
+                                  resource_size_t base,
+                                  int irq, void *pdata)
+{
+        struct resource resources[] = {
+                [0] = {
+                        .start  = base,
+                        .end    = base + SZ_4K - 1,
+                        .flags  = IORESOURCE_MEM,
+                },
+                [1] = {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return dbx500_add_platform_device(name, id, pdata, resources,
+                                          ARRAY_SIZE(resources));
+}
+
+static struct platform_device *
+dbx500_add_gpio(int id, resource_size_t addr, int irq,
+                struct nmk_gpio_platform_data *pdata)
+{
+        struct resource resources[] = {
+                {
+                        .start  = addr,
+                        .end    = addr + 127,
+                        .flags  = IORESOURCE_MEM,
+                },
+                {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return platform_device_register_resndata(NULL, "gpio", id,
+                                resources, ARRAY_SIZE(resources),
+                                pdata, sizeof(*pdata));
+}
+
+void dbx500_add_gpios(resource_size_t *base, int num, int irq,
+                      struct nmk_gpio_platform_data *pdata)
+{
+        int first = 0;
+        int i;
+
+        for (i = 0; i < num; i++, first += 32, irq++) {
+                pdata->first_gpio = first;
+                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+
+                dbx500_add_gpio(i, base[i], irq, pdata);
+        }
+}
diff --git a/arch/arm/mach-ux500/devices-common.h b/arch/arm/mach-ux500/devices-common.h
new file mode 100644
index 000000000000..cbadc117d2db
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-common.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_COMMON_H
+#define __DEVICES_COMMON_H
+
+extern struct amba_device *
+dbx500_add_amba_device(const char *name, resource_size_t base,
+                       int irq, void *pdata, unsigned int periphid);
+
+extern struct platform_device *
+dbx500_add_platform_device_4k1irq(const char *name, int id,
+                                  resource_size_t base,
+                                  int irq, void *pdata);
+
+struct spi_master_cntlr;
+
+static inline struct amba_device *
+dbx500_add_msp_spi(const char *name, resource_size_t base, int irq,
+                   struct spi_master_cntlr *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+static inline struct amba_device *
+dbx500_add_spi(const char *name, resource_size_t base, int irq,
+                                   struct spi_master_cntlr *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+struct mmci_platform_data;
+
+static inline struct amba_device *
+dbx500_add_sdi(const char *name, resource_size_t base, int irq,
+               struct mmci_platform_data *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, 0);
+}
+
+static inline struct amba_device *
+dbx500_add_uart(const char *name, resource_size_t base, int irq)
+{
+        return dbx500_add_amba_device(name, base, irq, NULL, 0);
+}
+
+struct nmk_i2c_controller;
+
+static inline struct platform_device *
+dbx500_add_i2c(int id, resource_size_t base, int irq,
+               struct nmk_i2c_controller *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("nmk-i2c", id, base, irq,
+                                                 pdata);
+}
+
+struct msp_i2s_platform_data;
+
+static inline struct platform_device *
+dbx500_add_msp_i2s(int id, resource_size_t base, int irq,
+                   struct msp_i2s_platform_data *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("MSP_I2S", id, base, irq,
+                                                 pdata);
+}
+
+static inline struct amba_device *
+dbx500_add_rtc(resource_size_t base, int irq)
+{
+        return dbx500_add_amba_device("rtc-pl031", base, irq, NULL, 0);
+}
+
+struct nmk_gpio_platform_data;
+
+void dbx500_add_gpios(resource_size_t *base, int num, int irq,
+                      struct nmk_gpio_platform_data *pdata);
+
+#endif
diff --git a/arch/arm/mach-ux500/devices-db5500.c b/arch/arm/mach-ux500/devices-db5500.c
deleted file mode 100644
index 33e5b56bebb6..000000000000
--- a/arch/arm/mach-ux500/devices-db5500.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-
-#include <mach/hardware.h>
-#include <mach/devices.h>
-
-static struct nmk_gpio_platform_data u5500_gpio_data[] = {
-        GPIO_DATA("GPIO-0-31", 0),
-        GPIO_DATA("GPIO-32-63", 32), /* 36..63 not routed to pin */
-        GPIO_DATA("GPIO-64-95", 64), /* 83..95 not routed to pin */
-        GPIO_DATA("GPIO-96-127", 96), /* 102..127 not routed to pin */
-        GPIO_DATA("GPIO-128-159", 128), /* 149..159 not routed to pin */
-        GPIO_DATA("GPIO-160-191", 160),
-        GPIO_DATA("GPIO-192-223", 192),
-        GPIO_DATA("GPIO-224-255", 224), /* 228..255 not routed to pin */
-};
-
-static struct resource u5500_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-        GPIO_RESOURCE(4),
-        GPIO_RESOURCE(5),
-        GPIO_RESOURCE(6),
-        GPIO_RESOURCE(7),
-};
-
-struct platform_device u5500_gpio_devs[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-        GPIO_DEVICE(4),
-        GPIO_DEVICE(5),
-        GPIO_DEVICE(6),
-        GPIO_DEVICE(7),
-};
diff --git a/arch/arm/mach-ux500/devices-db5500.h b/arch/arm/mach-ux500/devices-db5500.h
new file mode 100644
index 000000000000..c8d7901c1f2d
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db5500.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_DB5500_H
+#define __DEVICES_DB5500_H
+
+#include "devices-common.h"
+
+#define db5500_add_i2c1(pdata) \
+        dbx500_add_i2c(1, U5500_I2C1_BASE, IRQ_DB5500_I2C1, pdata)
+#define db5500_add_i2c2(pdata) \
+        dbx500_add_i2c(2, U5500_I2C2_BASE, IRQ_DB5500_I2C2, pdata)
+#define db5500_add_i2c3(pdata) \
+        dbx500_add_i2c(3, U5500_I2C3_BASE, IRQ_DB5500_I2C3, pdata)
+
+#define db5500_add_msp0_i2s(pdata) \
+        dbx500_add_msp_i2s(0, U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_i2s(pdata) \
+        dbx500_add_msp_i2s(1, U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_i2s(pdata) \
+        dbx500_add_msp_i2s(2, U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+
+#define db5500_add_msp0_spi(pdata) \
+        dbx500_add_msp_spi("msp0", U5500_MSP0_BASE, IRQ_DB5500_MSP0, pdata)
+#define db5500_add_msp1_spi(pdata) \
+        dbx500_add_msp_spi("msp1", U5500_MSP1_BASE, IRQ_DB5500_MSP1, pdata)
+#define db5500_add_msp2_spi(pdata) \
+        dbx500_add_msp_spi("msp2", U5500_MSP2_BASE, IRQ_DB5500_MSP2, pdata)
+
+#define db5500_add_rtc() \
+        dbx500_add_rtc(U5500_RTC_BASE, IRQ_DB5500_RTC);
+
+#define db5500_add_sdi0(pdata) \
+        dbx500_add_sdi("sdi0", U5500_SDI0_BASE, IRQ_DB5500_SDMMC0, pdata)
+#define db5500_add_sdi1(pdata) \
+        dbx500_add_sdi("sdi1", U5500_SDI1_BASE, IRQ_DB5500_SDMMC1, pdata)
+#define db5500_add_sdi2(pdata) \
+        dbx500_add_sdi("sdi2", U5500_SDI2_BASE, IRQ_DB5500_SDMMC2, pdata)
+#define db5500_add_sdi3(pdata) \
+        dbx500_add_sdi("sdi3", U5500_SDI3_BASE, IRQ_DB5500_SDMMC3, pdata)
+#define db5500_add_sdi4(pdata) \
+        dbx500_add_sdi("sdi4", U5500_SDI4_BASE, IRQ_DB5500_SDMMC4, pdata)
+
+#define db5500_add_spi0(pdata) \
+        dbx500_add_spi("spi0", U5500_SPI0_BASE, IRQ_DB5500_SPI0, pdata)
+#define db5500_add_spi1(pdata) \
+        dbx500_add_spi("spi1", U5500_SPI1_BASE, IRQ_DB5500_SPI1, pdata)
+#define db5500_add_spi2(pdata) \
+        dbx500_add_spi("spi2", U5500_SPI2_BASE, IRQ_DB5500_SPI2, pdata)
+#define db5500_add_spi3(pdata) \
+        dbx500_add_spi("spi3", U5500_SPI3_BASE, IRQ_DB5500_SPI3, pdata)
+
+#define db5500_add_uart0() \
+        dbx500_add_uart("uart0", U5500_UART0_BASE, IRQ_DB5500_UART0)
+#define db5500_add_uart1() \
+        dbx500_add_uart("uart1", U5500_UART1_BASE, IRQ_DB5500_UART1)
+#define db5500_add_uart2() \
+        dbx500_add_uart("uart2", U5500_UART2_BASE, IRQ_DB5500_UART2)
+#define db5500_add_uart3() \
+        dbx500_add_uart("uart3", U5500_UART3_BASE, IRQ_DB5500_UART3)
+
+#endif
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 4a94be3304b9..23c695d54977 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -19,173 +19,6 @@
 
 #include "ste-dma40-db8500.h"
 
-static struct nmk_gpio_platform_data u8500_gpio_data[] = {
-        GPIO_DATA("GPIO-0-31", 0),
-        GPIO_DATA("GPIO-32-63", 32), /* 37..63 not routed to pin */
-        GPIO_DATA("GPIO-64-95", 64),
-        GPIO_DATA("GPIO-96-127", 96), /* 98..127 not routed to pin */
-        GPIO_DATA("GPIO-128-159", 128),
-        GPIO_DATA("GPIO-160-191", 160), /* 172..191 not routed to pin */
-        GPIO_DATA("GPIO-192-223", 192),
-        GPIO_DATA("GPIO-224-255", 224), /* 231..255 not routed to pin */
-        GPIO_DATA("GPIO-256-288", 256), /* 268..288 not routed to pin */
-};
-
-static struct resource u8500_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-        GPIO_RESOURCE(4),
-        GPIO_RESOURCE(5),
-        GPIO_RESOURCE(6),
-        GPIO_RESOURCE(7),
-        GPIO_RESOURCE(8),
-};
-
-struct platform_device u8500_gpio_devs[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-        GPIO_DEVICE(4),
-        GPIO_DEVICE(5),
-        GPIO_DEVICE(6),
-        GPIO_DEVICE(7),
-        GPIO_DEVICE(8),
-};
-
-struct amba_device u8500_ssp0_device = {
-        .dev = {
-                .coherent_dma_mask = ~0,
-                .init_name = "ssp0",
-        },
-        .res = {
-                .start = U8500_SSP0_BASE,
-                .end   = U8500_SSP0_BASE + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_DB8500_SSP0, NO_IRQ },
-        /* ST-Ericsson modified id */
-        .periphid = SSP_PER_ID,
-};
-
-static struct resource u8500_i2c0_resources[] = {
-        [0] = {
-                .start  = U8500_I2C0_BASE,
-                .end    = U8500_I2C0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DB8500_I2C0,
-                .end    = IRQ_DB8500_I2C0,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device u8500_i2c0_device = {
-        .name           = "nmk-i2c",
-        .id             = 0,
-        .resource       = u8500_i2c0_resources,
-        .num_resources  = ARRAY_SIZE(u8500_i2c0_resources),
-};
-
-static struct resource u8500_i2c4_resources[] = {
-        [0] = {
-                .start  = U8500_I2C4_BASE,
-                .end    = U8500_I2C4_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DB8500_I2C4,
-                .end    = IRQ_DB8500_I2C4,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device u8500_i2c4_device = {
-        .name           = "nmk-i2c",
-        .id             = 4,
-        .resource       = u8500_i2c4_resources,
-        .num_resources  = ARRAY_SIZE(u8500_i2c4_resources),
-};
-
-/*
- * SD/MMC
- */
-
-struct amba_device u8500_sdi0_device = {
-        .dev            = {
-                .init_name = "sdi0",
-        },
-        .res            = {
-                .start  = U8500_SDI0_BASE,
-                .end    = U8500_SDI0_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC0, NO_IRQ},
-};
-
-struct amba_device u8500_sdi1_device = {
-        .dev            = {
-                .init_name = "sdi1",
-        },
-        .res            = {
-                .start  = U8500_SDI1_BASE,
-                .end    = U8500_SDI1_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC1, NO_IRQ},
-};
-
-struct amba_device u8500_sdi2_device = {
-        .dev            = {
-                .init_name = "sdi2",
-        },
-        .res            = {
-                .start  = U8500_SDI2_BASE,
-                .end    = U8500_SDI2_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC2, NO_IRQ},
-};
-
-struct amba_device u8500_sdi3_device = {
-        .dev            = {
-                .init_name = "sdi3",
-        },
-        .res            = {
-                .start  = U8500_SDI3_BASE,
-                .end    = U8500_SDI3_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC3, NO_IRQ},
-};
-
-struct amba_device u8500_sdi4_device = {
-        .dev            = {
-                .init_name = "sdi4",
-        },
-        .res            = {
-                .start  = U8500_SDI4_BASE,
-                .end    = U8500_SDI4_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC4, NO_IRQ},
-};
-
-struct amba_device u8500_sdi5_device = {
-        .dev            = {
-                .init_name = "sdi5",
-        },
-        .res            = {
-                .start  = U8500_SDI5_BASE,
-                .end    = U8500_SDI5_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq            = {IRQ_DB8500_SDMMC5, NO_IRQ},
-};
-
 static struct resource dma40_resources[] = {
         [0] = {
                 .start = U8500_DMA_BASE,
@@ -295,7 +128,7 @@ struct resource keypad_resources[] = {
         },
 };
 
-struct platform_device ux500_ske_keypad_device = {
+struct platform_device u8500_ske_keypad_device = {
         .name = "nmk-ske-keypad",
         .id = -1,
         .num_resources = ARRAY_SIZE(keypad_resources),
diff --git a/arch/arm/mach-ux500/devices-db8500.h b/arch/arm/mach-ux500/devices-db8500.h
new file mode 100644
index 000000000000..3a770c756979
--- /dev/null
+++ b/arch/arm/mach-ux500/devices-db8500.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
+ * License terms: GNU General Public License (GPL), version 2.
+ */
+
+#ifndef __DEVICES_DB8500_H
+#define __DEVICES_DB8500_H
+
+#include "devices-common.h"
+
+struct ske_keypad_platform_data;
+struct pl022_ssp_controller;
+
+static inline struct platform_device *
+db8500_add_ske_keypad(struct ske_keypad_platform_data *pdata)
+{
+        return dbx500_add_platform_device_4k1irq("nmk-ske-keypad", -1,
+                                                 U8500_SKE_BASE,
+                                                 IRQ_DB8500_KB, pdata);
+}
+
+static inline struct amba_device *
+db8500_add_ssp(const char *name, resource_size_t base, int irq,
+               struct pl022_ssp_controller *pdata)
+{
+        return dbx500_add_amba_device(name, base, irq, pdata, SSP_PER_ID);
+}
+
+
+#define db8500_add_i2c0(pdata) \
+        dbx500_add_i2c(0, U8500_I2C0_BASE, IRQ_DB8500_I2C0, pdata)
+#define db8500_add_i2c1(pdata) \
+        dbx500_add_i2c(1, U8500_I2C1_BASE, IRQ_DB8500_I2C1, pdata)
+#define db8500_add_i2c2(pdata) \
+        dbx500_add_i2c(2, U8500_I2C2_BASE, IRQ_DB8500_I2C2, pdata)
+#define db8500_add_i2c3(pdata) \
+        dbx500_add_i2c(3, U8500_I2C3_BASE, IRQ_DB8500_I2C3, pdata)
+#define db8500_add_i2c4(pdata) \
+        dbx500_add_i2c(4, U8500_I2C4_BASE, IRQ_DB8500_I2C4, pdata)
+
+#define db8500_add_msp0_i2s(pdata) \
+        dbx500_add_msp_i2s(0, U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_i2s(pdata) \
+        dbx500_add_msp_i2s(1, U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_i2s(pdata) \
+        dbx500_add_msp_i2s(2, U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_i2s(pdata) \
+        dbx500_add_msp_i2s(3, U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_msp0_spi(pdata) \
+        dbx500_add_msp_spi("msp0", U8500_MSP0_BASE, IRQ_DB8500_MSP0, pdata)
+#define db8500_add_msp1_spi(pdata) \
+        dbx500_add_msp_spi("msp1", U8500_MSP1_BASE, IRQ_DB8500_MSP1, pdata)
+#define db8500_add_msp2_spi(pdata) \
+        dbx500_add_msp_spi("msp2", U8500_MSP2_BASE, IRQ_DB8500_MSP2, pdata)
+#define db8500_add_msp3_spi(pdata) \
+        dbx500_add_msp_spi("msp3", U8500_MSP3_BASE, IRQ_DB8500_MSP1, pdata)
+
+#define db8500_add_rtc() \
+        dbx500_add_rtc(U8500_RTC_BASE, IRQ_DB8500_RTC);
+
+#define db8500_add_sdi0(pdata) \
+        dbx500_add_sdi("sdi0", U8500_SDI0_BASE, IRQ_DB8500_SDMMC0, pdata)
+#define db8500_add_sdi1(pdata) \
+        dbx500_add_sdi("sdi1", U8500_SDI1_BASE, IRQ_DB8500_SDMMC1, pdata)
+#define db8500_add_sdi2(pdata) \
+        dbx500_add_sdi("sdi2", U8500_SDI2_BASE, IRQ_DB8500_SDMMC2, pdata)
+#define db8500_add_sdi3(pdata) \
+        dbx500_add_sdi("sdi3", U8500_SDI3_BASE, IRQ_DB8500_SDMMC3, pdata)
+#define db8500_add_sdi4(pdata) \
+        dbx500_add_sdi("sdi4", U8500_SDI4_BASE, IRQ_DB8500_SDMMC4, pdata)
+#define db8500_add_sdi5(pdata) \
+        dbx500_add_sdi("sdi5", U8500_SDI5_BASE, IRQ_DB8500_SDMMC5, pdata)
+
+#define db8500_add_ssp0(pdata) \
+        db8500_add_ssp("ssp0", U8500_SSP0_BASE, IRQ_DB8500_SSP0, pdata)
+#define db8500_add_ssp1(pdata) \
+        db8500_add_ssp("ssp1", U8500_SSP1_BASE, IRQ_DB8500_SSP1, pdata)
+
+#define db8500_add_spi0(pdata) \
+        dbx500_add_spi("spi0", U8500_SPI0_BASE, IRQ_DB8500_SPI0, pdata)
+#define db8500_add_spi1(pdata) \
+        dbx500_add_spi("spi1", U8500_SPI1_BASE, IRQ_DB8500_SPI1, pdata)
+#define db8500_add_spi2(pdata) \
+        dbx500_add_spi("spi2", U8500_SPI2_BASE, IRQ_DB8500_SPI2, pdata)
+#define db8500_add_spi3(pdata) \
+        dbx500_add_spi("spi3", U8500_SPI3_BASE, IRQ_DB8500_SPI3, pdata)
+
+#define db8500_add_uart0() \
+        dbx500_add_uart("uart0", U8500_UART0_BASE, IRQ_DB8500_UART0)
+#define db8500_add_uart1() \
+        dbx500_add_uart("uart1", U8500_UART1_BASE, IRQ_DB8500_UART1)
+#define db8500_add_uart2() \
+        dbx500_add_uart("uart2", U8500_UART2_BASE, IRQ_DB8500_UART2)
+
+#endif
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
index 8a268893cb7f..ea0a2f92ca70 100644
--- a/arch/arm/mach-ux500/devices.c
+++ b/arch/arm/mach-ux500/devices.c
@@ -14,69 +14,6 @@
 #include <mach/hardware.h>
 #include <mach/setup.h>
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
-
-struct amba_device ux500_pl031_device = {
-        .dev = {
-                .init_name = "pl031",
-        },
-        .res = {
-                .start  = UX500_RTC_BASE,
-                .end    = UX500_RTC_BASE + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        .irq = {IRQ_RTC_RTT, NO_IRQ},
-};
-
-struct amba_device ux500_uart0_device = {
-        .dev = { .init_name = "uart0" },
-        __MEM_4K_RESOURCE(UX500_UART0_BASE),
-        .irq = {IRQ_UART0, NO_IRQ},
-};
-
-struct amba_device ux500_uart1_device = {
-        .dev = { .init_name = "uart1" },
-        __MEM_4K_RESOURCE(UX500_UART1_BASE),
-        .irq = {IRQ_UART1, NO_IRQ},
-};
-
-struct amba_device ux500_uart2_device = {
-        .dev = { .init_name = "uart2" },
-        __MEM_4K_RESOURCE(UX500_UART2_BASE),
-        .irq = {IRQ_UART2, NO_IRQ},
-};
-
-#define UX500_I2C_RESOURCES(id, size)                           \
-static struct resource ux500_i2c##id##_resources[] = {          \
-        [0] = {                                                 \
-                .start  = UX500_I2C##id##_BASE,                 \
-                .end    = UX500_I2C##id##_BASE + size - 1,      \
-                .flags  = IORESOURCE_MEM,                       \
-        },                                                      \
-        [1] = {                                                 \
-                .start  = IRQ_I2C##id,                          \
-                .end    = IRQ_I2C##id,                          \
-                .flags  = IORESOURCE_IRQ                        \
-        }                                                       \
-}
-
-UX500_I2C_RESOURCES(1, SZ_4K);
-UX500_I2C_RESOURCES(2, SZ_4K);
-UX500_I2C_RESOURCES(3, SZ_4K);
-
-#define UX500_I2C_PDEVICE(cid)                                  \
-struct platform_device ux500_i2c##cid##_device = {              \
-        .name           = "nmk-i2c",                            \
-        .id             = cid,                                  \
-        .num_resources  = 2,                                    \
-        .resource       = ux500_i2c##cid##_resources,           \
-}
-
-UX500_I2C_PDEVICE(1);
-UX500_I2C_PDEVICE(2);
-UX500_I2C_PDEVICE(3);
-
 void __init amba_add_devices(struct amba_device *devs[], int num)
 {
         int i;
diff --git a/arch/arm/mach-ux500/dma-db5500.c b/arch/arm/mach-ux500/dma-db5500.c
new file mode 100644
index 000000000000..32a061f8a95b
--- /dev/null
+++ b/arch/arm/mach-ux500/dma-db5500.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
+ * Author: Rabin Vincent <rabinv.vincent@stericsson.com> for ST-Ericsson
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <plat/ste_dma40.h>
+#include <mach/setup.h>
+#include <mach/hardware.h>
+
+#include "ste-dma40-db5500.h"
+
+static struct resource dma40_resources[] = {
+        [0] = {
+                .start = U5500_DMA_BASE,
+                .end   = U5500_DMA_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+                .name  = "base",
+        },
+        [1] = {
+                .start = U5500_DMA_LCPA_BASE,
+                .end   = U5500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
+                .flags = IORESOURCE_MEM,
+                .name  = "lcpa",
+        },
+        [2] = {
+                .start = IRQ_DB5500_DMA,
+                .end   = IRQ_DB5500_DMA,
+                .flags = IORESOURCE_IRQ
+        }
+};
+
+/* Default configuration for physical memcpy */
+static struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
+        .mode = STEDMA40_MODE_PHYSICAL,
+        .dir = STEDMA40_MEM_TO_MEM,
+
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .src_info.psize = STEDMA40_PSIZE_PHY_1,
+        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.psize = STEDMA40_PSIZE_PHY_1,
+        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
+/* Default configuration for logical memcpy */
+static struct stedma40_chan_cfg dma40_memcpy_conf_log = {
+        .dir = STEDMA40_MEM_TO_MEM,
+
+        .src_info.data_width = STEDMA40_BYTE_WIDTH,
+        .src_info.psize = STEDMA40_PSIZE_LOG_1,
+        .src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+
+        .dst_info.data_width = STEDMA40_BYTE_WIDTH,
+        .dst_info.psize = STEDMA40_PSIZE_LOG_1,
+        .dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
+};
+
+/*
+ * Mapping between soruce event lines and physical device address This was
+ * created assuming that the event line is tied to a device and therefore the
+ * address is constant, however this is not true for at least USB, and the
+ * values are just placeholders for USB.  This table is preserved and used for
+ * now.
+ */
+static const dma_addr_t dma40_rx_map[DB5500_DMA_NR_DEV] = {
+        [DB5500_DMA_DEV24_SDMMC0_RX] = -1,
+};
+
+/* Mapping between destination event lines and physical device address */
+static const dma_addr_t dma40_tx_map[DB5500_DMA_NR_DEV] = {
+        [DB5500_DMA_DEV24_SDMMC0_TX] = -1,
+};
+
+static int dma40_memcpy_event[] = {
+        DB5500_DMA_MEMCPY_TX_1,
+        DB5500_DMA_MEMCPY_TX_2,
+        DB5500_DMA_MEMCPY_TX_3,
+        DB5500_DMA_MEMCPY_TX_4,
+        DB5500_DMA_MEMCPY_TX_5,
+};
+
+static struct stedma40_platform_data dma40_plat_data = {
+        .dev_len                = ARRAY_SIZE(dma40_rx_map),
+        .dev_rx                 = dma40_rx_map,
+        .dev_tx                 = dma40_tx_map,
+        .memcpy                 = dma40_memcpy_event,
+        .memcpy_len             = ARRAY_SIZE(dma40_memcpy_event),
+        .memcpy_conf_phy        = &dma40_memcpy_conf_phy,
+        .memcpy_conf_log        = &dma40_memcpy_conf_log,
+        .disabled_channels      = {-1},
+};
+
+static struct platform_device dma40_device = {
+        .dev = {
+                .platform_data = &dma40_plat_data,
+        },
+        .name           = "dma40",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(dma40_resources),
+        .resource       = dma40_resources
+};
+
+void __init db5500_dma_init(void)
+{
+        int ret;
+
+        ret = platform_device_register(&dma40_device);
+        if (ret)
+                dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
+
+}
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index 3eafc0e24ba5..bd88c1e74060 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -114,4 +114,8 @@
 #define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
 #define U5500_MBOX2_LOCAL_END   (U5500_MBOX_BASE + 0x3F)
 
+#define U5500_ESRAM_BASE                0x40000000
+#define U5500_ESRAM_DMA_LCPA_OFFSET     0x10000
+#define U5500_DMA_LCPA_BASE    (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
+
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index f07d0986409d..0fefb34c11e4 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -92,7 +92,8 @@
 #define U8500_SCR_BASE          (U8500_PER4_BASE + 0x05000)
 #define U8500_DMC_BASE          (U8500_PER4_BASE + 0x06000)
 #define U8500_PRCMU_BASE        (U8500_PER4_BASE + 0x07000)
-#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x68000)
 
 /* per3 base addresses */
 #define U8500_FSMC_BASE         (U8500_PER3_BASE + 0x0000)
diff --git a/arch/arm/mach-ux500/include/mach/devices.h b/arch/arm/mach-ux500/include/mach/devices.h
index b91a4d1211a2..020b6369a30a 100644
--- a/arch/arm/mach-ux500/include/mach/devices.h
+++ b/arch/arm/mach-ux500/include/mach/devices.h
@@ -14,27 +14,10 @@ extern struct platform_device u5500_gpio_devs[];
 extern struct platform_device u8500_gpio_devs[];
 
 extern struct amba_device ux500_pl031_device;
-extern struct amba_device u8500_ssp0_device;
-extern struct amba_device ux500_uart0_device;
-extern struct amba_device ux500_uart1_device;
-extern struct amba_device ux500_uart2_device;
 
-extern struct platform_device ux500_i2c1_device;
-extern struct platform_device ux500_i2c2_device;
-extern struct platform_device ux500_i2c3_device;
-
-extern struct platform_device u8500_i2c0_device;
-extern struct platform_device u8500_i2c4_device;
 extern struct platform_device u8500_dma40_device;
 extern struct platform_device ux500_ske_keypad_device;
 
-extern struct amba_device u8500_sdi0_device;
-extern struct amba_device u8500_sdi1_device;
-extern struct amba_device u8500_sdi2_device;
-extern struct amba_device u8500_sdi3_device;
-extern struct amba_device u8500_sdi4_device;
-extern struct amba_device u8500_sdi5_device;
-
 void dma40_u8500ed_fixup(void);
 
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/gpio.h b/arch/arm/mach-ux500/include/mach/gpio.h
index d548a622e7d2..3c4cd31ad9f7 100644
--- a/arch/arm/mach-ux500/include/mach/gpio.h
+++ b/arch/arm/mach-ux500/include/mach/gpio.h
@@ -9,42 +9,4 @@
 
 #include <plat/gpio.h>
 
-#define __GPIO_RESOURCE(soc, block)                                     \
-        {                                                               \
-                .start  = soc##_GPIOBANK##block##_BASE,                 \
-                .end    = soc##_GPIOBANK##block##_BASE + 127,           \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        {                                                               \
-                .start  = IRQ_GPIO##block,                              \
-                .end    = IRQ_GPIO##block,                              \
-                .flags  = IORESOURCE_IRQ,                               \
-        }
-
-#define __GPIO_DEVICE(soc, block)                                       \
-        {                                                               \
-                .name           = "gpio",                               \
-                .id             = block,                                \
-                .num_resources  = 2,                                    \
-                .resource       = &soc##_gpio_resources[block * 2],     \
-                .dev = {                                                \
-                        .platform_data = &soc##_gpio_data[block],       \
-                },                                                      \
-        }
-
-#define GPIO_DATA(_name, first)                                         \
-        {                                                               \
-                .name           = _name,                                \
-                .first_gpio     = first,                                \
-                .first_irq      = NOMADIK_GPIO_TO_IRQ(first),           \
-        }
-
-#ifdef CONFIG_UX500_SOC_DB8500
-#define GPIO_RESOURCE(block)    __GPIO_RESOURCE(U8500, block)
-#define GPIO_DEVICE(block)      __GPIO_DEVICE(u8500, block)
-#elif defined(CONFIG_UX500_SOC_DB5500)
-#define GPIO_RESOURCE(block)    __GPIO_RESOURCE(U5500, block)
-#define GPIO_DEVICE(block)      __GPIO_DEVICE(u5500, block)
-#endif
-
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index 32e883a8f2a2..6295cc581355 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -142,6 +142,8 @@ static inline bool cpu_is_u5500(void)
 #endif
 }
 
+#define ARRAY_AND_SIZE(x)       (x), ARRAY_SIZE(x)
+
 #endif
 
 #endif                          /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index cca4f705601e..7cdeb2af0ebb 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -8,12 +8,36 @@
 #ifndef __MACH_IRQS_BOARD_MOP500_H
 #define __MACH_IRQS_BOARD_MOP500_H
 
-#define AB8500_NR_IRQS                  104
+/* Number of AB8500 irqs is taken from header file */
+#include <linux/mfd/ab8500.h>
 
 #define MOP500_AB8500_IRQ_BASE          IRQ_BOARD_START
 #define MOP500_AB8500_IRQ_END           (MOP500_AB8500_IRQ_BASE \
                                          + AB8500_NR_IRQS)
-#define MOP500_IRQ_END                  MOP500_AB8500_IRQ_END
+
+/* TC35892 */
+#define TC35892_NR_INTERNAL_IRQS        8
+#define TC35892_INT_GPIO(x)             (TC35892_NR_INTERNAL_IRQS + (x))
+#define TC35892_NR_GPIOS                24
+#define TC35892_NR_IRQS                 TC35892_INT_GPIO(TC35892_NR_GPIOS)
+
+#define MOP500_EGPIO_NR_IRQS            TC35892_NR_IRQS
+
+#define MOP500_EGPIO_IRQ_BASE           MOP500_AB8500_IRQ_END
+#define MOP500_EGPIO_IRQ_END            (MOP500_EGPIO_IRQ_BASE \
+                                         + MOP500_EGPIO_NR_IRQS)
+/* STMPE1601 irqs */
+#define STMPE_NR_INTERNAL_IRQS          9
+#define STMPE_INT_GPIO(x)               (STMPE_NR_INTERNAL_IRQS + (x))
+#define STMPE_NR_GPIOS                  24
+#define STMPE_NR_IRQS                   STMPE_INT_GPIO(STMPE_NR_GPIOS)
+
+#define MOP500_STMPE1601_IRQBASE        MOP500_EGPIO_IRQ_END
+#define MOP500_STMPE1601_IRQ(x)         (MOP500_STMPE1601_IRQBASE + (x))
+
+#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
+
+#define MOP500_IRQ_END          MOP500_NR_IRQS
 
 #if MOP500_IRQ_END > IRQ_BOARD_END
 #undef IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 693aa57de88d..880ae45bc235 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -21,50 +21,6 @@
 
 /* Interrupt numbers generic for shared peripheral */
 #define IRQ_MTU0                (IRQ_SHPI_START + 4)
-#define IRQ_SPI2                (IRQ_SHPI_START + 6)
-#define IRQ_SPI0                (IRQ_SHPI_START + 8)
-#define IRQ_UART0               (IRQ_SHPI_START + 11)
-#define IRQ_I2C3                (IRQ_SHPI_START + 12)
-#define IRQ_SSP0                (IRQ_SHPI_START + 14)
-#define IRQ_MTU1                (IRQ_SHPI_START + 17)
-#define IRQ_RTC_RTT             (IRQ_SHPI_START + 18)
-#define IRQ_UART1               (IRQ_SHPI_START + 19)
-#define IRQ_I2C0                (IRQ_SHPI_START + 21)
-#define IRQ_I2C1                (IRQ_SHPI_START + 22)
-#define IRQ_USBOTG              (IRQ_SHPI_START + 23)
-#define IRQ_DMA                 (IRQ_SHPI_START + 25)
-#define IRQ_UART2               (IRQ_SHPI_START + 26)
-#define IRQ_HSIR_EXCEP          (IRQ_SHPI_START + 29)
-#define IRQ_MSP0                (IRQ_SHPI_START + 31)
-#define IRQ_HSIR_CH0_OVRRUN     (IRQ_SHPI_START + 32)
-#define IRQ_HSIR_CH1_OVRRUN     (IRQ_SHPI_START + 33)
-#define IRQ_HSIR_CH2_OVRRUN     (IRQ_SHPI_START + 34)
-#define IRQ_HSIR_CH3_OVRRUN     (IRQ_SHPI_START + 35)
-#define IRQ_AB8500              (IRQ_SHPI_START + 40)
-#define IRQ_PRCMU               (IRQ_SHPI_START + 47)
-#define IRQ_DISP                (IRQ_SHPI_START + 48)
-#define IRQ_SiPI3               (IRQ_SHPI_START + 49)
-#define IRQ_I2C4                (IRQ_SHPI_START + 51)
-#define IRQ_SSP1                (IRQ_SHPI_START + 52)
-#define IRQ_I2C2                (IRQ_SHPI_START + 55)
-#define IRQ_SDMMC0              (IRQ_SHPI_START + 60)
-#define IRQ_MSP1                (IRQ_SHPI_START + 62)
-#define IRQ_SPI1                (IRQ_SHPI_START + 96)
-#define IRQ_MSP2                (IRQ_SHPI_START + 98)
-#define IRQ_SDMMC4              (IRQ_SHPI_START + 99)
-#define IRQ_HSIRD0              (IRQ_SHPI_START + 104)
-#define IRQ_HSIRD1              (IRQ_SHPI_START + 105)
-#define IRQ_HSITD0              (IRQ_SHPI_START + 106)
-#define IRQ_HSITD1              (IRQ_SHPI_START + 107)
-#define IRQ_GPIO0               (IRQ_SHPI_START + 119)
-#define IRQ_GPIO1               (IRQ_SHPI_START + 120)
-#define IRQ_GPIO2               (IRQ_SHPI_START + 121)
-#define IRQ_GPIO3               (IRQ_SHPI_START + 122)
-#define IRQ_GPIO4               (IRQ_SHPI_START + 123)
-#define IRQ_GPIO5               (IRQ_SHPI_START + 124)
-#define IRQ_GPIO6               (IRQ_SHPI_START + 125)
-#define IRQ_GPIO7               (IRQ_SHPI_START + 126)
-#define IRQ_GPIO8               (IRQ_SHPI_START + 127)
 
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
diff --git a/arch/arm/mach-ux500/include/mach/mbox.h b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
index 7f9da4d2fbda..7f9da4d2fbda 100644
--- a/arch/arm/mach-ux500/include/mach/mbox.h
+++ b/arch/arm/mach-ux500/include/mach/mbox-db5500.h
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
new file mode 100644
index 000000000000..848ba64b561f
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Martin Persson <martin.persson@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit definitions
+ */
+
+#ifndef __MACH_PRCMU_DEFS_H
+#define __MACH_PRCMU_DEFS_H
+
+enum prcmu_cpu_opp {
+        CPU_OPP_INIT      = 0x00,
+        CPU_OPP_NO_CHANGE = 0x01,
+        CPU_OPP_100       = 0x02,
+        CPU_OPP_50        = 0x03,
+        CPU_OPP_MAX       = 0x04,
+        CPU_OPP_EXT_CLK   = 0x07
+};
+enum prcmu_ape_opp {
+        APE_OPP_NO_CHANGE = 0x00,
+        APE_OPP_100       = 0x02,
+        APE_OPP_50        = 0x03,
+};
+
+#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
index 8885f39a6421..455467e88791 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
@@ -1,10 +1,15 @@
 /*
- * Copyright (c) 2009 ST-Ericsson SA
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation.
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
  */
+
 #ifndef __MACH_PRCMU_REGS_H
 #define __MACH_PRCMU_REGS_H
 
@@ -88,4 +93,4 @@
 /* Miscellaneous unit registers */
 #define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
 
-#endif /* __MACH_PRCMU__REGS_H */
+#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
index 549843ff6dbe..c49e456162ef 100644
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ b/arch/arm/mach-ux500/include/mach/prcmu.h
@@ -2,14 +2,27 @@
  * Copyright (C) STMicroelectronics 2009
  * Copyright (C) ST-Ericsson SA 2010
  *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
  * License Terms: GNU General Public License v2
  *
- * PRCMU f/w APIs
+ * PRCM Unit f/w API
  */
 #ifndef __MACH_PRCMU_H
 #define __MACH_PRCMU_H
+#include <mach/prcmu-defs.h>
 
+void __init prcmu_early_init(void);
 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
+int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
+int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
+                           enum prcmu_cpu_opp cpu_opp);
+int prcmu_get_ape_opp(void);
+int prcmu_get_cpu_opp(void);
+bool prcmu_has_arm_maxopp(void);
 
 #endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/setup.h b/arch/arm/mach-ux500/include/mach/setup.h
index 54bbe648bf58..469877e0de90 100644
--- a/arch/arm/mach-ux500/include/mach/setup.h
+++ b/arch/arm/mach-ux500/include/mach/setup.h
@@ -18,14 +18,19 @@ extern void __init ux500_map_io(void);
 extern void __init u5500_map_io(void);
 extern void __init u8500_map_io(void);
 
-extern void __init ux500_init_devices(void);
 extern void __init u5500_init_devices(void);
 extern void __init u8500_init_devices(void);
 
 extern void __init ux500_init_irq(void);
+
+extern void __init u5500_sdi_init(void);
+
+extern void __init db5500_dma_init(void);
+
 /* We re-use nomadik_timer for this platform */
 extern void nmdk_timer_init(void);
 
+struct amba_device;
 extern void __init amba_add_devices(struct amba_device *devs[], int num);
 
 struct sys_timer;
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 0271ca0a83df..9a6614c6808e 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -19,38 +19,43 @@
 #define __ASM_ARCH_UNCOMPRESS_H
 
 #include <asm/setup.h>
+#include <asm/mach-types.h>
 #include <linux/io.h>
+#include <linux/amba/serial.h>
 #include <mach/hardware.h>
 
-#define U8500_UART_DR           0x80007000
-#define U8500_UART_LCRH         0x8000702c
-#define U8500_UART_CR           0x80007030
-#define U8500_UART_FR           0x80007018
+static u32 ux500_uart_base;
 
 static void putc(const char c)
 {
         /* Do nothing if the UART is not enabled. */
-        if (!(__raw_readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
                 return;
 
         if (c == '\n')
                 putc('\r');
 
-        while (__raw_readb(U8500_UART_FR) & (1 << 5))
+        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 5))
                 barrier();
-        __raw_writeb(c, U8500_UART_DR);
+        __raw_writeb(c, ux500_uart_base + UART01x_DR);
 }
 
 static void flush(void)
 {
-        if (!(__raw_readb(U8500_UART_CR) & 0x1))
+        if (!(__raw_readb(ux500_uart_base + UART011_CR) & 0x1))
                 return;
-        while (__raw_readb(U8500_UART_FR) & (1 << 3))
+        while (__raw_readb(ux500_uart_base + UART01x_FR) & (1 << 3))
                 barrier();
 }
 
 static inline void arch_decomp_setup(void)
 {
+        if (machine_is_u8500())
+                ux500_uart_base = U8500_UART2_BASE;
+        else if (machine_is_u5500())
+                ux500_uart_base = U5500_UART0_BASE;
+        else /* not much can be done to help here */
+                ux500_uart_base = U8500_UART2_BASE;
 }
 
 #define arch_decomp_wdog() /* nothing to do here */
diff --git a/arch/arm/mach-ux500/mbox.c b/arch/arm/mach-ux500/mbox-db5500.c
index 63435389c544..cbf15718fc3c 100644
--- a/arch/arm/mach-ux500/mbox.c
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -38,7 +38,7 @@
 #include <linux/debugfs.h>
 #include <linux/seq_file.h>
 #include <linux/completion.h>
-#include <mach/mbox.h>
+#include <mach/mbox-db5500.h>
 
 #define MBOX_NAME "mbox"
 
diff --git a/arch/arm/mach-ux500/modem_irq.c b/arch/arm/mach-ux500/modem-irq-db5500.c
index 3187f8871169..3187f8871169 100644
--- a/arch/arm/mach-ux500/modem_irq.c
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 9e4c678de785..ade2e17f253c 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -26,7 +26,7 @@
  * control for which core is the next to come out of the secondary
  * boot "holding pen"
  */
-volatile int __cpuinitdata pen_release = -1;
+volatile int pen_release = -1;
 
 static unsigned int __init get_core_count(void)
 {
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
index 293274d1342a..c522d26ef348 100644
--- a/arch/arm/mach-ux500/prcmu.c
+++ b/arch/arm/mach-ux500/prcmu.c
@@ -1,10 +1,14 @@
 /*
- * Copyright (C) ST Ericsson SA 2010
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
  *
  * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
  *
- * U8500 PRCMU driver.
+ * U8500 PRCM Unit interface driver
+ *
  */
 #include <linux/kernel.h>
 #include <linux/module.h>
@@ -19,11 +23,26 @@
 
 #include <mach/hardware.h>
 #include <mach/prcmu-regs.h>
+#include <mach/prcmu-defs.h>
+
+/* Global var to runtime determine TCDM base for v2 or v1 */
+static __iomem void *tcdm_base;
+
+#define _MBOX_HEADER            (tcdm_base + 0xFE8)
+#define MBOX_HEADER_REQ_MB0     (_MBOX_HEADER + 0x0)
+
+#define REQ_MB1 (tcdm_base + 0xFD0)
+#define REQ_MB5 (tcdm_base + 0xE44)
 
-#define PRCMU_TCDM_BASE __io_address(U8500_PRCMU_TCDM_BASE)
+#define REQ_MB1_ARMOPP          (REQ_MB1 + 0x0)
+#define REQ_MB1_APEOPP          (REQ_MB1 + 0x1)
+#define REQ_MB1_BOOSTOPP        (REQ_MB1 + 0x2)
 
-#define REQ_MB5 (PRCMU_TCDM_BASE + 0xE44)
-#define ACK_MB5 (PRCMU_TCDM_BASE + 0xDF4)
+#define ACK_MB1 (tcdm_base + 0xE04)
+#define ACK_MB5 (tcdm_base + 0xDF4)
+
+#define ACK_MB1_CURR_ARMOPP             (ACK_MB1 + 0x0)
+#define ACK_MB1_CURR_APEOPP             (ACK_MB1 + 0x1)
 
 #define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
 #define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
@@ -33,10 +52,33 @@
 #define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
 #define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
 
-#define I2C_WRITE(slave) ((slave) << 1)
-#define I2C_READ(slave) (((slave) << 1) | BIT(0))
+#define PRCM_AVS_VARM_MAX_OPP           (tcdm_base + 0x2E4)
+#define PRCM_AVS_ISMODEENABLE           7
+#define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
+
+#define I2C_WRITE(slave) \
+        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
+#define I2C_READ(slave) \
+        (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
 #define I2C_STOP_EN BIT(3)
 
+enum mb1_h {
+        MB1H_ARM_OPP = 1,
+        MB1H_APE_OPP,
+        MB1H_ARM_APE_OPP,
+};
+
+static struct {
+        struct mutex lock;
+        struct completion work;
+        struct {
+                u8 arm_opp;
+                u8 ape_opp;
+                u8 arm_status;
+                u8 ape_status;
+        } ack;
+} mb1_transfer;
+
 enum ack_mb5_status {
         I2C_WR_OK = 0x01,
         I2C_RD_OK = 0x02,
@@ -145,6 +187,104 @@ unlock_and_return:
 }
 EXPORT_SYMBOL(prcmu_abb_write);
 
+static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
+                            enum prcmu_cpu_opp cpu_opp)
+{
+        bool do_ape;
+        bool do_arm;
+        int err = 0;
+
+        do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
+        do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
+
+        mutex_lock(&mb1_transfer.lock);
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+                cpu_relax();
+
+        writeb(0, MBOX_HEADER_REQ_MB0);
+        writeb(cpu_opp, REQ_MB1_ARMOPP);
+        writeb(ape_opp, REQ_MB1_APEOPP);
+        writeb(0, REQ_MB1_BOOSTOPP);
+        writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
+        wait_for_completion(&mb1_transfer.work);
+        if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
+                err = -EIO;
+        if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
+                err = -EIO;
+
+        mutex_unlock(&mb1_transfer.lock);
+
+        return err;
+}
+
+/**
+ * prcmu_set_ape_opp() - Set the OPP of the APE.
+ * @opp:        The OPP to set.
+ *
+ * This function sets the OPP of the APE.
+ */
+int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
+{
+        return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
+}
+EXPORT_SYMBOL(prcmu_set_ape_opp);
+
+/**
+ * prcmu_set_cpu_opp() - Set the OPP of the CPU.
+ * @opp:        The OPP to set.
+ *
+ * This function sets the OPP of the CPU.
+ */
+int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
+{
+        return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
+}
+EXPORT_SYMBOL(prcmu_set_cpu_opp);
+
+/**
+ * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
+ * @ape_opp:    The APE OPP to set.
+ * @cpu_opp:    The CPU OPP to set.
+ *
+ * This function sets the OPPs of the APE and the CPU.
+ */
+int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
+                           enum prcmu_cpu_opp cpu_opp)
+{
+        return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
+}
+EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
+
+/**
+ * prcmu_get_ape_opp() - Get the OPP of the APE.
+ *
+ * This function gets the OPP of the APE.
+ */
+enum prcmu_ape_opp prcmu_get_ape_opp(void)
+{
+        return readb(ACK_MB1_CURR_APEOPP);
+}
+EXPORT_SYMBOL(prcmu_get_ape_opp);
+
+/**
+ * prcmu_get_cpu_opp() - Get the OPP of the CPU.
+ *
+ * This function gets the OPP of the CPU. The OPP is specified in %%.
+ * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
+ */
+int prcmu_get_cpu_opp(void)
+{
+        return readb(ACK_MB1_CURR_ARMOPP);
+}
+EXPORT_SYMBOL(prcmu_get_cpu_opp);
+
+bool prcmu_has_arm_maxopp(void)
+{
+        return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
+                == PRCM_AVS_ISMODEENABLE_MASK;
+}
+
 static void read_mailbox_0(void)
 {
         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
@@ -152,6 +292,9 @@ static void read_mailbox_0(void)
 
 static void read_mailbox_1(void)
 {
+        mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
+        mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
+        complete(&mb1_transfer.work);
         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
 }
 
@@ -217,15 +360,35 @@ static irqreturn_t prcmu_irq_handler(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+void __init prcmu_early_init(void)
+{
+        if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
+                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
+        } else if (cpu_is_u8500v2()) {
+                tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
+        } else {
+                pr_err("prcmu: Unsupported chip version\n");
+                BUG();
+        }
+}
+
 static int __init prcmu_init(void)
 {
+        if (cpu_is_u8500ed()) {
+                pr_err("prcmu: Unsupported chip version\n");
+                return 0;
+        }
+
+        mutex_init(&mb1_transfer.lock);
+        init_completion(&mb1_transfer.work);
         mutex_init(&mb5_transfer.lock);
         init_completion(&mb5_transfer.work);
 
         /* Clean up the mailbox interrupts after pre-kernel code. */
         writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
 
-        return request_irq(IRQ_PRCMU, prcmu_irq_handler, 0, "prcmu", NULL);
+        return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
+                           "prcmu", NULL);
 }
 
 arch_initcall(prcmu_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4414a01e1e8a..a099efed0e63 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -382,6 +382,12 @@ config CPU_FEROCEON_OLD_ID
           for which the CPU ID is equal to the ARM926 ID.
           Relevant for Feroceon-1850 and early Feroceon-2850.
 
+# Marvell PJ4
+config CPU_PJ4
+        bool
+        select CPU_V7
+        select ARM_THUMBEE
+
 # ARMv6
 config CPU_V6
         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || ARCH_DOVE
@@ -789,7 +795,7 @@ config CACHE_PL310
 
 config CACHE_TAUROS2
         bool "Enable the Tauros2 L2 cache controller"
-        depends on (ARCH_DOVE || ARCH_MMP)
+        depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
         default y
         select OUTER_CACHE
         help
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 99fa688dfadd..c96fa1b3f49f 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -203,6 +203,10 @@ ENTRY(v6_flush_kern_dcache_area)
  *      - end     - virtual end address of region
  */
 v6_dma_inv_range:
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrb    r2, [r0]                        @ read for ownership
+        strb    r2, [r0]                        @ write for ownership
+#endif
         tst     r0, #D_CACHE_LINE_SIZE - 1
         bic     r0, r0, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
@@ -211,6 +215,10 @@ v6_dma_inv_range:
         mcrne   p15, 0, r0, c7, c11, 1          @ clean unified line
 #endif
         tst     r1, #D_CACHE_LINE_SIZE - 1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrneb  r2, [r1, #-1]                   @ read for ownership
+        strneb  r2, [r1, #-1]                   @ write for ownership
+#endif
         bic     r1, r1, #D_CACHE_LINE_SIZE - 1
 #ifdef HARVARD_CACHE
         mcrne   p15, 0, r1, c7, c14, 1          @ clean & invalidate D line
@@ -218,10 +226,6 @@ v6_dma_inv_range:
         mcrne   p15, 0, r1, c7, c15, 1          @ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
-        str     r2, [r0]                        @ write for ownership
-#endif
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c6, 1           @ invalidate D line
 #else
@@ -229,6 +233,10 @@ v6_dma_inv_range:
 #endif
         add     r0, r0, #D_CACHE_LINE_SIZE
         cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlo   r2, [r0]                        @ read for ownership
+        strlo   r2, [r0]                        @ write for ownership
+#endif
         blo     1b
         mov     r0, #0
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
@@ -263,12 +271,12 @@ v6_dma_clean_range:
  *      - end     - virtual end address of region
  */
 ENTRY(v6_dma_flush_range)
-        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
-1:
 #ifdef CONFIG_DMA_CACHE_RWFO
-        ldr     r2, [r0]                        @ read for ownership
-        str     r2, [r0]                        @ write for ownership
+        ldrb    r2, [r0]                @ read for ownership
+        strb    r2, [r0]                @ write for ownership
 #endif
+        bic     r0, r0, #D_CACHE_LINE_SIZE - 1
+1:
 #ifdef HARVARD_CACHE
         mcr     p15, 0, r0, c7, c14, 1          @ clean & invalidate D line
 #else
@@ -276,6 +284,10 @@ ENTRY(v6_dma_flush_range)
 #endif
         add     r0, r0, #D_CACHE_LINE_SIZE
         cmp     r0, r1
+#ifdef CONFIG_DMA_CACHE_RWFO
+        ldrlob  r2, [r0]                        @ read for ownership
+        strlob  r2, [r0]                        @ write for ownership
+#endif
         blo     1b
         mov     r0, #0
         mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a3ebf7a4f49b..6136e68ce953 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -173,15 +173,22 @@ ENTRY(v7_coherent_user_range)
  UNWIND(.fnstart                )
         dcache_line_size r2, r3
         sub     r3, r2, #1
-        bic     r0, r0, r3
+        bic     r12, r0, r3
 1:
- USER(  mcr     p15, 0, r0, c7, c11, 1  )       @ clean D line to the point of unification
+ USER(  mcr     p15, 0, r12, c7, c11, 1 )       @ clean D line to the point of unification
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     1b
         dsb
- USER(  mcr     p15, 0, r0, c7, c5, 1   )       @ invalidate I line
-        add     r0, r0, r2
+        icache_line_size r2, r3
+        sub     r3, r2, #1
+        bic     r12, r0, r3
 2:
-        cmp     r0, r1
-        blo     1b
+ USER(  mcr     p15, 0, r12, c7, c5, 1  )       @ invalidate I line
+        add     r12, r12, r2
+        cmp     r12, r1
+        blo     2b
+3:
         mov     r0, #0
         ALT_SMP(mcr     p15, 0, r0, c7, c1, 6)  @ invalidate BTB Inner Shareable
         ALT_UP(mcr      p15, 0, r0, c7, c5, 6)  @ invalidate BTB
@@ -194,10 +201,10 @@ ENTRY(v7_coherent_user_range)
  * isn't mapped, just try the next page.
  */
 9001:
-        mov     r0, r0, lsr #12
-        mov     r0, r0, lsl #12
-        add     r0, r0, #4096
-        b       2b
+        mov     r12, r12, lsr #12
+        mov     r12, r12, lsl #12
+        add     r12, r12, #4096
+        b       3b
  UNWIND(.fnend          )
 ENDPROC(v7_coherent_kern_range)
 ENDPROC(v7_coherent_user_range)
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63beaf9745..b795afd0a2c6 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -61,17 +61,27 @@
         .endm
 
 /*
- * cache_line_size - get the cache line size from the CSIDR register
- * (available on ARMv7+). It assumes that the CSSR register was configured
- * to access the L1 data cache CSIDR.
+ * dcache_line_size - get the minimum D-cache line size from the CTR register
+ * on ARMv7.
  */
         .macro  dcache_line_size, reg, tmp
-        mrc     p15, 1, \tmp, c0, c0, 0         @ read CSIDR
-        and     \tmp, \tmp, #7                  @ cache line size encoding
-        mov     \reg, #16                       @ size offset
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
+        lsr     \tmp, \tmp, #16
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
         mov     \reg, \reg, lsl \tmp            @ actual cache line size
         .endm
 
+/*
+ * icache_line_size - get the minimum I-cache line size from the CTR register
+ * on ARMv7.
+ */
+        .macro  icache_line_size, reg, tmp
+        mrc     p15, 0, \tmp, c0, c0, 1         @ read ctr
+        and     \tmp, \tmp, #0xf                @ cache line size encoding
+        mov     \reg, #4                        @ bytes per word
+        mov     \reg, \reg, lsl \tmp            @ actual cache line size
+        .endm
 
 /*
  * Sanity check the PTE configuration for the code below - which makes
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 85e6fd212a41..eda4e3a11a3d 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -119,7 +119,7 @@ static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
 }
 
 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
-                             pin_cfg_t cfg)
+                             pin_cfg_t cfg, bool sleep)
 {
         static const char *afnames[] = {
                 [NMK_GPIO_ALT_GPIO]     = "GPIO",
@@ -145,11 +145,34 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
         int output = PIN_DIR(cfg);
         int val = PIN_VAL(cfg);
 
-        dev_dbg(nmk_chip->chip.dev, "pin %d: af %s, pull %s, slpm %s (%s%s)\n",
-                pin, afnames[af], pullnames[pull], slpmnames[slpm],
+        dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
+                pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
                 output ? "output " : "input",
                 output ? (val ? "high" : "low") : "");
 
+        if (sleep) {
+                int slpm_pull = PIN_SLPM_PULL(cfg);
+                int slpm_output = PIN_SLPM_DIR(cfg);
+                int slpm_val = PIN_SLPM_VAL(cfg);
+
+                /*
+                 * The SLPM_* values are normal values + 1 to allow zero to
+                 * mean "same as normal".
+                 */
+                if (slpm_pull)
+                        pull = slpm_pull - 1;
+                if (slpm_output)
+                        output = slpm_output - 1;
+                if (slpm_val)
+                        val = slpm_val - 1;
+
+                dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
+                        pin,
+                        slpm_pull ? pullnames[pull] : "same",
+                        slpm_output ? (output ? "output" : "input") : "same",
+                        slpm_val ? (val ? "high" : "low") : "same");
+        }
+
         if (output)
                 __nmk_gpio_make_output(nmk_chip, offset, val);
         else {
@@ -175,7 +198,7 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
  * side-effects.  The gpio can be manipulated later using standard GPIO API
  * calls.
  */
-int nmk_config_pin(pin_cfg_t cfg)
+int nmk_config_pin(pin_cfg_t cfg, bool sleep)
 {
         struct nmk_gpio_chip *nmk_chip;
         int gpio = PIN_NUM(cfg);
@@ -186,7 +209,7 @@ int nmk_config_pin(pin_cfg_t cfg)
                 return -EINVAL;
 
         spin_lock_irqsave(&nmk_chip->lock, flags);
-        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg);
+        __nmk_config_pin(nmk_chip, gpio - nmk_chip->chip.base, cfg, sleep);
         spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
         return 0;
@@ -207,7 +230,7 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
         int i;
 
         for (i = 0; i < num; i++) {
-                int ret = nmk_config_pin(cfgs[i]);
+                ret = nmk_config_pin(cfgs[i], false);
                 if (ret)
                         break;
         }
@@ -216,6 +239,21 @@ int nmk_config_pins(pin_cfg_t *cfgs, int num)
 }
 EXPORT_SYMBOL(nmk_config_pins);
 
+int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
+{
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < num; i++) {
+                ret = nmk_config_pin(cfgs[i], true);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(nmk_config_pins_sleep);
+
 /**
  * nmk_gpio_set_slpm() - configure the sleep mode of a pin
  * @gpio: pin number
@@ -634,7 +672,7 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev)
 
         chip = &nmk_chip->chip;
         chip->base = pdata->first_gpio;
-        chip->label = pdata->name;
+        chip->label = pdata->name ?: dev_name(&dev->dev);
         chip->dev = &dev->dev;
         chip->owner = THIS_MODULE;
 
diff --git a/arch/arm/plat-nomadik/include/plat/pincfg.h b/arch/arm/plat-nomadik/include/plat/pincfg.h
index 8c5ae3f2acf8..05a3936ae6d1 100644
--- a/arch/arm/plat-nomadik/include/plat/pincfg.h
+++ b/arch/arm/plat-nomadik/include/plat/pincfg.h
@@ -19,16 +19,22 @@
  *      bit  9..10 - Alternate Function Selection
  *      bit 11..12 - Pull up/down state
  *      bit     13 - Sleep mode behaviour
- *      bit     14 - (sleep mode) Direction
- *      bit     15 - (sleep mode) Value (if output)
+ *      bit     14 - Direction
+ *      bit     15 - Value (if output)
+ *      bit 16..18 - SLPM pull up/down state
+ *      bit 19..20 - SLPM direction
+ *      bit 21..22 - SLPM Value (if output)
  *
  * to facilitate the definition, the following macros are provided
  *
  * PIN_CFG_DEFAULT - default config (0):
  *                   pull up/down = disabled
  *                   sleep mode = input/wakeup
- *                   (sleep mode) direction = input
- *                   (sleep mode) value = low
+ *                   direction = input
+ *                   value = low
+ *                   SLPM direction = same as normal
+ *                   SLPM pull = same as normal
+ *                   SLPM value = same as normal
  *
  * PIN_CFG         - default config with alternate function
  * PIN_CFG_PULL    - default config with alternate function and pull up/down
@@ -75,30 +81,64 @@ typedef unsigned long pin_cfg_t;
 #define PIN_VAL_LOW             (0 << PIN_VAL_SHIFT)
 #define PIN_VAL_HIGH            (1 << PIN_VAL_SHIFT)
 
-/* Shortcuts.  Use these instead of separate DIR and VAL.  */
-#define PIN_INPUT               PIN_DIR_INPUT
+#define PIN_SLPM_PULL_SHIFT     16
+#define PIN_SLPM_PULL_MASK      (0x7 << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL(x)        \
+        (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_NONE      \
+        ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_UP        \
+        ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
+#define PIN_SLPM_PULL_DOWN      \
+        ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
+
+#define PIN_SLPM_DIR_SHIFT      19
+#define PIN_SLPM_DIR_MASK       (0x3 << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR(x)         \
+        (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_INPUT      ((1 + 0) << PIN_SLPM_DIR_SHIFT)
+#define PIN_SLPM_DIR_OUTPUT     ((1 + 1) << PIN_SLPM_DIR_SHIFT)
+
+#define PIN_SLPM_VAL_SHIFT      21
+#define PIN_SLPM_VAL_MASK       (0x3 << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL(x)         \
+        (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_LOW        ((1 + 0) << PIN_SLPM_VAL_SHIFT)
+#define PIN_SLPM_VAL_HIGH       ((1 + 1) << PIN_SLPM_VAL_SHIFT)
+
+/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
+#define PIN_INPUT_PULLDOWN      (PIN_DIR_INPUT | PIN_PULL_DOWN)
+#define PIN_INPUT_PULLUP        (PIN_DIR_INPUT | PIN_PULL_UP)
+#define PIN_INPUT_NOPULL        (PIN_DIR_INPUT | PIN_PULL_NONE)
 #define PIN_OUTPUT_LOW          (PIN_DIR_OUTPUT | PIN_VAL_LOW)
 #define PIN_OUTPUT_HIGH         (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
 
-/*
- * These are the same as the ones above, but should make more sense to the
- * reader when seen along with a setting a pin to AF mode.
- */
-#define PIN_SLPM_INPUT          PIN_INPUT
-#define PIN_SLPM_OUTPUT_LOW     PIN_OUTPUT_LOW
-#define PIN_SLPM_OUTPUT_HIGH    PIN_OUTPUT_HIGH
+#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
+#define PIN_SLPM_INPUT_PULLUP   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
+#define PIN_SLPM_INPUT_NOPULL   (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
+#define PIN_SLPM_OUTPUT_LOW     (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
+#define PIN_SLPM_OUTPUT_HIGH    (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
 
-#define PIN_CFG_DEFAULT         (PIN_PULL_NONE | PIN_SLPM_INPUT)
+#define PIN_CFG_DEFAULT         (0)
 
 #define PIN_CFG(num, alt)               \
         (PIN_CFG_DEFAULT |\
          (PIN_NUM(num) | PIN_##alt))
 
+#define PIN_CFG_INPUT(num, alt, pull)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
+
+#define PIN_CFG_OUTPUT(num, alt, val)           \
+        (PIN_CFG_DEFAULT |\
+         (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
+
 #define PIN_CFG_PULL(num, alt, pull)    \
         ((PIN_CFG_DEFAULT & ~PIN_PULL_MASK) |\
          (PIN_NUM(num) | PIN_##alt | PIN_PULL_##pull))
 
-extern int nmk_config_pin(pin_cfg_t cfg);
+extern int nmk_config_pin(pin_cfg_t cfg, bool sleep);
 extern int nmk_config_pins(pin_cfg_t *cfgs, int num);
+extern int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num);
 
 #endif
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 155fe43a672b..8722a136f3a5 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/err.h>
 
 #include <plat/common.h>
 #include <plat/board.h>
@@ -164,7 +165,7 @@ static int __init omap_init_clocksource_32k(void)
                         return -ENODEV;
 
                 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
-                if (sync_32k_ick)
+                if (!IS_ERR(sync_32k_ick))
                         clk_enable(sync_32k_ick);
 
                 clocksource_32k.mult = clocksource_hz2mult(32768,
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index e2c8eebe6b3a..74dac419d328 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -166,7 +166,7 @@ static void __init omap_detect_sram(void)
                      cpu_is_omap1710())
                         omap_sram_size = 0x4000;        /* 16K */
                 else if (cpu_is_omap1611())
-                        omap_sram_size = 0x3e800;       /* 250K */
+                        omap_sram_size = SZ_256K;
                 else {
                         printk(KERN_ERR "Could not detect SRAM size\n");
                         omap_sram_size = 0x4000;
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 4aacdd12c9cc..3aca5ba0f876 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -6,6 +6,7 @@ obj-y	:= dma.o
 
 obj-$(CONFIG_GENERIC_GPIO)      += gpio.o
 obj-$(CONFIG_PXA3xx)            += mfp.o
+obj-$(CONFIG_PXA95x)            += mfp.o
 obj-$(CONFIG_ARCH_MMP)          += mfp.o
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h
index 9e604c80618f..75f656471240 100644
--- a/arch/arm/plat-pxa/include/plat/mfp.h
+++ b/arch/arm/plat-pxa/include/plat/mfp.h
@@ -423,7 +423,7 @@ typedef unsigned long mfp_cfg_t;
         ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\
          (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm))
 
-#if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP)
+#if defined(CONFIG_PXA3xx) || defined(CONFIG_PXA95x) || defined(CONFIG_ARCH_MMP)
 /*
  * each MFP pin will have a MFPR register, since the offset of the
  * register varies between processors, the processor specific code
@@ -470,6 +470,6 @@ void mfp_write(int mfp, unsigned long mfpr_val);
 void mfp_config(unsigned long *mfp_cfgs, int num);
 void mfp_config_run(void);
 void mfp_config_lpm(void);
-#endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */
+#endif /* CONFIG_PXA3xx || CONFIG_PXA95x || CONFIG_ARCH_MMP */
 
 #endif /* __ASM_PLAT_MFP_H */
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 76d0858c3cbb..4a10c0f684b2 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -88,7 +88,7 @@ static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = 0x32440000,
                 .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2440_map_io,
                 .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2440_init,
@@ -97,7 +97,7 @@ static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = 0x32440001,
                 .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2440_map_io,
                 .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2440_init,
@@ -106,7 +106,7 @@ static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = 0x32440aaa,
                 .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2442_map_io,
                 .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2442_init,
@@ -115,7 +115,7 @@ static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = 0x32440aab,
                 .idmask         = 0xffffffff,
-                .map_io         = s3c244x_map_io,
+                .map_io         = s3c2442_map_io,
                 .init_clocks    = s3c244x_init_clocks,
                 .init_uarts     = s3c244x_init_uarts,
                 .init           = s3c2442_init,
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
index 24c6f5a30596..243b6411050d 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -82,8 +82,6 @@ static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
 struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
         .set_config     = s3c_gpio_setcfg_s3c24xx,
         .get_config     = s3c_gpio_getcfg_s3c24xx,
-        .set_pull       = s3c_gpio_setpull_1up,
-        .get_pull       = s3c_gpio_getpull_1up,
 };
 
 struct s3c_gpio_chip s3c24xx_gpios[] = {
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
index 307248d1ccbb..89e8d0a25f87 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c244x.h
@@ -21,17 +21,22 @@ extern void s3c244x_init_clocks(int xtal);
 #else
 #define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
-#define s3c244x_map_io NULL
 #endif
 
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
+
+extern void s3c2440_map_io(void);
 #else
 #define s3c2440_init NULL
+#define s3c2440_map_io NULL
 #endif
 
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
+
+extern void s3c2442_map_io(void);
 #else
 #define s3c2442_init NULL
+#define s3c2442_map_io NULL
 #endif
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index b732b773b9af..0aa32f242ee4 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -280,18 +280,17 @@ s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip,
 }
 #endif
 
-#ifdef CONFIG_S3C_GPIO_PULL_UP
-int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
-                         unsigned int off, s3c_gpio_pull_t pull)
+#if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN)
+static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull,
+                         s3c_gpio_pull_t updown)
 {
         void __iomem *reg = chip->base + 0x08;
         u32 pup = __raw_readl(reg);
 
-        pup = __raw_readl(reg);
-
-        if (pup == S3C_GPIO_PULL_UP)
+        if (pull == updown)
                 pup &= ~(1 << off);
-        else if (pup == S3C_GPIO_PULL_NONE)
+        else if (pull == S3C_GPIO_PULL_NONE)
                 pup |= (1 << off);
         else
                 return -EINVAL;
@@ -300,17 +299,45 @@ int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
         return 0;
 }
 
-s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
-                                     unsigned int off)
+static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip,
+                                     unsigned int off, s3c_gpio_pull_t updown)
 {
         void __iomem *reg = chip->base + 0x08;
         u32 pup = __raw_readl(reg);
 
         pup &= (1 << off);
-        return pup ? S3C_GPIO_PULL_NONE : S3C_GPIO_PULL_UP;
+        return pup ? S3C_GPIO_PULL_NONE : updown;
+}
+#endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */
+
+#ifdef CONFIG_S3C_GPIO_PULL_UP
+s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
+}
+
+int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
 }
 #endif /* CONFIG_S3C_GPIO_PULL_UP */
 
+#ifdef CONFIG_S3C_GPIO_PULL_DOWN
+s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
+                                     unsigned int off)
+{
+        return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
+}
+
+int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip,
+                         unsigned int off, s3c_gpio_pull_t pull)
+{
+        return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
+}
+#endif /* CONFIG_S3C_GPIO_PULL_DOWN */
+
 #ifdef CONFIG_S5P_GPIO_DRVSTR
 s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
 {
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 8fd65d8b5863..0d2c5703f1ee 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -210,6 +210,17 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip,
                                             unsigned int off);
 
 /**
+ * s3c_gpio_getpull_1down() - Get configuration for choice of down or none
+ * @chip: The gpio chip that the GPIO pin belongs to
+ * @off: The offset to the pin to get the configuration of.
+ *
+ * This helper function reads the state of the pull-down resistor for the
+ * given GPIO in the same case as s3c_gpio_setpull_1down.
+*/
+extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip,
+                                            unsigned int off);
+
+/**
  * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443.
  * @chip: The gpio chip that is being configured.
  * @off: The offset for the GPIO being configured.
diff --git a/arch/arm/plat-versatile/sched-clock.c b/arch/arm/plat-versatile/sched-clock.c
index 9768cf7e83d7..9696ddc238c9 100644
--- a/arch/arm/plat-versatile/sched-clock.c
+++ b/arch/arm/plat-versatile/sched-clock.c
@@ -20,6 +20,7 @@
  */
 #include <linux/cnt32_to_63.h>
 #include <linux/io.h>
+#include <linux/sched.h>
 #include <asm/div64.h>
 
 #include <mach/hardware.h>
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 55590a4d87c9..2fea897ebeb1 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Thu Sep 9 22:43:01 2010
+# Last update: Sun Dec 12 23:24:27 2010
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -2321,7 +2321,7 @@ mx31txtr		MACH_MX31TXTR		MX31TXTR		2332
 u380                    MACH_U380               U380                    2333
 oamp3_hualu             MACH_HUALU_BOARD        HUALU_BOARD             2334
 npcmx50                 MACH_NPCMX50            NPCMX50                 2335
-mx51_lange51            MACH_MX51_LANGE51       MX51_LANGE51            2336
+mx51_efikamx            MACH_MX51_EFIKAMX       MX51_EFIKAMX            2336
 mx51_lange52            MACH_MX51_LANGE52       MX51_LANGE52            2337
 riom                    MACH_RIOM               RIOM                    2338
 comcas                  MACH_COMCAS             COMCAS                  2339
@@ -2355,7 +2355,7 @@ at91sam9263cs		MACH_AT91SAM9263CS	AT91SAM9263CS		2366
 csb732                  MACH_CSB732             CSB732                  2367
 u8500                   MACH_U8500              U8500                   2368
 huqiu                   MACH_HUQIU              HUQIU                   2369
-mx51_kunlun             MACH_MX51_KUNLUN        MX51_KUNLUN             2370
+mx51_efikasb            MACH_MX51_EFIKASB       MX51_EFIKASB            2370
 pmt1g                   MACH_PMT1G              PMT1G                   2371
 htcelf                  MACH_HTCELF             HTCELF                  2372
 armadillo420            MACH_ARMADILLO420       ARMADILLO420            2373
@@ -2971,7 +2971,7 @@ premierwave_en		MACH_PREMIERWAVE_EN	PREMIERWAVE_EN		2985
 wasabi                  MACH_WASABI             WASABI                  2986
 vivow                   MACH_VIVOW              VIVOW                   2987
 mx50_rdp                MACH_MX50_RDP           MX50_RDP                2988
-universal               MACH_UNIVERSAL          UNIVERSAL               2989
+universal_c210          MACH_UNIVERSAL_C210     UNIVERSAL_C210          2989
 real6410                MACH_REAL6410           REAL6410                2990
 spx_sakura              MACH_SPX_SAKURA         SPX_SAKURA              2991
 ij3k_2440               MACH_IJ3K_2440          IJ3K_2440               2992
@@ -3044,3 +3044,178 @@ harvest_desoto		MACH_HARVEST_DESOTO	HARVEST_DESOTO		3059
 msm8x60_qrdc            MACH_MSM8X60_QRDC       MSM8X60_QRDC            3060
 spear900                MACH_SPEAR900           SPEAR900                3061
 pcontrol_g20            MACH_PCONTROL_G20       PCONTROL_G20            3062
+rdstor                  MACH_RDSTOR             RDSTOR                  3063
+usdloader               MACH_USDLOADER          USDLOADER               3064
+tsoploader              MACH_TSOPLOADER         TSOPLOADER              3065
+kronos                  MACH_KRONOS             KRONOS                  3066
+ffcore                  MACH_FFCORE             FFCORE                  3067
+mone                    MACH_MONE               MONE                    3068
+unit2s                  MACH_UNIT2S             UNIT2S                  3069
+acer_a5                 MACH_ACER_A5            ACER_A5                 3070
+etherpro_isp            MACH_ETHERPRO_ISP       ETHERPRO_ISP            3071
+stretchs7000            MACH_STRETCHS7000       STRETCHS7000            3072
+p87_smartsim            MACH_P87_SMARTSIM       P87_SMARTSIM            3073
+tulip                   MACH_TULIP              TULIP                   3074
+sunflower               MACH_SUNFLOWER          SUNFLOWER               3075
+rib                     MACH_RIB                RIB                     3076
+clod                    MACH_CLOD               CLOD                    3077
+rump                    MACH_RUMP               RUMP                    3078
+tenderloin              MACH_TENDERLOIN         TENDERLOIN              3079
+shortloin               MACH_SHORTLOIN          SHORTLOIN               3080
+crespo                  MACH_CRESPO             CRESPO                  3081
+antares                 MACH_ANTARES            ANTARES                 3082
+wb40n                   MACH_WB40N              WB40N                   3083
+herring                 MACH_HERRING            HERRING                 3084
+naxy400                 MACH_NAXY400            NAXY400                 3085
+naxy1200                MACH_NAXY1200           NAXY1200                3086
+vpr200                  MACH_VPR200             VPR200                  3087
+bug20                   MACH_BUG20              BUG20                   3088
+goflexnet               MACH_GOFLEXNET          GOFLEXNET               3089
+torbreck                MACH_TORBRECK           TORBRECK                3090
+saarb_mg1               MACH_SAARB_MG1          SAARB_MG1               3091
+callisto                MACH_CALLISTO           CALLISTO                3092
+multhsu                 MACH_MULTHSU            MULTHSU                 3093
+saluda                  MACH_SALUDA             SALUDA                  3094
+pemp_omap3_apollo       MACH_PEMP_OMAP3_APOLLO  PEMP_OMAP3_APOLLO       3095
+vc0718                  MACH_VC0718             VC0718                  3096
+mvblx                   MACH_MVBLX              MVBLX                   3097
+inhand_apeiron          MACH_INHAND_APEIRON     INHAND_APEIRON          3098
+inhand_fury             MACH_INHAND_FURY        INHAND_FURY             3099
+inhand_siren            MACH_INHAND_SIREN       INHAND_SIREN            3100
+hdnvp                   MACH_HDNVP              HDNVP                   3101
+softwinner              MACH_SOFTWINNER         SOFTWINNER              3102
+prima2_evb              MACH_PRIMA2_EVB         PRIMA2_EVB              3103
+nas6210                 MACH_NAS6210            NAS6210                 3104
+unisdev                 MACH_UNISDEV            UNISDEV                 3105
+sbca11                  MACH_SBCA11             SBCA11                  3106
+saga                    MACH_SAGA               SAGA                    3107
+ns_k330                 MACH_NS_K330            NS_K330                 3108
+tanna                   MACH_TANNA              TANNA                   3109
+imate8502               MACH_IMATE8502          IMATE8502               3110
+aspen                   MACH_ASPEN              ASPEN                   3111
+daintree_cwac           MACH_DAINTREE_CWAC      DAINTREE_CWAC           3112
+zmx25                   MACH_ZMX25              ZMX25                   3113
+maple1                  MACH_MAPLE1             MAPLE1                  3114
+qsd8x72_surf            MACH_QSD8X72_SURF       QSD8X72_SURF            3115
+qsd8x72_ffa             MACH_QSD8X72_FFA        QSD8X72_FFA             3116
+abilene                 MACH_ABILENE            ABILENE                 3117
+eigen_ttr               MACH_EIGEN_TTR          EIGEN_TTR               3118
+iomega_ix2_200          MACH_IOMEGA_IX2_200     IOMEGA_IX2_200          3119
+coretec_vcx7400         MACH_CORETEC_VCX7400    CORETEC_VCX7400         3120
+santiago                MACH_SANTIAGO           SANTIAGO                3121
+mx257sol                MACH_MX257SOL           MX257SOL                3122
+strasbourg              MACH_STRASBOURG         STRASBOURG              3123
+msm8x60_fluid           MACH_MSM8X60_FLUID      MSM8X60_FLUID           3124
+smartqv5                MACH_SMARTQV5           SMARTQV5                3125
+smartqv3                MACH_SMARTQV3           SMARTQV3                3126
+smartqv7                MACH_SMARTQV7           SMARTQV7                3127
+paz00                   MACH_PAZ00              PAZ00                   3128
+acmenetusfoxg20         MACH_ACMENETUSFOXG20    ACMENETUSFOXG20         3129
+htcwillow               MACH_HTCWILLOW          HTCWILLOW               3130
+fwbd_0404               MACH_FWBD_0404          FWBD_0404               3131
+hdgu                    MACH_HDGU               HDGU                    3132
+pyramid                 MACH_PYRAMID            PYRAMID                 3133
+epiphan                 MACH_EPIPHAN            EPIPHAN                 3134
+omap_bender             MACH_OMAP_BENDER        OMAP_BENDER             3135
+gurnard                 MACH_GURNARD            GURNARD                 3136
+gtl_it5100              MACH_GTL_IT5100         GTL_IT5100              3137
+bcm2708                 MACH_BCM2708            BCM2708                 3138
+mx51_ggc                MACH_MX51_GGC           MX51_GGC                3139
+sharespace              MACH_SHARESPACE         SHARESPACE              3140
+haba_knx_explorer       MACH_HABA_KNX_EXPLORER  HABA_KNX_EXPLORER       3141
+simtec_kirkmod          MACH_SIMTEC_KIRKMOD     SIMTEC_KIRKMOD          3142
+crux                    MACH_CRUX               CRUX                    3143
+mx51_bravo              MACH_MX51_BRAVO         MX51_BRAVO              3144
+charon                  MACH_CHARON             CHARON                  3145
+picocom3                MACH_PICOCOM3           PICOCOM3                3146
+picocom4                MACH_PICOCOM4           PICOCOM4                3147
+serrano                 MACH_SERRANO            SERRANO                 3148
+doubleshot              MACH_DOUBLESHOT         DOUBLESHOT              3149
+evsy                    MACH_EVSY               EVSY                    3150
+huashan                 MACH_HUASHAN            HUASHAN                 3151
+lausanne                MACH_LAUSANNE           LAUSANNE                3152
+emerald                 MACH_EMERALD            EMERALD                 3153
+tqma35                  MACH_TQMA35             TQMA35                  3154
+marvel                  MACH_MARVEL             MARVEL                  3155
+manuae                  MACH_MANUAE             MANUAE                  3156
+chacha                  MACH_CHACHA             CHACHA                  3157
+lemon                   MACH_LEMON              LEMON                   3158
+csc                     MACH_CSC                CSC                     3159
+gira_knxip_router       MACH_GIRA_KNXIP_ROUTER  GIRA_KNXIP_ROUTER       3160
+t20                     MACH_T20                T20                     3161
+hdmini                  MACH_HDMINI             HDMINI                  3162
+sciphone_g2             MACH_SCIPHONE_G2        SCIPHONE_G2             3163
+express                 MACH_EXPRESS            EXPRESS                 3164
+express_kt              MACH_EXPRESS_KT         EXPRESS_KT              3165
+maximasp                MACH_MAXIMASP           MAXIMASP                3166
+nitrogen_imx51          MACH_NITROGEN_IMX51     NITROGEN_IMX51          3167
+nitrogen_imx53          MACH_NITROGEN_IMX53     NITROGEN_IMX53          3168
+sunfire                 MACH_SUNFIRE            SUNFIRE                 3169
+arowana                 MACH_AROWANA            AROWANA                 3170
+tegra_daytona           MACH_TEGRA_DAYTONA      TEGRA_DAYTONA           3171
+tegra_swordfish         MACH_TEGRA_SWORDFISH    TEGRA_SWORDFISH         3172
+edison                  MACH_EDISON             EDISON                  3173
+svp8500v1               MACH_SVP8500V1          SVP8500V1               3174
+svp8500v2               MACH_SVP8500V2          SVP8500V2               3175
+svp5500                 MACH_SVP5500            SVP5500                 3176
+b5500                   MACH_B5500              B5500                   3177
+s5500                   MACH_S5500              S5500                   3178
+icon                    MACH_ICON               ICON                    3179
+elephant                MACH_ELEPHANT           ELEPHANT                3180
+msm8x60_fusion          MACH_MSM8X60_FUSION     MSM8X60_FUSION          3181
+shooter                 MACH_SHOOTER            SHOOTER                 3182
+spade_lte               MACH_SPADE_LTE          SPADE_LTE               3183
+philhwani               MACH_PHILHWANI          PHILHWANI               3184
+gsncomm                 MACH_GSNCOMM            GSNCOMM                 3185
+strasbourg_a2           MACH_STRASBOURG_A2      STRASBOURG_A2           3186
+mmm                     MACH_MMM                MMM                     3187
+davinci_dm365_bv        MACH_DAVINCI_DM365_BV   DAVINCI_DM365_BV        3188
+ag5evm                  MACH_AG5EVM             AG5EVM                  3189
+sc575plc                MACH_SC575PLC           SC575PLC                3190
+sc575hmi                MACH_SC575IPC           SC575IPC                3191
+omap3_tdm3730           MACH_OMAP3_TDM3730      OMAP3_TDM3730           3192
+g7                      MACH_G7                 G7                      3193
+top9000_eval            MACH_TOP9000_EVAL       TOP9000_EVAL            3194
+top9000_su              MACH_TOP9000_SU         TOP9000_SU              3195
+utm300                  MACH_UTM300             UTM300                  3196
+tsunagi                 MACH_TSUNAGI            TSUNAGI                 3197
+ts75xx                  MACH_TS75XX             TS75XX                  3198
+msm8x60_fusn_ffa        MACH_MSM8X60_FUSN_FFA   MSM8X60_FUSN_FFA        3199
+ts47xx                  MACH_TS47XX             TS47XX                  3200
+da850_k5                MACH_DA850_K5           DA850_K5                3201
+ax502                   MACH_AX502              AX502                   3202
+igep0032                MACH_IGEP0032           IGEP0032                3203
+antero                  MACH_ANTERO             ANTERO                  3204
+synergy                 MACH_SYNERGY            SYNERGY                 3205
+ics_if_voip             MACH_ICS_IF_VOIP        ICS_IF_VOIP             3206
+wlf_cragg_6410          MACH_WLF_CRAGG_6410     WLF_CRAGG_6410          3207
+punica                  MACH_PUNICA             PUNICA                  3208
+sbc_nt250               MACH_SBC_NT250          SBC_NT250               3209
+mx27_wmultra            MACH_MX27_WMULTRA       MX27_WMULTRA            3210
+mackerel                MACH_MACKEREL           MACKEREL                3211
+fa9x27                  MACH_FA9X27             FA9X27                  3213
+ns2816tb                MACH_NS2816TB           NS2816TB                3214
+ns2816_ntpad            MACH_NS2816_NTPAD       NS2816_NTPAD            3215
+ns2816_ntnb             MACH_NS2816_NTNB        NS2816_NTNB             3216
+kaen                    MACH_KAEN               KAEN                    3217
+nv1000                  MACH_NV1000             NV1000                  3218
+nuc950ts                MACH_NUC950TS           NUC950TS                3219
+nokia_rm680             MACH_NOKIA_RM680        NOKIA_RM680             3220
+ast2200                 MACH_AST2200            AST2200                 3221
+lead                    MACH_LEAD               LEAD                    3222
+unino1                  MACH_UNINO1             UNINO1                  3223
+greeco                  MACH_GREECO             GREECO                  3224
+verdi                   MACH_VERDI              VERDI                   3225
+dm6446_adbox            MACH_DM6446_ADBOX       DM6446_ADBOX            3226
+quad_salsa              MACH_QUAD_SALSA         QUAD_SALSA              3227
+abb_gma_1_1             MACH_ABB_GMA_1_1        ABB_GMA_1_1             3228
+svcid                   MACH_SVCID              SVCID                   3229
+msm8960_sim             MACH_MSM8960_SIM        MSM8960_SIM             3230
+msm8960_rumi3           MACH_MSM8960_RUMI3      MSM8960_RUMI3           3231
+icon_g                  MACH_ICON_G             ICON_G                  3232
+mb3                     MACH_MB3                MB3                     3233
+gsia18s                 MACH_GSIA18S            GSIA18S                 3234
+pivicc                  MACH_PIVICC             PIVICC                  3235
+pcm048                  MACH_PCM048             PCM048                  3236
+dds                     MACH_DDS                DDS                     3237
+chalten_xa1             MACH_CHALTEN_XA1        CHALTEN_XA1             3238
diff --git a/arch/mn10300/kernel/gdb-io-serial.c b/arch/mn10300/kernel/gdb-io-serial.c
index 0d5d63c91dc3..f28dc99c6f72 100644
--- a/arch/mn10300/kernel/gdb-io-serial.c
+++ b/arch/mn10300/kernel/gdb-io-serial.c
@@ -73,7 +73,8 @@ void gdbstub_io_init(void)
         GDBPORT_SERIAL_IER = UART_IER_RDI | UART_IER_RLSI;
 
         /* permit level 0 IRQs to take place */
-        local_change_intr_mask_level(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
+        arch_local_change_intr_mask_level(
+                NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
 }
 
 /*
diff --git a/arch/mn10300/kernel/gdb-io-ttysm.c b/arch/mn10300/kernel/gdb-io-ttysm.c
index 97dfda23342c..abdeea153c89 100644
--- a/arch/mn10300/kernel/gdb-io-ttysm.c
+++ b/arch/mn10300/kernel/gdb-io-ttysm.c
@@ -87,7 +87,8 @@ void __init gdbstub_io_init(void)
         tmp = *gdbstub_port->_control;
 
         /* permit level 0 IRQs only */
-        local_change_intr_mask_level(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
+        arch_local_change_intr_mask_level(
+                NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
 }
 
 /*
diff --git a/arch/mn10300/kernel/gdb-stub.c b/arch/mn10300/kernel/gdb-stub.c
index a5fc3f05309b..b169d99d9f20 100644
--- a/arch/mn10300/kernel/gdb-stub.c
+++ b/arch/mn10300/kernel/gdb-stub.c
@@ -1194,7 +1194,8 @@ static int gdbstub(struct pt_regs *regs, enum exception_code excep)
 
         asm volatile("mov mdr,%0" : "=d"(mdr));
         local_save_flags(epsw);
-        local_change_intr_mask_level(NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
+        arch_local_change_intr_mask_level(
+                NUM2EPSW_IM(CONFIG_GDBSTUB_IRQ_LEVEL + 1));
 
         gdbstub_store_fpu();
 
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 7f217b3a50a8..2e9d78d21fd3 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -22,7 +22,8 @@ config SUPERH
         select HAVE_SPARSE_IRQ
         select RTC_LIB
         select GENERIC_ATOMIC64
-        select GENERIC_HARDIRQS_NO_DEPRECATED
+        # Support the deprecated APIs until MFD and GPIOLIB catch up.
+        select GENERIC_HARDIRQS_NO_DEPRECATED if !MFD_SUPPORT && !GPIOLIB
         help
           The SuperH is a RISC processor targeted for use in embedded systems
           and consumer electronics; it was also used in the Sega Dreamcast
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 903cd618eb74..d6741fca89a4 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -368,8 +368,9 @@
 #define __NR_sendmsg            355
 #define __NR_recvmsg            356
 #define __NR_recvmmsg           357
+#define __NR_accept4            358
 
-#define NR_syscalls 358
+#define NR_syscalls 359
 
 #ifdef __KERNEL__
 
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index e872e81add8a..6fc347ebe59d 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -375,3 +375,4 @@ ENTRY(sys_call_table)
         .long sys_sendmsg               /* 355 */
         .long sys_recvmsg
         .long sys_recvmmsg
+        .long sys_accept4
diff --git a/arch/sparc/include/asm/openprom.h b/arch/sparc/include/asm/openprom.h
index 81cd43432dc0..47eaafad15ce 100644
--- a/arch/sparc/include/asm/openprom.h
+++ b/arch/sparc/include/asm/openprom.h
@@ -39,7 +39,7 @@ struct linux_dev_v2_funcs {
         int (*v2_dev_open)(char *devpath);
         void (*v2_dev_close)(int d);
         int (*v2_dev_read)(int d, char *buf, int nbytes);
-        int (*v2_dev_write)(int d, char *buf, int nbytes);
+        int (*v2_dev_write)(int d, const char *buf, int nbytes);
         int (*v2_dev_seek)(int d, int hi, int lo);
 
         /* Never issued (multistage load support) */
diff --git a/arch/sparc/include/asm/oplib_32.h b/arch/sparc/include/asm/oplib_32.h
index 51296a6f5005..9e5c64084b86 100644
--- a/arch/sparc/include/asm/oplib_32.h
+++ b/arch/sparc/include/asm/oplib_32.h
@@ -60,25 +60,6 @@ extern char *prom_getbootargs(void);
 extern char *prom_mapio(char *virt_hint, int io_space, unsigned int phys_addr, unsigned int num_bytes);
 extern void prom_unmapio(char *virt_addr, unsigned int num_bytes);
 
-/* Device operations. */
-
-/* Open the device described by the passed string.  Note, that the format
- * of the string is different on V0 vs. V2->higher proms.  The caller must
- * know what he/she is doing!  Returns the device descriptor, an int.
- */
-extern int prom_devopen(char *device_string);
-
-/* Close a previously opened device described by the passed integer
- * descriptor.
- */
-extern int prom_devclose(int device_handle);
-
-/* Do a seek operation on the device described by the passed integer
- * descriptor.
- */
-extern void prom_seek(int device_handle, unsigned int seek_hival,
-                      unsigned int seek_lowval);
-
 /* Miscellaneous routines, don't really fit in any category per se. */
 
 /* Reboot the machine with the command line passed. */
@@ -121,19 +102,8 @@ extern int prom_getrev(void);
 /* Get the prom firmware revision. */
 extern int prom_getprev(void);
 
-/* Character operations to/from the console.... */
-
-/* Non-blocking get character from console. */
-extern int prom_nbgetchar(void);
-
-/* Non-blocking put character to console. */
-extern int prom_nbputchar(char character);
-
-/* Blocking get character from console. */
-extern char prom_getchar(void);
-
-/* Blocking put character to console. */
-extern void prom_putchar(char character);
+/* Write a buffer of characters to the console. */
+extern void prom_console_write_buf(const char *buf, int len);
 
 /* Prom's internal routines, don't use in kernel/boot code. */
 extern void prom_printf(const char *fmt, ...);
@@ -238,7 +208,6 @@ extern int prom_node_has_property(phandle node, char *property);
 extern int prom_setprop(phandle node, const char *prop_name, char *prop_value,
                         int value_size);
 
-extern phandle prom_pathtoinode(char *path);
 extern phandle prom_inst2pkg(int);
 
 /* Dorking with Bus ranges... */
diff --git a/arch/sparc/include/asm/oplib_64.h b/arch/sparc/include/asm/oplib_64.h
index c9cc078e3e31..8cd0df34e82b 100644
--- a/arch/sparc/include/asm/oplib_64.h
+++ b/arch/sparc/include/asm/oplib_64.h
@@ -67,27 +67,6 @@ extern void prom_init(void *cif_handler, void *cif_stack);
 /* Boot argument acquisition, returns the boot command line string. */
 extern char *prom_getbootargs(void);
 
-/* Device utilities. */
-
-/* Device operations. */
-
-/* Open the device described by the passed string.  Note, that the format
- * of the string is different on V0 vs. V2->higher proms.  The caller must
- * know what he/she is doing!  Returns the device descriptor, an int.
- */
-extern int prom_devopen(const char *device_string);
-
-/* Close a previously opened device described by the passed integer
- * descriptor.
- */
-extern int prom_devclose(int device_handle);
-
-/* Do a seek operation on the device described by the passed integer
- * descriptor.
- */
-extern void prom_seek(int device_handle, unsigned int seek_hival,
-                      unsigned int seek_lowval);
-
 /* Miscellaneous routines, don't really fit in any category per se. */
 
 /* Reboot the machine with the command line passed. */
@@ -109,33 +88,14 @@ extern void prom_halt(void) __attribute__ ((noreturn));
 /* Halt and power-off the machine. */
 extern void prom_halt_power_off(void) __attribute__ ((noreturn));
 
-/* Set the PROM 'sync' callback function to the passed function pointer.
- * When the user gives the 'sync' command at the prom prompt while the
- * kernel is still active, the prom will call this routine.
- *
- */
-typedef int (*callback_func_t)(long *cmd);
-extern void prom_setcallback(callback_func_t func_ptr);
-
 /* Acquire the IDPROM of the root node in the prom device tree.  This
  * gets passed a buffer where you would like it stuffed.  The return value
  * is the format type of this idprom or 0xff on error.
  */
 extern unsigned char prom_get_idprom(char *idp_buffer, int idpbuf_size);
 
-/* Character operations to/from the console.... */
-
-/* Non-blocking get character from console. */
-extern int prom_nbgetchar(void);
-
-/* Non-blocking put character to console. */
-extern int prom_nbputchar(char character);
-
-/* Blocking get character from console. */
-extern char prom_getchar(void);
-
-/* Blocking put character to console. */
-extern void prom_putchar(char character);
+/* Write a buffer of characters to the console. */
+extern void prom_console_write_buf(const char *buf, int len);
 
 /* Prom's internal routines, don't use in kernel/boot code. */
 extern void prom_printf(const char *fmt, ...);
@@ -279,9 +239,7 @@ extern phandle prom_finddevice(const char *name);
 extern int prom_setprop(phandle node, const char *prop_name, char *prop_value,
                         int value_size);
 
-extern phandle prom_pathtoinode(const char *path);
 extern phandle prom_inst2pkg(int);
-extern int prom_service_exists(const char *service_name);
 extern void prom_sun4v_guest_soft_state(void);
 
 extern int prom_ihandle2path(int handle, char *buffer, int bufsize);
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
index 2d51527d810f..f01c42661ee5 100644
--- a/arch/sparc/kernel/leon_kernel.c
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -114,7 +114,7 @@ void __init leon_init_timers(irq_handler_t counter_fn)
         if (leon3_gptimer_regs && leon3_irqctrl_regs) {
                 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].val, 0);
                 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].rld,
-                                      (((1000000 / 100) - 1)));
+                                      (((1000000 / HZ) - 1)));
                 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].ctrl, 0);
 
 #ifdef CONFIG_SMP
@@ -128,7 +128,7 @@ void __init leon_init_timers(irq_handler_t counter_fn)
                 }
 
                 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].val, 0);
-                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].rld, (((1000000/100) - 1)));
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].rld, (((1000000/HZ) - 1)));
                 LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[1].ctrl, 0);
 # endif
 
diff --git a/arch/sparc/prom/Makefile b/arch/sparc/prom/Makefile
index 1b8c073adb44..816c0fa12dc0 100644
--- a/arch/sparc/prom/Makefile
+++ b/arch/sparc/prom/Makefile
@@ -6,7 +6,6 @@ ccflags := -Werror
 
 lib-y                 := bootstr_$(BITS).o
 lib-$(CONFIG_SPARC32) += devmap.o
-lib-y                 += devops_$(BITS).o
 lib-y                 += init_$(BITS).o
 lib-$(CONFIG_SPARC32) += memory.o
 lib-y                 += misc_$(BITS).o
diff --git a/arch/sparc/prom/console_32.c b/arch/sparc/prom/console_32.c
index 5340264b78f5..48863108a44c 100644
--- a/arch/sparc/prom/console_32.c
+++ b/arch/sparc/prom/console_32.c
@@ -16,63 +16,26 @@
 
 extern void restore_current(void);
 
-/* Non blocking get character from console input device, returns -1
- * if no input was taken.  This can be used for polling.
- */
-int
-prom_nbgetchar(void)
-{
-        static char inc;
-        int i = -1;
-        unsigned long flags;
-
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-                i = (*(romvec->pv_nbgetchar))();
-                break;
-        case PROM_V2:
-        case PROM_V3:
-                if( (*(romvec->pv_v2devops).v2_dev_read)(*romvec->pv_v2bootargs.fd_stdin , &inc, 0x1) == 1) {
-                        i = inc;
-                } else {
-                        i = -1;
-                }
-                break;
-        default:
-                i = -1;
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-        return i; /* Ugh, we could spin forever on unsupported proms ;( */
-}
-
 /* Non blocking put character to console device, returns -1 if
  * unsuccessful.
  */
-int
-prom_nbputchar(char c)
+static int prom_nbputchar(const char *buf)
 {
-        static char outc;
         unsigned long flags;
         int i = -1;
 
         spin_lock_irqsave(&prom_lock, flags);
         switch(prom_vers) {
         case PROM_V0:
-                i = (*(romvec->pv_nbputchar))(c);
+                i = (*(romvec->pv_nbputchar))(*buf);
                 break;
         case PROM_V2:
         case PROM_V3:
-                outc = c;
-                if( (*(romvec->pv_v2devops).v2_dev_write)(*romvec->pv_v2bootargs.fd_stdout, &outc, 0x1) == 1)
+                if ((*(romvec->pv_v2devops).v2_dev_write)(*romvec->pv_v2bootargs.fd_stdout,
+                                                          buf, 0x1) == 1)
                         i = 0;
-                else
-                        i = -1;
                 break;
         default:
-                i = -1;
                 break;
         };
         restore_current();
@@ -80,18 +43,14 @@ prom_nbputchar(char c)
         return i; /* Ugh, we could spin forever on unsupported proms ;( */
 }
 
-/* Blocking version of get character routine above. */
-char
-prom_getchar(void)
+void prom_console_write_buf(const char *buf, int len)
 {
-        int character;
-        while((character = prom_nbgetchar()) == -1) ;
-        return (char) character;
+        while (len) {
+                int n = prom_nbputchar(buf);
+                if (n)
+                        continue;
+                len--;
+                buf++;
+        }
 }
 
-/* Blocking version of put character routine above. */
-void
-prom_putchar(char c)
-{
-        while(prom_nbputchar(c) == -1) ;
-}
diff --git a/arch/sparc/prom/console_64.c b/arch/sparc/prom/console_64.c
index 10322dc2f557..ed39e75828bd 100644
--- a/arch/sparc/prom/console_64.c
+++ b/arch/sparc/prom/console_64.c
@@ -15,85 +15,34 @@
 
 extern int prom_stdin, prom_stdout;
 
-/* Non blocking get character from console input device, returns -1
- * if no input was taken.  This can be used for polling.
- */
-inline int
-prom_nbgetchar(void)
-{
-        unsigned long args[7];
-        char inc;
-
-        args[0] = (unsigned long) "read";
-        args[1] = 3;
-        args[2] = 1;
-        args[3] = (unsigned int) prom_stdin;
-        args[4] = (unsigned long) &inc;
-        args[5] = 1;
-        args[6] = (unsigned long) -1;
-
-        p1275_cmd_direct(args);
-
-        if (args[6] == 1)
-                return inc;
-        return -1;
-}
-
-/* Non blocking put character to console device, returns -1 if
- * unsuccessful.
- */
-inline int
-prom_nbputchar(char c)
+static int __prom_console_write_buf(const char *buf, int len)
 {
         unsigned long args[7];
-        char outc;
-        
-        outc = c;
+        int ret;
 
         args[0] = (unsigned long) "write";
         args[1] = 3;
         args[2] = 1;
         args[3] = (unsigned int) prom_stdout;
-        args[4] = (unsigned long) &outc;
-        args[5] = 1;
+        args[4] = (unsigned long) buf;
+        args[5] = (unsigned int) len;
         args[6] = (unsigned long) -1;
 
         p1275_cmd_direct(args);
 
-        if (args[6] == 1)
-                return 0;
-        else
+        ret = (int) args[6];
+        if (ret < 0)
                 return -1;
+        return ret;
 }
 
-/* Blocking version of get character routine above. */
-char
-prom_getchar(void)
-{
-        int character;
-        while((character = prom_nbgetchar()) == -1) ;
-        return (char) character;
-}
-
-/* Blocking version of put character routine above. */
-void
-prom_putchar(char c)
+void prom_console_write_buf(const char *buf, int len)
 {
-        prom_nbputchar(c);
-}
-
-void
-prom_puts(const char *s, int len)
-{
-        unsigned long args[7];
-
-        args[0] = (unsigned long) "write";
-        args[1] = 3;
-        args[2] = 1;
-        args[3] = (unsigned int) prom_stdout;
-        args[4] = (unsigned long) s;
-        args[5] = len;
-        args[6] = (unsigned long) -1;
-
-        p1275_cmd_direct(args);
+        while (len) {
+                int n = __prom_console_write_buf(buf, len);
+                if (n < 0)
+                        continue;
+                len -= n;
+                buf += len;
+        }
 }
diff --git a/arch/sparc/prom/devops_32.c b/arch/sparc/prom/devops_32.c
deleted file mode 100644
index 9c5d4687242a..000000000000
--- a/arch/sparc/prom/devops_32.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * devops.c:  Device operations using the PROM.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-
-extern void restore_current(void);
-
-/* Open the device described by the string 'dstr'.  Returns the handle
- * to that device used for subsequent operations on that device.
- * Returns -1 on failure.
- */
-int
-prom_devopen(char *dstr)
-{
-        int handle;
-        unsigned long flags;
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-                handle = (*(romvec->pv_v0devops.v0_devopen))(dstr);
-                if(handle == 0) handle = -1;
-                break;
-        case PROM_V2:
-        case PROM_V3:
-                handle = (*(romvec->pv_v2devops.v2_dev_open))(dstr);
-                break;
-        default:
-                handle = -1;
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-
-        return handle;
-}
-
-/* Close the device described by device handle 'dhandle'. */
-int
-prom_devclose(int dhandle)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-                (*(romvec->pv_v0devops.v0_devclose))(dhandle);
-                break;
-        case PROM_V2:
-        case PROM_V3:
-                (*(romvec->pv_v2devops.v2_dev_close))(dhandle);
-                break;
-        default:
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-        return 0;
-}
-
-/* Seek to specified location described by 'seekhi' and 'seeklo'
- * for device 'dhandle'.
- */
-void
-prom_seek(int dhandle, unsigned int seekhi, unsigned int seeklo)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&prom_lock, flags);
-        switch(prom_vers) {
-        case PROM_V0:
-                (*(romvec->pv_v0devops.v0_seekdev))(dhandle, seekhi, seeklo);
-                break;
-        case PROM_V2:
-        case PROM_V3:
-                (*(romvec->pv_v2devops.v2_dev_seek))(dhandle, seekhi, seeklo);
-                break;
-        default:
-                break;
-        };
-        restore_current();
-        spin_unlock_irqrestore(&prom_lock, flags);
-}
diff --git a/arch/sparc/prom/devops_64.c b/arch/sparc/prom/devops_64.c
deleted file mode 100644
index a017119e7ef1..000000000000
--- a/arch/sparc/prom/devops_64.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * devops.c:  Device operations using the PROM.
- *
- * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
- * Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/sched.h>
-
-#include <asm/openprom.h>
-#include <asm/oplib.h>
-
-/* Open the device described by the string 'dstr'.  Returns the handle
- * to that device used for subsequent operations on that device.
- * Returns 0 on failure.
- */
-int
-prom_devopen(const char *dstr)
-{
-        unsigned long args[5];
-
-        args[0] = (unsigned long) "open";
-        args[1] = 1;
-        args[2] = 1;
-        args[3] = (unsigned long) dstr;
-        args[4] = (unsigned long) -1;
-
-        p1275_cmd_direct(args);
-
-        return (int) args[4];
-}
-
-/* Close the device described by device handle 'dhandle'. */
-int
-prom_devclose(int dhandle)
-{
-        unsigned long args[4];
-
-        args[0] = (unsigned long) "close";
-        args[1] = 1;
-        args[2] = 0;
-        args[3] = (unsigned int) dhandle;
-
-        p1275_cmd_direct(args);
-
-        return 0;
-}
-
-/* Seek to specified location described by 'seekhi' and 'seeklo'
- * for device 'dhandle'.
- */
-void
-prom_seek(int dhandle, unsigned int seekhi, unsigned int seeklo)
-{
-        unsigned long args[7];
-
-        args[0] = (unsigned long) "seek";
-        args[1] = 3;
-        args[2] = 1;
-        args[3] = (unsigned int) dhandle;
-        args[4] = seekhi;
-        args[5] = seeklo;
-        args[6] = (unsigned long) -1;
-
-        p1275_cmd_direct(args);
-}
diff --git a/arch/sparc/prom/misc_64.c b/arch/sparc/prom/misc_64.c
index d24bc44e361e..e4f31d4d3715 100644
--- a/arch/sparc/prom/misc_64.c
+++ b/arch/sparc/prom/misc_64.c
@@ -18,7 +18,7 @@
 #include <asm/system.h>
 #include <asm/ldc.h>
 
-int prom_service_exists(const char *service_name)
+static int prom_service_exists(const char *service_name)
 {
         unsigned long args[5];
 
@@ -150,20 +150,6 @@ void prom_halt_power_off(void)
         prom_halt();
 }
 
-/* Set prom sync handler to call function 'funcp'. */
-void prom_setcallback(callback_func_t funcp)
-{
-        unsigned long args[5];
-        if (!funcp)
-                return;
-        args[0] = (unsigned long) "set-callback";
-        args[1] = 1;
-        args[2] = 1;
-        args[3] = (unsigned long) funcp;
-        args[4] = (unsigned long) -1;
-        p1275_cmd_direct(args);
-}
-
 /* Get the idprom and stuff it into buffer 'idbuf'.  Returns the
  * format type.  'num_bytes' is the number of bytes that your idbuf
  * has space for.  Returns 0xff on error.
diff --git a/arch/sparc/prom/printf.c b/arch/sparc/prom/printf.c
index ca869266b9f3..d9682f06b3b0 100644
--- a/arch/sparc/prom/printf.c
+++ b/arch/sparc/prom/printf.c
@@ -15,22 +15,45 @@
 
 #include <linux/kernel.h>
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 
 #include <asm/openprom.h>
 #include <asm/oplib.h>
 
+#define CONSOLE_WRITE_BUF_SIZE  1024
+
 static char ppbuf[1024];
+static char console_write_buf[CONSOLE_WRITE_BUF_SIZE];
+static DEFINE_RAW_SPINLOCK(console_write_lock);
 
 void notrace prom_write(const char *buf, unsigned int n)
 {
-        char ch;
+        unsigned int dest_len;
+        unsigned long flags;
+        char *dest;
+
+        dest = console_write_buf;
+        raw_spin_lock_irqsave(&console_write_lock, flags);
 
-        while (n != 0) {
-                --n;
-                if ((ch = *buf++) == '\n')
-                        prom_putchar('\r');
-                prom_putchar(ch);
+        dest_len = 0;
+        while (n-- != 0) {
+                char ch = *buf++;
+                if (ch == '\n') {
+                        *dest++ = '\r';
+                        dest_len++;
+                }
+                *dest++ = ch;
+                dest_len++;
+                if (dest_len >= CONSOLE_WRITE_BUF_SIZE - 1) {
+                        prom_console_write_buf(console_write_buf, dest_len);
+                        dest = console_write_buf;
+                        dest_len = 0;
+                }
         }
+        if (dest_len)
+                prom_console_write_buf(console_write_buf, dest_len);
+
+        raw_spin_unlock_irqrestore(&console_write_lock, flags);
 }
 
 void notrace prom_printf(const char *fmt, ...)
diff --git a/arch/sparc/prom/tree_32.c b/arch/sparc/prom/tree_32.c
index 63e08e149774..535e2e69ac1d 100644
--- a/arch/sparc/prom/tree_32.c
+++ b/arch/sparc/prom/tree_32.c
@@ -342,19 +342,3 @@ phandle prom_inst2pkg(int inst)
         if (node == -1) return 0;
         return node;
 }
-
-/* Return 'node' assigned to a particular prom 'path'
- * FIXME: Should work for v0 as well
- */
-phandle prom_pathtoinode(char *path)
-{
-        phandle node;
-        int inst;
-        
-        inst = prom_devopen (path);
-        if (inst == -1) return 0;
-        node = prom_inst2pkg (inst);
-        prom_devclose (inst);
-        if (node == -1) return 0;
-        return node;
-}
diff --git a/arch/sparc/prom/tree_64.c b/arch/sparc/prom/tree_64.c
index 691be68932f8..d93660048376 100644
--- a/arch/sparc/prom/tree_64.c
+++ b/arch/sparc/prom/tree_64.c
@@ -374,24 +374,6 @@ inline phandle prom_inst2pkg(int inst)
         return node;
 }
 
-/* Return 'node' assigned to a particular prom 'path'
- * FIXME: Should work for v0 as well
- */
-phandle prom_pathtoinode(const char *path)
-{
-        phandle node;
-        int inst;
-
-        inst = prom_devopen (path);
-        if (inst == 0)
-                return 0;
-        node = prom_inst2pkg(inst);
-        prom_devclose(inst);
-        if (node == -1)
-                return 0;
-        return node;
-}
-
 int prom_ihandle2path(int handle, char *buffer, int bufsize)
 {
         unsigned long args[7];
diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c
index cbcc8d8ea93a..7a6e68e4f748 100644
--- a/arch/x86/crypto/ghash-clmulni-intel_glue.c
+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c
@@ -10,6 +10,7 @@
  * by the Free Software Foundation.
  */
 
+#include <linux/err.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/kernel.h>
diff --git a/arch/x86/include/asm/pvclock.h b/arch/x86/include/asm/pvclock.h
index 7f7e577a0e39..31d84acc1512 100644
--- a/arch/x86/include/asm/pvclock.h
+++ b/arch/x86/include/asm/pvclock.h
@@ -11,6 +11,7 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src);
 void pvclock_read_wallclock(struct pvclock_wall_clock *wall,
                             struct pvclock_vcpu_time_info *vcpu,
                             struct timespec *ts);
+void pvclock_resume(void);
 
 /*
  * Scale a 64-bit delta by scaling and multiplying by a 32-bit fraction,
diff --git a/arch/x86/kernel/pvclock.c b/arch/x86/kernel/pvclock.c
index 008b91eefa18..42eb3300dfc6 100644
--- a/arch/x86/kernel/pvclock.c
+++ b/arch/x86/kernel/pvclock.c
@@ -83,6 +83,11 @@ unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src)
 
 static atomic64_t last_value = ATOMIC64_INIT(0);
 
+void pvclock_resume(void)
+{
+        atomic64_set(&last_value, 0);
+}
+
 cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src)
 {
         struct pvclock_shadow_time shadow;
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index b2bb5aa3b054..5da5e53fb94c 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -426,6 +426,8 @@ void xen_timer_resume(void)
 {
         int cpu;
 
+        pvclock_resume();
+
         if (xen_clockevent != &xen_vcpuop_clockevent)
                 return;