44 files changed, 9711 insertions, 3054 deletions

diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
new file mode 100644
index 000000000000..9ccfe508dea2
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -0,0 +1,664 @@
+/*
+ * Device Tree Source for AM33xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        rng_fck: rng_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm0_tbclk: ehrpwm0_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm0_gate_tbclk>;
+        };
+
+        ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm1_tbclk: ehrpwm1_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm1_gate_tbclk>;
+        };
+
+        ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0664>;
+        };
+
+        ehrpwm2_tbclk: ehrpwm2_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ehrpwm2_gate_tbclk>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0490>, <0x045c>, <0x0468>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0480>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0484>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x04d8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0488>, <0x0420>, <0x042c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a8>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0494>, <0x0434>, <0x0440>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x0498>, <0x0448>, <0x0454>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                reg = <0x04a4>;
+                ti,index-starts-at-one;
+                ti,set-rate-parent;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-no-gate-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x048c>, <0x0470>, <0x049c>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x04ac>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        cefuse_fck: cefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0a20>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x014c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
+                reg = <0x0530>;
+        };
+
+        mmu_fck: mmu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0914>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+                reg = <0x0528>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0508>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x050c>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0510>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0518>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x051c>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x0504>;
+        };
+
+        usbotg_fck: usbotg_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x047c>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ieee5000_fck: ieee5000_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x00e4>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x0538>;
+        };
+
+        l4_rtc_gclk: l4_rtc_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4fw_gclk: l4fw_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sysclk_div_ck: sysclk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
+                reg = <0x0520>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+                reg = <0x053c>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0408>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00ac>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b0>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <18>;
+                reg = <0x00b4>;
+        };
+
+        lcd_gclk: lcd_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x0534>;
+                ti,set-rate-parent;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x052c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x052c>;
+                ti,max-div = <2>;
+        };
+
+        sysclkout_pre_ck: sysclkout_pre_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
+                reg = <0x0700>;
+        };
+
+        clkout2_div_ck: clkout2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sysclkout_pre_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <8>;
+                reg = <0x0700>;
+        };
+
+        dbg_sysclk_ck: dbg_sysclk_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0414>;
+        };
+
+        dbg_clka_ck: dbg_clka_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_core_m4_ck>;
+                ti,bit-shift = <30>;
+                reg = <0x0414>;
+        };
+
+        stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0414>;
+        };
+
+        trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0414>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&stm_pmd_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&trace_pmd_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <64>;
+                reg = <0x0414>;
+                ti,index-power-of-two;
+        };
+
+        clkout2_ck: clkout2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkout2_div_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0700>;
+        };
+};
+
+&prcm_clockdomains {
+        clk_24mhz_clkdm: clk_24mhz_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&clkdiv32k_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f6d8ffe98d0b..6d95d3df33c7 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -102,6 +102,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44e00000 {
+                        compatible = "ti,am3-prcm";
+                        reg = <0x44e00000 0x4000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am3-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 intc: interrupt-controller@48200000 {
                         compatible = "ti,omap2-intc";
                         interrupt-controller;
@@ -794,3 +820,5 @@
                 };
         };
 };
+
+/include/ "am33xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 2fbe02faa8b1..788391f91684 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -61,3 +61,6 @@
                 };
         };
 };
+
+/include/ "am35xx-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
new file mode 100644
index 000000000000..df489d310b50
--- /dev/null
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -0,0 +1,128 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        emac_ick: emac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <1>;
+        };
+
+        emac_fck: emac_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&rmii_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <9>;
+        };
+
+        vpfe_ick: vpfe_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <2>;
+        };
+
+        vpfe_fck: vpfe_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pclk_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <10>;
+        };
+
+        hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&ipss_ick>;
+                reg = <0x059c>;
+                ti,bit-shift = <0>;
+        };
+
+        hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <8>;
+        };
+
+        hecc_ck: hecc_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x059c>;
+                ti,bit-shift = <3>;
+        };
+};
+&cm_clocks {
+        ipss_ick: ipss_ick {
+                #clock-cells = <0>;
+                compatible = "ti,am35xx-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        rmii_ck: rmii_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <50000000>;
+        };
+
+        pclk_ck: pclk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        uart4_ick_am35xx: uart4_ick_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        uart4_fck_am35xx: uart4_fck_am35xx {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
+                         <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
+                         <&hecc_ck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
+        };
+};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 974d103ab3b1..c6bd4d986c29 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,6 +67,32 @@
                 ranges;
                 ti,hwmods = "l3_main";
 
+                prcm: prcm@44df0000 {
+                        compatible = "ti,am4-prcm";
+                        reg = <0x44df0000 0x11000>;
+
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@44e10000 {
+                        compatible = "ti,am4-scrm";
+                        reg = <0x44e10000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 edma: edma@49000000 {
                         compatible = "ti,edma3";
                         ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
@@ -665,3 +691,5 @@
                 };
         };
 };
+
+/include/ "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
new file mode 100644
index 000000000000..142009cc9332
--- /dev/null
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -0,0 +1,656 @@
+/*
+ * Device Tree Source for AM43xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0040>;
+        };
+
+        adc_tsc_fck: adc_tsc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan0_fck: dcan0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dcan1_fck: dcan1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp0_fck: mcasp0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcasp1_fck: mcasp1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex0_fck: smartreflex0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        smartreflex1_fck: smartreflex1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sha0_fck: sha0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes0_fck: aes0_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&prcm_clocks {
+        clk_32768_ck: clk_32768_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        clk_rc32k_ck: clk_rc32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_24000000_ck: virt_24000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+        };
+
+        virt_25000000_ck: virt_25000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <25000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        tclkin_ck: tclkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m4_ck: dpll_core_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d38>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m5_ck: dpll_core_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d3c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m6_ck: dpll_core_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d40>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2d70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2da0>, <0x2da4>, <0x2dac>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_disp_ck: dpll_disp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+        };
+
+        dpll_disp_m2_ck: dpll_disp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_disp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e30>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2de0>, <0x2de4>, <0x2dec>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2df0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        clk_24mhz: clk_24mhz {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        clkdiv32k_ck: clkdiv32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&clk_24mhz>;
+                clock-mult = <1>;
+                clock-div = <732>;
+        };
+
+        clkdiv32k_ick: clkdiv32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a38>;
+        };
+
+        sysclk_div: sysclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pruss_ocp_gclk: pruss_ocp_gclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
+                reg = <0x4248>;
+        };
+
+        clk_32k_tpm_ck: clk_32k_tpm_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        timer1_fck: timer1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4200>;
+        };
+
+        timer2_fck: timer2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4204>;
+        };
+
+        timer3_fck: timer3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4208>;
+        };
+
+        timer4_fck: timer4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x420c>;
+        };
+
+        timer5_fck: timer5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4210>;
+        };
+
+        timer6_fck: timer6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4214>;
+        };
+
+        timer7_fck: timer7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+                reg = <0x4218>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+                reg = <0x422c>;
+        };
+
+        l3_gclk: l3_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l4hs_gclk: l4hs_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3s_gclk: l3s_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4ls_gclk: l4ls_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4_div2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
+                reg = <0x4238>;
+        };
+
+        clk_32k_mosc_ck: clk_32k_mosc_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4240>;
+        };
+
+        gpio0_dbclk: gpio0_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&gpio0_dbclk_mux_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2b68>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c78>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c80>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c88>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c90>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&clkdiv32k_ick>;
+                ti,bit-shift = <8>;
+                reg = <0x8c98>;
+        };
+
+        mmc_clk: mmc_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x423c>;
+        };
+
+        gfx_fck_div_ck: gfx_fck_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&gfx_fclk_clksel_ck>;
+                reg = <0x423c>;
+                ti,max-div = <2>;
+        };
+
+        disp_clk: disp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
+                reg = <0x4244>;
+        };
+
+        dpll_extdev_ck: dpll_extdev_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
+                reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+        };
+
+        dpll_extdev_m2_ck: dpll_extdev_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_extdev_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e70>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mux_synctimer32k_ck: mux_synctimer32k_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
+                reg = <0x4230>;
+        };
+
+        synctimer_32kclk: synctimer_32kclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&mux_synctimer32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x2a30>;
+        };
+
+        timer8_fck: timer8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x421c>;
+        };
+
+        timer9_fck: timer9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4220>;
+        };
+
+        timer10_fck: timer10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4224>;
+        };
+
+        timer11_fck: timer11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
+                reg = <0x4228>;
+        };
+
+        cpsw_50m_clkdiv: cpsw_50m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m5_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        cpsw_5m_clkdiv: cpsw_5m_clkdiv {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cpsw_50m_clkdiv>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,am3-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_m4_ck: dpll_ddr_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2db8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_clkdcoldo: dpll_per_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dll_aging_clk_div: dll_aging_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x4250>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        div_core_25m_ck: div_core_25m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sysclk_div>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_12m_clk: func_12m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        vtp_clk_div: vtp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usbphy_32khz_clkmux: usbphy_32khz_clkmux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
+                reg = <0x4260>;
+        };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index d0df4c4e8b0a..1fd75aa4639d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -104,6 +104,45 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,dra7-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a005000 {
+                        compatible = "ti,dra7-cm-core-aon";
+                        reg = <0x4a005000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,dra7-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -584,3 +623,5 @@
                 };
         };
 };
+
+/include/ "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
new file mode 100644
index 000000000000..e96da9a898ad
--- /dev/null
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -0,0 +1,2015 @@
+/*
+ * Device Tree Source for DRA7xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        atl_clkin0_ck: atl_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin1_ck: atl_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atl_clkin2_ck: atl_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        atlclkin3_ck: atlclkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        hdmi_clkin_ck: hdmi_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlb_clkin_ck: mlb_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        mlbp_clkin_ck: mlbp_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        pciesref_acs_clk_ck: pciesref_acs_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <100000000>;
+        };
+
+        ref_clkin0_ck: ref_clkin0_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin1_ck: ref_clkin1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin2_ck: ref_clkin2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        ref_clkin3_ck: ref_clkin3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        rmii_clk_ck: rmii_clk_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        sdvenc_clkin_ck: sdvenc_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_20000000_ck: virt_20000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <20000000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        sys_clkin2: sys_clkin2 {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <22579200>;
+        };
+
+        usb_otg_clkin_ck: usb_otg_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_clkin_ck: video1_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video1_m2_clkin_ck: video1_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_clkin_ck: video2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        video2_m2_clkin_ck: video2_m2_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dclk_div: mpu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_dsp_ck: dpll_dsp_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
+                reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
+        };
+
+        dpll_dsp_m2_ck: dpll_dsp_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0244>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_m2_ck: dpll_iva_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dclk: iva_dclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_iva_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_gpu_ck: dpll_gpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
+        };
+
+        dpll_gpu_m2_ck: dpll_gpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02e8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_dpll_out_dclk_div: core_dpll_out_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_ddr_ck: dpll_ddr_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
+        };
+
+        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0220>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_ck: dpll_gmac_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
+                reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
+        };
+
+        dpll_gmac_m2_ck: dpll_gmac_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        video2_dclk_div: video2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_dclk_div: video1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_m2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_dclk_div: hdmi_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_eve_ck: dpll_eve_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
+                reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
+        };
+
+        dpll_eve_m2_ck: dpll_eve_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_eve_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0294>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        eve_dclk_div: eve_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_eve_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_ddr_x2_ck: dpll_ddr_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_ddr_ck>;
+        };
+
+        dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0228>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_dsp_x2_ck: dpll_dsp_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_dsp_ck>;
+        };
+
+        dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0248>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_x2_ck: dpll_gmac_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_gmac_ck>;
+        };
+
+        dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02c8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x02bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        gmii_m_clk_div: gmii_m_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_gmac_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hdmi_clk2_div: hdmi_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdmi_div_clk: hdmi_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&hdmi_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_clk2_div: video1_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video1_div_clk: video1_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video1_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_clk2_div: video2_clk2_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        video2_div_clk: video2_div_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&video2_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ipu1_gfclk_mux: ipu1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0520>;
+        };
+
+        mcasp1_ahclkr_mux: mcasp1_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_ahclkx_mux: mcasp1_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x0550>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0560>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        uart6_gfclk_mux: uart6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin1: sys_clkin1 {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x0118>;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x0114>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x011c>;
+                ti,dividers = <8>, <16>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                reg = <0x0178>;
+                ti,max-div = <2>;
+        };
+
+        abe_giclk_div: abe_giclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                reg = <0x0174>;
+                ti,max-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                reg = <0x01d8>;
+                ti,dividers = <16>, <32>;
+        };
+
+        abe_sys_clk_div: abe_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0120>;
+                ti,max-div = <2>;
+        };
+
+        adc_gfclk_mux: adc_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
+                reg = <0x01dc>;
+        };
+
+        sys_clk1_dclk_div: sys_clk1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c8>;
+                ti,index-power-of-two;
+        };
+
+        sys_clk2_dclk_div: sys_clk2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin2>;
+                ti,max-div = <64>;
+                reg = <0x01cc>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_dclk_div: per_abe_x1_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01bc>;
+                ti,index-power-of-two;
+        };
+
+        dsp_gclk_div: dsp_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_dsp_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x018c>;
+                ti,index-power-of-two;
+        };
+
+        gpu_dclk: gpu_dclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gpu_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01a0>;
+                ti,index-power-of-two;
+        };
+
+        emif_phy_dclk_div: emif_phy_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_ddr_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0190>;
+                ti,index-power-of-two;
+        };
+
+        gmac_250m_dclk_div: gmac_250m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        l3init_480m_dclk_div: l3init_480m_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01ac>;
+                ti,index-power-of-two;
+        };
+
+        usb_otg_dclk_div: usb_otg_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&usb_otg_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0184>;
+                ti,index-power-of-two;
+        };
+
+        sata_dclk_div: sata_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x01c0>;
+                ti,index-power-of-two;
+        };
+
+        pcie2_dclk_div: pcie2_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b8>;
+                ti,index-power-of-two;
+        };
+
+        pcie_dclk_div: pcie_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x01b4>;
+                ti,index-power-of-two;
+        };
+
+        emu_dclk_div: emu_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                ti,max-div = <64>;
+                reg = <0x0194>;
+                ti,index-power-of-two;
+        };
+
+        secure_32k_dclk_div: secure_32k_dclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&secure_32k_clk_src_ck>;
+                ti,max-div = <64>;
+                reg = <0x01c4>;
+                ti,index-power-of-two;
+        };
+
+        clkoutmux0_clk_mux: clkoutmux0_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0158>;
+        };
+
+        clkoutmux1_clk_mux: clkoutmux1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x015c>;
+        };
+
+        clkoutmux2_clk_mux: clkoutmux2_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
+                reg = <0x0160>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        eve_clk: eve_clk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
+                reg = <0x0180>;
+        };
+
+        hdmi_dpll_clk_mux: hdmi_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01a4>;
+        };
+
+        mlb_clk: mlb_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlb_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0134>;
+                ti,index-power-of-two;
+        };
+
+        mlbp_clk: mlbp_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mlbp_clkin_ck>;
+                ti,max-div = <64>;
+                reg = <0x0130>;
+                ti,index-power-of-two;
+        };
+
+        per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                ti,max-div = <64>;
+                reg = <0x0138>;
+                ti,index-power-of-two;
+        };
+
+        timer_sys_clk_div: timer_sys_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin1>;
+                reg = <0x0144>;
+                ti,max-div = <2>;
+        };
+
+        video1_dpll_clk_mux: video1_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d0>;
+        };
+
+        video2_dpll_clk_mux: video2_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                reg = <0x01d4>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dcan1_sys_clk_mux: dcan1_sys_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin2>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart10_gfclk_mux: uart10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1880>;
+        };
+};
+&cm_core_clocks {
+        dpll_pcie_ref_ck: dpll_pcie_ref_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&sys_clkin1>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c 0x4>;
+                ti,bit-shift = <7>;
+        };
+
+        apll_pcie_ck: apll_pcie_ck {
+                #clock-cells = <0>;
+                compatible = "ti,dra7-apll-clock";
+                clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
+                reg = <0x021c>, <0x0220>;
+        };
+
+        optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
+                compatible = "ti,divider-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x021c>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+        };
+
+        optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&apll_pcie_ck>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <9>;
+        };
+
+        optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 {
+                compatible = "ti,gate-clock";
+                clocks = <&optfclk_pciephy_div>;
+                #clock-cells = <0>;
+                reg = <0x13b0>;
+                ti,bit-shift = <10>;
+        };
+
+        apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        apll_pcie_m2_ck: apll_pcie_m2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll_pcie_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_96m_aon_dclk_div: func_96m_aon_dclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_pcie_ref_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h13x2_ck: dpll_per_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+        };
+
+        dss_hdmi_clk: dss_hdmi_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&hdmi_dpll_clk_mux>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_video1_clk: dss_video1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video1_dpll_clk_mux>;
+                ti,bit-shift = <12>;
+                reg = <0x1120>;
+        };
+
+        dss_video2_clk: dss_video2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&video2_dpll_clk_mux>;
+                ti,bit-shift = <13>;
+                reg = <0x1120>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1760>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1768>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1770>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1778>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1780>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1810>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1818>;
+        };
+
+        mmc1_clk32k: mmc1_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1328>;
+        };
+
+        mmc2_clk32k: mmc2_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1330>;
+        };
+
+        mmc3_clk32k: mmc3_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1820>;
+        };
+
+        mmc4_clk32k: mmc4_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1828>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin1>;
+                ti,bit-shift = <8>;
+                reg = <0x1388>;
+        };
+
+        usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x13f0>;
+        };
+
+        usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x1340>;
+        };
+
+        usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0688>;
+        };
+
+        usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0698>;
+        };
+
+        atl_dpll_clk_mux: atl_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0c00>;
+        };
+
+        atl_gfclk_mux: atl_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
+                ti,bit-shift = <26>;
+                reg = <0x0c00>;
+        };
+
+        gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_gmac_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x13d0>;
+                ti,dividers = <2>;
+        };
+
+        gmac_rft_clk_mux: gmac_rft_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
+                ti,bit-shift = <25>;
+                reg = <0x13d0>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
+                ti,bit-shift = <26>;
+                reg = <0x1220>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                ti,bit-shift = <24>;
+                reg = <0x0e50>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        mcasp2_ahclkr_mux: mcasp2_ahclkr_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_ahclkx_mux: mcasp2_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <28>;
+                reg = <0x1860>;
+        };
+
+        mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1860>;
+        };
+
+        mcasp3_ahclkx_mux: mcasp3_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1868>;
+        };
+
+        mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1868>;
+        };
+
+        mcasp4_ahclkx_mux: mcasp4_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1898>;
+        };
+
+        mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1898>;
+        };
+
+        mcasp5_ahclkx_mux: mcasp5_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1878>;
+        };
+
+        mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1878>;
+        };
+
+        mcasp6_ahclkx_mux: mcasp6_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1904>;
+        };
+
+        mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1904>;
+        };
+
+        mcasp7_ahclkx_mux: mcasp7_ahclkx_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1908>;
+        };
+
+        mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <22>;
+                reg = <0x1908>;
+        };
+
+        mcasp8_ahclk_mux: mcasp8_ahclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atlclkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
+                ti,bit-shift = <22>;
+                reg = <0x1890>;
+        };
+
+        mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
+                ti,bit-shift = <24>;
+                reg = <0x1890>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        mmc1_fclk_div: mmc1_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1328>;
+                ti,index-power-of-two;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        mmc2_fclk_div: mmc2_fclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1330>;
+                ti,index-power-of-two;
+        };
+
+        mmc3_gfclk_mux: mmc3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1820>;
+        };
+
+        mmc3_gfclk_div: mmc3_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc3_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1820>;
+                ti,index-power-of-two;
+        };
+
+        mmc4_gfclk_mux: mmc4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1828>;
+        };
+
+        mmc4_gfclk_div: mmc4_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc4_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1828>;
+                ti,index-power-of-two;
+        };
+
+        qspi_gfclk_mux: qspi_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1838>;
+        };
+
+        qspi_gfclk_div: qspi_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&qspi_gfclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <4>;
+                reg = <0x1838>;
+                ti,index-power-of-two;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1728>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1730>;
+        };
+
+        timer13_gfclk_mux: timer13_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17c8>;
+        };
+
+        timer14_gfclk_mux: timer14_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d0>;
+        };
+
+        timer15_gfclk_mux: timer15_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x17d8>;
+        };
+
+        timer16_gfclk_mux: timer16_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1830>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1738>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1740>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1748>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x1750>;
+        };
+
+        uart1_gfclk_mux: uart1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        uart2_gfclk_mux: uart2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1848>;
+        };
+
+        uart3_gfclk_mux: uart3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1850>;
+        };
+
+        uart4_gfclk_mux: uart4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+        };
+
+        uart5_gfclk_mux: uart5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1870>;
+        };
+
+        uart7_gfclk_mux: uart7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18d0>;
+        };
+
+        uart8_gfclk_mux: uart8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e0>;
+        };
+
+        uart9_gfclk_mux: uart9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x18e8>;
+        };
+
+        vip1_gclk_mux: vip1_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1020>;
+        };
+
+        vip2_gclk_mux: vip2_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        vip3_gclk_mux: vip3_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+};
+
+&cm_core_clockdomains {
+        coreaon_clkdm: coreaon_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 427395c083f5..a5fc83b9c835 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -89,6 +89,45 @@
                         interrupts = <0>;
                 };
 
+                prm: prm@48306000 {
+                        compatible = "ti,omap3-prm";
+                        reg = <0x48306000 0x4000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm: cm@48004000 {
+                        compatible = "ti,omap3-cm";
+                        reg = <0x48004000 0x4000>;
+
+                        cm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@48002000 {
+                        compatible = "ti,omap3-scrm";
+                        reg = <0x48002000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@48320000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x48320000 0x20>;
@@ -632,3 +671,5 @@
                 };
         };
 };
+
+/include/ "omap3xxx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
new file mode 100644
index 000000000000..02f6c7fabbec
--- /dev/null
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -0,0 +1,208 @@
+/*
+ * Device Tree Source for OMAP3430 ES1 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        gfx_l3_ck: gfx_l3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        gfx_l3_fck: gfx_l3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,max-div = <7>;
+                reg = <0x0b40>;
+                ti,index-starts-at-one;
+        };
+
+        gfx_l3_ick: gfx_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&gfx_l3_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gfx_cg1_ck: gfx_cg1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <1>;
+        };
+
+        gfx_cg2_ck: gfx_cg2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&gfx_l3_fck>;
+                reg = <0x0b00>;
+                ti,bit-shift = <2>;
+        };
+
+        d2d_26m_fck: d2d_26m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <3>;
+        };
+
+        fshostusb_fck: fshostusb_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <5>;
+        };
+
+        ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es1: ssi_ssr_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es1>, <&ssi_ssr_div_fck_3430es1>;
+        };
+
+        ssi_sst_fck_3430es1: ssi_sst_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es1>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es1: hsotgusb_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        fac_ick: fac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <8>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es1: ssi_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usb_l4_gate_ick: usb_l4_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <5>;
+                reg = <0x0a10>;
+        };
+
+        usb_l4_div_ick: usb_l4_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <4>;
+                ti,max-div = <1>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        usb_l4_ick: usb_l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+        };
+
+        dss1_alwon_fck_3430es1: dss1_alwon_fck_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es1: dss_ick_3430es1 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es1>;
+        };
+
+        gfx_3430es1_clkdm: gfx_3430es1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gfx_l3_ck>, <&gfx_cg1_ck>, <&gfx_cg2_ck>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es1>, <&dss_ick_3430es1>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&d2d_26m_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&fshostusb_fck>, <&fac_ick>, <&ssi_ick_3430es1>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..b02017b7630e
--- /dev/null
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -0,0 +1,268 @@
+/*
+ * Device Tree Source for OMAP34XX/OMAP36XX clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        security_l4_ick2: security_l4_ick2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        aes1_ick: aes1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                ti,bit-shift = <3>;
+                reg = <0x0a14>;
+        };
+
+        rng_ick: rng_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <2>;
+        };
+
+        sha11_ick: sha11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <1>;
+        };
+
+        des1_ick: des1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l4_ick2>;
+                reg = <0x0a14>;
+                ti,bit-shift = <0>;
+        };
+
+        cam_mclk: cam_mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0f00>;
+                ti,set-rate-parent;
+        };
+
+        cam_ick: cam_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0f10>;
+                ti,bit-shift = <0>;
+        };
+
+        csi2_96m_fck: csi2_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0f00>;
+                ti,bit-shift = <1>;
+        };
+
+        security_l3_ick: security_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        pka_ick: pka_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&security_l3_ick>;
+                reg = <0x0a14>;
+                ti,bit-shift = <4>;
+        };
+
+        icr_ick: icr_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <29>;
+        };
+
+        des2_ick: des2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <26>;
+        };
+
+        mspro_ick: mspro_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <23>;
+        };
+
+        mailboxes_ick: mailboxes_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <7>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sr1_fck: sr1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <6>;
+        };
+
+        sr2_fck: sr2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <7>;
+        };
+
+        sr_l4_ick: sr_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll2_fck: dpll2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0040>;
+                ti,index-starts-at-one;
+        };
+
+        dpll2_ck: dpll2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll2_fck>;
+                reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
+                ti,low-power-stop;
+                ti,lock;
+                ti,low-power-bypass;
+        };
+
+        dpll2_m2_ck: dpll2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0044>;
+                ti,index-starts-at-one;
+        };
+
+        iva2_ck: iva2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll2_m2_ck>;
+                reg = <0x0000>;
+                ti,bit-shift = <0>;
+        };
+
+        modem_fck: modem_fck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <31>;
+        };
+
+        sad2d_ick: sad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <3>;
+        };
+
+        mad2d_ick: mad2d_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <3>;
+        };
+
+        mspro_fck: mspro_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <23>;
+        };
+};
+
+&cm_clockdomains {
+        cam_clkdm: cam_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cam_ick>, <&csi2_96m_fck>;
+        };
+
+        iva2_clkdm: iva2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&iva2_ck>;
+        };
+
+        dpll2_clkdm: dpll2_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll2_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
+        };
+
+        d2d_clkdm: d2d_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
+                         <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
+                         <&mspro_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 77d124678c95..2e92360da1f3 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -39,3 +39,7 @@
                 };
         };
 };
+
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..af9ae5346bf2
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,242 @@
+/*
+ * Device Tree Source for OMAP36xx/AM35xx/OMAP34xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        corex2_d3_fck: corex2_d3_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        corex2_d5_fck: corex2_d5_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&corex2_fck>;
+                clock-mult = <1>;
+                clock-div = <5>;
+        };
+};
+&cm_clocks {
+        dpll5_ck: dpll5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d04>, <0x0d24>, <0x0d4c>, <0x0d34>;
+                ti,low-power-stop;
+                ti,lock;
+        };
+
+        dpll5_m2_ck: dpll5_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll5_ck>;
+                ti,max-div = <31>;
+                reg = <0x0d50>;
+                ti,index-starts-at-one;
+        };
+
+        sgx_gate_fck: sgx_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0b00>;
+        };
+
+        core_d3_ck: core_d3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        core_d4_ck: core_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        core_d6_ck: core_d6_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <6>;
+        };
+
+        omap_192m_alwon_fck: omap_192m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_d2_ck: core_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        sgx_mux_fck: sgx_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_d3_ck>, <&core_d4_ck>, <&core_d6_ck>, <&cm_96m_fck>, <&omap_192m_alwon_fck>, <&core_d2_ck>, <&corex2_d3_fck>, <&corex2_d5_fck>;
+                reg = <0x0b40>;
+        };
+
+        sgx_fck: sgx_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&sgx_gate_fck>, <&sgx_mux_fck>;
+        };
+
+        sgx_ick: sgx_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&l3_ick>;
+                reg = <0x0b10>;
+                ti,bit-shift = <0>;
+        };
+
+        cpefuse_fck: cpefuse_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <0>;
+        };
+
+        ts_fck: ts_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_32k_fck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <1>;
+        };
+
+        usbtll_fck: usbtll_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x0a08>;
+                ti,bit-shift = <2>;
+        };
+
+        usbtll_ick: usbtll_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a18>;
+                ti,bit-shift = <2>;
+        };
+
+        mmchs3_ick: mmchs3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <30>;
+        };
+
+        mmchs3_fck: mmchs3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <30>;
+        };
+
+        dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&dpll4_m4x2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0e00>;
+                ti,set-rate-parent;
+        };
+
+        dss_ick_3430es2: dss_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x0e10>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_120m_fck: usbhost_120m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll5_m2_ck>;
+                reg = <0x1400>;
+                ti,bit-shift = <1>;
+        };
+
+        usbhost_48m_fck: usbhost_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,dss-gate-clock";
+                clocks = <&omap_48m_fck>;
+                reg = <0x1400>;
+                ti,bit-shift = <0>;
+        };
+
+        usbhost_ick: usbhost_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dss-interface-clock";
+                clocks = <&l4_ick>;
+                reg = <0x1410>;
+                ti,bit-shift = <0>;
+        };
+};
+
+&cm_clockdomains {
+        dpll5_clkdm: dpll5_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll5_ck>;
+        };
+
+        sgx_clkdm: sgx_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sgx_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>,
+                         <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>;
+        };
+
+        usbhost_clkdm: usbhost_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&usbhost_120m_fck>, <&usbhost_48m_fck>,
+                         <&usbhost_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
new file mode 100644
index 000000000000..2fcf253b677c
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Device Tree Source for OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-j-type-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-rate-parent;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,hsdiv-gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        uart4_fck: uart4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <18>;
+        };
+};
+
+&cm_clockdomains {
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>, <&uart4_fck>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
new file mode 100644
index 000000000000..8ed475dd63c9
--- /dev/null
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -0,0 +1,198 @@
+/*
+ * Device Tree Source for OMAP34xx/OMAP36xx clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_clocks {
+        ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0a00>;
+        };
+
+        ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&corex2_fck>;
+                ti,bit-shift = <8>;
+                reg = <0x0a40>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+        };
+
+        ssi_ssr_fck_3430es2: ssi_ssr_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_gate_fck_3430es2>, <&ssi_ssr_div_fck_3430es2>;
+        };
+
+        ssi_sst_fck_3430es2: ssi_sst_fck_3430es2 {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&ssi_ssr_fck_3430es2>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        hsotgusb_ick_3430es2: hsotgusb_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-hsotgusb-interface-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <4>;
+        };
+
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        ssi_ick_3430es2: ssi_ick_3430es2 {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-ssi-interface-clock";
+                clocks = <&ssi_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <0>;
+        };
+
+        usim_gate_fck: usim_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&omap_96m_fck>;
+                ti,bit-shift = <9>;
+                reg = <0x0c00>;
+        };
+
+        sys_d2_ck: sys_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d2_fck: omap_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_96m_d4_fck: omap_96m_d4_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        omap_96m_d8_fck: omap_96m_d8_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        omap_96m_d10_fck: omap_96m_d10_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <10>;
+        };
+
+        dpll5_m2_d4_ck: dpll5_m2_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll5_m2_d8_ck: dpll5_m2_d8_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        dpll5_m2_d16_ck: dpll5_m2_d16_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll5_m2_d20_ck: dpll5_m2_d20_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll5_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <20>;
+        };
+
+        usim_mux_fck: usim_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_ck>, <&sys_d2_ck>, <&omap_96m_d2_fck>, <&omap_96m_d4_fck>, <&omap_96m_d8_fck>, <&omap_96m_d10_fck>, <&dpll5_m2_d4_ck>, <&dpll5_m2_d8_ck>, <&dpll5_m2_d16_ck>, <&dpll5_m2_d20_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        usim_fck: usim_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usim_gate_fck>, <&usim_mux_fck>;
+        };
+
+        usim_ick: usim_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <9>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>, <&hsotgusb_ick_3430es2>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>, <&usim_ick>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
+                         <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
+                         <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
+                         <&ssi_ick_3430es2>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index b7c7bd96c404..7e8dee9175d6 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -51,3 +51,8 @@
                 };
         };
 };
+
+/include/ "omap36xx-clocks.dtsi"
+/include/ "omap34xx-omap36xx-clocks.dtsi"
+/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
+/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
new file mode 100644
index 000000000000..cb04d4b37e7f
--- /dev/null
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -0,0 +1,1660 @@
+/*
+ * Device Tree Source for OMAP3 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        virt_16_8m_ck: virt_16_8m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        osc_sys_ck: osc_sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12m_ck>, <&virt_13m_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_38_4m_ck>, <&virt_16_8m_ck>;
+                reg = <0x0d40>;
+        };
+
+        sys_ck: sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&osc_sys_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1270>;
+                ti,index-starts-at-one;
+        };
+
+        sys_clkout1: sys_clkout1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&osc_sys_ck>;
+                reg = <0x0d70>;
+                ti,bit-shift = <7>;
+        };
+
+        dpll3_x2_ck: dpll3_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m2x2_ck: dpll3_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_x2_ck: dpll4_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        corex2_fck: corex2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkup_l4_ick: wkup_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+&scrm_clocks {
+        mcbsp5_mux_fck: mcbsp5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp5_fck: mcbsp5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+        };
+
+        mcbsp1_mux_fck: mcbsp1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x0274>;
+        };
+
+        mcbsp1_fck: mcbsp1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+        };
+
+        mcbsp2_mux_fck: mcbsp2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <6>;
+                reg = <0x0274>;
+        };
+
+        mcbsp2_fck: mcbsp2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+        };
+
+        mcbsp3_mux_fck: mcbsp3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp3_fck: mcbsp3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+        };
+
+        mcbsp4_mux_fck: mcbsp4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&per_96m_fck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x02d8>;
+        };
+
+        mcbsp4_fck: mcbsp4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+        };
+};
+&cm_clocks {
+        dummy_apb_pclk: dummy_apb_pclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        omap_32k_fck: omap_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12m_ck: virt_12m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13m_ck: virt_13m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_38_4m_ck: virt_38_4m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        dpll4_ck: dpll4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-per-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
+        };
+
+        dpll4_m2_ck: dpll4_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0d48>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m2x2_mul_ck: dpll4_m2x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m2x2_ck: dpll4_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m2x2_mul_ck>;
+                ti,bit-shift = <0x1b>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_96m_alwon_fck: omap_96m_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll3_ck: dpll3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-core-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0d00>, <0x0d20>, <0x0d40>, <0x0d30>;
+        };
+
+        dpll3_m3_ck: dpll3_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <31>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll3_m3x2_mul_ck: dpll3_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll3_m3x2_ck: dpll3_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll3_m3x2_mul_ck>;
+                ti,bit-shift = <0xc>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_core_alwon_ck: emu_core_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sys_altclk: sys_altclk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        mcbsp_clks: mcbsp_clks {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+
+        dpll3_m2_ck: dpll3_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll3_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <31>;
+                reg = <0x0d40>;
+                ti,index-starts-at-one;
+        };
+
+        core_ck: core_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll3_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll1_fck: dpll1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <19>;
+                ti,max-div = <7>;
+                reg = <0x0940>;
+                ti,index-starts-at-one;
+        };
+
+        dpll1_ck: dpll1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-dpll-clock";
+                clocks = <&sys_ck>, <&dpll1_fck>;
+                reg = <0x0904>, <0x0924>, <0x0940>, <0x0934>;
+        };
+
+        dpll1_x2_ck: dpll1_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll1_x2m2_ck: dpll1_x2m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll1_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0944>;
+                ti,index-starts-at-one;
+        };
+
+        cm_96m_fck: cm_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        omap_96m_fck: omap_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0d40>;
+        };
+
+        dpll4_m3_ck: dpll4_m3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m3x2_mul_ck: dpll4_m3x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m3_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m3x2_ck: dpll4_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m3x2_mul_ck>;
+                ti,bit-shift = <0x1c>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        omap_54m_fck: omap_54m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll4_m3x2_ck>, <&sys_altclk>;
+                ti,bit-shift = <5>;
+                reg = <0x0d40>;
+        };
+
+        cm_96m_d2_fck: cm_96m_d2_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&cm_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        omap_48m_fck: omap_48m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&cm_96m_d2_fck>, <&sys_altclk>;
+                ti,bit-shift = <3>;
+                reg = <0x0d40>;
+        };
+
+        omap_12m_fck: omap_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dpll4_m4_ck: dpll4_m4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <32>;
+                reg = <0x0e40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m4x2_mul_ck: dpll4_m4x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m4_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m4x2_ck: dpll4_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m4x2_mul_ck>;
+                ti,bit-shift = <0x1d>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m5_ck: dpll4_m5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,max-div = <63>;
+                reg = <0x0f40>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m5_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m5x2_ck: dpll4_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m5x2_mul_ck>;
+                ti,bit-shift = <0x1e>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        dpll4_m6_ck: dpll4_m6_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll4_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <63>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        dpll4_m6x2_mul_ck: dpll4_m6x2_mul_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+
+        dpll4_m6x2_ck: dpll4_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll4_m6x2_mul_ck>;
+                ti,bit-shift = <0x1f>;
+                reg = <0x0d00>;
+                ti,set-bit-to-disable;
+        };
+
+        emu_per_alwon_ck: emu_per_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll4_m6x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        clkout2_src_gate_ck: clkout2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_mux_ck: clkout2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_ck>, <&sys_ck>, <&cm_96m_fck>, <&omap_54m_fck>;
+                reg = <0x0d70>;
+        };
+
+        clkout2_src_ck: clkout2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&clkout2_src_gate_ck>, <&clkout2_src_mux_ck>;
+        };
+
+        sys_clkout2: sys_clkout2 {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&clkout2_src_ck>;
+                ti,bit-shift = <3>;
+                ti,max-div = <64>;
+                reg = <0x0d70>;
+                ti,index-power-of-two;
+        };
+
+        mpu_ck: mpu_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll1_x2m2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        arm_fck: arm_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mpu_ck>;
+                reg = <0x0924>;
+                ti,max-div = <2>;
+        };
+
+        emu_mpu_alwon_ck: emu_mpu_alwon_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l3_ick: l3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        l4_ick: l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_ick>;
+                ti,bit-shift = <2>;
+                ti,max-div = <3>;
+                reg = <0x0a40>;
+                ti,index-starts-at-one;
+        };
+
+        rm_ick: rm_ick {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_ick>;
+                ti,bit-shift = <1>;
+                ti,max-div = <3>;
+                reg = <0x0c40>;
+                ti,index-starts-at-one;
+        };
+
+        gpt10_gate_fck: gpt10_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0a00>;
+        };
+
+        gpt10_mux_fck: gpt10_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0a40>;
+        };
+
+        gpt10_fck: gpt10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+        };
+
+        gpt11_gate_fck: gpt11_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0a00>;
+        };
+
+        gpt11_mux_fck: gpt11_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0a40>;
+        };
+
+        gpt11_fck: gpt11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+        };
+
+        core_96m_fck: core_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_fck: mmchs2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_fck: mmchs1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <24>;
+        };
+
+        i2c3_fck: i2c3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_fck: i2c2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_fck: i2c1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_96m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <15>;
+        };
+
+        mcbsp5_gate_fck: mcbsp5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <10>;
+                reg = <0x0a00>;
+        };
+
+        mcbsp1_gate_fck: mcbsp1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <9>;
+                reg = <0x0a00>;
+        };
+
+        core_48m_fck: core_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mcspi4_fck: mcspi4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_fck: mcspi3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_fck: mcspi2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_fck: mcspi1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <18>;
+        };
+
+        uart2_fck: uart2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_fck: uart1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_48m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <13>;
+        };
+
+        core_12m_fck: core_12m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_12m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        hdq_fck: hdq_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_12m_fck>;
+                reg = <0x0a00>;
+                ti,bit-shift = <22>;
+        };
+
+        core_l3_ick: core_l3_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        sdrc_ick: sdrc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_l3_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpmc_fck: gpmc_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_l3_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        core_l4_ick: core_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        mmchs2_ick: mmchs2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <25>;
+        };
+
+        mmchs1_ick: mmchs1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <24>;
+        };
+
+        hdq_ick: hdq_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <22>;
+        };
+
+        mcspi4_ick: mcspi4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <21>;
+        };
+
+        mcspi3_ick: mcspi3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <20>;
+        };
+
+        mcspi2_ick: mcspi2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <19>;
+        };
+
+        mcspi1_ick: mcspi1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <18>;
+        };
+
+        i2c3_ick: i2c3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <17>;
+        };
+
+        i2c2_ick: i2c2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <16>;
+        };
+
+        i2c1_ick: i2c1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <15>;
+        };
+
+        uart2_ick: uart2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <14>;
+        };
+
+        uart1_ick: uart1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <13>;
+        };
+
+        gpt11_ick: gpt11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <12>;
+        };
+
+        gpt10_ick: gpt10_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <11>;
+        };
+
+        mcbsp5_ick: mcbsp5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <10>;
+        };
+
+        mcbsp1_ick: mcbsp1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <9>;
+        };
+
+        omapctrl_ick: omapctrl_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <6>;
+        };
+
+        dss_tv_fck: dss_tv_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_54m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss_96m_fck: dss_96m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&omap_96m_fck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <2>;
+        };
+
+        dss2_alwon_fck: dss2_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_ck>;
+                reg = <0x0e00>;
+                ti,bit-shift = <1>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        gpt1_gate_fck: gpt1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0c00>;
+        };
+
+        gpt1_mux_fck: gpt1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x0c40>;
+        };
+
+        gpt1_fck: gpt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+        };
+
+        aes2_ick: aes2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                ti,bit-shift = <28>;
+                reg = <0x0a10>;
+        };
+
+        wkup_32k_fck: wkup_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbck: gpio1_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <3>;
+        };
+
+        sha12_ick: sha12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l4_ick>;
+                reg = <0x0a10>;
+                ti,bit-shift = <27>;
+        };
+
+        wdt2_fck: wdt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&wkup_32k_fck>;
+                reg = <0x0c00>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt2_ick: wdt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <5>;
+        };
+
+        wdt1_ick: wdt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <4>;
+        };
+
+        gpio1_ick: gpio1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <3>;
+        };
+
+        omap_32ksync_ick: omap_32ksync_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <2>;
+        };
+
+        gpt12_ick: gpt12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <1>;
+        };
+
+        gpt1_ick: gpt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&wkup_l4_ick>;
+                reg = <0x0c10>;
+                ti,bit-shift = <0>;
+        };
+
+        per_96m_fck: per_96m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_96m_alwon_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        per_48m_fck: per_48m_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_48m_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        uart3_fck: uart3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_48m_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <11>;
+        };
+
+        gpt2_gate_fck: gpt2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1000>;
+        };
+
+        gpt2_mux_fck: gpt2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                reg = <0x1040>;
+        };
+
+        gpt2_fck: gpt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+        };
+
+        gpt3_gate_fck: gpt3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1000>;
+        };
+
+        gpt3_mux_fck: gpt3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1040>;
+        };
+
+        gpt3_fck: gpt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+        };
+
+        gpt4_gate_fck: gpt4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1000>;
+        };
+
+        gpt4_mux_fck: gpt4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1040>;
+        };
+
+        gpt4_fck: gpt4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+        };
+
+        gpt5_gate_fck: gpt5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1000>;
+        };
+
+        gpt5_mux_fck: gpt5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x1040>;
+        };
+
+        gpt5_fck: gpt5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+        };
+
+        gpt6_gate_fck: gpt6_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1000>;
+        };
+
+        gpt6_mux_fck: gpt6_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x1040>;
+        };
+
+        gpt6_fck: gpt6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+        };
+
+        gpt7_gate_fck: gpt7_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1000>;
+        };
+
+        gpt7_mux_fck: gpt7_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x1040>;
+        };
+
+        gpt7_fck: gpt7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+        };
+
+        gpt8_gate_fck: gpt8_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x1000>;
+        };
+
+        gpt8_mux_fck: gpt8_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x1040>;
+        };
+
+        gpt8_fck: gpt8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+        };
+
+        gpt9_gate_fck: gpt9_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1000>;
+        };
+
+        gpt9_mux_fck: gpt9_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&omap_32k_fck>, <&sys_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1040>;
+        };
+
+        gpt9_fck: gpt9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+        };
+
+        per_32k_alwon_fck: per_32k_alwon_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&omap_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_dbck: gpio6_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_dbck: gpio5_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_dbck: gpio4_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_dbck: gpio3_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_dbck: gpio2_dbck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_fck: wdt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&per_32k_alwon_fck>;
+                reg = <0x1000>;
+                ti,bit-shift = <12>;
+        };
+
+        per_l4_ick: per_l4_ick {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l4_ick>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio6_ick: gpio6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <17>;
+        };
+
+        gpio5_ick: gpio5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <16>;
+        };
+
+        gpio4_ick: gpio4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <15>;
+        };
+
+        gpio3_ick: gpio3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <14>;
+        };
+
+        gpio2_ick: gpio2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <13>;
+        };
+
+        wdt3_ick: wdt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <12>;
+        };
+
+        uart3_ick: uart3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <11>;
+        };
+
+        uart4_ick: uart4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <18>;
+        };
+
+        gpt9_ick: gpt9_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <10>;
+        };
+
+        gpt8_ick: gpt8_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <9>;
+        };
+
+        gpt7_ick: gpt7_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <8>;
+        };
+
+        gpt6_ick: gpt6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <7>;
+        };
+
+        gpt5_ick: gpt5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <6>;
+        };
+
+        gpt4_ick: gpt4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <5>;
+        };
+
+        gpt3_ick: gpt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <4>;
+        };
+
+        gpt2_ick: gpt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <3>;
+        };
+
+        mcbsp2_ick: mcbsp2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <0>;
+        };
+
+        mcbsp3_ick: mcbsp3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <1>;
+        };
+
+        mcbsp4_ick: mcbsp4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&per_l4_ick>;
+                reg = <0x1010>;
+                ti,bit-shift = <2>;
+        };
+
+        mcbsp2_gate_fck: mcbsp2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <0>;
+                reg = <0x1000>;
+        };
+
+        mcbsp3_gate_fck: mcbsp3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <1>;
+                reg = <0x1000>;
+        };
+
+        mcbsp4_gate_fck: mcbsp4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x1000>;
+        };
+
+        emu_src_mux_ck: emu_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                reg = <0x1140>;
+        };
+
+        emu_src_ck: emu_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&emu_src_mux_ck>;
+        };
+
+        pclk_fck: pclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        pclkx2_fck: pclkx2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        atclk_fck: atclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&emu_src_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <3>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        traceclk_src_fck: traceclk_src_fck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_ck>, <&emu_core_alwon_ck>, <&emu_per_alwon_ck>, <&emu_mpu_alwon_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x1140>;
+        };
+
+        traceclk_fck: traceclk_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&traceclk_src_fck>;
+                ti,bit-shift = <11>;
+                ti,max-div = <7>;
+                reg = <0x1140>;
+                ti,index-starts-at-one;
+        };
+
+        secure_32k_fck: secure_32k_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        gpt12_fck: gpt12_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wdt1_fck: wdt1_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&secure_32k_fck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+};
+
+&cm_clockdomains {
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&sdrc_ick>;
+        };
+
+        dpll3_clkdm: dpll3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll3_ck>;
+        };
+
+        dpll1_clkdm: dpll1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll1_ck>;
+        };
+
+        per_clkdm: per_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
+                         <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
+                         <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
+                         <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
+                         <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
+                         <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
+                         <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>;
+        };
+
+        emu_clkdm: emu_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&emu_src_ck>;
+        };
+
+        dpll4_clkdm: dpll4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll4_ck>;
+        };
+
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
+                         <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
+                         <&gpt1_ick>;
+        };
+
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_tv_fck>, <&dss_96m_fck>, <&dss2_alwon_fck>;
+        };
+
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
+                         <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
+                         <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
+                         <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
+                         <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
+                         <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
+                         <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
+                         <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
+                         <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index a1e05853afcd..d3f8a6e8ca20 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,6 +107,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                cm1: cm1@4a004000 {
+                        compatible = "ti,omap4-cm1";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm1_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm1_clockdomains: clockdomains {
+                        };
+                };
+
+                prm: prm@4a306000 {
+                        compatible = "ti,omap4-prm";
+                        reg = <0x4a306000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm2: cm2@4a008000 {
+                        compatible = "ti,omap4-cm2";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm2_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm2_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4a30a000 {
+                        compatible = "ti,omap4-scrm";
+                        reg = <0x4a30a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4a304000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4a304000 0x20>;
@@ -707,3 +759,5 @@
                 };
         };
 };
+
+/include/ "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap443x-clocks.dtsi b/arch/arm/boot/dts/omap443x-clocks.dtsi
new file mode 100644
index 000000000000..2bd2166f88d3
--- /dev/null
+++ b/arch/arm/boot/dts/omap443x-clocks.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        bandgap_fclk: bandgap_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap443x.dtsi b/arch/arm/boot/dts/omap443x.dtsi
index ab607a19a613..8c1cfad30d60 100644
--- a/arch/arm/boot/dts/omap443x.dtsi
+++ b/arch/arm/boot/dts/omap443x.dtsi
@@ -44,3 +44,5 @@
                 };
         };
 };
+
+/include/ "omap443x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap4460.dtsi b/arch/arm/boot/dts/omap4460.dtsi
index 11566bed0035..6b32f520741a 100644
--- a/arch/arm/boot/dts/omap4460.dtsi
+++ b/arch/arm/boot/dts/omap4460.dtsi
@@ -52,3 +52,5 @@
                 };
         };
 };
+
+/include/ "omap446x-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap446x-clocks.dtsi b/arch/arm/boot/dts/omap446x-clocks.dtsi
new file mode 100644
index 000000000000..be033e9803e9
--- /dev/null
+++ b/arch/arm/boot/dts/omap446x-clocks.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prm_clocks {
+        div_ts_ck: div_ts_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1888>;
+                ti,dividers = <8>, <16>, <32>;
+        };
+
+        bandgap_ts_fclk: bandgap_ts_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&div_ts_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1888>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
new file mode 100644
index 000000000000..c821ff5e9b8d
--- /dev/null
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -0,0 +1,1651 @@
+/*
+ * Device Tree Source for OMAP4 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm1_clocks {
+        extalt_clkin_ck: extalt_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <59000000>;
+        };
+
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        tie_low_clock_ck: tie_low_clock_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+
+        utmi_phy_clkout_ck: utmi_phy_clkout_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60motg_ck: xclk60motg_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+                reg = <0x01f0>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x012c>;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_m6x2_ck: dpll_core_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ddrphy_ck: ddrphy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_m5x2_ck: dpll_core_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        div_core_ck: div_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        div_iva_hs_clk: div_iva_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x01dc>;
+                ti,index-power-of-two;
+        };
+
+        div_mpu_hs_clk: div_mpu_hs_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_m5x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x019c>;
+                ti,index-power-of-two;
+        };
+
+        dpll_core_m4x2_ck: dpll_core_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dll_clk_div_ck: dll_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_m4x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_abe_m2_ck: dpll_abe_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_ck>;
+                ti,max-div = <31>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0134>;
+        };
+
+        dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
+        };
+
+        dpll_core_m7x2_ck: dpll_core_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
+                ti,bit-shift = <23>;
+                reg = <0x01ac>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_m4x2_ck: dpll_iva_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_m5x2_ck: dpll_iva_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_hs_clk_div_ck: per_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_hs_clk_div_ck: usb_hs_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_div_ck: l3_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&div_core_ck>;
+                ti,bit-shift = <4>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        l4_div_ck: l4_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <8>;
+                ti,max-div = <2>;
+                reg = <0x0100>;
+        };
+
+        lp_clk_div_ck: lp_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        mpu_periphclk: mpu_periphclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_mpu_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        ocp_abe_iclk: ocp_abe_iclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&aess_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x0528>;
+                ti,dividers = <2>, <1>;
+        };
+
+        per_abe_24m_fclk: per_abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0538>;
+        };
+
+        func_dmic_abe_gfclk: func_dmic_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0540>;
+        };
+
+        func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0548>;
+        };
+
+        func_mcbsp1_gfclk: func_mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0550>;
+        };
+
+        func_mcbsp2_gfclk: func_mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
+                ti,bit-shift = <25>;
+                reg = <0x0558>;
+        };
+
+        func_mcbsp3_gfclk: func_mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        slimbus1_fclk_1: slimbus1_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24m_clk>;
+                ti,bit-shift = <9>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_0: slimbus1_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&abe_24m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_fclk_2: slimbus1_fclk_2 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0560>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        timer5_sync_mux: timer5_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_sync_mux: timer6_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_sync_mux: timer7_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_sync_mux: timer8_sync_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin_ck: sys_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        dbgclk_mux_ck: dbgclk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
+                reg = <0x0108>;
+        };
+
+        syc_clk_div_ck: syc_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkin_ck>;
+                reg = <0x0100>;
+                ti,max-div = <2>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1838>;
+        };
+
+        dmt1_clk_mux: dmt1_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1840>;
+        };
+
+        usim_ck: usim_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1858>;
+                ti,dividers = <14>, <18>;
+        };
+
+        usim_fclk: usim_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&usim_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1858>;
+        };
+
+        pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x1a20>;
+        };
+
+        pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x1a20>;
+        };
+
+        stm_clk_div_ck: stm_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_stm_clock_mux_ck>;
+                ti,bit-shift = <27>;
+                ti,max-div = <64>;
+                reg = <0x1a20>;
+                ti,index-power-of-two;
+        };
+
+        trace_clk_div_div_ck: trace_clk_div_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&pmd_trace_clk_mux_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1a20>;
+                ti,dividers = <0>, <1>, <2>, <0>, <4>;
+        };
+
+        trace_clk_div_ck: trace_clk_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,clkdm-gate-clock";
+                clocks = <&trace_clk_div_div_ck>;
+        };
+};
+
+&prm_clockdomains {
+        emu_sys_clkdm: emu_sys_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&trace_clk_div_ck>;
+        };
+};
+
+&cm2_clocks {
+        per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x014c>;
+        };
+
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+                reg = <0x0150>;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0154>;
+        };
+
+        dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
+        };
+
+        dpll_per_m4x2_ck: dpll_per_m4x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m5x2_ck: dpll_per_m5x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m6x2_ck: dpll_per_m6x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0160>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m7x2_ck: dpll_per_m7x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b4>;
+                ti,clock-mult = <1>;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        ducati_clk_mux_ck: ducati_clk_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
+                reg = <0x0100>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_24mc_fclk: func_24mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <4>, <8>;
+        };
+
+        func_48mc_fclk: func_48mc_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_64m_fclk: func_64m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                reg = <0x0108>;
+                ti,dividers = <2>, <4>;
+        };
+
+        init_60m_fclk: init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        per_abe_nc_fclk: per_abe_nc_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2_ck>;
+                reg = <0x0108>;
+                ti,max-div = <2>;
+        };
+
+        aes1_fck: aes1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a0>;
+        };
+
+        aes2_fck: aes2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15a8>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&syc_clk_div_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1120>;
+        };
+
+        dss_tv_clk: dss_tv_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&extalt_clkin_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1120>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m5x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1120>;
+                ti,set-rate-parent;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1120>;
+        };
+
+        dss_fck: dss_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x1120>;
+        };
+
+        fdif_fck: fdif_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m4x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1028>;
+                ti,index-power-of-two;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1460>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1468>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1470>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1478>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1480>;
+        };
+
+        sgx_clk_mux: sgx_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1220>;
+        };
+
+        hsi_fck: hsi_fck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <4>;
+                reg = <0x1338>;
+                ti,index-power-of-two;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1020>;
+        };
+
+        mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
+                ti,bit-shift = <25>;
+                reg = <0x14e0>;
+        };
+
+        per_mcbsp4_gfclk: per_mcbsp4_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x14e0>;
+        };
+
+        hsmmc1_fclk: hsmmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1328>;
+        };
+
+        hsmmc2_fclk: hsmmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_64m_fclk>, <&func_96m_fclk>;
+                ti,bit-shift = <24>;
+                reg = <0x1330>;
+        };
+
+        ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x13e0>;
+        };
+
+        sha2md5_fck: sha2md5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x15c8>;
+        };
+
+        slimbus2_fclk_1: slimbus2_fclk_1 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&per_abe_24m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_fclk_0: slimbus2_fclk_0 {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_24mc_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1538>;
+        };
+
+        slimbus2_slimbus_clk: slimbus2_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_slimbus_core_clks_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x1538>;
+        };
+
+        smartreflex_core_fck: smartreflex_core_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0638>;
+        };
+
+        smartreflex_iva_fck: smartreflex_iva_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0630>;
+        };
+
+        smartreflex_mpu_fck: smartreflex_mpu_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_wkup_clk_mux_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0628>;
+        };
+
+        cm2_dm10_mux: cm2_dm10_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1428>;
+        };
+
+        cm2_dm11_mux: cm2_dm11_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1430>;
+        };
+
+        cm2_dm2_mux: cm2_dm2_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1438>;
+        };
+
+        cm2_dm3_mux: cm2_dm3_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1440>;
+        };
+
+        cm2_dm4_mux: cm2_dm4_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1448>;
+        };
+
+        cm2_dm9_mux: cm2_dm9_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1450>;
+        };
+
+        usb_host_fs_fck: usb_host_fs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x13d0>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1358>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_func48mclk: usb_host_hs_func48mclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48mc_fclk>;
+                ti,bit-shift = <15>;
+                reg = <0x1358>;
+        };
+
+        usb_host_hs_fck: usb_host_hs_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <1>;
+                reg = <0x1358>;
+        };
+
+        otg_60m_gfclk: otg_60m_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_xclk: usb_otg_hs_xclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&otg_60m_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1360>;
+        };
+
+        usb_otg_hs_ick: usb_otg_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1360>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1368>;
+        };
+
+        usb_tll_hs_ick: usb_tll_hs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l4_div_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x1368>;
+        };
+};
+
+&cm2_clockdomains {
+        l3_init_clkdm: l3_init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclk5_src_gate_ck: auxclk5_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_mux_ck: auxclk5_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0324>;
+        };
+
+        auxclk5_src_ck: auxclk5_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
+        };
+
+        auxclk5_ck: auxclk5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk5_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0324>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+
+        auxclkreq4_ck: auxclkreq4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0220>;
+        };
+
+        auxclkreq5_ck: auxclkreq5_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0224>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index ab9a21ae82f3..a72813a9663e 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -117,6 +117,58 @@
                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 
+                prm: prm@4ae06000 {
+                        compatible = "ti,omap5-prm";
+                        reg = <0x4ae06000 0x3000>;
+
+                        prm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        prm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core_aon: cm_core_aon@4a004000 {
+                        compatible = "ti,omap5-cm-core-aon";
+                        reg = <0x4a004000 0x2000>;
+
+                        cm_core_aon_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_aon_clockdomains: clockdomains {
+                        };
+                };
+
+                scrm: scrm@4ae0a000 {
+                        compatible = "ti,omap5-scrm";
+                        reg = <0x4ae0a000 0x2000>;
+
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
+
+                cm_core: cm_core@4a008000 {
+                        compatible = "ti,omap5-cm-core";
+                        reg = <0x4a008000 0x3000>;
+
+                        cm_core_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+
+                        cm_core_clockdomains: clockdomains {
+                        };
+                };
+
                 counter32k: counter@4ae04000 {
                         compatible = "ti,omap-counter32k";
                         reg = <0x4ae04000 0x40>;
@@ -751,3 +803,5 @@
                 };
         };
 };
+
+/include/ "omap54xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
new file mode 100644
index 000000000000..d487fdab3921
--- /dev/null
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -0,0 +1,1399 @@
+/*
+ * Device Tree Source for OMAP5 clock data
+ *
+ * Copyright (C) 2013 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&cm_core_aon_clocks {
+        pad_clks_src_ck: pad_clks_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        pad_clks_ck: pad_clks_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&pad_clks_src_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0108>;
+        };
+
+        secure_32k_clk_src_ck: secure_32k_clk_src_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        slimbus_src_clk: slimbus_src_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        slimbus_clk: slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_src_clk>;
+                ti,bit-shift = <10>;
+                reg = <0x0108>;
+        };
+
+        sys_32k_ck: sys_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+
+        virt_12000000_ck: virt_12000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+
+        virt_13000000_ck: virt_13000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+
+        virt_16800000_ck: virt_16800000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <16800000>;
+        };
+
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+
+        virt_26000000_ck: virt_26000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+
+        virt_27000000_ck: virt_27000000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <27000000>;
+        };
+
+        virt_38400000_ck: virt_38400000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <38400000>;
+        };
+
+        xclk60mhsp1_ck: xclk60mhsp1_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        xclk60mhsp2_ck: xclk60mhsp2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <60000000>;
+        };
+
+        dpll_abe_ck: dpll_abe_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-m4xen-clock";
+                clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
+                reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
+        };
+
+        dpll_abe_x2_ck: dpll_abe_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_abe_ck>;
+        };
+
+        dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        abe_24m_fclk: abe_24m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+
+        abe_clk: abe_clk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                ti,max-div = <4>;
+                reg = <0x0108>;
+                ti,index-power-of-two;
+        };
+
+        abe_iclk: abe_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&abe_clk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        abe_lp_clk_div: abe_lp_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_abe_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01f4>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_ck: dpll_core_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-core-clock";
+                clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
+                reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
+        };
+
+        dpll_core_x2_ck: dpll_core_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_core_ck>;
+        };
+
+        dpll_core_h21x2_ck: dpll_core_h21x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        c2c_fclk: c2c_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h21x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        c2c_iclk: c2c_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&c2c_fclk>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dpll_core_h11x2_ck: dpll_core_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0138>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x013c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0144>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m2_ck: dpll_core_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0130>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_core_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0134>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_iva_ck: dpll_iva_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
+                reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
+        };
+
+        dpll_iva_x2_ck: dpll_iva_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_iva_ck>;
+        };
+
+        dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01b8>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_iva_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01bc>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_mpu_ck: dpll_mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
+                reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
+        };
+
+        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_mpu_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0170>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_abe_m3x2_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+
+        l3_iclk_div: l3_iclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_core_h12x2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpu_l3_iclk: gpu_l3_iclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        l4_root_clk_div: l4_root_clk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&l3_iclk_div>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&slimbus_clk>;
+                ti,bit-shift = <11>;
+                reg = <0x0560>;
+        };
+
+        aess_fclk: aess_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&abe_clk>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x0528>;
+        };
+
+        dmic_sync_mux_ck: dmic_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0538>;
+        };
+
+        dmic_gfclk: dmic_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0538>;
+        };
+
+        mcasp_sync_mux_ck: mcasp_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0540>;
+        };
+
+        mcasp_gfclk: mcasp_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0540>;
+        };
+
+        mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0548>;
+        };
+
+        mcbsp1_gfclk: mcbsp1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0548>;
+        };
+
+        mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0550>;
+        };
+
+        mcbsp2_gfclk: mcbsp2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0550>;
+        };
+
+        mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
+                ti,bit-shift = <26>;
+                reg = <0x0558>;
+        };
+
+        mcbsp3_gfclk: mcbsp3_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
+                ti,bit-shift = <24>;
+                reg = <0x0558>;
+        };
+
+        timer5_gfclk_mux: timer5_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0568>;
+        };
+
+        timer6_gfclk_mux: timer6_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0570>;
+        };
+
+        timer7_gfclk_mux: timer7_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0578>;
+        };
+
+        timer8_gfclk_mux: timer8_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0580>;
+        };
+
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+};
+&prm_clocks {
+        sys_clkin: sys_clkin {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
+                reg = <0x0110>;
+                ti,index-starts-at-one;
+        };
+
+        abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x0108>;
+        };
+
+        abe_dpll_clk_mux: abe_dpll_clk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                reg = <0x010c>;
+        };
+
+        custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        dss_syc_gfclk_div: dss_syc_gfclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        wkupaon_iclk_mux: wkupaon_iclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&abe_lp_clk_div>;
+                reg = <0x0108>;
+        };
+
+        l3instr_ts_gclk_div: l3instr_ts_gclk_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&wkupaon_iclk_mux>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        gpio1_dbclk: gpio1_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1938>;
+        };
+
+        timer1_gfclk_mux: timer1_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1940>;
+        };
+};
+&cm_core_clocks {
+        dpll_per_ck: dpll_per_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
+                reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
+        };
+
+        dpll_per_x2_ck: dpll_per_x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-x2-clock";
+                clocks = <&dpll_per_ck>;
+        };
+
+        dpll_per_h11x2_ck: dpll_per_h11x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0158>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x015c>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <63>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0164>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2_ck: dpll_per_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0150>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_x2_ck>;
+                ti,max-div = <31>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0154>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro1_ck: dpll_unipro1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
+        };
+
+        dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro1_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro1_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0210>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_unipro2_ck: dpll_unipro2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-clock";
+                clocks = <&sys_clkin>, <&sys_clkin>;
+                reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
+        };
+
+        dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_unipro2_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_unipro2_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x01d0>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        dpll_usb_ck: dpll_usb_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap4-dpll-j-type-clock";
+                clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
+                reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
+        };
+
+        dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_usb_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
+        dpll_usb_m2_ck: dpll_usb_m2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_ck>;
+                ti,max-div = <127>;
+                ti,autoidle-shift = <8>;
+                reg = <0x0190>;
+                ti,index-starts-at-one;
+                ti,invert-autoidle-bit;
+        };
+
+        func_128m_clk: func_128m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        func_12m_fclk: func_12m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+
+        func_24m_clk: func_24m_clk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_48m_fclk: func_48m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+
+        func_96m_fclk: func_96m_fclk {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+
+        l3init_60m_fclk: l3init_60m_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                reg = <0x0104>;
+                ti,dividers = <1>, <8>;
+        };
+
+        dss_32khz_clk: dss_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x1420>;
+        };
+
+        dss_48mhz_clk: dss_48mhz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_48m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1420>;
+        };
+
+        dss_dss_clk: dss_dss_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_h12x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1420>;
+        };
+
+        dss_sys_clk: dss_sys_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dss_syc_gfclk_div>;
+                ti,bit-shift = <10>;
+                reg = <0x1420>;
+        };
+
+        gpio2_dbclk: gpio2_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1060>;
+        };
+
+        gpio3_dbclk: gpio3_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1068>;
+        };
+
+        gpio4_dbclk: gpio4_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1070>;
+        };
+
+        gpio5_dbclk: gpio5_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1078>;
+        };
+
+        gpio6_dbclk: gpio6_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1080>;
+        };
+
+        gpio7_dbclk: gpio7_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1110>;
+        };
+
+        gpio8_dbclk: gpio8_dbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1118>;
+        };
+
+        iss_ctrlclk: iss_ctrlclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1320>;
+        };
+
+        lli_txphy_clk: lli_txphy_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x0f20>;
+        };
+
+        lli_txphy_ls_clk: lli_txphy_ls_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_unipro1_m2_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0f20>;
+        };
+
+        mmc1_32khz_clk: mmc1_32khz_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x1628>;
+        };
+
+        sata_ref_clk: sata_ref_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_clkin>;
+                ti,bit-shift = <8>;
+                reg = <0x1688>;
+        };
+
+        usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_m2_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <11>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <12>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <6>;
+                reg = <0x1658>;
+        };
+
+        utmi_p1_gfclk: utmi_p1_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p1_gfclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1658>;
+        };
+
+        utmi_p2_gfclk: utmi_p2_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&utmi_p2_gfclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1658>;
+        };
+
+        usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1658>;
+        };
+
+        usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x16f0>;
+        };
+
+        usb_phy_cm_clk32k: usb_phy_cm_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&sys_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0640>;
+        };
+
+        usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <8>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <9>;
+                reg = <0x1668>;
+        };
+
+        usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&l3init_60m_fclk>;
+                ti,bit-shift = <10>;
+                reg = <0x1668>;
+        };
+
+        fdif_fclk: fdif_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_h11x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1328>;
+        };
+
+        gpu_core_gclk_mux: gpu_core_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1520>;
+        };
+
+        gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x1520>;
+        };
+
+        hsi_fclk: hsi_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                ti,max-div = <2>;
+                reg = <0x1638>;
+        };
+
+        mmc1_fclk_mux: mmc1_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1628>;
+        };
+
+        mmc1_fclk: mmc1_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc1_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1628>;
+        };
+
+        mmc2_fclk_mux: mmc2_fclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1630>;
+        };
+
+        mmc2_fclk: mmc2_fclk {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&mmc2_fclk_mux>;
+                ti,bit-shift = <25>;
+                ti,max-div = <2>;
+                reg = <0x1630>;
+        };
+
+        timer10_gfclk_mux: timer10_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1028>;
+        };
+
+        timer11_gfclk_mux: timer11_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1030>;
+        };
+
+        timer2_gfclk_mux: timer2_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1038>;
+        };
+
+        timer3_gfclk_mux: timer3_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1040>;
+        };
+
+        timer4_gfclk_mux: timer4_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1048>;
+        };
+
+        timer9_gfclk_mux: timer9_gfclk_mux {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&sys_clkin>, <&sys_32k_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x1050>;
+        };
+};
+
+&cm_core_clockdomains {
+        l3init_clkdm: l3init_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_usb_ck>;
+        };
+};
+
+&scrm_clocks {
+        auxclk0_src_gate_ck: auxclk0_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_mux_ck: auxclk0_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0310>;
+        };
+
+        auxclk0_src_ck: auxclk0_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
+        };
+
+        auxclk0_ck: auxclk0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk0_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0310>;
+        };
+
+        auxclk1_src_gate_ck: auxclk1_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_mux_ck: auxclk1_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0314>;
+        };
+
+        auxclk1_src_ck: auxclk1_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
+        };
+
+        auxclk1_ck: auxclk1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk1_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0314>;
+        };
+
+        auxclk2_src_gate_ck: auxclk2_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_mux_ck: auxclk2_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0318>;
+        };
+
+        auxclk2_src_ck: auxclk2_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
+        };
+
+        auxclk2_ck: auxclk2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk2_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0318>;
+        };
+
+        auxclk3_src_gate_ck: auxclk3_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_mux_ck: auxclk3_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x031c>;
+        };
+
+        auxclk3_src_ck: auxclk3_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
+        };
+
+        auxclk3_ck: auxclk3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk3_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x031c>;
+        };
+
+        auxclk4_src_gate_ck: auxclk4_src_gate_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&dpll_core_m3x2_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_mux_ck: auxclk4_src_mux_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0320>;
+        };
+
+        auxclk4_src_ck: auxclk4_src_ck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
+        };
+
+        auxclk4_ck: auxclk4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&auxclk4_src_ck>;
+                ti,bit-shift = <16>;
+                ti,max-div = <16>;
+                reg = <0x0320>;
+        };
+
+        auxclkreq0_ck: auxclkreq0_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0210>;
+        };
+
+        auxclkreq1_ck: auxclkreq1_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+
+        auxclkreq2_ck: auxclkreq2_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0218>;
+        };
+
+        auxclkreq3_ck: auxclkreq3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+};
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4191ae08f4c8..653b489479e0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -76,6 +76,16 @@ config SOC_AM43XX
         select ARM_GIC
         select MACH_OMAP_GENERIC
 
+config SOC_DRA7XX
+        bool "TI DRA7XX"
+        depends on ARCH_MULTI_V7
+        select ARCH_OMAP2PLUS
+        select ARM_CPU_SUSPEND if PM
+        select ARM_GIC
+        select CPU_V7
+        select HAVE_SMP
+        select HAVE_ARM_ARCH_TIMER
+
 config ARCH_OMAP2PLUS
         bool
         select ARCH_HAS_BANDGAP
@@ -128,14 +138,6 @@ config SOC_HAS_REALTIME_COUNTER
         depends on SOC_OMAP5 || SOC_DRA7XX
         default y
 
-config SOC_DRA7XX
-        bool "TI DRA7XX"
-        select ARM_ARCH_TIMER
-        select CPU_V7
-        select ARM_GIC
-        select HAVE_SMP
-        select COMMON_CLK
-
 comment "OMAP Core Type"
         depends on ARCH_OMAP2
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f78b177e8f4f..e6eec6f72fd3 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_SOC_AM33XX)		+= $(voltagedomain-common)
 obj-$(CONFIG_SOC_AM43XX)                += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                 += $(voltagedomain-common)
 obj-$(CONFIG_SOC_OMAP5)                += voltagedomains54xx_data.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(voltagedomain-common)
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -184,12 +185,14 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clock34xx.o clkt34xx_dpll3m2.o
 obj-$(CONFIG_ARCH_OMAP3)                += clock3517.o clock36xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += dpll3xxx.o cclock3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) cclock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common)
 obj-$(CONFIG_ARCH_OMAP4)                += dpll3xxx.o dpll44xx.o
 obj-$(CONFIG_SOC_AM33XX)                += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX)                += cclock33xx_data.o
 obj-$(CONFIG_SOC_OMAP5)                 += $(clock-common)
 obj-$(CONFIG_SOC_OMAP5)                 += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_DRA7XX)                += $(clock-common)
+obj-$(CONFIG_SOC_DRA7XX)                += dpll3xxx.o dpll44xx.o
+obj-$(CONFIG_SOC_AM43XX)                += $(clock-common) dpll3xxx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
deleted file mode 100644
index 865d30ee812f..000000000000
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ /dev/null
@@ -1,1064 +0,0 @@
-/*
- * AM33XX Clock data
- *
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
- * Vaibhav Hiremath <hvaibhav@ti.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "am33xx.h"
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "control.h"
-#include "cm.h"
-#include "cm33xx.h"
-#include "cm-regbits-33xx.h"
-#include "prm.h"
-
-/* Modulemode control */
-#define AM33XX_MODULEMODE_HWCTRL_SHIFT          0
-#define AM33XX_MODULEMODE_SWCTRL_SHIFT          1
-
-/*LIST_HEAD(clocks);*/
-
-/* Root clocks */
-
-/* RTC 32k */
-DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
-
-/* On-Chip 32KHz RC OSC */
-DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
-
-/* Crystal input clks */
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-/* Oscillator clock */
-/* 19.2, 24, 25 or 26 MHz */
-static const char *sys_clkin_ck_parents[] = {
-        "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
-        "virt_26000000_ck",
-};
-
-/*
- * sys_clk in: input to the dpll and also used as funtional clock for,
- *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
- *
- */
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-               AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
-               AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
-               AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
-               0, NULL);
-
-/* External clock - 12 MHz */
-DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKDCOLDO output */
-static const char *dpll_core_ck_parents[] = {
-        "sys_clkin_ck",
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_core_ck,
-        },
-        .dpll_data      = &dpll_core_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-        "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static const struct clk_ops dpll_x2_ck_ops = {
-        .recalc_rate    = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_core_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-                   NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
-                   0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
-                   AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
-                   AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_mpu_ck;
-
-static const struct clk_ops dpll_mpu_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-        .hw = {
-                .clk    = &dpll_mpu_ck,
-        },
-        .dpll_data      = &dpll_mpu_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
-                   0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_DDR */
-static struct dpll_data dpll_ddr_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_ddr_ck;
-
-static const struct clk_ops dpll_ddr_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk_hw_omap dpll_ddr_ck_hw = {
-        .hw = {
-                .clk    = &dpll_ddr_ck,
-        },
-        .dpll_data      = &dpll_ddr_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
-                   0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
-                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* emif_fck functional clock */
-DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
-                        0x0, 1, 2);
-
-/* DPLL_DISP */
-static struct dpll_data dpll_disp_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
-        .mult_mask      = AM33XX_DPLL_MULT_MASK,
-        .div1_mask      = AM33XX_DPLL_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-/* CLKOUT: fdpll/M2 */
-static struct clk dpll_disp_ck;
-
-static struct clk_hw_omap dpll_disp_ck_hw = {
-        .hw = {
-                .clk    = &dpll_disp_ck,
-        },
-        .dpll_data      = &dpll_disp_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/*
- * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
- * and ALT_CLK1/2)
- */
-DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
-                   CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
-                   AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
-                   CLK_DIVIDER_ONE_BASED, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
-        .clk_bypass     = &sys_clkin_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
-        .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
-        .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
-        .enable_mask    = AM33XX_DPLL_EN_MASK,
-        .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-        .flags          = DPLL_J_TYPE,
-};
-
-/* CLKDCOLDO */
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-        .hw     = {
-                .clk    = &dpll_per_ck,
-        },
-        .dpll_data      = &dpll_per_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
-
-/* CLKOUT: fdpll/M2 */
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                   AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
-                   AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
-                   NULL);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
-                        &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
-                        &dpll_per_m2_ck, 0x0, 1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
-                        &dpll_core_m4_ck, 0x0, 1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                        1, 2);
-
-DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
-                        8);
-
-/*
- * Below clock nodes describes clockdomains derived out
- * of core clock.
- */
-static const struct clk_ops clk_ops_null = {
-};
-
-static const char *l3_gclk_parents[] = {
-        "dpll_core_m4_ck"
-};
-
-static struct clk l3_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
-DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
-
-static struct clk l4hs_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
-DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
-
-static const char *l3s_gclk_parents[] = {
-        "dpll_core_m4_div2_ck"
-};
-
-static struct clk l3s_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
-DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4fw_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
-DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk l4ls_gclk;
-DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
-DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
-
-static struct clk sysclk_div_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
-DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
-
-/*
- * In order to match the clock domain with hwmod clockdomain entry,
- * separate clock nodes is required for the modules which are
- * directly getting their funtioncal clock from sys_clkin.
- */
-static struct clk adc_tsc_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
-DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
-DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk dcan1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
-DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk mcasp1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
-DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk smartreflex1_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
-DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk sha0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
-DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk aes0_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
-DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
-
-static struct clk rng_fck;
-DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
-DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
-
-/*
- * Modules clock nodes
- *
- * The following clock leaf nodes are added for the moment because:
- *
- *  - hwmod data is not present for these modules, either hwmod
- *    control is not required or its not populated.
- *  - Driver code is not yet migrated to use hwmod/runtime pm
- *  - Modules outside kernel access (to disable them by default)
- *
- *     - mmu (gfx domain)
- *     - cefuse
- *     - usbotg_fck (its additional clock and not really a modulemode)
- *     - ieee5000
- */
-
-DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
-                AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-/*
- * clkdiv32 is generated from fixed division of 732.4219
- */
-DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
-
-static struct clk clkdiv32k_ick;
-
-static const char *clkdiv32k_ick_parent_names[] = {
-        "clkdiv32k_ck",
-};
-
-static const struct clk_ops clkdiv32k_ick_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap clkdiv32k_ick_hw = {
-        .hw     = {
-                .clk    = &clkdiv32k_ick,
-        },
-        .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
-        .enable_bit     = AM33XX_MODULEMODE_SWCTRL_SHIFT,
-        .clkdm_name     = "clk_24mhz_clkdm",
-};
-
-DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
-
-/* "usbotg_fck" is an additional clock and not really a modulemode */
-DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
-                0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
-                AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-/* Timers */
-static const struct clksel timer1_clkmux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = &tclkin_ck, .rates = div_1_2_rates },
-        { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-
-static const char *timer1_ck_parents[] = {
-        "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
-        "clk_32768_ck",
-};
-
-static struct clk timer1_fck;
-
-static const struct clk_ops timer1_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap timer1_fck_hw = {
-        .hw     = {
-                .clk    = &timer1_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer1_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
-
-static const struct clksel timer2_to_7_clk_sel[] = {
-        { .parent = &tclkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *timer2_to_7_ck_parents[] = {
-        "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
-};
-
-static struct clk timer2_fck;
-
-static struct clk_hw_omap timer2_fck_hw = {
-        .hw     = {
-                .clk    = &timer2_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer3_fck;
-
-static struct clk_hw_omap timer3_fck_hw = {
-        .hw     = {
-                .clk    = &timer3_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer4_fck;
-
-static struct clk_hw_omap timer4_fck_hw = {
-        .hw     = {
-                .clk    = &timer4_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer5_fck;
-
-static struct clk_hw_omap timer5_fck_hw = {
-        .hw     = {
-                .clk    = &timer5_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer6_fck;
-
-static struct clk_hw_omap timer6_fck_hw = {
-        .hw     = {
-                .clk    = &timer6_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-static struct clk timer7_fck;
-
-static struct clk_hw_omap timer7_fck_hw = {
-        .hw     = {
-                .clk    = &timer7_fck,
-        },
-        .clkdm_name     = "l4ls_clkdm",
-        .clksel         = timer2_to_7_clk_sel,
-        .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
-                        "dpll_core_m5_ck",
-                        &dpll_core_m5_ck,
-                        0x0,
-                        1, 2);
-
-static const struct clk_ops cpsw_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-};
-
-static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
-        { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *cpsw_cpts_rft_ck_parents[] = {
-        "dpll_core_m5_ck", "dpll_core_m4_ck",
-};
-
-static struct clk cpsw_cpts_rft_clk;
-
-static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
-        .hw     = {
-                .clk    = &cpsw_cpts_rft_clk,
-        },
-        .clkdm_name     = "cpsw_125mhz_clkdm",
-        .clksel         = cpsw_cpts_rft_clkmux_sel,
-        .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
-
-
-/* gpio */
-static const char *gpio0_ck_parents[] = {
-        "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel gpio0_dbclk_mux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clk_32768_ck, .rates = div_1_1_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const struct clk_ops gpio_fck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk gpio0_dbclk_mux_ck;
-
-static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
-        .hw     = {
-                .clk    = &gpio0_dbclk_mux_ck,
-        },
-        .clkdm_name     = "l4_wkup_clkdm",
-        .clksel         = gpio0_dbclk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
-
-DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
-                AM33XX_CM_WKUP_GPIO0_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO1_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO2_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
-                AM33XX_CM_PER_GPIO3_CLKCTRL,
-                AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
-
-
-static const char *pruss_ck_parents[] = {
-        "l3_gclk", "dpll_disp_m2_ck",
-};
-
-static const struct clksel pruss_ocp_clk_mux_sel[] = {
-        { .parent = &l3_gclk, .rates = div_1_0_rates },
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk pruss_ocp_gclk;
-
-static struct clk_hw_omap pruss_ocp_gclk_hw = {
-        .hw     = {
-                .clk    = &pruss_ocp_gclk,
-        },
-        .clkdm_name     = "pruss_ocp_clkdm",
-        .clksel         = pruss_ocp_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
-};
-
-DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
-
-static const char *lcd_ck_parents[] = {
-        "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel lcd_clk_mux_sel[] = {
-        { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static struct clk lcd_gclk;
-
-static struct clk_hw_omap lcd_gclk_hw = {
-        .hw     = {
-                .clk    = &lcd_gclk,
-        },
-        .clkdm_name     = "lcdc_clkdm",
-        .clksel         = lcd_clk_mux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
-                        gpio_fck_ops, CLK_SET_RATE_PARENT);
-
-DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
-
-static const char *gfx_ck_parents[] = {
-        "dpll_core_m4_ck", "dpll_per_m2_ck",
-};
-
-static const struct clksel gfx_clksel_sel[] = {
-        { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk gfx_fclk_clksel_ck;
-
-static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
-        .hw     = {
-                .clk    = &gfx_fclk_clksel_ck,
-        },
-        .clksel         = gfx_clksel_sel,
-        .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
-        .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
-
-static const struct clk_div_table div_1_0_2_1_rates[] = {
-        { .div = 1, .val = 0, },
-        { .div = 2, .val = 1, },
-        { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
-                         &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
-                         AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
-                         0x0, div_1_0_2_1_rates, NULL);
-
-static const char *sysclkout_ck_parents[] = {
-        "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
-        "lcd_gclk",
-};
-
-static const struct clksel sysclkout_pre_sel[] = {
-        { .parent = &clk_32768_ck, .rates = div_1_0_rates },
-        { .parent = &l3_gclk, .rates = div_1_1_rates },
-        { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
-        { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
-        { .parent = &lcd_gclk, .rates = div_1_4_rates },
-        { .parent = NULL },
-};
-
-static struct clk sysclkout_pre_ck;
-
-static struct clk_hw_omap sysclkout_pre_ck_hw = {
-        .hw     = {
-                .clk    = &sysclkout_pre_ck,
-        },
-        .clksel         = sysclkout_pre_sel,
-        .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
-        .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
-};
-
-DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
-
-/* Divide by 8 clock rates with default clock is 1/1*/
-static const struct clk_div_table div8_rates[] = {
-        { .div = 1, .val = 0, },
-        { .div = 2, .val = 1, },
-        { .div = 3, .val = 2, },
-        { .div = 4, .val = 3, },
-        { .div = 5, .val = 4, },
-        { .div = 6, .val = 5, },
-        { .div = 7, .val = 6, },
-        { .div = 8, .val = 7, },
-        { .div = 0 },
-};
-
-DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
-                         0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
-                         AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
-
-DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
-                AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
-
-static const char *wdt_ck_parents[] = {
-        "clk_rc32k_ck", "clkdiv32k_ick",
-};
-
-static const struct clksel wdt_clkmux_sel[] = {
-        { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
-        { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static struct clk wdt1_fck;
-
-static struct clk_hw_omap wdt1_fck_hw = {
-        .hw     = {
-                .clk    = &wdt1_fck,
-        },
-        .clkdm_name     = "l4_wkup_clkdm",
-        .clksel         = wdt_clkmux_sel,
-        .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
-        .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
-};
-
-DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
-
-static const char *pwmss_clk_parents[] = {
-        "dpll_per_m2_ck",
-};
-
-static const struct clk_ops ehrpwm_tbclk_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS0_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS1_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
-                         NULL, NULL, 0,
-                         AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
-                         AM33XX_PWMSS2_TBCLKEN_SHIFT,
-                         NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
-
-/*
- * debugss optional clocks
- */
-DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
-                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
-                0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
-
-static const char *stm_pmd_clock_mux_ck_parents[] = {
-        "dbg_sysclk_ck", "dbg_clka_ck",
-};
-
-DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
-               AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
-               AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-               AM33XX_TRC_PMD_CLKSEL_SHIFT,
-               AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
-                   &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                   AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
-                   AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
-                   &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
-                   AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
-                   AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-/*
- * clkdev
- */
-static struct omap_clk am33xx_clks[] = {
-        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck),
-        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck),
-        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck),
-        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck),
-        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck),
-        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck),
-        CLK(NULL,       "tclkin_ck",            &tclkin_ck),
-        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck),
-        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck),
-        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck),
-        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck),
-        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck),
-        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck),
-        CLK("cpu0",     NULL,                   &dpll_mpu_ck),
-        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck),
-        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck),
-        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck),
-        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck),
-        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck),
-        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck),
-        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck),
-        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck),
-        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck),
-        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck),
-        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck),
-        CLK(NULL,       "cefuse_fck",           &cefuse_fck),
-        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck),
-        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick),
-        CLK(NULL,       "dcan0_fck",            &dcan0_fck),
-        CLK("481cc000.d_can",   NULL,           &dcan0_fck),
-        CLK(NULL,       "dcan1_fck",            &dcan1_fck),
-        CLK("481d0000.d_can",   NULL,           &dcan1_fck),
-        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
-        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
-        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
-        CLK(NULL,       "mmu_fck",              &mmu_fck),
-        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
-        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
-        CLK(NULL,       "sha0_fck",             &sha0_fck),
-        CLK(NULL,       "aes0_fck",             &aes0_fck),
-        CLK(NULL,       "rng_fck",              &rng_fck),
-        CLK(NULL,       "timer1_fck",           &timer1_fck),
-        CLK(NULL,       "timer2_fck",           &timer2_fck),
-        CLK(NULL,       "timer3_fck",           &timer3_fck),
-        CLK(NULL,       "timer4_fck",           &timer4_fck),
-        CLK(NULL,       "timer5_fck",           &timer5_fck),
-        CLK(NULL,       "timer6_fck",           &timer6_fck),
-        CLK(NULL,       "timer7_fck",           &timer7_fck),
-        CLK(NULL,       "usbotg_fck",           &usbotg_fck),
-        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck),
-        CLK(NULL,       "wdt1_fck",             &wdt1_fck),
-        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk),
-        CLK(NULL,       "l3_gclk",              &l3_gclk),
-        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
-        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk),
-        CLK(NULL,       "l3s_gclk",             &l3s_gclk),
-        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk),
-        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk),
-        CLK(NULL,       "clk_24mhz",            &clk_24mhz),
-        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck),
-        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk),
-        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk),
-        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck),
-        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk),
-        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk),
-        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk),
-        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk),
-        CLK(NULL,       "lcd_gclk",             &lcd_gclk),
-        CLK(NULL,       "mmc_clk",              &mmc_clk),
-        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck),
-        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck),
-        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck),
-        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
-        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
-        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
-        CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
-        CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
-        CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
-        CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
-        CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
-        CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
-        CLK(NULL,       "clkout2_ck",           &clkout2_ck),
-        CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
-        CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
-        CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
-};
-
-
-static const char *enable_init_clks[] = {
-        "dpll_ddr_m2_ck",
-        "dpll_mpu_m2_ck",
-        "l3_gclk",
-        "l4hs_gclk",
-        "l4fw_gclk",
-        "l4ls_gclk",
-        "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
-};
-
-int __init am33xx_clk_init(void)
-{
-        if (soc_is_am33xx())
-                cpu_mask = RATE_IN_AM33XX;
-
-        omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
-
-        omap2_clk_disable_autoidle_all();
-
-        omap2_clk_enable_init_clocks(enable_init_clks,
-                                     ARRAY_SIZE(enable_init_clks));
-
-        /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
-         *    physically present, in such a case HWMOD enabling of
-         *    clock would be failure with default parent. And timer
-         *    probe thinks clock is already enabled, this leads to
-         *    crash upon accessing timer 3 & 6 registers in probe.
-         *    Fix by setting parent of both these timers to master
-         *    oscillator clock.
-         */
-
-        clk_set_parent(&timer3_fck, &sys_clkin_ck);
-        clk_set_parent(&timer6_fck, &sys_clkin_ck);
-        /*
-         * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
-         * the design/spec, so as a result, for example, timer which supposed
-         * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
-         * not expected by any use-case, so change WDT1 clock source to PRCM
-         * 32KHz clock.
-         */
-        clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
deleted file mode 100644
index ec0dc0b1755e..000000000000
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ /dev/null
@@ -1,1735 +0,0 @@
-/*
- * OMAP4 Clock data
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley (paul@pwsan.com)
- * Rajendra Nayak (rnayak@ti.com)
- * Benoit Cousson (b-cousson@ti.com)
- * Mike Turquette (mturquette@ti.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * XXX Some of the ES1 clocks have been removed/changed; once support
- * is added for discriminating clocks by ES level, these should be added back
- * in.
- *
- * XXX All of the remaining MODULEMODE clock nodes should be removed
- * once the drivers are updated to use pm_runtime or to use the appropriate
- * upstream clock node for rate/parent selection.
- */
-
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/clk-private.h>
-#include <linux/clkdev.h>
-#include <linux/io.h>
-
-#include "soc.h"
-#include "iomap.h"
-#include "clock.h"
-#include "clock44xx.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-#include "control.h"
-#include "scrm44xx.h"
-
-/* OMAP4 modulemode control */
-#define OMAP4430_MODULEMODE_HWCTRL_SHIFT                0
-#define OMAP4430_MODULEMODE_SWCTRL_SHIFT                1
-
-/*
- * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
- * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
- * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
- * half of this value.
- */
-#define OMAP4_DPLL_ABE_DEFFREQ                          98304000
-
-/*
- * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
- * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
- * locked frequency for the USB DPLL is 960MHz.
- */
-#define OMAP4_DPLL_USB_DEFFREQ                          960000000
-
-/* Root clocks */
-
-DEFINE_CLK_FIXED_RATE(extalt_clkin_ck, CLK_IS_ROOT, 59000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(pad_clks_src_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(pad_clks_ck, "pad_clks_src_ck", &pad_clks_src_ck, 0x0,
-                OMAP4430_CM_CLKSEL_ABE, OMAP4430_PAD_CLKS_GATE_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(pad_slimbus_core_clks_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(secure_32k_clk_src_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(slimbus_src_clk, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_GATE(slimbus_clk, "slimbus_src_clk", &slimbus_src_clk, 0x0,
-                OMAP4430_CM_CLKSEL_ABE, OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_FIXED_RATE(sys_32k_ck, CLK_IS_ROOT, 32768, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_12000000_ck, CLK_IS_ROOT, 12000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_13000000_ck, CLK_IS_ROOT, 13000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_16800000_ck, CLK_IS_ROOT, 16800000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_27000000_ck, CLK_IS_ROOT, 27000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(virt_38400000_ck, CLK_IS_ROOT, 38400000, 0x0);
-
-static const char *sys_clkin_ck_parents[] = {
-        "virt_12000000_ck", "virt_13000000_ck", "virt_16800000_ck",
-        "virt_19200000_ck", "virt_26000000_ck", "virt_27000000_ck",
-        "virt_38400000_ck",
-};
-
-DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
-               OMAP4430_CM_SYS_CLKSEL, OMAP4430_SYS_CLKSEL_SHIFT,
-               OMAP4430_SYS_CLKSEL_WIDTH, CLK_MUX_INDEX_ONE, NULL);
-
-DEFINE_CLK_FIXED_RATE(tie_low_clock_ck, CLK_IS_ROOT, 0, 0x0);
-
-DEFINE_CLK_FIXED_RATE(utmi_phy_clkout_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp1_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60mhsp2_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-DEFINE_CLK_FIXED_RATE(xclk60motg_ck, CLK_IS_ROOT, 60000000, 0x0);
-
-/* Module clocks and DPLL outputs */
-
-static const char *abe_dpll_bypass_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_MUX(abe_dpll_bypass_clk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents,
-               NULL, 0x0, OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_SHIFT,
-               OMAP4430_CLKSEL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(abe_dpll_refclk_mux_ck, abe_dpll_bypass_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_ABE_PLL_REF_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-/* DPLL_ABE */
-static struct dpll_data dpll_abe_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_ABE,
-        .clk_bypass     = &abe_dpll_bypass_clk_mux_ck,
-        .clk_ref        = &abe_dpll_refclk_mux_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_ABE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_ABE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_ABE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .m4xen_mask     = OMAP4430_DPLL_REGM4XEN_MASK,
-        .lpmode_mask    = OMAP4430_DPLL_LPMODE_EN_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-
-static const char *dpll_abe_ck_parents[] = {
-        "abe_dpll_refclk_mux_ck",
-};
-
-static struct clk dpll_abe_ck;
-
-static const struct clk_ops dpll_abe_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap4_dpll_regm4xen_recalc,
-        .round_rate     = &omap4_dpll_regm4xen_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_abe_ck_hw = {
-        .hw = {
-                .clk = &dpll_abe_ck,
-        },
-        .dpll_data      = &dpll_abe_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_ck, dpll_abe_ck_parents, dpll_abe_ck_ops);
-
-static const char *dpll_abe_x2_ck_parents[] = {
-        "dpll_abe_ck",
-};
-
-static struct clk dpll_abe_x2_ck;
-
-static const struct clk_ops dpll_abe_x2_ck_ops = {
-        .recalc_rate    = &omap3_clkoutx2_recalc,
-};
-
-static struct clk_hw_omap dpll_abe_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_abe_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_abe_x2_ck, dpll_abe_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-static const struct clk_ops omap_hsdivider_ops = {
-        .set_rate       = &omap2_clksel_set_rate,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .round_rate     = &omap2_clksel_round_rate,
-};
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m2x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M2_DPLL_ABE,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(abe_24m_fclk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-                        0x0, 1, 8);
-
-DEFINE_CLK_DIVIDER(abe_clk, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_ABE, OMAP4430_CLKSEL_OPP_SHIFT,
-                   OMAP4430_CLKSEL_OPP_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(aess_fclk, "abe_clk", &abe_clk, 0x0,
-                   OMAP4430_CM1_ABE_AESS_CLKCTRL,
-                   OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-                   OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_abe_m3x2_ck, "dpll_abe_x2_ck", &dpll_abe_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M3_DPLL_ABE,
-                          OMAP4430_DPLL_CLKOUTHIF_DIV_MASK);
-
-static const char *core_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "dpll_abe_m3x2_ck",
-};
-
-DEFINE_CLK_MUX(core_hsd_byp_clk_mux_ck, core_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_CORE,
-               OMAP4430_DPLL_BYP_CLKSEL_SHIFT, OMAP4430_DPLL_BYP_CLKSEL_WIDTH,
-               0x0, NULL);
-
-/* DPLL_CORE */
-static struct dpll_data dpll_core_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_CORE,
-        .clk_bypass     = &core_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_CORE,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_CORE,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-
-static const char *dpll_core_ck_parents[] = {
-        "sys_clkin_ck", "core_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_core_ck;
-
-static const struct clk_ops dpll_core_ck_ops = {
-        .recalc_rate    = &omap3_dpll_recalc,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_core_ck_hw = {
-        .hw = {
-                .clk = &dpll_core_ck,
-        },
-        .dpll_data      = &dpll_core_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
-
-static const char *dpll_core_x2_ck_parents[] = {
-        "dpll_core_ck",
-};
-
-static struct clk dpll_core_x2_ck;
-
-static struct clk_hw_omap dpll_core_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_core_x2_ck,
-        },
-};
-
-DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m6x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M6_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m2_ck, "dpll_core_ck", &dpll_core_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_CORE,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(ddrphy_ck, "dpll_core_m2_ck", &dpll_core_m2_ck, 0x0, 1,
-                        2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m5x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M5_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_DIVIDER(div_core_ck, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_CORE_SHIFT,
-                   OMAP4430_CLKSEL_CORE_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(div_iva_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-                   0x0, OMAP4430_CM_BYPCLK_DPLL_IVA, OMAP4430_CLKSEL_0_1_SHIFT,
-                   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_DIVIDER(div_mpu_hs_clk, "dpll_core_m5x2_ck", &dpll_core_m5x2_ck,
-                   0x0, OMAP4430_CM_BYPCLK_DPLL_MPU, OMAP4430_CLKSEL_0_1_SHIFT,
-                   OMAP4430_CLKSEL_0_1_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m4x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M4_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(dll_clk_div_ck, "dpll_core_m4x2_ck", &dpll_core_m4x2_ck,
-                        0x0, 1, 2);
-
-DEFINE_CLK_DIVIDER(dpll_abe_m2_ck, "dpll_abe_ck", &dpll_abe_ck, 0x0,
-                   OMAP4430_CM_DIV_M2_DPLL_ABE, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const struct clk_ops dpll_hsd_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static const struct clk_ops func_dmic_abe_gfclk_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-        .set_parent     = &omap2_clksel_set_parent,
-};
-
-static const char *dpll_core_m3x2_ck_parents[] = {
-        "dpll_core_x2_ck",
-};
-
-static const struct clksel dpll_core_m3x2_div[] = {
-        { .parent = &dpll_core_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_core_m3x2_ck, NULL, dpll_core_m3x2_div,
-                         OMAP4430_CM_DIV_M3_DPLL_CORE,
-                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-                         OMAP4430_CM_DIV_M3_DPLL_CORE,
-                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_core_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_core_m7x2_ck, "dpll_core_x2_ck",
-                          &dpll_core_x2_ck, 0x0, OMAP4430_CM_DIV_M7_DPLL_CORE,
-                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-static const char *iva_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "div_iva_hs_clk",
-};
-
-DEFINE_CLK_MUX(iva_hsd_byp_clk_mux_ck, iva_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_IVA, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_IVA */
-static struct dpll_data dpll_iva_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_IVA,
-        .clk_bypass     = &iva_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_IVA,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_IVA,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_iva_ck_parents[] = {
-        "sys_clkin_ck", "iva_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_iva_ck;
-
-static const struct clk_ops dpll_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-};
-
-static struct clk_hw_omap dpll_iva_ck_hw = {
-        .hw = {
-                .clk = &dpll_iva_ck,
-        },
-        .dpll_data      = &dpll_iva_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_ck, dpll_iva_ck_parents, dpll_ck_ops);
-
-static const char *dpll_iva_x2_ck_parents[] = {
-        "dpll_iva_ck",
-};
-
-static struct clk dpll_iva_x2_ck;
-
-static struct clk_hw_omap dpll_iva_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_iva_x2_ck,
-        },
-};
-
-DEFINE_STRUCT_CLK(dpll_iva_x2_ck, dpll_iva_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m4x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M4_DPLL_IVA,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_iva_m5x2_ck, "dpll_iva_x2_ck", &dpll_iva_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M5_DPLL_IVA,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-/* DPLL_MPU */
-static struct dpll_data dpll_mpu_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_MPU,
-        .clk_bypass     = &div_mpu_hs_clk,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_MPU,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_MPU,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_mpu_ck_parents[] = {
-        "sys_clkin_ck", "div_mpu_hs_clk"
-};
-
-static struct clk dpll_mpu_ck;
-
-static struct clk_hw_omap dpll_mpu_ck_hw = {
-        .hw = {
-                .clk = &dpll_mpu_ck,
-        },
-        .dpll_data      = &dpll_mpu_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_mpu_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_FIXED_FACTOR(mpu_periphclk, "dpll_mpu_ck", &dpll_mpu_ck, 0x0, 1, 2);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_MPU,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(per_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-                        &dpll_abe_m3x2_ck, 0x0, 1, 2);
-
-static const char *per_hsd_byp_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "per_hs_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(per_hsd_byp_clk_mux_ck, per_hsd_byp_clk_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM_CLKSEL_DPLL_PER, OMAP4430_DPLL_BYP_CLKSEL_SHIFT,
-               OMAP4430_DPLL_BYP_CLKSEL_WIDTH, 0x0, NULL);
-
-/* DPLL_PER */
-static struct dpll_data dpll_per_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_PER,
-        .clk_bypass     = &per_hsd_byp_clk_mux_ck,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_PER,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_PER,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_PER,
-        .mult_mask      = OMAP4430_DPLL_MULT_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .max_multiplier = 2047,
-        .max_divider    = 128,
-        .min_divider    = 1,
-};
-
-static const char *dpll_per_ck_parents[] = {
-        "sys_clkin_ck", "per_hsd_byp_clk_mux_ck"
-};
-
-static struct clk dpll_per_ck;
-
-static struct clk_hw_omap dpll_per_ck_hw = {
-        .hw = {
-                .clk = &dpll_per_ck,
-        },
-        .dpll_data      = &dpll_per_dd,
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_ck, dpll_per_ck_parents, dpll_ck_ops);
-
-DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
-                   OMAP4430_CM_DIV_M2_DPLL_PER, OMAP4430_DPLL_CLKOUT_DIV_SHIFT,
-                   OMAP4430_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
-
-static const char *dpll_per_x2_ck_parents[] = {
-        "dpll_per_ck",
-};
-
-static struct clk dpll_per_x2_ck;
-
-static struct clk_hw_omap dpll_per_x2_ck_hw = {
-        .hw = {
-                .clk = &dpll_per_x2_ck,
-        },
-        .flags          = CLOCK_CLKOUTX2,
-        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_per_x2_ck, dpll_per_x2_ck_parents, dpll_abe_x2_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m2x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M2_DPLL_PER,
-                          OMAP4430_DPLL_CLKOUT_DIV_MASK);
-
-static const char *dpll_per_m3x2_ck_parents[] = {
-        "dpll_per_x2_ck",
-};
-
-static const struct clksel dpll_per_m3x2_div[] = {
-        { .parent = &dpll_per_x2_ck, .rates = div31_1to31_rates },
-        { .parent = NULL },
-};
-
-/* XXX Missing round_rate, set_rate in ops */
-DEFINE_CLK_OMAP_MUX_GATE(dpll_per_m3x2_ck, NULL, dpll_per_m3x2_div,
-                         OMAP4430_CM_DIV_M3_DPLL_PER,
-                         OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-                         OMAP4430_CM_DIV_M3_DPLL_PER,
-                         OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT, NULL,
-                         dpll_per_m3x2_ck_parents, dpll_hsd_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m4x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M4_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m5x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M5_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m6x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M6_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_per_m7x2_ck, "dpll_per_x2_ck", &dpll_per_x2_ck,
-                          0x0, OMAP4430_CM_DIV_M7_DPLL_PER,
-                          OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK);
-
-DEFINE_CLK_FIXED_FACTOR(usb_hs_clk_div_ck, "dpll_abe_m3x2_ck",
-                        &dpll_abe_m3x2_ck, 0x0, 1, 3);
-
-/* DPLL_USB */
-static struct dpll_data dpll_usb_dd = {
-        .mult_div1_reg  = OMAP4430_CM_CLKSEL_DPLL_USB,
-        .clk_bypass     = &usb_hs_clk_div_ck,
-        .flags          = DPLL_J_TYPE,
-        .clk_ref        = &sys_clkin_ck,
-        .control_reg    = OMAP4430_CM_CLKMODE_DPLL_USB,
-        .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
-        .autoidle_reg   = OMAP4430_CM_AUTOIDLE_DPLL_USB,
-        .idlest_reg     = OMAP4430_CM_IDLEST_DPLL_USB,
-        .mult_mask      = OMAP4430_DPLL_MULT_USB_MASK,
-        .div1_mask      = OMAP4430_DPLL_DIV_0_7_MASK,
-        .enable_mask    = OMAP4430_DPLL_EN_MASK,
-        .autoidle_mask  = OMAP4430_AUTO_DPLL_MODE_MASK,
-        .idlest_mask    = OMAP4430_ST_DPLL_CLK_MASK,
-        .sddiv_mask     = OMAP4430_DPLL_SD_DIV_MASK,
-        .max_multiplier = 4095,
-        .max_divider    = 256,
-        .min_divider    = 1,
-};
-
-static const char *dpll_usb_ck_parents[] = {
-        "sys_clkin_ck", "usb_hs_clk_div_ck"
-};
-
-static struct clk dpll_usb_ck;
-
-static const struct clk_ops dpll_usb_ck_ops = {
-        .enable         = &omap3_noncore_dpll_enable,
-        .disable        = &omap3_noncore_dpll_disable,
-        .recalc_rate    = &omap3_dpll_recalc,
-        .round_rate     = &omap2_dpll_round_rate,
-        .set_rate       = &omap3_noncore_dpll_set_rate,
-        .get_parent     = &omap2_init_dpll_parent,
-        .init           = &omap2_init_clk_clkdm,
-};
-
-static struct clk_hw_omap dpll_usb_ck_hw = {
-        .hw = {
-                .clk = &dpll_usb_ck,
-        },
-        .dpll_data      = &dpll_usb_dd,
-        .clkdm_name     = "l3_init_clkdm",
-        .ops            = &clkhwops_omap3_dpll,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
-
-static const char *dpll_usb_clkdcoldo_ck_parents[] = {
-        "dpll_usb_ck",
-};
-
-static struct clk dpll_usb_clkdcoldo_ck;
-
-static const struct clk_ops dpll_usb_clkdcoldo_ck_ops = {
-};
-
-static struct clk_hw_omap dpll_usb_clkdcoldo_ck_hw = {
-        .hw = {
-                .clk = &dpll_usb_clkdcoldo_ck,
-        },
-        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
-        .ops            = &clkhwops_omap4_dpllmx,
-};
-
-DEFINE_STRUCT_CLK(dpll_usb_clkdcoldo_ck, dpll_usb_clkdcoldo_ck_parents,
-                  dpll_usb_clkdcoldo_ck_ops);
-
-DEFINE_CLK_OMAP_HSDIVIDER(dpll_usb_m2_ck, "dpll_usb_ck", &dpll_usb_ck, 0x0,
-                          OMAP4430_CM_DIV_M2_DPLL_USB,
-                          OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK);
-
-static const char *ducati_clk_mux_ck_parents[] = {
-        "div_core_ck", "dpll_per_m6x2_ck",
-};
-
-DEFINE_CLK_MUX(ducati_clk_mux_ck, ducati_clk_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_12m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 16);
-
-DEFINE_CLK_FIXED_FACTOR(func_24m_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0,
-                        1, 4);
-
-DEFINE_CLK_FIXED_FACTOR(func_24mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 8);
-
-static const struct clk_div_table func_48m_fclk_rates[] = {
-        { .div = 4, .val = 0 },
-        { .div = 8, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_48m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_48m_fclk_rates,
-                         NULL);
-
-DEFINE_CLK_FIXED_FACTOR(func_48mc_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                        0x0, 1, 4);
-
-static const struct clk_div_table func_64m_fclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 4, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_64m_fclk, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_64m_fclk_rates,
-                         NULL);
-
-static const struct clk_div_table func_96m_fclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 4, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(func_96m_fclk, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck,
-                         0x0, OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                         OMAP4430_SCALE_FCLK_WIDTH, 0x0, func_96m_fclk_rates,
-                         NULL);
-
-static const struct clk_div_table init_60m_fclk_rates[] = {
-        { .div = 1, .val = 0 },
-        { .div = 8, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(init_60m_fclk, "dpll_usb_m2_ck", &dpll_usb_m2_ck,
-                         0x0, OMAP4430_CM_CLKSEL_USB_60MHZ,
-                         OMAP4430_CLKSEL_0_0_SHIFT, OMAP4430_CLKSEL_0_0_WIDTH,
-                         0x0, init_60m_fclk_rates, NULL);
-
-DEFINE_CLK_DIVIDER(l3_div_ck, "div_core_ck", &div_core_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L3_SHIFT,
-                   OMAP4430_CLKSEL_L3_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(l4_div_ck, "l3_div_ck", &l3_div_ck, 0x0,
-                   OMAP4430_CM_CLKSEL_CORE, OMAP4430_CLKSEL_L4_SHIFT,
-                   OMAP4430_CLKSEL_L4_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(lp_clk_div_ck, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck,
-                        0x0, 1, 16);
-
-static const char *l4_wkup_clk_mux_ck_parents[] = {
-        "sys_clkin_ck", "lp_clk_div_ck",
-};
-
-DEFINE_CLK_MUX(l4_wkup_clk_mux_ck, l4_wkup_clk_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_L4_WKUP_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-               OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const struct clk_div_table ocp_abe_iclk_rates[] = {
-        { .div = 2, .val = 0 },
-        { .div = 1, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(ocp_abe_iclk, "aess_fclk", &aess_fclk, 0x0,
-                         OMAP4430_CM1_ABE_AESS_CLKCTRL,
-                         OMAP4430_CLKSEL_AESS_FCLK_SHIFT,
-                         OMAP4430_CLKSEL_AESS_FCLK_WIDTH,
-                         0x0, ocp_abe_iclk_rates, NULL);
-
-DEFINE_CLK_FIXED_FACTOR(per_abe_24m_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck,
-                        0x0, 1, 4);
-
-DEFINE_CLK_DIVIDER(per_abe_nc_fclk, "dpll_abe_m2_ck", &dpll_abe_m2_ck, 0x0,
-                   OMAP4430_CM_SCALE_FCLK, OMAP4430_SCALE_FCLK_SHIFT,
-                   OMAP4430_SCALE_FCLK_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(syc_clk_div_ck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
-                   OMAP4430_CM_ABE_DSS_SYS_CLKSEL, OMAP4430_CLKSEL_0_0_SHIFT,
-                   OMAP4430_CLKSEL_0_0_WIDTH, 0x0, NULL);
-
-static const char *dbgclk_mux_ck_parents[] = {
-        "sys_clkin_ck"
-};
-
-static struct clk dbgclk_mux_ck;
-DEFINE_STRUCT_CLK_HW_OMAP(dbgclk_mux_ck, NULL);
-DEFINE_STRUCT_CLK(dbgclk_mux_ck, dbgclk_mux_ck_parents,
-                  dpll_usb_clkdcoldo_ck_ops);
-
-/* Leaf clocks controlled by modules */
-
-DEFINE_CLK_GATE(aes1_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_AES1_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(aes2_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_AES2_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(bandgap_fclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table div_ts_ck_rates[] = {
-        { .div = 8, .val = 0 },
-        { .div = 16, .val = 1 },
-        { .div = 32, .val = 2 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(div_ts_ck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                         0x0, OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                         OMAP4430_CLKSEL_24_25_SHIFT,
-                         OMAP4430_CLKSEL_24_25_WIDTH, 0x0, div_ts_ck_rates,
-                         NULL);
-
-DEFINE_CLK_GATE(bandgap_ts_fclk, "div_ts_ck", &div_ts_ck, 0x0,
-                OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
-                OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
-                0x0, NULL);
-
-static const char *dmic_sync_mux_ck_parents[] = {
-        "abe_24m_fclk", "syc_clk_div_ck", "func_24m_clk",
-};
-
-DEFINE_CLK_MUX(dmic_sync_mux_ck, dmic_sync_mux_ck_parents, NULL,
-               0x0, OMAP4430_CM1_ABE_DMIC_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_dmic_abe_gfclk_sel[] = {
-        { .parent = &dmic_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_dmic_abe_gfclk_parents[] = {
-        "dmic_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_dmic_abe_gfclk, "abe_clkdm", func_dmic_abe_gfclk_sel,
-                    OMAP4430_CM1_ABE_DMIC_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-                    func_dmic_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(dss_sys_clk, "syc_clk_div_ck", &syc_clk_div_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_tv_clk, "extalt_clkin_ck", &extalt_clkin_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_TV_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(dss_dss_clk, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck,
-                CLK_SET_RATE_PARENT,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(dss_48mhz_clk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(dss_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_DSS_DSS_CLKCTRL, OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_DIVIDER(fdif_fck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-                   OMAP4430_CM_CAM_FDIF_CLKCTRL, OMAP4430_CLKSEL_FCLK_SHIFT,
-                   OMAP4430_CLKSEL_FCLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
-
-DEFINE_CLK_GATE(gpio1_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
-                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio2_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO2_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio3_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
-                OMAP4430_OPTFCLKEN_DBCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(gpio4_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO4_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio5_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO5_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_GATE(gpio6_dbclk, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_L4PER_GPIO6_CLKCTRL, OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
-                0x0, NULL);
-
-static const struct clksel sgx_clk_mux_sel[] = {
-        { .parent = &dpll_core_m7x2_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_per_m7x2_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *sgx_clk_mux_parents[] = {
-        "dpll_core_m7x2_ck", "dpll_per_m7x2_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(sgx_clk_mux, "l3_gfx_clkdm", sgx_clk_mux_sel,
-                    OMAP4430_CM_GFX_GFX_CLKCTRL, OMAP4430_CLKSEL_SGX_FCLK_MASK,
-                    sgx_clk_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_DIVIDER(hsi_fck, "dpll_per_m2x2_ck", &dpll_per_m2x2_ck, 0x0,
-                   OMAP4430_CM_L3INIT_HSI_CLKCTRL, OMAP4430_CLKSEL_24_25_SHIFT,
-                   OMAP4430_CLKSEL_24_25_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-DEFINE_CLK_GATE(iss_ctrlclk, "func_96m_fclk", &func_96m_fclk, 0x0,
-                OMAP4430_CM_CAM_ISS_CLKCTRL, OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
-                0x0, NULL);
-
-DEFINE_CLK_MUX(mcasp_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCASP_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcasp_abe_gfclk_sel[] = {
-        { .parent = &mcasp_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcasp_abe_gfclk_parents[] = {
-        "mcasp_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcasp_abe_gfclk, "abe_clkdm", func_mcasp_abe_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCASP_CLKCTRL, OMAP4430_CLKSEL_SOURCE_MASK,
-                    func_mcasp_abe_gfclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp1_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp1_gfclk_sel[] = {
-        { .parent = &mcbsp1_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp1_gfclk_parents[] = {
-        "mcbsp1_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp1_gfclk, "abe_clkdm", func_mcbsp1_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp1_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp2_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp2_gfclk_sel[] = {
-        { .parent = &mcbsp2_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp2_gfclk_parents[] = {
-        "mcbsp2_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp2_gfclk, "abe_clkdm", func_mcbsp2_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp2_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_MUX(mcbsp3_sync_mux_ck, dmic_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel func_mcbsp3_gfclk_sel[] = {
-        { .parent = &mcbsp3_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = &slimbus_clk, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *func_mcbsp3_gfclk_parents[] = {
-        "mcbsp3_sync_mux_ck", "pad_clks_ck", "slimbus_clk",
-};
-
-DEFINE_CLK_OMAP_MUX(func_mcbsp3_gfclk, "abe_clkdm", func_mcbsp3_gfclk_sel,
-                    OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_MASK, func_mcbsp3_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const char *mcbsp4_sync_mux_ck_parents[] = {
-        "func_96m_fclk", "per_abe_nc_fclk",
-};
-
-DEFINE_CLK_MUX(mcbsp4_sync_mux_ck, mcbsp4_sync_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT,
-               OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH, 0x0, NULL);
-
-static const struct clksel per_mcbsp4_gfclk_sel[] = {
-        { .parent = &mcbsp4_sync_mux_ck, .rates = div_1_0_rates },
-        { .parent = &pad_clks_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *per_mcbsp4_gfclk_parents[] = {
-        "mcbsp4_sync_mux_ck", "pad_clks_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(per_mcbsp4_gfclk, "l4_per_clkdm", per_mcbsp4_gfclk_sel,
-                    OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
-                    OMAP4430_CLKSEL_SOURCE_24_24_MASK, per_mcbsp4_gfclk_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const struct clksel hsmmc1_fclk_sel[] = {
-        { .parent = &func_64m_fclk, .rates = div_1_0_rates },
-        { .parent = &func_96m_fclk, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *hsmmc1_fclk_parents[] = {
-        "func_64m_fclk", "func_96m_fclk",
-};
-
-DEFINE_CLK_OMAP_MUX(hsmmc1_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-                    OMAP4430_CM_L3INIT_MMC1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(hsmmc2_fclk, "l3_init_clkdm", hsmmc1_fclk_sel,
-                    OMAP4430_CM_L3INIT_MMC2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    hsmmc1_fclk_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_GATE(ocp2scp_usb_phy_phy_48m, "func_48m_fclk", &func_48m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PHY_48M_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(sha2md5_fck, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_1, "func_24m_clk", &func_24m_clk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK1_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_0, "abe_24m_fclk", &abe_24m_fclk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK0_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_fclk_2, "pad_clks_ck", &pad_clks_ck, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FCLK2_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus1_slimbus_clk, "slimbus_clk", &slimbus_clk, 0x0,
-                OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_1, "per_abe_24m_fclk", &per_abe_24m_fclk, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_fclk_0, "func_24mc_fclk", &func_24mc_fclk, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(slimbus2_slimbus_clk, "pad_slimbus_core_clks_ck",
-                &pad_slimbus_core_clks_ck, 0x0,
-                OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
-                OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_core_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_iva_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(smartreflex_mpu_fck, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck,
-                0x0, OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clksel dmt1_clk_mux_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-DEFINE_CLK_OMAP_MUX(dmt1_clk_mux, "l4_wkup_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_WKUP_TIMER1_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm10_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm11_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm2_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm3_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm4_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static const struct clksel timer5_sync_mux_sel[] = {
-        { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
-        { .parent = &sys_32k_ck, .rates = div_1_1_rates },
-        { .parent = NULL },
-};
-
-static const char *timer5_sync_mux_parents[] = {
-        "syc_clk_div_ck", "sys_32k_ck",
-};
-
-DEFINE_CLK_OMAP_MUX(timer5_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER5_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer6_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER6_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer7_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER7_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(timer8_sync_mux, "abe_clkdm", timer5_sync_mux_sel,
-                    OMAP4430_CM1_ABE_TIMER8_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    timer5_sync_mux_parents, func_dmic_abe_gfclk_ops);
-
-DEFINE_CLK_OMAP_MUX(cm2_dm9_mux, "l4_per_clkdm", dmt1_clk_mux_sel,
-                    OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, OMAP4430_CLKSEL_MASK,
-                    abe_dpll_bypass_clk_mux_ck_parents,
-                    func_dmic_abe_gfclk_ops);
-
-static struct clk usb_host_fs_fck;
-
-static const char *usb_host_fs_fck_parent_names[] = {
-        "func_48mc_fclk",
-};
-
-static const struct clk_ops usb_host_fs_fck_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-};
-
-static struct clk_hw_omap usb_host_fs_fck_hw = {
-        .hw = {
-                .clk = &usb_host_fs_fck,
-        },
-        .enable_reg     = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
-        .enable_bit     = OMAP4430_MODULEMODE_SWCTRL_SHIFT,
-        .clkdm_name     = "l3_init_clkdm",
-};
-
-DEFINE_STRUCT_CLK(usb_host_fs_fck, usb_host_fs_fck_parent_names,
-                  usb_host_fs_fck_ops);
-
-static const char *utmi_p1_gfclk_parents[] = {
-        "init_60m_fclk", "xclk60mhsp1_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p1_gfclk, utmi_p1_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-               OMAP4430_CLKSEL_UTMI_P1_SHIFT, OMAP4430_CLKSEL_UTMI_P1_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p1_clk, "utmi_p1_gfclk", &utmi_p1_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT, 0x0, NULL);
-
-static const char *utmi_p2_gfclk_parents[] = {
-        "init_60m_fclk", "xclk60mhsp2_ck",
-};
-
-DEFINE_CLK_MUX(utmi_p2_gfclk, utmi_p2_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-               OMAP4430_CLKSEL_UTMI_P2_SHIFT, OMAP4430_CLKSEL_UTMI_P2_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p2_clk, "utmi_p2_gfclk", &utmi_p2_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_utmi_p3_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p1_clk, "dpll_usb_m2_ck",
-                &dpll_usb_m2_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p1_clk, "init_60m_fclk",
-                &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic60m_p2_clk, "init_60m_fclk",
-                &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_hsic480m_p2_clk, "dpll_usb_m2_ck",
-                &dpll_usb_m2_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_func48mclk, "func_48mc_fclk", &func_48mc_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_host_hs_fck, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
-                OMAP4430_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
-
-static const char *otg_60m_gfclk_parents[] = {
-        "utmi_phy_clkout_ck", "xclk60motg_ck",
-};
-
-DEFINE_CLK_MUX(otg_60m_gfclk, otg_60m_gfclk_parents, NULL, 0x0,
-               OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, OMAP4430_CLKSEL_60M_SHIFT,
-               OMAP4430_CLKSEL_60M_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_xclk, "otg_60m_gfclk", &otg_60m_gfclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-                OMAP4430_OPTFCLKEN_XCLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_otg_hs_ick, "l3_div_ck", &l3_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_phy_cm_clk32k, "sys_32k_ck", &sys_32k_ck, 0x0,
-                OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
-                OMAP4430_OPTFCLKEN_CLK32K_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch2_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch0_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_usb_ch1_clk, "init_60m_fclk", &init_60m_fclk, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT, 0x0, NULL);
-
-DEFINE_CLK_GATE(usb_tll_hs_ick, "l4_div_ck", &l4_div_ck, 0x0,
-                OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
-                OMAP4430_MODULEMODE_HWCTRL_SHIFT, 0x0, NULL);
-
-static const struct clk_div_table usim_ck_rates[] = {
-        { .div = 14, .val = 0 },
-        { .div = 18, .val = 1 },
-        { .div = 0 },
-};
-DEFINE_CLK_DIVIDER_TABLE(usim_ck, "dpll_per_m4x2_ck", &dpll_per_m4x2_ck, 0x0,
-                         OMAP4430_CM_WKUP_USIM_CLKCTRL,
-                         OMAP4430_CLKSEL_DIV_SHIFT, OMAP4430_CLKSEL_DIV_WIDTH,
-                         0x0, usim_ck_rates, NULL);
-
-DEFINE_CLK_GATE(usim_fclk, "usim_ck", &usim_ck, 0x0,
-                OMAP4430_CM_WKUP_USIM_CLKCTRL, OMAP4430_OPTFCLKEN_FCLK_SHIFT,
-                0x0, NULL);
-
-/* Remaining optional clocks */
-static const char *pmd_stm_clock_mux_ck_parents[] = {
-        "sys_clkin_ck", "dpll_core_m6x2_ck", "tie_low_clock_ck",
-};
-
-DEFINE_CLK_MUX(pmd_stm_clock_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, OMAP4430_PMD_STM_MUX_CTRL_SHIFT,
-               OMAP4430_PMD_STM_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_MUX(pmd_trace_clk_mux_ck, pmd_stm_clock_mux_ck_parents, NULL, 0x0,
-               OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-               OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT,
-               OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH, 0x0, NULL);
-
-DEFINE_CLK_DIVIDER(stm_clk_div_ck, "pmd_stm_clock_mux_ck",
-                   &pmd_stm_clock_mux_ck, 0x0, OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-                   OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT,
-                   OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
-                   NULL);
-
-static const char *trace_clk_div_ck_parents[] = {
-        "pmd_trace_clk_mux_ck",
-};
-
-static const struct clksel trace_clk_div_div[] = {
-        { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
-        { .parent = NULL },
-};
-
-static struct clk trace_clk_div_ck;
-
-static const struct clk_ops trace_clk_div_ck_ops = {
-        .recalc_rate    = &omap2_clksel_recalc,
-        .set_rate       = &omap2_clksel_set_rate,
-        .round_rate     = &omap2_clksel_round_rate,
-        .init           = &omap2_init_clk_clkdm,
-        .enable         = &omap2_clkops_enable_clkdm,
-        .disable        = &omap2_clkops_disable_clkdm,
-};
-
-static struct clk_hw_omap trace_clk_div_ck_hw = {
-        .hw = {
-                .clk = &trace_clk_div_ck,
-        },
-        .clkdm_name     = "emu_sys_clkdm",
-        .clksel         = trace_clk_div_div,
-        .clksel_reg     = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
-        .clksel_mask    = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
-};
-
-DEFINE_STRUCT_CLK(trace_clk_div_ck, trace_clk_div_ck_parents,
-                  trace_clk_div_ck_ops);
-
-/* SCRM aux clk nodes */
-
-static const struct clksel auxclk_src_sel[] = {
-        { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
-        { .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
-        { .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
-        { .parent = NULL },
-};
-
-static const char *auxclk_src_ck_parents[] = {
-        "sys_clkin_ck", "dpll_core_m3x2_ck", "dpll_per_m3x2_ck",
-};
-
-static const struct clk_ops auxclk_src_ck_ops = {
-        .enable         = &omap2_dflt_clk_enable,
-        .disable        = &omap2_dflt_clk_disable,
-        .is_enabled     = &omap2_dflt_clk_is_enabled,
-        .recalc_rate    = &omap2_clksel_recalc,
-        .get_parent     = &omap2_clksel_find_parent_index,
-};
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk0_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK0, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK0, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk0_ck, "auxclk0_src_ck", &auxclk0_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK0, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk1_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK1, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK1, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk1_ck, "auxclk1_src_ck", &auxclk1_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK1, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk2_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK2, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK2, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk2_ck, "auxclk2_src_ck", &auxclk2_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK2, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk3_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK3, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK3, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk3_ck, "auxclk3_src_ck", &auxclk3_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK3, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk4_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK4, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK4, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk4_ck, "auxclk4_src_ck", &auxclk4_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK4, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-DEFINE_CLK_OMAP_MUX_GATE(auxclk5_src_ck, NULL, auxclk_src_sel,
-                         OMAP4_SCRM_AUXCLK5, OMAP4_SRCSELECT_MASK,
-                         OMAP4_SCRM_AUXCLK5, OMAP4_ENABLE_SHIFT, NULL,
-                         auxclk_src_ck_parents, auxclk_src_ck_ops);
-
-DEFINE_CLK_DIVIDER(auxclk5_ck, "auxclk5_src_ck", &auxclk5_src_ck, 0x0,
-                   OMAP4_SCRM_AUXCLK5, OMAP4_CLKDIV_SHIFT, OMAP4_CLKDIV_WIDTH,
-                   0x0, NULL);
-
-static const char *auxclkreq_ck_parents[] = {
-        "auxclk0_ck", "auxclk1_ck", "auxclk2_ck", "auxclk3_ck", "auxclk4_ck",
-        "auxclk5_ck",
-};
-
-DEFINE_CLK_MUX(auxclkreq0_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ0, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq1_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ1, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq2_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ2, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq3_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ3, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq4_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ4, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
-               OMAP4_SCRM_AUXCLKREQ5, OMAP4_MAPPING_SHIFT, OMAP4_MAPPING_WIDTH,
-               0x0, NULL);
-
-/*
- * clocks specific to omap4460
- */
-static struct omap_clk omap446x_clks[] = {
-        CLK(NULL,       "div_ts_ck",                    &div_ts_ck),
-        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk),
-};
-
-/*
- * clocks specific to omap4430
- */
-static struct omap_clk omap443x_clks[] = {
-        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk),
-};
-
-/*
- * clocks common to omap44xx
- */
-static struct omap_clk omap44xx_clks[] = {
-        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck),
-        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck),
-        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck),
-        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck),
-        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck),
-        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk),
-        CLK(NULL,       "slimbus_clk",                  &slimbus_clk),
-        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck),
-        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck),
-        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck),
-        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck),
-        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck),
-        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck),
-        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck),
-        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck),
-        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck),
-        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck),
-        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck),
-        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck),
-        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck),
-        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck),
-        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck),
-        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck),
-        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck),
-        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck),
-        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck),
-        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk),
-        CLK(NULL,       "abe_clk",                      &abe_clk),
-        CLK(NULL,       "aess_fclk",                    &aess_fclk),
-        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck),
-        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck),
-        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck),
-        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck),
-        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck),
-        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck),
-        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck),
-        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck),
-        CLK(NULL,       "div_core_ck",                  &div_core_ck),
-        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk),
-        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk),
-        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck),
-        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck),
-        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck),
-        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck),
-        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck),
-        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck),
-        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck),
-        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck),
-        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck),
-        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck),
-        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck),
-        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck),
-        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck),
-        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck),
-        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck),
-        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck),
-        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck),
-        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck),
-        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck),
-        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck),
-        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck),
-        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck),
-        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck),
-        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck),
-        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck),
-        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck),
-        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck),
-        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk),
-        CLK(NULL,       "func_24m_clk",                 &func_24m_clk),
-        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk),
-        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk),
-        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk),
-        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk),
-        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk),
-        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk),
-        CLK(NULL,       "l3_div_ck",                    &l3_div_ck),
-        CLK(NULL,       "l4_div_ck",                    &l4_div_ck),
-        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck),
-        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck),
-        CLK("smp_twd",  NULL,                           &mpu_periphclk),
-        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk),
-        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk),
-        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck),
-        CLK(NULL,       "aes1_fck",                     &aes1_fck),
-        CLK(NULL,       "aes2_fck",                     &aes2_fck),
-        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck),
-        CLK(NULL,       "func_dmic_abe_gfclk",          &func_dmic_abe_gfclk),
-        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk),
-        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk),
-        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk),
-        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk),
-        CLK(NULL,       "dss_fck",                      &dss_fck),
-        CLK("omapdss_dss",      "ick",                  &dss_fck),
-        CLK(NULL,       "fdif_fck",                     &fdif_fck),
-        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk),
-        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk),
-        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk),
-        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk),
-        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk),
-        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk),
-        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux),
-        CLK(NULL,       "hsi_fck",                      &hsi_fck),
-        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk),
-        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck),
-        CLK(NULL,       "func_mcasp_abe_gfclk",         &func_mcasp_abe_gfclk),
-        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp1_gfclk",            &func_mcbsp1_gfclk),
-        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp2_gfclk",            &func_mcbsp2_gfclk),
-        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck),
-        CLK(NULL,       "func_mcbsp3_gfclk",            &func_mcbsp3_gfclk),
-        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck),
-        CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
-        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
-        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
-        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
-        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
-        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
-        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2),
-        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk),
-        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1),
-        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0),
-        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk),
-        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck),
-        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck),
-        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck),
-        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux),
-        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux),
-        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux),
-        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux),
-        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux),
-        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux),
-        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux),
-        CLK(NULL,       "timer6_sync_mux",              &timer6_sync_mux),
-        CLK(NULL,       "timer7_sync_mux",              &timer7_sync_mux),
-        CLK(NULL,       "timer8_sync_mux",              &timer8_sync_mux),
-        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck),
-        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck),
-        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk),
-        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk),
-        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk),
-        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk),
-        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck),
-        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck),
-        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk),
-        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk),
-        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick),
-        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick),
-        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k),
-        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk),
-        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk),
-        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick),
-        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick),
-        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick),
-        CLK(NULL,       "usim_ck",                      &usim_ck),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk),
-        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck),
-        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck),
-        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck),
-        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck),
-        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck),
-        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck),
-        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck),
-        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck),
-        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck),
-        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck),
-        CLK("50000000.gpmc",    "fck",                  &dummy_ck),
-        CLK("omap_i2c.1",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.2",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.3",       "ick",                  &dummy_ck),
-        CLK("omap_i2c.4",       "ick",                  &dummy_ck),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck),
-        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck),
-        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck),
-        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck),
-        CLK(NULL,       "uart1_ick",                    &dummy_ck),
-        CLK(NULL,       "uart2_ick",                    &dummy_ck),
-        CLK(NULL,       "uart3_ick",                    &dummy_ck),
-        CLK(NULL,       "uart4_ick",                    &dummy_ck),
-        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck),
-        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck),
-        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck),
-        CLK("omap_wdt", "ick",                          &dummy_ck),
-        CLK(NULL,       "timer_32k_ck", &sys_32k_ck),
-        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck),
-        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck),
-        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck),
-        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck),
-};
-
-int __init omap4xxx_clk_init(void)
-{
-        int rc;
-
-        if (cpu_is_omap443x()) {
-                cpu_mask = RATE_IN_4430;
-                omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
-        } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
-                cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-                omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
-                if (cpu_is_omap447x())
-                        pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
-        } else {
-                return 0;
-        }
-
-        omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
-
-        omap2_clk_disable_autoidle_all();
-
-        /*
-         * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
-         * when its in bypass. So always lock USB before ABE DPLL.
-         */
-        /*
-         * Lock USB DPLL on OMAP4 devices so that the L3INIT power
-         * domain can transition to retention state when not in use.
-         */
-        rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure USB DPLL!\n", __func__);
-
-        /*
-         * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
-         * state when turning the ABE clock domain. Workaround this by
-         * locking the ABE DPLL on boot.
-         * Lock the ABE DPLL in any case to avoid issues with audio.
-         */
-        rc = clk_set_parent(&abe_dpll_refclk_mux_ck, &sys_32k_ck);
-        if (!rc)
-                rc = clk_set_rate(&dpll_abe_ck, OMAP4_DPLL_ABE_DEFFREQ);
-        if (rc)
-                pr_err("%s: failed to configure ABE DPLL!\n", __func__);
-
-        return 0;
-}
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 0ec9f6fdf046..7ee26108ac0d 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,12 +97,12 @@ static void _write_clksel_reg(struct clk_hw_omap *clk, u32 field_val)
 {
         u32 v;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= ~clk->clksel_mask;
         v |= field_val << __ffs(clk->clksel_mask);
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 
-        v = __raw_readl(clk->clksel_reg); /* OCP barrier */
+        v = omap2_clk_readl(clk, clk->clksel_reg); /* OCP barrier */
 }
 
 /**
@@ -204,7 +204,7 @@ static u32 _read_divisor(struct clk_hw_omap *clk)
         if (!clk->clksel || !clk->clksel_mask)
                 return 0;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= clk->clksel_mask;
         v >>= __ffs(clk->clksel_mask);
 
@@ -320,7 +320,7 @@ u8 omap2_clksel_find_parent_index(struct clk_hw *hw)
         WARN((!clk->clksel || !clk->clksel_mask),
              "clock: %s: attempt to call on a non-clksel clock", clk_name);
 
-        r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
+        r = omap2_clk_readl(clk, clk->clksel_reg) & clk->clksel_mask;
         r >>= __ffs(clk->clksel_mask);
 
         for (clks = clk->clksel; clks->parent && !found; clks++) {
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 924c230f8948..47f9562ca7aa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -196,7 +196,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw)
         if (!dd)
                 return -EINVAL;
 
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
@@ -243,7 +243,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
                 return 0;
 
         /* Return bypass rate if DPLL is bypassed */
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
@@ -262,7 +262,7 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk)
                         return __clk_get_rate(dd->clk_bypass);
         }
 
-        v = __raw_readl(dd->mult_div1_reg);
+        v = omap2_clk_readl(clk, dd->mult_div1_reg);
         dpll_mult = v & dd->mult_mask;
         dpll_mult >>= __ffs(dd->mult_mask);
         dpll_div = v & dd->div1_mask;
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
index f10eb03ce3e2..333f0a666171 100644
--- a/arch/arm/mach-omap2/clkt_iclk.c
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -25,25 +25,29 @@
 /* XXX */
 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk)
 {
-        u32 v, r;
+        u32 v;
+        void __iomem *r;
 
-        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+        r = (__force void __iomem *)
+                ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-        v = __raw_readl((__force void __iomem *)r);
+        v = omap2_clk_readl(clk, r);
         v |= (1 << clk->enable_bit);
-        __raw_writel(v, (__force void __iomem *)r);
+        omap2_clk_writel(v, clk, r);
 }
 
 /* XXX */
 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk)
 {
-        u32 v, r;
+        u32 v;
+        void __iomem *r;
 
-        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+        r = (__force void __iomem *)
+                ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
 
-        v = __raw_readl((__force void __iomem *)r);
+        v = omap2_clk_readl(clk, r);
         v &= ~(1 << clk->enable_bit);
-        __raw_writel(v, (__force void __iomem *)r);
+        omap2_clk_writel(v, clk, r);
 }
 
 /* Public data */
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index c7c5d31e9082..591581a66532 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -26,7 +26,6 @@
 #include <linux/clk-private.h>
 #include <asm/cpu.h>
 
-
 #include <trace/events/power.h>
 
 #include "soc.h"
@@ -56,6 +55,31 @@ u16 cpu_mask;
 static bool clkdm_control = true;
 
 static LIST_HEAD(clk_hw_omap_clocks);
+void __iomem *clk_memmaps[CLK_MAX_MEMMAPS];
+
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg)
+{
+        if (clk->flags & MEMMAP_ADDRESSING) {
+                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+                writel_relaxed(val, clk_memmaps[r->index] + r->offset);
+        } else {
+                writel_relaxed(val, reg);
+        }
+}
+
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
+{
+        u32 val;
+
+        if (clk->flags & MEMMAP_ADDRESSING) {
+                struct clk_omap_reg *r = (struct clk_omap_reg *)&reg;
+                val = readl_relaxed(clk_memmaps[r->index] + r->offset);
+        } else {
+                val = readl_relaxed(reg);
+        }
+
+        return val;
+}
 
 /*
  * Used for clocks that have the same value as the parent clock,
@@ -87,6 +111,7 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 
 /**
  * _wait_idlest_generic - wait for a module to leave the idle state
+ * @clk: module clock to wait for (needed for register offsets)
  * @reg: virtual address of module IDLEST register
  * @mask: value to mask against to determine if the module is active
  * @idlest: idle state indicator (0 or 1) for the clock
@@ -98,14 +123,14 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
  * elapsed.  XXX Deprecated - should be moved into drivers for the
  * individual IP block that the IDLEST register exists in.
  */
-static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
-                                const char *name)
+static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg,
+                                u32 mask, u8 idlest, const char *name)
 {
         int i = 0, ena = 0;
 
         ena = (idlest) ? 0 : mask;
 
-        omap_test_timeout(((__raw_readl(reg) & mask) == ena),
+        omap_test_timeout(((omap2_clk_readl(clk, reg) & mask) == ena),
                           MAX_MODULE_ENABLE_WAIT, i);
 
         if (i < MAX_MODULE_ENABLE_WAIT)
@@ -138,7 +163,7 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
         /* Not all modules have multiple clocks that their IDLEST depends on */
         if (clk->ops->find_companion) {
                 clk->ops->find_companion(clk, &companion_reg, &other_bit);
-                if (!(__raw_readl(companion_reg) & (1 << other_bit)))
+                if (!(omap2_clk_readl(clk, companion_reg) & (1 << other_bit)))
                         return;
         }
 
@@ -146,8 +171,8 @@ static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
         r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
         if (r) {
                 /* IDLEST register not in the CM module */
-                _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
-                                     __clk_get_name(clk->hw.clk));
+                _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit),
+                                     idlest_val, __clk_get_name(clk->hw.clk));
         } else {
                 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
         };
@@ -309,13 +334,13 @@ int omap2_dflt_clk_enable(struct clk_hw *hw)
         }
 
         /* FIXME should not have INVERT_ENABLE bit here */
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
                 v &= ~(1 << clk->enable_bit);
         else
                 v |= (1 << clk->enable_bit);
-        __raw_writel(v, clk->enable_reg);
-        v = __raw_readl(clk->enable_reg); /* OCP barrier */
+        omap2_clk_writel(v, clk, clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg); /* OCP barrier */
 
         if (clk->ops && clk->ops->find_idlest)
                 _omap2_module_wait_ready(clk);
@@ -353,12 +378,12 @@ void omap2_dflt_clk_disable(struct clk_hw *hw)
                 return;
         }
 
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
         if (clk->flags & INVERT_ENABLE)
                 v |= (1 << clk->enable_bit);
         else
                 v &= ~(1 << clk->enable_bit);
-        __raw_writel(v, clk->enable_reg);
+        omap2_clk_writel(v, clk, clk->enable_reg);
         /* No OCP barrier needed here since it is a disable operation */
 
         if (clkdm_control && clk->clkdm)
@@ -454,7 +479,7 @@ int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
         struct clk_hw_omap *clk = to_clk_hw_omap(hw);
         u32 v;
 
-        v = __raw_readl(clk->enable_reg);
+        v = omap2_clk_readl(clk, clk->enable_reg);
 
         if (clk->flags & INVERT_ENABLE)
                 v ^= BIT(clk->enable_bit);
@@ -520,6 +545,9 @@ int omap2_clk_enable_autoidle_all(void)
         list_for_each_entry(c, &clk_hw_omap_clocks, node)
                 if (c->ops && c->ops->allow_idle)
                         c->ops->allow_idle(c);
+
+        of_ti_clk_allow_autoidle_all();
+
         return 0;
 }
 
@@ -539,6 +567,9 @@ int omap2_clk_disable_autoidle_all(void)
         list_for_each_entry(c, &clk_hw_omap_clocks, node)
                 if (c->ops && c->ops->deny_idle)
                         c->ops->deny_idle(c);
+
+        of_ti_clk_deny_autoidle_all();
+
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 82916cc82c92..bda767a9dea8 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
 
 #include <linux/clkdev.h>
 #include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 struct omap_clk {
         u16                             cpu;
@@ -37,7 +38,6 @@ struct omap_clk {
         }
 
 struct clockdomain;
-#define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
 #define DEFINE_STRUCT_CLK(_name, _parent_array_name, _clkops_name)      \
         static struct clk _name = {                             \
@@ -178,141 +178,6 @@ struct clksel {
         const struct clksel_rate *rates;
 };
 
-/**
- * struct dpll_data - DPLL registers and integration data
- * @mult_div1_reg: register containing the DPLL M and N bitfields
- * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
- * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
- * @clk_bypass: struct clk pointer to the clock's bypass clock input
- * @clk_ref: struct clk pointer to the clock's reference clock input
- * @control_reg: register containing the DPLL mode bitfield
- * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
- * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
- * @last_rounded_m4xen: cache of the last M4X result of
- *                      omap4_dpll_regm4xen_round_rate()
- * @last_rounded_lpmode: cache of the last lpmode result of
- *                       omap4_dpll_lpmode_recalc()
- * @max_multiplier: maximum valid non-bypass multiplier value (actual)
- * @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
- * @min_divider: minimum valid non-bypass divider value (actual)
- * @max_divider: maximum valid non-bypass divider value (actual)
- * @modes: possible values of @enable_mask
- * @autoidle_reg: register containing the DPLL autoidle mode bitfield
- * @idlest_reg: register containing the DPLL idle status bitfield
- * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
- * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
- * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
- * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
- * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
- * @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
- * @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
- * @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
- * @flags: DPLL type/features (see below)
- *
- * Possible values for @flags:
- * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
- *
- * @freqsel_mask is only used on the OMAP34xx family and AM35xx.
- *
- * XXX Some DPLLs have multiple bypass inputs, so it's not technically
- * correct to only have one @clk_bypass pointer.
- *
- * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
- * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a different structure, so that the runtime-fixed data
- * can be placed into read-only space.
- */
-struct dpll_data {
-        void __iomem            *mult_div1_reg;
-        u32                     mult_mask;
-        u32                     div1_mask;
-        struct clk              *clk_bypass;
-        struct clk              *clk_ref;
-        void __iomem            *control_reg;
-        u32                     enable_mask;
-        unsigned long           last_rounded_rate;
-        u16                     last_rounded_m;
-        u8                      last_rounded_m4xen;
-        u8                      last_rounded_lpmode;
-        u16                     max_multiplier;
-        u8                      last_rounded_n;
-        u8                      min_divider;
-        u16                     max_divider;
-        u8                      modes;
-        void __iomem            *autoidle_reg;
-        void __iomem            *idlest_reg;
-        u32                     autoidle_mask;
-        u32                     freqsel_mask;
-        u32                     idlest_mask;
-        u32                     dco_mask;
-        u32                     sddiv_mask;
-        u32                     lpmode_mask;
-        u32                     m4xen_mask;
-        u8                      auto_recal_bit;
-        u8                      recal_en_bit;
-        u8                      recal_st_bit;
-        u8                      flags;
-};
-
-/*
- * struct clk.flags possibilities
- *
- * XXX document the rest of the clock flags here
- *
- * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
- *     bits share the same register.  This flag allows the
- *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
- *     should be used.  This is a temporary solution - a better approach
- *     would be to associate clock type-specific data with the clock,
- *     similar to the struct dpll_data approach.
- */
-#define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
-#define CLOCK_IDLE_CONTROL      (1 << 1)
-#define CLOCK_NO_IDLE_PARENT    (1 << 2)
-#define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
-#define CLOCK_CLKOUTX2          (1 << 5)
-
-/**
- * struct clk_hw_omap - OMAP struct clk
- * @node: list_head connecting this clock into the full clock list
- * @enable_reg: register to write to enable the clock (see @enable_bit)
- * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
- * @flags: see "struct clk.flags possibilities" above
- * @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
- * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
- * @clkdm_name: clockdomain name that this clock is contained in
- * @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
- * @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
- * @src_offset: bitshift for source selection bitfield (OMAP1 only)
- *
- * XXX @rate_offset, @src_offset should probably be removed and OMAP1
- * clock code converted to use clksel.
- *
- */
-
-struct clk_hw_omap_ops;
-
-struct clk_hw_omap {
-        struct clk_hw           hw;
-        struct list_head        node;
-        unsigned long           fixed_rate;
-        u8                      fixed_div;
-        void __iomem            *enable_reg;
-        u8                      enable_bit;
-        u8                      flags;
-        void __iomem            *clksel_reg;
-        u32                     clksel_mask;
-        const struct clksel     *clksel;
-        struct dpll_data        *dpll_data;
-        const char              *clkdm_name;
-        struct clockdomain      *clkdm;
-        const struct clk_hw_omap_ops    *ops;
-};
-
 struct clk_hw_omap_ops {
         void                    (*find_idlest)(struct clk_hw_omap *oclk,
                                         void __iomem **idlest_reg,
@@ -348,36 +213,13 @@ unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
 #define OMAP4XXX_EN_DPLL_FRBYPASS               0x6
 #define OMAP4XXX_EN_DPLL_LOCKED                 0x7
 
-/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
-#define DPLL_LOW_POWER_STOP     0x1
-#define DPLL_LOW_POWER_BYPASS   0x5
-#define DPLL_LOCKED             0x7
-
-/* DPLL Type and DCO Selection Flags */
-#define DPLL_J_TYPE             0x1
-
-long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
-                        unsigned long *parent_rate);
-unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
-int omap3_noncore_dpll_enable(struct clk_hw *hw);
-void omap3_noncore_dpll_disable(struct clk_hw *hw);
-int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
-                                unsigned long parent_rate);
 u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
 void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
 void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
-unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
-                                    unsigned long parent_rate);
 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk);
 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk);
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk);
-unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
-                                unsigned long parent_rate);
-long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
-                                    unsigned long target_rate,
-                                    unsigned long *parent_rate);
 
-void omap2_init_clk_clkdm(struct clk_hw *clk);
 void __init omap2_clk_disable_clkdm_control(void);
 
 /* clkt_clksel.c public functions */
@@ -396,29 +238,25 @@ int omap2_clksel_set_parent(struct clk_hw *hw, u8 field_val);
 extern void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
 extern void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
 
-u8 omap2_init_dpll_parent(struct clk_hw *hw);
 unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
 
-int omap2_dflt_clk_enable(struct clk_hw *hw);
-void omap2_dflt_clk_disable(struct clk_hw *hw);
-int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
                                    void __iomem **other_reg,
                                    u8 *other_bit);
 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
                                 void __iomem **idlest_reg,
                                 u8 *idlest_bit, u8 *idlest_val);
-void omap2_init_clk_hw_omap_clocks(struct clk *clk);
 int omap2_clk_enable_autoidle_all(void);
-int omap2_clk_disable_autoidle_all(void);
 int omap2_clk_allow_idle(struct clk *clk);
 int omap2_clk_deny_idle(struct clk *clk);
-void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
 int omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name);
 void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
                                const char *core_ck_name,
                                const char *mpu_ck_name);
 
+u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg);
+void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg);
+
 extern u16 cpu_mask;
 
 extern const struct clkops clkops_omap2_dflt_wait;
@@ -433,19 +271,12 @@ extern const struct clksel_rate gfx_l3_rates[];
 extern const struct clksel_rate dsp_ick_rates[];
 extern struct clk dummy_ck;
 
-extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
 extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
 extern const struct clk_hw_omap_ops clkhwops_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
-extern const struct clk_hw_omap_ops clkhwops_iclk;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_ssi_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
-extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_omap3430es2_hsotgusb_wait;
 extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
-extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
 extern const struct clk_hw_omap_ops clkhwops_apll54;
 extern const struct clk_hw_omap_ops clkhwops_apll96;
 extern const struct clk_hw_omap_ops clkhwops_omap2xxx_dpll;
@@ -460,6 +291,8 @@ extern const struct clksel_rate div_1_3_rates[];
 extern const struct clksel_rate div_1_4_rates[];
 extern const struct clksel_rate div31_1to31_rates[];
 
+extern void __iomem *clk_memmaps[];
+
 extern int am33xx_clk_init(void);
 
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/clock36xx.c b/arch/arm/mach-omap2/clock36xx.c
index bbd6a3f717e6..91ccb962e09e 100644
--- a/arch/arm/mach-omap2/clock36xx.c
+++ b/arch/arm/mach-omap2/clock36xx.c
@@ -43,6 +43,7 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
         struct clk_divider *parent;
         struct clk_hw *parent_hw;
         u32 dummy_v, orig_v;
+        struct clk_hw_omap *omap_clk = to_clk_hw_omap(clk);
         int ret;
 
         /* Clear PWRDN bit of HSDIVIDER */
@@ -53,15 +54,15 @@ int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
 
         /* Restore the dividers */
         if (!ret) {
-                orig_v = __raw_readl(parent->reg);
+                orig_v = omap2_clk_readl(omap_clk, parent->reg);
                 dummy_v = orig_v;
 
                 /* Write any other value different from the Read value */
                 dummy_v ^= (1 << parent->shift);
-                __raw_writel(dummy_v, parent->reg);
+                omap2_clk_writel(dummy_v, omap_clk, parent->reg);
 
                 /* Write the original divider */
-                __raw_writel(orig_v, parent->reg);
+                omap2_clk_writel(orig_v, omap_clk, parent->reg);
         }
 
         return ret;
diff --git a/arch/arm/mach-omap2/clock3xxx.h b/arch/arm/mach-omap2/clock3xxx.h
index 8cd4b0a882ae..78d9f562e3ce 100644
--- a/arch/arm/mach-omap2/clock3xxx.h
+++ b/arch/arm/mach-omap2/clock3xxx.h
@@ -9,11 +9,8 @@
 #define __ARCH_ARM_MACH_OMAP2_CLOCK3XXX_H
 
 int omap3xxx_clk_init(void);
-int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
-                                        unsigned long parent_rate);
 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
                                         unsigned long parent_rate);
-void omap3_clk_lock_dpll5(void);
 
 extern struct clk *sdrc_ick_p;
 extern struct clk *arm_fck_p;
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 240db38f232c..e51527835160 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -306,7 +306,7 @@ struct omap_hwmod;
 extern int omap_dss_reset(struct omap_hwmod *);
 
 /* SoC specific clock initializer */
-extern int (*omap_clk_init)(void);
+int omap_clk_init(void);
 
 #endif /* __ASSEMBLER__ */
 #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 3a0296cfcace..3185ced807c9 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -50,10 +50,10 @@ static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits)
 
         dd = clk->dpll_data;
 
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         v &= ~dd->enable_mask;
         v |= clken_bits << __ffs(dd->enable_mask);
-        __raw_writel(v, dd->control_reg);
+        omap2_clk_writel(v, clk, dd->control_reg);
 }
 
 /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
@@ -69,8 +69,8 @@ static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state)
 
         state <<= __ffs(dd->idlest_mask);
 
-        while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) &&
-               i < MAX_DPLL_WAIT_TRIES) {
+        while (((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask)
+                != state) && i < MAX_DPLL_WAIT_TRIES) {
                 i++;
                 udelay(1);
         }
@@ -147,7 +147,7 @@ static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk)
         state <<= __ffs(dd->idlest_mask);
 
         /* Check if already locked */
-        if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state)
+        if ((omap2_clk_readl(clk, dd->idlest_reg) & dd->idlest_mask) == state)
                 goto done;
 
         ai = omap3_dpll_autoidle_read(clk);
@@ -311,14 +311,14 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
          * only since freqsel field is no longer present on other devices.
          */
         if (cpu_is_omap343x()) {
-                v = __raw_readl(dd->control_reg);
+                v = omap2_clk_readl(clk, dd->control_reg);
                 v &= ~dd->freqsel_mask;
                 v |= freqsel << __ffs(dd->freqsel_mask);
-                __raw_writel(v, dd->control_reg);
+                omap2_clk_writel(v, clk, dd->control_reg);
         }
 
         /* Set DPLL multiplier, divider */
-        v = __raw_readl(dd->mult_div1_reg);
+        v = omap2_clk_readl(clk, dd->mult_div1_reg);
         v &= ~(dd->mult_mask | dd->div1_mask);
         v |= dd->last_rounded_m << __ffs(dd->mult_mask);
         v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
@@ -336,11 +336,11 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
                 v |= sd_div << __ffs(dd->sddiv_mask);
         }
 
-        __raw_writel(v, dd->mult_div1_reg);
+        omap2_clk_writel(v, clk, dd->mult_div1_reg);
 
         /* Set 4X multiplier and low-power mode */
         if (dd->m4xen_mask || dd->lpmode_mask) {
-                v = __raw_readl(dd->control_reg);
+                v = omap2_clk_readl(clk, dd->control_reg);
 
                 if (dd->m4xen_mask) {
                         if (dd->last_rounded_m4xen)
@@ -356,7 +356,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
                                 v &= ~dd->lpmode_mask;
                 }
 
-                __raw_writel(v, dd->control_reg);
+                omap2_clk_writel(v, clk, dd->control_reg);
         }
 
         /* We let the clock framework set the other output dividers later */
@@ -554,7 +554,7 @@ u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk)
         if (!dd->autoidle_reg)
                 return -EINVAL;
 
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= dd->autoidle_mask;
         v >>= __ffs(dd->autoidle_mask);
 
@@ -588,10 +588,10 @@ void omap3_dpll_allow_idle(struct clk_hw_omap *clk)
          * by writing 0x5 instead of 0x1.  Add some mechanism to
          * optionally enter this mode.
          */
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
+        omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -614,10 +614,10 @@ void omap3_dpll_deny_idle(struct clk_hw_omap *clk)
         if (!dd->autoidle_reg)
                 return;
 
-        v = __raw_readl(dd->autoidle_reg);
+        v = omap2_clk_readl(clk, dd->autoidle_reg);
         v &= ~dd->autoidle_mask;
         v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask);
-        __raw_writel(v, dd->autoidle_reg);
+        omap2_clk_writel(v, clk, dd->autoidle_reg);
 
 }
 
@@ -639,6 +639,9 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
         struct clk_hw_omap *pclk = NULL;
         struct clk *parent;
 
+        if (!parent_rate)
+                return 0;
+
         /* Walk up the parents of clk, looking for a DPLL */
         do {
                 do {
@@ -660,7 +663,7 @@ unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
 
         WARN_ON(!dd->enable_mask);
 
-        v = __raw_readl(dd->control_reg) & dd->enable_mask;
+        v = omap2_clk_readl(pclk, dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
                 rate = parent_rate;
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
index d28b0f726715..52f9438b92f2 100644
--- a/arch/arm/mach-omap2/dpll44xx.c
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -42,7 +42,7 @@ int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         v &= mask;
         v >>= __ffs(mask);
 
@@ -61,10 +61,10 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         /* Clear the bit to allow gatectrl */
         v &= ~mask;
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
@@ -79,10 +79,10 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
                         OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
                         OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
 
-        v = __raw_readl(clk->clksel_reg);
+        v = omap2_clk_readl(clk, clk->clksel_reg);
         /* Set the bit to deny gatectrl */
         v |= mask;
-        __raw_writel(v, clk->clksel_reg);
+        omap2_clk_writel(v, clk, clk->clksel_reg);
 }
 
 const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
@@ -140,7 +140,7 @@ unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
         rate = omap2_get_dpll_rate(clk);
 
         /* regm4xen adds a multiplier of 4 to DPLL calculations */
-        v = __raw_readl(dd->control_reg);
+        v = omap2_clk_readl(clk, dd->control_reg);
         if (v & OMAP4430_DPLL_REGM4XEN_MASK)
                 rate *= OMAP4430_REGM4XEN_MULT;
 
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 07b68d5a7940..47381fd8746f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -55,10 +55,10 @@
 #include "prm44xx.h"
 
 /*
- * omap_clk_init: points to a function that does the SoC-specific
+ * omap_clk_soc_init: points to a function that does the SoC-specific
  * clock initializations
  */
-int (*omap_clk_init)(void);
+static int (*omap_clk_soc_init)(void);
 
 /*
  * The machine specific code may provide the extra mapping besides the
@@ -419,7 +419,7 @@ void __init omap2420_init_early(void)
         omap242x_clockdomains_init();
         omap2420_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap2420_clk_init;
+        omap_clk_soc_init = omap2420_clk_init;
 }
 
 void __init omap2420_init_late(void)
@@ -448,7 +448,7 @@ void __init omap2430_init_early(void)
         omap243x_clockdomains_init();
         omap2430_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap2430_clk_init;
+        omap_clk_soc_init = omap2430_clk_init;
 }
 
 void __init omap2430_init_late(void)
@@ -482,27 +482,35 @@ void __init omap3_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap3xxx_clk_init;
+        omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3430_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap35xx_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3430_dt_clk_init;
 }
 
 void __init omap3630_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = omap3630_dt_clk_init;
 }
 
 void __init am35xx_init_early(void)
 {
         omap3_init_early();
+        if (of_have_populated_dt())
+                omap_clk_soc_init = am35xx_dt_clk_init;
 }
 
 void __init ti81xx_init_early(void)
@@ -520,7 +528,10 @@ void __init ti81xx_init_early(void)
         omap3xxx_clockdomains_init();
         omap3xxx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap3xxx_clk_init;
+        if (of_have_populated_dt())
+                omap_clk_soc_init = ti81xx_dt_clk_init;
+        else
+                omap_clk_soc_init = omap3xxx_clk_init;
 }
 
 void __init omap3_init_late(void)
@@ -581,7 +592,7 @@ void __init am33xx_init_early(void)
         am33xx_clockdomains_init();
         am33xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = am33xx_clk_init;
+        omap_clk_soc_init = am33xx_dt_clk_init;
 }
 
 void __init am33xx_init_late(void)
@@ -606,6 +617,7 @@ void __init am43xx_init_early(void)
         am43xx_clockdomains_init();
         am43xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = am43xx_dt_clk_init;
 }
 
 void __init am43xx_init_late(void)
@@ -635,7 +647,7 @@ void __init omap4430_init_early(void)
         omap44xx_clockdomains_init();
         omap44xx_hwmod_init();
         omap_hwmod_init_postsetup();
-        omap_clk_init = omap4xxx_clk_init;
+        omap_clk_soc_init = omap4xxx_dt_clk_init;
 }
 
 void __init omap4430_init_late(void)
@@ -666,6 +678,7 @@ void __init omap5_init_early(void)
         omap54xx_clockdomains_init();
         omap54xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = omap5xxx_dt_clk_init;
 }
 
 void __init omap5_init_late(void)
@@ -691,6 +704,7 @@ void __init dra7xx_init_early(void)
         dra7xx_clockdomains_init();
         dra7xx_hwmod_init();
         omap_hwmod_init_postsetup();
+        omap_clk_soc_init = dra7xx_dt_clk_init;
 }
 
 void __init dra7xx_init_late(void)
@@ -710,3 +724,17 @@ void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                 _omap2_init_reprogram_sdrc();
         }
 }
+
+int __init omap_clk_init(void)
+{
+        int ret = 0;
+
+        if (!omap_clk_soc_init)
+                return 0;
+
+        ret = of_prcm_init();
+        if (!ret)
+                ret = omap_clk_soc_init();
+
+        return ret;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index f7a6fd35b1e4..42d81885c700 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -686,6 +686,8 @@ static struct clockdomain *_get_clkdm(struct omap_hwmod *oh)
         if (oh->clkdm) {
                 return oh->clkdm;
         } else if (oh->_clk) {
+                if (__clk_get_flags(oh->_clk) & CLK_IS_BASIC)
+                        return NULL;
                 clk = to_clk_hw_omap(__clk_get_hw(oh->_clk));
                 return  clk->clkdm;
         }
@@ -1576,7 +1578,7 @@ static int _init_clkdm(struct omap_hwmod *oh)
         if (!oh->clkdm) {
                 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
                         oh->name, oh->clkdm_name);
-                return -EINVAL;
+                return 0;
         }
 
         pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
@@ -4231,6 +4233,7 @@ void __init omap_hwmod_init(void)
                 soc_ops.assert_hardreset = _omap2_assert_hardreset;
                 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
                 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
         } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
                 soc_ops.enable_module = _omap4_enable_module;
                 soc_ops.disable_module = _omap4_disable_module;
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index ac25ae6667cf..623db40fdbbd 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -18,6 +18,7 @@
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
 extern void omap2_set_globals_prm(void __iomem *prm);
+int of_prcm_init(void);
 # endif
 
 
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index a2e1174ad1b6..b4c4ab9c8044 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -23,6 +23,10 @@
 #include <linux/irq.h>
 #include <linux/interrupt.h>
 #include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk-provider.h>
+#include <linux/clk/ti.h>
 
 #include "soc.h"
 #include "prm2xxx_3xxx.h"
@@ -30,6 +34,7 @@
 #include "prm3xxx.h"
 #include "prm44xx.h"
 #include "common.h"
+#include "clock.h"
 
 /*
  * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
@@ -464,3 +469,64 @@ int prm_unregister(struct prm_ll_data *pld)
 
         return 0;
 }
+
+static struct of_device_id omap_prcm_dt_match_table[] = {
+        { .compatible = "ti,am3-prcm" },
+        { .compatible = "ti,am3-scrm" },
+        { .compatible = "ti,am4-prcm" },
+        { .compatible = "ti,am4-scrm" },
+        { .compatible = "ti,omap3-prm" },
+        { .compatible = "ti,omap3-cm" },
+        { .compatible = "ti,omap3-scrm" },
+        { .compatible = "ti,omap4-cm1" },
+        { .compatible = "ti,omap4-prm" },
+        { .compatible = "ti,omap4-cm2" },
+        { .compatible = "ti,omap4-scrm" },
+        { .compatible = "ti,omap5-prm" },
+        { .compatible = "ti,omap5-cm-core-aon" },
+        { .compatible = "ti,omap5-scrm" },
+        { .compatible = "ti,omap5-cm-core" },
+        { .compatible = "ti,dra7-prm" },
+        { .compatible = "ti,dra7-cm-core-aon" },
+        { .compatible = "ti,dra7-cm-core" },
+        { }
+};
+
+static struct clk_hw_omap memmap_dummy_ck = {
+        .flags = MEMMAP_ADDRESSING,
+};
+
+static u32 prm_clk_readl(void __iomem *reg)
+{
+        return omap2_clk_readl(&memmap_dummy_ck, reg);
+}
+
+static void prm_clk_writel(u32 val, void __iomem *reg)
+{
+        omap2_clk_writel(val, &memmap_dummy_ck, reg);
+}
+
+static struct ti_clk_ll_ops omap_clk_ll_ops = {
+        .clk_readl = prm_clk_readl,
+        .clk_writel = prm_clk_writel,
+};
+
+int __init of_prcm_init(void)
+{
+        struct device_node *np;
+        void __iomem *mem;
+        int memmap_index = 0;
+
+        ti_clk_ll_ops = &omap_clk_ll_ops;
+
+        for_each_matching_node(np, omap_prcm_dt_match_table) {
+                mem = of_iomap(np, 0);
+                clk_memmaps[memmap_index] = mem;
+                ti_dt_clk_init_provider(np, memmap_index);
+                memmap_index++;
+        }
+
+        ti_dt_clockdomains_setup();
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ec084d158f64..74044aaf438b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -570,8 +570,7 @@ static inline void __init realtime_counter_init(void)
                                clksrc_nr, clksrc_src, clksrc_prop)      \
 void __init omap##name##_gptimer_timer_init(void)                       \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
+        omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src,         \
@@ -582,8 +581,7 @@ void __init omap##name##_gptimer_timer_init(void)			\
                                 clksrc_nr, clksrc_src, clksrc_prop)     \
 void __init omap##name##_sync32k_timer_init(void)               \
 {                                                                       \
-        if (omap_clk_init)                                              \
-                omap_clk_init();                                        \
+        omap_clk_init();                                        \
         omap_dmtimer_init();                                            \
         omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop);    \
         /* Enable the use of clocksource="gp_timer" kernel parameter */ \