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-rw-r--r--arch/microblaze/Kconfig54
-rw-r--r--arch/microblaze/Kconfig.platform (renamed from arch/microblaze/platform/Kconfig.platform)55
-rw-r--r--arch/microblaze/Makefile1
-rw-r--r--[l---------]arch/microblaze/boot/dts/system.dts367
-rw-r--r--arch/microblaze/include/asm/io.h302
-rw-r--r--arch/microblaze/include/asm/processor.h2
-rw-r--r--arch/microblaze/include/asm/setup.h6
-rw-r--r--arch/microblaze/include/uapi/asm/unistd.h6
-rw-r--r--arch/microblaze/kernel/Makefile2
-rw-r--r--arch/microblaze/kernel/heartbeat.c4
-rw-r--r--arch/microblaze/kernel/intc.c51
-rw-r--r--arch/microblaze/kernel/platform.c (renamed from arch/microblaze/platform/platform.c)0
-rw-r--r--arch/microblaze/kernel/process.c1
-rw-r--r--arch/microblaze/kernel/signal.c2
-rw-r--r--arch/microblaze/kernel/syscall_table.S8
-rw-r--r--arch/microblaze/kernel/timer.c66
-rw-r--r--arch/microblaze/mm/consistent.c2
-rw-r--r--arch/microblaze/mm/init.c2
-rw-r--r--arch/microblaze/mm/pgtable.c5
-rw-r--r--arch/microblaze/platform/Makefile6
-rw-r--r--arch/microblaze/platform/generic/Kconfig.auto61
-rw-r--r--arch/microblaze/platform/generic/Makefile3
-rw-r--r--arch/microblaze/platform/generic/system.dts366
23 files changed, 558 insertions, 814 deletions
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 79b9bcdfe498..9ae08541e30d 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -1,38 +1,38 @@
1config MICROBLAZE 1config MICROBLAZE
2 def_bool y 2 def_bool y
3 select ARCH_MIGHT_HAVE_PC_PARPORT 3 select ARCH_MIGHT_HAVE_PC_PARPORT
4 select HAVE_MEMBLOCK
5 select HAVE_MEMBLOCK_NODE_MAP
6 select HAVE_FUNCTION_TRACER
7 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
8 select HAVE_FUNCTION_GRAPH_TRACER
9 select HAVE_DYNAMIC_FTRACE
10 select HAVE_FTRACE_MCOUNT_RECORD
11 select ARCH_WANT_OPTIONAL_GPIOLIB
12 select HAVE_OPROFILE
13 select HAVE_ARCH_KGDB
14 select HAVE_DMA_ATTRS
15 select HAVE_DMA_API_DEBUG
16 select TRACING_SUPPORT
17 select OF
18 select OF_EARLY_FLATTREE
19 select ARCH_WANT_IPC_PARSE_VERSION 4 select ARCH_WANT_IPC_PARSE_VERSION
20 select HAVE_DEBUG_KMEMLEAK 5 select ARCH_WANT_OPTIONAL_GPIOLIB
21 select IRQ_DOMAIN 6 select BUILDTIME_EXTABLE_SORT
22 select VIRT_TO_BUS 7 select CLKSRC_OF
8 select CLONE_BACKWARDS3
9 select COMMON_CLK
10 select GENERIC_ATOMIC64
11 select GENERIC_CLOCKEVENTS
12 select GENERIC_CPU_DEVICES
13 select GENERIC_IDLE_POLL_SETUP
23 select GENERIC_IRQ_PROBE 14 select GENERIC_IRQ_PROBE
24 select GENERIC_IRQ_SHOW 15 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP 16 select GENERIC_PCI_IOMAP
26 select GENERIC_CPU_DEVICES
27 select GENERIC_ATOMIC64
28 select GENERIC_CLOCKEVENTS
29 select COMMON_CLK
30 select GENERIC_SCHED_CLOCK 17 select GENERIC_SCHED_CLOCK
31 select GENERIC_IDLE_POLL_SETUP 18 select HAVE_ARCH_KGDB
19 select HAVE_DEBUG_KMEMLEAK
20 select HAVE_DMA_API_DEBUG
21 select HAVE_DMA_ATTRS
22 select HAVE_DYNAMIC_FTRACE
23 select HAVE_FTRACE_MCOUNT_RECORD
24 select HAVE_FUNCTION_GRAPH_TRACER
25 select HAVE_FUNCTION_TRACE_MCOUNT_TEST
26 select HAVE_FUNCTION_TRACER
27 select HAVE_MEMBLOCK
28 select HAVE_MEMBLOCK_NODE_MAP
29 select HAVE_OPROFILE
30 select IRQ_DOMAIN
32 select MODULES_USE_ELF_RELA 31 select MODULES_USE_ELF_RELA
33 select CLONE_BACKWARDS3 32 select OF
34 select CLKSRC_OF 33 select OF_EARLY_FLATTREE
35 select BUILDTIME_EXTABLE_SORT 34 select TRACING_SUPPORT
35 select VIRT_TO_BUS
36 36
37config SWAP 37config SWAP
38 def_bool n 38 def_bool n
@@ -74,7 +74,7 @@ source "init/Kconfig"
74 74
75source "kernel/Kconfig.freezer" 75source "kernel/Kconfig.freezer"
76 76
77source "arch/microblaze/platform/Kconfig.platform" 77source "arch/microblaze/Kconfig.platform"
78 78
79menu "Processor type and features" 79menu "Processor type and features"
80 80
diff --git a/arch/microblaze/platform/Kconfig.platform b/arch/microblaze/Kconfig.platform
index db1aa5c22cea..1b3d8c849101 100644
--- a/arch/microblaze/platform/Kconfig.platform
+++ b/arch/microblaze/Kconfig.platform
@@ -5,18 +5,6 @@
5# 5#
6 6
7menu "Platform options" 7menu "Platform options"
8choice
9 prompt "Platform"
10 default PLATFORM_MICROBLAZE_AUTO
11 help
12 Choose which hardware board/platform you are targeting.
13
14config PLATFORM_GENERIC
15 bool "Generic"
16 help
17 Choose this option for the Generic platform.
18
19endchoice
20 8
21config OPT_LIB_FUNCTION 9config OPT_LIB_FUNCTION
22 bool "Optimalized lib function" 10 bool "Optimalized lib function"
@@ -37,8 +25,45 @@ config OPT_LIB_ASM
37 Allows turn on optimalized library function (memcpy and memmove). 25 Allows turn on optimalized library function (memcpy and memmove).
38 Function are written in asm code. 26 Function are written in asm code.
39 27
40if PLATFORM_GENERIC=y 28# Definitions for MICROBLAZE0
41 source "arch/microblaze/platform/generic/Kconfig.auto" 29comment "Definitions for MICROBLAZE0"
42endif 30
31config KERNEL_BASE_ADDR
32 hex "Physical address where Linux Kernel is"
33 default "0x90000000"
34 help
35 BASE Address for kernel
36
37config XILINX_MICROBLAZE0_FAMILY
38 string "Targeted FPGA family"
39 default "virtex5"
40
41config XILINX_MICROBLAZE0_USE_MSR_INSTR
42 int "USE_MSR_INSTR range (0:1)"
43 default 0
44
45config XILINX_MICROBLAZE0_USE_PCMP_INSTR
46 int "USE_PCMP_INSTR range (0:1)"
47 default 0
48
49config XILINX_MICROBLAZE0_USE_BARREL
50 int "USE_BARREL range (0:1)"
51 default 0
52
53config XILINX_MICROBLAZE0_USE_DIV
54 int "USE_DIV range (0:1)"
55 default 0
56
57config XILINX_MICROBLAZE0_USE_HW_MUL
58 int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
59 default 0
60
61config XILINX_MICROBLAZE0_USE_FPU
62 int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
63 default 0
64
65config XILINX_MICROBLAZE0_HW_VER
66 string "Core version number"
67 default 7.10.d
43 68
44endmenu 69endmenu
diff --git a/arch/microblaze/Makefile b/arch/microblaze/Makefile
index a69eaf2ab130..740f2b82a182 100644
--- a/arch/microblaze/Makefile
+++ b/arch/microblaze/Makefile
@@ -48,7 +48,6 @@ head-y := arch/microblaze/kernel/head.o
48libs-y += arch/microblaze/lib/ 48libs-y += arch/microblaze/lib/
49core-y += arch/microblaze/kernel/ 49core-y += arch/microblaze/kernel/
50core-y += arch/microblaze/mm/ 50core-y += arch/microblaze/mm/
51core-y += arch/microblaze/platform/
52core-$(CONFIG_PCI) += arch/microblaze/pci/ 51core-$(CONFIG_PCI) += arch/microblaze/pci/
53 52
54drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/ 53drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
diff --git a/arch/microblaze/boot/dts/system.dts b/arch/microblaze/boot/dts/system.dts
index 7cb657892f21..b620da23febb 120000..100644
--- a/arch/microblaze/boot/dts/system.dts
+++ b/arch/microblaze/boot/dts/system.dts
@@ -1 +1,366 @@
1../../platform/generic/system.dts \ No newline at end of file 1/*
2 * Device Tree Generator version: 1.1
3 *
4 * (C) Copyright 2007-2008 Xilinx, Inc.
5 * (C) Copyright 2007-2009 Michal Simek
6 *
7 * Michal SIMEK <monstr@monstr.eu>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * CAUTION: This file is automatically generated by libgen.
25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
26 *
27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
28 */
29
30/dts-v1/;
31/ {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "xlnx,microblaze";
35 hard-reset-gpios = <&LEDs_8Bit 2 1>;
36 model = "testing";
37 DDR2_SDRAM: memory@90000000 {
38 device_type = "memory";
39 reg = < 0x90000000 0x10000000 >;
40 } ;
41 aliases {
42 ethernet0 = &Hard_Ethernet_MAC;
43 serial0 = &RS232_Uart_1;
44 } ;
45 chosen {
46 bootargs = "console=ttyUL0,115200 highres=on";
47 linux,stdout-path = "/plb@0/serial@84000000";
48 } ;
49 cpus {
50 #address-cells = <1>;
51 #cpus = <0x1>;
52 #size-cells = <0>;
53 microblaze_0: cpu@0 {
54 clock-frequency = <125000000>;
55 compatible = "xlnx,microblaze-7.10.d";
56 d-cache-baseaddr = <0x90000000>;
57 d-cache-highaddr = <0x9fffffff>;
58 d-cache-line-size = <0x10>;
59 d-cache-size = <0x2000>;
60 device_type = "cpu";
61 i-cache-baseaddr = <0x90000000>;
62 i-cache-highaddr = <0x9fffffff>;
63 i-cache-line-size = <0x10>;
64 i-cache-size = <0x2000>;
65 model = "microblaze,7.10.d";
66 reg = <0>;
67 timebase-frequency = <125000000>;
68 xlnx,addr-tag-bits = <0xf>;
69 xlnx,allow-dcache-wr = <0x1>;
70 xlnx,allow-icache-wr = <0x1>;
71 xlnx,area-optimized = <0x0>;
72 xlnx,cache-byte-size = <0x2000>;
73 xlnx,d-lmb = <0x1>;
74 xlnx,d-opb = <0x0>;
75 xlnx,d-plb = <0x1>;
76 xlnx,data-size = <0x20>;
77 xlnx,dcache-addr-tag = <0xf>;
78 xlnx,dcache-always-used = <0x1>;
79 xlnx,dcache-byte-size = <0x2000>;
80 xlnx,dcache-line-len = <0x4>;
81 xlnx,dcache-use-fsl = <0x1>;
82 xlnx,debug-enabled = <0x1>;
83 xlnx,div-zero-exception = <0x1>;
84 xlnx,dopb-bus-exception = <0x0>;
85 xlnx,dynamic-bus-sizing = <0x1>;
86 xlnx,edge-is-positive = <0x1>;
87 xlnx,family = "virtex5";
88 xlnx,endianness = <0x1>;
89 xlnx,fpu-exception = <0x1>;
90 xlnx,fsl-data-size = <0x20>;
91 xlnx,fsl-exception = <0x0>;
92 xlnx,fsl-links = <0x0>;
93 xlnx,i-lmb = <0x1>;
94 xlnx,i-opb = <0x0>;
95 xlnx,i-plb = <0x1>;
96 xlnx,icache-always-used = <0x1>;
97 xlnx,icache-line-len = <0x4>;
98 xlnx,icache-use-fsl = <0x1>;
99 xlnx,ill-opcode-exception = <0x1>;
100 xlnx,instance = "microblaze_0";
101 xlnx,interconnect = <0x1>;
102 xlnx,interrupt-is-edge = <0x0>;
103 xlnx,iopb-bus-exception = <0x0>;
104 xlnx,mmu-dtlb-size = <0x4>;
105 xlnx,mmu-itlb-size = <0x2>;
106 xlnx,mmu-tlb-access = <0x3>;
107 xlnx,mmu-zones = <0x10>;
108 xlnx,number-of-pc-brk = <0x1>;
109 xlnx,number-of-rd-addr-brk = <0x0>;
110 xlnx,number-of-wr-addr-brk = <0x0>;
111 xlnx,opcode-0x0-illegal = <0x1>;
112 xlnx,pvr = <0x2>;
113 xlnx,pvr-user1 = <0x0>;
114 xlnx,pvr-user2 = <0x0>;
115 xlnx,reset-msr = <0x0>;
116 xlnx,sco = <0x0>;
117 xlnx,unaligned-exceptions = <0x1>;
118 xlnx,use-barrel = <0x1>;
119 xlnx,use-dcache = <0x1>;
120 xlnx,use-div = <0x1>;
121 xlnx,use-ext-brk = <0x1>;
122 xlnx,use-ext-nm-brk = <0x1>;
123 xlnx,use-extended-fsl-instr = <0x0>;
124 xlnx,use-fpu = <0x2>;
125 xlnx,use-hw-mul = <0x2>;
126 xlnx,use-icache = <0x1>;
127 xlnx,use-interrupt = <0x1>;
128 xlnx,use-mmu = <0x3>;
129 xlnx,use-msr-instr = <0x1>;
130 xlnx,use-pcmp-instr = <0x1>;
131 } ;
132 } ;
133 mb_plb: plb@0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
137 ranges ;
138 FLASH: flash@a0000000 {
139 bank-width = <2>;
140 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
141 reg = < 0xa0000000 0x2000000 >;
142 xlnx,family = "virtex5";
143 xlnx,include-datawidth-matching-0 = <0x1>;
144 xlnx,include-datawidth-matching-1 = <0x0>;
145 xlnx,include-datawidth-matching-2 = <0x0>;
146 xlnx,include-datawidth-matching-3 = <0x0>;
147 xlnx,include-negedge-ioregs = <0x0>;
148 xlnx,include-plb-ipif = <0x1>;
149 xlnx,include-wrbuf = <0x1>;
150 xlnx,max-mem-width = <0x10>;
151 xlnx,mch-native-dwidth = <0x20>;
152 xlnx,mch-plb-clk-period-ps = <0x1f40>;
153 xlnx,mch-splb-awidth = <0x20>;
154 xlnx,mch0-accessbuf-depth = <0x10>;
155 xlnx,mch0-protocol = <0x0>;
156 xlnx,mch0-rddatabuf-depth = <0x10>;
157 xlnx,mch1-accessbuf-depth = <0x10>;
158 xlnx,mch1-protocol = <0x0>;
159 xlnx,mch1-rddatabuf-depth = <0x10>;
160 xlnx,mch2-accessbuf-depth = <0x10>;
161 xlnx,mch2-protocol = <0x0>;
162 xlnx,mch2-rddatabuf-depth = <0x10>;
163 xlnx,mch3-accessbuf-depth = <0x10>;
164 xlnx,mch3-protocol = <0x0>;
165 xlnx,mch3-rddatabuf-depth = <0x10>;
166 xlnx,mem0-width = <0x10>;
167 xlnx,mem1-width = <0x20>;
168 xlnx,mem2-width = <0x20>;
169 xlnx,mem3-width = <0x20>;
170 xlnx,num-banks-mem = <0x1>;
171 xlnx,num-channels = <0x0>;
172 xlnx,priority-mode = <0x0>;
173 xlnx,synch-mem-0 = <0x0>;
174 xlnx,synch-mem-1 = <0x0>;
175 xlnx,synch-mem-2 = <0x0>;
176 xlnx,synch-mem-3 = <0x0>;
177 xlnx,synch-pipedelay-0 = <0x2>;
178 xlnx,synch-pipedelay-1 = <0x2>;
179 xlnx,synch-pipedelay-2 = <0x2>;
180 xlnx,synch-pipedelay-3 = <0x2>;
181 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
182 xlnx,tavdv-ps-mem-1 = <0x3a98>;
183 xlnx,tavdv-ps-mem-2 = <0x3a98>;
184 xlnx,tavdv-ps-mem-3 = <0x3a98>;
185 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
186 xlnx,tcedv-ps-mem-1 = <0x3a98>;
187 xlnx,tcedv-ps-mem-2 = <0x3a98>;
188 xlnx,tcedv-ps-mem-3 = <0x3a98>;
189 xlnx,thzce-ps-mem-0 = <0x88b8>;
190 xlnx,thzce-ps-mem-1 = <0x1b58>;
191 xlnx,thzce-ps-mem-2 = <0x1b58>;
192 xlnx,thzce-ps-mem-3 = <0x1b58>;
193 xlnx,thzoe-ps-mem-0 = <0x1b58>;
194 xlnx,thzoe-ps-mem-1 = <0x1b58>;
195 xlnx,thzoe-ps-mem-2 = <0x1b58>;
196 xlnx,thzoe-ps-mem-3 = <0x1b58>;
197 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
198 xlnx,tlzwe-ps-mem-1 = <0x0>;
199 xlnx,tlzwe-ps-mem-2 = <0x0>;
200 xlnx,tlzwe-ps-mem-3 = <0x0>;
201 xlnx,twc-ps-mem-0 = <0x2af8>;
202 xlnx,twc-ps-mem-1 = <0x3a98>;
203 xlnx,twc-ps-mem-2 = <0x3a98>;
204 xlnx,twc-ps-mem-3 = <0x3a98>;
205 xlnx,twp-ps-mem-0 = <0x11170>;
206 xlnx,twp-ps-mem-1 = <0x2ee0>;
207 xlnx,twp-ps-mem-2 = <0x2ee0>;
208 xlnx,twp-ps-mem-3 = <0x2ee0>;
209 xlnx,xcl0-linesize = <0x4>;
210 xlnx,xcl0-writexfer = <0x1>;
211 xlnx,xcl1-linesize = <0x4>;
212 xlnx,xcl1-writexfer = <0x1>;
213 xlnx,xcl2-linesize = <0x4>;
214 xlnx,xcl2-writexfer = <0x1>;
215 xlnx,xcl3-linesize = <0x4>;
216 xlnx,xcl3-writexfer = <0x1>;
217 } ;
218 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
219 #address-cells = <1>;
220 #size-cells = <1>;
221 compatible = "xlnx,compound";
222 ranges ;
223 ethernet@81c00000 {
224 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
225 interrupt-parent = <&xps_intc_0>;
226 interrupts = < 5 2 >;
227 llink-connected = <&PIM3>;
228 local-mac-address = [ 00 0a 35 00 00 00 ];
229 reg = < 0x81c00000 0x40 >;
230 xlnx,bus2core-clk-ratio = <0x1>;
231 xlnx,phy-type = <0x1>;
232 xlnx,phyaddr = <0x1>;
233 xlnx,rxcsum = <0x0>;
234 xlnx,rxfifo = <0x1000>;
235 xlnx,temac-type = <0x0>;
236 xlnx,txcsum = <0x0>;
237 xlnx,txfifo = <0x1000>;
238 } ;
239 } ;
240 IIC_EEPROM: i2c@81600000 {
241 compatible = "xlnx,xps-iic-2.00.a";
242 interrupt-parent = <&xps_intc_0>;
243 interrupts = < 6 2 >;
244 reg = < 0x81600000 0x10000 >;
245 xlnx,clk-freq = <0x7735940>;
246 xlnx,family = "virtex5";
247 xlnx,gpo-width = <0x1>;
248 xlnx,iic-freq = <0x186a0>;
249 xlnx,scl-inertial-delay = <0x0>;
250 xlnx,sda-inertial-delay = <0x0>;
251 xlnx,ten-bit-adr = <0x0>;
252 } ;
253 LEDs_8Bit: gpio@81400000 {
254 compatible = "xlnx,xps-gpio-1.00.a";
255 interrupt-parent = <&xps_intc_0>;
256 interrupts = < 7 2 >;
257 reg = < 0x81400000 0x10000 >;
258 xlnx,all-inputs = <0x0>;
259 xlnx,all-inputs-2 = <0x0>;
260 xlnx,dout-default = <0x0>;
261 xlnx,dout-default-2 = <0x0>;
262 xlnx,family = "virtex5";
263 xlnx,gpio-width = <0x8>;
264 xlnx,interrupt-present = <0x1>;
265 xlnx,is-bidir = <0x1>;
266 xlnx,is-bidir-2 = <0x1>;
267 xlnx,is-dual = <0x0>;
268 xlnx,tri-default = <0xffffffff>;
269 xlnx,tri-default-2 = <0xffffffff>;
270 #gpio-cells = <2>;
271 gpio-controller;
272 } ;
273
274 gpio-leds {
275 compatible = "gpio-leds";
276
277 heartbeat {
278 label = "Heartbeat";
279 gpios = <&LEDs_8Bit 4 1>;
280 linux,default-trigger = "heartbeat";
281 };
282
283 yellow {
284 label = "Yellow";
285 gpios = <&LEDs_8Bit 5 1>;
286 };
287
288 red {
289 label = "Red";
290 gpios = <&LEDs_8Bit 6 1>;
291 };
292
293 green {
294 label = "Green";
295 gpios = <&LEDs_8Bit 7 1>;
296 };
297 } ;
298 RS232_Uart_1: serial@84000000 {
299 clock-frequency = <125000000>;
300 compatible = "xlnx,xps-uartlite-1.00.a";
301 current-speed = <115200>;
302 device_type = "serial";
303 interrupt-parent = <&xps_intc_0>;
304 interrupts = < 8 0 >;
305 port-number = <0>;
306 reg = < 0x84000000 0x10000 >;
307 xlnx,baudrate = <0x1c200>;
308 xlnx,data-bits = <0x8>;
309 xlnx,family = "virtex5";
310 xlnx,odd-parity = <0x0>;
311 xlnx,use-parity = <0x0>;
312 } ;
313 SysACE_CompactFlash: sysace@83600000 {
314 compatible = "xlnx,xps-sysace-1.00.a";
315 interrupt-parent = <&xps_intc_0>;
316 interrupts = < 4 2 >;
317 reg = < 0x83600000 0x10000 >;
318 xlnx,family = "virtex5";
319 xlnx,mem-width = <0x10>;
320 } ;
321 debug_module: debug@84400000 {
322 compatible = "xlnx,mdm-1.00.d";
323 reg = < 0x84400000 0x10000 >;
324 xlnx,family = "virtex5";
325 xlnx,interconnect = <0x1>;
326 xlnx,jtag-chain = <0x2>;
327 xlnx,mb-dbg-ports = <0x1>;
328 xlnx,uart-width = <0x8>;
329 xlnx,use-uart = <0x1>;
330 xlnx,write-fsl-ports = <0x0>;
331 } ;
332 mpmc@90000000 {
333 #address-cells = <1>;
334 #size-cells = <1>;
335 compatible = "xlnx,mpmc-4.02.a";
336 ranges ;
337 PIM3: sdma@84600180 {
338 compatible = "xlnx,ll-dma-1.00.a";
339 interrupt-parent = <&xps_intc_0>;
340 interrupts = < 2 2 1 2 >;
341 reg = < 0x84600180 0x80 >;
342 } ;
343 } ;
344 xps_intc_0: interrupt-controller@81800000 {
345 #interrupt-cells = <0x2>;
346 compatible = "xlnx,xps-intc-1.00.a";
347 interrupt-controller ;
348 reg = < 0x81800000 0x10000 >;
349 xlnx,kind-of-intr = <0x100>;
350 xlnx,num-intr-inputs = <0x9>;
351 } ;
352 xps_timer_1: timer@83c00000 {
353 compatible = "xlnx,xps-timer-1.00.a";
354 interrupt-parent = <&xps_intc_0>;
355 interrupts = < 3 2 >;
356 reg = < 0x83c00000 0x10000 >;
357 xlnx,count-width = <0x20>;
358 xlnx,family = "virtex5";
359 xlnx,gen0-assert = <0x1>;
360 xlnx,gen1-assert = <0x1>;
361 xlnx,one-timer-only = <0x0>;
362 xlnx,trig0-assert = <0x1>;
363 xlnx,trig1-assert = <0x1>;
364 } ;
365 } ;
366} ;
diff --git a/arch/microblaze/include/asm/io.h b/arch/microblaze/include/asm/io.h
index 3fbb7f1db3bc..1e4c3329f62e 100644
--- a/arch/microblaze/include/asm/io.h
+++ b/arch/microblaze/include/asm/io.h
@@ -15,7 +15,6 @@
15#include <asm/page.h> 15#include <asm/page.h>
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/mm.h> /* Get struct page {...} */ 17#include <linux/mm.h> /* Get struct page {...} */
18#include <asm-generic/iomap.h>
19 18
20#ifndef CONFIG_PCI 19#ifndef CONFIG_PCI
21#define _IO_BASE 0 20#define _IO_BASE 0
@@ -25,211 +24,32 @@
25#define _IO_BASE isa_io_base 24#define _IO_BASE isa_io_base
26#define _ISA_MEM_BASE isa_mem_base 25#define _ISA_MEM_BASE isa_mem_base
27#define PCI_DRAM_OFFSET pci_dram_offset 26#define PCI_DRAM_OFFSET pci_dram_offset
28#endif 27struct pci_dev;
28extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
29#define pci_iounmap pci_iounmap
29 30
30extern unsigned long isa_io_base; 31extern unsigned long isa_io_base;
31extern unsigned long pci_io_base;
32extern unsigned long pci_dram_offset; 32extern unsigned long pci_dram_offset;
33
34extern resource_size_t isa_mem_base; 33extern resource_size_t isa_mem_base;
34#endif
35 35
36#define PCI_IOBASE ((void __iomem *)_IO_BASE)
36#define IO_SPACE_LIMIT (0xFFFFFFFF) 37#define IO_SPACE_LIMIT (0xFFFFFFFF)
37 38
38/* the following is needed to support PCI with some drivers */
39
40#define mmiowb()
41
42static inline unsigned char __raw_readb(const volatile void __iomem *addr)
43{
44 return *(volatile unsigned char __force *)addr;
45}
46static inline unsigned short __raw_readw(const volatile void __iomem *addr)
47{
48 return *(volatile unsigned short __force *)addr;
49}
50static inline unsigned int __raw_readl(const volatile void __iomem *addr)
51{
52 return *(volatile unsigned int __force *)addr;
53}
54static inline unsigned long __raw_readq(const volatile void __iomem *addr)
55{
56 return *(volatile unsigned long __force *)addr;
57}
58static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
59{
60 *(volatile unsigned char __force *)addr = v;
61}
62static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
63{
64 *(volatile unsigned short __force *)addr = v;
65}
66static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
67{
68 *(volatile unsigned int __force *)addr = v;
69}
70static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
71{
72 *(volatile unsigned long __force *)addr = v;
73}
74
75/*
76 * read (readb, readw, readl, readq) and write (writeb, writew,
77 * writel, writeq) accessors are for PCI and thus little endian.
78 * Linux 2.4 for Microblaze had this wrong.
79 */
80static inline unsigned char readb(const volatile void __iomem *addr)
81{
82 return *(volatile unsigned char __force *)addr;
83}
84static inline unsigned short readw(const volatile void __iomem *addr)
85{
86 return le16_to_cpu(*(volatile unsigned short __force *)addr);
87}
88static inline unsigned int readl(const volatile void __iomem *addr)
89{
90 return le32_to_cpu(*(volatile unsigned int __force *)addr);
91}
92#define readq readq
93static inline u64 readq(const volatile void __iomem *addr)
94{
95 return le64_to_cpu(__raw_readq(addr));
96}
97static inline void writeb(unsigned char v, volatile void __iomem *addr)
98{
99 *(volatile unsigned char __force *)addr = v;
100}
101static inline void writew(unsigned short v, volatile void __iomem *addr)
102{
103 *(volatile unsigned short __force *)addr = cpu_to_le16(v);
104}
105static inline void writel(unsigned int v, volatile void __iomem *addr)
106{
107 *(volatile unsigned int __force *)addr = cpu_to_le32(v);
108}
109#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
110
111/* ioread and iowrite variants. thease are for now same as __raw_
112 * variants of accessors. we might check for endianess in the feature
113 */
114#define ioread8(addr) __raw_readb((u8 *)(addr))
115#define ioread16(addr) __raw_readw((u16 *)(addr))
116#define ioread32(addr) __raw_readl((u32 *)(addr))
117#define iowrite8(v, addr) __raw_writeb((u8)(v), (u8 *)(addr))
118#define iowrite16(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
119#define iowrite32(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
120
121#define ioread16be(addr) __raw_readw((u16 *)(addr))
122#define ioread32be(addr) __raw_readl((u32 *)(addr))
123#define iowrite16be(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
124#define iowrite32be(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
125
126/* These are the definitions for the x86 IO instructions
127 * inb/inw/inl/outb/outw/outl, the "string" versions
128 * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
129 * inb_p/inw_p/...
130 * The macros don't do byte-swapping.
131 */
132#define inb(port) readb((u8 *)((unsigned long)(port)))
133#define outb(val, port) writeb((val), (u8 *)((unsigned long)(port)))
134#define inw(port) readw((u16 *)((unsigned long)(port)))
135#define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))
136#define inl(port) readl((u32 *)((unsigned long)(port)))
137#define outl(val, port) writel((val), (u32 *)((unsigned long)(port)))
138
139#define inb_p(port) inb((port))
140#define outb_p(val, port) outb((val), (port))
141#define inw_p(port) inw((port))
142#define outw_p(val, port) outw((val), (port))
143#define inl_p(port) inl((port))
144#define outl_p(val, port) outl((val), (port))
145
146#define memset_io(a, b, c) memset((void *)(a), (b), (c))
147#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
148#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
149
150#ifdef CONFIG_MMU 39#ifdef CONFIG_MMU
151
152#define phys_to_virt(addr) ((void *)__phys_to_virt(addr))
153#define virt_to_phys(addr) ((unsigned long)__virt_to_phys(addr))
154#define virt_to_bus(addr) ((unsigned long)__virt_to_phys(addr))
155
156#define page_to_bus(page) (page_to_phys(page)) 40#define page_to_bus(page) (page_to_phys(page))
157#define bus_to_virt(addr) (phys_to_virt(addr))
158 41
159extern void iounmap(void __iomem *addr); 42extern void iounmap(void __iomem *addr);
160/*extern void *__ioremap(phys_addr_t address, unsigned long size,
161 unsigned long flags);*/
162extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
163#define ioremap_writethrough(addr, size) ioremap((addr), (size))
164#define ioremap_nocache(addr, size) ioremap((addr), (size))
165#define ioremap_fullcache(addr, size) ioremap((addr), (size))
166
167#else /* CONFIG_MMU */
168
169/**
170 * virt_to_phys - map virtual addresses to physical
171 * @address: address to remap
172 *
173 * The returned physical address is the physical (CPU) mapping for
174 * the memory address given. It is only valid to use this function on
175 * addresses directly mapped or allocated via kmalloc.
176 *
177 * This function does not give bus mappings for DMA transfers. In
178 * almost all conceivable cases a device driver should not be using
179 * this function
180 */
181static inline unsigned long __iomem virt_to_phys(volatile void *address)
182{
183 return __pa((unsigned long)address);
184}
185
186#define virt_to_bus virt_to_phys
187
188/**
189 * phys_to_virt - map physical address to virtual
190 * @address: address to remap
191 *
192 * The returned virtual address is a current CPU mapping for
193 * the memory address given. It is only valid to use this function on
194 * addresses that have a kernel mapping
195 *
196 * This function does not handle bus mappings for DMA transfers. In
197 * almost all conceivable cases a device driver should not be using
198 * this function
199 */
200static inline void *phys_to_virt(unsigned long address)
201{
202 return (void *)__va(address);
203}
204 43
205#define bus_to_virt(a) phys_to_virt(a) 44extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
206 45#define ioremap_writethrough(addr, size) ioremap((addr), (size))
207static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size, 46#define ioremap_nocache(addr, size) ioremap((addr), (size))
208 unsigned long flags) 47#define ioremap_fullcache(addr, size) ioremap((addr), (size))
209{ 48#define ioremap_wc(addr, size) ioremap((addr), (size))
210 return (void *)address;
211}
212
213#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
214#define iounmap(addr) ((void)0)
215#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
216 49
217#endif /* CONFIG_MMU */ 50#endif /* CONFIG_MMU */
218 51
219/* 52/* Big Endian */
220 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
221 * access
222 */
223#define xlate_dev_mem_ptr(p) __va(p)
224
225/*
226 * Convert a virtual cached pointer to an uncached pointer
227 */
228#define xlate_dev_kmem_ptr(p) p
229
230/*
231 * Big Endian
232 */
233#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a)) 53#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
234#define out_be16(a, v) __raw_writew((v), (a)) 54#define out_be16(a, v) __raw_writew((v), (a))
235 55
@@ -239,10 +59,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
239#define writel_be(v, a) out_be32((__force unsigned *)a, v) 59#define writel_be(v, a) out_be32((__force unsigned *)a, v)
240#define readl_be(a) in_be32((__force unsigned *)a) 60#define readl_be(a) in_be32((__force unsigned *)a)
241 61
242/* 62/* Little endian */
243 * Little endian
244 */
245
246#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a)) 63#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
247#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a)) 64#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
248 65
@@ -253,100 +70,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
253#define out_8(a, v) __raw_writeb((v), (a)) 70#define out_8(a, v) __raw_writeb((v), (a))
254#define in_8(a) __raw_readb(a) 71#define in_8(a) __raw_readb(a)
255 72
256#define mmiowb() 73#include <asm-generic/io.h>
257
258#define ioport_map(port, nr) ((void __iomem *)(port))
259#define ioport_unmap(addr)
260
261/* from asm-generic/io.h */
262#ifndef insb
263static inline void insb(unsigned long addr, void *buffer, int count)
264{
265 if (count) {
266 u8 *buf = buffer;
267 do {
268 u8 x = inb(addr);
269 *buf++ = x;
270 } while (--count);
271 }
272}
273#endif
274
275#ifndef insw
276static inline void insw(unsigned long addr, void *buffer, int count)
277{
278 if (count) {
279 u16 *buf = buffer;
280 do {
281 u16 x = inw(addr);
282 *buf++ = x;
283 } while (--count);
284 }
285}
286#endif
287
288#ifndef insl
289static inline void insl(unsigned long addr, void *buffer, int count)
290{
291 if (count) {
292 u32 *buf = buffer;
293 do {
294 u32 x = inl(addr);
295 *buf++ = x;
296 } while (--count);
297 }
298}
299#endif
300
301#ifndef outsb
302static inline void outsb(unsigned long addr, const void *buffer, int count)
303{
304 if (count) {
305 const u8 *buf = buffer;
306 do {
307 outb(*buf++, addr);
308 } while (--count);
309 }
310}
311#endif
312
313#ifndef outsw
314static inline void outsw(unsigned long addr, const void *buffer, int count)
315{
316 if (count) {
317 const u16 *buf = buffer;
318 do {
319 outw(*buf++, addr);
320 } while (--count);
321 }
322}
323#endif
324
325#ifndef outsl
326static inline void outsl(unsigned long addr, const void *buffer, int count)
327{
328 if (count) {
329 const u32 *buf = buffer;
330 do {
331 outl(*buf++, addr);
332 } while (--count);
333 }
334}
335#endif
336
337#define ioread8_rep(p, dst, count) \
338 insb((unsigned long) (p), (dst), (count))
339#define ioread16_rep(p, dst, count) \
340 insw((unsigned long) (p), (dst), (count))
341#define ioread32_rep(p, dst, count) \
342 insl((unsigned long) (p), (dst), (count))
343
344#define iowrite8_rep(p, src, count) \
345 outsb((unsigned long) (p), (src), (count))
346#define iowrite16_rep(p, src, count) \
347 outsw((unsigned long) (p), (src), (count))
348#define iowrite32_rep(p, src, count) \
349 outsl((unsigned long) (p), (src), (count))
350 74
351#define readb_relaxed readb 75#define readb_relaxed readb
352#define readw_relaxed readw 76#define readw_relaxed readw
diff --git a/arch/microblaze/include/asm/processor.h b/arch/microblaze/include/asm/processor.h
index d6e0ffea28b6..9d31b057c355 100644
--- a/arch/microblaze/include/asm/processor.h
+++ b/arch/microblaze/include/asm/processor.h
@@ -122,7 +122,7 @@ struct thread_struct {
122} 122}
123 123
124/* Free all resources held by a thread. */ 124/* Free all resources held by a thread. */
125extern inline void release_thread(struct task_struct *dead_task) 125static inline void release_thread(struct task_struct *dead_task)
126{ 126{
127} 127}
128 128
diff --git a/arch/microblaze/include/asm/setup.h b/arch/microblaze/include/asm/setup.h
index f05df5630c84..be84a4d3917f 100644
--- a/arch/microblaze/include/asm/setup.h
+++ b/arch/microblaze/include/asm/setup.h
@@ -19,14 +19,12 @@ extern char cmd_line[COMMAND_LINE_SIZE];
19 19
20extern char *klimit; 20extern char *klimit;
21 21
22void early_printk(const char *fmt, ...);
23
24int setup_early_printk(char *opt); 22int setup_early_printk(char *opt);
25void remap_early_printk(void); 23void remap_early_printk(void);
26void disable_early_printk(void); 24void disable_early_printk(void);
27 25
28void heartbeat(void); 26void microblaze_heartbeat(void);
29void setup_heartbeat(void); 27void microblaze_setup_heartbeat(void);
30 28
31# ifdef CONFIG_MMU 29# ifdef CONFIG_MMU
32extern void mmu_reset(void); 30extern void mmu_reset(void);
diff --git a/arch/microblaze/include/uapi/asm/unistd.h b/arch/microblaze/include/uapi/asm/unistd.h
index 20043b67d158..8d0791b49b31 100644
--- a/arch/microblaze/include/uapi/asm/unistd.h
+++ b/arch/microblaze/include/uapi/asm/unistd.h
@@ -93,7 +93,7 @@
93#define __NR_settimeofday 79 /* ok */ 93#define __NR_settimeofday 79 /* ok */
94#define __NR_getgroups 80 /* ok */ 94#define __NR_getgroups 80 /* ok */
95#define __NR_setgroups 81 /* ok */ 95#define __NR_setgroups 81 /* ok */
96#define __NR_select 82 /* obsolete -> sys_pselect7 */ 96#define __NR_select 82 /* obsolete -> sys_pselect6 */
97#define __NR_symlink 83 /* symlinkat */ 97#define __NR_symlink 83 /* symlinkat */
98#define __NR_oldlstat 84 /* remove */ 98#define __NR_oldlstat 84 /* remove */
99#define __NR_readlink 85 /* obsolete -> sys_readlinkat */ 99#define __NR_readlink 85 /* obsolete -> sys_readlinkat */
@@ -320,7 +320,7 @@
320#define __NR_readlinkat 305 /* ok */ 320#define __NR_readlinkat 305 /* ok */
321#define __NR_fchmodat 306 /* ok */ 321#define __NR_fchmodat 306 /* ok */
322#define __NR_faccessat 307 /* ok */ 322#define __NR_faccessat 307 /* ok */
323#define __NR_pselect6 308 /* obsolete -> sys_pselect7 */ 323#define __NR_pselect6 308 /* ok */
324#define __NR_ppoll 309 /* ok */ 324#define __NR_ppoll 309 /* ok */
325#define __NR_unshare 310 /* ok */ 325#define __NR_unshare 310 /* ok */
326#define __NR_set_robust_list 311 /* ok */ 326#define __NR_set_robust_list 311 /* ok */
@@ -396,5 +396,7 @@
396#define __NR_process_vm_writev 378 396#define __NR_process_vm_writev 378
397#define __NR_kcmp 379 397#define __NR_kcmp 379
398#define __NR_finit_module 380 398#define __NR_finit_module 380
399#define __NR_sched_setattr 381
400#define __NR_sched_getattr 382
399 401
400#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */ 402#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
diff --git a/arch/microblaze/kernel/Makefile b/arch/microblaze/kernel/Makefile
index 5b0e512c78e5..08d50cc55e7d 100644
--- a/arch/microblaze/kernel/Makefile
+++ b/arch/microblaze/kernel/Makefile
@@ -16,7 +16,7 @@ extra-y := head.o vmlinux.lds
16 16
17obj-y += dma.o exceptions.o \ 17obj-y += dma.o exceptions.o \
18 hw_exception_handler.o intc.o irq.o \ 18 hw_exception_handler.o intc.o irq.o \
19 process.o prom.o prom_parse.o ptrace.o \ 19 platform.o process.o prom.o prom_parse.o ptrace.o \
20 reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o 20 reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
21 21
22obj-y += cpu/ 22obj-y += cpu/
diff --git a/arch/microblaze/kernel/heartbeat.c b/arch/microblaze/kernel/heartbeat.c
index 1879a0527776..4643e3ab9414 100644
--- a/arch/microblaze/kernel/heartbeat.c
+++ b/arch/microblaze/kernel/heartbeat.c
@@ -17,7 +17,7 @@
17 17
18static unsigned int base_addr; 18static unsigned int base_addr;
19 19
20void heartbeat(void) 20void microblaze_heartbeat(void)
21{ 21{
22 static unsigned int cnt, period, dist; 22 static unsigned int cnt, period, dist;
23 23
@@ -42,7 +42,7 @@ void heartbeat(void)
42 } 42 }
43} 43}
44 44
45void setup_heartbeat(void) 45void microblaze_setup_heartbeat(void)
46{ 46{
47 struct device_node *gpio = NULL; 47 struct device_node *gpio = NULL;
48 int *prop; 48 int *prop;
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index 581451ad4687..15c7c12ea0e7 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr;
32#define MER_ME (1<<0) 32#define MER_ME (1<<0)
33#define MER_HIE (1<<1) 33#define MER_HIE (1<<1)
34 34
35static unsigned int (*read_fn)(void __iomem *);
36static void (*write_fn)(u32, void __iomem *);
37
38static void intc_write32(u32 val, void __iomem *addr)
39{
40 iowrite32(val, addr);
41}
42
43static unsigned int intc_read32(void __iomem *addr)
44{
45 return ioread32(addr);
46}
47
48static void intc_write32_be(u32 val, void __iomem *addr)
49{
50 iowrite32be(val, addr);
51}
52
53static unsigned int intc_read32_be(void __iomem *addr)
54{
55 return ioread32be(addr);
56}
57
35static void intc_enable_or_unmask(struct irq_data *d) 58static void intc_enable_or_unmask(struct irq_data *d)
36{ 59{
37 unsigned long mask = 1 << d->hwirq; 60 unsigned long mask = 1 << d->hwirq;
@@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
43 * acks the irq before calling the interrupt handler 66 * acks the irq before calling the interrupt handler
44 */ 67 */
45 if (irqd_is_level_type(d)) 68 if (irqd_is_level_type(d))
46 out_be32(intc_baseaddr + IAR, mask); 69 write_fn(mask, intc_baseaddr + IAR);
47 70
48 out_be32(intc_baseaddr + SIE, mask); 71 write_fn(mask, intc_baseaddr + SIE);
49} 72}
50 73
51static void intc_disable_or_mask(struct irq_data *d) 74static void intc_disable_or_mask(struct irq_data *d)
52{ 75{
53 pr_debug("disable: %ld\n", d->hwirq); 76 pr_debug("disable: %ld\n", d->hwirq);
54 out_be32(intc_baseaddr + CIE, 1 << d->hwirq); 77 write_fn(1 << d->hwirq, intc_baseaddr + CIE);
55} 78}
56 79
57static void intc_ack(struct irq_data *d) 80static void intc_ack(struct irq_data *d)
58{ 81{
59 pr_debug("ack: %ld\n", d->hwirq); 82 pr_debug("ack: %ld\n", d->hwirq);
60 out_be32(intc_baseaddr + IAR, 1 << d->hwirq); 83 write_fn(1 << d->hwirq, intc_baseaddr + IAR);
61} 84}
62 85
63static void intc_mask_ack(struct irq_data *d) 86static void intc_mask_ack(struct irq_data *d)
@@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d)
65 unsigned long mask = 1 << d->hwirq; 88 unsigned long mask = 1 << d->hwirq;
66 89
67 pr_debug("disable_and_ack: %ld\n", d->hwirq); 90 pr_debug("disable_and_ack: %ld\n", d->hwirq);
68 out_be32(intc_baseaddr + CIE, mask); 91 write_fn(mask, intc_baseaddr + CIE);
69 out_be32(intc_baseaddr + IAR, mask); 92 write_fn(mask, intc_baseaddr + IAR);
70} 93}
71 94
72static struct irq_chip intc_dev = { 95static struct irq_chip intc_dev = {
@@ -83,7 +106,7 @@ unsigned int get_irq(void)
83{ 106{
84 unsigned int hwirq, irq = -1; 107 unsigned int hwirq, irq = -1;
85 108
86 hwirq = in_be32(intc_baseaddr + IVR); 109 hwirq = read_fn(intc_baseaddr + IVR);
87 if (hwirq != -1U) 110 if (hwirq != -1U)
88 irq = irq_find_mapping(root_domain, hwirq); 111 irq = irq_find_mapping(root_domain, hwirq);
89 112
@@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
140 pr_info("%s: num_irq=%d, edge=0x%x\n", 163 pr_info("%s: num_irq=%d, edge=0x%x\n",
141 intc->full_name, nr_irq, intr_mask); 164 intc->full_name, nr_irq, intr_mask);
142 165
166 write_fn = intc_write32;
167 read_fn = intc_read32;
168
143 /* 169 /*
144 * Disable all external interrupts until they are 170 * Disable all external interrupts until they are
145 * explicity requested. 171 * explicity requested.
146 */ 172 */
147 out_be32(intc_baseaddr + IER, 0); 173 write_fn(0, intc_baseaddr + IER);
148 174
149 /* Acknowledge any pending interrupts just in case. */ 175 /* Acknowledge any pending interrupts just in case. */
150 out_be32(intc_baseaddr + IAR, 0xffffffff); 176 write_fn(0xffffffff, intc_baseaddr + IAR);
151 177
152 /* Turn on the Master Enable. */ 178 /* Turn on the Master Enable. */
153 out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); 179 write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
180 if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
181 write_fn = intc_write32_be;
182 read_fn = intc_read32_be;
183 write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
184 }
154 185
155 /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm 186 /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
156 * lazy and Michal can clean it up to something nicer when he tests 187 * lazy and Michal can clean it up to something nicer when he tests
diff --git a/arch/microblaze/platform/platform.c b/arch/microblaze/kernel/platform.c
index b9529caa507a..b9529caa507a 100644
--- a/arch/microblaze/platform/platform.c
+++ b/arch/microblaze/kernel/platform.c
diff --git a/arch/microblaze/kernel/process.c b/arch/microblaze/kernel/process.c
index 7d1a9c8b1f3d..b2dd37196b3b 100644
--- a/arch/microblaze/kernel/process.c
+++ b/arch/microblaze/kernel/process.c
@@ -8,6 +8,7 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/cpu.h>
11#include <linux/export.h> 12#include <linux/export.h>
12#include <linux/sched.h> 13#include <linux/sched.h>
13#include <linux/pm.h> 14#include <linux/pm.h>
diff --git a/arch/microblaze/kernel/signal.c b/arch/microblaze/kernel/signal.c
index d26d7e7a6913..49a07a4d76d0 100644
--- a/arch/microblaze/kernel/signal.c
+++ b/arch/microblaze/kernel/signal.c
@@ -216,7 +216,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
216 /* MS: I need add offset in page */ 216 /* MS: I need add offset in page */
217 address += ((unsigned long)frame->tramp) & ~PAGE_MASK; 217 address += ((unsigned long)frame->tramp) & ~PAGE_MASK;
218 /* MS address is virtual */ 218 /* MS address is virtual */
219 address = virt_to_phys(address); 219 address = __virt_to_phys(address);
220 invalidate_icache_range(address, address + 8); 220 invalidate_icache_range(address, address + 8);
221 flush_dcache_range(address, address + 8); 221 flush_dcache_range(address, address + 8);
222 } 222 }
diff --git a/arch/microblaze/kernel/syscall_table.S b/arch/microblaze/kernel/syscall_table.S
index b882ad50535b..329dfbad810b 100644
--- a/arch/microblaze/kernel/syscall_table.S
+++ b/arch/microblaze/kernel/syscall_table.S
@@ -308,7 +308,7 @@ ENTRY(sys_call_table)
308 .long sys_readlinkat /* 305 */ 308 .long sys_readlinkat /* 305 */
309 .long sys_fchmodat 309 .long sys_fchmodat
310 .long sys_faccessat 310 .long sys_faccessat
311 .long sys_ni_syscall /* pselect6 */ 311 .long sys_pselect6
312 .long sys_ppoll 312 .long sys_ppoll
313 .long sys_unshare /* 310 */ 313 .long sys_unshare /* 310 */
314 .long sys_set_robust_list 314 .long sys_set_robust_list
@@ -363,8 +363,8 @@ ENTRY(sys_call_table)
363 .long sys_sendmsg /* 360 */ 363 .long sys_sendmsg /* 360 */
364 .long sys_recvmsg 364 .long sys_recvmsg
365 .long sys_accept4 365 .long sys_accept4
366 .long sys_ni_syscall 366 .long sys_preadv
367 .long sys_ni_syscall 367 .long sys_pwritev
368 .long sys_rt_tgsigqueueinfo /* 365 */ 368 .long sys_rt_tgsigqueueinfo /* 365 */
369 .long sys_perf_event_open 369 .long sys_perf_event_open
370 .long sys_recvmmsg 370 .long sys_recvmmsg
@@ -381,3 +381,5 @@ ENTRY(sys_call_table)
381 .long sys_process_vm_writev 381 .long sys_process_vm_writev
382 .long sys_kcmp 382 .long sys_kcmp
383 .long sys_finit_module 383 .long sys_finit_module
384 .long sys_sched_setattr
385 .long sys_sched_getattr
diff --git a/arch/microblaze/kernel/timer.c b/arch/microblaze/kernel/timer.c
index fb0c61443f19..dd96f0e4bfa2 100644
--- a/arch/microblaze/kernel/timer.c
+++ b/arch/microblaze/kernel/timer.c
@@ -43,10 +43,33 @@ static unsigned int timer_clock_freq;
43#define TCSR_PWMA (1<<9) 43#define TCSR_PWMA (1<<9)
44#define TCSR_ENALL (1<<10) 44#define TCSR_ENALL (1<<10)
45 45
46static unsigned int (*read_fn)(void __iomem *);
47static void (*write_fn)(u32, void __iomem *);
48
49static void timer_write32(u32 val, void __iomem *addr)
50{
51 iowrite32(val, addr);
52}
53
54static unsigned int timer_read32(void __iomem *addr)
55{
56 return ioread32(addr);
57}
58
59static void timer_write32_be(u32 val, void __iomem *addr)
60{
61 iowrite32be(val, addr);
62}
63
64static unsigned int timer_read32_be(void __iomem *addr)
65{
66 return ioread32be(addr);
67}
68
46static inline void xilinx_timer0_stop(void) 69static inline void xilinx_timer0_stop(void)
47{ 70{
48 out_be32(timer_baseaddr + TCSR0, 71 write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
49 in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); 72 timer_baseaddr + TCSR0);
50} 73}
51 74
52static inline void xilinx_timer0_start_periodic(unsigned long load_val) 75static inline void xilinx_timer0_start_periodic(unsigned long load_val)
@@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
54 if (!load_val) 77 if (!load_val)
55 load_val = 1; 78 load_val = 1;
56 /* loading value to timer reg */ 79 /* loading value to timer reg */
57 out_be32(timer_baseaddr + TLR0, load_val); 80 write_fn(load_val, timer_baseaddr + TLR0);
58 81
59 /* load the initial value */ 82 /* load the initial value */
60 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 83 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
61 84
62 /* see timer data sheet for detail 85 /* see timer data sheet for detail
63 * !ENALL - don't enable 'em all 86 * !ENALL - don't enable 'em all
@@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
72 * UDT - set the timer as down counter 95 * UDT - set the timer as down counter
73 * !MDT0 - generate mode 96 * !MDT0 - generate mode
74 */ 97 */
75 out_be32(timer_baseaddr + TCSR0, 98 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
76 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 99 timer_baseaddr + TCSR0);
77} 100}
78 101
79static inline void xilinx_timer0_start_oneshot(unsigned long load_val) 102static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
@@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
81 if (!load_val) 104 if (!load_val)
82 load_val = 1; 105 load_val = 1;
83 /* loading value to timer reg */ 106 /* loading value to timer reg */
84 out_be32(timer_baseaddr + TLR0, load_val); 107 write_fn(load_val, timer_baseaddr + TLR0);
85 108
86 /* load the initial value */ 109 /* load the initial value */
87 out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); 110 write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
88 111
89 out_be32(timer_baseaddr + TCSR0, 112 write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
90 TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); 113 timer_baseaddr + TCSR0);
91} 114}
92 115
93static int xilinx_timer_set_next_event(unsigned long delta, 116static int xilinx_timer_set_next_event(unsigned long delta,
@@ -133,14 +156,14 @@ static struct clock_event_device clockevent_xilinx_timer = {
133 156
134static inline void timer_ack(void) 157static inline void timer_ack(void)
135{ 158{
136 out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); 159 write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
137} 160}
138 161
139static irqreturn_t timer_interrupt(int irq, void *dev_id) 162static irqreturn_t timer_interrupt(int irq, void *dev_id)
140{ 163{
141 struct clock_event_device *evt = &clockevent_xilinx_timer; 164 struct clock_event_device *evt = &clockevent_xilinx_timer;
142#ifdef CONFIG_HEART_BEAT 165#ifdef CONFIG_HEART_BEAT
143 heartbeat(); 166 microblaze_heartbeat();
144#endif 167#endif
145 timer_ack(); 168 timer_ack();
146 evt->event_handler(evt); 169 evt->event_handler(evt);
@@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void)
169 192
170static u64 xilinx_clock_read(void) 193static u64 xilinx_clock_read(void)
171{ 194{
172 return in_be32(timer_baseaddr + TCR1); 195 return read_fn(timer_baseaddr + TCR1);
173} 196}
174 197
175static cycle_t xilinx_read(struct clocksource *cs) 198static cycle_t xilinx_read(struct clocksource *cs)
@@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void)
217 panic("failed to register clocksource"); 240 panic("failed to register clocksource");
218 241
219 /* stop timer1 */ 242 /* stop timer1 */
220 out_be32(timer_baseaddr + TCSR1, 243 write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
221 in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); 244 timer_baseaddr + TCSR1);
222 /* start timer1 - up counting without interrupt */ 245 /* start timer1 - up counting without interrupt */
223 out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); 246 write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
224 247
225 /* register timecounter - for ftrace support */ 248 /* register timecounter - for ftrace support */
226 init_xilinx_timecounter(); 249 init_xilinx_timecounter();
@@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer)
245 BUG(); 268 BUG();
246 } 269 }
247 270
271 write_fn = timer_write32;
272 read_fn = timer_read32;
273
274 write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
275 if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
276 write_fn = timer_write32_be;
277 read_fn = timer_read32_be;
278 }
279
248 irq = irq_of_parse_and_map(timer, 0); 280 irq = irq_of_parse_and_map(timer, 0);
249 281
250 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); 282 of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
@@ -274,7 +306,7 @@ static void __init xilinx_timer_init(struct device_node *timer)
274 306
275 setup_irq(irq, &timer_irqaction); 307 setup_irq(irq, &timer_irqaction);
276#ifdef CONFIG_HEART_BEAT 308#ifdef CONFIG_HEART_BEAT
277 setup_heartbeat(); 309 microblaze_setup_heartbeat();
278#endif 310#endif
279 xilinx_clocksource_init(); 311 xilinx_clocksource_init();
280 xilinx_clockevent_init(); 312 xilinx_clockevent_init();
diff --git a/arch/microblaze/mm/consistent.c b/arch/microblaze/mm/consistent.c
index dbbf2246a260..e10ad930895e 100644
--- a/arch/microblaze/mm/consistent.c
+++ b/arch/microblaze/mm/consistent.c
@@ -117,7 +117,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
117 ret = (void *)va; 117 ret = (void *)va;
118 118
119 /* This gives us the real physical address of the first page. */ 119 /* This gives us the real physical address of the first page. */
120 *dma_handle = pa = virt_to_bus((void *)vaddr); 120 *dma_handle = pa = __virt_to_phys(vaddr);
121#endif 121#endif
122 122
123 /* 123 /*
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index 89077d346714..77bc7c7e6522 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -369,7 +369,7 @@ asmlinkage void __init mmu_init(void)
369 if (initrd_start) { 369 if (initrd_start) {
370 unsigned long size; 370 unsigned long size;
371 size = initrd_end - initrd_start; 371 size = initrd_end - initrd_start;
372 memblock_reserve(virt_to_phys(initrd_start), size); 372 memblock_reserve(__virt_to_phys(initrd_start), size);
373 } 373 }
374#endif /* CONFIG_BLK_DEV_INITRD */ 374#endif /* CONFIG_BLK_DEV_INITRD */
375 375
diff --git a/arch/microblaze/mm/pgtable.c b/arch/microblaze/mm/pgtable.c
index 10b3bd0a980d..4f4520e779a5 100644
--- a/arch/microblaze/mm/pgtable.c
+++ b/arch/microblaze/mm/pgtable.c
@@ -69,10 +69,11 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size,
69 * 69 *
70 * However, allow remap of rootfs: TBD 70 * However, allow remap of rootfs: TBD
71 */ 71 */
72
72 if (mem_init_done && 73 if (mem_init_done &&
73 p >= memory_start && p < virt_to_phys(high_memory) && 74 p >= memory_start && p < virt_to_phys(high_memory) &&
74 !(p >= virt_to_phys((unsigned long)&__bss_stop) && 75 !(p >= __virt_to_phys((phys_addr_t)__bss_stop) &&
75 p < virt_to_phys((unsigned long)__bss_stop))) { 76 p < __virt_to_phys((phys_addr_t)__bss_stop))) {
76 pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n", 77 pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n",
77 (unsigned long)p, __builtin_return_address(0)); 78 (unsigned long)p, __builtin_return_address(0));
78 return NULL; 79 return NULL;
diff --git a/arch/microblaze/platform/Makefile b/arch/microblaze/platform/Makefile
deleted file mode 100644
index ea1b75cc5775..000000000000
--- a/arch/microblaze/platform/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
1#
2# Makefile for arch/microblaze/platform directory
3#
4#obj-$(CONFIG_PLATFORM_GENERIC) += generic/
5
6obj-y += platform.o
diff --git a/arch/microblaze/platform/generic/Kconfig.auto b/arch/microblaze/platform/generic/Kconfig.auto
deleted file mode 100644
index 25a6f019e94d..000000000000
--- a/arch/microblaze/platform/generic/Kconfig.auto
+++ /dev/null
@@ -1,61 +0,0 @@
1#
2# (C) Copyright 2007 Michal Simek
3#
4# Michal SIMEK <monstr@monstr.eu>
5#
6# This program is free software; you can redistribute it and/or
7# modify it under the terms of the GNU General Public License as
8# published by the Free Software Foundation; either version 2 of
9# the License, or (at your option) any later version.
10#
11# This program is distributed in the hope that it will be useful,
12# but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14# GNU General Public License for more details.
15#
16# You should have received a copy of the GNU General Public License
17# along with this program; if not, write to the Free Software
18# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19# MA 02111-1307 USA
20#
21
22# Definitions for MICROBLAZE0
23comment "Definitions for MICROBLAZE0"
24
25config KERNEL_BASE_ADDR
26 hex "Physical address where Linux Kernel is"
27 default "0x90000000"
28 help
29 BASE Address for kernel
30
31config XILINX_MICROBLAZE0_FAMILY
32 string "Targeted FPGA family"
33 default "virtex5"
34
35config XILINX_MICROBLAZE0_USE_MSR_INSTR
36 int "USE_MSR_INSTR range (0:1)"
37 default 0
38
39config XILINX_MICROBLAZE0_USE_PCMP_INSTR
40 int "USE_PCMP_INSTR range (0:1)"
41 default 0
42
43config XILINX_MICROBLAZE0_USE_BARREL
44 int "USE_BARREL range (0:1)"
45 default 0
46
47config XILINX_MICROBLAZE0_USE_DIV
48 int "USE_DIV range (0:1)"
49 default 0
50
51config XILINX_MICROBLAZE0_USE_HW_MUL
52 int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
53 default 0
54
55config XILINX_MICROBLAZE0_USE_FPU
56 int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
57 default 0
58
59config XILINX_MICROBLAZE0_HW_VER
60 string "Core version number"
61 default 7.10.d
diff --git a/arch/microblaze/platform/generic/Makefile b/arch/microblaze/platform/generic/Makefile
deleted file mode 100644
index 9a8b1bd3fa6d..000000000000
--- a/arch/microblaze/platform/generic/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
1#
2# Empty Makefile to keep make clean happy
3#
diff --git a/arch/microblaze/platform/generic/system.dts b/arch/microblaze/platform/generic/system.dts
deleted file mode 100644
index b620da23febb..000000000000
--- a/arch/microblaze/platform/generic/system.dts
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * Device Tree Generator version: 1.1
3 *
4 * (C) Copyright 2007-2008 Xilinx, Inc.
5 * (C) Copyright 2007-2009 Michal Simek
6 *
7 * Michal SIMEK <monstr@monstr.eu>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * CAUTION: This file is automatically generated by libgen.
25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
26 *
27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
28 */
29
30/dts-v1/;
31/ {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "xlnx,microblaze";
35 hard-reset-gpios = <&LEDs_8Bit 2 1>;
36 model = "testing";
37 DDR2_SDRAM: memory@90000000 {
38 device_type = "memory";
39 reg = < 0x90000000 0x10000000 >;
40 } ;
41 aliases {
42 ethernet0 = &Hard_Ethernet_MAC;
43 serial0 = &RS232_Uart_1;
44 } ;
45 chosen {
46 bootargs = "console=ttyUL0,115200 highres=on";
47 linux,stdout-path = "/plb@0/serial@84000000";
48 } ;
49 cpus {
50 #address-cells = <1>;
51 #cpus = <0x1>;
52 #size-cells = <0>;
53 microblaze_0: cpu@0 {
54 clock-frequency = <125000000>;
55 compatible = "xlnx,microblaze-7.10.d";
56 d-cache-baseaddr = <0x90000000>;
57 d-cache-highaddr = <0x9fffffff>;
58 d-cache-line-size = <0x10>;
59 d-cache-size = <0x2000>;
60 device_type = "cpu";
61 i-cache-baseaddr = <0x90000000>;
62 i-cache-highaddr = <0x9fffffff>;
63 i-cache-line-size = <0x10>;
64 i-cache-size = <0x2000>;
65 model = "microblaze,7.10.d";
66 reg = <0>;
67 timebase-frequency = <125000000>;
68 xlnx,addr-tag-bits = <0xf>;
69 xlnx,allow-dcache-wr = <0x1>;
70 xlnx,allow-icache-wr = <0x1>;
71 xlnx,area-optimized = <0x0>;
72 xlnx,cache-byte-size = <0x2000>;
73 xlnx,d-lmb = <0x1>;
74 xlnx,d-opb = <0x0>;
75 xlnx,d-plb = <0x1>;
76 xlnx,data-size = <0x20>;
77 xlnx,dcache-addr-tag = <0xf>;
78 xlnx,dcache-always-used = <0x1>;
79 xlnx,dcache-byte-size = <0x2000>;
80 xlnx,dcache-line-len = <0x4>;
81 xlnx,dcache-use-fsl = <0x1>;
82 xlnx,debug-enabled = <0x1>;
83 xlnx,div-zero-exception = <0x1>;
84 xlnx,dopb-bus-exception = <0x0>;
85 xlnx,dynamic-bus-sizing = <0x1>;
86 xlnx,edge-is-positive = <0x1>;
87 xlnx,family = "virtex5";
88 xlnx,endianness = <0x1>;
89 xlnx,fpu-exception = <0x1>;
90 xlnx,fsl-data-size = <0x20>;
91 xlnx,fsl-exception = <0x0>;
92 xlnx,fsl-links = <0x0>;
93 xlnx,i-lmb = <0x1>;
94 xlnx,i-opb = <0x0>;
95 xlnx,i-plb = <0x1>;
96 xlnx,icache-always-used = <0x1>;
97 xlnx,icache-line-len = <0x4>;
98 xlnx,icache-use-fsl = <0x1>;
99 xlnx,ill-opcode-exception = <0x1>;
100 xlnx,instance = "microblaze_0";
101 xlnx,interconnect = <0x1>;
102 xlnx,interrupt-is-edge = <0x0>;
103 xlnx,iopb-bus-exception = <0x0>;
104 xlnx,mmu-dtlb-size = <0x4>;
105 xlnx,mmu-itlb-size = <0x2>;
106 xlnx,mmu-tlb-access = <0x3>;
107 xlnx,mmu-zones = <0x10>;
108 xlnx,number-of-pc-brk = <0x1>;
109 xlnx,number-of-rd-addr-brk = <0x0>;
110 xlnx,number-of-wr-addr-brk = <0x0>;
111 xlnx,opcode-0x0-illegal = <0x1>;
112 xlnx,pvr = <0x2>;
113 xlnx,pvr-user1 = <0x0>;
114 xlnx,pvr-user2 = <0x0>;
115 xlnx,reset-msr = <0x0>;
116 xlnx,sco = <0x0>;
117 xlnx,unaligned-exceptions = <0x1>;
118 xlnx,use-barrel = <0x1>;
119 xlnx,use-dcache = <0x1>;
120 xlnx,use-div = <0x1>;
121 xlnx,use-ext-brk = <0x1>;
122 xlnx,use-ext-nm-brk = <0x1>;
123 xlnx,use-extended-fsl-instr = <0x0>;
124 xlnx,use-fpu = <0x2>;
125 xlnx,use-hw-mul = <0x2>;
126 xlnx,use-icache = <0x1>;
127 xlnx,use-interrupt = <0x1>;
128 xlnx,use-mmu = <0x3>;
129 xlnx,use-msr-instr = <0x1>;
130 xlnx,use-pcmp-instr = <0x1>;
131 } ;
132 } ;
133 mb_plb: plb@0 {
134 #address-cells = <1>;
135 #size-cells = <1>;
136 compatible = "xlnx,plb-v46-1.03.a", "xlnx,plb-v46-1.00.a", "simple-bus";
137 ranges ;
138 FLASH: flash@a0000000 {
139 bank-width = <2>;
140 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
141 reg = < 0xa0000000 0x2000000 >;
142 xlnx,family = "virtex5";
143 xlnx,include-datawidth-matching-0 = <0x1>;
144 xlnx,include-datawidth-matching-1 = <0x0>;
145 xlnx,include-datawidth-matching-2 = <0x0>;
146 xlnx,include-datawidth-matching-3 = <0x0>;
147 xlnx,include-negedge-ioregs = <0x0>;
148 xlnx,include-plb-ipif = <0x1>;
149 xlnx,include-wrbuf = <0x1>;
150 xlnx,max-mem-width = <0x10>;
151 xlnx,mch-native-dwidth = <0x20>;
152 xlnx,mch-plb-clk-period-ps = <0x1f40>;
153 xlnx,mch-splb-awidth = <0x20>;
154 xlnx,mch0-accessbuf-depth = <0x10>;
155 xlnx,mch0-protocol = <0x0>;
156 xlnx,mch0-rddatabuf-depth = <0x10>;
157 xlnx,mch1-accessbuf-depth = <0x10>;
158 xlnx,mch1-protocol = <0x0>;
159 xlnx,mch1-rddatabuf-depth = <0x10>;
160 xlnx,mch2-accessbuf-depth = <0x10>;
161 xlnx,mch2-protocol = <0x0>;
162 xlnx,mch2-rddatabuf-depth = <0x10>;
163 xlnx,mch3-accessbuf-depth = <0x10>;
164 xlnx,mch3-protocol = <0x0>;
165 xlnx,mch3-rddatabuf-depth = <0x10>;
166 xlnx,mem0-width = <0x10>;
167 xlnx,mem1-width = <0x20>;
168 xlnx,mem2-width = <0x20>;
169 xlnx,mem3-width = <0x20>;
170 xlnx,num-banks-mem = <0x1>;
171 xlnx,num-channels = <0x0>;
172 xlnx,priority-mode = <0x0>;
173 xlnx,synch-mem-0 = <0x0>;
174 xlnx,synch-mem-1 = <0x0>;
175 xlnx,synch-mem-2 = <0x0>;
176 xlnx,synch-mem-3 = <0x0>;
177 xlnx,synch-pipedelay-0 = <0x2>;
178 xlnx,synch-pipedelay-1 = <0x2>;
179 xlnx,synch-pipedelay-2 = <0x2>;
180 xlnx,synch-pipedelay-3 = <0x2>;
181 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
182 xlnx,tavdv-ps-mem-1 = <0x3a98>;
183 xlnx,tavdv-ps-mem-2 = <0x3a98>;
184 xlnx,tavdv-ps-mem-3 = <0x3a98>;
185 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
186 xlnx,tcedv-ps-mem-1 = <0x3a98>;
187 xlnx,tcedv-ps-mem-2 = <0x3a98>;
188 xlnx,tcedv-ps-mem-3 = <0x3a98>;
189 xlnx,thzce-ps-mem-0 = <0x88b8>;
190 xlnx,thzce-ps-mem-1 = <0x1b58>;
191 xlnx,thzce-ps-mem-2 = <0x1b58>;
192 xlnx,thzce-ps-mem-3 = <0x1b58>;
193 xlnx,thzoe-ps-mem-0 = <0x1b58>;
194 xlnx,thzoe-ps-mem-1 = <0x1b58>;
195 xlnx,thzoe-ps-mem-2 = <0x1b58>;
196 xlnx,thzoe-ps-mem-3 = <0x1b58>;
197 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
198 xlnx,tlzwe-ps-mem-1 = <0x0>;
199 xlnx,tlzwe-ps-mem-2 = <0x0>;
200 xlnx,tlzwe-ps-mem-3 = <0x0>;
201 xlnx,twc-ps-mem-0 = <0x2af8>;
202 xlnx,twc-ps-mem-1 = <0x3a98>;
203 xlnx,twc-ps-mem-2 = <0x3a98>;
204 xlnx,twc-ps-mem-3 = <0x3a98>;
205 xlnx,twp-ps-mem-0 = <0x11170>;
206 xlnx,twp-ps-mem-1 = <0x2ee0>;
207 xlnx,twp-ps-mem-2 = <0x2ee0>;
208 xlnx,twp-ps-mem-3 = <0x2ee0>;
209 xlnx,xcl0-linesize = <0x4>;
210 xlnx,xcl0-writexfer = <0x1>;
211 xlnx,xcl1-linesize = <0x4>;
212 xlnx,xcl1-writexfer = <0x1>;
213 xlnx,xcl2-linesize = <0x4>;
214 xlnx,xcl2-writexfer = <0x1>;
215 xlnx,xcl3-linesize = <0x4>;
216 xlnx,xcl3-writexfer = <0x1>;
217 } ;
218 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
219 #address-cells = <1>;
220 #size-cells = <1>;
221 compatible = "xlnx,compound";
222 ranges ;
223 ethernet@81c00000 {
224 compatible = "xlnx,xps-ll-temac-1.01.b", "xlnx,xps-ll-temac-1.00.a";
225 interrupt-parent = <&xps_intc_0>;
226 interrupts = < 5 2 >;
227 llink-connected = <&PIM3>;
228 local-mac-address = [ 00 0a 35 00 00 00 ];
229 reg = < 0x81c00000 0x40 >;
230 xlnx,bus2core-clk-ratio = <0x1>;
231 xlnx,phy-type = <0x1>;
232 xlnx,phyaddr = <0x1>;
233 xlnx,rxcsum = <0x0>;
234 xlnx,rxfifo = <0x1000>;
235 xlnx,temac-type = <0x0>;
236 xlnx,txcsum = <0x0>;
237 xlnx,txfifo = <0x1000>;
238 } ;
239 } ;
240 IIC_EEPROM: i2c@81600000 {
241 compatible = "xlnx,xps-iic-2.00.a";
242 interrupt-parent = <&xps_intc_0>;
243 interrupts = < 6 2 >;
244 reg = < 0x81600000 0x10000 >;
245 xlnx,clk-freq = <0x7735940>;
246 xlnx,family = "virtex5";
247 xlnx,gpo-width = <0x1>;
248 xlnx,iic-freq = <0x186a0>;
249 xlnx,scl-inertial-delay = <0x0>;
250 xlnx,sda-inertial-delay = <0x0>;
251 xlnx,ten-bit-adr = <0x0>;
252 } ;
253 LEDs_8Bit: gpio@81400000 {
254 compatible = "xlnx,xps-gpio-1.00.a";
255 interrupt-parent = <&xps_intc_0>;
256 interrupts = < 7 2 >;
257 reg = < 0x81400000 0x10000 >;
258 xlnx,all-inputs = <0x0>;
259 xlnx,all-inputs-2 = <0x0>;
260 xlnx,dout-default = <0x0>;
261 xlnx,dout-default-2 = <0x0>;
262 xlnx,family = "virtex5";
263 xlnx,gpio-width = <0x8>;
264 xlnx,interrupt-present = <0x1>;
265 xlnx,is-bidir = <0x1>;
266 xlnx,is-bidir-2 = <0x1>;
267 xlnx,is-dual = <0x0>;
268 xlnx,tri-default = <0xffffffff>;
269 xlnx,tri-default-2 = <0xffffffff>;
270 #gpio-cells = <2>;
271 gpio-controller;
272 } ;
273
274 gpio-leds {
275 compatible = "gpio-leds";
276
277 heartbeat {
278 label = "Heartbeat";
279 gpios = <&LEDs_8Bit 4 1>;
280 linux,default-trigger = "heartbeat";
281 };
282
283 yellow {
284 label = "Yellow";
285 gpios = <&LEDs_8Bit 5 1>;
286 };
287
288 red {
289 label = "Red";
290 gpios = <&LEDs_8Bit 6 1>;
291 };
292
293 green {
294 label = "Green";
295 gpios = <&LEDs_8Bit 7 1>;
296 };
297 } ;
298 RS232_Uart_1: serial@84000000 {
299 clock-frequency = <125000000>;
300 compatible = "xlnx,xps-uartlite-1.00.a";
301 current-speed = <115200>;
302 device_type = "serial";
303 interrupt-parent = <&xps_intc_0>;
304 interrupts = < 8 0 >;
305 port-number = <0>;
306 reg = < 0x84000000 0x10000 >;
307 xlnx,baudrate = <0x1c200>;
308 xlnx,data-bits = <0x8>;
309 xlnx,family = "virtex5";
310 xlnx,odd-parity = <0x0>;
311 xlnx,use-parity = <0x0>;
312 } ;
313 SysACE_CompactFlash: sysace@83600000 {
314 compatible = "xlnx,xps-sysace-1.00.a";
315 interrupt-parent = <&xps_intc_0>;
316 interrupts = < 4 2 >;
317 reg = < 0x83600000 0x10000 >;
318 xlnx,family = "virtex5";
319 xlnx,mem-width = <0x10>;
320 } ;
321 debug_module: debug@84400000 {
322 compatible = "xlnx,mdm-1.00.d";
323 reg = < 0x84400000 0x10000 >;
324 xlnx,family = "virtex5";
325 xlnx,interconnect = <0x1>;
326 xlnx,jtag-chain = <0x2>;
327 xlnx,mb-dbg-ports = <0x1>;
328 xlnx,uart-width = <0x8>;
329 xlnx,use-uart = <0x1>;
330 xlnx,write-fsl-ports = <0x0>;
331 } ;
332 mpmc@90000000 {
333 #address-cells = <1>;
334 #size-cells = <1>;
335 compatible = "xlnx,mpmc-4.02.a";
336 ranges ;
337 PIM3: sdma@84600180 {
338 compatible = "xlnx,ll-dma-1.00.a";
339 interrupt-parent = <&xps_intc_0>;
340 interrupts = < 2 2 1 2 >;
341 reg = < 0x84600180 0x80 >;
342 } ;
343 } ;
344 xps_intc_0: interrupt-controller@81800000 {
345 #interrupt-cells = <0x2>;
346 compatible = "xlnx,xps-intc-1.00.a";
347 interrupt-controller ;
348 reg = < 0x81800000 0x10000 >;
349 xlnx,kind-of-intr = <0x100>;
350 xlnx,num-intr-inputs = <0x9>;
351 } ;
352 xps_timer_1: timer@83c00000 {
353 compatible = "xlnx,xps-timer-1.00.a";
354 interrupt-parent = <&xps_intc_0>;
355 interrupts = < 3 2 >;
356 reg = < 0x83c00000 0x10000 >;
357 xlnx,count-width = <0x20>;
358 xlnx,family = "virtex5";
359 xlnx,gen0-assert = <0x1>;
360 xlnx,gen1-assert = <0x1>;
361 xlnx,one-timer-only = <0x0>;
362 xlnx,trig0-assert = <0x1>;
363 xlnx,trig1-assert = <0x1>;
364 } ;
365 } ;
366} ;
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-08 03:59:04 -0500