diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-davinci/include/mach/nand.h | 8 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/nand.h | 31 |
2 files changed, 25 insertions, 14 deletions
diff --git a/arch/arm/mach-davinci/include/mach/nand.h b/arch/arm/mach-davinci/include/mach/nand.h index aa482841270b..b520c4b5678a 100644 --- a/arch/arm/mach-davinci/include/mach/nand.h +++ b/arch/arm/mach-davinci/include/mach/nand.h | |||
@@ -68,10 +68,14 @@ struct davinci_nand_pdata { /* platform_data */ | |||
68 | 68 | ||
69 | /* none == NAND_ECC_NONE (strongly *not* advised!!) | 69 | /* none == NAND_ECC_NONE (strongly *not* advised!!) |
70 | * soft == NAND_ECC_SOFT | 70 | * soft == NAND_ECC_SOFT |
71 | * 1-bit == NAND_ECC_HW | 71 | * else == NAND_ECC_HW, according to ecc_bits |
72 | * 4-bit == NAND_ECC_HW_SYNDROME (not on all chips) | 72 | * |
73 | * All DaVinci-family chips support 1-bit hardware ECC. | ||
74 | * Newer ones also support 4-bit ECC, but are awkward | ||
75 | * using it with large page chips. | ||
73 | */ | 76 | */ |
74 | nand_ecc_modes_t ecc_mode; | 77 | nand_ecc_modes_t ecc_mode; |
78 | u8 ecc_bits; | ||
75 | 79 | ||
76 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ | 80 | /* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */ |
77 | unsigned options; | 81 | unsigned options; |
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h index f4dcd14af059..18f958801e64 100644 --- a/arch/arm/plat-s3c/include/plat/nand.h +++ b/arch/arm/plat-s3c/include/plat/nand.h | |||
@@ -10,19 +10,26 @@ | |||
10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
11 | */ | 11 | */ |
12 | 12 | ||
13 | /* struct s3c2410_nand_set | 13 | /** |
14 | * struct s3c2410_nand_set - define a set of one or more nand chips | ||
15 | * @disable_ecc: Entirely disable ECC - Dangerous | ||
16 | * @flash_bbt: Openmoko u-boot can create a Bad Block Table | ||
17 | * Setting this flag will allow the kernel to | ||
18 | * look for it at boot time and also skip the NAND | ||
19 | * scan. | ||
20 | * @nr_chips: Number of chips in this set | ||
21 | * @nr_partitions: Number of partitions pointed to by @partitions | ||
22 | * @name: Name of set (optional) | ||
23 | * @nr_map: Map for low-layer logical to physical chip numbers (option) | ||
24 | * @partitions: The mtd partition list | ||
14 | * | 25 | * |
15 | * define an set of one or more nand chips registered with an unique mtd | 26 | * define a set of one or more nand chips registered with an unique mtd. Also |
16 | * | 27 | * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger |
17 | * nr_chips = number of chips in this set | 28 | * a warning at boot time. |
18 | * nr_partitions = number of partitions pointed to be partitoons (or zero) | 29 | */ |
19 | * name = name of set (optional) | ||
20 | * nr_map = map for low-layer logical to physical chip numbers (option) | ||
21 | * partitions = mtd partition list | ||
22 | */ | ||
23 | |||
24 | struct s3c2410_nand_set { | 30 | struct s3c2410_nand_set { |
25 | unsigned int disable_ecc : 1; | 31 | unsigned int disable_ecc:1; |
32 | unsigned int flash_bbt:1; | ||
26 | 33 | ||
27 | int nr_chips; | 34 | int nr_chips; |
28 | int nr_partitions; | 35 | int nr_partitions; |
@@ -39,7 +46,7 @@ struct s3c2410_platform_nand { | |||
39 | int twrph0; /* active time for nWE/nOE */ | 46 | int twrph0; /* active time for nWE/nOE */ |
40 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ | 47 | int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */ |
41 | 48 | ||
42 | unsigned int ignore_unset_ecc : 1; | 49 | unsigned int ignore_unset_ecc:1; |
43 | 50 | ||
44 | int nr_sets; | 51 | int nr_sets; |
45 | struct s3c2410_nand_set *sets; | 52 | struct s3c2410_nand_set *sets; |