aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c1310
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h1287
-rw-r--r--arch/arm/mach-omap2/cm44xx.h90
-rw-r--r--arch/arm/mach-omap2/control.c25
-rw-r--r--arch/arm/mach-omap2/hsmmc.c67
-rw-r--r--arch/arm/mach-omap2/id.c2
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h391
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h1409
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h236
-rw-r--r--arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h92
-rw-r--r--arch/arm/mach-omap2/powerdomains44xx.h2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-44xx.h1314
-rw-r--r--arch/arm/mach-omap2/prm44xx.h14
-rw-r--r--arch/arm/mach-omap2/sram34xx.S6
-rw-r--r--arch/arm/plat-omap/common.c3
-rw-r--r--arch/arm/plat-omap/include/plat/common.h1
-rw-r--r--arch/arm/plat-omap/include/plat/control.h31
-rw-r--r--arch/arm/plat-omap/include/plat/powerdomain.h1
18 files changed, 4499 insertions, 1782 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index e10db7a90cb2..67fac44cb6e6 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -17,12 +17,15 @@
17 * This program is free software; you can redistribute it and/or modify 17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as 18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation. 19 * published by the Free Software Foundation.
20 *
21 * XXX Some of the ES1 clocks have been removed/changed; once support
22 * is added for discriminating clocks by ES level, these should be added back
23 * in.
20 */ 24 */
21 25
22#include <linux/kernel.h> 26#include <linux/kernel.h>
23#include <linux/list.h> 27#include <linux/list.h>
24#include <linux/clk.h> 28#include <linux/clk.h>
25
26#include <plat/control.h> 29#include <plat/control.h>
27#include <plat/clkdev_omap.h> 30#include <plat/clkdev_omap.h>
28 31
@@ -175,21 +178,27 @@ static struct clk sys_clkin_ck = {
175 .recalc = &omap2_clksel_recalc, 178 .recalc = &omap2_clksel_recalc,
176}; 179};
177 180
181static struct clk tie_low_clock_ck = {
182 .name = "tie_low_clock_ck",
183 .rate = 0,
184 .ops = &clkops_null,
185};
186
178static struct clk utmi_phy_clkout_ck = { 187static struct clk utmi_phy_clkout_ck = {
179 .name = "utmi_phy_clkout_ck", 188 .name = "utmi_phy_clkout_ck",
180 .rate = 12000000, 189 .rate = 60000000,
181 .ops = &clkops_null, 190 .ops = &clkops_null,
182}; 191};
183 192
184static struct clk xclk60mhsp1_ck = { 193static struct clk xclk60mhsp1_ck = {
185 .name = "xclk60mhsp1_ck", 194 .name = "xclk60mhsp1_ck",
186 .rate = 12000000, 195 .rate = 60000000,
187 .ops = &clkops_null, 196 .ops = &clkops_null,
188}; 197};
189 198
190static struct clk xclk60mhsp2_ck = { 199static struct clk xclk60mhsp2_ck = {
191 .name = "xclk60mhsp2_ck", 200 .name = "xclk60mhsp2_ck",
192 .rate = 12000000, 201 .rate = 60000000,
193 .ops = &clkops_null, 202 .ops = &clkops_null,
194}; 203};
195 204
@@ -201,39 +210,23 @@ static struct clk xclk60motg_ck = {
201 210
202/* Module clocks and DPLL outputs */ 211/* Module clocks and DPLL outputs */
203 212
204static const struct clksel_rate div2_1to2_rates[] = { 213static const struct clksel abe_dpll_bypass_clk_mux_sel[] = {
205 { .div = 1, .val = 0, .flags = RATE_IN_4430 }, 214 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
206 { .div = 2, .val = 1, .flags = RATE_IN_4430 }, 215 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
207 { .div = 0 },
208};
209
210static const struct clksel dpll_sys_ref_clk_div[] = {
211 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
212 { .parent = NULL }, 216 { .parent = NULL },
213}; 217};
214 218
215static struct clk dpll_sys_ref_clk = { 219static struct clk abe_dpll_bypass_clk_mux_ck = {
216 .name = "dpll_sys_ref_clk", 220 .name = "abe_dpll_bypass_clk_mux_ck",
217 .parent = &sys_clkin_ck, 221 .parent = &sys_clkin_ck,
218 .clksel = dpll_sys_ref_clk_div,
219 .clksel_reg = OMAP4430_CM_DPLL_SYS_REF_CLKSEL,
220 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
221 .ops = &clkops_null, 222 .ops = &clkops_null,
222 .recalc = &omap2_clksel_recalc, 223 .recalc = &followparent_recalc,
223 .round_rate = &omap2_clksel_round_rate,
224 .set_rate = &omap2_clksel_set_rate,
225};
226
227static const struct clksel abe_dpll_refclk_mux_sel[] = {
228 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates },
229 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
230 { .parent = NULL },
231}; 224};
232 225
233static struct clk abe_dpll_refclk_mux_ck = { 226static struct clk abe_dpll_refclk_mux_ck = {
234 .name = "abe_dpll_refclk_mux_ck", 227 .name = "abe_dpll_refclk_mux_ck",
235 .parent = &dpll_sys_ref_clk, 228 .parent = &sys_clkin_ck,
236 .clksel = abe_dpll_refclk_mux_sel, 229 .clksel = abe_dpll_bypass_clk_mux_sel,
237 .init = &omap2_init_clksel_parent, 230 .init = &omap2_init_clksel_parent,
238 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL, 231 .clksel_reg = OMAP4430_CM_ABE_PLL_REF_CLKSEL,
239 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 232 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
@@ -244,7 +237,7 @@ static struct clk abe_dpll_refclk_mux_ck = {
244/* DPLL_ABE */ 237/* DPLL_ABE */
245static struct dpll_data dpll_abe_dd = { 238static struct dpll_data dpll_abe_dd = {
246 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE, 239 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_ABE,
247 .clk_bypass = &sys_clkin_ck, 240 .clk_bypass = &abe_dpll_bypass_clk_mux_ck,
248 .clk_ref = &abe_dpll_refclk_mux_ck, 241 .clk_ref = &abe_dpll_refclk_mux_ck,
249 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE, 242 .control_reg = OMAP4430_CM_CLKMODE_DPLL_ABE,
250 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 243 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
@@ -310,6 +303,12 @@ static struct clk abe_clk = {
310 .set_rate = &omap2_clksel_set_rate, 303 .set_rate = &omap2_clksel_set_rate,
311}; 304};
312 305
306static const struct clksel_rate div2_1to2_rates[] = {
307 { .div = 1, .val = 0, .flags = RATE_IN_4430 },
308 { .div = 2, .val = 1, .flags = RATE_IN_4430 },
309 { .div = 0 },
310};
311
313static const struct clksel aess_fclk_div[] = { 312static const struct clksel aess_fclk_div[] = {
314 { .parent = &abe_clk, .rates = div2_1to2_rates }, 313 { .parent = &abe_clk, .rates = div2_1to2_rates },
315 { .parent = NULL }, 314 { .parent = NULL },
@@ -380,14 +379,14 @@ static struct clk dpll_abe_m3_ck = {
380}; 379};
381 380
382static const struct clksel core_hsd_byp_clk_mux_sel[] = { 381static const struct clksel core_hsd_byp_clk_mux_sel[] = {
383 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 382 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
384 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates }, 383 { .parent = &dpll_abe_m3_ck, .rates = div_1_1_rates },
385 { .parent = NULL }, 384 { .parent = NULL },
386}; 385};
387 386
388static struct clk core_hsd_byp_clk_mux_ck = { 387static struct clk core_hsd_byp_clk_mux_ck = {
389 .name = "core_hsd_byp_clk_mux_ck", 388 .name = "core_hsd_byp_clk_mux_ck",
390 .parent = &dpll_sys_ref_clk, 389 .parent = &sys_clkin_ck,
391 .clksel = core_hsd_byp_clk_mux_sel, 390 .clksel = core_hsd_byp_clk_mux_sel,
392 .init = &omap2_init_clksel_parent, 391 .init = &omap2_init_clksel_parent,
393 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 392 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
@@ -400,7 +399,7 @@ static struct clk core_hsd_byp_clk_mux_ck = {
400static struct dpll_data dpll_core_dd = { 399static struct dpll_data dpll_core_dd = {
401 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE, 400 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_CORE,
402 .clk_bypass = &core_hsd_byp_clk_mux_ck, 401 .clk_bypass = &core_hsd_byp_clk_mux_ck,
403 .clk_ref = &dpll_sys_ref_clk, 402 .clk_ref = &sys_clkin_ck,
404 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE, 403 .control_reg = OMAP4430_CM_CLKMODE_DPLL_CORE,
405 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 404 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
406 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE, 405 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_CORE,
@@ -418,7 +417,7 @@ static struct dpll_data dpll_core_dd = {
418 417
419static struct clk dpll_core_ck = { 418static struct clk dpll_core_ck = {
420 .name = "dpll_core_ck", 419 .name = "dpll_core_ck",
421 .parent = &dpll_sys_ref_clk, 420 .parent = &sys_clkin_ck,
422 .dpll_data = &dpll_core_dd, 421 .dpll_data = &dpll_core_dd,
423 .init = &omap2_init_dpll_parent, 422 .init = &omap2_init_dpll_parent,
424 .ops = &clkops_null, 423 .ops = &clkops_null,
@@ -596,14 +595,14 @@ static struct clk dpll_core_m7_ck = {
596}; 595};
597 596
598static const struct clksel iva_hsd_byp_clk_mux_sel[] = { 597static const struct clksel iva_hsd_byp_clk_mux_sel[] = {
599 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 598 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
600 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates }, 599 { .parent = &div_iva_hs_clk, .rates = div_1_1_rates },
601 { .parent = NULL }, 600 { .parent = NULL },
602}; 601};
603 602
604static struct clk iva_hsd_byp_clk_mux_ck = { 603static struct clk iva_hsd_byp_clk_mux_ck = {
605 .name = "iva_hsd_byp_clk_mux_ck", 604 .name = "iva_hsd_byp_clk_mux_ck",
606 .parent = &dpll_sys_ref_clk, 605 .parent = &sys_clkin_ck,
607 .ops = &clkops_null, 606 .ops = &clkops_null,
608 .recalc = &followparent_recalc, 607 .recalc = &followparent_recalc,
609}; 608};
@@ -612,7 +611,7 @@ static struct clk iva_hsd_byp_clk_mux_ck = {
612static struct dpll_data dpll_iva_dd = { 611static struct dpll_data dpll_iva_dd = {
613 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA, 612 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_IVA,
614 .clk_bypass = &iva_hsd_byp_clk_mux_ck, 613 .clk_bypass = &iva_hsd_byp_clk_mux_ck,
615 .clk_ref = &dpll_sys_ref_clk, 614 .clk_ref = &sys_clkin_ck,
616 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA, 615 .control_reg = OMAP4430_CM_CLKMODE_DPLL_IVA,
617 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 616 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
618 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA, 617 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_IVA,
@@ -630,7 +629,7 @@ static struct dpll_data dpll_iva_dd = {
630 629
631static struct clk dpll_iva_ck = { 630static struct clk dpll_iva_ck = {
632 .name = "dpll_iva_ck", 631 .name = "dpll_iva_ck",
633 .parent = &dpll_sys_ref_clk, 632 .parent = &sys_clkin_ck,
634 .dpll_data = &dpll_iva_dd, 633 .dpll_data = &dpll_iva_dd,
635 .init = &omap2_init_dpll_parent, 634 .init = &omap2_init_dpll_parent,
636 .ops = &clkops_omap3_noncore_dpll_ops, 635 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -672,7 +671,7 @@ static struct clk dpll_iva_m5_ck = {
672static struct dpll_data dpll_mpu_dd = { 671static struct dpll_data dpll_mpu_dd = {
673 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU, 672 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_MPU,
674 .clk_bypass = &div_mpu_hs_clk, 673 .clk_bypass = &div_mpu_hs_clk,
675 .clk_ref = &dpll_sys_ref_clk, 674 .clk_ref = &sys_clkin_ck,
676 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU, 675 .control_reg = OMAP4430_CM_CLKMODE_DPLL_MPU,
677 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 676 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
678 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU, 677 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_MPU,
@@ -690,7 +689,7 @@ static struct dpll_data dpll_mpu_dd = {
690 689
691static struct clk dpll_mpu_ck = { 690static struct clk dpll_mpu_ck = {
692 .name = "dpll_mpu_ck", 691 .name = "dpll_mpu_ck",
693 .parent = &dpll_sys_ref_clk, 692 .parent = &sys_clkin_ck,
694 .dpll_data = &dpll_mpu_dd, 693 .dpll_data = &dpll_mpu_dd,
695 .init = &omap2_init_dpll_parent, 694 .init = &omap2_init_dpll_parent,
696 .ops = &clkops_omap3_noncore_dpll_ops, 695 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -724,14 +723,14 @@ static struct clk per_hs_clk_div_ck = {
724}; 723};
725 724
726static const struct clksel per_hsd_byp_clk_mux_sel[] = { 725static const struct clksel per_hsd_byp_clk_mux_sel[] = {
727 { .parent = &dpll_sys_ref_clk, .rates = div_1_0_rates }, 726 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
728 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates }, 727 { .parent = &per_hs_clk_div_ck, .rates = div_1_1_rates },
729 { .parent = NULL }, 728 { .parent = NULL },
730}; 729};
731 730
732static struct clk per_hsd_byp_clk_mux_ck = { 731static struct clk per_hsd_byp_clk_mux_ck = {
733 .name = "per_hsd_byp_clk_mux_ck", 732 .name = "per_hsd_byp_clk_mux_ck",
734 .parent = &dpll_sys_ref_clk, 733 .parent = &sys_clkin_ck,
735 .clksel = per_hsd_byp_clk_mux_sel, 734 .clksel = per_hsd_byp_clk_mux_sel,
736 .init = &omap2_init_clksel_parent, 735 .init = &omap2_init_clksel_parent,
737 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 736 .clksel_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
@@ -744,7 +743,7 @@ static struct clk per_hsd_byp_clk_mux_ck = {
744static struct dpll_data dpll_per_dd = { 743static struct dpll_data dpll_per_dd = {
745 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER, 744 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_PER,
746 .clk_bypass = &per_hsd_byp_clk_mux_ck, 745 .clk_bypass = &per_hsd_byp_clk_mux_ck,
747 .clk_ref = &dpll_sys_ref_clk, 746 .clk_ref = &sys_clkin_ck,
748 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER, 747 .control_reg = OMAP4430_CM_CLKMODE_DPLL_PER,
749 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 748 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
750 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER, 749 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_PER,
@@ -762,7 +761,7 @@ static struct dpll_data dpll_per_dd = {
762 761
763static struct clk dpll_per_ck = { 762static struct clk dpll_per_ck = {
764 .name = "dpll_per_ck", 763 .name = "dpll_per_ck",
765 .parent = &dpll_sys_ref_clk, 764 .parent = &sys_clkin_ck,
766 .dpll_data = &dpll_per_dd, 765 .dpll_data = &dpll_per_dd,
767 .init = &omap2_init_dpll_parent, 766 .init = &omap2_init_dpll_parent,
768 .ops = &clkops_omap3_noncore_dpll_ops, 767 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -858,8 +857,8 @@ static struct clk dpll_per_m7_ck = {
858/* DPLL_UNIPRO */ 857/* DPLL_UNIPRO */
859static struct dpll_data dpll_unipro_dd = { 858static struct dpll_data dpll_unipro_dd = {
860 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO, 859 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
861 .clk_bypass = &dpll_sys_ref_clk, 860 .clk_bypass = &sys_clkin_ck,
862 .clk_ref = &dpll_sys_ref_clk, 861 .clk_ref = &sys_clkin_ck,
863 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO, 862 .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
864 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 863 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
865 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO, 864 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
@@ -877,7 +876,7 @@ static struct dpll_data dpll_unipro_dd = {
877 876
878static struct clk dpll_unipro_ck = { 877static struct clk dpll_unipro_ck = {
879 .name = "dpll_unipro_ck", 878 .name = "dpll_unipro_ck",
880 .parent = &dpll_sys_ref_clk, 879 .parent = &sys_clkin_ck,
881 .dpll_data = &dpll_unipro_dd, 880 .dpll_data = &dpll_unipro_dd,
882 .init = &omap2_init_dpll_parent, 881 .init = &omap2_init_dpll_parent,
883 .ops = &clkops_omap3_noncore_dpll_ops, 882 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -914,7 +913,8 @@ static struct clk usb_hs_clk_div_ck = {
914static struct dpll_data dpll_usb_dd = { 913static struct dpll_data dpll_usb_dd = {
915 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB, 914 .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_USB,
916 .clk_bypass = &usb_hs_clk_div_ck, 915 .clk_bypass = &usb_hs_clk_div_ck,
917 .clk_ref = &dpll_sys_ref_clk, 916 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL,
917 .clk_ref = &sys_clkin_ck,
918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB, 918 .control_reg = OMAP4430_CM_CLKMODE_DPLL_USB,
919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), 919 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB, 920 .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_USB,
@@ -927,13 +927,12 @@ static struct dpll_data dpll_usb_dd = {
927 .max_multiplier = OMAP4430_MAX_DPLL_MULT, 927 .max_multiplier = OMAP4430_MAX_DPLL_MULT,
928 .max_divider = OMAP4430_MAX_DPLL_DIV, 928 .max_divider = OMAP4430_MAX_DPLL_DIV,
929 .min_divider = 1, 929 .min_divider = 1,
930 .flags = DPLL_J_TYPE | DPLL_NO_DCO_SEL
931}; 930};
932 931
933 932
934static struct clk dpll_usb_ck = { 933static struct clk dpll_usb_ck = {
935 .name = "dpll_usb_ck", 934 .name = "dpll_usb_ck",
936 .parent = &dpll_sys_ref_clk, 935 .parent = &sys_clkin_ck,
937 .dpll_data = &dpll_usb_dd, 936 .dpll_data = &dpll_usb_dd,
938 .init = &omap2_init_dpll_parent, 937 .init = &omap2_init_dpll_parent,
939 .ops = &clkops_omap3_noncore_dpll_ops, 938 .ops = &clkops_omap3_noncore_dpll_ops,
@@ -1222,7 +1221,7 @@ static struct clk per_abe_24m_fclk = {
1222static const struct clksel pmd_stm_clock_mux_sel[] = { 1221static const struct clksel pmd_stm_clock_mux_sel[] = {
1223 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1222 { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
1224 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates }, 1223 { .parent = &dpll_core_m6_ck, .rates = div_1_1_rates },
1225 { .parent = &dpll_per_m7_ck, .rates = div_1_2_rates }, 1224 { .parent = &tie_low_clock_ck, .rates = div_1_2_rates },
1226 { .parent = NULL }, 1225 { .parent = NULL },
1227}; 1226};
1228 1227
@@ -1240,10 +1239,15 @@ static struct clk pmd_trace_clk_mux_ck = {
1240 .recalc = &followparent_recalc, 1239 .recalc = &followparent_recalc,
1241}; 1240};
1242 1241
1242static const struct clksel syc_clk_div_div[] = {
1243 { .parent = &sys_clkin_ck, .rates = div2_1to2_rates },
1244 { .parent = NULL },
1245};
1246
1243static struct clk syc_clk_div_ck = { 1247static struct clk syc_clk_div_ck = {
1244 .name = "syc_clk_div_ck", 1248 .name = "syc_clk_div_ck",
1245 .parent = &sys_clkin_ck, 1249 .parent = &sys_clkin_ck,
1246 .clksel = dpll_sys_ref_clk_div, 1250 .clksel = syc_clk_div_div,
1247 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL, 1251 .clksel_reg = OMAP4430_CM_ABE_DSS_SYS_CLKSEL,
1248 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK, 1252 .clksel_mask = OMAP4430_CLKSEL_0_0_MASK,
1249 .ops = &clkops_null, 1253 .ops = &clkops_null,
@@ -1284,13 +1288,13 @@ static struct clk aess_fck = {
1284 .recalc = &followparent_recalc, 1288 .recalc = &followparent_recalc,
1285}; 1289};
1286 1290
1287static struct clk cust_efuse_fck = { 1291static struct clk bandgap_fclk = {
1288 .name = "cust_efuse_fck", 1292 .name = "bandgap_fclk",
1289 .ops = &clkops_omap2_dflt, 1293 .ops = &clkops_omap2_dflt,
1290 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL, 1294 .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
1291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1295 .enable_bit = OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT,
1292 .clkdm_name = "l4_cefuse_clkdm", 1296 .clkdm_name = "l4_wkup_clkdm",
1293 .parent = &sys_clkin_ck, 1297 .parent = &sys_32k_ck,
1294 .recalc = &followparent_recalc, 1298 .recalc = &followparent_recalc,
1295}; 1299};
1296 1300
@@ -1344,6 +1348,56 @@ static struct clk dmic_fck = {
1344 .clkdm_name = "abe_clkdm", 1348 .clkdm_name = "abe_clkdm",
1345}; 1349};
1346 1350
1351static struct clk dsp_fck = {
1352 .name = "dsp_fck",
1353 .ops = &clkops_omap2_dflt,
1354 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
1355 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1356 .clkdm_name = "tesla_clkdm",
1357 .parent = &dpll_iva_m4_ck,
1358 .recalc = &followparent_recalc,
1359};
1360
1361static struct clk dss_sys_clk = {
1362 .name = "dss_sys_clk",
1363 .ops = &clkops_omap2_dflt,
1364 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1365 .enable_bit = OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT,
1366 .clkdm_name = "l3_dss_clkdm",
1367 .parent = &syc_clk_div_ck,
1368 .recalc = &followparent_recalc,
1369};
1370
1371static struct clk dss_tv_clk = {
1372 .name = "dss_tv_clk",
1373 .ops = &clkops_omap2_dflt,
1374 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1375 .enable_bit = OMAP4430_OPTFCLKEN_TV_CLK_SHIFT,
1376 .clkdm_name = "l3_dss_clkdm",
1377 .parent = &extalt_clkin_ck,
1378 .recalc = &followparent_recalc,
1379};
1380
1381static struct clk dss_dss_clk = {
1382 .name = "dss_dss_clk",
1383 .ops = &clkops_omap2_dflt,
1384 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1385 .enable_bit = OMAP4430_OPTFCLKEN_DSSCLK_SHIFT,
1386 .clkdm_name = "l3_dss_clkdm",
1387 .parent = &dpll_per_m5_ck,
1388 .recalc = &followparent_recalc,
1389};
1390
1391static struct clk dss_48mhz_clk = {
1392 .name = "dss_48mhz_clk",
1393 .ops = &clkops_omap2_dflt,
1394 .enable_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
1395 .enable_bit = OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT,
1396 .clkdm_name = "l3_dss_clkdm",
1397 .parent = &func_48mc_fclk,
1398 .recalc = &followparent_recalc,
1399};
1400
1347static struct clk dss_fck = { 1401static struct clk dss_fck = {
1348 .name = "dss_fck", 1402 .name = "dss_fck",
1349 .ops = &clkops_omap2_dflt, 1403 .ops = &clkops_omap2_dflt,
@@ -1354,18 +1408,18 @@ static struct clk dss_fck = {
1354 .recalc = &followparent_recalc, 1408 .recalc = &followparent_recalc,
1355}; 1409};
1356 1410
1357static struct clk ducati_ick = { 1411static struct clk efuse_ctrl_cust_fck = {
1358 .name = "ducati_ick", 1412 .name = "efuse_ctrl_cust_fck",
1359 .ops = &clkops_omap2_dflt, 1413 .ops = &clkops_omap2_dflt,
1360 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL, 1414 .enable_reg = OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL,
1361 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1415 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1362 .clkdm_name = "ducati_clkdm", 1416 .clkdm_name = "l4_cefuse_clkdm",
1363 .parent = &ducati_clk_mux_ck, 1417 .parent = &sys_clkin_ck,
1364 .recalc = &followparent_recalc, 1418 .recalc = &followparent_recalc,
1365}; 1419};
1366 1420
1367static struct clk emif1_ick = { 1421static struct clk emif1_fck = {
1368 .name = "emif1_ick", 1422 .name = "emif1_fck",
1369 .ops = &clkops_omap2_dflt, 1423 .ops = &clkops_omap2_dflt,
1370 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL, 1424 .enable_reg = OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL,
1371 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1425 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1375,8 +1429,8 @@ static struct clk emif1_ick = {
1375 .recalc = &followparent_recalc, 1429 .recalc = &followparent_recalc,
1376}; 1430};
1377 1431
1378static struct clk emif2_ick = { 1432static struct clk emif2_fck = {
1379 .name = "emif2_ick", 1433 .name = "emif2_fck",
1380 .ops = &clkops_omap2_dflt, 1434 .ops = &clkops_omap2_dflt,
1381 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL, 1435 .enable_reg = OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL,
1382 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1436 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1407,42 +1461,24 @@ static struct clk fdif_fck = {
1407 .clkdm_name = "iss_clkdm", 1461 .clkdm_name = "iss_clkdm",
1408}; 1462};
1409 1463
1410static const struct clksel per_sgx_fclk_div[] = { 1464static struct clk fpka_fck = {
1411 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates }, 1465 .name = "fpka_fck",
1412 { .parent = NULL }, 1466 .ops = &clkops_omap2_dflt,
1413}; 1467 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL,
1414 1468 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1415static struct clk per_sgx_fclk = { 1469 .clkdm_name = "l4_secure_clkdm",
1416 .name = "per_sgx_fclk", 1470 .parent = &l4_div_ck,
1417 .parent = &dpll_per_m2x2_ck, 1471 .recalc = &followparent_recalc,
1418 .clksel = per_sgx_fclk_div,
1419 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1420 .clksel_mask = OMAP4430_CLKSEL_PER_192M_MASK,
1421 .ops = &clkops_null,
1422 .recalc = &omap2_clksel_recalc,
1423 .round_rate = &omap2_clksel_round_rate,
1424 .set_rate = &omap2_clksel_set_rate,
1425};
1426
1427static const struct clksel sgx_clk_mux_sel[] = {
1428 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1429 { .parent = &per_sgx_fclk, .rates = div_1_1_rates },
1430 { .parent = NULL },
1431}; 1472};
1432 1473
1433/* Merged sgx_clk_mux into gfx */ 1474static struct clk gpio1_dbclk = {
1434static struct clk gfx_fck = { 1475 .name = "gpio1_dbclk",
1435 .name = "gfx_fck",
1436 .parent = &dpll_core_m7_ck,
1437 .clksel = sgx_clk_mux_sel,
1438 .init = &omap2_init_clksel_parent,
1439 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1440 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1441 .ops = &clkops_omap2_dflt, 1476 .ops = &clkops_omap2_dflt,
1442 .recalc = &omap2_clksel_recalc, 1477 .enable_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
1443 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL, 1478 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1444 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1479 .clkdm_name = "l4_wkup_clkdm",
1445 .clkdm_name = "l3_gfx_clkdm", 1480 .parent = &sys_32k_ck,
1481 .recalc = &followparent_recalc,
1446}; 1482};
1447 1483
1448static struct clk gpio1_ick = { 1484static struct clk gpio1_ick = {
@@ -1455,6 +1491,16 @@ static struct clk gpio1_ick = {
1455 .recalc = &followparent_recalc, 1491 .recalc = &followparent_recalc,
1456}; 1492};
1457 1493
1494static struct clk gpio2_dbclk = {
1495 .name = "gpio2_dbclk",
1496 .ops = &clkops_omap2_dflt,
1497 .enable_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
1498 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1499 .clkdm_name = "l4_per_clkdm",
1500 .parent = &sys_32k_ck,
1501 .recalc = &followparent_recalc,
1502};
1503
1458static struct clk gpio2_ick = { 1504static struct clk gpio2_ick = {
1459 .name = "gpio2_ick", 1505 .name = "gpio2_ick",
1460 .ops = &clkops_omap2_dflt, 1506 .ops = &clkops_omap2_dflt,
@@ -1465,6 +1511,16 @@ static struct clk gpio2_ick = {
1465 .recalc = &followparent_recalc, 1511 .recalc = &followparent_recalc,
1466}; 1512};
1467 1513
1514static struct clk gpio3_dbclk = {
1515 .name = "gpio3_dbclk",
1516 .ops = &clkops_omap2_dflt,
1517 .enable_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
1518 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1519 .clkdm_name = "l4_per_clkdm",
1520 .parent = &sys_32k_ck,
1521 .recalc = &followparent_recalc,
1522};
1523
1468static struct clk gpio3_ick = { 1524static struct clk gpio3_ick = {
1469 .name = "gpio3_ick", 1525 .name = "gpio3_ick",
1470 .ops = &clkops_omap2_dflt, 1526 .ops = &clkops_omap2_dflt,
@@ -1475,6 +1531,16 @@ static struct clk gpio3_ick = {
1475 .recalc = &followparent_recalc, 1531 .recalc = &followparent_recalc,
1476}; 1532};
1477 1533
1534static struct clk gpio4_dbclk = {
1535 .name = "gpio4_dbclk",
1536 .ops = &clkops_omap2_dflt,
1537 .enable_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
1538 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1539 .clkdm_name = "l4_per_clkdm",
1540 .parent = &sys_32k_ck,
1541 .recalc = &followparent_recalc,
1542};
1543
1478static struct clk gpio4_ick = { 1544static struct clk gpio4_ick = {
1479 .name = "gpio4_ick", 1545 .name = "gpio4_ick",
1480 .ops = &clkops_omap2_dflt, 1546 .ops = &clkops_omap2_dflt,
@@ -1485,6 +1551,16 @@ static struct clk gpio4_ick = {
1485 .recalc = &followparent_recalc, 1551 .recalc = &followparent_recalc,
1486}; 1552};
1487 1553
1554static struct clk gpio5_dbclk = {
1555 .name = "gpio5_dbclk",
1556 .ops = &clkops_omap2_dflt,
1557 .enable_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
1558 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1559 .clkdm_name = "l4_per_clkdm",
1560 .parent = &sys_32k_ck,
1561 .recalc = &followparent_recalc,
1562};
1563
1488static struct clk gpio5_ick = { 1564static struct clk gpio5_ick = {
1489 .name = "gpio5_ick", 1565 .name = "gpio5_ick",
1490 .ops = &clkops_omap2_dflt, 1566 .ops = &clkops_omap2_dflt,
@@ -1495,6 +1571,16 @@ static struct clk gpio5_ick = {
1495 .recalc = &followparent_recalc, 1571 .recalc = &followparent_recalc,
1496}; 1572};
1497 1573
1574static struct clk gpio6_dbclk = {
1575 .name = "gpio6_dbclk",
1576 .ops = &clkops_omap2_dflt,
1577 .enable_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
1578 .enable_bit = OMAP4430_OPTFCLKEN_DBCLK_SHIFT,
1579 .clkdm_name = "l4_per_clkdm",
1580 .parent = &sys_32k_ck,
1581 .recalc = &followparent_recalc,
1582};
1583
1498static struct clk gpio6_ick = { 1584static struct clk gpio6_ick = {
1499 .name = "gpio6_ick", 1585 .name = "gpio6_ick",
1500 .ops = &clkops_omap2_dflt, 1586 .ops = &clkops_omap2_dflt,
@@ -1515,214 +1601,25 @@ static struct clk gpmc_ick = {
1515 .recalc = &followparent_recalc, 1601 .recalc = &followparent_recalc,
1516}; 1602};
1517 1603
1518static const struct clksel dmt1_clk_mux_sel[] = { 1604static const struct clksel sgx_clk_mux_sel[] = {
1519 { .parent = &sys_clkin_ck, .rates = div_1_0_rates }, 1605 { .parent = &dpll_core_m7_ck, .rates = div_1_0_rates },
1520 { .parent = &sys_32k_ck, .rates = div_1_1_rates }, 1606 { .parent = &dpll_per_m7_ck, .rates = div_1_1_rates },
1521 { .parent = NULL },
1522};
1523
1524/*
1525 * Merged dmt1_clk_mux into gptimer1
1526 * gptimer1 renamed temporarily into gpt1 to match OMAP3 convention
1527 */
1528static struct clk gpt1_fck = {
1529 .name = "gpt1_fck",
1530 .parent = &sys_clkin_ck,
1531 .clksel = dmt1_clk_mux_sel,
1532 .init = &omap2_init_clksel_parent,
1533 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1534 .clksel_mask = OMAP4430_CLKSEL_MASK,
1535 .ops = &clkops_omap2_dflt,
1536 .recalc = &omap2_clksel_recalc,
1537 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
1538 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1539 .clkdm_name = "l4_wkup_clkdm",
1540};
1541
1542/*
1543 * Merged cm2_dm10_mux into gptimer10
1544 * gptimer10 renamed temporarily into gpt10 to match OMAP3 convention
1545 */
1546static struct clk gpt10_fck = {
1547 .name = "gpt10_fck",
1548 .parent = &sys_clkin_ck,
1549 .clksel = dmt1_clk_mux_sel,
1550 .init = &omap2_init_clksel_parent,
1551 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1552 .clksel_mask = OMAP4430_CLKSEL_MASK,
1553 .ops = &clkops_omap2_dflt,
1554 .recalc = &omap2_clksel_recalc,
1555 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
1556 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1557 .clkdm_name = "l4_per_clkdm",
1558};
1559
1560/*
1561 * Merged cm2_dm11_mux into gptimer11
1562 * gptimer11 renamed temporarily into gpt11 to match OMAP3 convention
1563 */
1564static struct clk gpt11_fck = {
1565 .name = "gpt11_fck",
1566 .parent = &sys_clkin_ck,
1567 .clksel = dmt1_clk_mux_sel,
1568 .init = &omap2_init_clksel_parent,
1569 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1570 .clksel_mask = OMAP4430_CLKSEL_MASK,
1571 .ops = &clkops_omap2_dflt,
1572 .recalc = &omap2_clksel_recalc,
1573 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
1574 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1575 .clkdm_name = "l4_per_clkdm",
1576};
1577
1578/*
1579 * Merged cm2_dm2_mux into gptimer2
1580 * gptimer2 renamed temporarily into gpt2 to match OMAP3 convention
1581 */
1582static struct clk gpt2_fck = {
1583 .name = "gpt2_fck",
1584 .parent = &sys_clkin_ck,
1585 .clksel = dmt1_clk_mux_sel,
1586 .init = &omap2_init_clksel_parent,
1587 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1588 .clksel_mask = OMAP4430_CLKSEL_MASK,
1589 .ops = &clkops_omap2_dflt,
1590 .recalc = &omap2_clksel_recalc,
1591 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
1592 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1593 .clkdm_name = "l4_per_clkdm",
1594};
1595
1596/*
1597 * Merged cm2_dm3_mux into gptimer3
1598 * gptimer3 renamed temporarily into gpt3 to match OMAP3 convention
1599 */
1600static struct clk gpt3_fck = {
1601 .name = "gpt3_fck",
1602 .parent = &sys_clkin_ck,
1603 .clksel = dmt1_clk_mux_sel,
1604 .init = &omap2_init_clksel_parent,
1605 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1606 .clksel_mask = OMAP4430_CLKSEL_MASK,
1607 .ops = &clkops_omap2_dflt,
1608 .recalc = &omap2_clksel_recalc,
1609 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
1610 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1611 .clkdm_name = "l4_per_clkdm",
1612};
1613
1614/*
1615 * Merged cm2_dm4_mux into gptimer4
1616 * gptimer4 renamed temporarily into gpt4 to match OMAP3 convention
1617 */
1618static struct clk gpt4_fck = {
1619 .name = "gpt4_fck",
1620 .parent = &sys_clkin_ck,
1621 .clksel = dmt1_clk_mux_sel,
1622 .init = &omap2_init_clksel_parent,
1623 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1624 .clksel_mask = OMAP4430_CLKSEL_MASK,
1625 .ops = &clkops_omap2_dflt,
1626 .recalc = &omap2_clksel_recalc,
1627 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
1628 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1629 .clkdm_name = "l4_per_clkdm",
1630};
1631
1632static const struct clksel timer5_sync_mux_sel[] = {
1633 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
1634 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
1635 { .parent = NULL }, 1607 { .parent = NULL },
1636}; 1608};
1637 1609
1638/* 1610/* Merged sgx_clk_mux into gpu */
1639 * Merged timer5_sync_mux into gptimer5 1611static struct clk gpu_fck = {
1640 * gptimer5 renamed temporarily into gpt5 to match OMAP3 convention 1612 .name = "gpu_fck",
1641 */ 1613 .parent = &dpll_core_m7_ck,
1642static struct clk gpt5_fck = { 1614 .clksel = sgx_clk_mux_sel,
1643 .name = "gpt5_fck",
1644 .parent = &syc_clk_div_ck,
1645 .clksel = timer5_sync_mux_sel,
1646 .init = &omap2_init_clksel_parent,
1647 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1648 .clksel_mask = OMAP4430_CLKSEL_MASK,
1649 .ops = &clkops_omap2_dflt,
1650 .recalc = &omap2_clksel_recalc,
1651 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
1652 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1653 .clkdm_name = "abe_clkdm",
1654};
1655
1656/*
1657 * Merged timer6_sync_mux into gptimer6
1658 * gptimer6 renamed temporarily into gpt6 to match OMAP3 convention
1659 */
1660static struct clk gpt6_fck = {
1661 .name = "gpt6_fck",
1662 .parent = &syc_clk_div_ck,
1663 .clksel = timer5_sync_mux_sel,
1664 .init = &omap2_init_clksel_parent,
1665 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1666 .clksel_mask = OMAP4430_CLKSEL_MASK,
1667 .ops = &clkops_omap2_dflt,
1668 .recalc = &omap2_clksel_recalc,
1669 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
1670 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1671 .clkdm_name = "abe_clkdm",
1672};
1673
1674/*
1675 * Merged timer7_sync_mux into gptimer7
1676 * gptimer7 renamed temporarily into gpt7 to match OMAP3 convention
1677 */
1678static struct clk gpt7_fck = {
1679 .name = "gpt7_fck",
1680 .parent = &syc_clk_div_ck,
1681 .clksel = timer5_sync_mux_sel,
1682 .init = &omap2_init_clksel_parent,
1683 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1684 .clksel_mask = OMAP4430_CLKSEL_MASK,
1685 .ops = &clkops_omap2_dflt,
1686 .recalc = &omap2_clksel_recalc,
1687 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
1688 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1689 .clkdm_name = "abe_clkdm",
1690};
1691
1692/*
1693 * Merged timer8_sync_mux into gptimer8
1694 * gptimer8 renamed temporarily into gpt8 to match OMAP3 convention
1695 */
1696static struct clk gpt8_fck = {
1697 .name = "gpt8_fck",
1698 .parent = &syc_clk_div_ck,
1699 .clksel = timer5_sync_mux_sel,
1700 .init = &omap2_init_clksel_parent,
1701 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1702 .clksel_mask = OMAP4430_CLKSEL_MASK,
1703 .ops = &clkops_omap2_dflt,
1704 .recalc = &omap2_clksel_recalc,
1705 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
1706 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1707 .clkdm_name = "abe_clkdm",
1708};
1709
1710/*
1711 * Merged cm2_dm9_mux into gptimer9
1712 * gptimer9 renamed temporarily into gpt9 to match OMAP3 convention
1713 */
1714static struct clk gpt9_fck = {
1715 .name = "gpt9_fck",
1716 .parent = &sys_clkin_ck,
1717 .clksel = dmt1_clk_mux_sel,
1718 .init = &omap2_init_clksel_parent, 1615 .init = &omap2_init_clksel_parent,
1719 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1616 .clksel_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1720 .clksel_mask = OMAP4430_CLKSEL_MASK, 1617 .clksel_mask = OMAP4430_CLKSEL_SGX_FCLK_MASK,
1721 .ops = &clkops_omap2_dflt, 1618 .ops = &clkops_omap2_dflt,
1722 .recalc = &omap2_clksel_recalc, 1619 .recalc = &omap2_clksel_recalc,
1723 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL, 1620 .enable_reg = OMAP4430_CM_GFX_GFX_CLKCTRL,
1724 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1621 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1725 .clkdm_name = "l4_per_clkdm", 1622 .clkdm_name = "l3_gfx_clkdm",
1726}; 1623};
1727 1624
1728static struct clk hdq1w_fck = { 1625static struct clk hdq1w_fck = {
@@ -1735,11 +1632,16 @@ static struct clk hdq1w_fck = {
1735 .recalc = &followparent_recalc, 1632 .recalc = &followparent_recalc,
1736}; 1633};
1737 1634
1635static const struct clksel hsi_fclk_div[] = {
1636 { .parent = &dpll_per_m2x2_ck, .rates = div3_1to4_rates },
1637 { .parent = NULL },
1638};
1639
1738/* Merged hsi_fclk into hsi */ 1640/* Merged hsi_fclk into hsi */
1739static struct clk hsi_ick = { 1641static struct clk hsi_fck = {
1740 .name = "hsi_ick", 1642 .name = "hsi_fck",
1741 .parent = &dpll_per_m2x2_ck, 1643 .parent = &dpll_per_m2x2_ck,
1742 .clksel = per_sgx_fclk_div, 1644 .clksel = hsi_fclk_div,
1743 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL, 1645 .clksel_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
1744 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK, 1646 .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
1745 .ops = &clkops_omap2_dflt, 1647 .ops = &clkops_omap2_dflt,
@@ -1791,6 +1693,26 @@ static struct clk i2c4_fck = {
1791 .recalc = &followparent_recalc, 1693 .recalc = &followparent_recalc,
1792}; 1694};
1793 1695
1696static struct clk ipu_fck = {
1697 .name = "ipu_fck",
1698 .ops = &clkops_omap2_dflt,
1699 .enable_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
1700 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
1701 .clkdm_name = "ducati_clkdm",
1702 .parent = &ducati_clk_mux_ck,
1703 .recalc = &followparent_recalc,
1704};
1705
1706static struct clk iss_ctrlclk = {
1707 .name = "iss_ctrlclk",
1708 .ops = &clkops_omap2_dflt,
1709 .enable_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
1710 .enable_bit = OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT,
1711 .clkdm_name = "iss_clkdm",
1712 .parent = &func_96m_fclk,
1713 .recalc = &followparent_recalc,
1714};
1715
1794static struct clk iss_fck = { 1716static struct clk iss_fck = {
1795 .name = "iss_fck", 1717 .name = "iss_fck",
1796 .ops = &clkops_omap2_dflt, 1718 .ops = &clkops_omap2_dflt,
@@ -1801,8 +1723,8 @@ static struct clk iss_fck = {
1801 .recalc = &followparent_recalc, 1723 .recalc = &followparent_recalc,
1802}; 1724};
1803 1725
1804static struct clk ivahd_ick = { 1726static struct clk iva_fck = {
1805 .name = "ivahd_ick", 1727 .name = "iva_fck",
1806 .ops = &clkops_omap2_dflt, 1728 .ops = &clkops_omap2_dflt,
1807 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL, 1729 .enable_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
1808 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1730 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1811,8 +1733,8 @@ static struct clk ivahd_ick = {
1811 .recalc = &followparent_recalc, 1733 .recalc = &followparent_recalc,
1812}; 1734};
1813 1735
1814static struct clk keyboard_fck = { 1736static struct clk kbd_fck = {
1815 .name = "keyboard_fck", 1737 .name = "kbd_fck",
1816 .ops = &clkops_omap2_dflt, 1738 .ops = &clkops_omap2_dflt,
1817 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL, 1739 .enable_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
1818 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 1740 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -1821,8 +1743,8 @@ static struct clk keyboard_fck = {
1821 .recalc = &followparent_recalc, 1743 .recalc = &followparent_recalc,
1822}; 1744};
1823 1745
1824static struct clk l3_instr_interconnect_ick = { 1746static struct clk l3_instr_ick = {
1825 .name = "l3_instr_interconnect_ick", 1747 .name = "l3_instr_ick",
1826 .ops = &clkops_omap2_dflt, 1748 .ops = &clkops_omap2_dflt,
1827 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 1749 .enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
1828 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1750 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -1831,8 +1753,8 @@ static struct clk l3_instr_interconnect_ick = {
1831 .recalc = &followparent_recalc, 1753 .recalc = &followparent_recalc,
1832}; 1754};
1833 1755
1834static struct clk l3_interconnect_3_ick = { 1756static struct clk l3_main_3_ick = {
1835 .name = "l3_interconnect_3_ick", 1757 .name = "l3_main_3_ick",
1836 .ops = &clkops_omap2_dflt, 1758 .ops = &clkops_omap2_dflt,
1837 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 1759 .enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
1838 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 1760 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2005,6 +1927,16 @@ static struct clk mcbsp4_fck = {
2005 .clkdm_name = "l4_per_clkdm", 1927 .clkdm_name = "l4_per_clkdm",
2006}; 1928};
2007 1929
1930static struct clk mcpdm_fck = {
1931 .name = "mcpdm_fck",
1932 .ops = &clkops_omap2_dflt,
1933 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
1934 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
1935 .clkdm_name = "abe_clkdm",
1936 .parent = &pad_clks_ck,
1937 .recalc = &followparent_recalc,
1938};
1939
2008static struct clk mcspi1_fck = { 1940static struct clk mcspi1_fck = {
2009 .name = "mcspi1_fck", 1941 .name = "mcspi1_fck",
2010 .ops = &clkops_omap2_dflt, 1942 .ops = &clkops_omap2_dflt,
@@ -2105,33 +2037,33 @@ static struct clk mmc5_fck = {
2105 .recalc = &followparent_recalc, 2037 .recalc = &followparent_recalc,
2106}; 2038};
2107 2039
2108static struct clk ocp_wp1_ick = { 2040static struct clk ocp2scp_usb_phy_phy_48m = {
2109 .name = "ocp_wp1_ick", 2041 .name = "ocp2scp_usb_phy_phy_48m",
2110 .ops = &clkops_omap2_dflt, 2042 .ops = &clkops_omap2_dflt,
2111 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL, 2043 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2112 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2044 .enable_bit = OMAP4430_OPTFCLKEN_PHY_48M_SHIFT,
2113 .clkdm_name = "l3_instr_clkdm", 2045 .clkdm_name = "l3_init_clkdm",
2114 .parent = &l3_div_ck, 2046 .parent = &func_48m_fclk,
2115 .recalc = &followparent_recalc, 2047 .recalc = &followparent_recalc,
2116}; 2048};
2117 2049
2118static struct clk pdm_fck = { 2050static struct clk ocp2scp_usb_phy_ick = {
2119 .name = "pdm_fck", 2051 .name = "ocp2scp_usb_phy_ick",
2120 .ops = &clkops_omap2_dflt, 2052 .ops = &clkops_omap2_dflt,
2121 .enable_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL, 2053 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
2122 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2054 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2123 .clkdm_name = "abe_clkdm", 2055 .clkdm_name = "l3_init_clkdm",
2124 .parent = &pad_clks_ck, 2056 .parent = &l4_div_ck,
2125 .recalc = &followparent_recalc, 2057 .recalc = &followparent_recalc,
2126}; 2058};
2127 2059
2128static struct clk pkaeip29_fck = { 2060static struct clk ocp_wp_noc_ick = {
2129 .name = "pkaeip29_fck", 2061 .name = "ocp_wp_noc_ick",
2130 .ops = &clkops_omap2_dflt, 2062 .ops = &clkops_omap2_dflt,
2131 .enable_reg = OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL, 2063 .enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
2132 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2064 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2133 .clkdm_name = "l4_secure_clkdm", 2065 .clkdm_name = "l3_instr_clkdm",
2134 .parent = &l4_div_ck, 2066 .parent = &l3_div_ck,
2135 .recalc = &followparent_recalc, 2067 .recalc = &followparent_recalc,
2136}; 2068};
2137 2069
@@ -2145,8 +2077,8 @@ static struct clk rng_ick = {
2145 .recalc = &followparent_recalc, 2077 .recalc = &followparent_recalc,
2146}; 2078};
2147 2079
2148static struct clk sha2md51_fck = { 2080static struct clk sha2md5_fck = {
2149 .name = "sha2md51_fck", 2081 .name = "sha2md5_fck",
2150 .ops = &clkops_omap2_dflt, 2082 .ops = &clkops_omap2_dflt,
2151 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL, 2083 .enable_reg = OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL,
2152 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2084 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2155,8 +2087,8 @@ static struct clk sha2md51_fck = {
2155 .recalc = &followparent_recalc, 2087 .recalc = &followparent_recalc,
2156}; 2088};
2157 2089
2158static struct clk sl2_ick = { 2090static struct clk sl2if_ick = {
2159 .name = "sl2_ick", 2091 .name = "sl2if_ick",
2160 .ops = &clkops_omap2_dflt, 2092 .ops = &clkops_omap2_dflt,
2161 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL, 2093 .enable_reg = OMAP4430_CM_IVAHD_SL2_CLKCTRL,
2162 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2094 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
@@ -2165,6 +2097,46 @@ static struct clk sl2_ick = {
2165 .recalc = &followparent_recalc, 2097 .recalc = &followparent_recalc,
2166}; 2098};
2167 2099
2100static struct clk slimbus1_fclk_1 = {
2101 .name = "slimbus1_fclk_1",
2102 .ops = &clkops_omap2_dflt,
2103 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2104 .enable_bit = OMAP4430_OPTFCLKEN_FCLK1_SHIFT,
2105 .clkdm_name = "abe_clkdm",
2106 .parent = &func_24m_clk,
2107 .recalc = &followparent_recalc,
2108};
2109
2110static struct clk slimbus1_fclk_0 = {
2111 .name = "slimbus1_fclk_0",
2112 .ops = &clkops_omap2_dflt,
2113 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2114 .enable_bit = OMAP4430_OPTFCLKEN_FCLK0_SHIFT,
2115 .clkdm_name = "abe_clkdm",
2116 .parent = &abe_24m_fclk,
2117 .recalc = &followparent_recalc,
2118};
2119
2120static struct clk slimbus1_fclk_2 = {
2121 .name = "slimbus1_fclk_2",
2122 .ops = &clkops_omap2_dflt,
2123 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2124 .enable_bit = OMAP4430_OPTFCLKEN_FCLK2_SHIFT,
2125 .clkdm_name = "abe_clkdm",
2126 .parent = &pad_clks_ck,
2127 .recalc = &followparent_recalc,
2128};
2129
2130static struct clk slimbus1_slimbus_clk = {
2131 .name = "slimbus1_slimbus_clk",
2132 .ops = &clkops_omap2_dflt,
2133 .enable_reg = OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL,
2134 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT,
2135 .clkdm_name = "abe_clkdm",
2136 .parent = &slimbus_clk,
2137 .recalc = &followparent_recalc,
2138};
2139
2168static struct clk slimbus1_fck = { 2140static struct clk slimbus1_fck = {
2169 .name = "slimbus1_fck", 2141 .name = "slimbus1_fck",
2170 .ops = &clkops_omap2_dflt, 2142 .ops = &clkops_omap2_dflt,
@@ -2175,6 +2147,36 @@ static struct clk slimbus1_fck = {
2175 .recalc = &followparent_recalc, 2147 .recalc = &followparent_recalc,
2176}; 2148};
2177 2149
2150static struct clk slimbus2_fclk_1 = {
2151 .name = "slimbus2_fclk_1",
2152 .ops = &clkops_omap2_dflt,
2153 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2154 .enable_bit = OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT,
2155 .clkdm_name = "l4_per_clkdm",
2156 .parent = &per_abe_24m_fclk,
2157 .recalc = &followparent_recalc,
2158};
2159
2160static struct clk slimbus2_fclk_0 = {
2161 .name = "slimbus2_fclk_0",
2162 .ops = &clkops_omap2_dflt,
2163 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2164 .enable_bit = OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT,
2165 .clkdm_name = "l4_per_clkdm",
2166 .parent = &func_24mc_fclk,
2167 .recalc = &followparent_recalc,
2168};
2169
2170static struct clk slimbus2_slimbus_clk = {
2171 .name = "slimbus2_slimbus_clk",
2172 .ops = &clkops_omap2_dflt,
2173 .enable_reg = OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL,
2174 .enable_bit = OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT,
2175 .clkdm_name = "l4_per_clkdm",
2176 .parent = &pad_slimbus_core_clks_ck,
2177 .recalc = &followparent_recalc,
2178};
2179
2178static struct clk slimbus2_fck = { 2180static struct clk slimbus2_fck = {
2179 .name = "slimbus2_fck", 2181 .name = "slimbus2_fck",
2180 .ops = &clkops_omap2_dflt, 2182 .ops = &clkops_omap2_dflt,
@@ -2185,8 +2187,8 @@ static struct clk slimbus2_fck = {
2185 .recalc = &followparent_recalc, 2187 .recalc = &followparent_recalc,
2186}; 2188};
2187 2189
2188static struct clk sr_core_fck = { 2190static struct clk smartreflex_core_fck = {
2189 .name = "sr_core_fck", 2191 .name = "smartreflex_core_fck",
2190 .ops = &clkops_omap2_dflt, 2192 .ops = &clkops_omap2_dflt,
2191 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL, 2193 .enable_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
2192 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2194 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2195,8 +2197,8 @@ static struct clk sr_core_fck = {
2195 .recalc = &followparent_recalc, 2197 .recalc = &followparent_recalc,
2196}; 2198};
2197 2199
2198static struct clk sr_iva_fck = { 2200static struct clk smartreflex_iva_fck = {
2199 .name = "sr_iva_fck", 2201 .name = "smartreflex_iva_fck",
2200 .ops = &clkops_omap2_dflt, 2202 .ops = &clkops_omap2_dflt,
2201 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL, 2203 .enable_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
2202 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2204 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2205,8 +2207,8 @@ static struct clk sr_iva_fck = {
2205 .recalc = &followparent_recalc, 2207 .recalc = &followparent_recalc,
2206}; 2208};
2207 2209
2208static struct clk sr_mpu_fck = { 2210static struct clk smartreflex_mpu_fck = {
2209 .name = "sr_mpu_fck", 2211 .name = "smartreflex_mpu_fck",
2210 .ops = &clkops_omap2_dflt, 2212 .ops = &clkops_omap2_dflt,
2211 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL, 2213 .enable_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
2212 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2214 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
@@ -2215,14 +2217,175 @@ static struct clk sr_mpu_fck = {
2215 .recalc = &followparent_recalc, 2217 .recalc = &followparent_recalc,
2216}; 2218};
2217 2219
2218static struct clk tesla_ick = { 2220/* Merged dmt1_clk_mux into timer1 */
2219 .name = "tesla_ick", 2221static struct clk timer1_fck = {
2222 .name = "timer1_fck",
2223 .parent = &sys_clkin_ck,
2224 .clksel = abe_dpll_bypass_clk_mux_sel,
2225 .init = &omap2_init_clksel_parent,
2226 .clksel_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2227 .clksel_mask = OMAP4430_CLKSEL_MASK,
2220 .ops = &clkops_omap2_dflt, 2228 .ops = &clkops_omap2_dflt,
2221 .enable_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL, 2229 .recalc = &omap2_clksel_recalc,
2222 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2230 .enable_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
2223 .clkdm_name = "tesla_clkdm", 2231 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2224 .parent = &dpll_iva_m4_ck, 2232 .clkdm_name = "l4_wkup_clkdm",
2225 .recalc = &followparent_recalc, 2233};
2234
2235/* Merged cm2_dm10_mux into timer10 */
2236static struct clk timer10_fck = {
2237 .name = "timer10_fck",
2238 .parent = &sys_clkin_ck,
2239 .clksel = abe_dpll_bypass_clk_mux_sel,
2240 .init = &omap2_init_clksel_parent,
2241 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2242 .clksel_mask = OMAP4430_CLKSEL_MASK,
2243 .ops = &clkops_omap2_dflt,
2244 .recalc = &omap2_clksel_recalc,
2245 .enable_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
2246 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2247 .clkdm_name = "l4_per_clkdm",
2248};
2249
2250/* Merged cm2_dm11_mux into timer11 */
2251static struct clk timer11_fck = {
2252 .name = "timer11_fck",
2253 .parent = &sys_clkin_ck,
2254 .clksel = abe_dpll_bypass_clk_mux_sel,
2255 .init = &omap2_init_clksel_parent,
2256 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2257 .clksel_mask = OMAP4430_CLKSEL_MASK,
2258 .ops = &clkops_omap2_dflt,
2259 .recalc = &omap2_clksel_recalc,
2260 .enable_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
2261 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2262 .clkdm_name = "l4_per_clkdm",
2263};
2264
2265/* Merged cm2_dm2_mux into timer2 */
2266static struct clk timer2_fck = {
2267 .name = "timer2_fck",
2268 .parent = &sys_clkin_ck,
2269 .clksel = abe_dpll_bypass_clk_mux_sel,
2270 .init = &omap2_init_clksel_parent,
2271 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2272 .clksel_mask = OMAP4430_CLKSEL_MASK,
2273 .ops = &clkops_omap2_dflt,
2274 .recalc = &omap2_clksel_recalc,
2275 .enable_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
2276 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2277 .clkdm_name = "l4_per_clkdm",
2278};
2279
2280/* Merged cm2_dm3_mux into timer3 */
2281static struct clk timer3_fck = {
2282 .name = "timer3_fck",
2283 .parent = &sys_clkin_ck,
2284 .clksel = abe_dpll_bypass_clk_mux_sel,
2285 .init = &omap2_init_clksel_parent,
2286 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2287 .clksel_mask = OMAP4430_CLKSEL_MASK,
2288 .ops = &clkops_omap2_dflt,
2289 .recalc = &omap2_clksel_recalc,
2290 .enable_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
2291 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2292 .clkdm_name = "l4_per_clkdm",
2293};
2294
2295/* Merged cm2_dm4_mux into timer4 */
2296static struct clk timer4_fck = {
2297 .name = "timer4_fck",
2298 .parent = &sys_clkin_ck,
2299 .clksel = abe_dpll_bypass_clk_mux_sel,
2300 .init = &omap2_init_clksel_parent,
2301 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2302 .clksel_mask = OMAP4430_CLKSEL_MASK,
2303 .ops = &clkops_omap2_dflt,
2304 .recalc = &omap2_clksel_recalc,
2305 .enable_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
2306 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2307 .clkdm_name = "l4_per_clkdm",
2308};
2309
2310static const struct clksel timer5_sync_mux_sel[] = {
2311 { .parent = &syc_clk_div_ck, .rates = div_1_0_rates },
2312 { .parent = &sys_32k_ck, .rates = div_1_1_rates },
2313 { .parent = NULL },
2314};
2315
2316/* Merged timer5_sync_mux into timer5 */
2317static struct clk timer5_fck = {
2318 .name = "timer5_fck",
2319 .parent = &syc_clk_div_ck,
2320 .clksel = timer5_sync_mux_sel,
2321 .init = &omap2_init_clksel_parent,
2322 .clksel_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2323 .clksel_mask = OMAP4430_CLKSEL_MASK,
2324 .ops = &clkops_omap2_dflt,
2325 .recalc = &omap2_clksel_recalc,
2326 .enable_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
2327 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2328 .clkdm_name = "abe_clkdm",
2329};
2330
2331/* Merged timer6_sync_mux into timer6 */
2332static struct clk timer6_fck = {
2333 .name = "timer6_fck",
2334 .parent = &syc_clk_div_ck,
2335 .clksel = timer5_sync_mux_sel,
2336 .init = &omap2_init_clksel_parent,
2337 .clksel_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2338 .clksel_mask = OMAP4430_CLKSEL_MASK,
2339 .ops = &clkops_omap2_dflt,
2340 .recalc = &omap2_clksel_recalc,
2341 .enable_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2343 .clkdm_name = "abe_clkdm",
2344};
2345
2346/* Merged timer7_sync_mux into timer7 */
2347static struct clk timer7_fck = {
2348 .name = "timer7_fck",
2349 .parent = &syc_clk_div_ck,
2350 .clksel = timer5_sync_mux_sel,
2351 .init = &omap2_init_clksel_parent,
2352 .clksel_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2353 .clksel_mask = OMAP4430_CLKSEL_MASK,
2354 .ops = &clkops_omap2_dflt,
2355 .recalc = &omap2_clksel_recalc,
2356 .enable_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
2357 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2358 .clkdm_name = "abe_clkdm",
2359};
2360
2361/* Merged timer8_sync_mux into timer8 */
2362static struct clk timer8_fck = {
2363 .name = "timer8_fck",
2364 .parent = &syc_clk_div_ck,
2365 .clksel = timer5_sync_mux_sel,
2366 .init = &omap2_init_clksel_parent,
2367 .clksel_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2368 .clksel_mask = OMAP4430_CLKSEL_MASK,
2369 .ops = &clkops_omap2_dflt,
2370 .recalc = &omap2_clksel_recalc,
2371 .enable_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
2372 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2373 .clkdm_name = "abe_clkdm",
2374};
2375
2376/* Merged cm2_dm9_mux into timer9 */
2377static struct clk timer9_fck = {
2378 .name = "timer9_fck",
2379 .parent = &sys_clkin_ck,
2380 .clksel = abe_dpll_bypass_clk_mux_sel,
2381 .init = &omap2_init_clksel_parent,
2382 .clksel_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2383 .clksel_mask = OMAP4430_CLKSEL_MASK,
2384 .ops = &clkops_omap2_dflt,
2385 .recalc = &omap2_clksel_recalc,
2386 .enable_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
2387 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2388 .clkdm_name = "l4_per_clkdm",
2226}; 2389};
2227 2390
2228static struct clk uart1_fck = { 2391static struct clk uart1_fck = {
@@ -2265,105 +2428,148 @@ static struct clk uart4_fck = {
2265 .recalc = &followparent_recalc, 2428 .recalc = &followparent_recalc,
2266}; 2429};
2267 2430
2268static struct clk unipro1_fck = { 2431static struct clk usb_host_fs_fck = {
2269 .name = "unipro1_fck", 2432 .name = "usb_host_fs_fck",
2270 .ops = &clkops_omap2_dflt, 2433 .ops = &clkops_omap2_dflt,
2271 .enable_reg = OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL, 2434 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL,
2272 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2435 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2273 .clkdm_name = "l3_init_clkdm", 2436 .clkdm_name = "l3_init_clkdm",
2274 .parent = &func_96m_fclk, 2437 .parent = &func_48mc_fclk,
2275 .recalc = &followparent_recalc, 2438 .recalc = &followparent_recalc,
2276}; 2439};
2277 2440
2278static struct clk usb_host_fck = { 2441static struct clk usb_host_hs_utmi_p3_clk = {
2279 .name = "usb_host_fck", 2442 .name = "usb_host_hs_utmi_p3_clk",
2280 .ops = &clkops_omap2_dflt, 2443 .ops = &clkops_omap2_dflt,
2281 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2444 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2282 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2445 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT,
2283 .clkdm_name = "l3_init_clkdm", 2446 .clkdm_name = "l3_init_clkdm",
2284 .parent = &init_60m_fclk, 2447 .parent = &init_60m_fclk,
2285 .recalc = &followparent_recalc, 2448 .recalc = &followparent_recalc,
2286}; 2449};
2287 2450
2288static struct clk usb_host_fs_fck = { 2451static struct clk usb_host_hs_hsic60m_p1_clk = {
2289 .name = "usb_host_fs_fck", 2452 .name = "usb_host_hs_hsic60m_p1_clk",
2290 .ops = &clkops_omap2_dflt, 2453 .ops = &clkops_omap2_dflt,
2291 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL, 2454 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2292 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2455 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT,
2293 .clkdm_name = "l3_init_clkdm", 2456 .clkdm_name = "l3_init_clkdm",
2294 .parent = &func_48mc_fclk, 2457 .parent = &init_60m_fclk,
2295 .recalc = &followparent_recalc, 2458 .recalc = &followparent_recalc,
2296}; 2459};
2297 2460
2298static struct clk usb_otg_ick = { 2461static struct clk usb_host_hs_hsic60m_p2_clk = {
2299 .name = "usb_otg_ick", 2462 .name = "usb_host_hs_hsic60m_p2_clk",
2300 .ops = &clkops_omap2_dflt, 2463 .ops = &clkops_omap2_dflt,
2301 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL, 2464 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2302 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2465 .enable_bit = OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT,
2303 .clkdm_name = "l3_init_clkdm", 2466 .clkdm_name = "l3_init_clkdm",
2304 .parent = &l3_div_ck, 2467 .parent = &init_60m_fclk,
2305 .recalc = &followparent_recalc, 2468 .recalc = &followparent_recalc,
2306}; 2469};
2307 2470
2308static struct clk usb_tll_ick = { 2471static const struct clksel utmi_p1_gfclk_sel[] = {
2309 .name = "usb_tll_ick", 2472 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2473 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates },
2474 { .parent = NULL },
2475};
2476
2477static struct clk utmi_p1_gfclk = {
2478 .name = "utmi_p1_gfclk",
2479 .parent = &init_60m_fclk,
2480 .clksel = utmi_p1_gfclk_sel,
2481 .init = &omap2_init_clksel_parent,
2482 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2483 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2484 .ops = &clkops_null,
2485 .recalc = &omap2_clksel_recalc,
2486};
2487
2488static struct clk usb_host_hs_utmi_p1_clk = {
2489 .name = "usb_host_hs_utmi_p1_clk",
2310 .ops = &clkops_omap2_dflt, 2490 .ops = &clkops_omap2_dflt,
2311 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL, 2491 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2312 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2492 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT,
2313 .clkdm_name = "l3_init_clkdm", 2493 .clkdm_name = "l3_init_clkdm",
2314 .parent = &l4_div_ck, 2494 .parent = &utmi_p1_gfclk,
2315 .recalc = &followparent_recalc, 2495 .recalc = &followparent_recalc,
2316}; 2496};
2317 2497
2318static struct clk usbphyocp2scp_ick = { 2498static const struct clksel utmi_p2_gfclk_sel[] = {
2319 .name = "usbphyocp2scp_ick", 2499 { .parent = &init_60m_fclk, .rates = div_1_0_rates },
2500 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2501 { .parent = NULL },
2502};
2503
2504static struct clk utmi_p2_gfclk = {
2505 .name = "utmi_p2_gfclk",
2506 .parent = &init_60m_fclk,
2507 .clksel = utmi_p2_gfclk_sel,
2508 .init = &omap2_init_clksel_parent,
2509 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2510 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2511 .ops = &clkops_null,
2512 .recalc = &omap2_clksel_recalc,
2513};
2514
2515static struct clk usb_host_hs_utmi_p2_clk = {
2516 .name = "usb_host_hs_utmi_p2_clk",
2320 .ops = &clkops_omap2_dflt, 2517 .ops = &clkops_omap2_dflt,
2321 .enable_reg = OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, 2518 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2322 .enable_bit = OMAP4430_MODULEMODE_HWCTRL, 2519 .enable_bit = OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT,
2323 .clkdm_name = "l3_init_clkdm", 2520 .clkdm_name = "l3_init_clkdm",
2324 .parent = &l4_div_ck, 2521 .parent = &utmi_p2_gfclk,
2325 .recalc = &followparent_recalc, 2522 .recalc = &followparent_recalc,
2326}; 2523};
2327 2524
2328static struct clk usim_fck = { 2525static struct clk usb_host_hs_hsic480m_p1_clk = {
2329 .name = "usim_fck", 2526 .name = "usb_host_hs_hsic480m_p1_clk",
2330 .ops = &clkops_omap2_dflt, 2527 .ops = &clkops_omap2_dflt,
2331 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2528 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2332 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2529 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT,
2333 .clkdm_name = "l4_wkup_clkdm", 2530 .clkdm_name = "l3_init_clkdm",
2334 .parent = &sys_32k_ck, 2531 .parent = &dpll_usb_m2_ck,
2335 .recalc = &followparent_recalc, 2532 .recalc = &followparent_recalc,
2336}; 2533};
2337 2534
2338static struct clk wdt2_fck = { 2535static struct clk usb_host_hs_hsic480m_p2_clk = {
2339 .name = "wdt2_fck", 2536 .name = "usb_host_hs_hsic480m_p2_clk",
2340 .ops = &clkops_omap2_dflt, 2537 .ops = &clkops_omap2_dflt,
2341 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL, 2538 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2342 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2539 .enable_bit = OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT,
2343 .clkdm_name = "l4_wkup_clkdm", 2540 .clkdm_name = "l3_init_clkdm",
2344 .parent = &sys_32k_ck, 2541 .parent = &dpll_usb_m2_ck,
2345 .recalc = &followparent_recalc, 2542 .recalc = &followparent_recalc,
2346}; 2543};
2347 2544
2348static struct clk wdt3_fck = { 2545static struct clk usb_host_hs_func48mclk = {
2349 .name = "wdt3_fck", 2546 .name = "usb_host_hs_func48mclk",
2350 .ops = &clkops_omap2_dflt, 2547 .ops = &clkops_omap2_dflt,
2351 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL, 2548 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2549 .enable_bit = OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT,
2550 .clkdm_name = "l3_init_clkdm",
2551 .parent = &func_48mc_fclk,
2552 .recalc = &followparent_recalc,
2553};
2554
2555static struct clk usb_host_hs_fck = {
2556 .name = "usb_host_hs_fck",
2557 .ops = &clkops_omap2_dflt,
2558 .enable_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL,
2352 .enable_bit = OMAP4430_MODULEMODE_SWCTRL, 2559 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2353 .clkdm_name = "abe_clkdm", 2560 .clkdm_name = "l3_init_clkdm",
2354 .parent = &sys_32k_ck, 2561 .parent = &init_60m_fclk,
2355 .recalc = &followparent_recalc, 2562 .recalc = &followparent_recalc,
2356}; 2563};
2357 2564
2358/* Remaining optional clocks */
2359static const struct clksel otg_60m_gfclk_sel[] = { 2565static const struct clksel otg_60m_gfclk_sel[] = {
2360 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates }, 2566 { .parent = &utmi_phy_clkout_ck, .rates = div_1_0_rates },
2361 { .parent = &xclk60motg_ck, .rates = div_1_1_rates }, 2567 { .parent = &xclk60motg_ck, .rates = div_1_1_rates },
2362 { .parent = NULL }, 2568 { .parent = NULL },
2363}; 2569};
2364 2570
2365static struct clk otg_60m_gfclk_ck = { 2571static struct clk otg_60m_gfclk = {
2366 .name = "otg_60m_gfclk_ck", 2572 .name = "otg_60m_gfclk",
2367 .parent = &utmi_phy_clkout_ck, 2573 .parent = &utmi_phy_clkout_ck,
2368 .clksel = otg_60m_gfclk_sel, 2574 .clksel = otg_60m_gfclk_sel,
2369 .init = &omap2_init_clksel_parent, 2575 .init = &omap2_init_clksel_parent,
@@ -2373,38 +2579,74 @@ static struct clk otg_60m_gfclk_ck = {
2373 .recalc = &omap2_clksel_recalc, 2579 .recalc = &omap2_clksel_recalc,
2374}; 2580};
2375 2581
2376static const struct clksel stm_clk_div_div[] = { 2582static struct clk usb_otg_hs_xclk = {
2377 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates }, 2583 .name = "usb_otg_hs_xclk",
2378 { .parent = NULL }, 2584 .ops = &clkops_omap2_dflt,
2585 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2586 .enable_bit = OMAP4430_OPTFCLKEN_XCLK_SHIFT,
2587 .clkdm_name = "l3_init_clkdm",
2588 .parent = &otg_60m_gfclk,
2589 .recalc = &followparent_recalc,
2379}; 2590};
2380 2591
2381static struct clk stm_clk_div_ck = { 2592static struct clk usb_otg_hs_ick = {
2382 .name = "stm_clk_div_ck", 2593 .name = "usb_otg_hs_ick",
2383 .parent = &pmd_stm_clock_mux_ck, 2594 .ops = &clkops_omap2_dflt,
2384 .clksel = stm_clk_div_div, 2595 .enable_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
2385 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2596 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2386 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK, 2597 .clkdm_name = "l3_init_clkdm",
2387 .ops = &clkops_null, 2598 .parent = &l3_div_ck,
2388 .recalc = &omap2_clksel_recalc, 2599 .recalc = &followparent_recalc,
2389 .round_rate = &omap2_clksel_round_rate,
2390 .set_rate = &omap2_clksel_set_rate,
2391}; 2600};
2392 2601
2393static const struct clksel trace_clk_div_div[] = { 2602static struct clk usb_phy_cm_clk32k = {
2394 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates }, 2603 .name = "usb_phy_cm_clk32k",
2395 { .parent = NULL }, 2604 .ops = &clkops_omap2_dflt,
2605 .enable_reg = OMAP4430_CM_ALWON_USBPHY_CLKCTRL,
2606 .enable_bit = OMAP4430_OPTFCLKEN_CLK32K_SHIFT,
2607 .clkdm_name = "l4_ao_clkdm",
2608 .parent = &sys_32k_ck,
2609 .recalc = &followparent_recalc,
2396}; 2610};
2397 2611
2398static struct clk trace_clk_div_ck = { 2612static struct clk usb_tll_hs_usb_ch2_clk = {
2399 .name = "trace_clk_div_ck", 2613 .name = "usb_tll_hs_usb_ch2_clk",
2400 .parent = &pmd_trace_clk_mux_ck, 2614 .ops = &clkops_omap2_dflt,
2401 .clksel = trace_clk_div_div, 2615 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2402 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL, 2616 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT,
2403 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK, 2617 .clkdm_name = "l3_init_clkdm",
2404 .ops = &clkops_null, 2618 .parent = &init_60m_fclk,
2405 .recalc = &omap2_clksel_recalc, 2619 .recalc = &followparent_recalc,
2406 .round_rate = &omap2_clksel_round_rate, 2620};
2407 .set_rate = &omap2_clksel_set_rate, 2621
2622static struct clk usb_tll_hs_usb_ch0_clk = {
2623 .name = "usb_tll_hs_usb_ch0_clk",
2624 .ops = &clkops_omap2_dflt,
2625 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2626 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT,
2627 .clkdm_name = "l3_init_clkdm",
2628 .parent = &init_60m_fclk,
2629 .recalc = &followparent_recalc,
2630};
2631
2632static struct clk usb_tll_hs_usb_ch1_clk = {
2633 .name = "usb_tll_hs_usb_ch1_clk",
2634 .ops = &clkops_omap2_dflt,
2635 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2636 .enable_bit = OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT,
2637 .clkdm_name = "l3_init_clkdm",
2638 .parent = &init_60m_fclk,
2639 .recalc = &followparent_recalc,
2640};
2641
2642static struct clk usb_tll_hs_ick = {
2643 .name = "usb_tll_hs_ick",
2644 .ops = &clkops_omap2_dflt,
2645 .enable_reg = OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL,
2646 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2647 .clkdm_name = "l3_init_clkdm",
2648 .parent = &l4_div_ck,
2649 .recalc = &followparent_recalc,
2408}; 2650};
2409 2651
2410static const struct clksel_rate div2_14to18_rates[] = { 2652static const struct clksel_rate div2_14to18_rates[] = {
@@ -2418,8 +2660,8 @@ static const struct clksel usim_fclk_div[] = {
2418 { .parent = NULL }, 2660 { .parent = NULL },
2419}; 2661};
2420 2662
2421static struct clk usim_fclk = { 2663static struct clk usim_ck = {
2422 .name = "usim_fclk", 2664 .name = "usim_ck",
2423 .parent = &dpll_per_m4_ck, 2665 .parent = &dpll_per_m4_ck,
2424 .clksel = usim_fclk_div, 2666 .clksel = usim_fclk_div,
2425 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL, 2667 .clksel_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
@@ -2430,38 +2672,79 @@ static struct clk usim_fclk = {
2430 .set_rate = &omap2_clksel_set_rate, 2672 .set_rate = &omap2_clksel_set_rate,
2431}; 2673};
2432 2674
2433static const struct clksel utmi_p1_gfclk_sel[] = { 2675static struct clk usim_fclk = {
2434 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2676 .name = "usim_fclk",
2435 { .parent = &xclk60mhsp1_ck, .rates = div_1_1_rates }, 2677 .ops = &clkops_omap2_dflt,
2678 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2679 .enable_bit = OMAP4430_OPTFCLKEN_FCLK_SHIFT,
2680 .clkdm_name = "l4_wkup_clkdm",
2681 .parent = &usim_ck,
2682 .recalc = &followparent_recalc,
2683};
2684
2685static struct clk usim_fck = {
2686 .name = "usim_fck",
2687 .ops = &clkops_omap2_dflt,
2688 .enable_reg = OMAP4430_CM_WKUP_USIM_CLKCTRL,
2689 .enable_bit = OMAP4430_MODULEMODE_HWCTRL,
2690 .clkdm_name = "l4_wkup_clkdm",
2691 .parent = &sys_32k_ck,
2692 .recalc = &followparent_recalc,
2693};
2694
2695static struct clk wd_timer2_fck = {
2696 .name = "wd_timer2_fck",
2697 .ops = &clkops_omap2_dflt,
2698 .enable_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
2699 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2700 .clkdm_name = "l4_wkup_clkdm",
2701 .parent = &sys_32k_ck,
2702 .recalc = &followparent_recalc,
2703};
2704
2705static struct clk wd_timer3_fck = {
2706 .name = "wd_timer3_fck",
2707 .ops = &clkops_omap2_dflt,
2708 .enable_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
2709 .enable_bit = OMAP4430_MODULEMODE_SWCTRL,
2710 .clkdm_name = "abe_clkdm",
2711 .parent = &sys_32k_ck,
2712 .recalc = &followparent_recalc,
2713};
2714
2715/* Remaining optional clocks */
2716static const struct clksel stm_clk_div_div[] = {
2717 { .parent = &pmd_stm_clock_mux_ck, .rates = div3_1to4_rates },
2436 { .parent = NULL }, 2718 { .parent = NULL },
2437}; 2719};
2438 2720
2439static struct clk utmi_p1_gfclk_ck = { 2721static struct clk stm_clk_div_ck = {
2440 .name = "utmi_p1_gfclk_ck", 2722 .name = "stm_clk_div_ck",
2441 .parent = &init_60m_fclk, 2723 .parent = &pmd_stm_clock_mux_ck,
2442 .clksel = utmi_p1_gfclk_sel, 2724 .clksel = stm_clk_div_div,
2443 .init = &omap2_init_clksel_parent, 2725 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2444 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2726 .clksel_mask = OMAP4430_CLKSEL_PMD_STM_CLK_MASK,
2445 .clksel_mask = OMAP4430_CLKSEL_UTMI_P1_MASK,
2446 .ops = &clkops_null, 2727 .ops = &clkops_null,
2447 .recalc = &omap2_clksel_recalc, 2728 .recalc = &omap2_clksel_recalc,
2729 .round_rate = &omap2_clksel_round_rate,
2730 .set_rate = &omap2_clksel_set_rate,
2448}; 2731};
2449 2732
2450static const struct clksel utmi_p2_gfclk_sel[] = { 2733static const struct clksel trace_clk_div_div[] = {
2451 { .parent = &init_60m_fclk, .rates = div_1_0_rates }, 2734 { .parent = &pmd_trace_clk_mux_ck, .rates = div3_1to4_rates },
2452 { .parent = &xclk60mhsp2_ck, .rates = div_1_1_rates },
2453 { .parent = NULL }, 2735 { .parent = NULL },
2454}; 2736};
2455 2737
2456static struct clk utmi_p2_gfclk_ck = { 2738static struct clk trace_clk_div_ck = {
2457 .name = "utmi_p2_gfclk_ck", 2739 .name = "trace_clk_div_ck",
2458 .parent = &init_60m_fclk, 2740 .parent = &pmd_trace_clk_mux_ck,
2459 .clksel = utmi_p2_gfclk_sel, 2741 .clksel = trace_clk_div_div,
2460 .init = &omap2_init_clksel_parent, 2742 .clksel_reg = OMAP4430_CM_EMU_DEBUGSS_CLKCTRL,
2461 .clksel_reg = OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL, 2743 .clksel_mask = OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK,
2462 .clksel_mask = OMAP4430_CLKSEL_UTMI_P2_MASK,
2463 .ops = &clkops_null, 2744 .ops = &clkops_null,
2464 .recalc = &omap2_clksel_recalc, 2745 .recalc = &omap2_clksel_recalc,
2746 .round_rate = &omap2_clksel_round_rate,
2747 .set_rate = &omap2_clksel_set_rate,
2465}; 2748};
2466 2749
2467/* 2750/*
@@ -2483,11 +2766,12 @@ static struct omap_clk omap44xx_clks[] = {
2483 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X), 2766 CLK(NULL, "virt_27000000_ck", &virt_27000000_ck, CK_443X),
2484 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X), 2767 CLK(NULL, "virt_38400000_ck", &virt_38400000_ck, CK_443X),
2485 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X), 2768 CLK(NULL, "sys_clkin_ck", &sys_clkin_ck, CK_443X),
2769 CLK(NULL, "tie_low_clock_ck", &tie_low_clock_ck, CK_443X),
2486 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X), 2770 CLK(NULL, "utmi_phy_clkout_ck", &utmi_phy_clkout_ck, CK_443X),
2487 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X), 2771 CLK(NULL, "xclk60mhsp1_ck", &xclk60mhsp1_ck, CK_443X),
2488 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X), 2772 CLK(NULL, "xclk60mhsp2_ck", &xclk60mhsp2_ck, CK_443X),
2489 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X), 2773 CLK(NULL, "xclk60motg_ck", &xclk60motg_ck, CK_443X),
2490 CLK(NULL, "dpll_sys_ref_clk", &dpll_sys_ref_clk, CK_443X), 2774 CLK(NULL, "abe_dpll_bypass_clk_mux_ck", &abe_dpll_bypass_clk_mux_ck, CK_443X),
2491 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X), 2775 CLK(NULL, "abe_dpll_refclk_mux_ck", &abe_dpll_refclk_mux_ck, CK_443X),
2492 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X), 2776 CLK(NULL, "dpll_abe_ck", &dpll_abe_ck, CK_443X),
2493 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X), 2777 CLK(NULL, "dpll_abe_m2x2_ck", &dpll_abe_m2x2_ck, CK_443X),
@@ -2557,46 +2841,48 @@ static struct omap_clk omap44xx_clks[] = {
2557 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X), 2841 CLK(NULL, "aes1_fck", &aes1_fck, CK_443X),
2558 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X), 2842 CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
2559 CLK(NULL, "aess_fck", &aess_fck, CK_443X), 2843 CLK(NULL, "aess_fck", &aess_fck, CK_443X),
2560 CLK(NULL, "cust_efuse_fck", &cust_efuse_fck, CK_443X), 2844 CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
2561 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X), 2845 CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
2562 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X), 2846 CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
2563 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X), 2847 CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
2848 CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
2849 CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
2850 CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
2851 CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
2852 CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
2564 CLK(NULL, "dss_fck", &dss_fck, CK_443X), 2853 CLK(NULL, "dss_fck", &dss_fck, CK_443X),
2565 CLK(NULL, "ducati_ick", &ducati_ick, CK_443X), 2854 CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
2566 CLK(NULL, "emif1_ick", &emif1_ick, CK_443X), 2855 CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
2567 CLK(NULL, "emif2_ick", &emif2_ick, CK_443X), 2856 CLK(NULL, "emif2_fck", &emif2_fck, CK_443X),
2568 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X), 2857 CLK(NULL, "fdif_fck", &fdif_fck, CK_443X),
2569 CLK(NULL, "per_sgx_fclk", &per_sgx_fclk, CK_443X), 2858 CLK(NULL, "fpka_fck", &fpka_fck, CK_443X),
2570 CLK(NULL, "gfx_fck", &gfx_fck, CK_443X), 2859 CLK(NULL, "gpio1_dbck", &gpio1_dbclk, CK_443X),
2571 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X), 2860 CLK(NULL, "gpio1_ick", &gpio1_ick, CK_443X),
2861 CLK(NULL, "gpio2_dbck", &gpio2_dbclk, CK_443X),
2572 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X), 2862 CLK(NULL, "gpio2_ick", &gpio2_ick, CK_443X),
2863 CLK(NULL, "gpio3_dbck", &gpio3_dbclk, CK_443X),
2573 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X), 2864 CLK(NULL, "gpio3_ick", &gpio3_ick, CK_443X),
2865 CLK(NULL, "gpio4_dbck", &gpio4_dbclk, CK_443X),
2574 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X), 2866 CLK(NULL, "gpio4_ick", &gpio4_ick, CK_443X),
2867 CLK(NULL, "gpio5_dbck", &gpio5_dbclk, CK_443X),
2575 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X), 2868 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_443X),
2869 CLK(NULL, "gpio6_dbck", &gpio6_dbclk, CK_443X),
2576 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X), 2870 CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
2577 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X), 2871 CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
2578 CLK(NULL, "gpt1_fck", &gpt1_fck, CK_443X), 2872 CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
2579 CLK(NULL, "gpt10_fck", &gpt10_fck, CK_443X),
2580 CLK(NULL, "gpt11_fck", &gpt11_fck, CK_443X),
2581 CLK(NULL, "gpt2_fck", &gpt2_fck, CK_443X),
2582 CLK(NULL, "gpt3_fck", &gpt3_fck, CK_443X),
2583 CLK(NULL, "gpt4_fck", &gpt4_fck, CK_443X),
2584 CLK(NULL, "gpt5_fck", &gpt5_fck, CK_443X),
2585 CLK(NULL, "gpt6_fck", &gpt6_fck, CK_443X),
2586 CLK(NULL, "gpt7_fck", &gpt7_fck, CK_443X),
2587 CLK(NULL, "gpt8_fck", &gpt8_fck, CK_443X),
2588 CLK(NULL, "gpt9_fck", &gpt9_fck, CK_443X),
2589 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X), 2873 CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
2590 CLK(NULL, "hsi_ick", &hsi_ick, CK_443X), 2874 CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
2591 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X), 2875 CLK("i2c_omap.1", "fck", &i2c1_fck, CK_443X),
2592 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X), 2876 CLK("i2c_omap.2", "fck", &i2c2_fck, CK_443X),
2593 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X), 2877 CLK("i2c_omap.3", "fck", &i2c3_fck, CK_443X),
2594 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X), 2878 CLK("i2c_omap.4", "fck", &i2c4_fck, CK_443X),
2879 CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
2880 CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
2595 CLK(NULL, "iss_fck", &iss_fck, CK_443X), 2881 CLK(NULL, "iss_fck", &iss_fck, CK_443X),
2596 CLK(NULL, "ivahd_ick", &ivahd_ick, CK_443X), 2882 CLK(NULL, "iva_fck", &iva_fck, CK_443X),
2597 CLK(NULL, "keyboard_fck", &keyboard_fck, CK_443X), 2883 CLK(NULL, "kbd_fck", &kbd_fck, CK_443X),
2598 CLK(NULL, "l3_instr_interconnect_ick", &l3_instr_interconnect_ick, CK_443X), 2884 CLK(NULL, "l3_instr_ick", &l3_instr_ick, CK_443X),
2599 CLK(NULL, "l3_interconnect_3_ick", &l3_interconnect_3_ick, CK_443X), 2885 CLK(NULL, "l3_main_3_ick", &l3_main_3_ick, CK_443X),
2600 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X), 2886 CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
2601 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X), 2887 CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
2602 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X), 2888 CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
@@ -2607,6 +2893,7 @@ static struct omap_clk omap44xx_clks[] = {
2607 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X), 2893 CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
2608 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X), 2894 CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
2609 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X), 2895 CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
2896 CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
2610 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X), 2897 CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
2611 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 2898 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
2612 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 2899 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
@@ -2616,43 +2903,66 @@ static struct omap_clk omap44xx_clks[] = {
2616 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 2903 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X),
2617 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 2904 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X),
2618 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 2905 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X),
2619 CLK(NULL, "ocp_wp1_ick", &ocp_wp1_ick, CK_443X), 2906 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
2620 CLK(NULL, "pdm_fck", &pdm_fck, CK_443X), 2907 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
2621 CLK(NULL, "pkaeip29_fck", &pkaeip29_fck, CK_443X), 2908 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
2622 CLK("omap_rng", "ick", &rng_ick, CK_443X), 2909 CLK("omap_rng", "ick", &rng_ick, CK_443X),
2623 CLK(NULL, "sha2md51_fck", &sha2md51_fck, CK_443X), 2910 CLK(NULL, "sha2md5_fck", &sha2md5_fck, CK_443X),
2624 CLK(NULL, "sl2_ick", &sl2_ick, CK_443X), 2911 CLK(NULL, "sl2if_ick", &sl2if_ick, CK_443X),
2912 CLK(NULL, "slimbus1_fclk_1", &slimbus1_fclk_1, CK_443X),
2913 CLK(NULL, "slimbus1_fclk_0", &slimbus1_fclk_0, CK_443X),
2914 CLK(NULL, "slimbus1_fclk_2", &slimbus1_fclk_2, CK_443X),
2915 CLK(NULL, "slimbus1_slimbus_clk", &slimbus1_slimbus_clk, CK_443X),
2625 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X), 2916 CLK(NULL, "slimbus1_fck", &slimbus1_fck, CK_443X),
2917 CLK(NULL, "slimbus2_fclk_1", &slimbus2_fclk_1, CK_443X),
2918 CLK(NULL, "slimbus2_fclk_0", &slimbus2_fclk_0, CK_443X),
2919 CLK(NULL, "slimbus2_slimbus_clk", &slimbus2_slimbus_clk, CK_443X),
2626 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X), 2920 CLK(NULL, "slimbus2_fck", &slimbus2_fck, CK_443X),
2627 CLK(NULL, "sr_core_fck", &sr_core_fck, CK_443X), 2921 CLK(NULL, "smartreflex_core_fck", &smartreflex_core_fck, CK_443X),
2628 CLK(NULL, "sr_iva_fck", &sr_iva_fck, CK_443X), 2922 CLK(NULL, "smartreflex_iva_fck", &smartreflex_iva_fck, CK_443X),
2629 CLK(NULL, "sr_mpu_fck", &sr_mpu_fck, CK_443X), 2923 CLK(NULL, "smartreflex_mpu_fck", &smartreflex_mpu_fck, CK_443X),
2630 CLK(NULL, "tesla_ick", &tesla_ick, CK_443X), 2924 CLK(NULL, "gpt1_fck", &timer1_fck, CK_443X),
2925 CLK(NULL, "gpt10_fck", &timer10_fck, CK_443X),
2926 CLK(NULL, "gpt11_fck", &timer11_fck, CK_443X),
2927 CLK(NULL, "gpt2_fck", &timer2_fck, CK_443X),
2928 CLK(NULL, "gpt3_fck", &timer3_fck, CK_443X),
2929 CLK(NULL, "gpt4_fck", &timer4_fck, CK_443X),
2930 CLK(NULL, "gpt5_fck", &timer5_fck, CK_443X),
2931 CLK(NULL, "gpt6_fck", &timer6_fck, CK_443X),
2932 CLK(NULL, "gpt7_fck", &timer7_fck, CK_443X),
2933 CLK(NULL, "gpt8_fck", &timer8_fck, CK_443X),
2934 CLK(NULL, "gpt9_fck", &timer9_fck, CK_443X),
2631 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X), 2935 CLK(NULL, "uart1_fck", &uart1_fck, CK_443X),
2632 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X), 2936 CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
2633 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X), 2937 CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
2634 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X), 2938 CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
2635 CLK(NULL, "unipro1_fck", &unipro1_fck, CK_443X),
2636 CLK(NULL, "usb_host_fck", &usb_host_fck, CK_443X),
2637 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X), 2939 CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
2638 CLK("musb_hdrc", "ick", &usb_otg_ick, CK_443X), 2940 CLK(NULL, "usb_host_hs_utmi_p3_clk", &usb_host_hs_utmi_p3_clk, CK_443X),
2639 CLK(NULL, "usb_tll_ick", &usb_tll_ick, CK_443X), 2941 CLK(NULL, "usb_host_hs_hsic60m_p1_clk", &usb_host_hs_hsic60m_p1_clk, CK_443X),
2640 CLK(NULL, "usbphyocp2scp_ick", &usbphyocp2scp_ick, CK_443X), 2942 CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
2943 CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
2944 CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
2945 CLK(NULL, "utmi_p2_gfclk", &utmi_p2_gfclk, CK_443X),
2946 CLK(NULL, "usb_host_hs_utmi_p2_clk", &usb_host_hs_utmi_p2_clk, CK_443X),
2947 CLK(NULL, "usb_host_hs_hsic480m_p1_clk", &usb_host_hs_hsic480m_p1_clk, CK_443X),
2948 CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
2949 CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
2950 CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
2951 CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
2952 CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
2953 CLK("musb_hdrc", "ick", &usb_otg_hs_ick, CK_443X),
2954 CLK(NULL, "usb_phy_cm_clk32k", &usb_phy_cm_clk32k, CK_443X),
2955 CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
2956 CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
2957 CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
2958 CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
2959 CLK(NULL, "usim_ck", &usim_ck, CK_443X),
2960 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2641 CLK(NULL, "usim_fck", &usim_fck, CK_443X), 2961 CLK(NULL, "usim_fck", &usim_fck, CK_443X),
2642 CLK("omap_wdt", "fck", &wdt2_fck, CK_443X), 2962 CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
2643 CLK(NULL, "wdt3_fck", &wdt3_fck, CK_443X), 2963 CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
2644 CLK(NULL, "otg_60m_gfclk_ck", &otg_60m_gfclk_ck, CK_443X),
2645 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X), 2964 CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
2646 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X), 2965 CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
2647 CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
2648 CLK(NULL, "utmi_p1_gfclk_ck", &utmi_p1_gfclk_ck, CK_443X),
2649 CLK(NULL, "utmi_p2_gfclk_ck", &utmi_p2_gfclk_ck, CK_443X),
2650 CLK(NULL, "gpio1_dbck", &dummy_ck, CK_443X),
2651 CLK(NULL, "gpio2_dbck", &dummy_ck, CK_443X),
2652 CLK(NULL, "gpio3_dbck", &dummy_ck, CK_443X),
2653 CLK(NULL, "gpio4_dbck", &dummy_ck, CK_443X),
2654 CLK(NULL, "gpio5_dbck", &dummy_ck, CK_443X),
2655 CLK(NULL, "gpio6_dbck", &dummy_ck, CK_443X),
2656 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X), 2966 CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
2657 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X), 2967 CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
2658 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X), 2968 CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -2669,19 +2979,19 @@ static struct omap_clk omap44xx_clks[] = {
2669 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X), 2979 CLK("i2c_omap.2", "ick", &dummy_ck, CK_443X),
2670 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X), 2980 CLK("i2c_omap.3", "ick", &dummy_ck, CK_443X),
2671 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X), 2981 CLK("i2c_omap.4", "ick", &dummy_ck, CK_443X),
2982 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2983 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2984 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2985 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2986 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2672 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 2987 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
2673 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 2988 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
2674 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 2989 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
2675 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X), 2990 CLK("omap-mcbsp.4", "ick", &dummy_ck, CK_443X),
2676 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X), 2991 CLK("omap2_mcspi.1", "ick", &dummy_ck, CK_443X),
2677 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X), 2992 CLK("omap2_mcspi.2", "ick", &dummy_ck, CK_443X),
2678 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X), 2993 CLK("omap2_mcspi.3", "ick", &dummy_ck, CK_443X),
2679 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X), 2994 CLK("omap2_mcspi.4", "ick", &dummy_ck, CK_443X),
2680 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X),
2681 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X),
2682 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X),
2683 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X),
2684 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X),
2685 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X), 2995 CLK(NULL, "uart1_ick", &dummy_ck, CK_443X),
2686 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X), 2996 CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
2687 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X), 2997 CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index ac8458e43252..0b72be433776 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP44xx Clock Management register bits 2 * OMAP44xx Clock Management register bits
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com) 8 * Rajendra Nayak (rnayak@ti.com)
@@ -25,453 +25,459 @@
25#include "cm.h" 25#include "cm.h"
26 26
27 27
28/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 28/*
29 * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
30 * CM_TESLA_DYNAMICDEP
31 */
29#define OMAP4430_ABE_DYNDEP_SHIFT 3 32#define OMAP4430_ABE_DYNDEP_SHIFT 3
30#define OMAP4430_ABE_DYNDEP_MASK BITFIELD(3, 3) 33#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
31 34
32/* 35/*
33 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 36 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
34 * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, 37 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
35 * CM_TESLA_STATICDEP 38 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
36 */ 39 */
37#define OMAP4430_ABE_STATDEP_SHIFT 3 40#define OMAP4430_ABE_STATDEP_SHIFT 3
38#define OMAP4430_ABE_STATDEP_MASK BITFIELD(3, 3) 41#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
39 42
40/* Used by CM_L4CFG_DYNAMICDEP */ 43/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
41#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 44#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
42#define OMAP4430_ALWONCORE_DYNDEP_MASK BITFIELD(16, 16) 45#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
43 46
44/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 47/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
45#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 48#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
46#define OMAP4430_ALWONCORE_STATDEP_MASK BITFIELD(16, 16) 49#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
47 50
48/* 51/*
49 * Used by CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB, 52 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, 53 * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
51 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU 54 * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
55 * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 */ 56 */
53#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 57#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
54#define OMAP4430_AUTO_DPLL_MODE_MASK BITFIELD(0, 2) 58#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
55 59
56/* Used by CM_L4CFG_DYNAMICDEP */ 60/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
57#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 61#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
58#define OMAP4430_CEFUSE_DYNDEP_MASK BITFIELD(17, 17) 62#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
59 63
60/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ 64/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
61#define OMAP4430_CEFUSE_STATDEP_SHIFT 17 65#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
62#define OMAP4430_CEFUSE_STATDEP_MASK BITFIELD(17, 17) 66#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
63 67
64/* Used by CM1_ABE_CLKSTCTRL */ 68/* Used by CM1_ABE_CLKSTCTRL */
65#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 69#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
66#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK BITFIELD(13, 13) 70#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
67 71
68/* Used by CM1_ABE_CLKSTCTRL */ 72/* Used by CM1_ABE_CLKSTCTRL */
69#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 73#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
70#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK BITFIELD(12, 12) 74#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
71 75
72/* Used by CM_WKUP_CLKSTCTRL */ 76/* Used by CM_WKUP_CLKSTCTRL */
73#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 77#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
74#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK BITFIELD(9, 9) 78#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
75 79
76/* Used by CM1_ABE_CLKSTCTRL */ 80/* Used by CM1_ABE_CLKSTCTRL */
77#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 81#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
78#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK BITFIELD(11, 11) 82#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
79 83
80/* Used by CM1_ABE_CLKSTCTRL */ 84/* Used by CM1_ABE_CLKSTCTRL */
81#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 85#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
82#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK BITFIELD(8, 8) 86#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
83 87
84/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 88/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
85#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 89#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
86#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK BITFIELD(11, 11) 90#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
87 91
88/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 92/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
89#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 93#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
90#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK BITFIELD(12, 12) 94#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
91 95
92/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 96/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
93#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 97#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
94#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK BITFIELD(13, 13) 98#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
95 99
96/* Used by CM_CAM_CLKSTCTRL */ 100/* Used by CM_CAM_CLKSTCTRL */
97#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 101#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
98#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK BITFIELD(9, 9) 102#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
103
104/* Used by CM_ALWON_CLKSTCTRL */
105#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
106#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
99 107
100/* Used by CM_EMU_CLKSTCTRL */ 108/* Used by CM_EMU_CLKSTCTRL */
101#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 109#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
102#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK BITFIELD(9, 9) 110#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
103 111
104/* Used by CM_CEFUSE_CLKSTCTRL */ 112/* Used by CM_CEFUSE_CLKSTCTRL */
105#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 113#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
106#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK BITFIELD(9, 9) 114#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
107 115
108/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 116/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
109#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 117#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
110#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK BITFIELD(9, 9) 118#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
111 119
112/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 120/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
113#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 121#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
114#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK BITFIELD(9, 9) 122#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
115 123
116/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 124/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
117#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 125#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
118#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK BITFIELD(10, 10) 126#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
119 127
120/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 128/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
121#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 129#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
122#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK BITFIELD(11, 11) 130#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
123 131
124/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 132/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
125#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 133#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
126#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK BITFIELD(12, 12) 134#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
127 135
128/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 136/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
129#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 137#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
130#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK BITFIELD(13, 13) 138#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
131 139
132/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 140/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
133#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 141#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
134#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK BITFIELD(14, 14) 142#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
135 143
136/* Used by CM_DSS_CLKSTCTRL */ 144/* Used by CM_DSS_CLKSTCTRL */
137#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 145#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
138#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK BITFIELD(10, 10) 146#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10)
139 147
140/* Used by CM_DSS_CLKSTCTRL */ 148/* Used by CM_DSS_CLKSTCTRL */
141#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 149#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
142#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK BITFIELD(9, 9) 150#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9)
143 151
144/* Used by CM_DUCATI_CLKSTCTRL */ 152/* Used by CM_DUCATI_CLKSTCTRL */
145#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 153#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
146#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK BITFIELD(8, 8) 154#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8)
147
148/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
149#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_SHIFT 10
150#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK_MASK BITFIELD(10, 10)
151 155
152/* Used by CM_EMU_CLKSTCTRL */ 156/* Used by CM_EMU_CLKSTCTRL */
153#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 157#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
154#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK BITFIELD(8, 8) 158#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
155 159
156/* Used by CM_CAM_CLKSTCTRL */ 160/* Used by CM_CAM_CLKSTCTRL */
157#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 161#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
158#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK BITFIELD(10, 10) 162#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
159 163
160/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 164/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
161#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 165#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
162#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK BITFIELD(15, 15) 166#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
163 167
164/* Used by CM1_ABE_CLKSTCTRL */ 168/* Used by CM1_ABE_CLKSTCTRL */
165#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 169#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
166#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK BITFIELD(10, 10) 170#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
167 171
168/* Used by CM_DSS_CLKSTCTRL */ 172/* Used by CM_DSS_CLKSTCTRL */
169#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 173#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
170#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK BITFIELD(11, 11) 174#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
171 175
172/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 176/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
173#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 177#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
174#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK BITFIELD(20, 20) 178#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
175 179
176/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 180/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
177#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 181#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
178#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK BITFIELD(26, 26) 182#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
179 183
180/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 184/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
181#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 185#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
182#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK BITFIELD(21, 21) 186#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
183 187
184/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 188/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
185#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 189#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
186#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK BITFIELD(27, 27) 190#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
187
188/* Used by CM_L3INIT_CLKSTCTRL */
189#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_SHIFT 31
190#define OMAP4430_CLKACTIVITY_INIT_32K_GFCLK_MASK BITFIELD(31, 31)
191 191
192/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 192/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
193#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 193#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
194#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK BITFIELD(13, 13) 194#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
195 195
196/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 196/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
197#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 197#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
198#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK BITFIELD(12, 12) 198#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
199 199
200/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 200/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
201#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 201#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
202#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK BITFIELD(28, 28) 202#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
203 203
204/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 204/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
205#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 205#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
206#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK BITFIELD(29, 29) 206#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
207 207
208/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 208/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
209#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 209#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
210#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK BITFIELD(11, 11) 210#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
211 211
212/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 212/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
213#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 213#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
214#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK BITFIELD(16, 16) 214#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
215 215
216/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 216/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
217#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 217#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
218#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK BITFIELD(17, 17) 218#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
219 219
220/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 220/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
221#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 221#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
222#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK BITFIELD(18, 18) 222#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
223 223
224/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 224/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
225#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 225#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
226#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK BITFIELD(19, 19) 226#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
227 227
228/* Used by CM_CAM_CLKSTCTRL */ 228/* Used by CM_CAM_CLKSTCTRL */
229#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 229#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
230#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK BITFIELD(8, 8) 230#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8)
231 231
232/* Used by CM_IVAHD_CLKSTCTRL */ 232/* Used by CM_IVAHD_CLKSTCTRL */
233#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 233#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
234#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK BITFIELD(8, 8) 234#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8)
235 235
236/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 236/* Used by CM_D2D_CLKSTCTRL */
237#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_SHIFT 14 237#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
238#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK_MASK BITFIELD(14, 14) 238#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
239 239
240/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */ 240/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
241#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 241#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
242#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK BITFIELD(8, 8) 242#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
243 243
244/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */ 244/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
245#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 245#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
246#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK BITFIELD(8, 8) 246#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
247 247
248/* Used by CM_D2D_CLKSTCTRL */ 248/* Used by CM_D2D_CLKSTCTRL */
249#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 249#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
250#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK BITFIELD(8, 8) 250#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8)
251 251
252/* Used by CM_SDMA_CLKSTCTRL */ 252/* Used by CM_SDMA_CLKSTCTRL */
253#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 253#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
254#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK BITFIELD(8, 8) 254#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8)
255 255
256/* Used by CM_DSS_CLKSTCTRL */ 256/* Used by CM_DSS_CLKSTCTRL */
257#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 257#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
258#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK BITFIELD(8, 8) 258#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
259 259
260/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 260/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
261#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 261#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
262#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK BITFIELD(8, 8) 262#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
263 263
264/* Used by CM_GFX_CLKSTCTRL */ 264/* Used by CM_GFX_CLKSTCTRL */
265#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 265#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
266#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK BITFIELD(8, 8) 266#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
267 267
268/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 268/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
269#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 269#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
270#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK BITFIELD(8, 8) 270#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
271 271
272/* Used by CM_L3INSTR_CLKSTCTRL */ 272/* Used by CM_L3INSTR_CLKSTCTRL */
273#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 273#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
274#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK BITFIELD(8, 8) 274#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8)
275 275
276/* Used by CM_L4SEC_CLKSTCTRL */ 276/* Used by CM_L4SEC_CLKSTCTRL */
277#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 277#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
278#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK BITFIELD(8, 8) 278#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8)
279 279
280/* Used by CM_ALWON_CLKSTCTRL */ 280/* Used by CM_ALWON_CLKSTCTRL */
281#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 281#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
282#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK BITFIELD(8, 8) 282#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8)
283 283
284/* Used by CM_CEFUSE_CLKSTCTRL */ 284/* Used by CM_CEFUSE_CLKSTCTRL */
285#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 285#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
286#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK BITFIELD(8, 8) 286#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
287 287
288/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */ 288/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
289#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 289#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
290#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK BITFIELD(8, 8) 290#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
291 291
292/* Used by CM_D2D_CLKSTCTRL */ 292/* Used by CM_D2D_CLKSTCTRL */
293#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 293#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
294#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK BITFIELD(9, 9) 294#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
295 295
296/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 296/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
297#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 297#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
298#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK BITFIELD(9, 9) 298#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
299 299
300/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 300/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
301#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 301#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
302#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK BITFIELD(8, 8) 302#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
303 303
304/* Used by CM_L4SEC_CLKSTCTRL */ 304/* Used by CM_L4SEC_CLKSTCTRL */
305#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 305#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
306#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK BITFIELD(9, 9) 306#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9)
307 307
308/* Used by CM_WKUP_CLKSTCTRL */ 308/* Used by CM_WKUP_CLKSTCTRL */
309#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 309#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
310#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK BITFIELD(12, 12) 310#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
311 311
312/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */ 312/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
313#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 313#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
314#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK BITFIELD(8, 8) 314#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
315 315
316/* Used by CM1_ABE_CLKSTCTRL */ 316/* Used by CM1_ABE_CLKSTCTRL */
317#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 317#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
318#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK BITFIELD(9, 9) 318#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
319 319
320/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 320/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
321#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 321#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
322#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK BITFIELD(16, 16) 322#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
323 323
324/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 324/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
325#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 325#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
326#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK BITFIELD(17, 17) 326#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
327 327
328/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 328/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
329#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 329#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
330#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK BITFIELD(18, 18) 330#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
331 331
332/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 332/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
333#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 333#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
334#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK BITFIELD(19, 19) 334#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
335 335
336/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 336/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
337#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 337#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
338#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK BITFIELD(25, 25) 338#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
339
340/* Used by CM_EMU_CLKSTCTRL */
341#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_SHIFT 10
342#define OMAP4430_CLKACTIVITY_PER_DPLL_EMU_CLK_MASK BITFIELD(10, 10)
343 339
344/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 340/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
345#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 341#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
346#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK BITFIELD(20, 20) 342#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
347 343
348/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 344/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
349#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 345#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
350#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK BITFIELD(21, 21) 346#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
351 347
352/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 348/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
353#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 349#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
354#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK BITFIELD(22, 22) 350#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
355 351
356/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */ 352/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
357#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 353#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
358#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK BITFIELD(24, 24) 354#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
359 355
360/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */ 356/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
361#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 357#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
362#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK BITFIELD(10, 10) 358#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
363 359
364/* Used by CM_GFX_CLKSTCTRL */ 360/* Used by CM_GFX_CLKSTCTRL */
365#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 361#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
366#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK BITFIELD(9, 9) 362#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9)
367 363
368/* Used by CM_ALWON_CLKSTCTRL */ 364/* Used by CM_ALWON_CLKSTCTRL */
369#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 365#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
370#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK BITFIELD(11, 11) 366#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11)
371 367
372/* Used by CM_ALWON_CLKSTCTRL */ 368/* Used by CM_ALWON_CLKSTCTRL */
373#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 369#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
374#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK BITFIELD(10, 10) 370#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10)
375 371
376/* Used by CM_ALWON_CLKSTCTRL */ 372/* Used by CM_ALWON_CLKSTCTRL */
377#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 373#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
378#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK BITFIELD(9, 9) 374#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9)
379 375
380/* Used by CM_WKUP_CLKSTCTRL */ 376/* Used by CM_WKUP_CLKSTCTRL */
381#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 377#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
382#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK BITFIELD(8, 8) 378#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
383 379
384/* Used by CM_TESLA_CLKSTCTRL */ 380/* Used by CM_TESLA_CLKSTCTRL */
385#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 381#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
386#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK BITFIELD(8, 8) 382#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
387 383
388/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 384/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
389#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 385#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
390#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK BITFIELD(22, 22) 386#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
391 387
392/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 388/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
393#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 389#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
394#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK BITFIELD(23, 23) 390#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
395 391
396/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 392/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
397#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 393#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
398#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK BITFIELD(24, 24) 394#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
395
396/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
397#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
398#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
399
400/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
401#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
402#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
399 403
400/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 404/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
401#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 405#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
402#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK BITFIELD(15, 15) 406#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
403 407
404/* Used by CM_WKUP_CLKSTCTRL */ 408/* Used by CM_WKUP_CLKSTCTRL */
405#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 409#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
406#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK BITFIELD(10, 10) 410#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
407 411
408/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 412/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
409#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 413#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
410#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK BITFIELD(30, 30) 414#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
411 415
412/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */ 416/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
413#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 417#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
414#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK BITFIELD(25, 25) 418#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
415 419
416/* Used by CM_WKUP_CLKSTCTRL */ 420/* Used by CM_WKUP_CLKSTCTRL */
417#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 421#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
418#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK BITFIELD(11, 11) 422#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
419 423
420/* 424/*
421 * Used by CM_WKUP_TIMER1_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, 425 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
426 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
427 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
422 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, 428 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
423 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, 429 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
424 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, 430 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
425 * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, 431 * CM_WKUP_TIMER1_CLKCTRL
426 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
427 * CM1_ABE_TIMER8_CLKCTRL
428 */ 432 */
429#define OMAP4430_CLKSEL_SHIFT 24 433#define OMAP4430_CLKSEL_SHIFT 24
430#define OMAP4430_CLKSEL_MASK BITFIELD(24, 24) 434#define OMAP4430_CLKSEL_MASK (1 << 24)
431 435
432/* 436/*
433 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, 437 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
434 * CM_DPLL_SYS_REF_CLKSEL, CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, 438 * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
435 * CM_CLKSEL_USB_60MHZ
436 */ 439 */
437#define OMAP4430_CLKSEL_0_0_SHIFT 0 440#define OMAP4430_CLKSEL_0_0_SHIFT 0
438#define OMAP4430_CLKSEL_0_0_MASK BITFIELD(0, 0) 441#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
439 442
440/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ 443/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
441#define OMAP4430_CLKSEL_0_1_SHIFT 0 444#define OMAP4430_CLKSEL_0_1_SHIFT 0
442#define OMAP4430_CLKSEL_0_1_MASK BITFIELD(0, 1) 445#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0)
443 446
444/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ 447/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
445#define OMAP4430_CLKSEL_24_25_SHIFT 24 448#define OMAP4430_CLKSEL_24_25_SHIFT 24
446#define OMAP4430_CLKSEL_24_25_MASK BITFIELD(24, 25) 449#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24)
447 450
448/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 451/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
449#define OMAP4430_CLKSEL_60M_SHIFT 24 452#define OMAP4430_CLKSEL_60M_SHIFT 24
450#define OMAP4430_CLKSEL_60M_MASK BITFIELD(24, 24) 453#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
451 454
452/* Used by CM1_ABE_AESS_CLKCTRL */ 455/* Used by CM1_ABE_AESS_CLKCTRL */
453#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 456#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
454#define OMAP4430_CLKSEL_AESS_FCLK_MASK BITFIELD(24, 24) 457#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
455 458
456/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 459/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
457#define OMAP4430_CLKSEL_CORE_SHIFT 0 460#define OMAP4430_CLKSEL_CORE_SHIFT 0
458#define OMAP4430_CLKSEL_CORE_MASK BITFIELD(0, 0) 461#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
459 462
460/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ 463/*
464 * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
465 * CM_SHADOW_FREQ_CONFIG2
466 */
461#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 467#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
462#define OMAP4430_CLKSEL_CORE_1_1_MASK BITFIELD(1, 1) 468#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
463 469
464/* Used by CM_WKUP_USIM_CLKCTRL */ 470/* Used by CM_WKUP_USIM_CLKCTRL */
465#define OMAP4430_CLKSEL_DIV_SHIFT 24 471#define OMAP4430_CLKSEL_DIV_SHIFT 24
466#define OMAP4430_CLKSEL_DIV_MASK BITFIELD(24, 24) 472#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
467 473
468/* Used by CM_CAM_FDIF_CLKCTRL */ 474/* Used by CM_CAM_FDIF_CLKCTRL */
469#define OMAP4430_CLKSEL_FCLK_SHIFT 24 475#define OMAP4430_CLKSEL_FCLK_SHIFT 24
470#define OMAP4430_CLKSEL_FCLK_MASK BITFIELD(24, 25) 476#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
471 477
472/* Used by CM_L4PER_MCBSP4_CLKCTRL */ 478/* Used by CM_L4PER_MCBSP4_CLKCTRL */
473#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 479#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
474#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK BITFIELD(25, 25) 480#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25)
475 481
476/* 482/*
477 * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, 483 * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
@@ -479,836 +485,869 @@
479 * CM1_ABE_MCBSP3_CLKCTRL 485 * CM1_ABE_MCBSP3_CLKCTRL
480 */ 486 */
481#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 487#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
482#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK BITFIELD(26, 27) 488#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
483 489
484/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 490/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
485#define OMAP4430_CLKSEL_L3_SHIFT 4 491#define OMAP4430_CLKSEL_L3_SHIFT 4
486#define OMAP4430_CLKSEL_L3_MASK BITFIELD(4, 4) 492#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
487 493
488/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ 494/*
495 * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
496 * CM_SHADOW_FREQ_CONFIG2
497 */
489#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 498#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
490#define OMAP4430_CLKSEL_L3_SHADOW_MASK BITFIELD(2, 2) 499#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
491 500
492/* Used by CM_CLKSEL_CORE_RESTORE, CM_CLKSEL_CORE */ 501/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
493#define OMAP4430_CLKSEL_L4_SHIFT 8 502#define OMAP4430_CLKSEL_L4_SHIFT 8
494#define OMAP4430_CLKSEL_L4_MASK BITFIELD(8, 8) 503#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
495 504
496/* Used by CM_CLKSEL_ABE */ 505/* Used by CM_CLKSEL_ABE */
497#define OMAP4430_CLKSEL_OPP_SHIFT 0 506#define OMAP4430_CLKSEL_OPP_SHIFT 0
498#define OMAP4430_CLKSEL_OPP_MASK BITFIELD(0, 1) 507#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0)
499
500/* Used by CM_GFX_GFX_CLKCTRL */
501#define OMAP4430_CLKSEL_PER_192M_SHIFT 25
502#define OMAP4430_CLKSEL_PER_192M_MASK BITFIELD(25, 26)
503 508
504/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 509/* Used by CM_EMU_DEBUGSS_CLKCTRL */
505#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 510#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
506#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK BITFIELD(27, 29) 511#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27)
507 512
508/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 513/* Used by CM_EMU_DEBUGSS_CLKCTRL */
509#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 514#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
510#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK BITFIELD(24, 26) 515#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
511 516
512/* Used by CM_GFX_GFX_CLKCTRL */ 517/* Used by CM_GFX_GFX_CLKCTRL */
513#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 518#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
514#define OMAP4430_CLKSEL_SGX_FCLK_MASK BITFIELD(24, 24) 519#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
515 520
516/* 521/*
517 * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, 522 * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
518 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL 523 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
519 */ 524 */
520#define OMAP4430_CLKSEL_SOURCE_SHIFT 24 525#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
521#define OMAP4430_CLKSEL_SOURCE_MASK BITFIELD(24, 25) 526#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
522 527
523/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ 528/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
524#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 529#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
525#define OMAP4430_CLKSEL_SOURCE_24_24_MASK BITFIELD(24, 24) 530#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
526 531
527/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 532/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
528#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 533#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
529#define OMAP4430_CLKSEL_UTMI_P1_MASK BITFIELD(24, 24) 534#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
530 535
531/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 536/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
532#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 537#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
533#define OMAP4430_CLKSEL_UTMI_P2_MASK BITFIELD(25, 25) 538#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
534 539
535/* 540/*
536 * Used by CM_WKUP_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_D2D_CLKSTCTRL, 541 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
537 * CM_DUCATI_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, 542 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
538 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, 543 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
539 * CM_SDMA_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, 544 * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
540 * CM_L3INIT_CLKSTCTRL, CM_CAM_CLKSTCTRL, CM_CEFUSE_CLKSTCTRL, 545 * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
541 * CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3_1_CLKSTCTRL_RESTORE, 546 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
542 * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL_RESTORE, 547 * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
543 * CM_L4PER_CLKSTCTRL_RESTORE, CM_MEMIF_CLKSTCTRL_RESTORE, CM_ALWON_CLKSTCTRL, 548 * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
544 * CM_IVAHD_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_TESLA_CLKSTCTRL, 549 * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
545 * CM1_ABE_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE 550 * CM_WKUP_CLKSTCTRL
546 */ 551 */
547#define OMAP4430_CLKTRCTRL_SHIFT 0 552#define OMAP4430_CLKTRCTRL_SHIFT 0
548#define OMAP4430_CLKTRCTRL_MASK BITFIELD(0, 1) 553#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
549 554
550/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 555/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
551#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 556#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
552#define OMAP4430_CORE_DPLL_EMU_DIV_MASK BITFIELD(0, 6) 557#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
553 558
554/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ 559/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
555#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 560#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
556#define OMAP4430_CORE_DPLL_EMU_MULT_MASK BITFIELD(8, 18) 561#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
562
563/* Used by REVISION_CM1, REVISION_CM2 */
564#define OMAP4430_CUSTOM_SHIFT 6
565#define OMAP4430_CUSTOM_MASK (0x3 << 6)
557 566
558/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 567/*
568 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
569 * CM_L4CFG_DYNAMICDEP_RESTORE
570 */
559#define OMAP4430_D2D_DYNDEP_SHIFT 18 571#define OMAP4430_D2D_DYNDEP_SHIFT 18
560#define OMAP4430_D2D_DYNDEP_MASK BITFIELD(18, 18) 572#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
561 573
562/* Used by CM_MPU_STATICDEP */ 574/* Used by CM_MPU_STATICDEP */
563#define OMAP4430_D2D_STATDEP_SHIFT 18 575#define OMAP4430_D2D_STATDEP_SHIFT 18
564#define OMAP4430_D2D_STATDEP_MASK BITFIELD(18, 18) 576#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
565 577
566/* 578/*
567 * Used by CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO, 579 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
568 * CM_SSC_DELTAMSTEP_DPLL_USB, CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, 580 * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
569 * CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, 581 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
570 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, 582 * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
571 * CM_SSC_DELTAMSTEP_DPLL_MPU 583 * CM_SSC_DELTAMSTEP_DPLL_USB
572 */ 584 */
573#define OMAP4430_DELTAMSTEP_SHIFT 0 585#define OMAP4430_DELTAMSTEP_SHIFT 0
574#define OMAP4430_DELTAMSTEP_MASK BITFIELD(0, 19) 586#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
575 587
576/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 588/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
577#define OMAP4430_DLL_OVERRIDE_SHIFT 2 589#define OMAP4430_DLL_OVERRIDE_SHIFT 2
578#define OMAP4430_DLL_OVERRIDE_MASK BITFIELD(2, 2) 590#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
579 591
580/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */ 592/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
581#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0 593#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0
582#define OMAP4430_DLL_OVERRIDE_0_0_MASK BITFIELD(0, 0) 594#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0)
583 595
584/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 596/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
585#define OMAP4430_DLL_RESET_SHIFT 3 597#define OMAP4430_DLL_RESET_SHIFT 3
586#define OMAP4430_DLL_RESET_MASK BITFIELD(3, 3) 598#define OMAP4430_DLL_RESET_MASK (1 << 3)
587 599
588/* 600/*
589 * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB, 601 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
590 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 602 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
591 * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 603 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
604 * CM_CLKSEL_DPLL_USB
592 */ 605 */
593#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 606#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
594#define OMAP4430_DPLL_BYP_CLKSEL_MASK BITFIELD(23, 23) 607#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
595 608
596/* Used by CM_CLKDCOLDO_DPLL_USB */ 609/* Used by CM_CLKDCOLDO_DPLL_USB */
597#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 610#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
598#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK BITFIELD(8, 8) 611#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
599 612
600/* Used by CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_CORE */ 613/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
601#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 614#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
602#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK BITFIELD(20, 20) 615#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
603 616
604/* 617/*
605 * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 618 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
606 * CM_DIV_M3_DPLL_CORE 619 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
607 */ 620 */
608#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 621#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
609#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK BITFIELD(0, 4) 622#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
610 623
611/* 624/*
612 * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 625 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
613 * CM_DIV_M3_DPLL_CORE 626 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
614 */ 627 */
615#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 628#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
616#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK BITFIELD(5, 5) 629#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
617 630
618/* 631/*
619 * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 632 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
620 * CM_DIV_M3_DPLL_CORE 633 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
621 */ 634 */
622#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 635#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
623#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK BITFIELD(8, 8) 636#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
624 637
625/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ 638/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
626#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 639#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
627#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK BITFIELD(10, 10) 640#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
628 641
629/* 642/*
630 * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, 643 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
631 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 644 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
632 * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU 645 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
633 */ 646 */
634#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 647#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
635#define OMAP4430_DPLL_CLKOUT_DIV_MASK BITFIELD(0, 4) 648#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
636 649
637/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ 650/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
638#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 651#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
639#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK BITFIELD(0, 6) 652#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
640 653
641/* 654/*
642 * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, 655 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
643 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, 656 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
644 * CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU 657 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
645 */ 658 */
646#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 659#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
647#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK BITFIELD(5, 5) 660#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
648 661
649/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ 662/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
650#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 663#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
651#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK BITFIELD(7, 7) 664#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
652 665
653/* 666/*
654 * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, 667 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
655 * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, 668 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
656 * CM_DIV_M2_DPLL_MPU 669 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
657 */ 670 */
658#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 671#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
659#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK BITFIELD(8, 8) 672#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
660 673
661/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 674/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
662#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 675#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
663#define OMAP4430_DPLL_CORE_DPLL_EN_MASK BITFIELD(8, 10) 676#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
664 677
665/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 678/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
666#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 679#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
667#define OMAP4430_DPLL_CORE_M2_DIV_MASK BITFIELD(11, 15) 680#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
668 681
669/* Used by CM_SHADOW_FREQ_CONFIG2 */ 682/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
670#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 683#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
671#define OMAP4430_DPLL_CORE_M5_DIV_MASK BITFIELD(3, 7) 684#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
672
673/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */
674#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_SHIFT 1
675#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL_MASK BITFIELD(1, 1)
676 685
677/* 686/*
678 * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 687 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
679 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 688 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
680 * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 689 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
681 */ 690 */
682#define OMAP4430_DPLL_DIV_SHIFT 0 691#define OMAP4430_DPLL_DIV_SHIFT 0
683#define OMAP4430_DPLL_DIV_MASK BITFIELD(0, 6) 692#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
684 693
685/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ 694/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
686#define OMAP4430_DPLL_DIV_0_7_SHIFT 0 695#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
687#define OMAP4430_DPLL_DIV_0_7_MASK BITFIELD(0, 7) 696#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
688 697
689/* 698/*
690 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_USB, 699 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
691 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 700 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
692 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 701 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
693 */ 702 */
694#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 703#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
695#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK BITFIELD(8, 8) 704#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
696 705
697/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ 706/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
698#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 707#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
699#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK BITFIELD(3, 3) 708#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
700 709
701/* 710/*
702 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 711 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
703 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 712 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
704 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 713 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
714 * CM_CLKMODE_DPLL_USB
705 */ 715 */
706#define OMAP4430_DPLL_EN_SHIFT 0 716#define OMAP4430_DPLL_EN_SHIFT 0
707#define OMAP4430_DPLL_EN_MASK BITFIELD(0, 2) 717#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
708 718
709/* 719/*
710 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 720 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
711 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 721 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
712 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 722 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
713 */ 723 */
714#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 724#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
715#define OMAP4430_DPLL_LPMODE_EN_MASK BITFIELD(10, 10) 725#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
716 726
717/* 727/*
718 * Used by CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO, 728 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
719 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, 729 * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
720 * CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU 730 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
721 */ 731 */
722#define OMAP4430_DPLL_MULT_SHIFT 8 732#define OMAP4430_DPLL_MULT_SHIFT 8
723#define OMAP4430_DPLL_MULT_MASK BITFIELD(8, 18) 733#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
724 734
725/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ 735/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
726#define OMAP4430_DPLL_MULT_USB_SHIFT 8 736#define OMAP4430_DPLL_MULT_USB_SHIFT 8
727#define OMAP4430_DPLL_MULT_USB_MASK BITFIELD(8, 19) 737#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
728 738
729/* 739/*
730 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, 740 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
731 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 741 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
732 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 742 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
733 */ 743 */
734#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 744#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
735#define OMAP4430_DPLL_REGM4XEN_MASK BITFIELD(11, 11) 745#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
736 746
737/* Used by CM_CLKSEL_DPLL_USB */ 747/* Used by CM_CLKSEL_DPLL_USB */
738#define OMAP4430_DPLL_SD_DIV_SHIFT 24 748#define OMAP4430_DPLL_SD_DIV_SHIFT 24
739#define OMAP4430_DPLL_SD_DIV_MASK BITFIELD(24, 31) 749#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
740 750
741/* 751/*
742 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 752 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
743 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 753 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
744 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 754 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
755 * CM_CLKMODE_DPLL_USB
745 */ 756 */
746#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 757#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
747#define OMAP4430_DPLL_SSC_ACK_MASK BITFIELD(13, 13) 758#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
748 759
749/* 760/*
750 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 761 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
751 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 762 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
752 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 763 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
764 * CM_CLKMODE_DPLL_USB
753 */ 765 */
754#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 766#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
755#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK BITFIELD(14, 14) 767#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
756 768
757/* 769/*
758 * Used by CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB, 770 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
759 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, 771 * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
760 * CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU 772 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
773 * CM_CLKMODE_DPLL_USB
761 */ 774 */
762#define OMAP4430_DPLL_SSC_EN_SHIFT 12 775#define OMAP4430_DPLL_SSC_EN_SHIFT 12
763#define OMAP4430_DPLL_SSC_EN_MASK BITFIELD(12, 12) 776#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
764 777
765/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 778/*
779 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
780 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
781 */
766#define OMAP4430_DSS_DYNDEP_SHIFT 8 782#define OMAP4430_DSS_DYNDEP_SHIFT 8
767#define OMAP4430_DSS_DYNDEP_MASK BITFIELD(8, 8) 783#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
768 784
769/* 785/*
770 * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 786 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
771 * CM_MPU_STATICDEP 787 * CM_SDMA_STATICDEP_RESTORE
772 */ 788 */
773#define OMAP4430_DSS_STATDEP_SHIFT 8 789#define OMAP4430_DSS_STATDEP_SHIFT 8
774#define OMAP4430_DSS_STATDEP_MASK BITFIELD(8, 8) 790#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
775 791
776/* Used by CM_L3_2_DYNAMICDEP */ 792/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
777#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 793#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
778#define OMAP4430_DUCATI_DYNDEP_MASK BITFIELD(0, 0) 794#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
779 795
780/* Used by CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP */ 796/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
781#define OMAP4430_DUCATI_STATDEP_SHIFT 0 797#define OMAP4430_DUCATI_STATDEP_SHIFT 0
782#define OMAP4430_DUCATI_STATDEP_MASK BITFIELD(0, 0) 798#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
783 799
784/* Used by CM_SHADOW_FREQ_CONFIG1_RESTORE, CM_SHADOW_FREQ_CONFIG1 */ 800/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
785#define OMAP4430_FREQ_UPDATE_SHIFT 0 801#define OMAP4430_FREQ_UPDATE_SHIFT 0
786#define OMAP4430_FREQ_UPDATE_MASK BITFIELD(0, 0) 802#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
803
804/* Used by REVISION_CM1, REVISION_CM2 */
805#define OMAP4430_FUNC_SHIFT 16
806#define OMAP4430_FUNC_MASK (0xfff << 16)
787 807
788/* Used by CM_L3_2_DYNAMICDEP */ 808/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
789#define OMAP4430_GFX_DYNDEP_SHIFT 10 809#define OMAP4430_GFX_DYNDEP_SHIFT 10
790#define OMAP4430_GFX_DYNDEP_MASK BITFIELD(10, 10) 810#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
791 811
792/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 812/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
793#define OMAP4430_GFX_STATDEP_SHIFT 10 813#define OMAP4430_GFX_STATDEP_SHIFT 10
794#define OMAP4430_GFX_STATDEP_MASK BITFIELD(10, 10) 814#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
795 815
796/* Used by CM_SHADOW_FREQ_CONFIG2 */ 816/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
797#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 817#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
798#define OMAP4430_GPMC_FREQ_UPDATE_MASK BITFIELD(0, 0) 818#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
799 819
800/* 820/*
801 * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 821 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
802 * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 822 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
803 */ 823 */
804#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 824#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
805#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK BITFIELD(0, 4) 825#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
806 826
807/* 827/*
808 * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 828 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
809 * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 829 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
810 */ 830 */
811#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 831#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
812#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK BITFIELD(5, 5) 832#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
813 833
814/* 834/*
815 * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 835 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
816 * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 836 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
817 */ 837 */
818#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 838#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
819#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK BITFIELD(8, 8) 839#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
820 840
821/* 841/*
822 * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 842 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
823 * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 843 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
824 */ 844 */
825#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 845#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
826#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK BITFIELD(12, 12) 846#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
827 847
828/* 848/*
829 * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 849 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
830 * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 850 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
831 */ 851 */
832#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 852#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
833#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK BITFIELD(0, 4) 853#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
834 854
835/* 855/*
836 * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 856 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
837 * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 857 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
838 */ 858 */
839#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 859#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
840#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK BITFIELD(5, 5) 860#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
841 861
842/* 862/*
843 * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 863 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
844 * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 864 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
845 */ 865 */
846#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 866#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
847#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK BITFIELD(8, 8) 867#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
848 868
849/* 869/*
850 * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 870 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
851 * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 871 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
852 */ 872 */
853#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 873#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
854#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK BITFIELD(12, 12) 874#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
855 875
856/* 876/*
857 * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 877 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
858 * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 878 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
859 */ 879 */
860#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 880#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
861#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK BITFIELD(0, 4) 881#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
862 882
863/* 883/*
864 * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 884 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
865 * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 885 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
866 */ 886 */
867#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 887#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
868#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK BITFIELD(5, 5) 888#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
869 889
870/* 890/*
871 * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 891 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
872 * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 892 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
873 */ 893 */
874#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 894#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
875#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK BITFIELD(8, 8) 895#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
876 896
877/* 897/*
878 * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 898 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
879 * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 899 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
880 */ 900 */
881#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 901#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
882#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK BITFIELD(12, 12) 902#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
883 903
884/* 904/*
885 * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 905 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
886 * CM_DIV_M7_DPLL_CORE 906 * CM_DIV_M7_DPLL_PER
887 */ 907 */
888#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 908#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
889#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK BITFIELD(0, 4) 909#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
890 910
891/* 911/*
892 * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 912 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
893 * CM_DIV_M7_DPLL_CORE 913 * CM_DIV_M7_DPLL_PER
894 */ 914 */
895#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 915#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
896#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK BITFIELD(5, 5) 916#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
897 917
898/* 918/*
899 * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 919 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
900 * CM_DIV_M7_DPLL_CORE 920 * CM_DIV_M7_DPLL_PER
901 */ 921 */
902#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 922#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
903#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK BITFIELD(8, 8) 923#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
904 924
905/* 925/*
906 * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 926 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
907 * CM_DIV_M7_DPLL_CORE 927 * CM_DIV_M7_DPLL_PER
908 */ 928 */
909#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 929#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
910#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK BITFIELD(12, 12) 930#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
911 931
912/* 932/*
913 * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, 933 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
914 * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, 934 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
915 * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, 935 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
916 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, 936 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
917 * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, 937 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
918 * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 938 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
919 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 939 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
920 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, 940 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
921 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, 941 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
922 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 942 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
923 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 943 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
924 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 944 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
925 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 945 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
926 * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
927 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
928 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
929 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
930 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
931 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
932 * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
933 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
934 * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
935 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
936 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
937 * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
938 * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
939 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
940 * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
941 * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
942 * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
943 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 946 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
944 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 947 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
945 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 948 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
946 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 949 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
947 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 950 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
948 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 951 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
949 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 952 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
950 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, 953 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
951 * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 954 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
952 * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 955 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
953 * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 956 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
954 * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 957 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
955 * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, 958 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
956 * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, 959 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
957 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 960 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
958 * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, 961 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
959 * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, 962 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
960 * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, 963 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
961 * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, 964 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
962 * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, 965 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
963 * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL 966 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
967 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
968 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
969 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
970 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
971 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
972 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
973 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
974 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
975 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
976 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
977 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
978 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
979 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
980 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
981 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
982 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
983 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
984 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
964 */ 985 */
965#define OMAP4430_IDLEST_SHIFT 16 986#define OMAP4430_IDLEST_SHIFT 16
966#define OMAP4430_IDLEST_MASK BITFIELD(16, 17) 987#define OMAP4430_IDLEST_MASK (0x3 << 16)
967 988
968/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ 989/*
990 * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
991 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
992 */
969#define OMAP4430_ISS_DYNDEP_SHIFT 9 993#define OMAP4430_ISS_DYNDEP_SHIFT 9
970#define OMAP4430_ISS_DYNDEP_MASK BITFIELD(9, 9) 994#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
971 995
972/* 996/*
973 * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 997 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
974 * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 998 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
975 */ 999 */
976#define OMAP4430_ISS_STATDEP_SHIFT 9 1000#define OMAP4430_ISS_STATDEP_SHIFT 9
977#define OMAP4430_ISS_STATDEP_MASK BITFIELD(9, 9) 1001#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
978 1002
979/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ 1003/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
980#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 1004#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
981#define OMAP4430_IVAHD_DYNDEP_MASK BITFIELD(2, 2) 1005#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
982 1006
983/* 1007/*
984 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1008 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
985 * CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1009 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
986 * CM_SDMA_STATICDEP_RESTORE, CM_DSS_STATICDEP, CM_MPU_STATICDEP, 1010 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
987 * CM_TESLA_STATICDEP 1011 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
988 */ 1012 */
989#define OMAP4430_IVAHD_STATDEP_SHIFT 2 1013#define OMAP4430_IVAHD_STATDEP_SHIFT 2
990#define OMAP4430_IVAHD_STATDEP_MASK BITFIELD(2, 2) 1014#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
991 1015
992/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1016/*
1017 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1018 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
1019 */
993#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 1020#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
994#define OMAP4430_L3INIT_DYNDEP_MASK BITFIELD(7, 7) 1021#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
995 1022
996/* 1023/*
997 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1024 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
998 * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1025 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
1026 * CM_TESLA_STATICDEP
999 */ 1027 */
1000#define OMAP4430_L3INIT_STATDEP_SHIFT 7 1028#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1001#define OMAP4430_L3INIT_STATDEP_MASK BITFIELD(7, 7) 1029#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1002 1030
1003/* 1031/*
1004 * Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, 1032 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1005 * CM_DSS_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1033 * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1034 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1006 */ 1035 */
1007#define OMAP4430_L3_1_DYNDEP_SHIFT 5 1036#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1008#define OMAP4430_L3_1_DYNDEP_MASK BITFIELD(5, 5) 1037#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1009 1038
1010/* 1039/*
1011 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1040 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1012 * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1041 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1013 * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1042 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1014 * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1043 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1015 */ 1044 */
1016#define OMAP4430_L3_1_STATDEP_SHIFT 5 1045#define OMAP4430_L3_1_STATDEP_SHIFT 5
1017#define OMAP4430_L3_1_STATDEP_MASK BITFIELD(5, 5) 1046#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1018 1047
1019/* 1048/*
1020 * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, 1049 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
1021 * CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_SDMA_DYNAMICDEP, 1050 * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
1022 * CM_GFX_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, 1051 * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
1023 * CM_CAM_DYNAMICDEP, CM_IVAHD_DYNAMICDEP 1052 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1053 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1024 */ 1054 */
1025#define OMAP4430_L3_2_DYNDEP_SHIFT 6 1055#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1026#define OMAP4430_L3_2_DYNDEP_MASK BITFIELD(6, 6) 1056#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1027 1057
1028/* 1058/*
1029 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1059 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1030 * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1060 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1031 * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1061 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1032 * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1062 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1033 */ 1063 */
1034#define OMAP4430_L3_2_STATDEP_SHIFT 6 1064#define OMAP4430_L3_2_STATDEP_SHIFT 6
1035#define OMAP4430_L3_2_STATDEP_MASK BITFIELD(6, 6) 1065#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1036 1066
1037/* Used by CM_L3_1_DYNAMICDEP */ 1067/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
1038#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 1068#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1039#define OMAP4430_L4CFG_DYNDEP_MASK BITFIELD(12, 12) 1069#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1040 1070
1041/* 1071/*
1042 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1072 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1043 * CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, 1073 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1044 * CM_TESLA_STATICDEP 1074 * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1045 */ 1075 */
1046#define OMAP4430_L4CFG_STATDEP_SHIFT 12 1076#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1047#define OMAP4430_L4CFG_STATDEP_MASK BITFIELD(12, 12) 1077#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1048 1078
1049/* Used by CM_L3_2_DYNAMICDEP */ 1079/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
1050#define OMAP4430_L4PER_DYNDEP_SHIFT 13 1080#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1051#define OMAP4430_L4PER_DYNDEP_MASK BITFIELD(13, 13) 1081#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1052 1082
1053/* 1083/*
1054 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1084 * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
1055 * CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_SDMA_STATICDEP_RESTORE, 1085 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1056 * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1086 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1057 */ 1087 */
1058#define OMAP4430_L4PER_STATDEP_SHIFT 13 1088#define OMAP4430_L4PER_STATDEP_SHIFT 13
1059#define OMAP4430_L4PER_STATDEP_MASK BITFIELD(13, 13) 1089#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1060 1090
1061/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ 1091/*
1092 * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1093 * CM_L4PER_DYNAMICDEP_RESTORE
1094 */
1062#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 1095#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1063#define OMAP4430_L4SEC_DYNDEP_MASK BITFIELD(14, 14) 1096#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1064 1097
1065/* 1098/*
1066 * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, 1099 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1067 * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP 1100 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
1068 */ 1101 */
1069#define OMAP4430_L4SEC_STATDEP_SHIFT 14 1102#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1070#define OMAP4430_L4SEC_STATDEP_MASK BITFIELD(14, 14) 1103#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1071 1104
1072/* Used by CM_L4CFG_DYNAMICDEP */ 1105/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1073#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 1106#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1074#define OMAP4430_L4WKUP_DYNDEP_MASK BITFIELD(15, 15) 1107#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1075 1108
1076/* 1109/*
1077 * Used by CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, CM_L3INIT_STATICDEP, 1110 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1078 * CM_SDMA_STATICDEP_RESTORE, CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1111 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1079 */ 1112 */
1080#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 1113#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1081#define OMAP4430_L4WKUP_STATDEP_MASK BITFIELD(15, 15) 1114#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1082 1115
1083/* 1116/*
1084 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, 1117 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
1085 * CM_MPU_DYNAMICDEP 1118 * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1119 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
1086 */ 1120 */
1087#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 1121#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1088#define OMAP4430_MEMIF_DYNDEP_MASK BITFIELD(4, 4) 1122#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1089 1123
1090/* 1124/*
1091 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_SDMA_STATICDEP, 1125 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
1092 * CM_GFX_STATICDEP, CM_L4SEC_STATICDEP, CM_L3INIT_STATICDEP, CM_CAM_STATICDEP, 1126 * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1093 * CM_SDMA_STATICDEP_RESTORE, CM_IVAHD_STATICDEP, CM_DSS_STATICDEP, 1127 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1094 * CM_MPU_STATICDEP, CM_TESLA_STATICDEP 1128 * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
1095 */ 1129 */
1096#define OMAP4430_MEMIF_STATDEP_SHIFT 4 1130#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1097#define OMAP4430_MEMIF_STATDEP_MASK BITFIELD(4, 4) 1131#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1098 1132
1099/* 1133/*
1100 * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1134 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1101 * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, 1135 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1102 * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1136 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1103 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, 1137 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1104 * CM_SSC_MODFREQDIV_DPLL_MPU 1138 * CM_SSC_MODFREQDIV_DPLL_USB
1105 */ 1139 */
1106#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 1140#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1107#define OMAP4430_MODFREQDIV_EXPONENT_MASK BITFIELD(8, 10) 1141#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1108 1142
1109/* 1143/*
1110 * Used by CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO, 1144 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1111 * CM_SSC_MODFREQDIV_DPLL_USB, CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, 1145 * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
1112 * CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, 1146 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1113 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, 1147 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
1114 * CM_SSC_MODFREQDIV_DPLL_MPU 1148 * CM_SSC_MODFREQDIV_DPLL_USB
1115 */ 1149 */
1116#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 1150#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1117#define OMAP4430_MODFREQDIV_MANTISSA_MASK BITFIELD(0, 6) 1151#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1118 1152
1119/* 1153/*
1120 * Used by PRM_PRM_PROFILING_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, 1154 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1121 * CM_WKUP_KEYBOARD_CLKCTRL, CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, 1155 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1122 * CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, 1156 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1123 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, 1157 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1124 * CM_WKUP_WDT2_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, 1158 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
1125 * CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, 1159 * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
1126 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, 1160 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
1127 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, 1161 * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
1128 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, 1162 * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
1129 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, 1163 * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
1130 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, 1164 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1131 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL, 1165 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1132 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1166 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1133 * CM_L4PER_ADC_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
1134 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
1135 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
1136 * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1137 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1138 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL,
1139 * CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1140 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1141 * CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
1142 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1143 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL,
1144 * CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL,
1145 * CM_L4PER_MSPROHG_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1146 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1147 * CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL,
1148 * CM_L4SEC_DES3DES_CLKCTRL, CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1149 * CM_L4SEC_SHA2MD51_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1150 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1167 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1151 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1168 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1152 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1169 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1153 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL, 1170 * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
1154 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL, 1171 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1155 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 1172 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1156 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, 1173 * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
1157 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, 1174 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
1158 * CM_L3INSTR_L3_3_CLKCTRL_RESTORE, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE, 1175 * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
1159 * CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1176 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
1160 * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1177 * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
1161 * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE, 1178 * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
1162 * CM_ALWON_MDMINTC_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, 1179 * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
1163 * CM_ALWON_SR_MPU_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, CM_IVAHD_SL2_CLKCTRL, 1180 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1164 * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_CM2_PROFILING_CLKCTRL, 1181 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1165 * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL, 1182 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1166 * CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, 1183 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1167 * CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL, 1184 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1168 * CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, CM1_ABE_TIMER5_CLKCTRL, 1185 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1169 * CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, 1186 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1170 * CM1_ABE_WDT3_CLKCTRL, CM_CM1_PROFILING_CLKCTRL 1187 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
1188 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
1189 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1190 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1191 * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
1192 * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
1193 * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1194 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
1195 * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
1196 * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1197 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1198 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1199 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1200 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
1201 * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1202 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1203 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
1204 * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
1205 * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1171 */ 1206 */
1172#define OMAP4430_MODULEMODE_SHIFT 0 1207#define OMAP4430_MODULEMODE_SHIFT 0
1173#define OMAP4430_MODULEMODE_MASK BITFIELD(0, 1) 1208#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1174 1209
1175/* Used by CM_DSS_DSS_CLKCTRL */ 1210/* Used by CM_DSS_DSS_CLKCTRL */
1176#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 1211#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1177#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK BITFIELD(9, 9) 1212#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1178 1213
1179/* Used by CM_WKUP_BANDGAP_CLKCTRL */ 1214/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1180#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 1215#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
1181#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK BITFIELD(8, 8) 1216#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8)
1182 1217
1183/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 1218/* Used by CM_ALWON_USBPHY_CLKCTRL */
1184#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 9 1219#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
1185#define OMAP4430_OPTFCLKEN_CLK32K_MASK BITFIELD(9, 9) 1220#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8)
1186 1221
1187/* Used by CM_CAM_ISS_CLKCTRL */ 1222/* Used by CM_CAM_ISS_CLKCTRL */
1188#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 1223#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
1189#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK BITFIELD(8, 8) 1224#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1190 1225
1191/* 1226/*
1192 * Used by CM_WKUP_GPIO1_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, 1227 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
1193 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, 1228 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
1194 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE, 1229 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
1195 * CM_L4PER_GPIO3_CLKCTRL_RESTORE, CM_L4PER_GPIO4_CLKCTRL_RESTORE, 1230 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
1196 * CM_L4PER_GPIO5_CLKCTRL_RESTORE, CM_L4PER_GPIO6_CLKCTRL_RESTORE 1231 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
1197 */ 1232 */
1198#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 1233#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1199#define OMAP4430_OPTFCLKEN_DBCLK_MASK BITFIELD(8, 8) 1234#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
1200 1235
1201/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ 1236/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1202#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 1237#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
1203#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK BITFIELD(8, 8) 1238#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1204 1239
1205/* Used by CM_DSS_DSS_CLKCTRL */ 1240/* Used by CM_DSS_DSS_CLKCTRL */
1206#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 1241#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
1207#define OMAP4430_OPTFCLKEN_DSSCLK_MASK BITFIELD(8, 8) 1242#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1243
1244/* Used by CM_WKUP_USIM_CLKCTRL */
1245#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
1246#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8)
1208 1247
1209/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1248/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1210#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 1249#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
1211#define OMAP4430_OPTFCLKEN_FCLK0_MASK BITFIELD(8, 8) 1250#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8)
1212 1251
1213/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1252/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1214#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 1253#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
1215#define OMAP4430_OPTFCLKEN_FCLK1_MASK BITFIELD(9, 9) 1254#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9)
1216 1255
1217/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1256/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1218#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 1257#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1219#define OMAP4430_OPTFCLKEN_FCLK2_MASK BITFIELD(10, 10) 1258#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1220 1259
1221/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1260/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1222#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 1261#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1223#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK BITFIELD(15, 15) 1262#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1224 1263
1225/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1264/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1226#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 1265#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1227#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK BITFIELD(13, 13) 1266#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1228 1267
1229/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1268/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1230#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 1269#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1231#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK BITFIELD(14, 14) 1270#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1232 1271
1233/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1272/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1234#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 1273#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1235#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK BITFIELD(11, 11) 1274#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1236 1275
1237/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1276/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1238#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 1277#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1239#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK BITFIELD(12, 12) 1278#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1240 1279
1241/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1280/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1242#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 1281#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
1243#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK BITFIELD(8, 8) 1282#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8)
1244 1283
1245/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1284/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1246#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 1285#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
1247#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK BITFIELD(9, 9) 1286#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9)
1248 1287
1249/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ 1288/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1250#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 1289#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
1251#define OMAP4430_OPTFCLKEN_PHY_48M_MASK BITFIELD(8, 8) 1290#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8)
1252 1291
1253/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ 1292/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1254#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 1293#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
1255#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK BITFIELD(10, 10) 1294#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10)
1256 1295
1257/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ 1296/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1258#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 1297#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
1259#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK BITFIELD(11, 11) 1298#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11)
1260 1299
1261/* Used by CM_DSS_DSS_CLKCTRL */ 1300/* Used by CM_DSS_DSS_CLKCTRL */
1262#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 1301#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1263#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK BITFIELD(10, 10) 1302#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1264 1303
1265/* Used by CM_DSS_DSS_CLKCTRL */ 1304/* Used by CM_DSS_DSS_CLKCTRL */
1266#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 1305#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1267#define OMAP4430_OPTFCLKEN_TV_CLK_MASK BITFIELD(11, 11) 1306#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
1268 1307
1269/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ 1308/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1270#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 1309#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1271#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK BITFIELD(8, 8) 1310#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1272 1311
1273/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1312/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1274#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 1313#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1275#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK BITFIELD(8, 8) 1314#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1276 1315
1277/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1316/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1278#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 1317#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1279#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK BITFIELD(9, 9) 1318#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1280 1319
1281/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */ 1320/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
1282#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 1321#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1283#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK BITFIELD(10, 10) 1322#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1284 1323
1285/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1324/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1286#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 1325#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1287#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK BITFIELD(8, 8) 1326#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1288 1327
1289/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1328/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1290#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 1329#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1291#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK BITFIELD(9, 9) 1330#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1292 1331
1293/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */ 1332/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
1294#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 1333#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1295#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK BITFIELD(10, 10) 1334#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1296 1335
1297/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ 1336/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1298#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 1337#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
1299#define OMAP4430_OPTFCLKEN_XCLK_MASK BITFIELD(8, 8) 1338#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8)
1300 1339
1301/* Used by CM_EMU_OVERRIDE_DPLL_PER, CM_EMU_OVERRIDE_DPLL_CORE */ 1340/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1302#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 1341#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
1303#define OMAP4430_OVERRIDE_ENABLE_MASK BITFIELD(19, 19) 1342#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19)
1304 1343
1305/* Used by CM_CLKSEL_ABE */ 1344/* Used by CM_CLKSEL_ABE */
1306#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 1345#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
1307#define OMAP4430_PAD_CLKS_GATE_MASK BITFIELD(8, 8) 1346#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8)
1308 1347
1309/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ 1348/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1310#define OMAP4430_PERF_CURRENT_SHIFT 0 1349#define OMAP4430_PERF_CURRENT_SHIFT 0
1311#define OMAP4430_PERF_CURRENT_MASK BITFIELD(0, 7) 1350#define OMAP4430_PERF_CURRENT_MASK (0xff << 0)
1312 1351
1313/* 1352/*
1314 * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, 1353 * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
@@ -1316,159 +1355,173 @@
1316 * CM_IVA_DVFS_PERF_TESLA 1355 * CM_IVA_DVFS_PERF_TESLA
1317 */ 1356 */
1318#define OMAP4430_PERF_REQ_SHIFT 0 1357#define OMAP4430_PERF_REQ_SHIFT 0
1319#define OMAP4430_PERF_REQ_MASK BITFIELD(0, 7) 1358#define OMAP4430_PERF_REQ_MASK (0xff << 0)
1320
1321/* Used by CM_EMU_OVERRIDE_DPLL_PER */
1322#define OMAP4430_PER_DPLL_EMU_DIV_SHIFT 0
1323#define OMAP4430_PER_DPLL_EMU_DIV_MASK BITFIELD(0, 6)
1324
1325/* Used by CM_EMU_OVERRIDE_DPLL_PER */
1326#define OMAP4430_PER_DPLL_EMU_MULT_SHIFT 8
1327#define OMAP4430_PER_DPLL_EMU_MULT_MASK BITFIELD(8, 18)
1328 1359
1329/* Used by CM_RESTORE_ST */ 1360/* Used by CM_RESTORE_ST */
1330#define OMAP4430_PHASE1_COMPLETED_SHIFT 0 1361#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
1331#define OMAP4430_PHASE1_COMPLETED_MASK BITFIELD(0, 0) 1362#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0)
1332 1363
1333/* Used by CM_RESTORE_ST */ 1364/* Used by CM_RESTORE_ST */
1334#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 1365#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
1335#define OMAP4430_PHASE2A_COMPLETED_MASK BITFIELD(1, 1) 1366#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1)
1336 1367
1337/* Used by CM_RESTORE_ST */ 1368/* Used by CM_RESTORE_ST */
1338#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 1369#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
1339#define OMAP4430_PHASE2B_COMPLETED_MASK BITFIELD(2, 2) 1370#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2)
1340 1371
1341/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1372/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1342#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 1373#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
1343#define OMAP4430_PMD_STM_MUX_CTRL_MASK BITFIELD(20, 21) 1374#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20)
1344 1375
1345/* Used by CM_EMU_DEBUGSS_CLKCTRL */ 1376/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1346#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 1377#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1347#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK BITFIELD(22, 23) 1378#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1348 1379
1349/* Used by CM_DYN_DEP_PRESCAL */ 1380/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
1350#define OMAP4430_PRESCAL_SHIFT 0 1381#define OMAP4430_PRESCAL_SHIFT 0
1351#define OMAP4430_PRESCAL_MASK BITFIELD(0, 5) 1382#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1352 1383
1353/* Used by REVISION_CM2, REVISION_CM1 */ 1384/* Used by REVISION_CM1, REVISION_CM2 */
1354#define OMAP4430_REV_SHIFT 0 1385#define OMAP4430_R_RTL_SHIFT 11
1355#define OMAP4430_REV_MASK BITFIELD(0, 7) 1386#define OMAP4430_R_RTL_MASK (0x1f << 11)
1356 1387
1357/* 1388/*
1358 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, 1389 * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1359 * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE 1390 * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
1360 */ 1391 */
1361#define OMAP4430_SAR_MODE_SHIFT 4 1392#define OMAP4430_SAR_MODE_SHIFT 4
1362#define OMAP4430_SAR_MODE_MASK BITFIELD(4, 4) 1393#define OMAP4430_SAR_MODE_MASK (1 << 4)
1363 1394
1364/* Used by CM_SCALE_FCLK */ 1395/* Used by CM_SCALE_FCLK */
1365#define OMAP4430_SCALE_FCLK_SHIFT 0 1396#define OMAP4430_SCALE_FCLK_SHIFT 0
1366#define OMAP4430_SCALE_FCLK_MASK BITFIELD(0, 0) 1397#define OMAP4430_SCALE_FCLK_MASK (1 << 0)
1398
1399/* Used by REVISION_CM1, REVISION_CM2 */
1400#define OMAP4430_SCHEME_SHIFT 30
1401#define OMAP4430_SCHEME_MASK (0x3 << 30)
1367 1402
1368/* Used by CM_L4CFG_DYNAMICDEP */ 1403/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1369#define OMAP4430_SDMA_DYNDEP_SHIFT 11 1404#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1370#define OMAP4430_SDMA_DYNDEP_MASK BITFIELD(11, 11) 1405#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1371 1406
1372/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1407/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1373#define OMAP4430_SDMA_STATDEP_SHIFT 11 1408#define OMAP4430_SDMA_STATDEP_SHIFT 11
1374#define OMAP4430_SDMA_STATDEP_MASK BITFIELD(11, 11) 1409#define OMAP4430_SDMA_STATDEP_MASK (1 << 11)
1375 1410
1376/* Used by CM_CLKSEL_ABE */ 1411/* Used by CM_CLKSEL_ABE */
1377#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 1412#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
1378#define OMAP4430_SLIMBUS_CLK_GATE_MASK BITFIELD(10, 10) 1413#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10)
1379 1414
1380/* 1415/*
1381 * Used by CM_EMU_DEBUGSS_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, 1416 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1382 * CM_DUCATI_DUCATI_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, CM_GFX_GFX_CLKCTRL, 1417 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1383 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL, 1418 * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
1419 * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
1384 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, 1420 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1385 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL, 1421 * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
1386 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL, 1422 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
1387 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, 1423 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
1388 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_CAM_FDIF_CLKCTRL, 1424 * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
1389 * CM_CAM_ISS_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, 1425 * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1390 * CM_IVAHD_IVAHD_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, 1426 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
1391 * CM_MPU_MPU_CLKCTRL, CM_TESLA_TESLA_CLKCTRL, CM1_ABE_AESS_CLKCTRL
1392 */ 1427 */
1393#define OMAP4430_STBYST_SHIFT 18 1428#define OMAP4430_STBYST_SHIFT 18
1394#define OMAP4430_STBYST_MASK BITFIELD(18, 18) 1429#define OMAP4430_STBYST_MASK (1 << 18)
1395 1430
1396/* 1431/*
1397 * Used by CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB, 1432 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1398 * CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, 1433 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1399 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU 1434 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1400 */ 1435 */
1401#define OMAP4430_ST_DPLL_CLK_SHIFT 0 1436#define OMAP4430_ST_DPLL_CLK_SHIFT 0
1402#define OMAP4430_ST_DPLL_CLK_MASK BITFIELD(0, 0) 1437#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
1403 1438
1404/* Used by CM_CLKDCOLDO_DPLL_USB */ 1439/* Used by CM_CLKDCOLDO_DPLL_USB */
1405#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 1440#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
1406#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK BITFIELD(9, 9) 1441#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1407 1442
1408/* 1443/*
1409 * Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB, CM_DIV_M2_DPLL_CORE_RESTORE, 1444 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
1410 * CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, 1445 * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
1411 * CM_DIV_M2_DPLL_MPU 1446 * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1412 */ 1447 */
1413#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 1448#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1414#define OMAP4430_ST_DPLL_CLKOUT_MASK BITFIELD(9, 9) 1449#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1415 1450
1416/* 1451/*
1417 * Used by CM_DIV_M3_DPLL_PER, CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_ABE, 1452 * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
1418 * CM_DIV_M3_DPLL_CORE 1453 * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
1419 */ 1454 */
1420#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 1455#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1421#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK BITFIELD(9, 9) 1456#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1422 1457
1423/* Used by CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO, CM_DIV_M2_DPLL_ABE */ 1458/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1424#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 1459#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
1425#define OMAP4430_ST_DPLL_CLKOUTX2_MASK BITFIELD(11, 11) 1460#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1426 1461
1427/* 1462/*
1428 * Used by CM_DIV_M4_DPLL_PER, CM_DIV_M4_DPLL_CORE_RESTORE, 1463 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
1429 * CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA 1464 * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
1430 */ 1465 */
1431#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 1466#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1432#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK BITFIELD(9, 9) 1467#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1433 1468
1434/* 1469/*
1435 * Used by CM_DIV_M5_DPLL_PER, CM_DIV_M5_DPLL_CORE_RESTORE, 1470 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
1436 * CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA 1471 * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
1437 */ 1472 */
1438#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 1473#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1439#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK BITFIELD(9, 9) 1474#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1440 1475
1441/* 1476/*
1442 * Used by CM_DIV_M6_DPLL_PER, CM_DIV_M6_DPLL_CORE_RESTORE, 1477 * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
1443 * CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY 1478 * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
1444 */ 1479 */
1445#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 1480#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1446#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK BITFIELD(9, 9) 1481#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1447 1482
1448/* 1483/*
1449 * Used by CM_DIV_M7_DPLL_PER, CM_DIV_M7_DPLL_CORE_RESTORE, 1484 * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
1450 * CM_DIV_M7_DPLL_CORE 1485 * CM_DIV_M7_DPLL_PER
1451 */ 1486 */
1452#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 1487#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1453#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK BITFIELD(9, 9) 1488#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1489
1490/*
1491 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1492 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1493 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1494 */
1495#define OMAP4430_ST_MN_BYPASS_SHIFT 8
1496#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8)
1454 1497
1455/* Used by CM_SYS_CLKSEL */ 1498/* Used by CM_SYS_CLKSEL */
1456#define OMAP4430_SYS_CLKSEL_SHIFT 0 1499#define OMAP4430_SYS_CLKSEL_SHIFT 0
1457#define OMAP4430_SYS_CLKSEL_MASK BITFIELD(0, 2) 1500#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1458 1501
1459/* Used by CM_L4CFG_DYNAMICDEP */ 1502/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
1460#define OMAP4430_TESLA_DYNDEP_SHIFT 1 1503#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1461#define OMAP4430_TESLA_DYNDEP_MASK BITFIELD(1, 1) 1504#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1462 1505
1463/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ 1506/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1464#define OMAP4430_TESLA_STATDEP_SHIFT 1 1507#define OMAP4430_TESLA_STATDEP_SHIFT 1
1465#define OMAP4430_TESLA_STATDEP_MASK BITFIELD(1, 1) 1508#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1466 1509
1467/* 1510/*
1468 * Used by CM_EMU_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, 1511 * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
1469 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, 1512 * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
1470 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP 1513 * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
1514 * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
1515 * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1471 */ 1516 */
1472#define OMAP4430_WINDOWSIZE_SHIFT 24 1517#define OMAP4430_WINDOWSIZE_SHIFT 24
1473#define OMAP4430_WINDOWSIZE_MASK BITFIELD(24, 27) 1518#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
1519
1520/* Used by REVISION_CM1, REVISION_CM2 */
1521#define OMAP4430_X_MAJOR_SHIFT 8
1522#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
1523
1524/* Used by REVISION_CM1, REVISION_CM2 */
1525#define OMAP4430_Y_MINOR_SHIFT 0
1526#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
1474#endif 1527#endif
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 336d94889e5b..3c35a87cb90c 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -195,6 +195,42 @@
195#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 195#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
196#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088) 196#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0088)
197 197
198/* CM1.RESTORE_CM1 register offsets */
199#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
200#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0000)
201#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
202#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0004)
203#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
204#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0008)
205#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
206#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x000c)
207#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
208#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0010)
209#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
210#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0014)
211#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
212#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0018)
213#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
214#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x001c)
215#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
216#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0020)
217#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
218#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0024)
219#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
220#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0028)
221#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
222#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x002c)
223#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
224#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0030)
225#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
226#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0034)
227#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
228#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0038)
229#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
230#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x003c)
231#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
232#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_MOD, 0x0040)
233
198/* CM2 */ 234/* CM2 */
199 235
200/* CM2.OCP_SOCKET_CM2 register offsets */ 236/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -252,8 +288,6 @@
252#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068) 288#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0068)
253#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c 289#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
254#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c) 290#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x006c)
255#define OMAP4_CM_EMU_OVERRIDE_DPLL_PER_OFFSET 0x0070
256#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0070)
257#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 291#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
258#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080) 292#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0080)
259#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 293#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@@ -296,6 +330,8 @@
296#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030) 330#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0030)
297#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 331#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038
298#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038) 332#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0038)
333#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040
334#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0040)
299 335
300/* CM2.CORE_CM2 register offsets */ 336/* CM2.CORE_CM2 register offsets */
301#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 337#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000
@@ -578,4 +614,54 @@
578#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000) 614#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0000)
579#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 615#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
580#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020) 616#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0020)
617
618/* CM2.RESTORE_CM2 register offsets */
619#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
620#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0000)
621#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
622#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0004)
623#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
624#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0008)
625#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
626#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x000c)
627#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
628#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0010)
629#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
630#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0014)
631#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
632#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0018)
633#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
634#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x001c)
635#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
636#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0020)
637#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
638#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0024)
639#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
640#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0028)
641#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
642#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x002c)
643#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
644#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0030)
645#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
646#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0034)
647#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
648#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0038)
649#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
650#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x003c)
651#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
652#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0040)
653#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
654#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0044)
655#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
656#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0048)
657#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
658#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x004c)
659#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
660#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0050)
661#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
662#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0054)
663#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
664#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x0058)
665#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
666#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_MOD, 0x005c)
581#endif 667#endif
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a8d20eef2306..8b3c469e7bcd 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -25,6 +25,7 @@
25#include "sdrc.h" 25#include "sdrc.h"
26 26
27static void __iomem *omap2_ctrl_base; 27static void __iomem *omap2_ctrl_base;
28static void __iomem *omap4_ctrl_pad_base;
28 29
29#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 30#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
30struct omap3_scratchpad { 31struct omap3_scratchpad {
@@ -137,6 +138,7 @@ static struct omap3_control_regs control_context;
137#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ 138#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */
138 139
139#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) 140#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
141#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg))
140 142
141void __init omap2_set_globals_control(struct omap_globals *omap2_globals) 143void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
142{ 144{
@@ -145,6 +147,12 @@ void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
145 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K); 147 omap2_ctrl_base = ioremap(omap2_globals->ctrl, SZ_4K);
146 WARN_ON(!omap2_ctrl_base); 148 WARN_ON(!omap2_ctrl_base);
147 } 149 }
150
151 /* Static mapping, never released */
152 if (omap2_globals->ctrl_pad) {
153 omap4_ctrl_pad_base = ioremap(omap2_globals->ctrl_pad, SZ_4K);
154 WARN_ON(!omap4_ctrl_pad_base);
155 }
148} 156}
149 157
150void __iomem *omap_ctrl_base_get(void) 158void __iomem *omap_ctrl_base_get(void)
@@ -182,6 +190,23 @@ void omap_ctrl_writel(u32 val, u16 offset)
182 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 190 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
183} 191}
184 192
193/*
194 * On OMAP4 control pad are not addressable from control
195 * core base. So the common omap_ctrl_read/write APIs breaks
196 * Hence export separate APIs to manage the omap4 pad control
197 * registers. This APIs will work only for OMAP4
198 */
199
200u32 omap4_ctrl_pad_readl(u16 offset)
201{
202 return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
203}
204
205void omap4_ctrl_pad_writel(u32 val, u16 offset)
206{
207 __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
208}
209
185#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 210#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
186/* 211/*
187 * Clears the scratchpad contents in case of cold boot- 212 * Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 87ce6ffccefc..eb92b8107d2c 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -135,10 +135,11 @@ static void omap4_hsmmc1_before_set_reg(struct device *dev, int slot,
135 * 135 *
136 * FIXME handle VMMC1A as needed ... 136 * FIXME handle VMMC1A as needed ...
137 */ 137 */
138 reg = omap_ctrl_readl(control_pbias_offset); 138 reg = omap4_ctrl_pad_readl(control_pbias_offset);
139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | 139 reg &= ~(OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
140 OMAP4_USBC1_ICUSB_PWRDNZ); 140 OMAP4_MMC1_PWRDNZ_MASK |
141 omap_ctrl_writel(reg, control_pbias_offset); 141 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
142 omap4_ctrl_pad_writel(reg, control_pbias_offset);
142} 143}
143 144
144static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot, 145static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
@@ -147,30 +148,33 @@ static void omap4_hsmmc1_after_set_reg(struct device *dev, int slot,
147 u32 reg; 148 u32 reg;
148 149
149 if (power_on) { 150 if (power_on) {
150 reg = omap_ctrl_readl(control_pbias_offset); 151 reg = omap4_ctrl_pad_readl(control_pbias_offset);
151 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ; 152 reg |= OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK;
152 if ((1 << vdd) <= MMC_VDD_165_195) 153 if ((1 << vdd) <= MMC_VDD_165_195)
153 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE; 154 reg &= ~OMAP4_MMC1_PBIASLITE_VMODE_MASK;
154 else 155 else
155 reg |= OMAP4_MMC1_PBIASLITE_VMODE; 156 reg |= OMAP4_MMC1_PBIASLITE_VMODE_MASK;
156 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | OMAP4_MMC1_PWRDNZ | 157 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
157 OMAP4_USBC1_ICUSB_PWRDNZ); 158 OMAP4_MMC1_PWRDNZ_MASK |
158 omap_ctrl_writel(reg, control_pbias_offset); 159 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
160 omap4_ctrl_pad_writel(reg, control_pbias_offset);
159 /* 4 microsec delay for comparator to generate an error*/ 161 /* 4 microsec delay for comparator to generate an error*/
160 udelay(4); 162 udelay(4);
161 reg = omap_ctrl_readl(control_pbias_offset); 163 reg = omap4_ctrl_pad_readl(control_pbias_offset);
162 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR) { 164 if (reg & OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK) {
163 pr_err("Pbias Voltage is not same as LDO\n"); 165 pr_err("Pbias Voltage is not same as LDO\n");
164 /* Caution : On VMODE_ERROR Power Down MMC IO */ 166 /* Caution : On VMODE_ERROR Power Down MMC IO */
165 reg &= ~(OMAP4_MMC1_PWRDNZ | OMAP4_USBC1_ICUSB_PWRDNZ); 167 reg &= ~(OMAP4_MMC1_PWRDNZ_MASK |
166 omap_ctrl_writel(reg, control_pbias_offset); 168 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
169 omap4_ctrl_pad_writel(reg, control_pbias_offset);
167 } 170 }
168 } else { 171 } else {
169 reg = omap_ctrl_readl(control_pbias_offset); 172 reg = omap4_ctrl_pad_readl(control_pbias_offset);
170 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ | 173 reg |= (OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK |
171 OMAP4_MMC1_PBIASLITE_VMODE | OMAP4_MMC1_PWRDNZ | 174 OMAP4_MMC1_PWRDNZ_MASK |
172 OMAP4_USBC1_ICUSB_PWRDNZ); 175 OMAP4_MMC1_PBIASLITE_VMODE_MASK |
173 omap_ctrl_writel(reg, control_pbias_offset); 176 OMAP4_USBC1_ICUSB_PWRDNZ_MASK);
177 omap4_ctrl_pad_writel(reg, control_pbias_offset);
174 } 178 }
175} 179}
176 180
@@ -218,17 +222,18 @@ void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
218 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
219 } 223 }
220 } else { 224 } else {
221 control_pbias_offset = OMAP44XX_CONTROL_PBIAS_LITE; 225 control_pbias_offset =
222 control_mmc1 = OMAP44XX_CONTROL_MMC1; 226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
223 reg = omap_ctrl_readl(control_mmc1); 227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
224 reg |= (OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 | 228 reg = omap4_ctrl_pad_readl(control_mmc1);
225 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1); 229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
226 reg &= ~(OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 | 230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
227 OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3); 231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
228 reg |= (OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL | 232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
229 OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL | 233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
230 OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL); 234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
231 omap_ctrl_writel(reg, control_mmc1); 235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
236 omap4_ctrl_pad_writel(reg, control_mmc1);
232 } 237 }
233 238
234 for (c = controllers; c->mmc; c++) { 239 for (c = controllers; c->mmc; c++) {
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 91d7df402b35..0412233da2b3 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -60,7 +60,7 @@ int omap_type(void)
60 } else if (cpu_is_omap34xx()) { 60 } else if (cpu_is_omap34xx()) {
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
62 } else if (cpu_is_omap44xx()) { 62 } else if (cpu_is_omap44xx()) {
63 val = omap_ctrl_readl(OMAP44XX_CONTROL_STATUS); 63 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
64 } else { 64 } else {
65 pr_err("Cannot detect omap type!\n"); 65 pr_err("Cannot detect omap type!\n");
66 goto out; 66 goto out;
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
new file mode 100644
index 000000000000..2f7ac70a20d8
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -0,0 +1,391 @@
1/*
2 * OMAP44xx CTRL_MODULE_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_CORE 0x4a002000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200
32#define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204
33#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208
34#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c
35#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210
36#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214
37#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218
38#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c
39#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228
40#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260
41#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264
42#define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268
43#define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4
44#define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300
45#define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314
46#define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318
47#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320
48#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324
49#define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328
50#define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c
51#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330
52#define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334
53#define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c
54#define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340
55#define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350
56#define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400
57#define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408
58#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c
59#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430
60#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434
61#define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438
62#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440
63#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444
64#define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448
65#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c
66#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450
67#define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454
68#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480
69#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484
70#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488
71#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c
72#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490
73#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494
74#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498
75#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c
76#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0
77#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4
78#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8
79#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac
80#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0
81#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4
82#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8
83#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc
84#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0
85#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4
86#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8
87#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc
88#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0
89#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4
90#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8
91#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc
92#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0
93#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4
94#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8
95#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec
96#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0
97#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4
98#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8
99#define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc
100
101/* Registers shifts and masks */
102
103/* IP_REVISION */
104#define OMAP4_IP_REV_SCHEME_SHIFT 30
105#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
106#define OMAP4_IP_REV_FUNC_SHIFT 16
107#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
108#define OMAP4_IP_REV_RTL_SHIFT 11
109#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
110#define OMAP4_IP_REV_MAJOR_SHIFT 8
111#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
112#define OMAP4_IP_REV_CUSTOM_SHIFT 6
113#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
114#define OMAP4_IP_REV_MINOR_SHIFT 0
115#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
116
117/* IP_HWINFO */
118#define OMAP4_IP_HWINFO_SHIFT 0
119#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
120
121/* IP_SYSCONFIG */
122#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
123#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
124
125/* STD_FUSE_DIE_ID_0 */
126#define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0
127#define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0)
128
129/* ID_CODE */
130#define OMAP4_STD_FUSE_IDCODE_SHIFT 0
131#define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0)
132
133/* STD_FUSE_DIE_ID_1 */
134#define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0
135#define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0)
136
137/* STD_FUSE_DIE_ID_2 */
138#define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0
139#define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0)
140
141/* STD_FUSE_DIE_ID_3 */
142#define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0
143#define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0)
144
145/* STD_FUSE_PROD_ID_0 */
146#define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0
147#define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0)
148
149/* STD_FUSE_PROD_ID_1 */
150#define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0
151#define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0)
152
153/* STD_FUSE_USB_CONF */
154#define OMAP4_USB_PROD_ID_SHIFT 16
155#define OMAP4_USB_PROD_ID_MASK (0xffff << 16)
156#define OMAP4_USB_VENDOR_ID_SHIFT 0
157#define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0)
158
159/* STD_FUSE_OPP_VDD_WKUP */
160#define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0
161#define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0)
162
163/* STD_FUSE_OPP_BGAP */
164#define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0
165#define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0)
166
167/* STD_FUSE_OPP_DPLL_0 */
168#define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0
169#define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0)
170
171/* STD_FUSE_OPP_DPLL_1 */
172#define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0
173#define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0)
174
175/* STATUS */
176#define OMAP4_ATTILA_CONF_SHIFT 11
177#define OMAP4_ATTILA_CONF_MASK (0x3 << 11)
178#define OMAP4_DEVICE_TYPE_SHIFT 8
179#define OMAP4_DEVICE_TYPE_MASK (0x7 << 8)
180#define OMAP4_SYS_BOOT_SHIFT 0
181#define OMAP4_SYS_BOOT_MASK (0xff << 0)
182
183/* DEV_CONF */
184#define OMAP4_DEV_CONF_SHIFT 1
185#define OMAP4_DEV_CONF_MASK (0x7fffffff << 1)
186#define OMAP4_USBPHY_PD_SHIFT 0
187#define OMAP4_USBPHY_PD_MASK (1 << 0)
188
189/* LDOVBB_IVA_VOLTAGE_CTRL */
190#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26
191#define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26)
192#define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21
193#define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21)
194#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16
195#define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16)
196#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10
197#define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10)
198#define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5
199#define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5)
200#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0
201#define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0)
202
203/* LDOVBB_MPU_VOLTAGE_CTRL */
204#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26
205#define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26)
206#define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21
207#define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21)
208#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16
209#define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16)
210#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10
211#define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10)
212#define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5
213#define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5)
214#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0
215#define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0)
216
217/* LDOSRAM_IVA_VOLTAGE_CTRL */
218#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26
219#define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26)
220#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21
221#define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21)
222#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16
223#define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16)
224#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10
225#define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10)
226#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5
227#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5)
228#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0
229#define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0)
230
231/* LDOSRAM_MPU_VOLTAGE_CTRL */
232#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26
233#define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26)
234#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21
235#define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21)
236#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16
237#define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16)
238#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10
239#define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10)
240#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5
241#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5)
242#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0
243#define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0)
244
245/* LDOSRAM_CORE_VOLTAGE_CTRL */
246#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26
247#define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26)
248#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21
249#define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21)
250#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16
251#define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16)
252#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10
253#define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10)
254#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5
255#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5)
256#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0
257#define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0)
258
259/* TEMP_SENSOR */
260#define OMAP4_BGAP_TEMPSOFF_SHIFT 12
261#define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12)
262#define OMAP4_BGAP_TSHUT_SHIFT 11
263#define OMAP4_BGAP_TSHUT_MASK (1 << 11)
264#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10
265#define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10)
266#define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9
267#define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9)
268#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8
269#define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8)
270#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0
271#define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0)
272
273/* DPLL_NWELL_TRIM_0 */
274#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29
275#define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
276#define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24
277#define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24)
278#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23
279#define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
280#define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18
281#define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18)
282#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17
283#define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
284#define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12
285#define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12)
286#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11
287#define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
288#define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6
289#define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6)
290#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5
291#define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
292#define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0
293#define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0)
294
295/* DPLL_NWELL_TRIM_1 */
296#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29
297#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29)
298#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24
299#define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24)
300#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23
301#define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23)
302#define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18
303#define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18)
304#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17
305#define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17)
306#define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12
307#define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12)
308#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11
309#define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11)
310#define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6
311#define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6)
312#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5
313#define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5)
314#define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0
315#define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0)
316
317/* USBOTGHS_CONTROL */
318#define OMAP4_DISCHRGVBUS_SHIFT 8
319#define OMAP4_DISCHRGVBUS_MASK (1 << 8)
320#define OMAP4_CHRGVBUS_SHIFT 7
321#define OMAP4_CHRGVBUS_MASK (1 << 7)
322#define OMAP4_DRVVBUS_SHIFT 6
323#define OMAP4_DRVVBUS_MASK (1 << 6)
324#define OMAP4_IDPULLUP_SHIFT 5
325#define OMAP4_IDPULLUP_MASK (1 << 5)
326#define OMAP4_IDDIG_SHIFT 4
327#define OMAP4_IDDIG_MASK (1 << 4)
328#define OMAP4_SESSEND_SHIFT 3
329#define OMAP4_SESSEND_MASK (1 << 3)
330#define OMAP4_VBUSVALID_SHIFT 2
331#define OMAP4_VBUSVALID_MASK (1 << 2)
332#define OMAP4_BVALID_SHIFT 1
333#define OMAP4_BVALID_MASK (1 << 1)
334#define OMAP4_AVALID_SHIFT 0
335#define OMAP4_AVALID_MASK (1 << 0)
336
337/* DSS_CONTROL */
338#define OMAP4_DSS_MUX6_SELECT_SHIFT 0
339#define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0)
340
341/* HWOBS_CONTROL */
342#define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3
343#define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3)
344#define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2
345#define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2)
346#define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1
347#define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1)
348#define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0
349#define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0)
350
351/* DEBOBS_FINAL_MUX_SEL */
352#define OMAP4_SELECT_SHIFT 0
353#define OMAP4_SELECT_MASK (0xffffffff << 0)
354
355/* DEBOBS_MMR_MPU */
356#define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0
357#define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0)
358
359/* CONF_SDMA_REQ_SEL0 */
360#define OMAP4_MULT_SHIFT 0
361#define OMAP4_MULT_MASK (0x7f << 0)
362
363/* CONF_CLK_SEL0 */
364#define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0
365#define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0)
366
367/* CONF_CLK_SEL1 */
368#define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0
369#define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0)
370
371/* CONF_CLK_SEL2 */
372#define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0
373#define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0)
374
375/* CONF_DPLL_FREQLOCK_SEL */
376#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0
377#define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0)
378
379/* CONF_DPLL_TINITZ_SEL */
380#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0
381#define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0)
382
383/* CONF_DPLL_PHASELOCK_SEL */
384#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0
385#define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0)
386
387/* CONF_DEBUG_SEL_TST_0 */
388#define OMAP4_MODE_SHIFT 0
389#define OMAP4_MODE_MASK (0xf << 0)
390
391#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
new file mode 100644
index 000000000000..c88420de1151
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -0,0 +1,1409 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8
32#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc
33#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0
34#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4
35#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8
36#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec
37#define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0
38#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0
39#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4
40#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8
41#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac
42#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0
43#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4
44#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8
45#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc
46#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0
47#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4
48#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8
49#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600
50#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604
51#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608
52#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c
53#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610
54#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614
55#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618
56#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c
57#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620
58#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624
59#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628
60#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c
61#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630
62#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634
63#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638
64#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c
65#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640
66#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644
67#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648
68#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c
69#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650
70#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654
71#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658
72#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c
73#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660
74#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664
75#define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668
76#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700
77#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704
78#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708
79#define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c
80
81/* Registers shifts and masks */
82
83/* IP_REVISION */
84#define OMAP4_IP_REV_SCHEME_SHIFT 30
85#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
86#define OMAP4_IP_REV_FUNC_SHIFT 16
87#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
88#define OMAP4_IP_REV_RTL_SHIFT 11
89#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
90#define OMAP4_IP_REV_MAJOR_SHIFT 8
91#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
92#define OMAP4_IP_REV_CUSTOM_SHIFT 6
93#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
94#define OMAP4_IP_REV_MINOR_SHIFT 0
95#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
96
97/* IP_HWINFO */
98#define OMAP4_IP_HWINFO_SHIFT 0
99#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
100
101/* IP_SYSCONFIG */
102#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
103#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
104
105/* PADCONF_WAKEUPEVENT_0 */
106#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31
107#define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
108#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30
109#define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
110#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29
111#define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
112#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28
113#define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
114#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27
115#define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
116#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26
117#define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
118#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25
119#define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
120#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24
121#define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
122#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23
123#define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
124#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22
125#define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
126#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21
127#define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
128#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20
129#define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
130#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19
131#define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
132#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18
133#define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
134#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17
135#define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
136#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16
137#define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
138#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15
139#define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
140#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14
141#define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
142#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13
143#define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
144#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12
145#define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
146#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11
147#define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
148#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10
149#define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
150#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9
151#define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
152#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8
153#define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
154#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7
155#define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
156#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6
157#define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
158#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5
159#define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
160#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4
161#define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
162#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3
163#define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
164#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2
165#define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
166#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1
167#define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
168#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0
169#define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
170
171/* PADCONF_WAKEUPEVENT_1 */
172#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31
173#define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
174#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30
175#define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
176#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29
177#define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
178#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28
179#define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
180#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27
181#define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
182#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26
183#define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
184#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25
185#define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
186#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24
187#define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
188#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23
189#define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
190#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22
191#define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
192#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21
193#define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
194#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20
195#define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
196#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19
197#define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
198#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18
199#define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
200#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17
201#define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
202#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16
203#define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
204#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15
205#define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
206#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14
207#define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
208#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13
209#define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
210#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12
211#define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
212#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11
213#define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
214#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10
215#define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
216#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9
217#define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
218#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8
219#define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
220#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7
221#define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
222#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6
223#define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
224#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5
225#define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
226#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4
227#define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
228#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3
229#define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
230#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2
231#define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
232#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1
233#define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
234#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0
235#define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
236
237/* PADCONF_WAKEUPEVENT_2 */
238#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31
239#define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
240#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30
241#define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
242#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29
243#define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
244#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28
245#define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
246#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27
247#define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
248#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26
249#define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
250#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25
251#define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
252#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24
253#define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
254#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23
255#define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
256#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22
257#define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
258#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21
259#define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
260#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20
261#define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
262#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19
263#define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
264#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18
265#define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
266#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17
267#define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
268#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16
269#define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
270#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15
271#define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
272#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14
273#define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
274#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13
275#define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
276#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12
277#define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
278#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11
279#define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
280#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10
281#define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
282#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9
283#define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
284#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8
285#define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
286#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7
287#define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
288#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6
289#define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
290#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5
291#define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
292#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4
293#define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
294#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3
295#define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
296#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2
297#define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
298#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
299#define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
300#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0
301#define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
302
303/* PADCONF_WAKEUPEVENT_3 */
304#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31
305#define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
306#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30
307#define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
308#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29
309#define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
310#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28
311#define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
312#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27
313#define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
314#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26
315#define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
316#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25
317#define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
318#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24
319#define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
320#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23
321#define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
322#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22
323#define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
324#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21
325#define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
326#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20
327#define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
328#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19
329#define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
330#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18
331#define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
332#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17
333#define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
334#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16
335#define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
336#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
337#define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
338#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
339#define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
340#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13
341#define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
342#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12
343#define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
344#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11
345#define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
346#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10
347#define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
348#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9
349#define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
350#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8
351#define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
352#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7
353#define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
354#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6
355#define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
356#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5
357#define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
358#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4
359#define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
360#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3
361#define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
362#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2
363#define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
364#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1
365#define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
366#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0
367#define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
368
369/* PADCONF_WAKEUPEVENT_4 */
370#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31
371#define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
372#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30
373#define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
374#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29
375#define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
376#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28
377#define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
378#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27
379#define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
380#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26
381#define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
382#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25
383#define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
384#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24
385#define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
386#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23
387#define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
388#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22
389#define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
390#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21
391#define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
392#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20
393#define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
394#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19
395#define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
396#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18
397#define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
398#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17
399#define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
400#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16
401#define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
402#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15
403#define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
404#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14
405#define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
406#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13
407#define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
408#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12
409#define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
410#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11
411#define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
412#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10
413#define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
414#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9
415#define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
416#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8
417#define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
418#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7
419#define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
420#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6
421#define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
422#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5
423#define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
424#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4
425#define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
426#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3
427#define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
428#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2
429#define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
430#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1
431#define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
432#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0
433#define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
434
435/* PADCONF_WAKEUPEVENT_5 */
436#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31
437#define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31)
438#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30
439#define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30)
440#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29
441#define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29)
442#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28
443#define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28)
444#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27
445#define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27)
446#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26
447#define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26)
448#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25
449#define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25)
450#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24
451#define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
452#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23
453#define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
454#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22
455#define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
456#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21
457#define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
458#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20
459#define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
460#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19
461#define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
462#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18
463#define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
464#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17
465#define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
466#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16
467#define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
468#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15
469#define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
470#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14
471#define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
472#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13
473#define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
474#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12
475#define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
476#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11
477#define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
478#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
479#define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
480#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9
481#define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
482#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8
483#define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
484#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7
485#define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
486#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6
487#define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
488#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5
489#define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
490#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4
491#define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
492#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3
493#define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
494#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2
495#define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
496#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1
497#define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
498#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0
499#define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
500
501/* PADCONF_WAKEUPEVENT_6 */
502#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7
503#define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
504#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6
505#define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
506#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5
507#define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
508#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4
509#define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
510#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3
511#define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
512#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2
513#define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
514#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1
515#define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
516#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0
517#define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
518
519/* CONTROL_PADCONF_GLOBAL */
520#define OMAP4_FORCE_OFFMODE_EN_SHIFT 31
521#define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31)
522
523/* CONTROL_PADCONF_MODE */
524#define OMAP4_VDDS_DV_BANK0_SHIFT 31
525#define OMAP4_VDDS_DV_BANK0_MASK (1 << 31)
526#define OMAP4_VDDS_DV_BANK1_SHIFT 30
527#define OMAP4_VDDS_DV_BANK1_MASK (1 << 30)
528#define OMAP4_VDDS_DV_BANK3_SHIFT 29
529#define OMAP4_VDDS_DV_BANK3_MASK (1 << 29)
530#define OMAP4_VDDS_DV_BANK4_SHIFT 28
531#define OMAP4_VDDS_DV_BANK4_MASK (1 << 28)
532#define OMAP4_VDDS_DV_BANK5_SHIFT 27
533#define OMAP4_VDDS_DV_BANK5_MASK (1 << 27)
534#define OMAP4_VDDS_DV_BANK6_SHIFT 26
535#define OMAP4_VDDS_DV_BANK6_MASK (1 << 26)
536#define OMAP4_VDDS_DV_C2C_SHIFT 25
537#define OMAP4_VDDS_DV_C2C_MASK (1 << 25)
538#define OMAP4_VDDS_DV_CAM_SHIFT 24
539#define OMAP4_VDDS_DV_CAM_MASK (1 << 24)
540#define OMAP4_VDDS_DV_GPMC_SHIFT 23
541#define OMAP4_VDDS_DV_GPMC_MASK (1 << 23)
542#define OMAP4_VDDS_DV_SDMMC2_SHIFT 22
543#define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22)
544
545/* CONTROL_SMART1IO_PADCONF_0 */
546#define OMAP4_ABE_DR0_SC_SHIFT 30
547#define OMAP4_ABE_DR0_SC_MASK (0x3 << 30)
548#define OMAP4_CAM_DR0_SC_SHIFT 28
549#define OMAP4_CAM_DR0_SC_MASK (0x3 << 28)
550#define OMAP4_FREF_DR2_SC_SHIFT 26
551#define OMAP4_FREF_DR2_SC_MASK (0x3 << 26)
552#define OMAP4_FREF_DR3_SC_SHIFT 24
553#define OMAP4_FREF_DR3_SC_MASK (0x3 << 24)
554#define OMAP4_GPIO_DR8_SC_SHIFT 22
555#define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22)
556#define OMAP4_GPIO_DR9_SC_SHIFT 20
557#define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20)
558#define OMAP4_GPMC_DR2_SC_SHIFT 18
559#define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18)
560#define OMAP4_GPMC_DR3_SC_SHIFT 16
561#define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16)
562#define OMAP4_GPMC_DR6_SC_SHIFT 14
563#define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14)
564#define OMAP4_HDMI_DR0_SC_SHIFT 12
565#define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12)
566#define OMAP4_MCSPI1_DR0_SC_SHIFT 10
567#define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10)
568#define OMAP4_UART1_DR0_SC_SHIFT 8
569#define OMAP4_UART1_DR0_SC_MASK (0x3 << 8)
570#define OMAP4_UART3_DR0_SC_SHIFT 6
571#define OMAP4_UART3_DR0_SC_MASK (0x3 << 6)
572#define OMAP4_UART3_DR1_SC_SHIFT 4
573#define OMAP4_UART3_DR1_SC_MASK (0x3 << 4)
574#define OMAP4_UNIPRO_DR0_SC_SHIFT 2
575#define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2)
576#define OMAP4_UNIPRO_DR1_SC_SHIFT 0
577#define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0)
578
579/* CONTROL_SMART1IO_PADCONF_1 */
580#define OMAP4_ABE_DR0_LB_SHIFT 30
581#define OMAP4_ABE_DR0_LB_MASK (0x3 << 30)
582#define OMAP4_CAM_DR0_LB_SHIFT 28
583#define OMAP4_CAM_DR0_LB_MASK (0x3 << 28)
584#define OMAP4_FREF_DR2_LB_SHIFT 26
585#define OMAP4_FREF_DR2_LB_MASK (0x3 << 26)
586#define OMAP4_FREF_DR3_LB_SHIFT 24
587#define OMAP4_FREF_DR3_LB_MASK (0x3 << 24)
588#define OMAP4_GPIO_DR8_LB_SHIFT 22
589#define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22)
590#define OMAP4_GPIO_DR9_LB_SHIFT 20
591#define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20)
592#define OMAP4_GPMC_DR2_LB_SHIFT 18
593#define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18)
594#define OMAP4_GPMC_DR3_LB_SHIFT 16
595#define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16)
596#define OMAP4_GPMC_DR6_LB_SHIFT 14
597#define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14)
598#define OMAP4_HDMI_DR0_LB_SHIFT 12
599#define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12)
600#define OMAP4_MCSPI1_DR0_LB_SHIFT 10
601#define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10)
602#define OMAP4_UART1_DR0_LB_SHIFT 8
603#define OMAP4_UART1_DR0_LB_MASK (0x3 << 8)
604#define OMAP4_UART3_DR0_LB_SHIFT 6
605#define OMAP4_UART3_DR0_LB_MASK (0x3 << 6)
606#define OMAP4_UART3_DR1_LB_SHIFT 4
607#define OMAP4_UART3_DR1_LB_MASK (0x3 << 4)
608#define OMAP4_UNIPRO_DR0_LB_SHIFT 2
609#define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2)
610#define OMAP4_UNIPRO_DR1_LB_SHIFT 0
611#define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0)
612
613/* CONTROL_SMART2IO_PADCONF_0 */
614#define OMAP4_C2C_DR0_LB_SHIFT 31
615#define OMAP4_C2C_DR0_LB_MASK (1 << 31)
616#define OMAP4_DPM_DR1_LB_SHIFT 30
617#define OMAP4_DPM_DR1_LB_MASK (1 << 30)
618#define OMAP4_DPM_DR2_LB_SHIFT 29
619#define OMAP4_DPM_DR2_LB_MASK (1 << 29)
620#define OMAP4_DPM_DR3_LB_SHIFT 28
621#define OMAP4_DPM_DR3_LB_MASK (1 << 28)
622#define OMAP4_GPIO_DR0_LB_SHIFT 27
623#define OMAP4_GPIO_DR0_LB_MASK (1 << 27)
624#define OMAP4_GPIO_DR1_LB_SHIFT 26
625#define OMAP4_GPIO_DR1_LB_MASK (1 << 26)
626#define OMAP4_GPIO_DR10_LB_SHIFT 25
627#define OMAP4_GPIO_DR10_LB_MASK (1 << 25)
628#define OMAP4_GPIO_DR2_LB_SHIFT 24
629#define OMAP4_GPIO_DR2_LB_MASK (1 << 24)
630#define OMAP4_GPMC_DR0_LB_SHIFT 23
631#define OMAP4_GPMC_DR0_LB_MASK (1 << 23)
632#define OMAP4_GPMC_DR1_LB_SHIFT 22
633#define OMAP4_GPMC_DR1_LB_MASK (1 << 22)
634#define OMAP4_GPMC_DR4_LB_SHIFT 21
635#define OMAP4_GPMC_DR4_LB_MASK (1 << 21)
636#define OMAP4_GPMC_DR5_LB_SHIFT 20
637#define OMAP4_GPMC_DR5_LB_MASK (1 << 20)
638#define OMAP4_GPMC_DR7_LB_SHIFT 19
639#define OMAP4_GPMC_DR7_LB_MASK (1 << 19)
640#define OMAP4_HSI2_DR0_LB_SHIFT 18
641#define OMAP4_HSI2_DR0_LB_MASK (1 << 18)
642#define OMAP4_HSI2_DR1_LB_SHIFT 17
643#define OMAP4_HSI2_DR1_LB_MASK (1 << 17)
644#define OMAP4_HSI2_DR2_LB_SHIFT 16
645#define OMAP4_HSI2_DR2_LB_MASK (1 << 16)
646#define OMAP4_KPD_DR0_LB_SHIFT 15
647#define OMAP4_KPD_DR0_LB_MASK (1 << 15)
648#define OMAP4_KPD_DR1_LB_SHIFT 14
649#define OMAP4_KPD_DR1_LB_MASK (1 << 14)
650#define OMAP4_PDM_DR0_LB_SHIFT 13
651#define OMAP4_PDM_DR0_LB_MASK (1 << 13)
652#define OMAP4_SDMMC2_DR0_LB_SHIFT 12
653#define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12)
654#define OMAP4_SDMMC3_DR0_LB_SHIFT 11
655#define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11)
656#define OMAP4_SDMMC4_DR0_LB_SHIFT 10
657#define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10)
658#define OMAP4_SDMMC4_DR1_LB_SHIFT 9
659#define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9)
660#define OMAP4_SPI3_DR0_LB_SHIFT 8
661#define OMAP4_SPI3_DR0_LB_MASK (1 << 8)
662#define OMAP4_SPI3_DR1_LB_SHIFT 7
663#define OMAP4_SPI3_DR1_LB_MASK (1 << 7)
664#define OMAP4_UART3_DR2_LB_SHIFT 6
665#define OMAP4_UART3_DR2_LB_MASK (1 << 6)
666#define OMAP4_UART3_DR3_LB_SHIFT 5
667#define OMAP4_UART3_DR3_LB_MASK (1 << 5)
668#define OMAP4_UART3_DR4_LB_SHIFT 4
669#define OMAP4_UART3_DR4_LB_MASK (1 << 4)
670#define OMAP4_UART3_DR5_LB_SHIFT 3
671#define OMAP4_UART3_DR5_LB_MASK (1 << 3)
672#define OMAP4_USBA0_DR1_LB_SHIFT 2
673#define OMAP4_USBA0_DR1_LB_MASK (1 << 2)
674#define OMAP4_USBA_DR2_LB_SHIFT 1
675#define OMAP4_USBA_DR2_LB_MASK (1 << 1)
676
677/* CONTROL_SMART2IO_PADCONF_1 */
678#define OMAP4_USBB1_DR0_LB_SHIFT 31
679#define OMAP4_USBB1_DR0_LB_MASK (1 << 31)
680#define OMAP4_USBB2_DR0_LB_SHIFT 30
681#define OMAP4_USBB2_DR0_LB_MASK (1 << 30)
682#define OMAP4_USBA0_DR0_LB_SHIFT 29
683#define OMAP4_USBA0_DR0_LB_MASK (1 << 29)
684
685/* CONTROL_SMART3IO_PADCONF_0 */
686#define OMAP4_DMIC_DR0_MB_SHIFT 30
687#define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30)
688#define OMAP4_GPIO_DR3_MB_SHIFT 28
689#define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28)
690#define OMAP4_GPIO_DR4_MB_SHIFT 26
691#define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26)
692#define OMAP4_GPIO_DR5_MB_SHIFT 24
693#define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24)
694#define OMAP4_GPIO_DR6_MB_SHIFT 22
695#define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22)
696#define OMAP4_HSI_DR1_MB_SHIFT 20
697#define OMAP4_HSI_DR1_MB_MASK (0x3 << 20)
698#define OMAP4_HSI_DR2_MB_SHIFT 18
699#define OMAP4_HSI_DR2_MB_MASK (0x3 << 18)
700#define OMAP4_HSI_DR3_MB_SHIFT 16
701#define OMAP4_HSI_DR3_MB_MASK (0x3 << 16)
702#define OMAP4_MCBSP2_DR0_MB_SHIFT 14
703#define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14)
704#define OMAP4_MCSPI4_DR0_MB_SHIFT 12
705#define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12)
706#define OMAP4_MCSPI4_DR1_MB_SHIFT 10
707#define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10)
708#define OMAP4_SDMMC3_DR0_MB_SHIFT 8
709#define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8)
710#define OMAP4_SPI2_DR0_MB_SHIFT 0
711#define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0)
712
713/* CONTROL_SMART3IO_PADCONF_1 */
714#define OMAP4_SPI2_DR1_MB_SHIFT 30
715#define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30)
716#define OMAP4_SPI2_DR2_MB_SHIFT 28
717#define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28)
718#define OMAP4_UART2_DR0_MB_SHIFT 26
719#define OMAP4_UART2_DR0_MB_MASK (0x3 << 26)
720#define OMAP4_UART2_DR1_MB_SHIFT 24
721#define OMAP4_UART2_DR1_MB_MASK (0x3 << 24)
722#define OMAP4_UART4_DR0_MB_SHIFT 22
723#define OMAP4_UART4_DR0_MB_MASK (0x3 << 22)
724#define OMAP4_HSI_DR0_MB_SHIFT 20
725#define OMAP4_HSI_DR0_MB_MASK (0x3 << 20)
726
727/* CONTROL_SMART3IO_PADCONF_2 */
728#define OMAP4_DMIC_DR0_LB_SHIFT 31
729#define OMAP4_DMIC_DR0_LB_MASK (1 << 31)
730#define OMAP4_GPIO_DR3_LB_SHIFT 30
731#define OMAP4_GPIO_DR3_LB_MASK (1 << 30)
732#define OMAP4_GPIO_DR4_LB_SHIFT 29
733#define OMAP4_GPIO_DR4_LB_MASK (1 << 29)
734#define OMAP4_GPIO_DR5_LB_SHIFT 28
735#define OMAP4_GPIO_DR5_LB_MASK (1 << 28)
736#define OMAP4_GPIO_DR6_LB_SHIFT 27
737#define OMAP4_GPIO_DR6_LB_MASK (1 << 27)
738#define OMAP4_HSI_DR1_LB_SHIFT 26
739#define OMAP4_HSI_DR1_LB_MASK (1 << 26)
740#define OMAP4_HSI_DR2_LB_SHIFT 25
741#define OMAP4_HSI_DR2_LB_MASK (1 << 25)
742#define OMAP4_HSI_DR3_LB_SHIFT 24
743#define OMAP4_HSI_DR3_LB_MASK (1 << 24)
744#define OMAP4_MCBSP2_DR0_LB_SHIFT 23
745#define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23)
746#define OMAP4_MCSPI4_DR0_LB_SHIFT 22
747#define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22)
748#define OMAP4_MCSPI4_DR1_LB_SHIFT 21
749#define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21)
750#define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18
751#define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18)
752#define OMAP4_SPI2_DR0_LB_SHIFT 16
753#define OMAP4_SPI2_DR0_LB_MASK (1 << 16)
754#define OMAP4_SPI2_DR1_LB_SHIFT 15
755#define OMAP4_SPI2_DR1_LB_MASK (1 << 15)
756#define OMAP4_SPI2_DR2_LB_SHIFT 14
757#define OMAP4_SPI2_DR2_LB_MASK (1 << 14)
758#define OMAP4_UART2_DR0_LB_SHIFT 13
759#define OMAP4_UART2_DR0_LB_MASK (1 << 13)
760#define OMAP4_UART2_DR1_LB_SHIFT 12
761#define OMAP4_UART2_DR1_LB_MASK (1 << 12)
762#define OMAP4_UART4_DR0_LB_SHIFT 11
763#define OMAP4_UART4_DR0_LB_MASK (1 << 11)
764#define OMAP4_HSI_DR0_LB_SHIFT 10
765#define OMAP4_HSI_DR0_LB_MASK (1 << 10)
766
767/* CONTROL_USBB_HSIC */
768#define OMAP4_USBB2_DR1_SR_SHIFT 30
769#define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30)
770#define OMAP4_USBB2_DR1_I_SHIFT 27
771#define OMAP4_USBB2_DR1_I_MASK (0x7 << 27)
772#define OMAP4_USBB1_DR1_SR_SHIFT 25
773#define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25)
774#define OMAP4_USBB1_DR1_I_SHIFT 22
775#define OMAP4_USBB1_DR1_I_MASK (0x7 << 22)
776#define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20
777#define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20)
778#define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18
779#define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18)
780#define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16
781#define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16)
782#define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14
783#define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14)
784#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13
785#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13)
786#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11
787#define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11)
788#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10
789#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10)
790#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8
791#define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8)
792#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7
793#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7)
794#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5
795#define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5)
796#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4
797#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4)
798#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2
799#define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2)
800
801/* CONTROL_SLIMBUS */
802#define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30
803#define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30)
804#define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28
805#define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28)
806#define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26
807#define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26)
808#define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24
809#define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24)
810#define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22
811#define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22)
812#define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20
813#define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20)
814#define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19
815#define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19)
816#define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18
817#define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18)
818
819/* CONTROL_PBIASLITE */
820#define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31
821#define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31)
822#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30
823#define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30)
824#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29
825#define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29)
826#define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28
827#define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28)
828#define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27
829#define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27)
830#define OMAP4_MMC1_PWRDNZ_SHIFT 26
831#define OMAP4_MMC1_PWRDNZ_MASK (1 << 26)
832#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25
833#define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25)
834#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24
835#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24)
836#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23
837#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23)
838#define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22
839#define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22)
840#define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21
841#define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21)
842#define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20
843#define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20)
844
845/* CONTROL_I2C_0 */
846#define OMAP4_I2C4_SDA_GLFENB_SHIFT 31
847#define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31)
848#define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29
849#define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29)
850#define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28
851#define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28)
852#define OMAP4_I2C3_SDA_GLFENB_SHIFT 27
853#define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27)
854#define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25
855#define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25)
856#define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24
857#define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24)
858#define OMAP4_I2C2_SDA_GLFENB_SHIFT 23
859#define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23)
860#define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21
861#define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21)
862#define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20
863#define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20)
864#define OMAP4_I2C1_SDA_GLFENB_SHIFT 19
865#define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19)
866#define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17
867#define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17)
868#define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16
869#define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16)
870#define OMAP4_I2C4_SCL_GLFENB_SHIFT 15
871#define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15)
872#define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13
873#define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13)
874#define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12
875#define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12)
876#define OMAP4_I2C3_SCL_GLFENB_SHIFT 11
877#define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11)
878#define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9
879#define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9)
880#define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8
881#define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8)
882#define OMAP4_I2C2_SCL_GLFENB_SHIFT 7
883#define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7)
884#define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5
885#define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5)
886#define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4
887#define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4)
888#define OMAP4_I2C1_SCL_GLFENB_SHIFT 3
889#define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3)
890#define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1
891#define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1)
892#define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0
893#define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0)
894
895/* CONTROL_CAMERA_RX */
896#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31
897#define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31)
898#define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29
899#define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29)
900#define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24
901#define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24)
902#define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22
903#define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22)
904#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21
905#define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21)
906#define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19
907#define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19)
908#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18
909#define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18)
910#define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16
911#define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16)
912
913/* CONTROL_AVDAC */
914#define OMAP4_AVDAC_ACEN_SHIFT 31
915#define OMAP4_AVDAC_ACEN_MASK (1 << 31)
916#define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30
917#define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30)
918#define OMAP4_AVDAC_INPUTINV_SHIFT 29
919#define OMAP4_AVDAC_INPUTINV_MASK (1 << 29)
920#define OMAP4_AVDAC_CTL_SHIFT 13
921#define OMAP4_AVDAC_CTL_MASK (0xffff << 13)
922#define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12
923#define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12)
924
925/* CONTROL_HDMI_TX_PHY */
926#define OMAP4_HDMITXPHY_PADORDER_SHIFT 31
927#define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31)
928#define OMAP4_HDMITXPHY_TXVALID_SHIFT 30
929#define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30)
930#define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29
931#define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29)
932#define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28
933#define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28)
934
935/* CONTROL_MMC2 */
936#define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31
937#define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31)
938
939/* CONTROL_DSIPHY */
940#define OMAP4_DSI2_LANEENABLE_SHIFT 29
941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
942#define OMAP4_DSI1_LANEENABLE_SHIFT 24
943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
944#define OMAP4_DSI1_PIPD_SHIFT 19
945#define OMAP4_DSI1_PIPD_MASK (0x1f << 19)
946#define OMAP4_DSI2_PIPD_SHIFT 14
947#define OMAP4_DSI2_PIPD_MASK (0x1f << 14)
948
949/* CONTROL_MCBSPLP */
950#define OMAP4_ALBCTRLRX_FSX_SHIFT 31
951#define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31)
952#define OMAP4_ALBCTRLRX_CLKX_SHIFT 30
953#define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30)
954#define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29
955#define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29)
956
957/* CONTROL_USB2PHYCORE */
958#define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31
959#define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31)
960#define OMAP4_USB2PHY_DISCHGDET_SHIFT 30
961#define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30)
962#define OMAP4_USB2PHY_GPIOMODE_SHIFT 29
963#define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29)
964#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28
965#define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28)
966#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27
967#define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27)
968#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26
969#define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26)
970#define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25
971#define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25)
972#define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24
973#define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24)
974#define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21
975#define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21)
976#define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20
977#define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20)
978#define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19
979#define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19)
980#define OMAP4_USB2PHY_DATADET_SHIFT 18
981#define OMAP4_USB2PHY_DATADET_MASK (1 << 18)
982#define OMAP4_USB2PHY_SINKONDP_SHIFT 17
983#define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17)
984#define OMAP4_USB2PHY_SRCONDM_SHIFT 16
985#define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16)
986#define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15
987#define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15)
988#define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14
989#define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14)
990#define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13
991#define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13)
992#define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12
993#define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12)
994#define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11
995#define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11)
996#define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10
997#define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10)
998#define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9
999#define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9)
1000#define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8
1001#define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8)
1002#define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7
1003#define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7)
1004#define OMAP4_USBDPLL_FREQLOCK_SHIFT 6
1005#define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6)
1006#define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5
1007#define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5)
1008
1009/* CONTROL_I2C_1 */
1010#define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31
1011#define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31)
1012#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29
1013#define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29)
1014#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28
1015#define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28)
1016#define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27
1017#define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27)
1018#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25
1019#define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25)
1020#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24
1021#define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24)
1022#define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23
1023#define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23)
1024#define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22
1025#define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22)
1026#define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21
1027#define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21)
1028#define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20
1029#define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20)
1030
1031/* CONTROL_MMC1 */
1032#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31
1033#define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31)
1034#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30
1035#define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30)
1036#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29
1037#define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29)
1038#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28
1039#define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28)
1040#define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27
1041#define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27)
1042#define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26
1043#define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26)
1044#define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25
1045#define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25)
1046#define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24
1047#define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24)
1048#define OMAP4_USB_FD_CDEN_SHIFT 23
1049#define OMAP4_USB_FD_CDEN_MASK (1 << 23)
1050#define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22
1051#define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22)
1052#define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21
1053#define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21)
1054
1055/* CONTROL_HSI */
1056#define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31
1057#define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31)
1058#define OMAP4_HSI1_CALMUX_SEL_SHIFT 30
1059#define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30)
1060#define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29
1061#define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29)
1062#define OMAP4_HSI2_CALMUX_SEL_SHIFT 28
1063#define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28)
1064
1065/* CONTROL_USB */
1066#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31
1067#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31)
1068#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30
1069#define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30)
1070
1071/* CONTROL_HDQ */
1072#define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31
1073#define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31)
1074
1075/* CONTROL_LPDDR2IO1_0 */
1076#define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30
1077#define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30)
1078#define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27
1079#define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27)
1080#define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25
1081#define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25)
1082#define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22
1083#define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22)
1084#define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19
1085#define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19)
1086#define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17
1087#define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17)
1088#define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14
1089#define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14)
1090#define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11
1091#define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11)
1092#define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9
1093#define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9)
1094#define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6
1095#define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6)
1096#define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3
1097#define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3)
1098#define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1
1099#define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1)
1100
1101/* CONTROL_LPDDR2IO1_1 */
1102#define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30
1103#define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30)
1104#define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27
1105#define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27)
1106#define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25
1107#define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25)
1108#define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22
1109#define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22)
1110#define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19
1111#define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19)
1112#define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17
1113#define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17)
1114#define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14
1115#define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14)
1116#define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11
1117#define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11)
1118#define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9
1119#define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9)
1120#define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6
1121#define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6)
1122#define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3
1123#define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3)
1124#define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1
1125#define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1)
1126
1127/* CONTROL_LPDDR2IO1_2 */
1128#define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30
1129#define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30)
1130#define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27
1131#define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27)
1132#define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25
1133#define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25)
1134#define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22
1135#define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22)
1136#define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19
1137#define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19)
1138#define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17
1139#define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17)
1140#define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14
1141#define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14)
1142#define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11
1143#define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11)
1144#define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9
1145#define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9)
1146
1147/* CONTROL_LPDDR2IO1_3 */
1148#define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31
1149#define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31)
1150#define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30
1151#define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30)
1152#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29
1153#define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29)
1154#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28
1155#define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28)
1156#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27
1157#define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27)
1158#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26
1159#define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26)
1160#define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25
1161#define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25)
1162#define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24
1163#define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24)
1164#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23
1165#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1166#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22
1167#define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1168#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21
1169#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1170#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20
1171#define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1172#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19
1173#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1174#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18
1175#define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1176#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17
1177#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1178#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16
1179#define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1180#define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15
1181#define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15)
1182#define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14
1183#define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14)
1184#define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13
1185#define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13)
1186#define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12
1187#define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12)
1188
1189/* CONTROL_LPDDR2IO2_0 */
1190#define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30
1191#define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30)
1192#define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27
1193#define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27)
1194#define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25
1195#define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25)
1196#define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22
1197#define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22)
1198#define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19
1199#define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19)
1200#define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17
1201#define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17)
1202#define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14
1203#define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14)
1204#define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11
1205#define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11)
1206#define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9
1207#define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9)
1208#define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6
1209#define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6)
1210#define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3
1211#define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3)
1212#define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1
1213#define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1)
1214
1215/* CONTROL_LPDDR2IO2_1 */
1216#define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30
1217#define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30)
1218#define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27
1219#define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27)
1220#define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25
1221#define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25)
1222#define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22
1223#define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22)
1224#define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19
1225#define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19)
1226#define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17
1227#define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17)
1228#define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14
1229#define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14)
1230#define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11
1231#define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11)
1232#define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9
1233#define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9)
1234#define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6
1235#define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6)
1236#define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3
1237#define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3)
1238#define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1
1239#define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1)
1240
1241/* CONTROL_LPDDR2IO2_2 */
1242#define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30
1243#define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30)
1244#define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27
1245#define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27)
1246#define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25
1247#define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25)
1248#define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22
1249#define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22)
1250#define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19
1251#define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19)
1252#define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17
1253#define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17)
1254#define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14
1255#define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14)
1256#define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11
1257#define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11)
1258#define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9
1259#define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9)
1260
1261/* CONTROL_LPDDR2IO2_3 */
1262#define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31
1263#define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31)
1264#define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30
1265#define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30)
1266#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29
1267#define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29)
1268#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28
1269#define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28)
1270#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27
1271#define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27)
1272#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26
1273#define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26)
1274#define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25
1275#define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25)
1276#define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24
1277#define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24)
1278#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23
1279#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23)
1280#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22
1281#define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22)
1282#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21
1283#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21)
1284#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20
1285#define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20)
1286#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19
1287#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19)
1288#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18
1289#define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18)
1290#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17
1291#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17)
1292#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16
1293#define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16)
1294#define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15
1295#define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15)
1296#define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14
1297#define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14)
1298#define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13
1299#define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13)
1300#define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12
1301#define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12)
1302
1303/* CONTROL_BUS_HOLD */
1304#define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31
1305#define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31)
1306#define OMAP4_MCSPI1_CS3_EN_SHIFT 30
1307#define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30)
1308
1309/* CONTROL_C2C */
1310#define OMAP4_MIRROR_MODE_EN_SHIFT 31
1311#define OMAP4_MIRROR_MODE_EN_MASK (1 << 31)
1312#define OMAP4_C2C_SPARE_SHIFT 24
1313#define OMAP4_C2C_SPARE_MASK (0x7f << 24)
1314
1315/* CORE_CONTROL_SPARE_RW */
1316#define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0
1317#define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
1318
1319/* CORE_CONTROL_SPARE_R */
1320#define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0
1321#define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0)
1322
1323/* CORE_CONTROL_SPARE_R_C0 */
1324#define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31
1325#define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31)
1326#define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30
1327#define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30)
1328#define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29
1329#define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29)
1330#define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28
1331#define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28)
1332#define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27
1333#define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27)
1334#define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26
1335#define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26)
1336#define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25
1337#define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25)
1338#define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24
1339#define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24)
1340
1341/* CONTROL_EFUSE_1 */
1342#define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24
1343#define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24)
1344#define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16
1345#define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16)
1346#define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8
1347#define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8)
1348#define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0
1349#define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0)
1350
1351/* CONTROL_EFUSE_2 */
1352#define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31
1353#define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31)
1354#define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30
1355#define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30)
1356#define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29
1357#define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29)
1358#define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28
1359#define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28)
1360#define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27
1361#define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27)
1362#define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26
1363#define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26)
1364#define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25
1365#define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25)
1366#define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24
1367#define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24)
1368#define OMAP4_LPDDR2_PTV_N1_SHIFT 23
1369#define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23)
1370#define OMAP4_LPDDR2_PTV_N2_SHIFT 22
1371#define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22)
1372#define OMAP4_LPDDR2_PTV_N3_SHIFT 21
1373#define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21)
1374#define OMAP4_LPDDR2_PTV_N4_SHIFT 20
1375#define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20)
1376#define OMAP4_LPDDR2_PTV_N5_SHIFT 19
1377#define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19)
1378#define OMAP4_LPDDR2_PTV_P1_SHIFT 18
1379#define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18)
1380#define OMAP4_LPDDR2_PTV_P2_SHIFT 17
1381#define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17)
1382#define OMAP4_LPDDR2_PTV_P3_SHIFT 16
1383#define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16)
1384#define OMAP4_LPDDR2_PTV_P4_SHIFT 15
1385#define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15)
1386#define OMAP4_LPDDR2_PTV_P5_SHIFT 14
1387#define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14)
1388
1389/* CONTROL_EFUSE_3 */
1390#define OMAP4_STD_FUSE_SPARE_1_SHIFT 24
1391#define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24)
1392#define OMAP4_STD_FUSE_SPARE_2_SHIFT 16
1393#define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16)
1394#define OMAP4_STD_FUSE_SPARE_3_SHIFT 8
1395#define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8)
1396#define OMAP4_STD_FUSE_SPARE_4_SHIFT 0
1397#define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0)
1398
1399/* CONTROL_EFUSE_4 */
1400#define OMAP4_STD_FUSE_SPARE_5_SHIFT 24
1401#define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24)
1402#define OMAP4_STD_FUSE_SPARE_6_SHIFT 16
1403#define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16)
1404#define OMAP4_STD_FUSE_SPARE_7_SHIFT 8
1405#define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8)
1406#define OMAP4_STD_FUSE_SPARE_8_SHIFT 0
1407#define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0)
1408
1409#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
new file mode 100644
index 000000000000..17c9b37042c0
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_wkup_44xx.h
@@ -0,0 +1,236 @@
1/*
2 * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c
32#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0
33#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4
34#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8
35#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac
36#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600
37#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604
38#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608
39#define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c
40#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614
41#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618
42#define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c
43
44/* Registers shifts and masks */
45
46/* IP_REVISION */
47#define OMAP4_IP_REV_SCHEME_SHIFT 30
48#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
49#define OMAP4_IP_REV_FUNC_SHIFT 16
50#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
51#define OMAP4_IP_REV_RTL_SHIFT 11
52#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
53#define OMAP4_IP_REV_MAJOR_SHIFT 8
54#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
55#define OMAP4_IP_REV_CUSTOM_SHIFT 6
56#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
57#define OMAP4_IP_REV_MINOR_SHIFT 0
58#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
59
60/* IP_HWINFO */
61#define OMAP4_IP_HWINFO_SHIFT 0
62#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
63
64/* IP_SYSCONFIG */
65#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
66#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
67
68/* PADCONF_WAKEUPEVENT_0 */
69#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24
70#define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24)
71#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23
72#define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23)
73#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22
74#define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22)
75#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21
76#define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21)
77#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20
78#define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20)
79#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19
80#define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19)
81#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18
82#define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18)
83#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17
84#define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17)
85#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16
86#define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16)
87#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15
88#define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15)
89#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14
90#define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14)
91#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13
92#define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13)
93#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12
94#define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12)
95#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11
96#define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11)
97#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10
98#define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10)
99#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9
100#define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9)
101#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8
102#define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8)
103#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7
104#define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7)
105#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6
106#define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6)
107#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5
108#define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5)
109#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4
110#define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4)
111#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3
112#define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3)
113#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2
114#define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2)
115#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1
116#define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1)
117#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0
118#define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0)
119
120/* CONTROL_SMART1NOPMIO_PADCONF_0 */
121#define OMAP4_FREF_DR0_SC_SHIFT 30
122#define OMAP4_FREF_DR0_SC_MASK (0x3 << 30)
123#define OMAP4_FREF_DR1_SC_SHIFT 28
124#define OMAP4_FREF_DR1_SC_MASK (0x3 << 28)
125#define OMAP4_FREF_DR4_SC_SHIFT 26
126#define OMAP4_FREF_DR4_SC_MASK (0x3 << 26)
127#define OMAP4_FREF_DR5_SC_SHIFT 24
128#define OMAP4_FREF_DR5_SC_MASK (0x3 << 24)
129#define OMAP4_FREF_DR6_SC_SHIFT 22
130#define OMAP4_FREF_DR6_SC_MASK (0x3 << 22)
131#define OMAP4_FREF_DR7_SC_SHIFT 20
132#define OMAP4_FREF_DR7_SC_MASK (0x3 << 20)
133#define OMAP4_GPIO_DR7_SC_SHIFT 18
134#define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18)
135#define OMAP4_DPM_DR0_SC_SHIFT 14
136#define OMAP4_DPM_DR0_SC_MASK (0x3 << 14)
137#define OMAP4_SIM_DR0_SC_SHIFT 12
138#define OMAP4_SIM_DR0_SC_MASK (0x3 << 12)
139
140/* CONTROL_SMART1NOPMIO_PADCONF_1 */
141#define OMAP4_FREF_DR0_LB_SHIFT 30
142#define OMAP4_FREF_DR0_LB_MASK (0x3 << 30)
143#define OMAP4_FREF_DR1_LB_SHIFT 28
144#define OMAP4_FREF_DR1_LB_MASK (0x3 << 28)
145#define OMAP4_FREF_DR4_LB_SHIFT 26
146#define OMAP4_FREF_DR4_LB_MASK (0x3 << 26)
147#define OMAP4_FREF_DR5_LB_SHIFT 24
148#define OMAP4_FREF_DR5_LB_MASK (0x3 << 24)
149#define OMAP4_FREF_DR6_LB_SHIFT 22
150#define OMAP4_FREF_DR6_LB_MASK (0x3 << 22)
151#define OMAP4_FREF_DR7_LB_SHIFT 20
152#define OMAP4_FREF_DR7_LB_MASK (0x3 << 20)
153#define OMAP4_GPIO_DR7_LB_SHIFT 18
154#define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18)
155#define OMAP4_DPM_DR0_LB_SHIFT 14
156#define OMAP4_DPM_DR0_LB_MASK (0x3 << 14)
157#define OMAP4_SIM_DR0_LB_SHIFT 12
158#define OMAP4_SIM_DR0_LB_MASK (0x3 << 12)
159
160/* CONTROL_PADCONF_MODE */
161#define OMAP4_VDDS_DV_FREF_SHIFT 31
162#define OMAP4_VDDS_DV_FREF_MASK (1 << 31)
163#define OMAP4_VDDS_DV_BANK2_SHIFT 30
164#define OMAP4_VDDS_DV_BANK2_MASK (1 << 30)
165
166/* CONTROL_XTAL_OSCILLATOR */
167#define OMAP4_OSCILLATOR_BOOST_SHIFT 31
168#define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31)
169#define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30
170#define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30)
171
172/* CONTROL_USIMIO */
173#define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31
174#define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31)
175#define OMAP4_PAD_USIM_RST_LOW_SHIFT 29
176#define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29)
177#define OMAP4_USIM_PWRDNZ_SHIFT 28
178#define OMAP4_USIM_PWRDNZ_MASK (1 << 28)
179
180/* CONTROL_I2C_2 */
181#define OMAP4_SR_SDA_GLFENB_SHIFT 31
182#define OMAP4_SR_SDA_GLFENB_MASK (1 << 31)
183#define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29
184#define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29)
185#define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28
186#define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28)
187#define OMAP4_SR_SCL_GLFENB_SHIFT 27
188#define OMAP4_SR_SCL_GLFENB_MASK (1 << 27)
189#define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25
190#define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25)
191#define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24
192#define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24)
193
194/* CONTROL_JTAG */
195#define OMAP4_JTAG_NTRST_EN_SHIFT 31
196#define OMAP4_JTAG_NTRST_EN_MASK (1 << 31)
197#define OMAP4_JTAG_TCK_EN_SHIFT 30
198#define OMAP4_JTAG_TCK_EN_MASK (1 << 30)
199#define OMAP4_JTAG_RTCK_EN_SHIFT 29
200#define OMAP4_JTAG_RTCK_EN_MASK (1 << 29)
201#define OMAP4_JTAG_TDI_EN_SHIFT 28
202#define OMAP4_JTAG_TDI_EN_MASK (1 << 28)
203#define OMAP4_JTAG_TDO_EN_SHIFT 27
204#define OMAP4_JTAG_TDO_EN_MASK (1 << 27)
205
206/* CONTROL_SYS */
207#define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31
208#define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31)
209
210/* WKUP_CONTROL_SPARE_RW */
211#define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0
212#define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0)
213
214/* WKUP_CONTROL_SPARE_R */
215#define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0
216#define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0)
217
218/* WKUP_CONTROL_SPARE_R_C0 */
219#define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31
220#define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31)
221#define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30
222#define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30)
223#define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29
224#define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29)
225#define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28
226#define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28)
227#define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27
228#define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27)
229#define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26
230#define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26)
231#define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25
232#define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25)
233#define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24
234#define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24)
235
236#endif
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
new file mode 100644
index 000000000000..a0af9baec3f7
--- /dev/null
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_wkup_44xx.h
@@ -0,0 +1,92 @@
1/*
2 * OMAP44xx CTRL_MODULE_WKUP registers and bitfields
3 *
4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 *
6 * Benoit Cousson (b-cousson@ti.com)
7 * Santosh Shilimkar (santosh.shilimkar@ti.com)
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
21#define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_WKUP_44XX_H
22
23
24/* Base address */
25#define OMAP4_CTRL_MODULE_WKUP 0x4a30c000
26
27/* Registers offset */
28#define OMAP4_CTRL_MODULE_WKUP_IP_REVISION 0x0000
29#define OMAP4_CTRL_MODULE_WKUP_IP_HWINFO 0x0004
30#define OMAP4_CTRL_MODULE_WKUP_IP_SYSCONFIG 0x0010
31#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_0 0x0460
32#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_1 0x0464
33#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_2 0x0468
34#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_3 0x046c
35#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_4 0x0470
36#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_5 0x0474
37#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_6 0x0478
38#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_7 0x047c
39#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_8 0x0480
40#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_9 0x0484
41#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_10 0x0488
42#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_11 0x048c
43#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_12 0x0490
44#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_13 0x0494
45#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_14 0x0498
46#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_15 0x049c
47#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_16 0x04a0
48#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_17 0x04a4
49#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_18 0x04a8
50#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_19 0x04ac
51#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_20 0x04b0
52#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_21 0x04b4
53#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_22 0x04b8
54#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_23 0x04bc
55#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_24 0x04c0
56#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_25 0x04c4
57#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_26 0x04c8
58#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_27 0x04cc
59#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_28 0x04d0
60#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_29 0x04d4
61#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_30 0x04d8
62#define OMAP4_CTRL_MODULE_WKUP_CONF_DEBUG_SEL_TST_31 0x04dc
63
64/* Registers shifts and masks */
65
66/* IP_REVISION */
67#define OMAP4_IP_REV_SCHEME_SHIFT 30
68#define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30)
69#define OMAP4_IP_REV_FUNC_SHIFT 16
70#define OMAP4_IP_REV_FUNC_MASK (0xfff << 16)
71#define OMAP4_IP_REV_RTL_SHIFT 11
72#define OMAP4_IP_REV_RTL_MASK (0x1f << 11)
73#define OMAP4_IP_REV_MAJOR_SHIFT 8
74#define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8)
75#define OMAP4_IP_REV_CUSTOM_SHIFT 6
76#define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6)
77#define OMAP4_IP_REV_MINOR_SHIFT 0
78#define OMAP4_IP_REV_MINOR_MASK (0x3f << 0)
79
80/* IP_HWINFO */
81#define OMAP4_IP_HWINFO_SHIFT 0
82#define OMAP4_IP_HWINFO_MASK (0xffffffff << 0)
83
84/* IP_SYSCONFIG */
85#define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2
86#define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2)
87
88/* CONF_DEBUG_SEL_TST_0 */
89#define OMAP4_WKUP_MODE_SHIFT 0
90#define OMAP4_WKUP_MODE_MASK (1 << 0)
91
92#endif
diff --git a/arch/arm/mach-omap2/powerdomains44xx.h b/arch/arm/mach-omap2/powerdomains44xx.h
index c7219513472a..9c01b55d6102 100644
--- a/arch/arm/mach-omap2/powerdomains44xx.h
+++ b/arch/arm/mach-omap2/powerdomains44xx.h
@@ -98,7 +98,7 @@ static struct powerdomain dss_44xx_pwrdm = {
98 .prcm_offs = OMAP4430_PRM_DSS_MOD, 98 .prcm_offs = OMAP4430_PRM_DSS_MOD,
99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), 99 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
100 .pwrsts = PWRSTS_OFF_RET_ON, 100 .pwrsts = PWRSTS_OFF_RET_ON,
101 .pwrsts_logic_ret = PWRSTS_OFF_RET, 101 .pwrsts_logic_ret = PWRSTS_OFF,
102 .banks = 1, 102 .banks = 1,
103 .pwrsts_mem_ret = { 103 .pwrsts_mem_ret = {
104 [0] = PWRDM_POWER_OFF, /* dss_mem */ 104 [0] = PWRDM_POWER_OFF, /* dss_mem */
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 597be4a2b9ff..25b19b610177 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -1,8 +1,8 @@
1/* 1/*
2 * OMAP44xx Power Management register bits 2 * OMAP44xx Power Management register bits
3 * 3 *
4 * Copyright (C) 2009 Texas Instruments, Inc. 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009 Nokia Corporation 5 * Copyright (C) 2009-2010 Nokia Corporation
6 * 6 *
7 * Paul Walmsley (paul@pwsan.com) 7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com) 8 * Rajendra Nayak (rnayak@ti.com)
@@ -30,587 +30,611 @@
30 * PRM_LDO_SRAM_MPU_SETUP 30 * PRM_LDO_SRAM_MPU_SETUP
31 */ 31 */
32#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 32#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
33#define OMAP4430_ABBOFF_ACT_EXPORT_MASK BITFIELD(1, 1) 33#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1)
34 34
35/* 35/*
36 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 36 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
37 * PRM_LDO_SRAM_MPU_SETUP 37 * PRM_LDO_SRAM_MPU_SETUP
38 */ 38 */
39#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 39#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
40#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK BITFIELD(2, 2) 40#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
41 41
42/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 42/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
43#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 43#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
44#define OMAP4430_ABB_IVA_DONE_EN_MASK BITFIELD(31, 31) 44#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31)
45 45
46/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 46/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
47#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 47#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
48#define OMAP4430_ABB_IVA_DONE_ST_MASK BITFIELD(31, 31) 48#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31)
49 49
50/* Used by PRM_IRQENABLE_MPU_2 */ 50/* Used by PRM_IRQENABLE_MPU_2 */
51#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 51#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
52#define OMAP4430_ABB_MPU_DONE_EN_MASK BITFIELD(7, 7) 52#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7)
53 53
54/* Used by PRM_IRQSTATUS_MPU_2 */ 54/* Used by PRM_IRQSTATUS_MPU_2 */
55#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 55#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
56#define OMAP4430_ABB_MPU_DONE_ST_MASK BITFIELD(7, 7) 56#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7)
57 57
58/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 58/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
59#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 59#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
60#define OMAP4430_ACTIVE_FBB_SEL_MASK BITFIELD(2, 2) 60#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2)
61 61
62/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 62/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
63#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 63#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
64#define OMAP4430_ACTIVE_RBB_SEL_MASK BITFIELD(1, 1) 64#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1)
65 65
66/* Used by PM_ABE_PWRSTCTRL */ 66/* Used by PM_ABE_PWRSTCTRL */
67#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 67#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
68#define OMAP4430_AESSMEM_ONSTATE_MASK BITFIELD(16, 17) 68#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16)
69 69
70/* Used by PM_ABE_PWRSTCTRL */ 70/* Used by PM_ABE_PWRSTCTRL */
71#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 71#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
72#define OMAP4430_AESSMEM_RETSTATE_MASK BITFIELD(8, 8) 72#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8)
73 73
74/* Used by PM_ABE_PWRSTST */ 74/* Used by PM_ABE_PWRSTST */
75#define OMAP4430_AESSMEM_STATEST_SHIFT 4 75#define OMAP4430_AESSMEM_STATEST_SHIFT 4
76#define OMAP4430_AESSMEM_STATEST_MASK BITFIELD(4, 5) 76#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4)
77 77
78/* 78/*
79 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 79 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
80 * PRM_LDO_SRAM_MPU_SETUP 80 * PRM_LDO_SRAM_MPU_SETUP
81 */ 81 */
82#define OMAP4430_AIPOFF_SHIFT 8 82#define OMAP4430_AIPOFF_SHIFT 8
83#define OMAP4430_AIPOFF_MASK BITFIELD(8, 8) 83#define OMAP4430_AIPOFF_MASK (1 << 8)
84 84
85/* Used by PRM_VOLTCTRL */ 85/* Used by PRM_VOLTCTRL */
86#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 86#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
87#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK BITFIELD(0, 1) 87#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
88 88
89/* Used by PRM_VOLTCTRL */ 89/* Used by PRM_VOLTCTRL */
90#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 90#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
91#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK BITFIELD(4, 5) 91#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4)
92 92
93/* Used by PRM_VOLTCTRL */ 93/* Used by PRM_VOLTCTRL */
94#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 94#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
95#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK BITFIELD(2, 3) 95#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
96
97/* Used by PRM_VC_ERRST */
98#define OMAP4430_BYPS_RA_ERR_SHIFT 25
99#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25)
100
101/* Used by PRM_VC_ERRST */
102#define OMAP4430_BYPS_SA_ERR_SHIFT 24
103#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24)
104
105/* Used by PRM_VC_ERRST */
106#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26
107#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26)
108
109/* Used by PRM_RSTST */
110#define OMAP4430_C2C_RST_SHIFT 10
111#define OMAP4430_C2C_RST_MASK (1 << 10)
96 112
97/* Used by PM_CAM_PWRSTCTRL */ 113/* Used by PM_CAM_PWRSTCTRL */
98#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 114#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
99#define OMAP4430_CAM_MEM_ONSTATE_MASK BITFIELD(16, 17) 115#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16)
100 116
101/* Used by PM_CAM_PWRSTST */ 117/* Used by PM_CAM_PWRSTST */
102#define OMAP4430_CAM_MEM_STATEST_SHIFT 4 118#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
103#define OMAP4430_CAM_MEM_STATEST_MASK BITFIELD(4, 5) 119#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4)
104 120
105/* Used by PRM_CLKREQCTRL */ 121/* Used by PRM_CLKREQCTRL */
106#define OMAP4430_CLKREQ_COND_SHIFT 0 122#define OMAP4430_CLKREQ_COND_SHIFT 0
107#define OMAP4430_CLKREQ_COND_MASK BITFIELD(0, 2) 123#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0)
108 124
109/* Used by PRM_VC_VAL_SMPS_RA_CMD */ 125/* Used by PRM_VC_VAL_SMPS_RA_CMD */
110#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 126#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
111#define OMAP4430_CMDRA_VDD_CORE_L_MASK BITFIELD(0, 7) 127#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
112 128
113/* Used by PRM_VC_VAL_SMPS_RA_CMD */ 129/* Used by PRM_VC_VAL_SMPS_RA_CMD */
114#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 130#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
115#define OMAP4430_CMDRA_VDD_IVA_L_MASK BITFIELD(8, 15) 131#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
116 132
117/* Used by PRM_VC_VAL_SMPS_RA_CMD */ 133/* Used by PRM_VC_VAL_SMPS_RA_CMD */
118#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 134#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
119#define OMAP4430_CMDRA_VDD_MPU_L_MASK BITFIELD(16, 23) 135#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
120 136
121/* Used by PRM_VC_CFG_CHANNEL */ 137/* Used by PRM_VC_CFG_CHANNEL */
122#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 138#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
123#define OMAP4430_CMD_VDD_CORE_L_MASK BITFIELD(4, 4) 139#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
124 140
125/* Used by PRM_VC_CFG_CHANNEL */ 141/* Used by PRM_VC_CFG_CHANNEL */
126#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 142#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
127#define OMAP4430_CMD_VDD_IVA_L_MASK BITFIELD(12, 12) 143#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
128 144
129/* Used by PRM_VC_CFG_CHANNEL */ 145/* Used by PRM_VC_CFG_CHANNEL */
130#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 146#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
131#define OMAP4430_CMD_VDD_MPU_L_MASK BITFIELD(17, 17) 147#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
132 148
133/* Used by PM_CORE_PWRSTCTRL */ 149/* Used by PM_CORE_PWRSTCTRL */
134#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 150#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
135#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK BITFIELD(18, 19) 151#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
136 152
137/* Used by PM_CORE_PWRSTCTRL */ 153/* Used by PM_CORE_PWRSTCTRL */
138#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 154#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
139#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK BITFIELD(9, 9) 155#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
140 156
141/* Used by PM_CORE_PWRSTST */ 157/* Used by PM_CORE_PWRSTST */
142#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 158#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
143#define OMAP4430_CORE_OCMRAM_STATEST_MASK BITFIELD(6, 7) 159#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
144 160
145/* Used by PM_CORE_PWRSTCTRL */ 161/* Used by PM_CORE_PWRSTCTRL */
146#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 162#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
147#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK BITFIELD(16, 17) 163#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
148 164
149/* Used by PM_CORE_PWRSTCTRL */ 165/* Used by PM_CORE_PWRSTCTRL */
150#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 166#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
151#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK BITFIELD(8, 8) 167#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
152 168
153/* Used by PM_CORE_PWRSTST */ 169/* Used by PM_CORE_PWRSTST */
154#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 170#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
155#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK BITFIELD(4, 5) 171#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
172
173/* Used by REVISION_PRM */
174#define OMAP4430_CUSTOM_SHIFT 6
175#define OMAP4430_CUSTOM_MASK (0x3 << 6)
156 176
157/* Used by PRM_VC_VAL_BYPASS */ 177/* Used by PRM_VC_VAL_BYPASS */
158#define OMAP4430_DATA_SHIFT 16 178#define OMAP4430_DATA_SHIFT 16
159#define OMAP4430_DATA_MASK BITFIELD(16, 23) 179#define OMAP4430_DATA_MASK (0xff << 16)
160 180
161/* Used by PRM_DEVICE_OFF_CTRL */ 181/* Used by PRM_DEVICE_OFF_CTRL */
162#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 182#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
163#define OMAP4430_DEVICE_OFF_ENABLE_MASK BITFIELD(0, 0) 183#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
164 184
165/* Used by PRM_VC_CFG_I2C_MODE */ 185/* Used by PRM_VC_CFG_I2C_MODE */
166#define OMAP4430_DFILTEREN_SHIFT 6 186#define OMAP4430_DFILTEREN_SHIFT 6
167#define OMAP4430_DFILTEREN_MASK BITFIELD(6, 6) 187#define OMAP4430_DFILTEREN_MASK (1 << 6)
168 188
169/* Used by PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 189/*
190 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
191 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
192 */
193#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
194#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
195
196/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
170#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 197#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
171#define OMAP4430_DPLL_ABE_RECAL_EN_MASK BITFIELD(4, 4) 198#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
172 199
173/* Used by PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 200/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
174#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 201#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
175#define OMAP4430_DPLL_ABE_RECAL_ST_MASK BITFIELD(4, 4) 202#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
176 203
177/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 204/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
178#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 205#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
179#define OMAP4430_DPLL_CORE_RECAL_EN_MASK BITFIELD(0, 0) 206#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
180 207
181/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 208/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
182#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 209#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
183#define OMAP4430_DPLL_CORE_RECAL_ST_MASK BITFIELD(0, 0) 210#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
184 211
185/* Used by PRM_IRQENABLE_MPU */ 212/* Used by PRM_IRQENABLE_MPU */
186#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 213#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
187#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK BITFIELD(6, 6) 214#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
188 215
189/* Used by PRM_IRQSTATUS_MPU */ 216/* Used by PRM_IRQSTATUS_MPU */
190#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 217#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
191#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK BITFIELD(6, 6) 218#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
192 219
193/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ 220/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
194#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 221#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
195#define OMAP4430_DPLL_IVA_RECAL_EN_MASK BITFIELD(2, 2) 222#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
196 223
197/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ 224/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
198#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 225#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
199#define OMAP4430_DPLL_IVA_RECAL_ST_MASK BITFIELD(2, 2) 226#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
200 227
201/* Used by PRM_IRQENABLE_MPU */ 228/* Used by PRM_IRQENABLE_MPU */
202#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 229#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
203#define OMAP4430_DPLL_MPU_RECAL_EN_MASK BITFIELD(1, 1) 230#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
204 231
205/* Used by PRM_IRQSTATUS_MPU */ 232/* Used by PRM_IRQSTATUS_MPU */
206#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 233#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
207#define OMAP4430_DPLL_MPU_RECAL_ST_MASK BITFIELD(1, 1) 234#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
208 235
209/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 236/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
210#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 237#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
211#define OMAP4430_DPLL_PER_RECAL_EN_MASK BITFIELD(3, 3) 238#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
212 239
213/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 240/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
214#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 241#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
215#define OMAP4430_DPLL_PER_RECAL_ST_MASK BITFIELD(3, 3) 242#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
216 243
217/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 244/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
218#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 245#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
219#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK BITFIELD(7, 7) 246#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
220 247
221/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 248/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
222#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 249#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
223#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK BITFIELD(7, 7) 250#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
224
225/* Used by PRM_IRQENABLE_MPU */
226#define OMAP4430_DPLL_USB_RECAL_EN_SHIFT 5
227#define OMAP4430_DPLL_USB_RECAL_EN_MASK BITFIELD(5, 5)
228
229/* Used by PRM_IRQSTATUS_MPU */
230#define OMAP4430_DPLL_USB_RECAL_ST_SHIFT 5
231#define OMAP4430_DPLL_USB_RECAL_ST_MASK BITFIELD(5, 5)
232 251
233/* Used by PM_DSS_PWRSTCTRL */ 252/* Used by PM_DSS_PWRSTCTRL */
234#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 253#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
235#define OMAP4430_DSS_MEM_ONSTATE_MASK BITFIELD(16, 17) 254#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
236 255
237/* Used by PM_DSS_PWRSTCTRL */ 256/* Used by PM_DSS_PWRSTCTRL */
238#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 257#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
239#define OMAP4430_DSS_MEM_RETSTATE_MASK BITFIELD(8, 8) 258#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
240 259
241/* Used by PM_DSS_PWRSTST */ 260/* Used by PM_DSS_PWRSTST */
242#define OMAP4430_DSS_MEM_STATEST_SHIFT 4 261#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
243#define OMAP4430_DSS_MEM_STATEST_MASK BITFIELD(4, 5) 262#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
244 263
245/* Used by PM_CORE_PWRSTCTRL */ 264/* Used by PM_CORE_PWRSTCTRL */
246#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 265#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
247#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK BITFIELD(20, 21) 266#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
248 267
249/* Used by PM_CORE_PWRSTCTRL */ 268/* Used by PM_CORE_PWRSTCTRL */
250#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 269#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
251#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK BITFIELD(10, 10) 270#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
252 271
253/* Used by PM_CORE_PWRSTST */ 272/* Used by PM_CORE_PWRSTST */
254#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 273#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
255#define OMAP4430_DUCATI_L2RAM_STATEST_MASK BITFIELD(8, 9) 274#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
256 275
257/* Used by PM_CORE_PWRSTCTRL */ 276/* Used by PM_CORE_PWRSTCTRL */
258#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 277#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
259#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK BITFIELD(22, 23) 278#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
260 279
261/* Used by PM_CORE_PWRSTCTRL */ 280/* Used by PM_CORE_PWRSTCTRL */
262#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 281#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
263#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK BITFIELD(11, 11) 282#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
264 283
265/* Used by PM_CORE_PWRSTST */ 284/* Used by PM_CORE_PWRSTST */
266#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 285#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
267#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK BITFIELD(10, 11) 286#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
268 287
269/* Used by RM_MPU_RSTST */ 288/* Used by RM_MPU_RSTST */
270#define OMAP4430_EMULATION_RST_SHIFT 0 289#define OMAP4430_EMULATION_RST_SHIFT 0
271#define OMAP4430_EMULATION_RST_MASK BITFIELD(0, 0) 290#define OMAP4430_EMULATION_RST_MASK (1 << 0)
272 291
273/* Used by RM_DUCATI_RSTST */ 292/* Used by RM_DUCATI_RSTST */
274#define OMAP4430_EMULATION_RST1ST_SHIFT 3 293#define OMAP4430_EMULATION_RST1ST_SHIFT 3
275#define OMAP4430_EMULATION_RST1ST_MASK BITFIELD(3, 3) 294#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
276 295
277/* Used by RM_DUCATI_RSTST */ 296/* Used by RM_DUCATI_RSTST */
278#define OMAP4430_EMULATION_RST2ST_SHIFT 4 297#define OMAP4430_EMULATION_RST2ST_SHIFT 4
279#define OMAP4430_EMULATION_RST2ST_MASK BITFIELD(4, 4) 298#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
280 299
281/* Used by RM_IVAHD_RSTST */ 300/* Used by RM_IVAHD_RSTST */
282#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 301#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
283#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK BITFIELD(3, 3) 302#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
284 303
285/* Used by RM_IVAHD_RSTST */ 304/* Used by RM_IVAHD_RSTST */
286#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 305#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
287#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK BITFIELD(4, 4) 306#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
288 307
289/* Used by PM_EMU_PWRSTCTRL */ 308/* Used by PM_EMU_PWRSTCTRL */
290#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 309#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
291#define OMAP4430_EMU_BANK_ONSTATE_MASK BITFIELD(16, 17) 310#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
292 311
293/* Used by PM_EMU_PWRSTST */ 312/* Used by PM_EMU_PWRSTST */
294#define OMAP4430_EMU_BANK_STATEST_SHIFT 4 313#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
295#define OMAP4430_EMU_BANK_STATEST_MASK BITFIELD(4, 5) 314#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
296
297/*
298 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
299 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
300 */
301#define OMAP4430_ENABLE_RTA_EXPORT_SHIFT 0
302#define OMAP4430_ENABLE_RTA_EXPORT_MASK BITFIELD(0, 0)
303 315
304/* 316/*
305 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 317 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
306 * PRM_LDO_SRAM_MPU_SETUP 318 * PRM_LDO_SRAM_MPU_SETUP
307 */ 319 */
308#define OMAP4430_ENFUNC1_SHIFT 3 320#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
309#define OMAP4430_ENFUNC1_MASK BITFIELD(3, 3) 321#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
310 322
311/* 323/*
312 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 324 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
313 * PRM_LDO_SRAM_MPU_SETUP 325 * PRM_LDO_SRAM_MPU_SETUP
314 */ 326 */
315#define OMAP4430_ENFUNC3_SHIFT 5 327#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
316#define OMAP4430_ENFUNC3_MASK BITFIELD(5, 5) 328#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
317 329
318/* 330/*
319 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 331 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
320 * PRM_LDO_SRAM_MPU_SETUP 332 * PRM_LDO_SRAM_MPU_SETUP
321 */ 333 */
322#define OMAP4430_ENFUNC4_SHIFT 6 334#define OMAP4430_ENFUNC4_SHIFT 6
323#define OMAP4430_ENFUNC4_MASK BITFIELD(6, 6) 335#define OMAP4430_ENFUNC4_MASK (1 << 6)
324 336
325/* 337/*
326 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, 338 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
327 * PRM_LDO_SRAM_MPU_SETUP 339 * PRM_LDO_SRAM_MPU_SETUP
328 */ 340 */
329#define OMAP4430_ENFUNC5_SHIFT 7 341#define OMAP4430_ENFUNC5_SHIFT 7
330#define OMAP4430_ENFUNC5_MASK BITFIELD(7, 7) 342#define OMAP4430_ENFUNC5_MASK (1 << 7)
331 343
332/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 344/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
333#define OMAP4430_ERRORGAIN_SHIFT 16 345#define OMAP4430_ERRORGAIN_SHIFT 16
334#define OMAP4430_ERRORGAIN_MASK BITFIELD(16, 23) 346#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
335 347
336/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 348/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
337#define OMAP4430_ERROROFFSET_SHIFT 24 349#define OMAP4430_ERROROFFSET_SHIFT 24
338#define OMAP4430_ERROROFFSET_MASK BITFIELD(24, 31) 350#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
339 351
340/* Used by PRM_RSTST */ 352/* Used by PRM_RSTST */
341#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 353#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
342#define OMAP4430_EXTERNAL_WARM_RST_MASK BITFIELD(5, 5) 354#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
343 355
344/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 356/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
345#define OMAP4430_FORCEUPDATE_SHIFT 1 357#define OMAP4430_FORCEUPDATE_SHIFT 1
346#define OMAP4430_FORCEUPDATE_MASK BITFIELD(1, 1) 358#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
347 359
348/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 360/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
349#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 361#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
350#define OMAP4430_FORCEUPDATEWAIT_MASK BITFIELD(8, 31) 362#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8)
351 363
352/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ 364/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
353#define OMAP4430_FORCEWKUP_EN_SHIFT 10 365#define OMAP4430_FORCEWKUP_EN_SHIFT 10
354#define OMAP4430_FORCEWKUP_EN_MASK BITFIELD(10, 10) 366#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10)
355 367
356/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ 368/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
357#define OMAP4430_FORCEWKUP_ST_SHIFT 10 369#define OMAP4430_FORCEWKUP_ST_SHIFT 10
358#define OMAP4430_FORCEWKUP_ST_MASK BITFIELD(10, 10) 370#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10)
371
372/* Used by REVISION_PRM */
373#define OMAP4430_FUNC_SHIFT 16
374#define OMAP4430_FUNC_MASK (0xfff << 16)
359 375
360/* Used by PM_GFX_PWRSTCTRL */ 376/* Used by PM_GFX_PWRSTCTRL */
361#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 377#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
362#define OMAP4430_GFX_MEM_ONSTATE_MASK BITFIELD(16, 17) 378#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16)
363 379
364/* Used by PM_GFX_PWRSTST */ 380/* Used by PM_GFX_PWRSTST */
365#define OMAP4430_GFX_MEM_STATEST_SHIFT 4 381#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
366#define OMAP4430_GFX_MEM_STATEST_MASK BITFIELD(4, 5) 382#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4)
367 383
368/* Used by PRM_RSTST */ 384/* Used by PRM_RSTST */
369#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 385#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
370#define OMAP4430_GLOBAL_COLD_RST_MASK BITFIELD(0, 0) 386#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0)
371 387
372/* Used by PRM_RSTST */ 388/* Used by PRM_RSTST */
373#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 389#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
374#define OMAP4430_GLOBAL_WARM_SW_RST_MASK BITFIELD(1, 1) 390#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1)
375 391
376/* Used by PRM_IO_PMCTRL */ 392/* Used by PRM_IO_PMCTRL */
377#define OMAP4430_GLOBAL_WUEN_SHIFT 16 393#define OMAP4430_GLOBAL_WUEN_SHIFT 16
378#define OMAP4430_GLOBAL_WUEN_MASK BITFIELD(16, 16) 394#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
379 395
380/* Used by PRM_VC_CFG_I2C_MODE */ 396/* Used by PRM_VC_CFG_I2C_MODE */
381#define OMAP4430_HSMCODE_SHIFT 0 397#define OMAP4430_HSMCODE_SHIFT 0
382#define OMAP4430_HSMCODE_MASK BITFIELD(0, 2) 398#define OMAP4430_HSMCODE_MASK (0x7 << 0)
383 399
384/* Used by PRM_VC_CFG_I2C_MODE */ 400/* Used by PRM_VC_CFG_I2C_MODE */
385#define OMAP4430_HSMODEEN_SHIFT 3 401#define OMAP4430_HSMODEEN_SHIFT 3
386#define OMAP4430_HSMODEEN_MASK BITFIELD(3, 3) 402#define OMAP4430_HSMODEEN_MASK (1 << 3)
387 403
388/* Used by PRM_VC_CFG_I2C_CLK */ 404/* Used by PRM_VC_CFG_I2C_CLK */
389#define OMAP4430_HSSCLH_SHIFT 16 405#define OMAP4430_HSSCLH_SHIFT 16
390#define OMAP4430_HSSCLH_MASK BITFIELD(16, 23) 406#define OMAP4430_HSSCLH_MASK (0xff << 16)
391 407
392/* Used by PRM_VC_CFG_I2C_CLK */ 408/* Used by PRM_VC_CFG_I2C_CLK */
393#define OMAP4430_HSSCLL_SHIFT 24 409#define OMAP4430_HSSCLL_SHIFT 24
394#define OMAP4430_HSSCLL_MASK BITFIELD(24, 31) 410#define OMAP4430_HSSCLL_MASK (0xff << 24)
395 411
396/* Used by PM_IVAHD_PWRSTCTRL */ 412/* Used by PM_IVAHD_PWRSTCTRL */
397#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 413#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
398#define OMAP4430_HWA_MEM_ONSTATE_MASK BITFIELD(16, 17) 414#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16)
399 415
400/* Used by PM_IVAHD_PWRSTCTRL */ 416/* Used by PM_IVAHD_PWRSTCTRL */
401#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 417#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
402#define OMAP4430_HWA_MEM_RETSTATE_MASK BITFIELD(8, 8) 418#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8)
403 419
404/* Used by PM_IVAHD_PWRSTST */ 420/* Used by PM_IVAHD_PWRSTST */
405#define OMAP4430_HWA_MEM_STATEST_SHIFT 4 421#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
406#define OMAP4430_HWA_MEM_STATEST_MASK BITFIELD(4, 5) 422#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4)
407 423
408/* Used by RM_MPU_RSTST */ 424/* Used by RM_MPU_RSTST */
409#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 425#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
410#define OMAP4430_ICECRUSHER_MPU_RST_MASK BITFIELD(1, 1) 426#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1)
411 427
412/* Used by RM_DUCATI_RSTST */ 428/* Used by RM_DUCATI_RSTST */
413#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 429#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
414#define OMAP4430_ICECRUSHER_RST1ST_MASK BITFIELD(5, 5) 430#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5)
415 431
416/* Used by RM_DUCATI_RSTST */ 432/* Used by RM_DUCATI_RSTST */
417#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 433#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
418#define OMAP4430_ICECRUSHER_RST2ST_MASK BITFIELD(6, 6) 434#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6)
419 435
420/* Used by RM_IVAHD_RSTST */ 436/* Used by RM_IVAHD_RSTST */
421#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 437#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
422#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK BITFIELD(5, 5) 438#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5)
423 439
424/* Used by RM_IVAHD_RSTST */ 440/* Used by RM_IVAHD_RSTST */
425#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 441#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
426#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK BITFIELD(6, 6) 442#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6)
427 443
428/* Used by PRM_RSTST */ 444/* Used by PRM_RSTST */
429#define OMAP4430_ICEPICK_RST_SHIFT 9 445#define OMAP4430_ICEPICK_RST_SHIFT 9
430#define OMAP4430_ICEPICK_RST_MASK BITFIELD(9, 9) 446#define OMAP4430_ICEPICK_RST_MASK (1 << 9)
431 447
432/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 448/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
433#define OMAP4430_INITVDD_SHIFT 2 449#define OMAP4430_INITVDD_SHIFT 2
434#define OMAP4430_INITVDD_MASK BITFIELD(2, 2) 450#define OMAP4430_INITVDD_MASK (1 << 2)
435 451
436/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 452/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
437#define OMAP4430_INITVOLTAGE_SHIFT 8 453#define OMAP4430_INITVOLTAGE_SHIFT 8
438#define OMAP4430_INITVOLTAGE_MASK BITFIELD(8, 15) 454#define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
439 455
440/* 456/*
441 * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 457 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
442 * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 458 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
443 * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 459 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
444 */ 460 */
445#define OMAP4430_INTRANSITION_SHIFT 20 461#define OMAP4430_INTRANSITION_SHIFT 20
446#define OMAP4430_INTRANSITION_MASK BITFIELD(20, 20) 462#define OMAP4430_INTRANSITION_MASK (1 << 20)
447 463
448/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 464/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
449#define OMAP4430_IO_EN_SHIFT 9 465#define OMAP4430_IO_EN_SHIFT 9
450#define OMAP4430_IO_EN_MASK BITFIELD(9, 9) 466#define OMAP4430_IO_EN_MASK (1 << 9)
451 467
452/* Used by PRM_IO_PMCTRL */ 468/* Used by PRM_IO_PMCTRL */
453#define OMAP4430_IO_ON_STATUS_SHIFT 5 469#define OMAP4430_IO_ON_STATUS_SHIFT 5
454#define OMAP4430_IO_ON_STATUS_MASK BITFIELD(5, 5) 470#define OMAP4430_IO_ON_STATUS_MASK (1 << 5)
455 471
456/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 472/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
457#define OMAP4430_IO_ST_SHIFT 9 473#define OMAP4430_IO_ST_SHIFT 9
458#define OMAP4430_IO_ST_MASK BITFIELD(9, 9) 474#define OMAP4430_IO_ST_MASK (1 << 9)
459 475
460/* Used by PRM_IO_PMCTRL */ 476/* Used by PRM_IO_PMCTRL */
461#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 477#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
462#define OMAP4430_ISOCLK_OVERRIDE_MASK BITFIELD(0, 0) 478#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0)
463 479
464/* Used by PRM_IO_PMCTRL */ 480/* Used by PRM_IO_PMCTRL */
465#define OMAP4430_ISOCLK_STATUS_SHIFT 1 481#define OMAP4430_ISOCLK_STATUS_SHIFT 1
466#define OMAP4430_ISOCLK_STATUS_MASK BITFIELD(1, 1) 482#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1)
467 483
468/* Used by PRM_IO_PMCTRL */ 484/* Used by PRM_IO_PMCTRL */
469#define OMAP4430_ISOOVR_EXTEND_SHIFT 4 485#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
470#define OMAP4430_ISOOVR_EXTEND_MASK BITFIELD(4, 4) 486#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4)
471 487
472/* Used by PRM_IO_COUNT */ 488/* Used by PRM_IO_COUNT */
473#define OMAP4430_ISO_2_ON_TIME_SHIFT 0 489#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
474#define OMAP4430_ISO_2_ON_TIME_MASK BITFIELD(0, 7) 490#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0)
475 491
476/* Used by PM_L3INIT_PWRSTCTRL */ 492/* Used by PM_L3INIT_PWRSTCTRL */
477#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 493#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
478#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK BITFIELD(16, 17) 494#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
479 495
480/* Used by PM_L3INIT_PWRSTCTRL */ 496/* Used by PM_L3INIT_PWRSTCTRL */
481#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 497#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
482#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK BITFIELD(8, 8) 498#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
483 499
484/* Used by PM_L3INIT_PWRSTST */ 500/* Used by PM_L3INIT_PWRSTST */
485#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 501#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
486#define OMAP4430_L3INIT_BANK1_STATEST_MASK BITFIELD(4, 5) 502#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
503
504/*
505 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
506 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
507 */
508#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
509#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
487 510
488/* 511/*
489 * Used by PM_CORE_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, 512 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
490 * PM_MPU_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, 513 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
491 * PM_IVAHD_PWRSTCTRL 514 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
492 */ 515 */
493#define OMAP4430_LOGICRETSTATE_SHIFT 2 516#define OMAP4430_LOGICRETSTATE_SHIFT 2
494#define OMAP4430_LOGICRETSTATE_MASK BITFIELD(2, 2) 517#define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
495 518
496/* 519/*
497 * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 520 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
498 * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 521 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
499 * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 522 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
500 */ 523 */
501#define OMAP4430_LOGICSTATEST_SHIFT 2 524#define OMAP4430_LOGICSTATEST_SHIFT 2
502#define OMAP4430_LOGICSTATEST_MASK BITFIELD(2, 2) 525#define OMAP4430_LOGICSTATEST_MASK (1 << 2)
503 526
504/* 527/*
505 * Used by RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, 528 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
506 * RM_WKUP_L4WKUP_CONTEXT, RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT,
507 * RM_WKUP_SYNCTIMER_CONTEXT, RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT,
508 * RM_WKUP_USIM_CONTEXT, RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT,
509 * RM_EMU_DEBUGSS_CONTEXT, RM_D2D_SAD2D_CONTEXT, RM_D2D_SAD2D_FW_CONTEXT,
510 * RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
511 * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_OCP_WP1_CONTEXT,
512 * RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, RM_L3_2_OCMC_RAM_CONTEXT,
513 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, RM_MEMIF_DLL_CONTEXT,
514 * RM_MEMIF_DLL_H_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT,
515 * RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
516 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
517 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
518 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
519 * RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
520 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, 529 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
521 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, 530 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
522 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, 531 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
523 * RM_ABE_WDT3_CONTEXT, RM_GFX_GFX_CONTEXT, RM_MPU_MPU_CONTEXT, 532 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
524 * RM_CEFUSE_CEFUSE_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, 533 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
525 * RM_ALWON_SR_CORE_CONTEXT, RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, 534 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
526 * RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, RM_L4PER_ADC_CONTEXT, 535 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
527 * RM_L4PER_DMTIMER10_CONTEXT, RM_L4PER_DMTIMER11_CONTEXT, 536 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
528 * RM_L4PER_DMTIMER2_CONTEXT, RM_L4PER_DMTIMER3_CONTEXT, 537 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
529 * RM_L4PER_DMTIMER4_CONTEXT, RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, 538 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
530 * RM_L4PER_HDQ1W_CONTEXT, RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 539 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
531 * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, 540 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
532 * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, 541 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
533 * RM_L4PER_MCASP3_CONTEXT, RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, 542 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
534 * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, 543 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
535 * RM_L4PER_MGATE_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, 544 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
536 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_MSPROHG_CONTEXT, 545 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
537 * RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT, 546 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
538 * RM_TESLA_TESLA_CONTEXT, RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT 547 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
548 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
549 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
550 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
551 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
552 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
553 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
554 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
555 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
556 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
557 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
558 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
559 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
560 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
561 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
539 */ 562 */
540#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 563#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
541#define OMAP4430_LOSTCONTEXT_DFF_MASK BITFIELD(0, 0) 564#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
542 565
543/* 566/*
544 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, 567 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
545 * RM_D2D_SAD2D_FW_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, 568 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
569 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
570 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
571 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
572 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
546 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, 573 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
547 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, 574 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
548 * RM_L4CFG_MAILBOX_CONTEXT, RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, 575 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
549 * RM_MEMIF_EMIF_2_CONTEXT, RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, 576 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
550 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_L3INIT_HSI_CONTEXT, 577 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
551 * RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_MMC6_CONTEXT, 578 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
552 * RM_L3INIT_USB_HOST_CONTEXT, RM_L3INIT_USB_HOST_FS_CONTEXT, 579 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
553 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_USB_TLL_CONTEXT, RM_DSS_DSS_CONTEXT, 580 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
554 * RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, RM_L4PER_GPIO4_CONTEXT, 581 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
555 * RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, RM_L4PER_I2C1_CONTEXT, 582 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
556 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, 583 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
557 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4SEC_AES1_CONTEXT,
558 * RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, RM_L4SEC_DES3DES_CONTEXT,
559 * RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, RM_TESLA_TESLA_CONTEXT
560 */ 584 */
561#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 585#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
562#define OMAP4430_LOSTCONTEXT_RFF_MASK BITFIELD(1, 1) 586#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1)
563 587
564/* Used by RM_ABE_AESS_CONTEXT */ 588/* Used by RM_ABE_AESS_CONTEXT */
565#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 589#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
566#define OMAP4430_LOSTMEM_AESSMEM_MASK BITFIELD(8, 8) 590#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
567 591
568/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ 592/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
569#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 593#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
570#define OMAP4430_LOSTMEM_CAM_MEM_MASK BITFIELD(8, 8) 594#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8)
571 595
572/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ 596/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
573#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 597#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
574#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK BITFIELD(8, 8) 598#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
575 599
576/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ 600/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
577#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 601#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
578#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK BITFIELD(9, 9) 602#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9)
579 603
580/* Used by RM_L3_2_OCMC_RAM_CONTEXT */ 604/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
581#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 605#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
582#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK BITFIELD(8, 8) 606#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
583 607
584/* 608/*
585 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, 609 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
586 * RM_SDMA_SDMA_CONTEXT 610 * RM_SDMA_SDMA_CONTEXT
587 */ 611 */
588#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 612#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
589#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK BITFIELD(8, 8) 613#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
590 614
591/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ 615/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
592#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 616#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
593#define OMAP4430_LOSTMEM_DSS_MEM_MASK BITFIELD(8, 8) 617#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8)
594 618
595/* Used by RM_DUCATI_DUCATI_CONTEXT */ 619/* Used by RM_DUCATI_DUCATI_CONTEXT */
596#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 620#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
597#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK BITFIELD(9, 9) 621#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9)
598 622
599/* Used by RM_DUCATI_DUCATI_CONTEXT */ 623/* Used by RM_DUCATI_DUCATI_CONTEXT */
600#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 624#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
601#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK BITFIELD(8, 8) 625#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8)
602 626
603/* Used by RM_EMU_DEBUGSS_CONTEXT */ 627/* Used by RM_EMU_DEBUGSS_CONTEXT */
604#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 628#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
605#define OMAP4430_LOSTMEM_EMU_BANK_MASK BITFIELD(8, 8) 629#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8)
606 630
607/* Used by RM_GFX_GFX_CONTEXT */ 631/* Used by RM_GFX_GFX_CONTEXT */
608#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 632#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
609#define OMAP4430_LOSTMEM_GFX_MEM_MASK BITFIELD(8, 8) 633#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8)
610 634
611/* Used by RM_IVAHD_IVAHD_CONTEXT */ 635/* Used by RM_IVAHD_IVAHD_CONTEXT */
612#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 636#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
613#define OMAP4430_LOSTMEM_HWA_MEM_MASK BITFIELD(10, 10) 637#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10)
614 638
615/* 639/*
616 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, 640 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
@@ -620,19 +644,19 @@
620 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT 644 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
621 */ 645 */
622#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 646#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
623#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK BITFIELD(8, 8) 647#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
624 648
625/* Used by RM_MPU_MPU_CONTEXT */ 649/* Used by RM_MPU_MPU_CONTEXT */
626#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 650#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
627#define OMAP4430_LOSTMEM_MPU_L1_MASK BITFIELD(8, 8) 651#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8)
628 652
629/* Used by RM_MPU_MPU_CONTEXT */ 653/* Used by RM_MPU_MPU_CONTEXT */
630#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 654#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
631#define OMAP4430_LOSTMEM_MPU_L2_MASK BITFIELD(9, 9) 655#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9)
632 656
633/* Used by RM_MPU_MPU_CONTEXT */ 657/* Used by RM_MPU_MPU_CONTEXT */
634#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 658#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
635#define OMAP4430_LOSTMEM_MPU_RAM_MASK BITFIELD(10, 10) 659#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10)
636 660
637/* 661/*
638 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, 662 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
@@ -640,14 +664,14 @@
640 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT 664 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
641 */ 665 */
642#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 666#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
643#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK BITFIELD(8, 8) 667#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
644 668
645/* 669/*
646 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, 670 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
647 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT 671 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
648 */ 672 */
649#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 673#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
650#define OMAP4430_LOSTMEM_PERIHPMEM_MASK BITFIELD(8, 8) 674#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8)
651 675
652/* 676/*
653 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, 677 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
@@ -655,245 +679,237 @@
655 * RM_L4SEC_CRYPTODMA_CONTEXT 679 * RM_L4SEC_CRYPTODMA_CONTEXT
656 */ 680 */
657#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 681#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
658#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK BITFIELD(8, 8) 682#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
659 683
660/* Used by RM_IVAHD_SL2_CONTEXT */ 684/* Used by RM_IVAHD_SL2_CONTEXT */
661#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 685#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
662#define OMAP4430_LOSTMEM_SL2_MEM_MASK BITFIELD(8, 8) 686#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8)
663 687
664/* Used by RM_IVAHD_IVAHD_CONTEXT */ 688/* Used by RM_IVAHD_IVAHD_CONTEXT */
665#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 689#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
666#define OMAP4430_LOSTMEM_TCM1_MEM_MASK BITFIELD(8, 8) 690#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8)
667 691
668/* Used by RM_IVAHD_IVAHD_CONTEXT */ 692/* Used by RM_IVAHD_IVAHD_CONTEXT */
669#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 693#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
670#define OMAP4430_LOSTMEM_TCM2_MEM_MASK BITFIELD(9, 9) 694#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9)
671 695
672/* Used by RM_TESLA_TESLA_CONTEXT */ 696/* Used by RM_TESLA_TESLA_CONTEXT */
673#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 697#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
674#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK BITFIELD(10, 10) 698#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10)
675 699
676/* Used by RM_TESLA_TESLA_CONTEXT */ 700/* Used by RM_TESLA_TESLA_CONTEXT */
677#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 701#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
678#define OMAP4430_LOSTMEM_TESLA_L1_MASK BITFIELD(8, 8) 702#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8)
679 703
680/* Used by RM_TESLA_TESLA_CONTEXT */ 704/* Used by RM_TESLA_TESLA_CONTEXT */
681#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 705#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
682#define OMAP4430_LOSTMEM_TESLA_L2_MASK BITFIELD(9, 9) 706#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9)
683 707
684/* Used by RM_WKUP_SARRAM_CONTEXT */ 708/* Used by RM_WKUP_SARRAM_CONTEXT */
685#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 709#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
686#define OMAP4430_LOSTMEM_WKUP_BANK_MASK BITFIELD(8, 8) 710#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8)
687 711
688/* 712/*
689 * Used by PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, 713 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
690 * PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, 714 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
691 * PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL 715 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
692 */ 716 */
693#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 717#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
694#define OMAP4430_LOWPOWERSTATECHANGE_MASK BITFIELD(4, 4) 718#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
695
696/* Used by PM_CORE_PWRSTCTRL */
697#define OMAP4430_MEMORYCHANGE_SHIFT 3
698#define OMAP4430_MEMORYCHANGE_MASK BITFIELD(3, 3)
699 719
700/* Used by PRM_MODEM_IF_CTRL */ 720/* Used by PRM_MODEM_IF_CTRL */
701#define OMAP4430_MODEM_READY_SHIFT 1 721#define OMAP4430_MODEM_READY_SHIFT 1
702#define OMAP4430_MODEM_READY_MASK BITFIELD(1, 1) 722#define OMAP4430_MODEM_READY_MASK (1 << 1)
703 723
704/* Used by PRM_MODEM_IF_CTRL */ 724/* Used by PRM_MODEM_IF_CTRL */
705#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 725#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
706#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK BITFIELD(9, 9) 726#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
707 727
708/* Used by PRM_MODEM_IF_CTRL */ 728/* Used by PRM_MODEM_IF_CTRL */
709#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 729#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
710#define OMAP4430_MODEM_SLEEP_ST_MASK BITFIELD(16, 16) 730#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
711 731
712/* Used by PRM_MODEM_IF_CTRL */ 732/* Used by PRM_MODEM_IF_CTRL */
713#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 733#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
714#define OMAP4430_MODEM_WAKE_IRQ_MASK BITFIELD(8, 8) 734#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
715 735
716/* Used by PM_MPU_PWRSTCTRL */ 736/* Used by PM_MPU_PWRSTCTRL */
717#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 737#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
718#define OMAP4430_MPU_L1_ONSTATE_MASK BITFIELD(16, 17) 738#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
719 739
720/* Used by PM_MPU_PWRSTCTRL */ 740/* Used by PM_MPU_PWRSTCTRL */
721#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 741#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
722#define OMAP4430_MPU_L1_RETSTATE_MASK BITFIELD(8, 8) 742#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
723 743
724/* Used by PM_MPU_PWRSTST */ 744/* Used by PM_MPU_PWRSTST */
725#define OMAP4430_MPU_L1_STATEST_SHIFT 4 745#define OMAP4430_MPU_L1_STATEST_SHIFT 4
726#define OMAP4430_MPU_L1_STATEST_MASK BITFIELD(4, 5) 746#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
727 747
728/* Used by PM_MPU_PWRSTCTRL */ 748/* Used by PM_MPU_PWRSTCTRL */
729#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 749#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
730#define OMAP4430_MPU_L2_ONSTATE_MASK BITFIELD(18, 19) 750#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
731 751
732/* Used by PM_MPU_PWRSTCTRL */ 752/* Used by PM_MPU_PWRSTCTRL */
733#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 753#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
734#define OMAP4430_MPU_L2_RETSTATE_MASK BITFIELD(9, 9) 754#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
735 755
736/* Used by PM_MPU_PWRSTST */ 756/* Used by PM_MPU_PWRSTST */
737#define OMAP4430_MPU_L2_STATEST_SHIFT 6 757#define OMAP4430_MPU_L2_STATEST_SHIFT 6
738#define OMAP4430_MPU_L2_STATEST_MASK BITFIELD(6, 7) 758#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
739 759
740/* Used by PM_MPU_PWRSTCTRL */ 760/* Used by PM_MPU_PWRSTCTRL */
741#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 761#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
742#define OMAP4430_MPU_RAM_ONSTATE_MASK BITFIELD(20, 21) 762#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
743 763
744/* Used by PM_MPU_PWRSTCTRL */ 764/* Used by PM_MPU_PWRSTCTRL */
745#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 765#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
746#define OMAP4430_MPU_RAM_RETSTATE_MASK BITFIELD(10, 10) 766#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
747 767
748/* Used by PM_MPU_PWRSTST */ 768/* Used by PM_MPU_PWRSTST */
749#define OMAP4430_MPU_RAM_STATEST_SHIFT 8 769#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
750#define OMAP4430_MPU_RAM_STATEST_MASK BITFIELD(8, 9) 770#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
751 771
752/* Used by PRM_RSTST */ 772/* Used by PRM_RSTST */
753#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 773#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
754#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK BITFIELD(2, 2) 774#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
755 775
756/* Used by PRM_RSTST */ 776/* Used by PRM_RSTST */
757#define OMAP4430_MPU_WDT_RST_SHIFT 3 777#define OMAP4430_MPU_WDT_RST_SHIFT 3
758#define OMAP4430_MPU_WDT_RST_MASK BITFIELD(3, 3) 778#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
759 779
760/* Used by PM_L4PER_PWRSTCTRL */ 780/* Used by PM_L4PER_PWRSTCTRL */
761#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 781#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
762#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK BITFIELD(18, 19) 782#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
763 783
764/* Used by PM_L4PER_PWRSTCTRL */ 784/* Used by PM_L4PER_PWRSTCTRL */
765#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 785#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
766#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK BITFIELD(9, 9) 786#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
767 787
768/* Used by PM_L4PER_PWRSTST */ 788/* Used by PM_L4PER_PWRSTST */
769#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 789#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
770#define OMAP4430_NONRETAINED_BANK_STATEST_MASK BITFIELD(6, 7) 790#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
771 791
772/* Used by PM_CORE_PWRSTCTRL */ 792/* Used by PM_CORE_PWRSTCTRL */
773#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 793#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
774#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK BITFIELD(24, 25) 794#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
775 795
776/* Used by PM_CORE_PWRSTCTRL */ 796/* Used by PM_CORE_PWRSTCTRL */
777#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 797#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
778#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK BITFIELD(12, 12) 798#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
779 799
780/* Used by PM_CORE_PWRSTST */ 800/* Used by PM_CORE_PWRSTST */
781#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 801#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
782#define OMAP4430_OCP_NRET_BANK_STATEST_MASK BITFIELD(12, 13) 802#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
783 803
784/* 804/*
785 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 805 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
786 * PRM_VC_VAL_CMD_VDD_MPU_L 806 * PRM_VC_VAL_CMD_VDD_MPU_L
787 */ 807 */
788#define OMAP4430_OFF_SHIFT 0 808#define OMAP4430_OFF_SHIFT 0
789#define OMAP4430_OFF_MASK BITFIELD(0, 7) 809#define OMAP4430_OFF_MASK (0xff << 0)
790
791/* Used by PRM_LDO_BANDGAP_CTRL */
792#define OMAP4430_OFF_ENABLE_SHIFT 0
793#define OMAP4430_OFF_ENABLE_MASK BITFIELD(0, 0)
794 810
795/* 811/*
796 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 812 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
797 * PRM_VC_VAL_CMD_VDD_MPU_L 813 * PRM_VC_VAL_CMD_VDD_MPU_L
798 */ 814 */
799#define OMAP4430_ON_SHIFT 24 815#define OMAP4430_ON_SHIFT 24
800#define OMAP4430_ON_MASK BITFIELD(24, 31) 816#define OMAP4430_ON_MASK (0xff << 24)
801 817
802/* 818/*
803 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 819 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
804 * PRM_VC_VAL_CMD_VDD_MPU_L 820 * PRM_VC_VAL_CMD_VDD_MPU_L
805 */ 821 */
806#define OMAP4430_ONLP_SHIFT 16 822#define OMAP4430_ONLP_SHIFT 16
807#define OMAP4430_ONLP_MASK BITFIELD(16, 23) 823#define OMAP4430_ONLP_MASK (0xff << 16)
808 824
809/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 825/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
810#define OMAP4430_OPP_CHANGE_SHIFT 2 826#define OMAP4430_OPP_CHANGE_SHIFT 2
811#define OMAP4430_OPP_CHANGE_MASK BITFIELD(2, 2) 827#define OMAP4430_OPP_CHANGE_MASK (1 << 2)
812 828
813/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 829/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
814#define OMAP4430_OPP_SEL_SHIFT 0 830#define OMAP4430_OPP_SEL_SHIFT 0
815#define OMAP4430_OPP_SEL_MASK BITFIELD(0, 1) 831#define OMAP4430_OPP_SEL_MASK (0x3 << 0)
816 832
817/* Used by PRM_SRAM_COUNT */ 833/* Used by PRM_SRAM_COUNT */
818#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 834#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
819#define OMAP4430_PCHARGECNT_VALUE_MASK BITFIELD(0, 5) 835#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0)
820 836
821/* Used by PRM_PSCON_COUNT */ 837/* Used by PRM_PSCON_COUNT */
822#define OMAP4430_PCHARGE_TIME_SHIFT 0 838#define OMAP4430_PCHARGE_TIME_SHIFT 0
823#define OMAP4430_PCHARGE_TIME_MASK BITFIELD(0, 7) 839#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0)
824 840
825/* Used by PM_ABE_PWRSTCTRL */ 841/* Used by PM_ABE_PWRSTCTRL */
826#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 842#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
827#define OMAP4430_PERIPHMEM_ONSTATE_MASK BITFIELD(20, 21) 843#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
828 844
829/* Used by PM_ABE_PWRSTCTRL */ 845/* Used by PM_ABE_PWRSTCTRL */
830#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 846#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
831#define OMAP4430_PERIPHMEM_RETSTATE_MASK BITFIELD(10, 10) 847#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10)
832 848
833/* Used by PM_ABE_PWRSTST */ 849/* Used by PM_ABE_PWRSTST */
834#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 850#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
835#define OMAP4430_PERIPHMEM_STATEST_MASK BITFIELD(8, 9) 851#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8)
836 852
837/* Used by PRM_PHASE1_CNDP */ 853/* Used by PRM_PHASE1_CNDP */
838#define OMAP4430_PHASE1_CNDP_SHIFT 0 854#define OMAP4430_PHASE1_CNDP_SHIFT 0
839#define OMAP4430_PHASE1_CNDP_MASK BITFIELD(0, 31) 855#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0)
840 856
841/* Used by PRM_PHASE2A_CNDP */ 857/* Used by PRM_PHASE2A_CNDP */
842#define OMAP4430_PHASE2A_CNDP_SHIFT 0 858#define OMAP4430_PHASE2A_CNDP_SHIFT 0
843#define OMAP4430_PHASE2A_CNDP_MASK BITFIELD(0, 31) 859#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0)
844 860
845/* Used by PRM_PHASE2B_CNDP */ 861/* Used by PRM_PHASE2B_CNDP */
846#define OMAP4430_PHASE2B_CNDP_SHIFT 0 862#define OMAP4430_PHASE2B_CNDP_SHIFT 0
847#define OMAP4430_PHASE2B_CNDP_MASK BITFIELD(0, 31) 863#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0)
848 864
849/* Used by PRM_PSCON_COUNT */ 865/* Used by PRM_PSCON_COUNT */
850#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 866#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
851#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK BITFIELD(8, 15) 867#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
852 868
853/* 869/*
854 * Used by PM_EMU_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_CAM_PWRSTCTRL, 870 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
855 * PM_L3INIT_PWRSTCTRL, PM_ABE_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, 871 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
856 * PM_CEFUSE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_L4PER_PWRSTCTRL, 872 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
857 * PM_TESLA_PWRSTCTRL, PM_IVAHD_PWRSTCTRL 873 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
858 */ 874 */
859#define OMAP4430_POWERSTATE_SHIFT 0 875#define OMAP4430_POWERSTATE_SHIFT 0
860#define OMAP4430_POWERSTATE_MASK BITFIELD(0, 1) 876#define OMAP4430_POWERSTATE_MASK (0x3 << 0)
861 877
862/* 878/*
863 * Used by PM_EMU_PWRSTST, PM_CORE_PWRSTST, PM_CAM_PWRSTST, PM_L3INIT_PWRSTST, 879 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
864 * PM_ABE_PWRSTST, PM_GFX_PWRSTST, PM_MPU_PWRSTST, PM_CEFUSE_PWRSTST, 880 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
865 * PM_DSS_PWRSTST, PM_L4PER_PWRSTST, PM_TESLA_PWRSTST, PM_IVAHD_PWRSTST 881 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
866 */ 882 */
867#define OMAP4430_POWERSTATEST_SHIFT 0 883#define OMAP4430_POWERSTATEST_SHIFT 0
868#define OMAP4430_POWERSTATEST_MASK BITFIELD(0, 1) 884#define OMAP4430_POWERSTATEST_MASK (0x3 << 0)
869 885
870/* Used by PRM_PWRREQCTRL */ 886/* Used by PRM_PWRREQCTRL */
871#define OMAP4430_PWRREQ_COND_SHIFT 0 887#define OMAP4430_PWRREQ_COND_SHIFT 0
872#define OMAP4430_PWRREQ_COND_MASK BITFIELD(0, 1) 888#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0)
873 889
874/* Used by PRM_VC_CFG_CHANNEL */ 890/* Used by PRM_VC_CFG_CHANNEL */
875#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 891#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
876#define OMAP4430_RACEN_VDD_CORE_L_MASK BITFIELD(3, 3) 892#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3)
877 893
878/* Used by PRM_VC_CFG_CHANNEL */ 894/* Used by PRM_VC_CFG_CHANNEL */
879#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 895#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
880#define OMAP4430_RACEN_VDD_IVA_L_MASK BITFIELD(11, 11) 896#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11)
881 897
882/* Used by PRM_VC_CFG_CHANNEL */ 898/* Used by PRM_VC_CFG_CHANNEL */
883#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 899#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
884#define OMAP4430_RACEN_VDD_MPU_L_MASK BITFIELD(20, 20) 900#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20)
885 901
886/* Used by PRM_VC_CFG_CHANNEL */ 902/* Used by PRM_VC_CFG_CHANNEL */
887#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 903#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
888#define OMAP4430_RAC_VDD_CORE_L_MASK BITFIELD(2, 2) 904#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2)
889 905
890/* Used by PRM_VC_CFG_CHANNEL */ 906/* Used by PRM_VC_CFG_CHANNEL */
891#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 907#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
892#define OMAP4430_RAC_VDD_IVA_L_MASK BITFIELD(10, 10) 908#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10)
893 909
894/* Used by PRM_VC_CFG_CHANNEL */ 910/* Used by PRM_VC_CFG_CHANNEL */
895#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 911#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
896#define OMAP4430_RAC_VDD_MPU_L_MASK BITFIELD(19, 19) 912#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19)
897 913
898/* 914/*
899 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 915 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -901,7 +917,7 @@
901 * PRM_VOLTSETUP_MPU_RET_SLEEP 917 * PRM_VOLTSETUP_MPU_RET_SLEEP
902 */ 918 */
903#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 919#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
904#define OMAP4430_RAMP_DOWN_COUNT_MASK BITFIELD(16, 21) 920#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16)
905 921
906/* 922/*
907 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 923 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -909,7 +925,7 @@
909 * PRM_VOLTSETUP_MPU_RET_SLEEP 925 * PRM_VOLTSETUP_MPU_RET_SLEEP
910 */ 926 */
911#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 927#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
912#define OMAP4430_RAMP_DOWN_PRESCAL_MASK BITFIELD(24, 25) 928#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
913 929
914/* 930/*
915 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 931 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -917,7 +933,7 @@
917 * PRM_VOLTSETUP_MPU_RET_SLEEP 933 * PRM_VOLTSETUP_MPU_RET_SLEEP
918 */ 934 */
919#define OMAP4430_RAMP_UP_COUNT_SHIFT 0 935#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
920#define OMAP4430_RAMP_UP_COUNT_MASK BITFIELD(0, 5) 936#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0)
921 937
922/* 938/*
923 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, 939 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
@@ -925,1281 +941,1381 @@
925 * PRM_VOLTSETUP_MPU_RET_SLEEP 941 * PRM_VOLTSETUP_MPU_RET_SLEEP
926 */ 942 */
927#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 943#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
928#define OMAP4430_RAMP_UP_PRESCAL_MASK BITFIELD(8, 9) 944#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8)
929 945
930/* Used by PRM_VC_CFG_CHANNEL */ 946/* Used by PRM_VC_CFG_CHANNEL */
931#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 947#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
932#define OMAP4430_RAV_VDD_CORE_L_MASK BITFIELD(1, 1) 948#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1)
933 949
934/* Used by PRM_VC_CFG_CHANNEL */ 950/* Used by PRM_VC_CFG_CHANNEL */
935#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 951#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
936#define OMAP4430_RAV_VDD_IVA_L_MASK BITFIELD(9, 9) 952#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9)
937 953
938/* Used by PRM_VC_CFG_CHANNEL */ 954/* Used by PRM_VC_CFG_CHANNEL */
939#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 955#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
940#define OMAP4430_RAV_VDD_MPU_L_MASK BITFIELD(18, 18) 956#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18)
941 957
942/* Used by PRM_VC_VAL_BYPASS */ 958/* Used by PRM_VC_VAL_BYPASS */
943#define OMAP4430_REGADDR_SHIFT 8 959#define OMAP4430_REGADDR_SHIFT 8
944#define OMAP4430_REGADDR_MASK BITFIELD(8, 15) 960#define OMAP4430_REGADDR_MASK (0xff << 8)
945 961
946/* 962/*
947 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, 963 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
948 * PRM_VC_VAL_CMD_VDD_MPU_L 964 * PRM_VC_VAL_CMD_VDD_MPU_L
949 */ 965 */
950#define OMAP4430_RET_SHIFT 8 966#define OMAP4430_RET_SHIFT 8
951#define OMAP4430_RET_MASK BITFIELD(8, 15) 967#define OMAP4430_RET_MASK (0xff << 8)
952 968
953/* Used by PM_L4PER_PWRSTCTRL */ 969/* Used by PM_L4PER_PWRSTCTRL */
954#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 970#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
955#define OMAP4430_RETAINED_BANK_ONSTATE_MASK BITFIELD(16, 17) 971#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
956 972
957/* Used by PM_L4PER_PWRSTCTRL */ 973/* Used by PM_L4PER_PWRSTCTRL */
958#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 974#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
959#define OMAP4430_RETAINED_BANK_RETSTATE_MASK BITFIELD(8, 8) 975#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8)
960 976
961/* Used by PM_L4PER_PWRSTST */ 977/* Used by PM_L4PER_PWRSTST */
962#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 978#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
963#define OMAP4430_RETAINED_BANK_STATEST_MASK BITFIELD(4, 5) 979#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4)
964 980
965/* 981/*
966 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 982 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
967 * PRM_LDO_SRAM_MPU_CTRL 983 * PRM_LDO_SRAM_MPU_CTRL
968 */ 984 */
969#define OMAP4430_RETMODE_ENABLE_SHIFT 0 985#define OMAP4430_RETMODE_ENABLE_SHIFT 0
970#define OMAP4430_RETMODE_ENABLE_MASK BITFIELD(0, 0) 986#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0)
971 987
972/* Used by REVISION_PRM */ 988/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
973#define OMAP4430_REV_SHIFT 0
974#define OMAP4430_REV_MASK BITFIELD(0, 7)
975
976/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */
977#define OMAP4430_RST1_SHIFT 0 989#define OMAP4430_RST1_SHIFT 0
978#define OMAP4430_RST1_MASK BITFIELD(0, 0) 990#define OMAP4430_RST1_MASK (1 << 0)
979 991
980/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ 992/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
981#define OMAP4430_RST1ST_SHIFT 0 993#define OMAP4430_RST1ST_SHIFT 0
982#define OMAP4430_RST1ST_MASK BITFIELD(0, 0) 994#define OMAP4430_RST1ST_MASK (1 << 0)
983 995
984/* Used by RM_DUCATI_RSTCTRL, RM_TESLA_RSTCTRL, RM_IVAHD_RSTCTRL */ 996/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
985#define OMAP4430_RST2_SHIFT 1 997#define OMAP4430_RST2_SHIFT 1
986#define OMAP4430_RST2_MASK BITFIELD(1, 1) 998#define OMAP4430_RST2_MASK (1 << 1)
987 999
988/* Used by RM_DUCATI_RSTST, RM_TESLA_RSTST, RM_IVAHD_RSTST */ 1000/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
989#define OMAP4430_RST2ST_SHIFT 1 1001#define OMAP4430_RST2ST_SHIFT 1
990#define OMAP4430_RST2ST_MASK BITFIELD(1, 1) 1002#define OMAP4430_RST2ST_MASK (1 << 1)
991 1003
992/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ 1004/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
993#define OMAP4430_RST3_SHIFT 2 1005#define OMAP4430_RST3_SHIFT 2
994#define OMAP4430_RST3_MASK BITFIELD(2, 2) 1006#define OMAP4430_RST3_MASK (1 << 2)
995 1007
996/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ 1008/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
997#define OMAP4430_RST3ST_SHIFT 2 1009#define OMAP4430_RST3ST_SHIFT 2
998#define OMAP4430_RST3ST_MASK BITFIELD(2, 2) 1010#define OMAP4430_RST3ST_MASK (1 << 2)
999 1011
1000/* Used by PRM_RSTTIME */ 1012/* Used by PRM_RSTTIME */
1001#define OMAP4430_RSTTIME1_SHIFT 0 1013#define OMAP4430_RSTTIME1_SHIFT 0
1002#define OMAP4430_RSTTIME1_MASK BITFIELD(0, 9) 1014#define OMAP4430_RSTTIME1_MASK (0x3ff << 0)
1003 1015
1004/* Used by PRM_RSTTIME */ 1016/* Used by PRM_RSTTIME */
1005#define OMAP4430_RSTTIME2_SHIFT 10 1017#define OMAP4430_RSTTIME2_SHIFT 10
1006#define OMAP4430_RSTTIME2_MASK BITFIELD(10, 14) 1018#define OMAP4430_RSTTIME2_MASK (0x1f << 10)
1007 1019
1008/* Used by PRM_RSTCTRL */ 1020/* Used by PRM_RSTCTRL */
1009#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 1021#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
1010#define OMAP4430_RST_GLOBAL_COLD_SW_MASK BITFIELD(1, 1) 1022#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1)
1011 1023
1012/* Used by PRM_RSTCTRL */ 1024/* Used by PRM_RSTCTRL */
1013#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 1025#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
1014#define OMAP4430_RST_GLOBAL_WARM_SW_MASK BITFIELD(0, 0) 1026#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1027
1028/* Used by REVISION_PRM */
1029#define OMAP4430_R_RTL_SHIFT 11
1030#define OMAP4430_R_RTL_MASK (0x1f << 11)
1015 1031
1016/* Used by PRM_VC_CFG_CHANNEL */ 1032/* Used by PRM_VC_CFG_CHANNEL */
1017#define OMAP4430_SA_VDD_CORE_L_SHIFT 0 1033#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
1018#define OMAP4430_SA_VDD_CORE_L_MASK BITFIELD(0, 0) 1034#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0)
1019 1035
1020/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ 1036/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
1021#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 1037#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
1022#define OMAP4430_SA_VDD_CORE_L_0_6_MASK BITFIELD(0, 6) 1038#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
1023 1039
1024/* Used by PRM_VC_CFG_CHANNEL */ 1040/* Used by PRM_VC_CFG_CHANNEL */
1025#define OMAP4430_SA_VDD_IVA_L_SHIFT 8 1041#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
1026#define OMAP4430_SA_VDD_IVA_L_MASK BITFIELD(8, 8) 1042#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8)
1027 1043
1028/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ 1044/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
1029#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 1045#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
1030#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK BITFIELD(8, 14) 1046#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
1031 1047
1032/* Used by PRM_VC_CFG_CHANNEL */ 1048/* Used by PRM_VC_CFG_CHANNEL */
1033#define OMAP4430_SA_VDD_MPU_L_SHIFT 16 1049#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
1034#define OMAP4430_SA_VDD_MPU_L_MASK BITFIELD(16, 16) 1050#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16)
1035 1051
1036/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ 1052/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
1037#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 1053#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
1038#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK BITFIELD(16, 22) 1054#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
1055
1056/* Used by REVISION_PRM */
1057#define OMAP4430_SCHEME_SHIFT 30
1058#define OMAP4430_SCHEME_MASK (0x3 << 30)
1039 1059
1040/* Used by PRM_VC_CFG_I2C_CLK */ 1060/* Used by PRM_VC_CFG_I2C_CLK */
1041#define OMAP4430_SCLH_SHIFT 0 1061#define OMAP4430_SCLH_SHIFT 0
1042#define OMAP4430_SCLH_MASK BITFIELD(0, 7) 1062#define OMAP4430_SCLH_MASK (0xff << 0)
1043 1063
1044/* Used by PRM_VC_CFG_I2C_CLK */ 1064/* Used by PRM_VC_CFG_I2C_CLK */
1045#define OMAP4430_SCLL_SHIFT 8 1065#define OMAP4430_SCLL_SHIFT 8
1046#define OMAP4430_SCLL_MASK BITFIELD(8, 15) 1066#define OMAP4430_SCLL_MASK (0xff << 8)
1047 1067
1048/* Used by PRM_RSTST */ 1068/* Used by PRM_RSTST */
1049#define OMAP4430_SECURE_WDT_RST_SHIFT 4 1069#define OMAP4430_SECURE_WDT_RST_SHIFT 4
1050#define OMAP4430_SECURE_WDT_RST_MASK BITFIELD(4, 4) 1070#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4)
1051 1071
1052/* Used by PM_IVAHD_PWRSTCTRL */ 1072/* Used by PM_IVAHD_PWRSTCTRL */
1053#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 1073#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
1054#define OMAP4430_SL2_MEM_ONSTATE_MASK BITFIELD(18, 19) 1074#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18)
1055 1075
1056/* Used by PM_IVAHD_PWRSTCTRL */ 1076/* Used by PM_IVAHD_PWRSTCTRL */
1057#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 1077#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
1058#define OMAP4430_SL2_MEM_RETSTATE_MASK BITFIELD(9, 9) 1078#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9)
1059 1079
1060/* Used by PM_IVAHD_PWRSTST */ 1080/* Used by PM_IVAHD_PWRSTST */
1061#define OMAP4430_SL2_MEM_STATEST_SHIFT 6 1081#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
1062#define OMAP4430_SL2_MEM_STATEST_MASK BITFIELD(6, 7) 1082#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6)
1063 1083
1064/* Used by PRM_VC_VAL_BYPASS */ 1084/* Used by PRM_VC_VAL_BYPASS */
1065#define OMAP4430_SLAVEADDR_SHIFT 0 1085#define OMAP4430_SLAVEADDR_SHIFT 0
1066#define OMAP4430_SLAVEADDR_MASK BITFIELD(0, 6) 1086#define OMAP4430_SLAVEADDR_MASK (0x7f << 0)
1067 1087
1068/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1088/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1069#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 1089#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
1070#define OMAP4430_SLEEP_RBB_SEL_MASK BITFIELD(3, 3) 1090#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3)
1071 1091
1072/* Used by PRM_SRAM_COUNT */ 1092/* Used by PRM_SRAM_COUNT */
1073#define OMAP4430_SLPCNT_VALUE_SHIFT 16 1093#define OMAP4430_SLPCNT_VALUE_SHIFT 16
1074#define OMAP4430_SLPCNT_VALUE_MASK BITFIELD(16, 23) 1094#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16)
1075 1095
1076/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 1096/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1077#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 1097#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
1078#define OMAP4430_SMPSWAITTIMEMAX_MASK BITFIELD(8, 23) 1098#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
1079 1099
1080/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 1100/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1081#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 1101#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
1082#define OMAP4430_SMPSWAITTIMEMIN_MASK BITFIELD(8, 23) 1102#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1103
1104/* Used by PRM_VC_ERRST */
1105#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1
1106#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1)
1107
1108/* Used by PRM_VC_ERRST */
1109#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9
1110#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9)
1111
1112/* Used by PRM_VC_ERRST */
1113#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17
1114#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17)
1115
1116/* Used by PRM_VC_ERRST */
1117#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0
1118#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0)
1119
1120/* Used by PRM_VC_ERRST */
1121#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8
1122#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8)
1123
1124/* Used by PRM_VC_ERRST */
1125#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16
1126#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16)
1127
1128/* Used by PRM_VC_ERRST */
1129#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1130#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1131
1132/* Used by PRM_VC_ERRST */
1133#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10
1134#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10)
1135
1136/* Used by PRM_VC_ERRST */
1137#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18
1138#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18)
1083 1139
1084/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1140/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1085#define OMAP4430_SR2EN_SHIFT 0 1141#define OMAP4430_SR2EN_SHIFT 0
1086#define OMAP4430_SR2EN_MASK BITFIELD(0, 0) 1142#define OMAP4430_SR2EN_MASK (1 << 0)
1087 1143
1088/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 1144/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1089#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 1145#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
1090#define OMAP4430_SR2_IN_TRANSITION_MASK BITFIELD(6, 6) 1146#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6)
1091 1147
1092/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ 1148/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1093#define OMAP4430_SR2_STATUS_SHIFT 3 1149#define OMAP4430_SR2_STATUS_SHIFT 3
1094#define OMAP4430_SR2_STATUS_MASK BITFIELD(3, 4) 1150#define OMAP4430_SR2_STATUS_MASK (0x3 << 3)
1095 1151
1096/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ 1152/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1097#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 1153#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
1098#define OMAP4430_SR2_WTCNT_VALUE_MASK BITFIELD(8, 15) 1154#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8)
1099 1155
1100/* 1156/*
1101 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1157 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1102 * PRM_LDO_SRAM_MPU_CTRL 1158 * PRM_LDO_SRAM_MPU_CTRL
1103 */ 1159 */
1104#define OMAP4430_SRAMLDO_STATUS_SHIFT 8 1160#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
1105#define OMAP4430_SRAMLDO_STATUS_MASK BITFIELD(8, 8) 1161#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8)
1106 1162
1107/* 1163/*
1108 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, 1164 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1109 * PRM_LDO_SRAM_MPU_CTRL 1165 * PRM_LDO_SRAM_MPU_CTRL
1110 */ 1166 */
1111#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 1167#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
1112#define OMAP4430_SRAM_IN_TRANSITION_MASK BITFIELD(9, 9) 1168#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9)
1113 1169
1114/* Used by PRM_VC_CFG_I2C_MODE */ 1170/* Used by PRM_VC_CFG_I2C_MODE */
1115#define OMAP4430_SRMODEEN_SHIFT 4 1171#define OMAP4430_SRMODEEN_SHIFT 4
1116#define OMAP4430_SRMODEEN_MASK BITFIELD(4, 4) 1172#define OMAP4430_SRMODEEN_MASK (1 << 4)
1117 1173
1118/* Used by PRM_VOLTSETUP_WARMRESET */ 1174/* Used by PRM_VOLTSETUP_WARMRESET */
1119#define OMAP4430_STABLE_COUNT_SHIFT 0 1175#define OMAP4430_STABLE_COUNT_SHIFT 0
1120#define OMAP4430_STABLE_COUNT_MASK BITFIELD(0, 5) 1176#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0)
1121 1177
1122/* Used by PRM_VOLTSETUP_WARMRESET */ 1178/* Used by PRM_VOLTSETUP_WARMRESET */
1123#define OMAP4430_STABLE_PRESCAL_SHIFT 8 1179#define OMAP4430_STABLE_PRESCAL_SHIFT 8
1124#define OMAP4430_STABLE_PRESCAL_MASK BITFIELD(8, 9) 1180#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8)
1181
1182/* Used by PRM_LDO_BANDGAP_SETUP */
1183#define OMAP4430_STARTUP_COUNT_SHIFT 0
1184#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0)
1185
1186/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1187#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24
1188#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24)
1125 1189
1126/* Used by PM_IVAHD_PWRSTCTRL */ 1190/* Used by PM_IVAHD_PWRSTCTRL */
1127#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 1191#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
1128#define OMAP4430_TCM1_MEM_ONSTATE_MASK BITFIELD(20, 21) 1192#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
1129 1193
1130/* Used by PM_IVAHD_PWRSTCTRL */ 1194/* Used by PM_IVAHD_PWRSTCTRL */
1131#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 1195#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
1132#define OMAP4430_TCM1_MEM_RETSTATE_MASK BITFIELD(10, 10) 1196#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10)
1133 1197
1134/* Used by PM_IVAHD_PWRSTST */ 1198/* Used by PM_IVAHD_PWRSTST */
1135#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 1199#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
1136#define OMAP4430_TCM1_MEM_STATEST_MASK BITFIELD(8, 9) 1200#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8)
1137 1201
1138/* Used by PM_IVAHD_PWRSTCTRL */ 1202/* Used by PM_IVAHD_PWRSTCTRL */
1139#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 1203#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
1140#define OMAP4430_TCM2_MEM_ONSTATE_MASK BITFIELD(22, 23) 1204#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
1141 1205
1142/* Used by PM_IVAHD_PWRSTCTRL */ 1206/* Used by PM_IVAHD_PWRSTCTRL */
1143#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 1207#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
1144#define OMAP4430_TCM2_MEM_RETSTATE_MASK BITFIELD(11, 11) 1208#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11)
1145 1209
1146/* Used by PM_IVAHD_PWRSTST */ 1210/* Used by PM_IVAHD_PWRSTST */
1147#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 1211#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
1148#define OMAP4430_TCM2_MEM_STATEST_MASK BITFIELD(10, 11) 1212#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10)
1149 1213
1150/* Used by RM_TESLA_RSTST */ 1214/* Used by RM_TESLA_RSTST */
1151#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 1215#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
1152#define OMAP4430_TESLASS_EMU_RSTST_MASK BITFIELD(2, 2) 1216#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2)
1153 1217
1154/* Used by RM_TESLA_RSTST */ 1218/* Used by RM_TESLA_RSTST */
1155#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 1219#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
1156#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK BITFIELD(3, 3) 1220#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3)
1157 1221
1158/* Used by PM_TESLA_PWRSTCTRL */ 1222/* Used by PM_TESLA_PWRSTCTRL */
1159#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 1223#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
1160#define OMAP4430_TESLA_EDMA_ONSTATE_MASK BITFIELD(20, 21) 1224#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20)
1161 1225
1162/* Used by PM_TESLA_PWRSTCTRL */ 1226/* Used by PM_TESLA_PWRSTCTRL */
1163#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 1227#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
1164#define OMAP4430_TESLA_EDMA_RETSTATE_MASK BITFIELD(10, 10) 1228#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10)
1165 1229
1166/* Used by PM_TESLA_PWRSTST */ 1230/* Used by PM_TESLA_PWRSTST */
1167#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 1231#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
1168#define OMAP4430_TESLA_EDMA_STATEST_MASK BITFIELD(8, 9) 1232#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8)
1169 1233
1170/* Used by PM_TESLA_PWRSTCTRL */ 1234/* Used by PM_TESLA_PWRSTCTRL */
1171#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 1235#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
1172#define OMAP4430_TESLA_L1_ONSTATE_MASK BITFIELD(16, 17) 1236#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16)
1173 1237
1174/* Used by PM_TESLA_PWRSTCTRL */ 1238/* Used by PM_TESLA_PWRSTCTRL */
1175#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 1239#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
1176#define OMAP4430_TESLA_L1_RETSTATE_MASK BITFIELD(8, 8) 1240#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8)
1177 1241
1178/* Used by PM_TESLA_PWRSTST */ 1242/* Used by PM_TESLA_PWRSTST */
1179#define OMAP4430_TESLA_L1_STATEST_SHIFT 4 1243#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
1180#define OMAP4430_TESLA_L1_STATEST_MASK BITFIELD(4, 5) 1244#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4)
1181 1245
1182/* Used by PM_TESLA_PWRSTCTRL */ 1246/* Used by PM_TESLA_PWRSTCTRL */
1183#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 1247#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
1184#define OMAP4430_TESLA_L2_ONSTATE_MASK BITFIELD(18, 19) 1248#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18)
1185 1249
1186/* Used by PM_TESLA_PWRSTCTRL */ 1250/* Used by PM_TESLA_PWRSTCTRL */
1187#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 1251#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
1188#define OMAP4430_TESLA_L2_RETSTATE_MASK BITFIELD(9, 9) 1252#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9)
1189 1253
1190/* Used by PM_TESLA_PWRSTST */ 1254/* Used by PM_TESLA_PWRSTST */
1191#define OMAP4430_TESLA_L2_STATEST_SHIFT 6 1255#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
1192#define OMAP4430_TESLA_L2_STATEST_MASK BITFIELD(6, 7) 1256#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6)
1193 1257
1194/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1258/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1195#define OMAP4430_TIMEOUT_SHIFT 0 1259#define OMAP4430_TIMEOUT_SHIFT 0
1196#define OMAP4430_TIMEOUT_MASK BITFIELD(0, 15) 1260#define OMAP4430_TIMEOUT_MASK (0xffff << 0)
1197 1261
1198/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 1262/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
1199#define OMAP4430_TIMEOUTEN_SHIFT 3 1263#define OMAP4430_TIMEOUTEN_SHIFT 3
1200#define OMAP4430_TIMEOUTEN_MASK BITFIELD(3, 3) 1264#define OMAP4430_TIMEOUTEN_MASK (1 << 3)
1201 1265
1202/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1266/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1203#define OMAP4430_TRANSITION_EN_SHIFT 8 1267#define OMAP4430_TRANSITION_EN_SHIFT 8
1204#define OMAP4430_TRANSITION_EN_MASK BITFIELD(8, 8) 1268#define OMAP4430_TRANSITION_EN_MASK (1 << 8)
1205 1269
1206/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1270/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1207#define OMAP4430_TRANSITION_ST_SHIFT 8 1271#define OMAP4430_TRANSITION_ST_SHIFT 8
1208#define OMAP4430_TRANSITION_ST_MASK BITFIELD(8, 8) 1272#define OMAP4430_TRANSITION_ST_MASK (1 << 8)
1209 1273
1210/* Used by PRM_VC_VAL_BYPASS */ 1274/* Used by PRM_VC_VAL_BYPASS */
1211#define OMAP4430_VALID_SHIFT 24 1275#define OMAP4430_VALID_SHIFT 24
1212#define OMAP4430_VALID_MASK BITFIELD(24, 24) 1276#define OMAP4430_VALID_MASK (1 << 24)
1213 1277
1214/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1278/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1215#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 1279#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
1216#define OMAP4430_VC_BYPASSACK_EN_MASK BITFIELD(14, 14) 1280#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14)
1217 1281
1218/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1282/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1219#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 1283#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
1220#define OMAP4430_VC_BYPASSACK_ST_MASK BITFIELD(14, 14) 1284#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14)
1285
1286/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1287#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22
1288#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22)
1289
1290/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1291#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22
1292#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22)
1221 1293
1222/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1294/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1223#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 1295#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
1224#define OMAP4430_VC_IVA_VPACK_EN_MASK BITFIELD(30, 30) 1296#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30)
1225 1297
1226/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1298/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1227#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 1299#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
1228#define OMAP4430_VC_IVA_VPACK_ST_MASK BITFIELD(30, 30) 1300#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30)
1229 1301
1230/* Used by PRM_IRQENABLE_MPU_2 */ 1302/* Used by PRM_IRQENABLE_MPU_2 */
1231#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 1303#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
1232#define OMAP4430_VC_MPU_VPACK_EN_MASK BITFIELD(6, 6) 1304#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6)
1233 1305
1234/* Used by PRM_IRQSTATUS_MPU_2 */ 1306/* Used by PRM_IRQSTATUS_MPU_2 */
1235#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 1307#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
1236#define OMAP4430_VC_MPU_VPACK_ST_MASK BITFIELD(6, 6) 1308#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6)
1237 1309
1238/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1310/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1239#define OMAP4430_VC_RAERR_EN_SHIFT 12 1311#define OMAP4430_VC_RAERR_EN_SHIFT 12
1240#define OMAP4430_VC_RAERR_EN_MASK BITFIELD(12, 12) 1312#define OMAP4430_VC_RAERR_EN_MASK (1 << 12)
1241 1313
1242/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1314/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1243#define OMAP4430_VC_RAERR_ST_SHIFT 12 1315#define OMAP4430_VC_RAERR_ST_SHIFT 12
1244#define OMAP4430_VC_RAERR_ST_MASK BITFIELD(12, 12) 1316#define OMAP4430_VC_RAERR_ST_MASK (1 << 12)
1245 1317
1246/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1318/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1247#define OMAP4430_VC_SAERR_EN_SHIFT 11 1319#define OMAP4430_VC_SAERR_EN_SHIFT 11
1248#define OMAP4430_VC_SAERR_EN_MASK BITFIELD(11, 11) 1320#define OMAP4430_VC_SAERR_EN_MASK (1 << 11)
1249 1321
1250/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1322/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1251#define OMAP4430_VC_SAERR_ST_SHIFT 11 1323#define OMAP4430_VC_SAERR_ST_SHIFT 11
1252#define OMAP4430_VC_SAERR_ST_MASK BITFIELD(11, 11) 1324#define OMAP4430_VC_SAERR_ST_MASK (1 << 11)
1253 1325
1254/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1326/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1255#define OMAP4430_VC_TOERR_EN_SHIFT 13 1327#define OMAP4430_VC_TOERR_EN_SHIFT 13
1256#define OMAP4430_VC_TOERR_EN_MASK BITFIELD(13, 13) 1328#define OMAP4430_VC_TOERR_EN_MASK (1 << 13)
1257 1329
1258/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1330/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1259#define OMAP4430_VC_TOERR_ST_SHIFT 13 1331#define OMAP4430_VC_TOERR_ST_SHIFT 13
1260#define OMAP4430_VC_TOERR_ST_MASK BITFIELD(13, 13) 1332#define OMAP4430_VC_TOERR_ST_MASK (1 << 13)
1261 1333
1262/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1334/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1263#define OMAP4430_VDDMAX_SHIFT 24 1335#define OMAP4430_VDDMAX_SHIFT 24
1264#define OMAP4430_VDDMAX_MASK BITFIELD(24, 31) 1336#define OMAP4430_VDDMAX_MASK (0xff << 24)
1265 1337
1266/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ 1338/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1267#define OMAP4430_VDDMIN_SHIFT 16 1339#define OMAP4430_VDDMIN_SHIFT 16
1268#define OMAP4430_VDDMIN_MASK BITFIELD(16, 23) 1340#define OMAP4430_VDDMIN_MASK (0xff << 16)
1269 1341
1270/* Used by PRM_VOLTCTRL */ 1342/* Used by PRM_VOLTCTRL */
1271#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 1343#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
1272#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK BITFIELD(12, 12) 1344#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
1273 1345
1274/* Used by PRM_RSTST */ 1346/* Used by PRM_RSTST */
1275#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 1347#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
1276#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK BITFIELD(8, 8) 1348#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
1277 1349
1278/* Used by PRM_VOLTCTRL */ 1350/* Used by PRM_VOLTCTRL */
1279#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 1351#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
1280#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK BITFIELD(14, 14) 1352#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14)
1281 1353
1282/* Used by PRM_VOLTCTRL */ 1354/* Used by PRM_VOLTCTRL */
1283#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 1355#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
1284#define OMAP4430_VDD_IVA_PRESENCE_MASK BITFIELD(9, 9) 1356#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9)
1285 1357
1286/* Used by PRM_RSTST */ 1358/* Used by PRM_RSTST */
1287#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 1359#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
1288#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK BITFIELD(7, 7) 1360#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7)
1289 1361
1290/* Used by PRM_VOLTCTRL */ 1362/* Used by PRM_VOLTCTRL */
1291#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 1363#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
1292#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK BITFIELD(13, 13) 1364#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
1293 1365
1294/* Used by PRM_VOLTCTRL */ 1366/* Used by PRM_VOLTCTRL */
1295#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 1367#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
1296#define OMAP4430_VDD_MPU_PRESENCE_MASK BITFIELD(8, 8) 1368#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8)
1297 1369
1298/* Used by PRM_RSTST */ 1370/* Used by PRM_RSTST */
1299#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 1371#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
1300#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK BITFIELD(6, 6) 1372#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1373
1374/* Used by PRM_VC_ERRST */
1375#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4
1376#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4)
1377
1378/* Used by PRM_VC_ERRST */
1379#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12
1380#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12)
1381
1382/* Used by PRM_VC_ERRST */
1383#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20
1384#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20)
1385
1386/* Used by PRM_VC_ERRST */
1387#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3
1388#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3)
1389
1390/* Used by PRM_VC_ERRST */
1391#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11
1392#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11)
1393
1394/* Used by PRM_VC_ERRST */
1395#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19
1396#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19)
1397
1398/* Used by PRM_VC_ERRST */
1399#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1400#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1401
1402/* Used by PRM_VC_ERRST */
1403#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13
1404#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13)
1405
1406/* Used by PRM_VC_ERRST */
1407#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21
1408#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21)
1301 1409
1302/* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1410/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1303#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 1411#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
1304#define OMAP4430_VOLRA_VDD_CORE_L_MASK BITFIELD(0, 7) 1412#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
1305 1413
1306/* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1414/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1307#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 1415#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
1308#define OMAP4430_VOLRA_VDD_IVA_L_MASK BITFIELD(8, 15) 1416#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
1309 1417
1310/* Used by PRM_VC_VAL_SMPS_RA_VOL */ 1418/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1311#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 1419#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
1312#define OMAP4430_VOLRA_VDD_MPU_L_MASK BITFIELD(16, 23) 1420#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
1313 1421
1314/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ 1422/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
1315#define OMAP4430_VPENABLE_SHIFT 0 1423#define OMAP4430_VPENABLE_SHIFT 0
1316#define OMAP4430_VPENABLE_MASK BITFIELD(0, 0) 1424#define OMAP4430_VPENABLE_MASK (1 << 0)
1317 1425
1318/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ 1426/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
1319#define OMAP4430_VPINIDLE_SHIFT 0 1427#define OMAP4430_VPINIDLE_SHIFT 0
1320#define OMAP4430_VPINIDLE_MASK BITFIELD(0, 0) 1428#define OMAP4430_VPINIDLE_MASK (1 << 0)
1321 1429
1322/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ 1430/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
1323#define OMAP4430_VPVOLTAGE_SHIFT 0 1431#define OMAP4430_VPVOLTAGE_SHIFT 0
1324#define OMAP4430_VPVOLTAGE_MASK BITFIELD(0, 7) 1432#define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
1325 1433
1326/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1434/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1327#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 1435#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
1328#define OMAP4430_VP_CORE_EQVALUE_EN_MASK BITFIELD(20, 20) 1436#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20)
1329 1437
1330/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1438/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1331#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 1439#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
1332#define OMAP4430_VP_CORE_EQVALUE_ST_MASK BITFIELD(20, 20) 1440#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20)
1333 1441
1334/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1442/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1335#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 1443#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
1336#define OMAP4430_VP_CORE_MAXVDD_EN_MASK BITFIELD(18, 18) 1444#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18)
1337 1445
1338/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1446/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1339#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 1447#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
1340#define OMAP4430_VP_CORE_MAXVDD_ST_MASK BITFIELD(18, 18) 1448#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18)
1341 1449
1342/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1450/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1343#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 1451#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
1344#define OMAP4430_VP_CORE_MINVDD_EN_MASK BITFIELD(17, 17) 1452#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17)
1345 1453
1346/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1454/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1347#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 1455#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
1348#define OMAP4430_VP_CORE_MINVDD_ST_MASK BITFIELD(17, 17) 1456#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17)
1349 1457
1350/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1458/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1351#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 1459#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
1352#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK BITFIELD(19, 19) 1460#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
1353 1461
1354/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1462/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1355#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 1463#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
1356#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK BITFIELD(19, 19) 1464#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
1357 1465
1358/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1466/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1359#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 1467#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
1360#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK BITFIELD(16, 16) 1468#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
1361 1469
1362/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1470/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1363#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 1471#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
1364#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK BITFIELD(16, 16) 1472#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
1365 1473
1366/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1474/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1367#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 1475#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
1368#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK BITFIELD(21, 21) 1476#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
1369 1477
1370/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1478/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1371#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 1479#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
1372#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK BITFIELD(21, 21) 1480#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
1373 1481
1374/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1482/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1375#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 1483#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
1376#define OMAP4430_VP_IVA_EQVALUE_EN_MASK BITFIELD(28, 28) 1484#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28)
1377 1485
1378/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1486/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1379#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 1487#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
1380#define OMAP4430_VP_IVA_EQVALUE_ST_MASK BITFIELD(28, 28) 1488#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28)
1381 1489
1382/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1490/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1383#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 1491#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
1384#define OMAP4430_VP_IVA_MAXVDD_EN_MASK BITFIELD(26, 26) 1492#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26)
1385 1493
1386/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1494/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1387#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 1495#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
1388#define OMAP4430_VP_IVA_MAXVDD_ST_MASK BITFIELD(26, 26) 1496#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26)
1389 1497
1390/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1498/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1391#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 1499#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
1392#define OMAP4430_VP_IVA_MINVDD_EN_MASK BITFIELD(25, 25) 1500#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25)
1393 1501
1394/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1502/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1395#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 1503#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
1396#define OMAP4430_VP_IVA_MINVDD_ST_MASK BITFIELD(25, 25) 1504#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25)
1397 1505
1398/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1506/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1399#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 1507#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
1400#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK BITFIELD(27, 27) 1508#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27)
1401 1509
1402/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1510/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1403#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 1511#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
1404#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK BITFIELD(27, 27) 1512#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27)
1405 1513
1406/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1514/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1407#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 1515#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
1408#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK BITFIELD(24, 24) 1516#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24)
1409 1517
1410/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1518/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1411#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 1519#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
1412#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK BITFIELD(24, 24) 1520#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24)
1413 1521
1414/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ 1522/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1415#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 1523#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
1416#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK BITFIELD(29, 29) 1524#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29)
1417 1525
1418/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ 1526/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1419#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 1527#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
1420#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK BITFIELD(29, 29) 1528#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
1421 1529
1422/* Used by PRM_IRQENABLE_MPU_2 */ 1530/* Used by PRM_IRQENABLE_MPU_2 */
1423#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 1531#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
1424#define OMAP4430_VP_MPU_EQVALUE_EN_MASK BITFIELD(4, 4) 1532#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4)
1425 1533
1426/* Used by PRM_IRQSTATUS_MPU_2 */ 1534/* Used by PRM_IRQSTATUS_MPU_2 */
1427#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 1535#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
1428#define OMAP4430_VP_MPU_EQVALUE_ST_MASK BITFIELD(4, 4) 1536#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4)
1429 1537
1430/* Used by PRM_IRQENABLE_MPU_2 */ 1538/* Used by PRM_IRQENABLE_MPU_2 */
1431#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 1539#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
1432#define OMAP4430_VP_MPU_MAXVDD_EN_MASK BITFIELD(2, 2) 1540#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2)
1433 1541
1434/* Used by PRM_IRQSTATUS_MPU_2 */ 1542/* Used by PRM_IRQSTATUS_MPU_2 */
1435#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 1543#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
1436#define OMAP4430_VP_MPU_MAXVDD_ST_MASK BITFIELD(2, 2) 1544#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2)
1437 1545
1438/* Used by PRM_IRQENABLE_MPU_2 */ 1546/* Used by PRM_IRQENABLE_MPU_2 */
1439#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 1547#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
1440#define OMAP4430_VP_MPU_MINVDD_EN_MASK BITFIELD(1, 1) 1548#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1)
1441 1549
1442/* Used by PRM_IRQSTATUS_MPU_2 */ 1550/* Used by PRM_IRQSTATUS_MPU_2 */
1443#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 1551#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
1444#define OMAP4430_VP_MPU_MINVDD_ST_MASK BITFIELD(1, 1) 1552#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1)
1445 1553
1446/* Used by PRM_IRQENABLE_MPU_2 */ 1554/* Used by PRM_IRQENABLE_MPU_2 */
1447#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 1555#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
1448#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK BITFIELD(3, 3) 1556#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
1449 1557
1450/* Used by PRM_IRQSTATUS_MPU_2 */ 1558/* Used by PRM_IRQSTATUS_MPU_2 */
1451#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 1559#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
1452#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK BITFIELD(3, 3) 1560#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
1453 1561
1454/* Used by PRM_IRQENABLE_MPU_2 */ 1562/* Used by PRM_IRQENABLE_MPU_2 */
1455#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 1563#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
1456#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK BITFIELD(0, 0) 1564#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
1457 1565
1458/* Used by PRM_IRQSTATUS_MPU_2 */ 1566/* Used by PRM_IRQSTATUS_MPU_2 */
1459#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 1567#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
1460#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK BITFIELD(0, 0) 1568#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
1461 1569
1462/* Used by PRM_IRQENABLE_MPU_2 */ 1570/* Used by PRM_IRQENABLE_MPU_2 */
1463#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 1571#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
1464#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK BITFIELD(5, 5) 1572#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
1465 1573
1466/* Used by PRM_IRQSTATUS_MPU_2 */ 1574/* Used by PRM_IRQSTATUS_MPU_2 */
1467#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 1575#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
1468#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK BITFIELD(5, 5) 1576#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
1469 1577
1470/* Used by PRM_SRAM_COUNT */ 1578/* Used by PRM_SRAM_COUNT */
1471#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 1579#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
1472#define OMAP4430_VSETUPCNT_VALUE_MASK BITFIELD(8, 15) 1580#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8)
1473 1581
1474/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ 1582/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1475#define OMAP4430_VSTEPMAX_SHIFT 0 1583#define OMAP4430_VSTEPMAX_SHIFT 0
1476#define OMAP4430_VSTEPMAX_MASK BITFIELD(0, 7) 1584#define OMAP4430_VSTEPMAX_MASK (0xff << 0)
1477 1585
1478/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ 1586/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1479#define OMAP4430_VSTEPMIN_SHIFT 0 1587#define OMAP4430_VSTEPMIN_SHIFT 0
1480#define OMAP4430_VSTEPMIN_MASK BITFIELD(0, 7) 1588#define OMAP4430_VSTEPMIN_MASK (0xff << 0)
1481 1589
1482/* Used by PRM_MODEM_IF_CTRL */ 1590/* Used by PRM_MODEM_IF_CTRL */
1483#define OMAP4430_WAKE_MODEM_SHIFT 0 1591#define OMAP4430_WAKE_MODEM_SHIFT 0
1484#define OMAP4430_WAKE_MODEM_MASK BITFIELD(0, 0) 1592#define OMAP4430_WAKE_MODEM_MASK (1 << 0)
1485 1593
1486/* Used by PM_DSS_DSS_WKDEP */ 1594/* Used by PM_DSS_DSS_WKDEP */
1487#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 1595#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
1488#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK BITFIELD(1, 1) 1596#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1)
1489 1597
1490/* Used by PM_DSS_DSS_WKDEP */ 1598/* Used by PM_DSS_DSS_WKDEP */
1491#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 1599#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
1492#define OMAP4430_WKUPDEP_DISPC_MPU_MASK BITFIELD(0, 0) 1600#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0)
1493 1601
1494/* Used by PM_DSS_DSS_WKDEP */ 1602/* Used by PM_DSS_DSS_WKDEP */
1495#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 1603#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
1496#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK BITFIELD(3, 3) 1604#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
1497 1605
1498/* Used by PM_DSS_DSS_WKDEP */ 1606/* Used by PM_DSS_DSS_WKDEP */
1499#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 1607#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
1500#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK BITFIELD(2, 2) 1608#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2)
1501 1609
1502/* Used by PM_ABE_DMIC_WKDEP */ 1610/* Used by PM_ABE_DMIC_WKDEP */
1503#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 1611#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
1504#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK BITFIELD(7, 7) 1612#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
1505 1613
1506/* Used by PM_ABE_DMIC_WKDEP */ 1614/* Used by PM_ABE_DMIC_WKDEP */
1507#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 1615#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
1508#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK BITFIELD(6, 6) 1616#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6)
1509 1617
1510/* Used by PM_ABE_DMIC_WKDEP */ 1618/* Used by PM_ABE_DMIC_WKDEP */
1511#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 1619#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
1512#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK BITFIELD(0, 0) 1620#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
1513 1621
1514/* Used by PM_ABE_DMIC_WKDEP */ 1622/* Used by PM_ABE_DMIC_WKDEP */
1515#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 1623#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
1516#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK BITFIELD(2, 2) 1624#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2)
1517 1625
1518/* Used by PM_L4PER_DMTIMER10_WKDEP */ 1626/* Used by PM_L4PER_DMTIMER10_WKDEP */
1519#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 1627#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
1520#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK BITFIELD(0, 0) 1628#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0)
1521 1629
1522/* Used by PM_L4PER_DMTIMER11_WKDEP */ 1630/* Used by PM_L4PER_DMTIMER11_WKDEP */
1523#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 1631#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
1524#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK BITFIELD(1, 1) 1632#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1)
1525 1633
1526/* Used by PM_L4PER_DMTIMER11_WKDEP */ 1634/* Used by PM_L4PER_DMTIMER11_WKDEP */
1527#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 1635#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
1528#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK BITFIELD(0, 0) 1636#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0)
1529 1637
1530/* Used by PM_L4PER_DMTIMER2_WKDEP */ 1638/* Used by PM_L4PER_DMTIMER2_WKDEP */
1531#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 1639#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
1532#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK BITFIELD(0, 0) 1640#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0)
1533 1641
1534/* Used by PM_L4PER_DMTIMER3_WKDEP */ 1642/* Used by PM_L4PER_DMTIMER3_WKDEP */
1535#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 1643#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
1536#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK BITFIELD(1, 1) 1644#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1)
1537 1645
1538/* Used by PM_L4PER_DMTIMER3_WKDEP */ 1646/* Used by PM_L4PER_DMTIMER3_WKDEP */
1539#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 1647#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
1540#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK BITFIELD(0, 0) 1648#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0)
1541 1649
1542/* Used by PM_L4PER_DMTIMER4_WKDEP */ 1650/* Used by PM_L4PER_DMTIMER4_WKDEP */
1543#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 1651#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
1544#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK BITFIELD(1, 1) 1652#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1)
1545 1653
1546/* Used by PM_L4PER_DMTIMER4_WKDEP */ 1654/* Used by PM_L4PER_DMTIMER4_WKDEP */
1547#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 1655#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
1548#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK BITFIELD(0, 0) 1656#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0)
1549 1657
1550/* Used by PM_L4PER_DMTIMER9_WKDEP */ 1658/* Used by PM_L4PER_DMTIMER9_WKDEP */
1551#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 1659#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
1552#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK BITFIELD(1, 1) 1660#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1)
1553 1661
1554/* Used by PM_L4PER_DMTIMER9_WKDEP */ 1662/* Used by PM_L4PER_DMTIMER9_WKDEP */
1555#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 1663#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
1556#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK BITFIELD(0, 0) 1664#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0)
1557 1665
1558/* Used by PM_DSS_DSS_WKDEP */ 1666/* Used by PM_DSS_DSS_WKDEP */
1559#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 1667#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
1560#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK BITFIELD(5, 5) 1668#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5)
1561 1669
1562/* Used by PM_DSS_DSS_WKDEP */ 1670/* Used by PM_DSS_DSS_WKDEP */
1563#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 1671#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
1564#define OMAP4430_WKUPDEP_DSI1_MPU_MASK BITFIELD(4, 4) 1672#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4)
1565 1673
1566/* Used by PM_DSS_DSS_WKDEP */ 1674/* Used by PM_DSS_DSS_WKDEP */
1567#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 1675#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
1568#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK BITFIELD(7, 7) 1676#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7)
1569 1677
1570/* Used by PM_DSS_DSS_WKDEP */ 1678/* Used by PM_DSS_DSS_WKDEP */
1571#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 1679#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
1572#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK BITFIELD(6, 6) 1680#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6)
1573 1681
1574/* Used by PM_DSS_DSS_WKDEP */ 1682/* Used by PM_DSS_DSS_WKDEP */
1575#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 1683#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
1576#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK BITFIELD(9, 9) 1684#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9)
1577 1685
1578/* Used by PM_DSS_DSS_WKDEP */ 1686/* Used by PM_DSS_DSS_WKDEP */
1579#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 1687#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
1580#define OMAP4430_WKUPDEP_DSI2_MPU_MASK BITFIELD(8, 8) 1688#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8)
1581 1689
1582/* Used by PM_DSS_DSS_WKDEP */ 1690/* Used by PM_DSS_DSS_WKDEP */
1583#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 1691#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
1584#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK BITFIELD(11, 11) 1692#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11)
1585 1693
1586/* Used by PM_DSS_DSS_WKDEP */ 1694/* Used by PM_DSS_DSS_WKDEP */
1587#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 1695#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
1588#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK BITFIELD(10, 10) 1696#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10)
1589 1697
1590/* Used by PM_WKUP_GPIO1_WKDEP */ 1698/* Used by PM_WKUP_GPIO1_WKDEP */
1591#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 1699#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
1592#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK BITFIELD(1, 1) 1700#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1)
1593 1701
1594/* Used by PM_WKUP_GPIO1_WKDEP */ 1702/* Used by PM_WKUP_GPIO1_WKDEP */
1595#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 1703#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
1596#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK BITFIELD(0, 0) 1704#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
1597 1705
1598/* Used by PM_WKUP_GPIO1_WKDEP */ 1706/* Used by PM_WKUP_GPIO1_WKDEP */
1599#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 1707#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
1600#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK BITFIELD(6, 6) 1708#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6)
1601 1709
1602/* Used by PM_L4PER_GPIO2_WKDEP */ 1710/* Used by PM_L4PER_GPIO2_WKDEP */
1603#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 1711#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
1604#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK BITFIELD(1, 1) 1712#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1)
1605 1713
1606/* Used by PM_L4PER_GPIO2_WKDEP */ 1714/* Used by PM_L4PER_GPIO2_WKDEP */
1607#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 1715#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
1608#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK BITFIELD(0, 0) 1716#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
1609 1717
1610/* Used by PM_L4PER_GPIO2_WKDEP */ 1718/* Used by PM_L4PER_GPIO2_WKDEP */
1611#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 1719#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
1612#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK BITFIELD(6, 6) 1720#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6)
1613 1721
1614/* Used by PM_L4PER_GPIO3_WKDEP */ 1722/* Used by PM_L4PER_GPIO3_WKDEP */
1615#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 1723#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
1616#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK BITFIELD(0, 0) 1724#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
1617 1725
1618/* Used by PM_L4PER_GPIO3_WKDEP */ 1726/* Used by PM_L4PER_GPIO3_WKDEP */
1619#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 1727#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
1620#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK BITFIELD(6, 6) 1728#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6)
1621 1729
1622/* Used by PM_L4PER_GPIO4_WKDEP */ 1730/* Used by PM_L4PER_GPIO4_WKDEP */
1623#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 1731#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
1624#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK BITFIELD(0, 0) 1732#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
1625 1733
1626/* Used by PM_L4PER_GPIO4_WKDEP */ 1734/* Used by PM_L4PER_GPIO4_WKDEP */
1627#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 1735#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
1628#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK BITFIELD(6, 6) 1736#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6)
1629 1737
1630/* Used by PM_L4PER_GPIO5_WKDEP */ 1738/* Used by PM_L4PER_GPIO5_WKDEP */
1631#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 1739#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
1632#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK BITFIELD(0, 0) 1740#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
1633 1741
1634/* Used by PM_L4PER_GPIO5_WKDEP */ 1742/* Used by PM_L4PER_GPIO5_WKDEP */
1635#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 1743#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
1636#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK BITFIELD(6, 6) 1744#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6)
1637 1745
1638/* Used by PM_L4PER_GPIO6_WKDEP */ 1746/* Used by PM_L4PER_GPIO6_WKDEP */
1639#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 1747#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
1640#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK BITFIELD(0, 0) 1748#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
1641 1749
1642/* Used by PM_L4PER_GPIO6_WKDEP */ 1750/* Used by PM_L4PER_GPIO6_WKDEP */
1643#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 1751#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
1644#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK BITFIELD(6, 6) 1752#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6)
1645 1753
1646/* Used by PM_DSS_DSS_WKDEP */ 1754/* Used by PM_DSS_DSS_WKDEP */
1647#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 1755#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
1648#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK BITFIELD(19, 19) 1756#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
1649 1757
1650/* Used by PM_DSS_DSS_WKDEP */ 1758/* Used by PM_DSS_DSS_WKDEP */
1651#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 1759#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
1652#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK BITFIELD(13, 13) 1760#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13)
1653 1761
1654/* Used by PM_DSS_DSS_WKDEP */ 1762/* Used by PM_DSS_DSS_WKDEP */
1655#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 1763#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
1656#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK BITFIELD(12, 12) 1764#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
1657 1765
1658/* Used by PM_DSS_DSS_WKDEP */ 1766/* Used by PM_DSS_DSS_WKDEP */
1659#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 1767#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
1660#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK BITFIELD(14, 14) 1768#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14)
1661 1769
1662/* Used by PM_L4PER_HECC1_WKDEP */ 1770/* Used by PM_L4PER_HECC1_WKDEP */
1663#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 1771#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
1664#define OMAP4430_WKUPDEP_HECC1_MPU_MASK BITFIELD(0, 0) 1772#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0)
1665 1773
1666/* Used by PM_L4PER_HECC2_WKDEP */ 1774/* Used by PM_L4PER_HECC2_WKDEP */
1667#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 1775#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
1668#define OMAP4430_WKUPDEP_HECC2_MPU_MASK BITFIELD(0, 0) 1776#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0)
1669 1777
1670/* Used by PM_L3INIT_HSI_WKDEP */ 1778/* Used by PM_L3INIT_HSI_WKDEP */
1671#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 1779#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
1672#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK BITFIELD(6, 6) 1780#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6)
1673 1781
1674/* Used by PM_L3INIT_HSI_WKDEP */ 1782/* Used by PM_L3INIT_HSI_WKDEP */
1675#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 1783#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
1676#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK BITFIELD(1, 1) 1784#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1)
1677 1785
1678/* Used by PM_L3INIT_HSI_WKDEP */ 1786/* Used by PM_L3INIT_HSI_WKDEP */
1679#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 1787#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
1680#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK BITFIELD(0, 0) 1788#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
1681 1789
1682/* Used by PM_L4PER_I2C1_WKDEP */ 1790/* Used by PM_L4PER_I2C1_WKDEP */
1683#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 1791#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
1684#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK BITFIELD(7, 7) 1792#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
1685 1793
1686/* Used by PM_L4PER_I2C1_WKDEP */ 1794/* Used by PM_L4PER_I2C1_WKDEP */
1687#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 1795#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
1688#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK BITFIELD(1, 1) 1796#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1)
1689 1797
1690/* Used by PM_L4PER_I2C1_WKDEP */ 1798/* Used by PM_L4PER_I2C1_WKDEP */
1691#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 1799#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
1692#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK BITFIELD(0, 0) 1800#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
1693 1801
1694/* Used by PM_L4PER_I2C2_WKDEP */ 1802/* Used by PM_L4PER_I2C2_WKDEP */
1695#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 1803#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
1696#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK BITFIELD(7, 7) 1804#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
1697 1805
1698/* Used by PM_L4PER_I2C2_WKDEP */ 1806/* Used by PM_L4PER_I2C2_WKDEP */
1699#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 1807#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
1700#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK BITFIELD(1, 1) 1808#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1)
1701 1809
1702/* Used by PM_L4PER_I2C2_WKDEP */ 1810/* Used by PM_L4PER_I2C2_WKDEP */
1703#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 1811#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
1704#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK BITFIELD(0, 0) 1812#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
1705 1813
1706/* Used by PM_L4PER_I2C3_WKDEP */ 1814/* Used by PM_L4PER_I2C3_WKDEP */
1707#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 1815#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
1708#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK BITFIELD(7, 7) 1816#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
1709 1817
1710/* Used by PM_L4PER_I2C3_WKDEP */ 1818/* Used by PM_L4PER_I2C3_WKDEP */
1711#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 1819#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
1712#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK BITFIELD(1, 1) 1820#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1)
1713 1821
1714/* Used by PM_L4PER_I2C3_WKDEP */ 1822/* Used by PM_L4PER_I2C3_WKDEP */
1715#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 1823#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
1716#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK BITFIELD(0, 0) 1824#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
1717 1825
1718/* Used by PM_L4PER_I2C4_WKDEP */ 1826/* Used by PM_L4PER_I2C4_WKDEP */
1719#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 1827#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
1720#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK BITFIELD(7, 7) 1828#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
1721 1829
1722/* Used by PM_L4PER_I2C4_WKDEP */ 1830/* Used by PM_L4PER_I2C4_WKDEP */
1723#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 1831#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
1724#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK BITFIELD(1, 1) 1832#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1)
1725 1833
1726/* Used by PM_L4PER_I2C4_WKDEP */ 1834/* Used by PM_L4PER_I2C4_WKDEP */
1727#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 1835#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
1728#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK BITFIELD(0, 0) 1836#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
1729 1837
1730/* Used by PM_L4PER_I2C5_WKDEP */ 1838/* Used by PM_L4PER_I2C5_WKDEP */
1731#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 1839#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
1732#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK BITFIELD(7, 7) 1840#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7)
1733 1841
1734/* Used by PM_L4PER_I2C5_WKDEP */ 1842/* Used by PM_L4PER_I2C5_WKDEP */
1735#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 1843#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
1736#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK BITFIELD(0, 0) 1844#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
1737 1845
1738/* Used by PM_WKUP_KEYBOARD_WKDEP */ 1846/* Used by PM_WKUP_KEYBOARD_WKDEP */
1739#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 1847#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
1740#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK BITFIELD(0, 0) 1848#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0)
1741 1849
1742/* Used by PM_ABE_MCASP_WKDEP */ 1850/* Used by PM_ABE_MCASP_WKDEP */
1743#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 1851#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
1744#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK BITFIELD(7, 7) 1852#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7)
1745 1853
1746/* Used by PM_ABE_MCASP_WKDEP */ 1854/* Used by PM_ABE_MCASP_WKDEP */
1747#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 1855#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
1748#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK BITFIELD(6, 6) 1856#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6)
1749 1857
1750/* Used by PM_ABE_MCASP_WKDEP */ 1858/* Used by PM_ABE_MCASP_WKDEP */
1751#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 1859#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
1752#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK BITFIELD(0, 0) 1860#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
1753 1861
1754/* Used by PM_ABE_MCASP_WKDEP */ 1862/* Used by PM_ABE_MCASP_WKDEP */
1755#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 1863#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
1756#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK BITFIELD(2, 2) 1864#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2)
1757 1865
1758/* Used by PM_L4PER_MCASP2_WKDEP */ 1866/* Used by PM_L4PER_MCASP2_WKDEP */
1759#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 1867#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
1760#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK BITFIELD(7, 7) 1868#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7)
1761 1869
1762/* Used by PM_L4PER_MCASP2_WKDEP */ 1870/* Used by PM_L4PER_MCASP2_WKDEP */
1763#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 1871#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
1764#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK BITFIELD(6, 6) 1872#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6)
1765 1873
1766/* Used by PM_L4PER_MCASP2_WKDEP */ 1874/* Used by PM_L4PER_MCASP2_WKDEP */
1767#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 1875#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
1768#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK BITFIELD(0, 0) 1876#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
1769 1877
1770/* Used by PM_L4PER_MCASP2_WKDEP */ 1878/* Used by PM_L4PER_MCASP2_WKDEP */
1771#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 1879#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
1772#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK BITFIELD(2, 2) 1880#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2)
1773 1881
1774/* Used by PM_L4PER_MCASP3_WKDEP */ 1882/* Used by PM_L4PER_MCASP3_WKDEP */
1775#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 1883#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
1776#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK BITFIELD(7, 7) 1884#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7)
1777 1885
1778/* Used by PM_L4PER_MCASP3_WKDEP */ 1886/* Used by PM_L4PER_MCASP3_WKDEP */
1779#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 1887#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
1780#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK BITFIELD(6, 6) 1888#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6)
1781 1889
1782/* Used by PM_L4PER_MCASP3_WKDEP */ 1890/* Used by PM_L4PER_MCASP3_WKDEP */
1783#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 1891#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
1784#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK BITFIELD(0, 0) 1892#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
1785 1893
1786/* Used by PM_L4PER_MCASP3_WKDEP */ 1894/* Used by PM_L4PER_MCASP3_WKDEP */
1787#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 1895#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
1788#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK BITFIELD(2, 2) 1896#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2)
1789 1897
1790/* Used by PM_ABE_MCBSP1_WKDEP */ 1898/* Used by PM_ABE_MCBSP1_WKDEP */
1791#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 1899#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
1792#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK BITFIELD(0, 0) 1900#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
1793 1901
1794/* Used by PM_ABE_MCBSP1_WKDEP */ 1902/* Used by PM_ABE_MCBSP1_WKDEP */
1795#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 1903#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
1796#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK BITFIELD(3, 3) 1904#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
1797 1905
1798/* Used by PM_ABE_MCBSP1_WKDEP */ 1906/* Used by PM_ABE_MCBSP1_WKDEP */
1799#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 1907#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
1800#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK BITFIELD(2, 2) 1908#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2)
1801 1909
1802/* Used by PM_ABE_MCBSP2_WKDEP */ 1910/* Used by PM_ABE_MCBSP2_WKDEP */
1803#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 1911#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
1804#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK BITFIELD(0, 0) 1912#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
1805 1913
1806/* Used by PM_ABE_MCBSP2_WKDEP */ 1914/* Used by PM_ABE_MCBSP2_WKDEP */
1807#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 1915#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
1808#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK BITFIELD(3, 3) 1916#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
1809 1917
1810/* Used by PM_ABE_MCBSP2_WKDEP */ 1918/* Used by PM_ABE_MCBSP2_WKDEP */
1811#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 1919#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
1812#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK BITFIELD(2, 2) 1920#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2)
1813 1921
1814/* Used by PM_ABE_MCBSP3_WKDEP */ 1922/* Used by PM_ABE_MCBSP3_WKDEP */
1815#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 1923#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
1816#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK BITFIELD(0, 0) 1924#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
1817 1925
1818/* Used by PM_ABE_MCBSP3_WKDEP */ 1926/* Used by PM_ABE_MCBSP3_WKDEP */
1819#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 1927#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
1820#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK BITFIELD(3, 3) 1928#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
1821 1929
1822/* Used by PM_ABE_MCBSP3_WKDEP */ 1930/* Used by PM_ABE_MCBSP3_WKDEP */
1823#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 1931#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
1824#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK BITFIELD(2, 2) 1932#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2)
1825 1933
1826/* Used by PM_L4PER_MCBSP4_WKDEP */ 1934/* Used by PM_L4PER_MCBSP4_WKDEP */
1827#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 1935#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
1828#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK BITFIELD(0, 0) 1936#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0)
1829 1937
1830/* Used by PM_L4PER_MCBSP4_WKDEP */ 1938/* Used by PM_L4PER_MCBSP4_WKDEP */
1831#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 1939#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
1832#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK BITFIELD(3, 3) 1940#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3)
1833 1941
1834/* Used by PM_L4PER_MCBSP4_WKDEP */ 1942/* Used by PM_L4PER_MCBSP4_WKDEP */
1835#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 1943#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
1836#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK BITFIELD(2, 2) 1944#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2)
1837 1945
1838/* Used by PM_L4PER_MCSPI1_WKDEP */ 1946/* Used by PM_L4PER_MCSPI1_WKDEP */
1839#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 1947#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
1840#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK BITFIELD(1, 1) 1948#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1)
1841 1949
1842/* Used by PM_L4PER_MCSPI1_WKDEP */ 1950/* Used by PM_L4PER_MCSPI1_WKDEP */
1843#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 1951#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
1844#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK BITFIELD(0, 0) 1952#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
1845 1953
1846/* Used by PM_L4PER_MCSPI1_WKDEP */ 1954/* Used by PM_L4PER_MCSPI1_WKDEP */
1847#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 1955#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
1848#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK BITFIELD(3, 3) 1956#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
1849 1957
1850/* Used by PM_L4PER_MCSPI1_WKDEP */ 1958/* Used by PM_L4PER_MCSPI1_WKDEP */
1851#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 1959#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
1852#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK BITFIELD(2, 2) 1960#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2)
1853 1961
1854/* Used by PM_L4PER_MCSPI2_WKDEP */ 1962/* Used by PM_L4PER_MCSPI2_WKDEP */
1855#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 1963#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
1856#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK BITFIELD(1, 1) 1964#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1)
1857 1965
1858/* Used by PM_L4PER_MCSPI2_WKDEP */ 1966/* Used by PM_L4PER_MCSPI2_WKDEP */
1859#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 1967#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
1860#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK BITFIELD(0, 0) 1968#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
1861 1969
1862/* Used by PM_L4PER_MCSPI2_WKDEP */ 1970/* Used by PM_L4PER_MCSPI2_WKDEP */
1863#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 1971#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
1864#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK BITFIELD(3, 3) 1972#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
1865 1973
1866/* Used by PM_L4PER_MCSPI3_WKDEP */ 1974/* Used by PM_L4PER_MCSPI3_WKDEP */
1867#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 1975#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
1868#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK BITFIELD(0, 0) 1976#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
1869 1977
1870/* Used by PM_L4PER_MCSPI3_WKDEP */ 1978/* Used by PM_L4PER_MCSPI3_WKDEP */
1871#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 1979#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
1872#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK BITFIELD(3, 3) 1980#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
1873 1981
1874/* Used by PM_L4PER_MCSPI4_WKDEP */ 1982/* Used by PM_L4PER_MCSPI4_WKDEP */
1875#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 1983#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
1876#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK BITFIELD(0, 0) 1984#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
1877 1985
1878/* Used by PM_L4PER_MCSPI4_WKDEP */ 1986/* Used by PM_L4PER_MCSPI4_WKDEP */
1879#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 1987#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
1880#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK BITFIELD(3, 3) 1988#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
1881 1989
1882/* Used by PM_L3INIT_MMC1_WKDEP */ 1990/* Used by PM_L3INIT_MMC1_WKDEP */
1883#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 1991#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
1884#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK BITFIELD(1, 1) 1992#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1)
1885 1993
1886/* Used by PM_L3INIT_MMC1_WKDEP */ 1994/* Used by PM_L3INIT_MMC1_WKDEP */
1887#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 1995#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
1888#define OMAP4430_WKUPDEP_MMC1_MPU_MASK BITFIELD(0, 0) 1996#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0)
1889 1997
1890/* Used by PM_L3INIT_MMC1_WKDEP */ 1998/* Used by PM_L3INIT_MMC1_WKDEP */
1891#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 1999#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
1892#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK BITFIELD(3, 3) 2000#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
1893 2001
1894/* Used by PM_L3INIT_MMC1_WKDEP */ 2002/* Used by PM_L3INIT_MMC1_WKDEP */
1895#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 2003#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
1896#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK BITFIELD(2, 2) 2004#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2)
1897 2005
1898/* Used by PM_L3INIT_MMC2_WKDEP */ 2006/* Used by PM_L3INIT_MMC2_WKDEP */
1899#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 2007#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
1900#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK BITFIELD(1, 1) 2008#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1)
1901 2009
1902/* Used by PM_L3INIT_MMC2_WKDEP */ 2010/* Used by PM_L3INIT_MMC2_WKDEP */
1903#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 2011#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
1904#define OMAP4430_WKUPDEP_MMC2_MPU_MASK BITFIELD(0, 0) 2012#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0)
1905 2013
1906/* Used by PM_L3INIT_MMC2_WKDEP */ 2014/* Used by PM_L3INIT_MMC2_WKDEP */
1907#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 2015#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
1908#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK BITFIELD(3, 3) 2016#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
1909 2017
1910/* Used by PM_L3INIT_MMC2_WKDEP */ 2018/* Used by PM_L3INIT_MMC2_WKDEP */
1911#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 2019#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
1912#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK BITFIELD(2, 2) 2020#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2)
1913 2021
1914/* Used by PM_L3INIT_MMC6_WKDEP */ 2022/* Used by PM_L3INIT_MMC6_WKDEP */
1915#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 2023#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
1916#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK BITFIELD(1, 1) 2024#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1)
1917 2025
1918/* Used by PM_L3INIT_MMC6_WKDEP */ 2026/* Used by PM_L3INIT_MMC6_WKDEP */
1919#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 2027#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
1920#define OMAP4430_WKUPDEP_MMC6_MPU_MASK BITFIELD(0, 0) 2028#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0)
1921 2029
1922/* Used by PM_L3INIT_MMC6_WKDEP */ 2030/* Used by PM_L3INIT_MMC6_WKDEP */
1923#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 2031#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
1924#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK BITFIELD(2, 2) 2032#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2)
1925 2033
1926/* Used by PM_L4PER_MMCSD3_WKDEP */ 2034/* Used by PM_L4PER_MMCSD3_WKDEP */
1927#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 2035#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
1928#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK BITFIELD(1, 1) 2036#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1)
1929 2037
1930/* Used by PM_L4PER_MMCSD3_WKDEP */ 2038/* Used by PM_L4PER_MMCSD3_WKDEP */
1931#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 2039#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
1932#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK BITFIELD(0, 0) 2040#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0)
1933 2041
1934/* Used by PM_L4PER_MMCSD3_WKDEP */ 2042/* Used by PM_L4PER_MMCSD3_WKDEP */
1935#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 2043#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
1936#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK BITFIELD(3, 3) 2044#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3)
1937 2045
1938/* Used by PM_L4PER_MMCSD4_WKDEP */ 2046/* Used by PM_L4PER_MMCSD4_WKDEP */
1939#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 2047#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
1940#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK BITFIELD(1, 1) 2048#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1)
1941 2049
1942/* Used by PM_L4PER_MMCSD4_WKDEP */ 2050/* Used by PM_L4PER_MMCSD4_WKDEP */
1943#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 2051#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
1944#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK BITFIELD(0, 0) 2052#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0)
1945 2053
1946/* Used by PM_L4PER_MMCSD4_WKDEP */ 2054/* Used by PM_L4PER_MMCSD4_WKDEP */
1947#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 2055#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
1948#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK BITFIELD(3, 3) 2056#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3)
1949 2057
1950/* Used by PM_L4PER_MMCSD5_WKDEP */ 2058/* Used by PM_L4PER_MMCSD5_WKDEP */
1951#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 2059#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
1952#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK BITFIELD(1, 1) 2060#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1)
1953 2061
1954/* Used by PM_L4PER_MMCSD5_WKDEP */ 2062/* Used by PM_L4PER_MMCSD5_WKDEP */
1955#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 2063#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
1956#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK BITFIELD(0, 0) 2064#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0)
1957 2065
1958/* Used by PM_L4PER_MMCSD5_WKDEP */ 2066/* Used by PM_L4PER_MMCSD5_WKDEP */
1959#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 2067#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
1960#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK BITFIELD(3, 3) 2068#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3)
1961 2069
1962/* Used by PM_L3INIT_PCIESS_WKDEP */ 2070/* Used by PM_L3INIT_PCIESS_WKDEP */
1963#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 2071#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
1964#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK BITFIELD(0, 0) 2072#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0)
1965 2073
1966/* Used by PM_L3INIT_PCIESS_WKDEP */ 2074/* Used by PM_L3INIT_PCIESS_WKDEP */
1967#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 2075#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
1968#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK BITFIELD(2, 2) 2076#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2)
1969 2077
1970/* Used by PM_ABE_PDM_WKDEP */ 2078/* Used by PM_ABE_PDM_WKDEP */
1971#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 2079#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
1972#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK BITFIELD(7, 7) 2080#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7)
1973 2081
1974/* Used by PM_ABE_PDM_WKDEP */ 2082/* Used by PM_ABE_PDM_WKDEP */
1975#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 2083#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
1976#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK BITFIELD(6, 6) 2084#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6)
1977 2085
1978/* Used by PM_ABE_PDM_WKDEP */ 2086/* Used by PM_ABE_PDM_WKDEP */
1979#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 2087#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
1980#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK BITFIELD(0, 0) 2088#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0)
1981 2089
1982/* Used by PM_ABE_PDM_WKDEP */ 2090/* Used by PM_ABE_PDM_WKDEP */
1983#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 2091#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
1984#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK BITFIELD(2, 2) 2092#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2)
1985 2093
1986/* Used by PM_WKUP_RTC_WKDEP */ 2094/* Used by PM_WKUP_RTC_WKDEP */
1987#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 2095#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
1988#define OMAP4430_WKUPDEP_RTC_MPU_MASK BITFIELD(0, 0) 2096#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0)
1989 2097
1990/* Used by PM_L3INIT_SATA_WKDEP */ 2098/* Used by PM_L3INIT_SATA_WKDEP */
1991#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 2099#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
1992#define OMAP4430_WKUPDEP_SATA_MPU_MASK BITFIELD(0, 0) 2100#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0)
1993 2101
1994/* Used by PM_L3INIT_SATA_WKDEP */ 2102/* Used by PM_L3INIT_SATA_WKDEP */
1995#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 2103#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
1996#define OMAP4430_WKUPDEP_SATA_TESLA_MASK BITFIELD(2, 2) 2104#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2)
1997 2105
1998/* Used by PM_ABE_SLIMBUS_WKDEP */ 2106/* Used by PM_ABE_SLIMBUS_WKDEP */
1999#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 2107#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
2000#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK BITFIELD(7, 7) 2108#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
2001 2109
2002/* Used by PM_ABE_SLIMBUS_WKDEP */ 2110/* Used by PM_ABE_SLIMBUS_WKDEP */
2003#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 2111#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
2004#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK BITFIELD(6, 6) 2112#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6)
2005 2113
2006/* Used by PM_ABE_SLIMBUS_WKDEP */ 2114/* Used by PM_ABE_SLIMBUS_WKDEP */
2007#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 2115#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
2008#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK BITFIELD(0, 0) 2116#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
2009 2117
2010/* Used by PM_ABE_SLIMBUS_WKDEP */ 2118/* Used by PM_ABE_SLIMBUS_WKDEP */
2011#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 2119#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
2012#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK BITFIELD(2, 2) 2120#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2)
2013 2121
2014/* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2122/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2015#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 2123#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
2016#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK BITFIELD(7, 7) 2124#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7)
2017 2125
2018/* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2126/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2019#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 2127#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
2020#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK BITFIELD(6, 6) 2128#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6)
2021 2129
2022/* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2130/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2023#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 2131#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
2024#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK BITFIELD(0, 0) 2132#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0)
2025 2133
2026/* Used by PM_L4PER_SLIMBUS2_WKDEP */ 2134/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2027#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 2135#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
2028#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK BITFIELD(2, 2) 2136#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2)
2029 2137
2030/* Used by PM_ALWON_SR_CORE_WKDEP */ 2138/* Used by PM_ALWON_SR_CORE_WKDEP */
2031#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 2139#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
2032#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK BITFIELD(1, 1) 2140#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1)
2033 2141
2034/* Used by PM_ALWON_SR_CORE_WKDEP */ 2142/* Used by PM_ALWON_SR_CORE_WKDEP */
2035#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 2143#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
2036#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK BITFIELD(0, 0) 2144#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0)
2037 2145
2038/* Used by PM_ALWON_SR_IVA_WKDEP */ 2146/* Used by PM_ALWON_SR_IVA_WKDEP */
2039#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 2147#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
2040#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK BITFIELD(1, 1) 2148#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1)
2041 2149
2042/* Used by PM_ALWON_SR_IVA_WKDEP */ 2150/* Used by PM_ALWON_SR_IVA_WKDEP */
2043#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 2151#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
2044#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK BITFIELD(0, 0) 2152#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0)
2045 2153
2046/* Used by PM_ALWON_SR_MPU_WKDEP */ 2154/* Used by PM_ALWON_SR_MPU_WKDEP */
2047#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 2155#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
2048#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK BITFIELD(0, 0) 2156#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0)
2049 2157
2050/* Used by PM_WKUP_TIMER12_WKDEP */ 2158/* Used by PM_WKUP_TIMER12_WKDEP */
2051#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 2159#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
2052#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK BITFIELD(0, 0) 2160#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
2053 2161
2054/* Used by PM_WKUP_TIMER1_WKDEP */ 2162/* Used by PM_WKUP_TIMER1_WKDEP */
2055#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 2163#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
2056#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK BITFIELD(0, 0) 2164#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
2057 2165
2058/* Used by PM_ABE_TIMER5_WKDEP */ 2166/* Used by PM_ABE_TIMER5_WKDEP */
2059#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 2167#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
2060#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK BITFIELD(0, 0) 2168#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
2061 2169
2062/* Used by PM_ABE_TIMER5_WKDEP */ 2170/* Used by PM_ABE_TIMER5_WKDEP */
2063#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 2171#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
2064#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK BITFIELD(2, 2) 2172#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2)
2065 2173
2066/* Used by PM_ABE_TIMER6_WKDEP */ 2174/* Used by PM_ABE_TIMER6_WKDEP */
2067#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 2175#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
2068#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK BITFIELD(0, 0) 2176#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
2069 2177
2070/* Used by PM_ABE_TIMER6_WKDEP */ 2178/* Used by PM_ABE_TIMER6_WKDEP */
2071#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 2179#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
2072#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK BITFIELD(2, 2) 2180#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2)
2073 2181
2074/* Used by PM_ABE_TIMER7_WKDEP */ 2182/* Used by PM_ABE_TIMER7_WKDEP */
2075#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 2183#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
2076#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK BITFIELD(0, 0) 2184#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
2077 2185
2078/* Used by PM_ABE_TIMER7_WKDEP */ 2186/* Used by PM_ABE_TIMER7_WKDEP */
2079#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 2187#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
2080#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK BITFIELD(2, 2) 2188#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2)
2081 2189
2082/* Used by PM_ABE_TIMER8_WKDEP */ 2190/* Used by PM_ABE_TIMER8_WKDEP */
2083#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 2191#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
2084#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK BITFIELD(0, 0) 2192#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
2085 2193
2086/* Used by PM_ABE_TIMER8_WKDEP */ 2194/* Used by PM_ABE_TIMER8_WKDEP */
2087#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 2195#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
2088#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK BITFIELD(2, 2) 2196#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2)
2089 2197
2090/* Used by PM_L4PER_UART1_WKDEP */ 2198/* Used by PM_L4PER_UART1_WKDEP */
2091#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 2199#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
2092#define OMAP4430_WKUPDEP_UART1_MPU_MASK BITFIELD(0, 0) 2200#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0)
2093 2201
2094/* Used by PM_L4PER_UART1_WKDEP */ 2202/* Used by PM_L4PER_UART1_WKDEP */
2095#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 2203#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
2096#define OMAP4430_WKUPDEP_UART1_SDMA_MASK BITFIELD(3, 3) 2204#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3)
2097 2205
2098/* Used by PM_L4PER_UART2_WKDEP */ 2206/* Used by PM_L4PER_UART2_WKDEP */
2099#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 2207#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
2100#define OMAP4430_WKUPDEP_UART2_MPU_MASK BITFIELD(0, 0) 2208#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0)
2101 2209
2102/* Used by PM_L4PER_UART2_WKDEP */ 2210/* Used by PM_L4PER_UART2_WKDEP */
2103#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 2211#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
2104#define OMAP4430_WKUPDEP_UART2_SDMA_MASK BITFIELD(3, 3) 2212#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3)
2105 2213
2106/* Used by PM_L4PER_UART3_WKDEP */ 2214/* Used by PM_L4PER_UART3_WKDEP */
2107#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 2215#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
2108#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK BITFIELD(1, 1) 2216#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1)
2109 2217
2110/* Used by PM_L4PER_UART3_WKDEP */ 2218/* Used by PM_L4PER_UART3_WKDEP */
2111#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 2219#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
2112#define OMAP4430_WKUPDEP_UART3_MPU_MASK BITFIELD(0, 0) 2220#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0)
2113 2221
2114/* Used by PM_L4PER_UART3_WKDEP */ 2222/* Used by PM_L4PER_UART3_WKDEP */
2115#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 2223#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
2116#define OMAP4430_WKUPDEP_UART3_SDMA_MASK BITFIELD(3, 3) 2224#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3)
2117 2225
2118/* Used by PM_L4PER_UART3_WKDEP */ 2226/* Used by PM_L4PER_UART3_WKDEP */
2119#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 2227#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
2120#define OMAP4430_WKUPDEP_UART3_TESLA_MASK BITFIELD(2, 2) 2228#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2)
2121 2229
2122/* Used by PM_L4PER_UART4_WKDEP */ 2230/* Used by PM_L4PER_UART4_WKDEP */
2123#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 2231#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
2124#define OMAP4430_WKUPDEP_UART4_MPU_MASK BITFIELD(0, 0) 2232#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0)
2125 2233
2126/* Used by PM_L4PER_UART4_WKDEP */ 2234/* Used by PM_L4PER_UART4_WKDEP */
2127#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 2235#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
2128#define OMAP4430_WKUPDEP_UART4_SDMA_MASK BITFIELD(3, 3) 2236#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3)
2129 2237
2130/* Used by PM_L3INIT_UNIPRO1_WKDEP */ 2238/* Used by PM_L3INIT_UNIPRO1_WKDEP */
2131#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 2239#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
2132#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK BITFIELD(1, 1) 2240#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1)
2133 2241
2134/* Used by PM_L3INIT_UNIPRO1_WKDEP */ 2242/* Used by PM_L3INIT_UNIPRO1_WKDEP */
2135#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 2243#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
2136#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK BITFIELD(0, 0) 2244#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0)
2137 2245
2138/* Used by PM_L3INIT_USB_HOST_WKDEP */ 2246/* Used by PM_L3INIT_USB_HOST_WKDEP */
2139#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 2247#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
2140#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK BITFIELD(1, 1) 2248#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1)
2141 2249
2142/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 2250/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
2143#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 2251#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
2144#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK BITFIELD(1, 1) 2252#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1)
2145 2253
2146/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ 2254/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
2147#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 2255#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
2148#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK BITFIELD(0, 0) 2256#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0)
2149 2257
2150/* Used by PM_L3INIT_USB_HOST_WKDEP */ 2258/* Used by PM_L3INIT_USB_HOST_WKDEP */
2151#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 2259#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
2152#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK BITFIELD(0, 0) 2260#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0)
2153 2261
2154/* Used by PM_L3INIT_USB_OTG_WKDEP */ 2262/* Used by PM_L3INIT_USB_OTG_WKDEP */
2155#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 2263#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
2156#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK BITFIELD(1, 1) 2264#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1)
2157 2265
2158/* Used by PM_L3INIT_USB_OTG_WKDEP */ 2266/* Used by PM_L3INIT_USB_OTG_WKDEP */
2159#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 2267#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
2160#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK BITFIELD(0, 0) 2268#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0)
2161 2269
2162/* Used by PM_L3INIT_USB_TLL_WKDEP */ 2270/* Used by PM_L3INIT_USB_TLL_WKDEP */
2163#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 2271#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
2164#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK BITFIELD(1, 1) 2272#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1)
2165 2273
2166/* Used by PM_L3INIT_USB_TLL_WKDEP */ 2274/* Used by PM_L3INIT_USB_TLL_WKDEP */
2167#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 2275#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
2168#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK BITFIELD(0, 0) 2276#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0)
2169 2277
2170/* Used by PM_WKUP_USIM_WKDEP */ 2278/* Used by PM_WKUP_USIM_WKDEP */
2171#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 2279#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
2172#define OMAP4430_WKUPDEP_USIM_MPU_MASK BITFIELD(0, 0) 2280#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0)
2173 2281
2174/* Used by PM_WKUP_USIM_WKDEP */ 2282/* Used by PM_WKUP_USIM_WKDEP */
2175#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 2283#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
2176#define OMAP4430_WKUPDEP_USIM_SDMA_MASK BITFIELD(3, 3) 2284#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3)
2177 2285
2178/* Used by PM_WKUP_WDT2_WKDEP */ 2286/* Used by PM_WKUP_WDT2_WKDEP */
2179#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 2287#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
2180#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK BITFIELD(1, 1) 2288#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1)
2181 2289
2182/* Used by PM_WKUP_WDT2_WKDEP */ 2290/* Used by PM_WKUP_WDT2_WKDEP */
2183#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 2291#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
2184#define OMAP4430_WKUPDEP_WDT2_MPU_MASK BITFIELD(0, 0) 2292#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0)
2185 2293
2186/* Used by PM_ABE_WDT3_WKDEP */ 2294/* Used by PM_ABE_WDT3_WKDEP */
2187#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 2295#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
2188#define OMAP4430_WKUPDEP_WDT3_MPU_MASK BITFIELD(0, 0) 2296#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0)
2189 2297
2190/* Used by PM_L3INIT_HSI_WKDEP */ 2298/* Used by PM_L3INIT_HSI_WKDEP */
2191#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 2299#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
2192#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK BITFIELD(8, 8) 2300#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8)
2193 2301
2194/* Used by PM_L3INIT_XHPI_WKDEP */ 2302/* Used by PM_L3INIT_XHPI_WKDEP */
2195#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 2303#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
2196#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK BITFIELD(1, 1) 2304#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1)
2197 2305
2198/* Used by PRM_IO_PMCTRL */ 2306/* Used by PRM_IO_PMCTRL */
2199#define OMAP4430_WUCLK_CTRL_SHIFT 8 2307#define OMAP4430_WUCLK_CTRL_SHIFT 8
2200#define OMAP4430_WUCLK_CTRL_MASK BITFIELD(8, 8) 2308#define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
2201 2309
2202/* Used by PRM_IO_PMCTRL */ 2310/* Used by PRM_IO_PMCTRL */
2203#define OMAP4430_WUCLK_STATUS_SHIFT 9 2311#define OMAP4430_WUCLK_STATUS_SHIFT 9
2204#define OMAP4430_WUCLK_STATUS_MASK BITFIELD(9, 9) 2312#define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
2313
2314/* Used by REVISION_PRM */
2315#define OMAP4430_X_MAJOR_SHIFT 8
2316#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
2317
2318/* Used by REVISION_PRM */
2319#define OMAP4430_Y_MINOR_SHIFT 0
2320#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
2205#endif 2321#endif
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index fe8ef26431e5..59839dbabd84 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -44,14 +44,12 @@
44#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030) 44#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0030)
45#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 45#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038
46#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038) 46#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0038)
47#define OMAP4_PRM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 47#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
48#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040) 48#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_MOD, 0x0040)
49 49
50/* PRM.CKGEN_PRM register offsets */ 50/* PRM.CKGEN_PRM register offsets */
51#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 51#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000
52#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000) 52#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0000)
53#define OMAP4_CM_DPLL_SYS_REF_CLKSEL_OFFSET 0x0004
54#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0004)
55#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 53#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008
56#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008) 54#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_MOD, 0x0008)
57#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c 55#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c
@@ -686,8 +684,8 @@
686#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8) 684#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00d8)
687#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc 685#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc
688#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc) 686#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00dc)
689#define OMAP4_PRM_LDO_BANDGAP_CTRL_OFFSET 0x00e0 687#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0
690#define OMAP4430_PRM_LDO_BANDGAP_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0) 688#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e0)
691#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 689#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4
692#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4) 690#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00e4)
693#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 691#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8
@@ -698,6 +696,8 @@
698#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0) 696#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f0)
699#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 697#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
700#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4) 698#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f4)
699#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
700#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_MOD, 0x00f8)
701 701
702/* 702/*
703 * PRCM_MPU 703 * PRCM_MPU
@@ -715,6 +715,8 @@
715/* PRCM_MPU.DEVICE_PRM register offsets */ 715/* PRCM_MPU.DEVICE_PRM register offsets */
716#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 716#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
717#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000) 717#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0000)
718#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
719#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_MOD, 0x0004)
718 720
719/* PRCM_MPU.CPU0 register offsets */ 721/* PRCM_MPU.CPU0 register offsets */
720#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 722#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index de99ba2a57ab..3637274af5be 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm/mach-omap2/sram34xx.S
@@ -129,8 +129,11 @@ ENTRY(omap3_sram_configure_core_dpll)
129 ldr r4, [sp, #80] 129 ldr r4, [sp, #80]
130 str r4, omap_sdrc_mr_1_val 130 str r4, omap_sdrc_mr_1_val
131skip_cs1_params: 131skip_cs1_params:
132 mrc p15, 0, r8, c1, c0, 0 @ read ctrl register
133 bic r10, r8, #0x800 @ clear Z-bit, disable branch prediction
134 mcr p15, 0, r10, c1, c0, 0 @ write ctrl register
132 dsb @ flush buffered writes to interconnect 135 dsb @ flush buffered writes to interconnect
133 136 isb @ prevent speculative exec past here
134 cmp r3, #1 @ if increasing SDRC clk rate, 137 cmp r3, #1 @ if increasing SDRC clk rate,
135 bleq configure_sdrc @ program the SDRC regs early (for RFR) 138 bleq configure_sdrc @ program the SDRC regs early (for RFR)
136 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state 139 cmp r1, #SDRC_UNLOCK_DLL @ set the intended DLL state
@@ -148,6 +151,7 @@ skip_cs1_params:
148 beq return_to_sdram @ return to SDRAM code, otherwise, 151 beq return_to_sdram @ return to SDRAM code, otherwise,
149 bl configure_sdrc @ reprogram SDRC regs now 152 bl configure_sdrc @ reprogram SDRC regs now
150return_to_sdram: 153return_to_sdram:
154 mcr p15, 0, r8, c1, c0, 0 @ restore ctrl register
151 isb @ prevent speculative exec past here 155 isb @ prevent speculative exec past here
152 mov r0, #0 @ return value 156 mov r0, #0 @ return value
153 ldmfd sp!, {r1-r12, pc} @ restore regs and return 157 ldmfd sp!, {r1-r12, pc} @ restore regs and return
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 3008e7104487..7d668b3b5363 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -336,7 +336,8 @@ void __init omap3_map_io(void)
336static struct omap_globals omap4_globals = { 336static struct omap_globals omap4_globals = {
337 .class = OMAP443X_CLASS, 337 .class = OMAP443X_CLASS,
338 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), 338 .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
339 .ctrl = OMAP443X_CTRL_BASE, 339 .ctrl = OMAP443X_SCM_BASE,
340 .ctrl_pad = OMAP443X_CTRL_BASE,
340 .prm = OMAP4430_PRM_BASE, 341 .prm = OMAP4430_PRM_BASE,
341 .cm = OMAP4430_CM_BASE, 342 .cm = OMAP4430_CM_BASE,
342 .cm2 = OMAP4430_CM2_BASE, 343 .cm2 = OMAP4430_CM2_BASE,
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index c45dbb975e09..2d8f98d7ae50 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -47,6 +47,7 @@ struct omap_globals {
47 unsigned long sdrc; /* SDRAM Controller */ 47 unsigned long sdrc; /* SDRAM Controller */
48 unsigned long sms; /* SDRAM Memory Scheduler */ 48 unsigned long sms; /* SDRAM Memory Scheduler */
49 unsigned long ctrl; /* System Control Module */ 49 unsigned long ctrl; /* System Control Module */
50 unsigned long ctrl_pad; /* PAD Control Module */
50 unsigned long prm; /* Power and Reset Management */ 51 unsigned long prm; /* Power and Reset Management */
51 unsigned long cm; /* Clock Management */ 52 unsigned long cm; /* Clock Management */
52 unsigned long cm2; 53 unsigned long cm2;
diff --git a/arch/arm/plat-omap/include/plat/control.h b/arch/arm/plat-omap/include/plat/control.h
index 131bf405c2f6..19c9b2a82046 100644
--- a/arch/arm/plat-omap/include/plat/control.h
+++ b/arch/arm/plat-omap/include/plat/control.h
@@ -17,6 +17,10 @@
17#define __ASM_ARCH_CONTROL_H 17#define __ASM_ARCH_CONTROL_H
18 18
19#include <mach/io.h> 19#include <mach/io.h>
20#include <mach/ctrl_module_core_44xx.h>
21#include <mach/ctrl_module_wkup_44xx.h>
22#include <mach/ctrl_module_pad_core_44xx.h>
23#include <mach/ctrl_module_pad_wkup_44xx.h>
20 24
21#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
22#define OMAP242X_CTRL_REGADDR(reg) \ 26#define OMAP242X_CTRL_REGADDR(reg) \
@@ -204,12 +208,6 @@
204#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250 208#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
205#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254 209#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
206 210
207/* 44xx control status register offset */
208#define OMAP44XX_CONTROL_STATUS 0x2c4
209
210/* 44xx-only CONTROL_GENERAL register offsets */
211#define OMAP44XX_CONTROL_MMC1 0x628
212#define OMAP44XX_CONTROL_PBIAS_LITE 0x600
213/* 211/*
214 * REVISIT: This list of registers is not comprehensive - there are more 212 * REVISIT: This list of registers is not comprehensive - there are more
215 * that should be added. 213 * that should be added.
@@ -255,23 +253,6 @@
255#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1) 253#define OMAP2_PBIASLITEPWRDNZ0 (1 << 1)
256#define OMAP2_PBIASLITEVMODE0 (1 << 0) 254#define OMAP2_PBIASLITEVMODE0 (1 << 0)
257 255
258/* CONTROL_PBIAS_LITE bits for OMAP4 */
259#define OMAP4_MMC1_PWRDNZ (1 << 26)
260#define OMAP4_MMC1_PBIASLITE_HIZ_MODE (1 << 25)
261#define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT (1 << 24)
262#define OMAP4_MMC1_PBIASLITE_VMODE_ERROR (1 << 23)
263#define OMAP4_MMC1_PBIASLITE_PWRDNZ (1 << 22)
264#define OMAP4_MMC1_PBIASLITE_VMODE (1 << 21)
265#define OMAP4_USBC1_ICUSB_PWRDNZ (1 << 20)
266
267#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP0 (1 << 31)
268#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP1 (1 << 30)
269#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP2 (1 << 29)
270#define OMAP4_CONTROL_SDMMC1_PUSTRENGTHGRP3 (1 << 28)
271#define OMAP4_CONTROL_SDMMC1_DR0_SPEEDCTRL (1 << 27)
272#define OMAP4_CONTROL_SDMMC1_DR1_SPEEDCTRL (1 << 26)
273#define OMAP4_CONTROL_SDMMC1_DR2_SPEEDCTRL (1 << 25)
274
275/* CONTROL_PROG_IO1 bits */ 256/* CONTROL_PROG_IO1 bits */
276#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20) 257#define OMAP3630_PRG_SDMMC1_SPEEDCTRL (1 << 20)
277 258
@@ -354,9 +335,11 @@ extern void __iomem *omap_ctrl_base_get(void);
354extern u8 omap_ctrl_readb(u16 offset); 335extern u8 omap_ctrl_readb(u16 offset);
355extern u16 omap_ctrl_readw(u16 offset); 336extern u16 omap_ctrl_readw(u16 offset);
356extern u32 omap_ctrl_readl(u16 offset); 337extern u32 omap_ctrl_readl(u16 offset);
338extern u32 omap4_ctrl_pad_readl(u16 offset);
357extern void omap_ctrl_writeb(u8 val, u16 offset); 339extern void omap_ctrl_writeb(u8 val, u16 offset);
358extern void omap_ctrl_writew(u16 val, u16 offset); 340extern void omap_ctrl_writew(u16 val, u16 offset);
359extern void omap_ctrl_writel(u32 val, u16 offset); 341extern void omap_ctrl_writel(u32 val, u16 offset);
342extern void omap4_ctrl_pad_writel(u32 val, u16 offset);
360 343
361extern void omap3_save_scratchpad_contents(void); 344extern void omap3_save_scratchpad_contents(void);
362extern void omap3_clear_scratchpad_contents(void); 345extern void omap3_clear_scratchpad_contents(void);
@@ -371,9 +354,11 @@ extern void omap3_control_restore_context(void);
371#define omap_ctrl_readb(x) 0 354#define omap_ctrl_readb(x) 0
372#define omap_ctrl_readw(x) 0 355#define omap_ctrl_readw(x) 0
373#define omap_ctrl_readl(x) 0 356#define omap_ctrl_readl(x) 0
357#define omap4_ctrl_pad_readl(x) 0
374#define omap_ctrl_writeb(x, y) WARN_ON(1) 358#define omap_ctrl_writeb(x, y) WARN_ON(1)
375#define omap_ctrl_writew(x, y) WARN_ON(1) 359#define omap_ctrl_writew(x, y) WARN_ON(1)
376#define omap_ctrl_writel(x, y) WARN_ON(1) 360#define omap_ctrl_writel(x, y) WARN_ON(1)
361#define omap4_ctrl_pad_writel(x, y) WARN_ON(1)
377#endif 362#endif
378#endif /* __ASSEMBLY__ */ 363#endif /* __ASSEMBLY__ */
379 364
diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h
index fb6ec74fe39e..3ea722072e2f 100644
--- a/arch/arm/plat-omap/include/plat/powerdomain.h
+++ b/arch/arm/plat-omap/include/plat/powerdomain.h
@@ -32,6 +32,7 @@
32 32
33/* Powerdomain allowable state bitfields */ 33/* Powerdomain allowable state bitfields */
34#define PWRSTS_ON (1 << PWRDM_POWER_ON) 34#define PWRSTS_ON (1 << PWRDM_POWER_ON)
35#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
35#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ 36#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
36 (1 << PWRDM_POWER_ON)) 37 (1 << PWRDM_POWER_ON))
37 38
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 05:40:17 -0500