166 files changed, 1421 insertions, 970 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a91009c61870..8928b21a2dba 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -45,6 +45,9 @@ config ARM
         select GENERIC_SMP_IDLE_THREAD
         select KTIME_SCALAR
         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
+        select GENERIC_STRNCPY_FROM_USER
+        select GENERIC_STRNLEN_USER
+        select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -1961,6 +1964,25 @@ config ARM_ATAG_DTB_COMPAT
           bootloaders, this option allows zImage to extract the information
           from the ATAG list and store it at run time into the appended DTB.
 
+choice
+        prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
+        default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+
+config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
+        bool "Use bootloader kernel arguments if available"
+        help
+          Uses the command-line options passed by the boot loader instead of
+          the device tree bootargs property. If the boot loader doesn't provide
+          any, the device tree bootargs property will be used.
+
+config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
+        bool "Extend with bootloader kernel arguments"
+        help
+          The command-line arguments provided by the boot loader will be
+          appended to the the device tree bootargs property.
+
+endchoice
+
 config CMDLINE
         string "Default kernel command string"
         default ""
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a134141216..521e15bc6401 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -369,4 +369,13 @@ config ARM_KPROBES_TEST
         help
           Perform tests of kprobes API and instruction set simulation.
 
+config PID_IN_CONTEXTIDR
+        bool "Write the current PID to the CONTEXTIDR register"
+        depends on CPU_COPY_V6
+        help
+          Enabling this option causes the kernel to write the current PID to
+          the PROCID field of the CONTEXTIDR register, at the expense of some
+          additional instructions during context switch. Say Y here only if you
+          are planning to use hardware trace tools with this kernel.
+
 endmenu
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 0298b00fe241..f8ebf1e97027 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -10,6 +10,9 @@
 #
 # Copyright (C) 1995-2001 by Russell King
 
+# Ensure linker flags are correct
+LDFLAGS         :=
+
 LDFLAGS_vmlinux :=-p --no-undefined -X
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index 797f04bedb47..aabc02a68482 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -1,6 +1,12 @@
 #include <asm/setup.h>
 #include <libfdt.h>
 
+#if defined(CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND)
+#define do_extend_cmdline 1
+#else
+#define do_extend_cmdline 0
+#endif
+
 static int node_offset(void *fdt, const char *node_path)
 {
         int offset = fdt_path_offset(fdt, node_path);
@@ -36,6 +42,48 @@ static int setprop_cell(void *fdt, const char *node_path,
         return fdt_setprop_cell(fdt, offset, property, val);
 }
 
+static const void *getprop(const void *fdt, const char *node_path,
+                           const char *property, int *len)
+{
+        int offset = fdt_path_offset(fdt, node_path);
+
+        if (offset == -FDT_ERR_NOTFOUND)
+                return NULL;
+
+        return fdt_getprop(fdt, offset, property, len);
+}
+
+static void merge_fdt_bootargs(void *fdt, const char *fdt_cmdline)
+{
+        char cmdline[COMMAND_LINE_SIZE];
+        const char *fdt_bootargs;
+        char *ptr = cmdline;
+        int len = 0;
+
+        /* copy the fdt command line into the buffer */
+        fdt_bootargs = getprop(fdt, "/chosen", "bootargs", &len);
+        if (fdt_bootargs)
+                if (len < COMMAND_LINE_SIZE) {
+                        memcpy(ptr, fdt_bootargs, len);
+                        /* len is the length of the string
+                         * including the NULL terminator */
+                        ptr += len - 1;
+                }
+
+        /* and append the ATAG_CMDLINE */
+        if (fdt_cmdline) {
+                len = strlen(fdt_cmdline);
+                if (ptr - cmdline + len + 2 < COMMAND_LINE_SIZE) {
+                        *ptr++ = ' ';
+                        memcpy(ptr, fdt_cmdline, len);
+                        ptr += len;
+                }
+        }
+        *ptr = '\0';
+
+        setprop_string(fdt, "/chosen", "bootargs", cmdline);
+}
+
 /*
  * Convert and fold provided ATAGs into the provided FDT.
  *
@@ -72,8 +120,18 @@ int atags_to_fdt(void *atag_list, void *fdt, int total_space)
 
         for_each_tag(atag, atag_list) {
                 if (atag->hdr.tag == ATAG_CMDLINE) {
-                        setprop_string(fdt, "/chosen", "bootargs",
-                                        atag->u.cmdline.cmdline);
+                        /* Append the ATAGS command line to the device tree
+                         * command line.
+                         * NB: This means that if the same parameter is set in
+                         * the device tree and in the tags, the one from the
+                         * tags will be chosen.
+                         */
+                        if (do_extend_cmdline)
+                                merge_fdt_bootargs(fdt,
+                                                   atag->u.cmdline.cmdline);
+                        else
+                                setprop_string(fdt, "/chosen", "bootargs",
+                                               atag->u.cmdline.cmdline);
                 } else if (atag->hdr.tag == ATAG_MEM) {
                         if (memcount >= sizeof(mem_reg_property)/4)
                                 continue;
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 10dcec7e7321..f7b84aced654 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -43,8 +43,8 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 8 0x04
-                              0 9 0x04>;
+                interrupts = <0 6 0x04
+                              0 7 0x04>;
         };
 
         L2: l2-cache {
@@ -119,8 +119,8 @@
                 gmac0: eth@e2000000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe2000000 0x8000>;
-                        interrupts = <0 23 0x4
-                                      0 24 0x4>;
+                        interrupts = <0 33 0x4
+                                      0 34 0x4>;
                         interrupt-names = "macirq", "eth_wake_irq";
                         status = "disabled";
                 };
@@ -202,6 +202,7 @@
                         kbd@e0300000 {
                                 compatible = "st,spear300-kbd";
                                 reg = <0xe0300000 0x1000>;
+                                interrupts = <0 52 0x4>;
                                 status = "disabled";
                         };
 
@@ -224,7 +225,7 @@
                         serial@e0000000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0xe0000000 0x1000>;
-                                interrupts = <0 36 0x4>;
+                                interrupts = <0 35 0x4>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index c13fd1f3b09f..e4e912f95024 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -15,8 +15,8 @@
 /include/ "spear320.dtsi"
 
 / {
-        model = "ST SPEAr300 Evaluation Board";
-        compatible = "st,spear300-evb", "st,spear300";
+        model = "ST SPEAr320 Evaluation Board";
+        compatible = "st,spear320-evb", "st,spear320";
         #address-cells = <1>;
         #size-cells = <1>;
 
@@ -26,7 +26,7 @@
 
         ahb {
                 pinmux@b3000000 {
-                        st,pinmux-mode = <3>;
+                        st,pinmux-mode = <4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&state_default>;
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 089f0a42c50e..a3c36e47d7ef 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -181,6 +181,7 @@
                         timer@f0000000 {
                                 compatible = "st,spear-timer";
                                 reg = <0xf0000000 0x400>;
+                                interrupt-parent = <&vic0>;
                                 interrupts = <16>;
                         };
                 };
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9854ff4279e0..11828e632532 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -176,7 +176,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h
index ed2e95d46e29..62e75475e57e 100644
--- a/arch/arm/include/asm/arch_timer.h
+++ b/arch/arm/include/asm/arch_timer.h
@@ -1,7 +1,10 @@
 #ifndef __ASMARM_ARCH_TIMER_H
 #define __ASMARM_ARCH_TIMER_H
 
+#include <asm/errno.h>
+
 #ifdef CONFIG_ARM_ARCH_TIMER
+#define ARCH_HAS_READ_CURRENT_TIMER
 int arch_timer_of_register(void);
 int arch_timer_sched_clock_init(void);
 #else
diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
index b2deda181549..dc6145120de3 100644
--- a/arch/arm/include/asm/delay.h
+++ b/arch/arm/include/asm/delay.h
@@ -6,9 +6,22 @@
 #ifndef __ASM_ARM_DELAY_H
 #define __ASM_ARM_DELAY_H
 
+#include <asm/memory.h>
 #include <asm/param.h>  /* HZ */
 
-extern void __delay(int loops);
+#define MAX_UDELAY_MS   2
+#define UDELAY_MULT     ((UL(2199023) * HZ) >> 11)
+#define UDELAY_SHIFT    30
+
+#ifndef __ASSEMBLY__
+
+extern struct arm_delay_ops {
+        void (*delay)(unsigned long);
+        void (*const_udelay)(unsigned long);
+        void (*udelay)(unsigned long);
+} arm_delay_ops;
+
+#define __delay(n)              arm_delay_ops.delay(n)
 
 /*
  * This function intentionally does not exist; if you see references to
@@ -23,22 +36,27 @@ extern void __bad_udelay(void);
  * division by multiplication: you don't have to worry about
  * loss of precision.
  *
- * Use only for very small delays ( < 1 msec).  Should probably use a
+ * Use only for very small delays ( < 2 msec).  Should probably use a
  * lookup table, really, as the multiplications take much too long with
  * short delays.  This is a "reasonable" implementation, though (and the
  * first constant multiplications gets optimized away if the delay is
  * a constant)
  */
-extern void __udelay(unsigned long usecs);
-extern void __const_udelay(unsigned long);
-
-#define MAX_UDELAY_MS 2
+#define __udelay(n)             arm_delay_ops.udelay(n)
+#define __const_udelay(n)       arm_delay_ops.const_udelay(n)
 
 #define udelay(n)                                                       \
         (__builtin_constant_p(n) ?                                      \
           ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() :              \
-                        __const_udelay((n) * ((2199023U*HZ)>>11))) :    \
+                        __const_udelay((n) * UDELAY_MULT)) :            \
           __udelay(n))
 
+/* Loop-based definitions for assembly code. */
+extern void __loop_delay(unsigned long loops);
+extern void __loop_udelay(unsigned long usecs);
+extern void __loop_const_udelay(unsigned long);
+
+#endif /* __ASSEMBLY__ */
+
 #endif /* defined(_ARM_DELAY_H) */
 
diff --git a/arch/arm/include/asm/locks.h b/arch/arm/include/asm/locks.h
deleted file mode 100644
index ef4c897772d1..000000000000
--- a/arch/arm/include/asm/locks.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- *  arch/arm/include/asm/locks.h
- *
- *  Copyright (C) 2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *  Interrupt safe locking assembler. 
- */
-#ifndef __ASM_PROC_LOCKS_H
-#define __ASM_PROC_LOCKS_H
-
-#if __LINUX_ARM_ARCH__ >= 6
-
-#define __down_op(ptr,fail)                     \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op\n"                           \
-"1:     ldrex   lr, [%0]\n"                     \
-"       sub     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movmi   ip, %0\n"                       \
-"       blmi    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_ret(ptr,fail)                 \
-        ({                                      \
-                unsigned int ret;               \
-        __asm__ __volatile__(                   \
-        "@ down_op_ret\n"                       \
-"1:     ldrex   lr, [%1]\n"                     \
-"       sub     lr, lr, %2\n"                   \
-"       strex   ip, lr, [%1]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movmi   ip, %1\n"                       \
-"       movpl   ip, #0\n"                       \
-"       blmi    " #fail "\n"                    \
-"       mov     %0, ip"                         \
-        : "=&r" (ret)                           \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        ret;                                    \
-        })
-
-#define __up_op(ptr,wake)                       \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op\n"                             \
-"1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       cmp     lr, #0\n"                       \
-"       movle   ip, %0\n"                       \
-"       blle    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)               \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op_write\n"                     \
-"1:     ldrex   lr, [%0]\n"                     \
-"       sub     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       movne   ip, %0\n"                       \
-"       blne    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __up_op_write(ptr,wake)                 \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_write\n"                       \
-"1:     ldrex   lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       movcs   ip, %0\n"                       \
-"       blcs    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        })
-
-#define __down_op_read(ptr,fail)                \
-        __down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)                  \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
-"1:     ldrex   lr, [%0]\n"                     \
-"       add     lr, lr, %1\n"                   \
-"       strex   ip, lr, [%0]\n"                 \
-"       teq     ip, #0\n"                       \
-"       bne     1b\n"                           \
-"       teq     lr, #0\n"                       \
-"       moveq   ip, %0\n"                       \
-"       bleq    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-#else
-
-#define __down_op(ptr,fail)                     \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op\n"                           \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       subs    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movmi   ip, %0\n"                       \
-"       blmi    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_ret(ptr,fail)                 \
-        ({                                      \
-                unsigned int ret;               \
-        __asm__ __volatile__(                   \
-        "@ down_op_ret\n"                       \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%1]\n"                     \
-"       subs    lr, lr, %2\n"                   \
-"       str     lr, [%1]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movmi   ip, %1\n"                       \
-"       movpl   ip, #0\n"                       \
-"       blmi    " #fail "\n"                    \
-"       mov     %0, ip"                         \
-        : "=&r" (ret)                           \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        ret;                                    \
-        })
-
-#define __up_op(ptr,wake)                       \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op\n"                             \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movle   ip, %0\n"                       \
-"       blle    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-/*
- * The value 0x01000000 supports up to 128 processors and
- * lots of processes.  BIAS must be chosen such that sub'ing
- * BIAS once per CPU will result in the long remaining
- * negative.
- */
-#define RW_LOCK_BIAS      0x01000000
-#define RW_LOCK_BIAS_STR "0x01000000"
-
-#define __down_op_write(ptr,fail)               \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ down_op_write\n"                     \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       subs    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movne   ip, %0\n"                       \
-"       blne    " #fail                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __up_op_write(ptr,wake)                 \
-        ({                                      \
-        __asm__ __volatile__(                   \
-        "@ up_op_write\n"                       \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       movcs   ip, %0\n"                       \
-"       blcs    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
-        : "ip", "lr", "cc");                    \
-        smp_mb();                               \
-        })
-
-#define __down_op_read(ptr,fail)                \
-        __down_op(ptr, fail)
-
-#define __up_op_read(ptr,wake)                  \
-        ({                                      \
-        smp_mb();                               \
-        __asm__ __volatile__(                   \
-        "@ up_op_read\n"                        \
-"       mrs     ip, cpsr\n"                     \
-"       orr     lr, ip, #128\n"                 \
-"       msr     cpsr_c, lr\n"                   \
-"       ldr     lr, [%0]\n"                     \
-"       adds    lr, lr, %1\n"                   \
-"       str     lr, [%0]\n"                     \
-"       msr     cpsr_c, ip\n"                   \
-"       moveq   ip, %0\n"                       \
-"       bleq    " #wake                         \
-        :                                       \
-        : "r" (ptr), "I" (1)                    \
-        : "ip", "lr", "cc");                    \
-        })
-
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index fcb575747e5e..e965f1b560f1 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -16,7 +16,7 @@
 #include <linux/compiler.h>
 #include <linux/const.h>
 #include <linux/types.h>
-#include <asm/sizes.h>
+#include <linux/sizes.h>
 
 #ifdef CONFIG_NEED_MACH_MEMORY_H
 #include <mach/memory.h>
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index 00cbe10a50e3..e074948d8143 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,21 +12,6 @@
 #ifndef __ARM_PERF_EVENT_H__
 #define __ARM_PERF_EVENT_H__
 
-/* ARM perf PMU IDs for use by internal perf clients. */
-enum arm_perf_pmu_ids {
-        ARM_PERF_PMU_ID_XSCALE1 = 0,
-        ARM_PERF_PMU_ID_XSCALE2,
-        ARM_PERF_PMU_ID_V6,
-        ARM_PERF_PMU_ID_V6MP,
-        ARM_PERF_PMU_ID_CA8,
-        ARM_PERF_PMU_ID_CA9,
-        ARM_PERF_PMU_ID_CA5,
-        ARM_PERF_PMU_ID_CA15,
-        ARM_PERF_PMU_ID_CA7,
-        ARM_NUM_PMU_IDS,
-};
-
-extern enum arm_perf_pmu_ids
-armpmu_get_pmu_id(void);
+/* Nothing to see here... */
 
 #endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 90114faa9f3c..4432305f4a2a 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -103,10 +103,9 @@ struct pmu_hw_events {
 
 struct arm_pmu {
         struct pmu      pmu;
-        enum arm_perf_pmu_ids id;
         enum arm_pmu_type type;
         cpumask_t       active_irqs;
-        const char      *name;
+        char            *name;
         irqreturn_t     (*handle_irq)(int irq_num, void *dev);
         void            (*enable)(struct hw_perf_event *evt, int idx);
         void            (*disable)(struct hw_perf_event *evt, int idx);
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index 65fa3c88095c..b4ca707d0a69 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -59,18 +59,13 @@ static inline void dsb_sev(void)
 }
 
 /*
- * ARMv6 Spin-locking.
+ * ARMv6 ticket-based spin-locking.
  *
- * We exclusively read the old value.  If it is zero, we may have
- * won the lock, so we try exclusively storing it.  A memory barrier
- * is required after we get a lock, and before we release it, because
- * V6 CPUs are assumed to have weakly ordered memory.
- *
- * Unlocked value: 0
- * Locked value: 1
+ * A memory barrier is required after we get a lock, and before we
+ * release it, because V6 CPUs are assumed to have weakly ordered
+ * memory.
  */
 
-#define arch_spin_is_locked(x)          ((x)->lock != 0)
 #define arch_spin_unlock_wait(lock) \
         do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
 
@@ -79,31 +74,39 @@ static inline void dsb_sev(void)
 static inline void arch_spin_lock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
+        u32 newval;
+        arch_spinlock_t lockval;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-        WFE("ne")
-"       strexeq %0, %2, [%1]\n"
-"       teqeq   %0, #0\n"
+"1:     ldrex   %0, [%3]\n"
+"       add     %1, %0, %4\n"
+"       strex   %2, %1, [%3]\n"
+"       teq     %2, #0\n"
 "       bne     1b"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
+        : "=&r" (lockval), "=&r" (newval), "=&r" (tmp)
+        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
         : "cc");
 
+        while (lockval.tickets.next != lockval.tickets.owner) {
+                wfe();
+                lockval.tickets.owner = ACCESS_ONCE(lock->tickets.owner);
+        }
+
         smp_mb();
 }
 
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
 {
         unsigned long tmp;
+        u32 slock;
 
         __asm__ __volatile__(
-"       ldrex   %0, [%1]\n"
-"       teq     %0, #0\n"
-"       strexeq %0, %2, [%1]"
-        : "=&r" (tmp)
-        : "r" (&lock->lock), "r" (1)
+"       ldrex   %0, [%2]\n"
+"       subs    %1, %0, %0, ror #16\n"
+"       addeq   %0, %0, %3\n"
+"       strexeq %1, %0, [%2]"
+        : "=&r" (slock), "=&r" (tmp)
+        : "r" (&lock->slock), "I" (1 << TICKET_SHIFT)
         : "cc");
 
         if (tmp == 0) {
@@ -116,17 +119,38 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
 
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
+        unsigned long tmp;
+        u32 slock;
+
         smp_mb();
 
         __asm__ __volatile__(
-"       str     %1, [%0]\n"
-        :
-        : "r" (&lock->lock), "r" (0)
+"       mov     %1, #1\n"
+"1:     ldrex   %0, [%2]\n"
+"       uadd16  %0, %0, %1\n"
+"       strex   %1, %0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (slock), "=&r" (tmp)
+        : "r" (&lock->slock)
         : "cc");
 
         dsb_sev();
 }
 
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+        struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+        return tickets.owner != tickets.next;
+}
+
+static inline int arch_spin_is_contended(arch_spinlock_t *lock)
+{
+        struct __raw_tickets tickets = ACCESS_ONCE(lock->tickets);
+        return (tickets.next - tickets.owner) > 1;
+}
+#define arch_spin_is_contended  arch_spin_is_contended
+
 /*
  * RWLOCKS
  *
@@ -158,7 +182,7 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
         unsigned long tmp;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%1]\n"
+"       ldrex   %0, [%1]\n"
 "       teq     %0, #0\n"
 "       strexeq %0, %2, [%1]"
         : "=&r" (tmp)
@@ -244,7 +268,7 @@ static inline int arch_read_trylock(arch_rwlock_t *rw)
         unsigned long tmp, tmp2 = 1;
 
         __asm__ __volatile__(
-"1:     ldrex   %0, [%2]\n"
+"       ldrex   %0, [%2]\n"
 "       adds    %0, %0, #1\n"
 "       strexpl %1, %0, [%2]\n"
         : "=&r" (tmp), "+r" (tmp2)
diff --git a/arch/arm/include/asm/spinlock_types.h b/arch/arm/include/asm/spinlock_types.h
index d14d197ae04a..b262d2f8b478 100644
--- a/arch/arm/include/asm/spinlock_types.h
+++ b/arch/arm/include/asm/spinlock_types.h
@@ -5,11 +5,24 @@
 # error "please don't include this file directly"
 #endif
 
+#define TICKET_SHIFT    16
+
 typedef struct {
-        volatile unsigned int lock;
+        union {
+                u32 slock;
+                struct __raw_tickets {
+#ifdef __ARMEB__
+                        u16 next;
+                        u16 owner;
+#else
+                        u16 owner;
+                        u16 next;
+#endif
+                } tickets;
+        };
 } arch_spinlock_t;
 
-#define __ARCH_SPIN_LOCK_UNLOCKED       { 0 }
+#define __ARCH_SPIN_LOCK_UNLOCKED       { { 0 } }
 
 typedef struct {
         volatile unsigned int lock;
diff --git a/arch/arm/include/asm/timex.h b/arch/arm/include/asm/timex.h
index 3be8de3adaba..ce119442277c 100644
--- a/arch/arm/include/asm/timex.h
+++ b/arch/arm/include/asm/timex.h
@@ -12,13 +12,15 @@
 #ifndef _ASMARM_TIMEX_H
 #define _ASMARM_TIMEX_H
 
+#include <asm/arch_timer.h>
 #include <mach/timex.h>
 
 typedef unsigned long cycles_t;
 
-static inline cycles_t get_cycles (void)
-{
-        return 0;
-}
+#ifdef ARCH_HAS_READ_CURRENT_TIMER
+#define get_cycles()    ({ cycles_t c; read_current_timer(&c) ? 0 : c; })
+#else
+#define get_cycles()    (0)
+#endif
 
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 71f6536d17ac..479a6352e0b5 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -189,6 +189,9 @@ static inline void set_fs(mm_segment_t fs)
 
 #define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
 
+#define user_addr_max() \
+        (segment_eq(get_fs(), USER_DS) ? TASK_SIZE : ~0UL)
+
 /*
  * The "__xxx" versions of the user access functions do not verify the
  * address space - it must have been done previously with a separate
@@ -398,9 +401,6 @@ extern unsigned long __must_check __clear_user_std(void __user *addr, unsigned l
 #define __clear_user(addr,n)            (memset((void __force *)addr, 0, n), 0)
 #endif
 
-extern unsigned long __must_check __strncpy_from_user(char *to, const char __user *from, unsigned long count);
-extern unsigned long __must_check __strnlen_user(const char __user *s, long n);
-
 static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n)
 {
         if (access_ok(VERIFY_READ, from, n))
@@ -427,24 +427,9 @@ static inline unsigned long __must_check clear_user(void __user *to, unsigned lo
         return n;
 }
 
-static inline long __must_check strncpy_from_user(char *dst, const char __user *src, long count)
-{
-        long res = -EFAULT;
-        if (access_ok(VERIFY_READ, src, 1))
-                res = __strncpy_from_user(dst, src, count);
-        return res;
-}
-
-#define strlen_user(s)  strnlen_user(s, ~0UL >> 1)
+extern long strncpy_from_user(char *dest, const char __user *src, long count);
 
-static inline long __must_check strnlen_user(const char __user *s, long n)
-{
-        unsigned long res = 0;
-
-        if (__addr_ok(s))
-                res = __strnlen_user(s, n);
-
-        return res;
-}
+extern __must_check long strlen_user(const char __user *str);
+extern __must_check long strnlen_user(const char __user *str, long n);
 
 #endif /* _ASMARM_UACCESS_H */
diff --git a/arch/arm/include/asm/word-at-a-time.h b/arch/arm/include/asm/word-at-a-time.h
new file mode 100644
index 000000000000..4d52f92967a6
--- /dev/null
+++ b/arch/arm/include/asm/word-at-a-time.h
@@ -0,0 +1,96 @@
+#ifndef __ASM_ARM_WORD_AT_A_TIME_H
+#define __ASM_ARM_WORD_AT_A_TIME_H
+
+#ifndef __ARMEB__
+
+/*
+ * Little-endian word-at-a-time zero byte handling.
+ * Heavily based on the x86 algorithm.
+ */
+#include <linux/kernel.h>
+
+struct word_at_a_time {
+        const unsigned long one_bits, high_bits;
+};
+
+#define WORD_AT_A_TIME_CONSTANTS { REPEAT_BYTE(0x01), REPEAT_BYTE(0x80) }
+
+static inline unsigned long has_zero(unsigned long a, unsigned long *bits,
+                                     const struct word_at_a_time *c)
+{
+        unsigned long mask = ((a - c->one_bits) & ~a) & c->high_bits;
+        *bits = mask;
+        return mask;
+}
+
+#define prep_zero_mask(a, bits, c) (bits)
+
+static inline unsigned long create_zero_mask(unsigned long bits)
+{
+        bits = (bits - 1) & ~bits;
+        return bits >> 7;
+}
+
+static inline unsigned long find_zero(unsigned long mask)
+{
+        unsigned long ret;
+
+#if __LINUX_ARM_ARCH__ >= 5
+        /* We have clz available. */
+        ret = fls(mask) >> 3;
+#else
+        /* (000000 0000ff 00ffff ffffff) -> ( 1 1 2 3 ) */
+        ret = (0x0ff0001 + mask) >> 23;
+        /* Fix the 1 for 00 case */
+        ret &= mask;
+#endif
+
+        return ret;
+}
+
+#ifdef CONFIG_DCACHE_WORD_ACCESS
+
+#define zero_bytemask(mask) (mask)
+
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, offset;
+
+        /* Load word from unaligned pointer addr */
+        asm(
+        "1:     ldr     %0, [%2]\n"
+        "2:\n"
+        "       .pushsection .fixup,\"ax\"\n"
+        "       .align 2\n"
+        "3:     and     %1, %2, #0x3\n"
+        "       bic     %2, %2, #0x3\n"
+        "       ldr     %0, [%2]\n"
+        "       lsl     %1, %1, #0x3\n"
+        "       lsr     %0, %0, %1\n"
+        "       b       2b\n"
+        "       .popsection\n"
+        "       .pushsection __ex_table,\"a\"\n"
+        "       .align  3\n"
+        "       .long   1b, 3b\n"
+        "       .popsection"
+        : "=&r" (ret), "=&r" (offset)
+        : "r" (addr), "Qo" (*(unsigned long *)addr));
+
+        return ret;
+}
+
+
+#endif  /* DCACHE_WORD_ACCESS */
+
+#else   /* __ARMEB__ */
+#include <asm-generic/word-at-a-time.h>
+#endif
+
+#endif /* __ASM_ARM_WORD_AT_A_TIME_H */
diff --git a/arch/arm/kernel/arch_timer.c b/arch/arm/kernel/arch_timer.c
index dd58035621f7..cf258807160d 100644
--- a/arch/arm/kernel/arch_timer.c
+++ b/arch/arm/kernel/arch_timer.c
@@ -32,6 +32,8 @@ static int arch_timer_ppi2;
 
 static struct clock_event_device __percpu **arch_timer_evt;
 
+extern void init_current_timer_delay(unsigned long freq);
+
 /*
  * Architected system timer support.
  */
@@ -137,7 +139,7 @@ static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
         /* Be safe... */
         arch_timer_disable();
 
-        clk->features = CLOCK_EVT_FEAT_ONESHOT;
+        clk->features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP;
         clk->name = "arch_sys_timer";
         clk->rating = 450;
         clk->set_mode = arch_timer_set_mode;
@@ -223,6 +225,14 @@ static cycle_t arch_counter_read(struct clocksource *cs)
         return arch_counter_get_cntpct();
 }
 
+int read_current_timer(unsigned long *timer_val)
+{
+        if (!arch_timer_rate)
+                return -ENXIO;
+        *timer_val = arch_counter_get_cntpct();
+        return 0;
+}
+
 static struct clocksource clocksource_counter = {
         .name   = "arch_sys_counter",
         .rating = 400,
@@ -296,6 +306,7 @@ static int __init arch_timer_register(void)
         if (err)
                 goto out_free_irq;
 
+        init_current_timer_delay(arch_timer_rate);
         return 0;
 
 out_free_irq:
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index b57c75e0b01f..60d3b738d420 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -49,8 +49,7 @@ extern void __aeabi_ulcmp(void);
 extern void fpundefinstr(void);
 
         /* platform dependent support */
-EXPORT_SYMBOL(__udelay);
-EXPORT_SYMBOL(__const_udelay);
+EXPORT_SYMBOL(arm_delay_ops);
 
         /* networking */
 EXPORT_SYMBOL(csum_partial);
@@ -87,10 +86,6 @@ EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(memchr);
 EXPORT_SYMBOL(__memzero);
 
-        /* user mem (segment) */
-EXPORT_SYMBOL(__strnlen_user);
-EXPORT_SYMBOL(__strncpy_from_user);
-
 #ifdef CONFIG_MMU
 EXPORT_SYMBOL(copy_page);
 
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 4afed88d250a..49d9f9305247 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -95,13 +95,7 @@ ENDPROC(ret_to_user)
 ENTRY(ret_from_fork)
         bl      schedule_tail
         get_thread_info tsk
-        ldr     r1, [tsk, #TI_FLAGS]            @ check for syscall tracing
         mov     why, #1
-        tst     r1, #_TIF_SYSCALL_WORK          @ are we tracing syscalls?
-        beq     ret_slow_syscall
-        mov     r1, sp
-        mov     r0, #1                          @ trace exit [IP = 1]
-        bl      syscall_trace
         b       ret_slow_syscall
 ENDPROC(ret_from_fork)
 
@@ -448,10 +442,9 @@ ENDPROC(vector_swi)
          * context switches, and waiting for our parent to respond.
          */
 __sys_trace:
-        mov     r2, scno
-        add     r1, sp, #S_OFF
-        mov     r0, #0                          @ trace entry [IP = 0]
-        bl      syscall_trace
+        mov     r1, scno
+        add     r0, sp, #S_OFF
+        bl      syscall_trace_enter
 
         adr     lr, BSYM(__sys_trace_return)    @ return address
         mov     scno, r0                        @ syscall number (possibly new)
@@ -463,10 +456,9 @@ __sys_trace:
 
 __sys_trace_return:
         str     r0, [sp, #S_R0 + S_OFF]!        @ save returned r0
-        mov     r2, scno
-        mov     r1, sp
-        mov     r0, #1                          @ trace exit [IP = 1]
-        bl      syscall_trace
+        mov     r1, scno
+        mov     r0, sp
+        bl      syscall_trace_exit
         b       ret_slow_syscall
 
         .align  5
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 835898e7d704..3db960e20cb8 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -55,14 +55,6 @@
         add     \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
         .endm
 
-#ifdef CONFIG_XIP_KERNEL
-#define KERNEL_START    XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
-#define KERNEL_END      _edata_loc
-#else
-#define KERNEL_START    KERNEL_RAM_VADDR
-#define KERNEL_END      _end
-#endif
-
 /*
  * Kernel startup entry point.
  * ---------------------------
@@ -218,51 +210,46 @@ __create_page_tables:
         blo     1b
 
         /*
-         * Now setup the pagetables for our kernel direct
-         * mapped region.
+         * Map our RAM from the start to the end of the kernel .bss section.
          */
-        mov     r3, pc
-        mov     r3, r3, lsr #SECTION_SHIFT
-        orr     r3, r7, r3, lsl #SECTION_SHIFT
-        add     r0, r4,  #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
-        str     r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
-        ldr     r6, =(KERNEL_END - 1)
-        add     r0, r0, #1 << PMD_ORDER
+        add     r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER)
+        ldr     r6, =(_end - 1)
+        orr     r3, r8, r7
         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
-1:      cmp     r0, r6
+1:      str     r3, [r0], #1 << PMD_ORDER
         add     r3, r3, #1 << SECTION_SHIFT
-        strls   r3, [r0], #1 << PMD_ORDER
+        cmp     r0, r6
         bls     1b
 
 #ifdef CONFIG_XIP_KERNEL
         /*
-         * Map some ram to cover our .data and .bss areas.
+         * Map the kernel image separately as it is not located in RAM.
          */
-        add     r3, r8, #TEXT_OFFSET
-        orr     r3, r3, r7
-        add     r0, r4,  #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
-        str     r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
-        ldr     r6, =(_end - 1)
-        add     r0, r0, #4
+#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
+        mov     r3, pc
+        mov     r3, r3, lsr #SECTION_SHIFT
+        orr     r3, r7, r3, lsl #SECTION_SHIFT
+        add     r0, r4,  #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
+        str     r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
+        ldr     r6, =(_edata_loc - 1)
+        add     r0, r0, #1 << PMD_ORDER
         add     r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
 1:      cmp     r0, r6
-        add     r3, r3, #1 << 20
-        strls   r3, [r0], #4
+        add     r3, r3, #1 << SECTION_SHIFT
+        strls   r3, [r0], #1 << PMD_ORDER
         bls     1b
 #endif
 
         /*
-         * Then map boot params address in r2 or the first 1MB (2MB with LPAE)
-         * of ram if boot params address is not specified.
+         * Then map boot params address in r2 if specified.
          */
         mov     r0, r2, lsr #SECTION_SHIFT
         movs    r0, r0, lsl #SECTION_SHIFT
-        moveq   r0, r8
-        sub     r3, r0, r8
-        add     r3, r3, #PAGE_OFFSET
-        add     r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
-        orr     r6, r7, r0
-        str     r6, [r3]
+        subne   r3, r0, r8
+        addne   r3, r3, #PAGE_OFFSET
+        addne   r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
+        orrne   r6, r7, r0
+        strne   r6, [r3]
 
 #ifdef CONFIG_DEBUG_LL
 #if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING)
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index a02eada3aa5d..ab243b87118d 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -47,17 +47,14 @@ static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
 /* Set at runtime when we know what CPU type we are. */
 static struct arm_pmu *cpu_pmu;
 
-enum arm_perf_pmu_ids
-armpmu_get_pmu_id(void)
+const char *perf_pmu_name(void)
 {
-        int id = -ENODEV;
-
-        if (cpu_pmu != NULL)
-                id = cpu_pmu->id;
+        if (!cpu_pmu)
+                return NULL;
 
-        return id;
+        return cpu_pmu->pmu.name;
 }
-EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
+EXPORT_SYMBOL_GPL(perf_pmu_name);
 
 int perf_num_counters(void)
 {
@@ -760,7 +757,7 @@ init_hw_perf_events(void)
                         cpu_pmu->name, cpu_pmu->num_events);
                 cpu_pmu_init(cpu_pmu);
                 register_cpu_notifier(&pmu_cpu_notifier);
-                armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
+                armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
         } else {
                 pr_info("no hardware support available\n");
         }
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index ab627a740fa3..c90fcb2b6967 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -650,7 +650,6 @@ static int armv6_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu armv6pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6,
         .name                   = "v6",
         .handle_irq             = armv6pmu_handle_irq,
         .enable                 = armv6pmu_enable_event,
@@ -685,7 +684,6 @@ static int armv6mpcore_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu armv6mpcore_pmu = {
-        .id                     = ARM_PERF_PMU_ID_V6MP,
         .name                   = "v6mpcore",
         .handle_irq             = armv6pmu_handle_irq,
         .enable                 = armv6pmu_enable_event,
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index d3c536068162..f04070bd2183 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1258,7 +1258,6 @@ static u32 __init armv7_read_num_pmnc_events(void)
 
 static struct arm_pmu *__init armv7_a8_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA8;
         armv7pmu.name           = "ARMv7 Cortex-A8";
         armv7pmu.map_event      = armv7_a8_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1267,7 +1266,6 @@ static struct arm_pmu *__init armv7_a8_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a9_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA9;
         armv7pmu.name           = "ARMv7 Cortex-A9";
         armv7pmu.map_event      = armv7_a9_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1276,7 +1274,6 @@ static struct arm_pmu *__init armv7_a9_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a5_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA5;
         armv7pmu.name           = "ARMv7 Cortex-A5";
         armv7pmu.map_event      = armv7_a5_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1285,7 +1282,6 @@ static struct arm_pmu *__init armv7_a5_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a15_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA15;
         armv7pmu.name           = "ARMv7 Cortex-A15";
         armv7pmu.map_event      = armv7_a15_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
@@ -1295,7 +1291,6 @@ static struct arm_pmu *__init armv7_a15_pmu_init(void)
 
 static struct arm_pmu *__init armv7_a7_pmu_init(void)
 {
-        armv7pmu.id             = ARM_PERF_PMU_ID_CA7;
         armv7pmu.name           = "ARMv7 Cortex-A7";
         armv7pmu.map_event      = armv7_a7_map_event;
         armv7pmu.num_events     = armv7_read_num_pmnc_events();
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index e34e7254e652..f759fe0bab63 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -435,7 +435,6 @@ static int xscale_map_event(struct perf_event *event)
 }
 
 static struct arm_pmu xscale1pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE1,
         .name           = "xscale1",
         .handle_irq     = xscale1pmu_handle_irq,
         .enable         = xscale1pmu_enable_event,
@@ -803,7 +802,6 @@ xscale2pmu_write_counter(int counter, u32 val)
 }
 
 static struct arm_pmu xscale2pmu = {
-        .id             = ARM_PERF_PMU_ID_XSCALE2,
         .name           = "xscale2",
         .handle_irq     = xscale2pmu_handle_irq,
         .enable         = xscale2pmu_enable_event,
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 14e38261cd31..dab711e6e1ca 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -907,16 +907,16 @@ long arch_ptrace(struct task_struct *child, long request,
         return ret;
 }
 
-asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
+enum ptrace_syscall_dir {
+        PTRACE_SYSCALL_ENTER = 0,
+        PTRACE_SYSCALL_EXIT,
+};
+
+static int ptrace_syscall_trace(struct pt_regs *regs, int scno,
+                                enum ptrace_syscall_dir dir)
 {
         unsigned long ip;
 
-        if (why)
-                audit_syscall_exit(regs);
-        else
-                audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0,
-                                    regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
-
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
                 return scno;
 
@@ -927,14 +927,28 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
          * IP = 0 -> entry, =1 -> exit
          */
         ip = regs->ARM_ip;
-        regs->ARM_ip = why;
+        regs->ARM_ip = dir;
 
-        if (why)
+        if (dir == PTRACE_SYSCALL_EXIT)
                 tracehook_report_syscall_exit(regs, 0);
         else if (tracehook_report_syscall_entry(regs))
                 current_thread_info()->syscall = -1;
 
         regs->ARM_ip = ip;
-
         return current_thread_info()->syscall;
 }
+
+asmlinkage int syscall_trace_enter(struct pt_regs *regs, int scno)
+{
+        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_ENTER);
+        audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0, regs->ARM_r1,
+                            regs->ARM_r2, regs->ARM_r3);
+        return ret;
+}
+
+asmlinkage int syscall_trace_exit(struct pt_regs *regs, int scno)
+{
+        int ret = ptrace_syscall_trace(regs, scno, PTRACE_SYSCALL_EXIT);
+        audit_syscall_exit(regs);
+        return ret;
+}
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 8200deaa14f6..198b08456e90 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -17,11 +17,190 @@
 #include <linux/percpu.h>
 #include <linux/node.h>
 #include <linux/nodemask.h>
+#include <linux/of.h>
 #include <linux/sched.h>
+#include <linux/slab.h>
 
 #include <asm/cputype.h>
 #include <asm/topology.h>
 
+/*
+ * cpu power scale management
+ */
+
+/*
+ * cpu power table
+ * This per cpu data structure describes the relative capacity of each core.
+ * On a heteregenous system, cores don't have the same computation capacity
+ * and we reflect that difference in the cpu_power field so the scheduler can
+ * take this difference into account during load balance. A per cpu structure
+ * is preferred because each CPU updates its own cpu_power field during the
+ * load balance except for idle cores. One idle core is selected to run the
+ * rebalance_domains for all idle cores and the cpu_power can be updated
+ * during this sequence.
+ */
+static DEFINE_PER_CPU(unsigned long, cpu_scale);
+
+unsigned long arch_scale_freq_power(struct sched_domain *sd, int cpu)
+{
+        return per_cpu(cpu_scale, cpu);
+}
+
+static void set_power_scale(unsigned int cpu, unsigned long power)
+{
+        per_cpu(cpu_scale, cpu) = power;
+}
+
+#ifdef CONFIG_OF
+struct cpu_efficiency {
+        const char *compatible;
+        unsigned long efficiency;
+};
+
+/*
+ * Table of relative efficiency of each processors
+ * The efficiency value must fit in 20bit and the final
+ * cpu_scale value must be in the range
+ *   0 < cpu_scale < 3*SCHED_POWER_SCALE/2
+ * in order to return at most 1 when DIV_ROUND_CLOSEST
+ * is used to compute the capacity of a CPU.
+ * Processors that are not defined in the table,
+ * use the default SCHED_POWER_SCALE value for cpu_scale.
+ */
+struct cpu_efficiency table_efficiency[] = {
+        {"arm,cortex-a15", 3891},
+        {"arm,cortex-a7",  2048},
+        {NULL, },
+};
+
+struct cpu_capacity {
+        unsigned long hwid;
+        unsigned long capacity;
+};
+
+struct cpu_capacity *cpu_capacity;
+
+unsigned long middle_capacity = 1;
+
+/*
+ * Iterate all CPUs' descriptor in DT and compute the efficiency
+ * (as per table_efficiency). Also calculate a middle efficiency
+ * as close as possible to  (max{eff_i} - min{eff_i}) / 2
+ * This is later used to scale the cpu_power field such that an
+ * 'average' CPU is of middle power. Also see the comments near
+ * table_efficiency[] and update_cpu_power().
+ */
+static void __init parse_dt_topology(void)
+{
+        struct cpu_efficiency *cpu_eff;
+        struct device_node *cn = NULL;
+        unsigned long min_capacity = (unsigned long)(-1);
+        unsigned long max_capacity = 0;
+        unsigned long capacity = 0;
+        int alloc_size, cpu = 0;
+
+        alloc_size = nr_cpu_ids * sizeof(struct cpu_capacity);
+        cpu_capacity = (struct cpu_capacity *)kzalloc(alloc_size, GFP_NOWAIT);
+
+        while ((cn = of_find_node_by_type(cn, "cpu"))) {
+                const u32 *rate, *reg;
+                int len;
+
+                if (cpu >= num_possible_cpus())
+                        break;
+
+                for (cpu_eff = table_efficiency; cpu_eff->compatible; cpu_eff++)
+                        if (of_device_is_compatible(cn, cpu_eff->compatible))
+                                break;
+
+                if (cpu_eff->compatible == NULL)
+                        continue;
+
+                rate = of_get_property(cn, "clock-frequency", &len);
+                if (!rate || len != 4) {
+                        pr_err("%s missing clock-frequency property\n",
+                                cn->full_name);
+                        continue;
+                }
+
+                reg = of_get_property(cn, "reg", &len);
+                if (!reg || len != 4) {
+                        pr_err("%s missing reg property\n", cn->full_name);
+                        continue;
+                }
+
+                capacity = ((be32_to_cpup(rate)) >> 20) * cpu_eff->efficiency;
+
+                /* Save min capacity of the system */
+                if (capacity < min_capacity)
+                        min_capacity = capacity;
+
+                /* Save max capacity of the system */
+                if (capacity > max_capacity)
+                        max_capacity = capacity;
+
+                cpu_capacity[cpu].capacity = capacity;
+                cpu_capacity[cpu++].hwid = be32_to_cpup(reg);
+        }
+
+        if (cpu < num_possible_cpus())
+                cpu_capacity[cpu].hwid = (unsigned long)(-1);
+
+        /* If min and max capacities are equals, we bypass the update of the
+         * cpu_scale because all CPUs have the same capacity. Otherwise, we
+         * compute a middle_capacity factor that will ensure that the capacity
+         * of an 'average' CPU of the system will be as close as possible to
+         * SCHED_POWER_SCALE, which is the default value, but with the
+         * constraint explained near table_efficiency[].
+         */
+        if (min_capacity == max_capacity)
+                cpu_capacity[0].hwid = (unsigned long)(-1);
+        else if (4*max_capacity < (3*(max_capacity + min_capacity)))
+                middle_capacity = (min_capacity + max_capacity)
+                                >> (SCHED_POWER_SHIFT+1);
+        else
+                middle_capacity = ((max_capacity / 3)
+                                >> (SCHED_POWER_SHIFT-1)) + 1;
+
+}
+
+/*
+ * Look for a customed capacity of a CPU in the cpu_capacity table during the
+ * boot. The update of all CPUs is in O(n^2) for heteregeneous system but the
+ * function returns directly for SMP system.
+ */
+void update_cpu_power(unsigned int cpu, unsigned long hwid)
+{
+        unsigned int idx = 0;
+
+        /* look for the cpu's hwid in the cpu capacity table */
+        for (idx = 0; idx < num_possible_cpus(); idx++) {
+                if (cpu_capacity[idx].hwid == hwid)
+                        break;
+
+                if (cpu_capacity[idx].hwid == -1)
+                        return;
+        }
+
+        if (idx == num_possible_cpus())
+                return;
+
+        set_power_scale(cpu, cpu_capacity[idx].capacity / middle_capacity);
+
+        printk(KERN_INFO "CPU%u: update cpu_power %lu\n",
+                cpu, arch_scale_freq_power(NULL, cpu));
+}
+
+#else
+static inline void parse_dt_topology(void) {}
+static inline void update_cpu_power(unsigned int cpuid, unsigned int mpidr) {}
+#endif
+
+
+/*
+ * cpu topology management
+ */
+
 #define MPIDR_SMP_BITMASK (0x3 << 30)
 #define MPIDR_SMP_VALUE (0x2 << 30)
 
@@ -31,6 +210,7 @@
  * These masks reflect the current use of the affinity levels.
  * The affinity level can be up to 16 bits according to ARM ARM
  */
+#define MPIDR_HWID_BITMASK 0xFFFFFF
 
 #define MPIDR_LEVEL0_MASK 0x3
 #define MPIDR_LEVEL0_SHIFT 0
@@ -41,6 +221,9 @@
 #define MPIDR_LEVEL2_MASK 0xFF
 #define MPIDR_LEVEL2_SHIFT 16
 
+/*
+ * cpu topology table
+ */
 struct cputopo_arm cpu_topology[NR_CPUS];
 
 const struct cpumask *cpu_coregroup_mask(int cpu)
@@ -48,6 +231,32 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
         return &cpu_topology[cpu].core_sibling;
 }
 
+void update_siblings_masks(unsigned int cpuid)
+{
+        struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
+        int cpu;
+
+        /* update core and thread sibling masks */
+        for_each_possible_cpu(cpu) {
+                cpu_topo = &cpu_topology[cpu];
+
+                if (cpuid_topo->socket_id != cpu_topo->socket_id)
+                        continue;
+
+                cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
+                if (cpu != cpuid)
+                        cpumask_set_cpu(cpu, &cpuid_topo->core_sibling);
+
+                if (cpuid_topo->core_id != cpu_topo->core_id)
+                        continue;
+
+                cpumask_set_cpu(cpuid, &cpu_topo->thread_sibling);
+                if (cpu != cpuid)
+                        cpumask_set_cpu(cpu, &cpuid_topo->thread_sibling);
+        }
+        smp_wmb();
+}
+
 /*
  * store_cpu_topology is called at boot when only one cpu is running
  * and with the mutex cpu_hotplug.lock locked, when several cpus have booted,
@@ -57,7 +266,6 @@ void store_cpu_topology(unsigned int cpuid)
 {
         struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid];
         unsigned int mpidr;
-        unsigned int cpu;
 
         /* If the cpu topology has been already set, just return */
         if (cpuid_topo->core_id != -1)
@@ -99,26 +307,9 @@ void store_cpu_topology(unsigned int cpuid)
                 cpuid_topo->socket_id = -1;
         }
 
-        /* update core and thread sibling masks */
-        for_each_possible_cpu(cpu) {
-                struct cputopo_arm *cpu_topo = &cpu_topology[cpu];
-
-                if (cpuid_topo->socket_id == cpu_topo->socket_id) {
-                        cpumask_set_cpu(cpuid, &cpu_topo->core_sibling);
-                        if (cpu != cpuid)
-                                cpumask_set_cpu(cpu,
-                                        &cpuid_topo->core_sibling);
-
-                        if (cpuid_topo->core_id == cpu_topo->core_id) {
-                                cpumask_set_cpu(cpuid,
-                                        &cpu_topo->thread_sibling);
-                                if (cpu != cpuid)
-                                        cpumask_set_cpu(cpu,
-                                                &cpuid_topo->thread_sibling);
-                        }
-                }
-        }
-        smp_wmb();
+        update_siblings_masks(cpuid);
+
+        update_cpu_power(cpuid, mpidr & MPIDR_HWID_BITMASK);
 
         printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n",
                 cpuid, cpu_topology[cpuid].thread_id,
@@ -134,7 +325,7 @@ void init_cpu_topology(void)
 {
         unsigned int cpu;
 
-        /* init core mask */
+        /* init core mask and power*/
         for_each_possible_cpu(cpu) {
                 struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]);
 
@@ -143,6 +334,10 @@ void init_cpu_topology(void)
                 cpu_topo->socket_id = -1;
                 cpumask_clear(&cpu_topo->core_sibling);
                 cpumask_clear(&cpu_topo->thread_sibling);
+
+                set_power_scale(cpu, SCHED_POWER_SCALE);
         }
         smp_wmb();
+
+        parse_dt_topology();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 3647170e9a16..8b97d739b17b 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -233,9 +233,9 @@ void show_stack(struct task_struct *tsk, unsigned long *sp)
 #define S_ISA " ARM"
 #endif
 
-static int __die(const char *str, int err, struct thread_info *thread, struct pt_regs *regs)
+static int __die(const char *str, int err, struct pt_regs *regs)
 {
-        struct task_struct *tsk = thread->task;
+        struct task_struct *tsk = current;
         static int die_counter;
         int ret;
 
@@ -245,12 +245,12 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt
         /* trap and error numbers are mostly meaningless on ARM */
         ret = notify_die(DIE_OOPS, str, regs, err, tsk->thread.trap_no, SIGSEGV);
         if (ret == NOTIFY_STOP)
-                return ret;
+                return 1;
 
         print_modules();
         __show_regs(regs);
         printk(KERN_EMERG "Process %.*s (pid: %d, stack limit = 0x%p)\n",
-                TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), thread + 1);
+                TASK_COMM_LEN, tsk->comm, task_pid_nr(tsk), end_of_stack(tsk));
 
         if (!user_mode(regs) || in_interrupt()) {
                 dump_mem(KERN_EMERG, "Stack: ", regs->ARM_sp,
@@ -259,45 +259,77 @@ static int __die(const char *str, int err, struct thread_info *thread, struct pt
                 dump_instr(KERN_EMERG, regs);
         }
 
-        return ret;
+        return 0;
 }
 
-static DEFINE_RAW_SPINLOCK(die_lock);
+static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int die_owner = -1;
+static unsigned int die_nest_count;
 
-/*
- * This function is protected against re-entrancy.
- */
-void die(const char *str, struct pt_regs *regs, int err)
+static unsigned long oops_begin(void)
 {
-        struct thread_info *thread = current_thread_info();
-        int ret;
-        enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
+        int cpu;
+        unsigned long flags;
 
         oops_enter();
 
-        raw_spin_lock_irq(&die_lock);
+        /* racy, but better than risking deadlock. */
+        raw_local_irq_save(flags);
+        cpu = smp_processor_id();
+        if (!arch_spin_trylock(&die_lock)) {
+                if (cpu == die_owner)
+                        /* nested oops. should stop eventually */;
+                else
+                        arch_spin_lock(&die_lock);
+        }
+        die_nest_count++;
+        die_owner = cpu;
         console_verbose();
         bust_spinlocks(1);
-        if (!user_mode(regs))
-                bug_type = report_bug(regs->ARM_pc, regs);
-        if (bug_type != BUG_TRAP_TYPE_NONE)
-                str = "Oops - BUG";
-        ret = __die(str, err, thread, regs);
+        return flags;
+}
 
-        if (regs && kexec_should_crash(thread->task))
+static void oops_end(unsigned long flags, struct pt_regs *regs, int signr)
+{
+        if (regs && kexec_should_crash(current))
                 crash_kexec(regs);
 
         bust_spinlocks(0);
+        die_owner = -1;
         add_taint(TAINT_DIE);
-        raw_spin_unlock_irq(&die_lock);
+        die_nest_count--;
+        if (!die_nest_count)
+                /* Nest count reaches zero, release the lock. */
+                arch_spin_unlock(&die_lock);
+        raw_local_irq_restore(flags);
         oops_exit();
 
         if (in_interrupt())
                 panic("Fatal exception in interrupt");
         if (panic_on_oops)
                 panic("Fatal exception");
-        if (ret != NOTIFY_STOP)
-                do_exit(SIGSEGV);
+        if (signr)
+                do_exit(signr);
+}
+
+/*
+ * This function is protected against re-entrancy.
+ */
+void die(const char *str, struct pt_regs *regs, int err)
+{
+        enum bug_trap_type bug_type = BUG_TRAP_TYPE_NONE;
+        unsigned long flags = oops_begin();
+        int sig = SIGSEGV;
+
+        if (!user_mode(regs))
+                bug_type = report_bug(regs->ARM_pc, regs);
+        if (bug_type != BUG_TRAP_TYPE_NONE)
+                str = "Oops - BUG";
+
+        if (__die(str, err, regs))
+                sig = 0;
+
+        oops_end(flags, regs, sig);
 }
 
 void arm_notify_die(const char *str, struct pt_regs *regs,
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 992769ae2599..2473fd1fd51c 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -6,9 +6,8 @@
 
 lib-y           := backtrace.o changebit.o csumipv6.o csumpartial.o   \
                    csumpartialcopy.o csumpartialcopyuser.o clearbit.o \
-                   delay.o findbit.o memchr.o memcpy.o                \
+                   delay.o delay-loop.o findbit.o memchr.o memcpy.o   \
                    memmove.o memset.o memzero.o setbit.o              \
-                   strncpy_from_user.o strnlen_user.o                 \
                    strchr.o strrchr.o                                 \
                    testchangebit.o testclearbit.o testsetbit.o        \
                    ashldi3.o ashrdi3.o lshrdi3.o muldi3.o             \
diff --git a/arch/arm/lib/delay.S b/arch/arm/lib/delay-loop.S
index 3c9a05c8d20b..36b668d8e121 100644
--- a/arch/arm/lib/delay.S
+++ b/arch/arm/lib/delay-loop.S
@@ -9,11 +9,11 @@
  */
 #include <linux/linkage.h>
 #include <asm/assembler.h>
-#include <asm/param.h>
+#include <asm/delay.h>
                 .text
 
 .LC0:           .word   loops_per_jiffy
-.LC1:           .word   (2199023*HZ)>>11
+.LC1:           .word   UDELAY_MULT
 
 /*
  * r0  <= 2000
@@ -21,10 +21,10 @@
  * HZ  <= 1000
  */
 
-ENTRY(__udelay)
+ENTRY(__loop_udelay)
                 ldr     r2, .LC1
                 mul     r0, r2, r0
-ENTRY(__const_udelay)                           @ 0 <= r0 <= 0x7fffff06
+ENTRY(__loop_const_udelay)                      @ 0 <= r0 <= 0x7fffff06
                 mov     r1, #-1
                 ldr     r2, .LC0
                 ldr     r2, [r2]                @ max = 0x01ffffff
@@ -39,12 +39,10 @@ ENTRY(__const_udelay)				@ 0 <= r0 <= 0x7fffff06
 
 /*
  * loops = r0 * HZ * loops_per_jiffy / 1000000
- *
- * Oh, if only we had a cycle counter...
  */
 
 @ Delay routine
-ENTRY(__delay)
+ENTRY(__loop_delay)
                 subs    r0, r0, #1
 #if 0
                 movls   pc, lr
@@ -62,8 +60,8 @@ ENTRY(__delay)
                 movls   pc, lr
                 subs    r0, r0, #1
 #endif
-                bhi     __delay
+                bhi     __loop_delay
                 mov     pc, lr
-ENDPROC(__udelay)
-ENDPROC(__const_udelay)
-ENDPROC(__delay)
+ENDPROC(__loop_udelay)
+ENDPROC(__loop_const_udelay)
+ENDPROC(__loop_delay)
diff --git a/arch/arm/lib/delay.c b/arch/arm/lib/delay.c
new file mode 100644
index 000000000000..d6dacc69254e
--- /dev/null
+++ b/arch/arm/lib/delay.c
@@ -0,0 +1,71 @@
+/*
+ * Delay loops based on the OpenRISC implementation.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/timex.h>
+
+/*
+ * Default to the loop-based delay implementation.
+ */
+struct arm_delay_ops arm_delay_ops = {
+        .delay          = __loop_delay,
+        .const_udelay   = __loop_const_udelay,
+        .udelay         = __loop_udelay,
+};
+
+#ifdef ARCH_HAS_READ_CURRENT_TIMER
+static void __timer_delay(unsigned long cycles)
+{
+        cycles_t start = get_cycles();
+
+        while ((get_cycles() - start) < cycles)
+                cpu_relax();
+}
+
+static void __timer_const_udelay(unsigned long xloops)
+{
+        unsigned long long loops = xloops;
+        loops *= loops_per_jiffy;
+        __timer_delay(loops >> UDELAY_SHIFT);
+}
+
+static void __timer_udelay(unsigned long usecs)
+{
+        __timer_const_udelay(usecs * UDELAY_MULT);
+}
+
+void __init init_current_timer_delay(unsigned long freq)
+{
+        pr_info("Switching to timer-based delay loop\n");
+        lpj_fine                        = freq / HZ;
+        arm_delay_ops.delay             = __timer_delay;
+        arm_delay_ops.const_udelay      = __timer_const_udelay;
+        arm_delay_ops.udelay            = __timer_udelay;
+}
+
+unsigned long __cpuinit calibrate_delay_is_known(void)
+{
+        return lpj_fine;
+}
+#endif
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
deleted file mode 100644
index f202d7bd1647..000000000000
--- a/arch/arm/lib/strncpy_from_user.S
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  linux/arch/arm/lib/strncpy_from_user.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/*
- * Copy a string from user space to kernel space.
- *  r0 = dst, r1 = src, r2 = byte length
- * returns the number of characters copied (strlen of copied string),
- *  -EFAULT on exception, or "len" if we fill the whole buffer
- */
-ENTRY(__strncpy_from_user)
-        mov     ip, r1
-1:      subs    r2, r2, #1
-        ldrusr  r3, r1, 1, pl
-        bmi     2f
-        strb    r3, [r0], #1
-        teq     r3, #0
-        bne     1b
-        sub     r1, r1, #1      @ take NUL character out of count
-2:      sub     r0, r1, ip
-        mov     pc, lr
-ENDPROC(__strncpy_from_user)
-
-        .pushsection .fixup,"ax"
-        .align  0
-9001:   mov     r3, #0
-        strb    r3, [r0, #0]    @ null terminate
-        mov     r0, #-EFAULT
-        mov     pc, lr
-        .popsection
-
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
deleted file mode 100644
index 0ecbb459c4f1..000000000000
--- a/arch/arm/lib/strnlen_user.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- *  linux/arch/arm/lib/strnlen_user.S
- *
- *  Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-
-        .text
-        .align  5
-
-/* Prototype: unsigned long __strnlen_user(const char *str, long n)
- * Purpose  : get length of a string in user memory
- * Params   : str - address of string in user memory
- * Returns  : length of string *including terminator*
- *            or zero on exception, or n + 1 if too long
- */
-ENTRY(__strnlen_user)
-        mov     r2, r0
-1:
-        ldrusr  r3, r0, 1
-        teq     r3, #0
-        beq     2f
-        subs    r1, r1, #1
-        bne     1b
-        add     r0, r0, #1
-2:      sub     r0, r0, r2
-        mov     pc, lr
-ENDPROC(__strnlen_user)
-
-        .pushsection .fixup,"ax"
-        .align  0
-9001:   mov     r0, #0
-        mov     pc, lr
-        .popsection
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index e9fafcf163de..373c3c00d24c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -119,7 +119,9 @@ static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
                                                 struct exynos_pm_domain *pd)
 {
         if (pdev->dev.bus) {
-                if (pm_genpd_add_device(&pd->pd, &pdev->dev))
+                if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
+                        pm_genpd_dev_need_restore(&pdev->dev, true);
+                else
                         pr_info("%s: error in adding %s device to %s power"
                                 "domain\n", __func__, dev_name(&pdev->dev),
                                 pd->name);
@@ -151,9 +153,12 @@ static __init int exynos4_pm_init_power_domain(void)
         if (of_have_populated_dt())
                 return exynos_pm_dt_parse_domains();
 
-        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++)
-                pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL,
-                                exynos4_pm_domains[idx]->is_off);
+        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
+                struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
+                int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+
+                pm_genpd_init(&pd->pd, NULL, !on);
+        }
 
 #ifdef CONFIG_S5P_DEV_FIMD0
         exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index db0117ec55f4..e012dc8391cf 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -127,7 +127,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b58609bad8..6227e9505c2d 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -31,12 +31,16 @@
  *
  * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
  *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
+ *     active whenever the MPU is active.  True for interconnects and
+ *     the WKUP clockdomains.
  */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
 #define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
+#define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 839145e1cfbe..4972219653ce 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -88,4 +88,5 @@ struct clockdomain wkup_common_clkdm = {
         .name           = "wkup_clkdm",
         .pwrdm          = { .name = "wkup_pwrdm" },
         .dep_bit        = OMAP_EN_WKUP_SHIFT,
+        .flags          = CLKDM_ACTIVE_WITH_MPU,
 };
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index c53425847493..7f2133abe7d3 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -381,7 +381,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
         .cm_inst          = OMAP4430_PRM_WKUP_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
         .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
-        .flags            = CLKDM_CAN_HWSUP,
+        .flags            = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
 };
 
 static struct clockdomain emu_sys_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index deffbf1c9627..596eb70d37be 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -111,7 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
                 booted = true;
         }
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         /*
          * Now the secondary core is starting up let it run its
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 773193670ea2..2d710f50fca2 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1124,15 +1124,18 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap
  * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
- * If module is marked as SWSUP_SIDLE, force the module out of slave
- * idle; otherwise, configure it for smart-idle.  If module is marked
- * as SWSUP_MSUSPEND, force the module out of master standby;
- * otherwise, configure it for smart-standby.  No return value.
+ * Ensure that the OCP_SYSCONFIG register for the IP block represented
+ * by @oh is set to indicate to the PRCM that the IP block is active.
+ * Usually this means placing the module into smart-idle mode and
+ * smart-standby, but if there is a bug in the automatic idle handling
+ * for the IP block, it may need to be placed into the force-idle or
+ * no-idle variants of these modes.  No return value.
  */
 static void _enable_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
+        bool clkdm_act;
 
         if (!oh->class->sysc)
                 return;
@@ -1141,8 +1144,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
         sf = oh->class->sysc->sysc_flags;
 
         if (sf & SYSC_HAS_SIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
-                        HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+                clkdm_act = ((oh->clkdm &&
+                              oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) ||
+                             (oh->_clk && oh->_clk->clkdm &&
+                              oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU));
+                if (clkdm_act && !(oh->class->sysc->idlemodes &
+                                   (SIDLE_SMART | SIDLE_SMART_WKUP)))
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+                                HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
                 _set_slave_idlemode(oh, idlemode, &v);
         }
 
@@ -1208,8 +1219,13 @@ static void _idle_sysc(struct omap_hwmod *oh)
         sf = oh->class->sysc->sysc_flags;
 
         if (sf & SYSC_HAS_SIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
-                        HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+                /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */
+                if (oh->flags & HWMOD_SWSUP_SIDLE ||
+                    !(oh->class->sysc->idlemodes &
+                      (SIDLE_SMART | SIDLE_SMART_WKUP)))
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = HWMOD_IDLEMODE_SMART;
                 _set_slave_idlemode(oh, idlemode, &v);
         }
 
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h
index a3e5f86ef67e..628819995c52 100644
--- a/arch/arm/mach-pxa/include/mach/regs-ost.h
+++ b/arch/arm/mach-pxa/include/mach/regs-ost.h
@@ -7,17 +7,17 @@
  * OS Timer & Match Registers
  */
 
-#define OSMR0           __REG(0x40A00000)  /* */
-#define OSMR1           __REG(0x40A00004)  /* */
-#define OSMR2           __REG(0x40A00008)  /* */
-#define OSMR3           __REG(0x40A0000C)  /* */
-#define OSMR4           __REG(0x40A00080)  /* */
-#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
-#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
-#define OMCR4           __REG(0x40A000C0)  /* */
-#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
-#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
-#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+#define OSMR0           io_p2v(0x40A00000)  /* */
+#define OSMR1           io_p2v(0x40A00004)  /* */
+#define OSMR2           io_p2v(0x40A00008)  /* */
+#define OSMR3           io_p2v(0x40A0000C)  /* */
+#define OSMR4           io_p2v(0x40A00080)  /* */
+#define OSCR            io_p2v(0x40A00010)  /* OS Timer Counter Register */
+#define OSCR4           io_p2v(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4           io_p2v(0x40A000C0)  /* */
+#define OSSR            io_p2v(0x40A00014)  /* OS Timer Status Register */
+#define OWER            io_p2v(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER            io_p2v(0x40A0001C)  /* OS Timer Interrupt Enable Register */
 
 #define OSSR_M3         (1 << 3)        /* Match status channel 3 */
 #define OSSR_M2         (1 << 2)        /* Match status channel 2 */
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c
index b4528899ef08..3fab583755d4 100644
--- a/arch/arm/mach-pxa/reset.c
+++ b/arch/arm/mach-pxa/reset.c
@@ -77,9 +77,10 @@ static void do_gpio_reset(void)
 static void do_hw_reset(void)
 {
         /* Initialize the watchdog and let it fire */
-        OWER = OWER_WME;
-        OSSR = OSSR_M3;
-        OSMR3 = OSCR + 368640;  /* ... in 100 ms */
+        writel_relaxed(OWER_WME, OWER);
+        writel_relaxed(OSSR_M3, OSSR);
+        /* ... in 100 ms */
+        writel_relaxed(readl_relaxed(OSCR) + 368640, OSMR3);
 }
 
 void pxa_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 3d6c9bd90de6..4bc47d63698b 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -35,7 +35,7 @@
 
 static u32 notrace pxa_read_sched_clock(void)
 {
-        return OSCR;
+        return readl_relaxed(OSCR);
 }
 
 
@@ -47,8 +47,8 @@ pxa_ost0_interrupt(int irq, void *dev_id)
         struct clock_event_device *c = dev_id;
 
         /* Disarm the compare/match, signal the event. */
-        OIER &= ~OIER_E0;
-        OSSR = OSSR_M0;
+        writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+        writel_relaxed(OSSR_M0, OSSR);
         c->event_handler(c);
 
         return IRQ_HANDLED;
@@ -59,10 +59,10 @@ pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 {
         unsigned long next, oscr;
 
-        OIER |= OIER_E0;
-        next = OSCR + delta;
-        OSMR0 = next;
-        oscr = OSCR;
+        writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
+        next = readl_relaxed(OSCR) + delta;
+        writel_relaxed(next, OSMR0);
+        oscr = readl_relaxed(OSCR);
 
         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 }
@@ -72,15 +72,15 @@ pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 {
         switch (mode) {
         case CLOCK_EVT_MODE_ONESHOT:
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
                 /* initializing, released, or preparing for suspend */
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
@@ -108,8 +108,8 @@ static void __init pxa_timer_init(void)
 {
         unsigned long clock_tick_rate = get_clock_tick_rate();
 
-        OIER = 0;
-        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
         setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
 
@@ -122,7 +122,7 @@ static void __init pxa_timer_init(void)
 
         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 
-        clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
+        clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
                 clocksource_mmio_readl_up);
         clockevents_register_device(&ckevt_pxa_osmr0);
 }
@@ -132,12 +132,12 @@ static unsigned long osmr[4], oier, oscr;
 
 static void pxa_timer_suspend(void)
 {
-        osmr[0] = OSMR0;
-        osmr[1] = OSMR1;
-        osmr[2] = OSMR2;
-        osmr[3] = OSMR3;
-        oier = OIER;
-        oscr = OSCR;
+        osmr[0] = readl_relaxed(OSMR0);
+        osmr[1] = readl_relaxed(OSMR1);
+        osmr[2] = readl_relaxed(OSMR2);
+        osmr[3] = readl_relaxed(OSMR3);
+        oier = readl_relaxed(OIER);
+        oscr = readl_relaxed(OSCR);
 }
 
 static void pxa_timer_resume(void)
@@ -151,12 +151,12 @@ static void pxa_timer_resume(void)
         if (osmr[0] - oscr < MIN_OSCR_DELTA)
                 osmr[0] += MIN_OSCR_DELTA;
 
-        OSMR0 = osmr[0];
-        OSMR1 = osmr[1];
-        OSMR2 = osmr[2];
-        OSMR3 = osmr[3];
-        OIER = oier;
-        OSCR = oscr;
+        writel_relaxed(osmr[0], OSMR0);
+        writel_relaxed(osmr[1], OSMR1);
+        writel_relaxed(osmr[2], OSMR2);
+        writel_relaxed(osmr[3], OSMR3);
+        writel_relaxed(oier, OIER);
+        writel_relaxed(oscr, OSCR);
 }
 #else
 #define pxa_timer_suspend NULL
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 414364eb426c..cb2883d553b5 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -106,7 +106,7 @@ static struct clk s3c2440_clk_cam_upll = {
 static struct clk s3c2440_clk_ac97 = {
         .name           = "ac97",
         .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
+        .ctrlbit        = S3C2440_CLKCON_AC97,
 };
 
 static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index d1dc7f1a239c..d673211f121c 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -362,7 +362,7 @@ static void __init assabet_init(void)
 static void __init map_sa1100_gpio_regs( void )
 {
         unsigned long phys = __PREG(GPLR) & PMD_MASK;
-        unsigned long virt = io_p2v(phys);
+        unsigned long virt = (unsigned long)io_p2v(phys);
         int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
         pmd_t *pmd;
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index 19b2053f5af4..e8f4d1e19233 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -87,6 +87,7 @@
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/cpufreq.h>
+#include <linux/io.h>
 
 #include <asm/cputype.h>
 
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 675bf8ef97e8..48c45b0c92bb 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -19,6 +19,7 @@
 #include <linux/cpufreq.h>
 #include <linux/delay.h>
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/moduleparam.h>
 #include <linux/types.h>
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 3f2d1b60188c..0ac6cc08a19c 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
  *                      (read/write).
  */
 
-#define OSMR0           __REG(0x90000000)  /* OS timer Match Reg. 0 */
-#define OSMR1           __REG(0x90000004)  /* OS timer Match Reg. 1 */
-#define OSMR2           __REG(0x90000008)  /* OS timer Match Reg. 2 */
-#define OSMR3           __REG(0x9000000c)  /* OS timer Match Reg. 3 */
-#define OSCR    __REG(0x90000010)  /* OS timer Counter Reg. */
-#define OSSR    __REG(0x90000014        )  /* OS timer Status Reg. */
-#define OWER    __REG(0x90000018        )  /* OS timer Watch-dog Enable Reg. */
-#define OIER    __REG(0x9000001C        )  /* OS timer Interrupt Enable Reg. */
+#define OSMR0           io_p2v(0x90000000)  /* OS timer Match Reg. 0 */
+#define OSMR1           io_p2v(0x90000004)  /* OS timer Match Reg. 1 */
+#define OSMR2           io_p2v(0x90000008)  /* OS timer Match Reg. 2 */
+#define OSMR3           io_p2v(0x9000000c)  /* OS timer Match Reg. 3 */
+#define OSCR            io_p2v(0x90000010)  /* OS timer Counter Reg. */
+#define OSSR            io_p2v(0x90000014)  /* OS timer Status Reg. */
+#define OWER            io_p2v(0x90000018)  /* OS timer Watch-dog Enable Reg. */
+#define OIER            io_p2v(0x9000001C)  /* OS timer Interrupt Enable Reg. */
 
 #define OSSR_M(Nb)                      /* Match detected [0..3]           */ \
                         (0x00000001 << (Nb))
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index a38fc4f54241..6a9eecf3137e 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -24,6 +24,7 @@
 #ifndef __ASM_ARCH_SA1100_GPIO_H
 #define __ASM_ARCH_SA1100_GPIO_H
 
+#include <linux/io.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856d8de4..cbedd75a9d65 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -32,7 +32,7 @@
 #define PIO_START       0x80000000      /* physical start of IO space */
 
 #define io_p2v( x )             \
-   ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
+   IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
 #define io_v2p( x )             \
    ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
 
@@ -47,6 +47,8 @@
 #define CPU_SA1110_ID   (0x6901b110)
 #define CPU_SA1110_MASK (0xfffffff0)
 
+#define __MREG(x)       IOMEM(io_p2v(x))
+
 #ifndef __ASSEMBLY__
 
 #include <asm/cputype.h>
@@ -56,7 +58,7 @@
 #define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
 #define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
 
-# define __REG(x)       (*((volatile unsigned long *)io_p2v(x)))
+# define __REG(x)       (*((volatile unsigned long __iomem *)io_p2v(x)))
 # define __PREG(x)      (io_v2p((unsigned long)&(x)))
 
 static inline unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 6cb39ddde656..5cf71da60e42 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -8,6 +8,8 @@
 
 #include "hardware.h"
 
+#define IOMEM(x)        (x)
+
 /*
  * The following code assumes the serial port has already been
  * initialized by the bootloader.  We search for the first enabled
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 516ccc25d7fd..2124f1fc2fbe 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -12,6 +12,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/ioport.h>
 #include <linux/syscore_ops.h>
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index b412fc09c80c..7f07f08d8968 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/sched.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <mach/jornada720.h>
diff --git a/arch/arm/mach-sa1100/leds-cerf.c b/arch/arm/mach-sa1100/leds-cerf.c
index 040540fb7d8a..30fc3b2bf555 100644
--- a/arch/arm/mach-sa1100/leds-cerf.c
+++ b/arch/arm/mach-sa1100/leds-cerf.c
@@ -4,6 +4,7 @@
  * Author: ???
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/leds-lart.c b/arch/arm/mach-sa1100/leds-lart.c
index a51830c60e53..50a5b143b460 100644
--- a/arch/arm/mach-sa1100/leds-lart.c
+++ b/arch/arm/mach-sa1100/leds-lart.c
@@ -10,6 +10,7 @@
  *  pace of the LED.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 
 #include <mach/hardware.h>
 #include <asm/leds.h>
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 690cf0ce5c0c..6645d1e31f14 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -23,6 +23,7 @@
  *                              Storage is local on the stack now.
  */
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/suspend.h>
 #include <linux/errno.h>
 #include <linux/time.h>
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 30cc6721665b..85863741ef8b 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -38,9 +38,9 @@ ENTRY(sa1100_finish_suspend)
         orr     r4, r4, #MDREFR_K1DB2
         ldr     r5, =PPCR
 
-        @ Pre-load __udelay into the I-cache
+        @ Pre-load __loop_udelay into the I-cache
         mov     r0, #1
-        bl      __udelay
+        bl      __loop_udelay
         mov     r0, r0
 
         @ The following must all exist in a single cache line to
@@ -53,11 +53,11 @@ ENTRY(sa1100_finish_suspend)
         @ delay 90us and set CPU PLL to lowest speed
         @ fixes resume problem on high speed SA1110
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
         mov     r1, #0
         str     r1, [r5]
         mov     r0, #90
-        bl      __udelay
+        bl      __loop_udelay
 
         /*
          * SA1110 SDRAM controller workaround.  register values:
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 6af26e8d55e6..80702c9ecc77 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -22,7 +22,7 @@
 
 static u32 notrace sa1100_read_sched_clock(void)
 {
-        return OSCR;
+        return readl_relaxed(OSCR);
 }
 
 #define MIN_OSCR_DELTA 2
@@ -32,8 +32,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
         struct clock_event_device *c = dev_id;
 
         /* Disarm the compare/match, signal the event. */
-        OIER &= ~OIER_E0;
-        OSSR = OSSR_M0;
+        writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+        writel_relaxed(OSSR_M0, OSSR);
         c->event_handler(c);
 
         return IRQ_HANDLED;
@@ -44,10 +44,10 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
 {
         unsigned long next, oscr;
 
-        OIER |= OIER_E0;
-        next = OSCR + delta;
-        OSMR0 = next;
-        oscr = OSCR;
+        writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER);
+        next = readl_relaxed(OSCR) + delta;
+        writel_relaxed(next, OSMR0);
+        oscr = readl_relaxed(OSCR);
 
         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 }
@@ -59,8 +59,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
         case CLOCK_EVT_MODE_ONESHOT:
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
-                OIER &= ~OIER_E0;
-                OSSR = OSSR_M0;
+                writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER);
+                writel_relaxed(OSSR_M0, OSSR);
                 break;
 
         case CLOCK_EVT_MODE_RESUME:
@@ -86,8 +86,8 @@ static struct irqaction sa1100_timer_irq = {
 
 static void __init sa1100_timer_init(void)
 {
-        OIER = 0;
-        OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
+        writel_relaxed(0, OIER);
+        writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
 
         setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
 
@@ -100,7 +100,7 @@ static void __init sa1100_timer_init(void)
 
         setup_irq(IRQ_OST0, &sa1100_timer_irq);
 
-        clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+        clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
                 clocksource_mmio_readl_up);
         clockevents_register_device(&ckevt_sa1100_osmr0);
 }
@@ -110,26 +110,26 @@ unsigned long osmr[4], oier;
 
 static void sa1100_timer_suspend(void)
 {
-        osmr[0] = OSMR0;
-        osmr[1] = OSMR1;
-        osmr[2] = OSMR2;
-        osmr[3] = OSMR3;
-        oier = OIER;
+        osmr[0] = readl_relaxed(OSMR0);
+        osmr[1] = readl_relaxed(OSMR1);
+        osmr[2] = readl_relaxed(OSMR2);
+        osmr[3] = readl_relaxed(OSMR3);
+        oier = readl_relaxed(OIER);
 }
 
 static void sa1100_timer_resume(void)
 {
-        OSSR = 0x0f;
-        OSMR0 = osmr[0];
-        OSMR1 = osmr[1];
-        OSMR2 = osmr[2];
-        OSMR3 = osmr[3];
-        OIER = oier;
+        writel_relaxed(0x0f, OSSR);
+        writel_relaxed(osmr[0], OSMR0);
+        writel_relaxed(osmr[1], OSMR1);
+        writel_relaxed(osmr[2], OSMR2);
+        writel_relaxed(osmr[3], OSMR3);
+        writel_relaxed(oier, OIER);
 
         /*
          * OSMR0 is the system timer: make sure OSCR is sufficiently behind
          */
-        OSCR = OSMR0 - LATCH;
+        writel_relaxed(OSMR0 - LATCH, OSCR);
 }
 #else
 #define sa1100_timer_suspend NULL
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index e859fcdb3d58..fde0d23121dc 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -22,8 +22,13 @@
 #include <mach/common.h>
 #include <mach/emev2.h>
 
+#ifdef CONFIG_ARCH_SH73A0
 #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \
                         of_machine_is_compatible("renesas,sh73a0"))
+#else
+#define is_sh73a0() (0)
+#endif
+
 #define is_r8a7779() machine_is_marzen()
 
 #ifdef CONFIG_ARCH_EMEV2
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 0f41bd1c47c3..66db5f13af84 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void)
 
 static void __init spear3xx_timer_init(void)
 {
-        char pclk_name[] = "pll3_48m_clk";
+        char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
         spear3xx_clk_init();
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2e2e3596583e..9af67d003c62 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void)
 
 static void __init spear6xx_timer_init(void)
 {
-        char pclk_name[] = "pll3_48m_clk";
+        char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
         spear6xx_clk_init();
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 1509a3cb5833..4fd93f5c49ec 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -625,11 +625,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
         &ab8500_device,
 };
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-        &snowball_led_dev,
-        &snowball_key_dev,
-};
-
 static void __init mop500_init_machine(void)
 {
         struct device *parent = NULL;
@@ -769,6 +764,11 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
+static struct platform_device *snowball_of_platform_devs[] __initdata = {
+        &snowball_led_dev,
+        &snowball_key_dev,
+};
+
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires DMA and call-back bindings. */
         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
@@ -786,6 +786,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
+        /* Requires device name bindings. */
+        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
         {},
 };
 
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 741e71feca78..66e7f00884ab 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -63,8 +63,10 @@ static void __init ux500_timer_init(void)
 
         /* TODO: Once MTU has been DT:ed place code above into else. */
         if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
                 np = of_find_matching_node(NULL, prcmu_timer_of_match);
                 if (!np)
+#endif
                         goto dt_fail;
 
                 tmp_base = of_iomap(np, 0);
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 806cc4f63516..119bc52ab93e 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -14,6 +14,7 @@
 #include <linux/percpu.h>
 
 #include <asm/mmu_context.h>
+#include <asm/thread_notify.h>
 #include <asm/tlbflush.h>
 
 static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
@@ -48,6 +49,40 @@ void cpu_set_reserved_ttbr0(void)
 }
 #endif
 
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+static int contextidr_notifier(struct notifier_block *unused, unsigned long cmd,
+                               void *t)
+{
+        u32 contextidr;
+        pid_t pid;
+        struct thread_info *thread = t;
+
+        if (cmd != THREAD_NOTIFY_SWITCH)
+                return NOTIFY_DONE;
+
+        pid = task_pid_nr(thread->task) << ASID_BITS;
+        asm volatile(
+        "       mrc     p15, 0, %0, c13, c0, 1\n"
+        "       bfi     %1, %0, #0, %2\n"
+        "       mcr     p15, 0, %1, c13, c0, 1\n"
+        : "=r" (contextidr), "+r" (pid)
+        : "I" (ASID_BITS));
+        isb();
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block contextidr_notifier_block = {
+        .notifier_call = contextidr_notifier,
+};
+
+static int __init contextidr_notifier_init(void)
+{
+        return thread_register_notifier(&contextidr_notifier_block);
+}
+arch_initcall(contextidr_notifier_init);
+#endif
+
 /*
  * We fork()ed a process, and we need a new context for the child
  * to run in.
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4044abcf6f9d..5cfc98994076 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -23,12 +23,12 @@
 #include <linux/slab.h>
 #include <linux/iommu.h>
 #include <linux/vmalloc.h>
+#include <linux/sizes.h>
 
 #include <asm/memory.h>
 #include <asm/highmem.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 #include <asm/mach/arch.h>
 #include <asm/dma-iommu.h>
 #include <asm/mach/map.h>
@@ -1091,7 +1091,7 @@ error:
         while (--i)
                 if (pages[i])
                         __free_pages(pages[i], 0);
-        if (array_size < PAGE_SIZE)
+        if (array_size <= PAGE_SIZE)
                 kfree(pages);
         else
                 vfree(pages);
@@ -1106,7 +1106,7 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
         for (i = 0; i < count; i++)
                 if (pages[i])
                         __free_pages(pages[i], 0);
-        if (array_size < PAGE_SIZE)
+        if (array_size <= PAGE_SIZE)
                 kfree(pages);
         else
                 vfree(pages);
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f54d59219764..9aec41fa80ae 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -21,13 +21,13 @@
 #include <linux/gfp.h>
 #include <linux/memblock.h>
 #include <linux/dma-contiguous.h>
+#include <linux/sizes.h>
 
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
 #include <asm/prom.h>
 #include <asm/sections.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/tlb.h>
 #include <asm/fixmap.h>
 
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 4f55f5062ab7..566750fa57d4 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -25,6 +25,7 @@
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
 #include <linux/io.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -32,7 +33,6 @@
 #include <asm/mmu_context.h>
 #include <asm/pgalloc.h>
 #include <asm/tlbflush.h>
-#include <asm/sizes.h>
 #include <asm/system_info.h>
 
 #include <asm/mach/map.h>
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index cf4528d51774..4c2d0451e84a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -16,13 +16,13 @@
 #include <linux/memblock.h>
 #include <linux/fs.h>
 #include <linux/vmalloc.h>
+#include <linux/sizes.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
 #include <asm/sections.h>
 #include <asm/cachetype.h>
 #include <asm/setup.h>
-#include <asm/sizes.h>
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
@@ -422,12 +422,6 @@ static void __init build_mem_type_table(void)
         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 
         /*
-         * Only use write-through for non-SMP systems
-         */
-        if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
-                vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
-
-        /*
          * Enable CPU-specific coherency if supported.
          * (Only available on XSC3 at the moment.)
          */
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 5900cd520e84..86b8b480634f 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -107,6 +107,12 @@ ENTRY(cpu_v6_switch_mm)
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
         mcr     p15, 0, r2, c7, c10, 4          @ drain write buffer
         mcr     p15, 0, r0, c2, c0, 0           @ set TTB 0
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+        mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
+        bic     r2, r2, #0xff                   @ extract the PID
+        and     r1, r1, #0xff
+        orr     r1, r1, r2                      @ insert into new context ID
+#endif
         mcr     p15, 0, r1, c13, c0, 1          @ set context ID
 #endif
         mov     pc, lr
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index 42ac069c8012..fd045e706390 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -46,6 +46,11 @@ ENTRY(cpu_v7_switch_mm)
 #ifdef CONFIG_ARM_ERRATA_430973
         mcr     p15, 0, r2, c7, c5, 6           @ flush BTAC/BTB
 #endif
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+        mrc     p15, 0, r2, c13, c0, 1          @ read current context ID
+        lsr     r2, r2, #8                      @ extract the PID
+        bfi     r1, r2, #8, #24                 @ insert into new context ID
+#endif
 #ifdef CONFIG_ARM_ERRATA_754322
         dsb
 #endif
diff --git a/arch/arm/oprofile/common.c b/arch/arm/oprofile/common.c
index 4e0a371630b3..99c63d4b6af8 100644
--- a/arch/arm/oprofile/common.c
+++ b/arch/arm/oprofile/common.c
@@ -23,26 +23,37 @@
 #include <asm/ptrace.h>
 
 #ifdef CONFIG_HW_PERF_EVENTS
+
+/*
+ * OProfile has a curious naming scheme for the ARM PMUs, but they are
+ * part of the user ABI so we need to map from the perf PMU name for
+ * supported PMUs.
+ */
+static struct op_perf_name {
+        char *perf_name;
+        char *op_name;
+} op_perf_name_map[] = {
+        { "xscale1",            "arm/xscale1"   },
+        { "xscale1",            "arm/xscale2"   },
+        { "v6",                 "arm/armv6"     },
+        { "v6mpcore",           "arm/mpcore"    },
+        { "ARMv7 Cortex-A8",    "arm/armv7"     },
+        { "ARMv7 Cortex-A9",    "arm/armv7-ca9" },
+};
+
 char *op_name_from_perf_id(void)
 {
-        enum arm_perf_pmu_ids id = armpmu_get_pmu_id();
-
-        switch (id) {
-        case ARM_PERF_PMU_ID_XSCALE1:
-                return "arm/xscale1";
-        case ARM_PERF_PMU_ID_XSCALE2:
-                return "arm/xscale2";
-        case ARM_PERF_PMU_ID_V6:
-                return "arm/armv6";
-        case ARM_PERF_PMU_ID_V6MP:
-                return "arm/mpcore";
-        case ARM_PERF_PMU_ID_CA8:
-                return "arm/armv7";
-        case ARM_PERF_PMU_ID_CA9:
-                return "arm/armv7-ca9";
-        default:
-                return NULL;
+        int i;
+        struct op_perf_name names;
+        const char *perf_name = perf_pmu_name();
+
+        for (i = 0; i < ARRAY_SIZE(op_perf_name_map); ++i) {
+                names = op_perf_name_map[i];
+                if (!strcmp(names.perf_name, perf_name))
+                        return names.op_name;
         }
+
+        return NULL;
 }
 #endif
 
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 33ecd0c9f0c3..b1e05ccff3ac 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -157,11 +157,13 @@ int s3c_adc_start(struct s3c_adc_client *client,
                 return -EINVAL;
         }
 
-        if (client->is_ts && adc->ts_pend)
-                return -EAGAIN;
-
         spin_lock_irqsave(&adc->lock, flags);
 
+        if (client->is_ts && adc->ts_pend) {
+                spin_unlock_irqrestore(&adc->lock, flags);
+                return -EAGAIN;
+        }
+
         client->channel = channel;
         client->nr_samples = nr_samples;
 
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 1d214cb9d770..6303974c2ee0 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -126,7 +126,8 @@ struct platform_device s3c_device_adc = {
 #ifdef CONFIG_CPU_S3C2440
 static struct resource s3c_camif_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
-        [1] = DEFINE_RES_IRQ(IRQ_CAM),
+        [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
+        [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
 };
 
 struct platform_device s3c_device_camif = {
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 031a61899bef..48a159911037 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -37,6 +37,7 @@ struct clk clk_ext_xtal_mux = {
 struct clk clk_xusbxti = {
         .name           = "xusbxti",
         .id             = -1,
+        .rate           = 24000000,
 };
 
 struct clk s5p_clk_27m = {
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index 49c7db48c7f1..d7c5c171f5aa 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -85,7 +85,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * the boot monitor to read the system wide flags register,
          * and branch to the address found there.
          */
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        gic_raise_softirq(cpumask_of(cpu), 0);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
diff --git a/arch/h8300/include/asm/pgtable.h b/arch/h8300/include/asm/pgtable.h
index a09230a08e02..62ef17676b40 100644
--- a/arch/h8300/include/asm/pgtable.h
+++ b/arch/h8300/include/asm/pgtable.h
@@ -70,4 +70,7 @@ extern int is_in_rom(unsigned long);
 #define VMALLOC_END     0xffffffff
 
 #define arch_enter_lazy_cpu_mode()    do {} while (0)
+
+#include <asm-generic/pgtable.h>
+
 #endif /* _H8300_PGTABLE_H */
diff --git a/arch/h8300/include/asm/uaccess.h b/arch/h8300/include/asm/uaccess.h
index 356068cd0879..8725d1ad4272 100644
--- a/arch/h8300/include/asm/uaccess.h
+++ b/arch/h8300/include/asm/uaccess.h
@@ -100,7 +100,6 @@ extern int __put_user_bad(void);
         break;                                                  \
     default:                                                    \
         __gu_err = __get_user_bad();                            \
-        __gu_val = 0;                                           \
         break;                                                  \
     }                                                           \
     (x) = __gu_val;                                             \
@@ -159,4 +158,6 @@ clear_user(void *to, unsigned long n)
         return 0;
 }
 
+#define __clear_user    clear_user
+
 #endif /* _H8300_UACCESS_H */
diff --git a/arch/h8300/kernel/signal.c b/arch/h8300/kernel/signal.c
index fca10378701b..5adaadaf9218 100644
--- a/arch/h8300/kernel/signal.c
+++ b/arch/h8300/kernel/signal.c
@@ -447,7 +447,7 @@ handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka,
  * want to handle. Thus you cannot kill init even with a SIGKILL even by
  * mistake.
  */
-statis void do_signal(struct pt_regs *regs)
+static void do_signal(struct pt_regs *regs)
 {
         siginfo_t info;
         int signr;
diff --git a/arch/h8300/kernel/time.c b/arch/h8300/kernel/time.c
index 32263a138aa6..e0f74191d553 100644
--- a/arch/h8300/kernel/time.c
+++ b/arch/h8300/kernel/time.c
@@ -27,6 +27,7 @@
 #include <linux/profile.h>
 
 #include <asm/io.h>
+#include <asm/irq_regs.h>
 #include <asm/timer.h>
 
 #define TICK_SIZE (tick_nsec / 1000)
diff --git a/arch/m32r/boot/compressed/Makefile b/arch/m32r/boot/compressed/Makefile
index 177716b1d613..01729c2979ba 100644
--- a/arch/m32r/boot/compressed/Makefile
+++ b/arch/m32r/boot/compressed/Makefile
@@ -43,9 +43,9 @@ endif
 
 OBJCOPYFLAGS += -R .empty_zero_page
 
-suffix_$(CONFIG_KERNEL_GZIP)    = gz
-suffix_$(CONFIG_KERNEL_BZIP2)   = bz2
-suffix_$(CONFIG_KERNEL_LZMA)    = lzma
+suffix-$(CONFIG_KERNEL_GZIP)    = gz
+suffix-$(CONFIG_KERNEL_BZIP2)   = bz2
+suffix-$(CONFIG_KERNEL_LZMA)    = lzma
 
 $(obj)/piggy.o: $(obj)/vmlinux.scr $(obj)/vmlinux.bin.$(suffix-y) FORCE
         $(call if_changed,ld)
diff --git a/arch/m32r/boot/compressed/misc.c b/arch/m32r/boot/compressed/misc.c
index 370d60881977..28a09529f206 100644
--- a/arch/m32r/boot/compressed/misc.c
+++ b/arch/m32r/boot/compressed/misc.c
@@ -28,7 +28,7 @@ static unsigned long free_mem_ptr;
 static unsigned long free_mem_end_ptr;
 
 #ifdef CONFIG_KERNEL_BZIP2
-static void *memset(void *s, int c, size_t n)
+void *memset(void *s, int c, size_t n)
 {
         char *ss = s;
 
@@ -39,6 +39,16 @@ static void *memset(void *s, int c, size_t n)
 #endif
 
 #ifdef CONFIG_KERNEL_GZIP
+void *memcpy(void *dest, const void *src, size_t n)
+{
+        char *d = dest;
+        const char *s = src;
+        while (n--)
+                *d++ = *s++;
+
+        return dest;
+}
+
 #define BOOT_HEAP_SIZE             0x10000
 #include "../../../../lib/decompress_inflate.c"
 #endif
diff --git a/arch/m32r/include/asm/ptrace.h b/arch/m32r/include/asm/ptrace.h
index 527527584dd0..4313aa62b51b 100644
--- a/arch/m32r/include/asm/ptrace.h
+++ b/arch/m32r/include/asm/ptrace.h
@@ -113,9 +113,6 @@ struct pt_regs {
 
 #define PTRACE_OLDSETOPTIONS    21
 
-/* options set using PTRACE_SETOPTIONS */
-#define PTRACE_O_TRACESYSGOOD   0x00000001
-
 #ifdef __KERNEL__
 
 #include <asm/m32r.h>           /* M32R_PSW_BSM, M32R_PSW_BPM */
diff --git a/arch/m32r/kernel/ptrace.c b/arch/m32r/kernel/ptrace.c
index 4c03361537aa..51f5e9aa4901 100644
--- a/arch/m32r/kernel/ptrace.c
+++ b/arch/m32r/kernel/ptrace.c
@@ -591,17 +591,16 @@ void user_enable_single_step(struct task_struct *child)
 
         if (access_process_vm(child, pc&~3, &insn, sizeof(insn), 0)
             != sizeof(insn))
-                return -EIO;
+                return;
 
         compute_next_pc(insn, pc, &next_pc, child);
         if (next_pc & 0x80000000)
-                return -EIO;
+                return;
 
         if (embed_debug_trap(child, next_pc))
-                return -EIO;
+                return;
 
         invalidate_cache();
-        return 0;
 }
 
 void user_disable_single_step(struct task_struct *child)
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
index f3fb2c029cfc..d0f60b97bbc5 100644
--- a/arch/m32r/kernel/signal.c
+++ b/arch/m32r/kernel/signal.c
@@ -286,7 +286,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, siginfo_t *info,
                         case -ERESTARTNOINTR:
                                 regs->r0 = regs->orig_r0;
                                 if (prev_insn(regs) < 0)
-                                        return -EFAULT;
+                                        return;
                 }
         }
 
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 09ab87ee6fef..b3e10fdd3898 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -288,6 +288,7 @@ config MIPS_MALTA
         select SYS_HAS_CPU_MIPS32_R1
         select SYS_HAS_CPU_MIPS32_R2
         select SYS_HAS_CPU_MIPS64_R1
+        select SYS_HAS_CPU_MIPS64_R2
         select SYS_HAS_CPU_NEVADA
         select SYS_HAS_CPU_RM7000
         select SYS_HAS_EARLY_PRINTK
@@ -1423,6 +1424,7 @@ config CPU_SB1
 config CPU_CAVIUM_OCTEON
         bool "Cavium Octeon processor"
         depends on SYS_HAS_CPU_CAVIUM_OCTEON
+        select ARCH_SPARSEMEM_ENABLE
         select CPU_HAS_PREFETCH
         select CPU_SUPPORTS_64BIT_KERNEL
         select SYS_SUPPORTS_SMP
diff --git a/arch/mips/bcm47xx/Kconfig b/arch/mips/bcm47xx/Kconfig
index 6210b8d84109..b311be45a720 100644
--- a/arch/mips/bcm47xx/Kconfig
+++ b/arch/mips/bcm47xx/Kconfig
@@ -21,6 +21,7 @@ config BCM47XX_BCMA
         select BCMA
         select BCMA_HOST_SOC
         select BCMA_DRIVER_MIPS
+        select BCMA_HOST_PCI if PCI
         select BCMA_DRIVER_PCI_HOSTMODE if PCI
         default y
         help
diff --git a/arch/mips/bcm63xx/dev-pcmcia.c b/arch/mips/bcm63xx/dev-pcmcia.c
index de4d917fd54d..a551bab5ecb9 100644
--- a/arch/mips/bcm63xx/dev-pcmcia.c
+++ b/arch/mips/bcm63xx/dev-pcmcia.c
@@ -79,11 +79,11 @@ static int __init config_pcmcia_cs(unsigned int cs,
         return ret;
 }
 
-static const __initdata struct {
+static const struct {
         unsigned int    cs;
         unsigned int    base;
         unsigned int    size;
-} pcmcia_cs[3] = {
+} pcmcia_cs[3] __initconst = {
         {
                 .cs     = MPI_CS_PCMCIA_COMMON,
                 .base   = BCM_PCMCIA_COMMON_BASE_PA,
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
index f9e275a50d98..2f4f6d5e05b6 100644
--- a/arch/mips/cavium-octeon/Kconfig
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -82,10 +82,6 @@ config CAVIUM_OCTEON_LOCK_L2_MEMCPY
         help
           Lock the kernel's implementation of memcpy() into L2.
 
-config ARCH_SPARSEMEM_ENABLE
-        def_bool y
-        select SPARSEMEM_STATIC
-
 config IOMMU_HELPER
         bool
 
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 4b93048044eb..ee1fb9f7f517 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -185,7 +185,6 @@ static void __cpuinit octeon_init_secondary(void)
         octeon_init_cvmcount();
 
         octeon_irq_setup_secondary();
-        raw_local_irq_enable();
 }
 
 /**
@@ -233,6 +232,7 @@ static void octeon_smp_finish(void)
 
         /* to generate the first CPU timer interrupt */
         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+        local_irq_enable();
 }
 
 /**
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index 2e1ad4c652b7..82ad35ce2b45 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,7 +17,6 @@
 #include <linux/irqflags.h>
 #include <linux/types.h>
 #include <asm/barrier.h>
-#include <asm/bug.h>
 #include <asm/byteorder.h>              /* sigh ... */
 #include <asm/cpu-features.h>
 #include <asm/sgidefs.h>
diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxchg.h
index 285a41fa0b18..eee10dc07ac1 100644
--- a/arch/mips/include/asm/cmpxchg.h
+++ b/arch/mips/include/asm/cmpxchg.h
@@ -8,6 +8,7 @@
 #ifndef __ASM_CMPXCHG_H
 #define __ASM_CMPXCHG_H
 
+#include <linux/bug.h>
 #include <linux/irqflags.h>
 #include <asm/war.h>
 
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index f9fa2a479dd0..95e40c1e8ed1 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -94,6 +94,7 @@
 #define PRID_IMP_24KE           0x9600
 #define PRID_IMP_74K            0x9700
 #define PRID_IMP_1004K          0x9900
+#define PRID_IMP_M14KC          0x9c00
 
 /*
  * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -260,12 +261,12 @@ enum cpu_type_enum {
          */
         CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
         CPU_ALCHEMY, CPU_PR4450, CPU_BMIPS32, CPU_BMIPS3300, CPU_BMIPS4350,
-        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC,
+        CPU_BMIPS4380, CPU_BMIPS5000, CPU_JZRISC, CPU_M14KC,
 
         /*
          * MIPS64 class processors
          */
-        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
+        CPU_5KC, CPU_5KE, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
         CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_CAVIUM_OCTEON2,
         CPU_XLR, CPU_XLP,
 
@@ -288,7 +289,7 @@ enum cpu_type_enum {
 #define MIPS_CPU_ISA_M64R2      0x00000100
 
 #define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
-        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
+        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2)
 #define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
         MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
 
diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h
index 86548da650e7..991b659e2548 100644
--- a/arch/mips/include/asm/gic.h
+++ b/arch/mips/include/asm/gic.h
@@ -206,7 +206,7 @@
 
 #define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
 #define GIC_VPE_EIC_SS(intr) \
-        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
+        (GIC_VPE_EIC_SHADOW_SET_BASE + (4 * intr))
 
 #define GIC_VPE_EIC_VEC_BASE            0x0800
 #define GIC_VPE_EIC_VEC(intr) \
@@ -330,6 +330,17 @@ struct gic_intr_map {
 #define GIC_FLAG_TRANSPARENT   0x02
 };
 
+/*
+ * This is only used in EIC mode. This helps to figure out which
+ * shared interrupts we need to process when we get a vector interrupt.
+ */
+#define GIC_MAX_SHARED_INTR  0x5
+struct gic_shared_intr_map {
+        unsigned int num_shared_intr;
+        unsigned int intr_list[GIC_MAX_SHARED_INTR];
+        unsigned int local_intr_mask;
+};
+
 extern void gic_init(unsigned long gic_base_addr,
         unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
         unsigned int intrmap_size, unsigned int irqbase);
@@ -338,5 +349,7 @@ extern unsigned int gic_get_int(void);
 extern void gic_send_ipi(unsigned int intr);
 extern unsigned int plat_ipi_call_int_xlate(unsigned int);
 extern unsigned int plat_ipi_resched_int_xlate(unsigned int);
+extern void gic_bind_eic_interrupt(int irq, int set);
+extern unsigned int gic_get_timer_pending(void);
 
 #endif /* _ASM_GICREGS_H */
diff --git a/arch/mips/include/asm/inst.h b/arch/mips/include/asm/inst.h
index 7ebfc392e58d..ab84064283db 100644
--- a/arch/mips/include/asm/inst.h
+++ b/arch/mips/include/asm/inst.h
@@ -251,7 +251,7 @@ struct f_format {	/* FPU register format */
         unsigned int func : 6;
 };
 
-struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+struct ma_format {      /* FPU multiply and add format (MIPS IV) */
         unsigned int opcode : 6;
         unsigned int fr : 5;
         unsigned int ft : 5;
@@ -324,7 +324,7 @@ struct f_format {	/* FPU register format */
         unsigned int opcode : 6;
 };
 
-struct ma_format {      /* FPU multipy and add format (MIPS IV) */
+struct ma_format {      /* FPU multiply and add format (MIPS IV) */
         unsigned int fmt : 2;
         unsigned int func : 4;
         unsigned int fd : 5;
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index a58f22998a86..29d9c23c20c7 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -17,6 +17,7 @@
 #include <linux/types.h>
 
 #include <asm/addrspace.h>
+#include <asm/bug.h>
 #include <asm/byteorder.h>
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h
index fb698dc09bc9..78dbb8a86da2 100644
--- a/arch/mips/include/asm/irq.h
+++ b/arch/mips/include/asm/irq.h
@@ -136,6 +136,7 @@ extern void free_irqno(unsigned int irq);
  * IE7.  Since R2 their number has to be read from the c0_intctl register.
  */
 #define CP0_LEGACY_COMPARE_IRQ 7
+#define CP0_LEGACY_PERFCNT_IRQ 7
 
 extern int cp0_compare_irq;
 extern int cp0_compare_irq_shift;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index 94d4faad29a1..fdcd78ca1b03 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -99,7 +99,7 @@
 #define CKCTL_6368_USBH_CLK_EN          (1 << 15)
 #define CKCTL_6368_DISABLE_GLESS_EN     (1 << 16)
 #define CKCTL_6368_NAND_CLK_EN          (1 << 17)
-#define CKCTL_6368_IPSEC_CLK_EN         (1 << 17)
+#define CKCTL_6368_IPSEC_CLK_EN         (1 << 18)
 
 #define CKCTL_6368_ALL_SAFE_EN          (CKCTL_6368_SWPKT_USB_EN |      \
                                         CKCTL_6368_SWPKT_SAR_EN |       \
diff --git a/arch/mips/include/asm/mips-boards/maltaint.h b/arch/mips/include/asm/mips-boards/maltaint.h
index d11aa02a956a..5447d9fc4219 100644
--- a/arch/mips/include/asm/mips-boards/maltaint.h
+++ b/arch/mips/include/asm/mips-boards/maltaint.h
@@ -86,6 +86,16 @@
 #define GIC_CPU_INT4            4 /* .                  */
 #define GIC_CPU_INT5            5 /* Core Interrupt 5   */
 
+/* MALTA GIC local interrupts */
+#define GIC_INT_TMR             (GIC_CPU_INT5)
+#define GIC_INT_PERFCTR         (GIC_CPU_INT5)
+
+/* GIC constants */
+/* Add 2 to convert non-eic hw int # to eic vector # */
+#define GIC_CPU_TO_VEC_OFFSET   (2)
+/* If we map an intr to pin X, GIC will actually generate vector X+1 */
+#define GIC_PIN_TO_VEC_OFFSET   (1)
+
 #define GIC_EXT_INTR(x)         x
 
 /* External Interrupts used for IPI */
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index c9420aa97e32..e71ff4c317f2 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -48,7 +48,7 @@
 #define CP0_VPECONF0            $1, 2
 #define CP0_VPECONF1            $1, 3
 #define CP0_YQMASK              $1, 4
-#define CP0_VPESCHEDULE $1, 5
+#define CP0_VPESCHEDULE         $1, 5
 #define CP0_VPESCHEFBK          $1, 6
 #define CP0_TCSTATUS            $2, 1
 #define CP0_TCBIND              $2, 2
diff --git a/arch/mips/include/asm/switch_to.h b/arch/mips/include/asm/switch_to.h
index 5d33621b5658..4f8ddba8c360 100644
--- a/arch/mips/include/asm/switch_to.h
+++ b/arch/mips/include/asm/switch_to.h
@@ -22,7 +22,7 @@ struct task_struct;
  * switch_to(n) should switch tasks to task nr n, first
  * checking that n isn't the current task, in which case it does nothing.
  */
-extern asmlinkage void *resume(void *last, void *next, void *next_ti);
+extern asmlinkage void *resume(void *last, void *next, void *next_ti, u32 __usedfpu);
 
 extern unsigned int ll_bit;
 extern struct task_struct *ll_task;
@@ -66,11 +66,13 @@ do {									\
 
 #define switch_to(prev, next, last)                                     \
 do {                                                                    \
+        u32 __usedfpu;                                                  \
         __mips_mt_fpaff_switch_to(prev);                                \
         if (cpu_has_dsp)                                                \
                 __save_dsp(prev);                                       \
         __clear_software_ll_bit();                                      \
-        (last) = resume(prev, next, task_thread_info(next));            \
+        __usedfpu = test_and_clear_tsk_thread_flag(prev, TIF_USEDFPU);  \
+        (last) = resume(prev, next, task_thread_info(next), __usedfpu); \
 } while (0)
 
 #define finish_arch_switch(prev)                                        \
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index e2eca7d10598..ca97e0ecb64b 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -60,6 +60,8 @@ struct thread_info {
 register struct thread_info *__current_thread_info __asm__("$28");
 #define current_thread_info()  __current_thread_info
 
+#endif /* !__ASSEMBLY__ */
+
 /* thread information allocation */
 #if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
 #define THREAD_SIZE_ORDER (1)
@@ -85,8 +87,6 @@ register struct thread_info *__current_thread_info __asm__("$28");
 
 #define STACK_WARN      (THREAD_SIZE / 8)
 
-#endif /* !__ASSEMBLY__ */
-
 #define PREEMPT_ACTIVE          0x10000000
 
 /*
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 6ae7ce4ac63e..f4630e1082ab 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -4,7 +4,7 @@
  * Copyright (C) xxxx  the Anonymous
  * Copyright (C) 1994 - 2006 Ralf Baechle
  * Copyright (C) 2003, 2004  Maciej W. Rozycki
- * Copyright (C) 2001, 2004  MIPS Inc.
+ * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -199,6 +199,7 @@ void __init check_wait(void)
                 cpu_wait = rm7k_wait_irqoff;
                 break;
 
+        case CPU_M14KC:
         case CPU_24K:
         case CPU_34K:
         case CPU_1004K:
@@ -810,6 +811,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_5KC;
                 __cpu_name[cpu] = "MIPS 5Kc";
                 break;
+        case PRID_IMP_5KE:
+                c->cputype = CPU_5KE;
+                __cpu_name[cpu] = "MIPS 5KE";
+                break;
         case PRID_IMP_20KC:
                 c->cputype = CPU_20KC;
                 __cpu_name[cpu] = "MIPS 20Kc";
@@ -831,6 +836,10 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
                 c->cputype = CPU_74K;
                 __cpu_name[cpu] = "MIPS 74Kc";
                 break;
+        case PRID_IMP_M14KC:
+                c->cputype = CPU_M14KC;
+                __cpu_name[cpu] = "MIPS M14Kc";
+                break;
         case PRID_IMP_1004K:
                 c->cputype = CPU_1004K;
                 __cpu_name[cpu] = "MIPS 1004Kc";
diff --git a/arch/mips/kernel/mips_ksyms.c b/arch/mips/kernel/mips_ksyms.c
index 57ba13edb03a..3fc1691110dc 100644
--- a/arch/mips/kernel/mips_ksyms.c
+++ b/arch/mips/kernel/mips_ksyms.c
@@ -5,7 +5,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05 by Ralf Baechle
+ * Copyright (C) 1996, 97, 98, 99, 2000, 01, 03, 04, 05, 12 by Ralf Baechle
  * Copyright (C) 1999, 2000, 01 Silicon Graphics, Inc.
  */
 #include <linux/interrupt.h>
@@ -35,6 +35,12 @@ EXPORT_SYMBOL(memmove);
 EXPORT_SYMBOL(kernel_thread);
 
 /*
+ * Functions that operate on entire pages.  Mostly used by memory management.
+ */
+EXPORT_SYMBOL(clear_page);
+EXPORT_SYMBOL(copy_page);
+
+/*
  * Userspace access stuff.
  */
 EXPORT_SYMBOL(__copy_user);
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index ce89c8061708..0441f54b2a6a 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -31,7 +31,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
         .align  7
         LEAF(resume)
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index f29099b104c4..eb5e394a4650 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -162,11 +162,6 @@ static unsigned int counters_total_to_per_cpu(unsigned int counters)
         return counters >> vpe_shift();
 }
 
-static unsigned int counters_per_cpu_to_total(unsigned int counters)
-{
-        return counters << vpe_shift();
-}
-
 #else /* !CONFIG_MIPS_MT_SMP */
 #define vpe_id()        0
 
diff --git a/arch/mips/kernel/r2300_switch.S b/arch/mips/kernel/r2300_switch.S
index 293898391e67..9c51be5a163a 100644
--- a/arch/mips/kernel/r2300_switch.S
+++ b/arch/mips/kernel/r2300_switch.S
@@ -43,7 +43,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti) )
+ *                     struct thread_info *next_ti, int usedfpu)
  */
 LEAF(resume)
         mfc0    t1, CP0_STATUS
@@ -51,18 +51,9 @@ LEAF(resume)
         cpu_save_nonscratch a0
         sw      ra, THREAD_REG31(a0)
 
-        /*
-         * check if we need to save FPU registers
-         */
-        lw      t3, TASK_THREAD_INFO(a0)
-        lw      t0, TI_FLAGS(t3)
-        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
-        beqz    t2, 1f
-        nor     t1, zero, t1
+        beqz    a3, 1f
 
-        and     t0, t0, t1
-        sw      t0, TI_FLAGS(t3)
+        PTR_L   t3, TASK_THREAD_INFO(a0)
 
         /*
          * clear saved user stack CU1 bit
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 9414f9354469..42d2a3938420 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -41,7 +41,7 @@
 
 /*
  * task_struct *resume(task_struct *prev, task_struct *next,
- *                     struct thread_info *next_ti)
+ *                     struct thread_info *next_ti, int usedfpu)
  */
         .align  5
         LEAF(resume)
@@ -53,16 +53,10 @@
         /*
          * check if we need to save FPU registers
          */
-        PTR_L   t3, TASK_THREAD_INFO(a0)
-        LONG_L  t0, TI_FLAGS(t3)
-        li      t1, _TIF_USEDFPU
-        and     t2, t0, t1
-        beqz    t2, 1f
-        nor     t1, zero, t1
 
-        and     t0, t0, t1
-        LONG_S  t0, TI_FLAGS(t3)
+        beqz    a3, 1f
 
+        PTR_L   t3, TASK_THREAD_INFO(a0)
         /*
          * clear saved user stack CU1 bit
          */
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 3046e2986006..8e393b8443f7 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -15,7 +15,6 @@
 #include <linux/smp.h>
 #include <linux/interrupt.h>
 #include <linux/spinlock.h>
-#include <linux/init.h>
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <linux/reboot.h>
@@ -197,13 +196,6 @@ static void bmips_init_secondary(void)
 
         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 #endif
-
-        /* make sure there won't be a timer interrupt for a little while */
-        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
-
-        irq_enable_hazard();
-        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
-        irq_enable_hazard();
 }
 
 /*
@@ -212,6 +204,13 @@ static void bmips_init_secondary(void)
 static void bmips_smp_finish(void)
 {
         pr_info("SMP: CPU%d is running\n", smp_processor_id());
+
+        /* make sure there won't be a timer interrupt for a little while */
+        write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
+
+        irq_enable_hazard();
+        set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
+        irq_enable_hazard();
 }
 
 /*
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 48650c818040..1268392f1d27 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -122,13 +122,21 @@ asmlinkage __cpuinit void start_secondary(void)
 
         notify_cpu_starting(cpu);
 
-        mp_ops->smp_finish();
+        set_cpu_online(cpu, true);
+
         set_cpu_sibling_map(cpu);
 
         cpu_set(cpu, cpu_callin_map);
 
         synchronise_count_slave();
 
+        /*
+         * irq will be enabled in ->smp_finish(), enabling it too early
+         * is dangerous.
+         */
+        WARN_ON_ONCE(!irqs_disabled());
+        mp_ops->smp_finish();
+
         cpu_idle();
 }
 
@@ -196,8 +204,6 @@ int __cpuinit __cpu_up(unsigned int cpu, struct task_struct *tidle)
         while (!cpu_isset(cpu, cpu_callin_map))
                 udelay(100);
 
-        set_cpu_online(cpu, true);
-
         return 0;
 }
 
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f5dd38f1d015..15b5f3cfd20c 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -322,7 +322,7 @@ int __init smtc_build_cpu_map(int start_cpu_slot)
 
 /*
  * Common setup before any secondaries are started
- * Make sure all CPU's are in a sensible state before we boot any of the
+ * Make sure all CPUs are in a sensible state before we boot any of the
  * secondaries.
  *
  * For MIPS MT "SMTC" operation, we set up all TCs, spread as evenly
@@ -340,12 +340,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
         /*
          * TCContext gets an offset from the base of the IPIQ array
          * to be used in low-level code to detect the presence of
-         * an active IPI queue
+         * an active IPI queue.
          */
         write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
         /* Bind tc to vpe */
         write_tc_c0_tcbind(vpe);
-        /* In general, all TCs should have the same cpu_data indications */
+        /* In general, all TCs should have the same cpu_data indications. */
         memcpy(&cpu_data[cpu], &cpu_data[0], sizeof(struct cpuinfo_mips));
         /* For 34Kf, start with TC/CPU 0 as sole owner of single FPU context */
         if (cpu_data[0].cputype == CPU_34K ||
@@ -358,8 +358,8 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
 }
 
 /*
- * Tweak to get Count registes in as close a sync as possible.
- * Value seems good for 34K-class cores.
+ * Tweak to get Count registes in as close a sync as possible.  The
+ * value seems good for 34K-class cores.
  */
 
 #define CP0_SKEW 8
@@ -615,7 +615,6 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 
 void smtc_init_secondary(void)
 {
-        local_irq_enable();
 }
 
 void smtc_smp_finish(void)
@@ -631,6 +630,8 @@ void smtc_smp_finish(void)
         if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
                 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
 
+        local_irq_enable();
+
         printk("TC %d going on-line as CPU %d\n",
                 cpu_data[smp_processor_id()].tc_id, smp_processor_id());
 }
diff --git a/arch/mips/kernel/sync-r4k.c b/arch/mips/kernel/sync-r4k.c
index 99f913c8d7a6..842d55e411fd 100644
--- a/arch/mips/kernel/sync-r4k.c
+++ b/arch/mips/kernel/sync-r4k.c
@@ -111,7 +111,6 @@ void __cpuinit synchronise_count_master(void)
 void __cpuinit synchronise_count_slave(void)
 {
         int i;
-        unsigned long flags;
         unsigned int initcount;
         int ncpus;
 
@@ -123,8 +122,6 @@ void __cpuinit synchronise_count_slave(void)
         return;
 #endif
 
-        local_irq_save(flags);
-
         /*
          * Not every cpu is online at the time this gets called,
          * so we first wait for the master to say everyone is ready
@@ -154,7 +151,5 @@ void __cpuinit synchronise_count_slave(void)
         }
         /* Arrange for an interrupt in a short while */
         write_c0_compare(read_c0_count() + COUNTON);
-
-        local_irq_restore(flags);
 }
 #undef NR_LOOPS
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 2d0c2a277f52..c3c293543703 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -132,6 +132,9 @@ static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
         unsigned long ra = regs->regs[31];
         unsigned long pc = regs->cp0_epc;
 
+        if (!task)
+                task = current;
+
         if (raw_show_trace || !__kernel_text_address(pc)) {
                 show_raw_backtrace(sp);
                 return;
@@ -1249,6 +1252,7 @@ static inline void parity_protection_init(void)
                 break;
 
         case CPU_5KC:
+        case CPU_5KE:
                 write_c0_ecc(0x80000000);
                 back_to_back_c0_hazard();
                 /* Set the PE bit (bit 31) in the c0_errctl register. */
@@ -1498,6 +1502,7 @@ extern void flush_tlb_handlers(void);
  * Timer interrupt
  */
 int cp0_compare_irq;
+EXPORT_SYMBOL_GPL(cp0_compare_irq);
 int cp0_compare_irq_shift;
 
 /*
@@ -1597,7 +1602,7 @@ void __cpuinit per_cpu_trap_init(bool is_boot_cpu)
                         cp0_perfcount_irq = -1;
         } else {
                 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
-                cp0_compare_irq_shift = cp0_compare_irq;
+                cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ;
                 cp0_perfcount_irq = -1;
         }
 
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 924da5eb7031..df243a64f430 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -1,5 +1,6 @@
 #include <asm/asm-offsets.h>
 #include <asm/page.h>
+#include <asm/thread_info.h>
 #include <asm-generic/vmlinux.lds.h>
 
 #undef mips
@@ -72,7 +73,7 @@ SECTIONS
         .data : {       /* Data */
                 . = . + DATAOFFSET;             /* for CONFIG_MAPPED_KERNEL */
 
-                INIT_TASK_DATA(PAGE_SIZE)
+                INIT_TASK_DATA(THREAD_SIZE)
                 NOSAVE_DATA
                 CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
                 READ_MOSTLY_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 4aa20280613e..fd6203f14f1f 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -3,8 +3,8 @@
 #
 
 obj-y                           += cache.o dma-default.o extable.o fault.o \
-                                   gup.o init.o mmap.o page.o tlbex.o \
-                                   tlbex-fault.o uasm.o
+                                   gup.o init.o mmap.o page.o page-funcs.o \
+                                   tlbex.o tlbex-fault.o uasm.o
 
 obj-$(CONFIG_32BIT)             += ioremap.o pgtable-32.o
 obj-$(CONFIG_64BIT)             += pgtable-64.o
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5109be96d98d..f092c265dc63 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -977,7 +977,7 @@ static void __cpuinit probe_pcache(void)
                         c->icache.linesz = 2 << lsize;
                 else
                         c->icache.linesz = lsize;
-                c->icache.sets = 64 << ((config1 >> 22) & 7);
+                c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
                 c->icache.ways = 1 + ((config1 >> 16) & 7);
 
                 icache_size = c->icache.sets *
@@ -997,7 +997,7 @@ static void __cpuinit probe_pcache(void)
                         c->dcache.linesz = 2 << lsize;
                 else
                         c->dcache.linesz= lsize;
-                c->dcache.sets = 64 << ((config1 >> 13) & 7);
+                c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
 
                 dcache_size = c->dcache.sets *
@@ -1051,6 +1051,7 @@ static void __cpuinit probe_pcache(void)
         case CPU_R14000:
                 break;
 
+        case CPU_M14KC:
         case CPU_24K:
         case CPU_34K:
         case CPU_74K:
diff --git a/arch/mips/mm/page-funcs.S b/arch/mips/mm/page-funcs.S
new file mode 100644
index 000000000000..48a6b38ff13e
--- /dev/null
+++ b/arch/mips/mm/page-funcs.S
@@ -0,0 +1,50 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Micro-assembler generated clear_page/copy_page functions.
+ *
+ * Copyright (C) 2012  MIPS Technologies, Inc.
+ * Copyright (C) 2012  Ralf Baechle <ralf@linux-mips.org>
+ */
+#include <asm/asm.h>
+#include <asm/regdef.h>
+
+#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+#define cpu_clear_page_function_name    clear_page_cpu
+#define cpu_copy_page_function_name     copy_page_cpu
+#else
+#define cpu_clear_page_function_name    clear_page
+#define cpu_copy_page_function_name     copy_page
+#endif
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:             0x058 bytes
+ * R4600 v1.7:                          0x05c bytes
+ * R4600 v2.0:                          0x060 bytes
+ * With prefetching, 16 word strides    0x120 bytes
+ */
+EXPORT(__clear_page_start)
+LEAF(cpu_clear_page_function_name)
+1:      j       1b              /* Dummy, will be replaced. */
+        .space 288
+END(cpu_clear_page_function_name)
+EXPORT(__clear_page_end)
+
+/*
+ * Maximum sizes:
+ *
+ * R4000 128 bytes S-cache:             0x11c bytes
+ * R4600 v1.7:                          0x080 bytes
+ * R4600 v2.0:                          0x07c bytes
+ * With prefetching, 16 word strides    0x540 bytes
+ */
+EXPORT(__copy_page_start)
+LEAF(cpu_copy_page_function_name)
+1:      j       1b              /* Dummy, will be replaced. */
+        .space 1344
+END(cpu_copy_page_function_name)
+EXPORT(__copy_page_end)
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cc0b626858b3..98f530e18216 100644
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -6,6 +6,7 @@
  * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2007  Maciej W. Rozycki
  * Copyright (C) 2008  Thiemo Seufer
+ * Copyright (C) 2012  MIPS Technologies, Inc.
  */
 #include <linux/init.h>
 #include <linux/kernel.h>
@@ -71,45 +72,6 @@ static struct uasm_reloc __cpuinitdata relocs[5];
 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
 
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:             0x058 bytes
- * R4600 v1.7:                          0x05c bytes
- * R4600 v2.0:                          0x060 bytes
- * With prefetching, 16 word strides    0x120 bytes
- */
-
-static u32 clear_page_array[0x120 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void clear_page_cpu(void *page) __attribute__((alias("clear_page_array")));
-#else
-void clear_page(void *page) __attribute__((alias("clear_page_array")));
-#endif
-
-EXPORT_SYMBOL(clear_page);
-
-/*
- * Maximum sizes:
- *
- * R4000 128 bytes S-cache:             0x11c bytes
- * R4600 v1.7:                          0x080 bytes
- * R4600 v2.0:                          0x07c bytes
- * With prefetching, 16 word strides    0x540 bytes
- */
-static u32 copy_page_array[0x540 / 4];
-
-#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
-void
-copy_page_cpu(void *to, void *from) __attribute__((alias("copy_page_array")));
-#else
-void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
-#endif
-
-EXPORT_SYMBOL(copy_page);
-
-
 static int pref_bias_clear_store __cpuinitdata;
 static int pref_bias_copy_load __cpuinitdata;
 static int pref_bias_copy_store __cpuinitdata;
@@ -282,10 +244,15 @@ static inline void __cpuinit build_clear_pref(u32 **buf, int off)
                 }
 }
 
+extern u32 __clear_page_start;
+extern u32 __clear_page_end;
+extern u32 __copy_page_start;
+extern u32 __copy_page_end;
+
 void __cpuinit build_clear_page(void)
 {
         int off;
-        u32 *buf = (u32 *)&clear_page_array;
+        u32 *buf = &__clear_page_start;
         struct uasm_label *l = labels;
         struct uasm_reloc *r = relocs;
         int i;
@@ -356,17 +323,17 @@ void __cpuinit build_clear_page(void)
         uasm_i_jr(&buf, RA);
         uasm_i_nop(&buf);
 
-        BUG_ON(buf > clear_page_array + ARRAY_SIZE(clear_page_array));
+        BUG_ON(buf > &__clear_page_end);
 
         uasm_resolve_relocs(relocs, labels);
 
         pr_debug("Synthesized clear page handler (%u instructions).\n",
-                 (u32)(buf - clear_page_array));
+                 (u32)(buf - &__clear_page_start));
 
         pr_debug("\t.set push\n");
         pr_debug("\t.set noreorder\n");
-        for (i = 0; i < (buf - clear_page_array); i++)
-                pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
+        for (i = 0; i < (buf - &__clear_page_start); i++)
+                pr_debug("\t.word 0x%08x\n", (&__clear_page_start)[i]);
         pr_debug("\t.set pop\n");
 }
 
@@ -427,7 +394,7 @@ static inline void build_copy_store_pref(u32 **buf, int off)
 void __cpuinit build_copy_page(void)
 {
         int off;
-        u32 *buf = (u32 *)&copy_page_array;
+        u32 *buf = &__copy_page_start;
         struct uasm_label *l = labels;
         struct uasm_reloc *r = relocs;
         int i;
@@ -595,21 +562,23 @@ void __cpuinit build_copy_page(void)
         uasm_i_jr(&buf, RA);
         uasm_i_nop(&buf);
 
-        BUG_ON(buf > copy_page_array + ARRAY_SIZE(copy_page_array));
+        BUG_ON(buf > &__copy_page_end);
 
         uasm_resolve_relocs(relocs, labels);
 
         pr_debug("Synthesized copy page handler (%u instructions).\n",
-                 (u32)(buf - copy_page_array));
+                 (u32)(buf - &__copy_page_start));
 
         pr_debug("\t.set push\n");
         pr_debug("\t.set noreorder\n");
-        for (i = 0; i < (buf - copy_page_array); i++)
-                pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
+        for (i = 0; i < (buf - &__copy_page_start); i++)
+                pr_debug("\t.word 0x%08x\n", (&__copy_page_start)[i]);
         pr_debug("\t.set pop\n");
 }
 
 #ifdef CONFIG_SIBYTE_DMA_PAGEOPS
+extern void clear_page_cpu(void *page);
+extern void copy_page_cpu(void *to, void *from);
 
 /*
  * Pad descriptors to cacheline, since each is exclusively owned by a
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 0bc485b3cd60..03eb0ef91580 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -9,6 +9,7 @@
  * Copyright (C) 2005, 2007, 2008, 2009  Maciej W. Rozycki
  * Copyright (C) 2006  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (C) 2008, 2009 Cavium Networks, Inc.
+ * Copyright (C) 2011  MIPS Technologies, Inc.
  *
  * ... and the days got worse and worse and now you see
  * I've gone completly out of my mind.
@@ -494,6 +495,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
         case CPU_R14000:
         case CPU_4KC:
         case CPU_4KEC:
+        case CPU_M14KC:
         case CPU_SB1:
         case CPU_SB1A:
         case CPU_4KSC:
diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c
index bf80921f2f56..284dea54faf5 100644
--- a/arch/mips/mti-malta/malta-pci.c
+++ b/arch/mips/mti-malta/malta-pci.c
@@ -241,8 +241,9 @@ void __init mips_pcibios_init(void)
                 return;
         }
 
-        if (controller->io_resource->start < 0x00001000UL)      /* FIXME */
-                controller->io_resource->start = 0x00001000UL;
+        /* Change start address to avoid conflicts with ACPI and SMB devices */
+        if (controller->io_resource->start < 0x00002000UL)
+                controller->io_resource->start = 0x00002000UL;
 
         iomem_resource.end &= 0xfffffffffULL;                   /* 64 GB */
         ioport_resource.end = controller->io_resource->end;
@@ -253,7 +254,7 @@ void __init mips_pcibios_init(void)
 }
 
 /* Enable PCI 2.1 compatibility in PIIX4 */
-static void __init quirk_dlcsetup(struct pci_dev *dev)
+static void __devinit quirk_dlcsetup(struct pci_dev *dev)
 {
         u8 odlc, ndlc;
         (void) pci_read_config_byte(dev, 0x82, &odlc);
diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c
index b7f37d4982fa..2e28f653f66d 100644
--- a/arch/mips/mti-malta/malta-setup.c
+++ b/arch/mips/mti-malta/malta-setup.c
@@ -111,7 +111,7 @@ static void __init pci_clock_check(void)
         unsigned int __iomem *jmpr_p =
                 (unsigned int *) ioremap(MALTA_JMPRS_REG, sizeof(unsigned int));
         int jmpr = (__raw_readl(jmpr_p) >> 2) & 0x07;
-        static const int pciclocks[] __initdata = {
+        static const int pciclocks[] __initconst = {
                 33, 20, 25, 30, 12, 16, 37, 10
         };
         int pciclock = pciclocks[jmpr];
diff --git a/arch/mips/netlogic/xlp/setup.c b/arch/mips/netlogic/xlp/setup.c
index acb677a1227c..b3df7c2aad1e 100644
--- a/arch/mips/netlogic/xlp/setup.c
+++ b/arch/mips/netlogic/xlp/setup.c
@@ -82,8 +82,10 @@ void __init prom_free_prom_memory(void)
 
 void xlp_mmu_init(void)
 {
+        /* enable extended TLB and Large Fixed TLB */
         write_c0_config6(read_c0_config6() | 0x24);
-        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+
+        /* set page mask of Fixed TLB in config7 */
         write_c0_config7(PM_DEFAULT_MASK >>
                 (13 + (ffz(PM_DEFAULT_MASK >> 13) / 2)));
 }
@@ -100,6 +102,10 @@ void __init prom_init(void)
         nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
 #ifdef CONFIG_SMP
         nlm_wakeup_secondary_cpus(0xffffffff);
+
+        /* update TLB size after waking up threads */
+        current_cpu_data.tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
+
         register_smp_ops(&nlm_smp_ops);
 #endif
 }
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index d1f2d4c52d42..b6e378211a2c 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -78,6 +78,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 
         switch (current_cpu_type()) {
         case CPU_5KC:
+        case CPU_M14KC:
         case CPU_20KC:
         case CPU_24K:
         case CPU_25KF:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index baba3bcaa3c2..4d80a856048d 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -322,6 +322,10 @@ static int __init mipsxx_init(void)
 
         op_model_mipsxx_ops.num_counters = counters;
         switch (current_cpu_type()) {
+        case CPU_M14KC:
+                op_model_mipsxx_ops.cpu_type = "mips/M14Kc";
+                break;
+
         case CPU_20KC:
                 op_model_mipsxx_ops.cpu_type = "mips/20K";
                 break;
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index d5d4c018fb04..0857ab8c3919 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -48,7 +48,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         return 0;
 }
 
-static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_nec_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
@@ -60,7 +60,7 @@ static void __init loongson2e_nec_fixup(struct pci_dev *pdev)
         pci_write_config_dword(pdev, 0xe4, 1 << 5);
 }
 
-static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func0_fixup(struct pci_dev *pdev)
 {
         unsigned char c;
 
@@ -135,7 +135,7 @@ static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev)
         printk(KERN_INFO"via686b fix: ISA bridge done\n");
 }
 
-static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func1_fixup(struct pci_dev *pdev)
 {
         printk(KERN_INFO"via686b fix: IDE\n");
 
@@ -168,19 +168,19 @@ static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev)
         printk(KERN_INFO"via686b fix: IDE done\n");
 }
 
-static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func2_fixup(struct pci_dev *pdev)
 {
         /* irq routing */
         pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10);
 }
 
-static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func3_fixup(struct pci_dev *pdev)
 {
         /* irq routing */
         pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11);
 }
 
-static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev)
+static void __devinit loongson2e_686b_func5_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
         unsigned char c;
diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c
index 4b9768d5d729..a7b917dcf604 100644
--- a/arch/mips/pci/fixup-lemote2f.c
+++ b/arch/mips/pci/fixup-lemote2f.c
@@ -96,21 +96,21 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
 }
 
 /* CS5536 SPEC. fixup */
-static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_isa_fixup(struct pci_dev *pdev)
 {
         /* the uart1 and uart2 interrupt in PIC is enabled as default */
         pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1);
         pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1);
 }
 
-static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ide_fixup(struct pci_dev *pdev)
 {
         /* setting the mutex pin as IDE function */
         pci_write_config_dword(pdev, PCI_IDE_CFG_REG,
                                CS5536_IDE_FLASH_SIGNATURE);
 }
 
-static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_acc_fixup(struct pci_dev *pdev)
 {
         /* enable the AUDIO interrupt in PIC  */
         pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1);
@@ -118,14 +118,14 @@ static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev)
         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0);
 }
 
-static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ohci_fixup(struct pci_dev *pdev)
 {
         /* enable the OHCI interrupt in PIC */
         /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */
         pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1);
 }
 
-static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
+static void __devinit loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
 {
         u32 hi, lo;
 
@@ -137,7 +137,7 @@ static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev)
         pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000);
 }
 
-static void __init loongson_nec_fixup(struct pci_dev *pdev)
+static void __devinit loongson_nec_fixup(struct pci_dev *pdev)
 {
         unsigned int val;
 
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index 0f48498bc231..70073c98ed32 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -49,10 +49,10 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
         return 0;
 }
 
-static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
+static void __devinit malta_piix_func0_fixup(struct pci_dev *pdev)
 {
         unsigned char reg_val;
-        static int piixirqmap[16] __initdata = {  /* PIIX PIRQC[A:D] irq mappings */
+        static int piixirqmap[16] __devinitdata = {  /* PIIX PIRQC[A:D] irq mappings */
                 0,  0,  0,  3,
                 4,  5,  6,  7,
                 0,  9, 10, 11,
@@ -83,7 +83,7 @@ static void __init malta_piix_func0_fixup(struct pci_dev *pdev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
          malta_piix_func0_fixup);
 
-static void __init malta_piix_func1_fixup(struct pci_dev *pdev)
+static void __devinit malta_piix_func1_fixup(struct pci_dev *pdev)
 {
         unsigned char reg_val;
 
diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c
index e08f49cb6875..8e4f8288eca2 100644
--- a/arch/mips/pci/fixup-mpc30x.c
+++ b/arch/mips/pci/fixup-mpc30x.c
@@ -22,13 +22,13 @@
 
 #include <asm/vr41xx/mpc30x.h>
 
-static const int internal_func_irqs[] __initdata = {
+static const int internal_func_irqs[] __initconst = {
         VRC4173_CASCADE_IRQ,
         VRC4173_AC97_IRQ,
         VRC4173_USB_IRQ,
 };
 
-static const int irq_tab_mpc30x[] __initdata = {
+static const int irq_tab_mpc30x[] __initconst = {
  [12] = VRC4173_PCMCIA1_IRQ,
  [13] = VRC4173_PCMCIA2_IRQ,
  [29] = MQ200_IRQ,
diff --git a/arch/mips/pci/fixup-sb1250.c b/arch/mips/pci/fixup-sb1250.c
index f0bb9146e6c0..d02900a72916 100644
--- a/arch/mips/pci/fixup-sb1250.c
+++ b/arch/mips/pci/fixup-sb1250.c
@@ -15,7 +15,7 @@
  * Set the BCM1250, etc. PCI host bridge's TRDY timeout
  * to the finite max.
  */
-static void __init quirk_sb1250_pci(struct pci_dev *dev)
+static void __devinit quirk_sb1250_pci(struct pci_dev *dev)
 {
         pci_write_config_byte(dev, 0x40, 0xff);
 }
@@ -25,7 +25,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
 /*
  * The BCM1250, etc. PCI/HT bridge reports as a host bridge.
  */
-static void __init quirk_sb1250_ht(struct pci_dev *dev)
+static void __devinit quirk_sb1250_ht(struct pci_dev *dev)
 {
         dev->class = PCI_CLASS_BRIDGE_PCI << 8;
 }
@@ -35,7 +35,7 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
 /*
  * Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
  */
-static void __init quirk_sp1011(struct pci_dev *dev)
+static void __devinit quirk_sp1011(struct pci_dev *dev)
 {
         pci_write_config_byte(dev, 0x64, 0xff);
 }
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index a1e7e6d80c8c..bc13e29d2bb3 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -495,7 +495,7 @@ irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id)
 }
 
 #ifdef CONFIG_TOSHIBA_FPCIB0
-static void __init tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
+static void __devinit tx4927_quirk_slc90e66_bridge(struct pci_dev *dev)
 {
         struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(dev->bus);
 
diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c
index 0fbe4c0c170a..fdc24440294c 100644
--- a/arch/mips/pci/pci-ip27.c
+++ b/arch/mips/pci/pci-ip27.c
@@ -212,7 +212,7 @@ static inline void pci_enable_swapping(struct pci_dev *dev)
         bridge->b_widget.w_tflush;      /* Flush */
 }
 
-static void __init pci_fixup_ioc3(struct pci_dev *d)
+static void __devinit pci_fixup_ioc3(struct pci_dev *d)
 {
         pci_disable_swapping(d);
 }
diff --git a/arch/mips/pci/pci-lantiq.c b/arch/mips/pci/pci-lantiq.c
index ea453532a33c..075d87acd12a 100644
--- a/arch/mips/pci/pci-lantiq.c
+++ b/arch/mips/pci/pci-lantiq.c
@@ -129,7 +129,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
 
         /* setup reset gpio used by pci */
         reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
-        if (reset_gpio > 0)
+        if (gpio_is_valid(reset_gpio))
                 devm_gpio_request(&pdev->dev, reset_gpio, "pci-reset");
 
         /* enable auto-switching between PCI and EBU */
@@ -192,7 +192,7 @@ static int __devinit ltq_pci_startup(struct platform_device *pdev)
         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
 
         /* toggle reset pin */
-        if (reset_gpio > 0) {
+        if (gpio_is_valid(reset_gpio)) {
                 __gpio_set_value(reset_gpio, 0);
                 wmb();
                 mdelay(1);
diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c
index 1644805a6730..172af1cd5867 100644
--- a/arch/mips/pci/pci-xlr.c
+++ b/arch/mips/pci/pci-xlr.c
@@ -41,6 +41,7 @@
 #include <linux/irq.h>
 #include <linux/irqdesc.h>
 #include <linux/console.h>
+#include <linux/pci_regs.h>
 
 #include <asm/io.h>
 
@@ -156,35 +157,55 @@ struct pci_controller nlm_pci_controller = {
         .io_offset      = 0x00000000UL,
 };
 
+/*
+ * The top level PCIe links on the XLS PCIe controller appear as
+ * bridges. Given a device, this function finds which link it is
+ * on.
+ */
+static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev)
+{
+        struct pci_bus *bus, *p;
+
+        /* Find the bridge on bus 0 */
+        bus = dev->bus;
+        for (p = bus->parent; p && p->number != 0; p = p->parent)
+                bus = p;
+
+        return p ? bus->self : NULL;
+}
+
 static int get_irq_vector(const struct pci_dev *dev)
 {
+        struct pci_dev *lnk;
+
         if (!nlm_chip_is_xls())
-                return  PIC_PCIX_IRQ;   /* for XLR just one IRQ*/
+                return  PIC_PCIX_IRQ;   /* for XLR just one IRQ */
 
         /*
          * For XLS PCIe, there is an IRQ per Link, find out which
          * link the device is on to assign interrupts
-        */
-        if (dev->bus->self == NULL)
+         */
+        lnk = xls_get_pcie_link(dev);
+        if (lnk == NULL)
                 return 0;
 
-        switch  (dev->bus->self->devfn) {
-        case 0x0:
+        switch  (PCI_SLOT(lnk->devfn)) {
+        case 0:
                 return PIC_PCIE_LINK0_IRQ;
-        case 0x8:
+        case 1:
                 return PIC_PCIE_LINK1_IRQ;
-        case 0x10:
+        case 2:
                 if (nlm_chip_is_xls_b())
                         return PIC_PCIE_XLSB0_LINK2_IRQ;
                 else
                         return PIC_PCIE_LINK2_IRQ;
-        case 0x18:
+        case 3:
                 if (nlm_chip_is_xls_b())
                         return PIC_PCIE_XLSB0_LINK3_IRQ;
                 else
                         return PIC_PCIE_LINK3_IRQ;
         }
-        WARN(1, "Unexpected devfn %d\n", dev->bus->self->devfn);
+        WARN(1, "Unexpected devfn %d\n", lnk->devfn);
         return 0;
 }
 
@@ -202,7 +223,27 @@ void arch_teardown_msi_irq(unsigned int irq)
 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
 {
         struct msi_msg msg;
+        struct pci_dev *lnk;
         int irq, ret;
+        u16 val;
+
+        /* MSI not supported on XLR */
+        if (!nlm_chip_is_xls())
+                return 1;
+
+        /*
+         * Enable MSI on the XLS PCIe controller bridge which was disabled
+         * at enumeration, the bridge MSI capability is at 0x50
+         */
+        lnk = xls_get_pcie_link(dev);
+        if (lnk == NULL)
+                return 1;
+
+        pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val);
+        if ((val & PCI_MSI_FLAGS_ENABLE) == 0) {
+                val |= PCI_MSI_FLAGS_ENABLE;
+                pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val);
+        }
 
         irq = get_irq_vector(dev);
         if (irq <= 0)
@@ -327,7 +368,7 @@ static int __init pcibios_init(void)
                 }
         } else {
                 /* XLR PCI controller ACK */
-                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
+                irq_set_handler_data(PIC_PCIX_IRQ, xlr_pci_ack);
         }
 
         return 0;
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
index b71fae231049..5edab2bc6fc0 100644
--- a/arch/mips/pmc-sierra/yosemite/smp.c
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -115,11 +115,11 @@ static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
  */
 static void __cpuinit yos_init_secondary(void)
 {
-        set_c0_status(ST0_CO | ST0_IE | ST0_IM);
 }
 
 static void __cpuinit yos_smp_finish(void)
 {
+        set_c0_status(ST0_CO | ST0_IM | ST0_IE);
 }
 
 /* Hook for after all CPUs are online */
diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c
index 0a170e0ffeaa..7773f3d956b0 100644
--- a/arch/mips/powertv/asic/asic-calliope.c
+++ b/arch/mips/powertv/asic/asic-calliope.c
@@ -28,7 +28,7 @@
 
 #define CALLIOPE_ADDR(x)        (CALLIOPE_IO_BASE + (x))
 
-const struct register_map calliope_register_map __initdata = {
+const struct register_map calliope_register_map __initconst = {
         .eic_slow0_strt_add = {.phys = CALLIOPE_ADDR(0x800000)},
         .eic_cfg_bits = {.phys = CALLIOPE_ADDR(0x800038)},
         .eic_ready_status = {.phys = CALLIOPE_ADDR(0x80004c)},
diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c
index bbc0c122be5e..da076db7b7ed 100644
--- a/arch/mips/powertv/asic/asic-cronus.c
+++ b/arch/mips/powertv/asic/asic-cronus.c
@@ -28,7 +28,7 @@
 
 #define CRONUS_ADDR(x)  (CRONUS_IO_BASE + (x))
 
-const struct register_map cronus_register_map __initdata = {
+const struct register_map cronus_register_map __initconst = {
         .eic_slow0_strt_add = {.phys = CRONUS_ADDR(0x000000)},
         .eic_cfg_bits = {.phys = CRONUS_ADDR(0x000038)},
         .eic_ready_status = {.phys = CRONUS_ADDR(0x00004C)},
diff --git a/arch/mips/powertv/asic/asic-gaia.c b/arch/mips/powertv/asic/asic-gaia.c
index 91dda682752c..47683b370e74 100644
--- a/arch/mips/powertv/asic/asic-gaia.c
+++ b/arch/mips/powertv/asic/asic-gaia.c
@@ -23,7 +23,7 @@
 #include <linux/init.h>
 #include <asm/mach-powertv/asic.h>
 
-const struct register_map gaia_register_map __initdata = {
+const struct register_map gaia_register_map __initconst = {
         .eic_slow0_strt_add = {.phys = GAIA_IO_BASE + 0x000000},
         .eic_cfg_bits = {.phys = GAIA_IO_BASE + 0x000038},
         .eic_ready_status = {.phys = GAIA_IO_BASE + 0x00004C},
diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c
index 4a05bb096476..6ff4b10f09da 100644
--- a/arch/mips/powertv/asic/asic-zeus.c
+++ b/arch/mips/powertv/asic/asic-zeus.c
@@ -28,7 +28,7 @@
 
 #define ZEUS_ADDR(x)    (ZEUS_IO_BASE + (x))
 
-const struct register_map zeus_register_map __initdata = {
+const struct register_map zeus_register_map __initconst = {
         .eic_slow0_strt_add = {.phys = ZEUS_ADDR(0x000000)},
         .eic_cfg_bits = {.phys = ZEUS_ADDR(0x000038)},
         .eic_ready_status = {.phys = ZEUS_ADDR(0x00004c)},
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
index 682efb0c108d..64eb71b15280 100644
--- a/arch/mips/txx9/generic/pci.c
+++ b/arch/mips/txx9/generic/pci.c
@@ -269,7 +269,7 @@ txx9_i8259_irq_setup(int irq)
         return err;
 }
 
-static void __init quirk_slc90e66_bridge(struct pci_dev *dev)
+static void __devinit quirk_slc90e66_bridge(struct pci_dev *dev)
 {
         int irq;        /* PCI/ISA Bridge interrupt */
         u8 reg_64;
diff --git a/arch/mn10300/include/asm/ptrace.h b/arch/mn10300/include/asm/ptrace.h
index 55b79ef10028..44251b974f1d 100644
--- a/arch/mn10300/include/asm/ptrace.h
+++ b/arch/mn10300/include/asm/ptrace.h
@@ -81,9 +81,6 @@ struct pt_regs {
 #define PTRACE_GETFPREGS          14
 #define PTRACE_SETFPREGS          15
 
-/* options set using PTRACE_SETOPTIONS */
-#define PTRACE_O_TRACESYSGOOD     0x00000001
-
 #ifdef __KERNEL__
 
 #define user_mode(regs)                 (((regs)->epsw & EPSW_nSL) == EPSW_nSL)
diff --git a/arch/mn10300/include/asm/thread_info.h b/arch/mn10300/include/asm/thread_info.h
index 08251d6f6b11..ac519bbd42ff 100644
--- a/arch/mn10300/include/asm/thread_info.h
+++ b/arch/mn10300/include/asm/thread_info.h
@@ -123,7 +123,7 @@ static inline unsigned long current_stack_pointer(void)
 }
 
 #ifndef CONFIG_KGDB
-void arch_release_thread_info(struct thread_info *ti)
+void arch_release_thread_info(struct thread_info *ti);
 #endif
 #define get_thread_info(ti)     get_task_struct((ti)->task)
 #define put_thread_info(ti)     put_task_struct((ti)->task)
diff --git a/arch/mn10300/include/asm/timex.h b/arch/mn10300/include/asm/timex.h
index bd4e90dfe6c2..f8e66425cbf8 100644
--- a/arch/mn10300/include/asm/timex.h
+++ b/arch/mn10300/include/asm/timex.h
@@ -11,7 +11,6 @@
 #ifndef _ASM_TIMEX_H
 #define _ASM_TIMEX_H
 
-#include <asm/hardirq.h>
 #include <unit/timex.h>
 
 #define TICK_SIZE (tick_nsec / 1000)
@@ -30,16 +29,6 @@ static inline cycles_t get_cycles(void)
 extern int init_clockevents(void);
 extern int init_clocksource(void);
 
-static inline void setup_jiffies_interrupt(int irq,
-                                           struct irqaction *action)
-{
-        u16 tmp;
-        setup_irq(irq, action);
-        set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL));
-        GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
-        tmp = GxICR(irq);
-}
-
 #endif /* __KERNEL__ */
 
 #endif /* _ASM_TIMEX_H */
diff --git a/arch/mn10300/kernel/cevt-mn10300.c b/arch/mn10300/kernel/cevt-mn10300.c
index 69cae0260786..ccce35e3e179 100644
--- a/arch/mn10300/kernel/cevt-mn10300.c
+++ b/arch/mn10300/kernel/cevt-mn10300.c
@@ -70,6 +70,16 @@ static void event_handler(struct clock_event_device *dev)
 {
 }
 
+static inline void setup_jiffies_interrupt(int irq,
+                                           struct irqaction *action)
+{
+        u16 tmp;
+        setup_irq(irq, action);
+        set_intr_level(irq, NUM2GxICR_LEVEL(CONFIG_TIMER_IRQ_LEVEL));
+        GxICR(irq) |= GxICR_ENABLE | GxICR_DETECT | GxICR_REQUEST;
+        tmp = GxICR(irq);
+}
+
 int __init init_clockevents(void)
 {
         struct clock_event_device *cd;
diff --git a/arch/mn10300/kernel/internal.h b/arch/mn10300/kernel/internal.h
index a5ac755dd69f..2df440105a80 100644
--- a/arch/mn10300/kernel/internal.h
+++ b/arch/mn10300/kernel/internal.h
@@ -9,6 +9,8 @@
  * 2 of the Licence, or (at your option) any later version.
  */
 
+#include <linux/irqreturn.h>
+
 struct clocksource;
 struct clock_event_device;
 
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 2381df83bd00..35932a8de8b8 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -170,9 +170,9 @@ mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
         case SC1TXIRQ:
 #ifdef CONFIG_MN10300_TTYSM1_TIMER12
         case TM12IRQ:
-#elif CONFIG_MN10300_TTYSM1_TIMER9
+#elif defined(CONFIG_MN10300_TTYSM1_TIMER9)
         case TM9IRQ:
-#elif CONFIG_MN10300_TTYSM1_TIMER3
+#elif defined(CONFIG_MN10300_TTYSM1_TIMER3)
         case TM3IRQ:
 #endif /* CONFIG_MN10300_TTYSM1_TIMER12 */
 #endif /* CONFIG_MN10300_TTYSM1 */
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c
index 6ab0bee2a54f..4d584ae29ae1 100644
--- a/arch/mn10300/kernel/signal.c
+++ b/arch/mn10300/kernel/signal.c
@@ -459,10 +459,11 @@ static int handle_signal(int sig,
         else
                 ret = setup_frame(sig, ka, oldset, regs);
         if (ret)
-                return;
+                return ret;
 
         signal_delivered(sig, info, ka, regs,
-                                 test_thread_flag(TIF_SINGLESTEP));
+                         test_thread_flag(TIF_SINGLESTEP));
+        return 0;
 }
 
 /*
diff --git a/arch/mn10300/kernel/traps.c b/arch/mn10300/kernel/traps.c
index 94a9c6d53e1b..b900e5afa0ae 100644
--- a/arch/mn10300/kernel/traps.c
+++ b/arch/mn10300/kernel/traps.c
@@ -26,6 +26,7 @@
 #include <linux/kdebug.h>
 #include <linux/bug.h>
 #include <linux/irq.h>
+#include <linux/export.h>
 #include <asm/processor.h>
 #include <linux/uaccess.h>
 #include <asm/io.h>
diff --git a/arch/mn10300/mm/dma-alloc.c b/arch/mn10300/mm/dma-alloc.c
index 159acb02cfd4..e244ebe637e1 100644
--- a/arch/mn10300/mm/dma-alloc.c
+++ b/arch/mn10300/mm/dma-alloc.c
@@ -15,6 +15,7 @@
 #include <linux/string.h>
 #include <linux/pci.h>
 #include <linux/gfp.h>
+#include <linux/export.h>
 #include <asm/io.h>
 
 static unsigned long pci_sram_allocated = 0xbc000000;
diff --git a/arch/mn10300/unit-asb2303/include/unit/timex.h b/arch/mn10300/unit-asb2303/include/unit/timex.h
index cc18fe7d8b90..c37f9832cf17 100644
--- a/arch/mn10300/unit-asb2303/include/unit/timex.h
+++ b/arch/mn10300/unit-asb2303/include/unit/timex.h
@@ -11,10 +11,6 @@
 #ifndef _ASM_UNIT_TIMEX_H
 #define _ASM_UNIT_TIMEX_H
 
-#ifndef __ASSEMBLY__
-#include <linux/irq.h>
-#endif /* __ASSEMBLY__ */
-
 #include <asm/timer-regs.h>
 #include <unit/clock.h>
 #include <asm/param.h>
diff --git a/arch/mn10300/unit-asb2303/smc91111.c b/arch/mn10300/unit-asb2303/smc91111.c
index 43c246439413..53677694b165 100644
--- a/arch/mn10300/unit-asb2303/smc91111.c
+++ b/arch/mn10300/unit-asb2303/smc91111.c
@@ -15,6 +15,7 @@
 #include <linux/platform_device.h>
 
 #include <asm/io.h>
+#include <asm/irq.h>
 #include <asm/timex.h>
 #include <asm/processor.h>
 #include <asm/intctl-regs.h>
diff --git a/arch/mn10300/unit-asb2305/include/unit/timex.h b/arch/mn10300/unit-asb2305/include/unit/timex.h
index 758af30d1a16..4cefc224f448 100644
--- a/arch/mn10300/unit-asb2305/include/unit/timex.h
+++ b/arch/mn10300/unit-asb2305/include/unit/timex.h
@@ -11,10 +11,6 @@
 #ifndef _ASM_UNIT_TIMEX_H
 #define _ASM_UNIT_TIMEX_H
 
-#ifndef __ASSEMBLY__
-#include <linux/irq.h>
-#endif /* __ASSEMBLY__ */
-
 #include <asm/timer-regs.h>
 #include <unit/clock.h>
 #include <asm/param.h>
diff --git a/arch/mn10300/unit-asb2305/unit-init.c b/arch/mn10300/unit-asb2305/unit-init.c
index e1becd6b7571..bc4adfaf815c 100644
--- a/arch/mn10300/unit-asb2305/unit-init.c
+++ b/arch/mn10300/unit-asb2305/unit-init.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <asm/io.h>
+#include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/processor.h>
 #include <asm/intctl-regs.h>
diff --git a/arch/mn10300/unit-asb2364/include/unit/timex.h b/arch/mn10300/unit-asb2364/include/unit/timex.h
index ddb7ed010706..42f32db75087 100644
--- a/arch/mn10300/unit-asb2364/include/unit/timex.h
+++ b/arch/mn10300/unit-asb2364/include/unit/timex.h
@@ -11,10 +11,6 @@
 #ifndef _ASM_UNIT_TIMEX_H
 #define _ASM_UNIT_TIMEX_H
 
-#ifndef __ASSEMBLY__
-#include <linux/irq.h>
-#endif /* __ASSEMBLY__ */
-
 #include <asm/timer-regs.h>
 #include <unit/clock.h>
 #include <asm/param.h>
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 6eb75b80488c..0554ab062bdc 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -86,8 +86,8 @@ static inline bool arch_irqs_disabled(void)
 }
 
 #ifdef CONFIG_PPC_BOOK3E
-#define __hard_irq_enable()     asm volatile("wrteei 1" : : : "memory");
-#define __hard_irq_disable()    asm volatile("wrteei 0" : : : "memory");
+#define __hard_irq_enable()     asm volatile("wrteei 1" : : : "memory")
+#define __hard_irq_disable()    asm volatile("wrteei 0" : : : "memory")
 #else
 #define __hard_irq_enable()     __mtmsrd(local_paca->kernel_msr | MSR_EE, 1)
 #define __hard_irq_disable()    __mtmsrd(local_paca->kernel_msr, 1)
@@ -125,6 +125,8 @@ static inline bool arch_irq_disabled_regs(struct pt_regs *regs)
         return !regs->softe;
 }
 
+extern bool prep_irq_for_idle(void);
+
 #else /* CONFIG_PPC64 */
 
 #define SET_MSR_EE(x)   mtmsr(x)
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 1b415027ec0e..1f017bb7a7ce 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -229,7 +229,7 @@ notrace void arch_local_irq_restore(unsigned long en)
          */
         if (unlikely(irq_happened != PACA_IRQ_HARD_DIS))
                 __hard_irq_disable();
-#ifdef CONFIG_TRACE_IRQFLAG
+#ifdef CONFIG_TRACE_IRQFLAGS
         else {
                 /*
                  * We should already be hard disabled here. We had bugs
@@ -286,6 +286,52 @@ void notrace restore_interrupts(void)
                 __hard_irq_enable();
 }
 
+/*
+ * This is a helper to use when about to go into idle low-power
+ * when the latter has the side effect of re-enabling interrupts
+ * (such as calling H_CEDE under pHyp).
+ *
+ * You call this function with interrupts soft-disabled (this is
+ * already the case when ppc_md.power_save is called). The function
+ * will return whether to enter power save or just return.
+ *
+ * In the former case, it will have notified lockdep of interrupts
+ * being re-enabled and generally sanitized the lazy irq state,
+ * and in the latter case it will leave with interrupts hard
+ * disabled and marked as such, so the local_irq_enable() call
+ * in cpu_idle() will properly re-enable everything.
+ */
+bool prep_irq_for_idle(void)
+{
+        /*
+         * First we need to hard disable to ensure no interrupt
+         * occurs before we effectively enter the low power state
+         */
+        hard_irq_disable();
+
+        /*
+         * If anything happened while we were soft-disabled,
+         * we return now and do not enter the low power state.
+         */
+        if (lazy_irq_pending())
+                return false;
+
+        /* Tell lockdep we are about to re-enable */
+        trace_hardirqs_on();
+
+        /*
+         * Mark interrupts as soft-enabled and clear the
+         * PACA_IRQ_HARD_DIS from the pending mask since we
+         * are about to hard enable as well as a side effect
+         * of entering the low power state.
+         */
+        local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
+        local_paca->soft_enabled = 1;
+
+        /* Tell the caller to enter the low power state */
+        return true;
+}
+
 #endif /* CONFIG_PPC64 */
 
 int arch_show_interrupts(struct seq_file *p, int prec)
diff --git a/arch/powerpc/kvm/book3s_pr_papr.c b/arch/powerpc/kvm/book3s_pr_papr.c
index 3ff9013d6e79..ee02b30878ed 100644
--- a/arch/powerpc/kvm/book3s_pr_papr.c
+++ b/arch/powerpc/kvm/book3s_pr_papr.c
@@ -241,6 +241,7 @@ int kvmppc_h_pr(struct kvm_vcpu *vcpu, unsigned long cmd)
         case H_PUT_TCE:
                 return kvmppc_h_pr_put_tce(vcpu);
         case H_CEDE:
+                vcpu->arch.shared->msr |= MSR_EE;
                 kvm_vcpu_block(vcpu);
                 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
                 vcpu->stat.halt_wakeup++;
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index 6e8f677f5646..1e95556dc692 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -639,7 +639,7 @@ static void __init parse_drconf_memory(struct device_node *memory)
         unsigned int n, rc, ranges, is_kexec_kdump = 0;
         unsigned long lmb_size, base, size, sz;
         int nid;
-        struct assoc_arrays aa;
+        struct assoc_arrays aa = { .arrays = NULL };
 
         n = of_get_drconf_memory(memory, &dm);
         if (!n)
diff --git a/arch/powerpc/platforms/cell/pervasive.c b/arch/powerpc/platforms/cell/pervasive.c
index efdacc829576..d17e98bc0c10 100644
--- a/arch/powerpc/platforms/cell/pervasive.c
+++ b/arch/powerpc/platforms/cell/pervasive.c
@@ -42,11 +42,9 @@ static void cbe_power_save(void)
 {
         unsigned long ctrl, thread_switch_control;
 
-        /*
-         * We need to hard disable interrupts, the local_irq_enable() done by
-         * our caller upon return will hard re-enable.
-         */
-        hard_irq_disable();
+        /* Ensure our interrupt state is properly tracked */
+        if (!prep_irq_for_idle())
+                return;
 
         ctrl = mfspr(SPRN_CTRLF);
 
@@ -81,6 +79,9 @@ static void cbe_power_save(void)
          */
         ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
         mtspr(SPRN_CTRLT, ctrl);
+
+        /* Re-enable interrupts in MSR */
+        __hard_irq_enable();
 }
 
 static int cbe_system_reset_exception(struct pt_regs *regs)
diff --git a/arch/powerpc/platforms/pseries/processor_idle.c b/arch/powerpc/platforms/pseries/processor_idle.c
index e61483e8e960..c71be66bd5dc 100644
--- a/arch/powerpc/platforms/pseries/processor_idle.c
+++ b/arch/powerpc/platforms/pseries/processor_idle.c
@@ -99,15 +99,18 @@ out:
 static void check_and_cede_processor(void)
 {
         /*
-         * Interrupts are soft-disabled at this point,
-         * but not hard disabled. So an interrupt might have
-         * occurred before entering NAP, and would be potentially
-         * lost (edge events, decrementer events, etc...) unless
-         * we first hard disable then check.
+         * Ensure our interrupt state is properly tracked,
+         * also checks if no interrupt has occurred while we
+         * were soft-disabled
          */
-        hard_irq_disable();
-        if (!lazy_irq_pending())
+        if (prep_irq_for_idle()) {
                 cede_processor();
+#ifdef CONFIG_TRACE_IRQFLAGS
+                /* Ensure that H_CEDE returns with IRQs on */
+                if (WARN_ON(!(mfmsr() & MSR_EE)))
+                        __hard_irq_enable();
+#endif
+        }
 }
 
 static int dedicated_cede_loop(struct cpuidle_device *dev,
diff --git a/arch/sh/include/asm/io_noioport.h b/arch/sh/include/asm/io_noioport.h
index e136d28d1d2e..4d48f1436a63 100644
--- a/arch/sh/include/asm/io_noioport.h
+++ b/arch/sh/include/asm/io_noioport.h
@@ -19,9 +19,20 @@ static inline u32 inl(unsigned long addr)
         return -1;
 }
 
-#define outb(x, y)      BUG()
-#define outw(x, y)      BUG()
-#define outl(x, y)      BUG()
+static inline void outb(unsigned char x, unsigned long port)
+{
+        BUG();
+}
+
+static inline void outw(unsigned short x, unsigned long port)
+{
+        BUG();
+}
+
+static inline void outl(unsigned int x, unsigned long port)
+{
+        BUG();
+}
 
 #define inb_p(addr)     inb(addr)
 #define inw_p(addr)     inw(addr)
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7720.c b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
index 8832c526cdf9..c4a0336660dd 100644
--- a/arch/sh/kernel/cpu/sh3/serial-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
@@ -2,7 +2,7 @@
 #include <linux/serial_core.h>
 #include <linux/io.h>
 #include <cpu/serial.h>
-#include <asm/gpio.h>
+#include <cpu/gpio.h>
 
 static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
 {
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c
index 9092ce8aa6b4..f8b74ca83b92 100644
--- a/arch/tile/kernel/backtrace.c
+++ b/arch/tile/kernel/backtrace.c
@@ -14,6 +14,7 @@
 
 #include <linux/kernel.h>
 #include <linux/string.h>
+#include <asm/byteorder.h>
 #include <asm/backtrace.h>
 #include <asm/tile-desc.h>
 #include <arch/abi.h>
@@ -336,8 +337,12 @@ static void find_caller_pc_and_caller_sp(CallerLocation *location,
                                 bytes_to_prefetch / sizeof(tile_bundle_bits);
                 }
 
-                /* Decode the next bundle. */
-                bundle.bits = prefetched_bundles[next_bundle++];
+                /*
+                 * Decode the next bundle.
+                 * TILE always stores instruction bundles in little-endian
+                 * mode, even when the chip is running in big-endian mode.
+                 */
+                bundle.bits = le64_to_cpu(prefetched_bundles[next_bundle++]);
                 bundle.num_insns =
                         parse_insn_tile(bundle.bits, pc, bundle.insns);
                 num_info_ops = bt_get_info_ops(&bundle, info_operands);
diff --git a/arch/um/drivers/mconsole_kern.c b/arch/um/drivers/mconsole_kern.c
index 88e466b159dc..43b39d61b538 100644
--- a/arch/um/drivers/mconsole_kern.c
+++ b/arch/um/drivers/mconsole_kern.c
@@ -705,7 +705,6 @@ static void stack_proc(void *arg)
         struct task_struct *from = current, *to = arg;
 
         to->thread.saved_task = from;
-        rcu_switch_from(from);
         switch_to(from, to, from);
 }
 
diff --git a/arch/x86/kernel/vsyscall_64.c b/arch/x86/kernel/vsyscall_64.c
index 7515cf0e1805..5db36caf4289 100644
--- a/arch/x86/kernel/vsyscall_64.c
+++ b/arch/x86/kernel/vsyscall_64.c
@@ -139,6 +139,19 @@ static int addr_to_vsyscall_nr(unsigned long addr)
         return nr;
 }
 
+#ifdef CONFIG_SECCOMP
+static int vsyscall_seccomp(struct task_struct *tsk, int syscall_nr)
+{
+        if (!seccomp_mode(&tsk->seccomp))
+                return 0;
+        task_pt_regs(tsk)->orig_ax = syscall_nr;
+        task_pt_regs(tsk)->ax = syscall_nr;
+        return __secure_computing(syscall_nr);
+}
+#else
+#define vsyscall_seccomp(_tsk, _nr) 0
+#endif
+
 static bool write_ok_or_segv(unsigned long ptr, size_t size)
 {
         /*
@@ -174,6 +187,7 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
         int vsyscall_nr;
         int prev_sig_on_uaccess_error;
         long ret;
+        int skip;
 
         /*
          * No point in checking CS -- the only way to get here is a user mode
@@ -205,9 +219,6 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
         }
 
         tsk = current;
-        if (seccomp_mode(&tsk->seccomp))
-                do_exit(SIGKILL);
-
         /*
          * With a real vsyscall, page faults cause SIGSEGV.  We want to
          * preserve that behavior to make writing exploits harder.
@@ -222,8 +233,13 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
          * address 0".
          */
         ret = -EFAULT;
+        skip = 0;
         switch (vsyscall_nr) {
         case 0:
+                skip = vsyscall_seccomp(tsk, __NR_gettimeofday);
+                if (skip)
+                        break;
+
                 if (!write_ok_or_segv(regs->di, sizeof(struct timeval)) ||
                     !write_ok_or_segv(regs->si, sizeof(struct timezone)))
                         break;
@@ -234,6 +250,10 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
                 break;
 
         case 1:
+                skip = vsyscall_seccomp(tsk, __NR_time);
+                if (skip)
+                        break;
+
                 if (!write_ok_or_segv(regs->di, sizeof(time_t)))
                         break;
 
@@ -241,6 +261,10 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
                 break;
 
         case 2:
+                skip = vsyscall_seccomp(tsk, __NR_getcpu);
+                if (skip)
+                        break;
+
                 if (!write_ok_or_segv(regs->di, sizeof(unsigned)) ||
                     !write_ok_or_segv(regs->si, sizeof(unsigned)))
                         break;
@@ -253,6 +277,12 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
 
         current_thread_info()->sig_on_uaccess_error = prev_sig_on_uaccess_error;
 
+        if (skip) {
+                if ((long)regs->ax <= 0L) /* seccomp errno emulation */
+                        goto do_ret;
+                goto done; /* seccomp trace/trap */
+        }
+
         if (ret == -EFAULT) {
                 /* Bad news -- userspace fed a bad pointer to a vsyscall. */
                 warn_bad_vsyscall(KERN_INFO, regs,
@@ -271,10 +301,11 @@ bool emulate_vsyscall(struct pt_regs *regs, unsigned long address)
 
         regs->ax = ret;
 
+do_ret:
         /* Emulate a ret instruction. */
         regs->ip = caller;
         regs->sp += 8;
-
+done:
         return true;
 
 sigsegv:
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c
index 9b306e550e3f..2c8d6a3d250a 100644
--- a/arch/xtensa/kernel/process.c
+++ b/arch/xtensa/kernel/process.c
@@ -277,7 +277,7 @@ void xtensa_elf_core_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs)
 
         /* Don't leak any random bits. */
 
-        memset(elfregs, 0, sizeof (elfregs));
+        memset(elfregs, 0, sizeof(*elfregs));
 
         /* Note:  PS.EXCM is not set while user task is running; its
          * being set in regs->ps is for exception handling convenience.