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-rw-r--r--arch/arm/mach-at91rm9200/at91rm9200.c45
-rw-r--r--arch/arm/mach-at91rm9200/generic.h8
-rw-r--r--arch/arm/mach-at91rm9200/irq.c70
-rw-r--r--arch/arm/mach-pnx4008/core.c2
-rw-r--r--arch/arm/mach-pnx4008/dma.c1
-rw-r--r--arch/arm/mach-pnx4008/irq.c22
-rw-r--r--arch/arm/mach-pnx4008/time.c8
7 files changed, 79 insertions, 77 deletions
diff --git a/arch/arm/mach-at91rm9200/at91rm9200.c b/arch/arm/mach-at91rm9200/at91rm9200.c
index 7e1d072bdd80..0985b1c42c7c 100644
--- a/arch/arm/mach-at91rm9200/at91rm9200.c
+++ b/arch/arm/mach-at91rm9200/at91rm9200.c
@@ -107,3 +107,48 @@ void __init at91rm9200_map_io(void)
107 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc)); 107 iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
108} 108}
109 109
110/*
111 * The default interrupt priority levels (0 = lowest, 7 = highest).
112 */
113static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
114 7, /* Advanced Interrupt Controller (FIQ) */
115 7, /* System Peripherals */
116 0, /* Parallel IO Controller A */
117 0, /* Parallel IO Controller B */
118 0, /* Parallel IO Controller C */
119 0, /* Parallel IO Controller D */
120 6, /* USART 0 */
121 6, /* USART 1 */
122 6, /* USART 2 */
123 6, /* USART 3 */
124 0, /* Multimedia Card Interface */
125 4, /* USB Device Port */
126 0, /* Two-Wire Interface */
127 6, /* Serial Peripheral Interface */
128 5, /* Serial Synchronous Controller 0 */
129 5, /* Serial Synchronous Controller 1 */
130 5, /* Serial Synchronous Controller 2 */
131 0, /* Timer Counter 0 */
132 0, /* Timer Counter 1 */
133 0, /* Timer Counter 2 */
134 0, /* Timer Counter 3 */
135 0, /* Timer Counter 4 */
136 0, /* Timer Counter 5 */
137 3, /* USB Host port */
138 3, /* Ethernet MAC */
139 0, /* Advanced Interrupt Controller (IRQ0) */
140 0, /* Advanced Interrupt Controller (IRQ1) */
141 0, /* Advanced Interrupt Controller (IRQ2) */
142 0, /* Advanced Interrupt Controller (IRQ3) */
143 0, /* Advanced Interrupt Controller (IRQ4) */
144 0, /* Advanced Interrupt Controller (IRQ5) */
145 0 /* Advanced Interrupt Controller (IRQ6) */
146};
147
148void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
149{
150 if (!priority)
151 priority = at91rm9200_default_irq_priority;
152
153 at91_aic_init(priority);
154}
diff --git a/arch/arm/mach-at91rm9200/generic.h b/arch/arm/mach-at91rm9200/generic.h
index f0d969d7d874..7979d8ab7e07 100644
--- a/arch/arm/mach-at91rm9200/generic.h
+++ b/arch/arm/mach-at91rm9200/generic.h
@@ -8,13 +8,19 @@
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10 10
11void at91_gpio_irq_setup(unsigned banks); 11 /* Interrupts */
12extern void __init at91rm9200_init_irq(unsigned int priority[]);
13extern void __init at91_aic_init(unsigned int priority[]);
14extern void __init at91_gpio_irq_setup(unsigned banks);
12 15
16 /* Timer */
13struct sys_timer; 17struct sys_timer;
14extern struct sys_timer at91rm9200_timer; 18extern struct sys_timer at91rm9200_timer;
15 19
20 /* Memory Map */
16extern void __init at91rm9200_map_io(void); 21extern void __init at91rm9200_map_io(void);
17 22
23 /* Clocks */
18extern int __init at91_clock_init(unsigned long main_clock); 24extern int __init at91_clock_init(unsigned long main_clock);
19struct device; 25struct device;
20extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func); 26extern void __init at91_clock_associate(const char *id, struct device *dev, const char *func);
diff --git a/arch/arm/mach-at91rm9200/irq.c b/arch/arm/mach-at91rm9200/irq.c
index dcd560dbcfb7..9b0911320417 100644
--- a/arch/arm/mach-at91rm9200/irq.c
+++ b/arch/arm/mach-at91rm9200/irq.c
@@ -36,58 +36,20 @@
36 36
37#include "generic.h" 37#include "generic.h"
38 38
39/*
40 * The default interrupt priority levels (0 = lowest, 7 = highest).
41 */
42static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
43 7, /* Advanced Interrupt Controller */
44 7, /* System Peripheral */
45 0, /* Parallel IO Controller A */
46 0, /* Parallel IO Controller B */
47 0, /* Parallel IO Controller C */
48 0, /* Parallel IO Controller D */
49 6, /* USART 0 */
50 6, /* USART 1 */
51 6, /* USART 2 */
52 6, /* USART 3 */
53 0, /* Multimedia Card Interface */
54 4, /* USB Device Port */
55 0, /* Two-Wire Interface */
56 6, /* Serial Peripheral Interface */
57 5, /* Serial Synchronous Controller */
58 5, /* Serial Synchronous Controller */
59 5, /* Serial Synchronous Controller */
60 0, /* Timer Counter 0 */
61 0, /* Timer Counter 1 */
62 0, /* Timer Counter 2 */
63 0, /* Timer Counter 3 */
64 0, /* Timer Counter 4 */
65 0, /* Timer Counter 5 */
66 3, /* USB Host port */
67 3, /* Ethernet MAC */
68 0, /* Advanced Interrupt Controller */
69 0, /* Advanced Interrupt Controller */
70 0, /* Advanced Interrupt Controller */
71 0, /* Advanced Interrupt Controller */
72 0, /* Advanced Interrupt Controller */
73 0, /* Advanced Interrupt Controller */
74 0 /* Advanced Interrupt Controller */
75};
76 39
77 40static void at91_aic_mask_irq(unsigned int irq)
78static void at91rm9200_mask_irq(unsigned int irq)
79{ 41{
80 /* Disable interrupt on AIC */ 42 /* Disable interrupt on AIC */
81 at91_sys_write(AT91_AIC_IDCR, 1 << irq); 43 at91_sys_write(AT91_AIC_IDCR, 1 << irq);
82} 44}
83 45
84static void at91rm9200_unmask_irq(unsigned int irq) 46static void at91_aic_unmask_irq(unsigned int irq)
85{ 47{
86 /* Enable interrupt on AIC */ 48 /* Enable interrupt on AIC */
87 at91_sys_write(AT91_AIC_IECR, 1 << irq); 49 at91_sys_write(AT91_AIC_IECR, 1 << irq);
88} 50}
89 51
90static int at91rm9200_irq_type(unsigned irq, unsigned type) 52static int at91_aic_set_type(unsigned irq, unsigned type)
91{ 53{
92 unsigned int smr, srctype; 54 unsigned int smr, srctype;
93 55
@@ -122,7 +84,7 @@ static int at91rm9200_irq_type(unsigned irq, unsigned type)
122static u32 wakeups; 84static u32 wakeups;
123static u32 backups; 85static u32 backups;
124 86
125static int at91rm9200_irq_set_wake(unsigned irq, unsigned value) 87static int at91_aic_set_wake(unsigned irq, unsigned value)
126{ 88{
127 if (unlikely(irq >= 32)) 89 if (unlikely(irq >= 32))
128 return -EINVAL; 90 return -EINVAL;
@@ -149,28 +111,24 @@ void at91_irq_resume(void)
149} 111}
150 112
151#else 113#else
152#define at91rm9200_irq_set_wake NULL 114#define at91_aic_set_wake NULL
153#endif 115#endif
154 116
155static struct irqchip at91rm9200_irq_chip = { 117static struct irqchip at91_aic_chip = {
156 .ack = at91rm9200_mask_irq, 118 .ack = at91_aic_mask_irq,
157 .mask = at91rm9200_mask_irq, 119 .mask = at91_aic_mask_irq,
158 .unmask = at91rm9200_unmask_irq, 120 .unmask = at91_aic_unmask_irq,
159 .set_type = at91rm9200_irq_type, 121 .set_type = at91_aic_set_type,
160 .set_wake = at91rm9200_irq_set_wake, 122 .set_wake = at91_aic_set_wake,
161}; 123};
162 124
163/* 125/*
164 * Initialize the AIC interrupt controller. 126 * Initialize the AIC interrupt controller.
165 */ 127 */
166void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS]) 128void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
167{ 129{
168 unsigned int i; 130 unsigned int i;
169 131
170 /* No priority list specified for this board -> use defaults */
171 if (priority == NULL)
172 priority = at91rm9200_default_irq_priority;
173
174 /* 132 /*
175 * The IVR is used by macro get_irqnr_and_base to read and verify. 133 * The IVR is used by macro get_irqnr_and_base to read and verify.
176 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. 134 * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
@@ -178,10 +136,10 @@ void __init at91rm9200_init_irq(unsigned int priority[NR_AIC_IRQS])
178 for (i = 0; i < NR_AIC_IRQS; i++) { 136 for (i = 0; i < NR_AIC_IRQS; i++) {
179 /* Put irq number in Source Vector Register: */ 137 /* Put irq number in Source Vector Register: */
180 at91_sys_write(AT91_AIC_SVR(i), i); 138 at91_sys_write(AT91_AIC_SVR(i), i);
181 /* Store the Source Mode Register as defined in table above */ 139 /* Active Low interrupt, with the specified priority */
182 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); 140 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
183 141
184 set_irq_chip(i, &at91rm9200_irq_chip); 142 set_irq_chip(i, &at91_aic_chip);
185 set_irq_handler(i, do_level_IRQ); 143 set_irq_handler(i, do_level_IRQ);
186 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 144 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
187 145
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index ba91daad64fb..3d73c1e93752 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -27,7 +27,6 @@
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28 28
29#include <asm/hardware.h> 29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h> 30#include <asm/io.h>
32#include <asm/setup.h> 31#include <asm/setup.h>
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
@@ -36,7 +35,6 @@
36#include <asm/system.h> 35#include <asm/system.h>
37 36
38#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
39#include <asm/mach/irq.h>
40#include <asm/mach/map.h> 38#include <asm/mach/map.h>
41#include <asm/mach/time.h> 39#include <asm/mach/time.h>
42 40
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
index 981aa9dcdede..ec01574f88ac 100644
--- a/arch/arm/mach-pnx4008/dma.c
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -23,7 +23,6 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24 24
25#include <asm/system.h> 25#include <asm/system.h>
26#include <asm/irq.h>
27#include <asm/hardware.h> 26#include <asm/hardware.h>
28#include <asm/dma.h> 27#include <asm/dma.h>
29#include <asm/dma-mapping.h> 28#include <asm/dma-mapping.h>
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index 9b0a8e084e99..3a4bcf3d91fa 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -22,8 +22,8 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/ioport.h> 23#include <linux/ioport.h>
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/irq.h>
25#include <asm/hardware.h> 26#include <asm/hardware.h>
26#include <asm/irq.h>
27#include <asm/io.h> 27#include <asm/io.h>
28#include <asm/setup.h> 28#include <asm/setup.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
@@ -96,26 +96,24 @@ void __init pnx4008_init_irq(void)
96{ 96{
97 unsigned int i; 97 unsigned int i;
98 98
99 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */ 99 /* configure IRQ's */
100 for (i = 0; i < NR_IRQS; i++) {
101 set_irq_flags(i, IRQF_VALID);
102 set_irq_chip(i, &pnx4008_irq_chip);
103 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
104 }
105
106 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
100 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]); 107 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
101 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]); 108 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
102 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]); 109 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
103 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]); 110 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
104 111
112 /* mask all others */
105 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) | 113 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
106 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N), 114 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
107 INTC_ER(MAIN_BASE_INT)); 115 INTC_ER(MAIN_BASE_INT));
108 __raw_writel(0, INTC_ER(SIC1_BASE_INT)); 116 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
109 __raw_writel(0, INTC_ER(SIC2_BASE_INT)); 117 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
110
111 /* configure all other IRQ's */
112 for (i = 0; i < NR_IRQS; i++) {
113 if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
114 i == SUB2_IRQ_N || i == SUB1_IRQ_N)
115 continue;
116 set_irq_flags(i, IRQF_VALID);
117 set_irq_chip(i, &pnx4008_irq_chip);
118 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
119 }
120} 118}
121 119
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
index 888bf6cfba8a..756228ddd035 100644
--- a/arch/arm/mach-pnx4008/time.c
+++ b/arch/arm/mach-pnx4008/time.c
@@ -20,17 +20,15 @@
20#include <linux/spinlock.h> 20#include <linux/spinlock.h>
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/kallsyms.h> 22#include <linux/kallsyms.h>
23#include <linux/time.h>
24#include <linux/timex.h>
25#include <linux/irq.h>
23 26
24#include <asm/system.h> 27#include <asm/system.h>
25#include <asm/hardware.h> 28#include <asm/hardware.h>
26#include <asm/io.h> 29#include <asm/io.h>
27#include <asm/leds.h> 30#include <asm/leds.h>
28#include <asm/irq.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/time.h> 31#include <asm/mach/time.h>
31
32#include <linux/time.h>
33#include <linux/timex.h>
34#include <asm/errno.h> 32#include <asm/errno.h>
35 33
36/*! Note: all timers are UPCOUNTING */ 34/*! Note: all timers are UPCOUNTING */