aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig4
-rw-r--r--arch/powerpc/boot/dts/fsl/t2081si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi4
-rw-r--r--arch/powerpc/boot/dts/t1040rdb.dts48
-rw-r--r--arch/powerpc/boot/dts/t1042rdb.dts48
-rw-r--r--arch/powerpc/boot/dts/t1042rdb_pi.dts57
-rw-r--r--arch/powerpc/boot/dts/t104xrdb.dtsi156
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig2
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig46
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig4
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig4
-rw-r--r--arch/powerpc/configs/mpc86xx_defconfig3
-rw-r--r--arch/powerpc/include/asm/pgtable.h3
-rw-r--r--arch/powerpc/include/asm/reg.h3
-rw-r--r--arch/powerpc/kernel/dma-swiotlb.c8
-rw-r--r--arch/powerpc/kernel/dma.c33
-rw-r--r--arch/powerpc/kernel/head_8xx.S150
-rw-r--r--arch/powerpc/mm/mem.c68
-rw-r--r--arch/powerpc/mm/numa.c8
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig2
-rw-r--r--arch/powerpc/platforms/85xx/corenet_generic.c14
-rw-r--r--arch/powerpc/platforms/85xx/qemu_e500.c10
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c95
-rw-r--r--arch/powerpc/sysdev/fsl_msi.h4
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c3
25 files changed, 580 insertions, 201 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 56da47247fcc..98ae8b714d31 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -288,6 +288,10 @@ config PPC_EMULATE_SSTEP
288 bool 288 bool
289 default y if KPROBES || UPROBES || XMON || HAVE_HW_BREAKPOINT 289 default y if KPROBES || UPROBES || XMON || HAVE_HW_BREAKPOINT
290 290
291config ZONE_DMA32
292 bool
293 default y if PPC64
294
291source "init/Kconfig" 295source "init/Kconfig"
292 296
293source "kernel/Kconfig.freezer" 297source "kernel/Kconfig.freezer"
diff --git a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
index 97479f0ce630..aecee9690a88 100644
--- a/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t2081si-post.dtsi
@@ -410,7 +410,7 @@
410/include/ "qoriq-gpio-3.dtsi" 410/include/ "qoriq-gpio-3.dtsi"
411/include/ "qoriq-usb2-mph-0.dtsi" 411/include/ "qoriq-usb2-mph-0.dtsi"
412 usb0: usb@210000 { 412 usb0: usb@210000 {
413 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; 413 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
414 fsl,iommu-parent = <&pamu1>; 414 fsl,iommu-parent = <&pamu1>;
415 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */ 415 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
416 phy_type = "utmi"; 416 phy_type = "utmi";
@@ -418,7 +418,7 @@
418 }; 418 };
419/include/ "qoriq-usb2-dr-0.dtsi" 419/include/ "qoriq-usb2-dr-0.dtsi"
420 usb1: usb@211000 { 420 usb1: usb@211000 {
421 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 421 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
422 fsl,iommu-parent = <&pamu1>; 422 fsl,iommu-parent = <&pamu1>;
423 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */ 423 fsl,liodn-reg = <&guts 0x524>; /* USB1LIODNR */
424 dr_mode = "host"; 424 dr_mode = "host";
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
index a3d582e0361a..7e2fc7cdce48 100644
--- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -498,13 +498,13 @@
498/include/ "qoriq-gpio-3.dtsi" 498/include/ "qoriq-gpio-3.dtsi"
499/include/ "qoriq-usb2-mph-0.dtsi" 499/include/ "qoriq-usb2-mph-0.dtsi"
500 usb0: usb@210000 { 500 usb0: usb@210000 {
501 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph"; 501 compatible = "fsl-usb2-mph-v2.5", "fsl-usb2-mph";
502 phy_type = "utmi"; 502 phy_type = "utmi";
503 port0; 503 port0;
504 }; 504 };
505/include/ "qoriq-usb2-dr-0.dtsi" 505/include/ "qoriq-usb2-dr-0.dtsi"
506 usb1: usb@211000 { 506 usb1: usb@211000 {
507 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr"; 507 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
508 dr_mode = "host"; 508 dr_mode = "host";
509 phy_type = "utmi"; 509 phy_type = "utmi";
510 }; 510 };
diff --git a/arch/powerpc/boot/dts/t1040rdb.dts b/arch/powerpc/boot/dts/t1040rdb.dts
new file mode 100644
index 000000000000..79a0bed04c1a
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1040rdb.dts
@@ -0,0 +1,48 @@
1/*
2 * T1040RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xrdb.dtsi"
37
38/ {
39 model = "fsl,T1040RDB";
40 compatible = "fsl,T1040RDB";
41 ifc: localbus@ffe124000 {
42 cpld@3,0 {
43 compatible = "fsl,t1040rdb-cpld";
44 };
45 };
46};
47
48/include/ "fsl/t1040si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1042rdb.dts b/arch/powerpc/boot/dts/t1042rdb.dts
new file mode 100644
index 000000000000..738c23790e94
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1042rdb.dts
@@ -0,0 +1,48 @@
1/*
2 * T1042RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xrdb.dtsi"
37
38/ {
39 model = "fsl,T1042RDB";
40 compatible = "fsl,T1042RDB";
41 ifc: localbus@ffe124000 {
42 cpld@3,0 {
43 compatible = "fsl,t1042rdb-cpld";
44 };
45 };
46};
47
48/include/ "fsl/t1042si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t1042rdb_pi.dts b/arch/powerpc/boot/dts/t1042rdb_pi.dts
new file mode 100644
index 000000000000..634f751fa6d3
--- /dev/null
+++ b/arch/powerpc/boot/dts/t1042rdb_pi.dts
@@ -0,0 +1,57 @@
1/*
2 * T1042RDB_PI Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t104xsi-pre.dtsi"
36/include/ "t104xrdb.dtsi"
37
38/ {
39 model = "fsl,T1042RDB_PI";
40 compatible = "fsl,T1042RDB_PI";
41 ifc: localbus@ffe124000 {
42 cpld@3,0 {
43 compatible = "fsl,t1042rdb_pi-cpld";
44 };
45 };
46 soc: soc@ffe000000 {
47 i2c@118000 {
48 rtc@68 {
49 compatible = "dallas,ds1337";
50 reg = <0x68>;
51 interrupts = <0x2 0x1 0 0>;
52 };
53 };
54 };
55};
56
57/include/ "fsl/t1042si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/t104xrdb.dtsi b/arch/powerpc/boot/dts/t104xrdb.dtsi
new file mode 100644
index 000000000000..1cf0f3c5f7e5
--- /dev/null
+++ b/arch/powerpc/boot/dts/t104xrdb.dtsi
@@ -0,0 +1,156 @@
1/*
2 * T1040RDB/T1042RDB Device Tree Source
3 *
4 * Copyright 2014 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36
37 ifc: localbus@ffe124000 {
38 reg = <0xf 0xfe124000 0 0x2000>;
39 ranges = <0 0 0xf 0xe8000000 0x08000000
40 2 0 0xf 0xff800000 0x00010000
41 3 0 0xf 0xffdf0000 0x00008000>;
42
43 nor@0,0 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "cfi-flash";
47 reg = <0x0 0x0 0x8000000>;
48 bank-width = <2>;
49 device-width = <1>;
50 };
51
52 nand@2,0 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "fsl,ifc-nand";
56 reg = <0x2 0x0 0x10000>;
57 };
58
59 cpld@3,0 {
60 reg = <3 0 0x300>;
61 };
62 };
63
64 memory {
65 device_type = "memory";
66 };
67
68 dcsr: dcsr@f00000000 {
69 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
70 };
71
72 soc: soc@ffe000000 {
73 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
74 reg = <0xf 0xfe000000 0 0x00001000>;
75
76 spi@110000 {
77 flash@0 {
78 #address-cells = <1>;
79 #size-cells = <1>;
80 compatible = "micron,n25q512a";
81 reg = <0>;
82 spi-max-frequency = <10000000>; /* input clock */
83 };
84 };
85
86 i2c@118100 {
87 pca9546@77 {
88 compatible = "nxp,pca9546";
89 reg = <0x77>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 };
93 };
94
95 };
96
97 pci0: pcie@ffe240000 {
98 reg = <0xf 0xfe240000 0 0x10000>;
99 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x10000000
100 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
101 pcie@0 {
102 ranges = <0x02000000 0 0xe0000000
103 0x02000000 0 0xe0000000
104 0 0x10000000
105
106 0x01000000 0 0x00000000
107 0x01000000 0 0x00000000
108 0 0x00010000>;
109 };
110 };
111
112 pci1: pcie@ffe250000 {
113 reg = <0xf 0xfe250000 0 0x10000>;
114 ranges = <0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000
115 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
116 pcie@0 {
117 ranges = <0x02000000 0 0xe0000000
118 0x02000000 0 0xe0000000
119 0 0x10000000
120
121 0x01000000 0 0x00000000
122 0x01000000 0 0x00000000
123 0 0x00010000>;
124 };
125 };
126
127 pci2: pcie@ffe260000 {
128 reg = <0xf 0xfe260000 0 0x10000>;
129 ranges = <0x02000000 0 0xe0000000 0xc 0x20000000 0 0x10000000
130 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
131 pcie@0 {
132 ranges = <0x02000000 0 0xe0000000
133 0x02000000 0 0xe0000000
134 0 0x10000000
135
136 0x01000000 0 0x00000000
137 0x01000000 0 0x00000000
138 0 0x00010000>;
139 };
140 };
141
142 pci3: pcie@ffe270000 {
143 reg = <0xf 0xfe270000 0 0x10000>;
144 ranges = <0x02000000 0 0xe0000000 0xc 0x30000000 0 0x10000000
145 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
146 pcie@0 {
147 ranges = <0x02000000 0 0xe0000000
148 0x02000000 0 0xe0000000
149 0 0x10000000
150
151 0x01000000 0 0x00000000
152 0x01000000 0 0x00000000
153 0 0x00010000>;
154 };
155 };
156};
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 6a3c58adf253..688e9e4d29a1 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -165,6 +165,8 @@ CONFIG_NFS_FS=y
165CONFIG_NFS_V4=y 165CONFIG_NFS_V4=y
166CONFIG_ROOT_NFS=y 166CONFIG_ROOT_NFS=y
167CONFIG_NFSD=m 167CONFIG_NFSD=m
168CONFIG_NLS_CODEPAGE_437=y
169CONFIG_NLS_CODEPAGE_850=y
168CONFIG_NLS_ISO8859_1=y 170CONFIG_NLS_ISO8859_1=y
169CONFIG_NLS_UTF8=m 171CONFIG_NLS_UTF8=m
170CONFIG_MAGIC_SYSRQ=y 172CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 269d6e47c67d..6db97e4414b2 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -50,7 +50,6 @@ CONFIG_NET_IPIP=y
50CONFIG_IP_MROUTE=y 50CONFIG_IP_MROUTE=y
51CONFIG_IP_PIMSM_V1=y 51CONFIG_IP_PIMSM_V1=y
52CONFIG_IP_PIMSM_V2=y 52CONFIG_IP_PIMSM_V2=y
53CONFIG_ARPD=y
54CONFIG_INET_ESP=y 53CONFIG_INET_ESP=y
55# CONFIG_INET_XFRM_MODE_BEET is not set 54# CONFIG_INET_XFRM_MODE_BEET is not set
56# CONFIG_INET_LRO is not set 55# CONFIG_INET_LRO is not set
@@ -60,33 +59,17 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
60CONFIG_DEVTMPFS=y 59CONFIG_DEVTMPFS=y
61CONFIG_DEVTMPFS_MOUNT=y 60CONFIG_DEVTMPFS_MOUNT=y
62CONFIG_MTD=y 61CONFIG_MTD=y
63CONFIG_MTD_OF_PARTS=y
64CONFIG_MTD_CMDLINE_PARTS=y 62CONFIG_MTD_CMDLINE_PARTS=y
65CONFIG_MTD_CHAR=y
66CONFIG_MTD_BLKDEVS=y
67CONFIG_MTD_BLOCK=y 63CONFIG_MTD_BLOCK=y
68CONFIG_FTL=y 64CONFIG_FTL=y
69CONFIG_MTD_CFI=y 65CONFIG_MTD_CFI=y
70CONFIG_MTD_GEN_PROBE=y
71CONFIG_MTD_MAP_BANK_WIDTH_1=y
72CONFIG_MTD_MAP_BANK_WIDTH_2=y
73CONFIG_MTD_MAP_BANK_WIDTH_4=y
74CONFIG_MTD_CFI_I1=y
75CONFIG_MTD_CFI_I2=y
76CONFIG_MTD_CFI_INTELEXT=y 66CONFIG_MTD_CFI_INTELEXT=y
77CONFIG_MTD_CFI_AMDSTD=y 67CONFIG_MTD_CFI_AMDSTD=y
78CONFIG_MTD_PHYSMAP_OF=y 68CONFIG_MTD_PHYSMAP_OF=y
79CONFIG_MTD_M25P80=y
80CONFIG_MTD_CFI_UTIL=y
81CONFIG_MTD_NAND_ECC=y
82CONFIG_MTD_NAND=y 69CONFIG_MTD_NAND=y
83CONFIG_MTD_NAND_IDS=y
84CONFIG_MTD_NAND_FSL_ELBC=y 70CONFIG_MTD_NAND_FSL_ELBC=y
85CONFIG_MTD_NAND_FSL_IFC=y 71CONFIG_MTD_NAND_FSL_IFC=y
86CONFIG_MTD_UBI=y 72CONFIG_MTD_UBI=y
87CONFIG_MTD_UBI_WL_THRESHOLD=4096
88CONFIG_MTD_UBI_BEB_RESERVE=1
89CONFIG_PROC_DEVICETREE=y
90CONFIG_BLK_DEV_LOOP=y 73CONFIG_BLK_DEV_LOOP=y
91CONFIG_BLK_DEV_RAM=y 74CONFIG_BLK_DEV_RAM=y
92CONFIG_BLK_DEV_RAM_SIZE=131072 75CONFIG_BLK_DEV_RAM_SIZE=131072
@@ -102,6 +85,7 @@ CONFIG_INPUT_FF_MEMLESS=m
102# CONFIG_INPUT_KEYBOARD is not set 85# CONFIG_INPUT_KEYBOARD is not set
103# CONFIG_INPUT_MOUSE is not set 86# CONFIG_INPUT_MOUSE is not set
104CONFIG_SERIO_LIBPS2=y 87CONFIG_SERIO_LIBPS2=y
88CONFIG_PPC_EPAPR_HV_BYTECHAN=y
105CONFIG_SERIAL_8250=y 89CONFIG_SERIAL_8250=y
106CONFIG_SERIAL_8250_CONSOLE=y 90CONFIG_SERIAL_8250_CONSOLE=y
107CONFIG_SERIAL_8250_MANY_PORTS=y 91CONFIG_SERIAL_8250_MANY_PORTS=y
@@ -115,7 +99,6 @@ CONFIG_SPI_GPIO=y
115CONFIG_SPI_FSL_SPI=y 99CONFIG_SPI_FSL_SPI=y
116CONFIG_SPI_FSL_ESPI=y 100CONFIG_SPI_FSL_ESPI=y
117# CONFIG_HWMON is not set 101# CONFIG_HWMON is not set
118CONFIG_VIDEO_OUTPUT_CONTROL=y
119CONFIG_USB_HID=m 102CONFIG_USB_HID=m
120CONFIG_USB=y 103CONFIG_USB=y
121CONFIG_USB_MON=y 104CONFIG_USB_MON=y
@@ -124,14 +107,17 @@ CONFIG_USB_EHCI_FSL=y
124CONFIG_USB_STORAGE=y 107CONFIG_USB_STORAGE=y
125CONFIG_MMC=y 108CONFIG_MMC=y
126CONFIG_MMC_SDHCI=y 109CONFIG_MMC_SDHCI=y
110CONFIG_EDAC=y
111CONFIG_EDAC_MM_EDAC=y
127CONFIG_RTC_CLASS=y 112CONFIG_RTC_CLASS=y
128CONFIG_RTC_DRV_DS1307=y 113CONFIG_RTC_DRV_DS1307=y
129CONFIG_RTC_DRV_DS1374=y 114CONFIG_RTC_DRV_DS1374=y
130CONFIG_RTC_DRV_DS3232=y 115CONFIG_RTC_DRV_DS3232=y
131CONFIG_EDAC=y
132CONFIG_EDAC_MM_EDAC=y
133CONFIG_DMADEVICES=y 116CONFIG_DMADEVICES=y
134CONFIG_FSL_DMA=y 117CONFIG_FSL_DMA=y
118CONFIG_VIRT_DRIVERS=y
119CONFIG_FSL_HV_MANAGER=y
120CONFIG_FSL_CORENET_CF=y
135CONFIG_EXT2_FS=y 121CONFIG_EXT2_FS=y
136CONFIG_EXT3_FS=y 122CONFIG_EXT3_FS=y
137CONFIG_ISO9660_FS=m 123CONFIG_ISO9660_FS=m
@@ -144,35 +130,24 @@ CONFIG_NTFS_FS=y
144CONFIG_PROC_KCORE=y 130CONFIG_PROC_KCORE=y
145CONFIG_TMPFS=y 131CONFIG_TMPFS=y
146CONFIG_HUGETLBFS=y 132CONFIG_HUGETLBFS=y
147CONFIG_MISC_FILESYSTEMS=y
148CONFIG_JFFS2_FS=y 133CONFIG_JFFS2_FS=y
149CONFIG_JFFS2_FS_DEBUG=1 134CONFIG_JFFS2_FS_DEBUG=1
150CONFIG_JFFS2_FS_WRITEBUFFER=y
151CONFIG_JFFS2_ZLIB=y
152CONFIG_JFFS2_RTIME=y
153CONFIG_UBIFS_FS=y 135CONFIG_UBIFS_FS=y
154CONFIG_UBIFS_FS_XATTR=y
155CONFIG_UBIFS_FS_LZO=y
156CONFIG_UBIFS_FS_ZLIB=y
157CONFIG_NFS_FS=y 136CONFIG_NFS_FS=y
158CONFIG_NFS_V4=y 137CONFIG_NFS_V4=y
159CONFIG_ROOT_NFS=y 138CONFIG_ROOT_NFS=y
160CONFIG_NFSD=m 139CONFIG_NFSD=m
140CONFIG_NLS_CODEPAGE_437=y
141CONFIG_NLS_CODEPAGE_850=y
161CONFIG_NLS_ISO8859_1=y 142CONFIG_NLS_ISO8859_1=y
162CONFIG_NLS_UTF8=m 143CONFIG_NLS_UTF8=m
163CONFIG_CRC_T10DIF=y 144CONFIG_CRC_T10DIF=y
164CONFIG_CRC16=y 145CONFIG_DEBUG_INFO=y
165CONFIG_ZLIB_DEFLATE=y
166CONFIG_LZO_COMPRESS=y
167CONFIG_LZO_DECOMPRESS=y
168CONFIG_CRYPTO_DEFLATE=y
169CONFIG_CRYPTO_LZO=y
170CONFIG_FRAME_WARN=1024 146CONFIG_FRAME_WARN=1024
171CONFIG_MAGIC_SYSRQ=y
172CONFIG_DEBUG_FS=y 147CONFIG_DEBUG_FS=y
148CONFIG_MAGIC_SYSRQ=y
173CONFIG_DEBUG_SHIRQ=y 149CONFIG_DEBUG_SHIRQ=y
174CONFIG_DETECT_HUNG_TASK=y 150CONFIG_DETECT_HUNG_TASK=y
175CONFIG_DEBUG_INFO=y
176CONFIG_CRYPTO_NULL=y 151CONFIG_CRYPTO_NULL=y
177CONFIG_CRYPTO_PCBC=m 152CONFIG_CRYPTO_PCBC=m
178CONFIG_CRYPTO_MD4=y 153CONFIG_CRYPTO_MD4=y
@@ -180,4 +155,3 @@ CONFIG_CRYPTO_SHA256=y
180CONFIG_CRYPTO_SHA512=y 155CONFIG_CRYPTO_SHA512=y
181# CONFIG_CRYPTO_ANSI_CPRNG is not set 156# CONFIG_CRYPTO_ANSI_CPRNG is not set
182CONFIG_CRYPTO_DEV_FSL_CAAM=y 157CONFIG_CRYPTO_DEV_FSL_CAAM=y
183CONFIG_FSL_CORENET_CF=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index fa1bfd37f1ec..d2c415489f72 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -213,7 +213,6 @@ CONFIG_RTC_DRV_DS1307=y
213CONFIG_RTC_DRV_DS1374=y 213CONFIG_RTC_DRV_DS1374=y
214CONFIG_RTC_DRV_DS3232=y 214CONFIG_RTC_DRV_DS3232=y
215CONFIG_RTC_DRV_CMOS=y 215CONFIG_RTC_DRV_CMOS=y
216CONFIG_RTC_DRV_DS1307=y
217CONFIG_DMADEVICES=y 216CONFIG_DMADEVICES=y
218CONFIG_FSL_DMA=y 217CONFIG_FSL_DMA=y
219# CONFIG_NET_DMA is not set 218# CONFIG_NET_DMA is not set
@@ -227,6 +226,9 @@ CONFIG_UDF_FS=m
227CONFIG_MSDOS_FS=m 226CONFIG_MSDOS_FS=m
228CONFIG_VFAT_FS=y 227CONFIG_VFAT_FS=y
229CONFIG_NTFS_FS=y 228CONFIG_NTFS_FS=y
229CONFIG_NLS_CODEPAGE_437=y
230CONFIG_NLS_CODEPAGE_850=y
231CONFIG_NLS_ISO8859_1=y
230CONFIG_PROC_KCORE=y 232CONFIG_PROC_KCORE=y
231CONFIG_TMPFS=y 233CONFIG_TMPFS=y
232CONFIG_HUGETLBFS=y 234CONFIG_HUGETLBFS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 0b452ebd8b3d..87460083dbc7 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -214,7 +214,6 @@ CONFIG_RTC_DRV_DS1307=y
214CONFIG_RTC_DRV_DS1374=y 214CONFIG_RTC_DRV_DS1374=y
215CONFIG_RTC_DRV_DS3232=y 215CONFIG_RTC_DRV_DS3232=y
216CONFIG_RTC_DRV_CMOS=y 216CONFIG_RTC_DRV_CMOS=y
217CONFIG_RTC_DRV_DS1307=y
218CONFIG_DMADEVICES=y 217CONFIG_DMADEVICES=y
219CONFIG_FSL_DMA=y 218CONFIG_FSL_DMA=y
220# CONFIG_NET_DMA is not set 219# CONFIG_NET_DMA is not set
@@ -228,6 +227,9 @@ CONFIG_UDF_FS=m
228CONFIG_MSDOS_FS=m 227CONFIG_MSDOS_FS=m
229CONFIG_VFAT_FS=y 228CONFIG_VFAT_FS=y
230CONFIG_NTFS_FS=y 229CONFIG_NTFS_FS=y
230CONFIG_NLS_CODEPAGE_437=y
231CONFIG_NLS_CODEPAGE_850=y
232CONFIG_NLS_ISO8859_1=y
231CONFIG_PROC_KCORE=y 233CONFIG_PROC_KCORE=y
232CONFIG_TMPFS=y 234CONFIG_TMPFS=y
233CONFIG_HUGETLBFS=y 235CONFIG_HUGETLBFS=y
diff --git a/arch/powerpc/configs/mpc86xx_defconfig b/arch/powerpc/configs/mpc86xx_defconfig
index 35595ea74ff4..fc58aa8a89e4 100644
--- a/arch/powerpc/configs/mpc86xx_defconfig
+++ b/arch/powerpc/configs/mpc86xx_defconfig
@@ -145,6 +145,9 @@ CONFIG_UDF_FS=m
145CONFIG_MSDOS_FS=m 145CONFIG_MSDOS_FS=m
146CONFIG_VFAT_FS=y 146CONFIG_VFAT_FS=y
147CONFIG_NTFS_FS=y 147CONFIG_NTFS_FS=y
148CONFIG_NLS_CODEPAGE_437=y
149CONFIG_NLS_CODEPAGE_850=y
150CONFIG_NLS_ISO8859_1=y
148CONFIG_PROC_KCORE=y 151CONFIG_PROC_KCORE=y
149CONFIG_TMPFS=y 152CONFIG_TMPFS=y
150CONFIG_ADFS_FS=m 153CONFIG_ADFS_FS=m
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index d98c1ecc3266..6d74167bb6bf 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -4,6 +4,7 @@
4 4
5#ifndef __ASSEMBLY__ 5#ifndef __ASSEMBLY__
6#include <linux/mmdebug.h> 6#include <linux/mmdebug.h>
7#include <linux/mmzone.h>
7#include <asm/processor.h> /* For TASK_SIZE */ 8#include <asm/processor.h> /* For TASK_SIZE */
8#include <asm/mmu.h> 9#include <asm/mmu.h>
9#include <asm/page.h> 10#include <asm/page.h>
@@ -281,6 +282,8 @@ extern unsigned long empty_zero_page[];
281 282
282extern pgd_t swapper_pg_dir[]; 283extern pgd_t swapper_pg_dir[];
283 284
285void limit_zone_pfn(enum zone_type zone, unsigned long max_pfn);
286int dma_pfn_limit_to_zone(u64 pfn_limit);
284extern void paging_init(void); 287extern void paging_init(void);
285 288
286/* 289/*
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 0c0505956a29..fe3f9488f321 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -947,7 +947,7 @@
947 * 32-bit 8xx: 947 * 32-bit 8xx:
948 * - SPRG0 scratch for exception vectors 948 * - SPRG0 scratch for exception vectors
949 * - SPRG1 scratch for exception vectors 949 * - SPRG1 scratch for exception vectors
950 * - SPRG2 apparently unused but initialized 950 * - SPRG2 scratch for exception vectors
951 * 951 *
952 */ 952 */
953#ifdef CONFIG_PPC64 953#ifdef CONFIG_PPC64
@@ -1057,6 +1057,7 @@
1057#ifdef CONFIG_8xx 1057#ifdef CONFIG_8xx
1058#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 1058#define SPRN_SPRG_SCRATCH0 SPRN_SPRG0
1059#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 1059#define SPRN_SPRG_SCRATCH1 SPRN_SPRG1
1060#define SPRN_SPRG_SCRATCH2 SPRN_SPRG2
1060#endif 1061#endif
1061 1062
1062 1063
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index bd1a2aba599f..735979764cd4 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -106,10 +106,14 @@ int __init swiotlb_setup_bus_notifier(void)
106 return 0; 106 return 0;
107} 107}
108 108
109void swiotlb_detect_4g(void) 109void __init swiotlb_detect_4g(void)
110{ 110{
111 if ((memblock_end_of_DRAM() - 1) > 0xffffffff) 111 if ((memblock_end_of_DRAM() - 1) > 0xffffffff) {
112 ppc_swiotlb_enable = 1; 112 ppc_swiotlb_enable = 1;
113#ifdef CONFIG_ZONE_DMA32
114 limit_zone_pfn(ZONE_DMA32, (1ULL << 32) >> PAGE_SHIFT);
115#endif
116 }
113} 117}
114 118
115static int __init swiotlb_late_init(void) 119static int __init swiotlb_late_init(void)
diff --git a/arch/powerpc/kernel/dma.c b/arch/powerpc/kernel/dma.c
index 210ff9d3c182..adac9dc54aee 100644
--- a/arch/powerpc/kernel/dma.c
+++ b/arch/powerpc/kernel/dma.c
@@ -15,6 +15,7 @@
15#include <asm/vio.h> 15#include <asm/vio.h>
16#include <asm/bug.h> 16#include <asm/bug.h>
17#include <asm/machdep.h> 17#include <asm/machdep.h>
18#include <asm/swiotlb.h>
18 19
19/* 20/*
20 * Generic direct DMA implementation 21 * Generic direct DMA implementation
@@ -25,6 +26,18 @@
25 * default the offset is PCI_DRAM_OFFSET. 26 * default the offset is PCI_DRAM_OFFSET.
26 */ 27 */
27 28
29static u64 __maybe_unused get_pfn_limit(struct device *dev)
30{
31 u64 pfn = (dev->coherent_dma_mask >> PAGE_SHIFT) + 1;
32 struct dev_archdata __maybe_unused *sd = &dev->archdata;
33
34#ifdef CONFIG_SWIOTLB
35 if (sd->max_direct_dma_addr && sd->dma_ops == &swiotlb_dma_ops)
36 pfn = min_t(u64, pfn, sd->max_direct_dma_addr >> PAGE_SHIFT);
37#endif
38
39 return pfn;
40}
28 41
29void *dma_direct_alloc_coherent(struct device *dev, size_t size, 42void *dma_direct_alloc_coherent(struct device *dev, size_t size,
30 dma_addr_t *dma_handle, gfp_t flag, 43 dma_addr_t *dma_handle, gfp_t flag,
@@ -40,6 +53,26 @@ void *dma_direct_alloc_coherent(struct device *dev, size_t size,
40#else 53#else
41 struct page *page; 54 struct page *page;
42 int node = dev_to_node(dev); 55 int node = dev_to_node(dev);
56 u64 pfn = get_pfn_limit(dev);
57 int zone;
58
59 zone = dma_pfn_limit_to_zone(pfn);
60 if (zone < 0) {
61 dev_err(dev, "%s: No suitable zone for pfn %#llx\n",
62 __func__, pfn);
63 return NULL;
64 }
65
66 switch (zone) {
67 case ZONE_DMA:
68 flag |= GFP_DMA;
69 break;
70#ifdef CONFIG_ZONE_DMA32
71 case ZONE_DMA32:
72 flag |= GFP_DMA32;
73 break;
74#endif
75 };
43 76
44 /* ignore region specifiers */ 77 /* ignore region specifiers */
45 flag &= ~(__GFP_HIGHMEM); 78 flag &= ~(__GFP_HIGHMEM);
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 7ee876d2adb5..fafff8dbd5d9 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -104,12 +104,15 @@ turn_on_mmu:
104 * task's thread_struct. 104 * task's thread_struct.
105 */ 105 */
106#define EXCEPTION_PROLOG \ 106#define EXCEPTION_PROLOG \
107 mtspr SPRN_SPRG_SCRATCH0,r10; \ 107 EXCEPTION_PROLOG_0; \
108 mtspr SPRN_SPRG_SCRATCH1,r11; \
109 mfcr r10; \
110 EXCEPTION_PROLOG_1; \ 108 EXCEPTION_PROLOG_1; \
111 EXCEPTION_PROLOG_2 109 EXCEPTION_PROLOG_2
112 110
111#define EXCEPTION_PROLOG_0 \
112 mtspr SPRN_SPRG_SCRATCH0,r10; \
113 mtspr SPRN_SPRG_SCRATCH1,r11; \
114 mfcr r10
115
113#define EXCEPTION_PROLOG_1 \ 116#define EXCEPTION_PROLOG_1 \
114 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \ 117 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
115 andi. r11,r11,MSR_PR; \ 118 andi. r11,r11,MSR_PR; \
@@ -145,6 +148,14 @@ turn_on_mmu:
145 SAVE_2GPRS(7, r11) 148 SAVE_2GPRS(7, r11)
146 149
147/* 150/*
151 * Exception exit code.
152 */
153#define EXCEPTION_EPILOG_0 \
154 mtcr r10; \
155 mfspr r10,SPRN_SPRG_SCRATCH0; \
156 mfspr r11,SPRN_SPRG_SCRATCH1
157
158/*
148 * Note: code which follows this uses cr0.eq (set if from kernel), 159 * Note: code which follows this uses cr0.eq (set if from kernel),
149 * r11, r12 (SRR0), and r9 (SRR1). 160 * r11, r12 (SRR0), and r9 (SRR1).
150 * 161 *
@@ -293,16 +304,8 @@ InstructionTLBMiss:
293#ifdef CONFIG_8xx_CPU6 304#ifdef CONFIG_8xx_CPU6
294 stw r3, 8(r0) 305 stw r3, 8(r0)
295#endif 306#endif
296 DO_8xx_CPU6(0x3f80, r3) 307 EXCEPTION_PROLOG_0
297 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 308 mtspr SPRN_SPRG_SCRATCH2, r10
298 mfcr r10
299#ifdef CONFIG_8xx_CPU6
300 stw r10, 0(r0)
301 stw r11, 4(r0)
302#else
303 mtspr SPRN_DAR, r10
304 mtspr SPRN_SPRG2, r11
305#endif
306 mfspr r10, SPRN_SRR0 /* Get effective address of fault */ 309 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
307#ifdef CONFIG_8xx_CPU15 310#ifdef CONFIG_8xx_CPU15
308 addi r11, r10, 0x1000 311 addi r11, r10, 0x1000
@@ -359,18 +362,11 @@ InstructionTLBMiss:
359 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */ 362 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
360 363
361 /* Restore registers */ 364 /* Restore registers */
362#ifndef CONFIG_8xx_CPU6 365#ifdef CONFIG_8xx_CPU6
363 mfspr r10, SPRN_DAR
364 mtcr r10
365 mtspr SPRN_DAR, r11 /* Tag DAR */
366 mfspr r11, SPRN_SPRG2
367#else
368 lwz r11, 0(r0)
369 mtcr r11
370 lwz r11, 4(r0)
371 lwz r3, 8(r0) 366 lwz r3, 8(r0)
372#endif 367#endif
373 mfspr r10, SPRN_M_TW 368 mfspr r10, SPRN_SPRG_SCRATCH2
369 EXCEPTION_EPILOG_0
374 rfi 370 rfi
3752: 3712:
376 mfspr r11, SPRN_SRR1 372 mfspr r11, SPRN_SRR1
@@ -381,19 +377,11 @@ InstructionTLBMiss:
381 mtspr SPRN_SRR1, r11 377 mtspr SPRN_SRR1, r11
382 378
383 /* Restore registers */ 379 /* Restore registers */
384#ifndef CONFIG_8xx_CPU6 380#ifdef CONFIG_8xx_CPU6
385 mfspr r10, SPRN_DAR
386 mtcr r10
387 li r11, 0x00f0
388 mtspr SPRN_DAR, r11 /* Tag DAR */
389 mfspr r11, SPRN_SPRG2
390#else
391 lwz r11, 0(r0)
392 mtcr r11
393 lwz r11, 4(r0)
394 lwz r3, 8(r0) 381 lwz r3, 8(r0)
395#endif 382#endif
396 mfspr r10, SPRN_M_TW 383 mfspr r10, SPRN_SPRG_SCRATCH2
384 EXCEPTION_EPILOG_0
397 b InstructionAccess 385 b InstructionAccess
398 386
399 . = 0x1200 387 . = 0x1200
@@ -401,16 +389,8 @@ DataStoreTLBMiss:
401#ifdef CONFIG_8xx_CPU6 389#ifdef CONFIG_8xx_CPU6
402 stw r3, 8(r0) 390 stw r3, 8(r0)
403#endif 391#endif
404 DO_8xx_CPU6(0x3f80, r3) 392 EXCEPTION_PROLOG_0
405 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */ 393 mtspr SPRN_SPRG_SCRATCH2, r10
406 mfcr r10
407#ifdef CONFIG_8xx_CPU6
408 stw r10, 0(r0)
409 stw r11, 4(r0)
410#else
411 mtspr SPRN_DAR, r10
412 mtspr SPRN_SPRG2, r11
413#endif
414 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ 394 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
415 395
416 /* If we are faulting a kernel address, we have to use the 396 /* If we are faulting a kernel address, we have to use the
@@ -483,19 +463,12 @@ DataStoreTLBMiss:
483 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */ 463 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
484 464
485 /* Restore registers */ 465 /* Restore registers */
486#ifndef CONFIG_8xx_CPU6 466#ifdef CONFIG_8xx_CPU6
487 mfspr r10, SPRN_DAR
488 mtcr r10
489 mtspr SPRN_DAR, r11 /* Tag DAR */
490 mfspr r11, SPRN_SPRG2
491#else
492 mtspr SPRN_DAR, r11 /* Tag DAR */
493 lwz r11, 0(r0)
494 mtcr r11
495 lwz r11, 4(r0)
496 lwz r3, 8(r0) 467 lwz r3, 8(r0)
497#endif 468#endif
498 mfspr r10, SPRN_M_TW 469 mtspr SPRN_DAR, r11 /* Tag DAR */
470 mfspr r10, SPRN_SPRG_SCRATCH2
471 EXCEPTION_EPILOG_0
499 rfi 472 rfi
500 473
501/* This is an instruction TLB error on the MPC8xx. This could be due 474/* This is an instruction TLB error on the MPC8xx. This could be due
@@ -507,35 +480,18 @@ InstructionTLBError:
507 b InstructionAccess 480 b InstructionAccess
508 481
509/* This is the data TLB error on the MPC8xx. This could be due to 482/* This is the data TLB error on the MPC8xx. This could be due to
510 * many reasons, including a dirty update to a pte. We can catch that 483 * many reasons, including a dirty update to a pte. We bail out to
511 * one here, but anything else is an error. First, we track down the 484 * a higher level function that can handle it.
512 * Linux pte. If it is valid, write access is allowed, but the
513 * page dirty bit is not set, we will set it and reload the TLB. For
514 * any other case, we bail out to a higher level function that can
515 * handle it.
516 */ 485 */
517 . = 0x1400 486 . = 0x1400
518DataTLBError: 487DataTLBError:
519#ifdef CONFIG_8xx_CPU6 488 EXCEPTION_PROLOG_0
520 stw r3, 8(r0)
521#endif
522 DO_8xx_CPU6(0x3f80, r3)
523 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
524 mfcr r10
525 stw r10, 0(r0)
526 stw r11, 4(r0)
527 489
528 mfspr r10, SPRN_DAR 490 mfspr r11, SPRN_DAR
529 cmpwi cr0, r10, 0x00f0 491 cmpwi cr0, r11, 0x00f0
530 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */ 492 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
531DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */ 493DARFixed:/* Return from dcbx instruction bug workaround */
532 mfspr r10, SPRN_M_TW /* Restore registers */ 494 EXCEPTION_EPILOG_0
533 lwz r11, 0(r0)
534 mtcr r11
535 lwz r11, 4(r0)
536#ifdef CONFIG_8xx_CPU6
537 lwz r3, 8(r0)
538#endif
539 b DataAccess 495 b DataAccess
540 496
541 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE) 497 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
@@ -559,11 +515,15 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
559 515
560/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions 516/* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
561 * by decoding the registers used by the dcbx instruction and adding them. 517 * by decoding the registers used by the dcbx instruction and adding them.
562 * DAR is set to the calculated address and r10 also holds the EA on exit. 518 * DAR is set to the calculated address.
563 */ 519 */
564 /* define if you don't want to use self modifying code */ 520 /* define if you don't want to use self modifying code */
565#define NO_SELF_MODIFYING_CODE 521#define NO_SELF_MODIFYING_CODE
566FixupDAR:/* Entry point for dcbx workaround. */ 522FixupDAR:/* Entry point for dcbx workaround. */
523#ifdef CONFIG_8xx_CPU6
524 stw r3, 8(r0)
525#endif
526 mtspr SPRN_SPRG_SCRATCH2, r10
567 /* fetch instruction from memory. */ 527 /* fetch instruction from memory. */
568 mfspr r10, SPRN_SRR0 528 mfspr r10, SPRN_SRR0
569 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */ 529 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
@@ -579,16 +539,17 @@ FixupDAR:/* Entry point for dcbx workaround. */
579 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */ 539 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
580 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */ 540 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
581 lwz r11, 0(r11) /* Get the pte */ 541 lwz r11, 0(r11) /* Get the pte */
542#ifdef CONFIG_8xx_CPU6
543 lwz r3, 8(r0) /* restore r3 from memory */
544#endif
582 /* concat physical page address(r11) and page offset(r10) */ 545 /* concat physical page address(r11) and page offset(r10) */
583 rlwimi r11, r10, 0, 20, 31 546 rlwimi r11, r10, 0, 20, 31
584 lwz r11,0(r11) 547 lwz r11,0(r11)
585/* Check if it really is a dcbx instruction. */ 548/* Check if it really is a dcbx instruction. */
586/* dcbt and dcbtst does not generate DTLB Misses/Errors, 549/* dcbt and dcbtst does not generate DTLB Misses/Errors,
587 * no need to include them here */ 550 * no need to include them here */
588 srwi r10, r11, 26 /* check if major OP code is 31 */ 551 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
589 cmpwi cr0, r10, 31 552 rlwinm r10, r10, 0, 21, 5
590 bne- 141f
591 rlwinm r10, r11, 0, 21, 30
592 cmpwi cr0, r10, 2028 /* Is dcbz? */ 553 cmpwi cr0, r10, 2028 /* Is dcbz? */
593 beq+ 142f 554 beq+ 142f
594 cmpwi cr0, r10, 940 /* Is dcbi? */ 555 cmpwi cr0, r10, 940 /* Is dcbi? */
@@ -599,16 +560,13 @@ FixupDAR:/* Entry point for dcbx workaround. */
599 beq+ 142f 560 beq+ 142f
600 cmpwi cr0, r10, 1964 /* Is icbi? */ 561 cmpwi cr0, r10, 1964 /* Is icbi? */
601 beq+ 142f 562 beq+ 142f
602141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */ 563141: mfspr r10,SPRN_SPRG_SCRATCH2
603 b DARFixed /* Nope, go back to normal TLB processing */ 564 b DARFixed /* Nope, go back to normal TLB processing */
604 565
605144: mfspr r10, SPRN_DSISR 566144: mfspr r10, SPRN_DSISR
606 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */ 567 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
607 mtspr SPRN_DSISR, r10 568 mtspr SPRN_DSISR, r10
608142: /* continue, it was a dcbx, dcbi instruction. */ 569142: /* continue, it was a dcbx, dcbi instruction. */
609#ifdef CONFIG_8xx_CPU6
610 lwz r3, 8(r0) /* restore r3 from memory */
611#endif
612#ifndef NO_SELF_MODIFYING_CODE 570#ifndef NO_SELF_MODIFYING_CODE
613 andis. r10,r11,0x1f /* test if reg RA is r0 */ 571 andis. r10,r11,0x1f /* test if reg RA is r0 */
614 li r10,modified_instr@l 572 li r10,modified_instr@l
@@ -619,14 +577,15 @@ FixupDAR:/* Entry point for dcbx workaround. */
619 stw r11,0(r10) /* store add/and instruction */ 577 stw r11,0(r10) /* store add/and instruction */
620 dcbf 0,r10 /* flush new instr. to memory. */ 578 dcbf 0,r10 /* flush new instr. to memory. */
621 icbi 0,r10 /* invalidate instr. cache line */ 579 icbi 0,r10 /* invalidate instr. cache line */
622 lwz r11, 4(r0) /* restore r11 from memory */ 580 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
623 mfspr r10, SPRN_M_TW /* restore r10 from M_TW */ 581 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
624 isync /* Wait until new instr is loaded from memory */ 582 isync /* Wait until new instr is loaded from memory */
625modified_instr: 583modified_instr:
626 .space 4 /* this is where the add instr. is stored */ 584 .space 4 /* this is where the add instr. is stored */
627 bne+ 143f 585 bne+ 143f
628 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */ 586 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
629143: mtdar r10 /* store faulting EA in DAR */ 587143: mtdar r10 /* store faulting EA in DAR */
588 mfspr r10,SPRN_SPRG_SCRATCH2
630 b DARFixed /* Go back to normal TLB handling */ 589 b DARFixed /* Go back to normal TLB handling */
631#else 590#else
632 mfctr r10 591 mfctr r10
@@ -680,13 +639,16 @@ modified_instr:
680 mfdar r11 639 mfdar r11
681 mtctr r11 /* restore ctr reg from DAR */ 640 mtctr r11 /* restore ctr reg from DAR */
682 mtdar r10 /* save fault EA to DAR */ 641 mtdar r10 /* save fault EA to DAR */
642 mfspr r10,SPRN_SPRG_SCRATCH2
683 b DARFixed /* Go back to normal TLB handling */ 643 b DARFixed /* Go back to normal TLB handling */
684 644
685 /* special handling for r10,r11 since these are modified already */ 645 /* special handling for r10,r11 since these are modified already */
686153: lwz r11, 4(r0) /* load r11 from memory */ 646153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
687 b 155f 647 add r10, r10, r11 /* add it */
688154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */ 648 mfctr r11 /* restore r11 */
689155: add r10, r10, r11 /* add it */ 649 b 151b
650154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
651 add r10, r10, r11 /* add it */
690 mfctr r11 /* restore r11 */ 652 mfctr r11 /* restore r11 */
691 b 151b 653 b 151b
692#endif 654#endif
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index e0f7a189c48e..8ebaac75c940 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -260,6 +260,60 @@ static int __init mark_nonram_nosave(void)
260 } 260 }
261 return 0; 261 return 0;
262} 262}
263#else /* CONFIG_NEED_MULTIPLE_NODES */
264static int __init mark_nonram_nosave(void)
265{
266 return 0;
267}
268#endif
269
270static bool zone_limits_final;
271
272static unsigned long max_zone_pfns[MAX_NR_ZONES] = {
273 [0 ... MAX_NR_ZONES - 1] = ~0UL
274};
275
276/*
277 * Restrict the specified zone and all more restrictive zones
278 * to be below the specified pfn. May not be called after
279 * paging_init().
280 */
281void __init limit_zone_pfn(enum zone_type zone, unsigned long pfn_limit)
282{
283 int i;
284
285 if (WARN_ON(zone_limits_final))
286 return;
287
288 for (i = zone; i >= 0; i--) {
289 if (max_zone_pfns[i] > pfn_limit)
290 max_zone_pfns[i] = pfn_limit;
291 }
292}
293
294/*
295 * Find the least restrictive zone that is entirely below the
296 * specified pfn limit. Returns < 0 if no suitable zone is found.
297 *
298 * pfn_limit must be u64 because it can exceed 32 bits even on 32-bit
299 * systems -- the DMA limit can be higher than any possible real pfn.
300 */
301int dma_pfn_limit_to_zone(u64 pfn_limit)
302{
303 enum zone_type top_zone = ZONE_NORMAL;
304 int i;
305
306#ifdef CONFIG_HIGHMEM
307 top_zone = ZONE_HIGHMEM;
308#endif
309
310 for (i = top_zone; i >= 0; i--) {
311 if (max_zone_pfns[i] <= pfn_limit)
312 return i;
313 }
314
315 return -EPERM;
316}
263 317
264/* 318/*
265 * paging_init() sets up the page tables - in fact we've already done this. 319 * paging_init() sets up the page tables - in fact we've already done this.
@@ -268,7 +322,7 @@ void __init paging_init(void)
268{ 322{
269 unsigned long long total_ram = memblock_phys_mem_size(); 323 unsigned long long total_ram = memblock_phys_mem_size();
270 phys_addr_t top_of_ram = memblock_end_of_DRAM(); 324 phys_addr_t top_of_ram = memblock_end_of_DRAM();
271 unsigned long max_zone_pfns[MAX_NR_ZONES]; 325 enum zone_type top_zone;
272 326
273#ifdef CONFIG_PPC32 327#ifdef CONFIG_PPC32
274 unsigned long v = __fix_to_virt(__end_of_fixed_addresses - 1); 328 unsigned long v = __fix_to_virt(__end_of_fixed_addresses - 1);
@@ -290,18 +344,20 @@ void __init paging_init(void)
290 (unsigned long long)top_of_ram, total_ram); 344 (unsigned long long)top_of_ram, total_ram);
291 printk(KERN_DEBUG "Memory hole size: %ldMB\n", 345 printk(KERN_DEBUG "Memory hole size: %ldMB\n",
292 (long int)((top_of_ram - total_ram) >> 20)); 346 (long int)((top_of_ram - total_ram) >> 20));
293 memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); 347
294#ifdef CONFIG_HIGHMEM 348#ifdef CONFIG_HIGHMEM
295 max_zone_pfns[ZONE_DMA] = lowmem_end_addr >> PAGE_SHIFT; 349 top_zone = ZONE_HIGHMEM;
296 max_zone_pfns[ZONE_HIGHMEM] = top_of_ram >> PAGE_SHIFT; 350 limit_zone_pfn(ZONE_NORMAL, lowmem_end_addr >> PAGE_SHIFT);
297#else 351#else
298 max_zone_pfns[ZONE_DMA] = top_of_ram >> PAGE_SHIFT; 352 top_zone = ZONE_NORMAL;
299#endif 353#endif
354
355 limit_zone_pfn(top_zone, top_of_ram >> PAGE_SHIFT);
356 zone_limits_final = true;
300 free_area_init_nodes(max_zone_pfns); 357 free_area_init_nodes(max_zone_pfns);
301 358
302 mark_nonram_nosave(); 359 mark_nonram_nosave();
303} 360}
304#endif /* ! CONFIG_NEED_MULTIPLE_NODES */
305 361
306static void __init register_page_bootmem_info(void) 362static void __init register_page_bootmem_info(void)
307{ 363{
diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c
index ec32d463cad9..649666d5d1c2 100644
--- a/arch/powerpc/mm/numa.c
+++ b/arch/powerpc/mm/numa.c
@@ -1134,14 +1134,6 @@ void __init do_init_bootmem(void)
1134 } 1134 }
1135} 1135}
1136 1136
1137void __init paging_init(void)
1138{
1139 unsigned long max_zone_pfns[MAX_NR_ZONES];
1140 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1141 max_zone_pfns[ZONE_DMA] = memblock_end_of_DRAM() >> PAGE_SHIFT;
1142 free_area_init_nodes(max_zone_pfns);
1143}
1144
1145static int __init early_numa(char *p) 1137static int __init early_numa(char *p)
1146{ 1138{
1147 if (!p) 1139 if (!p)
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 0c1e6903597e..f22635a71d01 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -276,7 +276,7 @@ config CORENET_GENERIC
276 For 64bit kernel, the following boards are supported: 276 For 64bit kernel, the following boards are supported:
277 T208x QDS/RDB, T4240 QDS/RDB and B4 QDS 277 T208x QDS/RDB, T4240 QDS/RDB and B4 QDS
278 The following boards are supported for both 32bit and 64bit kernel: 278 The following boards are supported for both 32bit and 64bit kernel:
279 P5020 DS, P5040 DS and T104xQDS 279 P5020 DS, P5040 DS and T104xQDS/RDB
280 280
281endif # FSL_SOC_BOOKE 281endif # FSL_SOC_BOOKE
282 282
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index d22dd85e50bf..e56b89a792ed 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -20,6 +20,7 @@
20#include <asm/time.h> 20#include <asm/time.h>
21#include <asm/machdep.h> 21#include <asm/machdep.h>
22#include <asm/pci-bridge.h> 22#include <asm/pci-bridge.h>
23#include <asm/pgtable.h>
23#include <asm/ppc-pci.h> 24#include <asm/ppc-pci.h>
24#include <mm/mmu_decl.h> 25#include <mm/mmu_decl.h>
25#include <asm/prom.h> 26#include <asm/prom.h>
@@ -67,6 +68,16 @@ void __init corenet_gen_setup_arch(void)
67 68
68 swiotlb_detect_4g(); 69 swiotlb_detect_4g();
69 70
71#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
72 /*
73 * Inbound windows don't cover the full lower 4 GiB
74 * due to conflicts with PCICSRBAR and outbound windows,
75 * so limit the DMA32 zone to 2 GiB, to allow consistent
76 * allocations to succeed.
77 */
78 limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
79#endif
80
70 pr_info("%s board\n", ppc_md.name); 81 pr_info("%s board\n", ppc_md.name);
71 82
72 mpc85xx_qe_init(); 83 mpc85xx_qe_init();
@@ -129,6 +140,9 @@ static const char * const boards[] __initconst = {
129 "fsl,B4220QDS", 140 "fsl,B4220QDS",
130 "fsl,T1040QDS", 141 "fsl,T1040QDS",
131 "fsl,T1042QDS", 142 "fsl,T1042QDS",
143 "fsl,T1040RDB",
144 "fsl,T1042RDB",
145 "fsl,T1042RDB_PI",
132 "keymile,kmcoge4", 146 "keymile,kmcoge4",
133 NULL 147 NULL
134}; 148};
diff --git a/arch/powerpc/platforms/85xx/qemu_e500.c b/arch/powerpc/platforms/85xx/qemu_e500.c
index 7f2673293549..8ad2fe6f200a 100644
--- a/arch/powerpc/platforms/85xx/qemu_e500.c
+++ b/arch/powerpc/platforms/85xx/qemu_e500.c
@@ -18,6 +18,7 @@
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/of_fdt.h> 19#include <linux/of_fdt.h>
20#include <asm/machdep.h> 20#include <asm/machdep.h>
21#include <asm/pgtable.h>
21#include <asm/time.h> 22#include <asm/time.h>
22#include <asm/udbg.h> 23#include <asm/udbg.h>
23#include <asm/mpic.h> 24#include <asm/mpic.h>
@@ -44,6 +45,15 @@ static void __init qemu_e500_setup_arch(void)
44 45
45 fsl_pci_assign_primary(); 46 fsl_pci_assign_primary();
46 swiotlb_detect_4g(); 47 swiotlb_detect_4g();
48#if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
49 /*
50 * Inbound windows don't cover the full lower 4 GiB
51 * due to conflicts with PCICSRBAR and outbound windows,
52 * so limit the DMA32 zone to 2 GiB, to allow consistent
53 * allocations to succeed.
54 */
55 limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
56#endif
47 mpc85xx_smp_init(); 57 mpc85xx_smp_init();
48} 58}
49 59
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 77efbaec7b9c..e2ee226464f8 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -18,6 +18,8 @@
18#include <linux/pci.h> 18#include <linux/pci.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/of_platform.h> 20#include <linux/of_platform.h>
21#include <linux/interrupt.h>
22#include <linux/seq_file.h>
21#include <sysdev/fsl_soc.h> 23#include <sysdev/fsl_soc.h>
22#include <asm/prom.h> 24#include <asm/prom.h>
23#include <asm/hw_irq.h> 25#include <asm/hw_irq.h>
@@ -50,6 +52,7 @@ struct fsl_msi_feature {
50struct fsl_msi_cascade_data { 52struct fsl_msi_cascade_data {
51 struct fsl_msi *msi_data; 53 struct fsl_msi *msi_data;
52 int index; 54 int index;
55 int virq;
53}; 56};
54 57
55static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg) 58static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
@@ -65,11 +68,24 @@ static void fsl_msi_end_irq(struct irq_data *d)
65{ 68{
66} 69}
67 70
71static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
72{
73 struct fsl_msi *msi_data = irqd->domain->host_data;
74 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
75 int cascade_virq, srs;
76
77 srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
78 cascade_virq = msi_data->cascade_array[srs]->virq;
79
80 seq_printf(p, " fsl-msi-%d", cascade_virq);
81}
82
83
68static struct irq_chip fsl_msi_chip = { 84static struct irq_chip fsl_msi_chip = {
69 .irq_mask = mask_msi_irq, 85 .irq_mask = mask_msi_irq,
70 .irq_unmask = unmask_msi_irq, 86 .irq_unmask = unmask_msi_irq,
71 .irq_ack = fsl_msi_end_irq, 87 .irq_ack = fsl_msi_end_irq,
72 .name = "FSL-MSI", 88 .irq_print_chip = fsl_msi_print_chip,
73}; 89};
74 90
75static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq, 91static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
@@ -180,7 +196,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
180 np = of_parse_phandle(hose->dn, "fsl,msi", 0); 196 np = of_parse_phandle(hose->dn, "fsl,msi", 0);
181 if (np) { 197 if (np) {
182 if (of_device_is_compatible(np, "fsl,mpic-msi") || 198 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
183 of_device_is_compatible(np, "fsl,vmpic-msi")) 199 of_device_is_compatible(np, "fsl,vmpic-msi") ||
200 of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
184 phandle = np->phandle; 201 phandle = np->phandle;
185 else { 202 else {
186 dev_err(&pdev->dev, 203 dev_err(&pdev->dev,
@@ -239,40 +256,24 @@ out_free:
239 return rc; 256 return rc;
240} 257}
241 258
242static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) 259static irqreturn_t fsl_msi_cascade(int irq, void *data)
243{ 260{
244 struct irq_chip *chip = irq_desc_get_chip(desc);
245 struct irq_data *idata = irq_desc_get_irq_data(desc);
246 unsigned int cascade_irq; 261 unsigned int cascade_irq;
247 struct fsl_msi *msi_data; 262 struct fsl_msi *msi_data;
248 int msir_index = -1; 263 int msir_index = -1;
249 u32 msir_value = 0; 264 u32 msir_value = 0;
250 u32 intr_index; 265 u32 intr_index;
251 u32 have_shift = 0; 266 u32 have_shift = 0;
252 struct fsl_msi_cascade_data *cascade_data; 267 struct fsl_msi_cascade_data *cascade_data = data;
268 irqreturn_t ret = IRQ_NONE;
253 269
254 cascade_data = irq_get_handler_data(irq);
255 msi_data = cascade_data->msi_data; 270 msi_data = cascade_data->msi_data;
256 271
257 raw_spin_lock(&desc->lock);
258 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
259 if (chip->irq_mask_ack)
260 chip->irq_mask_ack(idata);
261 else {
262 chip->irq_mask(idata);
263 chip->irq_ack(idata);
264 }
265 }
266
267 if (unlikely(irqd_irq_inprogress(idata)))
268 goto unlock;
269
270 msir_index = cascade_data->index; 272 msir_index = cascade_data->index;
271 273
272 if (msir_index >= NR_MSI_REG_MAX) 274 if (msir_index >= NR_MSI_REG_MAX)
273 cascade_irq = NO_IRQ; 275 cascade_irq = NO_IRQ;
274 276
275 irqd_set_chained_irq_inprogress(idata);
276 switch (msi_data->feature & FSL_PIC_IP_MASK) { 277 switch (msi_data->feature & FSL_PIC_IP_MASK) {
277 case FSL_PIC_IP_MPIC: 278 case FSL_PIC_IP_MPIC:
278 msir_value = fsl_msi_read(msi_data->msi_regs, 279 msir_value = fsl_msi_read(msi_data->msi_regs,
@@ -301,40 +302,32 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
301 cascade_irq = irq_linear_revmap(msi_data->irqhost, 302 cascade_irq = irq_linear_revmap(msi_data->irqhost,
302 msi_hwirq(msi_data, msir_index, 303 msi_hwirq(msi_data, msir_index,
303 intr_index + have_shift)); 304 intr_index + have_shift));
304 if (cascade_irq != NO_IRQ) 305 if (cascade_irq != NO_IRQ) {
305 generic_handle_irq(cascade_irq); 306 generic_handle_irq(cascade_irq);
307 ret = IRQ_HANDLED;
308 }
306 have_shift += intr_index + 1; 309 have_shift += intr_index + 1;
307 msir_value = msir_value >> (intr_index + 1); 310 msir_value = msir_value >> (intr_index + 1);
308 } 311 }
309 irqd_clr_chained_irq_inprogress(idata);
310 312
311 switch (msi_data->feature & FSL_PIC_IP_MASK) { 313 return ret;
312 case FSL_PIC_IP_MPIC:
313 case FSL_PIC_IP_VMPIC:
314 chip->irq_eoi(idata);
315 break;
316 case FSL_PIC_IP_IPIC:
317 if (!irqd_irq_disabled(idata) && chip->irq_unmask)
318 chip->irq_unmask(idata);
319 break;
320 }
321unlock:
322 raw_spin_unlock(&desc->lock);
323} 314}
324 315
325static int fsl_of_msi_remove(struct platform_device *ofdev) 316static int fsl_of_msi_remove(struct platform_device *ofdev)
326{ 317{
327 struct fsl_msi *msi = platform_get_drvdata(ofdev); 318 struct fsl_msi *msi = platform_get_drvdata(ofdev);
328 int virq, i; 319 int virq, i;
329 struct fsl_msi_cascade_data *cascade_data;
330 320
331 if (msi->list.prev != NULL) 321 if (msi->list.prev != NULL)
332 list_del(&msi->list); 322 list_del(&msi->list);
333 for (i = 0; i < NR_MSI_REG_MAX; i++) { 323 for (i = 0; i < NR_MSI_REG_MAX; i++) {
334 virq = msi->msi_virqs[i]; 324 if (msi->cascade_array[i]) {
335 if (virq != NO_IRQ) { 325 virq = msi->cascade_array[i]->virq;
336 cascade_data = irq_get_handler_data(virq); 326
337 kfree(cascade_data); 327 BUG_ON(virq == NO_IRQ);
328
329 free_irq(virq, msi->cascade_array[i]);
330 kfree(msi->cascade_array[i]);
338 irq_dispose_mapping(virq); 331 irq_dispose_mapping(virq);
339 } 332 }
340 } 333 }
@@ -353,7 +346,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
353 int offset, int irq_index) 346 int offset, int irq_index)
354{ 347{
355 struct fsl_msi_cascade_data *cascade_data = NULL; 348 struct fsl_msi_cascade_data *cascade_data = NULL;
356 int virt_msir, i; 349 int virt_msir, i, ret;
357 350
358 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index); 351 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
359 if (virt_msir == NO_IRQ) { 352 if (virt_msir == NO_IRQ) {
@@ -368,11 +361,18 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
368 return -ENOMEM; 361 return -ENOMEM;
369 } 362 }
370 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class); 363 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
371 msi->msi_virqs[irq_index] = virt_msir;
372 cascade_data->index = offset; 364 cascade_data->index = offset;
373 cascade_data->msi_data = msi; 365 cascade_data->msi_data = msi;
374 irq_set_handler_data(virt_msir, cascade_data); 366 cascade_data->virq = virt_msir;
375 irq_set_chained_handler(virt_msir, fsl_msi_cascade); 367 msi->cascade_array[irq_index] = cascade_data;
368
369 ret = request_irq(virt_msir, fsl_msi_cascade, 0,
370 "fsl-msi-cascade", cascade_data);
371 if (ret) {
372 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
373 virt_msir, ret);
374 return ret;
375 }
376 376
377 /* Release the hwirqs corresponding to this MSI register */ 377 /* Release the hwirqs corresponding to this MSI register */
378 for (i = 0; i < IRQS_PER_MSI_REG; i++) 378 for (i = 0; i < IRQS_PER_MSI_REG; i++)
@@ -466,7 +466,8 @@ static int fsl_of_msi_probe(struct platform_device *dev)
466 466
467 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); 467 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
468 468
469 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3")) { 469 if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
470 of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
470 msi->srs_shift = MSIIR1_SRS_SHIFT; 471 msi->srs_shift = MSIIR1_SRS_SHIFT;
471 msi->ibs_shift = MSIIR1_IBS_SHIFT; 472 msi->ibs_shift = MSIIR1_IBS_SHIFT;
472 if (p) 473 if (p)
@@ -572,6 +573,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
572 .compatible = "fsl,vmpic-msi", 573 .compatible = "fsl,vmpic-msi",
573 .data = &vmpic_msi_feature, 574 .data = &vmpic_msi_feature,
574 }, 575 },
576 {
577 .compatible = "fsl,vmpic-msi-v4.3",
578 .data = &vmpic_msi_feature,
579 },
575#endif 580#endif
576 {} 581 {}
577}; 582};
diff --git a/arch/powerpc/sysdev/fsl_msi.h b/arch/powerpc/sysdev/fsl_msi.h
index df9aa9fe0933..420cfcbdac01 100644
--- a/arch/powerpc/sysdev/fsl_msi.h
+++ b/arch/powerpc/sysdev/fsl_msi.h
@@ -27,6 +27,8 @@
27#define FSL_PIC_IP_IPIC 0x00000002 27#define FSL_PIC_IP_IPIC 0x00000002
28#define FSL_PIC_IP_VMPIC 0x00000003 28#define FSL_PIC_IP_VMPIC 0x00000003
29 29
30struct fsl_msi_cascade_data;
31
30struct fsl_msi { 32struct fsl_msi {
31 struct irq_domain *irqhost; 33 struct irq_domain *irqhost;
32 34
@@ -37,7 +39,7 @@ struct fsl_msi {
37 u32 srs_shift; /* Shift of the shared interrupt register select */ 39 u32 srs_shift; /* Shift of the shared interrupt register select */
38 void __iomem *msi_regs; 40 void __iomem *msi_regs;
39 u32 feature; 41 u32 feature;
40 int msi_virqs[NR_MSI_REG_MAX]; 42 struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
41 43
42 struct msi_bitmap bitmap; 44 struct msi_bitmap bitmap;
43 45
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index c5077673bd94..65d2ed4549e6 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -522,7 +522,8 @@ int fsl_add_bridge(struct platform_device *pdev, int is_primary)
522 } else { 522 } else {
523 /* For PCI read PROG to identify controller mode */ 523 /* For PCI read PROG to identify controller mode */
524 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif); 524 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
525 if ((progif & 1) == 1) 525 if ((progif & 1) &&
526 !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
526 goto no_bridge; 527 goto no_bridge;
527 } 528 }
528 529
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-08 19:53:23 -0500