diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/blackfin/Kconfig | 24 | ||||
-rw-r--r-- | arch/blackfin/include/asm/cplb.h | 35 | ||||
-rw-r--r-- | arch/blackfin/mach-common/arch_checks.c | 7 |
3 files changed, 43 insertions, 23 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index c04e7a4836f2..f1a7969b46ca 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
@@ -913,7 +913,7 @@ config BFIN_ICACHE_LOCK | |||
913 | bool "Enable Instruction Cache Locking" | 913 | bool "Enable Instruction Cache Locking" |
914 | 914 | ||
915 | choice | 915 | choice |
916 | prompt "Policy" | 916 | prompt "External memory cache policy" |
917 | depends on BFIN_DCACHE | 917 | depends on BFIN_DCACHE |
918 | default BFIN_WB if !SMP | 918 | default BFIN_WB if !SMP |
919 | default BFIN_WT if SMP | 919 | default BFIN_WT if SMP |
@@ -954,12 +954,22 @@ config BFIN_WT | |||
954 | 954 | ||
955 | endchoice | 955 | endchoice |
956 | 956 | ||
957 | config BFIN_L2_CACHEABLE | 957 | choice |
958 | bool "Cache L2 SRAM" | 958 | prompt "L2 SRAM cache policy" |
959 | depends on (BFIN_DCACHE || BFIN_ICACHE) && (BF54x || (BF561 && !SMP)) | 959 | depends on (BF54x || BF561) |
960 | default n | 960 | default BFIN_L2_WT |
961 | help | 961 | config BFIN_L2_WB |
962 | Select to make L2 SRAM cacheable in L1 data and instruction cache. | 962 | bool "Write back" |
963 | depends on !SMP | ||
964 | |||
965 | config BFIN_L2_WT | ||
966 | bool "Write through" | ||
967 | depends on !SMP | ||
968 | |||
969 | config BFIN_L2_NOT_CACHED | ||
970 | bool "Not cached" | ||
971 | |||
972 | endchoice | ||
963 | 973 | ||
964 | config MPU | 974 | config MPU |
965 | bool "Enable the memory protection unit (EXPERIMENTAL)" | 975 | bool "Enable the memory protection unit (EXPERIMENTAL)" |
diff --git a/arch/blackfin/include/asm/cplb.h b/arch/blackfin/include/asm/cplb.h index ad566ff9ad16..a75a6a9f0949 100644 --- a/arch/blackfin/include/asm/cplb.h +++ b/arch/blackfin/include/asm/cplb.h | |||
@@ -53,29 +53,32 @@ | |||
53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) | 53 | #define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
54 | #endif | 54 | #endif |
55 | 55 | ||
56 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | ||
57 | #define SDRAM_EBIU (CPLB_COMMON) | ||
58 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
59 | |||
56 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) | 60 | #define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
57 | 61 | ||
58 | #ifdef CONFIG_SMP | 62 | #ifdef CONFIG_SMP |
59 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) | 63 | #define L2_ATTR (INITIAL_T | I_CPLB | D_CPLB) |
60 | #define L2_IMEMORY (CPLB_COMMON | CPLB_LOCK) | 64 | #define L2_IMEMORY (CPLB_COMMON) |
61 | #define L2_DMEMORY (CPLB_COMMON | CPLB_LOCK) | 65 | #define L2_DMEMORY (CPLB_LOCK | CPLB_COMMON) |
62 | 66 | ||
63 | #else | 67 | #else |
64 | #ifdef CONFIG_BFIN_L2_CACHEABLE | 68 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) |
65 | #define L2_IMEMORY (SDRAM_IGENERIC) | 69 | #define L2_IMEMORY (SDRAM_IGENERIC) |
66 | #define L2_DMEMORY (SDRAM_DGENERIC) | 70 | |
67 | #else | 71 | # if defined(CONFIG_BFIN_L2_WB) |
68 | #define L2_IMEMORY (CPLB_COMMON) | 72 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_COMMON) |
69 | #define L2_DMEMORY (CPLB_COMMON) | 73 | # elif defined(CONFIG_BFIN_L2_WT) |
70 | #endif /* CONFIG_BFIN_L2_CACHEABLE */ | 74 | # define L2_DMEMORY (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON) |
71 | 75 | # elif defined(CONFIG_BFIN_L2_NOT_CACHED) | |
72 | #define L2_ATTR (INITIAL_T | SWITCH_T | I_CPLB | D_CPLB) | 76 | # define L2_DMEMORY (CPLB_COMMON) |
77 | # else | ||
78 | # define L2_DMEMORY (0) | ||
79 | # endif | ||
73 | #endif /* CONFIG_SMP */ | 80 | #endif /* CONFIG_SMP */ |
74 | 81 | ||
75 | #define SDRAM_DNON_CHBL (CPLB_COMMON) | ||
76 | #define SDRAM_EBIU (CPLB_COMMON) | ||
77 | #define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY) | ||
78 | |||
79 | #define SIZE_1K 0x00000400 /* 1K */ | 82 | #define SIZE_1K 0x00000400 /* 1K */ |
80 | #define SIZE_4K 0x00001000 /* 4K */ | 83 | #define SIZE_4K 0x00001000 /* 4K */ |
81 | #define SIZE_1M 0x00100000 /* 1M */ | 84 | #define SIZE_1M 0x00100000 /* 1M */ |
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 80d39b2f9db2..da93d9207165 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c | |||
@@ -71,3 +71,10 @@ | |||
71 | #if ANOMALY_05000448 | 71 | #if ANOMALY_05000448 |
72 | # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. | 72 | # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. |
73 | #endif | 73 | #endif |
74 | |||
75 | /* if 220 exists, can not set External Memory WB and L2 not_cached, either External Memory not_cached and L2 WB */ | ||
76 | #if ANOMALY_05000220 && \ | ||
77 | ((defined(CONFIG_BFIN_WB) && defined(CONFIG_BFIN_L2_NOT_CACHED)) || \ | ||
78 | (!defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_L2_WB))) | ||
79 | # error You are exposing Anomaly 220 in this config, either config L2 as Write Through, or make External Memory WB. | ||
80 | #endif | ||