7 files changed, 318 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts
new file mode 100644
index 000000000000..d86bf2eb4c13
--- /dev/null
+++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,203 @@
+/*
+ * P5040DS Device Tree Source
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * This software is provided by Freescale Semiconductor "as is" and any
+ * express or implied warranties, including, but not limited to, the implied
+ * warranties of merchantability and fitness for a particular purpose are
+ * disclaimed. In no event shall Freescale Semiconductor be liable for any
+ * direct, indirect, incidental, special, exemplary, or consequential damages
+ * (including, but not limited to, procurement of substitute goods or services;
+ * loss of use, data, or profits; or business interruption) however caused and
+ * on any theory of liability, whether in contract, strict liability, or tort
+ * (including negligence or otherwise) arising in any way out of the use of this
+ * software, even if advised of the possibility of such damage.
+ */
+/include/ "fsl/p5040si-pre.dtsi"
+/ {
+        model = "fsl,P5040DS";
+        compatible = "fsl,P5040DS";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        interrupt-parent = <&mpic>;
+        memory {
+                device_type = "memory";
+        };
+        dcsr: dcsr@f00000000 {
+                ranges = <0x00000000 0xf 0x00000000 0x01008000>;
+        };
+        soc: soc@ffe000000 {
+                ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
+                reg = <0xf 0xfe000000 0 0x00001000>;
+                spi@110000 {
+                        flash@0 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                compatible = "spansion,s25sl12801";
+                                reg = <0>;
+                                spi-max-frequency = <40000000>; /* input clock */
+                                partition@u-boot {
+                                        label = "u-boot";
+                                        reg = <0x00000000 0x00100000>;
+                                };
+                                partition@kernel {
+                                        label = "kernel";
+                                        reg = <0x00100000 0x00500000>;
+                                };
+                                partition@dtb {
+                                        label = "dtb";
+                                        reg = <0x00600000 0x00100000>;
+                                };
+                                partition@fs {
+                                        label = "file system";
+                                        reg = <0x00700000 0x00900000>;
+                                };
+                        };
+                };
+                i2c@118100 {
+                        eeprom@51 {
+                                compatible = "at24,24c256";
+                                reg = <0x51>;
+                        };
+                        eeprom@52 {
+                                compatible = "at24,24c256";
+                                reg = <0x52>;
+                        };
+                };
+                i2c@119100 {
+                        rtc@68 {
+                                compatible = "dallas,ds3232";
+                                reg = <0x68>;
+                                interrupts = <0x1 0x1 0 0>;
+                        };
+                };
+        };
+        lbc: localbus@ffe124000 {
+                reg = <0xf 0xfe124000 0 0x1000>;
+                ranges = <0 0 0xf 0xe8000000 0x08000000
+                          2 0 0xf 0xffa00000 0x00040000
+                          3 0 0xf 0xffdf0000 0x00008000>;
+                flash@0,0 {
+                        compatible = "cfi-flash";
+                        reg = <0 0 0x08000000>;
+                        bank-width = <2>;
+                        device-width = <2>;
+                };
+                nand@2,0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "fsl,elbc-fcm-nand";
+                        reg = <0x2 0x0 0x40000>;
+                        partition@0 {
+                                label = "NAND U-Boot Image";
+                                reg = <0x0 0x02000000>;
+                        };
+                        partition@2000000 {
+                                label = "NAND Root File System";
+                                reg = <0x02000000 0x10000000>;
+                        };
+                        partition@12000000 {
+                                label = "NAND Compressed RFS Image";
+                                reg = <0x12000000 0x08000000>;
+                        };
+                        partition@1a000000 {
+                                label = "NAND Linux Kernel Image";
+                                reg = <0x1a000000 0x04000000>;
+                        };
+                        partition@1e000000 {
+                                label = "NAND DTB Image";
+                                reg = <0x1e000000 0x01000000>;
+                        };
+                        partition@1f000000 {
+                                label = "NAND Writable User area";
+                                reg = <0x1f000000 0x01000000>;
+                        };
+                };
+                board-control@3,0 {
+                        compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
+                        reg = <3 0 0x40>;
+                };
+        };
+        pci0: pcie@ffe200000 {
+                reg = <0xf 0xfe200000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci1: pcie@ffe201000 {
+                reg = <0xf 0xfe201000 0 0x1000>;
+                ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
+                          0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+        pci2: pcie@ffe202000 {
+                reg = <0xf 0xfe202000 0 0x1000>;
+                ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
+                          0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
+                pcie@0 {
+                        ranges = <0x02000000 0 0xe0000000
+                                  0x02000000 0 0xe0000000
+                                  0 0x20000000
+                                  0x01000000 0 0x00000000
+                                  0x01000000 0 0x00000000
+                                  0 0x00010000>;
+                };
+        };
+};
+/include/ "fsl/p5040si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 8b3d57c1ebe8..1c0f2432ecdb 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -27,6 +27,7 @@ CONFIG_P2041_RDB=y
 CONFIG_P3041_DS=y
 CONFIG_P4080_DS=y
 CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
 CONFIG_HIGHMEM=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_BINFMT_MISC=m
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 0516e22ca3de..88fa5c46f66f 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MAC_PARTITION=y
 CONFIG_P5020_DS=y
+CONFIG_P5040_DS=y
 # CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
 CONFIG_BINFMT_MISC=m
 CONFIG_IRQ_ALL_CPUS=y
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index 159c01e91463..31f0618ec677 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -254,6 +254,20 @@ config P5020_DS
        help
          This option enables support for the P5020 DS board
+config P5040_DS
+        bool "Freescale P5040 DS"
+        select DEFAULT_UIMAGE
+        select E500
+        select PPC_E500MC
+        select PHYS_64BIT
+        select SWIOTLB
+        select ARCH_REQUIRE_GPIOLIB
+        select GPIO_MPC8XXX
+        select HAS_RAPIDIO
+        select PPC_EPAPR_HV_PIC
+        help
+          This option enables support for the P5040 DS board
 config PPC_QEMU_E500
        bool "QEMU generic e500 platform"
        depends on EXPERIMENTAL
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 3dfe81175036..d99268aef556 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_P2041_RDB)   += p2041_rdb.o corenet_ds.o
 obj-$(CONFIG_P3041_DS)    += p3041_ds.o corenet_ds.o
 obj-$(CONFIG_P4080_DS)    += p4080_ds.o corenet_ds.o
 obj-$(CONFIG_P5020_DS)    += p5020_ds.o corenet_ds.o
+obj-$(CONFIG_P5040_DS)    += p5040_ds.o corenet_ds.o
 obj-$(CONFIG_STX_GP3)     += stx_gp3.o
 obj-$(CONFIG_TQM85xx)     += tqm85xx.o
 obj-$(CONFIG_SBC8548)     += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 925b02874233..473d57381119 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -63,7 +63,9 @@ void __init corenet_ds_setup_arch(void)
 #ifdef CONFIG_PCI
        for_each_node_by_type(np, "pci") {
                if (of_device_is_compatible(np, "fsl,p4080-pcie") ||
-                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {
+                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2") ||
+                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.3") ||
+                    of_device_is_compatible(np, "fsl,qoriq-pcie-v2.4")) {
                        fsl_add_bridge(np, 0);
                        hose = pci_find_hose_for_OF_device(np);
                        max = min(max, hose->dma_window_base_cur +
@@ -99,6 +101,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
        {
                .compatible     = "fsl,qoriq-pcie-v2.2",
        },
+        {
+                .compatible     = "fsl,qoriq-pcie-v2.3",
+        },
+        {
+                .compatible     = "fsl,qoriq-pcie-v2.4",
+        },
        /* The following two are for the Freescale hypervisor */
        {
                .name           = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
new file mode 100644
index 000000000000..8e22a3436e04
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,89 @@
+/*
+ * P5040 DS Setup
+ *
+ * Copyright 2009-2010 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <asm/machdep.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+#include <linux/of_fdt.h>
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include <asm/ehv_pic.h>
+#include "corenet_ds.h"
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init p5040_ds_probe(void)
+{
+        unsigned long root = of_get_flat_dt_root();
+#ifdef CONFIG_SMP
+        extern struct smp_ops_t smp_85xx_ops;
+#endif
+        if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
+                return 1;
+        /* Check if we're running under the Freescale hypervisor */
+        if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
+                ppc_md.init_IRQ = ehv_pic_init;
+                ppc_md.get_irq = ehv_pic_get_irq;
+                ppc_md.restart = fsl_hv_restart;
+                ppc_md.power_off = fsl_hv_halt;
+                ppc_md.halt = fsl_hv_halt;
+#ifdef CONFIG_SMP
+                /*
+                 * Disable the timebase sync operations because we can't write
+                 * to the timebase registers under the hypervisor.
+                  */
+                smp_85xx_ops.give_timebase = NULL;
+                smp_85xx_ops.take_timebase = NULL;
+#endif
+                return 1;
+        }
+        return 0;
+}
+define_machine(p5040_ds) {
+        .name                   = "P5040 DS",
+        .probe                  = p5040_ds_probe,
+        .setup_arch             = corenet_ds_setup_arch,
+        .init_IRQ               = corenet_ds_pic_init,
+#ifdef CONFIG_PCI
+        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
+#endif
+/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
+#ifdef CONFIG_PPC64
+        .get_irq                = mpic_get_irq,
+#else
+        .get_irq                = mpic_get_coreint_irq,
+#endif
+        .restart                = fsl_rstcr_restart,
+        .calibrate_decr         = generic_calibrate_decr,
+        .progress               = udbg_progress,
+#ifdef CONFIG_PPC64
+        .power_save             = book3e_idle,
+#else
+        .power_save             = e500_idle,
+#endif
+};
+machine_device_initcall(p5040_ds, corenet_ds_publish_devices);
+#ifdef CONFIG_SWIOTLB
+machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
+#endif

diff --git a/arch/powerpc/boot/dts/p5040ds.dts b/arch/powerpc/boot/dts/p5040ds.dts new file mode 100644 index 000000000000..d86bf2eb4c13 --- /dev/null +++ b/arch/powerpc/boot/dts/p5040ds.dts
@@ -0,0 +1,203 @@
		1	/*
		2	* P5040DS Device Tree Source
		3	*
		4	* Copyright 2012 Freescale Semiconductor Inc.
		5	*
		6	* Redistribution and use in source and binary forms, with or without
		7	* modification, are permitted provided that the following conditions are met:
		8	* * Redistributions of source code must retain the above copyright
		9	* notice, this list of conditions and the following disclaimer.
		10	* * Redistributions in binary form must reproduce the above copyright
		11	* notice, this list of conditions and the following disclaimer in the
		12	* documentation and/or other materials provided with the distribution.
		13	* * Neither the name of Freescale Semiconductor nor the
		14	* names of its contributors may be used to endorse or promote products
		15	* derived from this software without specific prior written permission.
		16	*
		17	*
		18	* ALTERNATIVELY, this software may be distributed under the terms of the
		19	* GNU General Public License ("GPL") as published by the Free Software
		20	* Foundation, either version 2 of that License or (at your option) any
		21	* later version.
		22	*
		23	* This software is provided by Freescale Semiconductor "as is" and any
		24	* express or implied warranties, including, but not limited to, the implied
		25	* warranties of merchantability and fitness for a particular purpose are
		26	* disclaimed. In no event shall Freescale Semiconductor be liable for any
		27	* direct, indirect, incidental, special, exemplary, or consequential damages
		28	* (including, but not limited to, procurement of substitute goods or services;
		29	* loss of use, data, or profits; or business interruption) however caused and
		30	* on any theory of liability, whether in contract, strict liability, or tort
		31	* (including negligence or otherwise) arising in any way out of the use of this
		32	* software, even if advised of the possibility of such damage.
		33	*/
		34
		35	/include/ "fsl/p5040si-pre.dtsi"
		36
		37	/ {
		38	model = "fsl,P5040DS";
		39	compatible = "fsl,P5040DS";
		40	#address-cells = <2>;
		41	#size-cells = <2>;
		42	interrupt-parent = <&mpic>;
		43
		44	memory {
		45	device_type = "memory";
		46	};
		47
		48	dcsr: dcsr@f00000000 {
		49	ranges = <0x00000000 0xf 0x00000000 0x01008000>;
		50	};
		51
		52	soc: soc@ffe000000 {
		53	ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		54	reg = <0xf 0xfe000000 0 0x00001000>;
		55	spi@110000 {
		56	flash@0 {
		57	#address-cells = <1>;
		58	#size-cells = <1>;
		59	compatible = "spansion,s25sl12801";
		60	reg = <0>;
		61	spi-max-frequency = <40000000>; /* input clock */
		62	partition@u-boot {
		63	label = "u-boot";
		64	reg = <0x00000000 0x00100000>;
		65	};
		66	partition@kernel {
		67	label = "kernel";
		68	reg = <0x00100000 0x00500000>;
		69	};
		70	partition@dtb {
		71	label = "dtb";
		72	reg = <0x00600000 0x00100000>;
		73	};
		74	partition@fs {
		75	label = "file system";
		76	reg = <0x00700000 0x00900000>;
		77	};
		78	};
		79	};
		80
		81	i2c@118100 {
		82	eeprom@51 {
		83	compatible = "at24,24c256";
		84	reg = <0x51>;
		85	};
		86	eeprom@52 {
		87	compatible = "at24,24c256";
		88	reg = <0x52>;
		89	};
		90	};
		91
		92	i2c@119100 {
		93	rtc@68 {
		94	compatible = "dallas,ds3232";
		95	reg = <0x68>;
		96	interrupts = <0x1 0x1 0 0>;
		97	};
		98	};
		99	};
		100
		101	lbc: localbus@ffe124000 {
		102	reg = <0xf 0xfe124000 0 0x1000>;
		103	ranges = <0 0 0xf 0xe8000000 0x08000000
		104	2 0 0xf 0xffa00000 0x00040000
		105	3 0 0xf 0xffdf0000 0x00008000>;
		106
		107	flash@0,0 {
		108	compatible = "cfi-flash";
		109	reg = <0 0 0x08000000>;
		110	bank-width = <2>;
		111	device-width = <2>;
		112	};
		113
		114	nand@2,0 {
		115	#address-cells = <1>;
		116	#size-cells = <1>;
		117	compatible = "fsl,elbc-fcm-nand";
		118	reg = <0x2 0x0 0x40000>;
		119
		120	partition@0 {
		121	label = "NAND U-Boot Image";
		122	reg = <0x0 0x02000000>;
		123	};
		124
		125	partition@2000000 {
		126	label = "NAND Root File System";
		127	reg = <0x02000000 0x10000000>;
		128	};
		129
		130	partition@12000000 {
		131	label = "NAND Compressed RFS Image";
		132	reg = <0x12000000 0x08000000>;
		133	};
		134
		135	partition@1a000000 {
		136	label = "NAND Linux Kernel Image";
		137	reg = <0x1a000000 0x04000000>;
		138	};
		139
		140	partition@1e000000 {
		141	label = "NAND DTB Image";
		142	reg = <0x1e000000 0x01000000>;
		143	};
		144
		145	partition@1f000000 {
		146	label = "NAND Writable User area";
		147	reg = <0x1f000000 0x01000000>;
		148	};
		149	};
		150
		151	board-control@3,0 {
		152	compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
		153	reg = <3 0 0x40>;
		154	};
		155	};
		156
		157	pci0: pcie@ffe200000 {
		158	reg = <0xf 0xfe200000 0 0x1000>;
		159	ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
		160	0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
		161	pcie@0 {
		162	ranges = <0x02000000 0 0xe0000000
		163	0x02000000 0 0xe0000000
		164	0 0x20000000
		165
		166	0x01000000 0 0x00000000
		167	0x01000000 0 0x00000000
		168	0 0x00010000>;
		169	};
		170	};
		171
		172	pci1: pcie@ffe201000 {
		173	reg = <0xf 0xfe201000 0 0x1000>;
		174	ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
		175	0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
		176	pcie@0 {
		177	ranges = <0x02000000 0 0xe0000000
		178	0x02000000 0 0xe0000000
		179	0 0x20000000
		180
		181	0x01000000 0 0x00000000
		182	0x01000000 0 0x00000000
		183	0 0x00010000>;
		184	};
		185	};
		186
		187	pci2: pcie@ffe202000 {
		188	reg = <0xf 0xfe202000 0 0x1000>;
		189	ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
		190	0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
		191	pcie@0 {
		192	ranges = <0x02000000 0 0xe0000000
		193	0x02000000 0 0xe0000000
		194	0 0x20000000
		195
		196	0x01000000 0 0x00000000
		197	0x01000000 0 0x00000000
		198	0 0x00010000>;
		199	};
		200	};
		201	};
		202
		203	/include/ "fsl/p5040si-post.dtsi"


diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig index 8b3d57c1ebe8..1c0f2432ecdb 100644 --- a/arch/powerpc/configs/corenet32_smp_defconfig +++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -27,6 +27,7 @@ CONFIG_P2041_RDB=y
27	CONFIG_P3041_DS=y	27	CONFIG_P3041_DS=y
28	CONFIG_P4080_DS=y	28	CONFIG_P4080_DS=y
29	CONFIG_P5020_DS=y	29	CONFIG_P5020_DS=y
		30	CONFIG_P5040_DS=y
30	CONFIG_HIGHMEM=y	31	CONFIG_HIGHMEM=y
31	# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set	32	# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32	CONFIG_BINFMT_MISC=m	33	CONFIG_BINFMT_MISC=m


diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig index 0516e22ca3de..88fa5c46f66f 100644 --- a/arch/powerpc/configs/corenet64_smp_defconfig +++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -23,6 +23,7 @@ CONFIG_MODVERSIONS=y
23	CONFIG_PARTITION_ADVANCED=y	23	CONFIG_PARTITION_ADVANCED=y
24	CONFIG_MAC_PARTITION=y	24	CONFIG_MAC_PARTITION=y
25	CONFIG_P5020_DS=y	25	CONFIG_P5020_DS=y
		26	CONFIG_P5040_DS=y
26	# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set	27	# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
27	CONFIG_BINFMT_MISC=m	28	CONFIG_BINFMT_MISC=m
28	CONFIG_IRQ_ALL_CPUS=y	29	CONFIG_IRQ_ALL_CPUS=y


diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 159c01e91463..31f0618ec677 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -254,6 +254,20 @@ config P5020_DS
254	help	254	help
255	This option enables support for the P5020 DS board	255	This option enables support for the P5020 DS board
256		256
		257	config P5040_DS
		258	bool "Freescale P5040 DS"
		259	select DEFAULT_UIMAGE
		260	select E500
		261	select PPC_E500MC
		262	select PHYS_64BIT
		263	select SWIOTLB
		264	select ARCH_REQUIRE_GPIOLIB
		265	select GPIO_MPC8XXX
		266	select HAS_RAPIDIO
		267	select PPC_EPAPR_HV_PIC
		268	help
		269	This option enables support for the P5040 DS board
		270
257	config PPC_QEMU_E500	271	config PPC_QEMU_E500
258	bool "QEMU generic e500 platform"	272	bool "QEMU generic e500 platform"
259	depends on EXPERIMENTAL	273	depends on EXPERIMENTAL


diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 3dfe81175036..d99268aef556 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o
20	obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o	20	obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
21	obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o	21	obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
22	obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o	22	obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
		23	obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
23	obj-$(CONFIG_STX_GP3) += stx_gp3.o	24	obj-$(CONFIG_STX_GP3) += stx_gp3.o
24	obj-$(CONFIG_TQM85xx) += tqm85xx.o	25	obj-$(CONFIG_TQM85xx) += tqm85xx.o
25	obj-$(CONFIG_SBC8548) += sbc8548.o	26	obj-$(CONFIG_SBC8548) += sbc8548.o


diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c index 925b02874233..473d57381119 100644 --- a/arch/powerpc/platforms/85xx/corenet_ds.c +++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -63,7 +63,9 @@ void __init corenet_ds_setup_arch(void)
63	#ifdef CONFIG_PCI	63	#ifdef CONFIG_PCI
64	for_each_node_by_type(np, "pci") {	64	for_each_node_by_type(np, "pci") {
65	if (of_device_is_compatible(np, "fsl,p4080-pcie") \|\|	65	if (of_device_is_compatible(np, "fsl,p4080-pcie") \|\|
66	of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2")) {	66	of_device_is_compatible(np, "fsl,qoriq-pcie-v2.2") \|\|
		67	of_device_is_compatible(np, "fsl,qoriq-pcie-v2.3") \|\|
		68	of_device_is_compatible(np, "fsl,qoriq-pcie-v2.4")) {
67	fsl_add_bridge(np, 0);	69	fsl_add_bridge(np, 0);
68	hose = pci_find_hose_for_OF_device(np);	70	hose = pci_find_hose_for_OF_device(np);
69	max = min(max, hose->dma_window_base_cur +	71	max = min(max, hose->dma_window_base_cur +
@@ -99,6 +101,12 @@ static const struct of_device_id of_device_ids[] __devinitconst = {
99	{	101	{
100	.compatible = "fsl,qoriq-pcie-v2.2",	102	.compatible = "fsl,qoriq-pcie-v2.2",
101	},	103	},
		104	{
		105	.compatible = "fsl,qoriq-pcie-v2.3",
		106	},
		107	{
		108	.compatible = "fsl,qoriq-pcie-v2.4",
		109	},
102	/* The following two are for the Freescale hypervisor */	110	/* The following two are for the Freescale hypervisor */
103	{	111	{
104	.name = "hypervisor",	112	.name = "hypervisor",


diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c new file mode 100644 index 000000000000..8e22a3436e04 --- /dev/null +++ b/arch/powerpc/platforms/85xx/p5040_ds.c
@@ -0,0 +1,89 @@
		1	/*
		2	* P5040 DS Setup
		3	*
		4	* Copyright 2009-2010 Freescale Semiconductor Inc.
		5	*
		6	* This program is free software; you can redistribute it and/or modify it
		7	* under the terms of the GNU General Public License as published by the
		8	* Free Software Foundation; either version 2 of the License, or (at your
		9	* option) any later version.
		10	*/
		11
		12	#include <linux/kernel.h>
		13	#include <linux/pci.h>
		14
		15	#include <asm/machdep.h>
		16	#include <asm/udbg.h>
		17	#include <asm/mpic.h>
		18
		19	#include <linux/of_fdt.h>
		20
		21	#include <sysdev/fsl_soc.h>
		22	#include <sysdev/fsl_pci.h>
		23	#include <asm/ehv_pic.h>
		24
		25	#include "corenet_ds.h"
		26
		27	/*
		28	* Called very early, device-tree isn't unflattened
		29	*/
		30	static int __init p5040_ds_probe(void)
		31	{
		32	unsigned long root = of_get_flat_dt_root();
		33	#ifdef CONFIG_SMP
		34	extern struct smp_ops_t smp_85xx_ops;
		35	#endif
		36
		37	if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
		38	return 1;
		39
		40	/* Check if we're running under the Freescale hypervisor */
		41	if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
		42	ppc_md.init_IRQ = ehv_pic_init;
		43	ppc_md.get_irq = ehv_pic_get_irq;
		44	ppc_md.restart = fsl_hv_restart;
		45	ppc_md.power_off = fsl_hv_halt;
		46	ppc_md.halt = fsl_hv_halt;
		47	#ifdef CONFIG_SMP
		48	/*
		49	* Disable the timebase sync operations because we can't write
		50	* to the timebase registers under the hypervisor.
		51	*/
		52	smp_85xx_ops.give_timebase = NULL;
		53	smp_85xx_ops.take_timebase = NULL;
		54	#endif
		55	return 1;
		56	}
		57
		58	return 0;
		59	}
		60
		61	define_machine(p5040_ds) {
		62	.name = "P5040 DS",
		63	.probe = p5040_ds_probe,
		64	.setup_arch = corenet_ds_setup_arch,
		65	.init_IRQ = corenet_ds_pic_init,
		66	#ifdef CONFIG_PCI
		67	.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
		68	#endif
		69	/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
		70	#ifdef CONFIG_PPC64
		71	.get_irq = mpic_get_irq,
		72	#else
		73	.get_irq = mpic_get_coreint_irq,
		74	#endif
		75	.restart = fsl_rstcr_restart,
		76	.calibrate_decr = generic_calibrate_decr,
		77	.progress = udbg_progress,
		78	#ifdef CONFIG_PPC64
		79	.power_save = book3e_idle,
		80	#else
		81	.power_save = e500_idle,
		82	#endif
		83	};
		84
		85	machine_device_initcall(p5040_ds, corenet_ds_publish_devices);
		86
		87	#ifdef CONFIG_SWIOTLB
		88	machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
		89	#endif