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-rw-r--r--arch/arm/mm/context.c11
-rw-r--r--arch/arm/mm/proc-v7.S10
2 files changed, 11 insertions, 10 deletions
diff --git a/arch/arm/mm/context.c b/arch/arm/mm/context.c
index 8bfae964b133..b6c776ae4039 100644
--- a/arch/arm/mm/context.c
+++ b/arch/arm/mm/context.c
@@ -24,7 +24,9 @@ DEFINE_PER_CPU(struct mm_struct *, current_mm);
24 24
25/* 25/*
26 * We fork()ed a process, and we need a new context for the child 26 * We fork()ed a process, and we need a new context for the child
27 * to run in. 27 * to run in. We reserve version 0 for initial tasks so we will
28 * always allocate an ASID. The ASID 0 is reserved for the TTBR
29 * register changing sequence.
28 */ 30 */
29void __init_new_context(struct task_struct *tsk, struct mm_struct *mm) 31void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
30{ 32{
@@ -34,11 +36,8 @@ void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
34 36
35static void flush_context(void) 37static void flush_context(void)
36{ 38{
37 u32 ttb; 39 /* set the reserved ASID before flushing the TLB */
38 /* Copy TTBR1 into TTBR0 */ 40 asm("mcr p15, 0, %0, c13, c0, 1\n" : : "r" (0));
39 asm volatile("mrc p15, 0, %0, c2, c0, 1\n"
40 "mcr p15, 0, %0, c2, c0, 0"
41 : "=r" (ttb));
42 isb(); 41 isb();
43 local_flush_tlb_all(); 42 local_flush_tlb_all();
44 if (icache_is_vivt_asid_tagged()) { 43 if (icache_is_vivt_asid_tagged()) {
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b3b566ec83d3..3c3867850a30 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -108,16 +108,18 @@ ENTRY(cpu_v7_switch_mm)
108#ifdef CONFIG_ARM_ERRATA_430973 108#ifdef CONFIG_ARM_ERRATA_430973
109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB 109 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
110#endif 110#endif
111 mrc p15, 0, r2, c2, c0, 1 @ load TTB 1 111#ifdef CONFIG_ARM_ERRATA_754322
112 mcr p15, 0, r2, c2, c0, 0 @ into TTB 0 112 dsb
113#endif
114 mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
115 isb
1161: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
113 isb 117 isb
114#ifdef CONFIG_ARM_ERRATA_754322 118#ifdef CONFIG_ARM_ERRATA_754322
115 dsb 119 dsb
116#endif 120#endif
117 mcr p15, 0, r1, c13, c0, 1 @ set context ID 121 mcr p15, 0, r1, c13, c0, 1 @ set context ID
118 isb 122 isb
119 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
120 isb
121#endif 123#endif
122 mov pc, lr 124 mov pc, lr
123ENDPROC(cpu_v7_switch_mm) 125ENDPROC(cpu_v7_switch_mm)