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-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c4
2 files changed, 2 insertions, 6 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
index c541301c7f2b..a63cdcaee0b2 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -154,8 +154,8 @@ static struct clk mstp_clks[] = {
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0), 154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0), 155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0), 156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0), 157 MSTP("tmu_fck", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0), 158 MSTP("cmt_fck", &r_clk, MSTPCR0, 14, 0),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0), 159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0), 160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0), 161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index 6f8394942fc5..3681cafdb4af 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -205,7 +205,6 @@ static struct platform_device jpu_device = {
205static struct sh_timer_config cmt_platform_data = { 205static struct sh_timer_config cmt_platform_data = {
206 .channel_offset = 0x60, 206 .channel_offset = 0x60,
207 .timer_bit = 5, 207 .timer_bit = 5,
208 .clk = "cmt0",
209 .clockevent_rating = 125, 208 .clockevent_rating = 125,
210 .clocksource_rating = 200, 209 .clocksource_rating = 200,
211}; 210};
@@ -235,7 +234,6 @@ static struct platform_device cmt_device = {
235static struct sh_timer_config tmu0_platform_data = { 234static struct sh_timer_config tmu0_platform_data = {
236 .channel_offset = 0x04, 235 .channel_offset = 0x04,
237 .timer_bit = 0, 236 .timer_bit = 0,
238 .clk = "tmu0",
239 .clockevent_rating = 200, 237 .clockevent_rating = 200,
240}; 238};
241 239
@@ -264,7 +262,6 @@ static struct platform_device tmu0_device = {
264static struct sh_timer_config tmu1_platform_data = { 262static struct sh_timer_config tmu1_platform_data = {
265 .channel_offset = 0x10, 263 .channel_offset = 0x10,
266 .timer_bit = 1, 264 .timer_bit = 1,
267 .clk = "tmu0",
268 .clocksource_rating = 200, 265 .clocksource_rating = 200,
269}; 266};
270 267
@@ -293,7 +290,6 @@ static struct platform_device tmu1_device = {
293static struct sh_timer_config tmu2_platform_data = { 290static struct sh_timer_config tmu2_platform_data = {
294 .channel_offset = 0x1c, 291 .channel_offset = 0x1c,
295 .timer_bit = 2, 292 .timer_bit = 2,
296 .clk = "tmu0",
297}; 293};
298 294
299static struct resource tmu2_resources[] = { 295static struct resource tmu2_resources[] = {