diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/powerpc/include/asm/exception-64e.h | 201 | ||||
-rw-r--r-- | arch/powerpc/include/asm/reg.h | 19 |
2 files changed, 220 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/exception-64e.h b/arch/powerpc/include/asm/exception-64e.h new file mode 100644 index 000000000000..94cb3d79d125 --- /dev/null +++ b/arch/powerpc/include/asm/exception-64e.h | |||
@@ -0,0 +1,201 @@ | |||
1 | /* | ||
2 | * Definitions for use by exception code on Book3-E | ||
3 | * | ||
4 | * Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or | ||
7 | * modify it under the terms of the GNU General Public License | ||
8 | * as published by the Free Software Foundation; either version | ||
9 | * 2 of the License, or (at your option) any later version. | ||
10 | */ | ||
11 | #ifndef _ASM_POWERPC_EXCEPTION_64E_H | ||
12 | #define _ASM_POWERPC_EXCEPTION_64E_H | ||
13 | |||
14 | /* | ||
15 | * SPRGs usage an other considerations... | ||
16 | * | ||
17 | * Since TLB miss and other standard exceptions can be interrupted by | ||
18 | * critical exceptions which can themselves be interrupted by machine | ||
19 | * checks, and since the two later can themselves cause a TLB miss when | ||
20 | * hitting the linear mapping for the kernel stacks, we need to be a bit | ||
21 | * creative on how we use SPRGs. | ||
22 | * | ||
23 | * The base idea is that we have one SRPG reserved for critical and one | ||
24 | * for machine check interrupts. Those are used to save a GPR that can | ||
25 | * then be used to get the PACA, and store as much context as we need | ||
26 | * to save in there. That includes saving the SPRGs used by the TLB miss | ||
27 | * handler for linear mapping misses and the associated SRR0/1 due to | ||
28 | * the above re-entrancy issue. | ||
29 | * | ||
30 | * So here's the current usage pattern. It's done regardless of which | ||
31 | * SPRGs are user-readable though, thus we might have to change some of | ||
32 | * this later. In order to do that more easily, we use special constants | ||
33 | * for naming them | ||
34 | * | ||
35 | * WARNING: Some of these SPRGs are user readable. We need to do something | ||
36 | * about it as some point by making sure they can't be used to leak kernel | ||
37 | * critical data | ||
38 | */ | ||
39 | |||
40 | |||
41 | /* We are out of SPRGs so we save some things in the PACA. The normal | ||
42 | * exception frame is smaller than the CRIT or MC one though | ||
43 | */ | ||
44 | #define EX_R1 (0 * 8) | ||
45 | #define EX_CR (1 * 8) | ||
46 | #define EX_R10 (2 * 8) | ||
47 | #define EX_R11 (3 * 8) | ||
48 | #define EX_R14 (4 * 8) | ||
49 | #define EX_R15 (5 * 8) | ||
50 | |||
51 | /* The TLB miss exception uses different slots */ | ||
52 | |||
53 | #define EX_TLB_R10 ( 0 * 8) | ||
54 | #define EX_TLB_R11 ( 1 * 8) | ||
55 | #define EX_TLB_R12 ( 2 * 8) | ||
56 | #define EX_TLB_R13 ( 3 * 8) | ||
57 | #define EX_TLB_R14 ( 4 * 8) | ||
58 | #define EX_TLB_R15 ( 5 * 8) | ||
59 | #define EX_TLB_R16 ( 6 * 8) | ||
60 | #define EX_TLB_CR ( 7 * 8) | ||
61 | #define EX_TLB_DEAR ( 8 * 8) /* Level 0 and 2 only */ | ||
62 | #define EX_TLB_ESR ( 9 * 8) /* Level 0 and 2 only */ | ||
63 | #define EX_TLB_SRR0 (10 * 8) | ||
64 | #define EX_TLB_SRR1 (11 * 8) | ||
65 | #define EX_TLB_MMUCR0 (12 * 8) /* Level 0 */ | ||
66 | #define EX_TLB_MAS1 (12 * 8) /* Level 0 */ | ||
67 | #define EX_TLB_MAS2 (13 * 8) /* Level 0 */ | ||
68 | #ifdef CONFIG_BOOK3E_MMU_TLB_STATS | ||
69 | #define EX_TLB_R8 (14 * 8) | ||
70 | #define EX_TLB_R9 (15 * 8) | ||
71 | #define EX_TLB_LR (16 * 8) | ||
72 | #define EX_TLB_SIZE (17 * 8) | ||
73 | #else | ||
74 | #define EX_TLB_SIZE (14 * 8) | ||
75 | #endif | ||
76 | |||
77 | #define START_EXCEPTION(label) \ | ||
78 | .globl exc_##label##_book3e; \ | ||
79 | exc_##label##_book3e: | ||
80 | |||
81 | /* TLB miss exception prolog | ||
82 | * | ||
83 | * This prolog handles re-entrancy (up to 3 levels supported in the PACA | ||
84 | * though we currently don't test for overflow). It provides you with a | ||
85 | * re-entrancy safe working space of r10...r16 and CR with r12 being used | ||
86 | * as the exception area pointer in the PACA for that level of re-entrancy | ||
87 | * and r13 containing the PACA pointer. | ||
88 | * | ||
89 | * SRR0 and SRR1 are saved, but DEAR and ESR are not, since they don't apply | ||
90 | * as-is for instruction exceptions. It's up to the actual exception code | ||
91 | * to save them as well if required. | ||
92 | */ | ||
93 | #define TLB_MISS_PROLOG \ | ||
94 | mtspr SPRN_SPRG_TLB_SCRATCH,r12; \ | ||
95 | mfspr r12,SPRN_SPRG_TLB_EXFRAME; \ | ||
96 | std r10,EX_TLB_R10(r12); \ | ||
97 | mfcr r10; \ | ||
98 | std r11,EX_TLB_R11(r12); \ | ||
99 | mfspr r11,SPRN_SPRG_TLB_SCRATCH; \ | ||
100 | std r13,EX_TLB_R13(r12); \ | ||
101 | mfspr r13,SPRN_SPRG_PACA; \ | ||
102 | std r14,EX_TLB_R14(r12); \ | ||
103 | addi r14,r12,EX_TLB_SIZE; \ | ||
104 | std r15,EX_TLB_R15(r12); \ | ||
105 | mfspr r15,SPRN_SRR1; \ | ||
106 | std r16,EX_TLB_R16(r12); \ | ||
107 | mfspr r16,SPRN_SRR0; \ | ||
108 | std r10,EX_TLB_CR(r12); \ | ||
109 | std r11,EX_TLB_R12(r12); \ | ||
110 | mtspr SPRN_SPRG_TLB_EXFRAME,r14; \ | ||
111 | std r15,EX_TLB_SRR1(r12); \ | ||
112 | std r16,EX_TLB_SRR0(r12); \ | ||
113 | TLB_MISS_PROLOG_STATS | ||
114 | |||
115 | /* And these are the matching epilogs that restores things | ||
116 | * | ||
117 | * There are 3 epilogs: | ||
118 | * | ||
119 | * - SUCCESS : Unwinds one level | ||
120 | * - ERROR : restore from level 0 and reset | ||
121 | * - ERROR_SPECIAL : restore from current level and reset | ||
122 | * | ||
123 | * Normal errors use ERROR, that is, they restore the initial fault context | ||
124 | * and trigger a fault. However, there is a special case for linear mapping | ||
125 | * errors. Those should basically never happen, but if they do happen, we | ||
126 | * want the error to point out the context that did that linear mapping | ||
127 | * fault, not the initial level 0 (basically, we got a bogus PGF or something | ||
128 | * like that). For userland errors on the linear mapping, there is no | ||
129 | * difference since those are always level 0 anyway | ||
130 | */ | ||
131 | |||
132 | #define TLB_MISS_RESTORE(freg) \ | ||
133 | ld r14,EX_TLB_CR(r12); \ | ||
134 | ld r10,EX_TLB_R10(r12); \ | ||
135 | ld r15,EX_TLB_SRR0(r12); \ | ||
136 | ld r16,EX_TLB_SRR1(r12); \ | ||
137 | mtspr SPRN_SPRG_TLB_EXFRAME,freg; \ | ||
138 | ld r11,EX_TLB_R11(r12); \ | ||
139 | mtcr r14; \ | ||
140 | ld r13,EX_TLB_R13(r12); \ | ||
141 | ld r14,EX_TLB_R14(r12); \ | ||
142 | mtspr SPRN_SRR0,r15; \ | ||
143 | ld r15,EX_TLB_R15(r12); \ | ||
144 | mtspr SPRN_SRR1,r16; \ | ||
145 | TLB_MISS_RESTORE_STATS \ | ||
146 | ld r16,EX_TLB_R16(r12); \ | ||
147 | ld r12,EX_TLB_R12(r12); \ | ||
148 | |||
149 | #define TLB_MISS_EPILOG_SUCCESS \ | ||
150 | TLB_MISS_RESTORE(r12) | ||
151 | |||
152 | #define TLB_MISS_EPILOG_ERROR \ | ||
153 | addi r12,r13,PACA_EXTLB; \ | ||
154 | TLB_MISS_RESTORE(r12) | ||
155 | |||
156 | #define TLB_MISS_EPILOG_ERROR_SPECIAL \ | ||
157 | addi r11,r13,PACA_EXTLB; \ | ||
158 | TLB_MISS_RESTORE(r11) | ||
159 | |||
160 | #ifdef CONFIG_BOOK3E_MMU_TLB_STATS | ||
161 | #define TLB_MISS_PROLOG_STATS \ | ||
162 | mflr r10; \ | ||
163 | std r8,EX_TLB_R8(r12); \ | ||
164 | std r9,EX_TLB_R9(r12); \ | ||
165 | std r10,EX_TLB_LR(r12); | ||
166 | #define TLB_MISS_RESTORE_STATS \ | ||
167 | ld r16,EX_TLB_LR(r12); \ | ||
168 | ld r9,EX_TLB_R9(r12); \ | ||
169 | ld r8,EX_TLB_R8(r12); \ | ||
170 | mtlr r16; | ||
171 | #define TLB_MISS_STATS_D(name) \ | ||
172 | addi r9,r13,MMSTAT_DSTATS+name; \ | ||
173 | bl .tlb_stat_inc; | ||
174 | #define TLB_MISS_STATS_I(name) \ | ||
175 | addi r9,r13,MMSTAT_ISTATS+name; \ | ||
176 | bl .tlb_stat_inc; | ||
177 | #define TLB_MISS_STATS_X(name) \ | ||
178 | ld r8,PACA_EXTLB+EX_TLB_ESR(r13); \ | ||
179 | cmpdi cr2,r8,-1; \ | ||
180 | beq cr2,61f; \ | ||
181 | addi r9,r13,MMSTAT_DSTATS+name; \ | ||
182 | b 62f; \ | ||
183 | 61: addi r9,r13,MMSTAT_ISTATS+name; \ | ||
184 | 62: bl .tlb_stat_inc; | ||
185 | #define TLB_MISS_STATS_SAVE_INFO \ | ||
186 | std r14,EX_TLB_ESR(r12); /* save ESR */ \ | ||
187 | |||
188 | |||
189 | #else | ||
190 | #define TLB_MISS_PROLOG_STATS | ||
191 | #define TLB_MISS_RESTORE_STATS | ||
192 | #define TLB_MISS_STATS_D(name) | ||
193 | #define TLB_MISS_STATS_I(name) | ||
194 | #define TLB_MISS_STATS_X(name) | ||
195 | #define TLB_MISS_STATS_Y(name) | ||
196 | #define TLB_MISS_STATS_SAVE_INFO | ||
197 | #endif | ||
198 | |||
199 | |||
200 | #endif /* _ASM_POWERPC_EXCEPTION_64E_H */ | ||
201 | |||
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index c8715331e1b0..6315edc205d8 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h | |||
@@ -652,6 +652,16 @@ | |||
652 | * - SPRG2 scratch for exception vectors | 652 | * - SPRG2 scratch for exception vectors |
653 | * - SPRG3 unused (user visible) | 653 | * - SPRG3 unused (user visible) |
654 | * | 654 | * |
655 | * 64-bit embedded | ||
656 | * - SPRG0 generic exception scratch | ||
657 | * - SPRG2 TLB exception stack | ||
658 | * - SPRG3 unused (user visible) | ||
659 | * - SPRG4 unused (user visible) | ||
660 | * - SPRG6 TLB miss scratch (user visible, sorry !) | ||
661 | * - SPRG7 critical exception scratch | ||
662 | * - SPRG8 machine check exception scratch | ||
663 | * - SPRG9 debug exception scratch | ||
664 | * | ||
655 | * All 32-bit: | 665 | * All 32-bit: |
656 | * - SPRG3 current thread_info pointer | 666 | * - SPRG3 current thread_info pointer |
657 | * (virtual on BookE, physical on others) | 667 | * (virtual on BookE, physical on others) |
@@ -705,6 +715,15 @@ | |||
705 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 | 715 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG2 |
706 | #endif | 716 | #endif |
707 | 717 | ||
718 | #ifdef CONFIG_PPC_BOOK3E_64 | ||
719 | #define SPRN_SPRG_MC_SCRATCH SPRN_SPRG8 | ||
720 | #define SPRN_SPRG_CRIT_SCRATCH SPRN_SPRG7 | ||
721 | #define SPRN_SPRG_DBG_SCRATCH SPRN_SPRG9 | ||
722 | #define SPRN_SPRG_TLB_EXFRAME SPRN_SPRG2 | ||
723 | #define SPRN_SPRG_TLB_SCRATCH SPRN_SPRG6 | ||
724 | #define SPRN_SPRG_GEN_SCRATCH SPRN_SPRG0 | ||
725 | #endif | ||
726 | |||
708 | #ifdef CONFIG_PPC_BOOK3S_32 | 727 | #ifdef CONFIG_PPC_BOOK3S_32 |
709 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 | 728 | #define SPRN_SPRG_SCRATCH0 SPRN_SPRG0 |
710 | #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 | 729 | #define SPRN_SPRG_SCRATCH1 SPRN_SPRG1 |