234 files changed, 11814 insertions, 3489 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ba1ac08b4e02..e39caa8b0c93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -303,6 +303,7 @@ config ARCH_CNS3XXX
         select CPU_V6
         select GENERIC_CLOCKEVENTS
         select ARM_GIC
+        select PCI_DOMAINS if PCI
         help
           Support for Cavium Networks CNS3XXX platform.
 
@@ -469,6 +470,19 @@ config ARCH_LOKI
         help
           Support for the Marvell Loki (88RC8480) SoC.
 
+config ARCH_LPC32XX
+        bool "NXP LPC32XX"
+        select CPU_ARM926T
+        select ARCH_REQUIRE_GPIOLIB
+        select HAVE_IDE
+        select ARM_AMBA
+        select USB_ARCH_HAS_OHCI
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        help
+          Support for the NXP LPC32XX family of processors
+
 config ARCH_MV78XX0
         bool "Marvell MV78xx0"
         select CPU_FEROCEON
@@ -573,6 +587,7 @@ config ARCH_MSM
         bool "Qualcomm MSM"
         select HAVE_CLK
         select GENERIC_CLOCKEVENTS
+        select ARCH_REQUIRE_GPIOLIB
         help
           Support for Qualcomm MSM/QSD based systems.  This runs on the
           apps processor of the MSM/QSD and depends on a shared memory
@@ -831,6 +846,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
 
 source "arch/arm/mach-loki/Kconfig"
 
+source "arch/arm/mach-lpc32xx/Kconfig"
+
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
@@ -1041,7 +1058,7 @@ config ISA_DMA_API
         bool
 
 config PCI
-        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+        bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
         help
           Find out whether you have a PCI motherboard. PCI is the name of a
           bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1372,6 +1389,24 @@ config UACCESS_WITH_MEMCPY
           However, if the CPU data cache is using a write-allocate mode,
           this option is unlikely to provide any performance gain.
 
+config CC_STACKPROTECTOR
+        bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+        help
+          This option turns on the -fstack-protector GCC feature. This
+          feature puts, at the beginning of functions, a canary value on
+          the stack just before the return address, and validates
+          the value just before actually returning.  Stack based buffer
+          overflows (that need to overwrite this return address) now also
+          overwrite the canary, which gets detected and the attack is then
+          neutralized via a kernel panic.
+          This feature requires gcc version 4.2 or above.
+
+config DEPRECATED_PARAM_STRUCT
+        bool "Provide old way to pass kernel parameters"
+        help
+          This was deprecated in 2001 and announced to live on for 5 years.
+          Some old boot loaders still use this way.
+
 endmenu
 
 menu "Boot options"
@@ -1482,6 +1517,105 @@ config ATAGS_PROC
           Should the atags used to boot the kernel be exported in an "atags"
           file in procfs. Useful with kexec.
 
+config AUTO_ZRELADDR
+        bool "Auto calculation of the decompressed kernel image address"
+        depends on !ZBOOT_ROM && !ARCH_U300
+        help
+          ZRELADDR is the physical address where the decompressed kernel
+          image will be placed. If AUTO_ZRELADDR is selected, the address
+          will be determined at run-time by masking the current IP with
+          0xf8000000. This assumes the zImage being placed in the first 128MB
+          from start of memory.
+
+config ZRELADDR
+        hex "Physical address of the decompressed kernel image"
+        depends on !AUTO_ZRELADDR
+        default 0x00008000 if ARCH_BCMRING ||\
+                ARCH_CNS3XXX ||\
+                ARCH_DOVE ||\
+                ARCH_EBSA110 ||\
+                ARCH_FOOTBRIDGE ||\
+                ARCH_INTEGRATOR ||\
+                ARCH_IOP13XX ||\
+                ARCH_IOP33X ||\
+                ARCH_IXP2000 ||\
+                ARCH_IXP23XX ||\
+                ARCH_IXP4XX ||\
+                ARCH_KIRKWOOD ||\
+                ARCH_KS8695 ||\
+                ARCH_LOKI ||\
+                ARCH_MMP ||\
+                ARCH_MV78XX0 ||\
+                ARCH_NOMADIK ||\
+                ARCH_NUC93X ||\
+                ARCH_NS9XXX ||\
+                ARCH_ORION5X ||\
+                ARCH_SPEAR3XX ||\
+                ARCH_SPEAR6XX ||\
+                ARCH_U8500 ||\
+                ARCH_VERSATILE ||\
+                ARCH_W90X900
+        default 0x08008000 if ARCH_MX1 ||\
+                ARCH_SHARK
+        default 0x10008000 if ARCH_MSM ||\
+                ARCH_OMAP1 ||\
+                ARCH_RPC
+        default 0x20008000 if ARCH_S5P6440 ||\
+                ARCH_S5P6442 ||\
+                ARCH_S5PC100 ||\
+                ARCH_S5PV210
+        default 0x30008000 if ARCH_S3C2410 ||\
+                ARCH_S3C2400 ||\
+                ARCH_S3C2412 ||\
+                ARCH_S3C2416 ||\
+                ARCH_S3C2440 ||\
+                ARCH_S3C2443
+        default 0x40008000 if ARCH_STMP378X ||\
+                ARCH_STMP37XX ||\
+                ARCH_SH7372 ||\
+                ARCH_SH7377
+        default 0x50008000 if ARCH_S3C64XX ||\
+                ARCH_SH7367
+        default 0x60008000 if ARCH_VEXPRESS
+        default 0x80008000 if ARCH_MX25 ||\
+                ARCH_MX3 ||\
+                ARCH_NETX ||\
+                ARCH_OMAP2PLUS ||\
+                ARCH_PNX4008
+        default 0x90008000 if ARCH_MX5 ||\
+                ARCH_MX91231
+        default 0xa0008000 if ARCH_IOP32X ||\
+                ARCH_PXA ||\
+                MACH_MX27
+        default 0xc0008000 if ARCH_LH7A40X ||\
+                MACH_MX21
+        default 0xf0008000 if ARCH_AAEC2000 ||\
+                ARCH_L7200
+        default 0xc0028000 if ARCH_CLPS711X
+        default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+        default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+        default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
+        default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
+        default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
+        default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
+        default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
+        default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
+        default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
+        default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
+        default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
+        default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
+        default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
+        default 0xc0208000 if ARCH_SA1100 && SA1111
+        default 0xc0008000 if ARCH_SA1100 && !SA1111
+        default 0x30108000 if ARCH_S3C2410 && PM_H1940
+        default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
+        default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
+        help
+          ZRELADDR is the physical address where the decompressed kernel
+          image will be placed. ZRELADDR has to be specified when the
+          assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
+          selected.
+
 endmenu
 
 menu "CPU Power Management"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index bea37a2512e7..63d998e8c672 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS   +=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
+ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
+KBUILD_CFLAGS   +=-fstack-protector
+endif
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS += -mbig-endian
 AS              += -EB
@@ -141,11 +145,12 @@ machine-$(CONFIG_ARCH_KIRKWOOD)		:= kirkwood
 machine-$(CONFIG_ARCH_KS8695)           := ks8695
 machine-$(CONFIG_ARCH_LH7A40X)          := lh7a40x
 machine-$(CONFIG_ARCH_LOKI)             := loki
+machine-$(CONFIG_ARCH_LPC32XX)          := lpc32xx
 machine-$(CONFIG_ARCH_MMP)              := mmp
 machine-$(CONFIG_ARCH_MSM)              := msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
-machine-$(CONFIG_ARCH_MX1)              := mx1
-machine-$(CONFIG_ARCH_MX2)              := mx2
+machine-$(CONFIG_ARCH_MX1)              := imx
+machine-$(CONFIG_ARCH_MX2)              := imx
 machine-$(CONFIG_ARCH_MX25)             := mx25
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_MX5)              := mx5
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4113e2..f705213caa88 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,18 +14,16 @@
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
+-include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+export INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 7a29301d516b..c2225fea3535 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,7 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD    = head.o
 OBJS    = misc.o decompress.o
 FONTC   = $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -75,19 +76,9 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
-# machine class defined the corresponding makefile variable.
-LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
-ifneq ($(PARAMS_PHYS),)
-LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644
index 491a037b2973..000000000000
--- a/arch/arm/boot/compressed/Makefile.debug
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# linux/arch/arm/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-COMPRESSED_EXTRA=../../lib/ll_char_wr.o
-OBJECTS=misc-debug.o ll_char_wr.aout.o
-
-CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
-
-test-gzip: piggy.aout.o $(OBJECTS)
-        $(CC) -o $@ $(OBJECTS) piggy.aout.o
-
-misc-debug.o: misc.c
-        $(CC) $(CFLAGS) -o $@ misc.c
-
-piggy.aout.o: piggy.o
-        arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
-
-ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
-        arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
-
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1532e8..abf4d65acf62 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
 
                 .text
                 adr     r0, LC0
- ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, r11, ip}   )
+ ARM(           ldmia   r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(         ldmia   r0, {r1, r2, r3, r5, r6, r11, ip}       )
  THUMB(         ldr     sp, [r0, #32]                           )
+#ifdef CONFIG_AUTO_ZRELADDR
+                @ determine final kernel image address
+                and     r4, pc, #0xf8000000
+                add     r4, r4, #TEXT_OFFSET
+#else
+                ldr     r4, =CONFIG_ZRELADDR
+#endif
                 subs    r0, r0, r1              @ calculate the delta offset
 
                                                 @ if delta is zero, we are
@@ -310,18 +317,17 @@ wont_overwrite:	mov	r0, r4
 LC0:            .word   LC0                     @ r1
                 .word   __bss_start             @ r2
                 .word   _end                    @ r3
-                .word   zreladdr                @ r4
                 .word   _start                  @ r5
                 .word   _image_size             @ r6
                 .word   _got_start              @ r11
                 .word   _got_end                @ ip
-                .word   user_stack+4096         @ sp
+                .word   user_stack_end          @ sp
 LC1:            .word   reloc_end - reloc_start
                 .size   LC0, . - LC0
 
 #ifdef CONFIG_ARCH_RPC
                 .globl  params
-params:         ldr     r0, =params_phys
+params:         ldr     r0, =0x10000100         @ params_phys for RPC
                 mov     pc, lr
                 .ltorg
                 .align
@@ -339,9 +345,8 @@ params:		ldr	r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -396,12 +401,18 @@ __armv3_mpu_cache_on:
 
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                /*
+                 * ?? ARMv3 MMU does not allow reading the control register,
+                 * does this really work on ARMv3 MPU?
+                 */
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                                                 @ .... .... .... WC.M
                 orr     r0, r0, #0x000d         @ .... .... .... 11.1
+                /* ?? this overwrites the value constructed above? */
                 mov     r0, #0
                 mcr     p15, 0, r0, c1, c0, 0   @ write control reg
 
+                /* ?? invalidate for the second time? */
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
@@ -771,8 +782,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
                 .align  5
 cache_off:      mov     r3, #12                 @ cache_off function
@@ -845,7 +858,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
@@ -988,7 +1001,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
                 mov     r1, #0
-                mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
+                mcr     p15, 0, r1, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
 
 /*
@@ -1001,6 +1014,7 @@ __armv3_mpu_cache_flush:
 phexbuf:        .space  12
                 .size   phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:           adr     r3, phexbuf
                 mov     r2, #0
                 strb    r2, [r3, r1]
@@ -1015,6 +1029,7 @@ phex:		adr	r3, phexbuf
                 strb    r2, [r3, r1]
                 b       1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:           loadsp  r3, r1
 1:              ldrb    r2, [r0], #1
                 teq     r2, #0
@@ -1029,12 +1044,14 @@ puts:		loadsp	r3, r1
                 teq     r0, #0
                 bne     1b
                 mov     pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
                 mov     r2, r0
                 mov     r0, #0
                 loadsp  r3, r1
                 b       2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:        mov     r12, r0
                 mov     r10, lr
                 mov     r11, #0
@@ -1070,3 +1087,4 @@ reloc_end:
                 .align
                 .section ".stack", "w"
 user_stack:     .space  4096
+user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index d2b2ef41cd4f..e653a6d3c8d9 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/unaligned.h>
 
-#ifdef STANDALONE_DEBUG
-#define putstr printf
-#else
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
         flush();
 }
 
-#endif
 
 void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
 
 extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
-#ifndef STANDALONE_DEBUG
 
 unsigned long
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
         putstr(" done, booting the kernel.\n");
         return output_ptr;
 }
-#else
-
-char output_buffer[1500*1024];
-
-int main()
-{
-        output_data = output_buffer;
-
-        putstr("Uncompressing Linux...");
-        decompress(input_data, input_data_end - input_data,
-                        NULL, NULL, output_data, NULL, error);
-        putstr("done.\n");
-        return 0;
-}
-#endif
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index f2e3a9088df6..ccc9c9959b82 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -13,11 +13,19 @@ CONFIG_MACH_RD88F6192_NAS=y
 CONFIG_MACH_RD88F6281=y
 CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662feb9f1d..6750b8e45a49 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,8 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 extern void elf_set_personality(const struct elf32_hdr *);
 #define SET_PERSONALITY(ex)     elf_set_personality(&(ex))
 
+struct mm_struct;
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1e97df..16330bd0657c 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
                                         /* IRQ mapping                          */
         int             (*map_irq)(struct pci_dev *, u8, u8);
         struct hw_pci   *hw;
+        void            *private_data;  /* platform controller private data     */
 };
 
 /*
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644
index 000000000000..de003327be97
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
+/*
+ * GCC stack protector support.
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on ARM.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+        unsigned long canary;
+
+        /* Try to get a semi random initial value. */
+        get_random_bytes(&canary, sizeof(canary));
+        canary ^= LINUX_VERSION_CODE;
+
+        current->stack_canary = canary;
+        __stack_chk_guard = current->stack_canary;
+}
+
+#endif  /* _ASM_STACKPROTECTOR_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index ea023c6aa31e..980b78e31328 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y           := compat.o elf.o entry-armv.o entry-common.o irq.o \
+obj-y           := elf.o entry-armv.o entry-common.o irq.o \
                    process.o ptrace.o return_address.o setup.o signal.o \
                    sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+
 obj-$(CONFIG_LEDS)              += leds.o
 obj-$(CONFIG_OC_ETM)            += etm.o
 
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 883511522fca..85f2a019f77b 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
 int main(void)
 {
   DEFINE(TSK_ACTIVE_MM,         offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_CC_STACKPROTECTOR
+  DEFINE(TSK_STACK_CANARY,      offsetof(struct task_struct, stack_canary));
+#endif
   BLANK();
   DEFINE(TI_FLAGS,              offsetof(struct thread_info, flags));
   DEFINE(TI_PREEMPT,            offsetof(struct thread_info, preempt_count));
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
index 0a1385442f43..925652318b8b 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/compat.c
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
         struct param_struct *params = (struct param_struct *)tags;
         build_tag_list(params, &params->u2);
 }
-
-void __init squash_mem_tags(struct tag *tag)
-{
-        for (; tag->hdr.size; tag = tag_next(tag))
-                if (tag->hdr.tag == ATAG_MEM)
-                        tag->hdr.tag = ATAG_NONE;
-}
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
index 27e61a68bd1c..39264ab1b9c6 100644
--- a/arch/arm/kernel/compat.h
+++ b/arch/arm/kernel/compat.h
@@ -9,5 +9,3 @@
 */
 
 extern void convert_to_tag_list(struct tag *tags);
-
-extern void squash_mem_tags(struct tag *tag);
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index e864e482118a..bb8e93a76407 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -737,6 +737,11 @@ ENTRY(__switch_to)
         ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
         set_tls r3, r4, r5
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+        ldr     r7, [r2, #TI_TASK]
+        ldr     r8, =__stack_chk_guard
+        ldr     r7, [r7, #TSK_STACK_CANARY]
+#endif
 #ifdef CONFIG_MMU
         mcr     p15, 0, r6, c3, c0, 0           @ Set domain register
 #endif
@@ -745,6 +750,9 @@ ENTRY(__switch_to)
         ldr     r0, =thread_notify_head
         mov     r1, #THREAD_NOTIFY_SWITCH
         bl      atomic_notifier_call_chain
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+        str     r7, [r8]
+#endif
  THUMB( mov     ip, r4                     )
         mov     r0, r5
  ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 2e2ec97cc50c..401e38be1f78 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,6 +28,7 @@
 #include <linux/tick.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
+#include <linux/random.h>
 
 #include <asm/cacheflush.h>
 #include <asm/leds.h>
@@ -37,6 +38,12 @@
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 static const char *processor_modes[] = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
@@ -445,3 +452,9 @@ unsigned long get_wchan(struct task_struct *p)
         } while (count ++ < 16);
         return 0;
 }
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+        unsigned long range_end = mm->brk + 0x02000000;
+        return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
+}
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 776ea1aa974b..d5231ae7355a 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -47,7 +47,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
+#endif
 #include "atags.h"
 #include "tcm.h"
 
@@ -755,6 +757,13 @@ static int __init setup_elfcorehdr(char *arg)
 early_param("elfcorehdr", setup_elfcorehdr);
 #endif /* CONFIG_CRASH_DUMP */
 
+static void __init squash_mem_tags(struct tag *tag)
+{
+        for (; tag->hdr.size; tag = tag_next(tag))
+                if (tag->hdr.tag == ATAG_MEM)
+                        tag->hdr.tag = ATAG_NONE;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
         struct tag *tags = (struct tag *)&init_tags;
@@ -775,12 +784,14 @@ void __init setup_arch(char **cmdline_p)
         else if (mdesc->boot_params)
                 tags = phys_to_virt(mdesc->boot_params);
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
         /*
          * If we have the old style parameters, convert them to
          * a tag list.
          */
         if (tags->hdr.tag != ATAG_CORE)
                 convert_to_tag_list(tags);
+#endif
         if (tags->hdr.tag != ATAG_CORE)
                 tags = (struct tag *)&init_tags;
 
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a2d696..11033f1c2e23 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)              += core.o pm.o devices.o
+obj-$(CONFIG_PCI)                       += pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)            += cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c8288740..9df8391fd78a 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -117,6 +118,9 @@ static void __init cns3420_init(void)
 {
         platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+        cns3xxx_ahci_init();
+        cns3xxx_sdhci_init();
+
         pm_power_off = cns3xxx_power_off;
 }
 
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 000000000000..50b4d31c27c0
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,111 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *                Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "devices.h"
+
+/*
+ * AHCI
+ */
+static struct resource cns3xxx_ahci_resource[] = {
+        [0] = {
+                .start  = CNS3XXX_SATA2_BASE,
+                .end    = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_CNS3XXX_SATA,
+                .end    = IRQ_CNS3XXX_SATA,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_ahci_pdev = {
+        .name           = "ahci",
+        .id             = 0,
+        .resource       = cns3xxx_ahci_resource,
+        .num_resources  = ARRAY_SIZE(cns3xxx_ahci_resource),
+        .dev            = {
+                .dma_mask               = &cns3xxx_ahci_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+};
+
+void __init cns3xxx_ahci_init(void)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(MISC_SATA_POWER_MODE);
+        tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+        tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+        __raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+        /* Enable SATA PHY */
+        cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+        cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+        /* Enable SATA Clock */
+        cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+        /* De-Asscer SATA Reset */
+        cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+
+        platform_device_register(&cns3xxx_ahci_pdev);
+}
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+        [0] = {
+                .start = CNS3XXX_SDIO_BASE,
+                .end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_CNS3XXX_SDIO,
+                .end   = IRQ_CNS3XXX_SDIO,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cns3xxx_sdhci_pdev = {
+        .name           = "sdhci-cns3xxx",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(cns3xxx_sdhci_resources),
+        .resource       = cns3xxx_sdhci_resources,
+};
+
+void __init cns3xxx_sdhci_init(void)
+{
+        u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+        u32 gpioa_pins = __raw_readl(gpioa);
+
+        /* MMC/SD pins share with GPIOA */
+        gpioa_pins |= 0x1fff0004;
+        __raw_writel(gpioa_pins, gpioa);
+
+        cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+        cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+        platform_device_register(&cns3xxx_sdhci_pdev);
+}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 000000000000..27e15a10aa85
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,20 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *                Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_ahci_init(void);
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */
diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a21d4ee..6dbce13771ca 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG                   MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG                    MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG               MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG          MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG          MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG               MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A       MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B       MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG           MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG          MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG                   MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG                    MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG                   MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG                   MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG                  MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG                MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG                MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE                    MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG                        MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG                        MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG                   MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG                   MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG                   MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG                   MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG                   MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG                    MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG               MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG          MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG          MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG               MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG               MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A       MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B       MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG           MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG          MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG           MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG          MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG                   MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG                    MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG                   MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG                   MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG                  MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG                MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG                MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE                    MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG                        MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG                        MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG                   MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG                   MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG                   MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG                   MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)                   MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)                     MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG                                 PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG                                 PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG                                   PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG                              PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG                                  PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG                                 PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG                         PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG                           PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG                             PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG                                 PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG                                 PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG                                 PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG                                      PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG                                 PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG                                 PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG                                   PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG                              PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG                                  PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG                                 PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG                         PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG                           PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG                             PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG                                 PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG                                 PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG                                 PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG                                      PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO                     (25)
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 000000000000..38088c36936c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *                Richard Liu <richard.liu@caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *                Anton Vorontsov <avorontsov@mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <asm/mach/map.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+        CNS3XXX_HOST_TYPE = 0,
+        CNS3XXX_CFG0_TYPE,
+        CNS3XXX_CFG1_TYPE,
+        CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+        struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+        unsigned int irqs[2];
+        struct resource res_io;
+        struct resource res_mem;
+        struct hw_pci hw_pci;
+
+        bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+        struct pci_sys_data *root = sysdata;
+
+        return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+        return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+        return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+                                  unsigned int devfn, int where)
+{
+        struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+        int busno = bus->number;
+        int slot = PCI_SLOT(devfn);
+        int offset;
+        enum cns3xxx_access_type type;
+        void __iomem *base;
+
+        /* If there is no link, just show the CNS PCI bridge. */
+        if (!cnspci->linked && (busno > 0 || slot > 0))
+                return NULL;
+
+        /*
+         * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+         * we still want to access it. For this to work, we must place
+         * the first device on the same bus as the CNS PCI bridge.
+         */
+        if (busno == 0) {
+                if (slot > 1)
+                        return NULL;
+                type = slot;
+        } else {
+                type = CNS3XXX_CFG1_TYPE;
+        }
+
+        base = (void __iomem *)cnspci->cfg_bases[type].virtual;
+        offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+        return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+                                   int where, int size, u32 *val)
+{
+        u32 v;
+        void __iomem *base;
+        u32 mask = (0x1ull << (size * 8)) - 1;
+        int shift = (where % 4) * 8;
+
+        base = cns3xxx_pci_cfg_base(bus, devfn, where);
+        if (!base) {
+                *val = 0xffffffff;
+                return PCIBIOS_SUCCESSFUL;
+        }
+
+        v = __raw_readl(base);
+
+        if (bus->number == 0 && devfn == 0 &&
+                        (where & 0xffc) == PCI_CLASS_REVISION) {
+                /*
+                 * RC's class is 0xb, but Linux PCI driver needs 0x604
+                 * for a PCIe bridge. So we must fixup the class code
+                 * to 0x604 here.
+                 */
+                v &= 0xff;
+                v |= 0x604 << 16;
+        }
+
+        *val = (v >> shift) & mask;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+                                    int where, int size, u32 val)
+{
+        u32 v;
+        void __iomem *base;
+        u32 mask = (0x1ull << (size * 8)) - 1;
+        int shift = (where % 4) * 8;
+
+        base = cns3xxx_pci_cfg_base(bus, devfn, where);
+        if (!base)
+                return PCIBIOS_SUCCESSFUL;
+
+        v = __raw_readl(base);
+
+        v &= ~(mask << shift);
+        v |= (val & mask) << shift;
+
+        __raw_writel(v, base);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+        struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+        struct resource *res_io = &cnspci->res_io;
+        struct resource *res_mem = &cnspci->res_mem;
+        struct resource **sysres = sys->resource;
+
+        BUG_ON(request_resource(&iomem_resource, res_io) ||
+               request_resource(&iomem_resource, res_mem));
+
+        sysres[0] = res_io;
+        sysres[1] = res_mem;
+
+        return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+        .read = cns3xxx_pci_read_config,
+        .write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+        int irq = cnspci->irqs[slot];
+
+        pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+                pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+                PCI_FUNC(dev->devfn), slot, pin, irq);
+
+        return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[] = {
+        [0] = {
+                .cfg_bases = {
+                        [CNS3XXX_HOST_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG0_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG1_TYPE] = {
+                                .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                },
+                .res_io = {
+                        .name = "PCIe0 I/O space",
+                        .start = CNS3XXX_PCIE0_IO_BASE,
+                        .end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_IO,
+                },
+                .res_mem = {
+                        .name = "PCIe0 non-prefetchable",
+                        .start = CNS3XXX_PCIE0_MEM_BASE,
+                        .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+                .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+                .hw_pci = {
+                        .domain = 0,
+                        .swizzle = pci_std_swizzle,
+                        .nr_controllers = 1,
+                        .setup = cns3xxx_pci_setup,
+                        .scan = cns3xxx_pci_scan_bus,
+                        .map_irq = cns3xxx_pcie_map_irq,
+                },
+        },
+        [1] = {
+                .cfg_bases = {
+                        [CNS3XXX_HOST_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG0_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                        [CNS3XXX_CFG1_TYPE] = {
+                                .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+                                .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+                                .length = SZ_16M,
+                                .type = MT_DEVICE,
+                        },
+                },
+                .res_io = {
+                        .name = "PCIe1 I/O space",
+                        .start = CNS3XXX_PCIE1_IO_BASE,
+                        .end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_IO,
+                },
+                .res_mem = {
+                        .name = "PCIe1 non-prefetchable",
+                        .start = CNS3XXX_PCIE1_MEM_BASE,
+                        .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+                        .flags = IORESOURCE_MEM,
+                },
+                .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+                .hw_pci = {
+                        .domain = 1,
+                        .swizzle = pci_std_swizzle,
+                        .nr_controllers = 1,
+                        .setup = cns3xxx_pci_setup,
+                        .scan = cns3xxx_pci_scan_bus,
+                        .map_irq = cns3xxx_pcie_map_irq,
+                },
+        },
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+        int port = cnspci->hw_pci.domain;
+        u32 reg;
+        unsigned long time;
+
+        reg = __raw_readl(MISC_PCIE_CTRL(port));
+        /*
+         * Enable Application Request to 1, it will exit L1 automatically,
+         * but when chip back, it will use another clock, still can use 0x1.
+         */
+        reg |= 0x3;
+        __raw_writel(reg, MISC_PCIE_CTRL(port));
+
+        pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+        pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+        time = jiffies;
+        while (1) {
+                reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+                if (reg & 0x1) {
+                        pr_info("Link up.\n");
+                        cnspci->linked = 1;
+                        break;
+                } else if (time_after(jiffies, time + 50)) {
+                        pr_info("Device not found.\n");
+                        break;
+                }
+        }
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+        int port = cnspci->hw_pci.domain;
+        struct pci_sys_data sd = {
+                .domain = port,
+        };
+        struct pci_bus bus = {
+                .number = 0,
+                .ops = &cns3xxx_pcie_ops,
+                .sysdata = &sd,
+        };
+        u32 io_base = cnspci->res_io.start >> 16;
+        u32 mem_base = cnspci->res_mem.start >> 16;
+        u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+        u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+        u32 devfn = 0;
+        u8 tmp8;
+        u16 pos;
+        u16 dc;
+
+        host_base = (__pfn_to_phys(host_base) - 1) >> 16;
+        cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
+
+        pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+        pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+        pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+        pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+        pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+        pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+        pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+        if (!cnspci->linked)
+                return;
+
+        /* Set Device Max_Read_Request_Size to 128 byte */
+        devfn = PCI_DEVFN(1, 0);
+        pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+        pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+        dc &= ~(0x3 << 12);     /* Clear Device Control Register [14:12] */
+        pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+        pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+        if (!(dc & (0x3 << 12)))
+                pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+        /* Disable PCIe0 Interrupt Mask INTA to INTD */
+        __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+                                      struct pt_regs *regs)
+{
+        if (fsr & (1 << 10))
+                regs->ARM_pc += 4;
+        return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+        int i;
+
+        hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+                        "imprecise external abort");
+
+        for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+                iotable_init(cns3xxx_pcie[i].cfg_bases,
+                             ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+                cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+                cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+                cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+                cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+                pci_common_init(&cns3xxx_pcie[i].hw_pci);
+        }
+
+        pci_assign_unassigned_resources();
+
+        return 0;
+}
+device_initcall(cns3xxx_pcie_init);
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4fc231..38e44706feab 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-        PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+        u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+        reg |= (block & PM_CLK_GATE_REG_MASK);
+        __raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-        PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+        u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+        reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+        __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
         /* Wait for 300us for the PLL output clock locked. */
         udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+        u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
         /* write '1' to power down */
-        PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+        reg |= (block & CNS3XXX_PWR_PLL_ALL);
+        __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+        u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
         /*
          * bit 0, 28, 29 => program low to reset,
          * the other else program low and then high
          */
         if (block & 0x30000001) {
-                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+                reg &= ~(block & PM_SOFT_RST_REG_MASK);
         } else {
-                PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-                PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+                reg &= ~(block & PM_SOFT_RST_REG_MASK);
+                reg |= (block & PM_SOFT_RST_REG_MASK);
         }
+
+        __raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+        u32 reg = __raw_readl(PM_CLK_CTRL_REG);
         int cpu;
         int cpu_sel;
         int div_sel;
 
-        cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-        div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+        cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+        div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
         cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
 
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf402c81..f7a12586a1f5 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -752,6 +752,67 @@ void __init dove_xor1_init(void)
         platform_device_register(&dove_xor11_channel);
 }
 
+/*****************************************************************************
+ * SDIO
+ ****************************************************************************/
+static u64 sdio_dmamask = DMA_BIT_MASK(32);
+
+static struct resource dove_sdio0_resources[] = {
+        {
+                .start  = DOVE_SDIO0_PHYS_BASE,
+                .end    = DOVE_SDIO0_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SDIO0,
+                .end    = IRQ_DOVE_SDIO0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dove_sdio0 = {
+        .name           = "sdhci-mv",
+        .id             = 0,
+        .dev            = {
+                .dma_mask               = &sdio_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = dove_sdio0_resources,
+        .num_resources  = ARRAY_SIZE(dove_sdio0_resources),
+};
+
+void __init dove_sdio0_init(void)
+{
+        platform_device_register(&dove_sdio0);
+}
+
+static struct resource dove_sdio1_resources[] = {
+        {
+                .start  = DOVE_SDIO1_PHYS_BASE,
+                .end    = DOVE_SDIO1_PHYS_BASE + 0xff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = IRQ_DOVE_SDIO1,
+                .end    = IRQ_DOVE_SDIO1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device dove_sdio1 = {
+        .name           = "sdhci-mv",
+        .id             = 1,
+        .dev            = {
+                .dma_mask               = &sdio_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = dove_sdio1_resources,
+        .num_resources  = ARRAY_SIZE(dove_sdio1_resources),
+};
+
+void __init dove_sdio1_init(void)
+{
+        platform_device_register(&dove_sdio1);
+}
+
 void __init dove_init(void)
 {
         int tclk;
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index b29e8937de4f..a51517c3fe76 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -36,5 +36,7 @@ void dove_uart3_init(void);
 void dove_spi0_init(void);
 void dove_spi1_init(void);
 void dove_i2c_init(void);
+void dove_sdio0_init(void);
+void dove_sdio1_init(void);
 
 #endif
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index f2971b745224..bef70460fbc6 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -82,6 +82,8 @@ static void __init dove_db_init(void)
         dove_ehci0_init();
         dove_ehci1_init();
         dove_sata_init(&dove_db_sata_data);
+        dove_sdio0_init();
+        dove_sdio1_init();
         dove_spi0_init();
         dove_spi1_init();
         dove_uart0_init();
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig
index 742fd4e6dcb9..c5c0369bb481 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,42 +1,103 @@
+config IMX_HAVE_DMA_V1
+        bool
+
+if ARCH_MX1
+
+config SOC_IMX1
+        select CPU_ARM920T
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
+comment "MX1 platforms:"
+config MACH_MXLADS
+        bool
+
+config ARCH_MX1ADS
+        bool "MX1ADS platform"
+        select MACH_MXLADS
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Say Y here if you are using Motorola MX1ADS/MXLADS boards
+
+config MACH_SCB9328
+        bool "Synertronixx scb9328"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        help
+          Say Y here if you are using a Synertronixx scb9328 board
+
+endif
+
 if ARCH_MX2
 
+config SOC_IMX21
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
+config SOC_IMX27
+        select CPU_ARM926T
+        select ARCH_MXC_AUDMUX_V1
+        select IMX_HAVE_DMA_V1
+        select IMX_HAVE_IOMUX_V1
+        bool
+
 choice
         prompt "CPUs:"
         default MACH_MX21
 
 config MACH_MX21
         bool "i.MX21 support"
-        select ARCH_MXC_AUDMUX_V1
+        select SOC_IMX21
         help
           This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
         bool "i.MX27 support"
-        select ARCH_MXC_AUDMUX_V1
+        select SOC_IMX27
         help
           This enables support for Freescale's MX2 based i.MX27 processor.
 
 endchoice
 
-comment "MX2 platforms:"
+endif
+
+if MACH_MX21
+
+comment "MX21 platforms:"
 
 config MACH_MX21ADS
         bool "MX21ADS platform"
-        depends on MACH_MX21
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for MX21ADS platform. This includes specific
           configurations for the board and its peripherals.
 
+endif
+
+if MACH_MX27
+
+comment "MX27 platforms:"
+
 config MACH_MX27ADS
         bool "MX27ADS platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for MX27ADS platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCM038
         bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -58,7 +119,9 @@ endchoice
 
 config MACH_CPUIMX27
         bool "Eukrea CPUIMX27 module"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for Eukrea CPUIMX27 platform. This includes
           specific configurations for the module and its peripherals.
@@ -67,9 +130,16 @@ config MACH_EUKREA_CPUIMX27_USESDHC2
         bool "CPUIMX27 integrates SDHC2 module"
         depends on MACH_CPUIMX27
         help
-          This adds support for the internal SDHC2 used on CPUIMX27 used
+          This adds support for the internal SDHC2 used on CPUIMX27
           for wifi or eMMC.
 
+config MACH_EUKREA_CPUIMX27_USEUART4
+        bool "CPUIMX27 integrates UART4 module"
+        depends on MACH_CPUIMX27
+        help
+          This adds support for the internal UART4 used on CPUIMX27
+          for bluetooth.
+
 choice
         prompt "Baseboard"
         depends on MACH_CPUIMX27
@@ -78,6 +148,8 @@ choice
 config MACH_EUKREA_MBIMX27_BASEBOARD
         prompt "Eukrea MBIMX27 development board"
         bool
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           This adds board specific devices that can be found on Eukrea's
           MBIMX27 evaluation board.
@@ -86,21 +158,24 @@ endchoice
 
 config MACH_MX27_3DS
         bool "MX27PDK platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX27PDK platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_IMX27LITE
         bool "LogicPD MX27 LITEKIT platform"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for MX27 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
 
 config MACH_PCA100
         bool "Phytec phyCARD-s (pca100)"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for phyCARD-s (aka pca100) platform. This
@@ -108,7 +183,9 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
         bool "Maxtrack i-MXT TD60"
-        depends on MACH_MX27
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         help
           Include support for i-MXT (aka td60) platform. This
           includes specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile
index e3254faac828..46a9fdfbbd15 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,14 +4,24 @@
 
 # Object file lists.
 
-obj-y   :=  devices.o serial.o
+obj-y   :=  devices.o
 
-obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
 
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
-obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
+obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
+
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
+
+# Support for CMOS sensor interface
+obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
+obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index e867398a8fdb..7988a85cf07d 100644
--- a/arch/arm/mach-mx2/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,3 +1,7 @@
+zreladdr-$(CONFIG_ARCH_MX1)     := 0x08008000
+params_phys-$(CONFIG_ARCH_MX1)  := 0x08000100
+initrd_phys-$(CONFIG_ARCH_MX1)  := 0x08800000
+
 zreladdr-$(CONFIG_MACH_MX21)    := 0xC0008000
 params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
 initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-imx/clock-imx1.c
index 6cf2d4a7511d..c05096c38301 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -2,18 +2,17 @@
  *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
 #include <linux/kernel.h>
@@ -29,7 +28,41 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include "crm_regs.h"
+
+#define IO_ADDR_CCM(off)        (MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR        IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0      IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0      IO_ADDR_CCM(0xc)
+#define CCM_PCDR        IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET    29
+#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
+#define CCM_CSCR_USB_OFFSET     26
+#define CCM_CSCR_USB_MASK       (0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT   17
+#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
+#define CCM_CSCR_BCLK_OFFSET    10
+#define CCM_CSCR_BCLK_MASK      (0xf << 10)
+#define CCM_CSCR_PRESC          (1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET   16
+#define CCM_PCDR_PCLK3_MASK     (0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET   4
+#define CCM_PCDR_PCLK2_MASK     (0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET   0
+#define CCM_PCDR_PCLK1_MASK     0xf
+
+#define IO_ADDR_SCM(off)        (MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR        IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
 
 static int _clk_enable(struct clk *clk)
 {
@@ -596,7 +629,8 @@ int __init mx1_clocks_init(unsigned long fref)
         clk_enable(&hclk);
         clk_enable(&fclk);
 
-        mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
+        mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+                        MX1_TIM1_INT);
 
         return 0;
 }
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef4d133..bb419ef4d133 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 0f0823c8b170..5a1aa15c8a16 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
         _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        _REGISTER_CLOCK(NULL, "csi", csi_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
         _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..d8d3b2d84dc5 100644
--- a/arch/arm/mach-mx2/cpu_imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
new file mode 100644
index 000000000000..a8d94f078196
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx1.h>
+#include <mach/devices-common.h>
+
+#define imx1_add_i2c_imx(pdata)         \
+        imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+
+#define imx1_add_imx_uart0(pdata)       \
+        imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
+#define imx1_add_imx_uart1(pdata)       \
+        imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
new file mode 100644
index 000000000000..42788e99d127
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx21.h>
+#include <mach/devices-common.h>
+
+#define imx21_add_i2c_imx(pdata)        \
+        imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+
+#define imx21_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
+#define imx21_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
+#define imx21_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
+#define imx21_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+
+#define imx21_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+
+#define imx21_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
+#define imx21_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
new file mode 100644
index 000000000000..65e7bb7ec2e8
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx27.h>
+#include <mach/devices-common.h>
+
+#define imx27_add_i2c_imx0(pdata)       \
+        imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
+#define imx27_add_i2c_imx1(pdata)       \
+        imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+
+#define imx27_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
+#define imx27_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
+#define imx27_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
+#define imx27_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
+#define imx27_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
+#define imx27_add_imx_uart5(pdata)      \
+        imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+
+#define imx27_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+
+#define imx27_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
+#define imx27_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
+#define imx27_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c
index a0aeb8a4adc1..9c271a752b84 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -11,6 +11,9 @@
  *
  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
+ * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -32,6 +35,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/serial.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
@@ -40,38 +44,179 @@
 
 #include "devices.h"
 
-/*
- * SPI master controller
- *
- * - i.MX1: 2 channel (slighly different register setting)
- * - i.MX21: 2 channel
- * - i.MX27: 3 channel
- */
-#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)                                 \
-        static struct resource mxc_spi_resources ## n[] = {                     \
-                {                                                               \
-                        .start = baseaddr,                                      \
-                        .end = baseaddr + SZ_4K - 1,                            \
-                        .flags = IORESOURCE_MEM,                                \
-                }, {                                                            \
-                        .start = irq,                                           \
-                        .end = irq,                                             \
-                        .flags = IORESOURCE_IRQ,                                \
-                },                                                              \
-        };                                                                      \
-                                                                                \
-        struct platform_device mxc_spi_device ## n = {                          \
-                .name = "spi_imx",                                              \
-                .id = n,                                                        \
-                .num_resources = ARRAY_SIZE(mxc_spi_resources ## n),            \
-                .resource = mxc_spi_resources ## n,                             \
+#if defined(CONFIG_ARCH_MX1)
+static struct resource imx1_camera_resources[] = {
+        {
+                .start  = 0x00224000,
+                .end    = 0x00224010,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_CSI_INT,
+                .end    = MX1_CSI_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device imx1_camera_device = {
+        .name           = "mx1-camera",
+        .id             = 0, /* This is used to put cameras on this interface */
+        .dev            = {
+                .dma_mask = &imx1_camera_dmamask,
+                .coherent_dma_mask = DMA_BIT_MASK(32),
+        },
+        .resource       = imx1_camera_resources,
+        .num_resources  = ARRAY_SIZE(imx1_camera_resources),
+};
+
+static struct resource imx_rtc_resources[] = {
+        {
+                .start  = 0x00204000,
+                .end    = 0x00204024,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_RTC_INT,
+                .end    = MX1_RTC_INT,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_RTC_SAMINT,
+                .end    = MX1_RTC_SAMINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_rtc_device = {
+        .name           = "rtc-imx",
+        .id             = 0,
+        .resource       = imx_rtc_resources,
+        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
+};
+
+static struct resource imx_wdt_resources[] = {
+        {
+                .start  = 0x00201000,
+                .end    = 0x00201008,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_WDT_INT,
+                .end    = MX1_WDT_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_wdt_device = {
+        .name           = "imx-wdt",
+        .id             = 0,
+        .resource       = imx_wdt_resources,
+        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
+};
+
+static struct resource imx_usb_resources[] = {
+        {
+                .start  = 0x00212000,
+                .end    = 0x00212148,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX1_USBD_INT0,
+                .end    = MX1_USBD_INT0,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT1,
+                .end    = MX1_USBD_INT1,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT2,
+                .end    = MX1_USBD_INT2,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT3,
+                .end    = MX1_USBD_INT3,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT4,
+                .end    = MX1_USBD_INT4,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT5,
+                .end    = MX1_USBD_INT5,
+                .flags  = IORESOURCE_IRQ,
+        }, {
+                .start  = MX1_USBD_INT6,
+                .end    = MX1_USBD_INT6,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_usb_device = {
+        .name           = "imx_udc",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(imx_usb_resources),
+        .resource       = imx_usb_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+                .irq = MX1_GPIO_INT_PORTA,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
+                .chip.label = "gpio-1",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+                .irq = MX1_GPIO_INT_PORTB,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
+                .chip.label = "gpio-2",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+                .irq = MX1_GPIO_INT_PORTC,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
+                .chip.label = "gpio-3",
+                .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+                .irq = MX1_GPIO_INT_PORTD,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
         }
+};
+
+int __init imx1_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+#endif
 
-DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
-DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 
 #ifdef CONFIG_MACH_MX27
-DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
+static struct resource mx27_camera_resources[] = {
+        {
+               .start = MX27_CSI_BASE_ADDR,
+               .end = MX27_CSI_BASE_ADDR + 0x1f,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MX27_EMMA_PRP_BASE_ADDR,
+               .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MX27_INT_CSI,
+               .end = MX27_INT_CSI,
+               .flags = IORESOURCE_IRQ,
+        },{
+               .start = MX27_INT_EMMAPRP,
+               .end = MX27_INT_EMMAPRP,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mx27_camera_device = {
+        .name = "mx2-camera",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mx27_camera_resources),
+        .resource = mx27_camera_resources,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
 #endif
 
 /*
@@ -140,34 +285,6 @@ struct platform_device mxc_w1_master_device = {
         .resource = mxc_w1_master_resources,
 };
 
-#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)                      \
-        static struct resource pfx ## _nand_resources[] = {             \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                },                                                      \
-        };                                                              \
-                                                                        \
-        struct platform_device pfx ## _nand_device = {                  \
-                .name = "mxc_nand",                                     \
-                .id = 0,                                                \
-                .num_resources = ARRAY_SIZE(pfx ## _nand_resources),    \
-                .resource = pfx ## _nand_resources,                     \
-        }
-
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
-#endif
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
-#endif
-
 /*
  * lcdc:
  * - i.MX1: the basic controller
@@ -218,32 +335,6 @@ struct platform_device mxc_fec_device = {
 };
 #endif
 
-#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)                         \
-        static struct resource mxc_i2c_resources ## n[] = {             \
-                {                                                       \
-                        .start = baseaddr,                              \
-                        .end = baseaddr + SZ_4K - 1,                    \
-                        .flags = IORESOURCE_MEM,                        \
-                }, {                                                    \
-                        .start = irq,                                   \
-                        .end = irq,                                     \
-                        .flags = IORESOURCE_IRQ,                        \
-                }                                                       \
-        };                                                              \
-                                                                        \
-        struct platform_device mxc_i2c_device ## n = {                  \
-                .name = "imx-i2c",                                      \
-                .id = n,                                                \
-                .num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),    \
-                .resource = mxc_i2c_resources ## n,                     \
-        }
-
-DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
-#endif
-
 static struct resource mxc_pwm_resources[] = {
         {
                 .start = MX2x_PWM_BASE_ADDR,
@@ -454,26 +545,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
 #ifdef CONFIG_MACH_MX21
 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+
+int __init imx21_register_gpios(void)
+{
+        return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+}
 #endif
 
 #ifdef CONFIG_MACH_MX27
 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-#endif
 
-int __init mxc_register_gpios(void)
+int __init imx27_register_gpios(void)
 {
-#ifdef CONFIG_MACH_MX21
-        if (cpu_is_mx21())
-                return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
-        else
-#endif
-#ifdef CONFIG_MACH_MX27
-        if (cpu_is_mx27())
-                return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
-        else
-#endif
-                return 0;
+        return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
+#endif
 
 #ifdef CONFIG_MACH_MX21
 static struct resource mx21_usbhc_resources[] = {
@@ -501,3 +587,23 @@ struct platform_device mx21_usbhc_device = {
 };
 #endif
 
+static struct resource imx_kpp_resources[] = {
+        {
+                .start  = MX2x_KPP_BASE_ADDR,
+                .end    = MX2x_KPP_BASE_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX2x_INT_KPP,
+                .end    = MX2x_INT_KPP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_kpp_device = {
+        .name = "imx-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(imx_kpp_resources),
+        .resource = imx_kpp_resources,
+};
+
+#endif
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h
index 84ed51380174..efd4527506a5 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,3 +1,11 @@
+#ifdef CONFIG_ARCH_MX1
+extern struct platform_device imx1_camera_device;
+extern struct platform_device imx_rtc_device;
+extern struct platform_device imx_wdt_device;
+extern struct platform_device imx_usb_device;
+#endif
+
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 extern struct platform_device mxc_gpt1;
 extern struct platform_device mxc_gpt2;
 #ifdef CONFIG_MACH_MX27
@@ -6,37 +14,19 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
-extern struct platform_device mxc_uart_device5;
 extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX21
-extern struct platform_device imx21_nand_device;
-#endif
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx27_nand_device;
-#endif
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_i2c_device0;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_i2c_device1;
-#endif
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mx27_camera_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_spi_device2;
-#endif
 extern struct platform_device mx21_usbhc_device;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
+extern struct platform_device imx_kpp_device;
+#endif
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/mach-imx/dma-v1.c
index e16014b0d13c..fd1d9197d06e 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
+ *  linux/arch/arm/plat-mxc/dma-v1.c
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -34,7 +34,7 @@
 #include <asm/system.h>
 #include <asm/irq.h>
 #include <mach/hardware.h>
-#include <mach/dma-mx1-mx2.h>
+#include <mach/dma-v1.h>
 
 #define DMA_DCR     0x00                /* Control Register */
 #define DMA_DISR    0x04                /* Interrupt status Register */
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index f3b169d5245f..4edc5f439201 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009-2010 Eric Benard - eric@eukrea.com
  *
  * Based on pcm970-baseboard.c which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -24,6 +24,9 @@
 #include <linux/platform_device.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
+#include <linux/backlight.h>
+#include <video/platform_lcd.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach/arch.h>
 
@@ -32,8 +35,11 @@
 #include <mach/imxfb.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
-#include <mach/imx-uart.h>
+#include <mach/spi.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_mbimx27_pins[] = {
@@ -48,10 +54,12 @@ static int eukrea_mbimx27_pins[] = {
         PE10_PF_UART3_CTS,
         PE11_PF_UART3_RTS,
         /* UART4 */
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
         PB31_AF_UART4_RXD,
+#endif
         /* SDHC1*/
         PE18_PF_SD1_D0,
         PE19_PF_SD1_D1,
@@ -84,10 +92,29 @@ static int eukrea_mbimx27_pins[] = {
         PA30_PF_CONTRAST,
         PA31_PF_OE_ACD,
         /* SPI1 */
-        PD28_PF_CSPI1_SS0,
         PD29_PF_CSPI1_SCLK,
         PD30_PF_CSPI1_MISO,
         PD31_PF_CSPI1_MOSI,
+        /* SSI4 */
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+        PC16_PF_SSI4_FS,
+        PC17_PF_SSI4_RXD | GPIO_PUEN,
+        PC18_PF_SSI4_TXD | GPIO_PUEN,
+        PC19_PF_SSI4_CLK,
+#endif
+};
+
+static const uint32_t eukrea_mbimx27_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+};
+
+static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
+        .keymap         = eukrea_mbimx27_keymap,
+        .keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
 };
 
 static struct gpio_led gpio_leds[] = {
@@ -103,12 +130,6 @@ static struct gpio_led gpio_leds[] = {
                 .active_low             = 1,
                 .gpio                   = GPIO_PORTF | 19,
         },
-        {
-                .name                   = "backlight",
-                .default_trigger        = "backlight",
-                .active_low             = 0,
-                .gpio                   = GPIO_PORTE | 5,
-        },
 };
 
 static struct gpio_led_platform_data gpio_led_info = {
@@ -127,7 +148,7 @@ static struct platform_device leds_gpio = {
 static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
         {
                 .mode = {
-                        .name           = "CMO-QGVA",
+                        .name           = "CMO-QVGA",
                         .refresh        = 60,
                         .xres           = 320,
                         .yres           = 240,
@@ -141,6 +162,38 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
                 },
                 .pcr            = 0xFAD08B80,
                 .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "DVI-VGA",
+                        .refresh        = 60,
+                        .xres           = 640,
+                        .yres           = 480,
+                        .pixclock       = 32000,
+                        .hsync_len      = 1,
+                        .left_margin    = 35,
+                        .right_margin   = 0,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 0,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "DVI-SVGA",
+                        .refresh        = 60,
+                        .xres           = 800,
+                        .yres           = 600,
+                        .pixclock       = 25000,
+                        .hsync_len      = 1,
+                        .left_margin    = 35,
+                        .right_margin   = 0,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 0,
+                },
+                .pcr            = 0xFA208B80,
+                .bpp            = 16,
         },
 };
 
@@ -153,16 +206,52 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
         .dmacr          = 0x00040060,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
+static void eukrea_mbimx27_bl_set_intensity(int intensity)
+{
+        if (intensity)
+                gpio_direction_output(GPIO_PORTE | 5, 1);
+        else
+                gpio_direction_output(GPIO_PORTE | 5, 0);
+}
+
+static struct generic_bl_info eukrea_mbimx27_bl_info = {
+        .name                   = "eukrea_mbimx27-bl",
+        .max_intensity          = 0xff,
+        .default_intensity      = 0xff,
+        .set_bl_intensity       = eukrea_mbimx27_bl_set_intensity,
+};
+
+static struct platform_device eukrea_mbimx27_bl_dev = {
+        .name                   = "generic-bl",
+        .id                     = 1,
+        .dev = {
+                .platform_data  = &eukrea_mbimx27_bl_info,
         },
 };
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+static void eukrea_mbimx27_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_PORTA | 25, 1);
+        else
+                gpio_direction_output(GPIO_PORTA | 25, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimx27_lcd_power_data = {
+        .set_power              = eukrea_mbimx27_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimx27_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimx27_lcd_power_data,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
 
 #define ADS7846_PENDOWN (GPIO_PORTD | 25)
@@ -173,7 +262,6 @@ static void ads7846_dev_init(void)
                 printk(KERN_ERR "can't get ads746 pen down GPIO\n");
                 return;
         }
-
         gpio_direction_input(ADS7846_PENDOWN);
 }
 
@@ -186,7 +274,9 @@ static struct ads7846_platform_data ads7846_config __initdata = {
         .get_pendown_state      = ads7846_get_pendown_state,
         .keep_vref_on           = 1,
 };
+#endif
 
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
         [0] = {
                 .modalias       = "ads7846",
@@ -201,16 +291,30 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
-static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
         .chipselect     = eukrea_mbimx27_spi_cs,
         .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
 };
 #endif
 
+static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
 static struct platform_device *platform_devices[] __initdata = {
         &leds_gpio,
 };
 
+static struct imxmmc_platform_data sdhc_pdata = {
+        .dat3_card_detect = 1,
+};
+
+struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
+        .flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
+};
+
 /*
  * system init for baseboard usage. Will be called by cpuimx27 init.
  *
@@ -222,21 +326,52 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
                 ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+        || defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
+        /* SSI unit master I2S codec connected to SSI_PINS_4*/
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_TFSDIR |
+                        MXC_AUDMUX_V1_PCR_TCLKDIR |
+                        MXC_AUDMUX_V1_PCR_RFSDIR |
+                        MXC_AUDMUX_V1_PCR_RCLKDIR |
+                        MXC_AUDMUX_V1_PCR_TFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RFCSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4) |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR3_SSI_PINS_4)
+        );
+        mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR3_SSI_PINS_4,
+                        MXC_AUDMUX_V1_PCR_SYN |
+                        MXC_AUDMUX_V1_PCR_RXDSEL(MX27_AUDMUX_HPCR1_SSI0)
+        );
+#endif
+
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+#if !defined(MACH_EUKREA_CPUIMX27_USEUART4)
+        imx27_add_imx_uart3(&uart_pdata);
+#endif
 
         mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
-        mxc_register_device(&mxc_sdhc_device0, NULL);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
 
-#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
+
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
+
+#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
         || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
-        /* SPI and ADS7846 Touchscreen controler init */
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        /* ADS7846 Touchscreen controller init */
         mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
-        mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+        ads7846_dev_init();
+#endif
+
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        /* SPI_CS0 init */
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
         spi_register_board_info(eukrea_mbimx27_spi_board_info,
                         ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
-        ads7846_dev_init();
 #endif
 
         /* Leds configuration */
@@ -244,6 +379,14 @@ void __init eukrea_mbimx27_baseboard_init(void)
         mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
         /* Backlight */
         mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+        gpio_request(GPIO_PORTE | 5, "backlight");
+        platform_device_register(&eukrea_mbimx27_bl_dev);
+        /* LCD Reset */
+        mxc_gpio_mode(GPIO_PORTA | 25 | GPIO_GPIO | GPIO_OUT);
+        gpio_request(GPIO_PORTA | 25, "lcd_enable");
+        platform_device_register(&eukrea_mbimx27_lcd_powerdev);
+
+        mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644
index 000000000000..df5f522da6b3
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-v1.h
index 7c4870bd5a21..287431cc13e5 100644
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -1,5 +1,5 @@
 /*
- *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+ *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
  *
  *  i.MX DMA registration and IRQ dispatching
  *
@@ -22,8 +22,10 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_DMA_H
-#define __ASM_ARCH_MXC_DMA_H
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1()        (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
 
 #define IMX_DMA_CHANNELS  16
 
@@ -102,4 +104,4 @@ enum imx_dma_prio {
 
 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 
-#endif  /* _ASM_ARCH_MXC_DMA_H */
+#endif  /* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 1f616dcaabc9..575ff1ae85a7 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -26,20 +26,24 @@
 #include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/eukrea-baseboards.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_cpuimx27_pins[] = {
@@ -49,10 +53,12 @@ static int eukrea_cpuimx27_pins[] = {
         PE14_PF_UART1_CTS,
         PE15_PF_UART1_RTS,
         /* UART4 */
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
         PB26_AF_UART4_RTS,
         PB28_AF_UART4_TXD,
         PB29_AF_UART4_CTS,
         PB31_AF_UART4_RXD,
+#endif
         /* FEC */
         PD0_AIN_FEC_TXD0,
         PD1_AIN_FEC_TXD1,
@@ -76,19 +82,47 @@ static int eukrea_cpuimx27_pins[] = {
         PD17_PF_I2C_DATA,
         PD18_PF_I2C_CLK,
         /* SDHC2 */
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         PB4_PF_SD2_D0,
         PB5_PF_SD2_D1,
         PB6_PF_SD2_D2,
         PB7_PF_SD2_D3,
         PB8_PF_SD2_CMD,
         PB9_PF_SD2_CLK,
+#endif
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         /* Quad UART's IRQ */
-        GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
-        GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 22 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 27 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTB | 30 | GPIO_GPIO | GPIO_IN,
 #endif
+        /* OTG */
+        PC7_PF_USBOTG_DATA5,
+        PC8_PF_USBOTG_DATA6,
+        PC9_PF_USBOTG_DATA0,
+        PC10_PF_USBOTG_DATA2,
+        PC11_PF_USBOTG_DATA1,
+        PC12_PF_USBOTG_DATA4,
+        PC13_PF_USBOTG_DATA3,
+        PE0_PF_USBOTG_NXT,
+        PE1_PF_USBOTG_STP,
+        PE2_PF_USBOTG_DIR,
+        PE24_PF_USBOTG_CLK,
+        PE25_PF_USBOTG_DATA7,
+        /* USBH2 */
+        PA0_PF_USBH2_CLK,
+        PA1_PF_USBH2_DIR,
+        PA2_PF_USBH2_DATA7,
+        PA3_PF_USBH2_NXT,
+        PA4_PF_USBH2_STP,
+        PD19_AF_USBH2_DATA4,
+        PD20_AF_USBH2_DATA3,
+        PD21_AF_USBH2_DATA6,
+        PD22_AF_USBH2_DATA0,
+        PD23_AF_USBH2_DATA2,
+        PD24_AF_USBH2_DATA1,
+        PD26_AF_USBH2_DATA5,
 };
 
 static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
@@ -111,15 +145,12 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
         .resource = &eukrea_cpuimx27_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+static const struct mxc_nand_platform_data
+cpuimx27_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -127,9 +158,11 @@ static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
 static struct platform_device *platform_devices[] __initdata = {
         &eukrea_cpuimx27_nor_mtd_device,
         &mxc_fec_device,
+        &mxc_wdt,
+        &mxc_w1_master_device,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -182,34 +215,83 @@ static struct platform_device serial_device = {
 };
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+#endif
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx27_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx27_otg_mode);
+
 static void __init eukrea_cpuimx27_init(void)
 {
         mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
                 ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        imx27_add_imx_uart0(&uart_pdata);
 
-        mxc_register_device(&imx27_nand_device,
-                        &eukrea_cpuimx27_nand_board_info);
+        imx27_add_mxc_nand(&cpuimx27_nand_board_info);
 
         i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+        imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
         mxc_register_device(&mxc_sdhc_device1, NULL);
+#endif
+#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
         /* in which case UART4 is also used for Bluetooth */
-        mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+        imx27_add_imx_uart3(&uart_pdata);
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
         platform_device_register(&serial_device);
 #endif
 
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg_host, &otg_pdata);
+        }
+
+        usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
 #ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
         eukrea_mbimx27_baseboard_init();
 #endif
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index b5710bf18b96..22a2b5d91213 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -26,10 +22,9 @@
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27lite.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27lite_pins[] = {
@@ -59,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
         PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -71,7 +66,7 @@ static void __init mx27lite_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
                 "imx27lite");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 51f3cfd83db2..77a760cfadc0 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,10 +26,10 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 static int mx1ads_pins[] = {
@@ -58,12 +58,12 @@ static int mx1ads_pins[] = {
  * UARTs platform data
  */
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+       
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
 };
 
 static struct resource flash_resource = {
-        .start  = IMX_CS0_PHYS,
-        .end    = IMX_CS0_PHYS + SZ_32M - 1,
+        .start  = MX1_CS0_PHYS,
+        .end    = MX1_CS0_PHYS + SZ_32M - 1,
         .flags  = IORESOURCE_MEM,
 };
 
@@ -98,7 +98,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
         }
 };
 
-static struct imxi2c_platform_data mx1ads_i2c_data = {
+static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
                 ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
         /* UART */
-        mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
-        mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
+        imx1_add_imx_uart0(&uart0_pdata);
+        imx1_add_imx_uart1(&uart1_pdata);
 
         /* Physmap flash */
         mxc_register_device(&flash_device, &mx1ads_flash_data);
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
         i2c_register_board_info(0, mx1ads_i2c_devices,
                                 ARRAY_SIZE(mx1ads_i2c_devices));
 
-        mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
+        imx1_add_i2c_imx(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
         /* Maintainer: Sascha Hauer, Pengutronix */
-        .phys_io        = IMX_IO_PHYS,
-        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+        .phys_io        = MX1_IO_BASE_ADDR,
+        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-        .phys_io        = IMX_IO_PHYS,
-        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
+        .phys_io        = MX1_IO_BASE_ADDR,
+        .io_pg_offst    = (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
         .boot_params    = MX1_PHYS_OFFSET + 0x100,
         .map_io         = mx1_map_io,
         .init_irq       = mx1_init_irq,
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 113e58d7cb40..96d7f8189f32 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -28,15 +24,49 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/imx-uart.h>
 #include <mach/imxfb.h>
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
-#include <mach/board-mx21ads.h>
 
+#include "devices-imx21.h"
 #include "devices.h"
 
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_MMIO_SIZE        SZ_16M
+
+#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
+                (MX21ADS_MMIO_BASE_ADDR + (offset))
+
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
+
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED3_ON      0x8000
+
 static unsigned int mx21ads_pins[] = {
 
         /* CS8900A */
@@ -133,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
         .resource = &mx21ads_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata_rts __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxuart_platform_data uart_norts_pdata = {
+static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 };
 
-
 static int mx21ads_fb_init(struct platform_device *pdev)
 {
         u16 tmp;
@@ -227,7 +256,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
         .exit = mx21ads_sdhc_exit,
 };
 
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx21ads_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -263,12 +293,12 @@ static void __init mx21ads_board_init(void)
         mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
                         "mx21ads");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
-        mxc_register_device(&mxc_uart_device3, &uart_pdata);
+        imx21_add_imx_uart0(&uart_pdata_rts);
+        imx21_add_imx_uart2(&uart_pdata_norts);
+        imx21_add_imx_uart3(&uart_pdata_rts);
         mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
-        mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
+        imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index b2f4e0db3fb3..e66ffaa1c26c 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -12,23 +12,25 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX27 3-Stack Development System
+ *  - i.MX27 Platform Development Kit (i.MX27 PDK)
  */
 
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
+#include <linux/input/matrix_keypad.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27pdk.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27pdk_pins[] = {
@@ -58,7 +60,7 @@ static unsigned int mx27pdk_pins[] = {
         PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -66,12 +68,34 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_fec_device,
 };
 
+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx27_3ds_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_ENTER),
+        KEY(2, 0, KEY_F6),
+        KEY(2, 1, KEY_F8),
+        KEY(2, 2, KEY_F9),
+        KEY(2, 3, KEY_F10),
+};
+
+static struct matrix_keymap_data mx27_3ds_keymap_data = {
+        .keymap         = mx27_3ds_keymap,
+        .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
+};
+
 static void __init mx27pdk_init(void)
 {
         mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
                 "mx27pdk");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
 }
 
 static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 6ce323669e58..9c77da98a10e 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,16 +28,44 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27ads.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xf4300000
+#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
+                (PBC_BASE_ADDRESS + (offset))
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
 static unsigned int mx27ads_pins[] = {
         /* UART0 */
         PE12_PF_UART1_TXD,
@@ -141,7 +165,8 @@ static unsigned int mx27ads_pins[] = {
         PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx27ads_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -168,7 +193,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
         .resource = &mx27ads_flash_resource,
 };
 
-static struct imxi2c_platform_data mx27ads_i2c_data = {
+static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -263,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_w1_master_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mx27ads_board_init(void)
@@ -284,18 +297,18 @@ static void __init mx27ads_board_init(void)
         mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
                         "mx27ads");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-        mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
-        mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
-        mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
-        mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+        imx27_add_imx_uart3(&uart_pdata);
+        imx27_add_imx_uart4(&uart_pdata);
+        imx27_add_imx_uart5(&uart_pdata);
+        imx27_add_mxc_nand(&mx27ads_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, mx27ads_i2c_devices,
                                 ARRAY_SIZE(mx27ads_i2c_devices));
-        mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+        imx27_add_i2c_imx1(&mx27ads_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
         mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
@@ -342,4 +355,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
         .init_machine   = mx27ads_board_init,
         .timer          = &mx27ads_timer,
 MACHINE_END
-
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index bc3855992677..a3a1e452d4c5 100644
--- a/arch/arm/mach-mx2/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
@@ -32,14 +28,13 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mxt_td60_pins[] __initdata = {
@@ -128,12 +123,13 @@ static unsigned int mxt_td60_pins[] __initdata = {
         PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+static const struct mxc_nand_platform_data
+mxt_td60_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -173,7 +169,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
         },
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -239,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_fec_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mxt_td60_board_init(void)
@@ -254,10 +244,10 @@ static void __init mxt_td60_board_init(void)
         mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
                         "MXT_TD60");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-        mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
+        imx27_add_mxc_nand(&mxt_td60_nand_board_info);
 
         i2c_register_board_info(0, mxt_td60_i2c_devices,
                                 ARRAY_SIZE(mxt_td60_i2c_devices));
@@ -265,8 +255,8 @@ static void __init mxt_td60_board_init(void)
         i2c_register_board_info(1, mxt_td60_i2c2_devices,
                                 ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
-        mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+        imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
+        imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
         mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
         mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index a87422ed4ff5..6c92deaf468f 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,12 +36,7 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/i2c.h>
 #include <asm/mach/time.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
-#include <mach/imx-uart.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 #include <mach/mxc_nand.h>
@@ -49,11 +44,16 @@
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
+#include <mach/imxfb.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+#define SPI1_SS0 (GPIO_PORTD + 28)
+#define SPI1_SS1 (GPIO_PORTD + 27)
+#define SD2_CD (GPIO_PORTC + 29)
 
 static int pca100_pins[] = {
         /* UART1 */
@@ -68,6 +68,7 @@ static int pca100_pins[] = {
         PB7_PF_SD2_D3,
         PB8_PF_SD2_CMD,
         PB9_PF_SD2_CLK,
+        SD2_CD | GPIO_GPIO | GPIO_IN,
         /* FEC */
         PD0_AIN_FEC_TXD0,
         PD1_AIN_FEC_TXD1,
@@ -131,13 +132,42 @@ static int pca100_pins[] = {
         PD23_AF_USBH2_DATA2,
         PD24_AF_USBH2_DATA1,
         PD26_AF_USBH2_DATA5,
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA26_PF_PS,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA31_PF_OE_ACD,
+        /* free GPIO */
+        GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
+        GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
+        GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pca100_nand_board_info = {
+static const struct mxc_nand_platform_data
+pca100_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -148,7 +178,7 @@ static struct platform_device *platform_devices[] __initdata = {
         &mxc_wdt,
 };
 
-static struct imxi2c_platform_data pca100_i2c_1_data = {
+static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -189,9 +219,9 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
         },
 };
 
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
-static struct spi_imx_master pca100_spi_0_data = {
+static const struct spi_imx_master pca100_spi0_data __initconst = {
         .chipselect     = pca100_spi_cs,
         .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
@@ -253,6 +283,7 @@ static struct imxmmc_platform_data sdhc_pdata = {
         .exit = pca100_sdhc2_exit,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static int otg_phy_init(struct platform_device *pdev)
 {
         gpio_set_value(OTG_PHY_CS_GPIO, 0);
@@ -276,6 +307,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -297,6 +329,45 @@ static int __init pca100_otg_mode(char *options)
 }
 __setup("otg_mode=", pca100_otg_mode);
 
+/* framebuffer info */
+static struct imx_fb_videomode pca100_fb_modes[] = {
+        {
+                .mode = {
+                        .name           = "EMERGING-ETV570G0DHU",
+                        .refresh        = 60,
+                        .xres           = 640,
+                        .yres           = 480,
+                        .pixclock       = 39722, /* in ps (25.175 MHz) */
+                        .hsync_len      = 30,
+                        .left_margin    = 114,
+                        .right_margin   = 16,
+                        .vsync_len      = 3,
+                        .upper_margin   = 32,
+                        .lower_margin   = 0,
+                },
+                /*
+                 * TFT
+                 * Pixel pol active high
+                 * HSYNC active low
+                 * VSYNC active low
+                 * use HSYNC for ACD count
+                 * line clock disable while idle
+                 * always enable line clock even if no data
+                 */
+                .pcr = 0xf0c08080,
+                .bpp = 16,
+        },
+};
+
+static struct imx_fb_platform_data pca100_fb_data = {
+        .mode = pca100_fb_modes,
+        .num_modes = ARRAY_SIZE(pca100_fb_modes),
+
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020010,
+};
+
 static void __init pca100_init(void)
 {
         int ret;
@@ -320,33 +391,24 @@ static void __init pca100_init(void)
 
         mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx27_add_imx_uart0(&uart_pdata);
 
-        mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
         mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
-        mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
+        imx27_add_mxc_nand(&pca100_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, pca100_i2c_devices,
                                 ARRAY_SIZE(pca100_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
-
-        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
-        /* GPIO0_IRQ */
-        mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
-        /* GPIO1_IRQ */
-        mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
-        /* GPIO2_IRQ */
-        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+        imx27_add_i2c_imx1(&pca100_i2c1_data);
 
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
+        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
         spi_register_board_info(pca100_spi_board_info,
                                 ARRAY_SIZE(pca100_spi_board_info));
-        mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+        imx27_add_spi_imx0(&pca100_spi_0_data);
 #endif
 
         gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
@@ -372,6 +434,8 @@ static void __init pca100_init(void)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
         }
 
+        mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 36c89431679a..9212e8f37001 100644
--- a/arch/arm/mach-mx2/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -35,14 +35,12 @@
 #include <mach/board-pcm038.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int pcm038_pins[] = {
@@ -162,17 +160,12 @@ static struct platform_device pcm038_nor_mtd_device = {
         .resource = &pcm038_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-        {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        }, {
-                .flags = IMXUART_HAVE_RTSCTS,
-        },
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm038_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -192,7 +185,7 @@ static void __init pcm038_init_sram(void)
         mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
 }
 
-static struct imxi2c_platform_data pcm038_i2c_1_data = {
+static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -215,7 +208,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
 
 static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
 
-static struct spi_imx_master pcm038_spi_0_data = {
+static const struct spi_imx_master pcm038_spi0_data __initconst = {
         .chipselect = pcm038_spi_cs,
         .num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
 };
@@ -305,18 +298,18 @@ static void __init pcm038_init(void)
 
         pcm038_init_sram();
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+        imx27_add_imx_uart0(&uart_pdata);
+        imx27_add_imx_uart1(&uart_pdata);
+        imx27_add_imx_uart2(&uart_pdata);
 
         mxc_gpio_mode(PE16_AF_OWIRE);
-        mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
+        imx27_add_mxc_nand(&pcm038_nand_board_info);
 
         /* only the i2c master 1 is used on this CPU card */
         i2c_register_board_info(1, pcm038_i2c_devices,
                                 ARRAY_SIZE(pcm038_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+        imx27_add_i2c_imx1(&pcm038_i2c1_data);
 
         /* PE18 for user-LED D40 */
         mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@@ -326,7 +319,7 @@ static void __init pcm038_init(void)
         /* MC13783 IRQ */
         mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
-        mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
+        imx27_add_spi_imx0(&pcm038_spi0_data);
         spi_register_board_info(pcm038_spi_board_info,
                                 ARRAY_SIZE(pcm038_spi_board_info));
 
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 7587a7a12460..88bf0d1e26e6 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,17 +22,17 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 /*
  * This scb9328 has a 32MiB flash
  */
 static struct resource flash_resource = {
-        .start  = IMX_CS0_PHYS,
-        .end    = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
+        .start  = MX1_CS0_PHYS,
+        .end    = MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
         .flags  = IORESOURCE_MEM,
 };
 
@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
 static struct resource dm9000x_resources[] = {
         {
                 .name   = "address area",
-                .start  = IMX_CS5_PHYS,
-                .end    = IMX_CS5_PHYS + 1,
+                .start  = MX1_CS5_PHYS,
+                .end    = MX1_CS5_PHYS + 1,
                 .flags  = IORESOURCE_MEM,       /* address access */
         }, {
                 .name   = "data area",
-                .start  = IMX_CS5_PHYS + 4,
-                .end    = IMX_CS5_PHYS + 5,
+                .start  = MX1_CS5_PHYS + 4,
+                .end    = MX1_CS5_PHYS + 5,
                 .flags  = IORESOURCE_MEM,       /* data access */
         }, {
                 .start  = IRQ_GPIOC(3),
@@ -108,14 +108,13 @@ static int uart1_mxc_init(struct platform_device *pdev)
                         ARRAY_SIZE(mxc_uart1_pins), "UART1");
 }
 
-static int uart1_mxc_exit(struct platform_device *pdev)
+static void uart1_mxc_exit(struct platform_device *pdev)
 {
         mxc_gpio_release_multiple_pins(mxc_uart1_pins,
                         ARRAY_SIZE(mxc_uart1_pins));
-        return 0;
 }
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .init = uart1_mxc_init,
         .exit = uart1_mxc_exit,
         .flags = IMXUART_HAVE_RTSCTS,
@@ -131,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
-        mxc_register_device(&imx_uart1_device, &uart_pdata);
+        imx1_add_imx_uart0(&uart_pdata);
 
         printk(KERN_INFO"Scb9328: Adding devices\n");
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-imx/mm-imx1.c
index 7f9fc1034c08..9be92b96dc89 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -3,7 +3,7 @@
  *  Created: april 20th, 2004
  *  Copyright: Synertronixx GmbH
  *
- *  Common code for i.MX machines
+ *  Common code for i.MX1 machines
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
@@ -31,23 +26,25 @@
 
 static struct map_desc imx_io_desc[] __initdata = {
         {
-                .virtual        = IMX_IO_BASE,
-                .pfn            = __phys_to_pfn(IMX_IO_PHYS),
-                .length         = IMX_IO_SIZE,
-                .type           = MT_DEVICE
+                .virtual = MX1_IO_BASE_ADDR_VIRT,
+                .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
+                .length = MX1_IO_SIZE,
+                .type = MT_DEVICE
         }
 };
 
 void __init mx1_map_io(void)
 {
         mxc_set_cpu_type(MXC_CPU_MX1);
-        mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
+        mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 
         iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
 
+int imx1_register_gpios(void);
+
 void __init mx1_init_irq(void)
 {
-        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+        mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
+        imx1_register_gpios();
 }
-
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 64134314d012..12faeeaa0a97 100644
--- a/arch/arm/mach-mx2/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx21.c
+ * arch/arm/mach-imx/mm-imx21.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
         iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
 }
 
+int imx21_register_gpios(void);
+
 void __init mx21_init_irq(void)
 {
         mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
+        imx21_register_gpios();
 }
diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 3366ed44cfd5..a24622957ff2 100644
--- a/arch/arm/mach-mx2/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx27.c
+ * arch/arm/mach-imx/mm-imx27.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
  *
@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
         iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
 }
 
+int imx27_register_gpios(void);
+
 void __init mx27_init_irq(void)
 {
         mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
+        imx27_register_gpios();
 }
diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
index b09ee12a4ff0..b09ee12a4ff0 100644
--- a/arch/arm/mach-mx1/ksym_mx1.c
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
index 9c69aa65bf17..9c69aa65bf17 100644
--- a/arch/arm/mach-mx1/mx1_camera_fiq.S
+++ b/arch/arm/mach-imx/mx1-camera-fiq.S
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index f490a406d57e..f490a406d57e 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
new file mode 100644
index 000000000000..afc17ce0bb54
--- /dev/null
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -0,0 +1,46 @@
+/*
+ * i.MX27 Power Management Routines
+ *
+ * Based on Freescale's BSP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+#include <mach/mx27.h>
+
+static int mx27_suspend_enter(suspend_state_t state)
+{
+        u32 cscr;
+        switch (state) {
+        case PM_SUSPEND_MEM:
+                /* Clear MPEN and SPEN to disable MPLL/SPLL */
+                cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+                cscr &= 0xFFFFFFFC;
+                __raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+                /* Executes WFI */
+                arch_idle();
+                break;
+
+        default:
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static struct platform_suspend_ops mx27_suspend_ops = {
+        .enter = mx27_suspend_enter,
+        .valid = suspend_valid_only_mem,
+};
+
+static int __init mx27_pm_init(void)
+{
+        suspend_set_ops(&mx27_suspend_ops);
+        return 0;
+}
+
+device_initcall(mx27_pm_init);
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163b1fe3..cc25501b57fa 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
           Say 'Y' here if you want your kernel to support the
           Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+        bool "Marvell OpenRD Ultimate Board"
+        select MACH_OPENRD
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
         bool "LaCie Network Space v2 NAS Board"
         help
@@ -87,6 +94,12 @@ config MACH_INETSPACE_V2
           Say 'Y' here if you want your kernel to support the
           LaCie Internet Space v2 NAS.
 
+config MACH_NETSPACE_MAX_V2
+        bool "LaCie Network Space Max v2 NAS Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Network Space Max v2 NAS.
+
 config MACH_NET2BIG_V2
         bool "LaCie 2Big Network v2 NAS Board"
         help
@@ -99,6 +112,12 @@ config MACH_NET5BIG_V2
           Say 'Y' here if you want your kernel to support the
           LaCie 5Big Network v2 NAS.
 
+config MACH_T5325
+        bool "HP t5325 Thin Client"
+        help
+          Say 'Y' here if you want your kernel to support the
+          HP t5325 Thin Client.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index c0cd5d362002..295d7baa6ae1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -12,7 +12,9 @@ obj-$(CONFIG_MACH_TS41X)		+= ts41x-setup.o tsx1x-common.o
 obj-$(CONFIG_MACH_OPENRD)               += openrd-setup.o
 obj-$(CONFIG_MACH_NETSPACE_V2)          += netspace_v2-setup.o
 obj-$(CONFIG_MACH_INETSPACE_V2)         += netspace_v2-setup.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2)      += netspace_v2-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)           += netxbig_v2-setup.o
 obj-$(CONFIG_MACH_NET5BIG_V2)           += netxbig_v2-setup.o
+obj-$(CONFIG_MACH_T5325)                += t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168fc699..8d03bcef5182 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0            0x3e
 #define ATTR_PCIE_IO            0xe0
 #define ATTR_PCIE_MEM           0xe8
+#define ATTR_PCIE1_IO           0xd0
+#define ATTR_PCIE1_MEM          0xd8
 #define ATTR_SRAM               0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
                       TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
         setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
                       TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+        setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+                      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+        setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+                      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
         /*
          * Setup window for NAND controller.
          */
-        setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+        setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
                       TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
         /*
          * Setup window for SRAM.
          */
-        setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+        setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
                       TARGET_SRAM, ATTR_SRAM, -1);
 
         /*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa5e66a..9dd67c7b4459 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
                 .length         = KIRKWOOD_PCIE_IO_SIZE,
                 .type           = MT_DEVICE,
         }, {
+                .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
+                .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+                .length         = KIRKWOOD_PCIE1_IO_SIZE,
+                .type           = MT_DEVICE,
+        }, {
                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                 .length         = KIRKWOOD_REGS_SIZE,
@@ -402,7 +407,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (rev == 0)  /* catch all Kirkwood Z0's */
+        if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
                 mvsdio_data->clock = 100000000;
         else
                 mvsdio_data->clock = 200000000;
@@ -847,8 +852,10 @@ int __init kirkwood_find_tclk(void)
         u32 dev, rev;
 
         kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
-                                        rev == MV88F6281_REV_A1))
+
+        if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                        rev == MV88F6281_REV_A1)) ||
+            (dev == MV88F6282_DEV_ID))
                 return 200000000;
 
         return 166666667;
@@ -891,13 +898,22 @@ static char * __init kirkwood_id(void)
                         return "MV88F6192-Z0";
                 else if (rev == MV88F6192_REV_A0)
                         return "MV88F6192-A0";
+                else if (rev == MV88F6192_REV_A1)
+                        return "MV88F6192-A1";
                 else
                         return "MV88F6192-Rev-Unsupported";
         } else if (dev == MV88F6180_DEV_ID) {
                 if (rev == MV88F6180_REV_A0)
                         return "MV88F6180-Rev-A0";
+                else if (rev == MV88F6180_REV_A1)
+                        return "MV88F6180-Rev-A1";
                 else
                         return "MV88F6180-Rev-Unsupported";
+        } else if (dev == MV88F6282_DEV_ID) {
+                if (rev == MV88F6282_REV_A0)
+                        return "MV88F6282-Rev-A0";
+                else
+                        return "MV88F6282-Rev-Unsupported";
         } else {
                 return "Device-Unknown";
         }
@@ -949,12 +965,14 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
         unsigned int curr = readl(CLOCK_GATING_CTRL);
+        u32 dev, rev;
 
+        kirkwood_pcie_id(&dev, &rev);
         printk(KERN_DEBUG "Gating clock of unused units\n");
         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
         /* Make sure those units are accessible */
-        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+        writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
         /* For SATA: first shutdown the phy */
         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -979,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
         }
 
+        /* For PCIe 1: first shutdown the phy */
+        if (dev == MV88F6282_DEV_ID) {
+                if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+                        writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+                        while (1)
+                                if (readl(PCIE1_STATUS) & 0x1)
+                                        break;
+                        writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+                }
+        } else  /* keep this bit set for devices that don't have PCIe1 */
+                kirkwood_clk_ctrl |= CGC_PEX1;
+
         /* Now gate clock the required units */
         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a5692e..5b2c1c18d641 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0        (1 << 0)
+#define KW_PCIE1        (1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4bcace9..16f6691e7c68 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
 };
 
 static unsigned int db88f6281_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_NF_IO3,
+        MPP2_NF_IO4,
+        MPP3_NF_IO5,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
         MPP37_GPIO,
         MPP38_GPIO,
         0
@@ -74,9 +82,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-        if (machine_is_db88f6281_bp())
-                kirkwood_pcie_init();
+        if (machine_is_db88f6281_bp()) {
+                u32 dev, rev;
 
+                kirkwood_pcie_id(&dev, &rev);
+                if (dev == MV88F6282_DEV_ID)
+                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+                else
+                        kirkwood_pcie_init(KW_PCIE0);
+        }
         return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f5017c50e..aff0e1327e38 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1               (1 << 15)
 #define CGC_XOR1                (1 << 16)
 #define CGC_CRYPTO              (1 << 17)
+#define CGC_PEX1                (1 << 18)
 #define CGC_GE1                 (1 << 19)
 #define CGC_TDM                 (1 << 20)
-#define CGC_RESERVED            ((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED            (0x6 << 21)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a45a67e..9da2eb59180b 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10     7
 #define IRQ_KIRKWOOD_XOR_11     8
 #define IRQ_KIRKWOOD_PCIE       9
+#define IRQ_KIRKWOOD_PCIE1      10
 #define IRQ_KIRKWOOD_GE00_SUM   11
 #define IRQ_KIRKWOOD_GE01_SUM   15
 #define IRQ_KIRKWOOD_USB        19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0ee22bd..d141af4c2744 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
  * Marvell Kirkwood address maps.
  *
  * phys
- * e0000000     PCIe Memory space
+ * e0000000     PCIe #0 Memory space
+ * e8000000     PCIe #1 Memory space
  * f1000000     on-chip peripheral registers
- * f2000000     PCIe I/O space
- * f3000000     NAND controller address window
- * f4000000     Security Accelerator SRAM
+ * f2000000     PCIe #0 I/O space
+ * f3000000     PCIe #1 I/O space
+ * f4000000     NAND controller address window
+ * f5000000     Security Accelerator SRAM
  *
  * virt         phys            size
- * fee00000     f1000000        1M      on-chip peripheral registers
- * fef00000     f2000000        1M      PCIe I/O space
+ * fed00000     f1000000        1M      on-chip peripheral registers
+ * fee00000     f2000000        1M      PCIe #0 I/O space
+ * fef00000     f3000000        1M      PCIe #1 I/O space
  */
 
-#define KIRKWOOD_SRAM_PHYS_BASE         0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE         0xf5000000
 #define KIRKWOOD_SRAM_SIZE              SZ_2K
 
-#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE     0xf4000000
 #define KIRKWOOD_NAND_MEM_SIZE          SZ_1K
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE     0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE     0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE      0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE          SZ_1M
+
 #define KIRKWOOD_PCIE_IO_PHYS_BASE      0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE      0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE       0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE           SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
 #define KIRKWOOD_PCIE_MEM_BUS_BASE      0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE          SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE    0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE     0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE         SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +84,9 @@
 #define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
@@ -107,8 +122,12 @@
 #define MV88F6192_DEV_ID        0x6192
 #define MV88F6192_REV_Z0        0
 #define MV88F6192_REV_A0        2
+#define MV88F6192_REV_A1        3
 
 #define MV88F6180_DEV_ID        0x6180
 #define MV88F6180_REV_A0        2
+#define MV88F6180_REV_A1        3
 
+#define MV88F6282_DEV_ID        0x6282
+#define MV88F6282_REV_A0        0
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/leds-ns2.h b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
new file mode 100644
index 000000000000..e21272e5f668
--- /dev/null
+++ b/arch/arm/mach-kirkwood/include/mach/leds-ns2.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-kirkwood/include/mach/leds-ns2.h
+ *
+ * Platform data structure for Network Space v2 LED driver
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __MACH_LEDS_NS2_H
+#define __MACH_LEDS_NS2_H
+
+struct ns2_led {
+        const char      *name;
+        const char      *default_trigger;
+        unsigned        cmd;
+        unsigned        slow;
+};
+
+struct ns2_led_platform_data {
+        int             num_leds;
+        struct ns2_led  *leds;
+};
+
+#endif /* __MACH_LEDS_NS2_H */
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f64e38c..065187d177c6 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
 
         kirkwood_pcie_id(&dev, &rev);
 
-        if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
+        if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
+            (dev == MV88F6282_DEV_ID))
                 return MPP_F6281_MASK;
         if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
                 return MPP_F6192_MASK;
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278ed311..9b0a94d85c3e 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
 #ifndef __KIRKWOOD_MPP_H
 #define __KIRKWOOD_MPP_H
 
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
         /* MPP number */                ((_num) & 0xff) | \
         /* MPP select value */          (((_sel) & 0xf) << 8) | \
         /* may be input signal */       ((!!(_in)) << 12) | \
@@ -19,282 +19,332 @@
         /* available on F6180 */        ((!!(_F6180)) << 14) | \
         /* available on F6190 */        ((!!(_F6190)) << 15) | \
         /* available on F6192 */        ((!!(_F6192)) << 16) | \
-        /* available on F6281 */        ((!!(_F6281)) << 17))
+        /* available on F6281 */        ((!!(_F6281)) << 17) | \
+        /* available on F6282 */        ((!!(_F6282)) << 18))
 
 #define MPP_NUM(x)      ((x) & 0xff)
 #define MPP_SEL(x)      (((x) >> 8) & 0xf)
 
-                                /*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA             MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK             MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0             MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI      MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1             MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO      MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2             MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3             MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK     MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0       DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4             MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO       MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5             MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK    MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6             MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK     MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7             MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI       MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8             MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK      MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9             MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10            MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11            MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12            MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO              MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13            MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14            MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15            MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI      MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO      MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK     MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO       MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC      MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK     MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI       MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK      MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+                                /*   num sel  i  o  6180 6190 6192 6281 6282 */
+
+#define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
+#define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
+
+#define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
+#define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
+#define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
+#define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
+#define MPP_F6282_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_LCD_VGA_HSYNC      MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+
+#define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_LCD_VGA_VSYNC      MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA            MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK            MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+
+#define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA           MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+
+#define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM            MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_AU_SPDIFI         MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI          MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK           MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+
+#define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_GE1_TXD0          MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP20_AU_SPDIFI         MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_LCD_D0            MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_GE1_TXD1          MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_LCD_D1            MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_GE1_TXD2          MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_LCD_D2            MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_GE1_TXD3          MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_LCD_D3            MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_GE1_RXD0          MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_LCD_D4            MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_GE1_RXD1          MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_LCD_D5            MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_GE1_RXD2          MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_LCD_D6            MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_GE1_RXD3          MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP27_AU_I2SDI          MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_LCD_D7            MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP28_GE1_COL           MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP28_AU_EXTCLK         MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_LCD_D8            MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP29_GE1_TCLK          MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP29_LCD_D9            MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_GE1_RXCTL         MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP30_LCD_D10           MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_GE1_RXCLK         MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP31_LCD_D11           MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_GE1_TCLKOUT       MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP32_LCD_D12           MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP33_GPO               MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_GE1_TXCTL         MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP33_LCD_D13           MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_GE1_TXEN          MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_LCD_D14           MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_GE1_RXERR         MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_LCD_D15           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI         MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_TW1_SDA           MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TW1_SCK           MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_LCD_D18           MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_LCD_D19           MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_LCD_D20           MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_LCD_D21           MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_LCD_D22           MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI          MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_LCD_D23           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK         MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_LCD_CLK           MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP245_LCD_E            MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_LCD_HSYNC         MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_LCD_VSYNC         MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_LCD_D16           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_GPO               MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
+#define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_LCD_D17           MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 
 #define MPP_MAX                 49
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711b1c67..c6b92b42eb4e 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
         if (machine_is_mv88f6281gtw_ge())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d72681..d26bf324738b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -39,6 +39,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
+#include <mach/leds-ns2.h>
 #include <plat/time.h>
 #include "common.h"
 #include "mpp.h"
@@ -126,6 +127,18 @@ static void __init netspace_v2_sata_power_init(void)
         }
         if (err)
                 pr_err("netspace_v2: failed to setup SATA0 power\n");
+
+        if (machine_is_netspace_max_v2()) {
+                err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
+                if (err == 0) {
+                        err = gpio_direction_output(
+                                        NETSPACE_V2_GPIO_SATA1_POWER, 1);
+                        if (err)
+                                gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
+                }
+                if (err)
+                        pr_err("netspace_v2: failed to setup SATA1 power\n");
+        }
 }
 
 /*****************************************************************************
@@ -160,36 +173,12 @@ static struct platform_device netspace_v2_gpio_buttons = {
  * GPIO LEDs
  ****************************************************************************/
 
-/*
- * The blue front LED is wired to a CPLD and can blink in relation with the
- * SATA activity.
- *
- * The following array detail the different LED registers and the combination
- * of their possible values:
- *
- *  cmd_led   |  slow_led  | /SATA active | LED state
- *            |            |              |
- *     1      |     0      |      x       |  off
- *     -      |     1      |      x       |  on
- *     0      |     0      |      1       |  on
- *     0      |     0      |      0       |  blink (rate 300ms)
- */
-
 #define NETSPACE_V2_GPIO_RED_LED        12
-#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
-#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
-
 
 static struct gpio_led netspace_v2_gpio_led_pins[] = {
         {
-                .name                   = "ns_v2:blue:sata",
-                .default_trigger        = "default-on",
-                .gpio                   = NETSPACE_V2_GPIO_BLUE_LED_CMD,
-                .active_low             = 1,
-        },
-        {
-                .name                   = "ns_v2:red:fail",
-                .gpio                   = NETSPACE_V2_GPIO_RED_LED,
+                .name   = "ns_v2:red:fail",
+                .gpio   = NETSPACE_V2_GPIO_RED_LED,
         },
 };
 
@@ -206,22 +195,33 @@ static struct platform_device netspace_v2_gpio_leds = {
         },
 };
 
-static void __init netspace_v2_gpio_leds_init(void)
-{
-        int err;
+/*****************************************************************************
+ * Dual-GPIO CPLD LEDs
+ ****************************************************************************/
 
-        /* Configure register slow_led to allow SATA activity LED blinking */
-        err = gpio_request(NETSPACE_V2_GPIO_BLUE_LED_SLOW, "blue LED slow");
-        if (err == 0) {
-                err = gpio_direction_output(NETSPACE_V2_GPIO_BLUE_LED_SLOW, 0);
-                if (err)
-                        gpio_free(NETSPACE_V2_GPIO_BLUE_LED_SLOW);
-        }
-        if (err)
-                pr_err("netspace_v2: failed to configure blue LED slow GPIO\n");
+#define NETSPACE_V2_GPIO_BLUE_LED_SLOW  29
+#define NETSPACE_V2_GPIO_BLUE_LED_CMD   30
 
-        platform_device_register(&netspace_v2_gpio_leds);
-}
+static struct ns2_led netspace_v2_led_pins[] = {
+        {
+                .name   = "ns_v2:blue:sata",
+                .cmd    = NETSPACE_V2_GPIO_BLUE_LED_CMD,
+                .slow   = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
+        },
+};
+
+static struct ns2_led_platform_data netspace_v2_leds_data = {
+        .num_leds       = ARRAY_SIZE(netspace_v2_led_pins),
+        .leds           = netspace_v2_led_pins,
+};
+
+static struct platform_device netspace_v2_leds = {
+        .name           = "leds-ns2",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &netspace_v2_leds_data,
+        },
+};
 
 /*****************************************************************************
  * Timer
@@ -249,17 +249,21 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
         MPP4_NF_IO6,
         MPP5_NF_IO7,
         MPP6_SYSRST_OUTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP7_GPO,               /* Fan speed (bit 1) */
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP12_GPO,              /* Red led */
         MPP14_GPIO,             /* USB fuse */
         MPP16_GPIO,             /* SATA 0 power */
+        MPP17_GPIO,             /* SATA 1 power */
         MPP18_NF_IO0,
         MPP19_NF_IO1,
         MPP20_SATA1_ACTn,
         MPP21_SATA0_ACTn,
+        MPP22_GPIO,             /* Fan speed (bit 0) */
+        MPP23_GPIO,             /* Fan power */
         MPP24_GPIO,             /* USB mode select */
         MPP25_GPIO,             /* Fan rotation fail */
         MPP26_GPIO,             /* USB device vbus */
@@ -268,6 +272,7 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
         MPP30_GPIO,             /* Blue led (command register) */
         MPP31_GPIO,             /* Board power off */
         MPP32_GPIO,             /* Power button (0 = Released, 1 = Pushed) */
+        MPP33_GPO,              /* Fan speed (bit 2) */
         0
 };
 
@@ -299,7 +304,8 @@ static void __init netspace_v2_init(void)
         i2c_register_board_info(0, netspace_v2_i2c_info,
                                 ARRAY_SIZE(netspace_v2_i2c_info));
 
-        netspace_v2_gpio_leds_init();
+        platform_device_register(&netspace_v2_leds);
+        platform_device_register(&netspace_v2_gpio_leds);
         platform_device_register(&netspace_v2_gpio_buttons);
 
         if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@@ -332,3 +338,15 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .timer          = &netspace_v2_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_NETSPACE_MAX_V2
+MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = netspace_v2_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &netspace_v2_timer,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb0228e4f..2bd14c5079de 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_GPO,               /* Request power-off */
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_GPO,               /* Request power-off */
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_GPIO,             /* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
         MPP15_GPIO,             /* Rear power switch (auto|off) */
         MPP16_GPIO,             /* SATA HDD1 power */
         MPP17_GPIO,             /* SATA HDD2 power */
-        MPP20_GE1_0,
-        MPP21_GE1_1,
-        MPP22_GE1_2,
-        MPP23_GE1_3,
-        MPP24_GE1_4,
-        MPP25_GE1_5,
-        MPP26_GE1_6,
-        MPP27_GE1_7,
+        MPP20_GE1_TXD0,
+        MPP21_GE1_TXD1,
+        MPP22_GE1_TXD2,
+        MPP23_GE1_TXD3,
+        MPP24_GE1_RXD0,
+        MPP25_GE1_RXD1,
+        MPP26_GE1_RXD2,
+        MPP27_GE1_RXD3,
         MPP28_GPIO,             /* USB enable host vbus */
         MPP29_GPIO,             /* CPLD extension ALE */
-        MPP30_GE1_10,
-        MPP31_GE1_11,
-        MPP32_GE1_12,
-        MPP33_GE1_13,
+        MPP30_GE1_RXCTL,
+        MPP31_GE1_RXCLK,
+        MPP32_GE1_TCLKOUT,
+        MPP33_GE1_TXCTL,
         MPP34_GPIO,             /* Rear Push button */
         MPP35_GPIO,             /* Inhibit switch power-off */
         MPP36_GPIO,             /* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec33796..fd64cd2b4e0a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
 
         kirkwood_ehci_init();
 
+        if (machine_is_openrd_ultimate()) {
+                openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+                openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+        }
+
         kirkwood_ge00_init(&openrd_ge00_data);
-        if (machine_is_openrd_client())
+        if (!machine_is_openrd_base())
                 kirkwood_ge01_init(&openrd_ge01_data);
+
         kirkwood_sata_init(&openrd_sata_data);
         kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,8 +90,10 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-        if (machine_is_openrd_base() || machine_is_openrd_client())
-                kirkwood_pcie_init();
+        if (machine_is_openrd_base() ||
+            machine_is_openrd_client() ||
+            machine_is_openrd_ultimate())
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         .timer          = &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = openrd_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff50d39..55e7f00836b7 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE       ((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+        u8                      root_bus_nr;
+        void __iomem            *base;
+        spinlock_t              conf_lock;
+        int                     irq;
+        struct resource         res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-        *dev = orion_pcie_dev_id(PCIE_BASE);
-        *rev = orion_pcie_rev(PCIE_BASE);
+        struct pci_sys_data *sys = bus->sysdata;
+        return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
         /*
          * Don't go out when trying to access --
          * 1. nonexisting device on local bus
          * 2. where there's no device connected (no link)
          */
-        if (bus == 0 && dev == 0)
+        if (bus == pp->root_bus_nr && dev == 0)
                 return 1;
 
-        if (!orion_pcie_link_up(PCIE_BASE))
+        if (!orion_pcie_link_up(pp->base))
                 return 0;
 
-        if (bus == 0 && dev != 1)
+        if (bus == pp->root_bus_nr && dev != 1)
                 return 0;
 
         return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
                         int size, u32 *val)
 {
+        struct pcie_port *pp = bus_to_port(bus);
         unsigned long flags;
         int ret;
 
-        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
                 *val = 0xffffffff;
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
 
-        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
 
         return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
                         int where, int size, u32 val)
 {
+        struct pcie_port *pp = bus_to_port(bus);
         unsigned long flags;
         int ret;
 
-        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+        if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
                 return PCIBIOS_DEVICE_NOT_FOUND;
 
-        spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-        spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+        spin_lock_irqsave(&pp->conf_lock, flags);
+        ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+        spin_unlock_irqrestore(&pp->conf_lock, flags);
 
         return ret;
 }
@@ -93,50 +108,98 @@ static struct pci_ops pcie_ops = {
         .write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        struct resource *res;
-        extern unsigned int kirkwood_clk_ctrl;
+        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->irq = IRQ_KIRKWOOD_PCIE;
 
         /*
-         * Generic PCIe unit setup.
+         * IORESOURCE_IO
          */
-        orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+        pp->res[0].name = "PCIe 0 I/O Space";
+        pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+        pp->res[0].flags = IORESOURCE_IO;
 
         /*
-         * Request resources.
+         * IORESOURCE_MEM
          */
-        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-        if (!res)
-                panic("pcie_setup unable to alloc resources");
+        pp->res[1].name = "PCIe 0 MEM";
+        pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+        pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static void __init pcie1_ioresources_init(struct pcie_port *pp)
+{
+        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->irq = IRQ_KIRKWOOD_PCIE1;
 
         /*
          * IORESOURCE_IO
          */
-        res[0].name = "PCIe I/O Space";
-        res[0].flags = IORESOURCE_IO;
-        res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-        res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-        if (request_resource(&ioport_resource, &res[0]))
-                panic("Request PCIe IO resource failed\n");
-        sys->resource[0] = &res[0];
+        pp->res[0].name = "PCIe 1 I/O Space";
+        pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+        pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+        pp->res[0].flags = IORESOURCE_IO;
 
         /*
          * IORESOURCE_MEM
          */
-        res[1].name = "PCIe Memory Space";
-        res[1].flags = IORESOURCE_MEM;
-        res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-        res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-        if (request_resource(&iomem_resource, &res[1]))
-                panic("Request PCIe Memory resource failed\n");
-        sys->resource[1] = &res[1];
+        pp->res[1].name = "PCIe 1 MEM";
+        pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+        pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+        pp->res[1].flags = IORESOURCE_MEM;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        extern unsigned int kirkwood_clk_ctrl;
+        struct pcie_port *pp;
+        int index;
 
+        if (nr >= num_pcie_ports)
+                return 0;
+
+        index = pcie_port_map[nr];
+        printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+        pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+        if (!pp)
+                panic("PCIe: failed to allocate pcie_port data");
+        sys->private_data = pp;
+        pp->root_bus_nr = sys->busnr;
+        spin_lock_init(&pp->conf_lock);
+
+        switch (index) {
+        case 0:
+                kirkwood_clk_ctrl |= CGC_PEX0;
+                pcie0_ioresources_init(pp);
+                break;
+        case 1:
+                kirkwood_clk_ctrl |= CGC_PEX1;
+                pcie1_ioresources_init(pp);
+                break;
+        default:
+                panic("PCIe setup: invalid controller %d", index);
+        }
+
+        if (request_resource(&ioport_resource, &pp->res[0]))
+                panic("Request PCIe%d IO resource failed\n", index);
+        if (request_resource(&iomem_resource, &pp->res[1]))
+                panic("Request PCIe%d Memory resource failed\n", index);
+
+        sys->resource[0] = &pp->res[0];
+        sys->resource[1] = &pp->res[1];
         sys->resource[2] = NULL;
         sys->io_offset = 0;
 
-        kirkwood_clk_ctrl |= CGC_PEX0;
+        /*
+         * Generic PCIe unit setup.
+         */
+        orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+        orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
         return 1;
 }
@@ -163,7 +226,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
         struct pci_bus *bus;
 
-        if (nr == 0) {
+        if (nr < num_pcie_ports) {
                 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
         } else {
                 bus = NULL;
@@ -175,18 +238,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-        return IRQ_KIRKWOOD_PCIE;
+        struct pcie_port *pp = bus_to_port(dev->bus);
+
+        return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-        .nr_controllers = 1,
         .swizzle        = pci_std_swizzle,
         .setup          = kirkwood_pcie_setup,
         .scan           = kirkwood_pcie_scan_bus,
         .map_irq        = kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
 {
+        printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+        if (orion_pcie_link_up((void __iomem *)base)) {
+                printk(KERN_INFO "link up\n");
+                pcie_port_map[num_pcie_ports++] = index;
+        } else
+                printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
+{
+        if (portmask & KW_PCIE0)
+                add_pcie_port(0, PCIE_VIRT_BASE);
+
+        if (portmask & KW_PCIE1)
+                add_pcie_port(1, PCIE1_VIRT_BASE);
+
+        kirkwood_pci.nr_controllers = num_pcie_ports;
         pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304158f6..c34718c2cfe5 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
         if (machine_is_rd88f6192_nas())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708ddbc83e..3d1477135e12 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
         if (machine_is_rd88f6281())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
         return 0;
 }
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
new file mode 100644
index 000000000000..d01bf89cedbe
--- /dev/null
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -0,0 +1,194 @@
+/*
+ *
+ * HP t5325 Thin Client setup
+ *
+ * Copyright (C) 2010  Martin Michlmayr <tbm@cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition hp_t5325_partitions[] = {
+        {
+                .name           = "u-boot env",
+                .size           = SZ_64K,
+                .offset         = SZ_512K + SZ_256K,
+        },
+        {
+                .name           = "permanent u-boot env",
+                .size           = SZ_64K,
+                .offset         = MTDPART_OFS_APPEND,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "HP env",
+                .size           = SZ_64K,
+                .offset         = MTDPART_OFS_APPEND,
+        },
+        {
+                .name           = "u-boot",
+                .size           = SZ_512K,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+        {
+                .name           = "SSD firmware",
+                .size           = SZ_256K,
+                .offset         = SZ_512K,
+        },
+};
+
+const struct flash_platform_data hp_t5325_flash = {
+        .type           = "mx25l8005",
+        .name           = "spi_flash",
+        .parts          = hp_t5325_partitions,
+        .nr_parts       = ARRAY_SIZE(hp_t5325_partitions),
+};
+
+struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
+        {
+                .modalias       = "m25p80",
+                .platform_data  = &hp_t5325_flash,
+                .irq            = -1,
+        },
+};
+
+static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data hp_t5325_sata_data = {
+        .n_ports        = 2,
+};
+
+static struct gpio_keys_button hp_t5325_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = 45,
+                .desc           = "Power",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data hp_t5325_button_data = {
+        .buttons        = hp_t5325_buttons,
+        .nbuttons       = ARRAY_SIZE(hp_t5325_buttons),
+};
+
+static struct platform_device hp_t5325_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &hp_t5325_button_data,
+        }
+};
+
+static unsigned int hp_t5325_mpp_config[] __initdata = {
+        MPP0_NF_IO2,
+        MPP1_SPI_MOSI,
+        MPP2_SPI_SCK,
+        MPP3_SPI_MISO,
+        MPP4_NF_IO6,
+        MPP5_NF_IO7,
+        MPP6_SYSRST_OUTn,
+        MPP7_SPI_SCn,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
+        MPP10_UART0_TXD,
+        MPP11_UART0_RXD,
+        MPP12_SD_CLK,
+        MPP13_GPIO,
+        MPP14_GPIO,
+        MPP15_GPIO,
+        MPP16_GPIO,
+        MPP17_GPIO,
+        MPP18_NF_IO0,
+        MPP19_NF_IO1,
+        MPP20_GPIO,
+        MPP21_GPIO,
+        MPP22_GPIO,
+        MPP23_GPIO,
+        MPP32_GPIO,
+        MPP33_GE1_TXCTL,
+        MPP39_AU_I2SBCLK,
+        MPP40_AU_I2SDO,
+        MPP41_AU_I2SLRCLK,
+        MPP42_AU_I2SMCLK,
+        MPP45_GPIO,             /* Power button */
+        MPP48_GPIO,             /* Board power off */
+        0
+};
+
+#define HP_T5325_GPIO_POWER_OFF         48
+
+static void hp_t5325_power_off(void)
+{
+        gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
+}
+
+static void __init hp_t5325_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(hp_t5325_mpp_config);
+
+        kirkwood_uart0_init();
+        spi_register_board_info(hp_t5325_spi_slave_info,
+                                ARRAY_SIZE(hp_t5325_spi_slave_info));
+        kirkwood_spi_init();
+        kirkwood_i2c_init();
+        kirkwood_ge00_init(&hp_t5325_ge00_data);
+        kirkwood_sata_init(&hp_t5325_sata_data);
+        kirkwood_ehci_init();
+        platform_device_register(&hp_t5325_button_device);
+
+        if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = hp_t5325_power_off;
+        else
+                pr_err("t5325: failed to configure power-off GPIO\n");
+}
+
+static int __init hp_t5325_pci_init(void)
+{
+        if (machine_is_t5325())
+                kirkwood_pcie_init(KW_PCIE0);
+
+        return 0;
+}
+subsys_initcall(hp_t5325_pci_init);
+
+MACHINE_START(T5325, "HP t5325 Thin Client")
+        /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = hp_t5325_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0fe80e0..a5bd7fde04a9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP4_SATA1_ACTn,
         MPP5_SATA0_ACTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
         MPP15_GPIO,             /* USB Copy button */
         MPP16_GPIO,             /* Reset button */
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
+        MPP44_GPIO,             /* Board ID: 0: TS-11x, 1: TS-21x */
         0
 };
 
@@ -110,10 +111,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+        if (machine_is_ts219())
+                kirkwood_pcie_init(KW_PCIE0);
 
-   return 0;
+        return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d9e74b..2e14afef07a2 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -2,7 +2,7 @@
  *
  * QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS Board Setup
  *
- * Copyright (C) 2009  Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2009-2010  Martin Michlmayr <tbm@cyrius.com>
  * Copyright (C) 2008  Byron Bradley <byron.bbradley@gmail.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -17,6 +17,7 @@
 #include <linux/i2c.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/ata_platform.h>
+#include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <asm/mach-types.h>
@@ -26,6 +27,8 @@
 #include "mpp.h"
 #include "tsx1x-common.h"
 
+#define QNAP_TS41X_JUMPER_JP1   45
+
 static struct i2c_board_info __initdata qnap_ts41x_i2c_rtc = {
         I2C_BOARD_INFO("s35390a", 0x30),
 };
@@ -78,31 +81,31 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
         MPP3_SPI_MISO,
         MPP6_SYSRST_OUTn,
         MPP7_PEX_RST_OUTn,
-        MPP8_TW_SDA,
-        MPP9_TW_SCK,
+        MPP8_TW0_SDA,
+        MPP9_TW0_SCK,
         MPP10_UART0_TXD,
         MPP11_UART0_RXD,
         MPP13_UART1_TXD,        /* PIC controller */
         MPP14_UART1_RXD,        /* PIC controller */
         MPP15_SATA0_ACTn,
         MPP16_SATA1_ACTn,
-        MPP20_GE1_0,
-        MPP21_GE1_1,
-        MPP22_GE1_2,
-        MPP23_GE1_3,
-        MPP24_GE1_4,
-        MPP25_GE1_5,
-        MPP26_GE1_6,
-        MPP27_GE1_7,
-        MPP30_GE1_10,
-        MPP31_GE1_11,
-        MPP32_GE1_12,
-        MPP33_GE1_13,
+        MPP20_GE1_TXD0,
+        MPP21_GE1_TXD1,
+        MPP22_GE1_TXD2,
+        MPP23_GE1_TXD3,
+        MPP24_GE1_RXD0,
+        MPP25_GE1_RXD1,
+        MPP26_GE1_RXD2,
+        MPP27_GE1_RXD3,
+        MPP30_GE1_RXCTL,
+        MPP31_GE1_RXCLK,
+        MPP32_GE1_TCLKOUT,
+        MPP33_GE1_TXCTL,
         MPP36_GPIO,             /* RAM: 0: 256 MB, 1: 512 MB */
         MPP37_GPIO,             /* Reset button */
         MPP43_GPIO,             /* USB Copy button */
         MPP44_GPIO,             /* Board ID: 0: TS-419U, 1: TS-419 */
-        MPP45_GPIO,             /* JP1: 0: console, 1: LCD */
+        MPP45_GPIO,             /* JP1: 0: LCD, 1: serial console */
         MPP46_GPIO,             /* External SATA HDD1 error indicator */
         MPP47_GPIO,             /* External SATA HDD2 error indicator */
         MPP48_GPIO,             /* External SATA HDD3 error indicator */
@@ -131,12 +134,14 @@ static void __init qnap_ts41x_init(void)
 
         pm_power_off = qnap_tsx1x_power_off;
 
+        if (gpio_request(QNAP_TS41X_JUMPER_JP1, "JP1") == 0)
+                gpio_export(QNAP_TS41X_JUMPER_JP1, 0);
 }
 
 static int __init ts41x_pci_init(void)
 {
         if (machine_is_ts41x())
-                kirkwood_pcie_init();
+                kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
new file mode 100644
index 000000000000..fde663508696
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -0,0 +1,33 @@
+if ARCH_LPC32XX
+
+menu "Individual UART enable selections"
+
+config ARCH_LPC32XX_UART3_SELECT
+        bool "Add support for standard UART3"
+        help
+         Adds support for standard UART 3 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART4_SELECT
+        bool "Add support for standard UART4"
+        help
+         Adds support for standard UART 4 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART5_SELECT
+        bool "Add support for standard UART5"
+        default y
+        help
+         Adds support for standard UART 5 when the 8250 serial support
+         is enabled.
+
+config ARCH_LPC32XX_UART6_SELECT
+        bool "Add support for standard UART6"
+        help
+         Adds support for standard UART 6 when the 8250 serial support
+         is enabled.
+
+endmenu
+
+endif
+
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
new file mode 100644
index 000000000000..a5fc5d0eeaeb
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+
+obj-y   := timer.o irq.o common.o serial.o clock.o
+obj-y   += gpiolib.o pm.o suspend.o
+obj-y   += phy3250.o
+
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
new file mode 100644
index 000000000000..b796b41ebf8f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x82000000
+
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
new file mode 100644
index 000000000000..32d63796430a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -0,0 +1,1137 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * LPC32xx clock management driver overview
+ *
+ * The LPC32XX contains a number of high level system clocks that can be
+ * generated from different sources. These system clocks are used to
+ * generate the CPU and bus rates and the individual peripheral clocks in
+ * the system. When Linux is started by the boot loader, the system
+ * clocks are already running. Stopping a system clock during normal
+ * Linux operation should never be attempted, as peripherals that require
+ * those clocks will quit working (ie, DRAM).
+ *
+ * The LPC32xx high level clock tree looks as follows. Clocks marked with
+ * an asterisk are always on and cannot be disabled. Clocks marked with
+ * an ampersand can only be disabled in CPU suspend mode. Clocks marked
+ * with a caret are always on if it is the selected clock for the SYSCLK
+ * source. The clock that isn't used for SYSCLK can be enabled and
+ * disabled normally.
+ *                               32KHz oscillator*
+ *                               /      |      \
+ *                             RTC*   PLL397^ TOUCH
+ *                                     /
+ *               Main oscillator^     /
+ *                   |        \      /
+ *                   |         SYSCLK&
+ *                   |            \
+ *                   |             \
+ *                USB_PLL       HCLK_PLL&
+ *                   |           |    |
+ *            USB host/device  PCLK&  |
+ *                               |    |
+ *                             Peripherals
+ *
+ * The CPU and chip bus rates are derived from the HCLK PLL, which can
+ * generate various clock rates up to 266MHz and beyond. The internal bus
+ * rates (PCLK and HCLK) are generated from dividers based on the HCLK
+ * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
+ * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
+ * level clocks are based on either HCLK or PCLK, but have their own
+ * dividers as part of the IP itself. Because of this, the system clock
+ * rates should not be changed.
+ *
+ * The HCLK PLL is clocked from SYSCLK, which can be derived from the
+ * main oscillator or PLL397. PLL397 generates a rate that is 397 times
+ * the 32KHz oscillator rate. The main oscillator runs at the selected
+ * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
+ * is normally 13MHz, but depends on the selection of external crystals
+ * or oscillators. If USB operation is required, the main oscillator must
+ * be used in the system.
+ *
+ * Switching SYSCLK between sources during normal Linux operation is not
+ * supported. SYSCLK is preset in the bootloader. Because of the
+ * complexities of clock management during clock frequency changes,
+ * there are some limitations to the clock driver explained below:
+ * - The PLL397 and main oscillator can be enabled and disabled by the
+ *   clk_enable() and clk_disable() functions unless SYSCLK is based
+ *   on that clock. This allows the other oscillator that isn't driving
+ *   the HCLK PLL to be used as another system clock that can be routed
+ *   to an external pin.
+ * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
+ *   this driver.
+ * - HCLK and PCLK rates cannot be changed as part of this driver.
+ * - Most peripherals have their own dividers are part of the peripheral
+ *   block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
+ *   will also impact the individual peripheral rates.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+
+#include <mach/hardware.h>
+#include <asm/clkdev.h>
+#include <mach/clkdev.h>
+#include <mach/platform.h>
+#include "clock.h"
+#include "common.h"
+
+static struct clk clk_armpll;
+static struct clk clk_usbpll;
+static DEFINE_MUTEX(clkm_lock);
+
+/*
+ * Post divider values for PLLs based on selected register value
+ */
+static const u32 pll_postdivs[4] = {1, 2, 4, 8};
+
+static unsigned long local_return_parent_rate(struct clk *clk)
+{
+        /*
+         * If a clock has a rate of 0, then it inherits it's parent
+         * clock rate
+         */
+        while (clk->rate == 0)
+                clk = clk->parent;
+
+        return clk->rate;
+}
+
+/* 32KHz clock has a fixed rate and is not stoppable */
+static struct clk osc_32KHz = {
+        .rate           = LPC32XX_CLOCK_OSC_FREQ,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int local_pll397_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL);
+
+        if (enable == 0) {
+                reg |= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+                __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+        } else {
+                /* Enable PLL397 */
+                reg &= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS;
+                __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL);
+
+                /* Wait for PLL397 lock */
+                while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                        LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0) &&
+                        (timeout > jiffies))
+                        cpu_relax();
+
+                if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL) &
+                        LPC32XX_CLKPWR_SYSCTRL_PLL397_STS) == 0)
+                        return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int local_oscmain_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+        if (enable == 0) {
+                reg |= LPC32XX_CLKPWR_MOSC_DISABLE;
+                __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+        } else {
+                /* Enable main oscillator */
+                reg &= ~LPC32XX_CLKPWR_MOSC_DISABLE;
+                __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL);
+
+                /* Wait for main oscillator to start */
+                while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                        LPC32XX_CLKPWR_MOSC_DISABLE) != 0) &&
+                        (timeout > jiffies))
+                        cpu_relax();
+
+                if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL) &
+                        LPC32XX_CLKPWR_MOSC_DISABLE) != 0)
+                        return -ENODEV;
+        }
+
+        return 0;
+}
+
+static struct clk osc_pll397 = {
+        .parent         = &osc_32KHz,
+        .enable         = local_pll397_enable,
+        .rate           = LPC32XX_CLOCK_OSC_FREQ * 397,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk osc_main = {
+        .enable         = local_oscmain_enable,
+        .rate           = LPC32XX_MAIN_OSC_FREQ,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_sys;
+
+/*
+ * Convert a PLL register value to a PLL output frequency
+ */
+u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval)
+{
+        struct clk_pll_setup pllcfg;
+
+        pllcfg.cco_bypass_b15 = 0;
+        pllcfg.direct_output_b14 = 0;
+        pllcfg.fdbk_div_ctrl_b13 = 0;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0)
+                pllcfg.cco_bypass_b15 = 1;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0)
+                pllcfg.direct_output_b14 = 1;
+        if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0)
+                pllcfg.fdbk_div_ctrl_b13 = 1;
+        pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF);
+        pllcfg.pll_n = 1 + ((regval >> 9) & 0x3);
+        pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)];
+
+        return clk_check_pll_setup(inputclk, &pllcfg);
+}
+
+/*
+ * Setup the HCLK PLL with a PLL structure
+ */
+static u32 local_clk_pll_setup(struct clk_pll_setup *PllSetup)
+{
+        u32 tv, tmp = 0;
+
+        if (PllSetup->analog_on != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_POWER_UP;
+        if (PllSetup->cco_bypass_b15 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS;
+        if (PllSetup->direct_output_b14 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS;
+        if (PllSetup->fdbk_div_ctrl_b13 != 0)
+                tmp |= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK;
+
+        tv = ffs(PllSetup->pll_p) - 1;
+        if ((!is_power_of_2(PllSetup->pll_p)) || (tv > 3))
+                return 0;
+
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv);
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup->pll_n - 1);
+        tmp |= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup->pll_m - 1);
+
+        return tmp;
+}
+
+/*
+ * Update the ARM core PLL frequency rate variable from the actual PLL setting
+ */
+static void local_update_armpll_rate(void)
+{
+        u32 clkin, pllreg;
+
+        clkin = clk_armpll.parent->rate;
+        pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+
+        clk_armpll.rate = clk_get_pllrate_from_reg(clkin, pllreg);
+}
+
+/*
+ * Find a PLL configuration for the selected input frequency
+ */
+static u32 local_clk_find_pll_cfg(u32 pllin_freq, u32 target_freq,
+        struct clk_pll_setup *pllsetup)
+{
+        u32 ifreq, freqtol, m, n, p, fclkout;
+
+        /* Determine frequency tolerance limits */
+        freqtol = target_freq / 250;
+        ifreq = pllin_freq;
+
+        /* Is direct bypass mode possible? */
+        if (abs(pllin_freq - target_freq) <= freqtol) {
+                pllsetup->analog_on = 0;
+                pllsetup->cco_bypass_b15 = 1;
+                pllsetup->direct_output_b14 = 1;
+                pllsetup->fdbk_div_ctrl_b13 = 1;
+                pllsetup->pll_p = pll_postdivs[0];
+                pllsetup->pll_n = 1;
+                pllsetup->pll_m = 1;
+                return clk_check_pll_setup(ifreq, pllsetup);
+        } else if (target_freq <= ifreq) {
+                pllsetup->analog_on = 0;
+                pllsetup->cco_bypass_b15 = 1;
+                pllsetup->direct_output_b14 = 0;
+                pllsetup->fdbk_div_ctrl_b13 = 1;
+                pllsetup->pll_n = 1;
+                pllsetup->pll_m = 1;
+                for (p = 0; p <= 3; p++) {
+                        pllsetup->pll_p = pll_postdivs[p];
+                        fclkout = clk_check_pll_setup(ifreq, pllsetup);
+                        if (abs(target_freq - fclkout) <= freqtol)
+                                return fclkout;
+                }
+        }
+
+        /* Is direct mode possible? */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 1;
+        pllsetup->fdbk_div_ctrl_b13 = 0;
+        pllsetup->pll_p = pll_postdivs[0];
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        /* Compute output frequency for this value */
+                        pllsetup->pll_n = n;
+                        pllsetup->pll_m = m;
+                        fclkout = clk_check_pll_setup(ifreq,
+                                pllsetup);
+                        if (abs(target_freq - fclkout) <=
+                                freqtol)
+                                return fclkout;
+                }
+        }
+
+        /* Is integer mode possible? */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 0;
+        pllsetup->fdbk_div_ctrl_b13 = 1;
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        for (p = 0; p < 4; p++) {
+                                /* Compute output frequency */
+                                pllsetup->pll_p = pll_postdivs[p];
+                                pllsetup->pll_n = n;
+                                pllsetup->pll_m = m;
+                                fclkout = clk_check_pll_setup(
+                                        ifreq, pllsetup);
+                                if (abs(target_freq - fclkout) <= freqtol)
+                                        return fclkout;
+                        }
+                }
+        }
+
+        /* Try non-integer mode */
+        pllsetup->analog_on = 1;
+        pllsetup->cco_bypass_b15 = 0;
+        pllsetup->direct_output_b14 = 0;
+        pllsetup->fdbk_div_ctrl_b13 = 0;
+        for (m = 1; m <= 256; m++) {
+                for (n = 1; n <= 4; n++) {
+                        for (p = 0; p < 4; p++) {
+                                /* Compute output frequency */
+                                pllsetup->pll_p = pll_postdivs[p];
+                                pllsetup->pll_n = n;
+                                pllsetup->pll_m = m;
+                                fclkout = clk_check_pll_setup(
+                                        ifreq, pllsetup);
+                                if (abs(target_freq - fclkout) <= freqtol)
+                                        return fclkout;
+                        }
+                }
+        }
+
+        return 0;
+}
+
+static struct clk clk_armpll = {
+        .parent         = &clk_sys,
+        .get_rate       = local_return_parent_rate,
+};
+
+/*
+ * Setup the USB PLL with a PLL structure
+ */
+static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
+{
+        u32 reg, tmp = local_clk_pll_setup(pHCLKPllSetup);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL) & ~0x1FFFF;
+        reg |= tmp;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        return clk_check_pll_setup(clk_usbpll.parent->rate,
+                pHCLKPllSetup);
+}
+
+static int local_usbpll_enable(struct clk *clk, int enable)
+{
+        u32 reg;
+        int ret = -ENODEV;
+        unsigned long timeout = 1 + msecs_to_jiffies(10);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+
+        if (enable == 0) {
+                reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
+                        LPC32XX_CLKPWR_USBCTRL_CLK_EN2);
+                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+        } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) {
+                reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+                __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+                /* Wait for PLL lock */
+                while ((timeout > jiffies) & (ret == -ENODEV)) {
+                        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+                        if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
+                                ret = 0;
+                }
+
+                if (ret == 0) {
+                        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+                        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+                }
+        }
+
+        return ret;
+}
+
+static unsigned long local_usbpll_round_rate(struct clk *clk,
+        unsigned long rate)
+{
+        u32 clkin, usbdiv;
+        struct clk_pll_setup pllsetup;
+
+        /*
+         * Unlike other clocks, this clock has a KHz input rate, so bump
+         * it up to work with the PLL function
+         */
+        rate = rate * 1000;
+
+        clkin = clk->parent->rate;
+        usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+                LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+        clkin = clkin / usbdiv;
+
+        /* Try to find a good rate setup */
+        if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+                return 0;
+
+        return clk_check_pll_setup(clkin, &pllsetup);
+}
+
+static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 clkin, reg, usbdiv;
+        struct clk_pll_setup pllsetup;
+
+        /*
+         * Unlike other clocks, this clock has a KHz input rate, so bump
+         * it up to work with the PLL function
+         */
+        rate = rate * 1000;
+
+        clkin = clk->get_rate(clk);
+        usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
+                LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
+        clkin = clkin / usbdiv;
+
+        /* Try to find a good rate setup */
+        if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
+                return -EINVAL;
+
+        local_usbpll_enable(clk, 0);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        pllsetup.analog_on = 1;
+        local_clk_usbpll_setup(&pllsetup);
+
+        clk->rate = clk_check_pll_setup(clkin, &pllsetup);
+
+        reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
+        reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2;
+        __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
+
+        return 0;
+}
+
+static struct clk clk_usbpll = {
+        .parent         = &osc_main,
+        .set_rate       = local_usbpll_set_rate,
+        .enable         = local_usbpll_enable,
+        .rate           = 48000, /* In KHz */
+        .get_rate       = local_return_parent_rate,
+        .round_rate     = local_usbpll_round_rate,
+};
+
+static u32 clk_get_hclk_div(void)
+{
+        static const u32 hclkdivs[4] = {1, 2, 4, 4};
+        return hclkdivs[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
+                __raw_readl(LPC32XX_CLKPWR_HCLK_DIV))];
+}
+
+static struct clk clk_hclk = {
+        .parent         = &clk_armpll,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_pclk = {
+        .parent         = &clk_armpll,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int local_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(clk->enable_reg);
+
+        if (enable == 0)
+                tmp &= ~clk->enable_mask;
+        else
+                tmp |= clk->enable_mask;
+
+        __raw_writel(tmp, clk->enable_reg);
+
+        return 0;
+}
+
+/* Peripheral clock sources */
+static struct clk clk_timer0 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer1 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer2 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_timer3 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1,
+        .enable_mask    = LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_wdt = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_TIMER_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_vfp9 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_DEBUG_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT,
+        .get_rate       = local_return_parent_rate,
+};
+static struct clk clk_dma = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_DMA_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart3 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart4 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart5 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_uart6 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_UART_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2C_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2c2 = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = io_p2v(LPC32XX_USB_BASE + 0xFF4),
+        .enable_mask    = 0x4,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_ssp1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_SSP_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_kscan = {
+        .parent         = &osc_32KHz,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_KEY_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_nand = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s0 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_i2s1 = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_net = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_MACCLK_CTRL,
+        .enable_mask    = (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN |
+                LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN |
+                LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN),
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_rtc = {
+        .parent         = &osc_32KHz,
+        .rate           = 1, /* 1 Hz */
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_usbd = {
+        .parent         = &clk_usbpll,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int tsc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        /* Make sure 32KHz clock is the selected clock */
+        tmp = __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+        tmp &= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL;
+        __raw_writel(tmp, LPC32XX_CLKPWR_ADC_CLK_CTRL_1);
+
+        if (enable == 0)
+                __raw_writel(0, clk->enable_reg);
+        else
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+        return 0;
+}
+
+static struct clk clk_tsc = {
+        .parent         = &osc_32KHz,
+        .enable         = tsc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_ADC_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN,
+        .get_rate       = local_return_parent_rate,
+};
+
+static int mmc_onoff_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+                ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+        /* If rate is 0, disable clock */
+        if (enable != 0)
+                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+
+        __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+        return 0;
+}
+
+static unsigned long mmc_get_rate(struct clk *clk)
+{
+        u32 div, rate, oldclk;
+
+        /* The MMC clock must be on when accessing an MMC register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+                LPC32XX_CLKPWR_MS_CTRL);
+        div = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+        /* Get the parent clock rate */
+        rate = clk->parent->get_rate(clk->parent);
+
+        /* Get the MMC controller clock divider value */
+        div = div & LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+
+        if (!div)
+                div = 1;
+
+        return rate / div;
+}
+
+static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long div, prate;
+
+        /* Get the parent clock rate */
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate >= prate)
+                return prate;
+
+        div = prate / rate;
+        if (div > 0xf)
+                div = 0xf;
+
+        return prate / div;
+}
+
+static int mmc_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 oldclk, tmp;
+        unsigned long prate, div, crate = mmc_round_rate(clk, rate);
+
+        prate = clk->parent->get_rate(clk->parent);
+
+        div = prate / crate;
+
+        /* The MMC clock must be on when accessing an MMC register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+                LPC32XX_CLKPWR_MS_CTRL);
+        tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
+                ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
+        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+        __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
+
+        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
+
+        return 0;
+}
+
+static struct clk clk_mmc = {
+        .parent         = &clk_armpll,
+        .set_rate       = mmc_set_rate,
+        .get_rate       = mmc_get_rate,
+        .round_rate     = mmc_round_rate,
+        .enable         = mmc_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_MS_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
+};
+
+static unsigned long clcd_get_rate(struct clk *clk)
+{
+        u32 tmp, div, rate, oldclk;
+
+        /* The LCD clock must be on when accessing an LCD register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+        tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+        __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        rate = clk->parent->get_rate(clk->parent);
+
+        /* Only supports internal clocking */
+        if (tmp & TIM2_BCD)
+                return rate;
+
+        div = (tmp & 0x1F) | ((tmp & 0xF8) >> 22);
+        tmp = rate / (2 + div);
+
+        return tmp;
+}
+
+static int clcd_set_rate(struct clk *clk, unsigned long rate)
+{
+        u32 tmp, prate, div, oldclk;
+
+        /* The LCD clock must be on when accessing an LCD register */
+        oldclk = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel(oldclk | LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        tmp = __raw_readl(io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2)) | TIM2_BCD;
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate < prate) {
+                /* Find closest divider */
+                div = prate / rate;
+                if (div >= 2) {
+                        div -= 2;
+                        tmp &= ~TIM2_BCD;
+                }
+
+                tmp &= ~(0xF800001F);
+                tmp |= (div & 0x1F);
+                tmp |= (((div >> 5) & 0x1F) << 27);
+        }
+
+        __raw_writel(tmp, io_p2v(LPC32XX_LCD_BASE + CLCD_TIM2));
+        __raw_writel(oldclk, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        return 0;
+}
+
+static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate)
+{
+        u32 prate, div;
+
+        prate = clk->parent->get_rate(clk->parent);
+
+        if (rate >= prate)
+                rate = prate;
+        else {
+                div = prate / rate;
+                if (div > 0x3ff)
+                        div = 0x3ff;
+
+                rate = prate / div;
+        }
+
+        return rate;
+}
+
+static struct clk clk_lcd = {
+        .parent         = &clk_hclk,
+        .set_rate       = clcd_set_rate,
+        .get_rate       = clcd_get_rate,
+        .round_rate     = clcd_round_rate,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_LCDCLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_LCDCTRL_CLK_EN,
+};
+
+static inline void clk_lock(void)
+{
+        mutex_lock(&clkm_lock);
+}
+
+static inline void clk_unlock(void)
+{
+        mutex_unlock(&clkm_lock);
+}
+
+static void local_clk_disable(struct clk *clk)
+{
+        WARN_ON(clk->usecount == 0);
+
+        /* Don't attempt to disable clock if it has no users */
+        if (clk->usecount > 0) {
+                clk->usecount--;
+
+                /* Only disable clock when it has no more users */
+                if ((clk->usecount == 0) && (clk->enable))
+                        clk->enable(clk, 0);
+
+                /* Check parent clocks, they may need to be disabled too */
+                if (clk->parent)
+                        local_clk_disable(clk->parent);
+        }
+}
+
+static int local_clk_enable(struct clk *clk)
+{
+        int ret = 0;
+
+        /* Enable parent clocks first and update use counts */
+        if (clk->parent)
+                ret = local_clk_enable(clk->parent);
+
+        if (!ret) {
+                /* Only enable clock if it's currently disabled */
+                if ((clk->usecount == 0) && (clk->enable))
+                        ret = clk->enable(clk, 1);
+
+                if (!ret)
+                        clk->usecount++;
+                else if (clk->parent)
+                        local_clk_disable(clk->parent);
+        }
+
+        return ret;
+}
+
+/*
+ * clk_enable - inform the system when the clock source should be running.
+ */
+int clk_enable(struct clk *clk)
+{
+        int ret;
+
+        clk_lock();
+        ret = local_clk_enable(clk);
+        clk_unlock();
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+/*
+ * clk_disable - inform the system when the clock source is no longer required
+ */
+void clk_disable(struct clk *clk)
+{
+        clk_lock();
+        local_clk_disable(clk);
+        clk_unlock();
+}
+EXPORT_SYMBOL(clk_disable);
+
+/*
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        unsigned long rate;
+
+        clk_lock();
+        rate = clk->get_rate(clk);
+        clk_unlock();
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+/*
+ * clk_set_rate - set the clock rate for a clock source
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        int ret = -EINVAL;
+
+        /*
+         * Most system clocks can only be enabled or disabled, with
+         * the actual rate set as part of the peripheral dividers
+         * instead of high level clock control
+         */
+        if (clk->set_rate) {
+                clk_lock();
+                ret = clk->set_rate(clk, rate);
+                clk_unlock();
+        }
+
+        return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+/*
+ * clk_round_rate - adjust a rate to the exact rate a clock can provide
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        clk_lock();
+
+        if (clk->round_rate)
+                rate = clk->round_rate(clk, rate);
+        else
+                rate = clk->get_rate(clk);
+
+        clk_unlock();
+
+        return rate;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+/*
+ * clk_set_parent - set the parent clock source for this clock
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        /* Clock re-parenting is not supported */
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+/*
+ * clk_get_parent - get the parent clock source for this clock
+ */
+struct clk *clk_get_parent(struct clk *clk)
+{
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = (d), \
+                .con_id = (n), \
+                .clk = &(c), \
+        },
+
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK(NULL, "osc_32KHz", osc_32KHz)
+        _REGISTER_CLOCK(NULL, "osc_pll397", osc_pll397)
+        _REGISTER_CLOCK(NULL, "osc_main", osc_main)
+        _REGISTER_CLOCK(NULL, "sys_ck", clk_sys)
+        _REGISTER_CLOCK(NULL, "arm_pll_ck", clk_armpll)
+        _REGISTER_CLOCK(NULL, "ck_pll5", clk_usbpll)
+        _REGISTER_CLOCK(NULL, "hclk_ck", clk_hclk)
+        _REGISTER_CLOCK(NULL, "pclk_ck", clk_pclk)
+        _REGISTER_CLOCK(NULL, "timer0_ck", clk_timer0)
+        _REGISTER_CLOCK(NULL, "timer1_ck", clk_timer1)
+        _REGISTER_CLOCK(NULL, "timer2_ck", clk_timer2)
+        _REGISTER_CLOCK(NULL, "timer3_ck", clk_timer3)
+        _REGISTER_CLOCK(NULL, "vfp9_ck", clk_vfp9)
+        _REGISTER_CLOCK(NULL, "clk_dmac", clk_dma)
+        _REGISTER_CLOCK("pnx4008-watchdog", NULL, clk_wdt)
+        _REGISTER_CLOCK(NULL, "uart3_ck", clk_uart3)
+        _REGISTER_CLOCK(NULL, "uart4_ck", clk_uart4)
+        _REGISTER_CLOCK(NULL, "uart5_ck", clk_uart5)
+        _REGISTER_CLOCK(NULL, "uart6_ck", clk_uart6)
+        _REGISTER_CLOCK("pnx-i2c.0", NULL, clk_i2c0)
+        _REGISTER_CLOCK("pnx-i2c.1", NULL, clk_i2c1)
+        _REGISTER_CLOCK("pnx-i2c.2", NULL, clk_i2c2)
+        _REGISTER_CLOCK("dev:ssp0", NULL, clk_ssp0)
+        _REGISTER_CLOCK("dev:ssp1", NULL, clk_ssp1)
+        _REGISTER_CLOCK("lpc32xx_keys.0", NULL, clk_kscan)
+        _REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
+        _REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
+        _REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
+        _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+        _REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
+        _REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
+        _REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
+        _REGISTER_CLOCK("lpc32xx_udc", "ck_usbd", clk_usbd)
+        _REGISTER_CLOCK("lpc32xx_rtc", NULL, clk_rtc)
+};
+
+static int __init clk_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+
+        /*
+         * Setup muxed SYSCLK for HCLK PLL base -this selects the
+         * parent clock used for the ARM PLL and is used to derive
+         * the many system clock rates in the device.
+         */
+        if (clk_is_sysclk_mainosc() != 0)
+                clk_sys.parent = &osc_main;
+        else
+                clk_sys.parent = &osc_pll397;
+
+        clk_sys.rate = clk_sys.parent->rate;
+
+        /* Compute the current ARM PLL and USB PLL frequencies */
+        local_update_armpll_rate();
+
+        /* Compute HCLK and PCLK bus rates */
+        clk_hclk.rate = clk_hclk.parent->rate / clk_get_hclk_div();
+        clk_pclk.rate = clk_pclk.parent->rate / clk_get_pclk_div();
+
+        /*
+         * Enable system clocks - this step is somewhat formal, as the
+         * clocks are already running, but it does get the clock data
+         * inline with the actual system state. Never disable these
+         * clocks as they will only stop if the system is going to sleep.
+         * In that case, the chip/system power management functions will
+         * handle clock gating.
+         */
+        if (clk_enable(&clk_hclk) || clk_enable(&clk_pclk))
+                printk(KERN_ERR "Error enabling system HCLK and PCLK\n");
+
+        /*
+         * Timers 0 and 1 were enabled and are being used by the high
+         * resolution tick function prior to this driver being initialized.
+         * Tag them now as used.
+         */
+        if (clk_enable(&clk_timer0) || clk_enable(&clk_timer1))
+                printk(KERN_ERR "Error enabling timer tick clocks\n");
+
+        return 0;
+}
+core_initcall(clk_init);
+
diff --git a/arch/arm/mach-lpc32xx/clock.h b/arch/arm/mach-lpc32xx/clock.h
new file mode 100644
index 000000000000..c0a8434307f7
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/clock.h
@@ -0,0 +1,38 @@
+/*
+ * arch/arm/mach-lpc32xx/clock.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_CLOCK_H
+#define __LPC32XX_CLOCK_H
+
+struct clk {
+        struct list_head node;
+        struct clk *parent;
+        u32 rate;
+        u32 usecount;
+
+        int (*set_rate) (struct clk *, unsigned long);
+        unsigned long (*round_rate) (struct clk *, unsigned long);
+        unsigned long (*get_rate) (struct clk *clk);
+        int (*enable) (struct clk *, int);
+
+        /* Register address and bit mask for simple clocks */
+        void __iomem *enable_reg;
+        u32 enable_mask;
+};
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
new file mode 100644
index 000000000000..ee24dc28e93e
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -0,0 +1,271 @@
+/*
+ * arch/arm/mach-lpc32xx/common.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/i2c-pnx.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/i2c.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Watchdog timer
+ */
+static struct resource watchdog_resources[] = {
+        [0] = {
+                .start = LPC32XX_WDTIM_BASE,
+                .end = LPC32XX_WDTIM_BASE + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device lpc32xx_watchdog_device = {
+        .name = "pnx4008-watchdog",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(watchdog_resources),
+        .resource = watchdog_resources,
+};
+
+/*
+ * I2C busses
+ */
+static struct i2c_pnx_data i2c0_data = {
+        .name = I2C_CHIP_NAME "1",
+        .base = LPC32XX_I2C1_BASE,
+        .irq = IRQ_LPC32XX_I2C_1,
+};
+
+static struct i2c_pnx_data i2c1_data = {
+        .name = I2C_CHIP_NAME "2",
+        .base = LPC32XX_I2C2_BASE,
+        .irq = IRQ_LPC32XX_I2C_2,
+};
+
+static struct i2c_pnx_data i2c2_data = {
+        .name = "USB-I2C",
+        .base = LPC32XX_OTG_I2C_BASE,
+        .irq = IRQ_LPC32XX_USB_I2C,
+};
+
+struct platform_device lpc32xx_i2c0_device = {
+        .name = "pnx-i2c",
+        .id = 0,
+        .dev = {
+                .platform_data = &i2c0_data,
+        },
+};
+
+struct platform_device lpc32xx_i2c1_device = {
+        .name = "pnx-i2c",
+        .id = 1,
+        .dev = {
+                .platform_data = &i2c1_data,
+        },
+};
+
+struct platform_device lpc32xx_i2c2_device = {
+        .name = "pnx-i2c",
+        .id = 2,
+        .dev = {
+                .platform_data = &i2c2_data,
+        },
+};
+
+/*
+ * Returns the unique ID for the device
+ */
+void lpc32xx_get_uid(u32 devid[4])
+{
+        int i;
+
+        for (i = 0; i < 4; i++)
+                devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
+}
+
+/*
+ * Returns SYSCLK source
+ * 0 = PLL397, 1 = main oscillator
+ */
+int clk_is_sysclk_mainosc(void)
+{
+        if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
+                LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
+                return 1;
+
+        return 0;
+}
+
+/*
+ * System reset via the watchdog timer
+ */
+void lpc32xx_watchdog_reset(void)
+{
+        /* Make sure WDT clocks are enabled */
+        __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
+                LPC32XX_CLKPWR_TIMER_CLK_CTRL);
+
+        /* Instant assert of RESETOUT_N with pulse length 1mS */
+        __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
+        __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
+}
+
+/*
+ * Detects and returns IRAM size for the device variation
+ */
+#define LPC32XX_IRAM_BANK_SIZE SZ_128K
+static u32 iram_size;
+u32 lpc32xx_return_iram_size(void)
+{
+        if (iram_size == 0) {
+                u32 savedval1, savedval2;
+                void __iomem *iramptr1, *iramptr2;
+
+                iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
+                iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
+                savedval1 = __raw_readl(iramptr1);
+                savedval2 = __raw_readl(iramptr2);
+
+                if (savedval1 == savedval2) {
+                        __raw_writel(savedval2 + 1, iramptr2);
+                        if (__raw_readl(iramptr1) == savedval2 + 1)
+                                iram_size = LPC32XX_IRAM_BANK_SIZE;
+                        else
+                                iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+                        __raw_writel(savedval2, iramptr2);
+                } else
+                        iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
+        }
+
+        return iram_size;
+}
+
+/*
+ * Computes PLL rate from PLL register and input clock
+ */
+u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
+{
+        u32 ilfreq, p, m, n, fcco, fref, cfreq;
+        int mode;
+
+        /*
+         * PLL requirements
+         * ifreq must be >= 1MHz and <= 20MHz
+         * FCCO must be >= 156MHz and <= 320MHz
+         * FREF must be >= 1MHz and <= 27MHz
+         * Assume the passed input data is not valid
+         */
+
+        ilfreq = ifreq;
+        m = pllsetup->pll_m;
+        n = pllsetup->pll_n;
+        p = pllsetup->pll_p;
+
+        mode = (pllsetup->cco_bypass_b15 << 2) |
+                (pllsetup->direct_output_b14 << 1) |
+        pllsetup->fdbk_div_ctrl_b13;
+
+        switch (mode) {
+        case 0x0: /* Non-integer mode */
+                cfreq = (m * ilfreq) / (2 * p * n);
+                fcco = (m * ilfreq) / n;
+                fref = ilfreq / n;
+                break;
+
+        case 0x1: /* integer mode */
+                cfreq = (m * ilfreq) / n;
+                fcco = (m * ilfreq) / (n * 2 * p);
+                fref = ilfreq / n;
+                break;
+
+        case 0x2:
+        case 0x3: /* Direct mode */
+                cfreq = (m * ilfreq) / n;
+                fcco = cfreq;
+                fref = ilfreq / n;
+                break;
+
+        case 0x4:
+        case 0x5: /* Bypass mode */
+                cfreq = ilfreq / (2 * p);
+                fcco = 156000000;
+                fref = 1000000;
+                break;
+
+        case 0x6:
+        case 0x7: /* Direct bypass mode */
+        default:
+                cfreq = ilfreq;
+                fcco = 156000000;
+                fref = 1000000;
+                break;
+        }
+
+        if (fcco < 156000000 || fcco > 320000000)
+                cfreq = 0;
+
+        if (fref < 1000000 || fref > 27000000)
+                cfreq = 0;
+
+        return (u32) cfreq;
+}
+
+u32 clk_get_pclk_div(void)
+{
+        return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
+}
+
+static struct map_desc lpc32xx_io_desc[] __initdata = {
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
+                .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
+                .length         = LPC32XX_AHB0_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
+                .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
+                .length         = LPC32XX_AHB1_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
+                .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
+                .length         = LPC32XX_FABAPB_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
+                .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
+                .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
+                .type           = MT_DEVICE
+        },
+};
+
+void __init lpc32xx_map_io(void)
+{
+        iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
+}
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
new file mode 100644
index 000000000000..f82211fd80c1
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -0,0 +1,73 @@
+/*
+ * arch/arm/mach-lpc32xx/common.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009-2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LPC32XX_COMMON_H
+#define __LPC32XX_COMMON_H
+
+#include <linux/platform_device.h>
+
+/*
+ * Arch specific platform device structures
+ */
+extern struct platform_device lpc32xx_watchdog_device;
+extern struct platform_device lpc32xx_i2c0_device;
+extern struct platform_device lpc32xx_i2c1_device;
+extern struct platform_device lpc32xx_i2c2_device;
+
+/*
+ * Other arch specific structures and functions
+ */
+extern struct sys_timer lpc32xx_timer;
+extern void __init lpc32xx_init_irq(void);
+extern void __init lpc32xx_map_io(void);
+extern void __init lpc32xx_serial_init(void);
+extern void __init lpc32xx_gpio_init(void);
+
+/*
+ * Structure used for setting up and querying the PLLS
+ */
+struct clk_pll_setup {
+        int analog_on;
+        int cco_bypass_b15;
+        int direct_output_b14;
+        int fdbk_div_ctrl_b13;
+        int pll_p;
+        int pll_n;
+        u32 pll_m;
+};
+
+extern int clk_is_sysclk_mainosc(void);
+extern u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup);
+extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
+extern u32 clk_get_pclk_div(void);
+
+/*
+ * Returns the LPC32xx unique 128-bit chip ID
+ */
+extern void lpc32xx_get_uid(u32 devid[4]);
+
+extern void lpc32xx_watchdog_reset(void);
+extern u32 lpc32xx_return_iram_size(void);
+
+/*
+ * Pointers used for sizing and copying suspend function data
+ */
+extern int lpc32xx_sys_suspend(void);
+extern int lpc32xx_sys_suspend_sz;
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/gpiolib.c b/arch/arm/mach-lpc32xx/gpiolib.c
new file mode 100644
index 000000000000..69061ea8997a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/gpiolib.c
@@ -0,0 +1,446 @@
+/*
+ * arch/arm/mach-lpc32xx/gpiolib.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_GPIO_P3_INP_STATE               _GPREG(0x000)
+#define LPC32XX_GPIO_P3_OUTP_SET                _GPREG(0x004)
+#define LPC32XX_GPIO_P3_OUTP_CLR                _GPREG(0x008)
+#define LPC32XX_GPIO_P3_OUTP_STATE              _GPREG(0x00C)
+#define LPC32XX_GPIO_P2_DIR_SET                 _GPREG(0x010)
+#define LPC32XX_GPIO_P2_DIR_CLR                 _GPREG(0x014)
+#define LPC32XX_GPIO_P2_DIR_STATE               _GPREG(0x018)
+#define LPC32XX_GPIO_P2_INP_STATE               _GPREG(0x01C)
+#define LPC32XX_GPIO_P2_OUTP_SET                _GPREG(0x020)
+#define LPC32XX_GPIO_P2_OUTP_CLR                _GPREG(0x024)
+#define LPC32XX_GPIO_P2_MUX_SET                 _GPREG(0x028)
+#define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
+#define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
+#define LPC32XX_GPIO_P0_INP_STATE               _GPREG(0x040)
+#define LPC32XX_GPIO_P0_OUTP_SET                _GPREG(0x044)
+#define LPC32XX_GPIO_P0_OUTP_CLR                _GPREG(0x048)
+#define LPC32XX_GPIO_P0_OUTP_STATE              _GPREG(0x04C)
+#define LPC32XX_GPIO_P0_DIR_SET                 _GPREG(0x050)
+#define LPC32XX_GPIO_P0_DIR_CLR                 _GPREG(0x054)
+#define LPC32XX_GPIO_P0_DIR_STATE               _GPREG(0x058)
+#define LPC32XX_GPIO_P1_INP_STATE               _GPREG(0x060)
+#define LPC32XX_GPIO_P1_OUTP_SET                _GPREG(0x064)
+#define LPC32XX_GPIO_P1_OUTP_CLR                _GPREG(0x068)
+#define LPC32XX_GPIO_P1_OUTP_STATE              _GPREG(0x06C)
+#define LPC32XX_GPIO_P1_DIR_SET                 _GPREG(0x070)
+#define LPC32XX_GPIO_P1_DIR_CLR                 _GPREG(0x074)
+#define LPC32XX_GPIO_P1_DIR_STATE               _GPREG(0x078)
+
+#define GPIO012_PIN_TO_BIT(x)                   (1 << (x))
+#define GPIO3_PIN_TO_BIT(x)                     (1 << ((x) + 25))
+#define GPO3_PIN_TO_BIT(x)                      (1 << (x))
+#define GPIO012_PIN_IN_SEL(x, y)                (((x) >> (y)) & 1)
+#define GPIO3_PIN_IN_SHIFT(x)                   ((x) == 5 ? 24 : 10 + (x))
+#define GPIO3_PIN_IN_SEL(x, y)                  ((x) >> GPIO3_PIN_IN_SHIFT(y))
+#define GPIO3_PIN5_IN_SEL(x)                    (((x) >> 24) & 1)
+#define GPI3_PIN_IN_SEL(x, y)                   (((x) >> (y)) & 1)
+
+struct gpio_regs {
+        void __iomem *inp_state;
+        void __iomem *outp_set;
+        void __iomem *outp_clr;
+        void __iomem *dir_set;
+        void __iomem *dir_clr;
+};
+
+/*
+ * GPIO names
+ */
+static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
+        "p0.0", "p0.1", "p0.2", "p0.3",
+        "p0.4", "p0.5", "p0.6", "p0.7"
+};
+
+static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = {
+        "p1.0", "p1.1", "p1.2", "p1.3",
+        "p1.4", "p1.5", "p1.6", "p1.7",
+        "p1.8", "p1.9", "p1.10", "p1.11",
+        "p1.12", "p1.13", "p1.14", "p1.15",
+        "p1.16", "p1.17", "p1.18", "p1.19",
+        "p1.20", "p1.21", "p1.22", "p1.23",
+};
+
+static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = {
+        "p2.0", "p2.1", "p2.2", "p2.3",
+        "p2.4", "p2.5", "p2.6", "p2.7",
+        "p2.8", "p2.9", "p2.10", "p2.11",
+        "p2.12"
+};
+
+static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = {
+        "gpi000", "gpio01", "gpio02", "gpio03",
+        "gpio04", "gpio05"
+};
+
+static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = {
+        "gpi00", "gpi01", "gpi02", "gpi03",
+        "gpi04", "gpi05", "gpi06", "gpi07",
+        "gpi08", "gpi09",  NULL,    NULL,
+         NULL,    NULL,    NULL,   "gpi15",
+        "gpi16", "gpi17", "gpi18", "gpi19",
+        "gpi20", "gpi21", "gpi22", "gpi23",
+        "gpi24", "gpi25", "gpi26", "gpi27"
+};
+
+static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = {
+        "gpo00", "gpo01", "gpo02", "gpo03",
+        "gpo04", "gpo05", "gpo06", "gpo07",
+        "gpo08", "gpo09", "gpo10", "gpo11",
+        "gpo12", "gpo13", "gpo14", "gpo15",
+        "gpo16", "gpo17", "gpo18", "gpo19",
+        "gpo20", "gpo21", "gpo22", "gpo23"
+};
+
+static struct gpio_regs gpio_grp_regs_p0 = {
+        .inp_state      = LPC32XX_GPIO_P0_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P0_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P0_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P0_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P0_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p1 = {
+        .inp_state      = LPC32XX_GPIO_P1_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P1_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P1_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P1_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P1_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p2 = {
+        .inp_state      = LPC32XX_GPIO_P2_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P2_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P2_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+static struct gpio_regs gpio_grp_regs_p3 = {
+        .inp_state      = LPC32XX_GPIO_P3_INP_STATE,
+        .outp_set       = LPC32XX_GPIO_P3_OUTP_SET,
+        .outp_clr       = LPC32XX_GPIO_P3_OUTP_CLR,
+        .dir_set        = LPC32XX_GPIO_P2_DIR_SET,
+        .dir_clr        = LPC32XX_GPIO_P2_DIR_CLR,
+};
+
+struct lpc32xx_gpio_chip {
+        struct gpio_chip        chip;
+        struct gpio_regs        *gpio_grp;
+};
+
+static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio(
+        struct gpio_chip *gpc)
+{
+        return container_of(gpc, struct lpc32xx_gpio_chip, chip);
+}
+
+static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int input)
+{
+        if (input)
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->dir_clr);
+        else
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int input)
+{
+        u32 u = GPIO3_PIN_TO_BIT(pin);
+
+        if (input)
+                __raw_writel(u, group->gpio_grp->dir_clr);
+        else
+                __raw_writel(u, group->gpio_grp->dir_set);
+}
+
+static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        if (high)
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->outp_set);
+        else
+                __raw_writel(GPIO012_PIN_TO_BIT(pin),
+                        group->gpio_grp->outp_clr);
+}
+
+static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        u32 u = GPIO3_PIN_TO_BIT(pin);
+
+        if (high)
+                __raw_writel(u, group->gpio_grp->outp_set);
+        else
+                __raw_writel(u, group->gpio_grp->outp_clr);
+}
+
+static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin, int high)
+{
+        if (high)
+                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
+        else
+                __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
+}
+
+static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
+                pin);
+}
+
+static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        int state = __raw_readl(group->gpio_grp->inp_state);
+
+        /*
+         * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
+         * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
+         */
+        return GPIO3_PIN_IN_SEL(state, pin);
+}
+
+static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
+        unsigned pin)
+{
+        return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
+        unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p012(group, pin, 1);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip,
+        unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p3(group, pin, 1);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip,
+        unsigned pin)
+{
+        return 0;
+}
+
+static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpio_state_p012(group, pin);
+}
+
+static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpio_state_p3(group, pin);
+}
+
+static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        return __get_gpi_state_p3(group, pin);
+}
+
+static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p012(group, pin, 0);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_dir_p3(group, pin, 0);
+
+        return 0;
+}
+
+static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        return 0;
+}
+
+static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_level_p012(group, pin, value);
+}
+
+static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpio_level_p3(group, pin, value);
+}
+
+static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin,
+        int value)
+{
+        struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip);
+
+        __set_gpo_level_p3(group, pin, value);
+}
+
+static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        if (pin < chip->ngpio)
+                return 0;
+
+        return -EINVAL;
+}
+
+static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = {
+        {
+                .chip = {
+                        .label                  = "gpio_p0",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P0_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P0_MAX,
+                        .names                  = gpio_p0_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p0,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p1",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P1_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P1_MAX,
+                        .names                  = gpio_p1_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p1,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p2",
+                        .direction_input        = lpc32xx_gpio_dir_input_p012,
+                        .get                    = lpc32xx_gpio_get_value_p012,
+                        .direction_output       = lpc32xx_gpio_dir_output_p012,
+                        .set                    = lpc32xx_gpio_set_value_p012,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P2_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P2_MAX,
+                        .names                  = gpio_p2_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p2,
+        },
+        {
+                .chip = {
+                        .label                  = "gpio_p3",
+                        .direction_input        = lpc32xx_gpio_dir_input_p3,
+                        .get                    = lpc32xx_gpio_get_value_p3,
+                        .direction_output       = lpc32xx_gpio_dir_output_p3,
+                        .set                    = lpc32xx_gpio_set_value_p3,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPIO_P3_GRP,
+                        .ngpio                  = LPC32XX_GPIO_P3_MAX,
+                        .names                  = gpio_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+        {
+                .chip = {
+                        .label                  = "gpi_p3",
+                        .direction_input        = lpc32xx_gpio_dir_in_always,
+                        .get                    = lpc32xx_gpi_get_value,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPI_P3_GRP,
+                        .ngpio                  = LPC32XX_GPI_P3_MAX,
+                        .names                  = gpi_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+        {
+                .chip = {
+                        .label                  = "gpo_p3",
+                        .direction_output       = lpc32xx_gpio_dir_out_always,
+                        .set                    = lpc32xx_gpo_set_value,
+                        .request                = lpc32xx_gpio_request,
+                        .base                   = LPC32XX_GPO_P3_GRP,
+                        .ngpio                  = LPC32XX_GPO_P3_MAX,
+                        .names                  = gpo_p3_names,
+                        .can_sleep              = 0,
+                },
+                .gpio_grp = &gpio_grp_regs_p3,
+        },
+};
+
+void __init lpc32xx_gpio_init(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++)
+                gpiochip_add(&lpc32xx_gpiochip[i].chip);
+}
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
index 13411709b13a..9bf0637e29ce 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/clkdev.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
-#define __ASM_ARCH_MXC_BOARD_PCM037_H__
+#ifndef __ASM_ARCH_CLKDEV_H
+#define __ASM_ARCH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 383f1c04df06..621744d6b152 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -1,5 +1,9 @@
 /*
- *  Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
+ * arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,18 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
+/*
+ * Debug output is hardcoded to standard UART 5
+*/
+
+        .macro  addruart,rx, tmp
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                         @ MMU enabled?
+        ldreq   \rx, =0x40090000
+        ldrne   \rx, =0xF4090000
+        .endm
 
-#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-lpc32xx/include/mach/entry-macro.S b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
new file mode 100644
index 000000000000..870227c96602
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/entry-macro.S
@@ -0,0 +1,47 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/entry-macro.S
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+#define LPC32XX_INTC_MASKED_STATUS_OFS  0x8
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IO_ADDRESS(LPC32XX_MIC_BASE)
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+/*
+ * Return IRQ number in irqnr. Also return processor Z flag status in CPSR
+ * as set if an interrupt is pending.
+ */
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #LPC32XX_INTC_MASKED_STATUS_OFS]
+        clz     \irqnr, \irqstat
+        rsb     \irqnr, \irqnr, #31
+        teq     \irqstat, #0
+        .endm
+
+        .macro  irq_prio_table
+        .endm
+
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
new file mode 100644
index 000000000000..67d03da1eee9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -0,0 +1,74 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/gpio.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#include <asm-generic/gpio.h>
+
+/*
+ * Note!
+ * Muxed GP pins need to be setup to the GP state in the board level
+ * code prior to using this driver.
+ * GPI pins : 28xP3 group
+ * GPO pins : 24xP3 group
+ * GPIO pins: 8xP0 group, 24xP1 group, 13xP2 group, 6xP3 group
+ */
+
+#define LPC32XX_GPIO_P0_MAX 8
+#define LPC32XX_GPIO_P1_MAX 24
+#define LPC32XX_GPIO_P2_MAX 13
+#define LPC32XX_GPIO_P3_MAX 6
+#define LPC32XX_GPI_P3_MAX 28
+#define LPC32XX_GPO_P3_MAX 24
+
+#define LPC32XX_GPIO_P0_GRP 0
+#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
+#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
+#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
+#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
+#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
+
+/*
+ * A specific GPIO can be selected with this macro
+ * ie, GPIO_05 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+ * See the LPC32x0 User's guide for GPIO group numbers
+ */
+#define LPC32XX_GPIO(x, y) ((x) + (y))
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned gpio)
+{
+        return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return __gpio_to_irq(gpio);
+}
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/hardware.h b/arch/arm/mach-lpc32xx/include/mach/hardware.h
new file mode 100644
index 000000000000..33e1dde37bd9
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/hardware.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/hardware.h
+ *
+ * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * Start of virtual addresses for IO devices
+ */
+#define IO_BASE         0xF0000000
+
+/*
+ * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
+ */
+#define IO_ADDRESS(x)   (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
+                         IO_BASE)
+
+#define io_p2v(x)       ((void __iomem *) (unsigned long) IO_ADDRESS(x))
+#define io_v2p(x)       ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/i2c.h b/arch/arm/mach-lpc32xx/include/mach/i2c.h
new file mode 100644
index 000000000000..034dc9286bcc
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/i2c.h
@@ -0,0 +1,63 @@
+/*
+ * PNX4008-specific tweaks for I2C IP3204 block
+ *
+ * Author: Vitaly Wool <vwool@ru.mvista.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+enum {
+        mstatus_tdi = 0x00000001,
+        mstatus_afi = 0x00000002,
+        mstatus_nai = 0x00000004,
+        mstatus_drmi = 0x00000008,
+        mstatus_active = 0x00000020,
+        mstatus_scl = 0x00000040,
+        mstatus_sda = 0x00000080,
+        mstatus_rff = 0x00000100,
+        mstatus_rfe = 0x00000200,
+        mstatus_tff = 0x00000400,
+        mstatus_tfe = 0x00000800,
+};
+
+enum {
+        mcntrl_tdie = 0x00000001,
+        mcntrl_afie = 0x00000002,
+        mcntrl_naie = 0x00000004,
+        mcntrl_drmie = 0x00000008,
+        mcntrl_daie = 0x00000020,
+        mcntrl_rffie = 0x00000040,
+        mcntrl_tffie = 0x00000080,
+        mcntrl_reset = 0x00000100,
+        mcntrl_cdbmode = 0x00000400,
+};
+
+enum {
+        rw_bit = 1 << 0,
+        start_bit = 1 << 8,
+        stop_bit = 1 << 9,
+};
+
+#define I2C_REG_RX(a)   ((a)->ioaddr)           /* Rx FIFO reg (RO) */
+#define I2C_REG_TX(a)   ((a)->ioaddr)           /* Tx FIFO reg (WO) */
+#define I2C_REG_STS(a)  ((a)->ioaddr + 0x04)    /* Status reg (RO) */
+#define I2C_REG_CTL(a)  ((a)->ioaddr + 0x08)    /* Ctl reg */
+#define I2C_REG_CKL(a)  ((a)->ioaddr + 0x0c)    /* Clock divider low */
+#define I2C_REG_CKH(a)  ((a)->ioaddr + 0x10)    /* Clock divider high */
+#define I2C_REG_ADR(a)  ((a)->ioaddr + 0x14)    /* I2C address */
+#define I2C_REG_RFL(a)  ((a)->ioaddr + 0x18)    /* Rx FIFO level (RO) */
+#define I2C_REG_TFL(a)  ((a)->ioaddr + 0x1c)    /* Tx FIFO level (RO) */
+#define I2C_REG_RXB(a)  ((a)->ioaddr + 0x20)    /* Num of bytes Rx-ed (RO) */
+#define I2C_REG_TXB(a)  ((a)->ioaddr + 0x24)    /* Num of bytes Tx-ed (RO) */
+#define I2C_REG_TXS(a)  ((a)->ioaddr + 0x28)    /* Tx slave FIFO (RO) */
+#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c)    /* Tx slave FIFO level (RO) */
+
+#define I2C_CHIP_NAME           "PNX4008-I2C"
+
+#endif                          /* __ASM_ARCH_I2C_H */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/mach-lpc32xx/include/mach/io.h
index 1ac4e1682e5c..9b59ab5cef89 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/mach-lpc32xx/include/mach/io.h
@@ -1,5 +1,9 @@
 /*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
+ * arch/arm/mach-lpc32xx/include/mach/io.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -10,13 +14,14 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
-#define __ASM_ARCH_MXC_BOARD_PCM043_H__
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT  0xffffffff
+
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
 
-#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/irqs.h b/arch/arm/mach-lpc32xx/include/mach/irqs.h
new file mode 100644
index 000000000000..2667f52e3b04
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/irqs.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/irqs.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_IRQS_H
+#define __ASM_ARM_ARCH_IRQS_H
+
+#define LPC32XX_SIC1_IRQ(n)             (32 + (n))
+#define LPC32XX_SIC2_IRQ(n)             (64 + (n))
+
+/*
+ * MIC interrupts
+ */
+#define IRQ_LPC32XX_SUB1IRQ             0
+#define IRQ_LPC32XX_SUB2IRQ             1
+#define IRQ_LPC32XX_PWM3                3
+#define IRQ_LPC32XX_PWM4                4
+#define IRQ_LPC32XX_HSTIMER             5
+#define IRQ_LPC32XX_WATCH               6
+#define IRQ_LPC32XX_UART_IIR3           7
+#define IRQ_LPC32XX_UART_IIR4           8
+#define IRQ_LPC32XX_UART_IIR5           9
+#define IRQ_LPC32XX_UART_IIR6           10
+#define IRQ_LPC32XX_FLASH               11
+#define IRQ_LPC32XX_SD1                 13
+#define IRQ_LPC32XX_LCD                 14
+#define IRQ_LPC32XX_SD0                 15
+#define IRQ_LPC32XX_TIMER0              16
+#define IRQ_LPC32XX_TIMER1              17
+#define IRQ_LPC32XX_TIMER2              18
+#define IRQ_LPC32XX_TIMER3              19
+#define IRQ_LPC32XX_SSP0                20
+#define IRQ_LPC32XX_SSP1                21
+#define IRQ_LPC32XX_I2S0                22
+#define IRQ_LPC32XX_I2S1                23
+#define IRQ_LPC32XX_UART_IIR7           24
+#define IRQ_LPC32XX_UART_IIR2           25
+#define IRQ_LPC32XX_UART_IIR1           26
+#define IRQ_LPC32XX_MSTIMER             27
+#define IRQ_LPC32XX_DMA                 28
+#define IRQ_LPC32XX_ETHERNET            29
+#define IRQ_LPC32XX_SUB1FIQ             30
+#define IRQ_LPC32XX_SUB2FIQ             31
+
+/*
+ * SIC1 interrupts start at offset 32
+ */
+#define IRQ_LPC32XX_JTAG_COMM_TX        LPC32XX_SIC1_IRQ(1)
+#define IRQ_LPC32XX_JTAG_COMM_RX        LPC32XX_SIC1_IRQ(2)
+#define IRQ_LPC32XX_GPI_11              LPC32XX_SIC1_IRQ(4)
+#define IRQ_LPC32XX_TS_P                LPC32XX_SIC1_IRQ(6)
+#define IRQ_LPC32XX_TS_IRQ              LPC32XX_SIC1_IRQ(7)
+#define IRQ_LPC32XX_TS_AUX              LPC32XX_SIC1_IRQ(8)
+#define IRQ_LPC32XX_SPI2                LPC32XX_SIC1_IRQ(12)
+#define IRQ_LPC32XX_PLLUSB              LPC32XX_SIC1_IRQ(13)
+#define IRQ_LPC32XX_PLLHCLK             LPC32XX_SIC1_IRQ(14)
+#define IRQ_LPC32XX_PLL397              LPC32XX_SIC1_IRQ(17)
+#define IRQ_LPC32XX_I2C_2               LPC32XX_SIC1_IRQ(18)
+#define IRQ_LPC32XX_I2C_1               LPC32XX_SIC1_IRQ(19)
+#define IRQ_LPC32XX_RTC                 LPC32XX_SIC1_IRQ(20)
+#define IRQ_LPC32XX_KEY                 LPC32XX_SIC1_IRQ(22)
+#define IRQ_LPC32XX_SPI1                LPC32XX_SIC1_IRQ(23)
+#define IRQ_LPC32XX_SW                  LPC32XX_SIC1_IRQ(24)
+#define IRQ_LPC32XX_USB_OTG_TIMER       LPC32XX_SIC1_IRQ(25)
+#define IRQ_LPC32XX_USB_OTG_ATX         LPC32XX_SIC1_IRQ(26)
+#define IRQ_LPC32XX_USB_HOST            LPC32XX_SIC1_IRQ(27)
+#define IRQ_LPC32XX_USB_DEV_DMA         LPC32XX_SIC1_IRQ(28)
+#define IRQ_LPC32XX_USB_DEV_LP          LPC32XX_SIC1_IRQ(29)
+#define IRQ_LPC32XX_USB_DEV_HP          LPC32XX_SIC1_IRQ(30)
+#define IRQ_LPC32XX_USB_I2C             LPC32XX_SIC1_IRQ(31)
+
+/*
+ * SIC2 interrupts start at offset 64
+ */
+#define IRQ_LPC32XX_GPIO_00             LPC32XX_SIC2_IRQ(0)
+#define IRQ_LPC32XX_GPIO_01             LPC32XX_SIC2_IRQ(1)
+#define IRQ_LPC32XX_GPIO_02             LPC32XX_SIC2_IRQ(2)
+#define IRQ_LPC32XX_GPIO_03             LPC32XX_SIC2_IRQ(3)
+#define IRQ_LPC32XX_GPIO_04             LPC32XX_SIC2_IRQ(4)
+#define IRQ_LPC32XX_GPIO_05             LPC32XX_SIC2_IRQ(5)
+#define IRQ_LPC32XX_SPI2_DATAIN         LPC32XX_SIC2_IRQ(6)
+#define IRQ_LPC32XX_U2_HCTS             LPC32XX_SIC2_IRQ(7)
+#define IRQ_LPC32XX_P0_P1_IRQ           LPC32XX_SIC2_IRQ(8)
+#define IRQ_LPC32XX_GPI_08              LPC32XX_SIC2_IRQ(9)
+#define IRQ_LPC32XX_GPI_09              LPC32XX_SIC2_IRQ(10)
+#define IRQ_LPC32XX_GPI_19              LPC32XX_SIC2_IRQ(11)
+#define IRQ_LPC32XX_U7_HCTS             LPC32XX_SIC2_IRQ(12)
+#define IRQ_LPC32XX_GPI_07              LPC32XX_SIC2_IRQ(15)
+#define IRQ_LPC32XX_SDIO                LPC32XX_SIC2_IRQ(18)
+#define IRQ_LPC32XX_U5_RX               LPC32XX_SIC2_IRQ(19)
+#define IRQ_LPC32XX_SPI1_DATAIN         LPC32XX_SIC2_IRQ(20)
+#define IRQ_LPC32XX_GPI_00              LPC32XX_SIC2_IRQ(22)
+#define IRQ_LPC32XX_GPI_01              LPC32XX_SIC2_IRQ(23)
+#define IRQ_LPC32XX_GPI_02              LPC32XX_SIC2_IRQ(24)
+#define IRQ_LPC32XX_GPI_03              LPC32XX_SIC2_IRQ(25)
+#define IRQ_LPC32XX_GPI_04              LPC32XX_SIC2_IRQ(26)
+#define IRQ_LPC32XX_GPI_05              LPC32XX_SIC2_IRQ(27)
+#define IRQ_LPC32XX_GPI_06              LPC32XX_SIC2_IRQ(28)
+#define IRQ_LPC32XX_SYSCLK              LPC32XX_SIC2_IRQ(31)
+
+#define NR_IRQS                         96
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
new file mode 100644
index 000000000000..044e1acecbe6
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/memory.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/memory.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset of bank 0
+ */
+#define PHYS_OFFSET     UL(0x80000000)
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
new file mode 100644
index 000000000000..14ea8d1aadb5
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -0,0 +1,694 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/platform.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_PLATFORM_H
+#define __ASM_ARCH_PLATFORM_H
+
+#define _SBF(f, v)                              ((v) << (f))
+#define _BIT(n)                                 _SBF(n, 1)
+
+/*
+ * AHB 0 physical base addresses
+ */
+#define LPC32XX_SLC_BASE                        0x20020000
+#define LPC32XX_SSP0_BASE                       0x20084000
+#define LPC32XX_SPI1_BASE                       0x20088000
+#define LPC32XX_SSP1_BASE                       0x2008C000
+#define LPC32XX_SPI2_BASE                       0x20090000
+#define LPC32XX_I2S0_BASE                       0x20094000
+#define LPC32XX_SD_BASE                         0x20098000
+#define LPC32XX_I2S1_BASE                       0x2009C000
+#define LPC32XX_MLC_BASE                        0x200A8000
+#define LPC32XX_AHB0_START                      LPC32XX_SLC_BASE
+#define LPC32XX_AHB0_SIZE                       0x00089000
+
+/*
+ * AHB 1 physical base addresses
+ */
+#define LPC32XX_DMA_BASE                        0x31000000
+#define LPC32XX_USB_BASE                        0x31020000
+#define LPC32XX_USBH_BASE                       0x31020000
+#define LPC32XX_USB_OTG_BASE                    0x31020000
+#define LPC32XX_OTG_I2C_BASE                    0x31020300
+#define LPC32XX_LCD_BASE                        0x31040000
+#define LPC32XX_ETHERNET_BASE                   0x31060000
+#define LPC32XX_EMC_BASE                        0x31080000
+#define LPC32XX_ETB_CFG_BASE                    0x310C0000
+#define LPC32XX_ETB_DATA_BASE                   0x310E0000
+#define LPC32XX_AHB1_START                      LPC32XX_DMA_BASE
+#define LPC32XX_AHB1_SIZE                       0x000E1000
+
+/*
+ * FAB physical base addresses
+ */
+#define LPC32XX_CLK_PM_BASE                     0x40004000
+#define LPC32XX_MIC_BASE                        0x40008000
+#define LPC32XX_SIC1_BASE                       0x4000C000
+#define LPC32XX_SIC2_BASE                       0x40010000
+#define LPC32XX_HS_UART1_BASE                   0x40014000
+#define LPC32XX_HS_UART2_BASE                   0x40018000
+#define LPC32XX_HS_UART7_BASE                   0x4001C000
+#define LPC32XX_RTC_BASE                        0x40024000
+#define LPC32XX_RTC_RAM_BASE                    0x40024080
+#define LPC32XX_GPIO_BASE                       0x40028000
+#define LPC32XX_PWM3_BASE                       0x4002C000
+#define LPC32XX_PWM4_BASE                       0x40030000
+#define LPC32XX_MSTIM_BASE                      0x40034000
+#define LPC32XX_HSTIM_BASE                      0x40038000
+#define LPC32XX_WDTIM_BASE                      0x4003C000
+#define LPC32XX_DEBUG_CTRL_BASE                 0x40040000
+#define LPC32XX_TIMER0_BASE                     0x40044000
+#define LPC32XX_ADC_BASE                        0x40048000
+#define LPC32XX_TIMER1_BASE                     0x4004C000
+#define LPC32XX_KSCAN_BASE                      0x40050000
+#define LPC32XX_UART_CTRL_BASE                  0x40054000
+#define LPC32XX_TIMER2_BASE                     0x40058000
+#define LPC32XX_PWM1_BASE                       0x4005C000
+#define LPC32XX_PWM2_BASE                       0x4005C004
+#define LPC32XX_TIMER3_BASE                     0x40060000
+
+/*
+ * APB physical base addresses
+ */
+#define LPC32XX_UART3_BASE                      0x40080000
+#define LPC32XX_UART4_BASE                      0x40088000
+#define LPC32XX_UART5_BASE                      0x40090000
+#define LPC32XX_UART6_BASE                      0x40098000
+#define LPC32XX_I2C1_BASE                       0x400A0000
+#define LPC32XX_I2C2_BASE                       0x400A8000
+
+/*
+ * FAB and APB base and sizing
+ */
+#define LPC32XX_FABAPB_START                    LPC32XX_CLK_PM_BASE
+#define LPC32XX_FABAPB_SIZE                     0x000A5000
+
+/*
+ * Internal memory bases and sizes
+ */
+#define LPC32XX_IRAM_BASE                       0x08000000
+#define LPC32XX_IROM_BASE                       0x0C000000
+
+/*
+ * External Static Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_CS0_BASE                    0xE0000000
+#define LPC32XX_EMC_CS1_BASE                    0xE1000000
+#define LPC32XX_EMC_CS2_BASE                    0xE2000000
+#define LPC32XX_EMC_CS3_BASE                    0xE3000000
+
+/*
+ * External SDRAM Memory Bank Address Space Bases
+ */
+#define LPC32XX_EMC_DYCS0_BASE                  0x80000000
+#define LPC32XX_EMC_DYCS1_BASE                  0xA0000000
+
+/*
+ * Clock and crystal information
+ */
+#define LPC32XX_MAIN_OSC_FREQ                   13000000
+#define LPC32XX_CLOCK_OSC_FREQ                  32768
+
+/*
+ * Clock and Power control register offsets
+ */
+#define _PMREG(x)                               io_p2v(LPC32XX_CLK_PM_BASE +\
+                                                (x))
+#define LPC32XX_CLKPWR_DEBUG_CTRL               _PMREG(0x000)
+#define LPC32XX_CLKPWR_BOOTMAP                  _PMREG(0x014)
+#define LPC32XX_CLKPWR_P01_ER                   _PMREG(0x018)
+#define LPC32XX_CLKPWR_USBCLK_PDIV              _PMREG(0x01C)
+#define LPC32XX_CLKPWR_INT_ER                   _PMREG(0x020)
+#define LPC32XX_CLKPWR_INT_RS                   _PMREG(0x024)
+#define LPC32XX_CLKPWR_INT_SR                   _PMREG(0x028)
+#define LPC32XX_CLKPWR_INT_AP                   _PMREG(0x02C)
+#define LPC32XX_CLKPWR_PIN_ER                   _PMREG(0x030)
+#define LPC32XX_CLKPWR_PIN_RS                   _PMREG(0x034)
+#define LPC32XX_CLKPWR_PIN_SR                   _PMREG(0x038)
+#define LPC32XX_CLKPWR_PIN_AP                   _PMREG(0x03C)
+#define LPC32XX_CLKPWR_HCLK_DIV                 _PMREG(0x040)
+#define LPC32XX_CLKPWR_PWR_CTRL                 _PMREG(0x044)
+#define LPC32XX_CLKPWR_PLL397_CTRL              _PMREG(0x048)
+#define LPC32XX_CLKPWR_MAIN_OSC_CTRL            _PMREG(0x04C)
+#define LPC32XX_CLKPWR_SYSCLK_CTRL              _PMREG(0x050)
+#define LPC32XX_CLKPWR_LCDCLK_CTRL              _PMREG(0x054)
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL             _PMREG(0x058)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1           _PMREG(0x060)
+#define LPC32XX_CLKPWR_USB_CTRL                 _PMREG(0x064)
+#define LPC32XX_CLKPWR_SDRAMCLK_CTRL            _PMREG(0x068)
+#define LPC32XX_CLKPWR_DDR_LAP_NOM              _PMREG(0x06C)
+#define LPC32XX_CLKPWR_DDR_LAP_COUNT            _PMREG(0x070)
+#define LPC32XX_CLKPWR_DDR_LAP_DELAY            _PMREG(0x074)
+#define LPC32XX_CLKPWR_SSP_CLK_CTRL             _PMREG(0x078)
+#define LPC32XX_CLKPWR_I2S_CLK_CTRL             _PMREG(0x07C)
+#define LPC32XX_CLKPWR_MS_CTRL                  _PMREG(0x080)
+#define LPC32XX_CLKPWR_MACCLK_CTRL              _PMREG(0x090)
+#define LPC32XX_CLKPWR_TEST_CLK_SEL             _PMREG(0x0A4)
+#define LPC32XX_CLKPWR_SFW_INT                  _PMREG(0x0A8)
+#define LPC32XX_CLKPWR_I2C_CLK_CTRL             _PMREG(0x0AC)
+#define LPC32XX_CLKPWR_KEY_CLK_CTRL             _PMREG(0x0B0)
+#define LPC32XX_CLKPWR_ADC_CLK_CTRL             _PMREG(0x0B4)
+#define LPC32XX_CLKPWR_PWM_CLK_CTRL             _PMREG(0x0B8)
+#define LPC32XX_CLKPWR_TIMER_CLK_CTRL           _PMREG(0x0BC)
+#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1   _PMREG(0x0C0)
+#define LPC32XX_CLKPWR_SPI_CLK_CTRL             _PMREG(0x0C4)
+#define LPC32XX_CLKPWR_NAND_CLK_CTRL            _PMREG(0x0C8)
+#define LPC32XX_CLKPWR_UART3_CLK_CTRL           _PMREG(0x0D0)
+#define LPC32XX_CLKPWR_UART4_CLK_CTRL           _PMREG(0x0D4)
+#define LPC32XX_CLKPWR_UART5_CLK_CTRL           _PMREG(0x0D8)
+#define LPC32XX_CLKPWR_UART6_CLK_CTRL           _PMREG(0x0DC)
+#define LPC32XX_CLKPWR_IRDA_CLK_CTRL            _PMREG(0x0E0)
+#define LPC32XX_CLKPWR_UART_CLK_CTRL            _PMREG(0x0E4)
+#define LPC32XX_CLKPWR_DMA_CLK_CTRL             _PMREG(0x0E8)
+#define LPC32XX_CLKPWR_AUTOCLOCK                _PMREG(0x0EC)
+#define LPC32XX_CLKPWR_DEVID(x)                 _PMREG(0x130 + (x))
+
+/*
+ * clkpwr_debug_ctrl register definitions
+*/
+#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT     _BIT(4)
+
+/*
+ * clkpwr_bootmap register definitions
+ */
+#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT          _BIT(1)
+
+/*
+ * clkpwr_start_gpio register bit definitions
+ */
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT       _BIT(31)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT       _BIT(30)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT       _BIT(29)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT       _BIT(28)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT       _BIT(27)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT       _BIT(26)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT       _BIT(25)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT       _BIT(24)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT       _BIT(23)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT       _BIT(22)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT       _BIT(21)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT       _BIT(20)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT       _BIT(19)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT       _BIT(18)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT        _BIT(17)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT        _BIT(16)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT        _BIT(15)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT        _BIT(14)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT        _BIT(13)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT        _BIT(12)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT        _BIT(11)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT        _BIT(10)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT        _BIT(9)
+#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT        _BIT(8)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT        _BIT(7)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT        _BIT(6)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT        _BIT(5)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT        _BIT(4)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT        _BIT(3)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT        _BIT(2)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT        _BIT(1)
+#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT        _BIT(0)
+
+/*
+ * clkpwr_usbclk_pdiv register definitions
+ */
+#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK         0xF
+
+/*
+ * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
+ * clkpwr_start_pol_int, register bit definitions
+ */
+#define LPC32XX_CLKPWR_INTSRC_ADC_BIT           _BIT(31)
+#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT          _BIT(30)
+#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT        _BIT(29)
+#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT  _BIT(26)
+#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT       _BIT(25)
+#define LPC32XX_CLKPWR_INTSRC_RTC_BIT           _BIT(24)
+#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT    _BIT(23)
+#define LPC32XX_CLKPWR_INTSRC_USB_BIT           _BIT(22)
+#define LPC32XX_CLKPWR_INTSRC_I2C_BIT           _BIT(21)
+#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT   _BIT(20)
+#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT     _BIT(19)
+#define LPC32XX_CLKPWR_INTSRC_KEY_BIT           _BIT(16)
+#define LPC32XX_CLKPWR_INTSRC_MAC_BIT           _BIT(7)
+#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT          _BIT(6)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT       _BIT(3)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT       _BIT(2)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT       _BIT(1)
+#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT       _BIT(0)
+
+/*
+ * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
+ * clkpwr_start_pol_pin register bit definitions
+ */
+#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT         _BIT(31)
+#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT       _BIT(30)
+#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT       _BIT(28)
+#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT         _BIT(26)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT        _BIT(25)
+#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT         _BIT(24)
+#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT       _BIT(23)
+#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT         _BIT(22)
+#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT         _BIT(21)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT     _BIT(18)
+#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT     _BIT(17)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT        _BIT(16)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT        _BIT(15)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT        _BIT(14)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT        _BIT(13)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT        _BIT(12)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT        _BIT(11)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT        _BIT(10)
+#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT      _BIT(9)
+#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT    _BIT(8)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT        _BIT(7)
+#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT    _BIT(6)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT        _BIT(5)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT        _BIT(4)
+#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT        _BIT(3)
+
+/*
+ * clkpwr_hclk_div register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP      (0x0 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM      (0x1 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF      (0x2 << 7)
+#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n)      (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n)      ((n) & 0x3)
+
+/*
+ * clkpwr_pwr_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK          _BIT(10)
+#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH          _BIT(9)
+#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH      _BIT(8)
+#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH     _BIT(7)
+#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT       _BIT(5)
+#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT       _BIT(4)
+#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN         _BIT(3)
+#define LPC32XX_CLKPWR_SELECT_RUN_MODE          _BIT(2)
+#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN         _BIT(1)
+#define LPC32XX_CLKPWR_STOP_MODE_CTRL           _BIT(0)
+
+/*
+ * clkpwr_pll397_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS        _BIT(10)
+#define LPC32XX_CLKPWR_PLL397_BYPASS            _BIT(9)
+#define LPC32XX_CLKPWR_PLL397_BIAS_NORM         0x000
+#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5        0x040
+#define LPC32XX_CLKPWR_PLL397_BIAS_N25          0x080
+#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5        0x0C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5        0x100
+#define LPC32XX_CLKPWR_PLL397_BIAS_P25          0x140
+#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5        0x180
+#define LPC32XX_CLKPWR_PLL397_BIAS_P50          0x1C0
+#define LPC32XX_CLKPWR_PLL397_BIAS_MASK         0x1C0
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS       _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS       _BIT(0)
+
+/*
+ * clkpwr_main_osc_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n)          (((n) & 0x7F) << 2)
+#define LPC32XX_CLKPWR_MOSC_CAP_MASK            (0x7F << 2)
+#define LPC32XX_CLKPWR_TEST_MODE                _BIT(1)
+#define LPC32XX_CLKPWR_MOSC_DISABLE             _BIT(0)
+
+/*
+ * clkpwr_sysclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n)       (((n) & 0x3FF) << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK          (0x3FF << 2)
+#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397        _BIT(1)
+#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX        _BIT(0)
+
+/*
+ * clkpwr_lcdclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12    0x000
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16    0x040
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15    0x080
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24    0x0C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M    0x100
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C    0x140
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M   0x180
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C   0x1C0
+#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK      0x01C0
+#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN           0x020
+#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n)    ((n - 1) & 0x1F)
+#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK       0x001F
+
+/*
+ * clkpwr_hclkpll_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP         _BIT(16)
+#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS       _BIT(15)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS   _BIT(14)
+#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK    _BIT(13)
+#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n)  (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n)  (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n)          (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS          _BIT(0)
+
+/*
+ * clkpwr_adc_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n)        (((n) & 0xFF) << 0)
+#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL        _BIT(8)
+
+/*
+ * clkpwr_usb_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN          _BIT(24)
+#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN        _BIT(23)
+#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN       _BIT(22)
+#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN      _BIT(21)
+#define LPC32XX_CLKPWR_USBCTRL_PU_ADD           (0x0 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER       (0x1 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_PD_ADD           (0x3 << 19)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2          _BIT(18)
+#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1          _BIT(17)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP        _BIT(16)
+#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS       _BIT(15)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS   _BIT(14)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK    _BIT(13)
+#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n)  (((n) & 0x3) << 11)
+#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n)  (((n) & 0x3) << 9)
+#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n)    (((n) & 0xFF) << 1)
+#define LPC32XX_CLKPWR_USBCTRL_PLL_STS          _BIT(0)
+
+/*
+ * clkpwr_sdramclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK      _BIT(22)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW          _BIT(21)
+#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT      _BIT(20)
+#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET      _BIT(19)
+#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n)       (((n) & 0x1F) << 14)
+#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS      _BIT(13)
+#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n)      (((n) & 0x7) << 10)
+#define LPC32XX_CLKPWR_SDRCLK_USE_CAL           _BIT(9)
+#define LPC32XX_CLKPWR_SDRCLK_DO_CAL            _BIT(8)
+#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC        _BIT(7)
+#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n)        (((n) & 0x1F) << 2)
+#define LPC32XX_CLKPWR_SDRCLK_USE_DDR           _BIT(1)
+#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS           _BIT(0)
+
+/*
+ * clkpwr_ssp_blk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX       _BIT(5)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX       _BIT(4)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX       _BIT(3)
+#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX       _BIT(2)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN       _BIT(1)
+#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN       _BIT(0)
+
+/*
+ * clkpwr_i2s_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX   _BIT(6)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX   _BIT(5)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA     _BIT(4)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX   _BIT(3)
+#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX   _BIT(2)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN       _BIT(1)
+#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN       _BIT(0)
+
+/*
+ * clkpwr_ms_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS     _BIT(10)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN       _BIT(9)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS       _BIT(8)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS        _BIT(7)
+#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS        _BIT(6)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN         _BIT(5)
+#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n)     ((n) & 0xF)
+
+/*
+ * clkpwr_macclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS      0x00
+#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS     0x08
+#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS    0x18
+#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK         0x18
+#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN        _BIT(2)
+#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN       _BIT(1)
+#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN        _BIT(0)
+
+/*
+ * clkpwr_test_clk_sel register definitions
+ */
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK      (0x0 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC         (0x1 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC        (0x2 << 5)
+#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK        (0x3 << 5)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN      _BIT(4)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK        (0x0 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK      (0x1 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK      (0x2 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC        (0x5 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397      (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK        (0x7 << 1)
+#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN      _BIT(0)
+
+/*
+ * clkpwr_sw_int register definitions
+ */
+#define LPC32XX_CLKPWR_SW_INT(n)                (_BIT(0) | (((n) & 0x7F) << 1))
+#define LPC32XX_CLKPWR_SW_GET_ARG(n)            (((n) & 0xFE) >> 1)
+
+/*
+ * clkpwr_i2c_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE    _BIT(4)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE      _BIT(3)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE      _BIT(2)
+#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN        _BIT(1)
+#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN        _BIT(0)
+
+/*
+ * clkpwr_key_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN        0x1
+
+/*
+ * clkpwr_adc_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN      0x1
+
+/*
+ * clkpwr_pwm_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n)       (((n) & 0xF) << 8)
+#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n)       (((n) & 0xF) << 4)
+#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK      0x8
+#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN        0x4
+#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK      0x2
+#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN        0x1
+
+/*
+ * clkpwr_timer_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN        0x2
+#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN           0x1
+
+/*
+ * clkpwr_timers_pwms_clk_ctrl_1 register definitions
+ */
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN      0x20
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN      0x10
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN      0x08
+#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN      0x04
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN        0x02
+#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN        0x01
+
+/*
+ * clkpwr_spi_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO     0x80
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK       0x40
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI2          0x20
+#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN        0x10
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO     0x08
+#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK       0x04
+#define LPC32XX_CLKPWR_SPICLK_USE_SPI1          0x02
+#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN        0x01
+
+/*
+ * clkpwr_nand_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC       0x20
+#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB          0x10
+#define LPC32XX_CLKPWR_NANDCLK_DMA_INT          0x08
+#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC          0x04
+#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN        0x02
+#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN        0x01
+
+/*
+ * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
+ * and clkpwr_uart6_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UART_Y_DIV(y)            ((y) & 0xFF)
+#define LPC32XX_CLKPWR_UART_X_DIV(x)            (((x) & 0xFF) << 8)
+#define LPC32XX_CLKPWR_UART_USE_HCLK            _BIT(16)
+
+/*
+ * clkpwr_irda_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_IRDA_Y_DIV(y)            ((y) & 0xFF)
+#define LPC32XX_CLKPWR_IRDA_X_DIV(x)            (((x) & 0xFF) << 8)
+
+/*
+ * clkpwr_uart_clk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN     _BIT(3)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN     _BIT(2)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN     _BIT(1)
+#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN     _BIT(0)
+
+/*
+ * clkpwr_dmaclk_ctrl register definitions
+ */
+#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN        0x1
+
+/*
+ * clkpwr_autoclock register definitions
+ */
+#define LPC32XX_CLKPWR_AUTOCLK_USB_EN           0x40
+#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN          0x02
+#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN          0x01
+
+/*
+ * Interrupt controller register offsets
+ */
+#define LPC32XX_INTC_MASK(x)                    io_p2v((x) + 0x00)
+#define LPC32XX_INTC_RAW_STAT(x)                io_p2v((x) + 0x04)
+#define LPC32XX_INTC_STAT(x)                    io_p2v((x) + 0x08)
+#define LPC32XX_INTC_POLAR(x)                   io_p2v((x) + 0x0C)
+#define LPC32XX_INTC_ACT_TYPE(x)                io_p2v((x) + 0x10)
+#define LPC32XX_INTC_TYPE(x)                    io_p2v((x) + 0x14)
+
+/*
+ * Timer/counter register offsets
+ */
+#define LCP32XX_TIMER_IR(x)                     io_p2v((x) + 0x00)
+#define LCP32XX_TIMER_TCR(x)                    io_p2v((x) + 0x04)
+#define LCP32XX_TIMER_TC(x)                     io_p2v((x) + 0x08)
+#define LCP32XX_TIMER_PR(x)                     io_p2v((x) + 0x0C)
+#define LCP32XX_TIMER_PC(x)                     io_p2v((x) + 0x10)
+#define LCP32XX_TIMER_MCR(x)                    io_p2v((x) + 0x14)
+#define LCP32XX_TIMER_MR0(x)                    io_p2v((x) + 0x18)
+#define LCP32XX_TIMER_MR1(x)                    io_p2v((x) + 0x1C)
+#define LCP32XX_TIMER_MR2(x)                    io_p2v((x) + 0x20)
+#define LCP32XX_TIMER_MR3(x)                    io_p2v((x) + 0x24)
+#define LCP32XX_TIMER_CCR(x)                    io_p2v((x) + 0x28)
+#define LCP32XX_TIMER_CR0(x)                    io_p2v((x) + 0x2C)
+#define LCP32XX_TIMER_CR1(x)                    io_p2v((x) + 0x30)
+#define LCP32XX_TIMER_CR2(x)                    io_p2v((x) + 0x34)
+#define LCP32XX_TIMER_CR3(x)                    io_p2v((x) + 0x38)
+#define LCP32XX_TIMER_EMR(x)                    io_p2v((x) + 0x3C)
+#define LCP32XX_TIMER_CTCR(x)                   io_p2v((x) + 0x70)
+
+/*
+ * ir register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MTCH_BIT(n)          (1 << ((n) & 0x3))
+#define LCP32XX_TIMER_CNTR_CAPT_BIT(n)          (1 << (4 + ((n) & 0x3)))
+
+/*
+ * tcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_TCR_EN               0x1
+#define LCP32XX_TIMER_CNTR_TCR_RESET            0x2
+
+/*
+ * mcr register definitions
+ */
+#define LCP32XX_TIMER_CNTR_MCR_MTCH(n)          (0x1 << ((n) * 3))
+#define LCP32XX_TIMER_CNTR_MCR_RESET(n)         (0x1 << (((n) * 3) + 1))
+#define LCP32XX_TIMER_CNTR_MCR_STOP(n)          (0x1 << (((n) * 3) + 2))
+
+/*
+ * Standard UART register offsets
+ */
+#define LPC32XX_UART_DLL_FIFO(x)                io_p2v((x) + 0x00)
+#define LPC32XX_UART_DLM_IER(x)                 io_p2v((x) + 0x04)
+#define LPC32XX_UART_IIR_FCR(x)                 io_p2v((x) + 0x08)
+#define LPC32XX_UART_LCR(x)                     io_p2v((x) + 0x0C)
+#define LPC32XX_UART_MODEM_CTRL(x)              io_p2v((x) + 0x10)
+#define LPC32XX_UART_LSR(x)                     io_p2v((x) + 0x14)
+#define LPC32XX_UART_MODEM_STATUS(x)            io_p2v((x) + 0x18)
+#define LPC32XX_UART_RXLEV(x)                   io_p2v((x) + 0x1C)
+
+/*
+ * UART control structure offsets
+ */
+#define _UCREG(x)                               io_p2v(\
+                                                LPC32XX_UART_CTRL_BASE + (x))
+#define LPC32XX_UARTCTL_CTRL                    _UCREG(0x00)
+#define LPC32XX_UARTCTL_CLKMODE                 _UCREG(0x04)
+#define LPC32XX_UARTCTL_CLOOP                   _UCREG(0x08)
+
+/*
+ * ctrl register definitions
+ */
+#define LPC32XX_UART_U3_MD_CTRL_EN              _BIT(11)
+#define LPC32XX_UART_IRRX6_INV_EN               _BIT(10)
+#define LPC32XX_UART_HDPX_EN                    _BIT(9)
+#define LPC32XX_UART_UART6_IRDAMOD_BYPASS       _BIT(5)
+#define LPC32XX_RT_IRTX6_INV_EN                 _BIT(4)
+#define LPC32XX_RT_IRTX6_INV_MIR_EN             _BIT(3)
+#define LPC32XX_RT_RX_IRPULSE_3_16_115K         _BIT(2)
+#define LPC32XX_RT_TX_IRPULSE_3_16_115K         _BIT(1)
+#define LPC32XX_UART_U5_ROUTE_TO_USB            _BIT(0)
+
+/*
+ * clkmode register definitions
+ */
+#define LPC32XX_UART_ENABLED_CLOCKS(n)          (((n) >> 16) & 0x7F)
+#define LPC32XX_UART_ENABLED_CLOCK(n, u)        (((n) >> (16 + (u))) & 0x1)
+#define LPC32XX_UART_ENABLED_CLKS_ANY           _BIT(14)
+#define LPC32XX_UART_CLKMODE_OFF                0x0
+#define LPC32XX_UART_CLKMODE_ON                 0x1
+#define LPC32XX_UART_CLKMODE_AUTO               0x2
+#define LPC32XX_UART_CLKMODE_MASK(u)            (0x3 << ((((u) - 3) * 2) + 4))
+#define LPC32XX_UART_CLKMODE_LOAD(m, u)         ((m) << ((((u) - 3) * 2) + 4))
+
+/*
+ * GPIO Module Register offsets
+ */
+#define _GPREG(x)                               io_p2v(LPC32XX_GPIO_BASE + (x))
+#define LPC32XX_GPIO_P_MUX_SET                  _GPREG(0x100)
+#define LPC32XX_GPIO_P_MUX_CLR                  _GPREG(0x104)
+#define LPC32XX_GPIO_P_MUX_STATE                _GPREG(0x108)
+#define LPC32XX_GPIO_P3_MUX_SET                 _GPREG(0x110)
+#define LPC32XX_GPIO_P3_MUX_CLR                 _GPREG(0x114)
+#define LPC32XX_GPIO_P3_MUX_STATE               _GPREG(0x118)
+#define LPC32XX_GPIO_P0_MUX_SET                 _GPREG(0x120)
+#define LPC32XX_GPIO_P0_MUX_CLR                 _GPREG(0x124)
+#define LPC32XX_GPIO_P0_MUX_STATE               _GPREG(0x128)
+#define LPC32XX_GPIO_P1_MUX_SET                 _GPREG(0x130)
+#define LPC32XX_GPIO_P1_MUX_CLR                 _GPREG(0x134)
+#define LPC32XX_GPIO_P1_MUX_STATE               _GPREG(0x138)
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/system.h b/arch/arm/mach-lpc32xx/include/mach/system.h
new file mode 100644
index 000000000000..df3b0dea4d7b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/system.h
@@ -0,0 +1,52 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/system.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+        extern void lpc32xx_watchdog_reset(void);
+
+        switch (mode) {
+        case 's':
+        case 'h':
+                printk(KERN_CRIT "RESET: Rebooting system\n");
+
+                /* Disable interrupts */
+                local_irq_disable();
+
+                lpc32xx_watchdog_reset();
+                break;
+
+        default:
+                /* Do nothing */
+                break;
+        }
+
+        /* Wait for watchdog to reset system */
+        while (1)
+                ;
+}
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/timex.h b/arch/arm/mach-lpc32xx/include/mach/timex.h
new file mode 100644
index 000000000000..8d4066b16b3f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/timex.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/timex.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/*
+ * Rate in Hz of the main system oscillator. This value should match
+ * the value 'MAIN_OSC_FREQ' in platform.h
+ */
+#define CLOCK_TICK_RATE 13000000
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/uncompress.h b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
new file mode 100644
index 000000000000..c142487d299a
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/uncompress.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARM_ARCH_UNCOMPRESS_H
+#define __ASM_ARM_ARCH_UNCOMPRESS_H
+
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+
+/*
+ * Uncompress output is hardcoded to standard UART 5
+ */
+
+#define UART_FIFO_CTL_TX_RESET  (1 << 2)
+#define UART_STATUS_TX_MT       (1 << 6)
+
+#define _UARTREG(x)             (void __iomem *)(LPC32XX_UART5_BASE + (x))
+
+#define LPC32XX_UART_DLLFIFO_O  0x00
+#define LPC32XX_UART_IIRFCR_O   0x08
+#define LPC32XX_UART_LSR_O      0x14
+
+static inline void putc(int ch)
+{
+        /* Wait for transmit FIFO to empty */
+        while ((__raw_readl(_UARTREG(LPC32XX_UART_LSR_O)) &
+                UART_STATUS_TX_MT) == 0)
+                ;
+
+        __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O));
+}
+
+static inline void flush(void)
+{
+        __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) |
+                UART_FIFO_CTL_TX_RESET, _UARTREG(LPC32XX_UART_IIRFCR_O));
+}
+
+/* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
new file mode 100644
index 000000000000..d1d936c7236d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+#define VMALLOC_END     0xF0000000
+
+#endif
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
new file mode 100644
index 000000000000..bd0df26c415b
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -0,0 +1,432 @@
+/*
+ * arch/arm/mach-lpc32xx/irq.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Default value representing the Activation polarity of all internal
+ * interrupt sources
+ */
+#define MIC_APR_DEFAULT         0x3FF0EFE0
+#define SIC1_APR_DEFAULT        0xFBD27186
+#define SIC2_APR_DEFAULT        0x801810C0
+
+/*
+ * Default value representing the Activation Type of all internal
+ * interrupt sources. All are level sensitive.
+ */
+#define MIC_ATR_DEFAULT         0x00000000
+#define SIC1_ATR_DEFAULT        0x00026000
+#define SIC2_ATR_DEFAULT        0x00000000
+
+struct lpc32xx_event_group_regs {
+        void __iomem *enab_reg;
+        void __iomem *edge_reg;
+        void __iomem *maskstat_reg;
+        void __iomem *rawstat_reg;
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_int_regs = {
+        .enab_reg = LPC32XX_CLKPWR_INT_ER,
+        .edge_reg = LPC32XX_CLKPWR_INT_AP,
+        .maskstat_reg = LPC32XX_CLKPWR_INT_SR,
+        .rawstat_reg = LPC32XX_CLKPWR_INT_RS,
+};
+
+static const struct lpc32xx_event_group_regs lpc32xx_event_pin_regs = {
+        .enab_reg = LPC32XX_CLKPWR_PIN_ER,
+        .edge_reg = LPC32XX_CLKPWR_PIN_AP,
+        .maskstat_reg = LPC32XX_CLKPWR_PIN_SR,
+        .rawstat_reg = LPC32XX_CLKPWR_PIN_RS,
+};
+
+struct lpc32xx_event_info {
+        const struct lpc32xx_event_group_regs *event_group;
+        u32 mask;
+};
+
+/*
+ * Maps an IRQ number to and event mask and register
+ */
+static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
+        [IRQ_LPC32XX_GPI_08] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT,
+        },
+        [IRQ_LPC32XX_GPI_09] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT,
+        },
+        [IRQ_LPC32XX_GPI_19] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT,
+        },
+        [IRQ_LPC32XX_GPI_07] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT,
+        },
+        [IRQ_LPC32XX_GPI_00] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT,
+        },
+        [IRQ_LPC32XX_GPI_01] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT,
+        },
+        [IRQ_LPC32XX_GPI_02] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT,
+        },
+        [IRQ_LPC32XX_GPI_03] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT,
+        },
+        [IRQ_LPC32XX_GPI_04] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT,
+        },
+        [IRQ_LPC32XX_GPI_05] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT,
+        },
+        [IRQ_LPC32XX_GPI_06] = {
+                .event_group = &lpc32xx_event_pin_regs,
+                .mask = LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_00] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_01] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_02] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_03] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_04] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT,
+        },
+        [IRQ_LPC32XX_GPIO_05] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT,
+        },
+        [IRQ_LPC32XX_KEY] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
+        },
+        [IRQ_LPC32XX_USB_OTG_ATX] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
+        },
+        [IRQ_LPC32XX_USB_HOST] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_USB_BIT,
+        },
+        [IRQ_LPC32XX_RTC] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+        },
+        [IRQ_LPC32XX_MSTIMER] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT,
+        },
+        [IRQ_LPC32XX_TS_AUX] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT,
+        },
+        [IRQ_LPC32XX_TS_P] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_TS_P_BIT,
+        },
+        [IRQ_LPC32XX_TS_IRQ] = {
+                .event_group = &lpc32xx_event_int_regs,
+                .mask = LPC32XX_CLKPWR_INTSRC_ADC_BIT,
+        },
+};
+
+static void get_controller(unsigned int irq, unsigned int *base,
+        unsigned int *irqbit)
+{
+        if (irq < 32) {
+                *base = LPC32XX_MIC_BASE;
+                *irqbit = 1 << irq;
+        } else if (irq < 64) {
+                *base = LPC32XX_SIC1_BASE;
+                *irqbit = 1 << (irq - 32);
+        } else {
+                *base = LPC32XX_SIC2_BASE;
+                *irqbit = 1 << (irq - 64);
+        }
+}
+
+static void lpc32xx_mask_irq(unsigned int irq)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) & ~mask;
+        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_unmask_irq(unsigned int irq)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        reg = __raw_readl(LPC32XX_INTC_MASK(ctrl)) | mask;
+        __raw_writel(reg, LPC32XX_INTC_MASK(ctrl));
+}
+
+static void lpc32xx_ack_irq(unsigned int irq)
+{
+        unsigned int ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl));
+
+        /* Also need to clear pending wake event */
+        if (lpc32xx_events[irq].mask != 0)
+                __raw_writel(lpc32xx_events[irq].mask,
+                        lpc32xx_events[irq].event_group->rawstat_reg);
+}
+
+static void __lpc32xx_set_irq_type(unsigned int irq, int use_high_level,
+        int use_edge)
+{
+        unsigned int reg, ctrl, mask;
+
+        get_controller(irq, &ctrl, &mask);
+
+        /* Activation level, high or low */
+        reg = __raw_readl(LPC32XX_INTC_POLAR(ctrl));
+        if (use_high_level)
+                reg |= mask;
+        else
+                reg &= ~mask;
+        __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl));
+
+        /* Activation type, edge or level */
+        reg = __raw_readl(LPC32XX_INTC_ACT_TYPE(ctrl));
+        if (use_edge)
+                reg |= mask;
+        else
+                reg &= ~mask;
+        __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl));
+
+        /* Use same polarity for the wake events */
+        if (lpc32xx_events[irq].mask != 0) {
+                reg = __raw_readl(lpc32xx_events[irq].event_group->edge_reg);
+
+                if (use_high_level)
+                        reg |= lpc32xx_events[irq].mask;
+                else
+                        reg &= ~lpc32xx_events[irq].mask;
+
+                __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg);
+        }
+}
+
+static int lpc32xx_set_irq_type(unsigned int irq, unsigned int type)
+{
+        switch (type) {
+        case IRQ_TYPE_EDGE_RISING:
+                /* Rising edge sensitive */
+                __lpc32xx_set_irq_type(irq, 1, 1);
+                break;
+
+        case IRQ_TYPE_EDGE_FALLING:
+                /* Falling edge sensitive */
+                __lpc32xx_set_irq_type(irq, 0, 1);
+                break;
+
+        case IRQ_TYPE_LEVEL_LOW:
+                /* Low level sensitive */
+                __lpc32xx_set_irq_type(irq, 0, 0);
+                break;
+
+        case IRQ_TYPE_LEVEL_HIGH:
+                /* High level sensitive */
+                __lpc32xx_set_irq_type(irq, 1, 0);
+                break;
+
+        /* Other modes are not supported */
+        default:
+                return -EINVAL;
+        }
+
+        /* Ok to use the level handler for all types */
+        set_irq_handler(irq, handle_level_irq);
+
+        return 0;
+}
+
+static int lpc32xx_irq_wake(unsigned int irqno, unsigned int state)
+{
+        unsigned long eventreg;
+
+        if (lpc32xx_events[irqno].mask != 0) {
+                eventreg = __raw_readl(lpc32xx_events[irqno].
+                        event_group->enab_reg);
+
+                if (state)
+                        eventreg |= lpc32xx_events[irqno].mask;
+                else
+                        eventreg &= ~lpc32xx_events[irqno].mask;
+
+                __raw_writel(eventreg,
+                        lpc32xx_events[irqno].event_group->enab_reg);
+
+                return 0;
+        }
+
+        /* Clear event */
+        __raw_writel(lpc32xx_events[irqno].mask,
+                lpc32xx_events[irqno].event_group->rawstat_reg);
+
+        return -ENODEV;
+}
+
+static void __init lpc32xx_set_default_mappings(unsigned int apr,
+        unsigned int atr, unsigned int offset)
+{
+        unsigned int i;
+
+        /* Set activation levels for each interrupt */
+        i = 0;
+        while (i < 32) {
+                __lpc32xx_set_irq_type(offset + i, ((apr >> i) & 0x1),
+                        ((atr >> i) & 0x1));
+                i++;
+        }
+}
+
+static struct irq_chip lpc32xx_irq_chip = {
+        .ack = lpc32xx_ack_irq,
+        .mask = lpc32xx_mask_irq,
+        .unmask = lpc32xx_unmask_irq,
+        .set_type = lpc32xx_set_irq_type,
+        .set_wake = lpc32xx_irq_wake
+};
+
+static void lpc32xx_sic1_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC1_BASE));
+
+        while (ints != 0) {
+                int irqno = fls(ints) - 1;
+
+                ints &= ~(1 << irqno);
+
+                generic_handle_irq(LPC32XX_SIC1_IRQ(irqno));
+        }
+}
+
+static void lpc32xx_sic2_handler(unsigned int irq, struct irq_desc *desc)
+{
+        unsigned long ints = __raw_readl(LPC32XX_INTC_STAT(LPC32XX_SIC2_BASE));
+
+        while (ints != 0) {
+                int irqno = fls(ints) - 1;
+
+                ints &= ~(1 << irqno);
+
+                generic_handle_irq(LPC32XX_SIC2_IRQ(irqno));
+        }
+}
+
+void __init lpc32xx_init_irq(void)
+{
+        unsigned int i;
+
+        /* Setup MIC */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_MIC_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_MIC_BASE));
+
+        /* Setup SIC1 */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC1_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC1_BASE));
+
+        /* Setup SIC2 */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+        __raw_writel(MIC_APR_DEFAULT, LPC32XX_INTC_POLAR(LPC32XX_SIC2_BASE));
+        __raw_writel(MIC_ATR_DEFAULT, LPC32XX_INTC_ACT_TYPE(LPC32XX_SIC2_BASE));
+
+        /* Configure supported IRQ's */
+        for (i = 0; i < NR_IRQS; i++) {
+                set_irq_chip(i, &lpc32xx_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+
+        /* Set default mappings */
+        lpc32xx_set_default_mappings(MIC_APR_DEFAULT, MIC_ATR_DEFAULT, 0);
+        lpc32xx_set_default_mappings(SIC1_APR_DEFAULT, SIC1_ATR_DEFAULT, 32);
+        lpc32xx_set_default_mappings(SIC2_APR_DEFAULT, SIC2_ATR_DEFAULT, 64);
+
+        /* mask all interrupts except SUBIRQ */
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_MIC_BASE));
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC1_BASE));
+        __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
+
+        /* MIC SUBIRQx interrupts will route handling to the chain handlers */
+        set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+        set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
+
+        /* Initially disable all wake events */
+        __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
+        __raw_writel(0, LPC32XX_CLKPWR_INT_ER);
+        __raw_writel(0, LPC32XX_CLKPWR_PIN_ER);
+
+        /*
+         * Default wake activation polarities, all pin sources are low edge
+         * triggered
+         */
+        __raw_writel(LPC32XX_CLKPWR_INTSRC_TS_P_BIT |
+                LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT |
+                LPC32XX_CLKPWR_INTSRC_RTC_BIT,
+                LPC32XX_CLKPWR_INT_AP);
+        __raw_writel(0, LPC32XX_CLKPWR_PIN_AP);
+
+        /* Clear latched wake event states */
+        __raw_writel(__raw_readl(LPC32XX_CLKPWR_PIN_RS),
+                LPC32XX_CLKPWR_PIN_RS);
+        __raw_writel(__raw_readl(LPC32XX_CLKPWR_INT_RS),
+                LPC32XX_CLKPWR_INT_RS);
+}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
new file mode 100644
index 000000000000..bc9a42da2145
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -0,0 +1,397 @@
+/*
+ * arch/arm/mach-lpc32xx/phy3250.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/amba/bus.h>
+#include <linux/amba/clcd.h>
+#include <linux/amba/pl022.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+/*
+ * Mapped GPIOLIB GPIOs
+ */
+#define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
+#define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
+
+/*
+ * AMBA LCD controller
+ */
+static struct clcd_panel conn_lcd_panel = {
+        .mode           = {
+                .name           = "QVGA portrait",
+                .refresh        = 60,
+                .xres           = 240,
+                .yres           = 320,
+                .pixclock       = 191828,
+                .left_margin    = 22,
+                .right_margin   = 11,
+                .upper_margin   = 2,
+                .lower_margin   = 1,
+                .hsync_len      = 5,
+                .vsync_len      = 2,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+        .width          = -1,
+        .height         = -1,
+        .tim2           = (TIM2_IVS | TIM2_IHS),
+        .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
+                                CNTL_LCDBPP16_565),
+        .bpp            = 16,
+};
+#define PANEL_SIZE (3 * SZ_64K)
+
+static int lpc32xx_clcd_setup(struct clcd_fb *fb)
+{
+        dma_addr_t dma;
+
+        fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
+                PANEL_SIZE, &dma, GFP_KERNEL);
+        if (!fb->fb.screen_base) {
+                printk(KERN_ERR "CLCD: unable to map framebuffer\n");
+                return -ENOMEM;
+        }
+
+        fb->fb.fix.smem_start = dma;
+        fb->fb.fix.smem_len = PANEL_SIZE;
+        fb->panel = &conn_lcd_panel;
+
+        if (gpio_request(LCD_POWER_GPIO, "LCD power"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        LCD_POWER_GPIO);
+        else if (gpio_direction_output(LCD_POWER_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        LCD_POWER_GPIO);
+
+        if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        BKL_POWER_GPIO);
+        else if (gpio_direction_output(BKL_POWER_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        BKL_POWER_GPIO);
+
+        return 0;
+}
+
+static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
+{
+        return dma_mmap_writecombine(&fb->dev->dev, vma,
+                fb->fb.screen_base, fb->fb.fix.smem_start,
+                fb->fb.fix.smem_len);
+}
+
+static void lpc32xx_clcd_remove(struct clcd_fb *fb)
+{
+        dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
+                fb->fb.screen_base, fb->fb.fix.smem_start);
+}
+
+/*
+ * On some early LCD modules (1307.0), the backlight logic is inverted.
+ * For those board variants, swap the disable and enable states for
+ * BKL_POWER_GPIO.
+*/
+static void clcd_disable(struct clcd_fb *fb)
+{
+        gpio_set_value(BKL_POWER_GPIO, 0);
+        gpio_set_value(LCD_POWER_GPIO, 0);
+}
+
+static void clcd_enable(struct clcd_fb *fb)
+{
+        gpio_set_value(BKL_POWER_GPIO, 1);
+        gpio_set_value(LCD_POWER_GPIO, 1);
+}
+
+static struct clcd_board lpc32xx_clcd_data = {
+        .name           = "Phytec LCD",
+        .check          = clcdfb_check,
+        .decode         = clcdfb_decode,
+        .disable        = clcd_disable,
+        .enable         = clcd_enable,
+        .setup          = lpc32xx_clcd_setup,
+        .mmap           = lpc32xx_clcd_mmap,
+        .remove         = lpc32xx_clcd_remove,
+};
+
+static struct amba_device lpc32xx_clcd_device = {
+        .dev                            = {
+                .coherent_dma_mask      = ~0,
+                .init_name              = "dev:clcd",
+                .platform_data          = &lpc32xx_clcd_data,
+        },
+        .res                            = {
+                .start                  = LPC32XX_LCD_BASE,
+                .end                    = (LPC32XX_LCD_BASE + SZ_4K - 1),
+                .flags                  = IORESOURCE_MEM,
+        },
+        .dma_mask                       = ~0,
+        .irq                            = {IRQ_LPC32XX_LCD, NO_IRQ},
+};
+
+/*
+ * AMBA SSP (SPI)
+ */
+static void phy3250_spi_cs_set(u32 control)
+{
+        gpio_set_value(SPI0_CS_GPIO, (int) control);
+}
+
+static struct pl022_config_chip spi0_chip_info = {
+        .lbm                    = LOOPBACK_DISABLED,
+        .com_mode               = INTERRUPT_TRANSFER,
+        .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
+        .hierarchy              = SSP_MASTER,
+        .slave_tx_disable       = 0,
+        .endian_tx              = SSP_TX_LSB,
+        .endian_rx              = SSP_RX_LSB,
+        .data_size              = SSP_DATA_BITS_8,
+        .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
+        .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
+        .clk_phase              = SSP_CLK_FIRST_EDGE,
+        .clk_pol                = SSP_CLK_POL_IDLE_LOW,
+        .ctrl_len               = SSP_BITS_8,
+        .wait_state             = SSP_MWIRE_WAIT_ZERO,
+        .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
+        .cs_control             = phy3250_spi_cs_set,
+};
+
+static struct pl022_ssp_controller lpc32xx_ssp0_data = {
+        .bus_id                 = 0,
+        .num_chipselect         = 1,
+        .enable_dma             = 0,
+};
+
+static struct amba_device lpc32xx_ssp0_device = {
+        .dev                            = {
+                .coherent_dma_mask      = ~0,
+                .init_name              = "dev:ssp0",
+                .platform_data          = &lpc32xx_ssp0_data,
+        },
+        .res                            = {
+                .start                  = LPC32XX_SSP0_BASE,
+                .end                    = (LPC32XX_SSP0_BASE + SZ_4K - 1),
+                .flags                  = IORESOURCE_MEM,
+        },
+        .dma_mask                       = ~0,
+        .irq                            = {IRQ_LPC32XX_SSP0, NO_IRQ},
+};
+
+/* AT25 driver registration */
+static int __init phy3250_spi_board_register(void)
+{
+#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
+        static struct spi_board_info info[] = {
+                {
+                        .modalias = "spidev",
+                        .max_speed_hz = 5000000,
+                        .bus_num = 0,
+                        .chip_select = 0,
+                        .controller_data = &spi0_chip_info,
+                },
+        };
+
+#else
+        static struct spi_eeprom eeprom = {
+                .name = "at25256a",
+                .byte_len = 0x8000,
+                .page_size = 64,
+                .flags = EE_ADDR2,
+        };
+
+        static struct spi_board_info info[] = {
+                {
+                        .modalias = "at25",
+                        .max_speed_hz = 5000000,
+                        .bus_num = 0,
+                        .chip_select = 0,
+                        .platform_data = &eeprom,
+                        .controller_data = &spi0_chip_info,
+                },
+        };
+#endif
+        return spi_register_board_info(info, ARRAY_SIZE(info));
+}
+arch_initcall(phy3250_spi_board_register);
+
+static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+static struct gpio_led phy_leds[] = {
+        {
+                .name                   = "led0",
+                .gpio                   = LED_GPIO,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+};
+
+static struct gpio_led_platform_data led_data = {
+        .leds = phy_leds,
+        .num_leds = ARRAY_SIZE(phy_leds),
+};
+
+static struct platform_device lpc32xx_gpio_led_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &led_data,
+};
+
+static struct platform_device *phy3250_devs[] __initdata = {
+        &lpc32xx_i2c0_device,
+        &lpc32xx_i2c1_device,
+        &lpc32xx_i2c2_device,
+        &lpc32xx_watchdog_device,
+        &lpc32xx_gpio_led_device,
+};
+
+static struct amba_device *amba_devs[] __initdata = {
+        &lpc32xx_clcd_device,
+        &lpc32xx_ssp0_device,
+};
+
+/*
+ * Board specific functions
+ */
+static void __init phy3250_board_init(void)
+{
+        u32 tmp;
+        int i;
+
+        lpc32xx_gpio_init();
+
+        /* Register GPIOs used on this board */
+        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
+                printk(KERN_ERR "Error requesting gpio %u",
+                        SPI0_CS_GPIO);
+        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
+                printk(KERN_ERR "Error setting gpio %u to output",
+                        SPI0_CS_GPIO);
+
+        /* Setup network interface for RMII mode */
+        tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
+        tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
+        tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
+        __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
+
+        /* Setup SLC NAND controller muxing */
+        __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
+                LPC32XX_CLKPWR_NAND_CLK_CTRL);
+
+        /* Setup LCD muxing to RGB565 */
+        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
+                ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
+                LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
+        tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
+        __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
+
+        /* Set up I2C pull levels */
+        tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
+        tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
+                LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
+        __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
+
+        /* Disable IrDA pulsing support on UART6 */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+        /* Enable DMA for I2S1 channel */
+        tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
+        tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
+        __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
+
+        lpc32xx_serial_init();
+
+        /*
+         * AMBA peripheral clocks need to be enabled prior to AMBA device
+         * detection or a data fault will occur, so enable the clocks
+         * here. However, we don't want to enable them if the peripheral
+         * isn't included in the image
+         */
+#ifdef CONFIG_FB_ARMCLCD
+        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
+        __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
+                LPC32XX_CLKPWR_LCDCLK_CTRL);
+#endif
+#ifdef CONFIG_SPI_PL022
+        tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
+        __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
+                LPC32XX_CLKPWR_SSP_CLK_CTRL);
+#endif
+
+        platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+
+        /* Test clock needed for UDA1380 initial init */
+        __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
+                LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
+                LPC32XX_CLKPWR_TEST_CLK_SEL);
+
+        i2c_register_board_info(0, phy3250_i2c_board_info,
+                ARRAY_SIZE(phy3250_i2c_board_info));
+}
+
+static int __init lpc32xx_display_uid(void)
+{
+        u32 uid[4];
+
+        lpc32xx_get_uid(uid);
+
+        printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
+                uid[3], uid[2], uid[1], uid[0]);
+
+        return 1;
+}
+arch_initcall(lpc32xx_display_uid);
+
+MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
+        /* Maintainer: Kevin Wells, NXP Semiconductors */
+        .phys_io        = LPC32XX_UART5_BASE,
+        .io_pg_offst    = ((IO_ADDRESS(LPC32XX_UART5_BASE))>>18) & 0xfffc,
+        .boot_params    = 0x80000100,
+        .map_io         = lpc32xx_map_io,
+        .init_irq       = lpc32xx_init_irq,
+        .timer          = &lpc32xx_timer,
+        .init_machine   = phy3250_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
new file mode 100644
index 000000000000..a6e2aed9a49f
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -0,0 +1,146 @@
+/*
+ * arch/arm/mach-lpc32xx/pm.c
+ *
+ * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * LPC32XX CPU and system power management
+ *
+ * The LCP32XX has three CPU modes for controlling system power: run,
+ * direct-run, and halt modes. When switching between halt and run modes,
+ * the CPU transistions through direct-run mode. For Linux, direct-run
+ * mode is not used in normal operation. Halt mode is used when the
+ * system is fully suspended.
+ *
+ * Run mode:
+ * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
+ * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
+ * the HCLK_PLL rate. Linux runs in this mode.
+ *
+ * Direct-run mode:
+ * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
+ * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
+ * source or the frequency of the main oscillator. In this mode, the
+ * HCLK_PLL can be safely enabled, changed, or disabled.
+ *
+ * Halt mode:
+ * SYSCLK is gated off and the CPU and system clocks are halted.
+ * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
+ * key scanner, etc.) still operate if enabled. In this state, an enabled
+ * system event (ie, GPIO state change, RTC match, key press, etc.) will
+ * wake the system up back into direct-run mode.
+ *
+ * DRAM refresh
+ * DRAM clocking and refresh are slightly different for systems with DDR
+ * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
+ * SDRAM will still be accessible in direct-run mode. In DDR based systems,
+ * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * Because of this, the code to switch power modes and the code to enter
+ * and exit DRAM self-refresh modes must not be executed in DRAM. A small
+ * section of IRAM is used instead for this.
+ *
+ * Suspend is handled with the following logic:
+ *  Backup a small area of IRAM used for the suspend code
+ *  Copy suspend code to IRAM
+ *  Transfer control to code in IRAM
+ *  Places DRAMs in self-refresh mode
+ *  Enter direct-run mode
+ *  Save state of HCLK_PLL PLL
+ *  Disable HCLK_PLL PLL
+ *  Enter halt mode - CPU and buses will stop
+ *  System enters direct-run mode when an enabled event occurs
+ *  HCLK PLL state is restored
+ *  Run mode is entered
+ *  DRAMS are placed back into normal mode
+ *  Code execution returns from IRAM
+ *  IRAM code are used for suspend is restored
+ *  Suspend mode is exited
+ */
+
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+#include "clock.h"
+
+#define TEMP_IRAM_AREA  IO_ADDRESS(LPC32XX_IRAM_BASE)
+
+/*
+ * Both STANDBY and MEM suspend states are handled the same with no
+ * loss of CPU or memory state
+ */
+static int lpc32xx_pm_enter(suspend_state_t state)
+{
+        int (*lpc32xx_suspend_ptr) (void);
+        void *iram_swap_area;
+
+        /* Allocate some space for temporary IRAM storage */
+        iram_swap_area = kmalloc(lpc32xx_sys_suspend_sz, GFP_KERNEL);
+        if (!iram_swap_area) {
+                printk(KERN_ERR
+                       "PM Suspend: cannot allocate memory to save portion "
+                        "of SRAM\n");
+                return -ENOMEM;
+        }
+
+        /* Backup a small area of IRAM used for the suspend code */
+        memcpy(iram_swap_area, (void *) TEMP_IRAM_AREA,
+                lpc32xx_sys_suspend_sz);
+
+        /*
+         * Copy code to suspend system into IRAM. The suspend code
+         * needs to run from IRAM as DRAM may no longer be available
+         * when the PLL is stopped.
+         */
+        memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
+                lpc32xx_sys_suspend_sz);
+        flush_icache_range((unsigned long)TEMP_IRAM_AREA,
+                (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
+
+        /* Transfer to suspend code in IRAM */
+        lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
+        flush_cache_all();
+        (void) lpc32xx_suspend_ptr();
+
+        /* Restore original IRAM contents */
+        memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
+                lpc32xx_sys_suspend_sz);
+
+        kfree(iram_swap_area);
+
+        return 0;
+}
+
+static struct platform_suspend_ops lpc32xx_pm_ops = {
+        .valid  = suspend_valid_only_mem,
+        .enter  = lpc32xx_pm_enter,
+};
+
+#define EMC_DYN_MEM_CTRL_OFS 0x20
+#define EMC_SRMMC           (1 << 3)
+#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
+static int __init lpc32xx_pm_init(void)
+{
+        /*
+         * Setup SDRAM self-refresh clock to automatically disable o
+         * start of self-refresh. This only needs to be done once.
+         */
+        __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
+
+        suspend_set_ops(&lpc32xx_pm_ops);
+
+        return 0;
+}
+arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
new file mode 100644
index 000000000000..429cfdbb2b3d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -0,0 +1,190 @@
+/*
+ * arch/arm/mach-lpc32xx/serial.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2010 NXP Semiconductors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+#define LPC32XX_SUART_FIFO_SIZE 64
+
+/* Standard 8250/16550 compatible serial ports */
+static struct plat_serial8250_port serial_std_platform_data[] = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART5_BASE),
+                .mapbase        = LPC32XX_UART5_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR5,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART3_BASE),
+                .mapbase        = LPC32XX_UART3_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR3,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART4_BASE),
+                .mapbase        = LPC32XX_UART4_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR4,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+        {
+                .membase        = io_p2v(LPC32XX_UART6_BASE),
+                .mapbase        = LPC32XX_UART6_BASE,
+                .irq            = IRQ_LPC32XX_UART_IIR6,
+                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
+                .regshift       = 2,
+                .iotype         = UPIO_MEM32,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
+                                        UPF_SKIP_TEST,
+        },
+#endif
+        { },
+};
+
+struct uartinit {
+        char *uart_ck_name;
+        u32 ck_mode_mask;
+        void __iomem *pdiv_clk_reg;
+};
+
+static struct uartinit uartinit_data[] __initdata = {
+#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
+        {
+                .uart_ck_name = "uart5_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
+        {
+                .uart_ck_name = "uart3_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
+        {
+                .uart_ck_name = "uart4_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
+        },
+#endif
+#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
+        {
+                .uart_ck_name = "uart6_ck",
+                .ck_mode_mask =
+                        LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
+                .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
+        },
+#endif
+};
+
+static struct platform_device serial_std_platform_device = {
+        .name                   = "serial8250",
+        .id                     = 0,
+        .dev                    = {
+                .platform_data  = serial_std_platform_data,
+        },
+};
+
+static struct platform_device *lpc32xx_serial_devs[] __initdata = {
+        &serial_std_platform_device,
+};
+
+void __init lpc32xx_serial_init(void)
+{
+        u32 tmp, clkmodes = 0;
+        struct clk *clk;
+        unsigned int puart;
+        int i, j;
+
+        /* UART clocks are off, let clock driver manage them */
+        __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL);
+
+        for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
+                clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
+                if (!IS_ERR(clk)) {
+                        clk_enable(clk);
+                        serial_std_platform_data[i].uartclk =
+                                clk_get_rate(clk);
+                }
+
+                /* Fall back on main osc rate if clock rate return fails */
+                if (serial_std_platform_data[i].uartclk == 0)
+                        serial_std_platform_data[i].uartclk =
+                                LPC32XX_MAIN_OSC_FREQ;
+
+                /* Setup UART clock modes for all UARTs, disable autoclock */
+                clkmodes |= uartinit_data[i].ck_mode_mask;
+
+                /* pre-UART clock divider set to 1 */
+                __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
+        }
+
+        /* This needs to be done after all UART clocks are setup */
+        __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
+        for (i = 0; i < ARRAY_SIZE(uartinit_data) - 1; i++) {
+                /* Force a flush of the RX FIFOs to work around a HW bug */
+                puart = serial_std_platform_data[i].mapbase;
+                __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
+                __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
+                j = LPC32XX_SUART_FIFO_SIZE;
+                while (j--)
+                        tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
+                __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
+        }
+
+        /* Disable UART5->USB transparent mode or USB won't work */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
+        platform_add_devices(lpc32xx_serial_devs,
+                ARRAY_SIZE(lpc32xx_serial_devs));
+}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
new file mode 100644
index 000000000000..374f9f07fe48
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/suspend.S
@@ -0,0 +1,151 @@
+/*
+ * arch/arm/mach-lpc32xx/suspend.S
+ *
+ * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
+ * Modified by Kevin Wells <kevin.wells@nxp.com>
+ *
+ * 2005 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/platform.h>
+#include <mach/hardware.h>
+
+/* Using named register defines makes the code easier to follow */
+#define WORK1_REG                       r0
+#define WORK2_REG                       r1
+#define SAVED_HCLK_DIV_REG              r2
+#define SAVED_HCLK_PLL_REG              r3
+#define SAVED_DRAM_CLKCTRL_REG          r4
+#define SAVED_PWR_CTRL_REG              r5
+#define CLKPWRBASE_REG                  r6
+#define EMCBASE_REG                     r7
+
+#define LPC32XX_EMC_STATUS_OFFS         0x04
+#define LPC32XX_EMC_STATUS_BUSY         0x1
+#define LPC32XX_EMC_STATUS_SELF_RFSH    0x4
+
+#define LPC32XX_CLKPWR_PWR_CTRL_OFFS    0x44
+#define LPC32XX_CLKPWR_HCLK_DIV_OFFS    0x40
+#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
+
+#define CLKPWR_PCLK_DIV_MASK            0xFFFFFE7F
+
+        .text
+
+ENTRY(lpc32xx_sys_suspend)
+        @ Save a copy of the used registers in IRAM, r0 is corrupted
+        adr     r0, tmp_stack_end
+        stmfd   r0!, {r3 - r7, sp, lr}
+
+        @ Load a few common register addresses
+        adr     WORK1_REG, reg_bases
+        ldr     CLKPWRBASE_REG, [WORK1_REG, #0]
+        ldr     EMCBASE_REG, [WORK1_REG, #4]
+
+        ldr     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        orr     WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
+
+        @ Wait for SDRAM busy status to go busy and then idle
+        @ This guarantees a small windows where DRAM isn't busy
+1:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        bne     1b @ Branch while idle
+2:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
+        beq     2b @ Branch until idle
+
+        @ Setup self-refresh with support for manual exit of
+        @ self-refresh mode
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        orr     WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Wait for self-refresh acknowledge, clocks to the DRAM device
+        @ will automatically stop on start of self-refresh
+3:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        cmp     WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        bne     3b @ Branch until self-refresh mode starts
+
+        @ Enter direct-run mode from run mode
+        bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Safe disable of DRAM clock in EMC block, prevents DDR sync
+        @ issues on restart
+        ldr     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+        and     WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+        @ Save HCLK PLL state and disable HCLK PLL
+        ldr     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+        bic     WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
+        str     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+
+        @ Enter stop mode until an enabled event occurs
+        orr     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        .rept 9
+        nop
+        .endr
+
+        @ Clear stop status
+        bic     WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
+
+        @ Restore original HCLK PLL value and wait for PLL lock
+        str     SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+4:
+        ldr     WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
+        bne     4b
+
+        @ Re-enter run mode with self-refresh flag cleared, but no DRAM
+        @ update yet. DRAM is still in self-refresh
+        str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Restore original DRAM clock mode to restore DRAM clocks
+        str     SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
+
+        @ Clear self-refresh mode
+        orr     WORK1_REG, SAVED_PWR_CTRL_REG,\
+                #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
+        str     WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+        str     SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
+                #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
+
+        @ Wait for EMC to clear self-refresh mode
+5:
+        ldr     WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
+        and     WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
+        bne     5b @ Branch until self-refresh has exited
+
+        @ restore regs and return
+        adr     r0, tmp_stack
+        ldmfd   r0!, {r3 - r7, sp, pc}
+
+reg_bases:
+        .long   IO_ADDRESS(LPC32XX_CLK_PM_BASE)
+        .long   IO_ADDRESS(LPC32XX_EMC_BASE)
+
+tmp_stack:
+        .long   0, 0, 0, 0, 0, 0, 0
+tmp_stack_end:
+
+ENTRY(lpc32xx_sys_suspend_sz)
+        .word   . - lpc32xx_sys_suspend
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
new file mode 100644
index 000000000000..630dd4a74b26
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -0,0 +1,182 @@
+/*
+ * arch/arm/mach-lpc32xx/timer.c
+ *
+ * Author: Kevin Wells <kevin.wells@nxp.com>
+ *
+ * Copyright (C) 2009 - 2010 NXP Semiconductors
+ * Copyright (C) 2009 Fontys University of Applied Sciences, Eindhoven
+ *                    Ed Schouten <e.schouten@fontys.nl>
+ *                    Laurens Timmermans <l.timmermans@fontys.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/time.h>
+#include <linux/err.h>
+#include <linux/clockchips.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/platform.h>
+#include "common.h"
+
+static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
+{
+        return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
+}
+
+static struct clocksource lpc32xx_clksrc = {
+        .name   = "lpc32xx_clksrc",
+        .shift  = 24,
+        .rating = 300,
+        .read   = lpc32xx_clksrc_read,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static int lpc32xx_clkevt_next_event(unsigned long delta,
+    struct clock_event_device *dev)
+{
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(delta, LCP32XX_TIMER_PR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+
+        return 0;
+}
+
+static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
+    struct clock_event_device *dev)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                WARN_ON(1);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                /*
+                 * Disable the timer. When using oneshot, we must also
+                 * disable the timer to wait for the first call to
+                 * set_next_event().
+                 */
+                __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+                break;
+
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device lpc32xx_clkevt = {
+        .name           = "lpc32xx_clkevt",
+        .features       = CLOCK_EVT_FEAT_ONESHOT,
+        .shift          = 32,
+        .rating         = 300,
+        .set_next_event = lpc32xx_clkevt_next_event,
+        .set_mode       = lpc32xx_clkevt_mode,
+};
+
+static irqreturn_t lpc32xx_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &lpc32xx_clkevt;
+
+        /* Clear match */
+        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction lpc32xx_timer_irq = {
+        .name           = "LPC32XX Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = lpc32xx_timer_interrupt,
+};
+
+/*
+ * The clock management driver isn't initialized at this point, so the
+ * clocks need to be enabled here manually and then tagged as used in
+ * the clock driver initialization
+ */
+static void __init lpc32xx_timer_init(void)
+{
+        u32 clkrate, pllreg;
+
+        /* Enable timer clock */
+        __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN |
+                LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN,
+                LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1);
+
+        /*
+         * The clock driver isn't initialized at this point. So determine if
+         * the SYSCLK is driven from the PLL397 or main oscillator and then use
+         * it to compute the PLL frequency and the PCLK divider to get the base
+         * timer rates. This rate is needed to compute the tick rate.
+         */
+        if (clk_is_sysclk_mainosc() != 0)
+                clkrate = LPC32XX_MAIN_OSC_FREQ;
+        else
+                clkrate = 397 * LPC32XX_CLOCK_OSC_FREQ;
+
+        /* Get ARM HCLKPLL register and convert it into a frequency */
+        pllreg = __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL) & 0x1FFFF;
+        clkrate = clk_get_pllrate_from_reg(clkrate, pllreg);
+
+        /* Get PCLK divider and divide ARM PLL clock by it to get timer rate */
+        clkrate = clkrate / clk_get_pclk_div();
+
+        /* Initial timer setup */
+        __raw_writel(0, LCP32XX_TIMER_TCR(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_MTCH_BIT(0),
+                LCP32XX_TIMER_IR(LPC32XX_TIMER0_BASE));
+        __raw_writel(1, LCP32XX_TIMER_MR0(LPC32XX_TIMER0_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_MCR_MTCH(0) |
+                LCP32XX_TIMER_CNTR_MCR_STOP(0) |
+                LCP32XX_TIMER_CNTR_MCR_RESET(0),
+                LCP32XX_TIMER_MCR(LPC32XX_TIMER0_BASE));
+
+        /* Setup tick interrupt */
+        setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
+
+        /* Setup the clockevent structure. */
+        lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
+                lpc32xx_clkevt.shift);
+        lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
+                &lpc32xx_clkevt);
+        lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
+                &lpc32xx_clkevt) + 1;
+        lpc32xx_clkevt.cpumask = cpumask_of(0);
+        clockevents_register_device(&lpc32xx_clkevt);
+
+        /* Use timer1 as clock source. */
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_RESET,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LCP32XX_TIMER_PR(LPC32XX_TIMER1_BASE));
+        __raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
+        __raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
+                LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
+        lpc32xx_clksrc.mult = clocksource_hz2mult(clkrate,
+                lpc32xx_clksrc.shift);
+        clocksource_register(&lpc32xx_clksrc);
+}
+
+struct sys_timer lpc32xx_timer = {
+        .init           = &lpc32xx_timer_init,
+};
+
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0acaed..7ff8020d4d24 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 
-obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644
index 000000000000..523d213bf79e
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
+/*
+ * linux/arch/arm/mach-msm/gpio.c
+ *
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2008 Google, Inc.
+ * Copyright (C) 2009 Pavel Machek <pavel@ucw.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include "board-trout.h"
+
+struct msm_gpio_chip {
+        struct gpio_chip        chip;
+        void __iomem            *reg;   /* Base of register bank */
+        u8                      shadow;
+};
+
+#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
+
+static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+        unsigned mask = 1 << offset;
+
+        return !!(readb(msm_gpio->reg) & mask);
+}
+
+static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+        struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+        unsigned mask = 1 << offset;
+
+        if (val)
+                msm_gpio->shadow |= mask;
+        else
+                msm_gpio->shadow &= ~mask;
+
+        writeb(msm_gpio->shadow, msm_gpio->reg);
+}
+
+static int msm_gpiolib_direction_input(struct gpio_chip *chip,
+                                        unsigned offset)
+{
+        msm_gpiolib_set(chip, offset, 0);
+        return 0;
+}
+
+static int msm_gpiolib_direction_output(struct gpio_chip *chip,
+                                         unsigned offset, int val)
+{
+        msm_gpiolib_set(chip, offset, val);
+        return 0;
+}
+
+#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)           \
+        {                                                               \
+                .chip = {                                               \
+                        .label            = name,                       \
+                        .direction_input  = msm_gpiolib_direction_input,\
+                        .direction_output = msm_gpiolib_direction_output, \
+                        .get              = msm_gpiolib_get,            \
+                        .set              = msm_gpiolib_set,            \
+                        .base             = base_gpio,                  \
+                        .ngpio            = 8,                          \
+                },                                                      \
+                .reg = (void *) reg_num + TROUT_CPLD_BASE,              \
+                .shadow = shadow_val,                                   \
+        }
+
+static struct msm_gpio_chip msm_gpio_banks[] = {
+#if defined(CONFIG_MSM_DEBUG_UART1)
+        /* H2W pins <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
+#else
+        /* H2W pins <-> UART3, Bluetooth <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x80),
+#endif
+        /* I2C pull */
+        TROUT_GPIO_BANK("MISC3", 0x02,   TROUT_GPIO_MISC3_BASE, 0x04),
+        TROUT_GPIO_BANK("MISC4", 0x04,   TROUT_GPIO_MISC4_BASE, 0),
+        /* mmdi 32k en */
+        TROUT_GPIO_BANK("MISC5", 0x06,   TROUT_GPIO_MISC5_BASE, 0x04),
+        TROUT_GPIO_BANK("INT2", 0x08,    TROUT_GPIO_INT2_BASE,  0),
+        TROUT_GPIO_BANK("MISC1", 0x0a,   TROUT_GPIO_MISC1_BASE, 0),
+        TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
+};
+
+/*
+ * Called from the processor-specific init to enable GPIO pin support.
+ */
+int __init trout_init_gpio(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
+                gpiochip_add(&msm_gpio_banks[i].chip);
+
+        return 0;
+}
+
+postcore_initcall(trout_init_gpio);
+
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5a0a61..651851c3e1dd 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
+/* linux/arch/arm/mach-msm/board-trout.h
+** Author: Brian Swetland <swetland@google.com>
+*/
+#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+
+#include <mach/board.h>
+
+#define MSM_SMI_BASE            0x00000000
+#define MSM_SMI_SIZE            0x00800000
+
+#define MSM_EBI_BASE            0x10000000
+#define MSM_EBI_SIZE            0x06e00000
+
+#define MSM_PMEM_GPU0_BASE      0x00000000
+#define MSM_PMEM_GPU0_SIZE      0x00700000
+
+#define MSM_PMEM_MDP_BASE       0x02000000
+#define MSM_PMEM_MDP_SIZE       0x00800000
+
+#define MSM_PMEM_ADSP_BASE      0x02800000
+#define MSM_PMEM_ADSP_SIZE      0x00800000
+
+#define MSM_PMEM_CAMERA_BASE    0x03000000
+#define MSM_PMEM_CAMERA_SIZE    0x00800000
+
+#define MSM_FB_BASE             0x03800000
+#define MSM_FB_SIZE             0x00100000
+
+#define MSM_LINUX_BASE          MSM_EBI_BASE
+#define MSM_LINUX_SIZE          0x06500000
+
+#define MSM_PMEM_GPU1_SIZE      0x800000
+#define MSM_PMEM_GPU1_BASE      (MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE)
+
+#define MSM_RAM_CONSOLE_BASE    (MSM_EBI_BASE + 0x6d00000)
+#define MSM_RAM_CONSOLE_SIZE    (128 * SZ_1K)
+
+#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
+#error invalid memory map
+#endif
+
+#define DECLARE_MSM_IOMAP
+#include <mach/msm_iomap.h>
+
+#define TROUT_4_BALL_UP_0     1
+#define TROUT_4_BALL_LEFT_0   18
+#define TROUT_4_BALL_DOWN_0   57
+#define TROUT_4_BALL_RIGHT_0  91
+
+#define TROUT_5_BALL_UP_0     94
+#define TROUT_5_BALL_LEFT_0   18
+#define TROUT_5_BALL_DOWN_0   90
+#define TROUT_5_BALL_RIGHT_0  19
+
+#define TROUT_POWER_KEY     20
+
+#define TROUT_4_TP_LS_EN    19
+#define TROUT_5_TP_LS_EN    1
 
 #define TROUT_CPLD_BASE   0xE8100000
 #define TROUT_CPLD_START  0x98000000
 #define TROUT_CPLD_SIZE   SZ_4K
 
+#define TROUT_GPIO_CABLE_IN1            (83)
+#define TROUT_GPIO_CABLE_IN2            (49)
+
+#define TROUT_GPIO_START (128)
+
+#define TROUT_GPIO_INT_MASK0_REG            (0x0c)
+#define TROUT_GPIO_INT_STAT0_REG            (0x0e)
+#define TROUT_GPIO_INT_MASK1_REG            (0x14)
+#define TROUT_GPIO_INT_STAT1_REG            (0x10)
+
+#define TROUT_GPIO_HAPTIC_PWM               (28)
+#define TROUT_GPIO_PS_HOLD                  (25)
+
+#define TROUT_GPIO_MISC2_BASE               (TROUT_GPIO_START + 0x00)
+#define TROUT_GPIO_MISC3_BASE               (TROUT_GPIO_START + 0x08)
+#define TROUT_GPIO_MISC4_BASE               (TROUT_GPIO_START + 0x10)
+#define TROUT_GPIO_MISC5_BASE               (TROUT_GPIO_START + 0x18)
+#define TROUT_GPIO_INT2_BASE                (TROUT_GPIO_START + 0x20)
+#define TROUT_GPIO_MISC1_BASE               (TROUT_GPIO_START + 0x28)
+#define TROUT_GPIO_VIRTUAL_BASE             (TROUT_GPIO_START + 0x30)
+#define TROUT_GPIO_INT5_BASE                (TROUT_GPIO_START + 0x48)
+
+#define TROUT_GPIO_CHARGER_EN               (TROUT_GPIO_MISC2_BASE + 0)
+#define TROUT_GPIO_ISET                     (TROUT_GPIO_MISC2_BASE + 1)
+#define TROUT_GPIO_H2W_DAT_DIR              (TROUT_GPIO_MISC2_BASE + 2)
+#define TROUT_GPIO_H2W_CLK_DIR              (TROUT_GPIO_MISC2_BASE + 3)
+#define TROUT_GPIO_H2W_DAT_GPO              (TROUT_GPIO_MISC2_BASE + 4)
+#define TROUT_GPIO_H2W_CLK_GPO              (TROUT_GPIO_MISC2_BASE + 5)
+#define TROUT_GPIO_H2W_SEL0                 (TROUT_GPIO_MISC2_BASE + 6)
+#define TROUT_GPIO_H2W_SEL1                 (TROUT_GPIO_MISC2_BASE + 7)
+
+#define TROUT_GPIO_SPOTLIGHT_EN             (TROUT_GPIO_MISC3_BASE + 0)
+#define TROUT_GPIO_FLASH_EN                 (TROUT_GPIO_MISC3_BASE + 1)
+#define TROUT_GPIO_I2C_PULL                 (TROUT_GPIO_MISC3_BASE + 2)
+#define TROUT_GPIO_TP_I2C_PULL              (TROUT_GPIO_MISC3_BASE + 3)
+#define TROUT_GPIO_TP_EN                    (TROUT_GPIO_MISC3_BASE + 4)
+#define TROUT_GPIO_JOG_EN                   (TROUT_GPIO_MISC3_BASE + 5)
+#define TROUT_GPIO_UI_LED_EN                (TROUT_GPIO_MISC3_BASE + 6)
+#define TROUT_GPIO_QTKEY_LED_EN             (TROUT_GPIO_MISC3_BASE + 7)
+
+#define TROUT_GPIO_VCM_PWDN                 (TROUT_GPIO_MISC4_BASE + 0)
+#define TROUT_GPIO_USB_H2W_SW               (TROUT_GPIO_MISC4_BASE + 1)
+#define TROUT_GPIO_COMPASS_RST_N            (TROUT_GPIO_MISC4_BASE + 2)
+#define TROUT_GPIO_HAPTIC_EN_UP             (TROUT_GPIO_MISC4_BASE + 3)
+#define TROUT_GPIO_HAPTIC_EN_MAIN           (TROUT_GPIO_MISC4_BASE + 4)
+#define TROUT_GPIO_USB_PHY_RST_N            (TROUT_GPIO_MISC4_BASE + 5)
+#define TROUT_GPIO_WIFI_PA_RESETX           (TROUT_GPIO_MISC4_BASE + 6)
+#define TROUT_GPIO_WIFI_EN                  (TROUT_GPIO_MISC4_BASE + 7)
+
+#define TROUT_GPIO_BT_32K_EN                (TROUT_GPIO_MISC5_BASE + 0)
+#define TROUT_GPIO_MAC_32K_EN               (TROUT_GPIO_MISC5_BASE + 1)
+#define TROUT_GPIO_MDDI_32K_EN              (TROUT_GPIO_MISC5_BASE + 2)
+#define TROUT_GPIO_COMPASS_32K_EN           (TROUT_GPIO_MISC5_BASE + 3)
+
+#define TROUT_GPIO_NAVI_ACT_N               (TROUT_GPIO_INT2_BASE + 0)
+#define TROUT_GPIO_COMPASS_IRQ              (TROUT_GPIO_INT2_BASE + 1)
+#define TROUT_GPIO_SLIDING_DET              (TROUT_GPIO_INT2_BASE + 2)
+#define TROUT_GPIO_AUD_HSMIC_DET_N          (TROUT_GPIO_INT2_BASE + 3)
+#define TROUT_GPIO_SD_DOOR_N                (TROUT_GPIO_INT2_BASE + 4)
+#define TROUT_GPIO_CAM_BTN_STEP1_N          (TROUT_GPIO_INT2_BASE + 5)
+#define TROUT_GPIO_CAM_BTN_STEP2_N          (TROUT_GPIO_INT2_BASE + 6)
+#define TROUT_GPIO_TP_ATT_N                 (TROUT_GPIO_INT2_BASE + 7)
+#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE   (TROUT_GPIO_NAVI_ACT_N)
+#define TROUT_GPIO_BANK0_LAST_INT_SOURCE    (TROUT_GPIO_TP_ATT_N)
+
+#define TROUT_GPIO_H2W_DAT_GPI              (TROUT_GPIO_MISC1_BASE + 0)
+#define TROUT_GPIO_H2W_CLK_GPI              (TROUT_GPIO_MISC1_BASE + 1)
+#define TROUT_GPIO_CPLD128_VER_0            (TROUT_GPIO_MISC1_BASE + 4)
+#define TROUT_GPIO_CPLD128_VER_1            (TROUT_GPIO_MISC1_BASE + 5)
+#define TROUT_GPIO_CPLD128_VER_2            (TROUT_GPIO_MISC1_BASE + 6)
+#define TROUT_GPIO_CPLD128_VER_3            (TROUT_GPIO_MISC1_BASE + 7)
+
+#define TROUT_GPIO_SDMC_CD_N                (TROUT_GPIO_VIRTUAL_BASE + 0)
+#define TROUT_GPIO_END                      (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE   (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_LAST_INT_SOURCE    (TROUT_GPIO_SDMC_CD_N)
+
+#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
+        (TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
+
+#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define TROUT_INT_BANK0_COUNT (8)
+#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_BANK1_COUNT (1)
+#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
+                        TROUT_INT_BANK1_COUNT - 1)
+#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
+        (TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
+        (TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
+
+#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
+#define TROUT_BANK_TO_MASK_REG(bank) \
+        (bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
+#define TROUT_BANK_TO_STAT_REG(bank) \
+        (bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
+
+#endif /* GUARD */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441b4374..83e47c0d5c2e 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
 /**
  * struct msm_gpio - GPIO pin description
  * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644
index eb7660f5d4b7..000000000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if ARCH_MX1
-
-comment "MX1 platforms:"
-
-config MACH_MXLADS
-        bool
-
-config ARCH_MX1ADS
-        bool "MX1ADS platform"
-        select MACH_MXLADS
-        help
-          Say Y here if you are using Motorola MX1ADS/MXLADS boards
-
-config MACH_SCB9328
-        bool "Synertronixx scb9328"
-        help
-          Say Y here if you are using a Synertronixx scb9328 board
-
-endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644
index fc2ddf82441b..000000000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
-obj-y                   += generic.o clock.o devices.o
-
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += ksym_mx1.o mx1_camera_fiq.o
-
-# Specific board support
-obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
-obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644
index 8ed1492288a2..000000000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y   := 0x08008000
-params_phys-y   := 0x08000100
-initrd_phys-y   := 0x08800000
-
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
deleted file mode 100644
index 22e866ff0c09..000000000000
--- a/arch/arm/mach-mx1/crm_regs.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- *
- * This file may be distributed under the terms of the GNU General
- * Public License, version 2.
- */
-
-#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-
-#define CCM_BASE        IO_ADDRESS(CCM_BASE_ADDR)
-#define SCM_BASE        IO_ADDRESS(SCM_BASE_ADDR)
-
-/* CCM register addresses */
-#define CCM_CSCR        (CCM_BASE + 0x0)
-#define CCM_MPCTL0      (CCM_BASE + 0x4)
-#define CCM_MPCTL1      (CCM_BASE + 0x8)
-#define CCM_SPCTL0      (CCM_BASE + 0xC)
-#define CCM_SPCTL1      (CCM_BASE + 0x10)
-#define CCM_PCDR        (CCM_BASE + 0x20)
-
-#define CCM_CSCR_CLKO_OFFSET    29
-#define CCM_CSCR_CLKO_MASK      (0x7 << 29)
-#define CCM_CSCR_USB_OFFSET     26
-#define CCM_CSCR_USB_MASK       (0x7 << 26)
-#define CCM_CSCR_SPLL_RESTART   (1 << 22)
-#define CCM_CSCR_MPLL_RESTART   (1 << 21)
-#define CCM_CSCR_OSC_EN_SHIFT   17
-#define CCM_CSCR_SYSTEM_SEL     (1 << 16)
-#define CCM_CSCR_BCLK_OFFSET    10
-#define CCM_CSCR_BCLK_MASK      (0xF << 10)
-#define CCM_CSCR_PRESC          (1 << 15)
-#define CCM_CSCR_SPEN           (1 << 1)
-#define CCM_CSCR_MPEN           (1 << 0)
-
-#define CCM_PCDR_PCLK3_OFFSET   16
-#define CCM_PCDR_PCLK3_MASK     (0x7F << 16)
-#define CCM_PCDR_PCLK2_OFFSET   4
-#define CCM_PCDR_PCLK2_MASK     (0xF << 4)
-#define CCM_PCDR_PCLK1_OFFSET   0
-#define CCM_PCDR_PCLK1_MASK     0xF
-
-/* SCM register addresses */
-#define SCM_SIDR        (SCM_BASE + 0x0)
-#define SCM_FMCR        (SCM_BASE + 0x4)
-#define SCM_GPCR        (SCM_BASE + 0x8)
-#define SCM_GCCR        (SCM_BASE + 0xC)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET      3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET      2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET      1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET     0
-
-#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644
index b6be29d1cb08..000000000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
- * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#include "devices.h"
-
-static struct resource imx_csi_resources[] = {
-        {
-                .start  = 0x00224000,
-                .end    = 0x00224010,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = CSI_INT,
-                .end    = CSI_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static u64 imx_csi_dmamask = 0xffffffffUL;
-
-struct platform_device imx_csi_device = {
-        .name           = "mx1-camera",
-        .id             = 0, /* This is used to put cameras on this interface */
-        .dev            = {
-                .dma_mask = &imx_csi_dmamask,
-                .coherent_dma_mask = 0xffffffff,
-        },
-        .resource       = imx_csi_resources,
-        .num_resources  = ARRAY_SIZE(imx_csi_resources),
-};
-
-static struct resource imx_i2c_resources[] = {
-        {
-                .start  = 0x00217000,
-                .end    = 0x00217010,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = I2C_INT,
-                .end    = I2C_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_i2c_device = {
-        .name           = "imx-i2c",
-        .id             = 0,
-        .resource       = imx_i2c_resources,
-        .num_resources  = ARRAY_SIZE(imx_i2c_resources),
-};
-
-static struct resource imx_uart1_resources[] = {
-        {
-                .start  = UART1_BASE_ADDR,
-                .end    = UART1_BASE_ADDR + 0xD0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = UART1_MINT_RX,
-                .end    = UART1_MINT_RX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART1_MINT_TX,
-                .end    = UART1_MINT_TX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART1_MINT_RTS,
-                .end    = UART1_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_uart1_device = {
-        .name           = "imx-uart",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_uart1_resources),
-        .resource       = imx_uart1_resources,
-};
-
-static struct resource imx_uart2_resources[] = {
-        {
-                .start  = UART2_BASE_ADDR,
-                .end    = UART2_BASE_ADDR + 0xD0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = UART2_MINT_RX,
-                .end    = UART2_MINT_RX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART2_MINT_TX,
-                .end    = UART2_MINT_TX,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = UART2_MINT_RTS,
-                .end    = UART2_MINT_RTS,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_uart2_device = {
-        .name           = "imx-uart",
-        .id             = 1,
-        .num_resources  = ARRAY_SIZE(imx_uart2_resources),
-        .resource       = imx_uart2_resources,
-};
-
-static struct resource imx_rtc_resources[] = {
-        {
-                .start  = 0x00204000,
-                .end    = 0x00204024,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = RTC_INT,
-                .end    = RTC_INT,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = RTC_SAMINT,
-                .end    = RTC_SAMINT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_rtc_device = {
-        .name           = "rtc-imx",
-        .id             = 0,
-        .resource       = imx_rtc_resources,
-        .num_resources  = ARRAY_SIZE(imx_rtc_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-        {
-                .start  = 0x00201000,
-                .end    = 0x00201008,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = WDT_INT,
-                .end    = WDT_INT,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_wdt_device = {
-        .name           = "imx-wdt",
-        .id             = 0,
-        .resource       = imx_wdt_resources,
-        .num_resources  = ARRAY_SIZE(imx_wdt_resources),
-};
-
-static struct resource imx_usb_resources[] = {
-        {
-                .start  = 0x00212000,
-                .end    = 0x00212148,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = USBD_INT0,
-                .end    = USBD_INT0,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT1,
-                .end    = USBD_INT1,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT2,
-                .end    = USBD_INT2,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT3,
-                .end    = USBD_INT3,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT4,
-                .end    = USBD_INT4,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT5,
-                .end    = USBD_INT5,
-                .flags  = IORESOURCE_IRQ,
-        }, {
-                .start  = USBD_INT6,
-                .end    = USBD_INT6,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device imx_usb_device = {
-        .name           = "imx_udc",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(imx_usb_resources),
-        .resource       = imx_usb_resources,
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-        {
-                .chip.label = "gpio-0",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
-                .irq = GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        }, {
-                .chip.label = "gpio-1",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
-                .irq = GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        }, {
-                .chip.label = "gpio-2",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
-                .irq = GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        }, {
-                .chip.label = "gpio-3",
-                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
-                .irq = GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        }
-};
-
-int __init mxc_register_gpios(void)
-{
-        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644
index 0da5d7cce3a2..000000000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
-extern struct platform_device imx_csi_device;
-extern struct platform_device imx_i2c_device;
-extern struct platform_device imx_uart1_device;
-extern struct platform_device imx_uart2_device;
-extern struct platform_device imx_rtc_device;
-extern struct platform_device imx_wdt_device;
-extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c
deleted file mode 100644
index 1c0c835b2252..000000000000
--- a/arch/arm/mach-mx2/serial.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include "devices.h"
-
-static struct resource uart0[] = {
-        {
-                .start = MX2x_UART1_BASE_ADDR,
-                .end = MX2x_UART1_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART1,
-                .end = MX2x_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = MX2x_UART2_BASE_ADDR,
-                .end = MX2x_UART2_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART2,
-                .end = MX2x_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = MX2x_UART3_BASE_ADDR,
-                .end = MX2x_UART3_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART3,
-                .end = MX2x_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-        {
-                .start = MX2x_UART4_BASE_ADDR,
-                .end = MX2x_UART4_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX2x_INT_UART4,
-                .end = MX2x_INT_UART4,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource uart4[] = {
-        {
-                .start = MX27_UART5_BASE_ADDR,
-                .end = MX27_UART5_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_UART5,
-                .end = MX27_INT_UART5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-
-static struct resource uart5[] = {
-        {
-                .start = MX27_UART6_BASE_ADDR,
-                .end = MX27_UART6_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MX27_INT_UART6,
-                .end = MX27_INT_UART6,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device5 = {
-        .name = "imx-uart",
-        .id = 5,
-        .resource = uart5,
-        .num_resources = ARRAY_SIZE(uart5),
-};
-#endif
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d217314ee9..c71a7bc19284 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,5 +4,28 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
         bool "Support MX25PDK (3DS) Platform"
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+
+config MACH_EUKREA_CPUIMX25
+        bool "Support Eukrea CPUIMX25 Platform"
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX25
+        default MACH_EUKREA_MBIMXSD25_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD25_BASEBOARD
+        prompt "Eukrea MBIMXSD development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
 
 endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5ced8c..d9e46ce00a4e 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
 obj-y                           := mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)         += clock.o
-obj-$(CONFIG_MACH_MX25_3DS)     += mach-mx25pdk.o
+obj-$(CONFIG_MACH_MX25_3DS)     += mach-mx25_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25)              += mach-cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 155014993b13..40c7cc41cee3 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
         return get_rate_per(15);
 }
 
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+        return get_rate_per(14);
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+        return get_rate_per(13);
+}
+
 static unsigned long get_rate_i2c(struct clk *clk)
 {
         return get_rate_per(6);
@@ -129,9 +139,17 @@ static unsigned long get_rate_lcdc(struct clk *clk)
         return get_rate_per(7);
 }
 
+static unsigned long get_rate_csi(struct clk *clk)
+{
+        return get_rate_per(0);
+}
+
 static unsigned long get_rate_otg(struct clk *clk)
 {
-        return 48000000; /* FIXME */
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_upll();
+
+        return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
 }
 
 static int clk_cgcr_enable(struct clk *clk)
@@ -166,14 +184,40 @@ static void clk_cgcr_disable(struct clk *clk)
                 .secondary      = s,                    \
         }
 
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit  reg     offset  clock
+ *
+ * 0    CGCR1   0       AUDMUX
+ * 12   CGCR1   12      ESAI
+ * 16   CGCR1   16      GPIO1
+ * 17   CGCR1   17      GPIO2
+ * 18   CGCR1   18      GPIO3
+ * 23   CGCR1   23      I2C1
+ * 24   CGCR1   24      I2C2
+ * 25   CGCR1   25      I2C3
+ * 27   CGCR1   27      IOMUXC
+ * 28   CGCR1   28      KPP
+ * 30   CGCR1   30      OWIRE
+ * 36   CGCR2   4       RTIC
+ * 51   CGCR2   19      WDOG
+ */
+
 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
+DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,        NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,       NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,       NULL, &lcdc_ahb_clk);
+DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
+DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +235,13 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,    0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,   0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
+DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
+DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
+DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
+DEFINE_CLOCK(can1_clk,   0, CCM_CGCR1,  2, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(can2_clk,   0, CCM_CGCR1,  3, get_rate_ipg, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)        \
         {                               \
@@ -217,7 +268,7 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
-        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
         _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
@@ -225,6 +276,13 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
         _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
         _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+        _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
+        _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+        _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+        _REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
+        _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
 };
 
 int __init mx25_clocks_init(void)
@@ -238,9 +296,13 @@ int __init mx25_clocks_init(void)
         __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
         __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
         __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+        clk_enable(&uart1_clk);
+#endif
 
-        /* Clock source for lcdc is upll */
-        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
+        /* Clock source for lcdc and csi is upll */
+        __raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
+                        CRM_BASE + 0x64);
 
         mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
new file mode 100644
index 000000000000..d86a7c3ca8b0
--- /dev/null
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx25.h>
+#include <mach/devices-common.h>
+
+#define imx25_add_flexcan0(pdata)       \
+        imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata)
+#define imx25_add_flexcan1(pdata)       \
+        imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata)
+
+#define imx25_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
+#define imx25_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
+#define imx25_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
+
+#define imx25_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
+#define imx25_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
+#define imx25_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
+#define imx25_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
+#define imx25_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+
+#define imx25_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
+
+#define imx25_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
+#define imx25_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
+#define imx25_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa400eb..3468eb15b236 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,103 +22,6 @@
 #include <mach/mx25.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-        {
-                .start = 0x43f90000,
-                .end = 0x43f93fff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 45,
-                .end = 45,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = 0x43f94000,
-                .end = 0x43f97fff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 32,
-                .end = 32,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = 0x5000c000,
-                .end = 0x5000ffff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 18,
-                .end = 18,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-        {
-                .start = 0x50008000,
-                .end = 0x5000bfff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 5,
-                .end = 5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-        {
-                .start = 0x5002c000,
-                .end = 0x5002ffff,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = 40,
-                .end = 40,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-
-#define MX25_OTG_BASE_ADDR 0x53FF4000
-
 static u64 otg_dmamask = DMA_BIT_MASK(32);
 
 static struct resource mxc_otg_resources[] = {
@@ -181,63 +84,6 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-static struct resource mxc_spi_resources0[] = {
-        {
-               .start = 0x43fa4000,
-               .end = 0x43fa7fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 14,
-               .end = 14,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device0 = {
-        .name = "spi_imx",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
-        .resource = mxc_spi_resources0,
-};
-
-static struct resource mxc_spi_resources1[] = {
-        {
-               .start = 0x50010000,
-               .end = 0x50013fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 13,
-               .end = 13,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device1 = {
-        .name = "spi_imx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
-        .resource = mxc_spi_resources1,
-};
-
-static struct resource mxc_spi_resources2[] = {
-        {
-               .start = 0x50004000,
-               .end = 0x50007fff,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = 0,
-               .end = 0,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device2 = {
-        .name = "spi_imx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
-        .resource = mxc_spi_resources2,
-};
-
 static struct resource mxc_pwm_resources0[] = {
         {
                 .start  = 0x53fe0000,
@@ -333,63 +179,6 @@ struct platform_device mxc_pwm_device3 = {
         .resource = mxc_pwm_resources3,
 };
 
-static struct resource mxc_i2c_1_resources[] = {
-        {
-                .start  = 0x43f80000,
-                .end    = 0x43f83fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 3,
-                .end    = 3,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-        .resource = mxc_i2c_1_resources,
-};
-
-static struct resource mxc_i2c_2_resources[] = {
-        {
-                .start  = 0x43f98000,
-                .end    = 0x43f9bfff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 4,
-                .end    = 4,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-        .resource = mxc_i2c_2_resources,
-};
-
-static struct resource mxc_i2c_3_resources[] = {
-        {
-                .start  = 0x43f84000,
-                .end    = 0x43f87fff,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = 10,
-                .end    = 10,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-
-struct platform_device mxc_i2c_device2 = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
-        .resource = mxc_i2c_3_resources,
-};
-
 static struct mxc_gpio_port imx_gpio_ports[] = {
         {
                 .chip.label = "gpio-0",
@@ -414,7 +203,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
         }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx25_register_gpios(void)
 {
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -439,26 +228,6 @@ struct platform_device mx25_fec_device = {
         .resource       = mx25_fec_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-        {
-                .start  = MX25_NFC_BASE_ADDR,
-                .end    = MX25_NFC_BASE_ADDR + 0x1fff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = MX25_INT_NANDFC,
-                .end    = MX25_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_nand_device = {
-        .name           = "mxc_nand",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(mxc_nand_resources),
-        .resource       = mxc_nand_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
         {
                 .start  = MX25_DRYICE_BASE_ADDR,
@@ -515,3 +284,83 @@ struct platform_device mxc_wdt = {
         .num_resources = ARRAY_SIZE(mxc_wdt_resources),
         .resource = mxc_wdt_resources,
 };
+
+static struct resource mx25_kpp_resources[] = {
+        {
+                .start  = MX25_KPP_BASE_ADDR,
+                .end    = MX25_KPP_BASE_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX25_INT_KPP,
+                .end    = MX25_INT_KPP,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mx25_kpp_device = {
+        .name   = "imx-keypad",
+        .id     = -1,
+        .num_resources  = ARRAY_SIZE(mx25_kpp_resources),
+        .resource       = mx25_kpp_resources,
+};
+
+static struct resource imx_ssi_resources0[] = {
+        {
+                .start  = MX25_SSI1_BASE_ADDR,
+                .end    = MX25_SSI1_BASE_ADDR + 0x3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MX25_INT_SSI1,
+                .end    = MX25_INT_SSI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource imx_ssi_resources1[] = {
+        {
+                .start  = MX25_SSI2_BASE_ADDR,
+                .end    = MX25_SSI2_BASE_ADDR + 0x3fff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MX25_INT_SSI2,
+                .end    = MX25_INT_SSI2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device imx_ssi_device0 = {
+        .name = "imx-ssi",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources0),
+        .resource = imx_ssi_resources0,
+};
+
+struct platform_device imx_ssi_device1 = {
+        .name = "imx-ssi",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_ssi_resources1),
+        .resource = imx_ssi_resources1,
+};
+
+static struct resource mx25_csi_resources[] = {
+        {
+                .start  = MX25_CSI_BASE_ADDR,
+                .end    = MX25_CSI_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = MX25_INT_CSI,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+struct platform_device mx25_csi_device = {
+        .name   = "mx2-camera",
+        .id     = 0,
+        .num_resources  = ARRAY_SIZE(mx25_csi_resources),
+        .resource       = mx25_csi_resources,
+        .dev            = {
+                .coherent_dma_mask = 0xffffffff,
+        },
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0a0be6..4aceb68e35a7 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -1,24 +1,16 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_otg;
 extern struct platform_device otg_udc_device;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device mxc_pwm_device0;
 extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx25_fec_device;
-extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mx25_kpp_device;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
+extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..91931dcb0689
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+        /* LCD */
+        MX25_PAD_LD0__LD0,
+        MX25_PAD_LD1__LD1,
+        MX25_PAD_LD2__LD2,
+        MX25_PAD_LD3__LD3,
+        MX25_PAD_LD4__LD4,
+        MX25_PAD_LD5__LD5,
+        MX25_PAD_LD6__LD6,
+        MX25_PAD_LD7__LD7,
+        MX25_PAD_LD8__LD8,
+        MX25_PAD_LD9__LD9,
+        MX25_PAD_LD10__LD10,
+        MX25_PAD_LD11__LD11,
+        MX25_PAD_LD12__LD12,
+        MX25_PAD_LD13__LD13,
+        MX25_PAD_LD14__LD14,
+        MX25_PAD_LD15__LD15,
+        MX25_PAD_GPIO_E__LD16,
+        MX25_PAD_GPIO_F__LD17,
+        MX25_PAD_HSYNC__HSYNC,
+        MX25_PAD_VSYNC__VSYNC,
+        MX25_PAD_LSCLK__LSCLK,
+        MX25_PAD_OE_ACD__OE_ACD,
+        MX25_PAD_CONTRAST__CONTRAST,
+        /* LCD_PWR */
+        MX25_PAD_PWM__GPIO_1_26,
+        /* LED */
+        MX25_PAD_POWER_FAIL__GPIO_3_19,
+        /* SWITCH */
+        MX25_PAD_VSTBY_ACK__GPIO_3_18,
+        /* UART2 */
+        MX25_PAD_UART2_RTS__UART2_RTS,
+        MX25_PAD_UART2_CTS__UART2_CTS,
+        MX25_PAD_UART2_TXD__UART2_TXD,
+        MX25_PAD_UART2_RXD__UART2_RXD,
+        /* SD1 */
+        MX25_PAD_SD1_CMD__SD1_CMD,
+        MX25_PAD_SD1_CLK__SD1_CLK,
+        MX25_PAD_SD1_DATA0__SD1_DATA0,
+        MX25_PAD_SD1_DATA1__SD1_DATA1,
+        MX25_PAD_SD1_DATA2__SD1_DATA2,
+        MX25_PAD_SD1_DATA3__SD1_DATA3,
+        /* SD1 CD */
+        MX25_PAD_DE_B__GPIO_2_20,
+        /* I2S */
+        MX25_PAD_KPP_COL3__AUD5_TXFS,
+        MX25_PAD_KPP_COL2__AUD5_TXC,
+        MX25_PAD_KPP_COL1__AUD5_RXD,
+        MX25_PAD_KPP_COL0__AUD5_TXD,
+};
+
+#define GPIO_LED1       83
+#define GPIO_SWITCH1    82
+#define GPIO_SD1CD      52
+#define GPIO_LCDPWR     26
+
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
+        {
+                .mode   = {
+                        .name           = "CMO-QVGA",
+                        .refresh        = 60,
+                        .xres           = 320,
+                        .yres           = 240,
+                        .pixclock       = KHZ2PICOS(6500),
+                        .left_margin    = 30,
+                        .right_margin   = 38,
+                        .upper_margin   = 20,
+                        .lower_margin   = 3,
+                        .hsync_len      = 15,
+                        .vsync_len      = 4,
+                },
+                .bpp    = 16,
+                .pcr    = 0xCAD08B80,
+        },
+};
+
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+        .mode           = eukrea_mximxsd_modes,
+        .num_modes      = ARRAY_SIZE(eukrea_mximxsd_modes),
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00040060,
+};
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_LCDPWR, 1);
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+        .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_LED1,
+        },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+        .leds           = eukrea_mbimxsd_leds,
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &eukrea_mbimxsd_led_info,
+        },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+        {
+                .gpio           = GPIO_SWITCH1,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &eukrea_mbimxsd_button_data,
+        }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_mbimxsd_leds_gpio,
+        &eukrea_mbimxsd_button_device,
+        &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx25 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD5*/
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(4),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+        );
+        mxc_audmux_v2_configure_port(4,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
+        imx25_add_imx_uart1(&uart_pdata);
+        mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+        gpio_request(GPIO_LED1, "LED1");
+        gpio_direction_output(GPIO_LED1, 1);
+        gpio_free(GPIO_LED1);
+
+        gpio_request(GPIO_SWITCH1, "SWITCH1");
+        gpio_direction_input(GPIO_SWITCH1);
+        gpio_free(GPIO_SWITCH1);
+
+        gpio_request(GPIO_LCDPWR, "LCDPWR");
+        gpio_direction_output(GPIO_LCDPWR, 1);
+        gpio_free(GPIO_SWITCH1);
+
+        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644
index 000000000000..56b2e26d23b4
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
+ * Copyright 2010 Eric Bénard - Eukréa Electromatique, <eric@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+#include <mach/iomux-mx25.h>
+
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc eukrea_cpuimx25_pads[] = {
+        /* FEC - RMII */
+        MX25_PAD_FEC_MDC__FEC_MDC,
+        MX25_PAD_FEC_MDIO__FEC_MDIO,
+        MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+        MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+        MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+        MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+        MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        /* I2C1 */
+        MX25_PAD_I2C1_CLK__I2C1_CLK,
+        MX25_PAD_I2C1_DAT__I2C1_DAT,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+        .phy    = PHY_INTERFACE_MODE_RMII,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx25_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx25_i2c0_data __initconst = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_UTMI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+        .portsc = MXC_EHCI_MODE_SERIAL,
+        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx25_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
+
+static void __init eukrea_cpuimx25_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
+                        ARRAY_SIZE(eukrea_cpuimx25_pads)))
+                printk(KERN_ERR "error setting cpuimx25 pads !\n");
+
+        imx25_add_imx_uart0(&uart_pdata);
+        imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
+        mxc_register_device(&mx25_rtc_device, NULL);
+        mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+
+        i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
+        imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg, &otg_pdata);
+        }
+        mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+        eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx25_timer_init(void)
+{
+        mx25_clocks_init();
+}
+
+static struct sys_timer eukrea_cpuimx25_timer = {
+        .init   = eukrea_cpuimx25_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+        /* Maintainer: Eukrea Electromatique */
+        .phys_io        = MX25_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = MX25_PHYS_OFFSET + 0x100,
+        .map_io         = mx25_map_io,
+        .init_irq       = mx25_init_irq,
+        .init_machine   = eukrea_cpuimx25_init,
+        .timer          = &eukrea_cpuimx25_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 83d74109e7d8..62bc21f11a71 100644
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -16,6 +16,12 @@
  * Boston, MA  02110-1301, USA.
  */
 
+/*
+ * This machine is known as:
+ *  - i.MX25 3-Stack Development System
+ *  - i.MX25 Platform Development Kit (i.MX25 PDK)
+ */
+
 #include <linux/types.h>
 #include <linux/init.h>
 #include <linux/delay.h>
@@ -24,6 +30,7 @@
 #include <linux/gpio.h>
 #include <linux/fec.h>
 #include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -32,14 +39,14 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx25.h>
-#include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
-#include "devices.h"
 #include <mach/iomux-mx25.h>
 
-static struct imxuart_platform_data uart_pdata = {
+#include "devices-imx25.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -80,6 +87,16 @@ static struct pad_desc mx25pdk_pads[] = {
         MX25_PAD_LSCLK__LSCLK,
         MX25_PAD_OE_ACD__OE_ACD,
         MX25_PAD_CONTRAST__CONTRAST,
+
+        /* Keypad */
+        MX25_PAD_KPP_ROW0__KPP_ROW0,
+        MX25_PAD_KPP_ROW1__KPP_ROW1,
+        MX25_PAD_KPP_ROW2__KPP_ROW2,
+        MX25_PAD_KPP_ROW3__KPP_ROW3,
+        MX25_PAD_KPP_COL0__KPP_COL0,
+        MX25_PAD_KPP_COL1__KPP_COL1,
+        MX25_PAD_KPP_COL2__KPP_COL2,
+        MX25_PAD_KPP_COL3__KPP_COL3,
 };
 
 static struct fec_platform_data mx25_fec_pdata = {
@@ -103,7 +120,8 @@ static void __init mx25pdk_fec_reset(void)
         gpio_set_value(FEC_RESET_B_GPIO, 1);
 }
 
-static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx25pdk_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
         .flash_bbt      = 1,
@@ -137,19 +155,45 @@ static struct imx_fb_platform_data mx25pdk_fb_pdata = {
         .dmacr          = 0x00020010,
 };
 
+static const uint32_t mx25pdk_keymap[] = {
+        KEY(0, 0, KEY_UP),
+        KEY(0, 1, KEY_DOWN),
+        KEY(0, 2, KEY_VOLUMEDOWN),
+        KEY(0, 3, KEY_HOME),
+        KEY(1, 0, KEY_RIGHT),
+        KEY(1, 1, KEY_LEFT),
+        KEY(1, 2, KEY_ENTER),
+        KEY(1, 3, KEY_VOLUMEUP),
+        KEY(2, 0, KEY_F6),
+        KEY(2, 1, KEY_F8),
+        KEY(2, 2, KEY_F9),
+        KEY(2, 3, KEY_F10),
+        KEY(3, 0, KEY_F1),
+        KEY(3, 1, KEY_F2),
+        KEY(3, 2, KEY_F3),
+        KEY(3, 3, KEY_POWER),
+};
+
+static struct matrix_keymap_data mx25pdk_keymap_data = {
+        .keymap         = mx25pdk_keymap,
+        .keymap_size    = ARRAY_SIZE(mx25pdk_keymap),
+};
+
 static void __init mx25pdk_init(void)
 {
         mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
                         ARRAY_SIZE(mx25pdk_pads));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx25_add_imx_uart0(&uart_pdata);
         mxc_register_device(&mxc_usbh2, NULL);
-        mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
+        imx25_add_mxc_nand(&mx25pdk_nand_board_info);
         mxc_register_device(&mx25_rtc_device, NULL);
         mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
+        mxc_register_device(&mxc_wdt, NULL);
 
         mx25pdk_fec_reset();
         mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+        mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data);
 }
 
 static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index a7e587ff3e9e..bb677111fb0f 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -69,8 +65,11 @@ void __init mx25_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx25_register_gpios(void);
+
 void __init mx25_init_irq(void)
 {
         mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+        imx25_register_gpios();
 }
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753fdf25e..85beece802aa 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -15,6 +15,8 @@ comment "MX3 platforms:"
 config MACH_MX31ADS
         bool "Support MX31ADS platforms"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
         default y
         help
           Include support for MX31ADS platform. This includes specific
@@ -34,6 +36,9 @@ config MACH_MX31ADS_WM1133_EV1
 config MACH_PCM037
         bool "Support Phytec pcm037 (i.MX31) platforms"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm037 platform. This includes
@@ -42,6 +47,7 @@ config MACH_PCM037
 config MACH_PCM037_EET
         bool "Support pcm037 EET board extensions"
         depends on MACH_PCM037
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Add support for PCM037 EET baseboard extensions. If you are using the
           OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
@@ -51,6 +57,9 @@ config MACH_MX31LITE
         bool "Support MX31 LITEKIT (LogicPD)"
         select ARCH_MX31
         select MXC_ULPI if USB_ULPI
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX31 LITEKIT platform. This includes specific
           configurations for the board and its peripherals.
@@ -58,6 +67,10 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
         bool "Support MX31PDK (3DS)"
         select ARCH_MX31
+        select MXC_DEBUG_BOARD
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_SPI_IMX
         help
           Include support for MX31PDK (3DS) platform. This includes specific
           configurations for the board and its peripherals.
@@ -74,6 +87,9 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 config MACH_MX31MOBOARD
         bool "Support mx31moboard platforms (EPFL Mobots group)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for mx31moboard platform. This includes specific
@@ -82,6 +98,8 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
         bool "Support MX31 LILLY-1131 platforms (INCO startec)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_SPI_IMX
         select MXC_ULPI if USB_ULPI
         help
           Include support for mx31 based LILLY1131 modules. This includes
@@ -90,6 +108,7 @@ config MACH_MX31LILLY
 config MACH_QONG
         bool "Support Dave/DENX QongEVB-LITE platform"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for Dave/DENX QongEVB-LITE platform. This includes
           specific configurations for the board and its peripherals.
@@ -97,6 +116,10 @@ config MACH_QONG
 config MACH_PCM043
         bool "Support Phytec pcm043 (i.MX35) platforms"
         select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_FLEXCAN
         select MXC_ULPI if USB_ULPI
         help
           Include support for Phytec pcm043 platform. This includes
@@ -105,6 +128,9 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
         bool "Support Atmark Armadillo-500 Development Base Board"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_MXC_NAND
         select MXC_ULPI if USB_ULPI
         help
           Include support for Atmark Armadillo-500 platform. This includes
@@ -113,6 +139,7 @@ config MACH_ARMADILLO5X0
 config MACH_MX35_3DS
         bool "Support MX35PDK platform"
         select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_UART
         default n
         help
           Include support for MX35PDK platform. This includes specific
@@ -121,8 +148,34 @@ config MACH_MX35_3DS
 config MACH_KZM_ARM11_01
         bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
         select ARCH_MX31
+        select IMX_HAVE_PLATFORM_IMX_UART
         help
           Include support for KZM-ARM11-01. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_EUKREA_CPUIMX35
+        bool "Support Eukrea CPUIMX35 Platform"
+        select ARCH_MX35
+        select IMX_HAVE_PLATFORM_IMX_UART
+        select IMX_HAVE_PLATFORM_IMX_I2C
+        select IMX_HAVE_PLATFORM_MXC_NAND
+        select MXC_ULPI if USB_ULPI
+        help
+          Include support for Eukrea CPUIMX35 platform. This includes
+          specific configurations for the board and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX35
+        default MACH_EUKREA_MBIMXSD35_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD35_BASEBOARD
+        prompt "Eukrea MBIMXSD development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMXSD evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fda5d5d..2bd7beceb991 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -22,5 +22,7 @@ obj-$(CONFIG_MACH_MX31MOBOARD)	+= mach-mx31moboard.o mx31moboard-devboard.o \
 obj-$(CONFIG_MACH_QONG)         += mach-qong.o
 obj-$(CONFIG_MACH_PCM043)       += mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35pdk.o
+obj-$(CONFIG_MACH_MX35_3DS)     += mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35)      += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD)   += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943e2232..d3af0fdf8475 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_ahb, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
 DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
 DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
@@ -428,8 +428,8 @@ static struct clk nfc_clk = {
 static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
         _REGISTER_CLOCK(NULL, "ata", ata_clk)
-        _REGISTER_CLOCK(NULL, "can", can1_clk)
-        _REGISTER_CLOCK(NULL, "can", can2_clk)
+        _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+        _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
         _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
         _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
         _REGISTER_CLOCK(NULL, "ect", ect_clk)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
new file mode 100644
index 000000000000..3b1a44a20585
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
+
+#define imx31_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
+#define imx31_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
+#define imx31_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+
+#define imx31_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
+#define imx31_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
+#define imx31_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
+#define imx31_add_imx_uart3(pdata)      \
+        imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
+#define imx31_add_imx_uart4(pdata)      \
+        imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+
+#define imx31_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+
+#define imx31_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
+#define imx31_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
+#define imx31_add_spi_imx2(pdata)       \
+        imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
new file mode 100644
index 000000000000..f6a431a4c3d2
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
+
+#define imx35_add_flexcan0(pdata)       \
+        imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata)
+#define imx35_add_flexcan1(pdata)       \
+        imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata)
+
+#define imx35_add_imx_i2c0(pdata)       \
+        imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
+#define imx35_add_imx_i2c1(pdata)       \
+        imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
+#define imx35_add_imx_i2c2(pdata)       \
+        imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+
+#define imx35_add_imx_uart0(pdata)      \
+        imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
+#define imx35_add_imx_uart1(pdata)      \
+        imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
+#define imx35_add_imx_uart2(pdata)      \
+        imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+
+#define imx35_add_mxc_nand(pdata)       \
+        imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+
+#define imx35_add_spi_imx0(pdata)       \
+        imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
+#define imx35_add_spi_imx1(pdata)       \
+        imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index db7acd6e9101..a4fd1a26fc91 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,108 +25,10 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx3_camera.h>
 
 #include "devices.h"
 
-static struct resource uart0[] = {
-        {
-                .start = UART1_BASE_ADDR,
-                .end = UART1_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART1,
-                .end = MXC_INT_UART1,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device0 = {
-        .name = "imx-uart",
-        .id = 0,
-        .resource = uart0,
-        .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-        {
-                .start = UART2_BASE_ADDR,
-                .end = UART2_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART2,
-                .end = MXC_INT_UART2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device1 = {
-        .name = "imx-uart",
-        .id = 1,
-        .resource = uart1,
-        .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-        {
-                .start = UART3_BASE_ADDR,
-                .end = UART3_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART3,
-                .end = MXC_INT_UART3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device2 = {
-        .name = "imx-uart",
-        .id = 2,
-        .resource = uart2,
-        .num_resources = ARRAY_SIZE(uart2),
-};
-
-#ifdef CONFIG_ARCH_MX31
-static struct resource uart3[] = {
-        {
-                .start = UART4_BASE_ADDR,
-                .end = UART4_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART4,
-                .end = MXC_INT_UART4,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device3 = {
-        .name = "imx-uart",
-        .id = 3,
-        .resource = uart3,
-        .num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-        {
-                .start = UART5_BASE_ADDR,
-                .end = UART5_BASE_ADDR + 0x0B5,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_UART5,
-                .end = MXC_INT_UART5,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_uart_device4 = {
-        .name = "imx-uart",
-        .id = 4,
-        .resource = uart4,
-        .num_resources = ARRAY_SIZE(uart4),
-};
-#endif /* CONFIG_ARCH_MX31 */
-
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
         {
@@ -147,7 +49,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
         }
 };
 
-int __init mxc_register_gpios(void)
+int __init imx3x_register_gpios(void)
 {
         return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
@@ -167,82 +69,6 @@ struct platform_device mxc_w1_master_device = {
         .resource = mxc_w1_master_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-        {
-                .start  = 0, /* runtime dependent */
-                .end    = 0,
-                .flags  = IORESOURCE_MEM,
-        }, {
-                .start  = MXC_INT_NANDFC,
-                .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_nand_device = {
-        .name = "mxc_nand",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_nand_resources),
-        .resource = mxc_nand_resources,
-};
-
-static struct resource mxc_i2c0_resources[] = {
-        {
-                .start = I2C_BASE_ADDR,
-                .end = I2C_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C,
-                .end = MXC_INT_I2C,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device0 = {
-        .name = "imx-i2c",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-        .resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-        {
-                .start = I2C2_BASE_ADDR,
-                .end = I2C2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C2,
-                .end = MXC_INT_I2C2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device1 = {
-        .name = "imx-i2c",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-        .resource = mxc_i2c1_resources,
-};
-
-static struct resource mxc_i2c2_resources[] = {
-        {
-                .start = I2C3_BASE_ADDR,
-                .end = I2C3_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_I2C3,
-                .end = MXC_INT_I2C3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_i2c_device2 = {
-        .name = "imx-i2c",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_i2c2_resources),
-        .resource = mxc_i2c2_resources,
-};
-
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
         {
@@ -455,68 +281,7 @@ struct platform_device mxc_usbh2 = {
         .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-/*
- * SPI master controller
- * 3 channels
- */
-static struct resource mxc_spi_0_resources[] = {
-        {
-               .start = CSPI1_BASE_ADDR,
-               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
-               .flags = IORESOURCE_MEM,
-        }, {
-               .start = MXC_INT_CSPI1,
-               .end = MXC_INT_CSPI1,
-               .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxc_spi_1_resources[] = {
-        {
-                .start = CSPI2_BASE_ADDR,
-                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_CSPI2,
-                .end = MXC_INT_CSPI2,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-static struct resource mxc_spi_2_resources[] = {
-        {
-                .start = CSPI3_BASE_ADDR,
-                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
-                .flags = IORESOURCE_MEM,
-        }, {
-                .start = MXC_INT_CSPI3,
-                .end = MXC_INT_CSPI3,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-
-struct platform_device mxc_spi_device0 = {
-        .name = "spi_imx",
-        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_spi_0_resources),
-        .resource = mxc_spi_0_resources,
-};
-
-struct platform_device mxc_spi_device1 = {
-        .name = "spi_imx",
-        .id = 1,
-        .num_resources = ARRAY_SIZE(mxc_spi_1_resources),
-        .resource = mxc_spi_1_resources,
-};
-
-struct platform_device mxc_spi_device2 = {
-        .name = "spi_imx",
-        .id = 2,
-        .num_resources = ARRAY_SIZE(mxc_spi_2_resources),
-        .resource = mxc_spi_2_resources,
-};
-
-#ifdef CONFIG_ARCH_MX35
+#if defined(CONFIG_ARCH_MX35)
 static struct resource mxc_fec_resources[] = {
         {
                 .start  = MXC_FEC_BASE_ADDR,
@@ -628,16 +393,15 @@ struct platform_device imx_kpp_device = {
 
 static int __init mx3_devices_init(void)
 {
+#if defined(CONFIG_ARCH_MX31)
         if (cpu_is_mx31()) {
-                mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
                 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
                 mxc_register_device(&mxc_rnga_device, NULL);
         }
+#endif
+#if defined(CONFIG_ARCH_MX35)
         if (cpu_is_mx35()) {
-                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
                 otg_resources[0].start = MX35_OTG_BASE_ADDR;
                 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
                 otg_resources[1].start = MXC_INT_USBOTG;
@@ -653,6 +417,7 @@ static int __init mx3_devices_init(void)
                 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
                 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
         }
+#endif
 
         return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 2c3c8646a29e..e5535234839f 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
-
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
-extern struct platform_device mxc_nand_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
@@ -20,9 +10,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 000000000000..1dc5004df866
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct fb_videomode fb_modedb[] = {
+        {
+                .name           = "CMO_QVGA",
+                .refresh        = 60,
+                .xres           = 320,
+                .yres           = 240,
+                .pixclock       = KHZ2PICOS(6500),
+                .left_margin    = 68,
+                .right_margin   = 20,
+                .upper_margin   = 15,
+                .lower_margin   = 4,
+                .hsync_len      = 30,
+                .vsync_len      = 3,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+                .flag           = 0,
+        },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+        .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+        .dma_dev        = &mx3_ipu.dev,
+        .name           = "CMO_QVGA",
+        .mode           = fb_modedb,
+        .num_modes      = ARRAY_SIZE(fb_modedb),
+};
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+        /* LCD */
+        MX35_PAD_LD0__IPU_DISPB_DAT_0,
+        MX35_PAD_LD1__IPU_DISPB_DAT_1,
+        MX35_PAD_LD2__IPU_DISPB_DAT_2,
+        MX35_PAD_LD3__IPU_DISPB_DAT_3,
+        MX35_PAD_LD4__IPU_DISPB_DAT_4,
+        MX35_PAD_LD5__IPU_DISPB_DAT_5,
+        MX35_PAD_LD6__IPU_DISPB_DAT_6,
+        MX35_PAD_LD7__IPU_DISPB_DAT_7,
+        MX35_PAD_LD8__IPU_DISPB_DAT_8,
+        MX35_PAD_LD9__IPU_DISPB_DAT_9,
+        MX35_PAD_LD10__IPU_DISPB_DAT_10,
+        MX35_PAD_LD11__IPU_DISPB_DAT_11,
+        MX35_PAD_LD12__IPU_DISPB_DAT_12,
+        MX35_PAD_LD13__IPU_DISPB_DAT_13,
+        MX35_PAD_LD14__IPU_DISPB_DAT_14,
+        MX35_PAD_LD15__IPU_DISPB_DAT_15,
+        MX35_PAD_LD16__IPU_DISPB_DAT_16,
+        MX35_PAD_LD17__IPU_DISPB_DAT_17,
+        MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+        MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+        MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+        /* Backlight */
+        MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+        /* LCD_PWR */
+        MX35_PAD_D3_CLS__GPIO1_4,
+        /* LED */
+        MX35_PAD_LD23__GPIO3_29,
+        /* SWITCH */
+        MX35_PAD_LD19__GPIO3_25,
+        /* UART2 */
+        MX35_PAD_CTS2__UART2_CTS,
+        MX35_PAD_RTS2__UART2_RTS,
+        MX35_PAD_TXD2__UART2_TXD_MUX,
+        MX35_PAD_RXD2__UART2_RXD_MUX,
+        /* I2S */
+        MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+        MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+        MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+        MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+};
+
+#define GPIO_LED1       (2 * 32 + 29)
+#define GPIO_SWITCH1    (2 * 32 + 25)
+#define GPIO_LCDPWR     (4)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+                                   unsigned int power)
+{
+        if (power)
+                gpio_direction_output(GPIO_LCDPWR, 1);
+        else
+                gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+        .set_power              = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+        .name                   = "platform-lcd",
+        .dev.platform_data      = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_LED1,
+        },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+        .leds           = eukrea_mbimxsd_leds,
+        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &eukrea_mbimxsd_led_info,
+        },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+        {
+                .gpio           = GPIO_SWITCH1,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+        .buttons        = eukrea_mbimxsd_gpio_buttons,
+        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &eukrea_mbimxsd_button_data,
+        }
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_mbimxsd_leds_gpio,
+        &eukrea_mbimxsd_button_device,
+        &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tlv320aic23", 0x1a),
+        },
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+                        ARRAY_SIZE(eukrea_mbimxsd_pads)))
+                printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+        /* SSI unit master I2S codec connected to SSI_AUD4 */
+        mxc_audmux_v2_configure_port(0,
+                        MXC_AUDMUX_V2_PTCR_SYN |
+                        MXC_AUDMUX_V2_PTCR_TFSDIR |
+                        MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+                        MXC_AUDMUX_V2_PTCR_TCLKDIR |
+                        MXC_AUDMUX_V2_PTCR_TCSEL(3),
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+        );
+        mxc_audmux_v2_configure_port(3,
+                        MXC_AUDMUX_V2_PTCR_SYN,
+                        MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+        );
+#endif
+
+        imx35_add_imx_uart1(&uart_pdata);
+        mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+        mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+        mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+        gpio_request(GPIO_LED1, "LED1");
+        gpio_direction_output(GPIO_LED1, 1);
+        gpio_free(GPIO_LED1);
+
+        gpio_request(GPIO_SWITCH1, "SWITCH1");
+        gpio_direction_input(GPIO_SWITCH1);
+        gpio_free(GPIO_SWITCH1);
+
+        gpio_request(GPIO_LCDPWR, "LCDPWR");
+        gpio_direction_output(GPIO_LCDPWR, 1);
+        gpio_free(GPIO_SWITCH1);
+
+        i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+                                ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec91af2d..96aadcadb4ff 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -48,16 +48,14 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/board-armadillo5x0.h>
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "crm_regs.h"
 
@@ -301,7 +299,8 @@ static struct platform_device armadillo5x0_button_device = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+armadillo5x0_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
 };
@@ -493,13 +492,12 @@ static struct platform_device armadillo5x0_smc911x_device = {
 };
 
 /* UART device data */
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static struct platform_device *devices[] __initdata = {
         &armadillo5x0_smc911x_device,
-        &mxc_i2c_device1,
         &armadillo5x0_button_device,
 };
 
@@ -512,10 +510,11 @@ static void __init armadillo5x0_init(void)
                         ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
+        imx31_add_imx_i2c1(NULL);
 
         /* Register UART */
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 
         /* SMSC9118 IRQ pin */
         gpio_direction_input(MX31_PIN_GPIO1_0);
@@ -532,7 +531,7 @@ static void __init armadillo5x0_init(void)
                             &armadillo5x0_nor_flash_pdata);
 
         /* Register NAND Flash */
-        mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+        imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
         /* set NAND page size to 2k if not configured via boot mode pins */
         __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644
index 000000000000..63f970f340a2
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx35.h"
+#include "devices.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data
+eukrea_cpuimx35_i2c0_data __initconst = {
+        .bitrate = 50000,
+};
+
+#define TSC2007_IRQGPIO         (2 * 32 + 2)
+static int ts_get_pendown_state(void)
+{
+        int val = 0;
+        gpio_free(TSC2007_IRQGPIO);
+        gpio_request(TSC2007_IRQGPIO, NULL);
+        gpio_direction_input(TSC2007_IRQGPIO);
+
+        val = gpio_get_value(TSC2007_IRQGPIO);
+
+        gpio_free(TSC2007_IRQGPIO);
+        gpio_request(TSC2007_IRQGPIO, NULL);
+
+        return val ? 0 : 1;
+}
+
+static int ts_init(void)
+{
+        gpio_request(TSC2007_IRQGPIO, NULL);
+        return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+        .model                  = 2007,
+        .x_plate_ohms           = 180,
+        .get_pendown_state      = ts_get_pendown_state,
+        .init_platform_hw       = ts_init,
+};
+
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        }, {
+                I2C_BOARD_INFO("tsc2007", 0x48),
+                .type           = "tsc2007",
+                .platform_data  = &tsc2007_info,
+                .irq            = gpio_to_irq(TSC2007_IRQGPIO),
+        },
+};
+
+static struct platform_device *devices[] __initdata = {
+        &mxc_fec_device,
+        &imx_wdt_device0,
+};
+
+static struct pad_desc eukrea_cpuimx35_pads[] = {
+        /* UART1 */
+        MX35_PAD_CTS1__UART1_CTS,
+        MX35_PAD_RTS1__UART1_RTS,
+        MX35_PAD_TXD1__UART1_TXD_MUX,
+        MX35_PAD_RXD1__UART1_RXD_MUX,
+        /* FEC */
+        MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+        MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+        MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+        MX35_PAD_FEC_COL__FEC_COL,
+        MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+        MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+        MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+        MX35_PAD_FEC_MDC__FEC_MDC,
+        MX35_PAD_FEC_MDIO__FEC_MDIO,
+        MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+        MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+        MX35_PAD_FEC_CRS__FEC_CRS,
+        MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+        MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+        MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+        MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+        MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+        MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+        /* I2C1 */
+        MX35_PAD_I2C1_CLK__I2C1_SCL,
+        MX35_PAD_I2C1_DAT__I2C1_SDA,
+        /* TSC2007 IRQ */
+        MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
+static const struct mxc_nand_platform_data
+eukrea_cpuimx35_nand_board_info __initconst = {
+        .width          = 1,
+        .hw_ecc         = 1,
+        .flash_bbt      = 1,
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+        .portsc = MXC_EHCI_MODE_UTMI,
+        .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+        .portsc = MXC_EHCI_MODE_SERIAL,
+        .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+                  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+                        ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        imx35_add_imx_uart0(&uart_pdata);
+        imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+
+        i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+                        ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
+        imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
+
+#if defined(CONFIG_USB_ULPI)
+        if (otg_mode_host) {
+                otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+                                USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+                mxc_register_device(&mxc_otg_host, &otg_pdata);
+        }
+        mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+#endif
+        if (!otg_mode_host)
+                mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+        eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+        mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+        .init   = eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+        /* Maintainer: Eukrea Electromatique */
+        .phys_io        = MX35_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = MX3x_PHYS_OFFSET + 0x100,
+        .map_io         = mx35_map_io,
+        .init_irq       = mx35_init_irq,
+        .init_machine   = mxc_board_init,
+        .timer          = &eukrea_cpuimx35_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index f085d5d1a6de..5b23e416d6c7 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -16,10 +16,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -37,13 +33,12 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/board-kzmarm11.h>
 #include <mach/clock.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/memory.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (                                       \
@@ -51,6 +46,23 @@
         IMX_IO_ADDRESS(x, MX31_CS5) ?:                                  \
         MX31_IO_ADDRESS(x))
 
+/*
+ *  KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1          (MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2          (MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1          (MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT    (MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV      (MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED      (MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS          (MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2        (MX31_CS4_BASE_ADDR + 0x1003)
+
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550         (MX31_CS4_BASE_ADDR + 0x1050)
+
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 /*
  * KZM-ARM11-01 has an external UART on FPGA
@@ -173,15 +185,14 @@ static inline int kzm_init_smsc9118(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init kzm_init_imx_uart(void)
 {
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 }
 #else
 static inline void kzm_init_imx_uart(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e57291b79d..6fe69e124d30 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -22,7 +18,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -37,19 +32,47 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31_3ds.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31_3ds.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Definitions for components on the Debug board */
+
+/* Base address of CPLD controller on the Debug board */
+#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR               MX3x_CS5_BASE_ADDR
+
+/* CPLD config and interrupt base address */
+#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
+
+/* status, interrupt */
+#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
+#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
+#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
+#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
+/* CPLD code version */
+#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
+
+#define MXC_MAX_EXP_IO_LINES    16
+
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 static int mx31_3ds_pins[] = {
@@ -145,7 +168,7 @@ static int spi1_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect     = spi1_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
 };
@@ -165,7 +188,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+mx31_3ds_nand_board_info __initconst = {
         .width          = 1,
         .hw_ecc         = 1,
 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
@@ -182,8 +206,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
 
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
 
-static void mx31_3ds_usbotg_init(void)
+static int mx31_3ds_usbotg_init(void)
 {
+        int err;
+
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -197,10 +223,25 @@ static void mx31_3ds_usbotg_init(void)
         mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
         mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
 
-        gpio_request(USBOTG_RST_B, "otgusb-reset");
-        gpio_direction_output(USBOTG_RST_B, 0);
+        err = gpio_request(USBOTG_RST_B, "otgusb-reset");
+        if (err) {
+                pr_err("Failed to request the USB OTG reset gpio\n");
+                return err;
+        }
+
+        err = gpio_direction_output(USBOTG_RST_B, 0);
+        if (err) {
+                pr_err("Failed to drive the USB OTG reset gpio\n");
+                goto usbotg_free_reset;
+        }
+
         mdelay(1);
         gpio_set_value(USBOTG_RST_B, 1);
+        return 0;
+
+usbotg_free_reset:
+        gpio_free(USBOTG_RST_B);
+        return err;
 }
 
 static struct fsl_usb2_platform_data usbotg_pdata = {
@@ -208,178 +249,16 @@ static struct fsl_usb2_platform_data usbotg_pdata = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-        .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
-        .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-        .phy_interface  = PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-        {
-                .start          = LAN9217_BASE_ADDR,
-                .end            = LAN9217_BASE_ADDR + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = EXPIO_INT_ENET,
-                .end            = EXPIO_INT_ENET,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device smsc911x_device = {
-        .name           = "smsc911x",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(smsc911x_resources),
-        .resource       = smsc911x_resources,
-        .dev            = {
-                .platform_data = &smsc911x_config,
-        },
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-        uint32_t imr_val;
-        uint32_t int_valid;
-        uint32_t expio_irq;
-
-        imr_val = __raw_readw(CPLD_INT_MASK_REG);
-        int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-        expio_irq = MXC_EXP_IO_BASE;
-        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-                if ((int_valid & 1) == 0)
-                        continue;
-                generic_handle_irq(expio_irq);
-        }
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-        uint16_t reg;
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* mask the interrupt */
-        reg = __raw_readw(CPLD_INT_MASK_REG);
-        reg |= 1 << expio;
-        __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* clear the interrupt status */
-        __raw_writew(1 << expio, CPLD_INT_RESET_REG);
-        __raw_writew(0, CPLD_INT_RESET_REG);
-        /* mask the interrupt */
-        expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-        uint16_t reg;
-        uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-        /* unmask the interrupt */
-        reg = __raw_readw(CPLD_INT_MASK_REG);
-        reg &= ~(1 << expio);
-        __raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-        .ack = expio_ack_irq,
-        .mask = expio_mask_irq,
-        .unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-        int i;
-        int ret;
-
-        /* Check if there's a debug board connected */
-        if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-            (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-            (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-                /* No Debug board found */
-                return -ENODEV;
-        }
-
-        pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-                __raw_readw(CPLD_CODE_VER_REG));
-
-        /*
-         * Configure INT line as GPIO input
-         */
-        ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-        if (ret)
-                pr_warning("could not get LAN irq gpio\n");
-        else
-                gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-        /* Disable the interrupts and clear the status */
-        __raw_writew(0, CPLD_INT_MASK_REG);
-        __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-        __raw_writew(0, CPLD_INT_RESET_REG);
-        __raw_writew(0x1F, CPLD_INT_MASK_REG);
-        for (i = MXC_EXP_IO_BASE;
-             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-             i++) {
-                set_irq_chip(i, &expio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                set_irq_flags(i, IRQF_VALID);
-        }
-        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-        return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-        {
-                .virtual = MX31_CS5_BASE_ADDR_VIRT,
-                .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-                .length = MX31_CS5_SIZE,
-                .type = MT_DEVICE,
-        },
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
         mx31_map_io();
-        iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -390,10 +269,10 @@ static void __init mxc_board_init(void)
         mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
                                       "mx31_3ds");
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx0(&spi1_pdata);
         spi_register_board_info(mx31_3ds_spi_devs,
                                                 ARRAY_SIZE(mx31_3ds_spi_devs));
 
@@ -402,8 +281,9 @@ static void __init mxc_board_init(void)
         mx31_3ds_usbotg_init();
         mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-        if (!mx31_3ds_init_expio())
-                platform_device_register(&smsc911x_device);
+        if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                printk(KERN_WARNING "Init of the debugboard failed, all "
+                                    "devices on the board are unusable.\n");
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b3d1a1895c20..94b3e7c42404 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -33,8 +29,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -43,14 +37,45 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
 
+#include "devices-imx31.h"
 #include "devices.h"
 
-/*!
- * @file mx31ads.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+/* Offsets for the PBC Controller register */
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS           0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS      0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET         0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA      0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB      0x010010
+
+#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+
+#define MXC_MAX_EXP_IO_LINES    16
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
@@ -98,7 +123,7 @@ static inline int mxc_init_extuart(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -112,7 +137,7 @@ static unsigned int uart_pins[] = {
 static inline void mxc_init_imx_uart(void)
 {
         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
@@ -475,7 +500,7 @@ static void mxc_init_i2c(void)
         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
         mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 
-        mxc_register_device(&mxc_i2c_device1, NULL);
+        imx31_add_imx_i2c1(NULL);
 }
 #else
 static void mxc_init_i2c(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b2c7f512070f..8f66f65e80e2 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -46,10 +42,10 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -269,12 +265,12 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
         .chipselect = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -289,6 +285,7 @@ static struct spi_board_info mc13783_dev __initdata = {
         .bus_num        = 1,
         .chip_select    = 0,
         .platform_data  = &mc13783_pdata,
+        .irq            = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
 };
 
 static struct platform_device *devices[] __initdata = {
@@ -331,8 +328,8 @@ static void __init mx31lilly_board_init(void)
         mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
         mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
 
-        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx0(&spi0_pdata);
+        imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(&mc13783_dev, 1);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d11400877..da236c497d2a 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -42,14 +38,12 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/board-mx31lite.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -69,7 +63,8 @@ static unsigned int mx31lite_pins[] = {
         MX31_PIN_CSPI2_SS2__SS2,
 };
 
-static struct mxc_nand_platform_data mx31lite_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx31lite_nand_board_info __initconst  = {
         .width = 1,
         .hw_ecc = 1,
 };
@@ -112,7 +107,7 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(0),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
         .chipselect     = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -253,9 +248,9 @@ static void __init mxc_board_init(void)
 
         /* NOR and NAND flash */
         platform_device_register(&physmap_flash_device);
-        mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+        imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
-        mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+        imx31_add_spi_imx1(&spi1_pdata);
         spi_register_board_info(&mc13783_spi_dev, 1);
 
 #if defined(CONFIG_USB_ULPI)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 62b5e40165df..67776bc61c33 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -42,16 +38,15 @@
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/mx3_camera.h>
 #include <mach/spi.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int moboard_pins[] = {
@@ -130,24 +125,36 @@ static struct platform_device mx31moboard_flash = {
 
 static int moboard_uart0_init(struct platform_device *pdev)
 {
-        gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
-        gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-        return 0;
+        int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+        if (ret)
+                return ret;
+
+        ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+        if (ret)
+                gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+
+        return ret;
+}
+
+static void moboard_uart0_exit(struct platform_device *pdev)
+{
+        gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 
-static struct imxuart_platform_data uart0_pdata = {
+static const struct imxuart_platform_data uart0_pdata __initconst = {
         .init = moboard_uart0_init,
+        .exit = moboard_uart0_exit,
 };
 
-static struct imxuart_platform_data uart4_pdata = {
+static const struct imxuart_platform_data uart4_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data moboard_i2c0_pdata = {
+static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
         .bitrate = 400000,
 };
 
-static struct imxi2c_platform_data moboard_i2c1_pdata = {
+static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
@@ -156,7 +163,7 @@ static int moboard_spi1_cs[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master moboard_spi1_master = {
+static const struct spi_imx_master moboard_spi1_pdata __initconst = {
         .chipselect     = moboard_spi1_cs,
         .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
 };
@@ -286,7 +293,7 @@ static int moboard_spi2_cs[] = {
         MXC_SPI_CS(1),
 };
 
-static struct spi_imx_master moboard_spi2_master = {
+static const struct spi_imx_master moboard_spi2_pdata __initconst = {
         .chipselect     = moboard_spi2_cs,
         .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
 };
@@ -499,15 +506,14 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-
-        mxc_register_device(&mxc_uart_device4, &uart4_pdata);
+        imx31_add_imx_uart0(&uart0_pdata);
+        imx31_add_imx_uart4(&uart4_pdata);
 
-        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
-        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+        imx31_add_imx_i2c0(&moboard_i2c0_data);
+        imx31_add_imx_i2c1(&moboard_i2c1_data);
 
-        mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
-        mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+        imx31_add_spi_imx1(&moboard_spi1_pdata);
+        imx31_add_spi_imx2(&moboard_spi2_pdata);
 
         gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
         gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index bcac84d4dca4..1c30d7212f17 100644
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -12,10 +12,12 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX35 3-Stack Development System
+ *  - i.MX35 Platform Development Kit (i.MX35 PDK)
  */
 
 #include <linux/types.h>
@@ -32,12 +34,12 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -90,7 +92,7 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx35_add_imx_uart0(&uart_pdata);
 
         mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index cce410662383..8a292dd1a714 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -43,20 +39,17 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/board-pcm037.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
 #include <mach/mmc.h>
 #include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "pcm037.h"
 
@@ -225,7 +218,7 @@ static struct platform_device pcm037_flash = {
         .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -279,16 +272,17 @@ static struct platform_device pcm037_sram_device = {
         .resource = &pcm038_sram_resource,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_1_data = {
+static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
         .bitrate = 100000,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_2_data = {
+static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
         .bitrate = 20000,
 };
 
@@ -545,6 +539,7 @@ static struct platform_device pcm970_sja1000 = {
         .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -554,6 +549,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
         .portsc = MXC_EHCI_MODE_ULPI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -581,7 +577,6 @@ __setup("otg_mode=", pcm037_otg_mode);
 static void __init mxc_board_init(void)
 {
         int ret;
-        u32 tmp;
 
         mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
 
@@ -614,9 +609,10 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
+        imx31_add_imx_uart1(&uart_pdata);
+        imx31_add_imx_uart2(&uart_pdata);
 
         mxc_register_device(&mxc_w1_master_device, NULL);
 
@@ -634,10 +630,10 @@ static void __init mxc_board_init(void)
         i2c_register_board_info(1, pcm037_i2c_devices,
                         ARRAY_SIZE(pcm037_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
-        mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
+        imx31_add_imx_i2c1(&pcm037_i2c1_data);
+        imx31_add_imx_i2c2(&pcm037_i2c2_data);
 
-        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+        imx31_add_mxc_nand(&pcm037_nand_board_info);
         mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
         mxc_register_device(&mx3_fb, &mx3fb_pdata);
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d386000fc40..c8b98218efee 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -13,9 +13,6 @@
 #include <linux/spi/spi.h>
 
 #include <mach/common.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
 #include <mach/iomux-mx3.h>
 
 #include <asm/mach-types.h>
@@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
 
-struct spi_imx_master pcm037_spi1_master = {
+static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
         .chipselect = pcm037_spi1_cs,
         .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
 };
@@ -184,7 +181,7 @@ static int eet_init_devices(void)
         /* SPI */
         spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-        mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master);
+        imx35_add_spi_imx0(&pcm037_spi1_pdata);
 #endif
 
         platform_device_register(&pcm037_gpio_keys_device);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 78d9185a9d4b..47f5311b301a 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -40,19 +36,15 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-#include <mach/i2c.h>
-#endif
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
@@ -122,12 +114,12 @@ static struct platform_device pcm043_flash = {
         .num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-static struct imxi2c_platform_data pcm043_i2c_1_data = {
+static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
         .bitrate = 50000,
 };
 
@@ -222,6 +214,9 @@ static struct pad_desc pcm043_pads[] = {
         MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
         MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
         MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+        /* CAN2 */
+        MX35_PAD_TX5_RX0__CAN2_TXCAN,
+        MX35_PAD_TX4_RX1__CAN2_RXCAN,
 };
 
 #define AC97_GPIO_TXFS  (1 * 32 + 31)
@@ -304,11 +299,13 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = {
         .flags = IMX_SSI_USE_AC97,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
         .width = 1,
         .hw_ecc = 1,
 };
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
         .portsc = MXC_EHCI_MODE_UTMI,
         .flags  = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -319,6 +316,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
         .flags  = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
                   MXC_EHCI_IPPUE_DOWN,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
         .operating_mode = FSL_USB2_DR_DEVICE,
@@ -361,17 +359,17 @@ static void __init mxc_board_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+        imx35_add_imx_uart0(&uart_pdata);
+        imx35_add_mxc_nand(&pcm037_nand_board_info);
         mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx35_add_imx_uart1(&uart_pdata);
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
         i2c_register_board_info(0, pcm043_i2c_devices,
                         ARRAY_SIZE(pcm043_i2c_devices));
 
-        mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
+        imx35_add_imx_i2c0(&pcm043_i2c0_data);
 #endif
 
         mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -390,6 +388,7 @@ static void __init mxc_board_init(void)
         if (!otg_mode_host)
                 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 
+        imx35_add_flexcan1(NULL);
 }
 
 static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index e5b5b8323a17..d44ac70222a5 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
@@ -34,9 +30,9 @@
 #include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/board-qong.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* FPGA defines */
@@ -62,7 +58,7 @@
  * This file contains the board-specific initialization routines.
  */
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -73,11 +69,11 @@ static int uart_pins[] = {
         MX31_PIN_RXD1__RXD1
 };
 
-static inline void mxc_init_imx_uart(void)
+static inline void __init mxc_init_imx_uart(void)
 {
         mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
                         "uart-0");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
 }
 
 static struct resource dnet_resources[] = {
@@ -116,7 +112,7 @@ static struct physmap_flash_data qong_flash_data = {
 
 static struct resource qong_flash_resource = {
         .start = MX31_CS0_BASE_ADDR,
-        .end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+        .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
         .flags = IORESOURCE_MEM,
 };
 
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 6858a4f9806c..20e48c0195c4 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
@@ -97,9 +93,12 @@ void __init mx35_map_io(void)
 }
 #endif
 
+int imx3x_register_gpios(void);
+
 void __init mx31_init_irq(void)
 {
         mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+        imx3x_register_gpios();
 }
 
 void __init mx35_init_irq(void)
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 7aebd74a12e8..827fd3c80201 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -36,13 +32,13 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
 #include <mach/mmc.h>
 #include <mach/mx3fb.h>
 #include <mach/ipu.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -96,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -217,9 +213,9 @@ void __init mx31lilly_db_init(void)
         mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
                                         ARRAY_SIZE(lilly_db_board_pins),
                                         "development board pins");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
+        imx31_add_imx_uart2(&uart_pdata);
         mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
         mx31lilly_init_fb();
 }
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 5f05bfbec380..7b0e74e275ba 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
@@ -37,12 +33,11 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
 #include <mach/mmc.h>
-#include <mach/spi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -76,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -161,7 +156,7 @@ static int spi_internal_chipselect[] = {
         MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
         .chipselect     = spi_internal_chipselect,
         .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -201,9 +196,9 @@ void __init mx31lite_db_init(void)
         mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
                                         ARRAY_SIZE(litekit_db_board_pins),
                                         "development board pins");
-        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        imx31_add_imx_uart0(&uart_pdata);
         mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
-        mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+        imx31_add_spi_imx0(&spi0_pdata);
         platform_device_register(&litekit_led_device);
         mxc_register_device(&imx_wdt_device0, NULL);
         mxc_register_device(&imx_rtc_device0, NULL);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 582299cb2c08..fc395a7a8599 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
@@ -27,13 +23,13 @@
 #include <linux/usb/otg.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int devboard_pins[] = {
@@ -56,7 +52,7 @@ static unsigned int devboard_pins[] = {
         MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -230,7 +226,7 @@ void __init mx31moboard_devboard_init(void)
         mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
                 "devboard");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        imx31_add_imx_uart1(&uart_pdata);
 
         mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 4930f8c27e66..0551eb39d97e 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 293eea6d9d97..40c3e7564cb6 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
@@ -30,7 +26,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/mxc_ehci.h>
@@ -38,6 +33,7 @@
 
 #include <media/soc_camera.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int smartbot_pins[] = {
@@ -59,7 +55,7 @@ static unsigned int smartbot_pins[] = {
         MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
         .flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -183,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board)
         mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
                 "smartbot");
 
-        mxc_register_device(&mxc_uart_device1, &uart_pdata);
-
+        imx31_add_imx_uart1(&uart_pdata);
 
         switch (board) {
         case MX31SMARTBOT:
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51e676c..0848db5dd364 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,31 @@ config MACH_MX51_BABBAGE
           u-boot. This includes specific configurations for the board and its
           peripherals.
 
+config MACH_MX51_3DS
+        bool "Support MX51PDK (3DS)"
+        select MXC_DEBUG_BOARD
+        help
+          Include support for MX51PDK (3DS) platform. This includes specific
+          configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+        bool "Support Eukrea CPUIMX51 module"
+        help
+          Include support for Eukrea CPUIMX51 platform. This includes
+          specific configurations for the module and its peripherals.
+
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX51
+        default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+        prompt "Eukrea MBIMX51 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMX51 evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f869ef51..86c66e7f52f3 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,6 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
new file mode 100644
index 000000000000..623607a20f57
--- /dev/null
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -0,0 +1,293 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * based on board-mx51_babbage.c which is
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
+#include <mach/mxc_ehci.h>
+
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "devices.h"
+
+#define CPUIMX51_USBH1_STP      (0*32 + 27)
+#define CPUIMX51_QUARTA_GPIO    (2*32 + 28)
+#define CPUIMX51_QUARTB_GPIO    (2*32 + 25)
+#define CPUIMX51_QUARTC_GPIO    (2*32 + 26)
+#define CPUIMX51_QUARTD_GPIO    (2*32 + 27)
+#define CPUIMX51_QUARTA_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
+#define CPUIMX51_QUARTB_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
+#define CPUIMX51_QUARTC_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
+#define CPUIMX51_QUARTD_IRQ     (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
+#define CPUIMX51_QUART_XTAL     14745600
+#define CPUIMX51_QUART_REGSHIFT 17
+
+/* USB_CTRL_1 */
+#define MX51_USB_CTRL_1_OFFSET          0x10
+#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
+
+#define MX51_USB_PLLDIV_12_MHZ          0x00
+#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
+#define MX51_USB_PLL_DIV_24_MHZ         0x02
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
+                .irq = CPUIMX51_QUARTA_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
+                .irq = CPUIMX51_QUARTB_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
+                .irq = CPUIMX51_QUARTC_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
+                .irq = CPUIMX51_QUARTD_IRQ,
+                .irqflags = IRQF_TRIGGER_HIGH,
+                .uartclk = CPUIMX51_QUART_XTAL,
+                .regshift = CPUIMX51_QUART_REGSHIFT,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+        }
+};
+
+static struct platform_device serial_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = serial_platform_data,
+        },
+};
+#endif
+
+static struct platform_device *devices[] __initdata = {
+        &mxc_fec_device,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        &serial_device,
+#endif
+};
+
+static struct pad_desc eukrea_cpuimx51_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* I2C2 */
+        MX51_PAD_GPIO_1_2__I2C2_SCL,
+        MX51_PAD_GPIO_1_3__I2C2_SDA,
+        MX51_PAD_NANDF_D10__GPIO_3_30,
+
+        /* QUART IRQ */
+        MX51_PAD_NANDF_D15__GPIO_3_25,
+        MX51_PAD_NANDF_D14__GPIO_3_26,
+        MX51_PAD_NANDF_D13__GPIO_3_27,
+        MX51_PAD_NANDF_D12__GPIO_3_28,
+
+        /* USB HOST1 */
+        MX51_PAD_USBH1_CLK__USBH1_CLK,
+        MX51_PAD_USBH1_DIR__USBH1_DIR,
+        MX51_PAD_USBH1_NXT__USBH1_NXT,
+        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
+        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
+        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
+        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
+        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
+        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
+        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
+        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
+        MX51_PAD_USBH1_STP__USBH1_STP,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx51_i2c_data = {
+        .bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+
+/* This function is board specific as the bit mask for the plldiv will also
+be different for other Freescale SoCs, thus a common bitmask is not
+possible and cannot get place in /plat-mxc/ehci.c.*/
+static int initialize_otg_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* Set the PHY clock to 19.2MHz */
+        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
+        v |= MX51_USB_PLL_DIV_19_2_MHZ;
+        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static int initialize_usbh1_port(struct platform_device *pdev)
+{
+        u32 v;
+        void __iomem *usb_base;
+        void __iomem *usbother_base;
+
+        usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
+        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
+
+        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
+        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
+        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
+        iounmap(usb_base);
+        return 0;
+}
+
+static struct mxc_usbh_platform_data dr_utmi_config = {
+        .init           = initialize_otg_port,
+        .portsc = MXC_EHCI_UTMI_16BIT,
+        .flags  = MXC_EHCI_INTERNAL_PHY,
+};
+
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
+};
+
+static struct mxc_usbh_platform_data usbh1_config = {
+        .init           = initialize_usbh1_port,
+        .portsc = MXC_EHCI_MODE_ULPI,
+        .flags  = (MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD),
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx51_otg_mode(char *options)
+{
+        if (!strcmp(options, "host"))
+                otg_mode_host = 1;
+        else if (!strcmp(options, "device"))
+                otg_mode_host = 0;
+        else
+                pr_info("otg_mode neither \"host\" nor \"device\". "
+                        "Defaulting to device\n");
+        return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx51_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init eukrea_cpuimx51_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
+                                        ARRAY_SIZE(eukrea_cpuimx51_pads));
+
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
+        gpio_direction_input(CPUIMX51_QUARTA_GPIO);
+        gpio_free(CPUIMX51_QUARTA_GPIO);
+        gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
+        gpio_direction_input(CPUIMX51_QUARTB_GPIO);
+        gpio_free(CPUIMX51_QUARTB_GPIO);
+        gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
+        gpio_direction_input(CPUIMX51_QUARTC_GPIO);
+        gpio_free(CPUIMX51_QUARTC_GPIO);
+        gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
+        gpio_direction_input(CPUIMX51_QUARTD_GPIO);
+        gpio_free(CPUIMX51_QUARTD_GPIO);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_register_device(&mxc_i2c_device1, &eukrea_cpuimx51_i2c_data);
+        i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
+
+        if (otg_mode_host)
+                mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
+        else {
+                initialize_otg_port(NULL);
+                mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
+        }
+        mxc_register_device(&mxc_usbh1_device, &usbh1_config);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
+        eukrea_mbimx51_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx51_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = eukrea_cpuimx51_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
+        /* Maintainer: Eric Bénard <eric@eukrea.com> */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine = eukrea_cpuimx51_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 000000000000..f95c2fd94667
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/imx-uart.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices.h"
+
+#define EXPIO_PARENT_INT        (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+static struct pad_desc mx51_3ds_pads[] = {
+        /* UART1 */
+        MX51_PAD_UART1_RXD__UART1_RXD,
+        MX51_PAD_UART1_TXD__UART1_TXD,
+        MX51_PAD_UART1_RTS__UART1_RTS,
+        MX51_PAD_UART1_CTS__UART1_CTS,
+
+        /* UART2 */
+        MX51_PAD_UART2_RXD__UART2_RXD,
+        MX51_PAD_UART2_TXD__UART2_TXD,
+        MX51_PAD_EIM_D25__UART2_CTS,
+        MX51_PAD_EIM_D26__UART2_RTS,
+
+        /* UART3 */
+        MX51_PAD_UART3_RXD__UART3_RXD,
+        MX51_PAD_UART3_TXD__UART3_TXD,
+        MX51_PAD_EIM_D24__UART3_CTS,
+        MX51_PAD_EIM_D27__UART3_RTS,
+
+        /* CPLD PARENT IRQ PIN */
+        MX51_PAD_GPIO_1_6__GPIO_1_6,
+
+        /* KPP */
+        MX51_PAD_KEY_ROW0__KEY_ROW0,
+        MX51_PAD_KEY_ROW1__KEY_ROW1,
+        MX51_PAD_KEY_ROW2__KEY_ROW2,
+        MX51_PAD_KEY_ROW3__KEY_ROW3,
+        MX51_PAD_KEY_COL0__KEY_COL0,
+        MX51_PAD_KEY_COL1__KEY_COL1,
+        MX51_PAD_KEY_COL2__KEY_COL2,
+        MX51_PAD_KEY_COL3__KEY_COL3,
+        MX51_PAD_KEY_COL4__KEY_COL4,
+        MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+        KEY(0, 0, KEY_1),
+        KEY(0, 1, KEY_2),
+        KEY(0, 2, KEY_3),
+        KEY(0, 3, KEY_F1),
+        KEY(0, 4, KEY_UP),
+        KEY(0, 5, KEY_F2),
+
+        KEY(1, 0, KEY_4),
+        KEY(1, 1, KEY_5),
+        KEY(1, 2, KEY_6),
+        KEY(1, 3, KEY_LEFT),
+        KEY(1, 4, KEY_SELECT),
+        KEY(1, 5, KEY_RIGHT),
+
+        KEY(2, 0, KEY_7),
+        KEY(2, 1, KEY_8),
+        KEY(2, 2, KEY_9),
+        KEY(2, 3, KEY_F3),
+        KEY(2, 4, KEY_DOWN),
+        KEY(2, 5, KEY_F4),
+
+        KEY(3, 0, KEY_0),
+        KEY(3, 1, KEY_OK),
+        KEY(3, 2, KEY_ESC),
+        KEY(3, 3, KEY_ENTER),
+        KEY(3, 4, KEY_MENU),
+        KEY(3, 5, KEY_BACK)
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+        .keymap         = mx51_3ds_board_keymap,
+        .keymap_size    = ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+        mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+                                        ARRAY_SIZE(mx51_3ds_pads));
+        mxc_init_imx_uart();
+
+        if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+                printk(KERN_WARNING "Init of the debugboard failed, all "
+                                    "devices on the board are unusable.\n");
+
+        mxc_init_keypad();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+        mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+        .init   = mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io = MX51_AIPS1_BASE_ADDR,
+        .io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params = PHYS_OFFSET + 0x100,
+        .map_io = mx51_map_io,
+        .init_irq = mx51_init_irq,
+        .init_machine = mxc_board_init,
+        .timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9d7b73..6e384d92e625 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -12,6 +12,7 @@
 
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/i2c.h>
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/io.h>
@@ -21,6 +22,7 @@
 #include <mach/hardware.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx51.h>
+#include <mach/i2c.h>
 #include <mach/mxc_ehci.h>
 
 #include <asm/irq.h>
@@ -64,6 +66,18 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_EIM_D27__UART3_RTS,
         MX51_PAD_EIM_D24__UART3_CTS,
 
+        /* I2C1 */
+        MX51_PAD_EIM_D16__I2C1_SDA,
+        MX51_PAD_EIM_D19__I2C1_SCL,
+
+        /* I2C2 */
+        MX51_PAD_KEY_COL4__I2C2_SCL,
+        MX51_PAD_KEY_COL5__I2C2_SDA,
+
+        /* HSI2C */
+        MX51_PAD_I2C1_CLK__HSI2C_CLK,
+        MX51_PAD_I2C1_DAT__HSI2C_DAT,
+
         /* USB HOST1 */
         MX51_PAD_USBH1_CLK__USBH1_CLK,
         MX51_PAD_USBH1_DIR__USBH1_DIR,
@@ -78,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
         /* USB HUB reset line*/
-        MX51_PAD_GPIO_1_7__GPIO1_7,
+        MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
@@ -99,6 +113,14 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+static struct imxi2c_platform_data babbage_i2c_data = {
+        .bitrate = 100000,
+};
+
+static struct imxi2c_platform_data babbage_hsi2c_data = {
+        .bitrate = 400000,
+};
+
 static int gpio_usbh1_active(void)
 {
         struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27;
@@ -230,6 +252,10 @@ static void __init mxc_board_init(void)
         mxc_init_imx_uart();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
+        mxc_register_device(&mxc_i2c_device0, &babbage_i2c_data);
+        mxc_register_device(&mxc_i2c_device1, &babbage_i2c_data);
+        mxc_register_device(&mxc_hsi2c_device, &babbage_hsi2c_data);
+
         if (otg_mode_host)
                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
         else {
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d3370e..6af69def357f 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
         .parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+        .id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)     \
         static struct clk name = {                      \
                 .id             = i,                    \
@@ -798,6 +802,14 @@ DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
 
+/* I2C */
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+        NULL, NULL, &ipg_clk, NULL);
+
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
         NULL,  NULL, &ipg_clk, NULL);
@@ -815,12 +827,16 @@ static struct clk_lookup lookups[] = {
         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+        _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449aacdc..1920ff4963b2 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -93,6 +93,64 @@ struct platform_device mxc_fec_device = {
         .resource = mxc_fec_resources,
 };
 
+static struct resource mxc_i2c0_resources[] = {
+        {
+                .start = MX51_I2C1_BASE_ADDR,
+                .end = MX51_I2C1_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MX51_MXC_INT_I2C1,
+                .end = MX51_MXC_INT_I2C1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c0_resources),
+        .resource = mxc_i2c0_resources,
+};
+
+static struct resource mxc_i2c1_resources[] = {
+        {
+                .start = MX51_I2C2_BASE_ADDR,
+                .end = MX51_I2C2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MX51_MXC_INT_I2C2,
+                .end = MX51_MXC_INT_I2C2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c1_resources),
+        .resource = mxc_i2c1_resources,
+};
+
+static struct resource mxc_hsi2c_resources[] = {
+        {
+                .start = MX51_HSI2C_DMA_BASE_ADDR,
+                .end = MX51_HSI2C_DMA_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = MX51_MXC_INT_HS_I2C,
+                .end = MX51_MXC_INT_HS_I2C,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+struct platform_device mxc_hsi2c_device = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_hsi2c_resources),
+        .resource = mxc_hsi2c_resources
+};
+
 static u64 usb_dma_mask = DMA_BIT_MASK(32);
 
 static struct resource usbotg_resources[] = {
@@ -168,34 +226,57 @@ struct platform_device mxc_wdt = {
         .resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+        {
+                .start = MX51_MXC_INT_KPP,
+                .end = MX51_MXC_INT_KPP,
+                .flags = IORESOURCE_IRQ,
+        } , {
+                .start = MX51_KPP_BASE_ADDR,
+                .end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device mxc_keypad_device = {
+        .name = "imx-keypad",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_kpp_resources),
+        .resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
         {
                 .chip.label = "gpio-0",
                 .base = MX51_IO_ADDRESS(MX51_GPIO1_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO1_LOW,
+                .irq_high = MX51_MXC_INT_GPIO1_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START
         },
         {
                 .chip.label = "gpio-1",
                 .base = MX51_IO_ADDRESS(MX51_GPIO2_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO2_LOW,
+                .irq_high = MX51_MXC_INT_GPIO2_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 1
         },
         {
                 .chip.label = "gpio-2",
                 .base = MX51_IO_ADDRESS(MX51_GPIO3_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO3_LOW,
+                .irq_high = MX51_MXC_INT_GPIO3_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 2
         },
         {
                 .chip.label = "gpio-3",
                 .base = MX51_IO_ADDRESS(MX51_GPIO4_BASE_ADDR),
                 .irq = MX51_MXC_INT_GPIO4_LOW,
+                .irq_high = MX51_MXC_INT_GPIO4_HIGH,
                 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
         },
 };
 
-int __init mxc_register_gpios(void)
+int __init imx51_register_gpios(void)
 {
         return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae71cd5b..e509cfaad1d4 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,7 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_hsi2c_device;
+extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
new file mode 100644
index 000000000000..ffa93d1d6ef8
--- /dev/null
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -0,0 +1,200 @@
+/*
+ *
+ * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/fsl_devices.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/leds.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx51.h>
+
+#include <asm/mach/arch.h>
+
+#include "devices.h"
+
+#define MBIMX51_TSC2007_GPIO    (2*32 + 30)
+#define MBIMX51_TSC2007_IRQ     (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
+#define MBIMX51_LED0            (2*32 + 5)
+#define MBIMX51_LED1            (2*32 + 6)
+#define MBIMX51_LED2            (2*32 + 7)
+#define MBIMX51_LED3            (2*32 + 8)
+
+static struct gpio_led mbimx51_leds[] = {
+        {
+                .name                   = "led0",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED0,
+        },
+        {
+                .name                   = "led1",
+                .default_trigger        = "nand-disk",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED1,
+        },
+        {
+                .name                   = "led2",
+                .default_trigger        = "mmc0",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED2,
+        },
+        {
+                .name                   = "led3",
+                .default_trigger        = "default-on",
+                .active_low             = 1,
+                .gpio                   = MBIMX51_LED3,
+        },
+};
+
+static struct gpio_led_platform_data mbimx51_leds_info = {
+        .leds           = mbimx51_leds,
+        .num_leds       = ARRAY_SIZE(mbimx51_leds),
+};
+
+static struct platform_device mbimx51_leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &mbimx51_leds_info,
+        },
+};
+
+static struct platform_device *devices[] __initdata = {
+        &mbimx51_leds_gpio,
+};
+
+static struct pad_desc mbimx51_pads[] = {
+        /* UART2 */
+        MX51_PAD_UART2_RXD__UART2_RXD,
+        MX51_PAD_UART2_TXD__UART2_TXD,
+
+        /* UART3 */
+        MX51_PAD_UART3_RXD__UART3_RXD,
+        MX51_PAD_UART3_TXD__UART3_TXD,
+        MX51_PAD_KEY_COL4__UART3_RTS,
+        MX51_PAD_KEY_COL5__UART3_CTS,
+
+        /* TSC2007 IRQ */
+        MX51_PAD_NANDF_D10__GPIO_3_30,
+
+        /* LEDS */
+        MX51_PAD_DISPB2_SER_DIN__GPIO_3_5,
+        MX51_PAD_DISPB2_SER_DIO__GPIO_3_6,
+        MX51_PAD_DISPB2_SER_CLK__GPIO_3_7,
+        MX51_PAD_DISPB2_SER_RS__GPIO_3_8,
+
+        /* KPP */
+        MX51_PAD_KEY_ROW0__KEY_ROW0,
+        MX51_PAD_KEY_ROW1__KEY_ROW1,
+        MX51_PAD_KEY_ROW2__KEY_ROW2,
+        MX51_PAD_KEY_ROW3__KEY_ROW3,
+        MX51_PAD_KEY_COL0__KEY_COL0,
+        MX51_PAD_KEY_COL1__KEY_COL1,
+        MX51_PAD_KEY_COL2__KEY_COL2,
+        MX51_PAD_KEY_COL3__KEY_COL3,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int mbimx51_keymap[] = {
+        KEY(0, 0, KEY_1),
+        KEY(0, 1, KEY_2),
+        KEY(0, 2, KEY_3),
+        KEY(0, 3, KEY_UP),
+
+        KEY(1, 0, KEY_4),
+        KEY(1, 1, KEY_5),
+        KEY(1, 2, KEY_6),
+        KEY(1, 3, KEY_LEFT),
+
+        KEY(2, 0, KEY_7),
+        KEY(2, 1, KEY_8),
+        KEY(2, 2, KEY_9),
+        KEY(2, 3, KEY_RIGHT),
+
+        KEY(3, 0, KEY_0),
+        KEY(3, 1, KEY_DOWN),
+        KEY(3, 2, KEY_ESC),
+        KEY(3, 3, KEY_ENTER),
+};
+
+static struct matrix_keymap_data mbimx51_map_data = {
+        .keymap         = mbimx51_keymap,
+        .keymap_size    = ARRAY_SIZE(mbimx51_keymap),
+};
+
+static int tsc2007_get_pendown_state(void)
+{
+        return !gpio_get_value(MBIMX51_TSC2007_GPIO);
+}
+
+struct tsc2007_platform_data tsc2007_data = {
+        .model = 2007,
+        .x_plate_ohms = 180,
+        .get_pendown_state = tsc2007_get_pendown_state,
+};
+
+static struct i2c_board_info mbimx51_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("tsc2007", 0x48),
+                .irq  = MBIMX51_TSC2007_IRQ,
+                .platform_data = &tsc2007_data,
+        },
+};
+
+/*
+ * baseboard initialization.
+ */
+void __init eukrea_mbimx51_baseboard_init(void)
+{
+        mxc_iomux_v3_setup_multiple_pads(mbimx51_pads,
+                                        ARRAY_SIZE(mbimx51_pads));
+
+        mxc_register_device(&mxc_uart_device1, NULL);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata);
+
+        gpio_request(MBIMX51_LED0, "LED0");
+        gpio_direction_output(MBIMX51_LED0, 1);
+        gpio_free(MBIMX51_LED0);
+        gpio_request(MBIMX51_LED1, "LED1");
+        gpio_direction_output(MBIMX51_LED1, 1);
+        gpio_free(MBIMX51_LED1);
+        gpio_request(MBIMX51_LED2, "LED2");
+        gpio_direction_output(MBIMX51_LED2, 1);
+        gpio_free(MBIMX51_LED2);
+        gpio_request(MBIMX51_LED3, "LED3");
+        gpio_direction_output(MBIMX51_LED3, 1);
+        gpio_free(MBIMX51_LED3);
+
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+
+        mxc_register_device(&mxc_keypad_device, &mbimx51_map_data);
+
+        gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
+        gpio_direction_input(MBIMX51_TSC2007_GPIO);
+        set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+        i2c_register_board_info(1, mbimx51_i2c_devices,
+                                ARRAY_SIZE(mbimx51_i2c_devices));
+}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index b7677ef80cc4..bc3f30db8d9a 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -65,6 +65,8 @@ void __init mx51_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx51_register_gpios(void);
+
 void __init mx51_init_irq(void)
 {
         unsigned long tzic_addr;
@@ -80,4 +82,5 @@ void __init mx51_init_irq(void)
                 panic("unable to map TZIC interrupt controller\n");
 
         tzic_init_irq(tzic_virt);
+        imx51_register_gpios();
 }
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
index ce4f59058189..b989baccd675 100644
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -11,11 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
index 353bd977b393..027af4f0d18a 100644
--- a/arch/arm/mach-mxc91231/devices.c
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
         },
 };
 
-int __init mxc_register_gpios(void)
+int __init mxc91231_register_gpios(void)
 {
         return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 6becda3ff331..aeccfd755fee 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -15,11 +15,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #include <linux/mm.h>
@@ -88,7 +83,10 @@ void __init mxc91231_map_io(void)
         iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int mxc91231_register_gpios(void);
+
 void __init mxc91231_init_irq(void)
 {
+        mxc91231_register_gpios();
         mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 905719a677ae..c897e03e413d 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -26,6 +26,7 @@ config MACH_KUROBOX_PRO
 config MACH_DNS323
         bool "D-Link DNS-323"
         select I2C_BOARDINFO
+        select PHYLIB
         help
           Say 'Y' here if you want your kernel to support the
           D-Link DNS-323 platform.
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de1698edc..a47100d46a4e 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
  *
+ * Support for HW Rev C1:
+ *
+ * Copyright (C) 2010 Benjamin Herrenschmidt <benh@kernel.crashing.org>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as
  * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/phy.h>
+#include <linux/marvell_phy.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
 #include "common.h"
 #include "mpp.h"
 
+/* Rev A1 and B1 */
 #define DNS323_GPIO_LED_RIGHT_AMBER     1
 #define DNS323_GPIO_LED_LEFT_AMBER      2
 #define DNS323_GPIO_SYSTEM_UP           3
@@ -42,6 +49,23 @@
 #define DNS323_GPIO_KEY_POWER           9
 #define DNS323_GPIO_KEY_RESET           10
 
+/* Rev C1 */
+#define DNS323C_GPIO_KEY_POWER          1
+#define DNS323C_GPIO_POWER_OFF          2
+#define DNS323C_GPIO_LED_RIGHT_AMBER    8
+#define DNS323C_GPIO_LED_LEFT_AMBER     9
+#define DNS323C_GPIO_LED_POWER          17
+#define DNS323C_GPIO_FAN_BIT1           18
+#define DNS323C_GPIO_FAN_BIT0           19
+
+/* Exposed to userspace, do not change */
+enum {
+        DNS323_REV_A1,  /* 0 */
+        DNS323_REV_B1,  /* 1 */
+        DNS323_REV_C1,  /* 2 */
+};
+
+
 /****************************************************************************
  * PCI setup
  */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
         .map_irq        = dns323_pci_map_irq,
 };
 
-static int __init dns323_dev_id(void)
-{
-        u32 dev, rev;
-
-        orion5x_pcie_id(&dev, &rev);
-
-        return dev;
-}
-
 static int __init dns323_pci_init(void)
 {
-        /* The 5182 doesn't really use its PCI bus, and initialising PCI
+        /* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
          * gets in the way of initialising the SATA controller.
          */
-        if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
+        if (machine_is_dns323() && system_rev == DNS323_REV_A1)
                 pci_common_init(&dns323_pci);
 
         return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
         }
 
         iounmap(mac_page);
-        printk("DNS323: Found ethernet MAC address: ");
+        printk("DNS-323: Found ethernet MAC address: ");
         for (i = 0; i < 6; i++)
                 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
 
@@ -259,12 +274,11 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
         return 0;
 }
 
-static struct gpio_led dns323_leds[] = {
+static struct gpio_led dns323ab_leds[] = {
         {
                 .name = "power:blue",
                 .gpio = DNS323_GPIO_LED_POWER2,
-                .default_trigger = "timer",
-                .active_low = 1,
+                .default_trigger = "default-on",
         }, {
                 .name = "right:amber",
                 .gpio = DNS323_GPIO_LED_RIGHT_AMBER,
@@ -276,9 +290,34 @@ static struct gpio_led dns323_leds[] = {
         },
 };
 
-static struct gpio_led_platform_data dns323_led_data = {
-        .num_leds       = ARRAY_SIZE(dns323_leds),
-        .leds           = dns323_leds,
+
+static struct gpio_led dns323c_leds[] = {
+        {
+                .name = "power:blue",
+                .gpio = DNS323C_GPIO_LED_POWER,
+                .default_trigger = "timer",
+                .active_low = 1,
+        }, {
+                .name = "right:amber",
+                .gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
+                .active_low = 1,
+        }, {
+                .name = "left:amber",
+                .gpio = DNS323C_GPIO_LED_LEFT_AMBER,
+                .active_low = 1,
+        },
+};
+
+
+static struct gpio_led_platform_data dns323ab_led_data = {
+        .num_leds       = ARRAY_SIZE(dns323ab_leds),
+        .leds           = dns323ab_leds,
+        .gpio_blink_set = dns323_gpio_blink_set,
+};
+
+static struct gpio_led_platform_data dns323c_led_data = {
+        .num_leds       = ARRAY_SIZE(dns323c_leds),
+        .leds           = dns323c_leds,
         .gpio_blink_set = dns323_gpio_blink_set,
 };
 
@@ -286,7 +325,7 @@ static struct platform_device dns323_gpio_leds = {
         .name           = "leds-gpio",
         .id             = -1,
         .dev            = {
-                .platform_data  = &dns323_led_data,
+                .platform_data  = &dns323ab_led_data,
         },
 };
 
@@ -294,7 +333,7 @@ static struct platform_device dns323_gpio_leds = {
  * GPIO Attached Keys
  */
 
-static struct gpio_keys_button dns323_buttons[] = {
+static struct gpio_keys_button dns323ab_buttons[] = {
         {
                 .code           = KEY_RESTART,
                 .gpio           = DNS323_GPIO_KEY_RESET,
@@ -308,9 +347,23 @@ static struct gpio_keys_button dns323_buttons[] = {
         },
 };
 
-static struct gpio_keys_platform_data dns323_button_data = {
-        .buttons        = dns323_buttons,
-        .nbuttons       = ARRAY_SIZE(dns323_buttons),
+static struct gpio_keys_platform_data dns323ab_button_data = {
+        .buttons        = dns323ab_buttons,
+        .nbuttons       = ARRAY_SIZE(dns323ab_buttons),
+};
+
+static struct gpio_keys_button dns323c_buttons[] = {
+        {
+                .code           = KEY_POWER,
+                .gpio           = DNS323C_GPIO_KEY_POWER,
+                .desc           = "Power Button",
+                .active_low     = 1,
+        },
+};
+
+static struct gpio_keys_platform_data dns323c_button_data = {
+        .buttons        = dns323c_buttons,
+        .nbuttons       = ARRAY_SIZE(dns323c_buttons),
 };
 
 static struct platform_device dns323_button_device = {
@@ -318,7 +371,7 @@ static struct platform_device dns323_button_device = {
         .id             = -1,
         .num_resources  = 0,
         .dev            = {
-                .platform_data  = &dns323_button_data,
+                .platform_data  = &dns323ab_button_data,
         },
 };
 
@@ -332,7 +385,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
         {  0, MPP_PCIE_RST_OUTn },
         {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
         {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -356,7 +409,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
         { -1 },
 };
 
-static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
         {  0, MPP_UNUSED },
         {  1, MPP_GPIO },               /* right amber LED (sata ch0) */
         {  2, MPP_GPIO },               /* left amber LED (sata ch1) */
@@ -380,15 +433,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
         { -1 },
 };
 
+static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },               /* ? input */
+        {  1, MPP_GPIO },               /* input power switch (0 = pressed) */
+        {  2, MPP_GPIO },               /* output power off */
+        {  3, MPP_UNUSED },             /* ? output */
+        {  4, MPP_UNUSED },             /* ? output */
+        {  5, MPP_UNUSED },             /* ? output */
+        {  6, MPP_UNUSED },             /* ? output */
+        {  7, MPP_UNUSED },             /* ? output */
+        {  8, MPP_GPIO },               /* i/o right amber LED */
+        {  9, MPP_GPIO },               /* i/o left amber LED */
+        { 10, MPP_GPIO },               /* input */
+        { 11, MPP_UNUSED },
+        { 12, MPP_SATA_LED },
+        { 13, MPP_SATA_LED },
+        { 14, MPP_SATA_LED },
+        { 15, MPP_SATA_LED },
+        { 16, MPP_UNUSED },
+        { 17, MPP_GPIO },               /* power button LED */
+        { 18, MPP_GPIO },               /* fan speed bit 0 */
+        { 19, MPP_GPIO },               /* fan speed bit 1 */
+        { -1 },
+};
+
+/* Rev C1 Fan speed notes:
+ *
+ * The fan is controlled by 2 GPIOs on this board. The settings
+ * of the bits is as follow:
+ *
+ *  GPIO 18    GPIO 19    Fan
+ *
+ *    0          0        stopped
+ *    0          1        low speed
+ *    1          0        high speed
+ *    1          1        don't do that (*)
+ *
+ * (*) I think the two bits control two feed-in resistors into a fixed
+ *     PWN circuit, setting both bits will basically go a 'bit' faster
+ *     than high speed, but d-link doesn't do it and you may get out of
+ *     HW spec so don't do it.
+ */
+
 /*
- * On the DNS-323 the following devices are attached via I2C:
+ * On the DNS-323 A1 and B1 the following devices are attached via I2C:
  *
  *  i2c addr | chip        | description
  *  0x3e     | GMT G760Af  | fan speed PWM controller
  *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
  *  0x68     | ST M41T80   | RTC w/ alarm
  */
-static struct i2c_board_info __initdata dns323_i2c_devices[] = {
+static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
         {
                 I2C_BOARD_INFO("g760a", 0x3e),
         }, {
@@ -398,36 +493,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
         },
 };
 
+/*
+ * On the DNS-323 C1 the following devices are attached via I2C:
+ *
+ *  i2c addr | chip        | description
+ *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
+ *  0x68     | ST M41T80   | RTC w/ alarm
+ */
+static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("lm75", 0x48),
+        }, {
+                I2C_BOARD_INFO("m41t80", 0x68),
+        },
+};
+
 /* DNS-323 rev. A specific power off method */
 static void dns323a_power_off(void)
 {
-        pr_info("%s: triggering power-off...\n", __func__);
+        pr_info("DNS-323: Triggering power-off...\n");
         gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
 }
 
 /* DNS-323 rev B specific power off method */
 static void dns323b_power_off(void)
 {
-        pr_info("%s: triggering power-off...\n", __func__);
+        pr_info("DNS-323: Triggering power-off...\n");
         /* Pin has to be changed to 1 and back to 0 to do actual power off. */
         gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
         mdelay(100);
         gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
 }
 
+/* DNS-323 rev. C specific power off method */
+static void dns323c_power_off(void)
+{
+        pr_info("DNS-323: Triggering power-off...\n");
+        gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
+}
+
+static int dns323c_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
+
+        return 0;
+}
+
+static int __init dns323_identify_rev(void)
+{
+        u32 dev, rev, i, reg;
+
+        pr_debug("DNS-323: Identifying board ... \n");
+
+        /* Rev A1 has a 5181 */
+        orion5x_pcie_id(&dev, &rev);
+        if (dev == MV88F5181_DEV_ID) {
+                pr_debug("DNS-323: 5181 found, board is A1\n");
+                return DNS323_REV_A1;
+        }
+        pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
+
+        /* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
+         * a bit gross but we want to do that without links into the eth
+         * driver so let's poke at it directly. We default to rev B1 in
+         * case the accesses fail
+         */
+
+#define ETH_SMI_REG             (ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
+#define  SMI_BUSY               0x10000000
+#define  SMI_READ_VALID         0x08000000
+#define  SMI_OPCODE_READ        0x04000000
+#define  SMI_OPCODE_WRITE       0x00000000
+
+        for (i = 0; i < 1000; i++) {
+                reg = readl(ETH_SMI_REG);
+                if (!(reg & SMI_BUSY))
+                        break;
+        }
+        if (i >= 1000) {
+                pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
+                return DNS323_REV_B1;
+        }
+        writel((3 << 21)        /* phy ID reg */ |
+               (8 << 16)        /* phy addr */ |
+               SMI_OPCODE_READ, ETH_SMI_REG);
+        for (i = 0; i < 1000; i++) {
+                reg = readl(ETH_SMI_REG);
+                if (reg & SMI_READ_VALID)
+                        break;
+        }
+        if (i >= 1000) {
+                pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
+                return DNS323_REV_B1;
+        }
+        pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
+
+        /* Note: the Marvell tools mask the ID with 0x3f0 before comparison
+         * but I don't see that making a difference here, at least with
+         * any known Marvell PHY ID
+         */
+        switch(reg & 0xfff0) {
+        case 0x0cc0: /* MV88E1111 */
+                return DNS323_REV_B1;
+        case 0x0e10: /* MV88E1118 */
+                return DNS323_REV_C1;
+        default:
+                pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
+                           reg & 0xffff);
+        }
+        return DNS323_REV_B1;
+}
+
 static void __init dns323_init(void)
 {
         /* Setup basic Orion functions. Need to be called early. */
         orion5x_init();
 
+        /* Identify revision */
+        system_rev = dns323_identify_rev();
+        pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
+
         /* Just to be tricky, the 5182 has a completely different
          * set of MPP modes to the 5181.
          */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
-                orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
-        else {
-                orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                orion5x_mpp_conf(dns323a_mpp_modes);
                 writel(0, MPP_DEV_CTRL);                /* DEV_D[31:16] */
+                break;
+        case DNS323_REV_B1:
+                orion5x_mpp_conf(dns323b_mpp_modes);
+                break;
+        case DNS323_REV_C1:
+                orion5x_mpp_conf(dns323c_mpp_modes);
+                break;
         }
 
         /* setup flash mapping
@@ -436,53 +635,96 @@ static void __init dns323_init(void)
         orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
         platform_device_register(&dns323_nor_flash);
 
-        /* The 5181 power LED is active low and requires
-         * DNS323_GPIO_LED_POWER1 to also be low.
-         */
-        if (dns323_dev_id() == MV88F5181_DEV_ID) {
-                dns323_leds[0].active_low = 1;
-                gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
-                gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+        /* Sort out LEDs, Buttons and i2c devices */
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                /* The 5181 power LED is active low and requires
+                 * DNS323_GPIO_LED_POWER1 to also be low.
+                 */
+                 dns323ab_leds[0].active_low = 1;
+                 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
+                 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+                /* Fall through */
+        case DNS323_REV_B1:
+                i2c_register_board_info(0, dns323ab_i2c_devices,
+                                ARRAY_SIZE(dns323ab_i2c_devices));
+                break;
+        case DNS323_REV_C1:
+                /* Hookup LEDs & Buttons */
+                dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
+                dns323_button_device.dev.platform_data = &dns323c_button_data;
+
+                /* Hookup i2c devices and fan driver */
+                i2c_register_board_info(0, dns323c_i2c_devices,
+                                ARRAY_SIZE(dns323c_i2c_devices));
+                platform_device_register_simple("dns323c-fan", 0, NULL, 0);
+
+                /* Register fixup for the PHY LEDs */
+                phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
+                                           MARVELL_PHY_ID_MASK,
+                                           dns323c_phy_fixup);
         }
 
         platform_device_register(&dns323_gpio_leds);
-
         platform_device_register(&dns323_button_device);
 
-        i2c_register_board_info(0, dns323_i2c_devices,
-                                ARRAY_SIZE(dns323_i2c_devices));
-
         /*
          * Configure peripherals.
          */
         if (dns323_read_mac_addr() < 0)
-                printk("DNS323: Failed to read MAC address\n");
-
+                printk("DNS-323: Failed to read MAC address\n");
         orion5x_ehci0_init();
         orion5x_eth_init(&dns323_eth_data);
         orion5x_i2c_init();
         orion5x_uart0_init();
 
-        /* The 5182 has its SATA controller on-chip, and needs its own little
-         * init routine.
-         */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
+        /* Remaining GPIOs */
+        switch(system_rev) {
+        case DNS323_REV_A1:
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
+                pm_power_off = dns323a_power_off;
+                break;
+        case DNS323_REV_B1:
+                /* 5182 built-in SATA init */
                 orion5x_sata_init(&dns323_sata_data);
 
-        /* The 5182 has flag to indicate the system is up. Without this flag
-         * set, power LED will flash and cannot be controlled via leds-gpio.
-         */
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
-                gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
-
-        /* Register dns323 specific power-off method */
-        if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
-            gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
-                pr_err("DNS323: failed to setup power-off GPIO\n");
-        if (dns323_dev_id() == MV88F5182_DEV_ID)
+                /* The DNS323 rev B1 has flag to indicate the system is up.
+                 * Without this flag set, power LED will flash and cannot be
+                 * controlled via leds-gpio.
+                 */
+                if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
+                        gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
+
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
                 pm_power_off = dns323b_power_off;
-        else
-                pm_power_off = dns323a_power_off;
+                break;
+        case DNS323_REV_C1:
+                /* 5182 built-in SATA init */
+                orion5x_sata_init(&dns323_sata_data);
+
+                /* Poweroff GPIO */
+                if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+                    gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
+                        pr_err("DNS-323: failed to setup power-off GPIO\n");
+                pm_power_off = dns323c_power_off;
+
+                /* Now, -this- should theorically be done by the sata_mv driver
+                 * once I figure out what's going on there. Maybe the behaviour
+                 * of the LEDs should be somewhat passed via the platform_data.
+                 * for now, just whack the register and make the LEDs happy
+                 *
+                 * Note: AFAIK, rev B1 needs the same treatement but I'll let
+                 * somebody else test it.
+                 */
+                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                break;
+        }
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c10458..a1d6e46ab035 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
          */
         orion5x_setbits(RSTOUTn_MASK, (1 << 2));
         orion5x_setbits(CPU_SOFT_RESET, 1);
+        mdelay(200);
+        orion5x_clrbits(CPU_SOFT_RESET, 1);
 }
 
 
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 240b68d511dc..7185b00650fe 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -398,28 +398,27 @@ static void __init free_unused_memmap(struct meminfo *mi)
         unsigned int i;
 
         /*
-         * [FIXME] This relies on each bank being in address order.  This
-         * may not be the case, especially if the user has provided the
-         * information on the command line.
+         * This relies on each bank being in address order.
+         * The banks are sorted previously in bootmem_init().
          */
         for_each_bank(i, mi) {
                 struct membank *bank = &mi->bank[i];
 
                 bank_start = bank_pfn_start(bank);
-                if (bank_start < prev_bank_end) {
-                        printk(KERN_ERR "MEM: unordered memory banks.  "
-                                "Not freeing memmap.\n");
-                        break;
-                }
 
                 /*
                  * If we had a previous bank, and there is a space
                  * between the current bank and the previous, free it.
                  */
-                if (prev_bank_end && prev_bank_end != bank_start)
+                if (prev_bank_end && prev_bank_end < bank_start)
                         free_memmap(prev_bank_end, bank_start);
 
-                prev_bank_end = bank_pfn_end(bank);
+                /*
+                 * Align up here since the VM subsystem insists that the
+                 * memmap entries are valid from the bank end aligned to
+                 * MAX_ORDER_NR_PAGES.
+                 */
+                prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
         }
 }
 
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51c5a07..4f5b39687df5 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
 #include <linux/shm.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/random.h>
 #include <asm/cputype.h>
 #include <asm/system.h>
 
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
                 start_addr = addr = TASK_UNMAPPED_BASE;
                 mm->cached_hole_size = 0;
         }
+        /* 8 bits of randomness in 20 address space bits */
+        if (current->flags & PF_RANDOMIZE)
+                addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
 
 full_search:
         if (do_align)
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644
index 000000000000..639c54a07992
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)    (n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)      (n + 0x8000)
+#define UARTB_BASE_ADDR(n)      (n + 0x10000)
+
+#define BOARD_IO_ADDR(n)        (n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG          0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG      0x08
+/* status, interrupt */
+#define INTR_STATUS_REG 0x10
+#define INTR_MASK_REG           0x38
+#define INTR_RESET_REG          0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG       0x40
+#define MAGIC_NUMBER2_REG       0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG       0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG       0x58
+/* module reset register*/
+#define MODULE_RESET_REG        0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG        0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES    16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET          (MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A       (MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B       (MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A      (MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B      (MXC_BOARD_IRQ_START + 4)
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+        {
+                .flags = IORESOURCE_MEM,
+        } , {
+                .start = EXPIO_INT_ENET,
+                .end = EXPIO_INT_ENET,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+        .name = "smsc911x",
+        .id = 0,
+        .dev = {
+                .platform_data = &smsc911x_config,
+        },
+        .num_resources = ARRAY_SIZE(smsc911x_resources),
+        .resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+        u32 imr_val;
+        u32 int_valid;
+        u32 expio_irq;
+
+        desc->chip->mask(irq);  /* irq = gpio irq number */
+
+        imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+        int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+        expio_irq = MXC_BOARD_IRQ_START;
+        for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+                struct irq_desc *d;
+                if ((int_valid & 1) == 0)
+                        continue;
+                d = irq_desc + expio_irq;
+                if (unlikely(!(d->handle_irq)))
+                        pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+                else
+                        d->handle_irq(expio_irq, d);
+        }
+
+        desc->chip->ack(irq);
+        desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+        u16 reg;
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        reg = __raw_readw(brd_io + INTR_MASK_REG);
+        reg |= (1 << expio);
+        __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        __raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+        __raw_writew(0, brd_io + INTR_RESET_REG);
+        expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+        u16 reg;
+        u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+        reg = __raw_readw(brd_io + INTR_MASK_REG);
+        reg &= ~(1 << expio);
+        __raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+        .ack = expio_ack_irq,
+        .mask = expio_mask_irq,
+        .unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+        int i;
+
+        brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+        if (brd_io == NULL)
+                return -ENOMEM;
+
+        if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+            (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+            (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+                pr_info("3-Stack Debug board not detected\n");
+                iounmap(brd_io);
+                brd_io = NULL;
+                return -ENODEV;
+        }
+
+        pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+                readw(brd_io + CPLD_CODE_VER_REG));
+
+        /*
+         * Configure INT line as GPIO input
+         */
+        gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+        gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+        /* disable the interrupt and clear the status */
+        __raw_writew(0, brd_io + INTR_MASK_REG);
+        __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+        __raw_writew(0, brd_io + INTR_RESET_REG);
+        __raw_writew(0x1F, brd_io + INTR_MASK_REG);
+        for (i = MXC_EXP_IO_BASE;
+             i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+                set_irq_chip(i, &expio_irq_chip);
+                set_irq_handler(i, handle_level_irq);
+                set_irq_flags(i, IRQF_VALID);
+        }
+        set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+        set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+        /* Register Lan device on the debugboard */
+        smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+        smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+        platform_device_register(&smsc_lan9217_device);
+
+        return 0;
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f289bd..0527e65318f4 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
 if ARCH_MXC
 
+source "arch/arm/plat-mxc/devices/Kconfig"
+
 menu "Freescale MXC Implementations"
 
 choice
@@ -8,15 +10,12 @@ choice
 
 config ARCH_MX1
         bool "MX1-based"
-        select CPU_ARM920T
-        select IMX_HAVE_IOMUX_V1
+        select SOC_IMX1
         help
           This enables support for systems based on the Freescale i.MX1 family
 
 config ARCH_MX2
         bool "MX2-based"
-        select CPU_ARM926T
-        select IMX_HAVE_IOMUX_V1
         help
           This enables support for systems based on the Freescale i.MX2 family
 
@@ -25,6 +24,7 @@ config ARCH_MX25
         select CPU_ARM926T
         select ARCH_MXC_IOMUX_V3
         select HAVE_FB_IMX
+        select ARCH_MXC_AUDMUX_V2
         help
           This enables support for systems based on the Freescale i.MX25 family
 
@@ -48,8 +48,7 @@ config ARCH_MX5
 
 endchoice
 
-source "arch/arm/mach-mx1/Kconfig"
-source "arch/arm/mach-mx2/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
 source "arch/arm/mach-mxc91231/Kconfig"
@@ -81,6 +80,17 @@ config MXC_PWM
         help
           Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+        bool "Enable MXC debug board(for 3-stack)"
+        help
+          The debug board is an integral part of the MXC 3-stack(PDK)
+          platforms, it can be attached or removed from the peripheral
+          board. On debug board, several debug devices(ethernet, UART,
+          buttons, LEDs and JTAG) are implemented. Between the MCU and
+          these devices, a CPLD is added as a bridge which performs
+          data/address de-multiplexing and decode, signal level shift,
+          interrupt control and various board functions.
+
 config MXC_ULPI
         bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c5e0c0..78d405ed8616 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 
-obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
-obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
@@ -17,7 +15,10 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
+
+obj-y += devices/
diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917ca3f95..1180bef7664b 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5cd4d83..f9e7cdbd0005 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
@@ -191,6 +187,7 @@ static int mxc_audmux_v2_init(void)
 {
         int ret;
 
+#if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31())
                 audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
 
@@ -204,7 +201,19 @@ static int mxc_audmux_v2_init(void)
                 }
                 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
         }
-
+#endif
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25()) {
+                audmux_clk = clk_get(NULL, "audmux");
+                if (IS_ERR(audmux_clk)) {
+                        ret = PTR_ERR(audmux_clk);
+                        printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+                                        ret);
+                        return ret;
+                }
+                audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+        }
+#endif
         audmux_debugfs_init();
 
         return 0;
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 323ff8ccc877..2ed3ab173add 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -52,13 +52,14 @@ static void __clk_disable(struct clk *clk)
 {
         if (clk == NULL || IS_ERR(clk))
                 return;
-
-        __clk_disable(clk->parent);
-        __clk_disable(clk->secondary);
-
         WARN_ON(!clk->usecount);
-        if (!(--clk->usecount) && clk->disable)
-                clk->disable(clk);
+
+        if (!(--clk->usecount)) {
+                if (clk->disable)
+                        clk->disable(clk);
+                __clk_disable(clk->parent);
+                __clk_disable(clk->secondary);
+        }
 }
 
 static int __clk_enable(struct clk *clk)
@@ -66,12 +67,13 @@ static int __clk_enable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
-        __clk_enable(clk->parent);
-        __clk_enable(clk->secondary);
-
-        if (clk->usecount++ == 0 && clk->enable)
-                clk->enable(clk);
+        if (clk->usecount++ == 0) {
+                __clk_enable(clk->parent);
+                __clk_enable(clk->secondary);
 
+                if (clk->enable)
+                        clk->enable(clk);
+        }
         return 0;
 }
 
@@ -160,17 +162,28 @@ EXPORT_SYMBOL(clk_set_rate);
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
         int ret = -EINVAL;
+        struct clk *old;
 
         if (clk == NULL || IS_ERR(clk) || parent == NULL ||
             IS_ERR(parent) || clk->set_parent == NULL)
                 return ret;
 
+        if (clk->usecount)
+                clk_enable(parent);
+
         mutex_lock(&clocks_mutex);
         ret = clk->set_parent(clk, parent);
-        if (ret == 0)
+        if (ret == 0) {
+                old = clk->parent;
                 clk->parent = parent;
+        } else {
+                old = parent;
+        }
         mutex_unlock(&clocks_mutex);
 
+        if (clk->usecount)
+                clk_disable(old);
+
         return ret;
 }
 EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5cc456..735776d84956 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/err.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
         return ret;
 }
 
+struct platform_device *__init imx_add_platform_device(const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data)
+{
+        int ret = -ENOMEM;
+        struct platform_device *pdev;
+
+        pdev = platform_device_alloc(name, id);
+        if (!pdev)
+                goto err;
+
+        if (res) {
+                ret = platform_device_add_resources(pdev, res, num_resources);
+                if (ret)
+                        goto err;
+        }
+
+        if (data) {
+                ret = platform_device_add_data(pdev, data, size_data);
+                if (ret)
+                        goto err;
+        }
+
+        ret = platform_device_add(pdev);
+        if (ret) {
+err:
+                platform_device_put(pdev);
+                return ERR_PTR(ret);
+        }
+
+        return pdev;
+}
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644
index 000000000000..9ab784b776f9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,15 @@
+config IMX_HAVE_PLATFORM_FLEXCAN
+        select HAVE_CAN_FLEXCAN
+        bool
+
+config IMX_HAVE_PLATFORM_IMX_I2C
+        bool
+
+config IMX_HAVE_PLATFORM_IMX_UART
+        bool
+
+config IMX_HAVE_PLATFORM_MXC_NAND
+        bool
+
+config IMX_HAVE_PLATFORM_SPI_IMX
+        bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 000000000000..347da5161f7e
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1,8 @@
+ifdef CONFIG_CAN_FLEXCAN
+# the ifdef can be removed once the flexcan driver has been merged
+obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) +=  platform-flexcan.o
+endif
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
new file mode 100644
index 000000000000..5e97a01f14f3
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2010 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644
index 000000000000..d0af9f7d8aed
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_i2c(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct imxi2c_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644
index 000000000000..fa3dff1433e8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irqrx, resource_size_t irqtx,
+                resource_size_t irqrts,
+                const struct imxuart_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irqrx,
+                        .end = irqrx,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irqtx,
+                        .end = irqtx,
+                        .flags = IORESOURCE_IRQ,
+                }, {
+                        .start = irqrts,
+                        .end = irqrx,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct imxuart_platform_data *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 000000000000..1c286418d123
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata,
+                resource_size_t iosize)
+{
+        static int id = 0;
+        
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata)
+{
+        return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
+}
+
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata)
+{
+        return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644
index 000000000000..2831a6d3eb4b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spi_imx(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct spi_imx_master *pdata)
+{
+        struct resource res[] = {
+                {
+                        .start = iobase,
+                        .end = iobase + iosize - 1,
+                        .flags = IORESOURCE_MEM,
+                }, {
+                        .start = irq,
+                        .end = irq,
+                        .flags = IORESOURCE_IRQ,
+                },
+        };
+
+        return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
+                        pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a8646173c2f..35a064ff02ba 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/platform_device.h>
@@ -73,7 +69,51 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
         unsigned int v;
-#ifdef CONFIG_ARCH_MX3
+#if defined(CONFIG_ARCH_MX25)
+        if (cpu_is_mx25()) {
+                v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+
+                switch (port) {
+                case 0: /* OTG port */
+                        v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                        << MX35_OTG_SIC_SHIFT;
+                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                                v |= MX35_OTG_PM_BIT;
+
+                        break;
+                case 1: /* H1 port */
+                        v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+                                MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                        v |= (flags & MXC_EHCI_INTERFACE_MASK)
+                                                << MX35_H1_SIC_SHIFT;
+                        if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+                                v |= MX35_H1_PM_BIT;
+
+                        if (!(flags & MXC_EHCI_TTL_ENABLED))
+                                v |= MX35_H1_TLL_BIT;
+
+                        if (flags & MXC_EHCI_INTERNAL_PHY)
+                                v |= MX35_H1_USBTE_BIT;
+
+                        if (flags & MXC_EHCI_IPPUE_DOWN)
+                                v |= MX35_H1_IPPUE_DOWN_BIT;
+
+                        if (flags & MXC_EHCI_IPPUE_UP)
+                                v |= MX35_H1_IPPUE_UP_BIT;
+
+                        break;
+                default:
+                        return -EINVAL;
+                }
+
+                writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+                                     USBCTRL_OTGBASE_OFFSET));
+                return 0;
+        }
+#endif /* CONFIG_ARCH_MX25 */
+#if defined(CONFIG_ARCH_MX3)
         if (cpu_is_mx31()) {
                 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
                                      USBCTRL_OTGBASE_OFFSET));
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 71437c61cfd7..57ec4a896a5d 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -214,13 +214,16 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
         struct mxc_gpio_port *port =
                 container_of(chip, struct mxc_gpio_port, chip);
         u32 l;
+        unsigned long flags;
 
+        spin_lock_irqsave(&port->lock, flags);
         l = __raw_readl(port->base + GPIO_GDIR);
         if (dir)
                 l |= 1 << offset;
         else
                 l &= ~(1 << offset);
         __raw_writel(l, port->base + GPIO_GDIR);
+        spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -229,9 +232,12 @@ static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                 container_of(chip, struct mxc_gpio_port, chip);
         void __iomem *reg = port->base + GPIO_DR;
         u32 l;
+        unsigned long flags;
 
+        spin_lock_irqsave(&port->lock, flags);
         l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
         __raw_writel(l, reg);
+        spin_unlock_irqrestore(&port->lock, flags);
 }
 
 static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
@@ -285,6 +291,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 port[i].chip.base = i * 32;
                 port[i].chip.ngpio = 32;
 
+                spin_lock_init(&port[i].lock);
+
                 /* its a serious configuration bug when it fails */
                 BUG_ON( gpiochip_add(&port[i].chip) < 0 );
 
@@ -292,6 +300,12 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                         /* setup one handler for each entry */
                         set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
                         set_irq_data(port[i].irq, &port[i]);
+                        if (port[i].irq_high) {
+                                /* setup handler for GPIO 16 to 31 */
+                                set_irq_chained_handler(port[i].irq_high,
+                                                mx3_gpio_irq_handler);
+                                set_irq_data(port[i].irq_high, &port[i]);
+                        }
                 }
         }
 
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 000000000000..a384fdd49c62
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c133c9f4..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>.
- * All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f104c7..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2009  Yoichi Yuasa <yuasa@linux-mips.org>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
-#define __ARM_ARCH_BOARD_KZM_ARM11_H
-
-/*
- *  KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1          (MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2          (MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1          (MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT    (MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV      (MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED      (MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS          (MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2        (MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550         (MX31_CS4_BASE_ADDR + 0x1050)
-
-#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
-
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa29510c..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-
-/*
- * Memory-mapped I/O on MX21ADS base board
- */
-#define MX21ADS_MMIO_BASE_ADDR   0xF5000000
-#define MX21ADS_MMIO_SIZE        SZ_16M
-
-#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-                (MX21ADS_MMIO_BASE_ADDR + (offset))
-
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
-#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP        0x0001 /* read */
-#define MX21ADS_IO_TP6          0x0001 /* write */
-#define MX21ADS_IO_SW_SEL       0x0002 /* read */
-#define MX21ADS_IO_TP7          0x0002 /* write */
-#define MX21ADS_IO_RESET_E_UART 0x0004
-#define MX21ADS_IO_RESET_BASE   0x0008
-#define MX21ADS_IO_CSI_CTL2     0x0010
-#define MX21ADS_IO_CSI_CTL1     0x0020
-#define MX21ADS_IO_CSI_CTL0     0x0040
-#define MX21ADS_IO_UART1_EN     0x0080
-#define MX21ADS_IO_UART4_EN     0x0100
-#define MX21ADS_IO_LCDON        0x0200
-#define MX21ADS_IO_IRDA_EN      0x0400
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
-#define MX21ADS_IO_IRDA_MD0_B   0x1000
-#define MX21ADS_IO_IRDA_MD1     0x2000
-#define MX21ADS_IO_LED4_ON      0x4000
-#define MX21ADS_IO_LED3_ON      0x8000
-
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d230327f..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-
-/* external interrupt multiplexer */
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-
-#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
-                                MXC_MAX_VIRTUAL_INTS)
-
-/*
- * @name Memory Size parameters
- */
-
-/*
- * Size of SDRAM memory
- */
-#define SDRAM_MEM_SIZE          SZ_128M
-
-/*
- * PBC Controller parameters
- */
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS        0xf4300000
-#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
-                (PBC_BASE_ADDRESS + (offset))
-
-/*
- * PBC Interupt name definitions
- */
-#define PBC_GPIO1_0  0
-#define PBC_GPIO1_1  1
-#define PBC_GPIO1_2  2
-#define PBC_GPIO1_3  3
-#define PBC_GPIO1_4  4
-#define PBC_GPIO1_5  5
-
-#define PBC_INTR_MAX_NUM 6
-#define PBC_INTR_SHARED_MAX_NUM 8
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH             0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 set address.
- */
-#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 clear address.
- */
-#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 clear address.
- */
-#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 4 clear address.
- */
-#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
-/*PBC_ADDR_SH
- * PBC Board status register 1.
- */
-#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt status register.
- */
-#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt current status register.
- */
-#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register set address.
- */
-#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register clear address.
- */
-#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
-/*
- * External UART A.
- */
-#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Status.
- */
-#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Set.
- */
-#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Clear.
- */
-#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller IO base address.
- */
-#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller Memory base address.
- */
-#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller DMA base address.
- */
-#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
-
-/* PBC Board Version Register bit definition */
-#define PBC_VERSION_ADS         0x8000  /* Bit15=1 means version for ads */
-#define PBC_VERSION_EVB_REVB    0x4000  /* BIT14=1 means version for evb revb */
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_ERST         0x0001  /* Ethernet Reset */
-#define PBC_BCTRL1_URST         0x0002  /* Reset External UART controller */
-#define PBC_BCTRL1_FRST         0x0004  /* FEC Reset */
-#define PBC_BCTRL1_ESLEEP       0x0010  /* Enable ethernet Sleep */
-#define PBC_BCTRL1_LCDON        0x0800  /* Enable the LCD */
-
-/* PBC Board Control Register 2 bit definitions */
-#define PBC_BCTRL2_VCC_EN       0x0004  /*   Enable VCC */
-#define PBC_BCTRL2_VPP_EN       0x0008  /*   Enable Vpp */
-#define PBC_BCTRL2_ATAFEC_EN    0X0010
-#define PBC_BCTRL2_ATAFEC_SEL   0X0020
-#define PBC_BCTRL2_ATA_EN       0X0040
-#define PBC_BCTRL2_IRDA_SD      0X0080
-#define PBC_BCTRL2_IRDA_EN      0X0100
-#define PBC_BCTRL2_CCTL10       0X0200
-#define PBC_BCTRL2_CCTL11       0X0400
-
-/* PBC Board Control Register 3 bit definitions */
-#define PBC_BCTRL3_HSH_EN       0X0020
-#define PBC_BCTRL3_FSH_MOD      0X0040
-#define PBC_BCTRL3_OTG_HS_EN    0X0080
-#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
-#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
-#define PBC_BCTRL3_USB_OTG_ON   0X0800
-#define PBC_BCTRL3_USB_FSH_ON   0X1000
-
-/* PBC Board Control Register 4 bit definitions */
-#define PBC_BCTRL4_REGEN_SEL    0X0001
-#define PBC_BCTRL4_USER_OFF     0X0002
-#define PBC_BCTRL4_VIB_EN       0X0004
-#define PBC_BCTRL4_PWRGT1_EN    0X0008
-#define PBC_BCTRL4_PWRGT2_EN    0X0010
-#define PBC_BCTRL4_STDBY_PRI    0X0020
-
-#ifndef __ASSEMBLY__
-/*
- * Enumerations for SD cards and memory stick card. This corresponds to
- * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
- */
-enum mxc_card_no {
-        MXC_CARD_SD2 = 0,
-        MXC_CARD_SD3,
-        MXC_CARD_MS,
-        MXC_CARD_SD1,
-        MXC_CARD_MIN = MXC_CARD_SD2,
-        MXC_CARD_MAX = MXC_CARD_SD1,
-};
-#endif
-
-#define MXC_CPLD_VER_1_50       0x01
-
-/*
- * PBC BSTAT Register bit definitions
- */
-#define PBC_BSTAT_PRI_INT       0X0001
-#define PBC_BSTAT_USB_BYP       0X0002
-#define PBC_BSTAT_ATA_IOCS16    0X0004
-#define PBC_BSTAT_ATA_CBLID     0X0008
-#define PBC_BSTAT_ATA_DASP      0X0010
-#define PBC_BSTAT_PWR_RDY       0X0020
-#define PBC_BSTAT_SD3_WP        0X0100
-#define PBC_BSTAT_SD2_WP        0X0200
-#define PBC_BSTAT_SD1_WP        0X0400
-#define PBC_BSTAT_SD3_DET       0X0800
-#define PBC_BSTAT_SD2_DET       0X1000
-#define PBC_BSTAT_SD1_DET       0X2000
-#define PBC_BSTAT_MS_DET        0X4000
-#define PBC_BSTAT_SD3_DET_BIT   11
-#define PBC_BSTAT_SD2_DET_BIT   12
-#define PBC_BSTAT_SD1_DET_BIT   13
-#define PBC_BSTAT_MS_DET_BIT    14
-#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
-                                 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
-                                 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
-                                 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
-                                        0x0))))
-
-/*
- * PBC UART Control Register bit definitions
- */
-#define PBC_UCTRL_DCE_DCD       0X0001
-#define PBC_UCTRL_DCE_DSR       0X0002
-#define PBC_UCTRL_DCE_RI        0X0004
-#define PBC_UCTRL_DTE_DTR       0X0100
-
-/*
- * PBC UART Status Register bit definitions
- */
-#define PBC_USTAT_DTE_DCD       0X0001
-#define PBC_USTAT_DTE_DSR       0X0002
-#define PBC_USTAT_DTE_RI        0X0004
-#define PBC_USTAT_DCE_DTR       0X0100
-
-/*
- * PBC Interupt mask register bit definitions
- */
-#define PBC_INTR_SD3_R_EN_BIT   4
-#define PBC_INTR_SD2_R_EN_BIT   0
-#define PBC_INTR_SD1_R_EN_BIT   6
-#define PBC_INTR_MS_R_EN_BIT    5
-#define PBC_INTR_SD3_EN_BIT     13
-#define PBC_INTR_SD2_EN_BIT     12
-#define PBC_INTR_MS_EN_BIT      14
-#define PBC_INTR_SD1_EN_BIT     15
-
-#define PBC_INTR_SD2_R_EN       0x0001
-#define PBC_INTR_LOW_BAT        0X0002
-#define PBC_INTR_OTG_FSOVER     0X0004
-#define PBC_INTR_FSH_OVER       0X0008
-#define PBC_INTR_SD3_R_EN       0x0010
-#define PBC_INTR_MS_R_EN        0x0020
-#define PBC_INTR_SD1_R_EN       0x0040
-#define PBC_INTR_FEC_INT        0X0080
-#define PBC_INTR_ENET_INT       0X0100
-#define PBC_INTR_OTGFS_INT      0X0200
-#define PBC_INTR_XUART_INT      0X0400
-#define PBC_INTR_CCTL12         0X0800
-#define PBC_INTR_SD2_EN         0x1000
-#define PBC_INTR_SD3_EN         0x2000
-#define PBC_INTR_MS_EN          0x4000
-#define PBC_INTR_SD1_EN         0x8000
-
-
-
-/* For interrupts like xuart, enet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
-#define MXC_MAX_EXP_IO_LINES    16
-
-/*
- * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
- *
- */
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
-
-/*
- * This is System IRQ used by CS8900A for interrupt generation
- * taken from platform.h
- */
-#define CS8900AIRQ              EXPIO_INT_ENET_INT
-/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
-#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
-
-#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
-
-/*
-* This is used to detect if the CPLD version is for mx27 evb board rev-a
-*/
-#define PBC_CPLD_VERSION_IS_REVA() \
-        ((__raw_readw(PBC_VERSION_REG) & \
-        (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
-        == 0)
-
-/* This is used to active or inactive ata signal in CPLD .
- *  It is dependent with hardware
- */
-#define PBC_ATA_SIGNAL_ACTIVE() \
-        __raw_writew(           \
-                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-                PBC_BCTRL2_CLEAR_REG)
-
-#define PBC_ATA_SIGNAL_INACTIVE() \
-        __raw_writew(  \
-                PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-                PBC_BCTRL2_SET_REG)
-
-#define MXC_BD_LED1             (1 << 5)
-#define MXC_BD_LED2             (1 << 6)
-#define MXC_BD_LED_ON(led) \
-        __raw_writew(led, PBC_BCTRL1_SET_REG)
-#define MXC_BD_LED_OFF(led) \
-        __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET      (1 << 3)
-
-#endif                          /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551d2736..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcfa9164..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933a233b..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS              CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR               CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR                       (DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG                    (CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG (EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG             (CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG               (CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG              (CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG          (CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG          (CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG               (CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG          (CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG           (CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG           (CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET          (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B       (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A      (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B      (MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES    16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199591c6..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* PBC Board status register offset */
-#define PBC_BSTAT               0x000002
-
-/* PBC Board control register 1 set address */
-#define PBC_BCTRL1_SET          0x000004
-
-/* PBC Board control register 1 clear address */
-#define PBC_BCTRL1_CLEAR        0x000006
-
-/* PBC Board control register 2 set address */
-#define PBC_BCTRL2_SET          0x000008
-
-/* PBC Board control register 2 clear address */
-#define PBC_BCTRL2_CLEAR        0x00000A
-
-/* PBC Board control register 3 set address */
-#define PBC_BCTRL3_SET          0x00000C
-
-/* PBC Board control register 3 clear address */
-#define PBC_BCTRL3_CLEAR        0x00000E
-
-/* PBC Board control register 4 set address */
-#define PBC_BCTRL4_SET          0x000010
-
-/* PBC Board control register 4 clear address */
-#define PBC_BCTRL4_CLEAR        0x000012
-
-/* PBC Board status register 1 */
-#define PBC_BSTAT1              0x000014
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS           0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS      0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET         0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR       0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA      0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB      0x010010
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-/* Ethernet Controller Memory base address */
-#define PBC_CS8900A_MEMBASE     0x021000
-
-/* Ethernet Controller DMA base address */
-#define PBC_CS8900A_DMABASE     0x022000
-
-/* External chip select 0 */
-#define PBC_XCS0                0x040000
-
-/* LCD Display enable */
-#define PBC_LCD_EN_B            0x060000
-
-/* Code test debug enable */
-#define PBC_CODE_B              0x070000
-
-/* PSRAM memory select */
-#define PBC_PSRAM_B             0x5000000
-
-#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-
-#define MXC_EXP_IO_BASE         (MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
-
-#define MXC_MAX_EXP_IO_LINES    16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a5024622e..0df71bfefbb1 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da0367578..c1ad0ae807cc 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3cedee1a..de14543891cf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f9786ed22..6f371e35753d 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside pcm038_init().
  *
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7af4b23..000000000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
-#define __ASM_ARCH_MXC_BOARD_QONG_H__
-
-/* NOR FLASH */
-#define QONG_NOR_SIZE           (128*1024*1024)
-
-#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 0b6e11eaeb8c..25606409aabc 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -23,8 +23,8 @@
 #error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
 #include <mach/mx25.h>
-#define UART_PADDR      UART1_BASE_ADDR
-#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+#define UART_PADDR      MX25_UART1_BASE_ADDR
+#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
 #endif
 
 #ifdef CONFIG_ARCH_MX2
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 000000000000..c5f68c587309
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *imx_add_platform_device(const char *name, int id,
+                const struct resource *res, unsigned int num_resources,
+                const void *data, size_t size_data);
+
+#if defined (CONFIG_CAN_FLEXCAN) || defined (CONFIG_CAN_FLEXCAN_MODULE)
+#include <linux/can/platform/flexcan.h>
+struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata);
+#else
+/* the ifdef can be removed once the flexcan driver has been merged */
+struct flexcan_platform_data;
+static inline struct platform_device *__init imx_add_flexcan(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct flexcan_platform_data *pdata)
+{
+        return NULL;
+}
+#endif
+
+#include <mach/i2c.h>
+struct platform_device *__init imx_add_imx_i2c(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct imxi2c_platform_data *pdata);
+
+#include <mach/imx-uart.h>
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irqrx, resource_size_t irqtx,
+                resource_size_t irqrts,
+                const struct imxuart_platform_data *pdata);
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+                resource_size_t iobase, resource_size_t iosize,
+                resource_size_t irq,
+                const struct imxuart_platform_data *pdata);
+
+#include <mach/mxc_nand.h>
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata);
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+                int irq, const struct mxc_nand_platform_data *pdata);
+
+#include <mach/spi.h>
+struct platform_device *__init imx_add_spi_imx(int id,
+                resource_size_t iobase, resource_size_t iosize, int irq,
+                const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
index a1fd5830af48..634e3f4c454d 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/eukrea-baseboards.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
  *
  * Based on board-pcm038.h which is :
  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
@@ -19,22 +19,29 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
-#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#ifndef __MACH_EUKREA_BASEBOARDS_H__
+#define __MACH_EUKREA_BASEBOARDS_H__
 
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx27_init().
+ * inside eukrea_cpuimx25_init() eukrea_cpuimx27_init()
+ * eukrea_cpuimx35_init() or eukrea_cpuimx51_init().
  *
  * This example here is for the development board. Refer
- * eukrea_mbimx27-baseboard.c
+ * mach-mx25/eukrea_mbimxsd-baseboard.c for cpuimx25
+ * mach-imx/eukrea_mbimx27-baseboard.c for cpuimx27
+ * mach-mx3/eukrea_mbimxsd-baseboard.c for cpuimx35
+ * mach-mx5/eukrea_mbimx51-baseboard.c for cpuimx51
  */
 
+extern void eukrea_mbimx25_baseboard_init(void);
 extern void eukrea_mbimx27_baseboard_init(void);
+extern void eukrea_mbimx35_baseboard_init(void);
+extern void eukrea_mbimx51_baseboard_init(void);
 
 #endif
 
-#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
+#endif /* __MACH_EUKREA_BASEBOARDS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index 894d2f87c856..661fbc605759 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -33,9 +33,11 @@
 struct mxc_gpio_port {
         void __iomem *base;
         int irq;
+        int irq_high;
         int virtual_irq_start;
         struct gpio_chip chip;
         u32 both_edges;
+        spinlock_t lock;
 };
 
 int mxc_gpio_init(struct mxc_gpio_port*, int);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d1b67a..d7f52c91f82e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__PWM4_PWMO    IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
@@ -371,30 +372,41 @@
 #define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTRL)
 #define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define KPP_CTL_ROW     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define KPP_CTL_COL     (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
+
+#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, KPP_CTL_ROW)
 #define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
 #define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL0__AUD5_TXD     IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL1__AUD5_RXD     IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL2__UART4_RTS    IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL2__AUD5_TXC     IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
-#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL3__UART4_CTS    IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL3__AUD5_TXFS    IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d953d0..21bfa46785bb 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
         IOMUX_CONFIG_ALT5,
         IOMUX_CONFIG_ALT6,
         IOMUX_CONFIG_ALT7,
-        IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
-        IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
+        IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+        IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -38,6 +38,8 @@ typedef enum iomux_config {
                                 PAD_CTL_SRE_FAST)
 #define MX51_UART3_PAD_CTRL     (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_SRE_FAST)
+#define MX51_I2C_PAD_CTRL       (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+                                PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_USBH1_PAD_CTRL     (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
                                 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
                                 PAD_CTL_PKE | PAD_CTL_HYS)
@@ -46,289 +48,278 @@ typedef enum iomux_config {
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*                                              PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16      IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17      IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18      IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19      IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20      IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21      IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5      IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22      IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23      IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS     IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD     IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD     IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS     IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28       IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29       IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30       IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31       IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16     IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17     IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18     IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19     IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20     IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21     IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22     IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23     IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24     IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25     IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26     IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27     IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0       IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1       IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2     IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3     IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE      IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0     IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1     IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2     IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3     IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4     IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5     IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK   IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA      IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE      IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1     IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B   IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B   IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE    IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE    IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B   IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0    IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1    IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2   IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3   IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND   IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4   IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5 IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7 IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6   IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0   IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1   IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2   IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3   IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4   IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5   IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6   IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7   IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT       IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15   IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14   IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13   IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12   IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11   IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10   IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9    IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8     IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7     IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6     IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5     IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4     IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3     IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2     IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1     IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0     IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8     IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9     IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10     IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11     IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12     IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13     IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14     IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15     IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16     IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17     IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18     IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19     IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK   IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0   IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12     IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13    IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14    IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15    IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16    IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17    IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18    IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19    IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC  IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC  IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0   IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK    IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT    IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK  IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS  IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI  IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO  IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0   IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1   IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY   IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK  IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x618, 0x228, IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD   IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD   IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE  IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0     IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1     IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2     IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3     IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0     IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1     IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2     IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3     IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4     IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5     IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK   IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR   IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27   IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT   IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11    IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12    IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13    IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS    IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS    IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3     IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2     IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4     IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2     IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3     IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6  IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7  IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8  IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9  IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0      IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1      IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD       IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK       IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0   IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1   IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2   IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3   IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2      IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3      IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4      IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5      IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6      IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7      IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8      IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-                                                (PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9      IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0       IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1       IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2       IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3       IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4       IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5       IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6       IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7       IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8       IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9       IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10     IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11     IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12     IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13     IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14     IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15     IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*                                                        PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0               IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1               IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2               IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3               IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4               IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5               IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6               IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7               IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8               IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9               IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10             IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11             IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12             IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13             IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14             IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15             IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA              IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
+                                                        0x09b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL              IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
+                                                        0x09b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5              IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__HSI2C_CLK            IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__HSI2C_DAT            IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD           IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD           IOMUX_PAD(0x634, 0x244, 1, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__UART3_RTS            IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL             IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
+                                                        0x09b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__UART3_CTS            IOMUX_PAD(0x660, 0x270, 2, 0,     0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA             IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
+                                                        0x09bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0             IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1             IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2             IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__I2C2_SCL             IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \
+                                                        0x9b8,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3             IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__I2C2_SDA             IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \
+                                                        0x9bc,   3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4             IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5             IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6             IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7             IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8             IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9             IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3fe29d4..15d59510f597 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d31d5ba..0880a4a1aed1 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST                (1 << 0)
 #define PAD_CTL_SRE_SLOW                (0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT      4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA      (0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB      (1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC      (2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD      (3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE      (4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF      (5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index c4b40c35a6a1..564ec9dbc93d 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -44,12 +44,12 @@
  */
 #define CONSISTENT_DMA_SIZE SZ_8M
 
-#elif defined(CONFIG_MX1_VIDEO)
+#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
 /*
  * Increase size of DMA-consistent memory region.
  * This is required for i.MX camera driver to capture at least four VGA frames.
  */
 #define CONSISTENT_DMA_SIZE SZ_4M
-#endif /* CONFIG_MX1_VIDEO */
+#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
 
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index de2128dada5c..29115f405af9 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -31,6 +31,9 @@ struct imxmmc_platform_data {
 
         /* adjust slot voltage */
         void (*setpower)(struct device *, unsigned int vdd);
+
+        /* enable card detect using DAT3 */
+        int dat3_card_detect;
 };
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6785de..641b24618239 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,24 +91,24 @@
 #define MX1_SIM_DATA_INT        16
 #define MX1_RTC_INT             17
 #define MX1_RTC_SAMINT          18
-#define MX1_UART2_MINT_PFERR    19
-#define MX1_UART2_MINT_RTS      20
-#define MX1_UART2_MINT_DTR      21
-#define MX1_UART2_MINT_UARTC    22
-#define MX1_UART2_MINT_TX       23
-#define MX1_UART2_MINT_RX       24
-#define MX1_UART1_MINT_PFERR    25
-#define MX1_UART1_MINT_RTS      26
-#define MX1_UART1_MINT_DTR      27
-#define MX1_UART1_MINT_UARTC    28
-#define MX1_UART1_MINT_TX       29
-#define MX1_UART1_MINT_RX       30
+#define MX1_INT_UART2PFERR      19
+#define MX1_INT_UART2RTS        20
+#define MX1_INT_UART2DTR        21
+#define MX1_INT_UART2UARTC      22
+#define MX1_INT_UART2TX         23
+#define MX1_INT_UART2RX         24
+#define MX1_INT_UART1PFERR      25
+#define MX1_INT_UART1RTS        26
+#define MX1_INT_UART1DTR        27
+#define MX1_INT_UART1UARTC      28
+#define MX1_INT_UART1TX         29
+#define MX1_INT_UART1RX         30
 #define MX1_VOICE_DAC_INT       31
 #define MX1_VOICE_ADC_INT       32
 #define MX1_PEN_DATA_INT        33
 #define MX1_PWM_INT             34
 #define MX1_SDHC_INT            35
-#define MX1_I2C_INT             39
+#define MX1_INT_I2C             39
 #define MX1_CSPI_INT            41
 #define MX1_SSI_TX_INT          42
 #define MX1_SSI_TX_ERR_INT      43
@@ -245,7 +245,7 @@
 #define PEN_DATA_INT MX1_PEN_DATA_INT
 #define PWM_INT MX1_PWM_INT
 #define SDHC_INT MX1_SDHC_INT
-#define I2C_INT MX1_I2C_INT
+#define I2C_INT MX1_INT_I2C
 #define CSPI_INT MX1_CSPI_INT
 #define SSI_TX_INT MX1_SSI_TX_INT
 #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e334bda5..4a6f800990f8 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,12 @@
 #define MX25_AVIC_BASE_ADDR_VIRT        0xfc400000
 #define MX25_AVIC_SIZE                  SZ_1M
 
+#define MX25_I2C1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_CAN1_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x88000)
+#define MX25_CAN2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x8c000)
+#define MX25_I2C2_BASE_ADDR             (MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR            (MX25_AIPS1_BASE_ADDR + 0xa4000)
 #define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
 
 #define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -27,22 +33,48 @@
         IMX_IO_ADDRESS(x, MX25_AIPS2) ?:                        \
         IMX_IO_ADDRESS(x, MX25_AVIC))
 
+#define MX25_AIPS1_IO_ADDRESS(x) \
+        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+
 #define MX25_UART1_BASE_ADDR            0x43f90000
 #define MX25_UART2_BASE_ADDR            0x43f94000
+#define MX25_AUDMUX_BASE_ADDR           0x43fb0000
+#define MX25_UART3_BASE_ADDR            0x5000c000
+#define MX25_UART4_BASE_ADDR            0x50008000
+#define MX25_UART5_BASE_ADDR            0x5002c000
 
+#define MX25_CSPI3_BASE_ADDR            0x50004000
+#define MX25_CSPI2_BASE_ADDR            0x50010000
 #define MX25_FEC_BASE_ADDR              0x50038000
+#define MX25_SSI2_BASE_ADDR             0x50014000
+#define MX25_SSI1_BASE_ADDR             0x50034000
 #define MX25_NFC_BASE_ADDR              0xbb000000
 #define MX25_DRYICE_BASE_ADDR           0x53ffc000
 #define MX25_LCDC_BASE_ADDR             0x53fbc000
+#define MX25_KPP_BASE_ADDR              0x43fa8000
+#define MX25_OTG_BASE_ADDR              0x53ff4000
+#define MX25_CSI_BASE_ADDR              0x53ff8000
 
-#define MX25_INT_DRYICE 25
-#define MX25_INT_FEC    57
-#define MX25_INT_NANDFC 33
-#define MX25_INT_LCDC   39
-
-#if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
-#define UART1_BASE_ADDR                 MX25_UART1_BASE_ADDR
-#define UART2_BASE_ADDR                 MX25_UART2_BASE_ADDR
-#endif
+#define MX25_INT_CSPI3          0
+#define MX25_INT_I2C1           3
+#define MX25_INT_I2C2           4
+#define MX25_INT_UART4          5
+#define MX25_INT_I2C3           10
+#define MX25_INT_SSI2           11
+#define MX25_INT_SSI1           12
+#define MX25_INT_CSPI2          13
+#define MX25_INT_CSPI1          14
+#define MX25_INT_CSI            17
+#define MX25_INT_UART3          18
+#define MX25_INT_KPP            24
+#define MX25_INT_DRYICE         25
+#define MX25_INT_UART2          32
+#define MX25_INT_NANDFC         33
+#define MX25_INT_LCDC           39
+#define MX25_INT_UART5          40
+#define MX25_INT_CAN1           43
+#define MX25_INT_CAN2           44
+#define MX25_INT_UART1          45
+#define MX25_INT_FEC            57
 
 #endif /* ifndef __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd75beee..a8ab2e02a8ca 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
 #define MX27_CSPI2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x0f000)
 #define MX27_SSI1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x10000)
 #define MX27_SSI2_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C_BASE_ADDR                      (MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_I2C1_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x12000)
 #define MX27_SDHC1_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x13000)
 #define MX27_SDHC2_BASE_ADDR                    (MX27_AIPI_BASE_ADDR + 0x14000)
 #define MX27_GPIO_BASE_ADDR                     (MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_SDHC3          9
 #define MX27_INT_SDHC2          10
 #define MX27_INT_SDHC1          11
-#define MX27_INT_I2C            12
+#define MX27_INT_I2C1           12
 #define MX27_INT_SSI2           13
 #define MX27_INT_SSI1           14
 #define MX27_INT_CSPI2          15
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
new file mode 100644
index 000000000000..3c080a32dbf5
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -0,0 +1,46 @@
+/*
+ * mx2-cam.h - i.MX27/i.MX25 camera driver header file
+ *
+ * Copyright (C) 2003, Intel Corporation
+ * Copyright (C) 2008, Sascha Hauer <s.hauer@pengutronix.de>
+ * Copyright (C) 2010, Baruch Siach <baruch@tkos.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX2_CAM_H_
+#define __MACH_MX2_CAM_H_
+
+#define MX2_CAMERA_SWAP16               (1 << 0)
+#define MX2_CAMERA_EXT_VSYNC            (1 << 1)
+#define MX2_CAMERA_CCIR                 (1 << 2)
+#define MX2_CAMERA_CCIR_INTERLACE       (1 << 3)
+#define MX2_CAMERA_HSYNC_HIGH           (1 << 4)
+#define MX2_CAMERA_GATED_CLOCK          (1 << 5)
+#define MX2_CAMERA_INV_DATA             (1 << 6)
+#define MX2_CAMERA_PCLK_SAMPLE_RISING   (1 << 7)
+#define MX2_CAMERA_PACK_DIR_MSB         (1 << 8)
+
+/**
+ * struct mx2_camera_platform_data - optional platform data for mx2_camera
+ * @flags: any combination of MX2_CAMERA_*
+ * @clk: clock rate of the csi block / 2
+ */
+struct mx2_camera_platform_data {
+        unsigned long flags;
+        unsigned long clk;
+};
+
+#endif /* __MACH_MX2_CAM_H_ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e119c2b5..afee3ab9d62e 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
 #define MX31_ETB_SLOT4_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x10000)
 #define MX31_ETB_SLOT5_BASE_ADDR                (MX31_AIPS1_BASE_ADDR + 0x14000)
 #define MX31_ECT_CTIO_BASE_ADDR                 (MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C1_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR                     (MX31_AIPS1_BASE_ADDR + 0x84000)
 #define MX31_OTG_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x88000)
 #define MX31_ATA_BASE_ADDR                      (MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_FIRI           7
 #define MX31_INT_MMC_SDHC2      8
 #define MX31_INT_MMC_SDHC1      9
-#define MX31_INT_I2C            10
+#define MX31_INT_I2C1           10
 #define MX31_INT_SSI2           11
 #define MX31_INT_SSI1           12
 #define MX31_INT_CSPI2          13
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a55842ae5..af3038c12e39 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
 #define MX35_ETB_SLOT4_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x10000)
 #define MX35_ETB_SLOT5_BASE_ADDR                (MX35_AIPS1_BASE_ADDR + 0x14000)
 #define MX35_ECT_CTIO_BASE_ADDR                 (MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C_BASE_ADDR                      (MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C1_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x80000)
 #define MX35_I2C3_BASE_ADDR                     (MX35_AIPS1_BASE_ADDR + 0x84000)
 #define MX35_UART1_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x90000)
 #define MX35_UART2_BASE_ADDR                    (MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -60,6 +60,8 @@
 #define MX35_RTC_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xd8000)
 #define MX35_WDOG_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xdc000)
 #define MX35_PWM_BASE_ADDR                      (MX35_AIPS2_BASE_ADDR + 0xe0000)
+#define MX35_CAN1_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe4000)
+#define MX35_CAN2_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xe8000)
 #define MX35_RTIC_BASE_ADDR                     (MX35_AIPS2_BASE_ADDR + 0xec000)
 #define MX35_OTG_BASE_ADDR              0x53ff4000
 
@@ -123,7 +125,7 @@
 #define MX35_INT_MMC_SDHC1      7
 #define MX35_INT_MMC_SDHC2      8
 #define MX35_INT_MMC_SDHC3      9
-#define MX35_INT_I2C            10
+#define MX35_INT_I2C1           10
 #define MX35_INT_SSI1           11
 #define MX35_INT_SSI2           12
 #define MX35_INT_CSPI2          13
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff27b5e2..f226ee3777e1 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b986b785..0ca3101ebf36 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __MACH_MXC91231_H__
 #define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 5d2d21d414e0..04c0d060d814 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -20,9 +20,13 @@
 #ifndef __ASM_ARCH_NAND_H
 #define __ASM_ARCH_NAND_H
 
+#include <linux/mtd/partitions.h>
+
 struct mxc_nand_platform_data {
-        int width;      /* data bus width in bytes */
-        int hw_ecc:1;   /* 0 if supress hardware ECC */
-        int flash_bbt:1; /* set to 1 to use a flash based bbt */
+        unsigned int width;     /* data bus width in bytes */
+        unsigned int hw_ecc:1;  /* 0 if supress hardware ECC */
+        unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
+        struct mtd_partition *parts;    /* partition table */
+        int nr_parts;                   /* size of parts */
 };
 #endif /* __ASM_ARCH_NAND_H */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199568de..4acd1143a9bd 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416ed11cd..2d9624697cc9 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0fddc48..d9bd37e4667a 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
 #define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a278434..ef6379c474be 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe57d89..7331f2ace5fe 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
         for (i = 0; i < 8; i++)
                 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-        /* init architectures chained interrupt handler */
-        mxc_register_gpios();
-
 #ifdef CONFIG_FIQ
         /* Initialize FIQ */
         init_FIQ();
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f42799fa58..925bce4607e7 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a60d43..b3da9aad4295 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
                 set_irq_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        mxc_register_gpios();
-
         pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a492a0f..779553a1595e 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <linux/delay.h>
 
 /*
  * PCIe unit register offsets.
@@ -46,6 +47,8 @@
 #define  PCIE_STAT_BUS_OFFS             8
 #define  PCIE_STAT_BUS_MASK             0xff
 #define  PCIE_STAT_LINK_DOWN            1
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET          (1<<20)
 
 
 u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
         writel(stat, base + PCIE_STAT_OFF);
 }
 
+void __init orion_pcie_reset(void __iomem *base)
+{
+        u32 reg;
+        int i;
+
+        /*
+         * MV-S104860-U0, Rev. C:
+         * PCI Express Unit Soft Reset
+         * When set, generates an internal reset in the PCI Express unit.
+         * This bit should be cleared after the link is re-established.
+         */
+        reg = readl(base + PCIE_DEBUG_CTRL);
+        reg |= PCIE_DEBUG_SOFT_RESET;
+        writel(reg, base + PCIE_DEBUG_CTRL);
+
+        for (i = 0; i < 20; i++) {
+                mdelay(10);
+
+                if (orion_pcie_link_up(base))
+                        break;
+        }
+
+        reg &= ~(PCIE_DEBUG_SOFT_RESET);
+        writel(reg, base + PCIE_DEBUG_CTRL);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
         u32 mask;
 
         /*
+         * soft reset PCIe unit
+         */
+        orion_pcie_reset(base);
+
+        /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
         orion_pcie_setup_wins(base, dram);