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-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/mach-s3c2410/Kconfig8
-rw-r--r--arch/arm/mach-s3c2410/Makefile.boot10
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-nrs.h25
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio-track.h4
-rw-r--r--arch/arm/mach-s3c2410/include/mach/gpio.h8
-rw-r--r--arch/arm/mach-s3c2410/include/mach/regs-gpio.h22
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c9
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c76
-rw-r--r--arch/arm/mach-s3c2410/pm.c15
-rw-r--r--arch/arm/mach-s3c2412/gpio.c20
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c2
-rw-r--r--arch/arm/mach-s3c2412/mach-smdk2413.c6
-rw-r--r--arch/arm/mach-s3c2440/Kconfig13
-rw-r--r--arch/arm/mach-s3c2440/Makefile1
-rw-r--r--arch/arm/mach-s3c2440/mach-rx1950.c582
-rw-r--r--arch/arm/mach-s3c2440/mach-rx3715.c2
-rw-r--r--arch/arm/mach-s3c2440/mach-smdk2440.c2
-rw-r--r--arch/arm/mach-s3c2443/mach-smdk2443.c2
-rw-r--r--arch/arm/mach-s3c64xx/clock.c36
-rw-r--r--arch/arm/mach-s3c64xx/dma.c2
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/regs-clock.h1
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6400.c2
-rw-r--r--arch/arm/mach-s3c64xx/mach-smdk6410.c2
-rw-r--r--arch/arm/mach-s5p6440/clock.c350
-rw-r--r--arch/arm/mach-s5p6440/cpu.c2
-rw-r--r--arch/arm/mach-s5p6440/include/mach/pwm-clock.h24
-rw-r--r--arch/arm/mach-s5p6442/cpu.c2
-rw-r--r--arch/arm/mach-s5p6442/include/mach/pwm-clock.h21
-rw-r--r--arch/arm/mach-s5pv210/Makefile2
-rw-r--r--arch/arm/mach-s5pv210/clock.c833
-rw-r--r--arch/arm/mach-s5pv210/cpu.c2
-rw-r--r--arch/arm/mach-s5pv210/gpiolib.c261
-rw-r--r--arch/arm/mach-s5pv210/include/mach/gpio.h18
-rw-r--r--arch/arm/mach-s5pv210/include/mach/pwm-clock.h21
-rw-r--r--arch/arm/mm/mmu.c5
-rw-r--r--arch/arm/plat-s3c24xx/devs.c19
-rw-r--r--arch/arm/plat-s3c24xx/dma.c2
-rw-r--r--arch/arm/plat-s3c24xx/gpio.c8
-rw-r--r--arch/arm/plat-s5p/clock.c13
-rw-r--r--arch/arm/plat-s5p/include/plat/irqs.h2
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h2
-rw-r--r--arch/arm/plat-samsung/Kconfig5
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/dev-hwmon.c42
-rw-r--r--arch/arm/plat-samsung/gpio-config.c12
-rw-r--r--arch/arm/plat-samsung/gpio.c15
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h4
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h14
-rw-r--r--arch/arm/plat-samsung/include/plat/hwmon.h10
-rw-r--r--arch/arm/plat-samsung/pm-gpio.c4
54 files changed, 2195 insertions, 357 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 15947397e12a..9505a70bfc0a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__
110head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o 110head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
111textofs-y := 0x00008000 111textofs-y := 0x00008000
112textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 112textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
113# We don't want the htc bootloader to corrupt kernel during resume
114textofs-$(CONFIG_PM_H1940) := 0x00108000
113# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory 115# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
114ifeq ($(CONFIG_ARCH_SA1100),y) 116ifeq ($(CONFIG_ARCH_SA1100),y)
115textofs-$(CONFIG_SA1111) := 0x00208000 117textofs-$(CONFIG_SA1111) := 0x00208000
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 9e5e96f12d86..a4c0b3fcdbba 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -96,12 +96,19 @@ config PM_H1940
96config MACH_N30 96config MACH_N30
97 bool "Acer N30 family" 97 bool "Acer N30 family"
98 select CPU_S3C2410 98 select CPU_S3C2410
99 select MACH_N35
99 select S3C_DEV_USB_HOST 100 select S3C_DEV_USB_HOST
100 select S3C_DEV_NAND 101 select S3C_DEV_NAND
101 help 102 help
102 Say Y here if you want suppt for the Acer N30, Acer N35, 103 Say Y here if you want suppt for the Acer N30, Acer N35,
103 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. 104 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
104 105
106config MACH_N35
107 bool
108 help
109 Internal node in order to enable support for Acer N35 if Acer N30 is
110 selected.
111
105config ARCH_BAST 112config ARCH_BAST
106 bool "Simtec Electronics BAST (EB2410ITX)" 113 bool "Simtec Electronics BAST (EB2410ITX)"
107 select CPU_S3C2410 114 select CPU_S3C2410
@@ -111,6 +118,7 @@ config ARCH_BAST
111 select MACH_BAST_IDE 118 select MACH_BAST_IDE
112 select S3C24XX_DCLK 119 select S3C24XX_DCLK
113 select ISA 120 select ISA
121 select S3C_DEV_HWMON
114 select S3C_DEV_USB_HOST 122 select S3C_DEV_USB_HOST
115 select S3C_DEV_NAND 123 select S3C_DEV_NAND
116 help 124 help
diff --git a/arch/arm/mach-s3c2410/Makefile.boot b/arch/arm/mach-s3c2410/Makefile.boot
index 7dab2a0325b5..58c1dd7f8e1d 100644
--- a/arch/arm/mach-s3c2410/Makefile.boot
+++ b/arch/arm/mach-s3c2410/Makefile.boot
@@ -1,3 +1,7 @@
1 zreladdr-y := 0x30008000 1ifeq ($(CONFIG_PM_H1940),y)
2params_phys-y := 0x30000100 2 zreladdr-y := 0x30108000
3 3 params_phys-y := 0x30100100
4else
5 zreladdr-y := 0x30008000
6 params_phys-y := 0x30000100
7endif
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
index f3182ff847cb..4f7bf3272e87 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h
@@ -16,15 +16,28 @@
16 16
17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) 17#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
18 18
19#define S3C2410_GPIO_BANKA (32*0)
20#define S3C2410_GPIO_BANKB (32*1)
21#define S3C2410_GPIO_BANKC (32*2)
22#define S3C2410_GPIO_BANKD (32*3)
23#define S3C2410_GPIO_BANKE (32*4)
24#define S3C2410_GPIO_BANKF (32*5)
25#define S3C2410_GPIO_BANKG (32*6) 19#define S3C2410_GPIO_BANKG (32*6)
26#define S3C2410_GPIO_BANKH (32*7) 20#define S3C2410_GPIO_BANKH (32*7)
27 21
22/* GPIO sizes for various SoCs:
23 *
24 * 2442
25 * 2410 2412 2440 2443 2416
26 * ---- ---- ---- ---- ----
27 * A 23 22 25 16 25
28 * B 11 11 11 11 9
29 * C 16 15 16 16 16
30 * D 16 16 16 16 16
31 * E 16 16 16 16 16
32 * F 8 8 8 8 8
33 * G 16 16 16 16 8
34 * H 11 11 9 15 15
35 * J -- -- 13 16 --
36 * K -- -- -- -- 16
37 * L -- -- -- 15 7
38 * M -- -- -- 2 2
39 */
40
28/* GPIO bank sizes */ 41/* GPIO bank sizes */
29#define S3C2410_GPIO_A_NR (32) 42#define S3C2410_GPIO_A_NR (32)
30#define S3C2410_GPIO_B_NR (32) 43#define S3C2410_GPIO_B_NR (32)
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
index acb259103808..d67819dde42a 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h
@@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
23{ 23{
24 struct s3c_gpio_chip *chip; 24 struct s3c_gpio_chip *chip;
25 25
26 if (pin > S3C2410_GPG(10)) 26 if (pin > S3C_GPIO_END)
27 return NULL; 27 return NULL;
28 28
29 chip = &s3c24xx_gpios[pin/32]; 29 chip = &s3c24xx_gpios[pin/32];
30 return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL; 30 return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
31} 31}
32 32
33#endif /* __ASM_ARCH_GPIO_CORE_H */ 33#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index 15f0b3e7ce69..b649bf2ccd5c 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -20,10 +20,18 @@
20 * devices that need GPIO. 20 * devices that need GPIO.
21 */ 21 */
22 22
23#ifdef CONFIG_CPU_S3C244X
24#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
25#else
23#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) 26#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
27#endif
24 28
25#include <asm-generic/gpio.h> 29#include <asm-generic/gpio.h>
26#include <mach/gpio-nrs.h> 30#include <mach/gpio-nrs.h>
27#include <mach/gpio-fns.h> 31#include <mach/gpio-fns.h>
28 32
33#ifdef CONFIG_CPU_S3C24XX
34#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
35#else
29#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) 36#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
37#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index a6384239eddf..a0a89d429296 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -17,29 +17,11 @@
17#include <mach/gpio-nrs.h> 17#include <mach/gpio-nrs.h>
18 18
19#ifdef CONFIG_CPU_S3C2400 19#ifdef CONFIG_CPU_S3C2400
20#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) 20#define S3C24XX_MISCCR S3C2400_MISCCR
21#define S3C24XX_MISCCR S3C2400_MISCCR
22#else 21#else
23#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) 22#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
24#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
25#endif /* CONFIG_CPU_S3C2400 */ 23#endif /* CONFIG_CPU_S3C2400 */
26 24
27
28/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
29
30#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
31#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
32#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
33 (2 * (S3C2400_BANKNUM(pin)-2)))
34
35#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
36 S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
37 S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
38
39
40#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
41#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
42
43/* general configuration options */ 25/* general configuration options */
44 26
45#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) 27#define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index b061ddcf3067..c1f90f6fab42 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -633,7 +633,7 @@ static void __init bast_map_io(void)
633 633
634 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); 634 s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
635 635
636 s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; 636 s3c_hwmon_set_platdata(&bast_hwmon_info);
637 637
638 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); 638 s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
639 s3c24xx_init_clocks(0); 639 s3c24xx_init_clocks(0);
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 9531b4c41deb..d2a2fad7db97 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -163,8 +163,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
163 .xres = 240, 163 .xres = 240,
164 .yres = 320, 164 .yres = 320,
165 .bpp = 16, 165 .bpp = 16,
166 .left_margin = 20, 166 .left_margin = 8,
167 .right_margin = 8, 167 .right_margin = 20,
168 .hsync_len = 4, 168 .hsync_len = 4,
169 .upper_margin = 8, 169 .upper_margin = 8,
170 .lower_margin = 7, 170 .lower_margin = 7,
@@ -272,7 +272,6 @@ static struct platform_device h1940_lcd_powerdev = {
272}; 272};
273 273
274static struct platform_device *h1940_devices[] __initdata = { 274static struct platform_device *h1940_devices[] __initdata = {
275 &s3c_device_ts,
276 &s3c_device_ohci, 275 &s3c_device_ohci,
277 &s3c_device_lcd, 276 &s3c_device_lcd,
278 &s3c_device_wdt, 277 &s3c_device_wdt,
@@ -286,6 +285,8 @@ static struct platform_device *h1940_devices[] __initdata = {
286 &s3c_device_timer[0], 285 &s3c_device_timer[0],
287 &h1940_backlight, 286 &h1940_backlight,
288 &h1940_lcd_powerdev, 287 &h1940_lcd_powerdev,
288 &s3c_device_adc,
289 &s3c_device_ts,
289}; 290};
290 291
291static void __init h1940_map_io(void) 292static void __init h1940_map_io(void)
@@ -339,7 +340,7 @@ static void __init h1940_init(void)
339} 340}
340 341
341MACHINE_START(H1940, "IPAQ-H1940") 342MACHINE_START(H1940, "IPAQ-H1940")
342 /* Maintainer: Ben Dooks <ben@fluff.org> */ 343 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
343 .phys_io = S3C2410_PA_UART, 344 .phys_io = S3C2410_PA_UART,
344 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 345 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
345 .boot_params = S3C2410_SDRAM_PA + 0x100, 346 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 75a9fd37a467..41f299d983eb 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -26,6 +26,7 @@
26#include <linux/serial_core.h> 26#include <linux/serial_core.h>
27#include <linux/timer.h> 27#include <linux/timer.h>
28#include <linux/io.h> 28#include <linux/io.h>
29#include <linux/mmc/host.h>
29 30
30#include <mach/hardware.h> 31#include <mach/hardware.h>
31#include <asm/irq.h> 32#include <asm/irq.h>
@@ -46,6 +47,7 @@
46#include <plat/clock.h> 47#include <plat/clock.h>
47#include <plat/cpu.h> 48#include <plat/cpu.h>
48#include <plat/devs.h> 49#include <plat/devs.h>
50#include <plat/mci.h>
49#include <plat/s3c2410.h> 51#include <plat/s3c2410.h>
50#include <plat/udc.h> 52#include <plat/udc.h>
51 53
@@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = {
172 { 174 {
173 .gpio = S3C2410_GPF(0), 175 .gpio = S3C2410_GPF(0),
174 .code = KEY_POWER, 176 .code = KEY_POWER,
177 .type = EV_PWR,
175 .desc = "Power", 178 .desc = "Power",
176 .active_low = 0, 179 .active_low = 0,
180 .wakeup = 1,
177 }, 181 },
178 { 182 {
179 .gpio = S3C2410_GPG(9), 183 .gpio = S3C2410_GPG(9),
@@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
264 .def_trigger = "", 268 .def_trigger = "",
265}; 269};
266 270
271/* This is the blue LED on the device. Originaly used to indicate GPS activity
272 * by flashing. */
273static struct s3c24xx_led_platdata n35_blue_led_pdata = {
274 .name = "blue_led",
275 .gpio = S3C2410_GPD(8),
276 .def_trigger = "",
277};
278
267/* This LED is driven by the battery microcontroller, and is blinking 279/* This LED is driven by the battery microcontroller, and is blinking
268 * red, blinking green or solid green when the battery is low, 280 * red, blinking green or solid green when the battery is low,
269 * charging or full respectively. By driving GPD9 low, it's possible 281 * charging or full respectively. By driving GPD9 low, it's possible
@@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = {
275 .def_trigger = "", 287 .def_trigger = "",
276}; 288};
277 289
290static struct s3c24xx_led_platdata n35_warning_led_pdata = {
291 .name = "warning_led",
292 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
293 .gpio = S3C2410_GPD(9),
294 .def_trigger = "",
295};
296
278static struct platform_device n30_blue_led = { 297static struct platform_device n30_blue_led = {
279 .name = "s3c24xx_led", 298 .name = "s3c24xx_led",
280 .id = 1, 299 .id = 1,
@@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = {
283 }, 302 },
284}; 303};
285 304
305static struct platform_device n35_blue_led = {
306 .name = "s3c24xx_led",
307 .id = 1,
308 .dev = {
309 .platform_data = &n35_blue_led_pdata,
310 },
311};
312
286static struct platform_device n30_warning_led = { 313static struct platform_device n30_warning_led = {
287 .name = "s3c24xx_led", 314 .name = "s3c24xx_led",
288 .id = 2, 315 .id = 2,
@@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = {
291 }, 318 },
292}; 319};
293 320
321static struct platform_device n35_warning_led = {
322 .name = "s3c24xx_led",
323 .id = 2,
324 .dev = {
325 .platform_data = &n35_warning_led_pdata,
326 },
327};
328
294static struct s3c2410fb_display n30_display __initdata = { 329static struct s3c2410fb_display n30_display __initdata = {
295 .type = S3C2410_LCDCON1_TFT, 330 .type = S3C2410_LCDCON1_TFT,
296 .width = 240, 331 .width = 240,
@@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
317 .lpcsel = 0x06, 352 .lpcsel = 0x06,
318}; 353};
319 354
355static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
356{
357 switch (power_mode) {
358 case MMC_POWER_ON:
359 case MMC_POWER_UP:
360 gpio_set_value(S3C2410_GPG(4), 1);
361 break;
362 case MMC_POWER_OFF:
363 default:
364 gpio_set_value(S3C2410_GPG(4), 0);
365 break;
366 }
367}
368
369static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
370 .gpio_detect = S3C2410_GPF(1),
371 .gpio_wprotect = S3C2410_GPG(10),
372 .ocr_avail = MMC_VDD_32_33,
373 .set_power = n30_sdi_set_power,
374};
375
320static struct platform_device *n30_devices[] __initdata = { 376static struct platform_device *n30_devices[] __initdata = {
321 &s3c_device_lcd, 377 &s3c_device_lcd,
322 &s3c_device_wdt, 378 &s3c_device_wdt,
323 &s3c_device_i2c0, 379 &s3c_device_i2c0,
324 &s3c_device_iis, 380 &s3c_device_iis,
325 &s3c_device_ohci, 381 &s3c_device_ohci,
382 &s3c_device_rtc,
326 &s3c_device_usbgadget, 383 &s3c_device_usbgadget,
384 &s3c_device_sdi,
327 &n30_button_device, 385 &n30_button_device,
328 &n30_blue_led, 386 &n30_blue_led,
329 &n30_warning_led, 387 &n30_warning_led,
@@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = {
334 &s3c_device_wdt, 392 &s3c_device_wdt,
335 &s3c_device_i2c0, 393 &s3c_device_i2c0,
336 &s3c_device_iis, 394 &s3c_device_iis,
395 &s3c_device_rtc,
337 &s3c_device_usbgadget, 396 &s3c_device_usbgadget,
397 &s3c_device_sdi,
338 &n35_button_device, 398 &n35_button_device,
399 &n35_blue_led,
400 &n35_warning_led,
339}; 401};
340 402
341static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { 403static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
@@ -490,17 +552,15 @@ static void __init n30_map_io(void)
490 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); 552 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
491} 553}
492 554
493static void __init n30_init_irq(void)
494{
495 s3c24xx_init_irq();
496}
497
498/* GPB3 is the line that controls the pull-up for the USB D+ line */ 555/* GPB3 is the line that controls the pull-up for the USB D+ line */
499 556
500static void __init n30_init(void) 557static void __init n30_init(void)
501{ 558{
559 WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
560
502 s3c24xx_fb_set_platdata(&n30_fb_info); 561 s3c24xx_fb_set_platdata(&n30_fb_info);
503 s3c24xx_udc_set_platdata(&n30_udc_cfg); 562 s3c24xx_udc_set_platdata(&n30_udc_cfg);
563 s3c24xx_mci_set_platdata(&n30_mci_cfg);
504 s3c_i2c0_set_platdata(&n30_i2ccfg); 564 s3c_i2c0_set_platdata(&n30_i2ccfg);
505 565
506 /* Turn off suspend on both USB ports, and switch the 566 /* Turn off suspend on both USB ports, and switch the
@@ -532,7 +592,7 @@ static void __init n30_init(void)
532 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | 592 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
533 S3C2410_MISCCR_USBSUSPND0 | 593 S3C2410_MISCCR_USBSUSPND0 |
534 S3C2410_MISCCR_USBSUSPND1, 594 S3C2410_MISCCR_USBSUSPND1,
535 S3C2410_MISCCR_USBSUSPND1); 595 S3C2410_MISCCR_USBSUSPND0);
536 596
537 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); 597 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
538 } 598 }
@@ -550,7 +610,7 @@ MACHINE_START(N30, "Acer-N30")
550 .boot_params = S3C2410_SDRAM_PA + 0x100, 610 .boot_params = S3C2410_SDRAM_PA + 0x100,
551 .timer = &s3c24xx_timer, 611 .timer = &s3c24xx_timer,
552 .init_machine = n30_init, 612 .init_machine = n30_init,
553 .init_irq = n30_init_irq, 613 .init_irq = s3c24xx_init_irq,
554 .map_io = n30_map_io, 614 .map_io = n30_map_io,
555MACHINE_END 615MACHINE_END
556 616
@@ -562,6 +622,6 @@ MACHINE_START(N35, "Acer-N35")
562 .boot_params = S3C2410_SDRAM_PA + 0x100, 622 .boot_params = S3C2410_SDRAM_PA + 0x100,
563 .timer = &s3c24xx_timer, 623 .timer = &s3c24xx_timer,
564 .init_machine = n30_init, 624 .init_machine = n30_init,
565 .init_irq = n30_init_irq, 625 .init_irq = s3c24xx_init_irq,
566 .map_io = n30_map_io, 626 .map_io = n30_map_io,
567MACHINE_END 627MACHINE_END
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 966119c8efee..725636fc4dc3 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void)
60 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); 60 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
61 } 61 }
62 62
63 /* the RX3715 uses similar code and the same H1940 and the 63 /* RX3715 and RX1950 use similar to H1940 code and the
64 * same offsets for resume and checksum pointers */ 64 * same offsets for resume and checksum pointers */
65 65
66 if (machine_is_rx3715()) { 66 if (machine_is_rx3715() || machine_is_rx1950()) {
67 void *base = phys_to_virt(H1940_SUSPEND_CHECK); 67 void *base = phys_to_virt(H1940_SUSPEND_CHECK);
68 unsigned long ptr; 68 unsigned long ptr;
69 unsigned long calc = 0; 69 unsigned long calc = 0;
@@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void)
79 if ( machine_is_aml_m5900() ) 79 if ( machine_is_aml_m5900() )
80 s3c2410_gpio_setpin(S3C2410_GPF(2), 1); 80 s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
81 81
82 if (machine_is_rx1950()) {
83 /* According to S3C2442 user's manual, page 7-17,
84 * when the system is operating in NAND boot mode,
85 * the hardware pin configuration - EINT[23:21] –
86 * must be set as input for starting up after
87 * wakeup from sleep mode
88 */
89 s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
90 s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
91 s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
92 }
82} 93}
83 94
84static int s3c2410_pm_resume(struct sys_device *dev) 95static int s3c2410_pm_resume(struct sys_device *dev)
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c
index f7afece7fc38..3404a876b33e 100644
--- a/arch/arm/mach-s3c2412/gpio.c
+++ b/arch/arm/mach-s3c2412/gpio.c
@@ -16,41 +16,43 @@
16#include <linux/types.h> 16#include <linux/types.h>
17#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/gpio.h>
19 20
20#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
21#include <asm/mach/map.h> 22#include <asm/mach/map.h>
22 23
23#include <mach/regs-gpio.h> 24#include <mach/regs-gpio.h>
24
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include <plat/gpio-core.h>
28
27int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) 29int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
28{ 30{
29 void __iomem *base = S3C24XX_GPIO_BASE(pin); 31 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
30 unsigned long offs = S3C2410_GPIO_OFFSET(pin); 32 unsigned long offs = pin - chip->chip.base;
31 unsigned long flags; 33 unsigned long flags;
32 unsigned long slpcon; 34 unsigned long slpcon;
33 35
34 offs *= 2; 36 offs *= 2;
35 37
36 if (pin < S3C2410_GPIO_BANKB) 38 if (pin < S3C2410_GPB(0))
37 return -EINVAL; 39 return -EINVAL;
38 40
39 if (pin >= S3C2410_GPIO_BANKF && 41 if (pin >= S3C2410_GPF(0) &&
40 pin <= S3C2410_GPIO_BANKG) 42 pin <= S3C2410_GPG(16))
41 return -EINVAL; 43 return -EINVAL;
42 44
43 if (pin > (S3C2410_GPIO_BANKH + 32)) 45 if (pin > S3C2410_GPH(16))
44 return -EINVAL; 46 return -EINVAL;
45 47
46 local_irq_save(flags); 48 local_irq_save(flags);
47 49
48 slpcon = __raw_readl(base + 0x0C); 50 slpcon = __raw_readl(chip->base + 0x0C);
49 51
50 slpcon &= ~(3 << offs); 52 slpcon &= ~(3 << offs);
51 slpcon |= state << offs; 53 slpcon |= state << offs;
52 54
53 __raw_writel(slpcon, base + 0x0C); 55 __raw_writel(slpcon, chip->base + 0x0C);
54 56
55 local_irq_restore(flags); 57 local_irq_restore(flags);
56 58
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 43160183571a..478f4b4606c2 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -674,7 +674,7 @@ static void __init jive_machine_init(void)
674} 674}
675 675
676MACHINE_START(JIVE, "JIVE") 676MACHINE_START(JIVE, "JIVE")
677 /* Maintainer: Ben Dooks <ben@fluff.org> */ 677 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
678 .phys_io = S3C2410_PA_UART, 678 .phys_io = S3C2410_PA_UART,
679 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 679 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
680 .boot_params = S3C2410_SDRAM_PA + 0x100, 680 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index faddb36ed23b..ba93a356a839 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void)
150} 150}
151 151
152MACHINE_START(S3C2413, "S3C2413") 152MACHINE_START(S3C2413, "S3C2413")
153 /* Maintainer: Ben Dooks <ben@fluff.org> */ 153 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
154 .phys_io = S3C2410_PA_UART, 154 .phys_io = S3C2410_PA_UART,
155 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 155 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
156 .boot_params = S3C2410_SDRAM_PA + 0x100, 156 .boot_params = S3C2410_SDRAM_PA + 0x100,
@@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413")
163MACHINE_END 163MACHINE_END
164 164
165MACHINE_START(SMDK2412, "SMDK2412") 165MACHINE_START(SMDK2412, "SMDK2412")
166 /* Maintainer: Ben Dooks <ben@fluff.org> */ 166 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
167 .phys_io = S3C2410_PA_UART, 167 .phys_io = S3C2410_PA_UART,
168 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 168 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
169 .boot_params = S3C2410_SDRAM_PA + 0x100, 169 .boot_params = S3C2410_SDRAM_PA + 0x100,
@@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
176MACHINE_END 176MACHINE_END
177 177
178MACHINE_START(SMDK2413, "SMDK2413") 178MACHINE_START(SMDK2413, "SMDK2413")
179 /* Maintainer: Ben Dooks <ben@fluff.org> */ 179 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
180 .phys_io = S3C2410_PA_UART, 180 .phys_io = S3C2410_PA_UART,
181 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 181 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
182 .boot_params = S3C2410_SDRAM_PA + 0x100, 182 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 9d102b912091..cd8e7de388f0 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -188,4 +188,17 @@ config MACH_MINI2440
188 Say Y here to select support for the MINI2440. Is a 10cm x 10cm board 188 Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
189 available via various sources. It can come with a 3.5" or 7" touch LCD. 189 available via various sources. It can come with a 3.5" or 7" touch LCD.
190 190
191config MACH_RX1950
192 bool "HP iPAQ rx1950"
193 select CPU_S3C2442
194 select S3C24XX_DCLK
195 select PM_H1940 if PM
196 select I2C
197 select S3C2410_PWM
198 select S3C_DEV_NAND
199 select S3C2410_IOTIMING if S3C2440_CPUFREQ
200 select S3C2440_XTAL_16934400
201 help
202 Say Y here if you're using HP iPAQ rx1950
203
191endmenu 204endmenu
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index c85ba32d8956..d5440fa34b04 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
34obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o 34obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
35obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o 35obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
36obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o 36obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
37obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
37 38
38# extra machine support 39# extra machine support
39 40
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
new file mode 100644
index 000000000000..8603b577a24b
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -0,0 +1,582 @@
1/* linux/arch/arm/mach-s3c2440/mach-rx1950.c
2 *
3 * Copyright (c) 2006-2009 Victor Chukhantsev, Denis Grigoriev,
4 * Copyright (c) 2007-2010 Vasily Khoruzhick
5 *
6 * based on smdk2440 written by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/interrupt.h>
17#include <linux/list.h>
18#include <linux/delay.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/gpio.h>
22#include <linux/platform_device.h>
23#include <linux/serial_core.h>
24#include <linux/input.h>
25#include <linux/gpio_keys.h>
26#include <linux/sysdev.h>
27#include <linux/pwm_backlight.h>
28#include <linux/pwm.h>
29
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32
33#include <linux/mmc/host.h>
34
35#include <asm/mach/arch.h>
36#include <asm/mach/map.h>
37#include <asm/mach-types.h>
38
39#include <mach/regs-gpio.h>
40#include <mach/regs-gpioj.h>
41#include <mach/h1940.h>
42#include <mach/fb.h>
43
44#include <plat/clock.h>
45#include <plat/regs-serial.h>
46#include <plat/regs-iic.h>
47#include <plat/mci.h>
48#include <plat/udc.h>
49#include <plat/nand.h>
50#include <plat/iic.h>
51#include <plat/devs.h>
52#include <plat/cpu.h>
53#include <plat/pm.h>
54#include <plat/irq.h>
55#include <plat/ts.h>
56
57#define LCD_PWM_PERIOD 192960
58#define LCD_PWM_DUTY 127353
59
60static struct map_desc rx1950_iodesc[] __initdata = {
61};
62
63static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
64 [0] = {
65 .name = "fclk",
66 .divisor = 0x0a,
67 .min_baud = 0,
68 .max_baud = 0,
69 },
70};
71
72static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = 0x3c5,
77 .ulcon = 0x03,
78 .ufcon = 0x51,
79 .clocks = rx1950_serial_clocks,
80 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
81 },
82 [1] = {
83 .hwport = 1,
84 .flags = 0,
85 .ucon = 0x3c5,
86 .ulcon = 0x03,
87 .ufcon = 0x51,
88 .clocks = rx1950_serial_clocks,
89 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
90 },
91 /* IR port */
92 [2] = {
93 .hwport = 2,
94 .flags = 0,
95 .ucon = 0x3c5,
96 .ulcon = 0x43,
97 .ufcon = 0xf1,
98 .clocks = rx1950_serial_clocks,
99 .clocks_size = ARRAY_SIZE(rx1950_serial_clocks),
100 },
101};
102
103static struct s3c2410fb_display rx1950_display = {
104 .type = S3C2410_LCDCON1_TFT,
105 .width = 240,
106 .height = 320,
107 .xres = 240,
108 .yres = 320,
109 .bpp = 16,
110
111 .pixclock = 260000,
112 .left_margin = 10,
113 .right_margin = 20,
114 .hsync_len = 10,
115 .upper_margin = 2,
116 .lower_margin = 2,
117 .vsync_len = 2,
118
119 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
120 S3C2410_LCDCON5_INVVCLK |
121 S3C2410_LCDCON5_INVVLINE |
122 S3C2410_LCDCON5_INVVFRAME |
123 S3C2410_LCDCON5_HWSWP |
124 (0x02 << 13) |
125 (0x02 << 15),
126
127};
128
129static struct s3c2410fb_mach_info rx1950_lcd_cfg = {
130 .displays = &rx1950_display,
131 .num_displays = 1,
132 .default_display = 0,
133
134 .lpcsel = 0x02,
135 .gpccon = 0xaa9556a9,
136 .gpccon_mask = 0xffc003fc,
137 .gpcup = 0x0000ffff,
138 .gpcup_mask = 0xffffffff,
139
140 .gpdcon = 0xaa90aaa1,
141 .gpdcon_mask = 0xffc0fff0,
142 .gpdup = 0x0000fcfd,
143 .gpdup_mask = 0xffffffff,
144
145};
146
147static struct pwm_device *lcd_pwm;
148
149void rx1950_lcd_power(int enable)
150{
151 int i;
152 static int enabled;
153 if (enabled == enable)
154 return;
155 if (!enable) {
156
157 /* GPC11-GPC15->OUTPUT */
158 for (i = 11; i < 16; i++)
159 gpio_direction_output(S3C2410_GPC(i), 1);
160
161 /* Wait a bit here... */
162 mdelay(100);
163
164 /* GPD2-GPD7->OUTPUT */
165 /* GPD11-GPD15->OUTPUT */
166 /* GPD2-GPD7->1, GPD11-GPD15->1 */
167 for (i = 2; i < 8; i++)
168 gpio_direction_output(S3C2410_GPD(i), 1);
169 for (i = 11; i < 16; i++)
170 gpio_direction_output(S3C2410_GPD(i), 1);
171
172 /* Wait a bit here...*/
173 mdelay(100);
174
175 /* GPB0->OUTPUT, GPB0->0 */
176 gpio_direction_output(S3C2410_GPB(0), 0);
177
178 /* GPC1-GPC4->OUTPUT, GPC1-4->0 */
179 for (i = 1; i < 5; i++)
180 gpio_direction_output(S3C2410_GPC(i), 0);
181
182 /* GPC15-GPC11->0 */
183 for (i = 11; i < 16; i++)
184 gpio_direction_output(S3C2410_GPC(i), 0);
185
186 /* GPD15-GPD11->0, GPD2->GPD7->0 */
187 for (i = 11; i < 16; i++)
188 gpio_direction_output(S3C2410_GPD(i), 0);
189
190 for (i = 2; i < 8; i++)
191 gpio_direction_output(S3C2410_GPD(i), 0);
192
193 /* GPC6->0, GPC7->0, GPC5->0 */
194 gpio_direction_output(S3C2410_GPC(6), 0);
195 gpio_direction_output(S3C2410_GPC(7), 0);
196 gpio_direction_output(S3C2410_GPC(5), 0);
197
198 /* GPB1->OUTPUT, GPB1->0 */
199 gpio_direction_output(S3C2410_GPB(1), 0);
200 pwm_config(lcd_pwm, 0, LCD_PWM_PERIOD);
201 pwm_disable(lcd_pwm);
202
203 /* GPC0->0, GPC10->0 */
204 gpio_direction_output(S3C2410_GPC(0), 0);
205 gpio_direction_output(S3C2410_GPC(10), 0);
206 } else {
207 pwm_config(lcd_pwm, LCD_PWM_DUTY, LCD_PWM_PERIOD);
208 pwm_enable(lcd_pwm);
209
210 gpio_direction_output(S3C2410_GPC(0), 1);
211 gpio_direction_output(S3C2410_GPC(5), 1);
212
213 s3c_gpio_cfgpin(S3C2410_GPB(1), S3C2410_GPB1_TOUT1);
214 gpio_direction_output(S3C2410_GPC(7), 1);
215
216 for (i = 1; i < 5; i++)
217 s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
218
219 for (i = 11; i < 16; i++)
220 s3c_gpio_cfgpin(S3C2410_GPC(i), S3C_GPIO_SFN(2));
221
222 for (i = 2; i < 8; i++)
223 s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
224
225 for (i = 11; i < 16; i++)
226 s3c_gpio_cfgpin(S3C2410_GPD(i), S3C_GPIO_SFN(2));
227
228 gpio_direction_output(S3C2410_GPC(10), 1);
229 gpio_direction_output(S3C2410_GPC(6), 1);
230 }
231 enabled = enable;
232}
233
234static void rx1950_bl_power(int enable)
235{
236 static int enabled;
237 if (enabled == enable)
238 return;
239 if (!enable) {
240 gpio_direction_output(S3C2410_GPB(0), 0);
241 } else {
242 /* LED driver need a "push" to power on */
243 gpio_direction_output(S3C2410_GPB(0), 1);
244 /* Warm up backlight for one period of PWM.
245 * Without this trick its almost impossible to
246 * enable backlight with low brightness value
247 */
248 ndelay(48000);
249 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPB0_TOUT0);
250 }
251 enabled = enable;
252}
253
254static int rx1950_backlight_init(struct device *dev)
255{
256 WARN_ON(gpio_request(S3C2410_GPB(0), "Backlight"));
257 lcd_pwm = pwm_request(1, "RX1950 LCD");
258 if (IS_ERR(lcd_pwm)) {
259 dev_err(dev, "Unable to request PWM for LCD power!\n");
260 return PTR_ERR(lcd_pwm);
261 }
262
263 rx1950_lcd_power(1);
264 rx1950_bl_power(1);
265
266 return 0;
267}
268
269static void rx1950_backlight_exit(struct device *dev)
270{
271 rx1950_bl_power(0);
272 rx1950_lcd_power(0);
273
274 pwm_free(lcd_pwm);
275 gpio_free(S3C2410_GPB(0));
276}
277
278
279static int rx1950_backlight_notify(struct device *dev, int brightness)
280{
281 if (!brightness) {
282 rx1950_bl_power(0);
283 rx1950_lcd_power(0);
284 } else {
285 rx1950_lcd_power(1);
286 rx1950_bl_power(1);
287 }
288 return brightness;
289}
290
291static struct platform_pwm_backlight_data rx1950_backlight_data = {
292 .pwm_id = 0,
293 .max_brightness = 24,
294 .dft_brightness = 4,
295 .pwm_period_ns = 48000,
296 .init = rx1950_backlight_init,
297 .notify = rx1950_backlight_notify,
298 .exit = rx1950_backlight_exit,
299};
300
301static struct platform_device rx1950_backlight = {
302 .name = "pwm-backlight",
303 .dev = {
304 .parent = &s3c_device_timer[0].dev,
305 .platform_data = &rx1950_backlight_data,
306 },
307};
308
309static void rx1950_set_mmc_power(unsigned char power_mode, unsigned short vdd)
310{
311 switch (power_mode) {
312 case MMC_POWER_OFF:
313 gpio_direction_output(S3C2410_GPJ(1), 0);
314 break;
315 case MMC_POWER_UP:
316 case MMC_POWER_ON:
317 gpio_direction_output(S3C2410_GPJ(1), 1);
318 break;
319 default:
320 break;
321 }
322}
323
324static struct s3c24xx_mci_pdata rx1950_mmc_cfg __initdata = {
325 .gpio_detect = S3C2410_GPF(5),
326 .gpio_wprotect = S3C2410_GPH(8),
327 .set_power = rx1950_set_mmc_power,
328 .ocr_avail = MMC_VDD_32_33,
329};
330
331static struct mtd_partition rx1950_nand_part[] = {
332 [0] = {
333 .name = "Boot0",
334 .offset = 0,
335 .size = 0x4000,
336 .mask_flags = MTD_WRITEABLE,
337 },
338 [1] = {
339 .name = "Boot1",
340 .offset = MTDPART_OFS_APPEND,
341 .size = 0x40000,
342 .mask_flags = MTD_WRITEABLE,
343 },
344 [2] = {
345 .name = "Kernel",
346 .offset = MTDPART_OFS_APPEND,
347 .size = 0x300000,
348 .mask_flags = 0,
349 },
350 [3] = {
351 .name = "Filesystem",
352 .offset = MTDPART_OFS_APPEND,
353 .size = MTDPART_SIZ_FULL,
354 .mask_flags = 0,
355 },
356};
357
358static struct s3c2410_nand_set rx1950_nand_sets[] = {
359 [0] = {
360 .name = "Internal",
361 .nr_chips = 1,
362 .nr_partitions = ARRAY_SIZE(rx1950_nand_part),
363 .partitions = rx1950_nand_part,
364 },
365};
366
367static struct s3c2410_platform_nand rx1950_nand_info = {
368 .tacls = 25,
369 .twrph0 = 50,
370 .twrph1 = 15,
371 .nr_sets = ARRAY_SIZE(rx1950_nand_sets),
372 .sets = rx1950_nand_sets,
373};
374
375static void rx1950_udc_pullup(enum s3c2410_udc_cmd_e cmd)
376{
377 switch (cmd) {
378 case S3C2410_UDC_P_ENABLE:
379 gpio_direction_output(S3C2410_GPJ(5), 1);
380 break;
381 case S3C2410_UDC_P_DISABLE:
382 gpio_direction_output(S3C2410_GPJ(5), 0);
383 break;
384 case S3C2410_UDC_P_RESET:
385 break;
386 default:
387 break;
388 }
389}
390
391static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {
392 .udc_command = rx1950_udc_pullup,
393 .vbus_pin = S3C2410_GPG(5),
394 .vbus_pin_inverted = 1,
395};
396
397static struct s3c2410_ts_mach_info rx1950_ts_cfg __initdata = {
398 .delay = 10000,
399 .presc = 49,
400 .oversampling_shift = 3,
401};
402
403static struct gpio_keys_button rx1950_gpio_keys_table[] = {
404 {
405 .code = KEY_POWER,
406 .gpio = S3C2410_GPF(0),
407 .active_low = 1,
408 .desc = "Power button",
409 .wakeup = 1,
410 },
411 {
412 .code = KEY_F5,
413 .gpio = S3C2410_GPF(7),
414 .active_low = 1,
415 .desc = "Record button",
416 },
417 {
418 .code = KEY_F1,
419 .gpio = S3C2410_GPG(0),
420 .active_low = 1,
421 .desc = "Calendar button",
422 },
423 {
424 .code = KEY_F2,
425 .gpio = S3C2410_GPG(2),
426 .active_low = 1,
427 .desc = "Contacts button",
428 },
429 {
430 .code = KEY_F3,
431 .gpio = S3C2410_GPG(3),
432 .active_low = 1,
433 .desc = "Mail button",
434 },
435 {
436 .code = KEY_F4,
437 .gpio = S3C2410_GPG(7),
438 .active_low = 1,
439 .desc = "WLAN button",
440 },
441 {
442 .code = KEY_LEFT,
443 .gpio = S3C2410_GPG(10),
444 .active_low = 1,
445 .desc = "Left button",
446 },
447 {
448 .code = KEY_RIGHT,
449 .gpio = S3C2410_GPG(11),
450 .active_low = 1,
451 .desc = "Right button",
452 },
453 {
454 .code = KEY_UP,
455 .gpio = S3C2410_GPG(4),
456 .active_low = 1,
457 .desc = "Up button",
458 },
459 {
460 .code = KEY_DOWN,
461 .gpio = S3C2410_GPG(6),
462 .active_low = 1,
463 .desc = "Down button",
464 },
465 {
466 .code = KEY_ENTER,
467 .gpio = S3C2410_GPG(9),
468 .active_low = 1,
469 .desc = "Ok button"
470 },
471};
472
473static struct gpio_keys_platform_data rx1950_gpio_keys_data = {
474 .buttons = rx1950_gpio_keys_table,
475 .nbuttons = ARRAY_SIZE(rx1950_gpio_keys_table),
476};
477
478static struct platform_device rx1950_device_gpiokeys = {
479 .name = "gpio-keys",
480 .dev.platform_data = &rx1950_gpio_keys_data,
481};
482
483static struct s3c2410_platform_i2c rx1950_i2c_data = {
484 .flags = 0,
485 .slave_addr = 0x42,
486 .frequency = 400 * 1000,
487 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
488};
489
490static struct platform_device *rx1950_devices[] __initdata = {
491 &s3c_device_lcd,
492 &s3c_device_wdt,
493 &s3c_device_i2c0,
494 &s3c_device_iis,
495 &s3c_device_usbgadget,
496 &s3c_device_rtc,
497 &s3c_device_nand,
498 &s3c_device_sdi,
499 &s3c_device_adc,
500 &s3c_device_ts,
501 &s3c_device_timer[0],
502 &s3c_device_timer[1],
503 &rx1950_backlight,
504 &rx1950_device_gpiokeys,
505};
506
507static struct clk *rx1950_clocks[] __initdata = {
508 &s3c24xx_clkout0,
509 &s3c24xx_clkout1,
510};
511
512static void __init rx1950_map_io(void)
513{
514 s3c24xx_clkout0.parent = &clk_h;
515 s3c24xx_clkout1.parent = &clk_f;
516
517 s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
518
519 s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
520 s3c24xx_init_clocks(16934000);
521 s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
522
523 /* setup PM */
524
525#ifdef CONFIG_PM_H1940
526 memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 8);
527#endif
528
529 s3c_pm_init();
530}
531
532static void __init rx1950_init_machine(void)
533{
534 int i;
535
536 s3c24xx_fb_set_platdata(&rx1950_lcd_cfg);
537 s3c24xx_udc_set_platdata(&rx1950_udc_cfg);
538 s3c24xx_ts_set_platdata(&rx1950_ts_cfg);
539 s3c24xx_mci_set_platdata(&rx1950_mmc_cfg);
540 s3c_i2c0_set_platdata(&rx1950_i2c_data);
541 s3c_nand_set_platdata(&rx1950_nand_info);
542
543 /* Turn off suspend on both USB ports, and switch the
544 * selectable USB port to USB device mode. */
545 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
546 S3C2410_MISCCR_USBSUSPND0 |
547 S3C2410_MISCCR_USBSUSPND1, 0x0);
548
549 WARN_ON(gpio_request(S3C2410_GPJ(5), "UDC pullup"));
550 gpio_direction_output(S3C2410_GPJ(5), 0);
551
552 /* mmc power is disabled by default */
553 WARN_ON(gpio_request(S3C2410_GPJ(1), "MMC power"));
554 gpio_direction_output(S3C2410_GPJ(1), 0);
555
556 for (i = 0; i < 8; i++)
557 WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
558
559 for (i = 10; i < 16; i++)
560 WARN_ON(gpio_request(S3C2410_GPC(i), "LCD power"));
561
562 for (i = 2; i < 8; i++)
563 WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
564
565 for (i = 11; i < 16; i++)
566 WARN_ON(gpio_request(S3C2410_GPD(i), "LCD power"));
567
568 WARN_ON(gpio_request(S3C2410_GPB(1), "LCD power"));
569
570 platform_add_devices(rx1950_devices, ARRAY_SIZE(rx1950_devices));
571}
572
573MACHINE_START(RX1950, "HP iPAQ RX1950")
574 /* Maintainers: Vasily Khoruzhick */
575 .phys_io = S3C2410_PA_UART,
576 .io_pg_offst = (((u32) S3C24XX_VA_UART) >> 18) & 0xfffc,
577 .boot_params = S3C2410_SDRAM_PA + 0x100,
578 .map_io = rx1950_map_io,
579 .init_irq = s3c24xx_init_irq,
580 .init_machine = rx1950_init_machine,
581 .timer = &s3c24xx_timer,
582MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 1e836e506f8b..d2946de3f365 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void)
209} 209}
210 210
211MACHINE_START(RX3715, "IPAQ-RX3715") 211MACHINE_START(RX3715, "IPAQ-RX3715")
212 /* Maintainer: Ben Dooks <ben@fluff.org> */ 212 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
213 .phys_io = S3C2410_PA_UART, 213 .phys_io = S3C2410_PA_UART,
214 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 214 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
215 .boot_params = S3C2410_SDRAM_PA + 0x100, 215 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index 3ac3d636d615..df83276d85ae 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void)
174} 174}
175 175
176MACHINE_START(S3C2440, "SMDK2440") 176MACHINE_START(S3C2440, "SMDK2440")
177 /* Maintainer: Ben Dooks <ben@fluff.org> */ 177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
178 .phys_io = S3C2410_PA_UART, 178 .phys_io = S3C2410_PA_UART,
179 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 179 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
180 .boot_params = S3C2410_SDRAM_PA + 0x100, 180 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index e2e362bda9b7..4c863d3a52f4 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void)
131} 131}
132 132
133MACHINE_START(SMDK2443, "SMDK2443") 133MACHINE_START(SMDK2443, "SMDK2443")
134 /* Maintainer: Ben Dooks <ben@fluff.org> */ 134 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
135 .phys_io = S3C2410_PA_UART, 135 .phys_io = S3C2410_PA_UART,
136 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, 136 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
137 .boot_params = S3C2410_SDRAM_PA + 0x100, 137 .boot_params = S3C2410_SDRAM_PA + 0x100,
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 2ac2e7d73e53..7a4138beb665 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -88,6 +88,12 @@ struct clk clk_48m = {
88 .enable = clk_48m_ctrl, 88 .enable = clk_48m_ctrl,
89}; 89};
90 90
91struct clk clk_xusbxti = {
92 .name = "xusbxti",
93 .id = -1,
94 .rate = 48000000,
95};
96
91static int inline s3c64xx_gate(void __iomem *reg, 97static int inline s3c64xx_gate(void __iomem *reg,
92 struct clk *clk, 98 struct clk *clk,
93 int enable) 99 int enable)
@@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = {
518 .id = -1, 524 .id = -1,
519}; 525};
520 526
527static struct clk clk_iisv4_cd = {
528 .name = "iis_cdclk_v4",
529 .id = -1,
530};
531
521static struct clk clk_pcm_cd = { 532static struct clk clk_pcm_cd = {
522 .name = "pcm_cdclk", 533 .name = "pcm_cdclk",
523 .id = -1, 534 .id = -1,
@@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = {
549 .nr_sources = ARRAY_SIZE(clkset_audio1_list), 560 .nr_sources = ARRAY_SIZE(clkset_audio1_list),
550}; 561};
551 562
563static struct clk *clkset_audio2_list[] = {
564 [0] = &clk_mout_epll.clk,
565 [1] = &clk_dout_mpll,
566 [2] = &clk_fin_epll,
567 [3] = &clk_iisv4_cd,
568 [4] = &clk_pcm_cd,
569};
570
571static struct clksrc_sources clkset_audio2 = {
572 .sources = clkset_audio2_list,
573 .nr_sources = ARRAY_SIZE(clkset_audio2_list),
574};
575
552static struct clk *clkset_camif_list[] = { 576static struct clk *clkset_camif_list[] = {
553 &clk_h2, 577 &clk_h2,
554}; 578};
@@ -652,6 +676,16 @@ static struct clksrc_clk clksrcs[] = {
652 .sources = &clkset_audio1, 676 .sources = &clkset_audio1,
653 }, { 677 }, {
654 .clk = { 678 .clk = {
679 .name = "audio-bus",
680 .id = -1, /* There's only one IISv4 port */
681 .ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
682 .enable = s3c64xx_sclk_ctrl,
683 },
684 .reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
685 .reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
686 .sources = &clkset_audio2,
687 }, {
688 .clk = {
655 .name = "irda-bus", 689 .name = "irda-bus",
656 .id = 0, 690 .id = 0,
657 .ctrlbit = S3C_CLKCON_SCLK_IRDA, 691 .ctrlbit = S3C_CLKCON_SCLK_IRDA,
@@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = {
749 &clk_ext_xtal_mux, 783 &clk_ext_xtal_mux,
750 &clk_iis_cd0, 784 &clk_iis_cd0,
751 &clk_iis_cd1, 785 &clk_iis_cd1,
786 &clk_iisv4_cd,
752 &clk_pcm_cd, 787 &clk_pcm_cd,
753 &clk_mout_epll.clk, 788 &clk_mout_epll.clk,
754 &clk_mout_mpll.clk, 789 &clk_mout_mpll.clk,
@@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = {
762 &clk_27m, 797 &clk_27m,
763 &clk_48m, 798 &clk_48m,
764 &clk_h2, 799 &clk_h2,
800 &clk_xusbxti,
765}; 801};
766 802
767/** 803/**
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 33ccf7bf766a..5567e037b0d1 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -414,7 +414,7 @@ err_buff:
414EXPORT_SYMBOL(s3c2410_dma_enqueue); 414EXPORT_SYMBOL(s3c2410_dma_enqueue);
415 415
416 416
417int s3c2410_dma_devconfig(int channel, 417int s3c2410_dma_devconfig(unsigned int channel,
418 enum s3c2410_dmasrc source, 418 enum s3c2410_dmasrc source,
419 unsigned long devaddr) 419 unsigned long devaddr)
420{ 420{
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index 3ef62741e5d1..0114eb0c1fe7 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -33,6 +33,7 @@
33#define S3C_PCLK_GATE S3C_CLKREG(0x34) 33#define S3C_PCLK_GATE S3C_CLKREG(0x34)
34#define S3C_SCLK_GATE S3C_CLKREG(0x38) 34#define S3C_SCLK_GATE S3C_CLKREG(0x38)
35#define S3C_MEM0_GATE S3C_CLKREG(0x3C) 35#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
36#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
36 37
37/* CLKDIV0 */ 38/* CLKDIV0 */
38#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) 39#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index f7b18983950c..59916676d8d2 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void)
84} 84}
85 85
86MACHINE_START(SMDK6400, "SMDK6400") 86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben@fluff.org> */ 87 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
88 .phys_io = S3C_PA_UART & 0xfff00000, 88 .phys_io = S3C_PA_UART & 0xfff00000,
89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, 89 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
90 .boot_params = S3C64XX_PA_SDRAM + 0x100, 90 .boot_params = S3C64XX_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 2d5afd221d77..9d51455feb31 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void)
656} 656}
657 657
658MACHINE_START(SMDK6410, "SMDK6410") 658MACHINE_START(SMDK6410, "SMDK6410")
659 /* Maintainer: Ben Dooks <ben@fluff.org> */ 659 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
660 .phys_io = S3C_PA_UART & 0xfff00000, 660 .phys_io = S3C_PA_UART & 0xfff00000,
661 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, 661 .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
662 .boot_params = S3C64XX_PA_SDRAM + 0x100, 662 .boot_params = S3C64XX_PA_SDRAM + 0x100,
diff --git a/arch/arm/mach-s5p6440/clock.c b/arch/arm/mach-s5p6440/clock.c
index b2672e16e7aa..ca6e48dce777 100644
--- a/arch/arm/mach-s5p6440/clock.c
+++ b/arch/arm/mach-s5p6440/clock.c
@@ -134,24 +134,6 @@ static struct clksrc_clk clk_mout_mpll = {
134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 }, 134 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 1, .size = 1 },
135}; 135};
136 136
137static struct clk clk_h_low = {
138 .name = "hclk_low",
139 .id = -1,
140 .rate = 0,
141 .parent = NULL,
142 .ctrlbit = 0,
143 .ops = &clk_ops_def_setrate,
144};
145
146static struct clk clk_p_low = {
147 .name = "pclk_low",
148 .id = -1,
149 .rate = 0,
150 .parent = NULL,
151 .ctrlbit = 0,
152 .ops = &clk_ops_def_setrate,
153};
154
155enum perf_level { 137enum perf_level {
156 L0 = 532*1000, 138 L0 = 532*1000,
157 L1 = 266*1000, 139 L1 = 266*1000,
@@ -247,23 +229,70 @@ static struct clk_ops s5p6440_clkarm_ops = {
247 .round_rate = s5p6440_armclk_round_rate, 229 .round_rate = s5p6440_armclk_round_rate,
248}; 230};
249 231
250static unsigned long s5p6440_clk_doutmpll_get_rate(struct clk *clk) 232static struct clksrc_clk clk_armclk = {
251{ 233 .clk = {
252 unsigned long rate = clk_get_rate(clk->parent); 234 .name = "armclk",
235 .id = 1,
236 .parent = &clk_mout_apll.clk,
237 .ops = &s5p6440_clkarm_ops,
238 },
239 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 4 },
240};
253 241
254 if (__raw_readl(S5P_CLK_DIV0) & S5P_CLKDIV0_MPLL_MASK) 242static struct clksrc_clk clk_dout_mpll = {
255 rate /= 2; 243 .clk = {
244 .name = "dout_mpll",
245 .id = -1,
246 .parent = &clk_mout_mpll.clk,
247 },
248 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 1 },
249};
256 250
257 return rate; 251static struct clksrc_clk clk_hclk = {
258} 252 .clk = {
253 .name = "clk_hclk",
254 .id = -1,
255 .parent = &clk_armclk.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 4 },
258};
259 259
260static struct clk clk_dout_mpll = { 260static struct clksrc_clk clk_pclk = {
261 .name = "dout_mpll", 261 .clk = {
262 .id = -1, 262 .name = "clk_pclk",
263 .parent = &clk_mout_mpll.clk, 263 .id = -1,
264 .ops = &(struct clk_ops) { 264 .parent = &clk_hclk.clk,
265 .get_rate = s5p6440_clk_doutmpll_get_rate,
266 }, 265 },
266 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 4 },
267};
268
269static struct clk *clkset_hclklow_list[] = {
270 &clk_mout_apll.clk,
271 &clk_mout_mpll.clk,
272};
273
274static struct clksrc_sources clkset_hclklow = {
275 .sources = clkset_hclklow_list,
276 .nr_sources = ARRAY_SIZE(clkset_hclklow_list),
277};
278
279static struct clksrc_clk clk_hclk_low = {
280 .clk = {
281 .name = "hclk_low",
282 .id = -1,
283 },
284 .sources = &clkset_hclklow,
285 .reg_src = { .reg = S5P_SYS_OTHERS, .shift = 6, .size = 1 },
286 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
287};
288
289static struct clksrc_clk clk_pclk_low = {
290 .clk = {
291 .name = "pclk_low",
292 .id = -1,
293 .parent = &clk_hclk_low.clk,
294 },
295 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
267}; 296};
268 297
269int s5p6440_clk48m_ctrl(struct clk *clk, int enable) 298int s5p6440_clk48m_ctrl(struct clk *clk, int enable)
@@ -307,6 +336,11 @@ static int s5p6440_sclk_ctrl(struct clk *clk, int enable)
307 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable); 336 return s5p_gatectrl(S5P_CLK_GATE_SCLK0, clk, enable);
308} 337}
309 338
339static int s5p6440_sclk1_ctrl(struct clk *clk, int enable)
340{
341 return s5p_gatectrl(S5P_CLK_GATE_SCLK1, clk, enable);
342}
343
310static int s5p6440_mem_ctrl(struct clk *clk, int enable) 344static int s5p6440_mem_ctrl(struct clk *clk, int enable)
311{ 345{
312 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable); 346 return s5p_gatectrl(S5P_CLK_GATE_MEM0, clk, enable);
@@ -321,37 +355,37 @@ static struct clk init_clocks_disable[] = {
321 { 355 {
322 .name = "nand", 356 .name = "nand",
323 .id = -1, 357 .id = -1,
324 .parent = &clk_h, 358 .parent = &clk_hclk.clk,
325 .enable = s5p6440_mem_ctrl, 359 .enable = s5p6440_mem_ctrl,
326 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON, 360 .ctrlbit = S5P_CLKCON_MEM0_HCLK_NFCON,
327 }, { 361 }, {
328 .name = "adc", 362 .name = "adc",
329 .id = -1, 363 .id = -1,
330 .parent = &clk_p_low, 364 .parent = &clk_pclk_low.clk,
331 .enable = s5p6440_pclk_ctrl, 365 .enable = s5p6440_pclk_ctrl,
332 .ctrlbit = S5P_CLKCON_PCLK_TSADC, 366 .ctrlbit = S5P_CLKCON_PCLK_TSADC,
333 }, { 367 }, {
334 .name = "i2c", 368 .name = "i2c",
335 .id = -1, 369 .id = -1,
336 .parent = &clk_p_low, 370 .parent = &clk_pclk_low.clk,
337 .enable = s5p6440_pclk_ctrl, 371 .enable = s5p6440_pclk_ctrl,
338 .ctrlbit = S5P_CLKCON_PCLK_IIC0, 372 .ctrlbit = S5P_CLKCON_PCLK_IIC0,
339 }, { 373 }, {
340 .name = "i2s_v40", 374 .name = "i2s_v40",
341 .id = 0, 375 .id = 0,
342 .parent = &clk_p_low, 376 .parent = &clk_pclk_low.clk,
343 .enable = s5p6440_pclk_ctrl, 377 .enable = s5p6440_pclk_ctrl,
344 .ctrlbit = S5P_CLKCON_PCLK_IIS2, 378 .ctrlbit = S5P_CLKCON_PCLK_IIS2,
345 }, { 379 }, {
346 .name = "spi", 380 .name = "spi",
347 .id = 0, 381 .id = 0,
348 .parent = &clk_p_low, 382 .parent = &clk_pclk_low.clk,
349 .enable = s5p6440_pclk_ctrl, 383 .enable = s5p6440_pclk_ctrl,
350 .ctrlbit = S5P_CLKCON_PCLK_SPI0, 384 .ctrlbit = S5P_CLKCON_PCLK_SPI0,
351 }, { 385 }, {
352 .name = "spi", 386 .name = "spi",
353 .id = 1, 387 .id = 1,
354 .parent = &clk_p_low, 388 .parent = &clk_pclk_low.clk,
355 .enable = s5p6440_pclk_ctrl, 389 .enable = s5p6440_pclk_ctrl,
356 .ctrlbit = S5P_CLKCON_PCLK_SPI1, 390 .ctrlbit = S5P_CLKCON_PCLK_SPI1,
357 }, { 391 }, {
@@ -387,58 +421,124 @@ static struct clk init_clocks_disable[] = {
387 }, { 421 }, {
388 .name = "otg", 422 .name = "otg",
389 .id = -1, 423 .id = -1,
390 .parent = &clk_h_low, 424 .parent = &clk_hclk_low.clk,
391 .enable = s5p6440_hclk0_ctrl, 425 .enable = s5p6440_hclk0_ctrl,
392 .ctrlbit = S5P_CLKCON_HCLK0_USB 426 .ctrlbit = S5P_CLKCON_HCLK0_USB
393 }, { 427 }, {
394 .name = "post", 428 .name = "post",
395 .id = -1, 429 .id = -1,
396 .parent = &clk_h_low, 430 .parent = &clk_hclk_low.clk,
397 .enable = s5p6440_hclk0_ctrl, 431 .enable = s5p6440_hclk0_ctrl,
398 .ctrlbit = S5P_CLKCON_HCLK0_POST0 432 .ctrlbit = S5P_CLKCON_HCLK0_POST0
399 }, { 433 }, {
400 .name = "lcd", 434 .name = "lcd",
401 .id = -1, 435 .id = -1,
402 .parent = &clk_h_low, 436 .parent = &clk_hclk_low.clk,
403 .enable = s5p6440_hclk1_ctrl, 437 .enable = s5p6440_hclk1_ctrl,
404 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON, 438 .ctrlbit = S5P_CLKCON_HCLK1_DISPCON,
405 }, { 439 }, {
406 .name = "hsmmc", 440 .name = "hsmmc",
407 .id = 0, 441 .id = 0,
408 .parent = &clk_h_low, 442 .parent = &clk_hclk_low.clk,
409 .enable = s5p6440_hclk0_ctrl, 443 .enable = s5p6440_hclk0_ctrl,
410 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0, 444 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC0,
411 }, { 445 }, {
412 .name = "hsmmc", 446 .name = "hsmmc",
413 .id = 1, 447 .id = 1,
414 .parent = &clk_h_low, 448 .parent = &clk_hclk_low.clk,
415 .enable = s5p6440_hclk0_ctrl, 449 .enable = s5p6440_hclk0_ctrl,
416 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1, 450 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC1,
417 }, { 451 }, {
418 .name = "hsmmc", 452 .name = "hsmmc",
419 .id = 2, 453 .id = 2,
420 .parent = &clk_h_low, 454 .parent = &clk_hclk_low.clk,
421 .enable = s5p6440_hclk0_ctrl, 455 .enable = s5p6440_hclk0_ctrl,
422 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2, 456 .ctrlbit = S5P_CLKCON_HCLK0_HSMMC2,
423 }, { 457 }, {
424 .name = "rtc", 458 .name = "rtc",
425 .id = -1, 459 .id = -1,
426 .parent = &clk_p_low, 460 .parent = &clk_pclk_low.clk,
427 .enable = s5p6440_pclk_ctrl, 461 .enable = s5p6440_pclk_ctrl,
428 .ctrlbit = S5P_CLKCON_PCLK_RTC, 462 .ctrlbit = S5P_CLKCON_PCLK_RTC,
429 }, { 463 }, {
430 .name = "watchdog", 464 .name = "watchdog",
431 .id = -1, 465 .id = -1,
432 .parent = &clk_p_low, 466 .parent = &clk_pclk_low.clk,
433 .enable = s5p6440_pclk_ctrl, 467 .enable = s5p6440_pclk_ctrl,
434 .ctrlbit = S5P_CLKCON_PCLK_WDT, 468 .ctrlbit = S5P_CLKCON_PCLK_WDT,
435 }, { 469 }, {
436 .name = "timers", 470 .name = "timers",
437 .id = -1, 471 .id = -1,
438 .parent = &clk_p_low, 472 .parent = &clk_pclk_low.clk,
439 .enable = s5p6440_pclk_ctrl, 473 .enable = s5p6440_pclk_ctrl,
440 .ctrlbit = S5P_CLKCON_PCLK_PWM, 474 .ctrlbit = S5P_CLKCON_PCLK_PWM,
441 } 475 }, {
476 .name = "hclk_fimgvg",
477 .id = -1,
478 .parent = &clk_hclk.clk,
479 .enable = s5p6440_hclk1_ctrl,
480 .ctrlbit = (1 << 2),
481 }, {
482 .name = "tsi",
483 .id = -1,
484 .parent = &clk_hclk_low.clk,
485 .enable = s5p6440_hclk1_ctrl,
486 .ctrlbit = (1 << 0),
487 }, {
488 .name = "pclk_fimgvg",
489 .id = -1,
490 .parent = &clk_pclk.clk,
491 .enable = s5p6440_pclk_ctrl,
492 .ctrlbit = (1 << 31),
493 }, {
494 .name = "dmc0",
495 .id = -1,
496 .parent = &clk_pclk.clk,
497 .enable = s5p6440_pclk_ctrl,
498 .ctrlbit = (1 << 30),
499 }, {
500 .name = "etm",
501 .id = -1,
502 .parent = &clk_pclk.clk,
503 .enable = s5p6440_pclk_ctrl,
504 .ctrlbit = (1 << 29),
505 }, {
506 .name = "dsim",
507 .id = -1,
508 .parent = &clk_pclk_low.clk,
509 .enable = s5p6440_pclk_ctrl,
510 .ctrlbit = (1 << 28),
511 }, {
512 .name = "gps",
513 .id = -1,
514 .parent = &clk_pclk_low.clk,
515 .enable = s5p6440_pclk_ctrl,
516 .ctrlbit = (1 << 25),
517 }, {
518 .name = "pcm",
519 .id = -1,
520 .parent = &clk_pclk_low.clk,
521 .enable = s5p6440_pclk_ctrl,
522 .ctrlbit = (1 << 8),
523 }, {
524 .name = "irom",
525 .id = -1,
526 .parent = &clk_hclk.clk,
527 .enable = s5p6440_hclk0_ctrl,
528 .ctrlbit = (1 << 25),
529 }, {
530 .name = "dma",
531 .id = -1,
532 .parent = &clk_hclk_low.clk,
533 .enable = s5p6440_hclk0_ctrl,
534 .ctrlbit = (1 << 12),
535 }, {
536 .name = "2d",
537 .id = -1,
538 .parent = &clk_hclk.clk,
539 .enable = s5p6440_hclk0_ctrl,
540 .ctrlbit = (1 << 8),
541 },
442}; 542};
443 543
444/* 544/*
@@ -448,34 +548,46 @@ static struct clk init_clocks[] = {
448 { 548 {
449 .name = "gpio", 549 .name = "gpio",
450 .id = -1, 550 .id = -1,
451 .parent = &clk_p_low, 551 .parent = &clk_pclk_low.clk,
452 .enable = s5p6440_pclk_ctrl, 552 .enable = s5p6440_pclk_ctrl,
453 .ctrlbit = S5P_CLKCON_PCLK_GPIO, 553 .ctrlbit = S5P_CLKCON_PCLK_GPIO,
454 }, { 554 }, {
455 .name = "uart", 555 .name = "uart",
456 .id = 0, 556 .id = 0,
457 .parent = &clk_p_low, 557 .parent = &clk_pclk_low.clk,
458 .enable = s5p6440_pclk_ctrl, 558 .enable = s5p6440_pclk_ctrl,
459 .ctrlbit = S5P_CLKCON_PCLK_UART0, 559 .ctrlbit = S5P_CLKCON_PCLK_UART0,
460 }, { 560 }, {
461 .name = "uart", 561 .name = "uart",
462 .id = 1, 562 .id = 1,
463 .parent = &clk_p_low, 563 .parent = &clk_pclk_low.clk,
464 .enable = s5p6440_pclk_ctrl, 564 .enable = s5p6440_pclk_ctrl,
465 .ctrlbit = S5P_CLKCON_PCLK_UART1, 565 .ctrlbit = S5P_CLKCON_PCLK_UART1,
466 }, { 566 }, {
467 .name = "uart", 567 .name = "uart",
468 .id = 2, 568 .id = 2,
469 .parent = &clk_p_low, 569 .parent = &clk_pclk_low.clk,
470 .enable = s5p6440_pclk_ctrl, 570 .enable = s5p6440_pclk_ctrl,
471 .ctrlbit = S5P_CLKCON_PCLK_UART2, 571 .ctrlbit = S5P_CLKCON_PCLK_UART2,
472 }, { 572 }, {
473 .name = "uart", 573 .name = "uart",
474 .id = 3, 574 .id = 3,
475 .parent = &clk_p_low, 575 .parent = &clk_pclk_low.clk,
476 .enable = s5p6440_pclk_ctrl, 576 .enable = s5p6440_pclk_ctrl,
477 .ctrlbit = S5P_CLKCON_PCLK_UART3, 577 .ctrlbit = S5P_CLKCON_PCLK_UART3,
478 } 578 }, {
579 .name = "mem",
580 .id = -1,
581 .parent = &clk_hclk.clk,
582 .enable = s5p6440_hclk0_ctrl,
583 .ctrlbit = (1 << 21),
584 }, {
585 .name = "intc",
586 .id = -1,
587 .parent = &clk_hclk.clk,
588 .enable = s5p6440_hclk0_ctrl,
589 .ctrlbit = (1 << 1),
590 },
479}; 591};
480 592
481static struct clk clk_iis_cd_v40 = { 593static struct clk clk_iis_cd_v40 = {
@@ -488,20 +600,20 @@ static struct clk clk_pcm_cd = {
488 .id = -1, 600 .id = -1,
489}; 601};
490 602
491static struct clk *clkset_spi_mmc_list[] = { 603static struct clk *clkset_group1_list[] = {
492 &clk_mout_epll.clk, 604 &clk_mout_epll.clk,
493 &clk_dout_mpll, 605 &clk_dout_mpll.clk,
494 &clk_fin_epll, 606 &clk_fin_epll,
495}; 607};
496 608
497static struct clksrc_sources clkset_spi_mmc = { 609static struct clksrc_sources clkset_group1 = {
498 .sources = clkset_spi_mmc_list, 610 .sources = clkset_group1_list,
499 .nr_sources = ARRAY_SIZE(clkset_spi_mmc_list), 611 .nr_sources = ARRAY_SIZE(clkset_group1_list),
500}; 612};
501 613
502static struct clk *clkset_uart_list[] = { 614static struct clk *clkset_uart_list[] = {
503 &clk_mout_epll.clk, 615 &clk_mout_epll.clk,
504 &clk_dout_mpll 616 &clk_dout_mpll.clk,
505}; 617};
506 618
507static struct clksrc_sources clkset_uart = { 619static struct clksrc_sources clkset_uart = {
@@ -509,6 +621,19 @@ static struct clksrc_sources clkset_uart = {
509 .nr_sources = ARRAY_SIZE(clkset_uart_list), 621 .nr_sources = ARRAY_SIZE(clkset_uart_list),
510}; 622};
511 623
624static struct clk *clkset_audio_list[] = {
625 &clk_mout_epll.clk,
626 &clk_dout_mpll.clk,
627 &clk_fin_epll,
628 &clk_iis_cd_v40,
629 &clk_pcm_cd,
630};
631
632static struct clksrc_sources clkset_audio = {
633 .sources = clkset_audio_list,
634 .nr_sources = ARRAY_SIZE(clkset_audio_list),
635};
636
512static struct clksrc_clk clksrcs[] = { 637static struct clksrc_clk clksrcs[] = {
513 { 638 {
514 .clk = { 639 .clk = {
@@ -517,7 +642,7 @@ static struct clksrc_clk clksrcs[] = {
517 .ctrlbit = S5P_CLKCON_SCLK0_MMC0, 642 .ctrlbit = S5P_CLKCON_SCLK0_MMC0,
518 .enable = s5p6440_sclk_ctrl, 643 .enable = s5p6440_sclk_ctrl,
519 }, 644 },
520 .sources = &clkset_spi_mmc, 645 .sources = &clkset_group1,
521 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 }, 646 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 18, .size = 2 },
522 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 }, 647 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4 },
523 }, { 648 }, {
@@ -527,7 +652,7 @@ static struct clksrc_clk clksrcs[] = {
527 .ctrlbit = S5P_CLKCON_SCLK0_MMC1, 652 .ctrlbit = S5P_CLKCON_SCLK0_MMC1,
528 .enable = s5p6440_sclk_ctrl, 653 .enable = s5p6440_sclk_ctrl,
529 }, 654 },
530 .sources = &clkset_spi_mmc, 655 .sources = &clkset_group1,
531 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 }, 656 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 2 },
532 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 }, 657 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 4 },
533 }, { 658 }, {
@@ -537,7 +662,7 @@ static struct clksrc_clk clksrcs[] = {
537 .ctrlbit = S5P_CLKCON_SCLK0_MMC2, 662 .ctrlbit = S5P_CLKCON_SCLK0_MMC2,
538 .enable = s5p6440_sclk_ctrl, 663 .enable = s5p6440_sclk_ctrl,
539 }, 664 },
540 .sources = &clkset_spi_mmc, 665 .sources = &clkset_group1,
541 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 }, 666 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 22, .size = 2 },
542 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 }, 667 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 4 },
543 }, { 668 }, {
@@ -557,7 +682,7 @@ static struct clksrc_clk clksrcs[] = {
557 .ctrlbit = S5P_CLKCON_SCLK0_SPI0, 682 .ctrlbit = S5P_CLKCON_SCLK0_SPI0,
558 .enable = s5p6440_sclk_ctrl, 683 .enable = s5p6440_sclk_ctrl,
559 }, 684 },
560 .sources = &clkset_spi_mmc, 685 .sources = &clkset_group1,
561 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 }, 686 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 14, .size = 2 },
562 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, 687 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
563 }, { 688 }, {
@@ -567,17 +692,63 @@ static struct clksrc_clk clksrcs[] = {
567 .ctrlbit = S5P_CLKCON_SCLK0_SPI1, 692 .ctrlbit = S5P_CLKCON_SCLK0_SPI1,
568 .enable = s5p6440_sclk_ctrl, 693 .enable = s5p6440_sclk_ctrl,
569 }, 694 },
570 .sources = &clkset_spi_mmc, 695 .sources = &clkset_group1,
571 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 }, 696 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 2 },
572 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, 697 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
573 } 698 }, {
699 .clk = {
700 .name = "sclk_post",
701 .id = -1,
702 .ctrlbit = (1 << 10),
703 .enable = s5p6440_sclk_ctrl,
704 },
705 .sources = &clkset_group1,
706 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 26, .size = 2 },
707 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
708 }, {
709 .clk = {
710 .name = "sclk_dispcon",
711 .id = -1,
712 .ctrlbit = (1 << 1),
713 .enable = s5p6440_sclk1_ctrl,
714 },
715 .sources = &clkset_group1,
716 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
717 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
718 }, {
719 .clk = {
720 .name = "sclk_fimgvg",
721 .id = -1,
722 .ctrlbit = (1 << 2),
723 .enable = s5p6440_sclk1_ctrl,
724 },
725 .sources = &clkset_group1,
726 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
727 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
728 }, {
729 .clk = {
730 .name = "sclk_audio2",
731 .id = -1,
732 .ctrlbit = (1 << 11),
733 .enable = s5p6440_sclk_ctrl,
734 },
735 .sources = &clkset_audio,
736 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 3 },
737 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 24, .size = 4 },
738 },
574}; 739};
575 740
576/* Clock initialisation code */ 741/* Clock initialisation code */
577static struct clksrc_clk *init_parents[] = { 742static struct clksrc_clk *sysclks[] = {
578 &clk_mout_apll, 743 &clk_mout_apll,
579 &clk_mout_epll, 744 &clk_mout_epll,
580 &clk_mout_mpll, 745 &clk_mout_mpll,
746 &clk_dout_mpll,
747 &clk_armclk,
748 &clk_hclk,
749 &clk_pclk,
750 &clk_hclk_low,
751 &clk_pclk_low,
581}; 752};
582 753
583void __init_or_cpufreq s5p6440_setup_clocks(void) 754void __init_or_cpufreq s5p6440_setup_clocks(void)
@@ -593,21 +764,13 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
593 unsigned long apll; 764 unsigned long apll;
594 unsigned long mpll; 765 unsigned long mpll;
595 unsigned int ptr; 766 unsigned int ptr;
596 u32 clkdiv0;
597 u32 clkdiv3;
598 767
599 /* Set S5P6440 functions for clk_fout_epll */ 768 /* Set S5P6440 functions for clk_fout_epll */
600 clk_fout_epll.enable = s5p6440_epll_enable; 769 clk_fout_epll.enable = s5p6440_epll_enable;
601 clk_fout_epll.ops = &s5p6440_epll_ops; 770 clk_fout_epll.ops = &s5p6440_epll_ops;
602 771
603 /* Set S5P6440 functions for arm clock */
604 clk_arm.parent = &clk_mout_apll.clk;
605 clk_arm.ops = &s5p6440_clkarm_ops;
606 clk_48m.enable = s5p6440_clk48m_ctrl; 772 clk_48m.enable = s5p6440_clk48m_ctrl;
607 773
608 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
609 clkdiv3 = __raw_readl(S5P_CLK_DIV3);
610
611 xtal_clk = clk_get(NULL, "ext_xtal"); 774 xtal_clk = clk_get(NULL, "ext_xtal");
612 BUG_ON(IS_ERR(xtal_clk)); 775 BUG_ON(IS_ERR(xtal_clk));
613 776
@@ -619,41 +782,28 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
619 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 782 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
620 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502); 783 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);
621 784
785 clk_fout_mpll.rate = mpll;
786 clk_fout_epll.rate = epll;
787 clk_fout_apll.rate = apll;
788
622 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ 789 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
623 " E=%ld.%ldMHz\n", 790 " E=%ld.%ldMHz\n",
624 print_mhz(apll), print_mhz(mpll), print_mhz(epll)); 791 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
625 792
626 fclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_ARM); 793 fclk = clk_get_rate(&clk_armclk.clk);
627 hclk = fclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK); 794 hclk = clk_get_rate(&clk_hclk.clk);
628 pclk = hclk / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK); 795 pclk = clk_get_rate(&clk_pclk.clk);
629 796 hclk_low = clk_get_rate(&clk_hclk_low.clk);
630 if (__raw_readl(S5P_OTHERS) & S5P_OTHERS_HCLK_LOW_SEL_MPLL) { 797 pclk_low = clk_get_rate(&clk_pclk_low.clk);
631 /* Asynchronous mode */
632 hclk_low = mpll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
633 } else {
634 /* Synchronous mode */
635 hclk_low = apll / GET_DIV(clkdiv3, S5P_CLKDIV3_HCLK_LOW);
636 }
637
638 pclk_low = hclk_low / GET_DIV(clkdiv3, S5P_CLKDIV3_PCLK_LOW);
639 798
640 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ 799 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
641 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", 800 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
642 print_mhz(hclk), print_mhz(hclk_low), 801 print_mhz(hclk), print_mhz(hclk_low),
643 print_mhz(pclk), print_mhz(pclk_low)); 802 print_mhz(pclk), print_mhz(pclk_low));
644 803
645 clk_fout_mpll.rate = mpll;
646 clk_fout_epll.rate = epll;
647 clk_fout_apll.rate = apll;
648
649 clk_f.rate = fclk; 804 clk_f.rate = fclk;
650 clk_h.rate = hclk; 805 clk_h.rate = hclk;
651 clk_p.rate = pclk; 806 clk_p.rate = pclk;
652 clk_h_low.rate = hclk_low;
653 clk_p_low.rate = pclk_low;
654
655 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
656 s3c_set_clksrc(init_parents[ptr], true);
657 807
658 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 808 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
659 s3c_set_clksrc(&clksrcs[ptr], true); 809 s3c_set_clksrc(&clksrcs[ptr], true);
@@ -661,13 +811,8 @@ void __init_or_cpufreq s5p6440_setup_clocks(void)
661 811
662static struct clk *clks[] __initdata = { 812static struct clk *clks[] __initdata = {
663 &clk_ext, 813 &clk_ext,
664 &clk_mout_epll.clk,
665 &clk_mout_mpll.clk,
666 &clk_dout_mpll,
667 &clk_iis_cd_v40, 814 &clk_iis_cd_v40,
668 &clk_pcm_cd, 815 &clk_pcm_cd,
669 &clk_p_low,
670 &clk_h_low,
671}; 816};
672 817
673void __init s5p6440_register_clocks(void) 818void __init s5p6440_register_clocks(void)
@@ -680,6 +825,9 @@ void __init s5p6440_register_clocks(void)
680 if (ret > 0) 825 if (ret > 0)
681 printk(KERN_ERR "Failed to register %u clocks\n", ret); 826 printk(KERN_ERR "Failed to register %u clocks\n", ret);
682 827
828 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
829 s3c_register_clksrc(sysclks[ptr], 1);
830
683 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 831 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
684 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 832 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
685 833
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
index 1794131aeacb..ca3b3206e6f8 100644
--- a/arch/arm/mach-s5p6440/cpu.c
+++ b/arch/arm/mach-s5p6440/cpu.c
@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void)
88 s5p_init_irq(vic, ARRAY_SIZE(vic)); 88 s5p_init_irq(vic, ARRAY_SIZE(vic));
89} 89}
90 90
91static struct sysdev_class s5p6440_sysclass = { 91struct sysdev_class s5p6440_sysclass = {
92 .name = "s5p6440-core", 92 .name = "s5p6440-core",
93}; 93};
94 94
diff --git a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
index c4bb7c555477..6a2a02fdf12a 100644
--- a/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
@@ -1,11 +1,14 @@
1/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 8 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/ 9 * http://armlinux.simtec.co.uk/
6 * 10 *
7 * Copyright 2009 Samsung Electronics Co., Ltd. 11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
8 * http://www.samsung.com/
9 * 12 *
10 * S5P6440 - pwm clock and timer support 13 * S5P6440 - pwm clock and timer support
11 * 14 *
@@ -14,16 +17,19 @@
14 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
15*/ 18*/
16 19
20#ifndef __ASM_ARCH_PWMCLK_H
21#define __ASM_ARCH_PWMCLK_H __FILE__
22
17/** 23/**
18 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk 24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
19 * @cfg: The timer TCFG1 register bits shifted down to 0. 25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
20 * 26 *
21 * Return true if the given configuration from TCFG1 is a TCLK instead 27 * Return true if the given configuration from TCFG1 is a TCLK instead
22 * any of the TDIV clocks. 28 * any of the TDIV clocks.
23 */ 29 */
24static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) 30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
25{ 31{
26 return tcfg == S3C2410_TCFG1_MUX_TCLK; 32 return 0;
27} 33}
28 34
29/** 35/**
@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
35 */ 41 */
36static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) 42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
37{ 43{
38 return 1 << (1 + tcfg1); 44 return 1 << tcfg1;
39} 45}
40 46
41/** 47/**
@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
45 */ 51 */
46static inline unsigned int pwm_tdiv_has_div1(void) 52static inline unsigned int pwm_tdiv_has_div1(void)
47{ 53{
48 return 0; 54 return 1;
49} 55}
50 56
51/** 57/**
@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
56 */ 62 */
57static inline unsigned long pwm_tdiv_div_bits(unsigned int div) 63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
58{ 64{
59 return ilog2(div) - 1; 65 return ilog2(div);
60} 66}
61 67
62#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK 68#define S3C_TCFG1_MUX_TCLK 0
69
70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5p6442/cpu.c b/arch/arm/mach-s5p6442/cpu.c
index bc2524df89b3..a48fb553fd01 100644
--- a/arch/arm/mach-s5p6442/cpu.c
+++ b/arch/arm/mach-s5p6442/cpu.c
@@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void)
95 s5p_init_irq(vic, ARRAY_SIZE(vic)); 95 s5p_init_irq(vic, ARRAY_SIZE(vic));
96} 96}
97 97
98static struct sysdev_class s5p6442_sysclass = { 98struct sysdev_class s5p6442_sysclass = {
99 .name = "s5p6442-core", 99 .name = "s5p6442-core",
100}; 100};
101 101
diff --git a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
index 15e8525da0f1..2724b37def31 100644
--- a/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
@@ -1,13 +1,14 @@
1/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 8 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/ 9 * http://armlinux.simtec.co.uk/
6 * 10 *
7 * Copyright 2010 Samsung Electronics Co., Ltd. 11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
8 * http://www.samsung.com/
9 *
10 * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
11 * 12 *
12 * S5P6442 - pwm clock and timer support 13 * S5P6442 - pwm clock and timer support
13 * 14 *
@@ -21,14 +22,14 @@
21 22
22/** 23/**
23 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk 24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
24 * @cfg: The timer TCFG1 register bits shifted down to 0. 25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
25 * 26 *
26 * Return true if the given configuration from TCFG1 is a TCLK instead 27 * Return true if the given configuration from TCFG1 is a TCLK instead
27 * any of the TDIV clocks. 28 * any of the TDIV clocks.
28 */ 29 */
29static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) 30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
30{ 31{
31 return tcfg == S3C2410_TCFG1_MUX_TCLK; 32 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
32} 33}
33 34
34/** 35/**
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
40 */ 41 */
41static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) 42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
42{ 43{
43 return 1 << (1 + tcfg1); 44 return 1 << tcfg1;
44} 45}
45 46
46/** 47/**
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
50 */ 51 */
51static inline unsigned int pwm_tdiv_has_div1(void) 52static inline unsigned int pwm_tdiv_has_div1(void)
52{ 53{
53 return 0; 54 return 1;
54} 55}
55 56
56/** 57/**
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
61 */ 62 */
62static inline unsigned long pwm_tdiv_div_bits(unsigned int div) 63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
63{ 64{
64 return ilog2(div) - 1; 65 return ilog2(div);
65} 66}
66 67
67#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK 68#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
68 69
69#endif /* __ASM_ARCH_PWMCLK_H */ 70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 8ebf51c52a01..0acbdb34b560 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -12,7 +12,7 @@ obj- :=
12 12
13# Core support for S5PV210 system 13# Core support for S5PV210 system
14 14
15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o 15obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o gpiolib.o
16 16
17# machine support 17# machine support
18 18
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ccccae262351..154bca4abc09 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -31,6 +31,128 @@
31#include <plat/clock-clksrc.h> 31#include <plat/clock-clksrc.h>
32#include <plat/s5pv210.h> 32#include <plat/s5pv210.h>
33 33
34static struct clksrc_clk clk_mout_apll = {
35 .clk = {
36 .name = "mout_apll",
37 .id = -1,
38 },
39 .sources = &clk_src_apll,
40 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
41};
42
43static struct clksrc_clk clk_mout_epll = {
44 .clk = {
45 .name = "mout_epll",
46 .id = -1,
47 },
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
50};
51
52static struct clksrc_clk clk_mout_mpll = {
53 .clk = {
54 .name = "mout_mpll",
55 .id = -1,
56 },
57 .sources = &clk_src_mpll,
58 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
59};
60
61static struct clk *clkset_armclk_list[] = {
62 [0] = &clk_mout_apll.clk,
63 [1] = &clk_mout_mpll.clk,
64};
65
66static struct clksrc_sources clkset_armclk = {
67 .sources = clkset_armclk_list,
68 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
69};
70
71static struct clksrc_clk clk_armclk = {
72 .clk = {
73 .name = "armclk",
74 .id = -1,
75 },
76 .sources = &clkset_armclk,
77 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
78 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79};
80
81static struct clksrc_clk clk_hclk_msys = {
82 .clk = {
83 .name = "hclk_msys",
84 .id = -1,
85 .parent = &clk_armclk.clk,
86 },
87 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
88};
89
90static struct clksrc_clk clk_pclk_msys = {
91 .clk = {
92 .name = "pclk_msys",
93 .id = -1,
94 .parent = &clk_hclk_msys.clk,
95 },
96 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
97};
98
99static struct clksrc_clk clk_sclk_a2m = {
100 .clk = {
101 .name = "sclk_a2m",
102 .id = -1,
103 .parent = &clk_mout_apll.clk,
104 },
105 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
106};
107
108static struct clk *clkset_hclk_sys_list[] = {
109 [0] = &clk_mout_mpll.clk,
110 [1] = &clk_sclk_a2m.clk,
111};
112
113static struct clksrc_sources clkset_hclk_sys = {
114 .sources = clkset_hclk_sys_list,
115 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
116};
117
118static struct clksrc_clk clk_hclk_dsys = {
119 .clk = {
120 .name = "hclk_dsys",
121 .id = -1,
122 },
123 .sources = &clkset_hclk_sys,
124 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
126};
127
128static struct clksrc_clk clk_pclk_dsys = {
129 .clk = {
130 .name = "pclk_dsys",
131 .id = -1,
132 .parent = &clk_hclk_dsys.clk,
133 },
134 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
135};
136
137static struct clksrc_clk clk_hclk_psys = {
138 .clk = {
139 .name = "hclk_psys",
140 .id = -1,
141 },
142 .sources = &clkset_hclk_sys,
143 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
145};
146
147static struct clksrc_clk clk_pclk_psys = {
148 .clk = {
149 .name = "pclk_psys",
150 .id = -1,
151 .parent = &clk_hclk_psys.clk,
152 },
153 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
154};
155
34static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable) 156static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
35{ 157{
36 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable); 158 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
@@ -51,176 +173,226 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
51 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable); 173 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
52} 174}
53 175
54static struct clk clk_h200 = { 176static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
55 .name = "hclk200", 177{
178 return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
179}
180
181static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
182{
183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184}
185
186static struct clk clk_sclk_hdmi27m = {
187 .name = "sclk_hdmi27m",
56 .id = -1, 188 .id = -1,
189 .rate = 27000000,
57}; 190};
58 191
59static struct clk clk_h100 = { 192static struct clk clk_sclk_hdmiphy = {
60 .name = "hclk100", 193 .name = "sclk_hdmiphy",
61 .id = -1, 194 .id = -1,
62}; 195};
63 196
64static struct clk clk_h166 = { 197static struct clk clk_sclk_usbphy0 = {
65 .name = "hclk166", 198 .name = "sclk_usbphy0",
66 .id = -1, 199 .id = -1,
67}; 200};
68 201
69static struct clk clk_h133 = { 202static struct clk clk_sclk_usbphy1 = {
70 .name = "hclk133", 203 .name = "sclk_usbphy1",
71 .id = -1, 204 .id = -1,
72}; 205};
73 206
74static struct clk clk_p100 = { 207static struct clk clk_pcmcdclk0 = {
75 .name = "pclk100", 208 .name = "pcmcdclk",
76 .id = -1, 209 .id = -1,
77}; 210};
78 211
79static struct clk clk_p83 = { 212static struct clk clk_pcmcdclk1 = {
80 .name = "pclk83", 213 .name = "pcmcdclk",
81 .id = -1, 214 .id = -1,
82}; 215};
83 216
84static struct clk clk_p66 = { 217static struct clk clk_pcmcdclk2 = {
85 .name = "pclk66", 218 .name = "pcmcdclk",
86 .id = -1, 219 .id = -1,
87}; 220};
88 221
89static struct clk *sys_clks[] = { 222static struct clk *clkset_vpllsrc_list[] = {
90 &clk_h200, 223 [0] = &clk_fin_vpll,
91 &clk_h100, 224 [1] = &clk_sclk_hdmi27m,
92 &clk_h166, 225};
93 &clk_h133, 226
94 &clk_p100, 227static struct clksrc_sources clkset_vpllsrc = {
95 &clk_p83, 228 .sources = clkset_vpllsrc_list,
96 &clk_p66 229 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
230};
231
232static struct clksrc_clk clk_vpllsrc = {
233 .clk = {
234 .name = "vpll_src",
235 .id = -1,
236 .enable = s5pv210_clk_mask0_ctrl,
237 .ctrlbit = (1 << 7),
238 },
239 .sources = &clkset_vpllsrc,
240 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
241};
242
243static struct clk *clkset_sclk_vpll_list[] = {
244 [0] = &clk_vpllsrc.clk,
245 [1] = &clk_fout_vpll,
246};
247
248static struct clksrc_sources clkset_sclk_vpll = {
249 .sources = clkset_sclk_vpll_list,
250 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
251};
252
253static struct clksrc_clk clk_sclk_vpll = {
254 .clk = {
255 .name = "sclk_vpll",
256 .id = -1,
257 },
258 .sources = &clkset_sclk_vpll,
259 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
260};
261
262static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
263{
264 return clk_get_rate(clk->parent) / 2;
265}
266
267static struct clk_ops clk_hclk_imem_ops = {
268 .get_rate = s5pv210_clk_imem_get_rate,
97}; 269};
98 270
99static struct clk init_clocks_disable[] = { 271static struct clk init_clocks_disable[] = {
100 { 272 {
101 .name = "rot", 273 .name = "rot",
102 .id = -1, 274 .id = -1,
103 .parent = &clk_h166, 275 .parent = &clk_hclk_dsys.clk,
104 .enable = s5pv210_clk_ip0_ctrl, 276 .enable = s5pv210_clk_ip0_ctrl,
105 .ctrlbit = (1<<29), 277 .ctrlbit = (1<<29),
106 }, { 278 }, {
107 .name = "otg", 279 .name = "otg",
108 .id = -1, 280 .id = -1,
109 .parent = &clk_h133, 281 .parent = &clk_hclk_psys.clk,
110 .enable = s5pv210_clk_ip1_ctrl, 282 .enable = s5pv210_clk_ip1_ctrl,
111 .ctrlbit = (1<<16), 283 .ctrlbit = (1<<16),
112 }, { 284 }, {
113 .name = "usb-host", 285 .name = "usb-host",
114 .id = -1, 286 .id = -1,
115 .parent = &clk_h133, 287 .parent = &clk_hclk_psys.clk,
116 .enable = s5pv210_clk_ip1_ctrl, 288 .enable = s5pv210_clk_ip1_ctrl,
117 .ctrlbit = (1<<17), 289 .ctrlbit = (1<<17),
118 }, { 290 }, {
119 .name = "lcd", 291 .name = "lcd",
120 .id = -1, 292 .id = -1,
121 .parent = &clk_h166, 293 .parent = &clk_hclk_dsys.clk,
122 .enable = s5pv210_clk_ip1_ctrl, 294 .enable = s5pv210_clk_ip1_ctrl,
123 .ctrlbit = (1<<0), 295 .ctrlbit = (1<<0),
124 }, { 296 }, {
125 .name = "cfcon", 297 .name = "cfcon",
126 .id = 0, 298 .id = 0,
127 .parent = &clk_h133, 299 .parent = &clk_hclk_psys.clk,
128 .enable = s5pv210_clk_ip1_ctrl, 300 .enable = s5pv210_clk_ip1_ctrl,
129 .ctrlbit = (1<<25), 301 .ctrlbit = (1<<25),
130 }, { 302 }, {
131 .name = "hsmmc", 303 .name = "hsmmc",
132 .id = 0, 304 .id = 0,
133 .parent = &clk_h133, 305 .parent = &clk_hclk_psys.clk,
134 .enable = s5pv210_clk_ip2_ctrl, 306 .enable = s5pv210_clk_ip2_ctrl,
135 .ctrlbit = (1<<16), 307 .ctrlbit = (1<<16),
136 }, { 308 }, {
137 .name = "hsmmc", 309 .name = "hsmmc",
138 .id = 1, 310 .id = 1,
139 .parent = &clk_h133, 311 .parent = &clk_hclk_psys.clk,
140 .enable = s5pv210_clk_ip2_ctrl, 312 .enable = s5pv210_clk_ip2_ctrl,
141 .ctrlbit = (1<<17), 313 .ctrlbit = (1<<17),
142 }, { 314 }, {
143 .name = "hsmmc", 315 .name = "hsmmc",
144 .id = 2, 316 .id = 2,
145 .parent = &clk_h133, 317 .parent = &clk_hclk_psys.clk,
146 .enable = s5pv210_clk_ip2_ctrl, 318 .enable = s5pv210_clk_ip2_ctrl,
147 .ctrlbit = (1<<18), 319 .ctrlbit = (1<<18),
148 }, { 320 }, {
149 .name = "hsmmc", 321 .name = "hsmmc",
150 .id = 3, 322 .id = 3,
151 .parent = &clk_h133, 323 .parent = &clk_hclk_psys.clk,
152 .enable = s5pv210_clk_ip2_ctrl, 324 .enable = s5pv210_clk_ip2_ctrl,
153 .ctrlbit = (1<<19), 325 .ctrlbit = (1<<19),
154 }, { 326 }, {
155 .name = "systimer", 327 .name = "systimer",
156 .id = -1, 328 .id = -1,
157 .parent = &clk_p66, 329 .parent = &clk_pclk_psys.clk,
158 .enable = s5pv210_clk_ip3_ctrl, 330 .enable = s5pv210_clk_ip3_ctrl,
159 .ctrlbit = (1<<16), 331 .ctrlbit = (1<<16),
160 }, { 332 }, {
161 .name = "watchdog", 333 .name = "watchdog",
162 .id = -1, 334 .id = -1,
163 .parent = &clk_p66, 335 .parent = &clk_pclk_psys.clk,
164 .enable = s5pv210_clk_ip3_ctrl, 336 .enable = s5pv210_clk_ip3_ctrl,
165 .ctrlbit = (1<<22), 337 .ctrlbit = (1<<22),
166 }, { 338 }, {
167 .name = "rtc", 339 .name = "rtc",
168 .id = -1, 340 .id = -1,
169 .parent = &clk_p66, 341 .parent = &clk_pclk_psys.clk,
170 .enable = s5pv210_clk_ip3_ctrl, 342 .enable = s5pv210_clk_ip3_ctrl,
171 .ctrlbit = (1<<15), 343 .ctrlbit = (1<<15),
172 }, { 344 }, {
173 .name = "i2c", 345 .name = "i2c",
174 .id = 0, 346 .id = 0,
175 .parent = &clk_p66, 347 .parent = &clk_pclk_psys.clk,
176 .enable = s5pv210_clk_ip3_ctrl, 348 .enable = s5pv210_clk_ip3_ctrl,
177 .ctrlbit = (1<<7), 349 .ctrlbit = (1<<7),
178 }, { 350 }, {
179 .name = "i2c", 351 .name = "i2c",
180 .id = 1, 352 .id = 1,
181 .parent = &clk_p66, 353 .parent = &clk_pclk_psys.clk,
182 .enable = s5pv210_clk_ip3_ctrl, 354 .enable = s5pv210_clk_ip3_ctrl,
183 .ctrlbit = (1<<8), 355 .ctrlbit = (1<<8),
184 }, { 356 }, {
185 .name = "i2c", 357 .name = "i2c",
186 .id = 2, 358 .id = 2,
187 .parent = &clk_p66, 359 .parent = &clk_pclk_psys.clk,
188 .enable = s5pv210_clk_ip3_ctrl, 360 .enable = s5pv210_clk_ip3_ctrl,
189 .ctrlbit = (1<<9), 361 .ctrlbit = (1<<9),
190 }, { 362 }, {
191 .name = "spi", 363 .name = "spi",
192 .id = 0, 364 .id = 0,
193 .parent = &clk_p66, 365 .parent = &clk_pclk_psys.clk,
194 .enable = s5pv210_clk_ip3_ctrl, 366 .enable = s5pv210_clk_ip3_ctrl,
195 .ctrlbit = (1<<12), 367 .ctrlbit = (1<<12),
196 }, { 368 }, {
197 .name = "spi", 369 .name = "spi",
198 .id = 1, 370 .id = 1,
199 .parent = &clk_p66, 371 .parent = &clk_pclk_psys.clk,
200 .enable = s5pv210_clk_ip3_ctrl, 372 .enable = s5pv210_clk_ip3_ctrl,
201 .ctrlbit = (1<<13), 373 .ctrlbit = (1<<13),
202 }, { 374 }, {
203 .name = "spi", 375 .name = "spi",
204 .id = 2, 376 .id = 2,
205 .parent = &clk_p66, 377 .parent = &clk_pclk_psys.clk,
206 .enable = s5pv210_clk_ip3_ctrl, 378 .enable = s5pv210_clk_ip3_ctrl,
207 .ctrlbit = (1<<14), 379 .ctrlbit = (1<<14),
208 }, { 380 }, {
209 .name = "timers", 381 .name = "timers",
210 .id = -1, 382 .id = -1,
211 .parent = &clk_p66, 383 .parent = &clk_pclk_psys.clk,
212 .enable = s5pv210_clk_ip3_ctrl, 384 .enable = s5pv210_clk_ip3_ctrl,
213 .ctrlbit = (1<<23), 385 .ctrlbit = (1<<23),
214 }, { 386 }, {
215 .name = "adc", 387 .name = "adc",
216 .id = -1, 388 .id = -1,
217 .parent = &clk_p66, 389 .parent = &clk_pclk_psys.clk,
218 .enable = s5pv210_clk_ip3_ctrl, 390 .enable = s5pv210_clk_ip3_ctrl,
219 .ctrlbit = (1<<24), 391 .ctrlbit = (1<<24),
220 }, { 392 }, {
221 .name = "keypad", 393 .name = "keypad",
222 .id = -1, 394 .id = -1,
223 .parent = &clk_p66, 395 .parent = &clk_pclk_psys.clk,
224 .enable = s5pv210_clk_ip3_ctrl, 396 .enable = s5pv210_clk_ip3_ctrl,
225 .ctrlbit = (1<<21), 397 .ctrlbit = (1<<21),
226 }, { 398 }, {
@@ -246,106 +418,537 @@ static struct clk init_clocks_disable[] = {
246 418
247static struct clk init_clocks[] = { 419static struct clk init_clocks[] = {
248 { 420 {
421 .name = "hclk_imem",
422 .id = -1,
423 .parent = &clk_hclk_msys.clk,
424 .ctrlbit = (1 << 5),
425 .enable = s5pv210_clk_ip0_ctrl,
426 .ops = &clk_hclk_imem_ops,
427 }, {
249 .name = "uart", 428 .name = "uart",
250 .id = 0, 429 .id = 0,
251 .parent = &clk_p66, 430 .parent = &clk_pclk_psys.clk,
252 .enable = s5pv210_clk_ip3_ctrl, 431 .enable = s5pv210_clk_ip3_ctrl,
253 .ctrlbit = (1<<7), 432 .ctrlbit = (1<<7),
254 }, { 433 }, {
255 .name = "uart", 434 .name = "uart",
256 .id = 1, 435 .id = 1,
257 .parent = &clk_p66, 436 .parent = &clk_pclk_psys.clk,
258 .enable = s5pv210_clk_ip3_ctrl, 437 .enable = s5pv210_clk_ip3_ctrl,
259 .ctrlbit = (1<<8), 438 .ctrlbit = (1<<8),
260 }, { 439 }, {
261 .name = "uart", 440 .name = "uart",
262 .id = 2, 441 .id = 2,
263 .parent = &clk_p66, 442 .parent = &clk_pclk_psys.clk,
264 .enable = s5pv210_clk_ip3_ctrl, 443 .enable = s5pv210_clk_ip3_ctrl,
265 .ctrlbit = (1<<9), 444 .ctrlbit = (1<<9),
266 }, { 445 }, {
267 .name = "uart", 446 .name = "uart",
268 .id = 3, 447 .id = 3,
269 .parent = &clk_p66, 448 .parent = &clk_pclk_psys.clk,
270 .enable = s5pv210_clk_ip3_ctrl, 449 .enable = s5pv210_clk_ip3_ctrl,
271 .ctrlbit = (1<<10), 450 .ctrlbit = (1<<10),
272 }, 451 },
273}; 452};
274 453
275static struct clksrc_clk clk_mout_apll = { 454static struct clk *clkset_uart_list[] = {
276 .clk = { 455 [6] = &clk_mout_mpll.clk,
277 .name = "mout_apll", 456 [7] = &clk_mout_epll.clk,
457};
458
459static struct clksrc_sources clkset_uart = {
460 .sources = clkset_uart_list,
461 .nr_sources = ARRAY_SIZE(clkset_uart_list),
462};
463
464static struct clk *clkset_group1_list[] = {
465 [0] = &clk_sclk_a2m.clk,
466 [1] = &clk_mout_mpll.clk,
467 [2] = &clk_mout_epll.clk,
468 [3] = &clk_sclk_vpll.clk,
469};
470
471static struct clksrc_sources clkset_group1 = {
472 .sources = clkset_group1_list,
473 .nr_sources = ARRAY_SIZE(clkset_group1_list),
474};
475
476static struct clk *clkset_sclk_onenand_list[] = {
477 [0] = &clk_hclk_psys.clk,
478 [1] = &clk_hclk_dsys.clk,
479};
480
481static struct clksrc_sources clkset_sclk_onenand = {
482 .sources = clkset_sclk_onenand_list,
483 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
484};
485
486static struct clk *clkset_sclk_dac_list[] = {
487 [0] = &clk_sclk_vpll.clk,
488 [1] = &clk_sclk_hdmiphy,
489};
490
491static struct clksrc_sources clkset_sclk_dac = {
492 .sources = clkset_sclk_dac_list,
493 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
494};
495
496static struct clksrc_clk clk_sclk_dac = {
497 .clk = {
498 .name = "sclk_dac",
278 .id = -1, 499 .id = -1,
500 .ctrlbit = (1 << 10),
501 .enable = s5pv210_clk_ip1_ctrl,
279 }, 502 },
280 .sources = &clk_src_apll, 503 .sources = &clkset_sclk_dac,
281 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, 504 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
282}; 505};
283 506
284static struct clksrc_clk clk_mout_epll = { 507static struct clksrc_clk clk_sclk_pixel = {
285 .clk = { 508 .clk = {
286 .name = "mout_epll", 509 .name = "sclk_pixel",
287 .id = -1, 510 .id = -1,
511 .parent = &clk_sclk_vpll.clk,
288 }, 512 },
289 .sources = &clk_src_epll, 513 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
290 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
291}; 514};
292 515
293static struct clksrc_clk clk_mout_mpll = { 516static struct clk *clkset_sclk_hdmi_list[] = {
294 .clk = { 517 [0] = &clk_sclk_pixel.clk,
295 .name = "mout_mpll", 518 [1] = &clk_sclk_hdmiphy,
519};
520
521static struct clksrc_sources clkset_sclk_hdmi = {
522 .sources = clkset_sclk_hdmi_list,
523 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
524};
525
526static struct clksrc_clk clk_sclk_hdmi = {
527 .clk = {
528 .name = "sclk_hdmi",
296 .id = -1, 529 .id = -1,
530 .enable = s5pv210_clk_ip1_ctrl,
531 .ctrlbit = (1 << 11),
297 }, 532 },
298 .sources = &clk_src_mpll, 533 .sources = &clkset_sclk_hdmi,
299 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, 534 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
300}; 535};
301 536
302static struct clk *clkset_uart_list[] = { 537static struct clk *clkset_sclk_mixer_list[] = {
538 [0] = &clk_sclk_dac.clk,
539 [1] = &clk_sclk_hdmi.clk,
540};
541
542static struct clksrc_sources clkset_sclk_mixer = {
543 .sources = clkset_sclk_mixer_list,
544 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
545};
546
547static struct clk *clkset_sclk_audio0_list[] = {
548 [0] = &clk_ext_xtal_mux,
549 [1] = &clk_pcmcdclk0,
550 [2] = &clk_sclk_hdmi27m,
551 [3] = &clk_sclk_usbphy0,
552 [4] = &clk_sclk_usbphy1,
553 [5] = &clk_sclk_hdmiphy,
303 [6] = &clk_mout_mpll.clk, 554 [6] = &clk_mout_mpll.clk,
304 [7] = &clk_mout_epll.clk, 555 [7] = &clk_mout_epll.clk,
556 [8] = &clk_sclk_vpll.clk,
305}; 557};
306 558
307static struct clksrc_sources clkset_uart = { 559static struct clksrc_sources clkset_sclk_audio0 = {
308 .sources = clkset_uart_list, 560 .sources = clkset_sclk_audio0_list,
309 .nr_sources = ARRAY_SIZE(clkset_uart_list), 561 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
562};
563
564static struct clksrc_clk clk_sclk_audio0 = {
565 .clk = {
566 .name = "sclk_audio",
567 .id = 0,
568 .enable = s5pv210_clk_ip3_ctrl,
569 .ctrlbit = (1 << 4),
570 },
571 .sources = &clkset_sclk_audio0,
572 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
573 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
574};
575
576static struct clk *clkset_sclk_audio1_list[] = {
577 [0] = &clk_ext_xtal_mux,
578 [1] = &clk_pcmcdclk1,
579 [2] = &clk_sclk_hdmi27m,
580 [3] = &clk_sclk_usbphy0,
581 [4] = &clk_sclk_usbphy1,
582 [5] = &clk_sclk_hdmiphy,
583 [6] = &clk_mout_mpll.clk,
584 [7] = &clk_mout_epll.clk,
585 [8] = &clk_sclk_vpll.clk,
586};
587
588static struct clksrc_sources clkset_sclk_audio1 = {
589 .sources = clkset_sclk_audio1_list,
590 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
591};
592
593static struct clksrc_clk clk_sclk_audio1 = {
594 .clk = {
595 .name = "sclk_audio",
596 .id = 1,
597 .enable = s5pv210_clk_ip3_ctrl,
598 .ctrlbit = (1 << 5),
599 },
600 .sources = &clkset_sclk_audio1,
601 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
602 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
603};
604
605static struct clk *clkset_sclk_audio2_list[] = {
606 [0] = &clk_ext_xtal_mux,
607 [1] = &clk_pcmcdclk0,
608 [2] = &clk_sclk_hdmi27m,
609 [3] = &clk_sclk_usbphy0,
610 [4] = &clk_sclk_usbphy1,
611 [5] = &clk_sclk_hdmiphy,
612 [6] = &clk_mout_mpll.clk,
613 [7] = &clk_mout_epll.clk,
614 [8] = &clk_sclk_vpll.clk,
615};
616
617static struct clksrc_sources clkset_sclk_audio2 = {
618 .sources = clkset_sclk_audio2_list,
619 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
620};
621
622static struct clksrc_clk clk_sclk_audio2 = {
623 .clk = {
624 .name = "sclk_audio",
625 .id = 2,
626 .enable = s5pv210_clk_ip3_ctrl,
627 .ctrlbit = (1 << 6),
628 },
629 .sources = &clkset_sclk_audio2,
630 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
631 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
632};
633
634static struct clk *clkset_sclk_spdif_list[] = {
635 [0] = &clk_sclk_audio0.clk,
636 [1] = &clk_sclk_audio1.clk,
637 [2] = &clk_sclk_audio2.clk,
638};
639
640static struct clksrc_sources clkset_sclk_spdif = {
641 .sources = clkset_sclk_spdif_list,
642 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
643};
644
645static struct clk *clkset_group2_list[] = {
646 [0] = &clk_ext_xtal_mux,
647 [1] = &clk_xusbxti,
648 [2] = &clk_sclk_hdmi27m,
649 [3] = &clk_sclk_usbphy0,
650 [4] = &clk_sclk_usbphy1,
651 [5] = &clk_sclk_hdmiphy,
652 [6] = &clk_mout_mpll.clk,
653 [7] = &clk_mout_epll.clk,
654 [8] = &clk_sclk_vpll.clk,
655};
656
657static struct clksrc_sources clkset_group2 = {
658 .sources = clkset_group2_list,
659 .nr_sources = ARRAY_SIZE(clkset_group2_list),
310}; 660};
311 661
312static struct clksrc_clk clksrcs[] = { 662static struct clksrc_clk clksrcs[] = {
313 { 663 {
314 .clk = { 664 .clk = {
315 .name = "uclk1", 665 .name = "sclk_dmc",
316 .id = -1, 666 .id = -1,
667 },
668 .sources = &clkset_group1,
669 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
670 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
671 }, {
672 .clk = {
673 .name = "sclk_onenand",
674 .id = -1,
675 },
676 .sources = &clkset_sclk_onenand,
677 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
678 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
679 }, {
680 .clk = {
681 .name = "uclk1",
682 .id = 0,
317 .ctrlbit = (1<<17), 683 .ctrlbit = (1<<17),
318 .enable = s5pv210_clk_ip3_ctrl, 684 .enable = s5pv210_clk_ip3_ctrl,
319 }, 685 },
320 .sources = &clkset_uart, 686 .sources = &clkset_uart,
321 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, 687 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
322 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, 688 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
323 } 689 }, {
690 .clk = {
691 .name = "uclk1",
692 .id = 1,
693 .enable = s5pv210_clk_ip3_ctrl,
694 .ctrlbit = (1 << 18),
695 },
696 .sources = &clkset_uart,
697 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
698 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
699 }, {
700 .clk = {
701 .name = "uclk1",
702 .id = 2,
703 .enable = s5pv210_clk_ip3_ctrl,
704 .ctrlbit = (1 << 19),
705 },
706 .sources = &clkset_uart,
707 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
708 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
709 }, {
710 .clk = {
711 .name = "uclk1",
712 .id = 3,
713 .enable = s5pv210_clk_ip3_ctrl,
714 .ctrlbit = (1 << 20),
715 },
716 .sources = &clkset_uart,
717 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
718 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
719 }, {
720 .clk = {
721 .name = "sclk_mixer",
722 .id = -1,
723 .enable = s5pv210_clk_ip1_ctrl,
724 .ctrlbit = (1 << 9),
725 },
726 .sources = &clkset_sclk_mixer,
727 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
728 }, {
729 .clk = {
730 .name = "sclk_spdif",
731 .id = -1,
732 .enable = s5pv210_clk_mask0_ctrl,
733 .ctrlbit = (1 << 27),
734 },
735 .sources = &clkset_sclk_spdif,
736 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
737 }, {
738 .clk = {
739 .name = "sclk_fimc",
740 .id = 0,
741 .enable = s5pv210_clk_ip0_ctrl,
742 .ctrlbit = (1 << 24),
743 },
744 .sources = &clkset_group2,
745 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
746 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
747 }, {
748 .clk = {
749 .name = "sclk_fimc",
750 .id = 1,
751 .enable = s5pv210_clk_ip0_ctrl,
752 .ctrlbit = (1 << 25),
753 },
754 .sources = &clkset_group2,
755 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
756 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
757 }, {
758 .clk = {
759 .name = "sclk_fimc",
760 .id = 2,
761 .enable = s5pv210_clk_ip0_ctrl,
762 .ctrlbit = (1 << 26),
763 },
764 .sources = &clkset_group2,
765 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
766 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
767 }, {
768 .clk = {
769 .name = "sclk_cam",
770 .id = 0,
771 },
772 .sources = &clkset_group2,
773 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
774 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
775 }, {
776 .clk = {
777 .name = "sclk_cam",
778 .id = 1,
779 },
780 .sources = &clkset_group2,
781 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
782 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
783 }, {
784 .clk = {
785 .name = "sclk_fimd",
786 .id = -1,
787 .enable = s5pv210_clk_ip1_ctrl,
788 .ctrlbit = (1 << 0),
789 },
790 .sources = &clkset_group2,
791 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
792 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
793 }, {
794 .clk = {
795 .name = "sclk_mmc",
796 .id = 0,
797 .enable = s5pv210_clk_ip2_ctrl,
798 .ctrlbit = (1 << 16),
799 },
800 .sources = &clkset_group2,
801 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
802 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
803 }, {
804 .clk = {
805 .name = "sclk_mmc",
806 .id = 1,
807 .enable = s5pv210_clk_ip2_ctrl,
808 .ctrlbit = (1 << 17),
809 },
810 .sources = &clkset_group2,
811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
812 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
813 }, {
814 .clk = {
815 .name = "sclk_mmc",
816 .id = 2,
817 .enable = s5pv210_clk_ip2_ctrl,
818 .ctrlbit = (1 << 18),
819 },
820 .sources = &clkset_group2,
821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
822 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
823 }, {
824 .clk = {
825 .name = "sclk_mmc",
826 .id = 3,
827 .enable = s5pv210_clk_ip2_ctrl,
828 .ctrlbit = (1 << 19),
829 },
830 .sources = &clkset_group2,
831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
832 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
833 }, {
834 .clk = {
835 .name = "sclk_mfc",
836 .id = -1,
837 .enable = s5pv210_clk_ip0_ctrl,
838 .ctrlbit = (1 << 16),
839 },
840 .sources = &clkset_group1,
841 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
842 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
843 }, {
844 .clk = {
845 .name = "sclk_g2d",
846 .id = -1,
847 .enable = s5pv210_clk_ip0_ctrl,
848 .ctrlbit = (1 << 12),
849 },
850 .sources = &clkset_group1,
851 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
852 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
853 }, {
854 .clk = {
855 .name = "sclk_g3d",
856 .id = -1,
857 .enable = s5pv210_clk_ip0_ctrl,
858 .ctrlbit = (1 << 8),
859 },
860 .sources = &clkset_group1,
861 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
862 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
863 }, {
864 .clk = {
865 .name = "sclk_csis",
866 .id = -1,
867 .enable = s5pv210_clk_ip0_ctrl,
868 .ctrlbit = (1 << 31),
869 },
870 .sources = &clkset_group2,
871 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
872 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
873 }, {
874 .clk = {
875 .name = "sclk_spi",
876 .id = 0,
877 .enable = s5pv210_clk_ip3_ctrl,
878 .ctrlbit = (1 << 12),
879 },
880 .sources = &clkset_group2,
881 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
882 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
883 }, {
884 .clk = {
885 .name = "sclk_spi",
886 .id = 1,
887 .enable = s5pv210_clk_ip3_ctrl,
888 .ctrlbit = (1 << 13),
889 },
890 .sources = &clkset_group2,
891 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
892 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
893 }, {
894 .clk = {
895 .name = "sclk_pwi",
896 .id = -1,
897 .enable = &s5pv210_clk_ip4_ctrl,
898 .ctrlbit = (1 << 2),
899 },
900 .sources = &clkset_group2,
901 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
902 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
903 }, {
904 .clk = {
905 .name = "sclk_pwm",
906 .id = -1,
907 .enable = s5pv210_clk_ip3_ctrl,
908 .ctrlbit = (1 << 23),
909 },
910 .sources = &clkset_group2,
911 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
912 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
913 },
324}; 914};
325 915
326/* Clock initialisation code */ 916/* Clock initialisation code */
327static struct clksrc_clk *init_parents[] = { 917static struct clksrc_clk *sysclks[] = {
328 &clk_mout_apll, 918 &clk_mout_apll,
329 &clk_mout_epll, 919 &clk_mout_epll,
330 &clk_mout_mpll, 920 &clk_mout_mpll,
921 &clk_armclk,
922 &clk_hclk_msys,
923 &clk_sclk_a2m,
924 &clk_hclk_dsys,
925 &clk_hclk_psys,
926 &clk_pclk_msys,
927 &clk_pclk_dsys,
928 &clk_pclk_psys,
929 &clk_vpllsrc,
930 &clk_sclk_vpll,
931 &clk_sclk_dac,
932 &clk_sclk_pixel,
933 &clk_sclk_hdmi,
331}; 934};
332 935
333#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
334
335void __init_or_cpufreq s5pv210_setup_clocks(void) 936void __init_or_cpufreq s5pv210_setup_clocks(void)
336{ 937{
337 struct clk *xtal_clk; 938 struct clk *xtal_clk;
338 unsigned long xtal; 939 unsigned long xtal;
940 unsigned long vpllsrc;
339 unsigned long armclk; 941 unsigned long armclk;
340 unsigned long hclk200; 942 unsigned long hclk_msys;
341 unsigned long hclk166; 943 unsigned long hclk_dsys;
342 unsigned long hclk133; 944 unsigned long hclk_psys;
343 unsigned long pclk100; 945 unsigned long pclk_msys;
344 unsigned long pclk83; 946 unsigned long pclk_dsys;
345 unsigned long pclk66; 947 unsigned long pclk_psys;
346 unsigned long apll; 948 unsigned long apll;
347 unsigned long mpll; 949 unsigned long mpll;
348 unsigned long epll; 950 unsigned long epll;
951 unsigned long vpll;
349 unsigned int ptr; 952 unsigned int ptr;
350 u32 clkdiv0, clkdiv1; 953 u32 clkdiv0, clkdiv1;
351 954
@@ -368,59 +971,46 @@ void __init_or_cpufreq s5pv210_setup_clocks(void)
368 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); 971 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
369 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); 972 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
370 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); 973 epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
371 974 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
372 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld", 975 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
373 apll, mpll, epll);
374
375 armclk = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_APLL);
376 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX200_MASK)
377 hclk200 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
378 else
379 hclk200 = armclk / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK200);
380
381 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX166_MASK) {
382 hclk166 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
383 hclk166 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
384 } else
385 hclk166 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK166);
386
387 if (__raw_readl(S5P_CLK_SRC0) & S5P_CLKSRC0_MUX133_MASK) {
388 hclk133 = apll / GET_DIV(clkdiv0, S5P_CLKDIV0_A2M);
389 hclk133 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
390 } else
391 hclk133 = mpll / GET_DIV(clkdiv0, S5P_CLKDIV0_HCLK133);
392
393 pclk100 = hclk200 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK100);
394 pclk83 = hclk166 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK83);
395 pclk66 = hclk133 / GET_DIV(clkdiv0, S5P_CLKDIV0_PCLK66);
396
397 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld, \
398 HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
399 armclk, hclk200, hclk166, hclk133, pclk100, pclk83, pclk66);
400 976
401 clk_fout_apll.rate = apll; 977 clk_fout_apll.rate = apll;
402 clk_fout_mpll.rate = mpll; 978 clk_fout_mpll.rate = mpll;
403 clk_fout_epll.rate = epll; 979 clk_fout_epll.rate = epll;
980 clk_fout_vpll.rate = vpll;
404 981
405 clk_f.rate = armclk; 982 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
406 clk_h.rate = hclk133; 983 apll, mpll, epll, vpll);
407 clk_p.rate = pclk66; 984
408 clk_p66.rate = pclk66; 985 armclk = clk_get_rate(&clk_armclk.clk);
409 clk_p83.rate = pclk83; 986 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
410 clk_h133.rate = hclk133; 987 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
411 clk_h166.rate = hclk166; 988 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
412 clk_h200.rate = hclk200; 989 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
990 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
991 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
992
993 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
994 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
995 armclk, hclk_msys, hclk_dsys, hclk_psys,
996 pclk_msys, pclk_dsys, pclk_psys);
413 997
414 for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++) 998 clk_f.rate = armclk;
415 s3c_set_clksrc(init_parents[ptr], true); 999 clk_h.rate = hclk_psys;
1000 clk_p.rate = pclk_psys;
416 1001
417 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) 1002 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
418 s3c_set_clksrc(&clksrcs[ptr], true); 1003 s3c_set_clksrc(&clksrcs[ptr], true);
419} 1004}
420 1005
421static struct clk *clks[] __initdata = { 1006static struct clk *clks[] __initdata = {
422 &clk_mout_epll.clk, 1007 &clk_sclk_hdmi27m,
423 &clk_mout_mpll.clk, 1008 &clk_sclk_hdmiphy,
1009 &clk_sclk_usbphy0,
1010 &clk_sclk_usbphy1,
1011 &clk_pcmcdclk0,
1012 &clk_pcmcdclk1,
1013 &clk_pcmcdclk2,
424}; 1014};
425 1015
426void __init s5pv210_register_clocks(void) 1016void __init s5pv210_register_clocks(void)
@@ -433,13 +1023,12 @@ void __init s5pv210_register_clocks(void)
433 if (ret > 0) 1023 if (ret > 0)
434 printk(KERN_ERR "Failed to register %u clocks\n", ret); 1024 printk(KERN_ERR "Failed to register %u clocks\n", ret);
435 1025
1026 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1027 s3c_register_clksrc(sysclks[ptr], 1);
1028
436 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); 1029 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
437 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); 1030 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
438 1031
439 ret = s3c24xx_register_clocks(sys_clks, ARRAY_SIZE(sys_clks));
440 if (ret > 0)
441 printk(KERN_ERR "Failed to register system clocks\n");
442
443 clkp = init_clocks_disable; 1032 clkp = init_clocks_disable;
444 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) { 1033 for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
445 ret = s3c24xx_register_clock(clkp); 1034 ret = s3c24xx_register_clock(clkp);
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 0e0f8fde2aa6..2b776eb5d150 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void)
100 s5p_init_irq(vic, ARRAY_SIZE(vic)); 100 s5p_init_irq(vic, ARRAY_SIZE(vic));
101} 101}
102 102
103static struct sysdev_class s5pv210_sysclass = { 103struct sysdev_class s5pv210_sysclass = {
104 .name = "s5pv210-core", 104 .name = "s5pv210-core",
105}; 105};
106 106
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
new file mode 100644
index 000000000000..9ea8972e023d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -0,0 +1,261 @@
1/* linux/arch/arm/mach-s5pv210/gpiolib.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PV210 - GPIOlib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/irq.h>
15#include <linux/io.h>
16#include <linux/gpio.h>
17#include <plat/gpio-core.h>
18#include <plat/gpio-cfg.h>
19#include <plat/gpio-cfg-helpers.h>
20#include <mach/map.h>
21
22static struct s3c_gpio_cfg gpio_cfg = {
23 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
24 .set_pull = s3c_gpio_setpull_updown,
25 .get_pull = s3c_gpio_getpull_updown,
26};
27
28static struct s3c_gpio_cfg gpio_cfg_noint = {
29 .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
30 .set_pull = s3c_gpio_setpull_updown,
31 .get_pull = s3c_gpio_getpull_updown,
32};
33
34/* GPIO bank's base address given the index of the bank in the
35 * list of all gpio banks.
36 */
37#define S5PV210_BANK_BASE(bank_nr) (S5P_VA_GPIO + ((bank_nr) * 0x20))
38
39/*
40 * Following are the gpio banks in v210.
41 *
42 * The 'config' member when left to NULL, is initialized to the default
43 * structure gpio_cfg in the init function below.
44 *
45 * The 'base' member is also initialized in the init function below.
46 * Note: The initialization of 'base' member of s3c_gpio_chip structure
47 * uses the above macro and depends on the banks being listed in order here.
48 */
49static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
50 {
51 .chip = {
52 .base = S5PV210_GPA0(0),
53 .ngpio = S5PV210_GPIO_A0_NR,
54 .label = "GPA0",
55 },
56 }, {
57 .chip = {
58 .base = S5PV210_GPA1(0),
59 .ngpio = S5PV210_GPIO_A1_NR,
60 .label = "GPA1",
61 },
62 }, {
63 .chip = {
64 .base = S5PV210_GPB(0),
65 .ngpio = S5PV210_GPIO_B_NR,
66 .label = "GPB",
67 },
68 }, {
69 .chip = {
70 .base = S5PV210_GPC0(0),
71 .ngpio = S5PV210_GPIO_C0_NR,
72 .label = "GPC0",
73 },
74 }, {
75 .chip = {
76 .base = S5PV210_GPC1(0),
77 .ngpio = S5PV210_GPIO_C1_NR,
78 .label = "GPC1",
79 },
80 }, {
81 .chip = {
82 .base = S5PV210_GPD0(0),
83 .ngpio = S5PV210_GPIO_D0_NR,
84 .label = "GPD0",
85 },
86 }, {
87 .chip = {
88 .base = S5PV210_GPD1(0),
89 .ngpio = S5PV210_GPIO_D1_NR,
90 .label = "GPD1",
91 },
92 }, {
93 .chip = {
94 .base = S5PV210_GPE0(0),
95 .ngpio = S5PV210_GPIO_E0_NR,
96 .label = "GPE0",
97 },
98 }, {
99 .chip = {
100 .base = S5PV210_GPE1(0),
101 .ngpio = S5PV210_GPIO_E1_NR,
102 .label = "GPE1",
103 },
104 }, {
105 .chip = {
106 .base = S5PV210_GPF0(0),
107 .ngpio = S5PV210_GPIO_F0_NR,
108 .label = "GPF0",
109 },
110 }, {
111 .chip = {
112 .base = S5PV210_GPF1(0),
113 .ngpio = S5PV210_GPIO_F1_NR,
114 .label = "GPF1",
115 },
116 }, {
117 .chip = {
118 .base = S5PV210_GPF2(0),
119 .ngpio = S5PV210_GPIO_F2_NR,
120 .label = "GPF2",
121 },
122 }, {
123 .chip = {
124 .base = S5PV210_GPF3(0),
125 .ngpio = S5PV210_GPIO_F3_NR,
126 .label = "GPF3",
127 },
128 }, {
129 .chip = {
130 .base = S5PV210_GPG0(0),
131 .ngpio = S5PV210_GPIO_G0_NR,
132 .label = "GPG0",
133 },
134 }, {
135 .chip = {
136 .base = S5PV210_GPG1(0),
137 .ngpio = S5PV210_GPIO_G1_NR,
138 .label = "GPG1",
139 },
140 }, {
141 .chip = {
142 .base = S5PV210_GPG2(0),
143 .ngpio = S5PV210_GPIO_G2_NR,
144 .label = "GPG2",
145 },
146 }, {
147 .chip = {
148 .base = S5PV210_GPG3(0),
149 .ngpio = S5PV210_GPIO_G3_NR,
150 .label = "GPG3",
151 },
152 }, {
153 .chip = {
154 .base = S5PV210_GPI(0),
155 .ngpio = S5PV210_GPIO_I_NR,
156 .label = "GPI",
157 },
158 }, {
159 .chip = {
160 .base = S5PV210_GPJ0(0),
161 .ngpio = S5PV210_GPIO_J0_NR,
162 .label = "GPJ0",
163 },
164 }, {
165 .chip = {
166 .base = S5PV210_GPJ1(0),
167 .ngpio = S5PV210_GPIO_J1_NR,
168 .label = "GPJ1",
169 },
170 }, {
171 .chip = {
172 .base = S5PV210_GPJ2(0),
173 .ngpio = S5PV210_GPIO_J2_NR,
174 .label = "GPJ2",
175 },
176 }, {
177 .chip = {
178 .base = S5PV210_GPJ3(0),
179 .ngpio = S5PV210_GPIO_J3_NR,
180 .label = "GPJ3",
181 },
182 }, {
183 .chip = {
184 .base = S5PV210_GPJ4(0),
185 .ngpio = S5PV210_GPIO_J4_NR,
186 .label = "GPJ4",
187 },
188 }, {
189 .config = &gpio_cfg_noint,
190 .chip = {
191 .base = S5PV210_MP01(0),
192 .ngpio = S5PV210_GPIO_MP01_NR,
193 .label = "MP01",
194 },
195 }, {
196 .config = &gpio_cfg_noint,
197 .chip = {
198 .base = S5PV210_MP02(0),
199 .ngpio = S5PV210_GPIO_MP02_NR,
200 .label = "MP02",
201 },
202 }, {
203 .config = &gpio_cfg_noint,
204 .chip = {
205 .base = S5PV210_MP03(0),
206 .ngpio = S5PV210_GPIO_MP03_NR,
207 .label = "MP03",
208 },
209 }, {
210 .base = (S5P_VA_GPIO + 0xC00),
211 .config = &gpio_cfg_noint,
212 .chip = {
213 .base = S5PV210_GPH0(0),
214 .ngpio = S5PV210_GPIO_H0_NR,
215 .label = "GPH0",
216 },
217 }, {
218 .base = (S5P_VA_GPIO + 0xC20),
219 .config = &gpio_cfg_noint,
220 .chip = {
221 .base = S5PV210_GPH1(0),
222 .ngpio = S5PV210_GPIO_H1_NR,
223 .label = "GPH1",
224 },
225 }, {
226 .base = (S5P_VA_GPIO + 0xC40),
227 .config = &gpio_cfg_noint,
228 .chip = {
229 .base = S5PV210_GPH2(0),
230 .ngpio = S5PV210_GPIO_H2_NR,
231 .label = "GPH2",
232 },
233 }, {
234 .base = (S5P_VA_GPIO + 0xC60),
235 .config = &gpio_cfg_noint,
236 .chip = {
237 .base = S5PV210_GPH3(0),
238 .ngpio = S5PV210_GPIO_H3_NR,
239 .label = "GPH3",
240 },
241 },
242};
243
244static __init int s5pv210_gpiolib_init(void)
245{
246 struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
247 int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
248 int i = 0;
249
250 for (i = 0; i < nr_chips; i++, chip++) {
251 if (chip->config == NULL)
252 chip->config = &gpio_cfg;
253 if (chip->base == NULL)
254 chip->base = S5PV210_BANK_BASE(i);
255 }
256
257 samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
258
259 return 0;
260}
261core_initcall(s5pv210_gpiolib_init);
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index 533b020e21e9..d6461ba2b71d 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -18,6 +18,8 @@
18#define gpio_cansleep __gpio_cansleep 18#define gpio_cansleep __gpio_cansleep
19#define gpio_to_irq __gpio_to_irq 19#define gpio_to_irq __gpio_to_irq
20 20
21/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
22
21/* GPIO bank sizes */ 23/* GPIO bank sizes */
22#define S5PV210_GPIO_A0_NR (8) 24#define S5PV210_GPIO_A0_NR (8)
23#define S5PV210_GPIO_A1_NR (4) 25#define S5PV210_GPIO_A1_NR (4)
@@ -47,6 +49,10 @@
47#define S5PV210_GPIO_J3_NR (8) 49#define S5PV210_GPIO_J3_NR (8)
48#define S5PV210_GPIO_J4_NR (5) 50#define S5PV210_GPIO_J4_NR (5)
49 51
52#define S5PV210_GPIO_MP01_NR (8)
53#define S5PV210_GPIO_MP02_NR (4)
54#define S5PV210_GPIO_MP03_NR (8)
55
50/* GPIO bank numbers */ 56/* GPIO bank numbers */
51 57
52/* CONFIG_S3C_GPIO_SPACE allows the user to select extra 58/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
@@ -85,6 +91,9 @@ enum s5p_gpio_number {
85 S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), 91 S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
86 S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), 92 S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
87 S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), 93 S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
94 S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
95 S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
96 S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
88}; 97};
89 98
90/* S5PV210 GPIO number definitions */ 99/* S5PV210 GPIO number definitions */
@@ -115,13 +124,16 @@ enum s5p_gpio_number {
115#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) 124#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
116#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) 125#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
117#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) 126#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
127#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
128#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
129#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
118 130
119/* the end of the S5PV210 specific gpios */ 131/* the end of the S5PV210 specific gpios */
120#define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1) 132#define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
121#define S3C_GPIO_END S5PV210_GPIO_END 133#define S3C_GPIO_END S5PV210_GPIO_END
122 134
123/* define the number of gpios we need to the one after the GPJ4() range */ 135/* define the number of gpios we need to the one after the MP03() range */
124#define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \ 136#define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \
125 CONFIG_SAMSUNG_GPIO_EXTRA + 1) 137 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
126 138
127#include <asm-generic/gpio.h> 139#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
index 69027fea987a..f8a9f1b330e0 100644
--- a/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
@@ -1,13 +1,14 @@
1/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h 1/* linux/arch/arm/mach-s5pv210/include/mach/pwm-clock.h
2 * 2 *
3 * Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2008 Openmoko, Inc.
3 * Copyright 2008 Simtec Electronics 7 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 8 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/ 9 * http://armlinux.simtec.co.uk/
6 * 10 *
7 * Copyright (c) 2009 Samsung Electronics Co., Ltd. 11 * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
8 * http://www.samsung.com/
9 *
10 * Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
11 * 12 *
12 * S5PV210 - pwm clock and timer support 13 * S5PV210 - pwm clock and timer support
13 * 14 *
@@ -21,14 +22,14 @@
21 22
22/** 23/**
23 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk 24 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
24 * @cfg: The timer TCFG1 register bits shifted down to 0. 25 * @tcfg: The timer TCFG1 register bits shifted down to 0.
25 * 26 *
26 * Return true if the given configuration from TCFG1 is a TCLK instead 27 * Return true if the given configuration from TCFG1 is a TCLK instead
27 * any of the TDIV clocks. 28 * any of the TDIV clocks.
28 */ 29 */
29static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) 30static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
30{ 31{
31 return tcfg == S3C2410_TCFG1_MUX_TCLK; 32 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
32} 33}
33 34
34/** 35/**
@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
40 */ 41 */
41static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) 42static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
42{ 43{
43 return 1 << (1 + tcfg1); 44 return 1 << tcfg1;
44} 45}
45 46
46/** 47/**
@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
50 */ 51 */
51static inline unsigned int pwm_tdiv_has_div1(void) 52static inline unsigned int pwm_tdiv_has_div1(void)
52{ 53{
53 return 0; 54 return 1;
54} 55}
55 56
56/** 57/**
@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
61 */ 62 */
62static inline unsigned long pwm_tdiv_div_bits(unsigned int div) 63static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
63{ 64{
64 return ilog2(div) - 1; 65 return ilog2(div);
65} 66}
66 67
67#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK 68#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
68 69
69#endif /* __ASM_ARCH_PWMCLK_H */ 70#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 241c24a1c18f..45a1bc275f0a 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -869,9 +869,10 @@ void __init reserve_node_zero(pg_data_t *pgdat)
869 if (machine_is_p720t()) 869 if (machine_is_p720t())
870 res_size = 0x00014000; 870 res_size = 0x00014000;
871 871
872 /* H1940 and RX3715 need to reserve this for suspend */ 872 /* H1940, RX3715 and RX1950 need to reserve this for suspend */
873 873
874 if (machine_is_h1940() || machine_is_rx3715()) { 874 if (machine_is_h1940() || machine_is_rx3715()
875 || machine_is_rx1950()) {
875 reserve_bootmem_node(pgdat, 0x30003000, 0x1000, 876 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
876 BOOTMEM_DEFAULT); 877 BOOTMEM_DEFAULT);
877 reserve_bootmem_node(pgdat, 0x30081000, 0x1000, 878 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 9265f09bfa58..cd5b41d0b5a4 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -21,6 +21,7 @@
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include <linux/string.h>
24 25
25#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
26#include <asm/mach/map.h> 27#include <asm/mach/map.h>
@@ -149,10 +150,14 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
149{ 150{
150 struct s3c2410fb_mach_info *npd; 151 struct s3c2410fb_mach_info *npd;
151 152
152 npd = kmalloc(sizeof(*npd), GFP_KERNEL); 153 npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
153 if (npd) { 154 if (npd) {
154 memcpy(npd, pd, sizeof(*npd));
155 s3c_device_lcd.dev.platform_data = npd; 155 s3c_device_lcd.dev.platform_data = npd;
156 npd->displays = kmemdup(pd->displays,
157 sizeof(struct s3c2410fb_display) * npd->num_displays,
158 GFP_KERNEL);
159 if (!npd->displays)
160 printk(KERN_ERR "no memory for LCD display data\n");
156 } else { 161 } else {
157 printk(KERN_ERR "no memory for LCD platform data\n"); 162 printk(KERN_ERR "no memory for LCD platform data\n");
158 } 163 }
@@ -338,14 +343,6 @@ struct platform_device s3c_device_adc = {
338 .resource = s3c_adc_resource, 343 .resource = s3c_adc_resource,
339}; 344};
340 345
341/* HWMON */
342
343struct platform_device s3c_device_hwmon = {
344 .name = "s3c-hwmon",
345 .id = -1,
346 .dev.parent = &s3c_device_adc.dev,
347};
348
349/* SDI */ 346/* SDI */
350 347
351static struct resource s3c_sdi_resource[] = { 348static struct resource s3c_sdi_resource[] = {
@@ -371,7 +368,7 @@ struct platform_device s3c_device_sdi = {
371 368
372EXPORT_SYMBOL(s3c_device_sdi); 369EXPORT_SYMBOL(s3c_device_sdi);
373 370
374void s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata) 371void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
375{ 372{
376 struct s3c24xx_mci_pdata *npd; 373 struct s3c24xx_mci_pdata *npd;
377 374
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index 93827b3d4e84..6ad274e7593d 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1104,7 +1104,7 @@ EXPORT_SYMBOL(s3c2410_dma_config);
1104 * devaddr: physical address of the source 1104 * devaddr: physical address of the source
1105*/ 1105*/
1106 1106
1107int s3c2410_dma_devconfig(int channel, 1107int s3c2410_dma_devconfig(unsigned int channel,
1108 enum s3c2410_dmasrc source, 1108 enum s3c2410_dmasrc source,
1109 unsigned long devaddr) 1109 unsigned long devaddr)
1110{ 1110{
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c
index 45126d3aafc6..2f3d7c089dfa 100644
--- a/arch/arm/plat-s3c24xx/gpio.c
+++ b/arch/arm/plat-s3c24xx/gpio.c
@@ -34,6 +34,8 @@
34 34
35#include <mach/regs-gpio.h> 35#include <mach/regs-gpio.h>
36 36
37#include <plat/gpio-core.h>
38
37/* gpiolib wrappers until these are totally eliminated */ 39/* gpiolib wrappers until these are totally eliminated */
38 40
39void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) 41void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
@@ -68,10 +70,10 @@ EXPORT_SYMBOL(s3c2410_gpio_setpin);
68 70
69unsigned int s3c2410_gpio_getpin(unsigned int pin) 71unsigned int s3c2410_gpio_getpin(unsigned int pin)
70{ 72{
71 void __iomem *base = S3C24XX_GPIO_BASE(pin); 73 struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
72 unsigned long offs = S3C2410_GPIO_OFFSET(pin); 74 unsigned long offs = pin - chip->chip.base;
73 75
74 return __raw_readl(base + 0x04) & (1<< offs); 76 return __raw_readl(chip->base + 0x04) & (1<< offs);
75} 77}
76 78
77EXPORT_SYMBOL(s3c2410_gpio_getpin); 79EXPORT_SYMBOL(s3c2410_gpio_getpin);
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index aa96e335073b..a8bfabf4b6bc 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -33,6 +33,11 @@ struct clk clk_ext_xtal_mux = {
33 .id = -1, 33 .id = -1,
34}; 34};
35 35
36struct clk clk_xusbxti = {
37 .name = "xusbxti",
38 .id = -1,
39};
40
36static struct clk s5p_clk_27m = { 41static struct clk s5p_clk_27m = {
37 .name = "clk_27m", 42 .name = "clk_27m",
38 .id = -1, 43 .id = -1,
@@ -69,6 +74,13 @@ struct clk clk_fout_epll = {
69 .ctrlbit = (1 << 31), 74 .ctrlbit = (1 << 31),
70}; 75};
71 76
77/* VPLL clock output */
78struct clk clk_fout_vpll = {
79 .name = "fout_vpll",
80 .id = -1,
81 .ctrlbit = (1 << 31),
82};
83
72/* ARM clock */ 84/* ARM clock */
73struct clk clk_arm = { 85struct clk clk_arm = {
74 .name = "armclk", 86 .name = "armclk",
@@ -133,6 +145,7 @@ static struct clk *s5p_clks[] __initdata = {
133 &clk_fout_apll, 145 &clk_fout_apll,
134 &clk_fout_mpll, 146 &clk_fout_mpll,
135 &clk_fout_epll, 147 &clk_fout_epll,
148 &clk_fout_vpll,
136 &clk_arm, 149 &clk_arm,
137 &clk_vpll, 150 &clk_vpll,
138}; 151};
diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
index 42e757f2e40c..9ff3d718be39 100644
--- a/arch/arm/plat-s5p/include/plat/irqs.h
+++ b/arch/arm/plat-s5p/include/plat/irqs.h
@@ -79,7 +79,7 @@
79#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) 79#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
80#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) 80#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
81 81
82#define S5P_TIMER_IRQ(x) S5P_IRQ(11 + (x)) 82#define S5P_TIMER_IRQ(x) (11 + (x))
83 83
84#define IRQ_TIMER0 S5P_TIMER_IRQ(0) 84#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
85#define IRQ_TIMER1 S5P_TIMER_IRQ(1) 85#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 56fb8b414d41..aa0447a18903 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -23,10 +23,12 @@
23#define clk_fin_vpll clk_ext_xtal_mux 23#define clk_fin_vpll clk_ext_xtal_mux
24 24
25extern struct clk clk_ext_xtal_mux; 25extern struct clk clk_ext_xtal_mux;
26extern struct clk clk_xusbxti;
26extern struct clk clk_48m; 27extern struct clk clk_48m;
27extern struct clk clk_fout_apll; 28extern struct clk clk_fout_apll;
28extern struct clk clk_fout_mpll; 29extern struct clk clk_fout_mpll;
29extern struct clk clk_fout_epll; 30extern struct clk clk_fout_epll;
31extern struct clk clk_fout_vpll;
30extern struct clk clk_arm; 32extern struct clk clk_arm;
31extern struct clk clk_vpll; 33extern struct clk clk_vpll;
32 34
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index d552c65fa1b0..7a36cf85e138 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2
160 help 160 help
161 Compile in platform device definitions for HSMMC channel 2 161 Compile in platform device definitions for HSMMC channel 2
162 162
163config S3C_DEV_HWMON
164 bool
165 help
166 Compile in platform device definitions for HWMON
167
163config S3C_DEV_I2C1 168config S3C_DEV_I2C1
164 bool 169 bool
165 help 170 help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 22c89d08f6e5..0ad820acc385 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC) += adc.o
33obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o 33obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o
34obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o 34obj-$(CONFIG_S3C_DEV_HSMMC1) += dev-hsmmc1.o
35obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o 35obj-$(CONFIG_S3C_DEV_HSMMC2) += dev-hsmmc2.o
36obj-$(CONFIG_S3C_DEV_HWMON) += dev-hwmon.o
36obj-y += dev-i2c0.o 37obj-y += dev-i2c0.o
37obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o 38obj-$(CONFIG_S3C_DEV_I2C1) += dev-i2c1.o
38obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o 39obj-$(CONFIG_S3C_DEV_FB) += dev-fb.o
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c
new file mode 100644
index 000000000000..b3ffb9587250
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hwmon.c
@@ -0,0 +1,42 @@
1/* linux/arch/arm/plat-samsung/dev-hwmon.c
2 *
3 * Copyright 2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * Adapted for HWMON by Maurus Cuelenaere
8 *
9 * Samsung series device definition for HWMON
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#include <linux/kernel.h>
17#include <linux/platform_device.h>
18
19#include <plat/devs.h>
20#include <plat/hwmon.h>
21
22struct platform_device s3c_device_hwmon = {
23 .name = "s3c-hwmon",
24 .id = -1,
25 .dev.parent = &s3c_device_adc.dev,
26};
27
28void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
29{
30 struct s3c_hwmon_pdata *npd;
31
32 if (!pd) {
33 printk(KERN_ERR "%s: no platform data\n", __func__);
34 return;
35 }
36
37 npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL);
38 if (!npd)
39 printk(KERN_ERR "%s: no memory for platform data\n", __func__);
40
41 s3c_device_hwmon.dev.platform_data = npd;
42}
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c
index 3282db360fa8..a76eef533392 100644
--- a/arch/arm/plat-samsung/gpio-config.c
+++ b/arch/arm/plat-samsung/gpio-config.c
@@ -33,9 +33,9 @@ int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
33 33
34 offset = pin - chip->chip.base; 34 offset = pin - chip->chip.base;
35 35
36 local_irq_save(flags); 36 s3c_gpio_lock(chip, flags);
37 ret = s3c_gpio_do_setcfg(chip, offset, config); 37 ret = s3c_gpio_do_setcfg(chip, offset, config);
38 local_irq_restore(flags); 38 s3c_gpio_unlock(chip, flags);
39 39
40 return ret; 40 return ret;
41} 41}
@@ -51,9 +51,9 @@ unsigned s3c_gpio_getcfg(unsigned int pin)
51 if (chip) { 51 if (chip) {
52 offset = pin - chip->chip.base; 52 offset = pin - chip->chip.base;
53 53
54 local_irq_save(flags); 54 s3c_gpio_lock(chip, flags);
55 ret = s3c_gpio_do_getcfg(chip, offset); 55 ret = s3c_gpio_do_getcfg(chip, offset);
56 local_irq_restore(flags); 56 s3c_gpio_unlock(chip, flags);
57 } 57 }
58 58
59 return ret; 59 return ret;
@@ -72,9 +72,9 @@ int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull)
72 72
73 offset = pin - chip->chip.base; 73 offset = pin - chip->chip.base;
74 74
75 local_irq_save(flags); 75 s3c_gpio_lock(chip, flags);
76 ret = s3c_gpio_do_setpull(chip, offset, pull); 76 ret = s3c_gpio_do_setpull(chip, offset, pull);
77 local_irq_restore(flags); 77 s3c_gpio_unlock(chip, flags);
78 78
79 return ret; 79 return ret;
80} 80}
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c
index 28d2ab8a08db..b83a83351cea 100644
--- a/arch/arm/plat-samsung/gpio.c
+++ b/arch/arm/plat-samsung/gpio.c
@@ -15,6 +15,7 @@
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/gpio.h> 17#include <linux/gpio.h>
18#include <linux/spinlock.h>
18 19
19#include <plat/gpio-core.h> 20#include <plat/gpio-core.h>
20 21
@@ -52,14 +53,14 @@ static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset)
52 unsigned long flags; 53 unsigned long flags;
53 unsigned long con; 54 unsigned long con;
54 55
55 local_irq_save(flags); 56 s3c_gpio_lock(ourchip, flags);
56 57
57 con = __raw_readl(base + 0x00); 58 con = __raw_readl(base + 0x00);
58 con &= ~(3 << (offset * 2)); 59 con &= ~(3 << (offset * 2));
59 60
60 __raw_writel(con, base + 0x00); 61 __raw_writel(con, base + 0x00);
61 62
62 local_irq_restore(flags); 63 s3c_gpio_unlock(ourchip, flags);
63 return 0; 64 return 0;
64} 65}
65 66
@@ -72,7 +73,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
72 unsigned long dat; 73 unsigned long dat;
73 unsigned long con; 74 unsigned long con;
74 75
75 local_irq_save(flags); 76 s3c_gpio_lock(ourchip, flags);
76 77
77 dat = __raw_readl(base + 0x04); 78 dat = __raw_readl(base + 0x04);
78 dat &= ~(1 << offset); 79 dat &= ~(1 << offset);
@@ -87,7 +88,7 @@ static int s3c_gpiolib_output(struct gpio_chip *chip,
87 __raw_writel(con, base + 0x00); 88 __raw_writel(con, base + 0x00);
88 __raw_writel(dat, base + 0x04); 89 __raw_writel(dat, base + 0x04);
89 90
90 local_irq_restore(flags); 91 s3c_gpio_unlock(ourchip, flags);
91 return 0; 92 return 0;
92} 93}
93 94
@@ -99,7 +100,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
99 unsigned long flags; 100 unsigned long flags;
100 unsigned long dat; 101 unsigned long dat;
101 102
102 local_irq_save(flags); 103 s3c_gpio_lock(ourchip, flags);
103 104
104 dat = __raw_readl(base + 0x04); 105 dat = __raw_readl(base + 0x04);
105 dat &= ~(1 << offset); 106 dat &= ~(1 << offset);
@@ -107,7 +108,7 @@ static void s3c_gpiolib_set(struct gpio_chip *chip,
107 dat |= 1 << offset; 108 dat |= 1 << offset;
108 __raw_writel(dat, base + 0x04); 109 __raw_writel(dat, base + 0x04);
109 110
110 local_irq_restore(flags); 111 s3c_gpio_unlock(ourchip, flags);
111} 112}
112 113
113static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) 114static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset)
@@ -131,6 +132,8 @@ __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip)
131 BUG_ON(!gc->label); 132 BUG_ON(!gc->label);
132 BUG_ON(!gc->ngpio); 133 BUG_ON(!gc->ngpio);
133 134
135 spin_lock_init(&chip->lock);
136
134 if (!gc->direction_input) 137 if (!gc->direction_input)
135 gc->direction_input = s3c_gpiolib_input; 138 gc->direction_input = s3c_gpiolib_input;
136 if (!gc->direction_output) 139 if (!gc->direction_output)
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 12caf48a6bdc..0fbcd0effd8e 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -74,6 +74,7 @@ extern struct clk clk_ext;
74extern struct clk clk_h2; 74extern struct clk clk_h2;
75extern struct clk clk_27m; 75extern struct clk clk_27m;
76extern struct clk clk_48m; 76extern struct clk clk_48m;
77extern struct clk clk_xusbxti;
77 78
78extern int clk_default_setrate(struct clk *clk, unsigned long rate); 79extern int clk_default_setrate(struct clk *clk, unsigned long rate);
79extern struct clk_ops clk_ops_def_setrate; 80extern struct clk_ops clk_ops_def_setrate;
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5dbeb7991e60..6412933d6fbb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -79,6 +79,9 @@ extern struct sysdev_class s3c2442_sysclass;
79extern struct sysdev_class s3c2443_sysclass; 79extern struct sysdev_class s3c2443_sysclass;
80extern struct sysdev_class s3c6410_sysclass; 80extern struct sysdev_class s3c6410_sysclass;
81extern struct sysdev_class s3c64xx_sysclass; 81extern struct sysdev_class s3c64xx_sysclass;
82extern struct sysdev_class s5p6440_sysclass;
83extern struct sysdev_class s5p6442_sysclass;
84extern struct sysdev_class s5pv210_sysclass;
82 85
83extern void (*s5pc1xx_idle)(void); 86extern void (*s5pc1xx_idle)(void);
84 87
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 7584d751ed51..2e8f8c6560d7 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -110,8 +110,8 @@ extern int s3c2410_dma_config(unsigned int channel, int xferunit);
110 * configure the device we're talking to 110 * configure the device we're talking to
111*/ 111*/
112 112
113extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source, 113extern int s3c2410_dma_devconfig(unsigned int channel,
114 unsigned long devaddr); 114 enum s3c2410_dmasrc source, unsigned long devaddr);
115 115
116/* s3c2410_dma_getposition 116/* s3c2410_dma_getposition
117 * 117 *
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index f0584f26d493..f3a68d1a07b9 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -44,16 +44,26 @@ struct s3c_gpio_cfg;
44 * @chip: The chip structure to be exported via gpiolib. 44 * @chip: The chip structure to be exported via gpiolib.
45 * @base: The base pointer to the gpio configuration registers. 45 * @base: The base pointer to the gpio configuration registers.
46 * @config: special function and pull-resistor control information. 46 * @config: special function and pull-resistor control information.
47 * @lock: Lock for exclusive access to this gpio bank.
47 * @pm_save: Save information for suspend/resume support. 48 * @pm_save: Save information for suspend/resume support.
48 * 49 *
49 * This wrapper provides the necessary information for the Samsung 50 * This wrapper provides the necessary information for the Samsung
50 * specific gpios being registered with gpiolib. 51 * specific gpios being registered with gpiolib.
52 *
53 * The lock protects each gpio bank from multiple access of the shared
54 * configuration registers, or from reading of data whilst another thread
55 * is writing to the register set.
56 *
57 * Each chip has its own lock to avoid any contention between different
58 * CPU cores trying to get one lock for different GPIO banks, where each
59 * bank of GPIO has its own register space and configuration registers.
51 */ 60 */
52struct s3c_gpio_chip { 61struct s3c_gpio_chip {
53 struct gpio_chip chip; 62 struct gpio_chip chip;
54 struct s3c_gpio_cfg *config; 63 struct s3c_gpio_cfg *config;
55 struct s3c_gpio_pm *pm; 64 struct s3c_gpio_pm *pm;
56 void __iomem *base; 65 void __iomem *base;
66 spinlock_t lock;
57#ifdef CONFIG_PM 67#ifdef CONFIG_PM
58 u32 pm_save[4]; 68 u32 pm_save[4];
59#endif 69#endif
@@ -138,3 +148,7 @@ extern struct s3c_gpio_pm s3c_gpio_pm_4bit;
138#define __gpio_pm(x) NULL 148#define __gpio_pm(x) NULL
139 149
140#endif /* CONFIG_PM */ 150#endif /* CONFIG_PM */
151
152/* locking wrappers to deal with multiple access to the same gpio bank */
153#define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl)
154#define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl)
diff --git a/arch/arm/plat-samsung/include/plat/hwmon.h b/arch/arm/plat-samsung/include/plat/hwmon.h
index 1ba88ea0aa31..c167e4429bc7 100644
--- a/arch/arm/plat-samsung/include/plat/hwmon.h
+++ b/arch/arm/plat-samsung/include/plat/hwmon.h
@@ -37,5 +37,15 @@ struct s3c_hwmon_pdata {
37 struct s3c_hwmon_chcfg *in[8]; 37 struct s3c_hwmon_chcfg *in[8];
38}; 38};
39 39
40/**
41 * s3c_hwmon_set_platdata - Set platform data for S3C HWMON device
42 * @pd: Platform data to register to device.
43 *
44 * Register the given platform data for use with the S3C HWMON device.
45 * The call will copy the platform data, so the board definitions can
46 * make the structure itself __initdata.
47 */
48extern void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd);
49
40#endif /* __ASM_ARCH_ADC_HWMON_H */ 50#endif /* __ASM_ARCH_ADC_HWMON_H */
41 51
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 69a4c7f02e25..d50ab9d2af53 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -329,7 +329,7 @@ void s3c_pm_save_gpios(void)
329 struct s3c_gpio_chip *ourchip; 329 struct s3c_gpio_chip *ourchip;
330 unsigned int gpio_nr; 330 unsigned int gpio_nr;
331 331
332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { 332 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
333 ourchip = s3c_gpiolib_getchip(gpio_nr); 333 ourchip = s3c_gpiolib_getchip(gpio_nr);
334 if (!ourchip) 334 if (!ourchip)
335 continue; 335 continue;
@@ -367,7 +367,7 @@ void s3c_pm_restore_gpios(void)
367 struct s3c_gpio_chip *ourchip; 367 struct s3c_gpio_chip *ourchip;
368 unsigned int gpio_nr; 368 unsigned int gpio_nr;
369 369
370 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END; gpio_nr++) { 370 for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) {
371 ourchip = s3c_gpiolib_getchip(gpio_nr); 371 ourchip = s3c_gpiolib_getchip(gpio_nr);
372 if (!ourchip) 372 if (!ourchip)
373 continue; 373 continue;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-11 01:50:05 -0500