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-rw-r--r--arch/mips/include/asm/mach-loongson/loongson.h182
-rw-r--r--arch/mips/include/asm/mach-loongson/machine.h2
-rw-r--r--arch/mips/include/asm/mach-loongson/pci.h6
-rw-r--r--arch/mips/include/asm/mips-boards/bonito64.h5
-rw-r--r--arch/mips/loongson/common/bonito-irq.c8
-rw-r--r--arch/mips/loongson/common/init.c2
-rw-r--r--arch/mips/loongson/common/irq.c12
-rw-r--r--arch/mips/loongson/common/pci.c12
-rw-r--r--arch/mips/loongson/common/reset.c2
-rw-r--r--arch/mips/loongson/fuloong-2e/irq.c4
-rw-r--r--arch/mips/loongson/fuloong-2e/reset.c4
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-fuloong2e.c5
-rw-r--r--arch/mips/pci/ops-bonito64.c7
-rw-r--r--arch/mips/pci/ops-fuloong2e.c154
15 files changed, 352 insertions, 55 deletions
diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h
index da70bcf2304e..e6869aa52bc8 100644
--- a/arch/mips/include/asm/mach-loongson/loongson.h
+++ b/arch/mips/include/asm/mach-loongson/loongson.h
@@ -15,9 +15,6 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */
19#include <asm/mips-boards/bonito64.h>
20
21/* loongson internal northbridge initialization */ 18/* loongson internal northbridge initialization */
22extern void bonito_irq_init(void); 19extern void bonito_irq_init(void);
23 20
@@ -41,24 +38,181 @@ extern void __init set_irq_trigger_mode(void);
41extern void __init mach_init_irq(void); 38extern void __init mach_init_irq(void);
42extern void mach_irq_dispatch(unsigned int pending); 39extern void mach_irq_dispatch(unsigned int pending);
43 40
41#define LOONGSON_REG(x) \
42 (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x)))
43
44#define LOONGSON_IRQ_BASE 32
45#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */
46
47#define LOONGSON_FLASH_BASE 0x1c000000
48#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */
49#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1)
50
51#define LOONGSON_LIO0_BASE 0x1e000000
52#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */
53#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1)
54
55#define LOONGSON_BOOT_BASE 0x1fc00000
56#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */
57#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1)
58#define LOONGSON_REG_BASE 0x1fe00000
59#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */
60#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1)
61
62#define LOONGSON_LIO1_BASE 0x1ff00000
63#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */
64#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1)
65
66#define LOONGSON_PCILO0_BASE 0x10000000
67#define LOONGSON_PCILO1_BASE 0x14000000
68#define LOONGSON_PCILO2_BASE 0x18000000
69#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE
70#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */
71#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1)
72
73#define LOONGSON_PCICFG_BASE 0x1fe80000
74#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */
75#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1)
76#define LOONGSON_PCIIO_BASE 0x1fd00000
77#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */
78#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1)
79
80/* Loongson Register Bases */
81
82#define LOONGSON_PCICONFIGBASE 0x00
83#define LOONGSON_REGBASE 0x100
84
44/* PCI Configuration Registers */ 85/* PCI Configuration Registers */
45#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) 86
87#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x))
88#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00)
89#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04)
90#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08)
91#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c)
92#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10)
93#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14)
94#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18)
95#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c)
96#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20)
97#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30)
98#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c)
99
100#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c)
101
102#define LOONGSON_PCICMD_PERR_CLR 0x80000000
103#define LOONGSON_PCICMD_SERR_CLR 0x40000000
104#define LOONGSON_PCICMD_MABORT_CLR 0x20000000
105#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000
106#define LOONGSON_PCICMD_TABORT_CLR 0x08000000
107#define LOONGSON_PCICMD_MPERR_CLR 0x01000000
108#define LOONGSON_PCICMD_PERRRESPEN 0x00000040
109#define LOONGSON_PCICMD_ASTEPEN 0x00000080
110#define LOONGSON_PCICMD_SERREN 0x00000100
111#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00
112#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8
113
114/* Loongson h/w Configuration */
115
116#define LOONGSON_GENCFG_OFFSET 0x4
117#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET)
118
119#define LOONGSON_GENCFG_DEBUGMODE 0x00000001
120#define LOONGSON_GENCFG_SNOOPEN 0x00000002
121#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004
122
123#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008
124#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010
125#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020
126#define LOONGSON_GENCFG_BYTESWAP 0x00000040
127
128#define LOONGSON_GENCFG_UNCACHED 0x00000080
129#define LOONGSON_GENCFG_PREFETCHEN 0x00000100
130#define LOONGSON_GENCFG_WBEHINDEN 0x00000200
131#define LOONGSON_GENCFG_CACHEALG 0x00000c00
132#define LOONGSON_GENCFG_CACHEALG_SHIFT 10
133#define LOONGSON_GENCFG_PCIQUEUE 0x00001000
134#define LOONGSON_GENCFG_CACHESTOP 0x00002000
135#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000
136#define LOONGSON_GENCFG_BUSERREN 0x00008000
137#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000
138#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000
139
140/* PCI address map control */
141
142#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10)
143#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14)
144#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18)
145
146/* GPIO Regs - r/w */
147
148#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c)
149#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20)
150
151/* ICU Configuration Regs - r/w */
152
153#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24)
154#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28)
155#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c)
156
157/* ICU Enable Regs - IntEn & IntISR are r/o. */
158
159#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30)
160#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34)
161#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38)
162#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c)
163
164/* ICU */
165#define LOONGSON_ICU_MBOXES 0x0000000f
166#define LOONGSON_ICU_MBOXES_SHIFT 0
167#define LOONGSON_ICU_DMARDY 0x00000010
168#define LOONGSON_ICU_DMAEMPTY 0x00000020
169#define LOONGSON_ICU_COPYRDY 0x00000040
170#define LOONGSON_ICU_COPYEMPTY 0x00000080
171#define LOONGSON_ICU_COPYERR 0x00000100
172#define LOONGSON_ICU_PCIIRQ 0x00000200
173#define LOONGSON_ICU_MASTERERR 0x00000400
174#define LOONGSON_ICU_SYSTEMERR 0x00000800
175#define LOONGSON_ICU_DRAMPERR 0x00001000
176#define LOONGSON_ICU_RETRYERR 0x00002000
177#define LOONGSON_ICU_GPIOS 0x01ff0000
178#define LOONGSON_ICU_GPIOS_SHIFT 16
179#define LOONGSON_ICU_GPINS 0x7e000000
180#define LOONGSON_ICU_GPINS_SHIFT 25
181#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N)))
182#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N)))
183#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N)))
184
185/* PCI prefetch window base & mask */
186
187#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40)
188#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44)
189#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48)
190#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c)
46 191
47/* PCI_Hit*_Sel_* */ 192/* PCI_Hit*_Sel_* */
48 193
49#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) 194#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50)
50#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) 195#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54)
51#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) 196#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58)
52#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) 197#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c)
53#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) 198#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60)
54#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) 199#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64)
55 200
56/* PXArb Config & Status */ 201/* PXArb Config & Status */
57 202
58#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) 203#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68)
59#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) 204#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c)
205
206/* pcimap */
60 207
61/* loongson2-specific perf counter IRQ */ 208#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f
62#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) 209#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0
210#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0
211#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6
212#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000
213#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12
214#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000
215#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \
216 ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
63 217
64#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ 218#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */
diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h
index 206ea2067916..ea5954c4b221 100644
--- a/arch/mips/include/asm/mach-loongson/machine.h
+++ b/arch/mips/include/asm/mach-loongson/machine.h
@@ -13,7 +13,7 @@
13 13
14#ifdef CONFIG_LEMOTE_FULOONG2E 14#ifdef CONFIG_LEMOTE_FULOONG2E
15 15
16#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8) 16#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x3f8)
17 17
18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E 18#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E
19 19
diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h
index f1663ca81da0..576487c00470 100644
--- a/arch/mips/include/asm/mach-loongson/pci.h
+++ b/arch/mips/include/asm/mach-loongson/pci.h
@@ -22,13 +22,13 @@
22#ifndef __ASM_MACH_LOONGSON_PCI_H_ 22#ifndef __ASM_MACH_LOONGSON_PCI_H_
23#define __ASM_MACH_LOONGSON_PCI_H_ 23#define __ASM_MACH_LOONGSON_PCI_H_
24 24
25extern struct pci_ops bonito64_pci_ops; 25extern struct pci_ops loongson_pci_ops;
26 26
27#ifdef CONFIG_LEMOTE_FULOONG2E 27#ifdef CONFIG_LEMOTE_FULOONG2E
28 28
29/* this pci memory space is mapped by pcimap in pci.c */ 29/* this pci memory space is mapped by pcimap in pci.c */
30#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE 30#define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE
31#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) 31#define LOONGSON_PCI_MEM_END (LOONGSON_PCILO1_BASE + 0x04000000 * 2)
32/* this is an offset from mips_io_port_base */ 32/* this is an offset from mips_io_port_base */
33#define LOONGSON_PCI_IO_START 0x00004000UL 33#define LOONGSON_PCI_IO_START 0x00004000UL
34 34
diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h
index a576ce044c3c..d14e2adc4be5 100644
--- a/arch/mips/include/asm/mips-boards/bonito64.h
+++ b/arch/mips/include/asm/mips-boards/bonito64.h
@@ -26,11 +26,6 @@
26/* offsets from base register */ 26/* offsets from base register */
27#define BONITO(x) (x) 27#define BONITO(x) (x)
28 28
29#elif defined(CONFIG_LEMOTE_FULOONG2E)
30
31#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
32#define BONITO_IRQ_BASE 32
33
34#else 29#else
35 30
36/* 31/*
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 3e31e7ad713e..a1cbd110a6e4 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -17,13 +17,13 @@
17 17
18static inline void bonito_irq_enable(unsigned int irq) 18static inline void bonito_irq_enable(unsigned int irq)
19{ 19{
20 BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); 20 LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE));
21 mmiowb(); 21 mmiowb();
22} 22}
23 23
24static inline void bonito_irq_disable(unsigned int irq) 24static inline void bonito_irq_disable(unsigned int irq)
25{ 25{
26 BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); 26 LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE));
27 mmiowb(); 27 mmiowb();
28} 28}
29 29
@@ -44,8 +44,8 @@ void bonito_irq_init(void)
44{ 44{
45 u32 i; 45 u32 i;
46 46
47 for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) 47 for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); 48 set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
49 49
50 setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); 50 setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
51} 51}
diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c
index 3abe927422a3..b7e4913627ab 100644
--- a/arch/mips/loongson/common/init.c
+++ b/arch/mips/loongson/common/init.c
@@ -18,7 +18,7 @@ void __init prom_init(void)
18{ 18{
19 /* init base address of io space */ 19 /* init base address of io space */
20 set_io_port_base((unsigned long) 20 set_io_port_base((unsigned long)
21 ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); 21 ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE));
22 22
23 prom_init_cmdline(); 23 prom_init_cmdline();
24 prom_init_env(); 24 prom_init_env();
diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c
index b32b4a3e5137..20e732831978 100644
--- a/arch/mips/loongson/common/irq.c
+++ b/arch/mips/loongson/common/irq.c
@@ -20,21 +20,21 @@ void bonito_irqdispatch(void)
20 int i; 20 int i;
21 21
22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */ 22 /* workaround the IO dma problem: let cpu looping to allow DMA finish */
23 int_status = BONITO_INTISR; 23 int_status = LOONGSON_INTISR;
24 if (int_status & (1 << 10)) { 24 if (int_status & (1 << 10)) {
25 while (int_status & (1 << 10)) { 25 while (int_status & (1 << 10)) {
26 udelay(1); 26 udelay(1);
27 int_status = BONITO_INTISR; 27 int_status = LOONGSON_INTISR;
28 } 28 }
29 } 29 }
30 30
31 /* Get pending sources, masked by current enables */ 31 /* Get pending sources, masked by current enables */
32 int_status = BONITO_INTISR & BONITO_INTEN; 32 int_status = LOONGSON_INTISR & LOONGSON_INTEN;
33 33
34 if (int_status != 0) { 34 if (int_status != 0) {
35 i = __ffs(int_status); 35 i = __ffs(int_status);
36 int_status &= ~(1 << i); 36 int_status &= ~(1 << i);
37 do_IRQ(BONITO_IRQ_BASE + i); 37 do_IRQ(LOONGSON_IRQ_BASE + i);
38 } 38 }
39} 39}
40 40
@@ -60,13 +60,13 @@ void __init arch_init_irq(void)
60 set_irq_trigger_mode(); 60 set_irq_trigger_mode();
61 61
62 /* no steer */ 62 /* no steer */
63 BONITO_INTSTEER = 0; 63 LOONGSON_INTSTEER = 0;
64 64
65 /* 65 /*
66 * Mask out all interrupt by writing "1" to all bit position in 66 * Mask out all interrupt by writing "1" to all bit position in
67 * the interrupt reset reg. 67 * the interrupt reset reg.
68 */ 68 */
69 BONITO_INTENCLR = ~0; 69 LOONGSON_INTENCLR = ~0;
70 70
71 /* machine specific irq init */ 71 /* machine specific irq init */
72 mach_init_irq(); 72 mach_init_irq();
diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c
index a3a4abfb6c9a..a7eb8b9c44ee 100644
--- a/arch/mips/loongson/common/pci.c
+++ b/arch/mips/loongson/common/pci.c
@@ -27,7 +27,7 @@ static struct resource loongson_pci_io_resource = {
27}; 27};
28 28
29static struct pci_controller loongson_pci_controller = { 29static struct pci_controller loongson_pci_controller = {
30 .pci_ops = &bonito64_pci_ops, 30 .pci_ops = &loongson_pci_ops,
31 .io_resource = &loongson_pci_io_resource, 31 .io_resource = &loongson_pci_io_resource,
32 .mem_resource = &loongson_pci_mem_resource, 32 .mem_resource = &loongson_pci_mem_resource,
33 .mem_offset = 0x00000000UL, 33 .mem_offset = 0x00000000UL,
@@ -44,15 +44,15 @@ static void __init setup_pcimap(void)
44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 44 * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0
45 * [<2G] [384M,448M] [320M,384M] [0M,64M] 45 * [<2G] [384M,448M] [320M,384M] [0M,64M]
46 */ 46 */
47 BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | 47 LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 |
48 BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | 48 LOONGSON_PCIMAP_WIN(2, LOONGSON_PCILO2_BASE) |
49 BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | 49 LOONGSON_PCIMAP_WIN(1, LOONGSON_PCILO1_BASE) |
50 BONITO_PCIMAP_WIN(0, 0); 50 LOONGSON_PCIMAP_WIN(0, 0);
51 51
52 /* 52 /*
53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] 53 * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M]
54 */ 54 */
55 BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ 55 LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */
56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */ 56 /* size: 256M, burst transmission, pre-fetch enable, 64bit */
57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; 57 LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul;
58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; 58 LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful;
diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c
index 97e918251edd..d57f1719da95 100644
--- a/arch/mips/loongson/common/reset.c
+++ b/arch/mips/loongson/common/reset.c
@@ -22,7 +22,7 @@ static void loongson_restart(char *command)
22 mach_prepare_reboot(); 22 mach_prepare_reboot();
23 23
24 /* reboot via jumping to boot base address */ 24 /* reboot via jumping to boot base address */
25 ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); 25 ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) ();
26} 26}
27 27
28static void loongson_halt(void) 28static void loongson_halt(void)
diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c
index 7888cf69424a..320e9379bdd7 100644
--- a/arch/mips/loongson/fuloong-2e/irq.c
+++ b/arch/mips/loongson/fuloong-2e/irq.c
@@ -47,8 +47,8 @@ static struct irqaction cascade_irqaction = {
47void __init set_irq_trigger_mode(void) 47void __init set_irq_trigger_mode(void)
48{ 48{
49 /* most bonito irq should be level triggered */ 49 /* most bonito irq should be level triggered */
50 BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | 50 LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
51 BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; 51 LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
52} 52}
53 53
54void __init mach_init_irq(void) 54void __init mach_init_irq(void)
diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c
index 677fe186db95..fc16c677d476 100644
--- a/arch/mips/loongson/fuloong-2e/reset.c
+++ b/arch/mips/loongson/fuloong-2e/reset.c
@@ -14,8 +14,8 @@
14 14
15void mach_prepare_reboot(void) 15void mach_prepare_reboot(void)
16{ 16{
17 BONITO_BONGENCFG &= ~(1 << 2); 17 LOONGSON_GENCFG &= ~(1 << 2);
18 BONITO_BONGENCFG |= (1 << 2); 18 LOONGSON_GENCFG |= (1 << 2);
19} 19}
20 20
21void mach_prepare_shutdown(void) 21void mach_prepare_shutdown(void)
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 91bfe73a7f60..0610c869852d 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 28obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o 29obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o
30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o 30obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o
31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o 31obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o
32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o 32obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o
33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o 33obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o 34obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c
index 0c4c7a81213f..4f6d8da07f93 100644
--- a/arch/mips/pci/fixup-fuloong2e.c
+++ b/arch/mips/pci/fixup-fuloong2e.c
@@ -13,7 +13,8 @@
13 */ 13 */
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include <asm/mips-boards/bonito64.h> 16
17#include <loongson.h>
17 18
18/* South bridge slot number is set by the pci probe process */ 19/* South bridge slot number is set by the pci probe process */
19static u8 sb_slot = 5; 20static u8 sb_slot = 5;
@@ -35,7 +36,7 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
35 break; 36 break;
36 } 37 }
37 } else { 38 } else {
38 irq = BONITO_IRQ_BASE + 25 + pin; 39 irq = LOONGSON_IRQ_BASE + 25 + pin;
39 } 40 }
40 return irq; 41 return irq;
41 42
diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c
index 54e55e7a2431..1b3e03f20c54 100644
--- a/arch/mips/pci/ops-bonito64.c
+++ b/arch/mips/pci/ops-bonito64.c
@@ -29,13 +29,8 @@
29#define PCI_ACCESS_READ 0 29#define PCI_ACCESS_READ 0
30#define PCI_ACCESS_WRITE 1 30#define PCI_ACCESS_WRITE 1
31 31
32#ifdef CONFIG_LEMOTE_FULOONG2E
33#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset))
34#define ID_SEL_BEGIN 11
35#else
36#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) 32#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset))
37#define ID_SEL_BEGIN 10 33#define ID_SEL_BEGIN 10
38#endif
39#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) 34#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
40 35
41 36
@@ -77,10 +72,8 @@ static int bonito64_pcibios_config_access(unsigned char access_type,
77 addrp = CFG_SPACE_REG(addr & 0xffff); 72 addrp = CFG_SPACE_REG(addr & 0xffff);
78 if (access_type == PCI_ACCESS_WRITE) { 73 if (access_type == PCI_ACCESS_WRITE) {
79 writel(cpu_to_le32(*data), addrp); 74 writel(cpu_to_le32(*data), addrp);
80#ifndef CONFIG_LEMOTE_FULOONG2E
81 /* Wait till done */ 75 /* Wait till done */
82 while (BONITO_PCIMSTAT & 0xF); 76 while (BONITO_PCIMSTAT & 0xF);
83#endif
84 } else { 77 } else {
85 *data = le32_to_cpu(readl(addrp)); 78 *data = le32_to_cpu(readl(addrp));
86 } 79 }
diff --git a/arch/mips/pci/ops-fuloong2e.c b/arch/mips/pci/ops-fuloong2e.c
new file mode 100644
index 000000000000..171f65c99ca1
--- /dev/null
+++ b/arch/mips/pci/ops-fuloong2e.c
@@ -0,0 +1,154 @@
1/*
2 * fuloong2e specific PCI support.
3 *
4 * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
5 * All rights reserved.
6 * Authors: Carsten Langgaard <carstenl@mips.com>
7 * Maciej W. Rozycki <macro@mips.com>
8 *
9 * Copyright (C) 2009 Lemote Inc.
10 * Author: Wu Zhangjin <wuzj@lemote.com>
11 *
12 * This program is free software; you can distribute it and/or modify it
13 * under the terms of the GNU General Public License (Version 2) as
14 * published by the Free Software Foundation.
15 */
16#include <linux/types.h>
17#include <linux/pci.h>
18#include <linux/kernel.h>
19#include <linux/init.h>
20
21#include <loongson.h>
22
23#define PCI_ACCESS_READ 0
24#define PCI_ACCESS_WRITE 1
25
26#define CFG_SPACE_REG(offset) \
27 (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset))
28#define ID_SEL_BEGIN 11
29#define MAX_DEV_NUM (31 - ID_SEL_BEGIN)
30
31
32static int loongson_pcibios_config_access(unsigned char access_type,
33 struct pci_bus *bus,
34 unsigned int devfn, int where,
35 u32 *data)
36{
37 u32 busnum = bus->number;
38 u32 addr, type;
39 u32 dummy;
40 void *addrp;
41 int device = PCI_SLOT(devfn);
42 int function = PCI_FUNC(devfn);
43 int reg = where & ~3;
44
45 if (busnum == 0) {
46 /* Type 0 configuration for onboard PCI bus */
47 if (device > MAX_DEV_NUM)
48 return -1;
49
50 addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg;
51 type = 0;
52 } else {
53 /* Type 1 configuration for offboard PCI bus */
54 addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
55 type = 0x10000;
56 }
57
58 /* Clear aborts */
59 LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \
60 LOONGSON_PCICMD_MTABORT_CLR;
61
62 LOONGSON_PCIMAP_CFG = (addr >> 16) | type;
63
64 /* Flush Bonito register block */
65 dummy = LOONGSON_PCIMAP_CFG;
66 mmiowb();
67
68 addrp = CFG_SPACE_REG(addr & 0xffff);
69 if (access_type == PCI_ACCESS_WRITE)
70 writel(cpu_to_le32(*data), addrp);
71 else
72 *data = le32_to_cpu(readl(addrp));
73
74 /* Detect Master/Target abort */
75 if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR |
76 LOONGSON_PCICMD_MTABORT_CLR)) {
77 /* Error occurred */
78
79 /* Clear bits */
80 LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR |
81 LOONGSON_PCICMD_MTABORT_CLR);
82
83 return -1;
84 }
85
86 return 0;
87
88}
89
90
91/*
92 * We can't address 8 and 16 bit words directly. Instead we have to
93 * read/write a 32bit word and mask/modify the data we actually want.
94 */
95static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn,
96 int where, int size, u32 *val)
97{
98 u32 data = 0;
99
100 if ((size == 2) && (where & 1))
101 return PCIBIOS_BAD_REGISTER_NUMBER;
102 else if ((size == 4) && (where & 3))
103 return PCIBIOS_BAD_REGISTER_NUMBER;
104
105 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
106 &data))
107 return -1;
108
109 if (size == 1)
110 *val = (data >> ((where & 3) << 3)) & 0xff;
111 else if (size == 2)
112 *val = (data >> ((where & 3) << 3)) & 0xffff;
113 else
114 *val = data;
115
116 return PCIBIOS_SUCCESSFUL;
117}
118
119static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn,
120 int where, int size, u32 val)
121{
122 u32 data = 0;
123
124 if ((size == 2) && (where & 1))
125 return PCIBIOS_BAD_REGISTER_NUMBER;
126 else if ((size == 4) && (where & 3))
127 return PCIBIOS_BAD_REGISTER_NUMBER;
128
129 if (size == 4)
130 data = val;
131 else {
132 if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
133 where, &data))
134 return -1;
135
136 if (size == 1)
137 data = (data & ~(0xff << ((where & 3) << 3))) |
138 (val << ((where & 3) << 3));
139 else if (size == 2)
140 data = (data & ~(0xffff << ((where & 3) << 3))) |
141 (val << ((where & 3) << 3));
142 }
143
144 if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
145 &data))
146 return -1;
147
148 return PCIBIOS_SUCCESSFUL;
149}
150
151struct pci_ops loongson_pci_ops = {
152 .read = loongson_pcibios_read,
153 .write = loongson_pcibios_write
154};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 17:35:22 -0500