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-rw-r--r--arch/arm/mm/proc-v7.S11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 6a8506d99ee9..1f16f9e3f441 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -204,8 +204,13 @@ __v7_setup:
204 bne 2f 204 bne 2f
205 and r5, r0, #0x00f00000 @ variant 205 and r5, r0, #0x00f00000 @ variant
206 and r6, r0, #0x0000000f @ revision 206 and r6, r0, #0x0000000f @ revision
207 orr r0, r6, r5, lsr #20-4 @ combine variant and revision 207 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
208 ubfx r0, r0, #4, #12 @ primary part number
208 209
210 /* Cortex-A8 Errata */
211 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
212 teq r0, r10
213 bne 2f
209#ifdef CONFIG_ARM_ERRATA_430973 214#ifdef CONFIG_ARM_ERRATA_430973
210 teq r5, #0x00100000 @ only present in r1p* 215 teq r5, #0x00100000 @ only present in r1p*
211 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 216 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
@@ -213,14 +218,14 @@ __v7_setup:
213 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 218 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
214#endif 219#endif
215#ifdef CONFIG_ARM_ERRATA_458693 220#ifdef CONFIG_ARM_ERRATA_458693
216 teq r0, #0x20 @ only present in r2p0 221 teq r6, #0x20 @ only present in r2p0
217 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register 222 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
218 orreq r10, r10, #(1 << 5) @ set L1NEON to 1 223 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
219 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 224 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
220 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register 225 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
221#endif 226#endif
222#ifdef CONFIG_ARM_ERRATA_460075 227#ifdef CONFIG_ARM_ERRATA_460075
223 teq r0, #0x20 @ only present in r2p0 228 teq r6, #0x20 @ only present in r2p0
224 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register 229 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
225 tsteq r10, #1 << 22 230 tsteq r10, #1 << 22
226 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit 231 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit