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-rw-r--r--arch/arm/mach-spear3xx/clock.c98
-rw-r--r--arch/arm/mach-spear3xx/include/mach/generic.h11
-rw-r--r--arch/arm/mach-spear3xx/include/mach/hardware.h21
-rw-r--r--arch/arm/mach-spear3xx/include/mach/irqs.h130
-rw-r--r--arch/arm/mach-spear3xx/include/mach/misc_regs.h144
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear.h38
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear300.h54
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear310.h58
-rw-r--r--arch/arm/mach-spear3xx/include/mach/spear320.h67
-rw-r--r--arch/arm/mach-spear3xx/spear300.c41
-rw-r--r--arch/arm/mach-spear3xx/spear310.c62
-rw-r--r--arch/arm/mach-spear3xx/spear320.c62
-rw-r--r--arch/arm/mach-spear3xx/spear3xx.c4
-rw-r--r--arch/arm/mach-spear6xx/clock.c106
-rw-r--r--arch/arm/mach-spear6xx/include/mach/generic.h29
-rw-r--r--arch/arm/mach-spear6xx/include/mach/hardware.h24
-rw-r--r--arch/arm/mach-spear6xx/include/mach/irqs.h75
-rw-r--r--arch/arm/mach-spear6xx/include/mach/misc_regs.h154
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear.h55
-rw-r--r--arch/arm/mach-spear6xx/include/mach/spear600.h21
-rw-r--r--arch/arm/mach-spear6xx/spear6xx.c49
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S2
-rw-r--r--arch/arm/plat-spear/include/plat/hardware.h17
-rw-r--r--arch/arm/plat-spear/include/plat/uncompress.h2
-rw-r--r--arch/arm/plat-spear/pl080.c1
-rw-r--r--arch/arm/plat-spear/restart.c2
-rw-r--r--arch/arm/plat-spear/time.c17
27 files changed, 423 insertions, 921 deletions
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index eeafe38eab25..cd6c11099083 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -19,6 +19,104 @@
19#include <asm/mach-types.h> 19#include <asm/mach-types.h>
20#include <plat/clock.h> 20#include <plat/clock.h>
21#include <mach/misc_regs.h> 21#include <mach/misc_regs.h>
22#include <mach/spear.h>
23
24#define PLL1_CTR (MISC_BASE + 0x008)
25#define PLL1_FRQ (MISC_BASE + 0x00C)
26#define PLL1_MOD (MISC_BASE + 0x010)
27#define PLL2_CTR (MISC_BASE + 0x014)
28/* PLL_CTR register masks */
29#define PLL_ENABLE 2
30#define PLL_MODE_SHIFT 4
31#define PLL_MODE_MASK 0x3
32#define PLL_MODE_NORMAL 0
33#define PLL_MODE_FRACTION 1
34#define PLL_MODE_DITH_DSB 2
35#define PLL_MODE_DITH_SSB 3
36
37#define PLL2_FRQ (MISC_BASE + 0x018)
38/* PLL FRQ register masks */
39#define PLL_DIV_N_SHIFT 0
40#define PLL_DIV_N_MASK 0xFF
41#define PLL_DIV_P_SHIFT 8
42#define PLL_DIV_P_MASK 0x7
43#define PLL_NORM_FDBK_M_SHIFT 24
44#define PLL_NORM_FDBK_M_MASK 0xFF
45#define PLL_DITH_FDBK_M_SHIFT 16
46#define PLL_DITH_FDBK_M_MASK 0xFFFF
47
48#define PLL2_MOD (MISC_BASE + 0x01C)
49#define PLL_CLK_CFG (MISC_BASE + 0x020)
50#define CORE_CLK_CFG (MISC_BASE + 0x024)
51/* CORE CLK CFG register masks */
52#define PLL_HCLK_RATIO_SHIFT 10
53#define PLL_HCLK_RATIO_MASK 0x3
54#define HCLK_PCLK_RATIO_SHIFT 8
55#define HCLK_PCLK_RATIO_MASK 0x3
56
57#define PERIP_CLK_CFG (MISC_BASE + 0x028)
58/* PERIP_CLK_CFG register masks */
59#define UART_CLK_SHIFT 4
60#define UART_CLK_MASK 0x1
61#define FIRDA_CLK_SHIFT 5
62#define FIRDA_CLK_MASK 0x3
63#define GPT0_CLK_SHIFT 8
64#define GPT1_CLK_SHIFT 11
65#define GPT2_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART_CLK_ENB 3
73#define SSP_CLK_ENB 5
74#define I2C_CLK_ENB 7
75#define JPEG_CLK_ENB 8
76#define FIRDA_CLK_ENB 10
77#define GPT1_CLK_ENB 11
78#define GPT2_CLK_ENB 12
79#define ADC_CLK_ENB 15
80#define RTC_CLK_ENB 17
81#define GPIO_CLK_ENB 18
82#define DMA_CLK_ENB 19
83#define SMI_CLK_ENB 21
84#define GMAC_CLK_ENB 23
85#define USBD_CLK_ENB 24
86#define USBH_CLK_ENB 25
87#define C3_CLK_ENB 31
88
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90
91#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
92#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
93#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
94/* gpt synthesizer register masks */
95#define GPT_MSCALE_SHIFT 0
96#define GPT_MSCALE_MASK 0xFFF
97#define GPT_NSCALE_SHIFT 12
98#define GPT_NSCALE_MASK 0xF
99
100#define AMEM_CLK_CFG (MISC_BASE + 0x050)
101#define EXPI_CLK_CFG (MISC_BASE + 0x054)
102#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
103#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
104#define UART_CLK_SYNT (MISC_BASE + 0x064)
105#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
106#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
107#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
108#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
109#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
110/* aux clk synthesiser register masks for irda to ras4 */
111#define AUX_SYNT_ENB 31
112#define AUX_EQ_SEL_SHIFT 30
113#define AUX_EQ_SEL_MASK 1
114#define AUX_EQ1_SEL 0
115#define AUX_EQ2_SEL 1
116#define AUX_XSCALE_SHIFT 16
117#define AUX_XSCALE_MASK 0xFFF
118#define AUX_YSCALE_SHIFT 0
119#define AUX_YSCALE_MASK 0xFFF
22 120
23/* root clks */ 121/* root clks */
24/* 32 KHz oscillator clock */ 122/* 32 KHz oscillator clock */
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index a7569584cbe8..e4f4d721cda2 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -22,22 +22,13 @@
22#include <asm/mach/map.h> 22#include <asm/mach/map.h>
23#include <plat/padmux.h> 23#include <plat/padmux.h>
24 24
25/* spear3xx declarations */
26/*
27 * Each GPT has 2 timer channels
28 * Following GPT channels will be used as clock source and clockevent
29 */
30#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
31#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
32#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
33
34/* Add spear3xx family device structure declarations here */ 25/* Add spear3xx family device structure declarations here */
35extern struct sys_timer spear3xx_timer; 26extern struct sys_timer spear3xx_timer;
36extern struct pl022_ssp_controller pl022_plat_data; 27extern struct pl022_ssp_controller pl022_plat_data;
37extern struct pl08x_platform_data pl080_plat_data; 28extern struct pl08x_platform_data pl080_plat_data;
38 29
39/* Add spear3xx family function declarations here */ 30/* Add spear3xx family function declarations here */
40void __init spear_setup_timer(void); 31void __init spear_setup_timer(resource_size_t base, int irq);
41void __init spear3xx_map_io(void); 32void __init spear3xx_map_io(void);
42void __init spear3xx_dt_init_irq(void); 33void __init spear3xx_dt_init_irq(void);
43 34
diff --git a/arch/arm/mach-spear3xx/include/mach/hardware.h b/arch/arm/mach-spear3xx/include/mach/hardware.h
index defa374f5bee..40a8c178f10d 100644
--- a/arch/arm/mach-spear3xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear3xx/include/mach/hardware.h
@@ -1,20 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear3xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 6e265442808e..319620a1afb4 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -14,141 +14,15 @@
14#ifndef __MACH_IRQS_H 14#ifndef __MACH_IRQS_H
15#define __MACH_IRQS_H 15#define __MACH_IRQS_H
16 16
17/* SPEAr3xx IRQ definitions */ 17/* FIXME: probe all these from DT */
18#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
19#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1 18#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
20#define SPEAR3XX_IRQ_CPU_GPT1_1 2 19#define SPEAR3XX_IRQ_CPU_GPT1_1 2
21#define SPEAR3XX_IRQ_CPU_GPT1_2 3
22#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
23#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
24#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
25#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
26#define SPEAR3XX_IRQ_BASIC_DMA 8
27#define SPEAR3XX_IRQ_BASIC_SMI 9
28#define SPEAR3XX_IRQ_BASIC_RTC 10
29#define SPEAR3XX_IRQ_BASIC_GPIO 11
30#define SPEAR3XX_IRQ_BASIC_WDT 12
31#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
32#define SPEAR3XX_IRQ_SYS_ERROR 14
33#define SPEAR3XX_IRQ_WAKEUP_RCV 15
34#define SPEAR3XX_IRQ_JPEG 16
35#define SPEAR3XX_IRQ_IRDA 17
36#define SPEAR3XX_IRQ_ADC 18
37#define SPEAR3XX_IRQ_UART 19
38#define SPEAR3XX_IRQ_SSP 20
39#define SPEAR3XX_IRQ_I2C 21
40#define SPEAR3XX_IRQ_MAC_1 22
41#define SPEAR3XX_IRQ_MAC_2 23
42#define SPEAR3XX_IRQ_USB_DEV 24
43#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
44#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
45#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
46#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
47#define SPEAR3XX_IRQ_GEN_RAS_1 28 20#define SPEAR3XX_IRQ_GEN_RAS_1 28
48#define SPEAR3XX_IRQ_GEN_RAS_2 29 21#define SPEAR3XX_IRQ_GEN_RAS_2 29
49#define SPEAR3XX_IRQ_GEN_RAS_3 30 22#define SPEAR3XX_IRQ_GEN_RAS_3 30
50#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
51#define SPEAR3XX_IRQ_VIC_END 32 23#define SPEAR3XX_IRQ_VIC_END 32
52
53#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END 24#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
54 25
55/* SPEAr300 Virtual irq definitions */ 26#define NR_IRQS 160
56/* IRQs sharing IRQ_GEN_RAS_1 */
57#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
58#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
59#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
60#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
61#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
62#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
63#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
64#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
65#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
66
67/* IRQs sharing IRQ_GEN_RAS_3 */
68#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
69
70/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
71#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
72
73/* SPEAr310 Virtual irq definitions */
74/* IRQs sharing IRQ_GEN_RAS_1 */
75#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
76#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
77#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
78#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
79#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
80#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
81#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
82#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
83
84/* IRQs sharing IRQ_GEN_RAS_2 */
85#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
86#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
87#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
88#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
89#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
90
91/* IRQs sharing IRQ_GEN_RAS_3 */
92#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
93#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
94
95/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
96#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
97#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
98#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
99
100/* SPEAr320 Virtual irq definitions */
101/* IRQs sharing IRQ_GEN_RAS_1 */
102#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
103#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
104#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
105
106/* IRQs sharing IRQ_GEN_RAS_2 */
107#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
108
109/* IRQs sharing IRQ_GEN_RAS_3 */
110#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
111#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
112#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
113
114/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
115#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
116#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
117#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
118#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
119#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
120#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
121#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
122#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
123#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
124#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
125#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
126
127/*
128 * GPIO pins virtual irqs
129 * Use the lowest number for the GPIO virtual IRQs base on which subarchs
130 * we have compiled in
131 */
132#if defined(CONFIG_MACH_SPEAR310)
133#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
134#elif defined(CONFIG_MACH_SPEAR320)
135#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
136#else
137#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
138#endif
139
140#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
141#define SPEAR3XX_PLGPIO_COUNT 102
142
143#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
144#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
145#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
146 SPEAR3XX_PLGPIO_COUNT)
147#else
148#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
149#endif
150
151#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
152#define NR_IRQS SPEAR3XX_VIRQ_END
153 27
154#endif /* __MACH_IRQS_H */ 28#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/misc_regs.h b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
index 5bd8cd8d4852..e0ab72e61507 100644
--- a/arch/arm/mach-spear3xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear3xx/include/mach/misc_regs.h
@@ -14,151 +14,7 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18
19#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE) 17#define MISC_BASE IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 11
64#define GPT2_CLK_SHIFT 12
65#define GPT_CLK_MASK 0x1
66#define AUX_CLK_PLL3_VAL 0
67#define AUX_CLK_PLL1_VAL 1
68
69#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
70/* PERIP1_CLK_ENB register masks */
71#define UART_CLK_ENB 3
72#define SSP_CLK_ENB 5
73#define I2C_CLK_ENB 7
74#define JPEG_CLK_ENB 8
75#define FIRDA_CLK_ENB 10
76#define GPT1_CLK_ENB 11
77#define GPT2_CLK_ENB 12
78#define ADC_CLK_ENB 15
79#define RTC_CLK_ENB 17
80#define GPIO_CLK_ENB 18
81#define DMA_CLK_ENB 19
82#define SMI_CLK_ENB 21
83#define GMAC_CLK_ENB 23
84#define USBD_CLK_ENB 24
85#define USBH_CLK_ENB 25
86#define C3_CLK_ENB 31
87
88#define SOC_CORE_ID (MISC_BASE + 0x030)
89#define RAS_CLK_ENB (MISC_BASE + 0x034)
90#define PERIP1_SOF_RST (MISC_BASE + 0x038)
91/* PERIP1_SOF_RST register masks */
92#define JPEG_SOF_RST 8
93
94#define SOC_USER_ID (MISC_BASE + 0x03C)
95#define RAS_SOF_RST (MISC_BASE + 0x040)
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
125
126#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
127#define ICM2_ARB_CFG (MISC_BASE + 0x080)
128#define ICM3_ARB_CFG (MISC_BASE + 0x084)
129#define ICM4_ARB_CFG (MISC_BASE + 0x088)
130#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
131#define ICM6_ARB_CFG (MISC_BASE + 0x090)
132#define ICM7_ARB_CFG (MISC_BASE + 0x094)
133#define ICM8_ARB_CFG (MISC_BASE + 0x098)
134#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
135#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 18#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
136#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
137#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
138#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
139#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
140#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
141#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
142#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
143#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
144#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
145#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
146#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
147#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
148#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
149#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
150#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
151#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
152#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
153#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
154#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
155#define BIST4_CFG_CTR (MISC_BASE + 0x100)
156#define BIST5_CFG_CTR (MISC_BASE + 0x104)
157#define BIST1_STS_RES (MISC_BASE + 0x108)
158#define BIST2_STS_RES (MISC_BASE + 0x10C)
159#define BIST3_STS_RES (MISC_BASE + 0x110)
160#define BIST4_STS_RES (MISC_BASE + 0x114)
161#define BIST5_STS_RES (MISC_BASE + 0x118)
162#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
163 19
164#endif /* __MACH_MISC_REGS_H */ 20#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear.h b/arch/arm/mach-spear3xx/include/mach/spear.h
index 8e3900aa0d45..6d4dadc67633 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear.h
@@ -15,61 +15,27 @@
15#define __MACH_SPEAR3XX_H 15#define __MACH_SPEAR3XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear300.h>
19#include <mach/spear310.h>
20#include <mach/spear320.h>
21
22#define SPEAR3XX_ML_SDRAM_BASE UL(0x00000000)
23
24#define SPEAR3XX_ICM9_BASE UL(0xC0000000)
25 18
26/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
27#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000) 20#define SPEAR3XX_ICM1_2_BASE UL(0xD0000000)
28#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000) 21#define VA_SPEAR3XX_ICM1_2_BASE UL(0xFD000000)
29#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000) 22#define SPEAR3XX_ICM1_UART_BASE UL(0xD0000000)
30#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE) 23#define VA_SPEAR3XX_ICM1_UART_BASE (VA_SPEAR3XX_ICM1_2_BASE | SPEAR3XX_ICM1_UART_BASE)
31#define SPEAR3XX_ICM1_ADC_BASE UL(0xD0080000)
32#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000) 24#define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
33#define SPEAR3XX_ICM1_I2C_BASE UL(0xD0180000)
34#define SPEAR3XX_ICM1_JPEG_BASE UL(0xD0800000)
35#define SPEAR3XX_ICM1_IRDA_BASE UL(0xD1000000)
36#define SPEAR3XX_ICM1_SRAM_BASE UL(0xD2800000)
37
38/* ICM2 - Application Subsystem */
39#define SPEAR3XX_ICM2_HWACCEL0_BASE UL(0xD8800000)
40#define SPEAR3XX_ICM2_HWACCEL1_BASE UL(0xD9000000)
41
42/* ICM4 - High Speed Connection */
43#define SPEAR3XX_ICM4_BASE UL(0xE0000000)
44#define SPEAR3XX_ICM4_MII_BASE UL(0xE0800000)
45#define SPEAR3XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
46#define SPEAR3XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
47#define SPEAR3XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
48#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE UL(0xE1800000)
49#define SPEAR3XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
50#define SPEAR3XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
51#define SPEAR3XX_ICM4_USB_ARB_BASE UL(0xE2800000)
52 25
53/* ML1 - Multi Layer CPU Subsystem */ 26/* ML1 - Multi Layer CPU Subsystem */
54#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000) 27#define SPEAR3XX_ICM3_ML1_2_BASE UL(0xF0000000)
55#define SPEAR3XX_ML1_TMR_BASE UL(0xF0000000) 28#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
56#define SPEAR3XX_ML1_VIC_BASE UL(0xF1100000) 29#define SPEAR3XX_CPU_TMR_BASE UL(0xF0000000)
57 30
58/* ICM3 - Basic Subsystem */ 31/* ICM3 - Basic Subsystem */
59#define SPEAR3XX_ICM3_SMEM_BASE UL(0xF8000000)
60#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 32#define SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
61#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 33#define VA_SPEAR3XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
62#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000) 34#define SPEAR3XX_ICM3_DMA_BASE UL(0xFC400000)
63#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
64#define SPEAR3XX_ICM3_TMR0_BASE UL(0xFC800000)
65#define SPEAR3XX_ICM3_WDT_BASE UL(0xFC880000)
66#define SPEAR3XX_ICM3_RTC_BASE UL(0xFC900000)
67#define SPEAR3XX_ICM3_GPIO_BASE UL(0xFC980000)
68#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 35#define SPEAR3XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
69#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE) 36#define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_SYS_CTRL_BASE)
70#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 37#define SPEAR3XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
71#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE) 38#define VA_SPEAR3XX_ICM3_MISC_REG_BASE (VA_SPEAR3XX_ICM3_SMI_CTRL_BASE | SPEAR3XX_ICM3_MISC_REG_BASE)
72#define SPEAR3XX_ICM3_TMR1_BASE UL(0xFCB00000)
73 39
74/* Debug uart for linux, will be used for debug and uncompress messages */ 40/* Debug uart for linux, will be used for debug and uncompress messages */
75#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE 41#define SPEAR_DBG_UART_BASE SPEAR3XX_ICM1_UART_BASE
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
deleted file mode 100644
index 3b6ea0729040..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear300.h
3 *
4 * SPEAr300 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR300
15
16#ifndef __MACH_SPEAR300_H
17#define __MACH_SPEAR300_H
18
19/* Base address of various IPs */
20#define SPEAR300_TELECOM_BASE UL(0x50000000)
21
22/* Interrupt registers offsets and masks */
23#define SPEAR300_INT_ENB_MASK_REG 0x54
24#define SPEAR300_INT_STS_MASK_REG 0x58
25#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
26#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
27#define SPEAR300_I2S_IRQ_MASK (1 << 2)
28#define SPEAR300_TDM_IRQ_MASK (1 << 3)
29#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
30#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
31#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
32#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
33#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
34
35#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
36
37#define SPEAR300_CLCD_BASE UL(0x60000000)
38#define SPEAR300_SDHCI_BASE UL(0x70000000)
39#define SPEAR300_NAND_0_BASE UL(0x80000000)
40#define SPEAR300_NAND_1_BASE UL(0x84000000)
41#define SPEAR300_NAND_2_BASE UL(0x88000000)
42#define SPEAR300_NAND_3_BASE UL(0x8c000000)
43#define SPEAR300_NOR_0_BASE UL(0x90000000)
44#define SPEAR300_NOR_1_BASE UL(0x91000000)
45#define SPEAR300_NOR_2_BASE UL(0x92000000)
46#define SPEAR300_NOR_3_BASE UL(0x93000000)
47#define SPEAR300_FSMC_BASE UL(0x94000000)
48#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
49#define SPEAR300_KEYBOARD_BASE UL(0xA0000000)
50#define SPEAR300_GPIO_BASE UL(0xA9000000)
51
52#endif /* __MACH_SPEAR300_H */
53
54#endif /* CONFIG_MACH_SPEAR300 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
deleted file mode 100644
index 1567d0da725f..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear310.h
3 *
4 * SPEAr310 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR310
15
16#ifndef __MACH_SPEAR310_H
17#define __MACH_SPEAR310_H
18
19#define SPEAR310_NAND_BASE UL(0x40000000)
20#define SPEAR310_FSMC_BASE UL(0x44000000)
21#define SPEAR310_UART1_BASE UL(0xB2000000)
22#define SPEAR310_UART2_BASE UL(0xB2080000)
23#define SPEAR310_UART3_BASE UL(0xB2100000)
24#define SPEAR310_UART4_BASE UL(0xB2180000)
25#define SPEAR310_UART5_BASE UL(0xB2200000)
26#define SPEAR310_HDLC_BASE UL(0xB2800000)
27#define SPEAR310_RS485_0_BASE UL(0xB3000000)
28#define SPEAR310_RS485_1_BASE UL(0xB3800000)
29#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
30
31/* Interrupt registers offsets and masks */
32#define SPEAR310_INT_STS_MASK_REG 0x04
33#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
34#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
35#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
36#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
37#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
38#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
39#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
40#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
41#define SPEAR310_UART1_IRQ_MASK (1 << 8)
42#define SPEAR310_UART2_IRQ_MASK (1 << 9)
43#define SPEAR310_UART3_IRQ_MASK (1 << 10)
44#define SPEAR310_UART4_IRQ_MASK (1 << 11)
45#define SPEAR310_UART5_IRQ_MASK (1 << 12)
46#define SPEAR310_EMI_IRQ_MASK (1 << 13)
47#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
48#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
49#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
50
51#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
52#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
53#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
54#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
55
56#endif /* __MACH_SPEAR310_H */
57
58#endif /* CONFIG_MACH_SPEAR310 */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
deleted file mode 100644
index 8cfa83fa1296..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/spear320.h
3 *
4 * SPEAr320 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR320
15
16#ifndef __MACH_SPEAR320_H
17#define __MACH_SPEAR320_H
18
19#define SPEAR320_EMI_CTRL_BASE UL(0x40000000)
20#define SPEAR320_FSMC_BASE UL(0x4C000000)
21#define SPEAR320_NAND_BASE UL(0x50000000)
22#define SPEAR320_I2S_BASE UL(0x60000000)
23#define SPEAR320_SDHCI_BASE UL(0x70000000)
24#define SPEAR320_CLCD_BASE UL(0x90000000)
25#define SPEAR320_PAR_PORT_BASE UL(0xA0000000)
26#define SPEAR320_CAN0_BASE UL(0xA1000000)
27#define SPEAR320_CAN1_BASE UL(0xA2000000)
28#define SPEAR320_UART1_BASE UL(0xA3000000)
29#define SPEAR320_UART2_BASE UL(0xA4000000)
30#define SPEAR320_SSP0_BASE UL(0xA5000000)
31#define SPEAR320_SSP1_BASE UL(0xA6000000)
32#define SPEAR320_I2C_BASE UL(0xA7000000)
33#define SPEAR320_PWM_BASE UL(0xA8000000)
34#define SPEAR320_SMII0_BASE UL(0xAA000000)
35#define SPEAR320_SMII1_BASE UL(0xAB000000)
36#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
37
38/* Interrupt registers offsets and masks */
39#define SPEAR320_INT_STS_MASK_REG 0x04
40#define SPEAR320_INT_CLR_MASK_REG 0x04
41#define SPEAR320_INT_ENB_MASK_REG 0x08
42#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
43#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
44#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
45#define SPEAR320_EMI_IRQ_MASK (1 << 7)
46#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
47#define SPEAR320_SPP_IRQ_MASK (1 << 9)
48#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
49#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
50#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
51#define SPEAR320_UART1_IRQ_MASK (1 << 13)
52#define SPEAR320_UART2_IRQ_MASK (1 << 14)
53#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
54#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
55#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
56#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
57#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
58#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
59#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
60
61#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
62#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
63#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
64
65#endif /* __MACH_SPEAR320_H */
66
67#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index f46fc2692ab6..febcdd8d4e92 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -19,7 +19,46 @@
19#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <plat/shirq.h> 20#include <plat/shirq.h>
21#include <mach/generic.h> 21#include <mach/generic.h>
22#include <mach/hardware.h> 22#include <mach/spear.h>
23
24/* Base address of various IPs */
25#define SPEAR300_TELECOM_BASE UL(0x50000000)
26
27/* Interrupt registers offsets and masks */
28#define SPEAR300_INT_ENB_MASK_REG 0x54
29#define SPEAR300_INT_STS_MASK_REG 0x58
30#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
31#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
32#define SPEAR300_I2S_IRQ_MASK (1 << 2)
33#define SPEAR300_TDM_IRQ_MASK (1 << 3)
34#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
35#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
36#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
37#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
38#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
39
40#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
41
42#define SPEAR300_SOC_CONFIG_BASE UL(0x99000000)
43
44
45/* SPEAr300 Virtual irq definitions */
46/* IRQs sharing IRQ_GEN_RAS_1 */
47#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
48#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
49#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
50#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
51#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
52#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
53#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
54#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
55#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
56
57/* IRQs sharing IRQ_GEN_RAS_3 */
58#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
59
60/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
61#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
23 62
24/* pad multiplexing support */ 63/* pad multiplexing support */
25/* muxing registers */ 64/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 063e7da0438a..b26e41566b50 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -20,7 +20,67 @@
20#include <asm/mach/arch.h> 20#include <asm/mach/arch.h>
21#include <plat/shirq.h> 21#include <plat/shirq.h>
22#include <mach/generic.h> 22#include <mach/generic.h>
23#include <mach/hardware.h> 23#include <mach/spear.h>
24
25#define SPEAR310_UART1_BASE UL(0xB2000000)
26#define SPEAR310_UART2_BASE UL(0xB2080000)
27#define SPEAR310_UART3_BASE UL(0xB2100000)
28#define SPEAR310_UART4_BASE UL(0xB2180000)
29#define SPEAR310_UART5_BASE UL(0xB2200000)
30#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR310_INT_STS_MASK_REG 0x04
34#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
35#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
36#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
37#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
38#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
39#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
40#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
41#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
42#define SPEAR310_UART1_IRQ_MASK (1 << 8)
43#define SPEAR310_UART2_IRQ_MASK (1 << 9)
44#define SPEAR310_UART3_IRQ_MASK (1 << 10)
45#define SPEAR310_UART4_IRQ_MASK (1 << 11)
46#define SPEAR310_UART5_IRQ_MASK (1 << 12)
47#define SPEAR310_EMI_IRQ_MASK (1 << 13)
48#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
49#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
50#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
51
52#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
53#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
54#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
55#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
56
57/* SPEAr310 Virtual irq definitions */
58/* IRQs sharing IRQ_GEN_RAS_1 */
59#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
60#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
61#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
62#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
63#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
64#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
65#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
66#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
67
68/* IRQs sharing IRQ_GEN_RAS_2 */
69#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
70#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
71#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
72#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
73#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
74
75/* IRQs sharing IRQ_GEN_RAS_3 */
76#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
77#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
78
79/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
80#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
81#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
82#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
83
24 84
25/* pad multiplexing support */ 85/* pad multiplexing support */
26/* muxing registers */ 86/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 1e74031e1213..2f5979b0c169 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -21,7 +21,67 @@
21#include <asm/mach/arch.h> 21#include <asm/mach/arch.h>
22#include <plat/shirq.h> 22#include <plat/shirq.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25
26#define SPEAR320_UART1_BASE UL(0xA3000000)
27#define SPEAR320_UART2_BASE UL(0xA4000000)
28#define SPEAR320_SSP0_BASE UL(0xA5000000)
29#define SPEAR320_SSP1_BASE UL(0xA6000000)
30#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
31
32/* Interrupt registers offsets and masks */
33#define SPEAR320_INT_STS_MASK_REG 0x04
34#define SPEAR320_INT_CLR_MASK_REG 0x04
35#define SPEAR320_INT_ENB_MASK_REG 0x08
36#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
37#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
38#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
39#define SPEAR320_EMI_IRQ_MASK (1 << 7)
40#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
41#define SPEAR320_SPP_IRQ_MASK (1 << 9)
42#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
43#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
44#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
45#define SPEAR320_UART1_IRQ_MASK (1 << 13)
46#define SPEAR320_UART2_IRQ_MASK (1 << 14)
47#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
48#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
49#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
50#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
51#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
52#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
53#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
54
55#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
56#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
57#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
58
59/* SPEAr320 Virtual irq definitions */
60/* IRQs sharing IRQ_GEN_RAS_1 */
61#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
62#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
63#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
64
65/* IRQs sharing IRQ_GEN_RAS_2 */
66#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
67
68/* IRQs sharing IRQ_GEN_RAS_3 */
69#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
70#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
71#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
72
73/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
74#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
75#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
76#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
77#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
78#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
79#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
80#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
81#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
82#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
83#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
84#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
25 85
26/* pad multiplexing support */ 86/* pad multiplexing support */
27/* muxing registers */ 87/* muxing registers */
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 17d4ac9a95e1..bbb11efa6056 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -21,7 +21,7 @@
21#include <asm/hardware/vic.h> 21#include <asm/hardware/vic.h>
22#include <plat/pl080.h> 22#include <plat/pl080.h>
23#include <mach/generic.h> 23#include <mach/generic.h>
24#include <mach/hardware.h> 24#include <mach/spear.h>
25 25
26/* pad multiplexing support */ 26/* pad multiplexing support */
27/* devices */ 27/* devices */
@@ -534,7 +534,7 @@ static void __init spear3xx_timer_init(void)
534 clk_put(gpt_clk); 534 clk_put(gpt_clk);
535 clk_put(pclk); 535 clk_put(pclk);
536 536
537 spear_setup_timer(); 537 spear_setup_timer(SPEAR3XX_CPU_TMR_BASE, SPEAR3XX_IRQ_CPU_GPT1_1);
538} 538}
539 539
540struct sys_timer spear3xx_timer = { 540struct sys_timer spear3xx_timer = {
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index adadef2b27b4..bef77d43db87 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -16,6 +16,112 @@
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <plat/clock.h> 17#include <plat/clock.h>
18#include <mach/misc_regs.h> 18#include <mach/misc_regs.h>
19#include <mach/spear.h>
20
21#define PLL1_CTR (MISC_BASE + 0x008)
22#define PLL1_FRQ (MISC_BASE + 0x00C)
23#define PLL1_MOD (MISC_BASE + 0x010)
24#define PLL2_CTR (MISC_BASE + 0x014)
25/* PLL_CTR register masks */
26#define PLL_ENABLE 2
27#define PLL_MODE_SHIFT 4
28#define PLL_MODE_MASK 0x3
29#define PLL_MODE_NORMAL 0
30#define PLL_MODE_FRACTION 1
31#define PLL_MODE_DITH_DSB 2
32#define PLL_MODE_DITH_SSB 3
33
34#define PLL2_FRQ (MISC_BASE + 0x018)
35/* PLL FRQ register masks */
36#define PLL_DIV_N_SHIFT 0
37#define PLL_DIV_N_MASK 0xFF
38#define PLL_DIV_P_SHIFT 8
39#define PLL_DIV_P_MASK 0x7
40#define PLL_NORM_FDBK_M_SHIFT 24
41#define PLL_NORM_FDBK_M_MASK 0xFF
42#define PLL_DITH_FDBK_M_SHIFT 16
43#define PLL_DITH_FDBK_M_MASK 0xFFFF
44
45#define PLL2_MOD (MISC_BASE + 0x01C)
46#define PLL_CLK_CFG (MISC_BASE + 0x020)
47#define CORE_CLK_CFG (MISC_BASE + 0x024)
48/* CORE CLK CFG register masks */
49#define PLL_HCLK_RATIO_SHIFT 10
50#define PLL_HCLK_RATIO_MASK 0x3
51#define HCLK_PCLK_RATIO_SHIFT 8
52#define HCLK_PCLK_RATIO_MASK 0x3
53
54#define PERIP_CLK_CFG (MISC_BASE + 0x028)
55/* PERIP_CLK_CFG register masks */
56#define CLCD_CLK_SHIFT 2
57#define CLCD_CLK_MASK 0x3
58#define UART_CLK_SHIFT 4
59#define UART_CLK_MASK 0x1
60#define FIRDA_CLK_SHIFT 5
61#define FIRDA_CLK_MASK 0x3
62#define GPT0_CLK_SHIFT 8
63#define GPT1_CLK_SHIFT 10
64#define GPT2_CLK_SHIFT 11
65#define GPT3_CLK_SHIFT 12
66#define GPT_CLK_MASK 0x1
67#define AUX_CLK_PLL3_VAL 0
68#define AUX_CLK_PLL1_VAL 1
69
70#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
71/* PERIP1_CLK_ENB register masks */
72#define UART0_CLK_ENB 3
73#define UART1_CLK_ENB 4
74#define SSP0_CLK_ENB 5
75#define SSP1_CLK_ENB 6
76#define I2C_CLK_ENB 7
77#define JPEG_CLK_ENB 8
78#define FSMC_CLK_ENB 9
79#define FIRDA_CLK_ENB 10
80#define GPT2_CLK_ENB 11
81#define GPT3_CLK_ENB 12
82#define GPIO2_CLK_ENB 13
83#define SSP2_CLK_ENB 14
84#define ADC_CLK_ENB 15
85#define GPT1_CLK_ENB 11
86#define RTC_CLK_ENB 17
87#define GPIO1_CLK_ENB 18
88#define DMA_CLK_ENB 19
89#define SMI_CLK_ENB 21
90#define CLCD_CLK_ENB 22
91#define GMAC_CLK_ENB 23
92#define USBD_CLK_ENB 24
93#define USBH0_CLK_ENB 25
94#define USBH1_CLK_ENB 26
95
96#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
97#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
98#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
99/* gpt synthesizer register masks */
100#define GPT_MSCALE_SHIFT 0
101#define GPT_MSCALE_MASK 0xFFF
102#define GPT_NSCALE_SHIFT 12
103#define GPT_NSCALE_MASK 0xF
104
105#define AMEM_CLK_CFG (MISC_BASE + 0x050)
106#define EXPI_CLK_CFG (MISC_BASE + 0x054)
107#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
108#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
109#define UART_CLK_SYNT (MISC_BASE + 0x064)
110#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
111#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
112#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
113#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
114#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
115/* aux clk synthesiser register masks for irda to ras4 */
116#define AUX_SYNT_ENB 31
117#define AUX_EQ_SEL_SHIFT 30
118#define AUX_EQ_SEL_MASK 1
119#define AUX_EQ1_SEL 0
120#define AUX_EQ2_SEL 1
121#define AUX_XSCALE_SHIFT 16
122#define AUX_XSCALE_MASK 0xFFF
123#define AUX_YSCALE_SHIFT 0
124#define AUX_YSCALE_MASK 0xFFF
19 125
20/* root clks */ 126/* root clks */
21/* 32 KHz oscillator clock */ 127/* 32 KHz oscillator clock */
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..7167fd331d86 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
15#define __MACH_GENERIC_H 15#define __MACH_GENERIC_H
16 16
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/amba/bus.h>
20#include <asm/mach/time.h>
21#include <asm/mach/map.h>
22
23/*
24 * Each GPT has 2 timer channels
25 * Following GPT channels will be used as clock source and clockevent
26 */
27#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE
28#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
29#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
30
31/* Add spear6xx family device structure declarations here */
32extern struct amba_device gpio_device[];
33extern struct amba_device uart_device[];
34extern struct sys_timer spear6xx_timer;
35
36/* Add spear6xx family function declarations here */
37void __init spear_setup_timer(void);
38void __init spear6xx_map_io(void);
39void __init spear6xx_init_irq(void);
40void __init spear6xx_init(void);
41void __init spear600_init(void);
42void __init spear6xx_clk_init(void);
43 18
19void __init spear_setup_timer(resource_size_t base, int irq);
44void spear_restart(char, const char *); 20void spear_restart(char, const char *);
45 21void __init spear6xx_clk_init(void);
46/* Add spear600 machine device structure declarations here */
47 22
48#endif /* __MACH_GENERIC_H */ 23#endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
1/* /* empty */
2 * arch/arm/mach-spear6xx/include/mach/hardware.h
3 *
4 * Hardware definitions for SPEAr6xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_HARDWARE_H
15#define __MACH_HARDWARE_H
16
17#include <plat/hardware.h>
18#include <mach/spear.h>
19
20/* Vitual to physical translation of statically mapped space */
21#define IO_ADDRESS(x) (x | 0xF0000000)
22
23#endif /* __MACH_HARDWARE_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..2b735389e74b 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,13 @@
16 16
17/* IRQ definitions */ 17/* IRQ definitions */
18/* VIC 1 */ 18/* VIC 1 */
19#define IRQ_INTRCOMM_SW_IRQ 0 19/* FIXME: probe this from DT */
20#define IRQ_INTRCOMM_CPU_1 1
21#define IRQ_INTRCOMM_CPU_2 2
22#define IRQ_INTRCOMM_RAS2A11_1 3
23#define IRQ_INTRCOMM_RAS2A11_2 4
24#define IRQ_INTRCOMM_RAS2A12_1 5
25#define IRQ_INTRCOMM_RAS2A12_2 6
26#define IRQ_GEN_RAS_0 7
27#define IRQ_GEN_RAS_1 8
28#define IRQ_GEN_RAS_2 9
29#define IRQ_GEN_RAS_3 10
30#define IRQ_GEN_RAS_4 11
31#define IRQ_GEN_RAS_5 12
32#define IRQ_GEN_RAS_6 13
33#define IRQ_GEN_RAS_7 14
34#define IRQ_GEN_RAS_8 15
35#define IRQ_CPU_GPT1_1 16 20#define IRQ_CPU_GPT1_1 16
36#define IRQ_CPU_GPT1_2 17
37#define IRQ_LOCAL_GPIO 18
38#define IRQ_PLL_UNLOCK 19
39#define IRQ_JPEG 20
40#define IRQ_FSMC 21
41#define IRQ_IRDA 22
42#define IRQ_RESERVED 23
43#define IRQ_UART_0 24
44#define IRQ_UART_1 25
45#define IRQ_SSP_1 26
46#define IRQ_SSP_2 27
47#define IRQ_I2C 28
48#define IRQ_GEN_RAS_9 29
49#define IRQ_GEN_RAS_10 30
50#define IRQ_GEN_RAS_11 31
51
52/* VIC 2 */
53#define IRQ_APPL_GPT1_1 32
54#define IRQ_APPL_GPT1_2 33
55#define IRQ_APPL_GPT2_1 34
56#define IRQ_APPL_GPT2_2 35
57#define IRQ_APPL_GPIO 36
58#define IRQ_APPL_SSP 37
59#define IRQ_APPL_ADC 38
60#define IRQ_APPL_RESERVED 39
61#define IRQ_AHB_EXP_MASTER 40
62#define IRQ_DDR_CONTROLLER 41
63#define IRQ_BASIC_DMA 42
64#define IRQ_BASIC_RESERVED1 43
65#define IRQ_BASIC_SMI 44
66#define IRQ_BASIC_CLCD 45
67#define IRQ_EXP_AHB_1 46
68#define IRQ_EXP_AHB_2 47
69#define IRQ_BASIC_GPT1_1 48
70#define IRQ_BASIC_GPT1_2 49
71#define IRQ_BASIC_RTC 50
72#define IRQ_BASIC_GPIO 51
73#define IRQ_BASIC_WDT 52
74#define IRQ_BASIC_RESERVED 53
75#define IRQ_AHB_EXP_SLAVE 54
76#define IRQ_GMAC_1 55
77#define IRQ_GMAC_2 56
78#define IRQ_USB_DEV 57
79#define IRQ_USB_H_OHCI_0 58
80#define IRQ_USB_H_EHCI_0 59
81#define IRQ_USB_H_OHCI_1 60
82#define IRQ_USB_H_EHCI_1 61
83#define IRQ_EXP_AHB_3 62
84#define IRQ_EXP_AHB_4 63
85 21
86#define IRQ_VIC_END 64 22#define IRQ_VIC_END 64
87 23
88/* GPIO pins virtual irqs */ 24/* GPIO pins virtual irqs */
89#define SPEAR_GPIO_INT_BASE IRQ_VIC_END 25#define VIRTUAL_IRQS 24
90#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE 26#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
91#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
92#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
93#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
94#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
95#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
96 27
97#endif /* __MACH_IRQS_H */ 28#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..2b9aaa6cdd11 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,7 @@
14#ifndef __MACH_MISC_REGS_H 14#ifndef __MACH_MISC_REGS_H
15#define __MACH_MISC_REGS_H 15#define __MACH_MISC_REGS_H
16 16
17#include <mach/hardware.h>
18
19#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE) 17#define MISC_BASE IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
20
21#define SOC_CFG_CTR (MISC_BASE + 0x000)
22#define DIAG_CFG_CTR (MISC_BASE + 0x004)
23#define PLL1_CTR (MISC_BASE + 0x008)
24#define PLL1_FRQ (MISC_BASE + 0x00C)
25#define PLL1_MOD (MISC_BASE + 0x010)
26#define PLL2_CTR (MISC_BASE + 0x014)
27/* PLL_CTR register masks */
28#define PLL_ENABLE 2
29#define PLL_MODE_SHIFT 4
30#define PLL_MODE_MASK 0x3
31#define PLL_MODE_NORMAL 0
32#define PLL_MODE_FRACTION 1
33#define PLL_MODE_DITH_DSB 2
34#define PLL_MODE_DITH_SSB 3
35
36#define PLL2_FRQ (MISC_BASE + 0x018)
37/* PLL FRQ register masks */
38#define PLL_DIV_N_SHIFT 0
39#define PLL_DIV_N_MASK 0xFF
40#define PLL_DIV_P_SHIFT 8
41#define PLL_DIV_P_MASK 0x7
42#define PLL_NORM_FDBK_M_SHIFT 24
43#define PLL_NORM_FDBK_M_MASK 0xFF
44#define PLL_DITH_FDBK_M_SHIFT 16
45#define PLL_DITH_FDBK_M_MASK 0xFFFF
46
47#define PLL2_MOD (MISC_BASE + 0x01C)
48#define PLL_CLK_CFG (MISC_BASE + 0x020)
49#define CORE_CLK_CFG (MISC_BASE + 0x024)
50/* CORE CLK CFG register masks */
51#define PLL_HCLK_RATIO_SHIFT 10
52#define PLL_HCLK_RATIO_MASK 0x3
53#define HCLK_PCLK_RATIO_SHIFT 8
54#define HCLK_PCLK_RATIO_MASK 0x3
55
56#define PERIP_CLK_CFG (MISC_BASE + 0x028)
57/* PERIP_CLK_CFG register masks */
58#define CLCD_CLK_SHIFT 2
59#define CLCD_CLK_MASK 0x3
60#define UART_CLK_SHIFT 4
61#define UART_CLK_MASK 0x1
62#define FIRDA_CLK_SHIFT 5
63#define FIRDA_CLK_MASK 0x3
64#define GPT0_CLK_SHIFT 8
65#define GPT1_CLK_SHIFT 10
66#define GPT2_CLK_SHIFT 11
67#define GPT3_CLK_SHIFT 12
68#define GPT_CLK_MASK 0x1
69#define AUX_CLK_PLL3_VAL 0
70#define AUX_CLK_PLL1_VAL 1
71
72#define PERIP1_CLK_ENB (MISC_BASE + 0x02C)
73/* PERIP1_CLK_ENB register masks */
74#define UART0_CLK_ENB 3
75#define UART1_CLK_ENB 4
76#define SSP0_CLK_ENB 5
77#define SSP1_CLK_ENB 6
78#define I2C_CLK_ENB 7
79#define JPEG_CLK_ENB 8
80#define FSMC_CLK_ENB 9
81#define FIRDA_CLK_ENB 10
82#define GPT2_CLK_ENB 11
83#define GPT3_CLK_ENB 12
84#define GPIO2_CLK_ENB 13
85#define SSP2_CLK_ENB 14
86#define ADC_CLK_ENB 15
87#define GPT1_CLK_ENB 11
88#define RTC_CLK_ENB 17
89#define GPIO1_CLK_ENB 18
90#define DMA_CLK_ENB 19
91#define SMI_CLK_ENB 21
92#define CLCD_CLK_ENB 22
93#define GMAC_CLK_ENB 23
94#define USBD_CLK_ENB 24
95#define USBH0_CLK_ENB 25
96#define USBH1_CLK_ENB 26
97
98#define SOC_CORE_ID (MISC_BASE + 0x030)
99#define RAS_CLK_ENB (MISC_BASE + 0x034)
100#define PERIP1_SOF_RST (MISC_BASE + 0x038)
101/* PERIP1_SOF_RST register masks */
102#define JPEG_SOF_RST 8
103
104#define SOC_USER_ID (MISC_BASE + 0x03C)
105#define RAS_SOF_RST (MISC_BASE + 0x040)
106#define PRSC1_CLK_CFG (MISC_BASE + 0x044)
107#define PRSC2_CLK_CFG (MISC_BASE + 0x048)
108#define PRSC3_CLK_CFG (MISC_BASE + 0x04C)
109/* gpt synthesizer register masks */
110#define GPT_MSCALE_SHIFT 0
111#define GPT_MSCALE_MASK 0xFFF
112#define GPT_NSCALE_SHIFT 12
113#define GPT_NSCALE_MASK 0xF
114
115#define AMEM_CLK_CFG (MISC_BASE + 0x050)
116#define EXPI_CLK_CFG (MISC_BASE + 0x054)
117#define CLCD_CLK_SYNT (MISC_BASE + 0x05C)
118#define FIRDA_CLK_SYNT (MISC_BASE + 0x060)
119#define UART_CLK_SYNT (MISC_BASE + 0x064)
120#define GMAC_CLK_SYNT (MISC_BASE + 0x068)
121#define RAS1_CLK_SYNT (MISC_BASE + 0x06C)
122#define RAS2_CLK_SYNT (MISC_BASE + 0x070)
123#define RAS3_CLK_SYNT (MISC_BASE + 0x074)
124#define RAS4_CLK_SYNT (MISC_BASE + 0x078)
125/* aux clk synthesiser register masks for irda to ras4 */
126#define AUX_SYNT_ENB 31
127#define AUX_EQ_SEL_SHIFT 30
128#define AUX_EQ_SEL_MASK 1
129#define AUX_EQ1_SEL 0
130#define AUX_EQ2_SEL 1
131#define AUX_XSCALE_SHIFT 16
132#define AUX_XSCALE_MASK 0xFFF
133#define AUX_YSCALE_SHIFT 0
134#define AUX_YSCALE_MASK 0xFFF
135
136#define ICM1_ARB_CFG (MISC_BASE + 0x07C)
137#define ICM2_ARB_CFG (MISC_BASE + 0x080)
138#define ICM3_ARB_CFG (MISC_BASE + 0x084)
139#define ICM4_ARB_CFG (MISC_BASE + 0x088)
140#define ICM5_ARB_CFG (MISC_BASE + 0x08C)
141#define ICM6_ARB_CFG (MISC_BASE + 0x090)
142#define ICM7_ARB_CFG (MISC_BASE + 0x094)
143#define ICM8_ARB_CFG (MISC_BASE + 0x098)
144#define ICM9_ARB_CFG (MISC_BASE + 0x09C)
145#define DMA_CHN_CFG (MISC_BASE + 0x0A0) 18#define DMA_CHN_CFG (MISC_BASE + 0x0A0)
146#define USB2_PHY_CFG (MISC_BASE + 0x0A4)
147#define GMAC_CFG_CTR (MISC_BASE + 0x0A8)
148#define EXPI_CFG_CTR (MISC_BASE + 0x0AC)
149#define PRC1_LOCK_CTR (MISC_BASE + 0x0C0)
150#define PRC2_LOCK_CTR (MISC_BASE + 0x0C4)
151#define PRC3_LOCK_CTR (MISC_BASE + 0x0C8)
152#define PRC4_LOCK_CTR (MISC_BASE + 0x0CC)
153#define PRC1_IRQ_CTR (MISC_BASE + 0x0D0)
154#define PRC2_IRQ_CTR (MISC_BASE + 0x0D4)
155#define PRC3_IRQ_CTR (MISC_BASE + 0x0D8)
156#define PRC4_IRQ_CTR (MISC_BASE + 0x0DC)
157#define PWRDOWN_CFG_CTR (MISC_BASE + 0x0E0)
158#define COMPSSTL_1V8_CFG (MISC_BASE + 0x0E4)
159#define COMPSSTL_2V5_CFG (MISC_BASE + 0x0E8)
160#define COMPCOR_3V3_CFG (MISC_BASE + 0x0EC)
161#define SSTLPAD_CFG_CTR (MISC_BASE + 0x0F0)
162#define BIST1_CFG_CTR (MISC_BASE + 0x0F4)
163#define BIST2_CFG_CTR (MISC_BASE + 0x0F8)
164#define BIST3_CFG_CTR (MISC_BASE + 0x0FC)
165#define BIST4_CFG_CTR (MISC_BASE + 0x100)
166#define BIST5_CFG_CTR (MISC_BASE + 0x104)
167#define BIST1_STS_RES (MISC_BASE + 0x108)
168#define BIST2_STS_RES (MISC_BASE + 0x10C)
169#define BIST3_STS_RES (MISC_BASE + 0x110)
170#define BIST4_STS_RES (MISC_BASE + 0x114)
171#define BIST5_STS_RES (MISC_BASE + 0x118)
172#define SYSERR_CFG_CTR (MISC_BASE + 0x11C)
173 19
174#endif /* __MACH_MISC_REGS_H */ 20#endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..d278ed047a53 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,26 @@
15#define __MACH_SPEAR6XX_H 15#define __MACH_SPEAR6XX_H
16 16
17#include <asm/memory.h> 17#include <asm/memory.h>
18#include <mach/spear600.h>
19 18
20#define SPEAR6XX_ML_SDRAM_BASE UL(0x00000000)
21/* ICM1 - Low speed connection */ 19/* ICM1 - Low speed connection */
22#define SPEAR6XX_ICM1_BASE UL(0xD0000000) 20#define SPEAR6XX_ICM1_BASE UL(0xD0000000)
23 21#define VA_SPEAR6XX_ICM1_BASE UL(0xFD000000)
24#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000) 22#define SPEAR6XX_ICM1_UART0_BASE UL(0xD0000000)
25#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) 23#define VA_SPEAR6XX_ICM1_UART0_BASE (VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
26
27#define SPEAR6XX_ICM1_UART1_BASE UL(0xD0080000)
28#define SPEAR6XX_ICM1_SSP0_BASE UL(0xD0100000)
29#define SPEAR6XX_ICM1_SSP1_BASE UL(0xD0180000)
30#define SPEAR6XX_ICM1_I2C_BASE UL(0xD0200000)
31#define SPEAR6XX_ICM1_JPEG_BASE UL(0xD0800000)
32#define SPEAR6XX_ICM1_IRDA_BASE UL(0xD1000000)
33#define SPEAR6XX_ICM1_FSMC_BASE UL(0xD1800000)
34#define SPEAR6XX_ICM1_NAND_BASE UL(0xD2000000)
35#define SPEAR6XX_ICM1_SRAM_BASE UL(0xD2800000)
36
37/* ICM2 - Application Subsystem */
38#define SPEAR6XX_ICM2_BASE UL(0xD8000000)
39#define SPEAR6XX_ICM2_TMR0_BASE UL(0xD8000000)
40#define SPEAR6XX_ICM2_TMR1_BASE UL(0xD8080000)
41#define SPEAR6XX_ICM2_GPIO_BASE UL(0xD8100000)
42#define SPEAR6XX_ICM2_SSP2_BASE UL(0xD8180000)
43#define SPEAR6XX_ICM2_ADC_BASE UL(0xD8200000)
44 24
45/* ML-1, 2 - Multi Layer CPU Subsystem */ 25/* ML-1, 2 - Multi Layer CPU Subsystem */
46#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000) 26#define SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
27#define VA_SPEAR6XX_ML_CPU_BASE UL(0xF0000000)
47#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000) 28#define SPEAR6XX_CPU_TMR_BASE UL(0xF0000000)
48#define SPEAR6XX_CPU_GPIO_BASE UL(0xF0100000)
49#define SPEAR6XX_CPU_VIC_SEC_BASE UL(0xF1000000)
50#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
51#define SPEAR6XX_CPU_VIC_PRI_BASE UL(0xF1100000)
52#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
53 29
54/* ICM3 - Basic Subsystem */ 30/* ICM3 - Basic Subsystem */
55#define SPEAR6XX_ICM3_BASE UL(0xF8000000)
56#define SPEAR6XX_ICM3_SMEM_BASE UL(0xF8000000)
57#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000) 31#define SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
58#define SPEAR6XX_ICM3_CLCD_BASE UL(0xFC200000) 32#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE UL(0xFC000000)
59#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000) 33#define SPEAR6XX_ICM3_DMA_BASE UL(0xFC400000)
60#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE UL(0xFC600000)
61#define SPEAR6XX_ICM3_TMR_BASE UL(0xFC800000)
62#define SPEAR6XX_ICM3_WDT_BASE UL(0xFC880000)
63#define SPEAR6XX_ICM3_RTC_BASE UL(0xFC900000)
64#define SPEAR6XX_ICM3_GPIO_BASE UL(0xFC980000)
65#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000) 34#define SPEAR6XX_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
66#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) 35#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
67#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000) 36#define SPEAR6XX_ICM3_MISC_REG_BASE UL(0xFCA80000)
68#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) 37#define VA_SPEAR6XX_ICM3_MISC_REG_BASE (VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
69
70/* ICM4 - High Speed Connection */
71#define SPEAR6XX_ICM4_BASE UL(0xE0000000)
72#define SPEAR6XX_ICM4_GMAC_BASE UL(0xE0800000)
73#define SPEAR6XX_ICM4_USBD_FIFO_BASE UL(0xE1000000)
74#define SPEAR6XX_ICM4_USBD_CSR_BASE UL(0xE1100000)
75#define SPEAR6XX_ICM4_USBD_PLDT_BASE UL(0xE1200000)
76#define SPEAR6XX_ICM4_USB_EHCI0_BASE UL(0xE1800000)
77#define SPEAR6XX_ICM4_USB_OHCI0_BASE UL(0xE1900000)
78#define SPEAR6XX_ICM4_USB_EHCI1_BASE UL(0xE2000000)
79#define SPEAR6XX_ICM4_USB_OHCI1_BASE UL(0xE2100000)
80#define SPEAR6XX_ICM4_USB_ARB_BASE UL(0xE2800000)
81 38
82/* Debug uart for linux, will be used for debug and uncompress messages */ 39/* Debug uart for linux, will be used for debug and uncompress messages */
83#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE 40#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-spear66xx/include/mach/spear600.h
3 *
4 * SPEAr600 Machine specific definition
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifdef CONFIG_MACH_SPEAR600
15
16#ifndef __MACH_SPEAR600_H
17#define __MACH_SPEAR600_H
18
19#endif /* __MACH_SPEAR600_H */
20
21#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 5b9e30f54cdb..de194dbb8371 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -14,6 +14,8 @@
14 */ 14 */
15 15
16#include <linux/amba/pl08x.h> 16#include <linux/amba/pl08x.h>
17#include <linux/clk.h>
18#include <linux/err.h>
17#include <linux/of.h> 19#include <linux/of.h>
18#include <linux/of_address.h> 20#include <linux/of_address.h>
19#include <linux/of_irq.h> 21#include <linux/of_irq.h>
@@ -21,9 +23,11 @@
21#include <asm/hardware/pl080.h> 23#include <asm/hardware/pl080.h>
22#include <asm/hardware/vic.h> 24#include <asm/hardware/vic.h>
23#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
24#include <plat/pl080.h> 28#include <plat/pl080.h>
25#include <mach/generic.h> 29#include <mach/generic.h>
26#include <mach/hardware.h> 30#include <mach/spear.h>
27 31
28/* dmac device registration */ 32/* dmac device registration */
29static struct pl08x_channel_data spear600_dma_info[] = { 33static struct pl08x_channel_data spear600_dma_info[] = {
@@ -384,32 +388,29 @@ struct pl08x_platform_data pl080_plat_data = {
384 .num_slave_channels = ARRAY_SIZE(spear600_dma_info), 388 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
385}; 389};
386 390
387/* Following will create static virtual/physical mappings */ 391/*
388static struct map_desc spear6xx_io_desc[] __initdata = { 392 * Following will create 16MB static virtual/physical mappings
393 * PHYSICAL VIRTUAL
394 * 0xF0000000 0xF0000000
395 * 0xF1000000 0xF1000000
396 * 0xD0000000 0xFD000000
397 * 0xFC000000 0xFC000000
398 */
399struct map_desc spear6xx_io_desc[] __initdata = {
389 { 400 {
390 .virtual = VA_SPEAR6XX_ICM1_UART0_BASE, 401 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
391 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE), 402 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
392 .length = SZ_4K, 403 .length = 2 * SZ_16M,
393 .type = MT_DEVICE
394 }, {
395 .virtual = VA_SPEAR6XX_CPU_VIC_PRI_BASE,
396 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
397 .length = SZ_4K,
398 .type = MT_DEVICE 404 .type = MT_DEVICE
399 }, { 405 }, {
400 .virtual = VA_SPEAR6XX_CPU_VIC_SEC_BASE, 406 .virtual = VA_SPEAR6XX_ICM1_BASE,
401 .pfn = __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE), 407 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
402 .length = SZ_4K, 408 .length = SZ_16M,
403 .type = MT_DEVICE
404 }, {
405 .virtual = VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
406 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
407 .length = SZ_4K,
408 .type = MT_DEVICE 409 .type = MT_DEVICE
409 }, { 410 }, {
410 .virtual = VA_SPEAR6XX_ICM3_MISC_REG_BASE, 411 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
411 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE), 412 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
412 .length = SZ_4K, 413 .length = SZ_16M,
413 .type = MT_DEVICE 414 .type = MT_DEVICE
414 }, 415 },
415}; 416};
@@ -447,7 +448,7 @@ static void __init spear6xx_timer_init(void)
447 clk_put(gpt_clk); 448 clk_put(gpt_clk);
448 clk_put(pclk); 449 clk_put(pclk);
449 450
450 spear_setup_timer(); 451 spear_setup_timer(SPEAR6XX_CPU_TMR_BASE, IRQ_CPU_GPT1_1);
451} 452}
452 453
453struct sys_timer spear6xx_timer = { 454struct sys_timer spear6xx_timer = {
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 02b160a1ec9b..ab3de721c5db 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14#include <linux/amba/serial.h> 14#include <linux/amba/serial.h>
15#include <mach/hardware.h> 15#include <mach/spear.h>
16 16
17 .macro addruart, rp, rv, tmp 17 .macro addruart, rp, rv, tmp
18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base 18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
diff --git a/arch/arm/plat-spear/include/plat/hardware.h b/arch/arm/plat-spear/include/plat/hardware.h
deleted file mode 100644
index 70187d763e26..000000000000
--- a/arch/arm/plat-spear/include/plat/hardware.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/hardware.h
3 *
4 * Hardware definitions for SPEAr
5 *
6 * Copyright (C) 2010 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_HARDWARE_H
15#define __PLAT_HARDWARE_H
16
17#endif /* __PLAT_HARDWARE_H */
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 1bf84527aee4..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -13,7 +13,7 @@
13 13
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/amba/serial.h> 15#include <linux/amba/serial.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17 17
18#ifndef __PLAT_UNCOMPRESS_H 18#ifndef __PLAT_UNCOMPRESS_H
19#define __PLAT_UNCOMPRESS_H 19#define __PLAT_UNCOMPRESS_H
diff --git a/arch/arm/plat-spear/pl080.c b/arch/arm/plat-spear/pl080.c
index d53d75e1af5e..a56a067717c1 100644
--- a/arch/arm/plat-spear/pl080.c
+++ b/arch/arm/plat-spear/pl080.c
@@ -17,6 +17,7 @@
17#include <linux/err.h> 17#include <linux/err.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/spinlock_types.h> 19#include <linux/spinlock_types.h>
20#include <mach/spear.h>
20#include <mach/misc_regs.h> 21#include <mach/misc_regs.h>
21 22
22static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x); 23static spinlock_t lock = __SPIN_LOCK_UNLOCKED(x);
diff --git a/arch/arm/plat-spear/restart.c b/arch/arm/plat-spear/restart.c
index 16f203e78d89..4471a232713a 100644
--- a/arch/arm/plat-spear/restart.c
+++ b/arch/arm/plat-spear/restart.c
@@ -13,7 +13,7 @@
13#include <linux/io.h> 13#include <linux/io.h>
14#include <asm/system_misc.h> 14#include <asm/system_misc.h>
15#include <asm/hardware/sp810.h> 15#include <asm/hardware/sp810.h>
16#include <mach/hardware.h> 16#include <mach/spear.h>
17#include <mach/generic.h> 17#include <mach/generic.h>
18 18
19void spear_restart(char mode, const char *cmd) 19void spear_restart(char mode, const char *cmd)
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index abb5bdecd509..a3164d1647fd 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -15,14 +15,13 @@
15#include <linux/err.h> 15#include <linux/err.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/ioport.h>
18#include <linux/io.h> 19#include <linux/io.h>
19#include <linux/kernel.h> 20#include <linux/kernel.h>
20#include <linux/time.h> 21#include <linux/time.h>
21#include <linux/irq.h> 22#include <linux/irq.h>
22#include <asm/mach/time.h> 23#include <asm/mach/time.h>
23#include <mach/generic.h> 24#include <mach/generic.h>
24#include <mach/hardware.h>
25#include <mach/irqs.h>
26 25
27/* 26/*
28 * We would use TIMER0 and TIMER1 as clockevent and clocksource. 27 * We would use TIMER0 and TIMER1 as clockevent and clocksource.
@@ -175,7 +174,7 @@ static struct irqaction spear_timer_irq = {
175 .handler = spear_timer_interrupt 174 .handler = spear_timer_interrupt
176}; 175};
177 176
178static void __init spear_clockevent_init(void) 177static void __init spear_clockevent_init(int irq)
179{ 178{
180 u32 tick_rate; 179 u32 tick_rate;
181 180
@@ -195,19 +194,19 @@ static void __init spear_clockevent_init(void)
195 194
196 clockevents_register_device(&clkevt); 195 clockevents_register_device(&clkevt);
197 196
198 setup_irq(SPEAR_GPT0_CHAN0_IRQ, &spear_timer_irq); 197 setup_irq(irq, &spear_timer_irq);
199} 198}
200 199
201void __init spear_setup_timer(void) 200void __init spear_setup_timer(resource_size_t base, int irq)
202{ 201{
203 int ret; 202 int ret;
204 203
205 if (!request_mem_region(SPEAR_GPT0_BASE, SZ_1K, "gpt0")) { 204 if (!request_mem_region(base, SZ_1K, "gpt0")) {
206 pr_err("%s:cannot get IO addr\n", __func__); 205 pr_err("%s:cannot get IO addr\n", __func__);
207 return; 206 return;
208 } 207 }
209 208
210 gpt_base = (void __iomem *)ioremap(SPEAR_GPT0_BASE, SZ_1K); 209 gpt_base = ioremap(base, SZ_1K);
211 if (!gpt_base) { 210 if (!gpt_base) {
212 pr_err("%s:ioremap failed for gpt\n", __func__); 211 pr_err("%s:ioremap failed for gpt\n", __func__);
213 goto err_mem; 212 goto err_mem;
@@ -225,7 +224,7 @@ void __init spear_setup_timer(void)
225 goto err_clk; 224 goto err_clk;
226 } 225 }
227 226
228 spear_clockevent_init(); 227 spear_clockevent_init(irq);
229 spear_clocksource_init(); 228 spear_clocksource_init();
230 229
231 return; 230 return;
@@ -235,5 +234,5 @@ err_clk:
235err_iomap: 234err_iomap:
236 iounmap(gpt_base); 235 iounmap(gpt_base);
237err_mem: 236err_mem:
238 release_mem_region(SPEAR_GPT0_BASE, SZ_1K); 237 release_mem_region(base, SZ_1K);
239} 238}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 03:30:20 -0400