aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/mcbsp.c77
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h1
2 files changed, 0 insertions, 78 deletions
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 6e046e1111b1..660e00b3ef82 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -25,8 +25,6 @@
25#include <plat/omap_device.h> 25#include <plat/omap_device.h>
26#include <linux/pm_runtime.h> 26#include <linux/pm_runtime.h>
27 27
28#include "control.h"
29
30/* 28/*
31 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. 29 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
32 * Sidetone needs non-gated ICLK and sidetone autoidle is broken. 30 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
@@ -34,73 +32,6 @@
34#include "cm2xxx_3xxx.h" 32#include "cm2xxx_3xxx.h"
35#include "cm-regbits-34xx.h" 33#include "cm-regbits-34xx.h"
36 34
37/* McBSP1 internal signal muxing function for OMAP2/3 */
38static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
39 const char *src)
40{
41 u32 v;
42
43 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
44
45 if (!strcmp(signal, "clkr")) {
46 if (!strcmp(src, "clkr"))
47 v &= ~OMAP2_MCBSP1_CLKR_MASK;
48 else if (!strcmp(src, "clkx"))
49 v |= OMAP2_MCBSP1_CLKR_MASK;
50 else
51 return -EINVAL;
52 } else if (!strcmp(signal, "fsr")) {
53 if (!strcmp(src, "fsr"))
54 v &= ~OMAP2_MCBSP1_FSR_MASK;
55 else if (!strcmp(src, "fsx"))
56 v |= OMAP2_MCBSP1_FSR_MASK;
57 else
58 return -EINVAL;
59 } else {
60 return -EINVAL;
61 }
62
63 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
64
65 return 0;
66}
67
68/* McBSP4 internal signal muxing function for OMAP4 */
69#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
70#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
71static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
72 const char *src)
73{
74 u32 v;
75
76 /*
77 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
78 * mux) is used */
79 v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
80
81 if (!strcmp(signal, "clkr")) {
82 if (!strcmp(src, "clkr"))
83 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
84 else if (!strcmp(src, "clkx"))
85 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
86 else
87 return -EINVAL;
88 } else if (!strcmp(signal, "fsr")) {
89 if (!strcmp(src, "fsr"))
90 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
91 else if (!strcmp(src, "fsx"))
92 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
93 else
94 return -EINVAL;
95 } else {
96 return -EINVAL;
97 }
98
99 omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
100
101 return 0;
102}
103
104static int omap3_enable_st_clock(unsigned int id, bool enable) 35static int omap3_enable_st_clock(unsigned int id, bool enable)
105{ 36{
106 unsigned int w; 37 unsigned int w;
@@ -143,14 +74,6 @@ static int __init omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
143 pdata->has_ccr = true; 74 pdata->has_ccr = true;
144 } 75 }
145 76
146 /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
147 if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
148 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
149
150 /* On OMAP4 the McBSP4 port has 6 pin configuration */
151 if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
152 pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
153
154 if (oh->class->rev == MCBSP_CONFIG_TYPE2) { 77 if (oh->class->rev == MCBSP_CONFIG_TYPE2) {
155 /* The FIFO has 128 locations */ 78 /* The FIFO has 128 locations */
156 pdata->buffer_size = 0x80; 79 pdata->buffer_size = 0x80;
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 0a7d5ca471e0..c78d90b28b19 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -47,7 +47,6 @@ struct omap_mcbsp_platform_data {
47 bool has_wakeup; /* Wakeup capability */ 47 bool has_wakeup; /* Wakeup capability */
48 bool has_ccr; /* Transceiver has configuration control registers */ 48 bool has_ccr; /* Transceiver has configuration control registers */
49 int (*enable_st_clock)(unsigned int, bool); 49 int (*enable_st_clock)(unsigned int, bool);
50 int (*mux_signal)(struct device *dev, const char *signal, const char *src);
51}; 50};
52 51
53/** 52/**