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-rw-r--r--arch/arm/mach-s3c2410/bast-irq.c22
-rw-r--r--arch/arm/mach-s3c2412/irq.c50
-rw-r--r--arch/arm/mach-s3c2416/irq.c76
-rw-r--r--arch/arm/mach-s3c2440/irq.c18
-rw-r--r--arch/arm/mach-s3c2440/s3c244x-irq.c18
-rw-r--r--arch/arm/mach-s3c2443/irq.c95
-rw-r--r--arch/arm/mach-s5pv310/irq-combiner.c26
-rw-r--r--arch/arm/mach-s5pv310/irq-eint.c53
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/irq.h4
-rw-r--r--arch/arm/plat-s3c24xx/irq-pm.c9
-rw-r--r--arch/arm/plat-s3c24xx/irq.c180
-rw-r--r--arch/arm/plat-s5p/irq-eint.c82
-rw-r--r--arch/arm/plat-s5p/irq-gpioint.c50
-rw-r--r--arch/arm/plat-s5p/irq-pm.c6
-rw-r--r--arch/arm/plat-samsung/irq-uart.c6
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c4
16 files changed, 345 insertions, 354 deletions
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 217b102866d0..606cb6b1cc47 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -75,38 +75,38 @@ static unsigned char bast_pc104_irqmasks[] = {
75static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 }; 75static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
76 76
77static void 77static void
78bast_pc104_mask(unsigned int irqno) 78bast_pc104_mask(struct irq_data *data)
79{ 79{
80 unsigned long temp; 80 unsigned long temp;
81 81
82 temp = __raw_readb(BAST_VA_PC104_IRQMASK); 82 temp = __raw_readb(BAST_VA_PC104_IRQMASK);
83 temp &= ~bast_pc104_irqmasks[irqno]; 83 temp &= ~bast_pc104_irqmasks[data->irq];
84 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 84 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
85} 85}
86 86
87static void 87static void
88bast_pc104_maskack(unsigned int irqno) 88bast_pc104_maskack(struct irq_data *data)
89{ 89{
90 struct irq_desc *desc = irq_desc + IRQ_ISA; 90 struct irq_desc *desc = irq_desc + IRQ_ISA;
91 91
92 bast_pc104_mask(irqno); 92 bast_pc104_mask(data);
93 desc->chip->ack(IRQ_ISA); 93 desc->irq_data.chip->irq_ack(&desc->irq_data);
94} 94}
95 95
96static void 96static void
97bast_pc104_unmask(unsigned int irqno) 97bast_pc104_unmask(struct irq_data *data)
98{ 98{
99 unsigned long temp; 99 unsigned long temp;
100 100
101 temp = __raw_readb(BAST_VA_PC104_IRQMASK); 101 temp = __raw_readb(BAST_VA_PC104_IRQMASK);
102 temp |= bast_pc104_irqmasks[irqno]; 102 temp |= bast_pc104_irqmasks[data->irq];
103 __raw_writeb(temp, BAST_VA_PC104_IRQMASK); 103 __raw_writeb(temp, BAST_VA_PC104_IRQMASK);
104} 104}
105 105
106static struct irq_chip bast_pc104_chip = { 106static struct irq_chip bast_pc104_chip = {
107 .mask = bast_pc104_mask, 107 .irq_mask = bast_pc104_mask,
108 .unmask = bast_pc104_unmask, 108 .irq_unmask = bast_pc104_unmask,
109 .ack = bast_pc104_maskack 109 .irq_ack = bast_pc104_maskack
110}; 110};
111 111
112static void 112static void
@@ -123,7 +123,7 @@ bast_irq_pc104_demux(unsigned int irq,
123 /* ack if we get an irq with nothing (ie, startup) */ 123 /* ack if we get an irq with nothing (ie, startup) */
124 124
125 desc = irq_desc + IRQ_ISA; 125 desc = irq_desc + IRQ_ISA;
126 desc->chip->ack(IRQ_ISA); 126 desc->irq_data.chip->irq_ack(&desc->irq_data);
127 } else { 127 } else {
128 /* handle the IRQ */ 128 /* handle the IRQ */
129 129
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index 6000ca9d1815..eddb52ba5b65 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -49,9 +49,9 @@
49*/ 49*/
50 50
51static void 51static void
52s3c2412_irq_mask(unsigned int irqno) 52s3c2412_irq_mask(struct irq_data *data)
53{ 53{
54 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 54 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
55 unsigned long mask; 55 unsigned long mask;
56 56
57 mask = __raw_readl(S3C2410_INTMSK); 57 mask = __raw_readl(S3C2410_INTMSK);
@@ -62,9 +62,9 @@ s3c2412_irq_mask(unsigned int irqno)
62} 62}
63 63
64static inline void 64static inline void
65s3c2412_irq_ack(unsigned int irqno) 65s3c2412_irq_ack(struct irq_data *data)
66{ 66{
67 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 67 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
68 68
69 __raw_writel(bitval, S3C2412_EINTPEND); 69 __raw_writel(bitval, S3C2412_EINTPEND);
70 __raw_writel(bitval, S3C2410_SRCPND); 70 __raw_writel(bitval, S3C2410_SRCPND);
@@ -72,9 +72,9 @@ s3c2412_irq_ack(unsigned int irqno)
72} 72}
73 73
74static inline void 74static inline void
75s3c2412_irq_maskack(unsigned int irqno) 75s3c2412_irq_maskack(struct irq_data *data)
76{ 76{
77 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 77 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
78 unsigned long mask; 78 unsigned long mask;
79 79
80 mask = __raw_readl(S3C2410_INTMSK); 80 mask = __raw_readl(S3C2410_INTMSK);
@@ -89,9 +89,9 @@ s3c2412_irq_maskack(unsigned int irqno)
89} 89}
90 90
91static void 91static void
92s3c2412_irq_unmask(unsigned int irqno) 92s3c2412_irq_unmask(struct irq_data *data)
93{ 93{
94 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 94 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
95 unsigned long mask; 95 unsigned long mask;
96 96
97 mask = __raw_readl(S3C2412_EINTMASK); 97 mask = __raw_readl(S3C2412_EINTMASK);
@@ -102,11 +102,11 @@ s3c2412_irq_unmask(unsigned int irqno)
102} 102}
103 103
104static struct irq_chip s3c2412_irq_eint0t4 = { 104static struct irq_chip s3c2412_irq_eint0t4 = {
105 .ack = s3c2412_irq_ack, 105 .irq_ack = s3c2412_irq_ack,
106 .mask = s3c2412_irq_mask, 106 .irq_mask = s3c2412_irq_mask,
107 .unmask = s3c2412_irq_unmask, 107 .irq_unmask = s3c2412_irq_unmask,
108 .set_wake = s3c_irq_wake, 108 .irq_set_wake = s3c_irq_wake,
109 .set_type = s3c_irqext_type, 109 .irq_set_type = s3c_irqext_type,
110}; 110};
111 111
112#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0))) 112#define INTBIT(x) (1 << ((x) - S3C2410_IRQSUB(0)))
@@ -132,29 +132,29 @@ static void s3c2412_irq_demux_cfsdi(unsigned int irq, struct irq_desc *desc)
132#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0)) 132#define INTMSK_CFSDI (1UL << (IRQ_S3C2412_CFSDI - IRQ_EINT0))
133#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF) 133#define SUBMSK_CFSDI INTMSK_SUB(IRQ_S3C2412_SDI, IRQ_S3C2412_CF)
134 134
135static void s3c2412_irq_cfsdi_mask(unsigned int irqno) 135static void s3c2412_irq_cfsdi_mask(struct irq_data *data)
136{ 136{
137 s3c_irqsub_mask(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); 137 s3c_irqsub_mask(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
138} 138}
139 139
140static void s3c2412_irq_cfsdi_unmask(unsigned int irqno) 140static void s3c2412_irq_cfsdi_unmask(struct irq_data *data)
141{ 141{
142 s3c_irqsub_unmask(irqno, INTMSK_CFSDI); 142 s3c_irqsub_unmask(data->irq, INTMSK_CFSDI);
143} 143}
144 144
145static void s3c2412_irq_cfsdi_ack(unsigned int irqno) 145static void s3c2412_irq_cfsdi_ack(struct irq_data *data)
146{ 146{
147 s3c_irqsub_maskack(irqno, INTMSK_CFSDI, SUBMSK_CFSDI); 147 s3c_irqsub_maskack(data->irq, INTMSK_CFSDI, SUBMSK_CFSDI);
148} 148}
149 149
150static struct irq_chip s3c2412_irq_cfsdi = { 150static struct irq_chip s3c2412_irq_cfsdi = {
151 .name = "s3c2412-cfsdi", 151 .name = "s3c2412-cfsdi",
152 .ack = s3c2412_irq_cfsdi_ack, 152 .irq_ack = s3c2412_irq_cfsdi_ack,
153 .mask = s3c2412_irq_cfsdi_mask, 153 .irq_mask = s3c2412_irq_cfsdi_mask,
154 .unmask = s3c2412_irq_cfsdi_unmask, 154 .irq_unmask = s3c2412_irq_cfsdi_unmask,
155}; 155};
156 156
157static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state) 157static int s3c2412_irq_rtc_wake(struct irq_data *data, unsigned int state)
158{ 158{
159 unsigned long pwrcfg; 159 unsigned long pwrcfg;
160 160
@@ -165,7 +165,7 @@ static int s3c2412_irq_rtc_wake(unsigned int irqno, unsigned int state)
165 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ; 165 pwrcfg |= S3C2412_PWRCFG_RTC_MASKIRQ;
166 __raw_writel(pwrcfg, S3C2412_PWRCFG); 166 __raw_writel(pwrcfg, S3C2412_PWRCFG);
167 167
168 return s3c_irq_chip.set_wake(irqno, state); 168 return s3c_irq_chip.irq_set_wake(data, state);
169} 169}
170 170
171static struct irq_chip s3c2412_irq_rtc_chip; 171static struct irq_chip s3c2412_irq_rtc_chip;
@@ -193,7 +193,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
193 /* change RTC IRQ's set wake method */ 193 /* change RTC IRQ's set wake method */
194 194
195 s3c2412_irq_rtc_chip = s3c_irq_chip; 195 s3c2412_irq_rtc_chip = s3c_irq_chip;
196 s3c2412_irq_rtc_chip.set_wake = s3c2412_irq_rtc_wake; 196 s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
197 197
198 set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); 198 set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
199 199
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 00174daf1526..680fe386aca5 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -77,28 +77,27 @@ static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
77#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) 77#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
78#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) 78#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
79 79
80static void s3c2416_irq_wdtac97_mask(unsigned int irqno) 80static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
81{ 81{
82 s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); 82 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
83} 83}
84 84
85static void s3c2416_irq_wdtac97_unmask(unsigned int irqno) 85static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
86{ 86{
87 s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); 87 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
88} 88}
89 89
90static void s3c2416_irq_wdtac97_ack(unsigned int irqno) 90static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
91{ 91{
92 s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); 92 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
93} 93}
94 94
95static struct irq_chip s3c2416_irq_wdtac97 = { 95static struct irq_chip s3c2416_irq_wdtac97 = {
96 .mask = s3c2416_irq_wdtac97_mask, 96 .irq_mask = s3c2416_irq_wdtac97_mask,
97 .unmask = s3c2416_irq_wdtac97_unmask, 97 .irq_unmask = s3c2416_irq_wdtac97_unmask,
98 .ack = s3c2416_irq_wdtac97_ack, 98 .irq_ack = s3c2416_irq_wdtac97_ack,
99}; 99};
100 100
101
102/* LCD sub interrupts */ 101/* LCD sub interrupts */
103 102
104static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) 103static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@@ -109,28 +108,27 @@ static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
109#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) 108#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
110#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) 109#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
111 110
112static void s3c2416_irq_lcd_mask(unsigned int irqno) 111static void s3c2416_irq_lcd_mask(struct irq_data *data)
113{ 112{
114 s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); 113 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
115} 114}
116 115
117static void s3c2416_irq_lcd_unmask(unsigned int irqno) 116static void s3c2416_irq_lcd_unmask(struct irq_data *data)
118{ 117{
119 s3c_irqsub_unmask(irqno, INTMSK_LCD); 118 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
120} 119}
121 120
122static void s3c2416_irq_lcd_ack(unsigned int irqno) 121static void s3c2416_irq_lcd_ack(struct irq_data *data)
123{ 122{
124 s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); 123 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
125} 124}
126 125
127static struct irq_chip s3c2416_irq_lcd = { 126static struct irq_chip s3c2416_irq_lcd = {
128 .mask = s3c2416_irq_lcd_mask, 127 .irq_mask = s3c2416_irq_lcd_mask,
129 .unmask = s3c2416_irq_lcd_unmask, 128 .irq_unmask = s3c2416_irq_lcd_unmask,
130 .ack = s3c2416_irq_lcd_ack, 129 .irq_ack = s3c2416_irq_lcd_ack,
131}; 130};
132 131
133
134/* DMA sub interrupts */ 132/* DMA sub interrupts */
135 133
136static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc) 134static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@@ -142,28 +140,27 @@ static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
142#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) 140#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
143 141
144 142
145static void s3c2416_irq_dma_mask(unsigned int irqno) 143static void s3c2416_irq_dma_mask(struct irq_data *data)
146{ 144{
147 s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); 145 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
148} 146}
149 147
150static void s3c2416_irq_dma_unmask(unsigned int irqno) 148static void s3c2416_irq_dma_unmask(struct irq_data *data)
151{ 149{
152 s3c_irqsub_unmask(irqno, INTMSK_DMA); 150 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
153} 151}
154 152
155static void s3c2416_irq_dma_ack(unsigned int irqno) 153static void s3c2416_irq_dma_ack(struct irq_data *data)
156{ 154{
157 s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); 155 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
158} 156}
159 157
160static struct irq_chip s3c2416_irq_dma = { 158static struct irq_chip s3c2416_irq_dma = {
161 .mask = s3c2416_irq_dma_mask, 159 .irq_mask = s3c2416_irq_dma_mask,
162 .unmask = s3c2416_irq_dma_unmask, 160 .irq_unmask = s3c2416_irq_dma_unmask,
163 .ack = s3c2416_irq_dma_ack, 161 .irq_ack = s3c2416_irq_dma_ack,
164}; 162};
165 163
166
167/* UART3 sub interrupts */ 164/* UART3 sub interrupts */
168 165
169static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) 166static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@@ -174,28 +171,27 @@ static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
174#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) 171#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
175#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) 172#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
176 173
177static void s3c2416_irq_uart3_mask(unsigned int irqno) 174static void s3c2416_irq_uart3_mask(struct irq_data *data)
178{ 175{
179 s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); 176 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
180} 177}
181 178
182static void s3c2416_irq_uart3_unmask(unsigned int irqno) 179static void s3c2416_irq_uart3_unmask(struct irq_data *data)
183{ 180{
184 s3c_irqsub_unmask(irqno, INTMSK_UART3); 181 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
185} 182}
186 183
187static void s3c2416_irq_uart3_ack(unsigned int irqno) 184static void s3c2416_irq_uart3_ack(struct irq_data *data)
188{ 185{
189 s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); 186 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
190} 187}
191 188
192static struct irq_chip s3c2416_irq_uart3 = { 189static struct irq_chip s3c2416_irq_uart3 = {
193 .mask = s3c2416_irq_uart3_mask, 190 .irq_mask = s3c2416_irq_uart3_mask,
194 .unmask = s3c2416_irq_uart3_unmask, 191 .irq_unmask = s3c2416_irq_uart3_unmask,
195 .ack = s3c2416_irq_uart3_ack, 192 .irq_ack = s3c2416_irq_uart3_ack,
196}; 193};
197 194
198
199/* IRQ initialisation code */ 195/* IRQ initialisation code */
200 196
201static int __init s3c2416_add_sub(unsigned int base, 197static int __init s3c2416_add_sub(unsigned int base,
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index 0c049b95c378..acad4428bef0 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -69,27 +69,27 @@ static void s3c_irq_demux_wdtac97(unsigned int irq,
69#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0)) 69#define INTMSK_WDT (1UL << (IRQ_WDT - IRQ_EINT0))
70 70
71static void 71static void
72s3c_irq_wdtac97_mask(unsigned int irqno) 72s3c_irq_wdtac97_mask(struct irq_data *data)
73{ 73{
74 s3c_irqsub_mask(irqno, INTMSK_WDT, 3<<13); 74 s3c_irqsub_mask(data->irq, INTMSK_WDT, 3 << 13);
75} 75}
76 76
77static void 77static void
78s3c_irq_wdtac97_unmask(unsigned int irqno) 78s3c_irq_wdtac97_unmask(struct irq_data *data)
79{ 79{
80 s3c_irqsub_unmask(irqno, INTMSK_WDT); 80 s3c_irqsub_unmask(data->irq, INTMSK_WDT);
81} 81}
82 82
83static void 83static void
84s3c_irq_wdtac97_ack(unsigned int irqno) 84s3c_irq_wdtac97_ack(struct irq_data *data)
85{ 85{
86 s3c_irqsub_maskack(irqno, INTMSK_WDT, 3<<13); 86 s3c_irqsub_maskack(data->irq, INTMSK_WDT, 3 << 13);
87} 87}
88 88
89static struct irq_chip s3c_irq_wdtac97 = { 89static struct irq_chip s3c_irq_wdtac97 = {
90 .mask = s3c_irq_wdtac97_mask, 90 .irq_mask = s3c_irq_wdtac97_mask,
91 .unmask = s3c_irq_wdtac97_unmask, 91 .irq_unmask = s3c_irq_wdtac97_unmask,
92 .ack = s3c_irq_wdtac97_ack, 92 .irq_ack = s3c_irq_wdtac97_ack,
93}; 93};
94 94
95static int s3c2440_irq_add(struct sys_device *sysdev) 95static int s3c2440_irq_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index a75c0c2431ea..83daf4ece764 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -68,27 +68,27 @@ static void s3c_irq_demux_cam(unsigned int irq,
68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) 68#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
69 69
70static void 70static void
71s3c_irq_cam_mask(unsigned int irqno) 71s3c_irq_cam_mask(struct irq_data *data)
72{ 72{
73 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11); 73 s3c_irqsub_mask(data->irq, INTMSK_CAM, 3 << 11);
74} 74}
75 75
76static void 76static void
77s3c_irq_cam_unmask(unsigned int irqno) 77s3c_irq_cam_unmask(struct irq_data *data)
78{ 78{
79 s3c_irqsub_unmask(irqno, INTMSK_CAM); 79 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
80} 80}
81 81
82static void 82static void
83s3c_irq_cam_ack(unsigned int irqno) 83s3c_irq_cam_ack(struct irq_data *data)
84{ 84{
85 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11); 85 s3c_irqsub_maskack(data->irq, INTMSK_CAM, 3 << 11);
86} 86}
87 87
88static struct irq_chip s3c_irq_cam = { 88static struct irq_chip s3c_irq_cam = {
89 .mask = s3c_irq_cam_mask, 89 .irq_mask = s3c_irq_cam_mask,
90 .unmask = s3c_irq_cam_unmask, 90 .irq_unmask = s3c_irq_cam_unmask,
91 .ack = s3c_irq_cam_ack, 91 .irq_ack = s3c_irq_cam_ack,
92}; 92};
93 93
94static int s3c244x_irq_add(struct sys_device *sysdev) 94static int s3c244x_irq_add(struct sys_device *sysdev)
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index 893424767ce1..c7820f9c1352 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -75,28 +75,27 @@ static void s3c2443_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
75#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0)) 75#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
76#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97) 76#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
77 77
78static void s3c2443_irq_wdtac97_mask(unsigned int irqno) 78static void s3c2443_irq_wdtac97_mask(struct irq_data *data)
79{ 79{
80 s3c_irqsub_mask(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); 80 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
81} 81}
82 82
83static void s3c2443_irq_wdtac97_unmask(unsigned int irqno) 83static void s3c2443_irq_wdtac97_unmask(struct irq_data *data)
84{ 84{
85 s3c_irqsub_unmask(irqno, INTMSK_WDTAC97); 85 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
86} 86}
87 87
88static void s3c2443_irq_wdtac97_ack(unsigned int irqno) 88static void s3c2443_irq_wdtac97_ack(struct irq_data *data)
89{ 89{
90 s3c_irqsub_maskack(irqno, INTMSK_WDTAC97, SUBMSK_WDTAC97); 90 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
91} 91}
92 92
93static struct irq_chip s3c2443_irq_wdtac97 = { 93static struct irq_chip s3c2443_irq_wdtac97 = {
94 .mask = s3c2443_irq_wdtac97_mask, 94 .irq_mask = s3c2443_irq_wdtac97_mask,
95 .unmask = s3c2443_irq_wdtac97_unmask, 95 .irq_unmask = s3c2443_irq_wdtac97_unmask,
96 .ack = s3c2443_irq_wdtac97_ack, 96 .irq_ack = s3c2443_irq_wdtac97_ack,
97}; 97};
98 98
99
100/* LCD sub interrupts */ 99/* LCD sub interrupts */
101 100
102static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc) 101static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
@@ -107,28 +106,27 @@ static void s3c2443_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
107#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0)) 106#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
108#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4) 107#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
109 108
110static void s3c2443_irq_lcd_mask(unsigned int irqno) 109static void s3c2443_irq_lcd_mask(struct irq_data *data)
111{ 110{
112 s3c_irqsub_mask(irqno, INTMSK_LCD, SUBMSK_LCD); 111 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
113} 112}
114 113
115static void s3c2443_irq_lcd_unmask(unsigned int irqno) 114static void s3c2443_irq_lcd_unmask(struct irq_data *data)
116{ 115{
117 s3c_irqsub_unmask(irqno, INTMSK_LCD); 116 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
118} 117}
119 118
120static void s3c2443_irq_lcd_ack(unsigned int irqno) 119static void s3c2443_irq_lcd_ack(struct irq_data *data)
121{ 120{
122 s3c_irqsub_maskack(irqno, INTMSK_LCD, SUBMSK_LCD); 121 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
123} 122}
124 123
125static struct irq_chip s3c2443_irq_lcd = { 124static struct irq_chip s3c2443_irq_lcd = {
126 .mask = s3c2443_irq_lcd_mask, 125 .irq_mask = s3c2443_irq_lcd_mask,
127 .unmask = s3c2443_irq_lcd_unmask, 126 .irq_unmask = s3c2443_irq_lcd_unmask,
128 .ack = s3c2443_irq_lcd_ack, 127 .irq_ack = s3c2443_irq_lcd_ack,
129}; 128};
130 129
131
132/* DMA sub interrupts */ 130/* DMA sub interrupts */
133 131
134static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc) 132static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
@@ -139,29 +137,27 @@ static void s3c2443_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
139#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0)) 137#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
140#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5) 138#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
141 139
142 140static void s3c2443_irq_dma_mask(struct irq_data *data)
143static void s3c2443_irq_dma_mask(unsigned int irqno)
144{ 141{
145 s3c_irqsub_mask(irqno, INTMSK_DMA, SUBMSK_DMA); 142 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
146} 143}
147 144
148static void s3c2443_irq_dma_unmask(unsigned int irqno) 145static void s3c2443_irq_dma_unmask(struct irq_data *data)
149{ 146{
150 s3c_irqsub_unmask(irqno, INTMSK_DMA); 147 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
151} 148}
152 149
153static void s3c2443_irq_dma_ack(unsigned int irqno) 150static void s3c2443_irq_dma_ack(struct irq_data *data)
154{ 151{
155 s3c_irqsub_maskack(irqno, INTMSK_DMA, SUBMSK_DMA); 152 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
156} 153}
157 154
158static struct irq_chip s3c2443_irq_dma = { 155static struct irq_chip s3c2443_irq_dma = {
159 .mask = s3c2443_irq_dma_mask, 156 .irq_mask = s3c2443_irq_dma_mask,
160 .unmask = s3c2443_irq_dma_unmask, 157 .irq_unmask = s3c2443_irq_dma_unmask,
161 .ack = s3c2443_irq_dma_ack, 158 .irq_ack = s3c2443_irq_dma_ack,
162}; 159};
163 160
164
165/* UART3 sub interrupts */ 161/* UART3 sub interrupts */
166 162
167static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc) 163static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
@@ -172,28 +168,27 @@ static void s3c2443_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
172#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0)) 168#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
173#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0))) 169#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
174 170
175static void s3c2443_irq_uart3_mask(unsigned int irqno) 171static void s3c2443_irq_uart3_mask(struct irq_data *data)
176{ 172{
177 s3c_irqsub_mask(irqno, INTMSK_UART3, SUBMSK_UART3); 173 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
178} 174}
179 175
180static void s3c2443_irq_uart3_unmask(unsigned int irqno) 176static void s3c2443_irq_uart3_unmask(struct irq_data *data)
181{ 177{
182 s3c_irqsub_unmask(irqno, INTMSK_UART3); 178 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
183} 179}
184 180
185static void s3c2443_irq_uart3_ack(unsigned int irqno) 181static void s3c2443_irq_uart3_ack(struct irq_data *data)
186{ 182{
187 s3c_irqsub_maskack(irqno, INTMSK_UART3, SUBMSK_UART3); 183 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
188} 184}
189 185
190static struct irq_chip s3c2443_irq_uart3 = { 186static struct irq_chip s3c2443_irq_uart3 = {
191 .mask = s3c2443_irq_uart3_mask, 187 .irq_mask = s3c2443_irq_uart3_mask,
192 .unmask = s3c2443_irq_uart3_unmask, 188 .irq_unmask = s3c2443_irq_uart3_unmask,
193 .ack = s3c2443_irq_uart3_ack, 189 .irq_ack = s3c2443_irq_uart3_ack,
194}; 190};
195 191
196
197/* CAM sub interrupts */ 192/* CAM sub interrupts */
198 193
199static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc) 194static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
@@ -204,25 +199,25 @@ static void s3c2443_irq_demux_cam(unsigned int irq, struct irq_desc *desc)
204#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0)) 199#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
205#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P) 200#define SUBMSK_CAM INTMSK(IRQ_S3C2440_CAM_C, IRQ_S3C2440_CAM_P)
206 201
207static void s3c2443_irq_cam_mask(unsigned int irqno) 202static void s3c2443_irq_cam_mask(struct irq_data *data)
208{ 203{
209 s3c_irqsub_mask(irqno, INTMSK_CAM, SUBMSK_CAM); 204 s3c_irqsub_mask(data->irq, INTMSK_CAM, SUBMSK_CAM);
210} 205}
211 206
212static void s3c2443_irq_cam_unmask(unsigned int irqno) 207static void s3c2443_irq_cam_unmask(struct irq_data *data)
213{ 208{
214 s3c_irqsub_unmask(irqno, INTMSK_CAM); 209 s3c_irqsub_unmask(data->irq, INTMSK_CAM);
215} 210}
216 211
217static void s3c2443_irq_cam_ack(unsigned int irqno) 212static void s3c2443_irq_cam_ack(struct irq_data *data)
218{ 213{
219 s3c_irqsub_maskack(irqno, INTMSK_CAM, SUBMSK_CAM); 214 s3c_irqsub_maskack(data->irq, INTMSK_CAM, SUBMSK_CAM);
220} 215}
221 216
222static struct irq_chip s3c2443_irq_cam = { 217static struct irq_chip s3c2443_irq_cam = {
223 .mask = s3c2443_irq_cam_mask, 218 .irq_mask = s3c2443_irq_cam_mask,
224 .unmask = s3c2443_irq_cam_unmask, 219 .irq_unmask = s3c2443_irq_cam_unmask,
225 .ack = s3c2443_irq_cam_ack, 220 .irq_ack = s3c2443_irq_cam_ack,
226}; 221};
227 222
228/* IRQ initialisation code */ 223/* IRQ initialisation code */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
index aad5c3d525d1..1ea4a9e83bbe 100644
--- a/arch/arm/mach-s5pv310/irq-combiner.c
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -30,24 +30,26 @@ struct combiner_chip_data {
30 30
31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR]; 31static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
32 32
33static inline void __iomem *combiner_base(unsigned int irq) 33static inline void __iomem *combiner_base(struct irq_data *data)
34{ 34{
35 struct combiner_chip_data *combiner_data = get_irq_chip_data(irq); 35 struct combiner_chip_data *combiner_data =
36 irq_data_get_irq_chip_data(data);
37
36 return combiner_data->base; 38 return combiner_data->base;
37} 39}
38 40
39static void combiner_mask_irq(unsigned int irq) 41static void combiner_mask_irq(struct irq_data *data)
40{ 42{
41 u32 mask = 1 << (irq % 32); 43 u32 mask = 1 << (data->irq % 32);
42 44
43 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR); 45 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
44} 46}
45 47
46static void combiner_unmask_irq(unsigned int irq) 48static void combiner_unmask_irq(struct irq_data *data)
47{ 49{
48 u32 mask = 1 << (irq % 32); 50 u32 mask = 1 << (data->irq % 32);
49 51
50 __raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET); 52 __raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
51} 53}
52 54
53static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 55static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
@@ -58,7 +60,7 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
58 unsigned long status; 60 unsigned long status;
59 61
60 /* primary controller ack'ing */ 62 /* primary controller ack'ing */
61 chip->ack(irq); 63 chip->irq_ack(&desc->irq_data);
62 64
63 spin_lock(&irq_controller_lock); 65 spin_lock(&irq_controller_lock);
64 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS); 66 status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -78,13 +80,13 @@ static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
78 80
79 out: 81 out:
80 /* primary controller unmasking */ 82 /* primary controller unmasking */
81 chip->unmask(irq); 83 chip->irq_unmask(&desc->irq_data);
82} 84}
83 85
84static struct irq_chip combiner_chip = { 86static struct irq_chip combiner_chip = {
85 .name = "COMBINER", 87 .name = "COMBINER",
86 .mask = combiner_mask_irq, 88 .irq_mask = combiner_mask_irq,
87 .unmask = combiner_unmask_irq, 89 .irq_unmask = combiner_unmask_irq,
88}; 90};
89 91
90void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) 92void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
diff --git a/arch/arm/mach-s5pv310/irq-eint.c b/arch/arm/mach-s5pv310/irq-eint.c
index f5a415edc0b6..477bd9e97f0f 100644
--- a/arch/arm/mach-s5pv310/irq-eint.c
+++ b/arch/arm/mach-s5pv310/irq-eint.c
@@ -48,42 +48,43 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
48 return ret; 48 return ret;
49} 49}
50 50
51static inline void s5pv310_irq_eint_mask(unsigned int irq) 51static inline void s5pv310_irq_eint_mask(struct irq_data *data)
52{ 52{
53 u32 mask; 53 u32 mask;
54 54
55 spin_lock(&eint_lock); 55 spin_lock(&eint_lock);
56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 56 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
57 mask |= eint_irq_to_bit(irq); 57 mask |= eint_irq_to_bit(data->irq);
58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 58 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
59 spin_unlock(&eint_lock); 59 spin_unlock(&eint_lock);
60} 60}
61 61
62static void s5pv310_irq_eint_unmask(unsigned int irq) 62static void s5pv310_irq_eint_unmask(struct irq_data *data)
63{ 63{
64 u32 mask; 64 u32 mask;
65 65
66 spin_lock(&eint_lock); 66 spin_lock(&eint_lock);
67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 67 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
68 mask &= ~(eint_irq_to_bit(irq)); 68 mask &= ~(eint_irq_to_bit(data->irq));
69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 69 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
70 spin_unlock(&eint_lock); 70 spin_unlock(&eint_lock);
71} 71}
72 72
73static inline void s5pv310_irq_eint_ack(unsigned int irq) 73static inline void s5pv310_irq_eint_ack(struct irq_data *data)
74{ 74{
75 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); 75 __raw_writel(eint_irq_to_bit(data->irq),
76 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
76} 77}
77 78
78static void s5pv310_irq_eint_maskack(unsigned int irq) 79static void s5pv310_irq_eint_maskack(struct irq_data *data)
79{ 80{
80 s5pv310_irq_eint_mask(irq); 81 s5pv310_irq_eint_mask(data);
81 s5pv310_irq_eint_ack(irq); 82 s5pv310_irq_eint_ack(data);
82} 83}
83 84
84static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type) 85static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
85{ 86{
86 int offs = EINT_OFFSET(irq); 87 int offs = EINT_OFFSET(data->irq);
87 int shift; 88 int shift;
88 u32 ctrl, mask; 89 u32 ctrl, mask;
89 u32 newvalue = 0; 90 u32 newvalue = 0;
@@ -118,10 +119,10 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
118 mask = 0x7 << shift; 119 mask = 0x7 << shift;
119 120
120 spin_lock(&eint_lock); 121 spin_lock(&eint_lock);
121 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); 122 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
122 ctrl &= ~mask; 123 ctrl &= ~mask;
123 ctrl |= newvalue << shift; 124 ctrl |= newvalue << shift;
124 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); 125 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
125 spin_unlock(&eint_lock); 126 spin_unlock(&eint_lock);
126 127
127 switch (offs) { 128 switch (offs) {
@@ -146,11 +147,11 @@ static int s5pv310_irq_eint_set_type(unsigned int irq, unsigned int type)
146 147
147static struct irq_chip s5pv310_irq_eint = { 148static struct irq_chip s5pv310_irq_eint = {
148 .name = "s5pv310-eint", 149 .name = "s5pv310-eint",
149 .mask = s5pv310_irq_eint_mask, 150 .irq_mask = s5pv310_irq_eint_mask,
150 .unmask = s5pv310_irq_eint_unmask, 151 .irq_unmask = s5pv310_irq_eint_unmask,
151 .mask_ack = s5pv310_irq_eint_maskack, 152 .irq_mask_ack = s5pv310_irq_eint_maskack,
152 .ack = s5pv310_irq_eint_ack, 153 .irq_ack = s5pv310_irq_eint_ack,
153 .set_type = s5pv310_irq_eint_set_type, 154 .irq_set_type = s5pv310_irq_eint_set_type,
154#ifdef CONFIG_PM 155#ifdef CONFIG_PM
155 .irq_set_wake = s3c_irqext_wake, 156 .irq_set_wake = s3c_irqext_wake,
156#endif 157#endif
@@ -192,14 +193,14 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
192 u32 *irq_data = get_irq_data(irq); 193 u32 *irq_data = get_irq_data(irq);
193 struct irq_chip *chip = get_irq_chip(irq); 194 struct irq_chip *chip = get_irq_chip(irq);
194 195
195 chip->mask(irq); 196 chip->irq_mask(&desc->irq_data);
196 197
197 if (chip->ack) 198 if (chip->irq_ack)
198 chip->ack(irq); 199 chip->irq_ack(&desc->irq_data);
199 200
200 generic_handle_irq(*irq_data); 201 generic_handle_irq(*irq_data);
201 202
202 chip->unmask(irq); 203 chip->irq_unmask(&desc->irq_data);
203} 204}
204 205
205int __init s5pv310_init_irq_eint(void) 206int __init s5pv310_init_irq_eint(void)
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h
index 69e1be8bec35..ec087d6054b1 100644
--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
@@ -107,9 +107,9 @@ s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
107/* exported for use in arch/arm/mach-s3c2410 */ 107/* exported for use in arch/arm/mach-s3c2410 */
108 108
109#ifdef CONFIG_PM 109#ifdef CONFIG_PM
110extern int s3c_irq_wake(unsigned int irqno, unsigned int state); 110extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
111#else 111#else
112#define s3c_irq_wake NULL 112#define s3c_irq_wake NULL
113#endif 113#endif
114 114
115extern int s3c_irqext_type(unsigned int irq, unsigned int type); 115extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c
index ea8dea3339a4..c3624d898630 100644
--- a/arch/arm/plat-s3c24xx/irq-pm.c
+++ b/arch/arm/plat-s3c24xx/irq-pm.c
@@ -15,11 +15,14 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/sysdev.h> 17#include <linux/sysdev.h>
18#include <linux/irq.h>
18 19
19#include <plat/cpu.h> 20#include <plat/cpu.h>
20#include <plat/pm.h> 21#include <plat/pm.h>
21#include <plat/irq.h> 22#include <plat/irq.h>
22 23
24#include <asm/irq.h>
25
23/* state for IRQs over sleep */ 26/* state for IRQs over sleep */
24 27
25/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources 28/* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
@@ -30,15 +33,15 @@
30unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; 33unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
31unsigned long s3c_irqwake_eintallow = 0x0000fff0L; 34unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
32 35
33int s3c_irq_wake(unsigned int irqno, unsigned int state) 36int s3c_irq_wake(struct irq_data *data, unsigned int state)
34{ 37{
35 unsigned long irqbit = 1 << (irqno - IRQ_EINT0); 38 unsigned long irqbit = 1 << (data->irq - IRQ_EINT0);
36 39
37 if (!(s3c_irqwake_intallow & irqbit)) 40 if (!(s3c_irqwake_intallow & irqbit))
38 return -ENOENT; 41 return -ENOENT;
39 42
40 printk(KERN_INFO "wake %s for irq %d\n", 43 printk(KERN_INFO "wake %s for irq %d\n",
41 state ? "enabled" : "disabled", irqno); 44 state ? "enabled" : "disabled", data->irq);
42 45
43 if (!state) 46 if (!state)
44 s3c_irqwake_intmask |= irqbit; 47 s3c_irqwake_intmask |= irqbit;
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 91ce38393ba6..4434cb56bd9a 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -34,30 +34,29 @@
34#include <plat/irq.h> 34#include <plat/irq.h>
35 35
36static void 36static void
37s3c_irq_mask(unsigned int irqno) 37s3c_irq_mask(struct irq_data *data)
38{ 38{
39 unsigned int irqno = data->irq - IRQ_EINT0;
39 unsigned long mask; 40 unsigned long mask;
40 41
41 irqno -= IRQ_EINT0;
42
43 mask = __raw_readl(S3C2410_INTMSK); 42 mask = __raw_readl(S3C2410_INTMSK);
44 mask |= 1UL << irqno; 43 mask |= 1UL << irqno;
45 __raw_writel(mask, S3C2410_INTMSK); 44 __raw_writel(mask, S3C2410_INTMSK);
46} 45}
47 46
48static inline void 47static inline void
49s3c_irq_ack(unsigned int irqno) 48s3c_irq_ack(struct irq_data *data)
50{ 49{
51 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 50 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
52 51
53 __raw_writel(bitval, S3C2410_SRCPND); 52 __raw_writel(bitval, S3C2410_SRCPND);
54 __raw_writel(bitval, S3C2410_INTPND); 53 __raw_writel(bitval, S3C2410_INTPND);
55} 54}
56 55
57static inline void 56static inline void
58s3c_irq_maskack(unsigned int irqno) 57s3c_irq_maskack(struct irq_data *data)
59{ 58{
60 unsigned long bitval = 1UL << (irqno - IRQ_EINT0); 59 unsigned long bitval = 1UL << (data->irq - IRQ_EINT0);
61 unsigned long mask; 60 unsigned long mask;
62 61
63 mask = __raw_readl(S3C2410_INTMSK); 62 mask = __raw_readl(S3C2410_INTMSK);
@@ -69,8 +68,9 @@ s3c_irq_maskack(unsigned int irqno)
69 68
70 69
71static void 70static void
72s3c_irq_unmask(unsigned int irqno) 71s3c_irq_unmask(struct irq_data *data)
73{ 72{
73 unsigned int irqno = data->irq;
74 unsigned long mask; 74 unsigned long mask;
75 75
76 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) 76 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
@@ -85,40 +85,39 @@ s3c_irq_unmask(unsigned int irqno)
85 85
86struct irq_chip s3c_irq_level_chip = { 86struct irq_chip s3c_irq_level_chip = {
87 .name = "s3c-level", 87 .name = "s3c-level",
88 .ack = s3c_irq_maskack, 88 .irq_ack = s3c_irq_maskack,
89 .mask = s3c_irq_mask, 89 .irq_mask = s3c_irq_mask,
90 .unmask = s3c_irq_unmask, 90 .irq_unmask = s3c_irq_unmask,
91 .set_wake = s3c_irq_wake 91 .irq_set_wake = s3c_irq_wake
92}; 92};
93 93
94struct irq_chip s3c_irq_chip = { 94struct irq_chip s3c_irq_chip = {
95 .name = "s3c", 95 .name = "s3c",
96 .ack = s3c_irq_ack, 96 .irq_ack = s3c_irq_ack,
97 .mask = s3c_irq_mask, 97 .irq_mask = s3c_irq_mask,
98 .unmask = s3c_irq_unmask, 98 .irq_unmask = s3c_irq_unmask,
99 .set_wake = s3c_irq_wake 99 .irq_set_wake = s3c_irq_wake
100}; 100};
101 101
102static void 102static void
103s3c_irqext_mask(unsigned int irqno) 103s3c_irqext_mask(struct irq_data *data)
104{ 104{
105 unsigned int irqno = data->irq - EXTINT_OFF;
105 unsigned long mask; 106 unsigned long mask;
106 107
107 irqno -= EXTINT_OFF;
108
109 mask = __raw_readl(S3C24XX_EINTMASK); 108 mask = __raw_readl(S3C24XX_EINTMASK);
110 mask |= ( 1UL << irqno); 109 mask |= ( 1UL << irqno);
111 __raw_writel(mask, S3C24XX_EINTMASK); 110 __raw_writel(mask, S3C24XX_EINTMASK);
112} 111}
113 112
114static void 113static void
115s3c_irqext_ack(unsigned int irqno) 114s3c_irqext_ack(struct irq_data *data)
116{ 115{
117 unsigned long req; 116 unsigned long req;
118 unsigned long bit; 117 unsigned long bit;
119 unsigned long mask; 118 unsigned long mask;
120 119
121 bit = 1UL << (irqno - EXTINT_OFF); 120 bit = 1UL << (data->irq - EXTINT_OFF);
122 121
123 mask = __raw_readl(S3C24XX_EINTMASK); 122 mask = __raw_readl(S3C24XX_EINTMASK);
124 123
@@ -129,64 +128,57 @@ s3c_irqext_ack(unsigned int irqno)
129 128
130 /* not sure if we should be acking the parent irq... */ 129 /* not sure if we should be acking the parent irq... */
131 130
132 if (irqno <= IRQ_EINT7 ) { 131 if (data->irq <= IRQ_EINT7) {
133 if ((req & 0xf0) == 0) 132 if ((req & 0xf0) == 0)
134 s3c_irq_ack(IRQ_EINT4t7); 133 s3c_irq_ack(irq_get_irq_data(IRQ_EINT4t7));
135 } else { 134 } else {
136 if ((req >> 8) == 0) 135 if ((req >> 8) == 0)
137 s3c_irq_ack(IRQ_EINT8t23); 136 s3c_irq_ack(irq_get_irq_data(IRQ_EINT8t23));
138 } 137 }
139} 138}
140 139
141static void 140static void
142s3c_irqext_unmask(unsigned int irqno) 141s3c_irqext_unmask(struct irq_data *data)
143{ 142{
143 unsigned int irqno = data->irq - EXTINT_OFF;
144 unsigned long mask; 144 unsigned long mask;
145 145
146 irqno -= EXTINT_OFF;
147
148 mask = __raw_readl(S3C24XX_EINTMASK); 146 mask = __raw_readl(S3C24XX_EINTMASK);
149 mask &= ~( 1UL << irqno); 147 mask &= ~(1UL << irqno);
150 __raw_writel(mask, S3C24XX_EINTMASK); 148 __raw_writel(mask, S3C24XX_EINTMASK);
151} 149}
152 150
153int 151int
154s3c_irqext_type(unsigned int irq, unsigned int type) 152s3c_irqext_type(struct irq_data *data, unsigned int type)
155{ 153{
156 void __iomem *extint_reg; 154 void __iomem *extint_reg;
157 void __iomem *gpcon_reg; 155 void __iomem *gpcon_reg;
158 unsigned long gpcon_offset, extint_offset; 156 unsigned long gpcon_offset, extint_offset;
159 unsigned long newvalue = 0, value; 157 unsigned long newvalue = 0, value;
160 158
161 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) 159 if ((data->irq >= IRQ_EINT0) && (data->irq <= IRQ_EINT3)) {
162 {
163 gpcon_reg = S3C2410_GPFCON; 160 gpcon_reg = S3C2410_GPFCON;
164 extint_reg = S3C24XX_EXTINT0; 161 extint_reg = S3C24XX_EXTINT0;
165 gpcon_offset = (irq - IRQ_EINT0) * 2; 162 gpcon_offset = (data->irq - IRQ_EINT0) * 2;
166 extint_offset = (irq - IRQ_EINT0) * 4; 163 extint_offset = (data->irq - IRQ_EINT0) * 4;
167 } 164 } else if ((data->irq >= IRQ_EINT4) && (data->irq <= IRQ_EINT7)) {
168 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
169 {
170 gpcon_reg = S3C2410_GPFCON; 165 gpcon_reg = S3C2410_GPFCON;
171 extint_reg = S3C24XX_EXTINT0; 166 extint_reg = S3C24XX_EXTINT0;
172 gpcon_offset = (irq - (EXTINT_OFF)) * 2; 167 gpcon_offset = (data->irq - (EXTINT_OFF)) * 2;
173 extint_offset = (irq - (EXTINT_OFF)) * 4; 168 extint_offset = (data->irq - (EXTINT_OFF)) * 4;
174 } 169 } else if ((data->irq >= IRQ_EINT8) && (data->irq <= IRQ_EINT15)) {
175 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
176 {
177 gpcon_reg = S3C2410_GPGCON; 170 gpcon_reg = S3C2410_GPGCON;
178 extint_reg = S3C24XX_EXTINT1; 171 extint_reg = S3C24XX_EXTINT1;
179 gpcon_offset = (irq - IRQ_EINT8) * 2; 172 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
180 extint_offset = (irq - IRQ_EINT8) * 4; 173 extint_offset = (data->irq - IRQ_EINT8) * 4;
181 } 174 } else if ((data->irq >= IRQ_EINT16) && (data->irq <= IRQ_EINT23)) {
182 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
183 {
184 gpcon_reg = S3C2410_GPGCON; 175 gpcon_reg = S3C2410_GPGCON;
185 extint_reg = S3C24XX_EXTINT2; 176 extint_reg = S3C24XX_EXTINT2;
186 gpcon_offset = (irq - IRQ_EINT8) * 2; 177 gpcon_offset = (data->irq - IRQ_EINT8) * 2;
187 extint_offset = (irq - IRQ_EINT16) * 4; 178 extint_offset = (data->irq - IRQ_EINT16) * 4;
188 } else 179 } else {
189 return -1; 180 return -1;
181 }
190 182
191 /* Set the GPIO to external interrupt mode */ 183 /* Set the GPIO to external interrupt mode */
192 value = __raw_readl(gpcon_reg); 184 value = __raw_readl(gpcon_reg);
@@ -234,20 +226,20 @@ s3c_irqext_type(unsigned int irq, unsigned int type)
234 226
235static struct irq_chip s3c_irqext_chip = { 227static struct irq_chip s3c_irqext_chip = {
236 .name = "s3c-ext", 228 .name = "s3c-ext",
237 .mask = s3c_irqext_mask, 229 .irq_mask = s3c_irqext_mask,
238 .unmask = s3c_irqext_unmask, 230 .irq_unmask = s3c_irqext_unmask,
239 .ack = s3c_irqext_ack, 231 .irq_ack = s3c_irqext_ack,
240 .set_type = s3c_irqext_type, 232 .irq_set_type = s3c_irqext_type,
241 .irq_set_wake = s3c_irqext_wake 233 .irq_set_wake = s3c_irqext_wake
242}; 234};
243 235
244static struct irq_chip s3c_irq_eint0t4 = { 236static struct irq_chip s3c_irq_eint0t4 = {
245 .name = "s3c-ext0", 237 .name = "s3c-ext0",
246 .ack = s3c_irq_ack, 238 .irq_ack = s3c_irq_ack,
247 .mask = s3c_irq_mask, 239 .irq_mask = s3c_irq_mask,
248 .unmask = s3c_irq_unmask, 240 .irq_unmask = s3c_irq_unmask,
249 .set_wake = s3c_irq_wake, 241 .irq_set_wake = s3c_irq_wake,
250 .set_type = s3c_irqext_type, 242 .irq_set_type = s3c_irqext_type,
251}; 243};
252 244
253/* mask values for the parent registers for each of the interrupt types */ 245/* mask values for the parent registers for each of the interrupt types */
@@ -261,109 +253,109 @@ static struct irq_chip s3c_irq_eint0t4 = {
261/* UART0 */ 253/* UART0 */
262 254
263static void 255static void
264s3c_irq_uart0_mask(unsigned int irqno) 256s3c_irq_uart0_mask(struct irq_data *data)
265{ 257{
266 s3c_irqsub_mask(irqno, INTMSK_UART0, 7); 258 s3c_irqsub_mask(data->irq, INTMSK_UART0, 7);
267} 259}
268 260
269static void 261static void
270s3c_irq_uart0_unmask(unsigned int irqno) 262s3c_irq_uart0_unmask(struct irq_data *data)
271{ 263{
272 s3c_irqsub_unmask(irqno, INTMSK_UART0); 264 s3c_irqsub_unmask(data->irq, INTMSK_UART0);
273} 265}
274 266
275static void 267static void
276s3c_irq_uart0_ack(unsigned int irqno) 268s3c_irq_uart0_ack(struct irq_data *data)
277{ 269{
278 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); 270 s3c_irqsub_maskack(data->irq, INTMSK_UART0, 7);
279} 271}
280 272
281static struct irq_chip s3c_irq_uart0 = { 273static struct irq_chip s3c_irq_uart0 = {
282 .name = "s3c-uart0", 274 .name = "s3c-uart0",
283 .mask = s3c_irq_uart0_mask, 275 .irq_mask = s3c_irq_uart0_mask,
284 .unmask = s3c_irq_uart0_unmask, 276 .irq_unmask = s3c_irq_uart0_unmask,
285 .ack = s3c_irq_uart0_ack, 277 .irq_ack = s3c_irq_uart0_ack,
286}; 278};
287 279
288/* UART1 */ 280/* UART1 */
289 281
290static void 282static void
291s3c_irq_uart1_mask(unsigned int irqno) 283s3c_irq_uart1_mask(struct irq_data *data)
292{ 284{
293 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3); 285 s3c_irqsub_mask(data->irq, INTMSK_UART1, 7 << 3);
294} 286}
295 287
296static void 288static void
297s3c_irq_uart1_unmask(unsigned int irqno) 289s3c_irq_uart1_unmask(struct irq_data *data)
298{ 290{
299 s3c_irqsub_unmask(irqno, INTMSK_UART1); 291 s3c_irqsub_unmask(data->irq, INTMSK_UART1);
300} 292}
301 293
302static void 294static void
303s3c_irq_uart1_ack(unsigned int irqno) 295s3c_irq_uart1_ack(struct irq_data *data)
304{ 296{
305 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); 297 s3c_irqsub_maskack(data->irq, INTMSK_UART1, 7 << 3);
306} 298}
307 299
308static struct irq_chip s3c_irq_uart1 = { 300static struct irq_chip s3c_irq_uart1 = {
309 .name = "s3c-uart1", 301 .name = "s3c-uart1",
310 .mask = s3c_irq_uart1_mask, 302 .irq_mask = s3c_irq_uart1_mask,
311 .unmask = s3c_irq_uart1_unmask, 303 .irq_unmask = s3c_irq_uart1_unmask,
312 .ack = s3c_irq_uart1_ack, 304 .irq_ack = s3c_irq_uart1_ack,
313}; 305};
314 306
315/* UART2 */ 307/* UART2 */
316 308
317static void 309static void
318s3c_irq_uart2_mask(unsigned int irqno) 310s3c_irq_uart2_mask(struct irq_data *data)
319{ 311{
320 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6); 312 s3c_irqsub_mask(data->irq, INTMSK_UART2, 7 << 6);
321} 313}
322 314
323static void 315static void
324s3c_irq_uart2_unmask(unsigned int irqno) 316s3c_irq_uart2_unmask(struct irq_data *data)
325{ 317{
326 s3c_irqsub_unmask(irqno, INTMSK_UART2); 318 s3c_irqsub_unmask(data->irq, INTMSK_UART2);
327} 319}
328 320
329static void 321static void
330s3c_irq_uart2_ack(unsigned int irqno) 322s3c_irq_uart2_ack(struct irq_data *data)
331{ 323{
332 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); 324 s3c_irqsub_maskack(data->irq, INTMSK_UART2, 7 << 6);
333} 325}
334 326
335static struct irq_chip s3c_irq_uart2 = { 327static struct irq_chip s3c_irq_uart2 = {
336 .name = "s3c-uart2", 328 .name = "s3c-uart2",
337 .mask = s3c_irq_uart2_mask, 329 .irq_mask = s3c_irq_uart2_mask,
338 .unmask = s3c_irq_uart2_unmask, 330 .irq_unmask = s3c_irq_uart2_unmask,
339 .ack = s3c_irq_uart2_ack, 331 .irq_ack = s3c_irq_uart2_ack,
340}; 332};
341 333
342/* ADC and Touchscreen */ 334/* ADC and Touchscreen */
343 335
344static void 336static void
345s3c_irq_adc_mask(unsigned int irqno) 337s3c_irq_adc_mask(struct irq_data *d)
346{ 338{
347 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9); 339 s3c_irqsub_mask(d->irq, INTMSK_ADCPARENT, 3 << 9);
348} 340}
349 341
350static void 342static void
351s3c_irq_adc_unmask(unsigned int irqno) 343s3c_irq_adc_unmask(struct irq_data *d)
352{ 344{
353 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT); 345 s3c_irqsub_unmask(d->irq, INTMSK_ADCPARENT);
354} 346}
355 347
356static void 348static void
357s3c_irq_adc_ack(unsigned int irqno) 349s3c_irq_adc_ack(struct irq_data *d)
358{ 350{
359 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); 351 s3c_irqsub_ack(d->irq, INTMSK_ADCPARENT, 3 << 9);
360} 352}
361 353
362static struct irq_chip s3c_irq_adc = { 354static struct irq_chip s3c_irq_adc = {
363 .name = "s3c-adc", 355 .name = "s3c-adc",
364 .mask = s3c_irq_adc_mask, 356 .irq_mask = s3c_irq_adc_mask,
365 .unmask = s3c_irq_adc_unmask, 357 .irq_unmask = s3c_irq_adc_unmask,
366 .ack = s3c_irq_adc_ack, 358 .irq_ack = s3c_irq_adc_ack,
367}; 359};
368 360
369/* irq demux for adc */ 361/* irq demux for adc */
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index f2f2e1ccd0e6..225aa25405db 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -28,39 +28,40 @@
28#include <plat/gpio-cfg.h> 28#include <plat/gpio-cfg.h>
29#include <mach/regs-gpio.h> 29#include <mach/regs-gpio.h>
30 30
31static inline void s5p_irq_eint_mask(unsigned int irq) 31static inline void s5p_irq_eint_mask(struct irq_data *data)
32{ 32{
33 u32 mask; 33 u32 mask;
34 34
35 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 35 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
36 mask |= eint_irq_to_bit(irq); 36 mask |= eint_irq_to_bit(data->irq);
37 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 37 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
38} 38}
39 39
40static void s5p_irq_eint_unmask(unsigned int irq) 40static void s5p_irq_eint_unmask(struct irq_data *data)
41{ 41{
42 u32 mask; 42 u32 mask;
43 43
44 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(irq))); 44 mask = __raw_readl(S5P_EINT_MASK(EINT_REG_NR(data->irq)));
45 mask &= ~(eint_irq_to_bit(irq)); 45 mask &= ~(eint_irq_to_bit(data->irq));
46 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(irq))); 46 __raw_writel(mask, S5P_EINT_MASK(EINT_REG_NR(data->irq)));
47} 47}
48 48
49static inline void s5p_irq_eint_ack(unsigned int irq) 49static inline void s5p_irq_eint_ack(struct irq_data *data)
50{ 50{
51 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); 51 __raw_writel(eint_irq_to_bit(data->irq),
52 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
52} 53}
53 54
54static void s5p_irq_eint_maskack(unsigned int irq) 55static void s5p_irq_eint_maskack(struct irq_data *data)
55{ 56{
56 /* compiler should in-line these */ 57 /* compiler should in-line these */
57 s5p_irq_eint_mask(irq); 58 s5p_irq_eint_mask(data);
58 s5p_irq_eint_ack(irq); 59 s5p_irq_eint_ack(data);
59} 60}
60 61
61static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) 62static int s5p_irq_eint_set_type(struct irq_data *data, unsigned int type)
62{ 63{
63 int offs = EINT_OFFSET(irq); 64 int offs = EINT_OFFSET(data->irq);
64 int shift; 65 int shift;
65 u32 ctrl, mask; 66 u32 ctrl, mask;
66 u32 newvalue = 0; 67 u32 newvalue = 0;
@@ -94,10 +95,10 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
94 shift = (offs & 0x7) * 4; 95 shift = (offs & 0x7) * 4;
95 mask = 0x7 << shift; 96 mask = 0x7 << shift;
96 97
97 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(irq))); 98 ctrl = __raw_readl(S5P_EINT_CON(EINT_REG_NR(data->irq)));
98 ctrl &= ~mask; 99 ctrl &= ~mask;
99 ctrl |= newvalue << shift; 100 ctrl |= newvalue << shift;
100 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(irq))); 101 __raw_writel(ctrl, S5P_EINT_CON(EINT_REG_NR(data->irq)));
101 102
102 if ((0 <= offs) && (offs < 8)) 103 if ((0 <= offs) && (offs < 8))
103 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE); 104 s3c_gpio_cfgpin(EINT_GPIO_0(offs & 0x7), EINT_MODE);
@@ -119,11 +120,11 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type)
119 120
120static struct irq_chip s5p_irq_eint = { 121static struct irq_chip s5p_irq_eint = {
121 .name = "s5p-eint", 122 .name = "s5p-eint",
122 .mask = s5p_irq_eint_mask, 123 .irq_mask = s5p_irq_eint_mask,
123 .unmask = s5p_irq_eint_unmask, 124 .irq_unmask = s5p_irq_eint_unmask,
124 .mask_ack = s5p_irq_eint_maskack, 125 .irq_mask_ack = s5p_irq_eint_maskack,
125 .ack = s5p_irq_eint_ack, 126 .irq_ack = s5p_irq_eint_ack,
126 .set_type = s5p_irq_eint_set_type, 127 .irq_set_type = s5p_irq_eint_set_type,
127#ifdef CONFIG_PM 128#ifdef CONFIG_PM
128 .irq_set_wake = s3c_irqext_wake, 129 .irq_set_wake = s3c_irqext_wake,
129#endif 130#endif
@@ -159,40 +160,41 @@ static void s5p_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
159 s5p_irq_demux_eint(IRQ_EINT(24)); 160 s5p_irq_demux_eint(IRQ_EINT(24));
160} 161}
161 162
162static inline void s5p_irq_vic_eint_mask(unsigned int irq) 163static inline void s5p_irq_vic_eint_mask(struct irq_data *data)
163{ 164{
164 void __iomem *base = get_irq_chip_data(irq); 165 void __iomem *base = irq_data_get_irq_chip_data(data);
165 166
166 s5p_irq_eint_mask(irq); 167 s5p_irq_eint_mask(data);
167 writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE_CLEAR); 168 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE_CLEAR);
168} 169}
169 170
170static void s5p_irq_vic_eint_unmask(unsigned int irq) 171static void s5p_irq_vic_eint_unmask(struct irq_data *data)
171{ 172{
172 void __iomem *base = get_irq_chip_data(irq); 173 void __iomem *base = irq_data_get_irq_chip_data(data);
173 174
174 s5p_irq_eint_unmask(irq); 175 s5p_irq_eint_unmask(data);
175 writel(1 << EINT_OFFSET(irq), base + VIC_INT_ENABLE); 176 writel(1 << EINT_OFFSET(data->irq), base + VIC_INT_ENABLE);
176} 177}
177 178
178static inline void s5p_irq_vic_eint_ack(unsigned int irq) 179static inline void s5p_irq_vic_eint_ack(struct irq_data *data)
179{ 180{
180 __raw_writel(eint_irq_to_bit(irq), S5P_EINT_PEND(EINT_REG_NR(irq))); 181 __raw_writel(eint_irq_to_bit(data->irq),
182 S5P_EINT_PEND(EINT_REG_NR(data->irq)));
181} 183}
182 184
183static void s5p_irq_vic_eint_maskack(unsigned int irq) 185static void s5p_irq_vic_eint_maskack(struct irq_data *data)
184{ 186{
185 s5p_irq_vic_eint_mask(irq); 187 s5p_irq_vic_eint_mask(data);
186 s5p_irq_vic_eint_ack(irq); 188 s5p_irq_vic_eint_ack(data);
187} 189}
188 190
189static struct irq_chip s5p_irq_vic_eint = { 191static struct irq_chip s5p_irq_vic_eint = {
190 .name = "s5p_vic_eint", 192 .name = "s5p_vic_eint",
191 .mask = s5p_irq_vic_eint_mask, 193 .irq_mask = s5p_irq_vic_eint_mask,
192 .unmask = s5p_irq_vic_eint_unmask, 194 .irq_unmask = s5p_irq_vic_eint_unmask,
193 .mask_ack = s5p_irq_vic_eint_maskack, 195 .irq_mask_ack = s5p_irq_vic_eint_maskack,
194 .ack = s5p_irq_vic_eint_ack, 196 .irq_ack = s5p_irq_vic_eint_ack,
195 .set_type = s5p_irq_eint_set_type, 197 .irq_set_type = s5p_irq_eint_set_type,
196#ifdef CONFIG_PM 198#ifdef CONFIG_PM
197 .irq_set_wake = s3c_irqext_wake, 199 .irq_set_wake = s3c_irqext_wake,
198#endif 200#endif
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index 0e5dc8cbf5e3..3b6bf89d1739 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -30,9 +30,9 @@
30 30
31static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR]; 31static struct s3c_gpio_chip *irq_chips[S5P_GPIOINT_GROUP_MAXNR];
32 32
33static int s5p_gpioint_get_group(unsigned int irq) 33static int s5p_gpioint_get_group(struct irq_data *data)
34{ 34{
35 struct gpio_chip *chip = get_irq_data(irq); 35 struct gpio_chip *chip = irq_data_get_irq_data(data);
36 struct s3c_gpio_chip *s3c_chip = container_of(chip, 36 struct s3c_gpio_chip *s3c_chip = container_of(chip,
37 struct s3c_gpio_chip, chip); 37 struct s3c_gpio_chip, chip);
38 int group; 38 int group;
@@ -44,22 +44,22 @@ static int s5p_gpioint_get_group(unsigned int irq)
44 return group; 44 return group;
45} 45}
46 46
47static int s5p_gpioint_get_offset(unsigned int irq) 47static int s5p_gpioint_get_offset(struct irq_data *data)
48{ 48{
49 struct gpio_chip *chip = get_irq_data(irq); 49 struct gpio_chip *chip = irq_data_get_irq_data(data);
50 struct s3c_gpio_chip *s3c_chip = container_of(chip, 50 struct s3c_gpio_chip *s3c_chip = container_of(chip,
51 struct s3c_gpio_chip, chip); 51 struct s3c_gpio_chip, chip);
52 52
53 return irq - s3c_chip->irq_base; 53 return data->irq - s3c_chip->irq_base;
54} 54}
55 55
56static void s5p_gpioint_ack(unsigned int irq) 56static void s5p_gpioint_ack(struct irq_data *data)
57{ 57{
58 int group, offset, pend_offset; 58 int group, offset, pend_offset;
59 unsigned int value; 59 unsigned int value;
60 60
61 group = s5p_gpioint_get_group(irq); 61 group = s5p_gpioint_get_group(data);
62 offset = s5p_gpioint_get_offset(irq); 62 offset = s5p_gpioint_get_offset(data);
63 pend_offset = group << 2; 63 pend_offset = group << 2;
64 64
65 value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); 65 value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
@@ -67,13 +67,13 @@ static void s5p_gpioint_ack(unsigned int irq)
67 __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset); 67 __raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
68} 68}
69 69
70static void s5p_gpioint_mask(unsigned int irq) 70static void s5p_gpioint_mask(struct irq_data *data)
71{ 71{
72 int group, offset, mask_offset; 72 int group, offset, mask_offset;
73 unsigned int value; 73 unsigned int value;
74 74
75 group = s5p_gpioint_get_group(irq); 75 group = s5p_gpioint_get_group(data);
76 offset = s5p_gpioint_get_offset(irq); 76 offset = s5p_gpioint_get_offset(data);
77 mask_offset = group << 2; 77 mask_offset = group << 2;
78 78
79 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 79 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@@ -81,13 +81,13 @@ static void s5p_gpioint_mask(unsigned int irq)
81 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 81 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
82} 82}
83 83
84static void s5p_gpioint_unmask(unsigned int irq) 84static void s5p_gpioint_unmask(struct irq_data *data)
85{ 85{
86 int group, offset, mask_offset; 86 int group, offset, mask_offset;
87 unsigned int value; 87 unsigned int value;
88 88
89 group = s5p_gpioint_get_group(irq); 89 group = s5p_gpioint_get_group(data);
90 offset = s5p_gpioint_get_offset(irq); 90 offset = s5p_gpioint_get_offset(data);
91 mask_offset = group << 2; 91 mask_offset = group << 2;
92 92
93 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 93 value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
@@ -95,19 +95,19 @@ static void s5p_gpioint_unmask(unsigned int irq)
95 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset); 95 __raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
96} 96}
97 97
98static void s5p_gpioint_mask_ack(unsigned int irq) 98static void s5p_gpioint_mask_ack(struct irq_data *data)
99{ 99{
100 s5p_gpioint_mask(irq); 100 s5p_gpioint_mask(data);
101 s5p_gpioint_ack(irq); 101 s5p_gpioint_ack(data);
102} 102}
103 103
104static int s5p_gpioint_set_type(unsigned int irq, unsigned int type) 104static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
105{ 105{
106 int group, offset, con_offset; 106 int group, offset, con_offset;
107 unsigned int value; 107 unsigned int value;
108 108
109 group = s5p_gpioint_get_group(irq); 109 group = s5p_gpioint_get_group(data);
110 offset = s5p_gpioint_get_offset(irq); 110 offset = s5p_gpioint_get_offset(data);
111 con_offset = group << 2; 111 con_offset = group << 2;
112 112
113 switch (type) { 113 switch (type) {
@@ -142,11 +142,11 @@ static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
142 142
143struct irq_chip s5p_gpioint = { 143struct irq_chip s5p_gpioint = {
144 .name = "s5p_gpioint", 144 .name = "s5p_gpioint",
145 .ack = s5p_gpioint_ack, 145 .irq_ack = s5p_gpioint_ack,
146 .mask = s5p_gpioint_mask, 146 .irq_mask = s5p_gpioint_mask,
147 .mask_ack = s5p_gpioint_mask_ack, 147 .irq_mask_ack = s5p_gpioint_mask_ack,
148 .unmask = s5p_gpioint_unmask, 148 .irq_unmask = s5p_gpioint_unmask,
149 .set_type = s5p_gpioint_set_type, 149 .irq_set_type = s5p_gpioint_set_type,
150}; 150};
151 151
152static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) 152static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
index dc33b9ecda45..5259ad458bc8 100644
--- a/arch/arm/plat-s5p/irq-pm.c
+++ b/arch/arm/plat-s5p/irq-pm.c
@@ -37,14 +37,14 @@
37unsigned long s3c_irqwake_intallow = 0x00000006L; 37unsigned long s3c_irqwake_intallow = 0x00000006L;
38unsigned long s3c_irqwake_eintallow = 0xffffffffL; 38unsigned long s3c_irqwake_eintallow = 0xffffffffL;
39 39
40int s3c_irq_wake(unsigned int irqno, unsigned int state) 40int s3c_irq_wake(struct irq_data *data, unsigned int state)
41{ 41{
42 unsigned long irqbit; 42 unsigned long irqbit;
43 43
44 switch (irqno) { 44 switch (data->irq) {
45 case IRQ_RTC_TIC: 45 case IRQ_RTC_TIC:
46 case IRQ_RTC_ALARM: 46 case IRQ_RTC_ALARM:
47 irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM); 47 irqbit = 1 << (data->irq + 1 - IRQ_RTC_ALARM);
48 if (!state) 48 if (!state)
49 s3c_irqwake_intmask |= irqbit; 49 s3c_irqwake_intmask |= irqbit;
50 else 50 else
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index da31d785cbd1..4e770355ccbc 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -30,7 +30,7 @@
30 30
31static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) 31static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
32{ 32{
33 struct s3c_uart_irq *uirq = data->chip_data; 33 struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
34 return uirq->regs; 34 return uirq->regs;
35} 35}
36 36
@@ -83,7 +83,7 @@ static void s3c_irq_uart_ack(struct irq_data *data)
83 83
84static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) 84static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
85{ 85{
86 struct s3c_uart_irq *uirq = desc->handler_data; 86 struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
87 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); 87 u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
88 int base = uirq->base_irq; 88 int base = uirq->base_irq;
89 89
@@ -124,7 +124,7 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
124 set_irq_flags(irq, IRQF_VALID); 124 set_irq_flags(irq, IRQF_VALID);
125 } 125 }
126 126
127 desc->handler_data = uirq; 127 desc->irq_data.handler_data = uirq;
128 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); 128 set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
129} 129}
130 130
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index 7ce77ddb729d..dd8692ae5c4c 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -24,7 +24,7 @@
24 24
25static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc) 25static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
26{ 26{
27 generic_handle_irq((int)desc->handler_data); 27 generic_handle_irq((int)desc->irq_data.handler_data);
28} 28}
29 29
30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */ 30/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
@@ -86,5 +86,5 @@ void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
86 set_irq_handler(timer_irq, handle_level_irq); 86 set_irq_handler(timer_irq, handle_level_irq);
87 set_irq_flags(timer_irq, IRQF_VALID); 87 set_irq_flags(timer_irq, IRQF_VALID);
88 88
89 desc->handler_data = (void *)timer_irq; 89 desc->irq_data.handler_data = (void *)timer_irq;
90} 90}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 00:48:44 -0500