diff options
Diffstat (limited to 'arch')
170 files changed, 27342 insertions, 978 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7a96ad317dcd..d778a699f577 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -228,6 +228,7 @@ config ARCH_REALVIEW | |||
| 228 | select ICST307 | 228 | select ICST307 |
| 229 | select GENERIC_TIME | 229 | select GENERIC_TIME |
| 230 | select GENERIC_CLOCKEVENTS | 230 | select GENERIC_CLOCKEVENTS |
| 231 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 231 | help | 232 | help |
| 232 | This enables support for ARM Ltd RealView boards. | 233 | This enables support for ARM Ltd RealView boards. |
| 233 | 234 | ||
| @@ -240,6 +241,7 @@ config ARCH_VERSATILE | |||
| 240 | select ICST307 | 241 | select ICST307 |
| 241 | select GENERIC_TIME | 242 | select GENERIC_TIME |
| 242 | select GENERIC_CLOCKEVENTS | 243 | select GENERIC_CLOCKEVENTS |
| 244 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 243 | help | 245 | help |
| 244 | This enables support for ARM Ltd Versatile board. | 246 | This enables support for ARM Ltd Versatile board. |
| 245 | 247 | ||
| @@ -518,10 +520,18 @@ config ARCH_W90X900 | |||
| 518 | select CPU_ARM926T | 520 | select CPU_ARM926T |
| 519 | select ARCH_REQUIRE_GPIOLIB | 521 | select ARCH_REQUIRE_GPIOLIB |
| 520 | select GENERIC_GPIO | 522 | select GENERIC_GPIO |
| 523 | select HAVE_CLK | ||
| 521 | select COMMON_CLKDEV | 524 | select COMMON_CLKDEV |
| 525 | select GENERIC_TIME | ||
| 526 | select GENERIC_CLOCKEVENTS | ||
| 522 | help | 527 | help |
| 523 | Support for Nuvoton (Winbond logic dept.) ARM9 processor,You | 528 | Support for Nuvoton (Winbond logic dept.) ARM9 processor, |
| 524 | can login www.mcuos.com or www.nuvoton.com to know more. | 529 | At present, the w90x900 has been renamed nuc900, regarding |
| 530 | the ARM series product line, you can login the following | ||
| 531 | link address to know more. | ||
| 532 | |||
| 533 | <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ | ||
| 534 | ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> | ||
| 525 | 535 | ||
| 526 | config ARCH_PNX4008 | 536 | config ARCH_PNX4008 |
| 527 | bool "Philips Nexperia PNX4008 Mobile" | 537 | bool "Philips Nexperia PNX4008 Mobile" |
| @@ -675,6 +685,18 @@ config ARCH_OMAP | |||
| 675 | help | 685 | help |
| 676 | Support for TI's OMAP platform (OMAP1 and OMAP2). | 686 | Support for TI's OMAP platform (OMAP1 and OMAP2). |
| 677 | 687 | ||
| 688 | config ARCH_BCMRING | ||
| 689 | bool "Broadcom BCMRING" | ||
| 690 | depends on MMU | ||
| 691 | select CPU_V6 | ||
| 692 | select ARM_AMBA | ||
| 693 | select COMMON_CLKDEV | ||
| 694 | select GENERIC_TIME | ||
| 695 | select GENERIC_CLOCKEVENTS | ||
| 696 | select ARCH_WANT_OPTIONAL_GPIOLIB | ||
| 697 | help | ||
| 698 | Support for Broadcom's BCMRing platform. | ||
| 699 | |||
| 678 | endchoice | 700 | endchoice |
| 679 | 701 | ||
| 680 | source "arch/arm/mach-clps711x/Kconfig" | 702 | source "arch/arm/mach-clps711x/Kconfig" |
| @@ -775,6 +797,8 @@ source "arch/arm/mach-u300/Kconfig" | |||
| 775 | 797 | ||
| 776 | source "arch/arm/mach-w90x900/Kconfig" | 798 | source "arch/arm/mach-w90x900/Kconfig" |
| 777 | 799 | ||
| 800 | source "arch/arm/mach-bcmring/Kconfig" | ||
| 801 | |||
| 778 | # Definitions to make life easier | 802 | # Definitions to make life easier |
| 779 | config ARCH_ACORN | 803 | config ARCH_ACORN |
| 780 | bool | 804 | bool |
| @@ -1103,6 +1127,11 @@ config HIGHMEM | |||
| 1103 | 1127 | ||
| 1104 | If unsure, say n. | 1128 | If unsure, say n. |
| 1105 | 1129 | ||
| 1130 | config HIGHPTE | ||
| 1131 | bool "Allocate 2nd-level pagetables from highmem" | ||
| 1132 | depends on HIGHMEM | ||
| 1133 | depends on !OUTER_CACHE | ||
| 1134 | |||
| 1106 | source "mm/Kconfig" | 1135 | source "mm/Kconfig" |
| 1107 | 1136 | ||
| 1108 | config LEDS | 1137 | config LEDS |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index b70f62c8fc0a..7350557a81e0 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -119,6 +119,7 @@ endif | |||
| 119 | # by CONFIG_* macro name. | 119 | # by CONFIG_* macro name. |
| 120 | machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 | 120 | machine-$(CONFIG_ARCH_AAEC2000) := aaec2000 |
| 121 | machine-$(CONFIG_ARCH_AT91) := at91 | 121 | machine-$(CONFIG_ARCH_AT91) := at91 |
| 122 | machine-$(CONFIG_ARCH_BCMRING) := bcmring | ||
| 122 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x | 123 | machine-$(CONFIG_ARCH_CLPS711X) := clps711x |
| 123 | machine-$(CONFIG_ARCH_DAVINCI) := davinci | 124 | machine-$(CONFIG_ARCH_DAVINCI) := davinci |
| 124 | machine-$(CONFIG_ARCH_EBSA110) := ebsa110 | 125 | machine-$(CONFIG_ARCH_EBSA110) := ebsa110 |
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig new file mode 100644 index 000000000000..bcc0bac551a5 --- /dev/null +++ b/arch/arm/configs/bcmring_defconfig | |||
| @@ -0,0 +1,725 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.31-rc3 | ||
| 4 | # Fri Jul 17 12:07:28 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_TIME=y | ||
| 9 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 10 | CONFIG_MMU=y | ||
| 11 | CONFIG_GENERIC_HARDIRQS=y | ||
| 12 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 13 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 14 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 15 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 16 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 17 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 18 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 19 | CONFIG_GENERIC_HWEIGHT=y | ||
| 20 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 21 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 22 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 23 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 24 | CONFIG_CONSTRUCTORS=y | ||
| 25 | |||
| 26 | # | ||
| 27 | # General setup | ||
| 28 | # | ||
| 29 | CONFIG_EXPERIMENTAL=y | ||
| 30 | CONFIG_BROKEN_ON_SMP=y | ||
| 31 | CONFIG_LOCK_KERNEL=y | ||
| 32 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 33 | CONFIG_LOCALVERSION="" | ||
| 34 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 35 | # CONFIG_SWAP is not set | ||
| 36 | CONFIG_SYSVIPC=y | ||
| 37 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 38 | # CONFIG_POSIX_MQUEUE is not set | ||
| 39 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 40 | # CONFIG_TASKSTATS is not set | ||
| 41 | # CONFIG_AUDIT is not set | ||
| 42 | |||
| 43 | # | ||
| 44 | # RCU Subsystem | ||
| 45 | # | ||
| 46 | CONFIG_CLASSIC_RCU=y | ||
| 47 | # CONFIG_TREE_RCU is not set | ||
| 48 | # CONFIG_PREEMPT_RCU is not set | ||
| 49 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 50 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 51 | # CONFIG_IKCONFIG is not set | ||
| 52 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 53 | # CONFIG_GROUP_SCHED is not set | ||
| 54 | # CONFIG_CGROUPS is not set | ||
| 55 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 56 | # CONFIG_RELAY is not set | ||
| 57 | # CONFIG_NAMESPACES is not set | ||
| 58 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 60 | CONFIG_SYSCTL=y | ||
| 61 | CONFIG_EMBEDDED=y | ||
| 62 | CONFIG_UID16=y | ||
| 63 | CONFIG_SYSCTL_SYSCALL=y | ||
| 64 | CONFIG_KALLSYMS=y | ||
| 65 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 66 | # CONFIG_HOTPLUG is not set | ||
| 67 | CONFIG_PRINTK=y | ||
| 68 | CONFIG_BUG=y | ||
| 69 | # CONFIG_ELF_CORE is not set | ||
| 70 | CONFIG_BASE_FULL=y | ||
| 71 | CONFIG_FUTEX=y | ||
| 72 | # CONFIG_EPOLL is not set | ||
| 73 | # CONFIG_SIGNALFD is not set | ||
| 74 | # CONFIG_TIMERFD is not set | ||
| 75 | # CONFIG_EVENTFD is not set | ||
| 76 | CONFIG_SHMEM=y | ||
| 77 | # CONFIG_AIO is not set | ||
| 78 | |||
| 79 | # | ||
| 80 | # Performance Counters | ||
| 81 | # | ||
| 82 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 83 | # CONFIG_SLUB_DEBUG is not set | ||
| 84 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 85 | # CONFIG_COMPAT_BRK is not set | ||
| 86 | # CONFIG_SLAB is not set | ||
| 87 | CONFIG_SLUB=y | ||
| 88 | # CONFIG_SLOB is not set | ||
| 89 | # CONFIG_PROFILING is not set | ||
| 90 | # CONFIG_MARKERS is not set | ||
| 91 | CONFIG_HAVE_OPROFILE=y | ||
| 92 | # CONFIG_KPROBES is not set | ||
| 93 | CONFIG_HAVE_KPROBES=y | ||
| 94 | CONFIG_HAVE_KRETPROBES=y | ||
| 95 | |||
| 96 | # | ||
| 97 | # GCOV-based kernel profiling | ||
| 98 | # | ||
| 99 | # CONFIG_SLOW_WORK is not set | ||
| 100 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 101 | CONFIG_RT_MUTEXES=y | ||
| 102 | CONFIG_BASE_SMALL=0 | ||
| 103 | CONFIG_MODULES=y | ||
| 104 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 105 | CONFIG_MODULE_UNLOAD=y | ||
| 106 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 107 | # CONFIG_MODVERSIONS is not set | ||
| 108 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 109 | CONFIG_BLOCK=y | ||
| 110 | CONFIG_LBDAF=y | ||
| 111 | # CONFIG_BLK_DEV_BSG is not set | ||
| 112 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 113 | |||
| 114 | # | ||
| 115 | # IO Schedulers | ||
| 116 | # | ||
| 117 | CONFIG_IOSCHED_NOOP=y | ||
| 118 | # CONFIG_IOSCHED_AS is not set | ||
| 119 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 120 | # CONFIG_IOSCHED_CFQ is not set | ||
| 121 | # CONFIG_DEFAULT_AS is not set | ||
| 122 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 123 | # CONFIG_DEFAULT_CFQ is not set | ||
| 124 | CONFIG_DEFAULT_NOOP=y | ||
| 125 | CONFIG_DEFAULT_IOSCHED="noop" | ||
| 126 | # CONFIG_FREEZER is not set | ||
| 127 | |||
| 128 | # | ||
| 129 | # System Type | ||
| 130 | # | ||
| 131 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 132 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 133 | # CONFIG_ARCH_REALVIEW is not set | ||
| 134 | # CONFIG_ARCH_VERSATILE is not set | ||
| 135 | # CONFIG_ARCH_AT91 is not set | ||
| 136 | # CONFIG_ARCH_CLPS711X is not set | ||
| 137 | # CONFIG_ARCH_GEMINI is not set | ||
| 138 | # CONFIG_ARCH_EBSA110 is not set | ||
| 139 | # CONFIG_ARCH_EP93XX is not set | ||
| 140 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 141 | # CONFIG_ARCH_MXC is not set | ||
| 142 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IOP13XX is not set | ||
| 146 | # CONFIG_ARCH_IOP32X is not set | ||
| 147 | # CONFIG_ARCH_IOP33X is not set | ||
| 148 | # CONFIG_ARCH_IXP23XX is not set | ||
| 149 | # CONFIG_ARCH_IXP2000 is not set | ||
| 150 | # CONFIG_ARCH_IXP4XX is not set | ||
| 151 | # CONFIG_ARCH_L7200 is not set | ||
| 152 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 153 | # CONFIG_ARCH_LOKI is not set | ||
| 154 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 155 | # CONFIG_ARCH_ORION5X is not set | ||
| 156 | # CONFIG_ARCH_MMP is not set | ||
| 157 | # CONFIG_ARCH_KS8695 is not set | ||
| 158 | # CONFIG_ARCH_NS9XXX is not set | ||
| 159 | # CONFIG_ARCH_W90X900 is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | # CONFIG_ARCH_MSM is not set | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_S3C64XX is not set | ||
| 167 | # CONFIG_ARCH_SHARK is not set | ||
| 168 | # CONFIG_ARCH_LH7A40X is not set | ||
| 169 | # CONFIG_ARCH_U300 is not set | ||
| 170 | # CONFIG_ARCH_DAVINCI is not set | ||
| 171 | # CONFIG_ARCH_OMAP is not set | ||
| 172 | CONFIG_ARCH_BCMRING=y | ||
| 173 | # CONFIG_ARCH_FPGA11107 is not set | ||
| 174 | CONFIG_ARCH_BCM11107=y | ||
| 175 | |||
| 176 | # | ||
| 177 | # BCMRING Options | ||
| 178 | # | ||
| 179 | CONFIG_BCM_ZRELADDR=0x8000 | ||
| 180 | |||
| 181 | # | ||
| 182 | # Processor Type | ||
| 183 | # | ||
| 184 | CONFIG_CPU_32=y | ||
| 185 | CONFIG_CPU_V6=y | ||
| 186 | CONFIG_CPU_32v6K=y | ||
| 187 | CONFIG_CPU_32v6=y | ||
| 188 | CONFIG_CPU_ABRT_EV6=y | ||
| 189 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 190 | CONFIG_CPU_CACHE_V6=y | ||
| 191 | CONFIG_CPU_CACHE_VIPT=y | ||
| 192 | CONFIG_CPU_COPY_V6=y | ||
| 193 | CONFIG_CPU_TLB_V6=y | ||
| 194 | CONFIG_CPU_HAS_ASID=y | ||
| 195 | CONFIG_CPU_CP15=y | ||
| 196 | CONFIG_CPU_CP15_MMU=y | ||
| 197 | |||
| 198 | # | ||
| 199 | # Processor Features | ||
| 200 | # | ||
| 201 | CONFIG_ARM_THUMB=y | ||
| 202 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 204 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 205 | # CONFIG_ARM_ERRATA_411920 is not set | ||
| 206 | CONFIG_COMMON_CLKDEV=y | ||
| 207 | |||
| 208 | # | ||
| 209 | # Bus support | ||
| 210 | # | ||
| 211 | CONFIG_ARM_AMBA=y | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | |||
| 215 | # | ||
| 216 | # Kernel Features | ||
| 217 | # | ||
| 218 | CONFIG_TICK_ONESHOT=y | ||
| 219 | CONFIG_NO_HZ=y | ||
| 220 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 221 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 222 | CONFIG_VMSPLIT_3G=y | ||
| 223 | # CONFIG_VMSPLIT_2G is not set | ||
| 224 | # CONFIG_VMSPLIT_1G is not set | ||
| 225 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 226 | CONFIG_PREEMPT=y | ||
| 227 | CONFIG_HZ=100 | ||
| 228 | CONFIG_AEABI=y | ||
| 229 | # CONFIG_OABI_COMPAT is not set | ||
| 230 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 231 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 232 | # CONFIG_HIGHMEM is not set | ||
| 233 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 234 | CONFIG_FLATMEM_MANUAL=y | ||
| 235 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 236 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 237 | CONFIG_FLATMEM=y | ||
| 238 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 239 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 240 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 241 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 242 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 243 | CONFIG_VIRT_TO_BUS=y | ||
| 244 | CONFIG_HAVE_MLOCK=y | ||
| 245 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 246 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 247 | CONFIG_ALIGNMENT_TRAP=y | ||
| 248 | CONFIG_UACCESS_WITH_MEMCPY=y | ||
| 249 | |||
| 250 | # | ||
| 251 | # Boot options | ||
| 252 | # | ||
| 253 | CONFIG_ZBOOT_ROM_TEXT=0x0e000000 | ||
| 254 | CONFIG_ZBOOT_ROM_BSS=0x0ea00000 | ||
| 255 | CONFIG_ZBOOT_ROM=y | ||
| 256 | CONFIG_CMDLINE="" | ||
| 257 | # CONFIG_KEXEC is not set | ||
| 258 | |||
| 259 | # | ||
| 260 | # CPU Power Management | ||
| 261 | # | ||
| 262 | # CONFIG_CPU_IDLE is not set | ||
| 263 | |||
| 264 | # | ||
| 265 | # Floating point emulation | ||
| 266 | # | ||
| 267 | |||
| 268 | # | ||
| 269 | # At least one emulation must be selected | ||
| 270 | # | ||
| 271 | # CONFIG_VFP is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # Userspace binary formats | ||
| 275 | # | ||
| 276 | CONFIG_BINFMT_ELF=y | ||
| 277 | CONFIG_HAVE_AOUT=y | ||
| 278 | # CONFIG_BINFMT_AOUT is not set | ||
| 279 | # CONFIG_BINFMT_MISC is not set | ||
| 280 | |||
| 281 | # | ||
| 282 | # Power management options | ||
| 283 | # | ||
| 284 | # CONFIG_PM is not set | ||
| 285 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 286 | CONFIG_NET=y | ||
| 287 | |||
| 288 | # | ||
| 289 | # Networking options | ||
| 290 | # | ||
| 291 | # CONFIG_PACKET is not set | ||
| 292 | # CONFIG_UNIX is not set | ||
| 293 | # CONFIG_NET_KEY is not set | ||
| 294 | # CONFIG_INET is not set | ||
| 295 | # CONFIG_NETWORK_SECMARK is not set | ||
| 296 | # CONFIG_NETFILTER is not set | ||
| 297 | # CONFIG_ATM is not set | ||
| 298 | # CONFIG_BRIDGE is not set | ||
| 299 | # CONFIG_NET_DSA is not set | ||
| 300 | # CONFIG_VLAN_8021Q is not set | ||
| 301 | # CONFIG_DECNET is not set | ||
| 302 | # CONFIG_LLC2 is not set | ||
| 303 | # CONFIG_IPX is not set | ||
| 304 | # CONFIG_ATALK is not set | ||
| 305 | # CONFIG_X25 is not set | ||
| 306 | # CONFIG_LAPB is not set | ||
| 307 | # CONFIG_WAN_ROUTER is not set | ||
| 308 | # CONFIG_PHONET is not set | ||
| 309 | # CONFIG_IEEE802154 is not set | ||
| 310 | # CONFIG_NET_SCHED is not set | ||
| 311 | # CONFIG_DCB is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # Network testing | ||
| 315 | # | ||
| 316 | # CONFIG_NET_PKTGEN is not set | ||
| 317 | # CONFIG_HAMRADIO is not set | ||
| 318 | # CONFIG_CAN is not set | ||
| 319 | # CONFIG_IRDA is not set | ||
| 320 | # CONFIG_BT is not set | ||
| 321 | # CONFIG_WIRELESS is not set | ||
| 322 | # CONFIG_WIMAX is not set | ||
| 323 | # CONFIG_RFKILL is not set | ||
| 324 | # CONFIG_NET_9P is not set | ||
| 325 | |||
| 326 | # | ||
| 327 | # Device Drivers | ||
| 328 | # | ||
| 329 | |||
| 330 | # | ||
| 331 | # Generic Driver Options | ||
| 332 | # | ||
| 333 | CONFIG_STANDALONE=y | ||
| 334 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 335 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 336 | # CONFIG_CONNECTOR is not set | ||
| 337 | CONFIG_MTD=y | ||
| 338 | # CONFIG_MTD_DEBUG is not set | ||
| 339 | CONFIG_MTD_CONCAT=y | ||
| 340 | CONFIG_MTD_PARTITIONS=y | ||
| 341 | # CONFIG_MTD_TESTS is not set | ||
| 342 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 343 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 344 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 345 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 346 | |||
| 347 | # | ||
| 348 | # User Modules And Translation Layers | ||
| 349 | # | ||
| 350 | CONFIG_MTD_CHAR=y | ||
| 351 | CONFIG_MTD_BLKDEVS=y | ||
| 352 | CONFIG_MTD_BLOCK=y | ||
| 353 | # CONFIG_FTL is not set | ||
| 354 | # CONFIG_NFTL is not set | ||
| 355 | # CONFIG_INFTL is not set | ||
| 356 | # CONFIG_RFD_FTL is not set | ||
| 357 | # CONFIG_SSFDC is not set | ||
| 358 | # CONFIG_MTD_OOPS is not set | ||
| 359 | |||
| 360 | # | ||
| 361 | # RAM/ROM/Flash chip drivers | ||
| 362 | # | ||
| 363 | CONFIG_MTD_CFI=y | ||
| 364 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 365 | CONFIG_MTD_GEN_PROBE=y | ||
| 366 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 367 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 368 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 369 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 370 | CONFIG_MTD_CFI_GEOMETRY=y | ||
| 371 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 372 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 373 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 374 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 375 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 376 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 377 | CONFIG_MTD_CFI_I1=y | ||
| 378 | # CONFIG_MTD_CFI_I2 is not set | ||
| 379 | # CONFIG_MTD_CFI_I4 is not set | ||
| 380 | # CONFIG_MTD_CFI_I8 is not set | ||
| 381 | # CONFIG_MTD_OTP is not set | ||
| 382 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 383 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 384 | # CONFIG_MTD_CFI_STAA is not set | ||
| 385 | CONFIG_MTD_CFI_UTIL=y | ||
| 386 | # CONFIG_MTD_RAM is not set | ||
| 387 | # CONFIG_MTD_ROM is not set | ||
| 388 | # CONFIG_MTD_ABSENT is not set | ||
| 389 | |||
| 390 | # | ||
| 391 | # Mapping drivers for chip access | ||
| 392 | # | ||
| 393 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 394 | # CONFIG_MTD_PHYSMAP is not set | ||
| 395 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 396 | # CONFIG_MTD_PLATRAM is not set | ||
| 397 | |||
| 398 | # | ||
| 399 | # Self-contained MTD device drivers | ||
| 400 | # | ||
| 401 | # CONFIG_MTD_SLRAM is not set | ||
| 402 | # CONFIG_MTD_PHRAM is not set | ||
| 403 | # CONFIG_MTD_MTDRAM is not set | ||
| 404 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 405 | |||
| 406 | # | ||
| 407 | # Disk-On-Chip Device Drivers | ||
| 408 | # | ||
| 409 | # CONFIG_MTD_DOC2000 is not set | ||
| 410 | # CONFIG_MTD_DOC2001 is not set | ||
| 411 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 412 | CONFIG_MTD_NAND=y | ||
| 413 | CONFIG_MTD_NAND_VERIFY_WRITE=y | ||
| 414 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 415 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 416 | CONFIG_MTD_NAND_IDS=y | ||
| 417 | CONFIG_MTD_NAND_BCM_UMI=y | ||
| 418 | CONFIG_MTD_NAND_BCM_UMI_HWCS=y | ||
| 419 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 420 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 421 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 422 | # CONFIG_MTD_ONENAND is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # LPDDR flash memory drivers | ||
| 426 | # | ||
| 427 | # CONFIG_MTD_LPDDR is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # UBI - Unsorted block images | ||
| 431 | # | ||
| 432 | # CONFIG_MTD_UBI is not set | ||
| 433 | # CONFIG_PARPORT is not set | ||
| 434 | CONFIG_BLK_DEV=y | ||
| 435 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 436 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 437 | # CONFIG_BLK_DEV_NBD is not set | ||
| 438 | # CONFIG_BLK_DEV_RAM is not set | ||
| 439 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 440 | # CONFIG_ATA_OVER_ETH is not set | ||
| 441 | # CONFIG_MISC_DEVICES is not set | ||
| 442 | CONFIG_HAVE_IDE=y | ||
| 443 | # CONFIG_IDE is not set | ||
| 444 | |||
| 445 | # | ||
| 446 | # SCSI device support | ||
| 447 | # | ||
| 448 | # CONFIG_RAID_ATTRS is not set | ||
| 449 | # CONFIG_SCSI is not set | ||
| 450 | # CONFIG_SCSI_DMA is not set | ||
| 451 | # CONFIG_SCSI_NETLINK is not set | ||
| 452 | # CONFIG_ATA is not set | ||
| 453 | # CONFIG_MD is not set | ||
| 454 | # CONFIG_NETDEVICES is not set | ||
| 455 | # CONFIG_ISDN is not set | ||
| 456 | |||
| 457 | # | ||
| 458 | # Input device support | ||
| 459 | # | ||
| 460 | CONFIG_INPUT=y | ||
| 461 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 462 | # CONFIG_INPUT_POLLDEV is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # Userland interfaces | ||
| 466 | # | ||
| 467 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 468 | # CONFIG_INPUT_JOYDEV is not set | ||
| 469 | # CONFIG_INPUT_EVDEV is not set | ||
| 470 | # CONFIG_INPUT_EVBUG is not set | ||
| 471 | |||
| 472 | # | ||
| 473 | # Input Device Drivers | ||
| 474 | # | ||
| 475 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 476 | # CONFIG_INPUT_MOUSE is not set | ||
| 477 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 478 | # CONFIG_INPUT_TABLET is not set | ||
| 479 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 480 | # CONFIG_INPUT_MISC is not set | ||
| 481 | |||
| 482 | # | ||
| 483 | # Hardware I/O ports | ||
| 484 | # | ||
| 485 | # CONFIG_SERIO is not set | ||
| 486 | # CONFIG_GAMEPORT is not set | ||
| 487 | |||
| 488 | # | ||
| 489 | # Character devices | ||
| 490 | # | ||
| 491 | CONFIG_VT=y | ||
| 492 | # CONFIG_CONSOLE_TRANSLATIONS is not set | ||
| 493 | CONFIG_VT_CONSOLE=y | ||
| 494 | CONFIG_HW_CONSOLE=y | ||
| 495 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 496 | # CONFIG_DEVKMEM is not set | ||
| 497 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 498 | |||
| 499 | # | ||
| 500 | # Serial drivers | ||
| 501 | # | ||
| 502 | # CONFIG_SERIAL_8250 is not set | ||
| 503 | |||
| 504 | # | ||
| 505 | # Non-8250 serial port support | ||
| 506 | # | ||
| 507 | # CONFIG_SERIAL_AMBA_PL010 is not set | ||
| 508 | CONFIG_SERIAL_AMBA_PL011=y | ||
| 509 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | ||
| 510 | CONFIG_SERIAL_CORE=y | ||
| 511 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 512 | CONFIG_UNIX98_PTYS=y | ||
| 513 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 514 | CONFIG_LEGACY_PTYS=y | ||
| 515 | CONFIG_LEGACY_PTY_COUNT=64 | ||
| 516 | # CONFIG_IPMI_HANDLER is not set | ||
| 517 | # CONFIG_HW_RANDOM is not set | ||
| 518 | # CONFIG_R3964 is not set | ||
| 519 | # CONFIG_RAW_DRIVER is not set | ||
| 520 | # CONFIG_TCG_TPM is not set | ||
| 521 | # CONFIG_I2C is not set | ||
| 522 | # CONFIG_SPI is not set | ||
| 523 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | ||
| 524 | # CONFIG_GPIOLIB is not set | ||
| 525 | # CONFIG_W1 is not set | ||
| 526 | # CONFIG_POWER_SUPPLY is not set | ||
| 527 | # CONFIG_HWMON is not set | ||
| 528 | # CONFIG_THERMAL is not set | ||
| 529 | # CONFIG_THERMAL_HWMON is not set | ||
| 530 | # CONFIG_WATCHDOG is not set | ||
| 531 | CONFIG_SSB_POSSIBLE=y | ||
| 532 | |||
| 533 | # | ||
| 534 | # Sonics Silicon Backplane | ||
| 535 | # | ||
| 536 | # CONFIG_SSB is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # Multifunction device drivers | ||
| 540 | # | ||
| 541 | # CONFIG_MFD_CORE is not set | ||
| 542 | # CONFIG_MFD_SM501 is not set | ||
| 543 | # CONFIG_HTC_PASIC3 is not set | ||
| 544 | # CONFIG_MFD_TMIO is not set | ||
| 545 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Graphics support | ||
| 549 | # | ||
| 550 | # CONFIG_VGASTATE is not set | ||
| 551 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 552 | # CONFIG_FB is not set | ||
| 553 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 554 | |||
| 555 | # | ||
| 556 | # Display device support | ||
| 557 | # | ||
| 558 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Console display driver support | ||
| 562 | # | ||
| 563 | # CONFIG_VGA_CONSOLE is not set | ||
| 564 | CONFIG_DUMMY_CONSOLE=y | ||
| 565 | # CONFIG_SOUND is not set | ||
| 566 | # CONFIG_HID_SUPPORT is not set | ||
| 567 | # CONFIG_USB_SUPPORT is not set | ||
| 568 | # CONFIG_MMC is not set | ||
| 569 | # CONFIG_MEMSTICK is not set | ||
| 570 | # CONFIG_ACCESSIBILITY is not set | ||
| 571 | # CONFIG_NEW_LEDS is not set | ||
| 572 | CONFIG_RTC_LIB=y | ||
| 573 | # CONFIG_RTC_CLASS is not set | ||
| 574 | # CONFIG_DMADEVICES is not set | ||
| 575 | # CONFIG_AUXDISPLAY is not set | ||
| 576 | # CONFIG_REGULATOR is not set | ||
| 577 | # CONFIG_UIO is not set | ||
| 578 | # CONFIG_STAGING is not set | ||
| 579 | |||
| 580 | # | ||
| 581 | # File systems | ||
| 582 | # | ||
| 583 | # CONFIG_EXT2_FS is not set | ||
| 584 | # CONFIG_EXT3_FS is not set | ||
| 585 | # CONFIG_EXT4_FS is not set | ||
| 586 | # CONFIG_REISERFS_FS is not set | ||
| 587 | # CONFIG_JFS_FS is not set | ||
| 588 | CONFIG_FS_POSIX_ACL=y | ||
| 589 | # CONFIG_XFS_FS is not set | ||
| 590 | # CONFIG_GFS2_FS is not set | ||
| 591 | # CONFIG_OCFS2_FS is not set | ||
| 592 | # CONFIG_BTRFS_FS is not set | ||
| 593 | # CONFIG_FILE_LOCKING is not set | ||
| 594 | # CONFIG_FSNOTIFY is not set | ||
| 595 | # CONFIG_INOTIFY is not set | ||
| 596 | # CONFIG_QUOTA is not set | ||
| 597 | # CONFIG_AUTOFS_FS is not set | ||
| 598 | # CONFIG_AUTOFS4_FS is not set | ||
| 599 | # CONFIG_FUSE_FS is not set | ||
| 600 | |||
| 601 | # | ||
| 602 | # Caches | ||
| 603 | # | ||
| 604 | # CONFIG_FSCACHE is not set | ||
| 605 | |||
| 606 | # | ||
| 607 | # CD-ROM/DVD Filesystems | ||
| 608 | # | ||
| 609 | # CONFIG_ISO9660_FS is not set | ||
| 610 | # CONFIG_UDF_FS is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # DOS/FAT/NT Filesystems | ||
| 614 | # | ||
| 615 | # CONFIG_MSDOS_FS is not set | ||
| 616 | # CONFIG_VFAT_FS is not set | ||
| 617 | # CONFIG_NTFS_FS is not set | ||
| 618 | |||
| 619 | # | ||
| 620 | # Pseudo filesystems | ||
| 621 | # | ||
| 622 | CONFIG_PROC_FS=y | ||
| 623 | CONFIG_PROC_SYSCTL=y | ||
| 624 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 625 | CONFIG_SYSFS=y | ||
| 626 | CONFIG_TMPFS=y | ||
| 627 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 628 | # CONFIG_HUGETLB_PAGE is not set | ||
| 629 | # CONFIG_CONFIGFS_FS is not set | ||
| 630 | CONFIG_MISC_FILESYSTEMS=y | ||
| 631 | # CONFIG_ADFS_FS is not set | ||
| 632 | # CONFIG_AFFS_FS is not set | ||
| 633 | # CONFIG_HFS_FS is not set | ||
| 634 | # CONFIG_HFSPLUS_FS is not set | ||
| 635 | # CONFIG_BEFS_FS is not set | ||
| 636 | # CONFIG_BFS_FS is not set | ||
| 637 | # CONFIG_EFS_FS is not set | ||
| 638 | CONFIG_JFFS2_FS=y | ||
| 639 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 640 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 641 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 642 | CONFIG_JFFS2_SUMMARY=y | ||
| 643 | CONFIG_JFFS2_FS_XATTR=y | ||
| 644 | CONFIG_JFFS2_FS_POSIX_ACL=y | ||
| 645 | # CONFIG_JFFS2_FS_SECURITY is not set | ||
| 646 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 647 | CONFIG_JFFS2_ZLIB=y | ||
| 648 | # CONFIG_JFFS2_LZO is not set | ||
| 649 | CONFIG_JFFS2_RTIME=y | ||
| 650 | # CONFIG_JFFS2_RUBIN is not set | ||
| 651 | # CONFIG_CRAMFS is not set | ||
| 652 | # CONFIG_SQUASHFS is not set | ||
| 653 | # CONFIG_VXFS_FS is not set | ||
| 654 | # CONFIG_MINIX_FS is not set | ||
| 655 | # CONFIG_OMFS_FS is not set | ||
| 656 | # CONFIG_HPFS_FS is not set | ||
| 657 | # CONFIG_QNX4FS_FS is not set | ||
| 658 | # CONFIG_ROMFS_FS is not set | ||
| 659 | # CONFIG_SYSV_FS is not set | ||
| 660 | # CONFIG_UFS_FS is not set | ||
| 661 | # CONFIG_NILFS2_FS is not set | ||
| 662 | # CONFIG_NETWORK_FILESYSTEMS is not set | ||
| 663 | |||
| 664 | # | ||
| 665 | # Partition Types | ||
| 666 | # | ||
| 667 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 668 | CONFIG_MSDOS_PARTITION=y | ||
| 669 | # CONFIG_NLS is not set | ||
| 670 | |||
| 671 | # | ||
| 672 | # Kernel hacking | ||
| 673 | # | ||
| 674 | # CONFIG_PRINTK_TIME is not set | ||
| 675 | # CONFIG_ENABLE_WARN_DEPRECATED is not set | ||
| 676 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 677 | CONFIG_FRAME_WARN=1024 | ||
| 678 | CONFIG_MAGIC_SYSRQ=y | ||
| 679 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 680 | # CONFIG_DEBUG_FS is not set | ||
| 681 | CONFIG_HEADERS_CHECK=y | ||
| 682 | # CONFIG_DEBUG_KERNEL is not set | ||
| 683 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 684 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 685 | CONFIG_FRAME_POINTER=y | ||
| 686 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 687 | # CONFIG_LATENCYTOP is not set | ||
| 688 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 689 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 690 | CONFIG_TRACING_SUPPORT=y | ||
| 691 | # CONFIG_FTRACE is not set | ||
| 692 | # CONFIG_BUILD_DOCSRC is not set | ||
| 693 | # CONFIG_SAMPLES is not set | ||
| 694 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 695 | # CONFIG_ARM_UNWIND is not set | ||
| 696 | # CONFIG_DEBUG_USER is not set | ||
| 697 | |||
| 698 | # | ||
| 699 | # Security options | ||
| 700 | # | ||
| 701 | # CONFIG_KEYS is not set | ||
| 702 | # CONFIG_SECURITY is not set | ||
| 703 | # CONFIG_SECURITYFS is not set | ||
| 704 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 705 | # CONFIG_CRYPTO is not set | ||
| 706 | # CONFIG_BINARY_PRINTF is not set | ||
| 707 | |||
| 708 | # | ||
| 709 | # Library routines | ||
| 710 | # | ||
| 711 | CONFIG_BITREVERSE=y | ||
| 712 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 713 | # CONFIG_CRC_CCITT is not set | ||
| 714 | # CONFIG_CRC16 is not set | ||
| 715 | # CONFIG_CRC_T10DIF is not set | ||
| 716 | # CONFIG_CRC_ITU_T is not set | ||
| 717 | CONFIG_CRC32=y | ||
| 718 | # CONFIG_CRC7 is not set | ||
| 719 | # CONFIG_LIBCRC32C is not set | ||
| 720 | CONFIG_ZLIB_INFLATE=y | ||
| 721 | CONFIG_ZLIB_DEFLATE=y | ||
| 722 | CONFIG_HAS_IOMEM=y | ||
| 723 | CONFIG_HAS_IOPORT=y | ||
| 724 | CONFIG_HAS_DMA=y | ||
| 725 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig new file mode 100644 index 000000000000..601e7f3d5e97 --- /dev/null +++ b/arch/arm/configs/cpu9260_defconfig | |||
| @@ -0,0 +1,1338 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.31-rc3 | ||
| 4 | # Tue Jul 14 14:57:55 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_GENERIC_HARDIRQS=y | ||
| 13 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | CONFIG_GENERIC_HWEIGHT=y | ||
| 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 23 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 25 | CONFIG_CONSTRUCTORS=y | ||
| 26 | |||
| 27 | # | ||
| 28 | # General setup | ||
| 29 | # | ||
| 30 | CONFIG_EXPERIMENTAL=y | ||
| 31 | CONFIG_BROKEN_ON_SMP=y | ||
| 32 | CONFIG_LOCK_KERNEL=y | ||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 34 | CONFIG_LOCALVERSION="" | ||
| 35 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 36 | # CONFIG_SWAP is not set | ||
| 37 | CONFIG_SYSVIPC=y | ||
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 39 | # CONFIG_POSIX_MQUEUE is not set | ||
| 40 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 41 | # CONFIG_TASKSTATS is not set | ||
| 42 | # CONFIG_AUDIT is not set | ||
| 43 | |||
| 44 | # | ||
| 45 | # RCU Subsystem | ||
| 46 | # | ||
| 47 | CONFIG_CLASSIC_RCU=y | ||
| 48 | # CONFIG_TREE_RCU is not set | ||
| 49 | # CONFIG_PREEMPT_RCU is not set | ||
| 50 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 51 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 52 | # CONFIG_IKCONFIG is not set | ||
| 53 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 54 | # CONFIG_GROUP_SCHED is not set | ||
| 55 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | ||
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_IPC_NS is not set | ||
| 62 | # CONFIG_USER_NS is not set | ||
| 63 | # CONFIG_PID_NS is not set | ||
| 64 | # CONFIG_NET_NS is not set | ||
| 65 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 66 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 67 | CONFIG_SYSCTL=y | ||
| 68 | CONFIG_ANON_INODES=y | ||
| 69 | # CONFIG_EMBEDDED is not set | ||
| 70 | CONFIG_UID16=y | ||
| 71 | CONFIG_SYSCTL_SYSCALL=y | ||
| 72 | CONFIG_KALLSYMS=y | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | |||
| 87 | # | ||
| 88 | # Performance Counters | ||
| 89 | # | ||
| 90 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 91 | CONFIG_SLUB_DEBUG=y | ||
| 92 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 93 | CONFIG_COMPAT_BRK=y | ||
| 94 | # CONFIG_SLAB is not set | ||
| 95 | CONFIG_SLUB=y | ||
| 96 | # CONFIG_SLOB is not set | ||
| 97 | # CONFIG_PROFILING is not set | ||
| 98 | # CONFIG_MARKERS is not set | ||
| 99 | CONFIG_HAVE_OPROFILE=y | ||
| 100 | # CONFIG_KPROBES is not set | ||
| 101 | CONFIG_HAVE_KPROBES=y | ||
| 102 | CONFIG_HAVE_KRETPROBES=y | ||
| 103 | CONFIG_HAVE_CLK=y | ||
| 104 | |||
| 105 | # | ||
| 106 | # GCOV-based kernel profiling | ||
| 107 | # | ||
| 108 | # CONFIG_SLOW_WORK is not set | ||
| 109 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 110 | CONFIG_SLABINFO=y | ||
| 111 | CONFIG_RT_MUTEXES=y | ||
| 112 | CONFIG_BASE_SMALL=0 | ||
| 113 | CONFIG_MODULES=y | ||
| 114 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 115 | CONFIG_MODULE_UNLOAD=y | ||
| 116 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 117 | # CONFIG_MODVERSIONS is not set | ||
| 118 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 119 | CONFIG_BLOCK=y | ||
| 120 | CONFIG_LBDAF=y | ||
| 121 | # CONFIG_BLK_DEV_BSG is not set | ||
| 122 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 123 | |||
| 124 | # | ||
| 125 | # IO Schedulers | ||
| 126 | # | ||
| 127 | CONFIG_IOSCHED_NOOP=y | ||
| 128 | # CONFIG_IOSCHED_AS is not set | ||
| 129 | CONFIG_IOSCHED_DEADLINE=y | ||
| 130 | # CONFIG_IOSCHED_CFQ is not set | ||
| 131 | # CONFIG_DEFAULT_AS is not set | ||
| 132 | CONFIG_DEFAULT_DEADLINE=y | ||
| 133 | # CONFIG_DEFAULT_CFQ is not set | ||
| 134 | # CONFIG_DEFAULT_NOOP is not set | ||
| 135 | CONFIG_DEFAULT_IOSCHED="deadline" | ||
| 136 | # CONFIG_FREEZER is not set | ||
| 137 | |||
| 138 | # | ||
| 139 | # System Type | ||
| 140 | # | ||
| 141 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 142 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 143 | # CONFIG_ARCH_REALVIEW is not set | ||
| 144 | # CONFIG_ARCH_VERSATILE is not set | ||
| 145 | CONFIG_ARCH_AT91=y | ||
| 146 | # CONFIG_ARCH_CLPS711X is not set | ||
| 147 | # CONFIG_ARCH_GEMINI is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | ||
| 149 | # CONFIG_ARCH_EP93XX is not set | ||
| 150 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 151 | # CONFIG_ARCH_MXC is not set | ||
| 152 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 153 | # CONFIG_ARCH_NETX is not set | ||
| 154 | # CONFIG_ARCH_H720X is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_LOKI is not set | ||
| 164 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 165 | # CONFIG_ARCH_ORION5X is not set | ||
| 166 | # CONFIG_ARCH_MMP is not set | ||
| 167 | # CONFIG_ARCH_KS8695 is not set | ||
| 168 | # CONFIG_ARCH_NS9XXX is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 170 | # CONFIG_ARCH_PNX4008 is not set | ||
| 171 | # CONFIG_ARCH_PXA is not set | ||
| 172 | # CONFIG_ARCH_MSM is not set | ||
| 173 | # CONFIG_ARCH_RPC is not set | ||
| 174 | # CONFIG_ARCH_SA1100 is not set | ||
| 175 | # CONFIG_ARCH_S3C2410 is not set | ||
| 176 | # CONFIG_ARCH_S3C64XX is not set | ||
| 177 | # CONFIG_ARCH_SHARK is not set | ||
| 178 | # CONFIG_ARCH_LH7A40X is not set | ||
| 179 | # CONFIG_ARCH_U300 is not set | ||
| 180 | # CONFIG_ARCH_DAVINCI is not set | ||
| 181 | # CONFIG_ARCH_OMAP is not set | ||
| 182 | |||
| 183 | # | ||
| 184 | # Atmel AT91 System-on-Chip | ||
| 185 | # | ||
| 186 | # CONFIG_ARCH_AT91RM9200 is not set | ||
| 187 | CONFIG_ARCH_AT91SAM9260=y | ||
| 188 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 189 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 190 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 191 | # CONFIG_ARCH_AT91SAM9G20 is not set | ||
| 192 | # CONFIG_ARCH_AT91CAP9 is not set | ||
| 193 | # CONFIG_ARCH_AT91X40 is not set | ||
| 194 | CONFIG_AT91_PMC_UNIT=y | ||
| 195 | |||
| 196 | # | ||
| 197 | # AT91SAM9260 Variants | ||
| 198 | # | ||
| 199 | # CONFIG_ARCH_AT91SAM9260_SAM9XE is not set | ||
| 200 | |||
| 201 | # | ||
| 202 | # AT91SAM9260 / AT91SAM9XE Board Type | ||
| 203 | # | ||
| 204 | # CONFIG_MACH_AT91SAM9260EK is not set | ||
| 205 | # CONFIG_MACH_CAM60 is not set | ||
| 206 | # CONFIG_MACH_SAM9_L9260 is not set | ||
| 207 | # CONFIG_MACH_AFEB9260 is not set | ||
| 208 | # CONFIG_MACH_USB_A9260 is not set | ||
| 209 | # CONFIG_MACH_QIL_A9260 is not set | ||
| 210 | CONFIG_MACH_CPU9260=y | ||
| 211 | |||
| 212 | # | ||
| 213 | # AT91 Board Options | ||
| 214 | # | ||
| 215 | |||
| 216 | # | ||
| 217 | # AT91 Feature Selections | ||
| 218 | # | ||
| 219 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 220 | CONFIG_AT91_TIMER_HZ=100 | ||
| 221 | CONFIG_AT91_EARLY_DBGU=y | ||
| 222 | # CONFIG_AT91_EARLY_USART0 is not set | ||
| 223 | # CONFIG_AT91_EARLY_USART1 is not set | ||
| 224 | # CONFIG_AT91_EARLY_USART2 is not set | ||
| 225 | # CONFIG_AT91_EARLY_USART3 is not set | ||
| 226 | # CONFIG_AT91_EARLY_USART4 is not set | ||
| 227 | # CONFIG_AT91_EARLY_USART5 is not set | ||
| 228 | |||
| 229 | # | ||
| 230 | # Processor Type | ||
| 231 | # | ||
| 232 | CONFIG_CPU_32=y | ||
| 233 | CONFIG_CPU_ARM926T=y | ||
| 234 | CONFIG_CPU_32v5=y | ||
| 235 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 236 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 237 | CONFIG_CPU_CACHE_VIVT=y | ||
| 238 | CONFIG_CPU_COPY_V4WB=y | ||
| 239 | CONFIG_CPU_TLB_V4WBI=y | ||
| 240 | CONFIG_CPU_CP15=y | ||
| 241 | CONFIG_CPU_CP15_MMU=y | ||
| 242 | |||
| 243 | # | ||
| 244 | # Processor Features | ||
| 245 | # | ||
| 246 | # CONFIG_ARM_THUMB is not set | ||
| 247 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 248 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 249 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 250 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 251 | |||
| 252 | # | ||
| 253 | # Bus support | ||
| 254 | # | ||
| 255 | # CONFIG_PCI_SYSCALL is not set | ||
| 256 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 257 | # CONFIG_PCCARD is not set | ||
| 258 | |||
| 259 | # | ||
| 260 | # Kernel Features | ||
| 261 | # | ||
| 262 | # CONFIG_NO_HZ is not set | ||
| 263 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 264 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 265 | CONFIG_VMSPLIT_3G=y | ||
| 266 | # CONFIG_VMSPLIT_2G is not set | ||
| 267 | # CONFIG_VMSPLIT_1G is not set | ||
| 268 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 269 | CONFIG_PREEMPT=y | ||
| 270 | CONFIG_HZ=100 | ||
| 271 | CONFIG_AEABI=y | ||
| 272 | CONFIG_OABI_COMPAT=y | ||
| 273 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 274 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 275 | # CONFIG_HIGHMEM is not set | ||
| 276 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 277 | CONFIG_FLATMEM_MANUAL=y | ||
| 278 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 279 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 280 | CONFIG_FLATMEM=y | ||
| 281 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 282 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 283 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 284 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 285 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 286 | CONFIG_VIRT_TO_BUS=y | ||
| 287 | CONFIG_HAVE_MLOCK=y | ||
| 288 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 289 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 290 | # CONFIG_LEDS is not set | ||
| 291 | CONFIG_ALIGNMENT_TRAP=y | ||
| 292 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 293 | |||
| 294 | # | ||
| 295 | # Boot options | ||
| 296 | # | ||
| 297 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 298 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 299 | CONFIG_CMDLINE="" | ||
| 300 | # CONFIG_XIP_KERNEL is not set | ||
| 301 | # CONFIG_KEXEC is not set | ||
| 302 | |||
| 303 | # | ||
| 304 | # CPU Power Management | ||
| 305 | # | ||
| 306 | # CONFIG_CPU_IDLE is not set | ||
| 307 | |||
| 308 | # | ||
| 309 | # Floating point emulation | ||
| 310 | # | ||
| 311 | |||
| 312 | # | ||
| 313 | # At least one emulation must be selected | ||
| 314 | # | ||
| 315 | # CONFIG_FPE_NWFPE is not set | ||
| 316 | # CONFIG_FPE_FASTFPE is not set | ||
| 317 | # CONFIG_VFP is not set | ||
| 318 | |||
| 319 | # | ||
| 320 | # Userspace binary formats | ||
| 321 | # | ||
| 322 | CONFIG_BINFMT_ELF=y | ||
| 323 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 324 | CONFIG_HAVE_AOUT=y | ||
| 325 | # CONFIG_BINFMT_AOUT is not set | ||
| 326 | # CONFIG_BINFMT_MISC is not set | ||
| 327 | |||
| 328 | # | ||
| 329 | # Power management options | ||
| 330 | # | ||
| 331 | # CONFIG_PM is not set | ||
| 332 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 333 | CONFIG_NET=y | ||
| 334 | |||
| 335 | # | ||
| 336 | # Networking options | ||
| 337 | # | ||
| 338 | CONFIG_PACKET=y | ||
| 339 | # CONFIG_PACKET_MMAP is not set | ||
| 340 | CONFIG_UNIX=y | ||
| 341 | # CONFIG_NET_KEY is not set | ||
| 342 | CONFIG_INET=y | ||
| 343 | # CONFIG_IP_MULTICAST is not set | ||
| 344 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 345 | CONFIG_IP_FIB_HASH=y | ||
| 346 | CONFIG_IP_PNP=y | ||
| 347 | # CONFIG_IP_PNP_DHCP is not set | ||
| 348 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 349 | # CONFIG_IP_PNP_RARP is not set | ||
| 350 | # CONFIG_NET_IPIP is not set | ||
| 351 | # CONFIG_NET_IPGRE is not set | ||
| 352 | # CONFIG_ARPD is not set | ||
| 353 | # CONFIG_SYN_COOKIES is not set | ||
| 354 | # CONFIG_INET_AH is not set | ||
| 355 | # CONFIG_INET_ESP is not set | ||
| 356 | # CONFIG_INET_IPCOMP is not set | ||
| 357 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 358 | # CONFIG_INET_TUNNEL is not set | ||
| 359 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 360 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 361 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 362 | CONFIG_INET_LRO=y | ||
| 363 | CONFIG_INET_DIAG=y | ||
| 364 | CONFIG_INET_TCP_DIAG=y | ||
| 365 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 366 | CONFIG_TCP_CONG_CUBIC=y | ||
| 367 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 368 | # CONFIG_TCP_MD5SIG is not set | ||
| 369 | # CONFIG_IPV6 is not set | ||
| 370 | # CONFIG_NETWORK_SECMARK is not set | ||
| 371 | # CONFIG_NETFILTER is not set | ||
| 372 | # CONFIG_IP_DCCP is not set | ||
| 373 | # CONFIG_IP_SCTP is not set | ||
| 374 | # CONFIG_TIPC is not set | ||
| 375 | # CONFIG_ATM is not set | ||
| 376 | # CONFIG_BRIDGE is not set | ||
| 377 | # CONFIG_NET_DSA is not set | ||
| 378 | # CONFIG_VLAN_8021Q is not set | ||
| 379 | # CONFIG_DECNET is not set | ||
| 380 | # CONFIG_LLC2 is not set | ||
| 381 | # CONFIG_IPX is not set | ||
| 382 | # CONFIG_ATALK is not set | ||
| 383 | # CONFIG_X25 is not set | ||
| 384 | # CONFIG_LAPB is not set | ||
| 385 | # CONFIG_ECONET is not set | ||
| 386 | # CONFIG_WAN_ROUTER is not set | ||
| 387 | # CONFIG_PHONET is not set | ||
| 388 | # CONFIG_IEEE802154 is not set | ||
| 389 | # CONFIG_NET_SCHED is not set | ||
| 390 | # CONFIG_DCB is not set | ||
| 391 | |||
| 392 | # | ||
| 393 | # Network testing | ||
| 394 | # | ||
| 395 | # CONFIG_NET_PKTGEN is not set | ||
| 396 | # CONFIG_HAMRADIO is not set | ||
| 397 | # CONFIG_CAN is not set | ||
| 398 | # CONFIG_IRDA is not set | ||
| 399 | # CONFIG_BT is not set | ||
| 400 | # CONFIG_AF_RXRPC is not set | ||
| 401 | # CONFIG_WIRELESS is not set | ||
| 402 | # CONFIG_WIMAX is not set | ||
| 403 | # CONFIG_RFKILL is not set | ||
| 404 | # CONFIG_NET_9P is not set | ||
| 405 | |||
| 406 | # | ||
| 407 | # Device Drivers | ||
| 408 | # | ||
| 409 | |||
| 410 | # | ||
| 411 | # Generic Driver Options | ||
| 412 | # | ||
| 413 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 414 | CONFIG_STANDALONE=y | ||
| 415 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 416 | CONFIG_FW_LOADER=y | ||
| 417 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 418 | CONFIG_EXTRA_FIRMWARE="" | ||
| 419 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 420 | # CONFIG_CONNECTOR is not set | ||
| 421 | CONFIG_MTD=y | ||
| 422 | # CONFIG_MTD_DEBUG is not set | ||
| 423 | # CONFIG_MTD_CONCAT is not set | ||
| 424 | CONFIG_MTD_PARTITIONS=y | ||
| 425 | # CONFIG_MTD_TESTS is not set | ||
| 426 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 427 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 428 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 429 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 430 | |||
| 431 | # | ||
| 432 | # User Modules And Translation Layers | ||
| 433 | # | ||
| 434 | CONFIG_MTD_CHAR=y | ||
| 435 | CONFIG_MTD_BLKDEVS=y | ||
| 436 | CONFIG_MTD_BLOCK=y | ||
| 437 | # CONFIG_FTL is not set | ||
| 438 | # CONFIG_NFTL is not set | ||
| 439 | # CONFIG_INFTL is not set | ||
| 440 | # CONFIG_RFD_FTL is not set | ||
| 441 | # CONFIG_SSFDC is not set | ||
| 442 | # CONFIG_MTD_OOPS is not set | ||
| 443 | |||
| 444 | # | ||
| 445 | # RAM/ROM/Flash chip drivers | ||
| 446 | # | ||
| 447 | CONFIG_MTD_CFI=y | ||
| 448 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 449 | CONFIG_MTD_GEN_PROBE=y | ||
| 450 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 451 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 452 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 453 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 454 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 455 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 456 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 457 | CONFIG_MTD_CFI_I1=y | ||
| 458 | CONFIG_MTD_CFI_I2=y | ||
| 459 | # CONFIG_MTD_CFI_I4 is not set | ||
| 460 | # CONFIG_MTD_CFI_I8 is not set | ||
| 461 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 462 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 463 | # CONFIG_MTD_CFI_STAA is not set | ||
| 464 | CONFIG_MTD_CFI_UTIL=y | ||
| 465 | CONFIG_MTD_RAM=y | ||
| 466 | # CONFIG_MTD_ROM is not set | ||
| 467 | # CONFIG_MTD_ABSENT is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Mapping drivers for chip access | ||
| 471 | # | ||
| 472 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 473 | CONFIG_MTD_PHYSMAP=y | ||
| 474 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 475 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 476 | CONFIG_MTD_PLATRAM=y | ||
| 477 | |||
| 478 | # | ||
| 479 | # Self-contained MTD device drivers | ||
| 480 | # | ||
| 481 | # CONFIG_MTD_SLRAM is not set | ||
| 482 | # CONFIG_MTD_PHRAM is not set | ||
| 483 | # CONFIG_MTD_MTDRAM is not set | ||
| 484 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 485 | |||
| 486 | # | ||
| 487 | # Disk-On-Chip Device Drivers | ||
| 488 | # | ||
| 489 | # CONFIG_MTD_DOC2000 is not set | ||
| 490 | # CONFIG_MTD_DOC2001 is not set | ||
| 491 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 492 | CONFIG_MTD_NAND=y | ||
| 493 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 494 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 495 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 496 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 497 | CONFIG_MTD_NAND_IDS=y | ||
| 498 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 499 | CONFIG_MTD_NAND_ATMEL=y | ||
| 500 | CONFIG_MTD_NAND_ATMEL_ECC_HW=y | ||
| 501 | # CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set | ||
| 502 | # CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set | ||
| 503 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 504 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 505 | # CONFIG_MTD_ALAUDA is not set | ||
| 506 | # CONFIG_MTD_ONENAND is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # LPDDR flash memory drivers | ||
| 510 | # | ||
| 511 | # CONFIG_MTD_LPDDR is not set | ||
| 512 | |||
| 513 | # | ||
| 514 | # UBI - Unsorted block images | ||
| 515 | # | ||
| 516 | # CONFIG_MTD_UBI is not set | ||
| 517 | # CONFIG_PARPORT is not set | ||
| 518 | CONFIG_BLK_DEV=y | ||
| 519 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 520 | CONFIG_BLK_DEV_LOOP=y | ||
| 521 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 522 | CONFIG_BLK_DEV_NBD=y | ||
| 523 | # CONFIG_BLK_DEV_UB is not set | ||
| 524 | CONFIG_BLK_DEV_RAM=y | ||
| 525 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 526 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 527 | # CONFIG_BLK_DEV_XIP is not set | ||
| 528 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 529 | # CONFIG_ATA_OVER_ETH is not set | ||
| 530 | # CONFIG_MG_DISK is not set | ||
| 531 | # CONFIG_MISC_DEVICES is not set | ||
| 532 | CONFIG_HAVE_IDE=y | ||
| 533 | # CONFIG_IDE is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # SCSI device support | ||
| 537 | # | ||
| 538 | # CONFIG_RAID_ATTRS is not set | ||
| 539 | CONFIG_SCSI=y | ||
| 540 | CONFIG_SCSI_DMA=y | ||
| 541 | # CONFIG_SCSI_TGT is not set | ||
| 542 | # CONFIG_SCSI_NETLINK is not set | ||
| 543 | CONFIG_SCSI_PROC_FS=y | ||
| 544 | |||
| 545 | # | ||
| 546 | # SCSI support type (disk, tape, CD-ROM) | ||
| 547 | # | ||
| 548 | CONFIG_BLK_DEV_SD=y | ||
| 549 | # CONFIG_CHR_DEV_ST is not set | ||
| 550 | # CONFIG_CHR_DEV_OSST is not set | ||
| 551 | # CONFIG_BLK_DEV_SR is not set | ||
| 552 | # CONFIG_CHR_DEV_SG is not set | ||
| 553 | # CONFIG_CHR_DEV_SCH is not set | ||
| 554 | CONFIG_SCSI_MULTI_LUN=y | ||
| 555 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 556 | # CONFIG_SCSI_LOGGING is not set | ||
| 557 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 558 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 559 | |||
| 560 | # | ||
| 561 | # SCSI Transports | ||
| 562 | # | ||
| 563 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 564 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 565 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 566 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 567 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 568 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 569 | # CONFIG_SCSI_DH is not set | ||
| 570 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 571 | # CONFIG_ATA is not set | ||
| 572 | # CONFIG_MD is not set | ||
| 573 | CONFIG_NETDEVICES=y | ||
| 574 | # CONFIG_DUMMY is not set | ||
| 575 | # CONFIG_BONDING is not set | ||
| 576 | # CONFIG_MACVLAN is not set | ||
| 577 | # CONFIG_EQUALIZER is not set | ||
| 578 | # CONFIG_TUN is not set | ||
| 579 | # CONFIG_VETH is not set | ||
| 580 | CONFIG_PHYLIB=y | ||
| 581 | |||
| 582 | # | ||
| 583 | # MII PHY device drivers | ||
| 584 | # | ||
| 585 | # CONFIG_MARVELL_PHY is not set | ||
| 586 | # CONFIG_DAVICOM_PHY is not set | ||
| 587 | # CONFIG_QSEMI_PHY is not set | ||
| 588 | # CONFIG_LXT_PHY is not set | ||
| 589 | # CONFIG_CICADA_PHY is not set | ||
| 590 | # CONFIG_VITESSE_PHY is not set | ||
| 591 | CONFIG_SMSC_PHY=y | ||
| 592 | # CONFIG_BROADCOM_PHY is not set | ||
| 593 | # CONFIG_ICPLUS_PHY is not set | ||
| 594 | # CONFIG_REALTEK_PHY is not set | ||
| 595 | # CONFIG_NATIONAL_PHY is not set | ||
| 596 | # CONFIG_STE10XP is not set | ||
| 597 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 598 | # CONFIG_FIXED_PHY is not set | ||
| 599 | # CONFIG_MDIO_BITBANG is not set | ||
| 600 | CONFIG_NET_ETHERNET=y | ||
| 601 | CONFIG_MII=y | ||
| 602 | CONFIG_MACB=y | ||
| 603 | # CONFIG_AX88796 is not set | ||
| 604 | # CONFIG_SMC91X is not set | ||
| 605 | # CONFIG_DM9000 is not set | ||
| 606 | # CONFIG_ETHOC is not set | ||
| 607 | # CONFIG_SMC911X is not set | ||
| 608 | # CONFIG_SMSC911X is not set | ||
| 609 | # CONFIG_DNET is not set | ||
| 610 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 611 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 612 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 613 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 614 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 615 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 616 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 617 | # CONFIG_B44 is not set | ||
| 618 | # CONFIG_KS8842 is not set | ||
| 619 | # CONFIG_NETDEV_1000 is not set | ||
| 620 | # CONFIG_NETDEV_10000 is not set | ||
| 621 | |||
| 622 | # | ||
| 623 | # Wireless LAN | ||
| 624 | # | ||
| 625 | # CONFIG_WLAN_PRE80211 is not set | ||
| 626 | # CONFIG_WLAN_80211 is not set | ||
| 627 | |||
| 628 | # | ||
| 629 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 630 | # | ||
| 631 | |||
| 632 | # | ||
| 633 | # USB Network Adapters | ||
| 634 | # | ||
| 635 | # CONFIG_USB_CATC is not set | ||
| 636 | # CONFIG_USB_KAWETH is not set | ||
| 637 | # CONFIG_USB_PEGASUS is not set | ||
| 638 | # CONFIG_USB_RTL8150 is not set | ||
| 639 | # CONFIG_USB_USBNET is not set | ||
| 640 | # CONFIG_WAN is not set | ||
| 641 | CONFIG_PPP=y | ||
| 642 | # CONFIG_PPP_MULTILINK is not set | ||
| 643 | # CONFIG_PPP_FILTER is not set | ||
| 644 | CONFIG_PPP_ASYNC=y | ||
| 645 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 646 | CONFIG_PPP_DEFLATE=y | ||
| 647 | CONFIG_PPP_BSDCOMP=y | ||
| 648 | # CONFIG_PPP_MPPE is not set | ||
| 649 | # CONFIG_PPPOE is not set | ||
| 650 | # CONFIG_PPPOL2TP is not set | ||
| 651 | # CONFIG_SLIP is not set | ||
| 652 | CONFIG_SLHC=y | ||
| 653 | # CONFIG_NETCONSOLE is not set | ||
| 654 | # CONFIG_NETPOLL is not set | ||
| 655 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 656 | # CONFIG_ISDN is not set | ||
| 657 | |||
| 658 | # | ||
| 659 | # Input device support | ||
| 660 | # | ||
| 661 | CONFIG_INPUT=y | ||
| 662 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 663 | # CONFIG_INPUT_POLLDEV is not set | ||
| 664 | |||
| 665 | # | ||
| 666 | # Userland interfaces | ||
| 667 | # | ||
| 668 | CONFIG_INPUT_MOUSEDEV=y | ||
| 669 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 670 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 671 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 672 | # CONFIG_INPUT_JOYDEV is not set | ||
| 673 | # CONFIG_INPUT_EVDEV is not set | ||
| 674 | # CONFIG_INPUT_EVBUG is not set | ||
| 675 | |||
| 676 | # | ||
| 677 | # Input Device Drivers | ||
| 678 | # | ||
| 679 | CONFIG_INPUT_KEYBOARD=y | ||
| 680 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 681 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 682 | CONFIG_KEYBOARD_GPIO=y | ||
| 683 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 684 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 685 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 686 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 687 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 688 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 689 | # CONFIG_INPUT_MOUSE is not set | ||
| 690 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 691 | # CONFIG_INPUT_TABLET is not set | ||
| 692 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 693 | # CONFIG_INPUT_MISC is not set | ||
| 694 | |||
| 695 | # | ||
| 696 | # Hardware I/O ports | ||
| 697 | # | ||
| 698 | # CONFIG_SERIO is not set | ||
| 699 | # CONFIG_GAMEPORT is not set | ||
| 700 | |||
| 701 | # | ||
| 702 | # Character devices | ||
| 703 | # | ||
| 704 | CONFIG_VT=y | ||
| 705 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 706 | CONFIG_VT_CONSOLE=y | ||
| 707 | CONFIG_HW_CONSOLE=y | ||
| 708 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 709 | CONFIG_DEVKMEM=y | ||
| 710 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 711 | |||
| 712 | # | ||
| 713 | # Serial drivers | ||
| 714 | # | ||
| 715 | # CONFIG_SERIAL_8250 is not set | ||
| 716 | |||
| 717 | # | ||
| 718 | # Non-8250 serial port support | ||
| 719 | # | ||
| 720 | CONFIG_SERIAL_ATMEL=y | ||
| 721 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 722 | CONFIG_SERIAL_ATMEL_PDC=y | ||
| 723 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 724 | CONFIG_SERIAL_CORE=y | ||
| 725 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 726 | CONFIG_UNIX98_PTYS=y | ||
| 727 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 728 | CONFIG_LEGACY_PTYS=y | ||
| 729 | CONFIG_LEGACY_PTY_COUNT=32 | ||
| 730 | # CONFIG_IPMI_HANDLER is not set | ||
| 731 | # CONFIG_HW_RANDOM is not set | ||
| 732 | # CONFIG_R3964 is not set | ||
| 733 | # CONFIG_RAW_DRIVER is not set | ||
| 734 | # CONFIG_TCG_TPM is not set | ||
| 735 | CONFIG_I2C=y | ||
| 736 | CONFIG_I2C_BOARDINFO=y | ||
| 737 | CONFIG_I2C_CHARDEV=y | ||
| 738 | CONFIG_I2C_HELPER_AUTO=y | ||
| 739 | CONFIG_I2C_ALGOBIT=y | ||
| 740 | |||
| 741 | # | ||
| 742 | # I2C Hardware Bus support | ||
| 743 | # | ||
| 744 | |||
| 745 | # | ||
| 746 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 747 | # | ||
| 748 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 749 | CONFIG_I2C_GPIO=y | ||
| 750 | # CONFIG_I2C_OCORES is not set | ||
| 751 | # CONFIG_I2C_SIMTEC is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # External I2C/SMBus adapter drivers | ||
| 755 | # | ||
| 756 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 757 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 758 | # CONFIG_I2C_TINY_USB is not set | ||
| 759 | |||
| 760 | # | ||
| 761 | # Other I2C/SMBus bus drivers | ||
| 762 | # | ||
| 763 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 764 | # CONFIG_I2C_STUB is not set | ||
| 765 | |||
| 766 | # | ||
| 767 | # Miscellaneous I2C Chip support | ||
| 768 | # | ||
| 769 | # CONFIG_DS1682 is not set | ||
| 770 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 771 | # CONFIG_PCF8575 is not set | ||
| 772 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 773 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 774 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 775 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 776 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 777 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 778 | # CONFIG_SPI is not set | ||
| 779 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 780 | CONFIG_GPIOLIB=y | ||
| 781 | CONFIG_GPIO_SYSFS=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # Memory mapped GPIO expanders: | ||
| 785 | # | ||
| 786 | |||
| 787 | # | ||
| 788 | # I2C GPIO expanders: | ||
| 789 | # | ||
| 790 | # CONFIG_GPIO_MAX732X is not set | ||
| 791 | # CONFIG_GPIO_PCA953X is not set | ||
| 792 | # CONFIG_GPIO_PCF857X is not set | ||
| 793 | |||
| 794 | # | ||
| 795 | # PCI GPIO expanders: | ||
| 796 | # | ||
| 797 | |||
| 798 | # | ||
| 799 | # SPI GPIO expanders: | ||
| 800 | # | ||
| 801 | # CONFIG_W1 is not set | ||
| 802 | # CONFIG_POWER_SUPPLY is not set | ||
| 803 | # CONFIG_HWMON is not set | ||
| 804 | # CONFIG_THERMAL is not set | ||
| 805 | # CONFIG_THERMAL_HWMON is not set | ||
| 806 | CONFIG_WATCHDOG=y | ||
| 807 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 808 | |||
| 809 | # | ||
| 810 | # Watchdog Device Drivers | ||
| 811 | # | ||
| 812 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 813 | CONFIG_AT91SAM9X_WATCHDOG=y | ||
| 814 | |||
| 815 | # | ||
| 816 | # USB-based Watchdog Cards | ||
| 817 | # | ||
| 818 | # CONFIG_USBPCWATCHDOG is not set | ||
| 819 | CONFIG_SSB_POSSIBLE=y | ||
| 820 | |||
| 821 | # | ||
| 822 | # Sonics Silicon Backplane | ||
| 823 | # | ||
| 824 | # CONFIG_SSB is not set | ||
| 825 | |||
| 826 | # | ||
| 827 | # Multifunction device drivers | ||
| 828 | # | ||
| 829 | # CONFIG_MFD_CORE is not set | ||
| 830 | # CONFIG_MFD_SM501 is not set | ||
| 831 | # CONFIG_MFD_ASIC3 is not set | ||
| 832 | # CONFIG_HTC_EGPIO is not set | ||
| 833 | # CONFIG_HTC_PASIC3 is not set | ||
| 834 | # CONFIG_TPS65010 is not set | ||
| 835 | # CONFIG_TWL4030_CORE is not set | ||
| 836 | # CONFIG_MFD_TMIO is not set | ||
| 837 | # CONFIG_MFD_T7L66XB is not set | ||
| 838 | # CONFIG_MFD_TC6387XB is not set | ||
| 839 | # CONFIG_MFD_TC6393XB is not set | ||
| 840 | # CONFIG_PMIC_DA903X is not set | ||
| 841 | # CONFIG_MFD_WM8400 is not set | ||
| 842 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 843 | # CONFIG_MFD_PCF50633 is not set | ||
| 844 | # CONFIG_AB3100_CORE is not set | ||
| 845 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 846 | |||
| 847 | # | ||
| 848 | # Graphics support | ||
| 849 | # | ||
| 850 | # CONFIG_VGASTATE is not set | ||
| 851 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 852 | # CONFIG_FB is not set | ||
| 853 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 854 | |||
| 855 | # | ||
| 856 | # Display device support | ||
| 857 | # | ||
| 858 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 859 | |||
| 860 | # | ||
| 861 | # Console display driver support | ||
| 862 | # | ||
| 863 | # CONFIG_VGA_CONSOLE is not set | ||
| 864 | CONFIG_DUMMY_CONSOLE=y | ||
| 865 | # CONFIG_SOUND is not set | ||
| 866 | # CONFIG_HID_SUPPORT is not set | ||
| 867 | CONFIG_USB_SUPPORT=y | ||
| 868 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 869 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 870 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 871 | CONFIG_USB=y | ||
| 872 | # CONFIG_USB_DEBUG is not set | ||
| 873 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 874 | |||
| 875 | # | ||
| 876 | # Miscellaneous USB options | ||
| 877 | # | ||
| 878 | # CONFIG_USB_DEVICEFS is not set | ||
| 879 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 880 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 881 | # CONFIG_USB_OTG is not set | ||
| 882 | # CONFIG_USB_MON is not set | ||
| 883 | # CONFIG_USB_WUSB is not set | ||
| 884 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 885 | |||
| 886 | # | ||
| 887 | # USB Host Controller Drivers | ||
| 888 | # | ||
| 889 | # CONFIG_USB_C67X00_HCD is not set | ||
| 890 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 891 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 892 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 893 | CONFIG_USB_OHCI_HCD=y | ||
| 894 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 895 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 896 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 897 | # CONFIG_USB_SL811_HCD is not set | ||
| 898 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 899 | # CONFIG_USB_HWA_HCD is not set | ||
| 900 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 901 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 902 | |||
| 903 | # | ||
| 904 | # USB Device Class drivers | ||
| 905 | # | ||
| 906 | # CONFIG_USB_ACM is not set | ||
| 907 | # CONFIG_USB_PRINTER is not set | ||
| 908 | # CONFIG_USB_WDM is not set | ||
| 909 | # CONFIG_USB_TMC is not set | ||
| 910 | |||
| 911 | # | ||
| 912 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 913 | # | ||
| 914 | |||
| 915 | # | ||
| 916 | # also be needed; see USB_STORAGE Help for more info | ||
| 917 | # | ||
| 918 | CONFIG_USB_STORAGE=y | ||
| 919 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 920 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 921 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 922 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 923 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 924 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 925 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 926 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 927 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 928 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 929 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 930 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 931 | # CONFIG_USB_LIBUSUAL is not set | ||
| 932 | |||
| 933 | # | ||
| 934 | # USB Imaging devices | ||
| 935 | # | ||
| 936 | # CONFIG_USB_MDC800 is not set | ||
| 937 | # CONFIG_USB_MICROTEK is not set | ||
| 938 | |||
| 939 | # | ||
| 940 | # USB port drivers | ||
| 941 | # | ||
| 942 | # CONFIG_USB_SERIAL is not set | ||
| 943 | |||
| 944 | # | ||
| 945 | # USB Miscellaneous drivers | ||
| 946 | # | ||
| 947 | # CONFIG_USB_EMI62 is not set | ||
| 948 | # CONFIG_USB_EMI26 is not set | ||
| 949 | # CONFIG_USB_ADUTUX is not set | ||
| 950 | # CONFIG_USB_SEVSEG is not set | ||
| 951 | # CONFIG_USB_RIO500 is not set | ||
| 952 | # CONFIG_USB_LEGOTOWER is not set | ||
| 953 | # CONFIG_USB_LCD is not set | ||
| 954 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 955 | # CONFIG_USB_LED is not set | ||
| 956 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 957 | # CONFIG_USB_CYTHERM is not set | ||
| 958 | # CONFIG_USB_IDMOUSE is not set | ||
| 959 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 960 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 961 | # CONFIG_USB_LD is not set | ||
| 962 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 963 | # CONFIG_USB_IOWARRIOR is not set | ||
| 964 | # CONFIG_USB_ISIGHTFW is not set | ||
| 965 | # CONFIG_USB_VST is not set | ||
| 966 | CONFIG_USB_GADGET=y | ||
| 967 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 968 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 969 | CONFIG_USB_GADGET_SELECTED=y | ||
| 970 | CONFIG_USB_GADGET_AT91=y | ||
| 971 | CONFIG_USB_AT91=y | ||
| 972 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 973 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 974 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 975 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 976 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 977 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 978 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 979 | # CONFIG_USB_GADGET_IMX is not set | ||
| 980 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 981 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 982 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 983 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 984 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 985 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 986 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 987 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 988 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 989 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 990 | # CONFIG_USB_ZERO is not set | ||
| 991 | # CONFIG_USB_AUDIO is not set | ||
| 992 | CONFIG_USB_ETH=y | ||
| 993 | CONFIG_USB_ETH_RNDIS=y | ||
| 994 | # CONFIG_USB_GADGETFS is not set | ||
| 995 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 996 | # CONFIG_USB_G_SERIAL is not set | ||
| 997 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 998 | # CONFIG_USB_G_PRINTER is not set | ||
| 999 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1000 | |||
| 1001 | # | ||
| 1002 | # OTG and related infrastructure | ||
| 1003 | # | ||
| 1004 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1005 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 1006 | CONFIG_MMC=y | ||
| 1007 | # CONFIG_MMC_DEBUG is not set | ||
| 1008 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1009 | |||
| 1010 | # | ||
| 1011 | # MMC/SD/SDIO Card Drivers | ||
| 1012 | # | ||
| 1013 | CONFIG_MMC_BLOCK=y | ||
| 1014 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1015 | # CONFIG_SDIO_UART is not set | ||
| 1016 | # CONFIG_MMC_TEST is not set | ||
| 1017 | |||
| 1018 | # | ||
| 1019 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1020 | # | ||
| 1021 | # CONFIG_MMC_SDHCI is not set | ||
| 1022 | CONFIG_MMC_AT91=y | ||
| 1023 | # CONFIG_MEMSTICK is not set | ||
| 1024 | # CONFIG_ACCESSIBILITY is not set | ||
| 1025 | CONFIG_NEW_LEDS=y | ||
| 1026 | CONFIG_LEDS_CLASS=y | ||
| 1027 | |||
| 1028 | # | ||
| 1029 | # LED drivers | ||
| 1030 | # | ||
| 1031 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1032 | CONFIG_LEDS_GPIO=y | ||
| 1033 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1034 | # CONFIG_LEDS_LP3944 is not set | ||
| 1035 | # CONFIG_LEDS_PCA955X is not set | ||
| 1036 | # CONFIG_LEDS_BD2802 is not set | ||
| 1037 | |||
| 1038 | # | ||
| 1039 | # LED Triggers | ||
| 1040 | # | ||
| 1041 | CONFIG_LEDS_TRIGGERS=y | ||
| 1042 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1043 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1044 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1045 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1046 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1047 | |||
| 1048 | # | ||
| 1049 | # iptables trigger is under Netfilter config (LED target) | ||
| 1050 | # | ||
| 1051 | CONFIG_RTC_LIB=y | ||
| 1052 | CONFIG_RTC_CLASS=y | ||
| 1053 | # CONFIG_RTC_HCTOSYS is not set | ||
| 1054 | # CONFIG_RTC_DEBUG is not set | ||
| 1055 | |||
| 1056 | # | ||
| 1057 | # RTC interfaces | ||
| 1058 | # | ||
| 1059 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1060 | CONFIG_RTC_INTF_PROC=y | ||
| 1061 | CONFIG_RTC_INTF_DEV=y | ||
| 1062 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1063 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1064 | |||
| 1065 | # | ||
| 1066 | # I2C RTC drivers | ||
| 1067 | # | ||
| 1068 | CONFIG_RTC_DRV_DS1307=y | ||
| 1069 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1070 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1071 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1072 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1073 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1074 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1075 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1076 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1077 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1078 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1079 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1080 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1081 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1082 | |||
| 1083 | # | ||
| 1084 | # SPI RTC drivers | ||
| 1085 | # | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # Platform RTC drivers | ||
| 1089 | # | ||
| 1090 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1091 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1092 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1093 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1094 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1095 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1096 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1097 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1098 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1099 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1100 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1101 | |||
| 1102 | # | ||
| 1103 | # on-CPU RTC drivers | ||
| 1104 | # | ||
| 1105 | # CONFIG_RTC_DRV_AT91SAM9 is not set | ||
| 1106 | # CONFIG_DMADEVICES is not set | ||
| 1107 | # CONFIG_AUXDISPLAY is not set | ||
| 1108 | # CONFIG_REGULATOR is not set | ||
| 1109 | # CONFIG_UIO is not set | ||
| 1110 | # CONFIG_STAGING is not set | ||
| 1111 | |||
| 1112 | # | ||
| 1113 | # File systems | ||
| 1114 | # | ||
| 1115 | CONFIG_EXT2_FS=y | ||
| 1116 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1117 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1118 | CONFIG_EXT3_FS=y | ||
| 1119 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1120 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1121 | # CONFIG_EXT4_FS is not set | ||
| 1122 | CONFIG_JBD=y | ||
| 1123 | # CONFIG_REISERFS_FS is not set | ||
| 1124 | # CONFIG_JFS_FS is not set | ||
| 1125 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1126 | # CONFIG_XFS_FS is not set | ||
| 1127 | # CONFIG_GFS2_FS is not set | ||
| 1128 | # CONFIG_OCFS2_FS is not set | ||
| 1129 | # CONFIG_BTRFS_FS is not set | ||
| 1130 | CONFIG_FILE_LOCKING=y | ||
| 1131 | CONFIG_FSNOTIFY=y | ||
| 1132 | CONFIG_DNOTIFY=y | ||
| 1133 | CONFIG_INOTIFY=y | ||
| 1134 | CONFIG_INOTIFY_USER=y | ||
| 1135 | # CONFIG_QUOTA is not set | ||
| 1136 | # CONFIG_AUTOFS_FS is not set | ||
| 1137 | CONFIG_AUTOFS4_FS=y | ||
| 1138 | # CONFIG_FUSE_FS is not set | ||
| 1139 | |||
| 1140 | # | ||
| 1141 | # Caches | ||
| 1142 | # | ||
| 1143 | # CONFIG_FSCACHE is not set | ||
| 1144 | |||
| 1145 | # | ||
| 1146 | # CD-ROM/DVD Filesystems | ||
| 1147 | # | ||
| 1148 | # CONFIG_ISO9660_FS is not set | ||
| 1149 | # CONFIG_UDF_FS is not set | ||
| 1150 | |||
| 1151 | # | ||
| 1152 | # DOS/FAT/NT Filesystems | ||
| 1153 | # | ||
| 1154 | CONFIG_FAT_FS=y | ||
| 1155 | CONFIG_MSDOS_FS=y | ||
| 1156 | CONFIG_VFAT_FS=y | ||
| 1157 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1158 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1159 | # CONFIG_NTFS_FS is not set | ||
| 1160 | |||
| 1161 | # | ||
| 1162 | # Pseudo filesystems | ||
| 1163 | # | ||
| 1164 | CONFIG_PROC_FS=y | ||
| 1165 | CONFIG_PROC_SYSCTL=y | ||
| 1166 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1167 | CONFIG_SYSFS=y | ||
| 1168 | CONFIG_TMPFS=y | ||
| 1169 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1170 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1171 | # CONFIG_CONFIGFS_FS is not set | ||
| 1172 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1173 | # CONFIG_ADFS_FS is not set | ||
| 1174 | # CONFIG_AFFS_FS is not set | ||
| 1175 | # CONFIG_HFS_FS is not set | ||
| 1176 | # CONFIG_HFSPLUS_FS is not set | ||
| 1177 | # CONFIG_BEFS_FS is not set | ||
| 1178 | # CONFIG_BFS_FS is not set | ||
| 1179 | # CONFIG_EFS_FS is not set | ||
| 1180 | CONFIG_JFFS2_FS=y | ||
| 1181 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1182 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1183 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1184 | CONFIG_JFFS2_SUMMARY=y | ||
| 1185 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1186 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1187 | CONFIG_JFFS2_ZLIB=y | ||
| 1188 | # CONFIG_JFFS2_LZO is not set | ||
| 1189 | CONFIG_JFFS2_RTIME=y | ||
| 1190 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1191 | CONFIG_CRAMFS=y | ||
| 1192 | # CONFIG_SQUASHFS is not set | ||
| 1193 | # CONFIG_VXFS_FS is not set | ||
| 1194 | CONFIG_MINIX_FS=y | ||
| 1195 | # CONFIG_OMFS_FS is not set | ||
| 1196 | # CONFIG_HPFS_FS is not set | ||
| 1197 | # CONFIG_QNX4FS_FS is not set | ||
| 1198 | # CONFIG_ROMFS_FS is not set | ||
| 1199 | # CONFIG_SYSV_FS is not set | ||
| 1200 | # CONFIG_UFS_FS is not set | ||
| 1201 | # CONFIG_NILFS2_FS is not set | ||
| 1202 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1203 | CONFIG_NFS_FS=y | ||
| 1204 | CONFIG_NFS_V3=y | ||
| 1205 | # CONFIG_NFS_V3_ACL is not set | ||
| 1206 | # CONFIG_NFS_V4 is not set | ||
| 1207 | CONFIG_ROOT_NFS=y | ||
| 1208 | # CONFIG_NFSD is not set | ||
| 1209 | CONFIG_LOCKD=y | ||
| 1210 | CONFIG_LOCKD_V4=y | ||
| 1211 | CONFIG_NFS_COMMON=y | ||
| 1212 | CONFIG_SUNRPC=y | ||
| 1213 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1214 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1215 | # CONFIG_SMB_FS is not set | ||
| 1216 | # CONFIG_CIFS is not set | ||
| 1217 | # CONFIG_NCP_FS is not set | ||
| 1218 | # CONFIG_CODA_FS is not set | ||
| 1219 | # CONFIG_AFS_FS is not set | ||
| 1220 | |||
| 1221 | # | ||
| 1222 | # Partition Types | ||
| 1223 | # | ||
| 1224 | CONFIG_PARTITION_ADVANCED=y | ||
| 1225 | # CONFIG_ACORN_PARTITION is not set | ||
| 1226 | # CONFIG_OSF_PARTITION is not set | ||
| 1227 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1228 | # CONFIG_ATARI_PARTITION is not set | ||
| 1229 | # CONFIG_MAC_PARTITION is not set | ||
| 1230 | CONFIG_MSDOS_PARTITION=y | ||
| 1231 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1232 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1233 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1234 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1235 | # CONFIG_LDM_PARTITION is not set | ||
| 1236 | # CONFIG_SGI_PARTITION is not set | ||
| 1237 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1238 | # CONFIG_SUN_PARTITION is not set | ||
| 1239 | # CONFIG_KARMA_PARTITION is not set | ||
| 1240 | # CONFIG_EFI_PARTITION is not set | ||
| 1241 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1242 | CONFIG_NLS=y | ||
| 1243 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1244 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1245 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1246 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1247 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1248 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1249 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1250 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1251 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1252 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1253 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1254 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1255 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1256 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1257 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1258 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1259 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1260 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1261 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1262 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1263 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1264 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1265 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1266 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1267 | # CONFIG_NLS_ASCII is not set | ||
| 1268 | CONFIG_NLS_ISO8859_1=y | ||
| 1269 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1270 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1271 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1272 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1273 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1274 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1275 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1276 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1277 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1278 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1279 | # CONFIG_NLS_KOI8_R is not set | ||
| 1280 | # CONFIG_NLS_KOI8_U is not set | ||
| 1281 | CONFIG_NLS_UTF8=y | ||
| 1282 | # CONFIG_DLM is not set | ||
| 1283 | |||
| 1284 | # | ||
| 1285 | # Kernel hacking | ||
| 1286 | # | ||
| 1287 | # CONFIG_PRINTK_TIME is not set | ||
| 1288 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1289 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1290 | CONFIG_FRAME_WARN=1024 | ||
| 1291 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1292 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1293 | # CONFIG_DEBUG_FS is not set | ||
| 1294 | # CONFIG_HEADERS_CHECK is not set | ||
| 1295 | # CONFIG_DEBUG_KERNEL is not set | ||
| 1296 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1297 | # CONFIG_SLUB_STATS is not set | ||
| 1298 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1299 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1300 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1301 | # CONFIG_LATENCYTOP is not set | ||
| 1302 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1303 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1304 | CONFIG_TRACING_SUPPORT=y | ||
| 1305 | # CONFIG_FTRACE is not set | ||
| 1306 | # CONFIG_SAMPLES is not set | ||
| 1307 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1308 | CONFIG_ARM_UNWIND=y | ||
| 1309 | # CONFIG_DEBUG_USER is not set | ||
| 1310 | |||
| 1311 | # | ||
| 1312 | # Security options | ||
| 1313 | # | ||
| 1314 | # CONFIG_KEYS is not set | ||
| 1315 | # CONFIG_SECURITY is not set | ||
| 1316 | # CONFIG_SECURITYFS is not set | ||
| 1317 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1318 | # CONFIG_CRYPTO is not set | ||
| 1319 | # CONFIG_BINARY_PRINTF is not set | ||
| 1320 | |||
| 1321 | # | ||
| 1322 | # Library routines | ||
| 1323 | # | ||
| 1324 | CONFIG_BITREVERSE=y | ||
| 1325 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1326 | CONFIG_CRC_CCITT=y | ||
| 1327 | # CONFIG_CRC16 is not set | ||
| 1328 | # CONFIG_CRC_T10DIF is not set | ||
| 1329 | # CONFIG_CRC_ITU_T is not set | ||
| 1330 | CONFIG_CRC32=y | ||
| 1331 | # CONFIG_CRC7 is not set | ||
| 1332 | # CONFIG_LIBCRC32C is not set | ||
| 1333 | CONFIG_ZLIB_INFLATE=y | ||
| 1334 | CONFIG_ZLIB_DEFLATE=y | ||
| 1335 | CONFIG_HAS_IOMEM=y | ||
| 1336 | CONFIG_HAS_IOPORT=y | ||
| 1337 | CONFIG_HAS_DMA=y | ||
| 1338 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig new file mode 100644 index 000000000000..b5b9cbbc6977 --- /dev/null +++ b/arch/arm/configs/cpu9g20_defconfig | |||
| @@ -0,0 +1,1328 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.31-rc3 | ||
| 4 | # Tue Jul 14 15:03:43 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_GENERIC_HARDIRQS=y | ||
| 13 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | CONFIG_GENERIC_HWEIGHT=y | ||
| 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 23 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 25 | CONFIG_CONSTRUCTORS=y | ||
| 26 | |||
| 27 | # | ||
| 28 | # General setup | ||
| 29 | # | ||
| 30 | CONFIG_EXPERIMENTAL=y | ||
| 31 | CONFIG_BROKEN_ON_SMP=y | ||
| 32 | CONFIG_LOCK_KERNEL=y | ||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 34 | CONFIG_LOCALVERSION="" | ||
| 35 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 36 | # CONFIG_SWAP is not set | ||
| 37 | CONFIG_SYSVIPC=y | ||
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 39 | # CONFIG_POSIX_MQUEUE is not set | ||
| 40 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 41 | # CONFIG_TASKSTATS is not set | ||
| 42 | # CONFIG_AUDIT is not set | ||
| 43 | |||
| 44 | # | ||
| 45 | # RCU Subsystem | ||
| 46 | # | ||
| 47 | CONFIG_CLASSIC_RCU=y | ||
| 48 | # CONFIG_TREE_RCU is not set | ||
| 49 | # CONFIG_PREEMPT_RCU is not set | ||
| 50 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 51 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 52 | # CONFIG_IKCONFIG is not set | ||
| 53 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 54 | # CONFIG_GROUP_SCHED is not set | ||
| 55 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | ||
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_IPC_NS is not set | ||
| 62 | # CONFIG_USER_NS is not set | ||
| 63 | # CONFIG_PID_NS is not set | ||
| 64 | # CONFIG_NET_NS is not set | ||
| 65 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 66 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 67 | CONFIG_SYSCTL=y | ||
| 68 | CONFIG_ANON_INODES=y | ||
| 69 | # CONFIG_EMBEDDED is not set | ||
| 70 | CONFIG_UID16=y | ||
| 71 | CONFIG_SYSCTL_SYSCALL=y | ||
| 72 | CONFIG_KALLSYMS=y | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | |||
| 87 | # | ||
| 88 | # Performance Counters | ||
| 89 | # | ||
| 90 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 91 | CONFIG_SLUB_DEBUG=y | ||
| 92 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 93 | CONFIG_COMPAT_BRK=y | ||
| 94 | # CONFIG_SLAB is not set | ||
| 95 | CONFIG_SLUB=y | ||
| 96 | # CONFIG_SLOB is not set | ||
| 97 | # CONFIG_PROFILING is not set | ||
| 98 | # CONFIG_MARKERS is not set | ||
| 99 | CONFIG_HAVE_OPROFILE=y | ||
| 100 | # CONFIG_KPROBES is not set | ||
| 101 | CONFIG_HAVE_KPROBES=y | ||
| 102 | CONFIG_HAVE_KRETPROBES=y | ||
| 103 | CONFIG_HAVE_CLK=y | ||
| 104 | |||
| 105 | # | ||
| 106 | # GCOV-based kernel profiling | ||
| 107 | # | ||
| 108 | # CONFIG_SLOW_WORK is not set | ||
| 109 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 110 | CONFIG_SLABINFO=y | ||
| 111 | CONFIG_RT_MUTEXES=y | ||
| 112 | CONFIG_BASE_SMALL=0 | ||
| 113 | CONFIG_MODULES=y | ||
| 114 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 115 | CONFIG_MODULE_UNLOAD=y | ||
| 116 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 117 | # CONFIG_MODVERSIONS is not set | ||
| 118 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 119 | CONFIG_BLOCK=y | ||
| 120 | CONFIG_LBDAF=y | ||
| 121 | # CONFIG_BLK_DEV_BSG is not set | ||
| 122 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 123 | |||
| 124 | # | ||
| 125 | # IO Schedulers | ||
| 126 | # | ||
| 127 | CONFIG_IOSCHED_NOOP=y | ||
| 128 | # CONFIG_IOSCHED_AS is not set | ||
| 129 | CONFIG_IOSCHED_DEADLINE=y | ||
| 130 | # CONFIG_IOSCHED_CFQ is not set | ||
| 131 | # CONFIG_DEFAULT_AS is not set | ||
| 132 | CONFIG_DEFAULT_DEADLINE=y | ||
| 133 | # CONFIG_DEFAULT_CFQ is not set | ||
| 134 | # CONFIG_DEFAULT_NOOP is not set | ||
| 135 | CONFIG_DEFAULT_IOSCHED="deadline" | ||
| 136 | # CONFIG_FREEZER is not set | ||
| 137 | |||
| 138 | # | ||
| 139 | # System Type | ||
| 140 | # | ||
| 141 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 142 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 143 | # CONFIG_ARCH_REALVIEW is not set | ||
| 144 | # CONFIG_ARCH_VERSATILE is not set | ||
| 145 | CONFIG_ARCH_AT91=y | ||
| 146 | # CONFIG_ARCH_CLPS711X is not set | ||
| 147 | # CONFIG_ARCH_GEMINI is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | ||
| 149 | # CONFIG_ARCH_EP93XX is not set | ||
| 150 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 151 | # CONFIG_ARCH_MXC is not set | ||
| 152 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 153 | # CONFIG_ARCH_NETX is not set | ||
| 154 | # CONFIG_ARCH_H720X is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_LOKI is not set | ||
| 164 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 165 | # CONFIG_ARCH_ORION5X is not set | ||
| 166 | # CONFIG_ARCH_MMP is not set | ||
| 167 | # CONFIG_ARCH_KS8695 is not set | ||
| 168 | # CONFIG_ARCH_NS9XXX is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 170 | # CONFIG_ARCH_PNX4008 is not set | ||
| 171 | # CONFIG_ARCH_PXA is not set | ||
| 172 | # CONFIG_ARCH_MSM is not set | ||
| 173 | # CONFIG_ARCH_RPC is not set | ||
| 174 | # CONFIG_ARCH_SA1100 is not set | ||
| 175 | # CONFIG_ARCH_S3C2410 is not set | ||
| 176 | # CONFIG_ARCH_S3C64XX is not set | ||
| 177 | # CONFIG_ARCH_SHARK is not set | ||
| 178 | # CONFIG_ARCH_LH7A40X is not set | ||
| 179 | # CONFIG_ARCH_U300 is not set | ||
| 180 | # CONFIG_ARCH_DAVINCI is not set | ||
| 181 | # CONFIG_ARCH_OMAP is not set | ||
| 182 | |||
| 183 | # | ||
| 184 | # Atmel AT91 System-on-Chip | ||
| 185 | # | ||
| 186 | # CONFIG_ARCH_AT91RM9200 is not set | ||
| 187 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 188 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 189 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 190 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 191 | CONFIG_ARCH_AT91SAM9G20=y | ||
| 192 | # CONFIG_ARCH_AT91CAP9 is not set | ||
| 193 | # CONFIG_ARCH_AT91X40 is not set | ||
| 194 | CONFIG_AT91_PMC_UNIT=y | ||
| 195 | |||
| 196 | # | ||
| 197 | # AT91SAM9G20 Board Type | ||
| 198 | # | ||
| 199 | # CONFIG_MACH_AT91SAM9G20EK is not set | ||
| 200 | CONFIG_MACH_CPU9G20=y | ||
| 201 | |||
| 202 | # | ||
| 203 | # AT91 Board Options | ||
| 204 | # | ||
| 205 | |||
| 206 | # | ||
| 207 | # AT91 Feature Selections | ||
| 208 | # | ||
| 209 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 210 | CONFIG_AT91_TIMER_HZ=100 | ||
| 211 | CONFIG_AT91_EARLY_DBGU=y | ||
| 212 | # CONFIG_AT91_EARLY_USART0 is not set | ||
| 213 | # CONFIG_AT91_EARLY_USART1 is not set | ||
| 214 | # CONFIG_AT91_EARLY_USART2 is not set | ||
| 215 | # CONFIG_AT91_EARLY_USART3 is not set | ||
| 216 | # CONFIG_AT91_EARLY_USART4 is not set | ||
| 217 | # CONFIG_AT91_EARLY_USART5 is not set | ||
| 218 | |||
| 219 | # | ||
| 220 | # Processor Type | ||
| 221 | # | ||
| 222 | CONFIG_CPU_32=y | ||
| 223 | CONFIG_CPU_ARM926T=y | ||
| 224 | CONFIG_CPU_32v5=y | ||
| 225 | CONFIG_CPU_ABRT_EV5TJ=y | ||
| 226 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 227 | CONFIG_CPU_CACHE_VIVT=y | ||
| 228 | CONFIG_CPU_COPY_V4WB=y | ||
| 229 | CONFIG_CPU_TLB_V4WBI=y | ||
| 230 | CONFIG_CPU_CP15=y | ||
| 231 | CONFIG_CPU_CP15_MMU=y | ||
| 232 | |||
| 233 | # | ||
| 234 | # Processor Features | ||
| 235 | # | ||
| 236 | # CONFIG_ARM_THUMB is not set | ||
| 237 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 238 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 239 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 240 | # CONFIG_CPU_CACHE_ROUND_ROBIN is not set | ||
| 241 | |||
| 242 | # | ||
| 243 | # Bus support | ||
| 244 | # | ||
| 245 | # CONFIG_PCI_SYSCALL is not set | ||
| 246 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 247 | # CONFIG_PCCARD is not set | ||
| 248 | |||
| 249 | # | ||
| 250 | # Kernel Features | ||
| 251 | # | ||
| 252 | # CONFIG_NO_HZ is not set | ||
| 253 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 254 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 255 | CONFIG_VMSPLIT_3G=y | ||
| 256 | # CONFIG_VMSPLIT_2G is not set | ||
| 257 | # CONFIG_VMSPLIT_1G is not set | ||
| 258 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 259 | CONFIG_PREEMPT=y | ||
| 260 | CONFIG_HZ=100 | ||
| 261 | CONFIG_AEABI=y | ||
| 262 | CONFIG_OABI_COMPAT=y | ||
| 263 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 264 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 265 | # CONFIG_HIGHMEM is not set | ||
| 266 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 267 | CONFIG_FLATMEM_MANUAL=y | ||
| 268 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 269 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 270 | CONFIG_FLATMEM=y | ||
| 271 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 272 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 273 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 274 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 275 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 276 | CONFIG_VIRT_TO_BUS=y | ||
| 277 | CONFIG_HAVE_MLOCK=y | ||
| 278 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 279 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 280 | # CONFIG_LEDS is not set | ||
| 281 | CONFIG_ALIGNMENT_TRAP=y | ||
| 282 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 283 | |||
| 284 | # | ||
| 285 | # Boot options | ||
| 286 | # | ||
| 287 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 288 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 289 | CONFIG_CMDLINE="" | ||
| 290 | # CONFIG_XIP_KERNEL is not set | ||
| 291 | # CONFIG_KEXEC is not set | ||
| 292 | |||
| 293 | # | ||
| 294 | # CPU Power Management | ||
| 295 | # | ||
| 296 | # CONFIG_CPU_IDLE is not set | ||
| 297 | |||
| 298 | # | ||
| 299 | # Floating point emulation | ||
| 300 | # | ||
| 301 | |||
| 302 | # | ||
| 303 | # At least one emulation must be selected | ||
| 304 | # | ||
| 305 | # CONFIG_FPE_NWFPE is not set | ||
| 306 | # CONFIG_FPE_FASTFPE is not set | ||
| 307 | # CONFIG_VFP is not set | ||
| 308 | |||
| 309 | # | ||
| 310 | # Userspace binary formats | ||
| 311 | # | ||
| 312 | CONFIG_BINFMT_ELF=y | ||
| 313 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 314 | CONFIG_HAVE_AOUT=y | ||
| 315 | # CONFIG_BINFMT_AOUT is not set | ||
| 316 | # CONFIG_BINFMT_MISC is not set | ||
| 317 | |||
| 318 | # | ||
| 319 | # Power management options | ||
| 320 | # | ||
| 321 | # CONFIG_PM is not set | ||
| 322 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 323 | CONFIG_NET=y | ||
| 324 | |||
| 325 | # | ||
| 326 | # Networking options | ||
| 327 | # | ||
| 328 | CONFIG_PACKET=y | ||
| 329 | # CONFIG_PACKET_MMAP is not set | ||
| 330 | CONFIG_UNIX=y | ||
| 331 | # CONFIG_NET_KEY is not set | ||
| 332 | CONFIG_INET=y | ||
| 333 | # CONFIG_IP_MULTICAST is not set | ||
| 334 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 335 | CONFIG_IP_FIB_HASH=y | ||
| 336 | CONFIG_IP_PNP=y | ||
| 337 | # CONFIG_IP_PNP_DHCP is not set | ||
| 338 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 339 | # CONFIG_IP_PNP_RARP is not set | ||
| 340 | # CONFIG_NET_IPIP is not set | ||
| 341 | # CONFIG_NET_IPGRE is not set | ||
| 342 | # CONFIG_ARPD is not set | ||
| 343 | # CONFIG_SYN_COOKIES is not set | ||
| 344 | # CONFIG_INET_AH is not set | ||
| 345 | # CONFIG_INET_ESP is not set | ||
| 346 | # CONFIG_INET_IPCOMP is not set | ||
| 347 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 348 | # CONFIG_INET_TUNNEL is not set | ||
| 349 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 350 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 351 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 352 | CONFIG_INET_LRO=y | ||
| 353 | CONFIG_INET_DIAG=y | ||
| 354 | CONFIG_INET_TCP_DIAG=y | ||
| 355 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 356 | CONFIG_TCP_CONG_CUBIC=y | ||
| 357 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 358 | # CONFIG_TCP_MD5SIG is not set | ||
| 359 | # CONFIG_IPV6 is not set | ||
| 360 | # CONFIG_NETWORK_SECMARK is not set | ||
| 361 | # CONFIG_NETFILTER is not set | ||
| 362 | # CONFIG_IP_DCCP is not set | ||
| 363 | # CONFIG_IP_SCTP is not set | ||
| 364 | # CONFIG_TIPC is not set | ||
| 365 | # CONFIG_ATM is not set | ||
| 366 | # CONFIG_BRIDGE is not set | ||
| 367 | # CONFIG_NET_DSA is not set | ||
| 368 | # CONFIG_VLAN_8021Q is not set | ||
| 369 | # CONFIG_DECNET is not set | ||
| 370 | # CONFIG_LLC2 is not set | ||
| 371 | # CONFIG_IPX is not set | ||
| 372 | # CONFIG_ATALK is not set | ||
| 373 | # CONFIG_X25 is not set | ||
| 374 | # CONFIG_LAPB is not set | ||
| 375 | # CONFIG_ECONET is not set | ||
| 376 | # CONFIG_WAN_ROUTER is not set | ||
| 377 | # CONFIG_PHONET is not set | ||
| 378 | # CONFIG_IEEE802154 is not set | ||
| 379 | # CONFIG_NET_SCHED is not set | ||
| 380 | # CONFIG_DCB is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # Network testing | ||
| 384 | # | ||
| 385 | # CONFIG_NET_PKTGEN is not set | ||
| 386 | # CONFIG_HAMRADIO is not set | ||
| 387 | # CONFIG_CAN is not set | ||
| 388 | # CONFIG_IRDA is not set | ||
| 389 | # CONFIG_BT is not set | ||
| 390 | # CONFIG_AF_RXRPC is not set | ||
| 391 | # CONFIG_WIRELESS is not set | ||
| 392 | # CONFIG_WIMAX is not set | ||
| 393 | # CONFIG_RFKILL is not set | ||
| 394 | # CONFIG_NET_9P is not set | ||
| 395 | |||
| 396 | # | ||
| 397 | # Device Drivers | ||
| 398 | # | ||
| 399 | |||
| 400 | # | ||
| 401 | # Generic Driver Options | ||
| 402 | # | ||
| 403 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 404 | CONFIG_STANDALONE=y | ||
| 405 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 406 | CONFIG_FW_LOADER=y | ||
| 407 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 408 | CONFIG_EXTRA_FIRMWARE="" | ||
| 409 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 410 | # CONFIG_CONNECTOR is not set | ||
| 411 | CONFIG_MTD=y | ||
| 412 | # CONFIG_MTD_DEBUG is not set | ||
| 413 | # CONFIG_MTD_CONCAT is not set | ||
| 414 | CONFIG_MTD_PARTITIONS=y | ||
| 415 | # CONFIG_MTD_TESTS is not set | ||
| 416 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 417 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 418 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 419 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 420 | |||
| 421 | # | ||
| 422 | # User Modules And Translation Layers | ||
| 423 | # | ||
| 424 | CONFIG_MTD_CHAR=y | ||
| 425 | CONFIG_MTD_BLKDEVS=y | ||
| 426 | CONFIG_MTD_BLOCK=y | ||
| 427 | # CONFIG_FTL is not set | ||
| 428 | # CONFIG_NFTL is not set | ||
| 429 | # CONFIG_INFTL is not set | ||
| 430 | # CONFIG_RFD_FTL is not set | ||
| 431 | # CONFIG_SSFDC is not set | ||
| 432 | # CONFIG_MTD_OOPS is not set | ||
| 433 | |||
| 434 | # | ||
| 435 | # RAM/ROM/Flash chip drivers | ||
| 436 | # | ||
| 437 | CONFIG_MTD_CFI=y | ||
| 438 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 439 | CONFIG_MTD_GEN_PROBE=y | ||
| 440 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 441 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 442 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 443 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 444 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 445 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 446 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 447 | CONFIG_MTD_CFI_I1=y | ||
| 448 | CONFIG_MTD_CFI_I2=y | ||
| 449 | # CONFIG_MTD_CFI_I4 is not set | ||
| 450 | # CONFIG_MTD_CFI_I8 is not set | ||
| 451 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 452 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 453 | # CONFIG_MTD_CFI_STAA is not set | ||
| 454 | CONFIG_MTD_CFI_UTIL=y | ||
| 455 | CONFIG_MTD_RAM=y | ||
| 456 | # CONFIG_MTD_ROM is not set | ||
| 457 | # CONFIG_MTD_ABSENT is not set | ||
| 458 | |||
| 459 | # | ||
| 460 | # Mapping drivers for chip access | ||
| 461 | # | ||
| 462 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 463 | CONFIG_MTD_PHYSMAP=y | ||
| 464 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 465 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 466 | CONFIG_MTD_PLATRAM=y | ||
| 467 | |||
| 468 | # | ||
| 469 | # Self-contained MTD device drivers | ||
| 470 | # | ||
| 471 | # CONFIG_MTD_SLRAM is not set | ||
| 472 | # CONFIG_MTD_PHRAM is not set | ||
| 473 | # CONFIG_MTD_MTDRAM is not set | ||
| 474 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 475 | |||
| 476 | # | ||
| 477 | # Disk-On-Chip Device Drivers | ||
| 478 | # | ||
| 479 | # CONFIG_MTD_DOC2000 is not set | ||
| 480 | # CONFIG_MTD_DOC2001 is not set | ||
| 481 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 482 | CONFIG_MTD_NAND=y | ||
| 483 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 484 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 485 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 486 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 487 | CONFIG_MTD_NAND_IDS=y | ||
| 488 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 489 | CONFIG_MTD_NAND_ATMEL=y | ||
| 490 | # CONFIG_MTD_NAND_ATMEL_ECC_HW is not set | ||
| 491 | CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y | ||
| 492 | # CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set | ||
| 493 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 494 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 495 | # CONFIG_MTD_ALAUDA is not set | ||
| 496 | # CONFIG_MTD_ONENAND is not set | ||
| 497 | |||
| 498 | # | ||
| 499 | # LPDDR flash memory drivers | ||
| 500 | # | ||
| 501 | # CONFIG_MTD_LPDDR is not set | ||
| 502 | |||
| 503 | # | ||
| 504 | # UBI - Unsorted block images | ||
| 505 | # | ||
| 506 | # CONFIG_MTD_UBI is not set | ||
| 507 | # CONFIG_PARPORT is not set | ||
| 508 | CONFIG_BLK_DEV=y | ||
| 509 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 510 | CONFIG_BLK_DEV_LOOP=y | ||
| 511 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 512 | CONFIG_BLK_DEV_NBD=y | ||
| 513 | # CONFIG_BLK_DEV_UB is not set | ||
| 514 | CONFIG_BLK_DEV_RAM=y | ||
| 515 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 516 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 517 | # CONFIG_BLK_DEV_XIP is not set | ||
| 518 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 519 | # CONFIG_ATA_OVER_ETH is not set | ||
| 520 | # CONFIG_MG_DISK is not set | ||
| 521 | # CONFIG_MISC_DEVICES is not set | ||
| 522 | CONFIG_HAVE_IDE=y | ||
| 523 | # CONFIG_IDE is not set | ||
| 524 | |||
| 525 | # | ||
| 526 | # SCSI device support | ||
| 527 | # | ||
| 528 | # CONFIG_RAID_ATTRS is not set | ||
| 529 | CONFIG_SCSI=y | ||
| 530 | CONFIG_SCSI_DMA=y | ||
| 531 | # CONFIG_SCSI_TGT is not set | ||
| 532 | # CONFIG_SCSI_NETLINK is not set | ||
| 533 | CONFIG_SCSI_PROC_FS=y | ||
| 534 | |||
| 535 | # | ||
| 536 | # SCSI support type (disk, tape, CD-ROM) | ||
| 537 | # | ||
| 538 | CONFIG_BLK_DEV_SD=y | ||
| 539 | # CONFIG_CHR_DEV_ST is not set | ||
| 540 | # CONFIG_CHR_DEV_OSST is not set | ||
| 541 | # CONFIG_BLK_DEV_SR is not set | ||
| 542 | # CONFIG_CHR_DEV_SG is not set | ||
| 543 | # CONFIG_CHR_DEV_SCH is not set | ||
| 544 | CONFIG_SCSI_MULTI_LUN=y | ||
| 545 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 546 | # CONFIG_SCSI_LOGGING is not set | ||
| 547 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 548 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 549 | |||
| 550 | # | ||
| 551 | # SCSI Transports | ||
| 552 | # | ||
| 553 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 554 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 555 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 556 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 557 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 558 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 559 | # CONFIG_SCSI_DH is not set | ||
| 560 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 561 | # CONFIG_ATA is not set | ||
| 562 | # CONFIG_MD is not set | ||
| 563 | CONFIG_NETDEVICES=y | ||
| 564 | # CONFIG_DUMMY is not set | ||
| 565 | # CONFIG_BONDING is not set | ||
| 566 | # CONFIG_MACVLAN is not set | ||
| 567 | # CONFIG_EQUALIZER is not set | ||
| 568 | # CONFIG_TUN is not set | ||
| 569 | # CONFIG_VETH is not set | ||
| 570 | CONFIG_PHYLIB=y | ||
| 571 | |||
| 572 | # | ||
| 573 | # MII PHY device drivers | ||
| 574 | # | ||
| 575 | # CONFIG_MARVELL_PHY is not set | ||
| 576 | # CONFIG_DAVICOM_PHY is not set | ||
| 577 | # CONFIG_QSEMI_PHY is not set | ||
| 578 | # CONFIG_LXT_PHY is not set | ||
| 579 | # CONFIG_CICADA_PHY is not set | ||
| 580 | # CONFIG_VITESSE_PHY is not set | ||
| 581 | CONFIG_SMSC_PHY=y | ||
| 582 | # CONFIG_BROADCOM_PHY is not set | ||
| 583 | # CONFIG_ICPLUS_PHY is not set | ||
| 584 | # CONFIG_REALTEK_PHY is not set | ||
| 585 | # CONFIG_NATIONAL_PHY is not set | ||
| 586 | # CONFIG_STE10XP is not set | ||
| 587 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 588 | # CONFIG_FIXED_PHY is not set | ||
| 589 | # CONFIG_MDIO_BITBANG is not set | ||
| 590 | CONFIG_NET_ETHERNET=y | ||
| 591 | CONFIG_MII=y | ||
| 592 | CONFIG_MACB=y | ||
| 593 | # CONFIG_AX88796 is not set | ||
| 594 | # CONFIG_SMC91X is not set | ||
| 595 | # CONFIG_DM9000 is not set | ||
| 596 | # CONFIG_ETHOC is not set | ||
| 597 | # CONFIG_SMC911X is not set | ||
| 598 | # CONFIG_SMSC911X is not set | ||
| 599 | # CONFIG_DNET is not set | ||
| 600 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 601 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 602 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 603 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 604 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 605 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 606 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 607 | # CONFIG_B44 is not set | ||
| 608 | # CONFIG_KS8842 is not set | ||
| 609 | # CONFIG_NETDEV_1000 is not set | ||
| 610 | # CONFIG_NETDEV_10000 is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # Wireless LAN | ||
| 614 | # | ||
| 615 | # CONFIG_WLAN_PRE80211 is not set | ||
| 616 | # CONFIG_WLAN_80211 is not set | ||
| 617 | |||
| 618 | # | ||
| 619 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 620 | # | ||
| 621 | |||
| 622 | # | ||
| 623 | # USB Network Adapters | ||
| 624 | # | ||
| 625 | # CONFIG_USB_CATC is not set | ||
| 626 | # CONFIG_USB_KAWETH is not set | ||
| 627 | # CONFIG_USB_PEGASUS is not set | ||
| 628 | # CONFIG_USB_RTL8150 is not set | ||
| 629 | # CONFIG_USB_USBNET is not set | ||
| 630 | # CONFIG_WAN is not set | ||
| 631 | CONFIG_PPP=y | ||
| 632 | # CONFIG_PPP_MULTILINK is not set | ||
| 633 | # CONFIG_PPP_FILTER is not set | ||
| 634 | CONFIG_PPP_ASYNC=y | ||
| 635 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 636 | CONFIG_PPP_DEFLATE=y | ||
| 637 | CONFIG_PPP_BSDCOMP=y | ||
| 638 | # CONFIG_PPP_MPPE is not set | ||
| 639 | # CONFIG_PPPOE is not set | ||
| 640 | # CONFIG_PPPOL2TP is not set | ||
| 641 | # CONFIG_SLIP is not set | ||
| 642 | CONFIG_SLHC=y | ||
| 643 | # CONFIG_NETCONSOLE is not set | ||
| 644 | # CONFIG_NETPOLL is not set | ||
| 645 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 646 | # CONFIG_ISDN is not set | ||
| 647 | |||
| 648 | # | ||
| 649 | # Input device support | ||
| 650 | # | ||
| 651 | CONFIG_INPUT=y | ||
| 652 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 653 | # CONFIG_INPUT_POLLDEV is not set | ||
| 654 | |||
| 655 | # | ||
| 656 | # Userland interfaces | ||
| 657 | # | ||
| 658 | CONFIG_INPUT_MOUSEDEV=y | ||
| 659 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 660 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 661 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 662 | # CONFIG_INPUT_JOYDEV is not set | ||
| 663 | # CONFIG_INPUT_EVDEV is not set | ||
| 664 | # CONFIG_INPUT_EVBUG is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # Input Device Drivers | ||
| 668 | # | ||
| 669 | CONFIG_INPUT_KEYBOARD=y | ||
| 670 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 671 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 672 | CONFIG_KEYBOARD_GPIO=y | ||
| 673 | # CONFIG_KEYBOARD_MATRIX is not set | ||
| 674 | # CONFIG_KEYBOARD_LM8323 is not set | ||
| 675 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 676 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 677 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 678 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 679 | # CONFIG_INPUT_MOUSE is not set | ||
| 680 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 681 | # CONFIG_INPUT_TABLET is not set | ||
| 682 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 683 | # CONFIG_INPUT_MISC is not set | ||
| 684 | |||
| 685 | # | ||
| 686 | # Hardware I/O ports | ||
| 687 | # | ||
| 688 | # CONFIG_SERIO is not set | ||
| 689 | # CONFIG_GAMEPORT is not set | ||
| 690 | |||
| 691 | # | ||
| 692 | # Character devices | ||
| 693 | # | ||
| 694 | CONFIG_VT=y | ||
| 695 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 696 | CONFIG_VT_CONSOLE=y | ||
| 697 | CONFIG_HW_CONSOLE=y | ||
| 698 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 699 | CONFIG_DEVKMEM=y | ||
| 700 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Serial drivers | ||
| 704 | # | ||
| 705 | # CONFIG_SERIAL_8250 is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # Non-8250 serial port support | ||
| 709 | # | ||
| 710 | CONFIG_SERIAL_ATMEL=y | ||
| 711 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 712 | CONFIG_SERIAL_ATMEL_PDC=y | ||
| 713 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 714 | CONFIG_SERIAL_CORE=y | ||
| 715 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 716 | CONFIG_UNIX98_PTYS=y | ||
| 717 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 718 | CONFIG_LEGACY_PTYS=y | ||
| 719 | CONFIG_LEGACY_PTY_COUNT=32 | ||
| 720 | # CONFIG_IPMI_HANDLER is not set | ||
| 721 | # CONFIG_HW_RANDOM is not set | ||
| 722 | # CONFIG_R3964 is not set | ||
| 723 | # CONFIG_RAW_DRIVER is not set | ||
| 724 | # CONFIG_TCG_TPM is not set | ||
| 725 | CONFIG_I2C=y | ||
| 726 | CONFIG_I2C_BOARDINFO=y | ||
| 727 | CONFIG_I2C_CHARDEV=y | ||
| 728 | CONFIG_I2C_HELPER_AUTO=y | ||
| 729 | CONFIG_I2C_ALGOBIT=y | ||
| 730 | |||
| 731 | # | ||
| 732 | # I2C Hardware Bus support | ||
| 733 | # | ||
| 734 | |||
| 735 | # | ||
| 736 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 737 | # | ||
| 738 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 739 | CONFIG_I2C_GPIO=y | ||
| 740 | # CONFIG_I2C_OCORES is not set | ||
| 741 | # CONFIG_I2C_SIMTEC is not set | ||
| 742 | |||
| 743 | # | ||
| 744 | # External I2C/SMBus adapter drivers | ||
| 745 | # | ||
| 746 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 747 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 748 | # CONFIG_I2C_TINY_USB is not set | ||
| 749 | |||
| 750 | # | ||
| 751 | # Other I2C/SMBus bus drivers | ||
| 752 | # | ||
| 753 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 754 | # CONFIG_I2C_STUB is not set | ||
| 755 | |||
| 756 | # | ||
| 757 | # Miscellaneous I2C Chip support | ||
| 758 | # | ||
| 759 | # CONFIG_DS1682 is not set | ||
| 760 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 761 | # CONFIG_PCF8575 is not set | ||
| 762 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 763 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 764 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 765 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 766 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 767 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 768 | # CONFIG_SPI is not set | ||
| 769 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 770 | CONFIG_GPIOLIB=y | ||
| 771 | CONFIG_GPIO_SYSFS=y | ||
| 772 | |||
| 773 | # | ||
| 774 | # Memory mapped GPIO expanders: | ||
| 775 | # | ||
| 776 | |||
| 777 | # | ||
| 778 | # I2C GPIO expanders: | ||
| 779 | # | ||
| 780 | # CONFIG_GPIO_MAX732X is not set | ||
| 781 | # CONFIG_GPIO_PCA953X is not set | ||
| 782 | # CONFIG_GPIO_PCF857X is not set | ||
| 783 | |||
| 784 | # | ||
| 785 | # PCI GPIO expanders: | ||
| 786 | # | ||
| 787 | |||
| 788 | # | ||
| 789 | # SPI GPIO expanders: | ||
| 790 | # | ||
| 791 | # CONFIG_W1 is not set | ||
| 792 | # CONFIG_POWER_SUPPLY is not set | ||
| 793 | # CONFIG_HWMON is not set | ||
| 794 | # CONFIG_THERMAL is not set | ||
| 795 | # CONFIG_THERMAL_HWMON is not set | ||
| 796 | CONFIG_WATCHDOG=y | ||
| 797 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 798 | |||
| 799 | # | ||
| 800 | # Watchdog Device Drivers | ||
| 801 | # | ||
| 802 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 803 | CONFIG_AT91SAM9X_WATCHDOG=y | ||
| 804 | |||
| 805 | # | ||
| 806 | # USB-based Watchdog Cards | ||
| 807 | # | ||
| 808 | # CONFIG_USBPCWATCHDOG is not set | ||
| 809 | CONFIG_SSB_POSSIBLE=y | ||
| 810 | |||
| 811 | # | ||
| 812 | # Sonics Silicon Backplane | ||
| 813 | # | ||
| 814 | # CONFIG_SSB is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # Multifunction device drivers | ||
| 818 | # | ||
| 819 | # CONFIG_MFD_CORE is not set | ||
| 820 | # CONFIG_MFD_SM501 is not set | ||
| 821 | # CONFIG_MFD_ASIC3 is not set | ||
| 822 | # CONFIG_HTC_EGPIO is not set | ||
| 823 | # CONFIG_HTC_PASIC3 is not set | ||
| 824 | # CONFIG_TPS65010 is not set | ||
| 825 | # CONFIG_TWL4030_CORE is not set | ||
| 826 | # CONFIG_MFD_TMIO is not set | ||
| 827 | # CONFIG_MFD_T7L66XB is not set | ||
| 828 | # CONFIG_MFD_TC6387XB is not set | ||
| 829 | # CONFIG_MFD_TC6393XB is not set | ||
| 830 | # CONFIG_PMIC_DA903X is not set | ||
| 831 | # CONFIG_MFD_WM8400 is not set | ||
| 832 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 833 | # CONFIG_MFD_PCF50633 is not set | ||
| 834 | # CONFIG_AB3100_CORE is not set | ||
| 835 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 836 | |||
| 837 | # | ||
| 838 | # Graphics support | ||
| 839 | # | ||
| 840 | # CONFIG_VGASTATE is not set | ||
| 841 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 842 | # CONFIG_FB is not set | ||
| 843 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 844 | |||
| 845 | # | ||
| 846 | # Display device support | ||
| 847 | # | ||
| 848 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 849 | |||
| 850 | # | ||
| 851 | # Console display driver support | ||
| 852 | # | ||
| 853 | # CONFIG_VGA_CONSOLE is not set | ||
| 854 | CONFIG_DUMMY_CONSOLE=y | ||
| 855 | # CONFIG_SOUND is not set | ||
| 856 | # CONFIG_HID_SUPPORT is not set | ||
| 857 | CONFIG_USB_SUPPORT=y | ||
| 858 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 859 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 860 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 861 | CONFIG_USB=y | ||
| 862 | # CONFIG_USB_DEBUG is not set | ||
| 863 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 864 | |||
| 865 | # | ||
| 866 | # Miscellaneous USB options | ||
| 867 | # | ||
| 868 | # CONFIG_USB_DEVICEFS is not set | ||
| 869 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 870 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 871 | # CONFIG_USB_OTG is not set | ||
| 872 | # CONFIG_USB_MON is not set | ||
| 873 | # CONFIG_USB_WUSB is not set | ||
| 874 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 875 | |||
| 876 | # | ||
| 877 | # USB Host Controller Drivers | ||
| 878 | # | ||
| 879 | # CONFIG_USB_C67X00_HCD is not set | ||
| 880 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 881 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 882 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 883 | CONFIG_USB_OHCI_HCD=y | ||
| 884 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 885 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 886 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 887 | # CONFIG_USB_SL811_HCD is not set | ||
| 888 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 889 | # CONFIG_USB_HWA_HCD is not set | ||
| 890 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 891 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 892 | |||
| 893 | # | ||
| 894 | # USB Device Class drivers | ||
| 895 | # | ||
| 896 | # CONFIG_USB_ACM is not set | ||
| 897 | # CONFIG_USB_PRINTER is not set | ||
| 898 | # CONFIG_USB_WDM is not set | ||
| 899 | # CONFIG_USB_TMC is not set | ||
| 900 | |||
| 901 | # | ||
| 902 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 903 | # | ||
| 904 | |||
| 905 | # | ||
| 906 | # also be needed; see USB_STORAGE Help for more info | ||
| 907 | # | ||
| 908 | CONFIG_USB_STORAGE=y | ||
| 909 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 910 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 911 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 912 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 913 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 914 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 915 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 916 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 917 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 918 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 919 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 920 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 921 | # CONFIG_USB_LIBUSUAL is not set | ||
| 922 | |||
| 923 | # | ||
| 924 | # USB Imaging devices | ||
| 925 | # | ||
| 926 | # CONFIG_USB_MDC800 is not set | ||
| 927 | # CONFIG_USB_MICROTEK is not set | ||
| 928 | |||
| 929 | # | ||
| 930 | # USB port drivers | ||
| 931 | # | ||
| 932 | # CONFIG_USB_SERIAL is not set | ||
| 933 | |||
| 934 | # | ||
| 935 | # USB Miscellaneous drivers | ||
| 936 | # | ||
| 937 | # CONFIG_USB_EMI62 is not set | ||
| 938 | # CONFIG_USB_EMI26 is not set | ||
| 939 | # CONFIG_USB_ADUTUX is not set | ||
| 940 | # CONFIG_USB_SEVSEG is not set | ||
| 941 | # CONFIG_USB_RIO500 is not set | ||
| 942 | # CONFIG_USB_LEGOTOWER is not set | ||
| 943 | # CONFIG_USB_LCD is not set | ||
| 944 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 945 | # CONFIG_USB_LED is not set | ||
| 946 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 947 | # CONFIG_USB_CYTHERM is not set | ||
| 948 | # CONFIG_USB_IDMOUSE is not set | ||
| 949 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 950 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 951 | # CONFIG_USB_LD is not set | ||
| 952 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 953 | # CONFIG_USB_IOWARRIOR is not set | ||
| 954 | # CONFIG_USB_ISIGHTFW is not set | ||
| 955 | # CONFIG_USB_VST is not set | ||
| 956 | CONFIG_USB_GADGET=y | ||
| 957 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 958 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 959 | CONFIG_USB_GADGET_SELECTED=y | ||
| 960 | CONFIG_USB_GADGET_AT91=y | ||
| 961 | CONFIG_USB_AT91=y | ||
| 962 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 963 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 964 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 965 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 966 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 967 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 968 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 969 | # CONFIG_USB_GADGET_IMX is not set | ||
| 970 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 971 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 972 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 973 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 974 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 975 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 976 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 977 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 978 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 979 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 980 | # CONFIG_USB_ZERO is not set | ||
| 981 | # CONFIG_USB_AUDIO is not set | ||
| 982 | CONFIG_USB_ETH=y | ||
| 983 | CONFIG_USB_ETH_RNDIS=y | ||
| 984 | # CONFIG_USB_GADGETFS is not set | ||
| 985 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 986 | # CONFIG_USB_G_SERIAL is not set | ||
| 987 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 988 | # CONFIG_USB_G_PRINTER is not set | ||
| 989 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 990 | |||
| 991 | # | ||
| 992 | # OTG and related infrastructure | ||
| 993 | # | ||
| 994 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 995 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 996 | CONFIG_MMC=y | ||
| 997 | # CONFIG_MMC_DEBUG is not set | ||
| 998 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 999 | |||
| 1000 | # | ||
| 1001 | # MMC/SD/SDIO Card Drivers | ||
| 1002 | # | ||
| 1003 | CONFIG_MMC_BLOCK=y | ||
| 1004 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1005 | # CONFIG_SDIO_UART is not set | ||
| 1006 | # CONFIG_MMC_TEST is not set | ||
| 1007 | |||
| 1008 | # | ||
| 1009 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1010 | # | ||
| 1011 | # CONFIG_MMC_SDHCI is not set | ||
| 1012 | CONFIG_MMC_AT91=y | ||
| 1013 | # CONFIG_MEMSTICK is not set | ||
| 1014 | # CONFIG_ACCESSIBILITY is not set | ||
| 1015 | CONFIG_NEW_LEDS=y | ||
| 1016 | CONFIG_LEDS_CLASS=y | ||
| 1017 | |||
| 1018 | # | ||
| 1019 | # LED drivers | ||
| 1020 | # | ||
| 1021 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1022 | CONFIG_LEDS_GPIO=y | ||
| 1023 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1024 | # CONFIG_LEDS_LP3944 is not set | ||
| 1025 | # CONFIG_LEDS_PCA955X is not set | ||
| 1026 | # CONFIG_LEDS_BD2802 is not set | ||
| 1027 | |||
| 1028 | # | ||
| 1029 | # LED Triggers | ||
| 1030 | # | ||
| 1031 | CONFIG_LEDS_TRIGGERS=y | ||
| 1032 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1033 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1034 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1035 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1036 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1037 | |||
| 1038 | # | ||
| 1039 | # iptables trigger is under Netfilter config (LED target) | ||
| 1040 | # | ||
| 1041 | CONFIG_RTC_LIB=y | ||
| 1042 | CONFIG_RTC_CLASS=y | ||
| 1043 | # CONFIG_RTC_HCTOSYS is not set | ||
| 1044 | # CONFIG_RTC_DEBUG is not set | ||
| 1045 | |||
| 1046 | # | ||
| 1047 | # RTC interfaces | ||
| 1048 | # | ||
| 1049 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1050 | CONFIG_RTC_INTF_PROC=y | ||
| 1051 | CONFIG_RTC_INTF_DEV=y | ||
| 1052 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1053 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1054 | |||
| 1055 | # | ||
| 1056 | # I2C RTC drivers | ||
| 1057 | # | ||
| 1058 | CONFIG_RTC_DRV_DS1307=y | ||
| 1059 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1060 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1061 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1062 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1063 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1064 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1065 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1066 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1067 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1068 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1069 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1070 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1071 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1072 | |||
| 1073 | # | ||
| 1074 | # SPI RTC drivers | ||
| 1075 | # | ||
| 1076 | |||
| 1077 | # | ||
| 1078 | # Platform RTC drivers | ||
| 1079 | # | ||
| 1080 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1081 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1082 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1083 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1084 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1085 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1086 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1087 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1088 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1089 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1090 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1091 | |||
| 1092 | # | ||
| 1093 | # on-CPU RTC drivers | ||
| 1094 | # | ||
| 1095 | # CONFIG_RTC_DRV_AT91SAM9 is not set | ||
| 1096 | # CONFIG_DMADEVICES is not set | ||
| 1097 | # CONFIG_AUXDISPLAY is not set | ||
| 1098 | # CONFIG_REGULATOR is not set | ||
| 1099 | # CONFIG_UIO is not set | ||
| 1100 | # CONFIG_STAGING is not set | ||
| 1101 | |||
| 1102 | # | ||
| 1103 | # File systems | ||
| 1104 | # | ||
| 1105 | CONFIG_EXT2_FS=y | ||
| 1106 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1107 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1108 | CONFIG_EXT3_FS=y | ||
| 1109 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1110 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1111 | # CONFIG_EXT4_FS is not set | ||
| 1112 | CONFIG_JBD=y | ||
| 1113 | # CONFIG_REISERFS_FS is not set | ||
| 1114 | # CONFIG_JFS_FS is not set | ||
| 1115 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1116 | # CONFIG_XFS_FS is not set | ||
| 1117 | # CONFIG_GFS2_FS is not set | ||
| 1118 | # CONFIG_OCFS2_FS is not set | ||
| 1119 | # CONFIG_BTRFS_FS is not set | ||
| 1120 | CONFIG_FILE_LOCKING=y | ||
| 1121 | CONFIG_FSNOTIFY=y | ||
| 1122 | CONFIG_DNOTIFY=y | ||
| 1123 | CONFIG_INOTIFY=y | ||
| 1124 | CONFIG_INOTIFY_USER=y | ||
| 1125 | # CONFIG_QUOTA is not set | ||
| 1126 | # CONFIG_AUTOFS_FS is not set | ||
| 1127 | CONFIG_AUTOFS4_FS=y | ||
| 1128 | # CONFIG_FUSE_FS is not set | ||
| 1129 | |||
| 1130 | # | ||
| 1131 | # Caches | ||
| 1132 | # | ||
| 1133 | # CONFIG_FSCACHE is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # CD-ROM/DVD Filesystems | ||
| 1137 | # | ||
| 1138 | # CONFIG_ISO9660_FS is not set | ||
| 1139 | # CONFIG_UDF_FS is not set | ||
| 1140 | |||
| 1141 | # | ||
| 1142 | # DOS/FAT/NT Filesystems | ||
| 1143 | # | ||
| 1144 | CONFIG_FAT_FS=y | ||
| 1145 | CONFIG_MSDOS_FS=y | ||
| 1146 | CONFIG_VFAT_FS=y | ||
| 1147 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1148 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1149 | # CONFIG_NTFS_FS is not set | ||
| 1150 | |||
| 1151 | # | ||
| 1152 | # Pseudo filesystems | ||
| 1153 | # | ||
| 1154 | CONFIG_PROC_FS=y | ||
| 1155 | CONFIG_PROC_SYSCTL=y | ||
| 1156 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1157 | CONFIG_SYSFS=y | ||
| 1158 | CONFIG_TMPFS=y | ||
| 1159 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1160 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1161 | # CONFIG_CONFIGFS_FS is not set | ||
| 1162 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1163 | # CONFIG_ADFS_FS is not set | ||
| 1164 | # CONFIG_AFFS_FS is not set | ||
| 1165 | # CONFIG_HFS_FS is not set | ||
| 1166 | # CONFIG_HFSPLUS_FS is not set | ||
| 1167 | # CONFIG_BEFS_FS is not set | ||
| 1168 | # CONFIG_BFS_FS is not set | ||
| 1169 | # CONFIG_EFS_FS is not set | ||
| 1170 | CONFIG_JFFS2_FS=y | ||
| 1171 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1172 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1173 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1174 | CONFIG_JFFS2_SUMMARY=y | ||
| 1175 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1176 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1177 | CONFIG_JFFS2_ZLIB=y | ||
| 1178 | # CONFIG_JFFS2_LZO is not set | ||
| 1179 | CONFIG_JFFS2_RTIME=y | ||
| 1180 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1181 | CONFIG_CRAMFS=y | ||
| 1182 | # CONFIG_SQUASHFS is not set | ||
| 1183 | # CONFIG_VXFS_FS is not set | ||
| 1184 | CONFIG_MINIX_FS=y | ||
| 1185 | # CONFIG_OMFS_FS is not set | ||
| 1186 | # CONFIG_HPFS_FS is not set | ||
| 1187 | # CONFIG_QNX4FS_FS is not set | ||
| 1188 | # CONFIG_ROMFS_FS is not set | ||
| 1189 | # CONFIG_SYSV_FS is not set | ||
| 1190 | # CONFIG_UFS_FS is not set | ||
| 1191 | # CONFIG_NILFS2_FS is not set | ||
| 1192 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1193 | CONFIG_NFS_FS=y | ||
| 1194 | CONFIG_NFS_V3=y | ||
| 1195 | # CONFIG_NFS_V3_ACL is not set | ||
| 1196 | # CONFIG_NFS_V4 is not set | ||
| 1197 | CONFIG_ROOT_NFS=y | ||
| 1198 | # CONFIG_NFSD is not set | ||
| 1199 | CONFIG_LOCKD=y | ||
| 1200 | CONFIG_LOCKD_V4=y | ||
| 1201 | CONFIG_NFS_COMMON=y | ||
| 1202 | CONFIG_SUNRPC=y | ||
| 1203 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1204 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1205 | # CONFIG_SMB_FS is not set | ||
| 1206 | # CONFIG_CIFS is not set | ||
| 1207 | # CONFIG_NCP_FS is not set | ||
| 1208 | # CONFIG_CODA_FS is not set | ||
| 1209 | # CONFIG_AFS_FS is not set | ||
| 1210 | |||
| 1211 | # | ||
| 1212 | # Partition Types | ||
| 1213 | # | ||
| 1214 | CONFIG_PARTITION_ADVANCED=y | ||
| 1215 | # CONFIG_ACORN_PARTITION is not set | ||
| 1216 | # CONFIG_OSF_PARTITION is not set | ||
| 1217 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1218 | # CONFIG_ATARI_PARTITION is not set | ||
| 1219 | # CONFIG_MAC_PARTITION is not set | ||
| 1220 | CONFIG_MSDOS_PARTITION=y | ||
| 1221 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1222 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1223 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1224 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1225 | # CONFIG_LDM_PARTITION is not set | ||
| 1226 | # CONFIG_SGI_PARTITION is not set | ||
| 1227 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1228 | # CONFIG_SUN_PARTITION is not set | ||
| 1229 | # CONFIG_KARMA_PARTITION is not set | ||
| 1230 | # CONFIG_EFI_PARTITION is not set | ||
| 1231 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1232 | CONFIG_NLS=y | ||
| 1233 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1234 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1235 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1236 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1237 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1238 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1239 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1240 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1241 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1242 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1243 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1244 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1245 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1246 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1247 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1248 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1249 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1250 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1251 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1252 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1253 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1254 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1255 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1256 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1257 | # CONFIG_NLS_ASCII is not set | ||
| 1258 | CONFIG_NLS_ISO8859_1=y | ||
| 1259 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1260 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1261 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1262 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1263 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1264 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1265 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1266 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1267 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1268 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1269 | # CONFIG_NLS_KOI8_R is not set | ||
| 1270 | # CONFIG_NLS_KOI8_U is not set | ||
| 1271 | CONFIG_NLS_UTF8=y | ||
| 1272 | # CONFIG_DLM is not set | ||
| 1273 | |||
| 1274 | # | ||
| 1275 | # Kernel hacking | ||
| 1276 | # | ||
| 1277 | # CONFIG_PRINTK_TIME is not set | ||
| 1278 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1279 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1280 | CONFIG_FRAME_WARN=1024 | ||
| 1281 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1282 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1283 | # CONFIG_DEBUG_FS is not set | ||
| 1284 | # CONFIG_HEADERS_CHECK is not set | ||
| 1285 | # CONFIG_DEBUG_KERNEL is not set | ||
| 1286 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1287 | # CONFIG_SLUB_STATS is not set | ||
| 1288 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1289 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1290 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1291 | # CONFIG_LATENCYTOP is not set | ||
| 1292 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1293 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1294 | CONFIG_TRACING_SUPPORT=y | ||
| 1295 | # CONFIG_FTRACE is not set | ||
| 1296 | # CONFIG_SAMPLES is not set | ||
| 1297 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1298 | CONFIG_ARM_UNWIND=y | ||
| 1299 | # CONFIG_DEBUG_USER is not set | ||
| 1300 | |||
| 1301 | # | ||
| 1302 | # Security options | ||
| 1303 | # | ||
| 1304 | # CONFIG_KEYS is not set | ||
| 1305 | # CONFIG_SECURITY is not set | ||
| 1306 | # CONFIG_SECURITYFS is not set | ||
| 1307 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1308 | # CONFIG_CRYPTO is not set | ||
| 1309 | # CONFIG_BINARY_PRINTF is not set | ||
| 1310 | |||
| 1311 | # | ||
| 1312 | # Library routines | ||
| 1313 | # | ||
| 1314 | CONFIG_BITREVERSE=y | ||
| 1315 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1316 | CONFIG_CRC_CCITT=y | ||
| 1317 | # CONFIG_CRC16 is not set | ||
| 1318 | # CONFIG_CRC_T10DIF is not set | ||
| 1319 | # CONFIG_CRC_ITU_T is not set | ||
| 1320 | CONFIG_CRC32=y | ||
| 1321 | # CONFIG_CRC7 is not set | ||
| 1322 | # CONFIG_LIBCRC32C is not set | ||
| 1323 | CONFIG_ZLIB_INFLATE=y | ||
| 1324 | CONFIG_ZLIB_DEFLATE=y | ||
| 1325 | CONFIG_HAS_IOMEM=y | ||
| 1326 | CONFIG_HAS_IOPORT=y | ||
| 1327 | CONFIG_HAS_DMA=y | ||
| 1328 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/configs/cpuat91_defconfig b/arch/arm/configs/cpuat91_defconfig new file mode 100644 index 000000000000..4901827253fb --- /dev/null +++ b/arch/arm/configs/cpuat91_defconfig | |||
| @@ -0,0 +1,1316 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.31-rc3 | ||
| 4 | # Tue Jul 14 14:45:01 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | CONFIG_GENERIC_HARDIRQS=y | ||
| 13 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 14 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 18 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 19 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 20 | CONFIG_GENERIC_HWEIGHT=y | ||
| 21 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 22 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 23 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 24 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 25 | CONFIG_CONSTRUCTORS=y | ||
| 26 | |||
| 27 | # | ||
| 28 | # General setup | ||
| 29 | # | ||
| 30 | CONFIG_EXPERIMENTAL=y | ||
| 31 | CONFIG_BROKEN_ON_SMP=y | ||
| 32 | CONFIG_LOCK_KERNEL=y | ||
| 33 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 34 | CONFIG_LOCALVERSION="" | ||
| 35 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 36 | # CONFIG_SWAP is not set | ||
| 37 | CONFIG_SYSVIPC=y | ||
| 38 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 39 | # CONFIG_POSIX_MQUEUE is not set | ||
| 40 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 41 | # CONFIG_TASKSTATS is not set | ||
| 42 | # CONFIG_AUDIT is not set | ||
| 43 | |||
| 44 | # | ||
| 45 | # RCU Subsystem | ||
| 46 | # | ||
| 47 | CONFIG_CLASSIC_RCU=y | ||
| 48 | # CONFIG_TREE_RCU is not set | ||
| 49 | # CONFIG_PREEMPT_RCU is not set | ||
| 50 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 51 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 52 | # CONFIG_IKCONFIG is not set | ||
| 53 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 54 | # CONFIG_GROUP_SCHED is not set | ||
| 55 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | ||
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_IPC_NS is not set | ||
| 62 | # CONFIG_USER_NS is not set | ||
| 63 | # CONFIG_PID_NS is not set | ||
| 64 | # CONFIG_NET_NS is not set | ||
| 65 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 66 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 67 | CONFIG_SYSCTL=y | ||
| 68 | CONFIG_ANON_INODES=y | ||
| 69 | # CONFIG_EMBEDDED is not set | ||
| 70 | CONFIG_UID16=y | ||
| 71 | CONFIG_SYSCTL_SYSCALL=y | ||
| 72 | CONFIG_KALLSYMS=y | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | |||
| 87 | # | ||
| 88 | # Performance Counters | ||
| 89 | # | ||
| 90 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 91 | CONFIG_SLUB_DEBUG=y | ||
| 92 | # CONFIG_STRIP_ASM_SYMS is not set | ||
| 93 | CONFIG_COMPAT_BRK=y | ||
| 94 | # CONFIG_SLAB is not set | ||
| 95 | CONFIG_SLUB=y | ||
| 96 | # CONFIG_SLOB is not set | ||
| 97 | # CONFIG_PROFILING is not set | ||
| 98 | # CONFIG_MARKERS is not set | ||
| 99 | CONFIG_HAVE_OPROFILE=y | ||
| 100 | # CONFIG_KPROBES is not set | ||
| 101 | CONFIG_HAVE_KPROBES=y | ||
| 102 | CONFIG_HAVE_KRETPROBES=y | ||
| 103 | CONFIG_HAVE_CLK=y | ||
| 104 | |||
| 105 | # | ||
| 106 | # GCOV-based kernel profiling | ||
| 107 | # | ||
| 108 | # CONFIG_SLOW_WORK is not set | ||
| 109 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 110 | CONFIG_SLABINFO=y | ||
| 111 | CONFIG_RT_MUTEXES=y | ||
| 112 | CONFIG_BASE_SMALL=0 | ||
| 113 | CONFIG_MODULES=y | ||
| 114 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 115 | CONFIG_MODULE_UNLOAD=y | ||
| 116 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 117 | # CONFIG_MODVERSIONS is not set | ||
| 118 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 119 | CONFIG_BLOCK=y | ||
| 120 | CONFIG_LBDAF=y | ||
| 121 | # CONFIG_BLK_DEV_BSG is not set | ||
| 122 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 123 | |||
| 124 | # | ||
| 125 | # IO Schedulers | ||
| 126 | # | ||
| 127 | CONFIG_IOSCHED_NOOP=y | ||
| 128 | # CONFIG_IOSCHED_AS is not set | ||
| 129 | CONFIG_IOSCHED_DEADLINE=y | ||
| 130 | # CONFIG_IOSCHED_CFQ is not set | ||
| 131 | # CONFIG_DEFAULT_AS is not set | ||
| 132 | CONFIG_DEFAULT_DEADLINE=y | ||
| 133 | # CONFIG_DEFAULT_CFQ is not set | ||
| 134 | # CONFIG_DEFAULT_NOOP is not set | ||
| 135 | CONFIG_DEFAULT_IOSCHED="deadline" | ||
| 136 | # CONFIG_FREEZER is not set | ||
| 137 | |||
| 138 | # | ||
| 139 | # System Type | ||
| 140 | # | ||
| 141 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 142 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 143 | # CONFIG_ARCH_REALVIEW is not set | ||
| 144 | # CONFIG_ARCH_VERSATILE is not set | ||
| 145 | CONFIG_ARCH_AT91=y | ||
| 146 | # CONFIG_ARCH_CLPS711X is not set | ||
| 147 | # CONFIG_ARCH_GEMINI is not set | ||
| 148 | # CONFIG_ARCH_EBSA110 is not set | ||
| 149 | # CONFIG_ARCH_EP93XX is not set | ||
| 150 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 151 | # CONFIG_ARCH_MXC is not set | ||
| 152 | # CONFIG_ARCH_STMP3XXX is not set | ||
| 153 | # CONFIG_ARCH_NETX is not set | ||
| 154 | # CONFIG_ARCH_H720X is not set | ||
| 155 | # CONFIG_ARCH_IOP13XX is not set | ||
| 156 | # CONFIG_ARCH_IOP32X is not set | ||
| 157 | # CONFIG_ARCH_IOP33X is not set | ||
| 158 | # CONFIG_ARCH_IXP23XX is not set | ||
| 159 | # CONFIG_ARCH_IXP2000 is not set | ||
| 160 | # CONFIG_ARCH_IXP4XX is not set | ||
| 161 | # CONFIG_ARCH_L7200 is not set | ||
| 162 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 163 | # CONFIG_ARCH_LOKI is not set | ||
| 164 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 165 | # CONFIG_ARCH_ORION5X is not set | ||
| 166 | # CONFIG_ARCH_MMP is not set | ||
| 167 | # CONFIG_ARCH_KS8695 is not set | ||
| 168 | # CONFIG_ARCH_NS9XXX is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 170 | # CONFIG_ARCH_PNX4008 is not set | ||
| 171 | # CONFIG_ARCH_PXA is not set | ||
| 172 | # CONFIG_ARCH_MSM is not set | ||
| 173 | # CONFIG_ARCH_RPC is not set | ||
| 174 | # CONFIG_ARCH_SA1100 is not set | ||
| 175 | # CONFIG_ARCH_S3C2410 is not set | ||
| 176 | # CONFIG_ARCH_S3C64XX is not set | ||
| 177 | # CONFIG_ARCH_SHARK is not set | ||
| 178 | # CONFIG_ARCH_LH7A40X is not set | ||
| 179 | # CONFIG_ARCH_U300 is not set | ||
| 180 | # CONFIG_ARCH_DAVINCI is not set | ||
| 181 | # CONFIG_ARCH_OMAP is not set | ||
| 182 | |||
| 183 | # | ||
| 184 | # Atmel AT91 System-on-Chip | ||
| 185 | # | ||
| 186 | CONFIG_ARCH_AT91RM9200=y | ||
| 187 | # CONFIG_ARCH_AT91SAM9260 is not set | ||
| 188 | # CONFIG_ARCH_AT91SAM9261 is not set | ||
| 189 | # CONFIG_ARCH_AT91SAM9263 is not set | ||
| 190 | # CONFIG_ARCH_AT91SAM9RL is not set | ||
| 191 | # CONFIG_ARCH_AT91SAM9G20 is not set | ||
| 192 | # CONFIG_ARCH_AT91CAP9 is not set | ||
| 193 | # CONFIG_ARCH_AT91X40 is not set | ||
| 194 | CONFIG_AT91_PMC_UNIT=y | ||
| 195 | |||
| 196 | # | ||
| 197 | # AT91RM9200 Board Type | ||
| 198 | # | ||
| 199 | # CONFIG_MACH_ONEARM is not set | ||
| 200 | # CONFIG_ARCH_AT91RM9200DK is not set | ||
| 201 | # CONFIG_MACH_AT91RM9200EK is not set | ||
| 202 | # CONFIG_MACH_CSB337 is not set | ||
| 203 | # CONFIG_MACH_CSB637 is not set | ||
| 204 | # CONFIG_MACH_CARMEVA is not set | ||
| 205 | # CONFIG_MACH_ATEB9200 is not set | ||
| 206 | # CONFIG_MACH_KB9200 is not set | ||
| 207 | # CONFIG_MACH_PICOTUX2XX is not set | ||
| 208 | # CONFIG_MACH_KAFA is not set | ||
| 209 | # CONFIG_MACH_ECBAT91 is not set | ||
| 210 | # CONFIG_MACH_YL9200 is not set | ||
| 211 | CONFIG_MACH_CPUAT91=y | ||
| 212 | |||
| 213 | # | ||
| 214 | # AT91 Board Options | ||
| 215 | # | ||
| 216 | |||
| 217 | # | ||
| 218 | # AT91 Feature Selections | ||
| 219 | # | ||
| 220 | # CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set | ||
| 221 | CONFIG_AT91_TIMER_HZ=100 | ||
| 222 | CONFIG_AT91_EARLY_DBGU=y | ||
| 223 | # CONFIG_AT91_EARLY_USART0 is not set | ||
| 224 | # CONFIG_AT91_EARLY_USART1 is not set | ||
| 225 | # CONFIG_AT91_EARLY_USART2 is not set | ||
| 226 | # CONFIG_AT91_EARLY_USART3 is not set | ||
| 227 | # CONFIG_AT91_EARLY_USART4 is not set | ||
| 228 | # CONFIG_AT91_EARLY_USART5 is not set | ||
| 229 | |||
| 230 | # | ||
| 231 | # Processor Type | ||
| 232 | # | ||
| 233 | CONFIG_CPU_32=y | ||
| 234 | CONFIG_CPU_ARM920T=y | ||
| 235 | CONFIG_CPU_32v4T=y | ||
| 236 | CONFIG_CPU_ABRT_EV4T=y | ||
| 237 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 238 | CONFIG_CPU_CACHE_V4WT=y | ||
| 239 | CONFIG_CPU_CACHE_VIVT=y | ||
| 240 | CONFIG_CPU_COPY_V4WB=y | ||
| 241 | CONFIG_CPU_TLB_V4WBI=y | ||
| 242 | CONFIG_CPU_CP15=y | ||
| 243 | CONFIG_CPU_CP15_MMU=y | ||
| 244 | |||
| 245 | # | ||
| 246 | # Processor Features | ||
| 247 | # | ||
| 248 | # CONFIG_ARM_THUMB is not set | ||
| 249 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 250 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 251 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 252 | |||
| 253 | # | ||
| 254 | # Bus support | ||
| 255 | # | ||
| 256 | # CONFIG_PCI_SYSCALL is not set | ||
| 257 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 258 | # CONFIG_PCCARD is not set | ||
| 259 | |||
| 260 | # | ||
| 261 | # Kernel Features | ||
| 262 | # | ||
| 263 | # CONFIG_NO_HZ is not set | ||
| 264 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 265 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 266 | CONFIG_VMSPLIT_3G=y | ||
| 267 | # CONFIG_VMSPLIT_2G is not set | ||
| 268 | # CONFIG_VMSPLIT_1G is not set | ||
| 269 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 270 | CONFIG_PREEMPT=y | ||
| 271 | CONFIG_HZ=100 | ||
| 272 | # CONFIG_AEABI is not set | ||
| 273 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 274 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 275 | # CONFIG_HIGHMEM is not set | ||
| 276 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 277 | CONFIG_FLATMEM_MANUAL=y | ||
| 278 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 279 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 280 | CONFIG_FLATMEM=y | ||
| 281 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 282 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 283 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 284 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 285 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 286 | CONFIG_VIRT_TO_BUS=y | ||
| 287 | CONFIG_HAVE_MLOCK=y | ||
| 288 | CONFIG_HAVE_MLOCKED_PAGE_BIT=y | ||
| 289 | CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 | ||
| 290 | # CONFIG_LEDS is not set | ||
| 291 | CONFIG_ALIGNMENT_TRAP=y | ||
| 292 | # CONFIG_UACCESS_WITH_MEMCPY is not set | ||
| 293 | |||
| 294 | # | ||
| 295 | # Boot options | ||
| 296 | # | ||
| 297 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 298 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 299 | CONFIG_CMDLINE="" | ||
| 300 | # CONFIG_XIP_KERNEL is not set | ||
| 301 | # CONFIG_KEXEC is not set | ||
| 302 | |||
| 303 | # | ||
| 304 | # CPU Power Management | ||
| 305 | # | ||
| 306 | # CONFIG_CPU_IDLE is not set | ||
| 307 | |||
| 308 | # | ||
| 309 | # Floating point emulation | ||
| 310 | # | ||
| 311 | |||
| 312 | # | ||
| 313 | # At least one emulation must be selected | ||
| 314 | # | ||
| 315 | # CONFIG_FPE_NWFPE is not set | ||
| 316 | # CONFIG_FPE_FASTFPE is not set | ||
| 317 | |||
| 318 | # | ||
| 319 | # Userspace binary formats | ||
| 320 | # | ||
| 321 | CONFIG_BINFMT_ELF=y | ||
| 322 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 323 | CONFIG_HAVE_AOUT=y | ||
| 324 | # CONFIG_BINFMT_AOUT is not set | ||
| 325 | # CONFIG_BINFMT_MISC is not set | ||
| 326 | # CONFIG_ARTHUR is not set | ||
| 327 | |||
| 328 | # | ||
| 329 | # Power management options | ||
| 330 | # | ||
| 331 | # CONFIG_PM is not set | ||
| 332 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 333 | CONFIG_NET=y | ||
| 334 | |||
| 335 | # | ||
| 336 | # Networking options | ||
| 337 | # | ||
| 338 | CONFIG_PACKET=y | ||
| 339 | # CONFIG_PACKET_MMAP is not set | ||
| 340 | CONFIG_UNIX=y | ||
| 341 | # CONFIG_NET_KEY is not set | ||
| 342 | CONFIG_INET=y | ||
| 343 | # CONFIG_IP_MULTICAST is not set | ||
| 344 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 345 | CONFIG_IP_FIB_HASH=y | ||
| 346 | CONFIG_IP_PNP=y | ||
| 347 | # CONFIG_IP_PNP_DHCP is not set | ||
| 348 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 349 | # CONFIG_IP_PNP_RARP is not set | ||
| 350 | # CONFIG_NET_IPIP is not set | ||
| 351 | # CONFIG_NET_IPGRE is not set | ||
| 352 | # CONFIG_ARPD is not set | ||
| 353 | # CONFIG_SYN_COOKIES is not set | ||
| 354 | # CONFIG_INET_AH is not set | ||
| 355 | # CONFIG_INET_ESP is not set | ||
| 356 | # CONFIG_INET_IPCOMP is not set | ||
| 357 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 358 | # CONFIG_INET_TUNNEL is not set | ||
| 359 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 360 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 361 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 362 | CONFIG_INET_LRO=y | ||
| 363 | CONFIG_INET_DIAG=y | ||
| 364 | CONFIG_INET_TCP_DIAG=y | ||
| 365 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 366 | CONFIG_TCP_CONG_CUBIC=y | ||
| 367 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 368 | # CONFIG_TCP_MD5SIG is not set | ||
| 369 | # CONFIG_IPV6 is not set | ||
| 370 | # CONFIG_NETWORK_SECMARK is not set | ||
| 371 | # CONFIG_NETFILTER is not set | ||
| 372 | # CONFIG_IP_DCCP is not set | ||
| 373 | # CONFIG_IP_SCTP is not set | ||
| 374 | # CONFIG_TIPC is not set | ||
| 375 | # CONFIG_ATM is not set | ||
| 376 | # CONFIG_BRIDGE is not set | ||
| 377 | # CONFIG_NET_DSA is not set | ||
| 378 | # CONFIG_VLAN_8021Q is not set | ||
| 379 | # CONFIG_DECNET is not set | ||
| 380 | # CONFIG_LLC2 is not set | ||
| 381 | # CONFIG_IPX is not set | ||
| 382 | # CONFIG_ATALK is not set | ||
| 383 | # CONFIG_X25 is not set | ||
| 384 | # CONFIG_LAPB is not set | ||
| 385 | # CONFIG_ECONET is not set | ||
| 386 | # CONFIG_WAN_ROUTER is not set | ||
| 387 | # CONFIG_PHONET is not set | ||
| 388 | # CONFIG_IEEE802154 is not set | ||
| 389 | # CONFIG_NET_SCHED is not set | ||
| 390 | # CONFIG_DCB is not set | ||
| 391 | |||
| 392 | # | ||
| 393 | # Network testing | ||
| 394 | # | ||
| 395 | # CONFIG_NET_PKTGEN is not set | ||
| 396 | # CONFIG_HAMRADIO is not set | ||
| 397 | # CONFIG_CAN is not set | ||
| 398 | # CONFIG_IRDA is not set | ||
| 399 | # CONFIG_BT is not set | ||
| 400 | # CONFIG_AF_RXRPC is not set | ||
| 401 | # CONFIG_WIRELESS is not set | ||
| 402 | # CONFIG_WIMAX is not set | ||
| 403 | # CONFIG_RFKILL is not set | ||
| 404 | # CONFIG_NET_9P is not set | ||
| 405 | |||
| 406 | # | ||
| 407 | # Device Drivers | ||
| 408 | # | ||
| 409 | |||
| 410 | # | ||
| 411 | # Generic Driver Options | ||
| 412 | # | ||
| 413 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 414 | CONFIG_STANDALONE=y | ||
| 415 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 416 | CONFIG_FW_LOADER=y | ||
| 417 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 418 | CONFIG_EXTRA_FIRMWARE="" | ||
| 419 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 420 | # CONFIG_CONNECTOR is not set | ||
| 421 | CONFIG_MTD=y | ||
| 422 | # CONFIG_MTD_DEBUG is not set | ||
| 423 | # CONFIG_MTD_CONCAT is not set | ||
| 424 | CONFIG_MTD_PARTITIONS=y | ||
| 425 | # CONFIG_MTD_TESTS is not set | ||
| 426 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 427 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 428 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 429 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 430 | |||
| 431 | # | ||
| 432 | # User Modules And Translation Layers | ||
| 433 | # | ||
| 434 | CONFIG_MTD_CHAR=y | ||
| 435 | CONFIG_MTD_BLKDEVS=y | ||
| 436 | CONFIG_MTD_BLOCK=y | ||
| 437 | # CONFIG_FTL is not set | ||
| 438 | # CONFIG_NFTL is not set | ||
| 439 | # CONFIG_INFTL is not set | ||
| 440 | # CONFIG_RFD_FTL is not set | ||
| 441 | # CONFIG_SSFDC is not set | ||
| 442 | # CONFIG_MTD_OOPS is not set | ||
| 443 | |||
| 444 | # | ||
| 445 | # RAM/ROM/Flash chip drivers | ||
| 446 | # | ||
| 447 | CONFIG_MTD_CFI=y | ||
| 448 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 449 | CONFIG_MTD_GEN_PROBE=y | ||
| 450 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 451 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 452 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 453 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 454 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 455 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 456 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 457 | CONFIG_MTD_CFI_I1=y | ||
| 458 | CONFIG_MTD_CFI_I2=y | ||
| 459 | # CONFIG_MTD_CFI_I4 is not set | ||
| 460 | # CONFIG_MTD_CFI_I8 is not set | ||
| 461 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 462 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 463 | # CONFIG_MTD_CFI_STAA is not set | ||
| 464 | CONFIG_MTD_CFI_UTIL=y | ||
| 465 | CONFIG_MTD_RAM=y | ||
| 466 | # CONFIG_MTD_ROM is not set | ||
| 467 | # CONFIG_MTD_ABSENT is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Mapping drivers for chip access | ||
| 471 | # | ||
| 472 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 473 | CONFIG_MTD_PHYSMAP=y | ||
| 474 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 475 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 476 | CONFIG_MTD_PLATRAM=y | ||
| 477 | |||
| 478 | # | ||
| 479 | # Self-contained MTD device drivers | ||
| 480 | # | ||
| 481 | # CONFIG_MTD_SLRAM is not set | ||
| 482 | # CONFIG_MTD_PHRAM is not set | ||
| 483 | # CONFIG_MTD_MTDRAM is not set | ||
| 484 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 485 | |||
| 486 | # | ||
| 487 | # Disk-On-Chip Device Drivers | ||
| 488 | # | ||
| 489 | # CONFIG_MTD_DOC2000 is not set | ||
| 490 | # CONFIG_MTD_DOC2001 is not set | ||
| 491 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 492 | # CONFIG_MTD_NAND is not set | ||
| 493 | # CONFIG_MTD_ONENAND is not set | ||
| 494 | |||
| 495 | # | ||
| 496 | # LPDDR flash memory drivers | ||
| 497 | # | ||
| 498 | # CONFIG_MTD_LPDDR is not set | ||
| 499 | |||
| 500 | # | ||
| 501 | # UBI - Unsorted block images | ||
| 502 | # | ||
| 503 | # CONFIG_MTD_UBI is not set | ||
| 504 | # CONFIG_PARPORT is not set | ||
| 505 | CONFIG_BLK_DEV=y | ||
| 506 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 507 | CONFIG_BLK_DEV_LOOP=y | ||
| 508 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 509 | CONFIG_BLK_DEV_NBD=y | ||
| 510 | # CONFIG_BLK_DEV_UB is not set | ||
| 511 | CONFIG_BLK_DEV_RAM=y | ||
| 512 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 513 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 514 | # CONFIG_BLK_DEV_XIP is not set | ||
| 515 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 516 | # CONFIG_ATA_OVER_ETH is not set | ||
| 517 | # CONFIG_MG_DISK is not set | ||
| 518 | # CONFIG_MISC_DEVICES is not set | ||
| 519 | CONFIG_HAVE_IDE=y | ||
| 520 | # CONFIG_IDE is not set | ||
| 521 | |||
| 522 | # | ||
| 523 | # SCSI device support | ||
| 524 | # | ||
| 525 | # CONFIG_RAID_ATTRS is not set | ||
| 526 | CONFIG_SCSI=y | ||
| 527 | CONFIG_SCSI_DMA=y | ||
| 528 | # CONFIG_SCSI_TGT is not set | ||
| 529 | # CONFIG_SCSI_NETLINK is not set | ||
| 530 | CONFIG_SCSI_PROC_FS=y | ||
| 531 | |||
| 532 | # | ||
| 533 | # SCSI support type (disk, tape, CD-ROM) | ||
| 534 | # | ||
| 535 | CONFIG_BLK_DEV_SD=y | ||
| 536 | # CONFIG_CHR_DEV_ST is not set | ||
| 537 | # CONFIG_CHR_DEV_OSST is not set | ||
| 538 | # CONFIG_BLK_DEV_SR is not set | ||
| 539 | # CONFIG_CHR_DEV_SG is not set | ||
| 540 | # CONFIG_CHR_DEV_SCH is not set | ||
| 541 | CONFIG_SCSI_MULTI_LUN=y | ||
| 542 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 543 | # CONFIG_SCSI_LOGGING is not set | ||
| 544 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 545 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 546 | |||
| 547 | # | ||
| 548 | # SCSI Transports | ||
| 549 | # | ||
| 550 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 551 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 552 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 553 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 554 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 555 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 556 | # CONFIG_SCSI_DH is not set | ||
| 557 | # CONFIG_SCSI_OSD_INITIATOR is not set | ||
| 558 | # CONFIG_ATA is not set | ||
| 559 | # CONFIG_MD is not set | ||
| 560 | CONFIG_NETDEVICES=y | ||
| 561 | # CONFIG_DUMMY is not set | ||
| 562 | # CONFIG_BONDING is not set | ||
| 563 | # CONFIG_MACVLAN is not set | ||
| 564 | # CONFIG_EQUALIZER is not set | ||
| 565 | # CONFIG_TUN is not set | ||
| 566 | # CONFIG_VETH is not set | ||
| 567 | CONFIG_PHYLIB=y | ||
| 568 | |||
| 569 | # | ||
| 570 | # MII PHY device drivers | ||
| 571 | # | ||
| 572 | # CONFIG_MARVELL_PHY is not set | ||
| 573 | # CONFIG_DAVICOM_PHY is not set | ||
| 574 | # CONFIG_QSEMI_PHY is not set | ||
| 575 | # CONFIG_LXT_PHY is not set | ||
| 576 | # CONFIG_CICADA_PHY is not set | ||
| 577 | # CONFIG_VITESSE_PHY is not set | ||
| 578 | # CONFIG_SMSC_PHY is not set | ||
| 579 | # CONFIG_BROADCOM_PHY is not set | ||
| 580 | # CONFIG_ICPLUS_PHY is not set | ||
| 581 | # CONFIG_REALTEK_PHY is not set | ||
| 582 | # CONFIG_NATIONAL_PHY is not set | ||
| 583 | # CONFIG_STE10XP is not set | ||
| 584 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 585 | # CONFIG_FIXED_PHY is not set | ||
| 586 | # CONFIG_MDIO_BITBANG is not set | ||
| 587 | CONFIG_NET_ETHERNET=y | ||
| 588 | CONFIG_MII=y | ||
| 589 | CONFIG_ARM_AT91_ETHER=y | ||
| 590 | # CONFIG_AX88796 is not set | ||
| 591 | # CONFIG_SMC91X is not set | ||
| 592 | # CONFIG_DM9000 is not set | ||
| 593 | # CONFIG_ETHOC is not set | ||
| 594 | # CONFIG_SMC911X is not set | ||
| 595 | # CONFIG_SMSC911X is not set | ||
| 596 | # CONFIG_DNET is not set | ||
| 597 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 598 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 599 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 600 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 601 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 602 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 603 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 604 | # CONFIG_B44 is not set | ||
| 605 | # CONFIG_KS8842 is not set | ||
| 606 | # CONFIG_NETDEV_1000 is not set | ||
| 607 | # CONFIG_NETDEV_10000 is not set | ||
| 608 | |||
| 609 | # | ||
| 610 | # Wireless LAN | ||
| 611 | # | ||
| 612 | # CONFIG_WLAN_PRE80211 is not set | ||
| 613 | # CONFIG_WLAN_80211 is not set | ||
| 614 | |||
| 615 | # | ||
| 616 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 617 | # | ||
| 618 | |||
| 619 | # | ||
| 620 | # USB Network Adapters | ||
| 621 | # | ||
| 622 | # CONFIG_USB_CATC is not set | ||
| 623 | # CONFIG_USB_KAWETH is not set | ||
| 624 | # CONFIG_USB_PEGASUS is not set | ||
| 625 | # CONFIG_USB_RTL8150 is not set | ||
| 626 | # CONFIG_USB_USBNET is not set | ||
| 627 | # CONFIG_WAN is not set | ||
| 628 | CONFIG_PPP=y | ||
| 629 | # CONFIG_PPP_MULTILINK is not set | ||
| 630 | # CONFIG_PPP_FILTER is not set | ||
| 631 | CONFIG_PPP_ASYNC=y | ||
| 632 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 633 | CONFIG_PPP_DEFLATE=y | ||
| 634 | CONFIG_PPP_BSDCOMP=y | ||
| 635 | # CONFIG_PPP_MPPE is not set | ||
| 636 | # CONFIG_PPPOE is not set | ||
| 637 | # CONFIG_PPPOL2TP is not set | ||
| 638 | # CONFIG_SLIP is not set | ||
| 639 | CONFIG_SLHC=y | ||
| 640 | # CONFIG_NETCONSOLE is not set | ||
| 641 | # CONFIG_NETPOLL is not set | ||
| 642 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 643 | # CONFIG_ISDN is not set | ||
| 644 | |||
| 645 | # | ||
| 646 | # Input device support | ||
| 647 | # | ||
| 648 | CONFIG_INPUT=y | ||
| 649 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 650 | # CONFIG_INPUT_POLLDEV is not set | ||
| 651 | |||
| 652 | # | ||
| 653 | # Userland interfaces | ||
| 654 | # | ||
| 655 | CONFIG_INPUT_MOUSEDEV=y | ||
| 656 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 657 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 658 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 659 | # CONFIG_INPUT_JOYDEV is not set | ||
| 660 | # CONFIG_INPUT_EVDEV is not set | ||
| 661 | # CONFIG_INPUT_EVBUG is not set | ||
| 662 | |||
| 663 | # | ||
| 664 | # Input Device Drivers | ||
| 665 | # | ||
| 666 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 667 | # CONFIG_INPUT_MOUSE is not set | ||
| 668 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 669 | # CONFIG_INPUT_TABLET is not set | ||
| 670 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 671 | # CONFIG_INPUT_MISC is not set | ||
| 672 | |||
| 673 | # | ||
| 674 | # Hardware I/O ports | ||
| 675 | # | ||
| 676 | # CONFIG_SERIO is not set | ||
| 677 | # CONFIG_GAMEPORT is not set | ||
| 678 | |||
| 679 | # | ||
| 680 | # Character devices | ||
| 681 | # | ||
| 682 | CONFIG_VT=y | ||
| 683 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 684 | CONFIG_VT_CONSOLE=y | ||
| 685 | CONFIG_HW_CONSOLE=y | ||
| 686 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 687 | CONFIG_DEVKMEM=y | ||
| 688 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 689 | |||
| 690 | # | ||
| 691 | # Serial drivers | ||
| 692 | # | ||
| 693 | # CONFIG_SERIAL_8250 is not set | ||
| 694 | |||
| 695 | # | ||
| 696 | # Non-8250 serial port support | ||
| 697 | # | ||
| 698 | CONFIG_SERIAL_ATMEL=y | ||
| 699 | CONFIG_SERIAL_ATMEL_CONSOLE=y | ||
| 700 | CONFIG_SERIAL_ATMEL_PDC=y | ||
| 701 | # CONFIG_SERIAL_ATMEL_TTYAT is not set | ||
| 702 | CONFIG_SERIAL_CORE=y | ||
| 703 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 704 | CONFIG_UNIX98_PTYS=y | ||
| 705 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 706 | CONFIG_LEGACY_PTYS=y | ||
| 707 | CONFIG_LEGACY_PTY_COUNT=32 | ||
| 708 | # CONFIG_IPMI_HANDLER is not set | ||
| 709 | # CONFIG_HW_RANDOM is not set | ||
| 710 | # CONFIG_R3964 is not set | ||
| 711 | # CONFIG_RAW_DRIVER is not set | ||
| 712 | # CONFIG_TCG_TPM is not set | ||
| 713 | CONFIG_I2C=y | ||
| 714 | CONFIG_I2C_BOARDINFO=y | ||
| 715 | CONFIG_I2C_CHARDEV=y | ||
| 716 | CONFIG_I2C_HELPER_AUTO=y | ||
| 717 | CONFIG_I2C_ALGOBIT=y | ||
| 718 | |||
| 719 | # | ||
| 720 | # I2C Hardware Bus support | ||
| 721 | # | ||
| 722 | |||
| 723 | # | ||
| 724 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 725 | # | ||
| 726 | # CONFIG_I2C_DESIGNWARE is not set | ||
| 727 | CONFIG_I2C_GPIO=y | ||
| 728 | # CONFIG_I2C_OCORES is not set | ||
| 729 | # CONFIG_I2C_SIMTEC is not set | ||
| 730 | |||
| 731 | # | ||
| 732 | # External I2C/SMBus adapter drivers | ||
| 733 | # | ||
| 734 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 735 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 736 | # CONFIG_I2C_TINY_USB is not set | ||
| 737 | |||
| 738 | # | ||
| 739 | # Other I2C/SMBus bus drivers | ||
| 740 | # | ||
| 741 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 742 | # CONFIG_I2C_STUB is not set | ||
| 743 | |||
| 744 | # | ||
| 745 | # Miscellaneous I2C Chip support | ||
| 746 | # | ||
| 747 | # CONFIG_DS1682 is not set | ||
| 748 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 749 | # CONFIG_PCF8575 is not set | ||
| 750 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 751 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 752 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 753 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 754 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 755 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 756 | # CONFIG_SPI is not set | ||
| 757 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 758 | CONFIG_GPIOLIB=y | ||
| 759 | CONFIG_GPIO_SYSFS=y | ||
| 760 | |||
| 761 | # | ||
| 762 | # Memory mapped GPIO expanders: | ||
| 763 | # | ||
| 764 | |||
| 765 | # | ||
| 766 | # I2C GPIO expanders: | ||
| 767 | # | ||
| 768 | # CONFIG_GPIO_MAX732X is not set | ||
| 769 | # CONFIG_GPIO_PCA953X is not set | ||
| 770 | # CONFIG_GPIO_PCF857X is not set | ||
| 771 | |||
| 772 | # | ||
| 773 | # PCI GPIO expanders: | ||
| 774 | # | ||
| 775 | |||
| 776 | # | ||
| 777 | # SPI GPIO expanders: | ||
| 778 | # | ||
| 779 | # CONFIG_W1 is not set | ||
| 780 | # CONFIG_POWER_SUPPLY is not set | ||
| 781 | # CONFIG_HWMON is not set | ||
| 782 | # CONFIG_THERMAL is not set | ||
| 783 | # CONFIG_THERMAL_HWMON is not set | ||
| 784 | CONFIG_WATCHDOG=y | ||
| 785 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 786 | |||
| 787 | # | ||
| 788 | # Watchdog Device Drivers | ||
| 789 | # | ||
| 790 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 791 | CONFIG_AT91RM9200_WATCHDOG=y | ||
| 792 | |||
| 793 | # | ||
| 794 | # USB-based Watchdog Cards | ||
| 795 | # | ||
| 796 | # CONFIG_USBPCWATCHDOG is not set | ||
| 797 | CONFIG_SSB_POSSIBLE=y | ||
| 798 | |||
| 799 | # | ||
| 800 | # Sonics Silicon Backplane | ||
| 801 | # | ||
| 802 | # CONFIG_SSB is not set | ||
| 803 | |||
| 804 | # | ||
| 805 | # Multifunction device drivers | ||
| 806 | # | ||
| 807 | # CONFIG_MFD_CORE is not set | ||
| 808 | # CONFIG_MFD_SM501 is not set | ||
| 809 | # CONFIG_MFD_ASIC3 is not set | ||
| 810 | # CONFIG_HTC_EGPIO is not set | ||
| 811 | # CONFIG_HTC_PASIC3 is not set | ||
| 812 | # CONFIG_TPS65010 is not set | ||
| 813 | # CONFIG_TWL4030_CORE is not set | ||
| 814 | # CONFIG_MFD_TMIO is not set | ||
| 815 | # CONFIG_MFD_T7L66XB is not set | ||
| 816 | # CONFIG_MFD_TC6387XB is not set | ||
| 817 | # CONFIG_MFD_TC6393XB is not set | ||
| 818 | # CONFIG_PMIC_DA903X is not set | ||
| 819 | # CONFIG_MFD_WM8400 is not set | ||
| 820 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 821 | # CONFIG_MFD_PCF50633 is not set | ||
| 822 | # CONFIG_AB3100_CORE is not set | ||
| 823 | # CONFIG_MEDIA_SUPPORT is not set | ||
| 824 | |||
| 825 | # | ||
| 826 | # Graphics support | ||
| 827 | # | ||
| 828 | # CONFIG_VGASTATE is not set | ||
| 829 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 830 | # CONFIG_FB is not set | ||
| 831 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 832 | |||
| 833 | # | ||
| 834 | # Display device support | ||
| 835 | # | ||
| 836 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 837 | |||
| 838 | # | ||
| 839 | # Console display driver support | ||
| 840 | # | ||
| 841 | # CONFIG_VGA_CONSOLE is not set | ||
| 842 | CONFIG_DUMMY_CONSOLE=y | ||
| 843 | # CONFIG_SOUND is not set | ||
| 844 | # CONFIG_HID_SUPPORT is not set | ||
| 845 | CONFIG_USB_SUPPORT=y | ||
| 846 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 847 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 848 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 849 | CONFIG_USB=y | ||
| 850 | # CONFIG_USB_DEBUG is not set | ||
| 851 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 852 | |||
| 853 | # | ||
| 854 | # Miscellaneous USB options | ||
| 855 | # | ||
| 856 | # CONFIG_USB_DEVICEFS is not set | ||
| 857 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 858 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 859 | # CONFIG_USB_OTG is not set | ||
| 860 | # CONFIG_USB_MON is not set | ||
| 861 | # CONFIG_USB_WUSB is not set | ||
| 862 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 863 | |||
| 864 | # | ||
| 865 | # USB Host Controller Drivers | ||
| 866 | # | ||
| 867 | # CONFIG_USB_C67X00_HCD is not set | ||
| 868 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 869 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 870 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 871 | CONFIG_USB_OHCI_HCD=y | ||
| 872 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 873 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 874 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 875 | # CONFIG_USB_SL811_HCD is not set | ||
| 876 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 877 | # CONFIG_USB_HWA_HCD is not set | ||
| 878 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 879 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 880 | |||
| 881 | # | ||
| 882 | # USB Device Class drivers | ||
| 883 | # | ||
| 884 | # CONFIG_USB_ACM is not set | ||
| 885 | # CONFIG_USB_PRINTER is not set | ||
| 886 | # CONFIG_USB_WDM is not set | ||
| 887 | # CONFIG_USB_TMC is not set | ||
| 888 | |||
| 889 | # | ||
| 890 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may | ||
| 891 | # | ||
| 892 | |||
| 893 | # | ||
| 894 | # also be needed; see USB_STORAGE Help for more info | ||
| 895 | # | ||
| 896 | CONFIG_USB_STORAGE=y | ||
| 897 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 898 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 899 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 900 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 901 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 902 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 903 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 904 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 905 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 906 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 907 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 908 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 909 | # CONFIG_USB_LIBUSUAL is not set | ||
| 910 | |||
| 911 | # | ||
| 912 | # USB Imaging devices | ||
| 913 | # | ||
| 914 | # CONFIG_USB_MDC800 is not set | ||
| 915 | # CONFIG_USB_MICROTEK is not set | ||
| 916 | |||
| 917 | # | ||
| 918 | # USB port drivers | ||
| 919 | # | ||
| 920 | # CONFIG_USB_SERIAL is not set | ||
| 921 | |||
| 922 | # | ||
| 923 | # USB Miscellaneous drivers | ||
| 924 | # | ||
| 925 | # CONFIG_USB_EMI62 is not set | ||
| 926 | # CONFIG_USB_EMI26 is not set | ||
| 927 | # CONFIG_USB_ADUTUX is not set | ||
| 928 | # CONFIG_USB_SEVSEG is not set | ||
| 929 | # CONFIG_USB_RIO500 is not set | ||
| 930 | # CONFIG_USB_LEGOTOWER is not set | ||
| 931 | # CONFIG_USB_LCD is not set | ||
| 932 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 933 | # CONFIG_USB_LED is not set | ||
| 934 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 935 | # CONFIG_USB_CYTHERM is not set | ||
| 936 | # CONFIG_USB_IDMOUSE is not set | ||
| 937 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 938 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 939 | # CONFIG_USB_LD is not set | ||
| 940 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 941 | # CONFIG_USB_IOWARRIOR is not set | ||
| 942 | # CONFIG_USB_ISIGHTFW is not set | ||
| 943 | # CONFIG_USB_VST is not set | ||
| 944 | CONFIG_USB_GADGET=y | ||
| 945 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 946 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 947 | CONFIG_USB_GADGET_SELECTED=y | ||
| 948 | CONFIG_USB_GADGET_AT91=y | ||
| 949 | CONFIG_USB_AT91=y | ||
| 950 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 951 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 952 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 953 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 954 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 955 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 956 | # CONFIG_USB_GADGET_S3C_HSOTG is not set | ||
| 957 | # CONFIG_USB_GADGET_IMX is not set | ||
| 958 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 959 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 960 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 961 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 962 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 963 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 964 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 965 | # CONFIG_USB_GADGET_LANGWELL is not set | ||
| 966 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 967 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 968 | # CONFIG_USB_ZERO is not set | ||
| 969 | # CONFIG_USB_AUDIO is not set | ||
| 970 | CONFIG_USB_ETH=y | ||
| 971 | CONFIG_USB_ETH_RNDIS=y | ||
| 972 | # CONFIG_USB_GADGETFS is not set | ||
| 973 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 974 | # CONFIG_USB_G_SERIAL is not set | ||
| 975 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 976 | # CONFIG_USB_G_PRINTER is not set | ||
| 977 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 978 | |||
| 979 | # | ||
| 980 | # OTG and related infrastructure | ||
| 981 | # | ||
| 982 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 983 | # CONFIG_NOP_USB_XCEIV is not set | ||
| 984 | CONFIG_MMC=y | ||
| 985 | # CONFIG_MMC_DEBUG is not set | ||
| 986 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 987 | |||
| 988 | # | ||
| 989 | # MMC/SD/SDIO Card Drivers | ||
| 990 | # | ||
| 991 | CONFIG_MMC_BLOCK=y | ||
| 992 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 993 | # CONFIG_SDIO_UART is not set | ||
| 994 | # CONFIG_MMC_TEST is not set | ||
| 995 | |||
| 996 | # | ||
| 997 | # MMC/SD/SDIO Host Controller Drivers | ||
| 998 | # | ||
| 999 | # CONFIG_MMC_SDHCI is not set | ||
| 1000 | CONFIG_MMC_AT91=y | ||
| 1001 | # CONFIG_MEMSTICK is not set | ||
| 1002 | # CONFIG_ACCESSIBILITY is not set | ||
| 1003 | CONFIG_NEW_LEDS=y | ||
| 1004 | CONFIG_LEDS_CLASS=y | ||
| 1005 | |||
| 1006 | # | ||
| 1007 | # LED drivers | ||
| 1008 | # | ||
| 1009 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1010 | CONFIG_LEDS_GPIO=y | ||
| 1011 | CONFIG_LEDS_GPIO_PLATFORM=y | ||
| 1012 | # CONFIG_LEDS_LP3944 is not set | ||
| 1013 | # CONFIG_LEDS_PCA955X is not set | ||
| 1014 | # CONFIG_LEDS_BD2802 is not set | ||
| 1015 | |||
| 1016 | # | ||
| 1017 | # LED Triggers | ||
| 1018 | # | ||
| 1019 | CONFIG_LEDS_TRIGGERS=y | ||
| 1020 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1021 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1022 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1023 | CONFIG_LEDS_TRIGGER_GPIO=y | ||
| 1024 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1025 | |||
| 1026 | # | ||
| 1027 | # iptables trigger is under Netfilter config (LED target) | ||
| 1028 | # | ||
| 1029 | CONFIG_RTC_LIB=y | ||
| 1030 | CONFIG_RTC_CLASS=y | ||
| 1031 | # CONFIG_RTC_HCTOSYS is not set | ||
| 1032 | # CONFIG_RTC_DEBUG is not set | ||
| 1033 | |||
| 1034 | # | ||
| 1035 | # RTC interfaces | ||
| 1036 | # | ||
| 1037 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1038 | CONFIG_RTC_INTF_PROC=y | ||
| 1039 | CONFIG_RTC_INTF_DEV=y | ||
| 1040 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1041 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1042 | |||
| 1043 | # | ||
| 1044 | # I2C RTC drivers | ||
| 1045 | # | ||
| 1046 | CONFIG_RTC_DRV_DS1307=y | ||
| 1047 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1048 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1049 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1050 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1051 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1052 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1053 | CONFIG_RTC_DRV_PCF8563=y | ||
| 1054 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1055 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1056 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1057 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1058 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1059 | # CONFIG_RTC_DRV_RX8025 is not set | ||
| 1060 | |||
| 1061 | # | ||
| 1062 | # SPI RTC drivers | ||
| 1063 | # | ||
| 1064 | |||
| 1065 | # | ||
| 1066 | # Platform RTC drivers | ||
| 1067 | # | ||
| 1068 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1069 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1070 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1071 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1072 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1073 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1074 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1075 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1076 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1077 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1078 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1079 | |||
| 1080 | # | ||
| 1081 | # on-CPU RTC drivers | ||
| 1082 | # | ||
| 1083 | # CONFIG_RTC_DRV_AT91RM9200 is not set | ||
| 1084 | # CONFIG_DMADEVICES is not set | ||
| 1085 | # CONFIG_AUXDISPLAY is not set | ||
| 1086 | # CONFIG_REGULATOR is not set | ||
| 1087 | # CONFIG_UIO is not set | ||
| 1088 | # CONFIG_STAGING is not set | ||
| 1089 | |||
| 1090 | # | ||
| 1091 | # File systems | ||
| 1092 | # | ||
| 1093 | CONFIG_EXT2_FS=y | ||
| 1094 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1095 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1096 | CONFIG_EXT3_FS=y | ||
| 1097 | # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set | ||
| 1098 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1099 | # CONFIG_EXT4_FS is not set | ||
| 1100 | CONFIG_JBD=y | ||
| 1101 | # CONFIG_REISERFS_FS is not set | ||
| 1102 | # CONFIG_JFS_FS is not set | ||
| 1103 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1104 | # CONFIG_XFS_FS is not set | ||
| 1105 | # CONFIG_GFS2_FS is not set | ||
| 1106 | # CONFIG_OCFS2_FS is not set | ||
| 1107 | # CONFIG_BTRFS_FS is not set | ||
| 1108 | CONFIG_FILE_LOCKING=y | ||
| 1109 | CONFIG_FSNOTIFY=y | ||
| 1110 | CONFIG_DNOTIFY=y | ||
| 1111 | CONFIG_INOTIFY=y | ||
| 1112 | CONFIG_INOTIFY_USER=y | ||
| 1113 | # CONFIG_QUOTA is not set | ||
| 1114 | # CONFIG_AUTOFS_FS is not set | ||
| 1115 | CONFIG_AUTOFS4_FS=y | ||
| 1116 | # CONFIG_FUSE_FS is not set | ||
| 1117 | |||
| 1118 | # | ||
| 1119 | # Caches | ||
| 1120 | # | ||
| 1121 | # CONFIG_FSCACHE is not set | ||
| 1122 | |||
| 1123 | # | ||
| 1124 | # CD-ROM/DVD Filesystems | ||
| 1125 | # | ||
| 1126 | # CONFIG_ISO9660_FS is not set | ||
| 1127 | # CONFIG_UDF_FS is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # DOS/FAT/NT Filesystems | ||
| 1131 | # | ||
| 1132 | CONFIG_FAT_FS=y | ||
| 1133 | CONFIG_MSDOS_FS=y | ||
| 1134 | CONFIG_VFAT_FS=y | ||
| 1135 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1136 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1137 | # CONFIG_NTFS_FS is not set | ||
| 1138 | |||
| 1139 | # | ||
| 1140 | # Pseudo filesystems | ||
| 1141 | # | ||
| 1142 | CONFIG_PROC_FS=y | ||
| 1143 | CONFIG_PROC_SYSCTL=y | ||
| 1144 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1145 | CONFIG_SYSFS=y | ||
| 1146 | CONFIG_TMPFS=y | ||
| 1147 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1148 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1149 | # CONFIG_CONFIGFS_FS is not set | ||
| 1150 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1151 | # CONFIG_ADFS_FS is not set | ||
| 1152 | # CONFIG_AFFS_FS is not set | ||
| 1153 | # CONFIG_HFS_FS is not set | ||
| 1154 | # CONFIG_HFSPLUS_FS is not set | ||
| 1155 | # CONFIG_BEFS_FS is not set | ||
| 1156 | # CONFIG_BFS_FS is not set | ||
| 1157 | # CONFIG_EFS_FS is not set | ||
| 1158 | CONFIG_JFFS2_FS=y | ||
| 1159 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1160 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1161 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1162 | CONFIG_JFFS2_SUMMARY=y | ||
| 1163 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1164 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1165 | CONFIG_JFFS2_ZLIB=y | ||
| 1166 | # CONFIG_JFFS2_LZO is not set | ||
| 1167 | CONFIG_JFFS2_RTIME=y | ||
| 1168 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1169 | CONFIG_CRAMFS=y | ||
| 1170 | # CONFIG_SQUASHFS is not set | ||
| 1171 | # CONFIG_VXFS_FS is not set | ||
| 1172 | CONFIG_MINIX_FS=y | ||
| 1173 | # CONFIG_OMFS_FS is not set | ||
| 1174 | # CONFIG_HPFS_FS is not set | ||
| 1175 | # CONFIG_QNX4FS_FS is not set | ||
| 1176 | # CONFIG_ROMFS_FS is not set | ||
| 1177 | # CONFIG_SYSV_FS is not set | ||
| 1178 | # CONFIG_UFS_FS is not set | ||
| 1179 | # CONFIG_NILFS2_FS is not set | ||
| 1180 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1181 | CONFIG_NFS_FS=y | ||
| 1182 | CONFIG_NFS_V3=y | ||
| 1183 | # CONFIG_NFS_V3_ACL is not set | ||
| 1184 | # CONFIG_NFS_V4 is not set | ||
| 1185 | CONFIG_ROOT_NFS=y | ||
| 1186 | # CONFIG_NFSD is not set | ||
| 1187 | CONFIG_LOCKD=y | ||
| 1188 | CONFIG_LOCKD_V4=y | ||
| 1189 | CONFIG_NFS_COMMON=y | ||
| 1190 | CONFIG_SUNRPC=y | ||
| 1191 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1192 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1193 | # CONFIG_SMB_FS is not set | ||
| 1194 | # CONFIG_CIFS is not set | ||
| 1195 | # CONFIG_NCP_FS is not set | ||
| 1196 | # CONFIG_CODA_FS is not set | ||
| 1197 | # CONFIG_AFS_FS is not set | ||
| 1198 | |||
| 1199 | # | ||
| 1200 | # Partition Types | ||
| 1201 | # | ||
| 1202 | CONFIG_PARTITION_ADVANCED=y | ||
| 1203 | # CONFIG_ACORN_PARTITION is not set | ||
| 1204 | # CONFIG_OSF_PARTITION is not set | ||
| 1205 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1206 | # CONFIG_ATARI_PARTITION is not set | ||
| 1207 | # CONFIG_MAC_PARTITION is not set | ||
| 1208 | CONFIG_MSDOS_PARTITION=y | ||
| 1209 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1210 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1211 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1212 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1213 | # CONFIG_LDM_PARTITION is not set | ||
| 1214 | # CONFIG_SGI_PARTITION is not set | ||
| 1215 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1216 | # CONFIG_SUN_PARTITION is not set | ||
| 1217 | # CONFIG_KARMA_PARTITION is not set | ||
| 1218 | # CONFIG_EFI_PARTITION is not set | ||
| 1219 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1220 | CONFIG_NLS=y | ||
| 1221 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1222 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1223 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1224 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1225 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1226 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1227 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1228 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1229 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1230 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1231 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1232 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1233 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1234 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1235 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1236 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1237 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1238 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1239 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1240 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1241 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1242 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1243 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1244 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1245 | # CONFIG_NLS_ASCII is not set | ||
| 1246 | CONFIG_NLS_ISO8859_1=y | ||
| 1247 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1248 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1249 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1250 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1251 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1252 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1253 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1254 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1255 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1256 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1257 | # CONFIG_NLS_KOI8_R is not set | ||
| 1258 | # CONFIG_NLS_KOI8_U is not set | ||
| 1259 | CONFIG_NLS_UTF8=y | ||
| 1260 | # CONFIG_DLM is not set | ||
| 1261 | |||
| 1262 | # | ||
| 1263 | # Kernel hacking | ||
| 1264 | # | ||
| 1265 | # CONFIG_PRINTK_TIME is not set | ||
| 1266 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1267 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1268 | CONFIG_FRAME_WARN=1024 | ||
| 1269 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1270 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1271 | # CONFIG_DEBUG_FS is not set | ||
| 1272 | # CONFIG_HEADERS_CHECK is not set | ||
| 1273 | # CONFIG_DEBUG_KERNEL is not set | ||
| 1274 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1275 | # CONFIG_SLUB_STATS is not set | ||
| 1276 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1277 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1278 | CONFIG_FRAME_POINTER=y | ||
| 1279 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1280 | # CONFIG_LATENCYTOP is not set | ||
| 1281 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1282 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1283 | CONFIG_TRACING_SUPPORT=y | ||
| 1284 | # CONFIG_FTRACE is not set | ||
| 1285 | # CONFIG_SAMPLES is not set | ||
| 1286 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1287 | # CONFIG_DEBUG_USER is not set | ||
| 1288 | |||
| 1289 | # | ||
| 1290 | # Security options | ||
| 1291 | # | ||
| 1292 | # CONFIG_KEYS is not set | ||
| 1293 | # CONFIG_SECURITY is not set | ||
| 1294 | # CONFIG_SECURITYFS is not set | ||
| 1295 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1296 | # CONFIG_CRYPTO is not set | ||
| 1297 | # CONFIG_BINARY_PRINTF is not set | ||
| 1298 | |||
| 1299 | # | ||
| 1300 | # Library routines | ||
| 1301 | # | ||
| 1302 | CONFIG_BITREVERSE=y | ||
| 1303 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1304 | CONFIG_CRC_CCITT=y | ||
| 1305 | # CONFIG_CRC16 is not set | ||
| 1306 | # CONFIG_CRC_T10DIF is not set | ||
| 1307 | # CONFIG_CRC_ITU_T is not set | ||
| 1308 | CONFIG_CRC32=y | ||
| 1309 | # CONFIG_CRC7 is not set | ||
| 1310 | # CONFIG_LIBCRC32C is not set | ||
| 1311 | CONFIG_ZLIB_INFLATE=y | ||
| 1312 | CONFIG_ZLIB_DEFLATE=y | ||
| 1313 | CONFIG_HAS_IOMEM=y | ||
| 1314 | CONFIG_HAS_IOPORT=y | ||
| 1315 | CONFIG_HAS_DMA=y | ||
| 1316 | CONFIG_NLATTR=y | ||
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h index 0d4c478e01b6..103f7ee97313 100644 --- a/arch/arm/include/asm/ftrace.h +++ b/arch/arm/include/asm/ftrace.h | |||
| @@ -12,4 +12,38 @@ extern void __gnu_mcount_nc(void); | |||
| 12 | 12 | ||
| 13 | #endif | 13 | #endif |
| 14 | 14 | ||
| 15 | #ifndef __ASSEMBLY__ | ||
| 16 | |||
| 17 | #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) | ||
| 18 | /* | ||
| 19 | * return_address uses walk_stackframe to do it's work. If both | ||
| 20 | * CONFIG_FRAME_POINTER=y and CONFIG_ARM_UNWIND=y walk_stackframe uses unwind | ||
| 21 | * information. For this to work in the function tracer many functions would | ||
| 22 | * have to be marked with __notrace. So for now just depend on | ||
| 23 | * !CONFIG_ARM_UNWIND. | ||
| 24 | */ | ||
| 25 | |||
| 26 | void *return_address(unsigned int); | ||
| 27 | |||
| 28 | #else | ||
| 29 | |||
| 30 | extern inline void *return_address(unsigned int level) | ||
| 31 | { | ||
| 32 | return NULL; | ||
| 33 | } | ||
| 34 | |||
| 35 | #endif | ||
| 36 | |||
| 37 | #define HAVE_ARCH_CALLER_ADDR | ||
| 38 | |||
| 39 | #define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0)) | ||
| 40 | #define CALLER_ADDR1 ((unsigned long)return_address(1)) | ||
| 41 | #define CALLER_ADDR2 ((unsigned long)return_address(2)) | ||
| 42 | #define CALLER_ADDR3 ((unsigned long)return_address(3)) | ||
| 43 | #define CALLER_ADDR4 ((unsigned long)return_address(4)) | ||
| 44 | #define CALLER_ADDR5 ((unsigned long)return_address(5)) | ||
| 45 | #define CALLER_ADDR6 ((unsigned long)return_address(6)) | ||
| 46 | |||
| 47 | #endif /* ifndef __ASSEMBLY__ */ | ||
| 48 | |||
| 15 | #endif /* _ASM_ARM_FTRACE */ | 49 | #endif /* _ASM_ARM_FTRACE */ |
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h index 4da332b03144..b490ecc79def 100644 --- a/arch/arm/include/asm/mach/mmc.h +++ b/arch/arm/include/asm/mach/mmc.h | |||
| @@ -10,6 +10,8 @@ struct mmc_platform_data { | |||
| 10 | unsigned int ocr_mask; /* available voltages */ | 10 | unsigned int ocr_mask; /* available voltages */ |
| 11 | u32 (*translate_vdd)(struct device *, unsigned int); | 11 | u32 (*translate_vdd)(struct device *, unsigned int); |
| 12 | unsigned int (*status)(struct device *); | 12 | unsigned int (*status)(struct device *); |
| 13 | int gpio_wp; | ||
| 14 | int gpio_cd; | ||
| 13 | }; | 15 | }; |
| 14 | 16 | ||
| 15 | #endif | 17 | #endif |
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 3dcd64bf1824..b12cc98bbe04 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h | |||
| @@ -36,6 +36,8 @@ extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd); | |||
| 36 | #define pgd_alloc(mm) get_pgd_slow(mm) | 36 | #define pgd_alloc(mm) get_pgd_slow(mm) |
| 37 | #define pgd_free(mm, pgd) free_pgd_slow(mm, pgd) | 37 | #define pgd_free(mm, pgd) free_pgd_slow(mm, pgd) |
| 38 | 38 | ||
| 39 | #define PGALLOC_GFP (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO) | ||
| 40 | |||
| 39 | /* | 41 | /* |
| 40 | * Allocate one PTE table. | 42 | * Allocate one PTE table. |
| 41 | * | 43 | * |
| @@ -57,7 +59,7 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr) | |||
| 57 | { | 59 | { |
| 58 | pte_t *pte; | 60 | pte_t *pte; |
| 59 | 61 | ||
| 60 | pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); | 62 | pte = (pte_t *)__get_free_page(PGALLOC_GFP); |
| 61 | if (pte) { | 63 | if (pte) { |
| 62 | clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE); | 64 | clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE); |
| 63 | pte += PTRS_PER_PTE; | 65 | pte += PTRS_PER_PTE; |
| @@ -71,10 +73,16 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr) | |||
| 71 | { | 73 | { |
| 72 | struct page *pte; | 74 | struct page *pte; |
| 73 | 75 | ||
| 74 | pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); | 76 | #ifdef CONFIG_HIGHPTE |
| 77 | pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0); | ||
| 78 | #else | ||
| 79 | pte = alloc_pages(PGALLOC_GFP, 0); | ||
| 80 | #endif | ||
| 75 | if (pte) { | 81 | if (pte) { |
| 76 | void *page = page_address(pte); | 82 | if (!PageHighMem(pte)) { |
| 77 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); | 83 | void *page = page_address(pte); |
| 84 | clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE); | ||
| 85 | } | ||
| 78 | pgtable_page_ctor(pte); | 86 | pgtable_page_ctor(pte); |
| 79 | } | 87 | } |
| 80 | 88 | ||
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index c433c6c73112..201ccaa11f61 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h | |||
| @@ -162,10 +162,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val); | |||
| 162 | * entries are stored 1024 bytes below. | 162 | * entries are stored 1024 bytes below. |
| 163 | */ | 163 | */ |
| 164 | #define L_PTE_PRESENT (1 << 0) | 164 | #define L_PTE_PRESENT (1 << 0) |
| 165 | #define L_PTE_FILE (1 << 1) /* only when !PRESENT */ | ||
| 166 | #define L_PTE_YOUNG (1 << 1) | 165 | #define L_PTE_YOUNG (1 << 1) |
| 167 | #define L_PTE_BUFFERABLE (1 << 2) /* obsolete, matches PTE */ | 166 | #define L_PTE_FILE (1 << 2) /* only when !PRESENT */ |
| 168 | #define L_PTE_CACHEABLE (1 << 3) /* obsolete, matches PTE */ | ||
| 169 | #define L_PTE_DIRTY (1 << 6) | 167 | #define L_PTE_DIRTY (1 << 6) |
| 170 | #define L_PTE_WRITE (1 << 7) | 168 | #define L_PTE_WRITE (1 << 7) |
| 171 | #define L_PTE_USER (1 << 8) | 169 | #define L_PTE_USER (1 << 8) |
| @@ -264,10 +262,19 @@ extern struct page *empty_zero_page; | |||
| 264 | #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) | 262 | #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0) |
| 265 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) | 263 | #define pte_page(pte) (pfn_to_page(pte_pfn(pte))) |
| 266 | #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | 264 | #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) |
| 267 | #define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | 265 | |
| 268 | #define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr)) | 266 | #define pte_offset_map(dir,addr) (__pte_map(dir, KM_PTE0) + __pte_index(addr)) |
| 269 | #define pte_unmap(pte) do { } while (0) | 267 | #define pte_offset_map_nested(dir,addr) (__pte_map(dir, KM_PTE1) + __pte_index(addr)) |
| 270 | #define pte_unmap_nested(pte) do { } while (0) | 268 | #define pte_unmap(pte) __pte_unmap(pte, KM_PTE0) |
| 269 | #define pte_unmap_nested(pte) __pte_unmap(pte, KM_PTE1) | ||
| 270 | |||
| 271 | #ifndef CONFIG_HIGHPTE | ||
| 272 | #define __pte_map(dir,km) pmd_page_vaddr(*(dir)) | ||
| 273 | #define __pte_unmap(pte,km) do { } while (0) | ||
| 274 | #else | ||
| 275 | #define __pte_map(dir,km) ((pte_t *)kmap_atomic(pmd_page(*(dir)), km) + PTRS_PER_PTE) | ||
| 276 | #define __pte_unmap(pte,km) kunmap_atomic((pte - PTRS_PER_PTE), km) | ||
| 277 | #endif | ||
| 271 | 278 | ||
| 272 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) | 279 | #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext) |
| 273 | 280 | ||
| @@ -381,13 +388,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |||
| 381 | * | 388 | * |
| 382 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | 389 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 383 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | 390 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 384 | * <--------------- offset --------------------> <--- type --> 0 0 | 391 | * <--------------- offset --------------------> <- type --> 0 0 0 |
| 385 | * | 392 | * |
| 386 | * This gives us up to 127 swap files and 32GB per swap file. Note that | 393 | * This gives us up to 63 swap files and 32GB per swap file. Note that |
| 387 | * the offset field is always non-zero. | 394 | * the offset field is always non-zero. |
| 388 | */ | 395 | */ |
| 389 | #define __SWP_TYPE_SHIFT 2 | 396 | #define __SWP_TYPE_SHIFT 3 |
| 390 | #define __SWP_TYPE_BITS 7 | 397 | #define __SWP_TYPE_BITS 6 |
| 391 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) | 398 | #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1) |
| 392 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) | 399 | #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT) |
| 393 | 400 | ||
| @@ -411,13 +418,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |||
| 411 | * | 418 | * |
| 412 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | 419 | * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 |
| 413 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | 420 | * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 |
| 414 | * <------------------------ offset -------------------------> 1 0 | 421 | * <----------------------- offset ------------------------> 1 0 0 |
| 415 | */ | 422 | */ |
| 416 | #define pte_file(pte) (pte_val(pte) & L_PTE_FILE) | 423 | #define pte_file(pte) (pte_val(pte) & L_PTE_FILE) |
| 417 | #define pte_to_pgoff(x) (pte_val(x) >> 2) | 424 | #define pte_to_pgoff(x) (pte_val(x) >> 3) |
| 418 | #define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE) | 425 | #define pgoff_to_pte(x) __pte(((x) << 3) | L_PTE_FILE) |
| 419 | 426 | ||
| 420 | #define PTE_FILE_MAX_BITS 30 | 427 | #define PTE_FILE_MAX_BITS 29 |
| 421 | 428 | ||
| 422 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ | 429 | /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */ |
| 423 | /* FIXME: this is not correct */ | 430 | /* FIXME: this is not correct */ |
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 73394e50cbca..e20d80539b42 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h | |||
| @@ -140,6 +140,7 @@ extern void vfp_sync_state(struct thread_info *thread); | |||
| 140 | #define TIF_USING_IWMMXT 17 | 140 | #define TIF_USING_IWMMXT 17 |
| 141 | #define TIF_MEMDIE 18 | 141 | #define TIF_MEMDIE 18 |
| 142 | #define TIF_FREEZE 19 | 142 | #define TIF_FREEZE 19 |
| 143 | #define TIF_RESTORE_SIGMASK 20 | ||
| 143 | 144 | ||
| 144 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) | 145 | #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) |
| 145 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) | 146 | #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) |
| @@ -147,6 +148,7 @@ extern void vfp_sync_state(struct thread_info *thread); | |||
| 147 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) | 148 | #define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG) |
| 148 | #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) | 149 | #define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT) |
| 149 | #define _TIF_FREEZE (1 << TIF_FREEZE) | 150 | #define _TIF_FREEZE (1 << TIF_FREEZE) |
| 151 | #define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) | ||
| 150 | 152 | ||
| 151 | /* | 153 | /* |
| 152 | * Change these and you break ASM code in entry-common.S | 154 | * Change these and you break ASM code in entry-common.S |
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 0e97b8cb77d5..9122c9ee18fb 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h | |||
| @@ -360,8 +360,8 @@ | |||
| 360 | #define __NR_readlinkat (__NR_SYSCALL_BASE+332) | 360 | #define __NR_readlinkat (__NR_SYSCALL_BASE+332) |
| 361 | #define __NR_fchmodat (__NR_SYSCALL_BASE+333) | 361 | #define __NR_fchmodat (__NR_SYSCALL_BASE+333) |
| 362 | #define __NR_faccessat (__NR_SYSCALL_BASE+334) | 362 | #define __NR_faccessat (__NR_SYSCALL_BASE+334) |
| 363 | /* 335 for pselect6 */ | 363 | #define __NR_pselect6 (__NR_SYSCALL_BASE+335) |
| 364 | /* 336 for ppoll */ | 364 | #define __NR_ppoll (__NR_SYSCALL_BASE+336) |
| 365 | #define __NR_unshare (__NR_SYSCALL_BASE+337) | 365 | #define __NR_unshare (__NR_SYSCALL_BASE+337) |
| 366 | #define __NR_set_robust_list (__NR_SYSCALL_BASE+338) | 366 | #define __NR_set_robust_list (__NR_SYSCALL_BASE+338) |
| 367 | #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) | 367 | #define __NR_get_robust_list (__NR_SYSCALL_BASE+339) |
| @@ -372,7 +372,7 @@ | |||
| 372 | #define __NR_vmsplice (__NR_SYSCALL_BASE+343) | 372 | #define __NR_vmsplice (__NR_SYSCALL_BASE+343) |
| 373 | #define __NR_move_pages (__NR_SYSCALL_BASE+344) | 373 | #define __NR_move_pages (__NR_SYSCALL_BASE+344) |
| 374 | #define __NR_getcpu (__NR_SYSCALL_BASE+345) | 374 | #define __NR_getcpu (__NR_SYSCALL_BASE+345) |
| 375 | /* 346 for epoll_pwait */ | 375 | #define __NR_epoll_pwait (__NR_SYSCALL_BASE+346) |
| 376 | #define __NR_kexec_load (__NR_SYSCALL_BASE+347) | 376 | #define __NR_kexec_load (__NR_SYSCALL_BASE+347) |
| 377 | #define __NR_utimensat (__NR_SYSCALL_BASE+348) | 377 | #define __NR_utimensat (__NR_SYSCALL_BASE+348) |
| 378 | #define __NR_signalfd (__NR_SYSCALL_BASE+349) | 378 | #define __NR_signalfd (__NR_SYSCALL_BASE+349) |
| @@ -432,6 +432,7 @@ | |||
| 432 | #define __ARCH_WANT_SYS_SIGPENDING | 432 | #define __ARCH_WANT_SYS_SIGPENDING |
| 433 | #define __ARCH_WANT_SYS_SIGPROCMASK | 433 | #define __ARCH_WANT_SYS_SIGPROCMASK |
| 434 | #define __ARCH_WANT_SYS_RT_SIGACTION | 434 | #define __ARCH_WANT_SYS_RT_SIGACTION |
| 435 | #define __ARCH_WANT_SYS_RT_SIGSUSPEND | ||
| 435 | 436 | ||
| 436 | #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT) | 437 | #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT) |
| 437 | #define __ARCH_WANT_SYS_TIME | 438 | #define __ARCH_WANT_SYS_TIME |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index ff89d0b3abc5..3213c9382b17 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -8,10 +8,12 @@ ifdef CONFIG_DYNAMIC_FTRACE | |||
| 8 | CFLAGS_REMOVE_ftrace.o = -pg | 8 | CFLAGS_REMOVE_ftrace.o = -pg |
| 9 | endif | 9 | endif |
| 10 | 10 | ||
| 11 | CFLAGS_REMOVE_return_address.o = -pg | ||
| 12 | |||
| 11 | # Object file lists. | 13 | # Object file lists. |
| 12 | 14 | ||
| 13 | obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ | 15 | obj-y := compat.o elf.o entry-armv.o entry-common.o irq.o \ |
| 14 | process.o ptrace.o setup.o signal.o \ | 16 | process.o ptrace.o return_address.o setup.o signal.o \ |
| 15 | sys_arm.o stacktrace.o time.o traps.o | 17 | sys_arm.o stacktrace.o time.o traps.o |
| 16 | 18 | ||
| 17 | obj-$(CONFIG_ISA_DMA_API) += dma.o | 19 | obj-$(CONFIG_ISA_DMA_API) += dma.o |
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S index f776e72a4cb8..ecfa98954d1d 100644 --- a/arch/arm/kernel/calls.S +++ b/arch/arm/kernel/calls.S | |||
| @@ -81,7 +81,7 @@ | |||
| 81 | CALL(sys_ni_syscall) /* was sys_ssetmask */ | 81 | CALL(sys_ni_syscall) /* was sys_ssetmask */ |
| 82 | /* 70 */ CALL(sys_setreuid16) | 82 | /* 70 */ CALL(sys_setreuid16) |
| 83 | CALL(sys_setregid16) | 83 | CALL(sys_setregid16) |
| 84 | CALL(sys_sigsuspend_wrapper) | 84 | CALL(sys_sigsuspend) |
| 85 | CALL(sys_sigpending) | 85 | CALL(sys_sigpending) |
| 86 | CALL(sys_sethostname) | 86 | CALL(sys_sethostname) |
| 87 | /* 75 */ CALL(sys_setrlimit) | 87 | /* 75 */ CALL(sys_setrlimit) |
| @@ -188,7 +188,7 @@ | |||
| 188 | CALL(sys_rt_sigpending) | 188 | CALL(sys_rt_sigpending) |
| 189 | CALL(sys_rt_sigtimedwait) | 189 | CALL(sys_rt_sigtimedwait) |
| 190 | CALL(sys_rt_sigqueueinfo) | 190 | CALL(sys_rt_sigqueueinfo) |
| 191 | CALL(sys_rt_sigsuspend_wrapper) | 191 | CALL(sys_rt_sigsuspend) |
| 192 | /* 180 */ CALL(ABI(sys_pread64, sys_oabi_pread64)) | 192 | /* 180 */ CALL(ABI(sys_pread64, sys_oabi_pread64)) |
| 193 | CALL(ABI(sys_pwrite64, sys_oabi_pwrite64)) | 193 | CALL(ABI(sys_pwrite64, sys_oabi_pwrite64)) |
| 194 | CALL(sys_chown16) | 194 | CALL(sys_chown16) |
| @@ -344,8 +344,8 @@ | |||
| 344 | CALL(sys_readlinkat) | 344 | CALL(sys_readlinkat) |
| 345 | CALL(sys_fchmodat) | 345 | CALL(sys_fchmodat) |
| 346 | CALL(sys_faccessat) | 346 | CALL(sys_faccessat) |
| 347 | /* 335 */ CALL(sys_ni_syscall) /* eventually pselect6 */ | 347 | /* 335 */ CALL(sys_pselect6) |
| 348 | CALL(sys_ni_syscall) /* eventually ppoll */ | 348 | CALL(sys_ppoll) |
| 349 | CALL(sys_unshare) | 349 | CALL(sys_unshare) |
| 350 | CALL(sys_set_robust_list) | 350 | CALL(sys_set_robust_list) |
| 351 | CALL(sys_get_robust_list) | 351 | CALL(sys_get_robust_list) |
| @@ -355,7 +355,7 @@ | |||
| 355 | CALL(sys_vmsplice) | 355 | CALL(sys_vmsplice) |
| 356 | CALL(sys_move_pages) | 356 | CALL(sys_move_pages) |
| 357 | /* 345 */ CALL(sys_getcpu) | 357 | /* 345 */ CALL(sys_getcpu) |
| 358 | CALL(sys_ni_syscall) /* eventually epoll_pwait */ | 358 | CALL(sys_epoll_pwait) |
| 359 | CALL(sys_kexec_load) | 359 | CALL(sys_kexec_load) |
| 360 | CALL(sys_utimensat) | 360 | CALL(sys_utimensat) |
| 361 | CALL(sys_signalfd) | 361 | CALL(sys_signalfd) |
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c index 99995c2b2312..769abe15cf91 100644 --- a/arch/arm/kernel/crunch.c +++ b/arch/arm/kernel/crunch.c | |||
| @@ -31,7 +31,7 @@ void crunch_task_release(struct thread_info *thread) | |||
| 31 | 31 | ||
| 32 | static int crunch_enabled(u32 devcfg) | 32 | static int crunch_enabled(u32 devcfg) |
| 33 | { | 33 | { |
| 34 | return !!(devcfg & EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE); | 34 | return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) | 37 | static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) |
| @@ -56,11 +56,16 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t) | |||
| 56 | break; | 56 | break; |
| 57 | 57 | ||
| 58 | case THREAD_NOTIFY_SWITCH: | 58 | case THREAD_NOTIFY_SWITCH: |
| 59 | devcfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); | 59 | devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG); |
| 60 | if (crunch_enabled(devcfg) || crunch_owner == crunch_state) { | 60 | if (crunch_enabled(devcfg) || crunch_owner == crunch_state) { |
| 61 | devcfg ^= EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE; | 61 | /* |
| 62 | * We don't use ep93xx_syscon_swlocked_write() here | ||
| 63 | * because we are on the context switch path and | ||
| 64 | * preemption is already disabled. | ||
| 65 | */ | ||
| 66 | devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA; | ||
| 62 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 67 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); |
| 63 | __raw_writel(devcfg, EP93XX_SYSCON_DEVICE_CONFIG); | 68 | __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG); |
| 64 | } | 69 | } |
| 65 | break; | 70 | break; |
| 66 | } | 71 | } |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index df19e8bf2e4a..3657c5328a5b 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -380,16 +380,6 @@ sys_clone_wrapper: | |||
| 380 | b sys_clone | 380 | b sys_clone |
| 381 | ENDPROC(sys_clone_wrapper) | 381 | ENDPROC(sys_clone_wrapper) |
| 382 | 382 | ||
| 383 | sys_sigsuspend_wrapper: | ||
| 384 | add r3, sp, #S_OFF | ||
| 385 | b sys_sigsuspend | ||
| 386 | ENDPROC(sys_sigsuspend_wrapper) | ||
| 387 | |||
| 388 | sys_rt_sigsuspend_wrapper: | ||
| 389 | add r2, sp, #S_OFF | ||
| 390 | b sys_rt_sigsuspend | ||
| 391 | ENDPROC(sys_rt_sigsuspend_wrapper) | ||
| 392 | |||
| 393 | sys_sigreturn_wrapper: | 383 | sys_sigreturn_wrapper: |
| 394 | add r0, sp, #S_OFF | 384 | add r0, sp, #S_OFF |
| 395 | b sys_sigreturn | 385 | b sys_sigreturn |
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c new file mode 100644 index 000000000000..df246da4ceca --- /dev/null +++ b/arch/arm/kernel/return_address.c | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/kernel/return_address.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de> | ||
| 5 | * for Pengutronix | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License version 2 as published by | ||
| 9 | * the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/module.h> | ||
| 12 | |||
| 13 | #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) | ||
| 14 | #include <linux/sched.h> | ||
| 15 | |||
| 16 | #include <asm/stacktrace.h> | ||
| 17 | |||
| 18 | struct return_address_data { | ||
| 19 | unsigned int level; | ||
| 20 | void *addr; | ||
| 21 | }; | ||
| 22 | |||
| 23 | static int save_return_addr(struct stackframe *frame, void *d) | ||
| 24 | { | ||
| 25 | struct return_address_data *data = d; | ||
| 26 | |||
| 27 | if (!data->level) { | ||
| 28 | data->addr = (void *)frame->lr; | ||
| 29 | |||
| 30 | return 1; | ||
| 31 | } else { | ||
| 32 | --data->level; | ||
| 33 | return 0; | ||
| 34 | } | ||
| 35 | } | ||
| 36 | |||
| 37 | void *return_address(unsigned int level) | ||
| 38 | { | ||
| 39 | struct return_address_data data; | ||
| 40 | struct stackframe frame; | ||
| 41 | register unsigned long current_sp asm ("sp"); | ||
| 42 | |||
| 43 | data.level = level + 1; | ||
| 44 | |||
| 45 | frame.fp = (unsigned long)__builtin_frame_address(0); | ||
| 46 | frame.sp = current_sp; | ||
| 47 | frame.lr = (unsigned long)__builtin_return_address(0); | ||
| 48 | frame.pc = (unsigned long)return_address; | ||
| 49 | |||
| 50 | walk_stackframe(&frame, save_return_addr, &data); | ||
| 51 | |||
| 52 | if (!data.level) | ||
| 53 | return data.addr; | ||
| 54 | else | ||
| 55 | return NULL; | ||
| 56 | } | ||
| 57 | |||
| 58 | #else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */ | ||
| 59 | |||
| 60 | #if defined(CONFIG_ARM_UNWIND) | ||
| 61 | #warning "TODO: return_address should use unwind tables" | ||
| 62 | #endif | ||
| 63 | |||
| 64 | void *return_address(unsigned int level) | ||
| 65 | { | ||
| 66 | return NULL; | ||
| 67 | } | ||
| 68 | |||
| 69 | #endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */ | ||
| 70 | |||
| 71 | EXPORT_SYMBOL_GPL(return_address); | ||
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c index 93bb4247b7ed..e27ee1f701d5 100644 --- a/arch/arm/kernel/signal.c +++ b/arch/arm/kernel/signal.c | |||
| @@ -47,57 +47,22 @@ const unsigned long sigreturn_codes[7] = { | |||
| 47 | MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN, | 47 | MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN, |
| 48 | }; | 48 | }; |
| 49 | 49 | ||
| 50 | static int do_signal(sigset_t *oldset, struct pt_regs * regs, int syscall); | ||
| 51 | |||
| 52 | /* | 50 | /* |
| 53 | * atomically swap in the new signal mask, and wait for a signal. | 51 | * atomically swap in the new signal mask, and wait for a signal. |
| 54 | */ | 52 | */ |
| 55 | asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask, struct pt_regs *regs) | 53 | asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask) |
| 56 | { | 54 | { |
| 57 | sigset_t saveset; | ||
| 58 | |||
| 59 | mask &= _BLOCKABLE; | 55 | mask &= _BLOCKABLE; |
| 60 | spin_lock_irq(¤t->sighand->siglock); | 56 | spin_lock_irq(¤t->sighand->siglock); |
| 61 | saveset = current->blocked; | 57 | current->saved_sigmask = current->blocked; |
| 62 | siginitset(¤t->blocked, mask); | 58 | siginitset(¤t->blocked, mask); |
| 63 | recalc_sigpending(); | 59 | recalc_sigpending(); |
| 64 | spin_unlock_irq(¤t->sighand->siglock); | 60 | spin_unlock_irq(¤t->sighand->siglock); |
| 65 | regs->ARM_r0 = -EINTR; | ||
| 66 | |||
| 67 | while (1) { | ||
| 68 | current->state = TASK_INTERRUPTIBLE; | ||
| 69 | schedule(); | ||
| 70 | if (do_signal(&saveset, regs, 0)) | ||
| 71 | return regs->ARM_r0; | ||
| 72 | } | ||
| 73 | } | ||
| 74 | |||
| 75 | asmlinkage int | ||
| 76 | sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize, struct pt_regs *regs) | ||
| 77 | { | ||
| 78 | sigset_t saveset, newset; | ||
| 79 | |||
| 80 | /* XXX: Don't preclude handling different sized sigset_t's. */ | ||
| 81 | if (sigsetsize != sizeof(sigset_t)) | ||
| 82 | return -EINVAL; | ||
| 83 | |||
| 84 | if (copy_from_user(&newset, unewset, sizeof(newset))) | ||
| 85 | return -EFAULT; | ||
| 86 | sigdelsetmask(&newset, ~_BLOCKABLE); | ||
| 87 | |||
| 88 | spin_lock_irq(¤t->sighand->siglock); | ||
| 89 | saveset = current->blocked; | ||
| 90 | current->blocked = newset; | ||
| 91 | recalc_sigpending(); | ||
| 92 | spin_unlock_irq(¤t->sighand->siglock); | ||
| 93 | regs->ARM_r0 = -EINTR; | ||
| 94 | 61 | ||
| 95 | while (1) { | 62 | current->state = TASK_INTERRUPTIBLE; |
| 96 | current->state = TASK_INTERRUPTIBLE; | 63 | schedule(); |
| 97 | schedule(); | 64 | set_restore_sigmask(); |
| 98 | if (do_signal(&saveset, regs, 0)) | 65 | return -ERESTARTNOHAND; |
| 99 | return regs->ARM_r0; | ||
| 100 | } | ||
| 101 | } | 66 | } |
| 102 | 67 | ||
| 103 | asmlinkage int | 68 | asmlinkage int |
| @@ -545,7 +510,7 @@ static inline void setup_syscall_restart(struct pt_regs *regs) | |||
| 545 | /* | 510 | /* |
| 546 | * OK, we're invoking a handler | 511 | * OK, we're invoking a handler |
| 547 | */ | 512 | */ |
| 548 | static void | 513 | static int |
| 549 | handle_signal(unsigned long sig, struct k_sigaction *ka, | 514 | handle_signal(unsigned long sig, struct k_sigaction *ka, |
| 550 | siginfo_t *info, sigset_t *oldset, | 515 | siginfo_t *info, sigset_t *oldset, |
| 551 | struct pt_regs * regs, int syscall) | 516 | struct pt_regs * regs, int syscall) |
| @@ -596,7 +561,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, | |||
| 596 | 561 | ||
| 597 | if (ret != 0) { | 562 | if (ret != 0) { |
| 598 | force_sigsegv(sig, tsk); | 563 | force_sigsegv(sig, tsk); |
| 599 | return; | 564 | return ret; |
| 600 | } | 565 | } |
| 601 | 566 | ||
| 602 | /* | 567 | /* |
| @@ -610,6 +575,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, | |||
| 610 | recalc_sigpending(); | 575 | recalc_sigpending(); |
| 611 | spin_unlock_irq(&tsk->sighand->siglock); | 576 | spin_unlock_irq(&tsk->sighand->siglock); |
| 612 | 577 | ||
| 578 | return 0; | ||
| 613 | } | 579 | } |
| 614 | 580 | ||
| 615 | /* | 581 | /* |
| @@ -621,7 +587,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka, | |||
| 621 | * the kernel can handle, and then we build all the user-level signal handling | 587 | * the kernel can handle, and then we build all the user-level signal handling |
| 622 | * stack-frames in one go after that. | 588 | * stack-frames in one go after that. |
| 623 | */ | 589 | */ |
| 624 | static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall) | 590 | static void do_signal(struct pt_regs *regs, int syscall) |
| 625 | { | 591 | { |
| 626 | struct k_sigaction ka; | 592 | struct k_sigaction ka; |
| 627 | siginfo_t info; | 593 | siginfo_t info; |
| @@ -634,7 +600,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall) | |||
| 634 | * if so. | 600 | * if so. |
| 635 | */ | 601 | */ |
| 636 | if (!user_mode(regs)) | 602 | if (!user_mode(regs)) |
| 637 | return 0; | 603 | return; |
| 638 | 604 | ||
| 639 | if (try_to_freeze()) | 605 | if (try_to_freeze()) |
| 640 | goto no_signal; | 606 | goto no_signal; |
| @@ -643,9 +609,24 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall) | |||
| 643 | 609 | ||
| 644 | signr = get_signal_to_deliver(&info, &ka, regs, NULL); | 610 | signr = get_signal_to_deliver(&info, &ka, regs, NULL); |
| 645 | if (signr > 0) { | 611 | if (signr > 0) { |
| 646 | handle_signal(signr, &ka, &info, oldset, regs, syscall); | 612 | sigset_t *oldset; |
| 613 | |||
| 614 | if (test_thread_flag(TIF_RESTORE_SIGMASK)) | ||
| 615 | oldset = ¤t->saved_sigmask; | ||
| 616 | else | ||
| 617 | oldset = ¤t->blocked; | ||
| 618 | if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) { | ||
| 619 | /* | ||
| 620 | * A signal was successfully delivered; the saved | ||
| 621 | * sigmask will have been stored in the signal frame, | ||
| 622 | * and will be restored by sigreturn, so we can simply | ||
| 623 | * clear the TIF_RESTORE_SIGMASK flag. | ||
| 624 | */ | ||
| 625 | if (test_thread_flag(TIF_RESTORE_SIGMASK)) | ||
| 626 | clear_thread_flag(TIF_RESTORE_SIGMASK); | ||
| 627 | } | ||
| 647 | single_step_set(current); | 628 | single_step_set(current); |
| 648 | return 1; | 629 | return; |
| 649 | } | 630 | } |
| 650 | 631 | ||
| 651 | no_signal: | 632 | no_signal: |
| @@ -697,14 +678,21 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall) | |||
| 697 | regs->ARM_r0 == -ERESTARTNOINTR) { | 678 | regs->ARM_r0 == -ERESTARTNOINTR) { |
| 698 | setup_syscall_restart(regs); | 679 | setup_syscall_restart(regs); |
| 699 | } | 680 | } |
| 681 | |||
| 682 | /* If there's no signal to deliver, we just put the saved sigmask | ||
| 683 | * back. | ||
| 684 | */ | ||
| 685 | if (test_thread_flag(TIF_RESTORE_SIGMASK)) { | ||
| 686 | clear_thread_flag(TIF_RESTORE_SIGMASK); | ||
| 687 | sigprocmask(SIG_SETMASK, ¤t->saved_sigmask, NULL); | ||
| 688 | } | ||
| 700 | } | 689 | } |
| 701 | single_step_set(current); | 690 | single_step_set(current); |
| 702 | return 0; | ||
| 703 | } | 691 | } |
| 704 | 692 | ||
| 705 | asmlinkage void | 693 | asmlinkage void |
| 706 | do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall) | 694 | do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall) |
| 707 | { | 695 | { |
| 708 | if (thread_flags & _TIF_SIGPENDING) | 696 | if (thread_flags & _TIF_SIGPENDING) |
| 709 | do_signal(¤t->blocked, regs, syscall); | 697 | do_signal(regs, syscall); |
| 710 | } | 698 | } |
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index 9f444e5cc165..20b7411e47fd 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c | |||
| @@ -21,7 +21,7 @@ | |||
| 21 | * Note that with framepointer enabled, even the leaf functions have the same | 21 | * Note that with framepointer enabled, even the leaf functions have the same |
| 22 | * prologue and epilogue, therefore we can ignore the LR value in this case. | 22 | * prologue and epilogue, therefore we can ignore the LR value in this case. |
| 23 | */ | 23 | */ |
| 24 | int unwind_frame(struct stackframe *frame) | 24 | int notrace unwind_frame(struct stackframe *frame) |
| 25 | { | 25 | { |
| 26 | unsigned long high, low; | 26 | unsigned long high, low; |
| 27 | unsigned long fp = frame->fp; | 27 | unsigned long fp = frame->fp; |
| @@ -43,7 +43,7 @@ int unwind_frame(struct stackframe *frame) | |||
| 43 | } | 43 | } |
| 44 | #endif | 44 | #endif |
| 45 | 45 | ||
| 46 | void walk_stackframe(struct stackframe *frame, | 46 | void notrace walk_stackframe(struct stackframe *frame, |
| 47 | int (*fn)(struct stackframe *, void *), void *data) | 47 | int (*fn)(struct stackframe *, void *), void *data) |
| 48 | { | 48 | { |
| 49 | while (1) { | 49 | while (1) { |
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 323b47f2b52f..a24d824c428b 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig | |||
| @@ -23,6 +23,12 @@ config ARCH_AT91SAM9261 | |||
| 23 | select GENERIC_TIME | 23 | select GENERIC_TIME |
| 24 | select GENERIC_CLOCKEVENTS | 24 | select GENERIC_CLOCKEVENTS |
| 25 | 25 | ||
| 26 | config ARCH_AT91SAM9G10 | ||
| 27 | bool "AT91SAM9G10" | ||
| 28 | select CPU_ARM926T | ||
| 29 | select GENERIC_TIME | ||
| 30 | select GENERIC_CLOCKEVENTS | ||
| 31 | |||
| 26 | config ARCH_AT91SAM9263 | 32 | config ARCH_AT91SAM9263 |
| 27 | bool "AT91SAM9263" | 33 | bool "AT91SAM9263" |
| 28 | select CPU_ARM926T | 34 | select CPU_ARM926T |
| @@ -41,6 +47,12 @@ config ARCH_AT91SAM9G20 | |||
| 41 | select GENERIC_TIME | 47 | select GENERIC_TIME |
| 42 | select GENERIC_CLOCKEVENTS | 48 | select GENERIC_CLOCKEVENTS |
| 43 | 49 | ||
| 50 | config ARCH_AT91SAM9G45 | ||
| 51 | bool "AT91SAM9G45" | ||
| 52 | select CPU_ARM926T | ||
| 53 | select GENERIC_TIME | ||
| 54 | select GENERIC_CLOCKEVENTS | ||
| 55 | |||
| 44 | config ARCH_AT91CAP9 | 56 | config ARCH_AT91CAP9 |
| 45 | bool "AT91CAP9" | 57 | bool "AT91CAP9" |
| 46 | select CPU_ARM926T | 58 | select CPU_ARM926T |
| @@ -144,6 +156,13 @@ config MACH_YL9200 | |||
| 144 | help | 156 | help |
| 145 | Select this if you are using the ucDragon YL-9200 board. | 157 | Select this if you are using the ucDragon YL-9200 board. |
| 146 | 158 | ||
| 159 | config MACH_CPUAT91 | ||
| 160 | bool "Eukrea CPUAT91" | ||
| 161 | depends on ARCH_AT91RM9200 | ||
| 162 | help | ||
| 163 | Select this if you are using the Eukrea Electromatique's | ||
| 164 | CPUAT91 board <http://www.eukrea.com/>. | ||
| 165 | |||
| 147 | endif | 166 | endif |
| 148 | 167 | ||
| 149 | # ---------------------------------------------------------- | 168 | # ---------------------------------------------------------- |
| @@ -205,6 +224,13 @@ config MACH_QIL_A9260 | |||
| 205 | Select this if you are using a Calao Systems QIL-A9260 Board. | 224 | Select this if you are using a Calao Systems QIL-A9260 Board. |
| 206 | <http://www.calao-systems.com> | 225 | <http://www.calao-systems.com> |
| 207 | 226 | ||
| 227 | config MACH_CPU9260 | ||
| 228 | bool "Eukrea CPU9260 board" | ||
| 229 | depends on ARCH_AT91SAM9260 | ||
| 230 | help | ||
| 231 | Select this if you are using a Eukrea Electromatique's | ||
| 232 | CPU9260 Board <http://www.eukrea.com/> | ||
| 233 | |||
| 208 | endif | 234 | endif |
| 209 | 235 | ||
| 210 | # ---------------------------------------------------------- | 236 | # ---------------------------------------------------------- |
| @@ -224,6 +250,21 @@ endif | |||
| 224 | 250 | ||
| 225 | # ---------------------------------------------------------- | 251 | # ---------------------------------------------------------- |
| 226 | 252 | ||
| 253 | if ARCH_AT91SAM9G10 | ||
| 254 | |||
| 255 | comment "AT91SAM9G10 Board Type" | ||
| 256 | |||
| 257 | config MACH_AT91SAM9G10EK | ||
| 258 | bool "Atmel AT91SAM9G10-EK Evaluation Kit" | ||
| 259 | depends on ARCH_AT91SAM9G10 | ||
| 260 | help | ||
| 261 | Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit. | ||
| 262 | <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588> | ||
| 263 | |||
| 264 | endif | ||
| 265 | |||
| 266 | # ---------------------------------------------------------- | ||
| 267 | |||
| 227 | if ARCH_AT91SAM9263 | 268 | if ARCH_AT91SAM9263 |
| 228 | 269 | ||
| 229 | comment "AT91SAM9263 Board Type" | 270 | comment "AT91SAM9263 Board Type" |
| @@ -276,6 +317,29 @@ config MACH_AT91SAM9G20EK | |||
| 276 | help | 317 | help |
| 277 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit. | 318 | Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit. |
| 278 | 319 | ||
| 320 | config MACH_CPU9G20 | ||
| 321 | bool "Eukrea CPU9G20 board" | ||
| 322 | depends on ARCH_AT91SAM9G20 | ||
| 323 | help | ||
| 324 | Select this if you are using a Eukrea Electromatique's | ||
| 325 | CPU9G20 Board <http://www.eukrea.com/> | ||
| 326 | |||
| 327 | endif | ||
| 328 | |||
| 329 | # ---------------------------------------------------------- | ||
| 330 | |||
| 331 | if ARCH_AT91SAM9G45 | ||
| 332 | |||
| 333 | comment "AT91SAM9G45 Board Type" | ||
| 334 | |||
| 335 | config MACH_AT91SAM9G45EKES | ||
| 336 | bool "Atmel AT91SAM9G45-EKES Evaluation Kit" | ||
| 337 | depends on ARCH_AT91SAM9G45 | ||
| 338 | help | ||
| 339 | Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit. | ||
| 340 | "ES" at the end of the name means that this board is an | ||
| 341 | Engineering Sample. | ||
| 342 | |||
| 279 | endif | 343 | endif |
| 280 | 344 | ||
| 281 | # ---------------------------------------------------------- | 345 | # ---------------------------------------------------------- |
| @@ -315,13 +379,13 @@ comment "AT91 Board Options" | |||
| 315 | 379 | ||
| 316 | config MTD_AT91_DATAFLASH_CARD | 380 | config MTD_AT91_DATAFLASH_CARD |
| 317 | bool "Enable DataFlash Card support" | 381 | bool "Enable DataFlash Card support" |
| 318 | depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) | 382 | depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926) |
| 319 | help | 383 | help |
| 320 | Enable support for the DataFlash card. | 384 | Enable support for the DataFlash card. |
| 321 | 385 | ||
| 322 | config MTD_NAND_ATMEL_BUSWIDTH_16 | 386 | config MTD_NAND_ATMEL_BUSWIDTH_16 |
| 323 | bool "Enable 16-bit data bus interface to NAND flash" | 387 | bool "Enable 16-bit data bus interface to NAND flash" |
| 324 | depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK) | 388 | depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK) |
| 325 | help | 389 | help |
| 326 | On AT91SAM926x boards both types of NAND flash can be present | 390 | On AT91SAM926x boards both types of NAND flash can be present |
| 327 | (8 and 16 bit data bus width). | 391 | (8 and 16 bit data bus width). |
| @@ -383,7 +447,7 @@ config AT91_EARLY_USART2 | |||
| 383 | 447 | ||
| 384 | config AT91_EARLY_USART3 | 448 | config AT91_EARLY_USART3 |
| 385 | bool "USART3" | 449 | bool "USART3" |
| 386 | depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20) | 450 | depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45) |
| 387 | 451 | ||
| 388 | config AT91_EARLY_USART4 | 452 | config AT91_EARLY_USART4 |
| 389 | bool "USART4" | 453 | bool "USART4" |
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index c69ff237fd14..a6ed015d82ed 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile | |||
| @@ -13,9 +13,11 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o | |||
| 13 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o | 13 | obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o |
| 14 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o | 14 | obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o |
| 15 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o | 15 | obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o |
| 16 | obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o | ||
| 16 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o | 17 | obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o |
| 17 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o | 18 | obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o |
| 18 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o | 19 | obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o |
| 20 | obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o | ||
| 19 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o | 21 | obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o |
| 20 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o | 22 | obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o |
| 21 | 23 | ||
| @@ -32,6 +34,7 @@ obj-$(CONFIG_MACH_KAFA) += board-kafa.o | |||
| 32 | obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o | 34 | obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o |
| 33 | obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o | 35 | obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o |
| 34 | obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o | 36 | obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o |
| 37 | obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o | ||
| 35 | 38 | ||
| 36 | # AT91SAM9260 board-specific support | 39 | # AT91SAM9260 board-specific support |
| 37 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o | 40 | obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o |
| @@ -40,9 +43,11 @@ obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o | |||
| 40 | obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o | 43 | obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o |
| 41 | obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o | 44 | obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o |
| 42 | obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o | 45 | obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o |
| 46 | obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o | ||
| 43 | 47 | ||
| 44 | # AT91SAM9261 board-specific support | 48 | # AT91SAM9261 board-specific support |
| 45 | obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o | 49 | obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o |
| 50 | obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o | ||
| 46 | 51 | ||
| 47 | # AT91SAM9263 board-specific support | 52 | # AT91SAM9263 board-specific support |
| 48 | obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o | 53 | obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o |
| @@ -54,6 +59,10 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o | |||
| 54 | 59 | ||
| 55 | # AT91SAM9G20 board-specific support | 60 | # AT91SAM9G20 board-specific support |
| 56 | obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o | 61 | obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o |
| 62 | obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o | ||
| 63 | |||
| 64 | # AT91SAM9G45 board-specific support | ||
| 65 | obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o | ||
| 57 | 66 | ||
| 58 | # AT91CAP9 board-specific support | 67 | # AT91CAP9 board-specific support |
| 59 | obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o | 68 | obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o |
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot index 071a2506a69f..3462b815054a 100644 --- a/arch/arm/mach-at91/Makefile.boot +++ b/arch/arm/mach-at91/Makefile.boot | |||
| @@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y) | |||
| 7 | zreladdr-y := 0x70008000 | 7 | zreladdr-y := 0x70008000 |
| 8 | params_phys-y := 0x70000100 | 8 | params_phys-y := 0x70000100 |
| 9 | initrd_phys-y := 0x70410000 | 9 | initrd_phys-y := 0x70410000 |
| 10 | else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y) | ||
| 11 | zreladdr-y := 0x70008000 | ||
| 12 | params_phys-y := 0x70000100 | ||
| 13 | initrd_phys-y := 0x70410000 | ||
| 10 | else | 14 | else |
| 11 | zreladdr-y := 0x20008000 | 15 | zreladdr-y := 0x20008000 |
| 12 | params_phys-y := 0x20000100 | 16 | params_phys-y := 0x20000100 |
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c index d74c9ac007e7..ee4ea0e720cf 100644 --- a/arch/arm/mach-at91/at91sam9260_devices.c +++ b/arch/arm/mach-at91/at91sam9260_devices.c | |||
| @@ -1113,6 +1113,122 @@ void __init at91_set_serial_console(unsigned portnr) {} | |||
| 1113 | void __init at91_add_device_serial(void) {} | 1113 | void __init at91_add_device_serial(void) {} |
| 1114 | #endif | 1114 | #endif |
| 1115 | 1115 | ||
| 1116 | /* -------------------------------------------------------------------- | ||
| 1117 | * CF/IDE | ||
| 1118 | * -------------------------------------------------------------------- */ | ||
| 1119 | |||
| 1120 | #if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \ | ||
| 1121 | defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \ | ||
| 1122 | defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) | ||
| 1123 | |||
| 1124 | static struct at91_cf_data cf0_data; | ||
| 1125 | |||
| 1126 | static struct resource cf0_resources[] = { | ||
| 1127 | [0] = { | ||
| 1128 | .start = AT91_CHIPSELECT_4, | ||
| 1129 | .end = AT91_CHIPSELECT_4 + SZ_256M - 1, | ||
| 1130 | .flags = IORESOURCE_MEM, | ||
| 1131 | } | ||
| 1132 | }; | ||
| 1133 | |||
| 1134 | static struct platform_device cf0_device = { | ||
| 1135 | .id = 0, | ||
| 1136 | .dev = { | ||
| 1137 | .platform_data = &cf0_data, | ||
| 1138 | }, | ||
| 1139 | .resource = cf0_resources, | ||
| 1140 | .num_resources = ARRAY_SIZE(cf0_resources), | ||
| 1141 | }; | ||
| 1142 | |||
| 1143 | static struct at91_cf_data cf1_data; | ||
| 1144 | |||
| 1145 | static struct resource cf1_resources[] = { | ||
| 1146 | [0] = { | ||
| 1147 | .start = AT91_CHIPSELECT_5, | ||
| 1148 | .end = AT91_CHIPSELECT_5 + SZ_256M - 1, | ||
| 1149 | .flags = IORESOURCE_MEM, | ||
| 1150 | } | ||
| 1151 | }; | ||
| 1152 | |||
| 1153 | static struct platform_device cf1_device = { | ||
| 1154 | .id = 1, | ||
| 1155 | .dev = { | ||
| 1156 | .platform_data = &cf1_data, | ||
| 1157 | }, | ||
| 1158 | .resource = cf1_resources, | ||
| 1159 | .num_resources = ARRAY_SIZE(cf1_resources), | ||
| 1160 | }; | ||
| 1161 | |||
| 1162 | void __init at91_add_device_cf(struct at91_cf_data *data) | ||
| 1163 | { | ||
| 1164 | struct platform_device *pdev; | ||
| 1165 | unsigned long csa; | ||
| 1166 | |||
| 1167 | if (!data) | ||
| 1168 | return; | ||
| 1169 | |||
| 1170 | csa = at91_sys_read(AT91_MATRIX_EBICSA); | ||
| 1171 | |||
| 1172 | switch (data->chipselect) { | ||
| 1173 | case 4: | ||
| 1174 | at91_set_multi_drive(AT91_PIN_PC8, 0); | ||
| 1175 | at91_set_A_periph(AT91_PIN_PC8, 0); | ||
| 1176 | csa |= AT91_MATRIX_CS4A_SMC_CF1; | ||
| 1177 | cf0_data = *data; | ||
| 1178 | pdev = &cf0_device; | ||
| 1179 | break; | ||
| 1180 | case 5: | ||
| 1181 | at91_set_multi_drive(AT91_PIN_PC9, 0); | ||
| 1182 | at91_set_A_periph(AT91_PIN_PC9, 0); | ||
| 1183 | csa |= AT91_MATRIX_CS5A_SMC_CF2; | ||
| 1184 | cf1_data = *data; | ||
| 1185 | pdev = &cf1_device; | ||
| 1186 | break; | ||
| 1187 | default: | ||
| 1188 | printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n", | ||
| 1189 | data->chipselect); | ||
| 1190 | return; | ||
| 1191 | } | ||
| 1192 | |||
| 1193 | at91_sys_write(AT91_MATRIX_EBICSA, csa); | ||
| 1194 | |||
| 1195 | if (data->rst_pin) { | ||
| 1196 | at91_set_multi_drive(data->rst_pin, 0); | ||
| 1197 | at91_set_gpio_output(data->rst_pin, 1); | ||
| 1198 | } | ||
| 1199 | |||
| 1200 | if (data->irq_pin) { | ||
| 1201 | at91_set_gpio_input(data->irq_pin, 0); | ||
| 1202 | at91_set_deglitch(data->irq_pin, 1); | ||
| 1203 | } | ||
| 1204 | |||
| 1205 | if (data->det_pin) { | ||
| 1206 | at91_set_gpio_input(data->det_pin, 0); | ||
| 1207 | at91_set_deglitch(data->det_pin, 1); | ||
| 1208 | } | ||
| 1209 | |||
| 1210 | at91_set_B_periph(AT91_PIN_PC6, 0); /* CFCE1 */ | ||
| 1211 | at91_set_B_periph(AT91_PIN_PC7, 0); /* CFCE2 */ | ||
| 1212 | at91_set_A_periph(AT91_PIN_PC10, 0); /* CFRNW */ | ||
| 1213 | at91_set_A_periph(AT91_PIN_PC15, 1); /* NWAIT */ | ||
| 1214 | |||
| 1215 | if (data->flags & AT91_CF_TRUE_IDE) | ||
| 1216 | #if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) | ||
| 1217 | pdev->name = "pata_at91"; | ||
| 1218 | #elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | ||
| 1219 | pdev->name = "at91_ide"; | ||
| 1220 | #else | ||
| 1221 | #warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91" | ||
| 1222 | #endif | ||
| 1223 | else | ||
| 1224 | pdev->name = "at91_cf"; | ||
| 1225 | |||
| 1226 | platform_device_register(pdev); | ||
| 1227 | } | ||
| 1228 | |||
| 1229 | #else | ||
| 1230 | void __init at91_add_device_cf(struct at91_cf_data * data) {} | ||
| 1231 | #endif | ||
| 1116 | 1232 | ||
| 1117 | /* -------------------------------------------------------------------- */ | 1233 | /* -------------------------------------------------------------------- */ |
| 1118 | /* | 1234 | /* |
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 3acd7d7e6a42..4ecf37996c77 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c | |||
| @@ -16,6 +16,7 @@ | |||
| 16 | #include <asm/irq.h> | 16 | #include <asm/irq.h> |
| 17 | #include <asm/mach/arch.h> | 17 | #include <asm/mach/arch.h> |
| 18 | #include <asm/mach/map.h> | 18 | #include <asm/mach/map.h> |
| 19 | #include <mach/cpu.h> | ||
| 19 | #include <mach/at91sam9261.h> | 20 | #include <mach/at91sam9261.h> |
| 20 | #include <mach/at91_pmc.h> | 21 | #include <mach/at91_pmc.h> |
| 21 | #include <mach/at91_rstc.h> | 22 | #include <mach/at91_rstc.h> |
| @@ -30,7 +31,11 @@ static struct map_desc at91sam9261_io_desc[] __initdata = { | |||
| 30 | .pfn = __phys_to_pfn(AT91_BASE_SYS), | 31 | .pfn = __phys_to_pfn(AT91_BASE_SYS), |
| 31 | .length = SZ_16K, | 32 | .length = SZ_16K, |
| 32 | .type = MT_DEVICE, | 33 | .type = MT_DEVICE, |
| 33 | }, { | 34 | }, |
| 35 | }; | ||
| 36 | |||
| 37 | static struct map_desc at91sam9261_sram_desc[] __initdata = { | ||
| 38 | { | ||
| 34 | .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, | 39 | .virtual = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE, |
| 35 | .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), | 40 | .pfn = __phys_to_pfn(AT91SAM9261_SRAM_BASE), |
| 36 | .length = AT91SAM9261_SRAM_SIZE, | 41 | .length = AT91SAM9261_SRAM_SIZE, |
| @@ -38,6 +43,15 @@ static struct map_desc at91sam9261_io_desc[] __initdata = { | |||
| 38 | }, | 43 | }, |
| 39 | }; | 44 | }; |
| 40 | 45 | ||
| 46 | static struct map_desc at91sam9g10_sram_desc[] __initdata = { | ||
| 47 | { | ||
| 48 | .virtual = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE, | ||
| 49 | .pfn = __phys_to_pfn(AT91SAM9G10_SRAM_BASE), | ||
| 50 | .length = AT91SAM9G10_SRAM_SIZE, | ||
| 51 | .type = MT_DEVICE, | ||
| 52 | }, | ||
| 53 | }; | ||
| 54 | |||
| 41 | /* -------------------------------------------------------------------- | 55 | /* -------------------------------------------------------------------- |
| 42 | * Clocks | 56 | * Clocks |
| 43 | * -------------------------------------------------------------------- */ | 57 | * -------------------------------------------------------------------- */ |
| @@ -263,6 +277,12 @@ void __init at91sam9261_initialize(unsigned long main_clock) | |||
| 263 | /* Map peripherals */ | 277 | /* Map peripherals */ |
| 264 | iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); | 278 | iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc)); |
| 265 | 279 | ||
| 280 | if (cpu_is_at91sam9g10()) | ||
| 281 | iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc)); | ||
| 282 | else | ||
| 283 | iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc)); | ||
| 284 | |||
| 285 | |||
| 266 | at91_arch_reset = at91sam9261_reset; | 286 | at91_arch_reset = at91sam9261_reset; |
| 267 | pm_power_off = at91sam9261_poweroff; | 287 | pm_power_off = at91sam9261_poweroff; |
| 268 | at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) | 288 | at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1) |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index b7f233242315..55719a974276 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -707,9 +707,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | |||
| 707 | * AC97 | 707 | * AC97 |
| 708 | * -------------------------------------------------------------------- */ | 708 | * -------------------------------------------------------------------- */ |
| 709 | 709 | ||
| 710 | #if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE) | 710 | #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE) |
| 711 | static u64 ac97_dmamask = DMA_BIT_MASK(32); | 711 | static u64 ac97_dmamask = DMA_BIT_MASK(32); |
| 712 | static struct atmel_ac97_data ac97_data; | 712 | static struct ac97c_platform_data ac97_data; |
| 713 | 713 | ||
| 714 | static struct resource ac97_resources[] = { | 714 | static struct resource ac97_resources[] = { |
| 715 | [0] = { | 715 | [0] = { |
| @@ -725,8 +725,8 @@ static struct resource ac97_resources[] = { | |||
| 725 | }; | 725 | }; |
| 726 | 726 | ||
| 727 | static struct platform_device at91sam9263_ac97_device = { | 727 | static struct platform_device at91sam9263_ac97_device = { |
| 728 | .name = "ac97c", | 728 | .name = "atmel_ac97c", |
| 729 | .id = 1, | 729 | .id = 0, |
| 730 | .dev = { | 730 | .dev = { |
| 731 | .dma_mask = &ac97_dmamask, | 731 | .dma_mask = &ac97_dmamask, |
| 732 | .coherent_dma_mask = DMA_BIT_MASK(32), | 732 | .coherent_dma_mask = DMA_BIT_MASK(32), |
| @@ -736,7 +736,7 @@ static struct platform_device at91sam9263_ac97_device = { | |||
| 736 | .num_resources = ARRAY_SIZE(ac97_resources), | 736 | .num_resources = ARRAY_SIZE(ac97_resources), |
| 737 | }; | 737 | }; |
| 738 | 738 | ||
| 739 | void __init at91_add_device_ac97(struct atmel_ac97_data *data) | 739 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) |
| 740 | { | 740 | { |
| 741 | if (!data) | 741 | if (!data) |
| 742 | return; | 742 | return; |
| @@ -750,11 +750,11 @@ void __init at91_add_device_ac97(struct atmel_ac97_data *data) | |||
| 750 | if (data->reset_pin) | 750 | if (data->reset_pin) |
| 751 | at91_set_gpio_output(data->reset_pin, 0); | 751 | at91_set_gpio_output(data->reset_pin, 0); |
| 752 | 752 | ||
| 753 | ac97_data = *ek_data; | 753 | ac97_data = *data; |
| 754 | platform_device_register(&at91sam9263_ac97_device); | 754 | platform_device_register(&at91sam9263_ac97_device); |
| 755 | } | 755 | } |
| 756 | #else | 756 | #else |
| 757 | void __init at91_add_device_ac97(struct atmel_ac97_data *data) {} | 757 | void __init at91_add_device_ac97(struct ac97c_platform_data *data) {} |
| 758 | #endif | 758 | #endif |
| 759 | 759 | ||
| 760 | 760 | ||
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c new file mode 100644 index 000000000000..85166b7e69a1 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45.c | |||
| @@ -0,0 +1,360 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific setup code for the AT91SAM9G45 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/pm.h> | ||
| 15 | |||
| 16 | #include <asm/irq.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <asm/mach/map.h> | ||
| 19 | #include <mach/at91sam9g45.h> | ||
| 20 | #include <mach/at91_pmc.h> | ||
| 21 | #include <mach/at91_rstc.h> | ||
| 22 | #include <mach/at91_shdwc.h> | ||
| 23 | |||
| 24 | #include "generic.h" | ||
| 25 | #include "clock.h" | ||
| 26 | |||
| 27 | static struct map_desc at91sam9g45_io_desc[] __initdata = { | ||
| 28 | { | ||
| 29 | .virtual = AT91_VA_BASE_SYS, | ||
| 30 | .pfn = __phys_to_pfn(AT91_BASE_SYS), | ||
| 31 | .length = SZ_16K, | ||
| 32 | .type = MT_DEVICE, | ||
| 33 | }, { | ||
| 34 | .virtual = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE, | ||
| 35 | .pfn = __phys_to_pfn(AT91SAM9G45_SRAM_BASE), | ||
| 36 | .length = AT91SAM9G45_SRAM_SIZE, | ||
| 37 | .type = MT_DEVICE, | ||
| 38 | } | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* -------------------------------------------------------------------- | ||
| 42 | * Clocks | ||
| 43 | * -------------------------------------------------------------------- */ | ||
| 44 | |||
| 45 | /* | ||
| 46 | * The peripheral clocks. | ||
| 47 | */ | ||
| 48 | static struct clk pioA_clk = { | ||
| 49 | .name = "pioA_clk", | ||
| 50 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOA, | ||
| 51 | .type = CLK_TYPE_PERIPHERAL, | ||
| 52 | }; | ||
| 53 | static struct clk pioB_clk = { | ||
| 54 | .name = "pioB_clk", | ||
| 55 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOB, | ||
| 56 | .type = CLK_TYPE_PERIPHERAL, | ||
| 57 | }; | ||
| 58 | static struct clk pioC_clk = { | ||
| 59 | .name = "pioC_clk", | ||
| 60 | .pmc_mask = 1 << AT91SAM9G45_ID_PIOC, | ||
| 61 | .type = CLK_TYPE_PERIPHERAL, | ||
| 62 | }; | ||
| 63 | static struct clk pioDE_clk = { | ||
| 64 | .name = "pioDE_clk", | ||
| 65 | .pmc_mask = 1 << AT91SAM9G45_ID_PIODE, | ||
| 66 | .type = CLK_TYPE_PERIPHERAL, | ||
| 67 | }; | ||
| 68 | static struct clk usart0_clk = { | ||
| 69 | .name = "usart0_clk", | ||
| 70 | .pmc_mask = 1 << AT91SAM9G45_ID_US0, | ||
| 71 | .type = CLK_TYPE_PERIPHERAL, | ||
| 72 | }; | ||
| 73 | static struct clk usart1_clk = { | ||
| 74 | .name = "usart1_clk", | ||
| 75 | .pmc_mask = 1 << AT91SAM9G45_ID_US1, | ||
| 76 | .type = CLK_TYPE_PERIPHERAL, | ||
| 77 | }; | ||
| 78 | static struct clk usart2_clk = { | ||
| 79 | .name = "usart2_clk", | ||
| 80 | .pmc_mask = 1 << AT91SAM9G45_ID_US2, | ||
| 81 | .type = CLK_TYPE_PERIPHERAL, | ||
| 82 | }; | ||
| 83 | static struct clk usart3_clk = { | ||
| 84 | .name = "usart3_clk", | ||
| 85 | .pmc_mask = 1 << AT91SAM9G45_ID_US3, | ||
| 86 | .type = CLK_TYPE_PERIPHERAL, | ||
| 87 | }; | ||
| 88 | static struct clk mmc0_clk = { | ||
| 89 | .name = "mci0_clk", | ||
| 90 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI0, | ||
| 91 | .type = CLK_TYPE_PERIPHERAL, | ||
| 92 | }; | ||
| 93 | static struct clk twi0_clk = { | ||
| 94 | .name = "twi0_clk", | ||
| 95 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI0, | ||
| 96 | .type = CLK_TYPE_PERIPHERAL, | ||
| 97 | }; | ||
| 98 | static struct clk twi1_clk = { | ||
| 99 | .name = "twi1_clk", | ||
| 100 | .pmc_mask = 1 << AT91SAM9G45_ID_TWI1, | ||
| 101 | .type = CLK_TYPE_PERIPHERAL, | ||
| 102 | }; | ||
| 103 | static struct clk spi0_clk = { | ||
| 104 | .name = "spi0_clk", | ||
| 105 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI0, | ||
| 106 | .type = CLK_TYPE_PERIPHERAL, | ||
| 107 | }; | ||
| 108 | static struct clk spi1_clk = { | ||
| 109 | .name = "spi1_clk", | ||
| 110 | .pmc_mask = 1 << AT91SAM9G45_ID_SPI1, | ||
| 111 | .type = CLK_TYPE_PERIPHERAL, | ||
| 112 | }; | ||
| 113 | static struct clk ssc0_clk = { | ||
| 114 | .name = "ssc0_clk", | ||
| 115 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC0, | ||
| 116 | .type = CLK_TYPE_PERIPHERAL, | ||
| 117 | }; | ||
| 118 | static struct clk ssc1_clk = { | ||
| 119 | .name = "ssc1_clk", | ||
| 120 | .pmc_mask = 1 << AT91SAM9G45_ID_SSC1, | ||
| 121 | .type = CLK_TYPE_PERIPHERAL, | ||
| 122 | }; | ||
| 123 | static struct clk tcb_clk = { | ||
| 124 | .name = "tcb_clk", | ||
| 125 | .pmc_mask = 1 << AT91SAM9G45_ID_TCB, | ||
| 126 | .type = CLK_TYPE_PERIPHERAL, | ||
| 127 | }; | ||
| 128 | static struct clk pwm_clk = { | ||
| 129 | .name = "pwm_clk", | ||
| 130 | .pmc_mask = 1 << AT91SAM9G45_ID_PWMC, | ||
| 131 | .type = CLK_TYPE_PERIPHERAL, | ||
| 132 | }; | ||
| 133 | static struct clk tsc_clk = { | ||
| 134 | .name = "tsc_clk", | ||
| 135 | .pmc_mask = 1 << AT91SAM9G45_ID_TSC, | ||
| 136 | .type = CLK_TYPE_PERIPHERAL, | ||
| 137 | }; | ||
| 138 | static struct clk dma_clk = { | ||
| 139 | .name = "dma_clk", | ||
| 140 | .pmc_mask = 1 << AT91SAM9G45_ID_DMA, | ||
| 141 | .type = CLK_TYPE_PERIPHERAL, | ||
| 142 | }; | ||
| 143 | static struct clk uhphs_clk = { | ||
| 144 | .name = "uhphs_clk", | ||
| 145 | .pmc_mask = 1 << AT91SAM9G45_ID_UHPHS, | ||
| 146 | .type = CLK_TYPE_PERIPHERAL, | ||
| 147 | }; | ||
| 148 | static struct clk lcdc_clk = { | ||
| 149 | .name = "lcdc_clk", | ||
| 150 | .pmc_mask = 1 << AT91SAM9G45_ID_LCDC, | ||
| 151 | .type = CLK_TYPE_PERIPHERAL, | ||
| 152 | }; | ||
| 153 | static struct clk ac97_clk = { | ||
| 154 | .name = "ac97_clk", | ||
| 155 | .pmc_mask = 1 << AT91SAM9G45_ID_AC97C, | ||
| 156 | .type = CLK_TYPE_PERIPHERAL, | ||
| 157 | }; | ||
| 158 | static struct clk macb_clk = { | ||
| 159 | .name = "macb_clk", | ||
| 160 | .pmc_mask = 1 << AT91SAM9G45_ID_EMAC, | ||
| 161 | .type = CLK_TYPE_PERIPHERAL, | ||
| 162 | }; | ||
| 163 | static struct clk isi_clk = { | ||
| 164 | .name = "isi_clk", | ||
| 165 | .pmc_mask = 1 << AT91SAM9G45_ID_ISI, | ||
| 166 | .type = CLK_TYPE_PERIPHERAL, | ||
| 167 | }; | ||
| 168 | static struct clk udphs_clk = { | ||
| 169 | .name = "udphs_clk", | ||
| 170 | .pmc_mask = 1 << AT91SAM9G45_ID_UDPHS, | ||
| 171 | .type = CLK_TYPE_PERIPHERAL, | ||
| 172 | }; | ||
| 173 | static struct clk mmc1_clk = { | ||
| 174 | .name = "mci1_clk", | ||
| 175 | .pmc_mask = 1 << AT91SAM9G45_ID_MCI1, | ||
| 176 | .type = CLK_TYPE_PERIPHERAL, | ||
| 177 | }; | ||
| 178 | |||
| 179 | /* One additional fake clock for ohci */ | ||
| 180 | static struct clk ohci_clk = { | ||
| 181 | .name = "ohci_clk", | ||
| 182 | .pmc_mask = 0, | ||
| 183 | .type = CLK_TYPE_PERIPHERAL, | ||
| 184 | .parent = &uhphs_clk, | ||
| 185 | }; | ||
| 186 | |||
| 187 | static struct clk *periph_clocks[] __initdata = { | ||
| 188 | &pioA_clk, | ||
| 189 | &pioB_clk, | ||
| 190 | &pioC_clk, | ||
| 191 | &pioDE_clk, | ||
| 192 | &usart0_clk, | ||
| 193 | &usart1_clk, | ||
| 194 | &usart2_clk, | ||
| 195 | &usart3_clk, | ||
| 196 | &mmc0_clk, | ||
| 197 | &twi0_clk, | ||
| 198 | &twi1_clk, | ||
| 199 | &spi0_clk, | ||
| 200 | &spi1_clk, | ||
| 201 | &ssc0_clk, | ||
| 202 | &ssc1_clk, | ||
| 203 | &tcb_clk, | ||
| 204 | &pwm_clk, | ||
| 205 | &tsc_clk, | ||
| 206 | &dma_clk, | ||
| 207 | &uhphs_clk, | ||
| 208 | &lcdc_clk, | ||
| 209 | &ac97_clk, | ||
| 210 | &macb_clk, | ||
| 211 | &isi_clk, | ||
| 212 | &udphs_clk, | ||
| 213 | &mmc1_clk, | ||
| 214 | // irq0 | ||
| 215 | &ohci_clk, | ||
| 216 | }; | ||
| 217 | |||
| 218 | /* | ||
| 219 | * The two programmable clocks. | ||
| 220 | * You must configure pin multiplexing to bring these signals out. | ||
| 221 | */ | ||
| 222 | static struct clk pck0 = { | ||
| 223 | .name = "pck0", | ||
| 224 | .pmc_mask = AT91_PMC_PCK0, | ||
| 225 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 226 | .id = 0, | ||
| 227 | }; | ||
| 228 | static struct clk pck1 = { | ||
| 229 | .name = "pck1", | ||
| 230 | .pmc_mask = AT91_PMC_PCK1, | ||
| 231 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 232 | .id = 1, | ||
| 233 | }; | ||
| 234 | |||
| 235 | static void __init at91sam9g45_register_clocks(void) | ||
| 236 | { | ||
| 237 | int i; | ||
| 238 | |||
| 239 | for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) | ||
| 240 | clk_register(periph_clocks[i]); | ||
| 241 | |||
| 242 | clk_register(&pck0); | ||
| 243 | clk_register(&pck1); | ||
| 244 | } | ||
| 245 | |||
| 246 | /* -------------------------------------------------------------------- | ||
| 247 | * GPIO | ||
| 248 | * -------------------------------------------------------------------- */ | ||
| 249 | |||
| 250 | static struct at91_gpio_bank at91sam9g45_gpio[] = { | ||
| 251 | { | ||
| 252 | .id = AT91SAM9G45_ID_PIOA, | ||
| 253 | .offset = AT91_PIOA, | ||
| 254 | .clock = &pioA_clk, | ||
| 255 | }, { | ||
| 256 | .id = AT91SAM9G45_ID_PIOB, | ||
| 257 | .offset = AT91_PIOB, | ||
| 258 | .clock = &pioB_clk, | ||
| 259 | }, { | ||
| 260 | .id = AT91SAM9G45_ID_PIOC, | ||
| 261 | .offset = AT91_PIOC, | ||
| 262 | .clock = &pioC_clk, | ||
| 263 | }, { | ||
| 264 | .id = AT91SAM9G45_ID_PIODE, | ||
| 265 | .offset = AT91_PIOD, | ||
| 266 | .clock = &pioDE_clk, | ||
| 267 | }, { | ||
| 268 | .id = AT91SAM9G45_ID_PIODE, | ||
| 269 | .offset = AT91_PIOE, | ||
| 270 | .clock = &pioDE_clk, | ||
| 271 | } | ||
| 272 | }; | ||
| 273 | |||
| 274 | static void at91sam9g45_reset(void) | ||
| 275 | { | ||
| 276 | at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST); | ||
| 277 | } | ||
| 278 | |||
| 279 | static void at91sam9g45_poweroff(void) | ||
| 280 | { | ||
| 281 | at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW); | ||
| 282 | } | ||
| 283 | |||
| 284 | |||
| 285 | /* -------------------------------------------------------------------- | ||
| 286 | * AT91SAM9G45 processor initialization | ||
| 287 | * -------------------------------------------------------------------- */ | ||
| 288 | |||
| 289 | void __init at91sam9g45_initialize(unsigned long main_clock) | ||
| 290 | { | ||
| 291 | /* Map peripherals */ | ||
| 292 | iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc)); | ||
| 293 | |||
| 294 | at91_arch_reset = at91sam9g45_reset; | ||
| 295 | pm_power_off = at91sam9g45_poweroff; | ||
| 296 | at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0); | ||
| 297 | |||
| 298 | /* Init clock subsystem */ | ||
| 299 | at91_clock_init(main_clock); | ||
| 300 | |||
| 301 | /* Register the processor-specific clocks */ | ||
| 302 | at91sam9g45_register_clocks(); | ||
| 303 | |||
| 304 | /* Register GPIO subsystem */ | ||
| 305 | at91_gpio_init(at91sam9g45_gpio, 5); | ||
| 306 | } | ||
| 307 | |||
| 308 | /* -------------------------------------------------------------------- | ||
| 309 | * Interrupt initialization | ||
| 310 | * -------------------------------------------------------------------- */ | ||
| 311 | |||
| 312 | /* | ||
| 313 | * The default interrupt priority levels (0 = lowest, 7 = highest). | ||
| 314 | */ | ||
| 315 | static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { | ||
| 316 | 7, /* Advanced Interrupt Controller (FIQ) */ | ||
| 317 | 7, /* System Peripherals */ | ||
| 318 | 1, /* Parallel IO Controller A */ | ||
| 319 | 1, /* Parallel IO Controller B */ | ||
| 320 | 1, /* Parallel IO Controller C */ | ||
| 321 | 1, /* Parallel IO Controller D and E */ | ||
| 322 | 0, | ||
| 323 | 5, /* USART 0 */ | ||
| 324 | 5, /* USART 1 */ | ||
| 325 | 5, /* USART 2 */ | ||
| 326 | 5, /* USART 3 */ | ||
| 327 | 0, /* Multimedia Card Interface 0 */ | ||
| 328 | 6, /* Two-Wire Interface 0 */ | ||
| 329 | 6, /* Two-Wire Interface 1 */ | ||
| 330 | 5, /* Serial Peripheral Interface 0 */ | ||
| 331 | 5, /* Serial Peripheral Interface 1 */ | ||
| 332 | 4, /* Serial Synchronous Controller 0 */ | ||
| 333 | 4, /* Serial Synchronous Controller 1 */ | ||
| 334 | 0, /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | ||
| 335 | 0, /* Pulse Width Modulation Controller */ | ||
| 336 | 0, /* Touch Screen Controller */ | ||
| 337 | 0, /* DMA Controller */ | ||
| 338 | 2, /* USB Host High Speed port */ | ||
| 339 | 3, /* LDC Controller */ | ||
| 340 | 5, /* AC97 Controller */ | ||
| 341 | 3, /* Ethernet */ | ||
| 342 | 0, /* Image Sensor Interface */ | ||
| 343 | 2, /* USB Device High speed port */ | ||
| 344 | 0, | ||
| 345 | 0, /* Multimedia Card Interface 1 */ | ||
| 346 | 0, | ||
| 347 | 0, /* Advanced Interrupt Controller (IRQ0) */ | ||
| 348 | }; | ||
| 349 | |||
| 350 | void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS]) | ||
| 351 | { | ||
| 352 | if (!priority) | ||
| 353 | priority = at91sam9g45_default_irq_priority; | ||
| 354 | |||
| 355 | /* Initialize the AIC interrupt controller */ | ||
| 356 | at91_aic_init(priority); | ||
| 357 | |||
| 358 | /* Enable GPIO interrupts */ | ||
| 359 | at91_gpio_irq_setup(); | ||
| 360 | } | ||
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c new file mode 100644 index 000000000000..d746e8621bc2 --- /dev/null +++ b/arch/arm/mach-at91/at91sam9g45_devices.c | |||
| @@ -0,0 +1,1230 @@ | |||
| 1 | /* | ||
| 2 | * On-Chip devices setup code for the AT91SAM9G45 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | #include <asm/mach/arch.h> | ||
| 13 | #include <asm/mach/map.h> | ||
| 14 | |||
| 15 | #include <linux/dma-mapping.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/i2c-gpio.h> | ||
| 18 | |||
| 19 | #include <linux/fb.h> | ||
| 20 | #include <video/atmel_lcdc.h> | ||
| 21 | |||
| 22 | #include <mach/board.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/at91sam9g45.h> | ||
| 25 | #include <mach/at91sam9g45_matrix.h> | ||
| 26 | #include <mach/at91sam9_smc.h> | ||
| 27 | |||
| 28 | #include "generic.h" | ||
| 29 | |||
| 30 | |||
| 31 | /* -------------------------------------------------------------------- | ||
| 32 | * USB Host (OHCI) | ||
| 33 | * -------------------------------------------------------------------- */ | ||
| 34 | |||
| 35 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 36 | static u64 ohci_dmamask = DMA_BIT_MASK(32); | ||
| 37 | static struct at91_usbh_data usbh_ohci_data; | ||
| 38 | |||
| 39 | static struct resource usbh_ohci_resources[] = { | ||
| 40 | [0] = { | ||
| 41 | .start = AT91SAM9G45_OHCI_BASE, | ||
| 42 | .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1, | ||
| 43 | .flags = IORESOURCE_MEM, | ||
| 44 | }, | ||
| 45 | [1] = { | ||
| 46 | .start = AT91SAM9G45_ID_UHPHS, | ||
| 47 | .end = AT91SAM9G45_ID_UHPHS, | ||
| 48 | .flags = IORESOURCE_IRQ, | ||
| 49 | }, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static struct platform_device at91_usbh_ohci_device = { | ||
| 53 | .name = "at91_ohci", | ||
| 54 | .id = -1, | ||
| 55 | .dev = { | ||
| 56 | .dma_mask = &ohci_dmamask, | ||
| 57 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 58 | .platform_data = &usbh_ohci_data, | ||
| 59 | }, | ||
| 60 | .resource = usbh_ohci_resources, | ||
| 61 | .num_resources = ARRAY_SIZE(usbh_ohci_resources), | ||
| 62 | }; | ||
| 63 | |||
| 64 | void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) | ||
| 65 | { | ||
| 66 | int i; | ||
| 67 | |||
| 68 | if (!data) | ||
| 69 | return; | ||
| 70 | |||
| 71 | /* Enable VBus control for UHP ports */ | ||
| 72 | for (i = 0; i < data->ports; i++) { | ||
| 73 | if (data->vbus_pin[i]) | ||
| 74 | at91_set_gpio_output(data->vbus_pin[i], 0); | ||
| 75 | } | ||
| 76 | |||
| 77 | usbh_ohci_data = *data; | ||
| 78 | platform_device_register(&at91_usbh_ohci_device); | ||
| 79 | } | ||
| 80 | #else | ||
| 81 | void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {} | ||
| 82 | #endif | ||
| 83 | |||
| 84 | |||
| 85 | /* -------------------------------------------------------------------- | ||
| 86 | * USB HS Device (Gadget) | ||
| 87 | * -------------------------------------------------------------------- */ | ||
| 88 | |||
| 89 | #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE) | ||
| 90 | static struct resource usba_udc_resources[] = { | ||
| 91 | [0] = { | ||
| 92 | .start = AT91SAM9G45_UDPHS_FIFO, | ||
| 93 | .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1, | ||
| 94 | .flags = IORESOURCE_MEM, | ||
| 95 | }, | ||
| 96 | [1] = { | ||
| 97 | .start = AT91SAM9G45_BASE_UDPHS, | ||
| 98 | .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1, | ||
| 99 | .flags = IORESOURCE_MEM, | ||
| 100 | }, | ||
| 101 | [2] = { | ||
| 102 | .start = AT91SAM9G45_ID_UDPHS, | ||
| 103 | .end = AT91SAM9G45_ID_UDPHS, | ||
| 104 | .flags = IORESOURCE_IRQ, | ||
| 105 | }, | ||
| 106 | }; | ||
| 107 | |||
| 108 | #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \ | ||
| 109 | [idx] = { \ | ||
| 110 | .name = nam, \ | ||
| 111 | .index = idx, \ | ||
| 112 | .fifo_size = maxpkt, \ | ||
| 113 | .nr_banks = maxbk, \ | ||
| 114 | .can_dma = dma, \ | ||
| 115 | .can_isoc = isoc, \ | ||
| 116 | } | ||
| 117 | |||
| 118 | static struct usba_ep_data usba_udc_ep[] __initdata = { | ||
| 119 | EP("ep0", 0, 64, 1, 0, 0), | ||
| 120 | EP("ep1", 1, 1024, 2, 1, 1), | ||
| 121 | EP("ep2", 2, 1024, 2, 1, 1), | ||
| 122 | EP("ep3", 3, 1024, 3, 1, 0), | ||
| 123 | EP("ep4", 4, 1024, 3, 1, 0), | ||
| 124 | EP("ep5", 5, 1024, 3, 1, 1), | ||
| 125 | EP("ep6", 6, 1024, 3, 1, 1), | ||
| 126 | }; | ||
| 127 | |||
| 128 | #undef EP | ||
| 129 | |||
| 130 | /* | ||
| 131 | * pdata doesn't have room for any endpoints, so we need to | ||
| 132 | * append room for the ones we need right after it. | ||
| 133 | */ | ||
| 134 | static struct { | ||
| 135 | struct usba_platform_data pdata; | ||
| 136 | struct usba_ep_data ep[7]; | ||
| 137 | } usba_udc_data; | ||
| 138 | |||
| 139 | static struct platform_device at91_usba_udc_device = { | ||
| 140 | .name = "atmel_usba_udc", | ||
| 141 | .id = -1, | ||
| 142 | .dev = { | ||
| 143 | .platform_data = &usba_udc_data.pdata, | ||
| 144 | }, | ||
| 145 | .resource = usba_udc_resources, | ||
| 146 | .num_resources = ARRAY_SIZE(usba_udc_resources), | ||
| 147 | }; | ||
| 148 | |||
| 149 | void __init at91_add_device_usba(struct usba_platform_data *data) | ||
| 150 | { | ||
| 151 | usba_udc_data.pdata.vbus_pin = -EINVAL; | ||
| 152 | usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep); | ||
| 153 | memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));; | ||
| 154 | |||
| 155 | if (data && data->vbus_pin > 0) { | ||
| 156 | at91_set_gpio_input(data->vbus_pin, 0); | ||
| 157 | at91_set_deglitch(data->vbus_pin, 1); | ||
| 158 | usba_udc_data.pdata.vbus_pin = data->vbus_pin; | ||
| 159 | } | ||
| 160 | |||
| 161 | /* Pullup pin is handled internally by USB device peripheral */ | ||
| 162 | |||
| 163 | /* Clocks */ | ||
| 164 | at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk"); | ||
| 165 | at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk"); | ||
| 166 | |||
| 167 | platform_device_register(&at91_usba_udc_device); | ||
| 168 | } | ||
| 169 | #else | ||
| 170 | void __init at91_add_device_usba(struct usba_platform_data *data) {} | ||
| 171 | #endif | ||
| 172 | |||
| 173 | |||
| 174 | /* -------------------------------------------------------------------- | ||
| 175 | * Ethernet | ||
| 176 | * -------------------------------------------------------------------- */ | ||
| 177 | |||
| 178 | #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE) | ||
| 179 | static u64 eth_dmamask = DMA_BIT_MASK(32); | ||
| 180 | static struct at91_eth_data eth_data; | ||
| 181 | |||
| 182 | static struct resource eth_resources[] = { | ||
| 183 | [0] = { | ||
| 184 | .start = AT91SAM9G45_BASE_EMAC, | ||
| 185 | .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1, | ||
| 186 | .flags = IORESOURCE_MEM, | ||
| 187 | }, | ||
| 188 | [1] = { | ||
| 189 | .start = AT91SAM9G45_ID_EMAC, | ||
| 190 | .end = AT91SAM9G45_ID_EMAC, | ||
| 191 | .flags = IORESOURCE_IRQ, | ||
| 192 | }, | ||
| 193 | }; | ||
| 194 | |||
| 195 | static struct platform_device at91sam9g45_eth_device = { | ||
| 196 | .name = "macb", | ||
| 197 | .id = -1, | ||
| 198 | .dev = { | ||
| 199 | .dma_mask = ð_dmamask, | ||
| 200 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 201 | .platform_data = ð_data, | ||
| 202 | }, | ||
| 203 | .resource = eth_resources, | ||
| 204 | .num_resources = ARRAY_SIZE(eth_resources), | ||
| 205 | }; | ||
| 206 | |||
| 207 | void __init at91_add_device_eth(struct at91_eth_data *data) | ||
| 208 | { | ||
| 209 | if (!data) | ||
| 210 | return; | ||
| 211 | |||
| 212 | if (data->phy_irq_pin) { | ||
| 213 | at91_set_gpio_input(data->phy_irq_pin, 0); | ||
| 214 | at91_set_deglitch(data->phy_irq_pin, 1); | ||
| 215 | } | ||
| 216 | |||
| 217 | /* Pins used for MII and RMII */ | ||
| 218 | at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ | ||
| 219 | at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ | ||
| 220 | at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ | ||
| 221 | at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ | ||
| 222 | at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ | ||
| 223 | at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ | ||
| 224 | at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ | ||
| 225 | at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ | ||
| 226 | at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ | ||
| 227 | at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ | ||
| 228 | |||
| 229 | if (!data->is_rmii) { | ||
| 230 | at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ | ||
| 231 | at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ | ||
| 232 | at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ | ||
| 233 | at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ | ||
| 234 | at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ | ||
| 235 | at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ | ||
| 236 | at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ | ||
| 237 | at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ | ||
| 238 | } | ||
| 239 | |||
| 240 | eth_data = *data; | ||
| 241 | platform_device_register(&at91sam9g45_eth_device); | ||
| 242 | } | ||
| 243 | #else | ||
| 244 | void __init at91_add_device_eth(struct at91_eth_data *data) {} | ||
| 245 | #endif | ||
| 246 | |||
| 247 | |||
| 248 | /* -------------------------------------------------------------------- | ||
| 249 | * NAND / SmartMedia | ||
| 250 | * -------------------------------------------------------------------- */ | ||
| 251 | |||
| 252 | #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE) | ||
| 253 | static struct atmel_nand_data nand_data; | ||
| 254 | |||
| 255 | #define NAND_BASE AT91_CHIPSELECT_3 | ||
| 256 | |||
| 257 | static struct resource nand_resources[] = { | ||
| 258 | [0] = { | ||
| 259 | .start = NAND_BASE, | ||
| 260 | .end = NAND_BASE + SZ_256M - 1, | ||
| 261 | .flags = IORESOURCE_MEM, | ||
| 262 | }, | ||
| 263 | [1] = { | ||
| 264 | .start = AT91_BASE_SYS + AT91_ECC, | ||
| 265 | .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1, | ||
| 266 | .flags = IORESOURCE_MEM, | ||
| 267 | } | ||
| 268 | }; | ||
| 269 | |||
| 270 | static struct platform_device at91sam9g45_nand_device = { | ||
| 271 | .name = "atmel_nand", | ||
| 272 | .id = -1, | ||
| 273 | .dev = { | ||
| 274 | .platform_data = &nand_data, | ||
| 275 | }, | ||
| 276 | .resource = nand_resources, | ||
| 277 | .num_resources = ARRAY_SIZE(nand_resources), | ||
| 278 | }; | ||
| 279 | |||
| 280 | void __init at91_add_device_nand(struct atmel_nand_data *data) | ||
| 281 | { | ||
| 282 | unsigned long csa; | ||
| 283 | |||
| 284 | if (!data) | ||
| 285 | return; | ||
| 286 | |||
| 287 | csa = at91_sys_read(AT91_MATRIX_EBICSA); | ||
| 288 | at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); | ||
| 289 | |||
| 290 | /* enable pin */ | ||
| 291 | if (data->enable_pin) | ||
| 292 | at91_set_gpio_output(data->enable_pin, 1); | ||
| 293 | |||
| 294 | /* ready/busy pin */ | ||
| 295 | if (data->rdy_pin) | ||
| 296 | at91_set_gpio_input(data->rdy_pin, 1); | ||
| 297 | |||
| 298 | /* card detect pin */ | ||
| 299 | if (data->det_pin) | ||
| 300 | at91_set_gpio_input(data->det_pin, 1); | ||
| 301 | |||
| 302 | nand_data = *data; | ||
| 303 | platform_device_register(&at91sam9g45_nand_device); | ||
| 304 | } | ||
| 305 | #else | ||
| 306 | void __init at91_add_device_nand(struct atmel_nand_data *data) {} | ||
| 307 | #endif | ||
| 308 | |||
| 309 | |||
| 310 | /* -------------------------------------------------------------------- | ||
| 311 | * TWI (i2c) | ||
| 312 | * -------------------------------------------------------------------- */ | ||
| 313 | |||
| 314 | /* | ||
| 315 | * Prefer the GPIO code since the TWI controller isn't robust | ||
| 316 | * (gets overruns and underruns under load) and can only issue | ||
| 317 | * repeated STARTs in one scenario (the driver doesn't yet handle them). | ||
| 318 | */ | ||
| 319 | #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE) | ||
| 320 | static struct i2c_gpio_platform_data pdata_i2c0 = { | ||
| 321 | .sda_pin = AT91_PIN_PA20, | ||
| 322 | .sda_is_open_drain = 1, | ||
| 323 | .scl_pin = AT91_PIN_PA21, | ||
| 324 | .scl_is_open_drain = 1, | ||
| 325 | .udelay = 2, /* ~100 kHz */ | ||
| 326 | }; | ||
| 327 | |||
| 328 | static struct platform_device at91sam9g45_twi0_device = { | ||
| 329 | .name = "i2c-gpio", | ||
| 330 | .id = 0, | ||
| 331 | .dev.platform_data = &pdata_i2c0, | ||
| 332 | }; | ||
| 333 | |||
| 334 | static struct i2c_gpio_platform_data pdata_i2c1 = { | ||
| 335 | .sda_pin = AT91_PIN_PB10, | ||
| 336 | .sda_is_open_drain = 1, | ||
| 337 | .scl_pin = AT91_PIN_PB11, | ||
| 338 | .scl_is_open_drain = 1, | ||
| 339 | .udelay = 2, /* ~100 kHz */ | ||
| 340 | }; | ||
| 341 | |||
| 342 | static struct platform_device at91sam9g45_twi1_device = { | ||
| 343 | .name = "i2c-gpio", | ||
| 344 | .id = 1, | ||
| 345 | .dev.platform_data = &pdata_i2c1, | ||
| 346 | }; | ||
| 347 | |||
| 348 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) | ||
| 349 | { | ||
| 350 | i2c_register_board_info(i2c_id, devices, nr_devices); | ||
| 351 | |||
| 352 | if (i2c_id == 0) { | ||
| 353 | at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */ | ||
| 354 | at91_set_multi_drive(AT91_PIN_PA20, 1); | ||
| 355 | |||
| 356 | at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */ | ||
| 357 | at91_set_multi_drive(AT91_PIN_PA21, 1); | ||
| 358 | |||
| 359 | platform_device_register(&at91sam9g45_twi0_device); | ||
| 360 | } else { | ||
| 361 | at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */ | ||
| 362 | at91_set_multi_drive(AT91_PIN_PB10, 1); | ||
| 363 | |||
| 364 | at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */ | ||
| 365 | at91_set_multi_drive(AT91_PIN_PB11, 1); | ||
| 366 | |||
| 367 | platform_device_register(&at91sam9g45_twi1_device); | ||
| 368 | } | ||
| 369 | } | ||
| 370 | |||
| 371 | #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE) | ||
| 372 | static struct resource twi0_resources[] = { | ||
| 373 | [0] = { | ||
| 374 | .start = AT91SAM9G45_BASE_TWI0, | ||
| 375 | .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1, | ||
| 376 | .flags = IORESOURCE_MEM, | ||
| 377 | }, | ||
| 378 | [1] = { | ||
| 379 | .start = AT91SAM9G45_ID_TWI0, | ||
| 380 | .end = AT91SAM9G45_ID_TWI0, | ||
| 381 | .flags = IORESOURCE_IRQ, | ||
| 382 | }, | ||
| 383 | }; | ||
| 384 | |||
| 385 | static struct platform_device at91sam9g45_twi0_device = { | ||
| 386 | .name = "at91_i2c", | ||
| 387 | .id = 0, | ||
| 388 | .resource = twi0_resources, | ||
| 389 | .num_resources = ARRAY_SIZE(twi0_resources), | ||
| 390 | }; | ||
| 391 | |||
| 392 | static struct resource twi1_resources[] = { | ||
| 393 | [0] = { | ||
| 394 | .start = AT91SAM9G45_BASE_TWI1, | ||
| 395 | .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1, | ||
| 396 | .flags = IORESOURCE_MEM, | ||
| 397 | }, | ||
| 398 | [1] = { | ||
| 399 | .start = AT91SAM9G45_ID_TWI1, | ||
| 400 | .end = AT91SAM9G45_ID_TWI1, | ||
| 401 | .flags = IORESOURCE_IRQ, | ||
| 402 | }, | ||
| 403 | }; | ||
| 404 | |||
| 405 | static struct platform_device at91sam9g45_twi1_device = { | ||
| 406 | .name = "at91_i2c", | ||
| 407 | .id = 1, | ||
| 408 | .resource = twi1_resources, | ||
| 409 | .num_resources = ARRAY_SIZE(twi1_resources), | ||
| 410 | }; | ||
| 411 | |||
| 412 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) | ||
| 413 | { | ||
| 414 | i2c_register_board_info(i2c_id, devices, nr_devices); | ||
| 415 | |||
| 416 | /* pins used for TWI interface */ | ||
| 417 | if (i2c_id == 0) { | ||
| 418 | at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */ | ||
| 419 | at91_set_multi_drive(AT91_PIN_PA20, 1); | ||
| 420 | |||
| 421 | at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */ | ||
| 422 | at91_set_multi_drive(AT91_PIN_PA21, 1); | ||
| 423 | |||
| 424 | platform_device_register(&at91sam9g45_twi0_device); | ||
| 425 | } else { | ||
| 426 | at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */ | ||
| 427 | at91_set_multi_drive(AT91_PIN_PB10, 1); | ||
| 428 | |||
| 429 | at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */ | ||
| 430 | at91_set_multi_drive(AT91_PIN_PB11, 1); | ||
| 431 | |||
| 432 | platform_device_register(&at91sam9g45_twi1_device); | ||
| 433 | } | ||
| 434 | } | ||
| 435 | #else | ||
| 436 | void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {} | ||
| 437 | #endif | ||
| 438 | |||
| 439 | |||
| 440 | /* -------------------------------------------------------------------- | ||
| 441 | * SPI | ||
| 442 | * -------------------------------------------------------------------- */ | ||
| 443 | |||
| 444 | #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE) | ||
| 445 | static u64 spi_dmamask = DMA_BIT_MASK(32); | ||
| 446 | |||
| 447 | static struct resource spi0_resources[] = { | ||
| 448 | [0] = { | ||
| 449 | .start = AT91SAM9G45_BASE_SPI0, | ||
| 450 | .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1, | ||
| 451 | .flags = IORESOURCE_MEM, | ||
| 452 | }, | ||
| 453 | [1] = { | ||
| 454 | .start = AT91SAM9G45_ID_SPI0, | ||
| 455 | .end = AT91SAM9G45_ID_SPI0, | ||
| 456 | .flags = IORESOURCE_IRQ, | ||
| 457 | }, | ||
| 458 | }; | ||
| 459 | |||
| 460 | static struct platform_device at91sam9g45_spi0_device = { | ||
| 461 | .name = "atmel_spi", | ||
| 462 | .id = 0, | ||
| 463 | .dev = { | ||
| 464 | .dma_mask = &spi_dmamask, | ||
| 465 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 466 | }, | ||
| 467 | .resource = spi0_resources, | ||
| 468 | .num_resources = ARRAY_SIZE(spi0_resources), | ||
| 469 | }; | ||
| 470 | |||
| 471 | static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 }; | ||
| 472 | |||
| 473 | static struct resource spi1_resources[] = { | ||
| 474 | [0] = { | ||
| 475 | .start = AT91SAM9G45_BASE_SPI1, | ||
| 476 | .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1, | ||
| 477 | .flags = IORESOURCE_MEM, | ||
| 478 | }, | ||
| 479 | [1] = { | ||
| 480 | .start = AT91SAM9G45_ID_SPI1, | ||
| 481 | .end = AT91SAM9G45_ID_SPI1, | ||
| 482 | .flags = IORESOURCE_IRQ, | ||
| 483 | }, | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct platform_device at91sam9g45_spi1_device = { | ||
| 487 | .name = "atmel_spi", | ||
| 488 | .id = 1, | ||
| 489 | .dev = { | ||
| 490 | .dma_mask = &spi_dmamask, | ||
| 491 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 492 | }, | ||
| 493 | .resource = spi1_resources, | ||
| 494 | .num_resources = ARRAY_SIZE(spi1_resources), | ||
| 495 | }; | ||
| 496 | |||
| 497 | static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 }; | ||
| 498 | |||
| 499 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) | ||
| 500 | { | ||
| 501 | int i; | ||
| 502 | unsigned long cs_pin; | ||
| 503 | short enable_spi0 = 0; | ||
| 504 | short enable_spi1 = 0; | ||
| 505 | |||
| 506 | /* Choose SPI chip-selects */ | ||
| 507 | for (i = 0; i < nr_devices; i++) { | ||
| 508 | if (devices[i].controller_data) | ||
| 509 | cs_pin = (unsigned long) devices[i].controller_data; | ||
| 510 | else if (devices[i].bus_num == 0) | ||
| 511 | cs_pin = spi0_standard_cs[devices[i].chip_select]; | ||
| 512 | else | ||
| 513 | cs_pin = spi1_standard_cs[devices[i].chip_select]; | ||
| 514 | |||
| 515 | if (devices[i].bus_num == 0) | ||
| 516 | enable_spi0 = 1; | ||
| 517 | else | ||
| 518 | enable_spi1 = 1; | ||
| 519 | |||
| 520 | /* enable chip-select pin */ | ||
| 521 | at91_set_gpio_output(cs_pin, 1); | ||
| 522 | |||
| 523 | /* pass chip-select pin to driver */ | ||
| 524 | devices[i].controller_data = (void *) cs_pin; | ||
| 525 | } | ||
| 526 | |||
| 527 | spi_register_board_info(devices, nr_devices); | ||
| 528 | |||
| 529 | /* Configure SPI bus(es) */ | ||
| 530 | if (enable_spi0) { | ||
| 531 | at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */ | ||
| 532 | at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */ | ||
| 533 | at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */ | ||
| 534 | |||
| 535 | at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk"); | ||
| 536 | platform_device_register(&at91sam9g45_spi0_device); | ||
| 537 | } | ||
| 538 | if (enable_spi1) { | ||
| 539 | at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */ | ||
| 540 | at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */ | ||
| 541 | at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */ | ||
| 542 | |||
| 543 | at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk"); | ||
| 544 | platform_device_register(&at91sam9g45_spi1_device); | ||
| 545 | } | ||
| 546 | } | ||
| 547 | #else | ||
| 548 | void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {} | ||
| 549 | #endif | ||
| 550 | |||
| 551 | |||
| 552 | /* -------------------------------------------------------------------- | ||
| 553 | * LCD Controller | ||
| 554 | * -------------------------------------------------------------------- */ | ||
| 555 | |||
| 556 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | ||
| 557 | static u64 lcdc_dmamask = DMA_BIT_MASK(32); | ||
| 558 | static struct atmel_lcdfb_info lcdc_data; | ||
| 559 | |||
| 560 | static struct resource lcdc_resources[] = { | ||
| 561 | [0] = { | ||
| 562 | .start = AT91SAM9G45_LCDC_BASE, | ||
| 563 | .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1, | ||
| 564 | .flags = IORESOURCE_MEM, | ||
| 565 | }, | ||
| 566 | [1] = { | ||
| 567 | .start = AT91SAM9G45_ID_LCDC, | ||
| 568 | .end = AT91SAM9G45_ID_LCDC, | ||
| 569 | .flags = IORESOURCE_IRQ, | ||
| 570 | }, | ||
| 571 | }; | ||
| 572 | |||
| 573 | static struct platform_device at91_lcdc_device = { | ||
| 574 | .name = "atmel_lcdfb", | ||
| 575 | .id = 0, | ||
| 576 | .dev = { | ||
| 577 | .dma_mask = &lcdc_dmamask, | ||
| 578 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 579 | .platform_data = &lcdc_data, | ||
| 580 | }, | ||
| 581 | .resource = lcdc_resources, | ||
| 582 | .num_resources = ARRAY_SIZE(lcdc_resources), | ||
| 583 | }; | ||
| 584 | |||
| 585 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) | ||
| 586 | { | ||
| 587 | if (!data) | ||
| 588 | return; | ||
| 589 | |||
| 590 | at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ | ||
| 591 | |||
| 592 | at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ | ||
| 593 | at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ | ||
| 594 | at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ | ||
| 595 | at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ | ||
| 596 | at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */ | ||
| 597 | at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ | ||
| 598 | at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ | ||
| 599 | at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ | ||
| 600 | at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ | ||
| 601 | at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ | ||
| 602 | at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ | ||
| 603 | at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ | ||
| 604 | at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ | ||
| 605 | at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ | ||
| 606 | at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ | ||
| 607 | at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ | ||
| 608 | at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ | ||
| 609 | at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ | ||
| 610 | at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */ | ||
| 611 | at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ | ||
| 612 | at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ | ||
| 613 | at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ | ||
| 614 | at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ | ||
| 615 | at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ | ||
| 616 | at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ | ||
| 617 | at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ | ||
| 618 | at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */ | ||
| 619 | at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ | ||
| 620 | at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ | ||
| 621 | |||
| 622 | lcdc_data = *data; | ||
| 623 | platform_device_register(&at91_lcdc_device); | ||
| 624 | } | ||
| 625 | #else | ||
| 626 | void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {} | ||
| 627 | #endif | ||
| 628 | |||
| 629 | |||
| 630 | /* -------------------------------------------------------------------- | ||
| 631 | * Timer/Counter block | ||
| 632 | * -------------------------------------------------------------------- */ | ||
| 633 | |||
| 634 | #ifdef CONFIG_ATMEL_TCLIB | ||
| 635 | static struct resource tcb0_resources[] = { | ||
| 636 | [0] = { | ||
| 637 | .start = AT91SAM9G45_BASE_TCB0, | ||
| 638 | .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1, | ||
| 639 | .flags = IORESOURCE_MEM, | ||
| 640 | }, | ||
| 641 | [1] = { | ||
| 642 | .start = AT91SAM9G45_ID_TCB, | ||
| 643 | .end = AT91SAM9G45_ID_TCB, | ||
| 644 | .flags = IORESOURCE_IRQ, | ||
| 645 | }, | ||
| 646 | }; | ||
| 647 | |||
| 648 | static struct platform_device at91sam9g45_tcb0_device = { | ||
| 649 | .name = "atmel_tcb", | ||
| 650 | .id = 0, | ||
| 651 | .resource = tcb0_resources, | ||
| 652 | .num_resources = ARRAY_SIZE(tcb0_resources), | ||
| 653 | }; | ||
| 654 | |||
| 655 | /* TCB1 begins with TC3 */ | ||
| 656 | static struct resource tcb1_resources[] = { | ||
| 657 | [0] = { | ||
| 658 | .start = AT91SAM9G45_BASE_TCB1, | ||
| 659 | .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1, | ||
| 660 | .flags = IORESOURCE_MEM, | ||
| 661 | }, | ||
| 662 | [1] = { | ||
| 663 | .start = AT91SAM9G45_ID_TCB, | ||
| 664 | .end = AT91SAM9G45_ID_TCB, | ||
| 665 | .flags = IORESOURCE_IRQ, | ||
| 666 | }, | ||
| 667 | }; | ||
| 668 | |||
| 669 | static struct platform_device at91sam9g45_tcb1_device = { | ||
| 670 | .name = "atmel_tcb", | ||
| 671 | .id = 1, | ||
| 672 | .resource = tcb1_resources, | ||
| 673 | .num_resources = ARRAY_SIZE(tcb1_resources), | ||
| 674 | }; | ||
| 675 | |||
| 676 | static void __init at91_add_device_tc(void) | ||
| 677 | { | ||
| 678 | /* this chip has one clock and irq for all six TC channels */ | ||
| 679 | at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk"); | ||
| 680 | platform_device_register(&at91sam9g45_tcb0_device); | ||
| 681 | at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk"); | ||
| 682 | platform_device_register(&at91sam9g45_tcb1_device); | ||
| 683 | } | ||
| 684 | #else | ||
| 685 | static void __init at91_add_device_tc(void) { } | ||
| 686 | #endif | ||
| 687 | |||
| 688 | |||
| 689 | /* -------------------------------------------------------------------- | ||
| 690 | * RTC | ||
| 691 | * -------------------------------------------------------------------- */ | ||
| 692 | |||
| 693 | #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE) | ||
| 694 | static struct platform_device at91sam9g45_rtc_device = { | ||
| 695 | .name = "at91_rtc", | ||
| 696 | .id = -1, | ||
| 697 | .num_resources = 0, | ||
| 698 | }; | ||
| 699 | |||
| 700 | static void __init at91_add_device_rtc(void) | ||
| 701 | { | ||
| 702 | platform_device_register(&at91sam9g45_rtc_device); | ||
| 703 | } | ||
| 704 | #else | ||
| 705 | static void __init at91_add_device_rtc(void) {} | ||
| 706 | #endif | ||
| 707 | |||
| 708 | |||
| 709 | /* -------------------------------------------------------------------- | ||
| 710 | * RTT | ||
| 711 | * -------------------------------------------------------------------- */ | ||
| 712 | |||
| 713 | static struct resource rtt_resources[] = { | ||
| 714 | { | ||
| 715 | .start = AT91_BASE_SYS + AT91_RTT, | ||
| 716 | .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1, | ||
| 717 | .flags = IORESOURCE_MEM, | ||
| 718 | } | ||
| 719 | }; | ||
| 720 | |||
| 721 | static struct platform_device at91sam9g45_rtt_device = { | ||
| 722 | .name = "at91_rtt", | ||
| 723 | .id = 0, | ||
| 724 | .resource = rtt_resources, | ||
| 725 | .num_resources = ARRAY_SIZE(rtt_resources), | ||
| 726 | }; | ||
| 727 | |||
| 728 | static void __init at91_add_device_rtt(void) | ||
| 729 | { | ||
| 730 | platform_device_register(&at91sam9g45_rtt_device); | ||
| 731 | } | ||
| 732 | |||
| 733 | |||
| 734 | /* -------------------------------------------------------------------- | ||
| 735 | * Watchdog | ||
| 736 | * -------------------------------------------------------------------- */ | ||
| 737 | |||
| 738 | #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE) | ||
| 739 | static struct platform_device at91sam9g45_wdt_device = { | ||
| 740 | .name = "at91_wdt", | ||
| 741 | .id = -1, | ||
| 742 | .num_resources = 0, | ||
| 743 | }; | ||
| 744 | |||
| 745 | static void __init at91_add_device_watchdog(void) | ||
| 746 | { | ||
| 747 | platform_device_register(&at91sam9g45_wdt_device); | ||
| 748 | } | ||
| 749 | #else | ||
| 750 | static void __init at91_add_device_watchdog(void) {} | ||
| 751 | #endif | ||
| 752 | |||
| 753 | |||
| 754 | /* -------------------------------------------------------------------- | ||
| 755 | * PWM | ||
| 756 | * --------------------------------------------------------------------*/ | ||
| 757 | |||
| 758 | #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE) | ||
| 759 | static u32 pwm_mask; | ||
| 760 | |||
| 761 | static struct resource pwm_resources[] = { | ||
| 762 | [0] = { | ||
| 763 | .start = AT91SAM9G45_BASE_PWMC, | ||
| 764 | .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1, | ||
| 765 | .flags = IORESOURCE_MEM, | ||
| 766 | }, | ||
| 767 | [1] = { | ||
| 768 | .start = AT91SAM9G45_ID_PWMC, | ||
| 769 | .end = AT91SAM9G45_ID_PWMC, | ||
| 770 | .flags = IORESOURCE_IRQ, | ||
| 771 | }, | ||
| 772 | }; | ||
| 773 | |||
| 774 | static struct platform_device at91sam9g45_pwm0_device = { | ||
| 775 | .name = "atmel_pwm", | ||
| 776 | .id = -1, | ||
| 777 | .dev = { | ||
| 778 | .platform_data = &pwm_mask, | ||
| 779 | }, | ||
| 780 | .resource = pwm_resources, | ||
| 781 | .num_resources = ARRAY_SIZE(pwm_resources), | ||
| 782 | }; | ||
| 783 | |||
| 784 | void __init at91_add_device_pwm(u32 mask) | ||
| 785 | { | ||
| 786 | if (mask & (1 << AT91_PWM0)) | ||
| 787 | at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */ | ||
| 788 | |||
| 789 | if (mask & (1 << AT91_PWM1)) | ||
| 790 | at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */ | ||
| 791 | |||
| 792 | if (mask & (1 << AT91_PWM2)) | ||
| 793 | at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */ | ||
| 794 | |||
| 795 | if (mask & (1 << AT91_PWM3)) | ||
| 796 | at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */ | ||
| 797 | |||
| 798 | pwm_mask = mask; | ||
| 799 | |||
| 800 | platform_device_register(&at91sam9g45_pwm0_device); | ||
| 801 | } | ||
| 802 | #else | ||
| 803 | void __init at91_add_device_pwm(u32 mask) {} | ||
| 804 | #endif | ||
| 805 | |||
| 806 | |||
| 807 | /* -------------------------------------------------------------------- | ||
| 808 | * SSC -- Synchronous Serial Controller | ||
| 809 | * -------------------------------------------------------------------- */ | ||
| 810 | |||
| 811 | #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE) | ||
| 812 | static u64 ssc0_dmamask = DMA_BIT_MASK(32); | ||
| 813 | |||
| 814 | static struct resource ssc0_resources[] = { | ||
| 815 | [0] = { | ||
| 816 | .start = AT91SAM9G45_BASE_SSC0, | ||
| 817 | .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1, | ||
| 818 | .flags = IORESOURCE_MEM, | ||
| 819 | }, | ||
| 820 | [1] = { | ||
| 821 | .start = AT91SAM9G45_ID_SSC0, | ||
| 822 | .end = AT91SAM9G45_ID_SSC0, | ||
| 823 | .flags = IORESOURCE_IRQ, | ||
| 824 | }, | ||
| 825 | }; | ||
| 826 | |||
| 827 | static struct platform_device at91sam9g45_ssc0_device = { | ||
| 828 | .name = "ssc", | ||
| 829 | .id = 0, | ||
| 830 | .dev = { | ||
| 831 | .dma_mask = &ssc0_dmamask, | ||
| 832 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 833 | }, | ||
| 834 | .resource = ssc0_resources, | ||
| 835 | .num_resources = ARRAY_SIZE(ssc0_resources), | ||
| 836 | }; | ||
| 837 | |||
| 838 | static inline void configure_ssc0_pins(unsigned pins) | ||
| 839 | { | ||
| 840 | if (pins & ATMEL_SSC_TF) | ||
| 841 | at91_set_A_periph(AT91_PIN_PD1, 1); | ||
| 842 | if (pins & ATMEL_SSC_TK) | ||
| 843 | at91_set_A_periph(AT91_PIN_PD0, 1); | ||
| 844 | if (pins & ATMEL_SSC_TD) | ||
| 845 | at91_set_A_periph(AT91_PIN_PD2, 1); | ||
| 846 | if (pins & ATMEL_SSC_RD) | ||
| 847 | at91_set_A_periph(AT91_PIN_PD3, 1); | ||
| 848 | if (pins & ATMEL_SSC_RK) | ||
| 849 | at91_set_A_periph(AT91_PIN_PD4, 1); | ||
| 850 | if (pins & ATMEL_SSC_RF) | ||
| 851 | at91_set_A_periph(AT91_PIN_PD5, 1); | ||
| 852 | } | ||
| 853 | |||
| 854 | static u64 ssc1_dmamask = DMA_BIT_MASK(32); | ||
| 855 | |||
| 856 | static struct resource ssc1_resources[] = { | ||
| 857 | [0] = { | ||
| 858 | .start = AT91SAM9G45_BASE_SSC1, | ||
| 859 | .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1, | ||
| 860 | .flags = IORESOURCE_MEM, | ||
| 861 | }, | ||
| 862 | [1] = { | ||
| 863 | .start = AT91SAM9G45_ID_SSC1, | ||
| 864 | .end = AT91SAM9G45_ID_SSC1, | ||
| 865 | .flags = IORESOURCE_IRQ, | ||
| 866 | }, | ||
| 867 | }; | ||
| 868 | |||
| 869 | static struct platform_device at91sam9g45_ssc1_device = { | ||
| 870 | .name = "ssc", | ||
| 871 | .id = 1, | ||
| 872 | .dev = { | ||
| 873 | .dma_mask = &ssc1_dmamask, | ||
| 874 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 875 | }, | ||
| 876 | .resource = ssc1_resources, | ||
| 877 | .num_resources = ARRAY_SIZE(ssc1_resources), | ||
| 878 | }; | ||
| 879 | |||
| 880 | static inline void configure_ssc1_pins(unsigned pins) | ||
| 881 | { | ||
| 882 | if (pins & ATMEL_SSC_TF) | ||
| 883 | at91_set_A_periph(AT91_PIN_PD14, 1); | ||
| 884 | if (pins & ATMEL_SSC_TK) | ||
| 885 | at91_set_A_periph(AT91_PIN_PD12, 1); | ||
| 886 | if (pins & ATMEL_SSC_TD) | ||
| 887 | at91_set_A_periph(AT91_PIN_PD10, 1); | ||
| 888 | if (pins & ATMEL_SSC_RD) | ||
| 889 | at91_set_A_periph(AT91_PIN_PD11, 1); | ||
| 890 | if (pins & ATMEL_SSC_RK) | ||
| 891 | at91_set_A_periph(AT91_PIN_PD13, 1); | ||
| 892 | if (pins & ATMEL_SSC_RF) | ||
| 893 | at91_set_A_periph(AT91_PIN_PD15, 1); | ||
| 894 | } | ||
| 895 | |||
| 896 | /* | ||
| 897 | * SSC controllers are accessed through library code, instead of any | ||
| 898 | * kind of all-singing/all-dancing driver. For example one could be | ||
| 899 | * used by a particular I2S audio codec's driver, while another one | ||
| 900 | * on the same system might be used by a custom data capture driver. | ||
| 901 | */ | ||
| 902 | void __init at91_add_device_ssc(unsigned id, unsigned pins) | ||
| 903 | { | ||
| 904 | struct platform_device *pdev; | ||
| 905 | |||
| 906 | /* | ||
| 907 | * NOTE: caller is responsible for passing information matching | ||
| 908 | * "pins" to whatever will be using each particular controller. | ||
| 909 | */ | ||
| 910 | switch (id) { | ||
| 911 | case AT91SAM9G45_ID_SSC0: | ||
| 912 | pdev = &at91sam9g45_ssc0_device; | ||
| 913 | configure_ssc0_pins(pins); | ||
| 914 | at91_clock_associate("ssc0_clk", &pdev->dev, "pclk"); | ||
| 915 | break; | ||
| 916 | case AT91SAM9G45_ID_SSC1: | ||
| 917 | pdev = &at91sam9g45_ssc1_device; | ||
| 918 | configure_ssc1_pins(pins); | ||
| 919 | at91_clock_associate("ssc1_clk", &pdev->dev, "pclk"); | ||
| 920 | break; | ||
| 921 | default: | ||
| 922 | return; | ||
| 923 | } | ||
| 924 | |||
| 925 | platform_device_register(pdev); | ||
| 926 | } | ||
| 927 | |||
| 928 | #else | ||
| 929 | void __init at91_add_device_ssc(unsigned id, unsigned pins) {} | ||
| 930 | #endif | ||
| 931 | |||
| 932 | |||
| 933 | /* -------------------------------------------------------------------- | ||
| 934 | * UART | ||
| 935 | * -------------------------------------------------------------------- */ | ||
| 936 | |||
| 937 | #if defined(CONFIG_SERIAL_ATMEL) | ||
| 938 | static struct resource dbgu_resources[] = { | ||
| 939 | [0] = { | ||
| 940 | .start = AT91_VA_BASE_SYS + AT91_DBGU, | ||
| 941 | .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1, | ||
| 942 | .flags = IORESOURCE_MEM, | ||
| 943 | }, | ||
| 944 | [1] = { | ||
| 945 | .start = AT91_ID_SYS, | ||
| 946 | .end = AT91_ID_SYS, | ||
| 947 | .flags = IORESOURCE_IRQ, | ||
| 948 | }, | ||
| 949 | }; | ||
| 950 | |||
| 951 | static struct atmel_uart_data dbgu_data = { | ||
| 952 | .use_dma_tx = 0, | ||
| 953 | .use_dma_rx = 0, | ||
| 954 | .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU), | ||
| 955 | }; | ||
| 956 | |||
| 957 | static u64 dbgu_dmamask = DMA_BIT_MASK(32); | ||
| 958 | |||
| 959 | static struct platform_device at91sam9g45_dbgu_device = { | ||
| 960 | .name = "atmel_usart", | ||
| 961 | .id = 0, | ||
| 962 | .dev = { | ||
| 963 | .dma_mask = &dbgu_dmamask, | ||
| 964 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 965 | .platform_data = &dbgu_data, | ||
| 966 | }, | ||
| 967 | .resource = dbgu_resources, | ||
| 968 | .num_resources = ARRAY_SIZE(dbgu_resources), | ||
| 969 | }; | ||
| 970 | |||
| 971 | static inline void configure_dbgu_pins(void) | ||
| 972 | { | ||
| 973 | at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ | ||
| 974 | at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ | ||
| 975 | } | ||
| 976 | |||
| 977 | static struct resource uart0_resources[] = { | ||
| 978 | [0] = { | ||
| 979 | .start = AT91SAM9G45_BASE_US0, | ||
| 980 | .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1, | ||
| 981 | .flags = IORESOURCE_MEM, | ||
| 982 | }, | ||
| 983 | [1] = { | ||
| 984 | .start = AT91SAM9G45_ID_US0, | ||
| 985 | .end = AT91SAM9G45_ID_US0, | ||
| 986 | .flags = IORESOURCE_IRQ, | ||
| 987 | }, | ||
| 988 | }; | ||
| 989 | |||
| 990 | static struct atmel_uart_data uart0_data = { | ||
| 991 | .use_dma_tx = 1, | ||
| 992 | .use_dma_rx = 1, | ||
| 993 | }; | ||
| 994 | |||
| 995 | static u64 uart0_dmamask = DMA_BIT_MASK(32); | ||
| 996 | |||
| 997 | static struct platform_device at91sam9g45_uart0_device = { | ||
| 998 | .name = "atmel_usart", | ||
| 999 | .id = 1, | ||
| 1000 | .dev = { | ||
| 1001 | .dma_mask = &uart0_dmamask, | ||
| 1002 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 1003 | .platform_data = &uart0_data, | ||
| 1004 | }, | ||
| 1005 | .resource = uart0_resources, | ||
| 1006 | .num_resources = ARRAY_SIZE(uart0_resources), | ||
| 1007 | }; | ||
| 1008 | |||
| 1009 | static inline void configure_usart0_pins(unsigned pins) | ||
| 1010 | { | ||
| 1011 | at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ | ||
| 1012 | at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ | ||
| 1013 | |||
| 1014 | if (pins & ATMEL_UART_RTS) | ||
| 1015 | at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */ | ||
| 1016 | if (pins & ATMEL_UART_CTS) | ||
| 1017 | at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */ | ||
| 1018 | } | ||
| 1019 | |||
| 1020 | static struct resource uart1_resources[] = { | ||
| 1021 | [0] = { | ||
| 1022 | .start = AT91SAM9G45_BASE_US1, | ||
| 1023 | .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1, | ||
| 1024 | .flags = IORESOURCE_MEM, | ||
| 1025 | }, | ||
| 1026 | [1] = { | ||
| 1027 | .start = AT91SAM9G45_ID_US1, | ||
| 1028 | .end = AT91SAM9G45_ID_US1, | ||
| 1029 | .flags = IORESOURCE_IRQ, | ||
| 1030 | }, | ||
| 1031 | }; | ||
| 1032 | |||
| 1033 | static struct atmel_uart_data uart1_data = { | ||
| 1034 | .use_dma_tx = 1, | ||
| 1035 | .use_dma_rx = 1, | ||
| 1036 | }; | ||
| 1037 | |||
| 1038 | static u64 uart1_dmamask = DMA_BIT_MASK(32); | ||
| 1039 | |||
| 1040 | static struct platform_device at91sam9g45_uart1_device = { | ||
| 1041 | .name = "atmel_usart", | ||
| 1042 | .id = 2, | ||
| 1043 | .dev = { | ||
| 1044 | .dma_mask = &uart1_dmamask, | ||
| 1045 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 1046 | .platform_data = &uart1_data, | ||
| 1047 | }, | ||
| 1048 | .resource = uart1_resources, | ||
| 1049 | .num_resources = ARRAY_SIZE(uart1_resources), | ||
| 1050 | }; | ||
| 1051 | |||
| 1052 | static inline void configure_usart1_pins(unsigned pins) | ||
| 1053 | { | ||
| 1054 | at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ | ||
| 1055 | at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ | ||
| 1056 | |||
| 1057 | if (pins & ATMEL_UART_RTS) | ||
| 1058 | at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */ | ||
| 1059 | if (pins & ATMEL_UART_CTS) | ||
| 1060 | at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */ | ||
| 1061 | } | ||
| 1062 | |||
| 1063 | static struct resource uart2_resources[] = { | ||
| 1064 | [0] = { | ||
| 1065 | .start = AT91SAM9G45_BASE_US2, | ||
| 1066 | .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1, | ||
| 1067 | .flags = IORESOURCE_MEM, | ||
| 1068 | }, | ||
| 1069 | [1] = { | ||
| 1070 | .start = AT91SAM9G45_ID_US2, | ||
| 1071 | .end = AT91SAM9G45_ID_US2, | ||
| 1072 | .flags = IORESOURCE_IRQ, | ||
| 1073 | }, | ||
| 1074 | }; | ||
| 1075 | |||
| 1076 | static struct atmel_uart_data uart2_data = { | ||
| 1077 | .use_dma_tx = 1, | ||
| 1078 | .use_dma_rx = 1, | ||
| 1079 | }; | ||
| 1080 | |||
| 1081 | static u64 uart2_dmamask = DMA_BIT_MASK(32); | ||
| 1082 | |||
| 1083 | static struct platform_device at91sam9g45_uart2_device = { | ||
| 1084 | .name = "atmel_usart", | ||
| 1085 | .id = 3, | ||
| 1086 | .dev = { | ||
| 1087 | .dma_mask = &uart2_dmamask, | ||
| 1088 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 1089 | .platform_data = &uart2_data, | ||
| 1090 | }, | ||
| 1091 | .resource = uart2_resources, | ||
| 1092 | .num_resources = ARRAY_SIZE(uart2_resources), | ||
| 1093 | }; | ||
| 1094 | |||
| 1095 | static inline void configure_usart2_pins(unsigned pins) | ||
| 1096 | { | ||
| 1097 | at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */ | ||
| 1098 | at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */ | ||
| 1099 | |||
| 1100 | if (pins & ATMEL_UART_RTS) | ||
| 1101 | at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */ | ||
| 1102 | if (pins & ATMEL_UART_CTS) | ||
| 1103 | at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */ | ||
| 1104 | } | ||
| 1105 | |||
| 1106 | static struct resource uart3_resources[] = { | ||
| 1107 | [0] = { | ||
| 1108 | .start = AT91SAM9G45_BASE_US3, | ||
| 1109 | .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1, | ||
| 1110 | .flags = IORESOURCE_MEM, | ||
| 1111 | }, | ||
| 1112 | [1] = { | ||
| 1113 | .start = AT91SAM9G45_ID_US3, | ||
| 1114 | .end = AT91SAM9G45_ID_US3, | ||
| 1115 | .flags = IORESOURCE_IRQ, | ||
| 1116 | }, | ||
| 1117 | }; | ||
| 1118 | |||
| 1119 | static struct atmel_uart_data uart3_data = { | ||
| 1120 | .use_dma_tx = 1, | ||
| 1121 | .use_dma_rx = 1, | ||
| 1122 | }; | ||
| 1123 | |||
| 1124 | static u64 uart3_dmamask = DMA_BIT_MASK(32); | ||
| 1125 | |||
| 1126 | static struct platform_device at91sam9g45_uart3_device = { | ||
| 1127 | .name = "atmel_usart", | ||
| 1128 | .id = 4, | ||
| 1129 | .dev = { | ||
| 1130 | .dma_mask = &uart3_dmamask, | ||
| 1131 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
| 1132 | .platform_data = &uart3_data, | ||
| 1133 | }, | ||
| 1134 | .resource = uart3_resources, | ||
| 1135 | .num_resources = ARRAY_SIZE(uart3_resources), | ||
| 1136 | }; | ||
| 1137 | |||
| 1138 | static inline void configure_usart3_pins(unsigned pins) | ||
| 1139 | { | ||
| 1140 | at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */ | ||
| 1141 | at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */ | ||
| 1142 | |||
| 1143 | if (pins & ATMEL_UART_RTS) | ||
| 1144 | at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */ | ||
| 1145 | if (pins & ATMEL_UART_CTS) | ||
| 1146 | at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */ | ||
| 1147 | } | ||
| 1148 | |||
| 1149 | static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */ | ||
| 1150 | struct platform_device *atmel_default_console_device; /* the serial console device */ | ||
| 1151 | |||
| 1152 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) | ||
| 1153 | { | ||
| 1154 | struct platform_device *pdev; | ||
| 1155 | |||
| 1156 | switch (id) { | ||
| 1157 | case 0: /* DBGU */ | ||
| 1158 | pdev = &at91sam9g45_dbgu_device; | ||
| 1159 | configure_dbgu_pins(); | ||
| 1160 | at91_clock_associate("mck", &pdev->dev, "usart"); | ||
| 1161 | break; | ||
| 1162 | case AT91SAM9G45_ID_US0: | ||
| 1163 | pdev = &at91sam9g45_uart0_device; | ||
| 1164 | configure_usart0_pins(pins); | ||
| 1165 | at91_clock_associate("usart0_clk", &pdev->dev, "usart"); | ||
| 1166 | break; | ||
| 1167 | case AT91SAM9G45_ID_US1: | ||
| 1168 | pdev = &at91sam9g45_uart1_device; | ||
| 1169 | configure_usart1_pins(pins); | ||
| 1170 | at91_clock_associate("usart1_clk", &pdev->dev, "usart"); | ||
| 1171 | break; | ||
| 1172 | case AT91SAM9G45_ID_US2: | ||
| 1173 | pdev = &at91sam9g45_uart2_device; | ||
| 1174 | configure_usart2_pins(pins); | ||
| 1175 | at91_clock_associate("usart2_clk", &pdev->dev, "usart"); | ||
| 1176 | break; | ||
| 1177 | case AT91SAM9G45_ID_US3: | ||
| 1178 | pdev = &at91sam9g45_uart3_device; | ||
| 1179 | configure_usart3_pins(pins); | ||
| 1180 | at91_clock_associate("usart3_clk", &pdev->dev, "usart"); | ||
| 1181 | break; | ||
| 1182 | default: | ||
| 1183 | return; | ||
| 1184 | } | ||
| 1185 | pdev->id = portnr; /* update to mapped ID */ | ||
| 1186 | |||
| 1187 | if (portnr < ATMEL_MAX_UART) | ||
| 1188 | at91_uarts[portnr] = pdev; | ||
| 1189 | } | ||
| 1190 | |||
| 1191 | void __init at91_set_serial_console(unsigned portnr) | ||
| 1192 | { | ||
| 1193 | if (portnr < ATMEL_MAX_UART) | ||
| 1194 | atmel_default_console_device = at91_uarts[portnr]; | ||
| 1195 | } | ||
| 1196 | |||
| 1197 | void __init at91_add_device_serial(void) | ||
| 1198 | { | ||
| 1199 | int i; | ||
| 1200 | |||
| 1201 | for (i = 0; i < ATMEL_MAX_UART; i++) { | ||
| 1202 | if (at91_uarts[i]) | ||
| 1203 | platform_device_register(at91_uarts[i]); | ||
| 1204 | } | ||
| 1205 | |||
| 1206 | if (!atmel_default_console_device) | ||
| 1207 | printk(KERN_INFO "AT91: No default serial console defined.\n"); | ||
| 1208 | } | ||
| 1209 | #else | ||
| 1210 | void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {} | ||
| 1211 | void __init at91_set_serial_console(unsigned portnr) {} | ||
| 1212 | void __init at91_add_device_serial(void) {} | ||
| 1213 | #endif | ||
| 1214 | |||
| 1215 | |||
| 1216 | /* -------------------------------------------------------------------- */ | ||
| 1217 | /* | ||
| 1218 | * These devices are always present and don't need any board-specific | ||
| 1219 | * setup. | ||
| 1220 | */ | ||
| 1221 | static int __init at91_add_standard_devices(void) | ||
| 1222 | { | ||
| 1223 | at91_add_device_rtc(); | ||
| 1224 | at91_add_device_rtt(); | ||
| 1225 | at91_add_device_watchdog(); | ||
| 1226 | at91_add_device_tc(); | ||
| 1227 | return 0; | ||
| 1228 | } | ||
| 1229 | |||
| 1230 | arch_initcall(at91_add_standard_devices); | ||
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c index 970fd6b6753e..61e52b66bc72 100644 --- a/arch/arm/mach-at91/board-afeb-9260v1.c +++ b/arch/arm/mach-at91/board-afeb-9260v1.c | |||
| @@ -174,6 +174,16 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = { | |||
| 174 | }, | 174 | }, |
| 175 | }; | 175 | }; |
| 176 | 176 | ||
| 177 | /* | ||
| 178 | * IDE (CF True IDE mode) | ||
| 179 | */ | ||
| 180 | static struct at91_cf_data afeb9260_cf_data = { | ||
| 181 | .chipselect = 4, | ||
| 182 | .irq_pin = AT91_PIN_PA6, | ||
| 183 | .rst_pin = AT91_PIN_PA7, | ||
| 184 | .flags = AT91_CF_TRUE_IDE, | ||
| 185 | }; | ||
| 186 | |||
| 177 | static void __init afeb9260_board_init(void) | 187 | static void __init afeb9260_board_init(void) |
| 178 | { | 188 | { |
| 179 | /* Serial */ | 189 | /* Serial */ |
| @@ -202,6 +212,8 @@ static void __init afeb9260_board_init(void) | |||
| 202 | ARRAY_SIZE(afeb9260_i2c_devices)); | 212 | ARRAY_SIZE(afeb9260_i2c_devices)); |
| 203 | /* Audio */ | 213 | /* Audio */ |
| 204 | at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); | 214 | at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); |
| 215 | /* IDE */ | ||
| 216 | at91_add_device_cf(&afeb9260_cf_data); | ||
| 205 | } | 217 | } |
| 206 | 218 | ||
| 207 | MACHINE_START(AFEB9260, "Custom afeb9260 board") | 219 | MACHINE_START(AFEB9260, "Custom afeb9260 board") |
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c new file mode 100644 index 000000000000..4bc2e9f6ebb5 --- /dev/null +++ b/arch/arm/mach-at91/board-cpu9krea.c | |||
| @@ -0,0 +1,385 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-cpu9krea.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 SAN People | ||
| 5 | * Copyright (C) 2006 Atmel | ||
| 6 | * Copyright (C) 2009 Eric Benard - eric@eukrea.com | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/types.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <linux/mm.h> | ||
| 26 | #include <linux/module.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/clk.h> | ||
| 29 | #include <linux/gpio_keys.h> | ||
| 30 | #include <linux/input.h> | ||
| 31 | #include <linux/mtd/physmap.h> | ||
| 32 | |||
| 33 | #include <asm/setup.h> | ||
| 34 | #include <asm/mach-types.h> | ||
| 35 | #include <asm/irq.h> | ||
| 36 | |||
| 37 | #include <asm/mach/arch.h> | ||
| 38 | #include <asm/mach/map.h> | ||
| 39 | #include <asm/mach/irq.h> | ||
| 40 | |||
| 41 | #include <mach/hardware.h> | ||
| 42 | #include <mach/board.h> | ||
| 43 | #include <mach/gpio.h> | ||
| 44 | #include <mach/at91sam9_smc.h> | ||
| 45 | #include <mach/at91sam9260_matrix.h> | ||
| 46 | |||
| 47 | #include "sam9_smc.h" | ||
| 48 | #include "generic.h" | ||
| 49 | |||
| 50 | static void __init cpu9krea_map_io(void) | ||
| 51 | { | ||
| 52 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 53 | at91sam9260_initialize(18432000); | ||
| 54 | |||
| 55 | /* DGBU on ttyS0. (Rx & Tx only) */ | ||
| 56 | at91_register_uart(0, 0, 0); | ||
| 57 | |||
| 58 | /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ | ||
| 59 | at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | | ||
| 60 | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | | ||
| 61 | ATMEL_UART_DCD | ATMEL_UART_RI); | ||
| 62 | |||
| 63 | /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ | ||
| 64 | at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | | ||
| 65 | ATMEL_UART_RTS); | ||
| 66 | |||
| 67 | /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */ | ||
| 68 | at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | | ||
| 69 | ATMEL_UART_RTS); | ||
| 70 | |||
| 71 | /* USART3 on ttyS4. (Rx, Tx) */ | ||
| 72 | at91_register_uart(AT91SAM9260_ID_US3, 4, 0); | ||
| 73 | |||
| 74 | /* USART4 on ttyS5. (Rx, Tx) */ | ||
| 75 | at91_register_uart(AT91SAM9260_ID_US4, 5, 0); | ||
| 76 | |||
| 77 | /* USART5 on ttyS6. (Rx, Tx) */ | ||
| 78 | at91_register_uart(AT91SAM9260_ID_US5, 6, 0); | ||
| 79 | |||
| 80 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 81 | at91_set_serial_console(0); | ||
| 82 | } | ||
| 83 | |||
| 84 | static void __init cpu9krea_init_irq(void) | ||
| 85 | { | ||
| 86 | at91sam9260_init_interrupts(NULL); | ||
| 87 | } | ||
| 88 | |||
| 89 | /* | ||
| 90 | * USB Host port | ||
| 91 | */ | ||
| 92 | static struct at91_usbh_data __initdata cpu9krea_usbh_data = { | ||
| 93 | .ports = 2, | ||
| 94 | }; | ||
| 95 | |||
| 96 | /* | ||
| 97 | * USB Device port | ||
| 98 | */ | ||
| 99 | static struct at91_udc_data __initdata cpu9krea_udc_data = { | ||
| 100 | .vbus_pin = AT91_PIN_PC8, | ||
| 101 | .pullup_pin = 0, /* pull-up driven by UDC */ | ||
| 102 | }; | ||
| 103 | |||
| 104 | /* | ||
| 105 | * MACB Ethernet device | ||
| 106 | */ | ||
| 107 | static struct at91_eth_data __initdata cpu9krea_macb_data = { | ||
| 108 | .is_rmii = 1, | ||
| 109 | }; | ||
| 110 | |||
| 111 | /* | ||
| 112 | * NAND flash | ||
| 113 | */ | ||
| 114 | static struct atmel_nand_data __initdata cpu9krea_nand_data = { | ||
| 115 | .ale = 21, | ||
| 116 | .cle = 22, | ||
| 117 | .rdy_pin = AT91_PIN_PC13, | ||
| 118 | .enable_pin = AT91_PIN_PC14, | ||
| 119 | .bus_width_16 = 0, | ||
| 120 | }; | ||
| 121 | |||
| 122 | #ifdef CONFIG_MACH_CPU9260 | ||
| 123 | static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = { | ||
| 124 | .ncs_read_setup = 0, | ||
| 125 | .nrd_setup = 1, | ||
| 126 | .ncs_write_setup = 0, | ||
| 127 | .nwe_setup = 1, | ||
| 128 | |||
| 129 | .ncs_read_pulse = 3, | ||
| 130 | .nrd_pulse = 3, | ||
| 131 | .ncs_write_pulse = 3, | ||
| 132 | .nwe_pulse = 3, | ||
| 133 | |||
| 134 | .read_cycle = 5, | ||
| 135 | .write_cycle = 5, | ||
| 136 | |||
| 137 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | ||
| 138 | | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, | ||
| 139 | .tdf_cycles = 2, | ||
| 140 | }; | ||
| 141 | #else | ||
| 142 | static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = { | ||
| 143 | .ncs_read_setup = 0, | ||
| 144 | .nrd_setup = 2, | ||
| 145 | .ncs_write_setup = 0, | ||
| 146 | .nwe_setup = 2, | ||
| 147 | |||
| 148 | .ncs_read_pulse = 4, | ||
| 149 | .nrd_pulse = 4, | ||
| 150 | .ncs_write_pulse = 4, | ||
| 151 | .nwe_pulse = 4, | ||
| 152 | |||
| 153 | .read_cycle = 7, | ||
| 154 | .write_cycle = 7, | ||
| 155 | |||
| 156 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | ||
| 157 | | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, | ||
| 158 | .tdf_cycles = 3, | ||
| 159 | }; | ||
| 160 | #endif | ||
| 161 | |||
| 162 | static void __init cpu9krea_add_device_nand(void) | ||
| 163 | { | ||
| 164 | sam9_smc_configure(3, &cpu9krea_nand_smc_config); | ||
| 165 | at91_add_device_nand(&cpu9krea_nand_data); | ||
| 166 | } | ||
| 167 | |||
| 168 | /* | ||
| 169 | * NOR flash | ||
| 170 | */ | ||
| 171 | static struct physmap_flash_data cpuat9260_nor_data = { | ||
| 172 | .width = 2, | ||
| 173 | }; | ||
| 174 | |||
| 175 | #define NOR_BASE AT91_CHIPSELECT_0 | ||
| 176 | #define NOR_SIZE SZ_64M | ||
| 177 | |||
| 178 | static struct resource nor_flash_resources[] = { | ||
| 179 | { | ||
| 180 | .start = NOR_BASE, | ||
| 181 | .end = NOR_BASE + NOR_SIZE - 1, | ||
| 182 | .flags = IORESOURCE_MEM, | ||
| 183 | } | ||
| 184 | }; | ||
| 185 | |||
| 186 | static struct platform_device cpu9krea_nor_flash = { | ||
| 187 | .name = "physmap-flash", | ||
| 188 | .id = 0, | ||
| 189 | .dev = { | ||
| 190 | .platform_data = &cpuat9260_nor_data, | ||
| 191 | }, | ||
| 192 | .resource = nor_flash_resources, | ||
| 193 | .num_resources = ARRAY_SIZE(nor_flash_resources), | ||
| 194 | }; | ||
| 195 | |||
| 196 | #ifdef CONFIG_MACH_CPU9260 | ||
| 197 | static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = { | ||
| 198 | .ncs_read_setup = 0, | ||
| 199 | .nrd_setup = 1, | ||
| 200 | .ncs_write_setup = 0, | ||
| 201 | .nwe_setup = 1, | ||
| 202 | |||
| 203 | .ncs_read_pulse = 10, | ||
| 204 | .nrd_pulse = 10, | ||
| 205 | .ncs_write_pulse = 6, | ||
| 206 | .nwe_pulse = 6, | ||
| 207 | |||
| 208 | .read_cycle = 12, | ||
| 209 | .write_cycle = 8, | ||
| 210 | |||
| 211 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | ||
| 212 | | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | ||
| 213 | | AT91_SMC_DBW_16, | ||
| 214 | .tdf_cycles = 2, | ||
| 215 | }; | ||
| 216 | #else | ||
| 217 | static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = { | ||
| 218 | .ncs_read_setup = 0, | ||
| 219 | .nrd_setup = 1, | ||
| 220 | .ncs_write_setup = 0, | ||
| 221 | .nwe_setup = 1, | ||
| 222 | |||
| 223 | .ncs_read_pulse = 13, | ||
| 224 | .nrd_pulse = 13, | ||
| 225 | .ncs_write_pulse = 8, | ||
| 226 | .nwe_pulse = 8, | ||
| 227 | |||
| 228 | .read_cycle = 15, | ||
| 229 | .write_cycle = 10, | ||
| 230 | |||
| 231 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | ||
| 232 | | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | ||
| 233 | | AT91_SMC_DBW_16, | ||
| 234 | .tdf_cycles = 2, | ||
| 235 | }; | ||
| 236 | #endif | ||
| 237 | |||
| 238 | static __init void cpu9krea_add_device_nor(void) | ||
| 239 | { | ||
| 240 | unsigned long csa; | ||
| 241 | |||
| 242 | csa = at91_sys_read(AT91_MATRIX_EBICSA); | ||
| 243 | at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V); | ||
| 244 | |||
| 245 | /* configure chip-select 0 (NOR) */ | ||
| 246 | sam9_smc_configure(0, &cpu9krea_nor_smc_config); | ||
| 247 | |||
| 248 | platform_device_register(&cpu9krea_nor_flash); | ||
| 249 | } | ||
| 250 | |||
| 251 | /* | ||
| 252 | * LEDs | ||
| 253 | */ | ||
| 254 | static struct gpio_led cpu9krea_leds[] = { | ||
| 255 | { /* LED1 */ | ||
| 256 | .name = "LED1", | ||
| 257 | .gpio = AT91_PIN_PC11, | ||
| 258 | .active_low = 1, | ||
| 259 | .default_trigger = "timer", | ||
| 260 | }, | ||
| 261 | { /* LED2 */ | ||
| 262 | .name = "LED2", | ||
| 263 | .gpio = AT91_PIN_PC12, | ||
| 264 | .active_low = 1, | ||
| 265 | .default_trigger = "heartbeat", | ||
| 266 | }, | ||
| 267 | { /* LED3 */ | ||
| 268 | .name = "LED3", | ||
| 269 | .gpio = AT91_PIN_PC7, | ||
| 270 | .active_low = 1, | ||
| 271 | .default_trigger = "none", | ||
| 272 | }, | ||
| 273 | { /* LED4 */ | ||
| 274 | .name = "LED4", | ||
| 275 | .gpio = AT91_PIN_PC9, | ||
| 276 | .active_low = 1, | ||
| 277 | .default_trigger = "none", | ||
| 278 | } | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = { | ||
| 282 | { | ||
| 283 | I2C_BOARD_INFO("rtc-ds1307", 0x68), | ||
| 284 | .type = "ds1339", | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | /* | ||
| 289 | * GPIO Buttons | ||
| 290 | */ | ||
| 291 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 292 | static struct gpio_keys_button cpu9krea_buttons[] = { | ||
| 293 | { | ||
| 294 | .gpio = AT91_PIN_PC3, | ||
| 295 | .code = BTN_0, | ||
| 296 | .desc = "BP1", | ||
| 297 | .active_low = 1, | ||
| 298 | .wakeup = 1, | ||
| 299 | }, | ||
| 300 | { | ||
| 301 | .gpio = AT91_PIN_PB20, | ||
| 302 | .code = BTN_1, | ||
| 303 | .desc = "BP2", | ||
| 304 | .active_low = 1, | ||
| 305 | .wakeup = 1, | ||
| 306 | } | ||
| 307 | }; | ||
| 308 | |||
| 309 | static struct gpio_keys_platform_data cpu9krea_button_data = { | ||
| 310 | .buttons = cpu9krea_buttons, | ||
| 311 | .nbuttons = ARRAY_SIZE(cpu9krea_buttons), | ||
| 312 | }; | ||
| 313 | |||
| 314 | static struct platform_device cpu9krea_button_device = { | ||
| 315 | .name = "gpio-keys", | ||
| 316 | .id = -1, | ||
| 317 | .num_resources = 0, | ||
| 318 | .dev = { | ||
| 319 | .platform_data = &cpu9krea_button_data, | ||
| 320 | } | ||
| 321 | }; | ||
| 322 | |||
| 323 | static void __init cpu9krea_add_device_buttons(void) | ||
| 324 | { | ||
| 325 | at91_set_gpio_input(AT91_PIN_PC3, 1); /* BP1 */ | ||
| 326 | at91_set_deglitch(AT91_PIN_PC3, 1); | ||
| 327 | at91_set_gpio_input(AT91_PIN_PB20, 1); /* BP2 */ | ||
| 328 | at91_set_deglitch(AT91_PIN_PB20, 1); | ||
| 329 | |||
| 330 | platform_device_register(&cpu9krea_button_device); | ||
| 331 | } | ||
| 332 | #else | ||
| 333 | static void __init cpu9krea_add_device_buttons(void) | ||
| 334 | { | ||
| 335 | } | ||
| 336 | #endif | ||
| 337 | |||
| 338 | /* | ||
| 339 | * MCI (SD/MMC) | ||
| 340 | */ | ||
| 341 | static struct at91_mmc_data __initdata cpu9krea_mmc_data = { | ||
| 342 | .slot_b = 0, | ||
| 343 | .wire4 = 1, | ||
| 344 | .det_pin = AT91_PIN_PA29, | ||
| 345 | }; | ||
| 346 | |||
| 347 | static void __init cpu9krea_board_init(void) | ||
| 348 | { | ||
| 349 | /* NOR */ | ||
| 350 | cpu9krea_add_device_nor(); | ||
| 351 | /* Serial */ | ||
| 352 | at91_add_device_serial(); | ||
| 353 | /* USB Host */ | ||
| 354 | at91_add_device_usbh(&cpu9krea_usbh_data); | ||
| 355 | /* USB Device */ | ||
| 356 | at91_add_device_udc(&cpu9krea_udc_data); | ||
| 357 | /* NAND */ | ||
| 358 | cpu9krea_add_device_nand(); | ||
| 359 | /* Ethernet */ | ||
| 360 | at91_add_device_eth(&cpu9krea_macb_data); | ||
| 361 | /* MMC */ | ||
| 362 | at91_add_device_mmc(0, &cpu9krea_mmc_data); | ||
| 363 | /* I2C */ | ||
| 364 | at91_add_device_i2c(cpu9krea_i2c_devices, | ||
| 365 | ARRAY_SIZE(cpu9krea_i2c_devices)); | ||
| 366 | /* LEDs */ | ||
| 367 | at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds)); | ||
| 368 | /* Push Buttons */ | ||
| 369 | cpu9krea_add_device_buttons(); | ||
| 370 | } | ||
| 371 | |||
| 372 | #ifdef CONFIG_MACH_CPU9260 | ||
| 373 | MACHINE_START(CPUAT9260, "Eukrea CPU9260") | ||
| 374 | #else | ||
| 375 | MACHINE_START(CPUAT9G20, "Eukrea CPU9G20") | ||
| 376 | #endif | ||
| 377 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | ||
| 378 | .phys_io = AT91_BASE_SYS, | ||
| 379 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 380 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 381 | .timer = &at91sam926x_timer, | ||
| 382 | .map_io = cpu9krea_map_io, | ||
| 383 | .init_irq = cpu9krea_init_irq, | ||
| 384 | .init_machine = cpu9krea_board_init, | ||
| 385 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c new file mode 100644 index 000000000000..a28d99656190 --- /dev/null +++ b/arch/arm/mach-at91/board-cpuat91.c | |||
| @@ -0,0 +1,185 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-at91/board-cpuat91.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Eric Benard - eric@eukrea.com | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/types.h> | ||
| 22 | #include <linux/init.h> | ||
| 23 | #include <linux/mm.h> | ||
| 24 | #include <linux/module.h> | ||
| 25 | #include <linux/platform_device.h> | ||
| 26 | #include <linux/mtd/physmap.h> | ||
| 27 | #include <linux/mtd/plat-ram.h> | ||
| 28 | |||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <asm/setup.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/irq.h> | ||
| 33 | |||
| 34 | #include <asm/mach/arch.h> | ||
| 35 | #include <asm/mach/map.h> | ||
| 36 | #include <asm/mach/irq.h> | ||
| 37 | |||
| 38 | #include <mach/board.h> | ||
| 39 | #include <mach/gpio.h> | ||
| 40 | #include <mach/at91rm9200_mc.h> | ||
| 41 | |||
| 42 | #include "generic.h" | ||
| 43 | |||
| 44 | static struct gpio_led cpuat91_leds[] = { | ||
| 45 | { | ||
| 46 | .name = "led1", | ||
| 47 | .default_trigger = "heartbeat", | ||
| 48 | .active_low = 1, | ||
| 49 | .gpio = AT91_PIN_PC0, | ||
| 50 | }, | ||
| 51 | }; | ||
| 52 | |||
| 53 | static void __init cpuat91_map_io(void) | ||
| 54 | { | ||
| 55 | /* Initialize processor: 18.432 MHz crystal */ | ||
| 56 | at91rm9200_initialize(18432000, AT91RM9200_PQFP); | ||
| 57 | |||
| 58 | /* DBGU on ttyS0. (Rx & Tx only) */ | ||
| 59 | at91_register_uart(0, 0, 0); | ||
| 60 | |||
| 61 | /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */ | ||
| 62 | at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | | ||
| 63 | ATMEL_UART_RTS); | ||
| 64 | |||
| 65 | /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ | ||
| 66 | at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | | ||
| 67 | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | | ||
| 68 | ATMEL_UART_DCD | ATMEL_UART_RI); | ||
| 69 | |||
| 70 | /* USART2 on ttyS3 (Rx, Tx) */ | ||
| 71 | at91_register_uart(AT91RM9200_ID_US2, 3, 0); | ||
| 72 | |||
| 73 | /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */ | ||
| 74 | at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS | | ||
| 75 | ATMEL_UART_RTS); | ||
| 76 | |||
| 77 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 78 | at91_set_serial_console(0); | ||
| 79 | } | ||
| 80 | |||
| 81 | static void __init cpuat91_init_irq(void) | ||
| 82 | { | ||
| 83 | at91rm9200_init_interrupts(NULL); | ||
| 84 | } | ||
| 85 | |||
| 86 | static struct at91_eth_data __initdata cpuat91_eth_data = { | ||
| 87 | .is_rmii = 1, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct at91_usbh_data __initdata cpuat91_usbh_data = { | ||
| 91 | .ports = 1, | ||
| 92 | }; | ||
| 93 | |||
| 94 | static struct at91_udc_data __initdata cpuat91_udc_data = { | ||
| 95 | .vbus_pin = AT91_PIN_PC15, | ||
| 96 | .pullup_pin = AT91_PIN_PC14, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct at91_mmc_data __initdata cpuat91_mmc_data = { | ||
| 100 | .det_pin = AT91_PIN_PC2, | ||
| 101 | .wire4 = 1, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct physmap_flash_data cpuat91_flash_data = { | ||
| 105 | .width = 2, | ||
| 106 | }; | ||
| 107 | |||
| 108 | static struct resource cpuat91_flash_resource = { | ||
| 109 | .start = AT91_CHIPSELECT_0, | ||
| 110 | .end = AT91_CHIPSELECT_0 + SZ_16M - 1, | ||
| 111 | .flags = IORESOURCE_MEM, | ||
| 112 | }; | ||
| 113 | |||
| 114 | static struct platform_device cpuat91_norflash = { | ||
| 115 | .name = "physmap-flash", | ||
| 116 | .id = 0, | ||
| 117 | .dev = { | ||
| 118 | .platform_data = &cpuat91_flash_data, | ||
| 119 | }, | ||
| 120 | .resource = &cpuat91_flash_resource, | ||
| 121 | .num_resources = 1, | ||
| 122 | }; | ||
| 123 | |||
| 124 | #ifdef CONFIG_MTD_PLATRAM | ||
| 125 | struct platdata_mtd_ram at91_sram_pdata = { | ||
| 126 | .mapname = "SRAM", | ||
| 127 | .bankwidth = 2, | ||
| 128 | }; | ||
| 129 | |||
| 130 | static struct resource at91_sram_resource[] = { | ||
| 131 | [0] = { | ||
| 132 | .start = AT91RM9200_SRAM_BASE, | ||
| 133 | .end = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1, | ||
| 134 | .flags = IORESOURCE_MEM, | ||
| 135 | }, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static struct platform_device at91_sram = { | ||
| 139 | .name = "mtd-ram", | ||
| 140 | .id = 0, | ||
| 141 | .resource = at91_sram_resource, | ||
| 142 | .num_resources = ARRAY_SIZE(at91_sram_resource), | ||
| 143 | .dev = { | ||
| 144 | .platform_data = &at91_sram_pdata, | ||
| 145 | }, | ||
| 146 | }; | ||
| 147 | #endif /* MTD_PLATRAM */ | ||
| 148 | |||
| 149 | static struct platform_device *platform_devices[] __initdata = { | ||
| 150 | &cpuat91_norflash, | ||
| 151 | #ifdef CONFIG_MTD_PLATRAM | ||
| 152 | &at91_sram, | ||
| 153 | #endif /* CONFIG_MTD_PLATRAM */ | ||
| 154 | }; | ||
| 155 | |||
| 156 | static void __init cpuat91_board_init(void) | ||
| 157 | { | ||
| 158 | /* Serial */ | ||
| 159 | at91_add_device_serial(); | ||
| 160 | /* LEDs. */ | ||
| 161 | at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds)); | ||
| 162 | /* Ethernet */ | ||
| 163 | at91_add_device_eth(&cpuat91_eth_data); | ||
| 164 | /* USB Host */ | ||
| 165 | at91_add_device_usbh(&cpuat91_usbh_data); | ||
| 166 | /* USB Device */ | ||
| 167 | at91_add_device_udc(&cpuat91_udc_data); | ||
| 168 | /* MMC */ | ||
| 169 | at91_add_device_mmc(0, &cpuat91_mmc_data); | ||
| 170 | /* I2C */ | ||
| 171 | at91_add_device_i2c(NULL, 0); | ||
| 172 | /* Platform devices */ | ||
| 173 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | ||
| 174 | } | ||
| 175 | |||
| 176 | MACHINE_START(CPUAT91, "Eukrea") | ||
| 177 | /* Maintainer: Eric Benard - EUKREA Electromatique */ | ||
| 178 | .phys_io = AT91_BASE_SYS, | ||
| 179 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 180 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 181 | .timer = &at91rm9200_timer, | ||
| 182 | .map_io = cpuat91_map_io, | ||
| 183 | .init_irq = cpuat91_init_irq, | ||
| 184 | .init_machine = cpuat91_board_init, | ||
| 185 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c index d5266da55311..f9b19993a7a9 100644 --- a/arch/arm/mach-at91/board-sam9261ek.c +++ b/arch/arm/mach-at91/board-sam9261ek.c | |||
| @@ -287,7 +287,11 @@ static void __init ek_add_device_ts(void) {} | |||
| 287 | */ | 287 | */ |
| 288 | static struct at73c213_board_info at73c213_data = { | 288 | static struct at73c213_board_info at73c213_data = { |
| 289 | .ssc_id = 1, | 289 | .ssc_id = 1, |
| 290 | #if defined(CONFIG_MACH_AT91SAM9261EK) | ||
| 290 | .shortname = "AT91SAM9261-EK external DAC", | 291 | .shortname = "AT91SAM9261-EK external DAC", |
| 292 | #else | ||
| 293 | .shortname = "AT91SAM9G10-EK external DAC", | ||
| 294 | #endif | ||
| 291 | }; | 295 | }; |
| 292 | 296 | ||
| 293 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) | 297 | #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE) |
| @@ -414,6 +418,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
| 414 | .default_monspecs = &at91fb_default_stn_monspecs, | 418 | .default_monspecs = &at91fb_default_stn_monspecs, |
| 415 | .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, | 419 | .atmel_lcdfb_power_control = at91_lcdc_stn_power_control, |
| 416 | .guard_time = 1, | 420 | .guard_time = 1, |
| 421 | #if defined(CONFIG_MACH_AT91SAM9G10EK) | ||
| 422 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 423 | #endif | ||
| 417 | }; | 424 | }; |
| 418 | 425 | ||
| 419 | #else | 426 | #else |
| @@ -467,6 +474,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | |||
| 467 | .default_monspecs = &at91fb_default_tft_monspecs, | 474 | .default_monspecs = &at91fb_default_tft_monspecs, |
| 468 | .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, | 475 | .atmel_lcdfb_power_control = at91_lcdc_tft_power_control, |
| 469 | .guard_time = 1, | 476 | .guard_time = 1, |
| 477 | #if defined(CONFIG_MACH_AT91SAM9G10EK) | ||
| 478 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 479 | #endif | ||
| 470 | }; | 480 | }; |
| 471 | #endif | 481 | #endif |
| 472 | 482 | ||
| @@ -600,7 +610,11 @@ static void __init ek_board_init(void) | |||
| 600 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | 610 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); |
| 601 | } | 611 | } |
| 602 | 612 | ||
| 613 | #if defined(CONFIG_MACH_AT91SAM9261EK) | ||
| 603 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") | 614 | MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK") |
| 615 | #else | ||
| 616 | MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK") | ||
| 617 | #endif | ||
| 604 | /* Maintainer: Atmel */ | 618 | /* Maintainer: Atmel */ |
| 605 | .phys_io = AT91_BASE_SYS, | 619 | .phys_io = AT91_BASE_SYS, |
| 606 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | 620 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, |
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c index 57d52528f224..1bf7bd4cbe13 100644 --- a/arch/arm/mach-at91/board-sam9263ek.c +++ b/arch/arm/mach-at91/board-sam9263ek.c | |||
| @@ -364,9 +364,9 @@ static void __init ek_add_device_buttons(void) {} | |||
| 364 | 364 | ||
| 365 | /* | 365 | /* |
| 366 | * AC97 | 366 | * AC97 |
| 367 | * reset_pin is not connected: NRST | ||
| 367 | */ | 368 | */ |
| 368 | static struct atmel_ac97_data ek_ac97_data = { | 369 | static struct ac97c_platform_data ek_ac97_data = { |
| 369 | .reset_pin = AT91_PIN_PA13, | ||
| 370 | }; | 370 | }; |
| 371 | 371 | ||
| 372 | 372 | ||
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index a55398ed1211..ca470d504ea0 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c | |||
| @@ -273,6 +273,7 @@ static void __init ek_add_device_buttons(void) {} | |||
| 273 | static struct i2c_board_info __initdata ek_i2c_devices[] = { | 273 | static struct i2c_board_info __initdata ek_i2c_devices[] = { |
| 274 | { | 274 | { |
| 275 | I2C_BOARD_INFO("24c512", 0x50), | 275 | I2C_BOARD_INFO("24c512", 0x50), |
| 276 | I2C_BOARD_INFO("wm8731", 0x1b), | ||
| 276 | }, | 277 | }, |
| 277 | }; | 278 | }; |
| 278 | 279 | ||
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c new file mode 100644 index 000000000000..b8558eae5229 --- /dev/null +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c | |||
| @@ -0,0 +1,389 @@ | |||
| 1 | /* | ||
| 2 | * Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family | ||
| 3 | * | ||
| 4 | * Covers: * AT91SAM9G45-EKES board | ||
| 5 | * * AT91SAM9M10G45-EK board | ||
| 6 | * | ||
| 7 | * Copyright (C) 2009 Atmel Corporation. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/mm.h> | ||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/platform_device.h> | ||
| 21 | #include <linux/spi/spi.h> | ||
| 22 | #include <linux/fb.h> | ||
| 23 | #include <linux/gpio_keys.h> | ||
| 24 | #include <linux/input.h> | ||
| 25 | #include <linux/leds.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | |||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <video/atmel_lcdc.h> | ||
| 30 | |||
| 31 | #include <asm/setup.h> | ||
| 32 | #include <asm/mach-types.h> | ||
| 33 | #include <asm/irq.h> | ||
| 34 | |||
| 35 | #include <asm/mach/arch.h> | ||
| 36 | #include <asm/mach/map.h> | ||
| 37 | #include <asm/mach/irq.h> | ||
| 38 | |||
| 39 | #include <mach/hardware.h> | ||
| 40 | #include <mach/board.h> | ||
| 41 | #include <mach/gpio.h> | ||
| 42 | #include <mach/at91sam9_smc.h> | ||
| 43 | #include <mach/at91_shdwc.h> | ||
| 44 | |||
| 45 | #include "sam9_smc.h" | ||
| 46 | #include "generic.h" | ||
| 47 | |||
| 48 | |||
| 49 | static void __init ek_map_io(void) | ||
| 50 | { | ||
| 51 | /* Initialize processor: 12.000 MHz crystal */ | ||
| 52 | at91sam9g45_initialize(12000000); | ||
| 53 | |||
| 54 | /* DGBU on ttyS0. (Rx & Tx only) */ | ||
| 55 | at91_register_uart(0, 0, 0); | ||
| 56 | |||
| 57 | /* USART0 not connected on the -EK board */ | ||
| 58 | /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ | ||
| 59 | at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); | ||
| 60 | |||
| 61 | /* set serial console to ttyS0 (ie, DBGU) */ | ||
| 62 | at91_set_serial_console(0); | ||
| 63 | } | ||
| 64 | |||
| 65 | static void __init ek_init_irq(void) | ||
| 66 | { | ||
| 67 | at91sam9g45_init_interrupts(NULL); | ||
| 68 | } | ||
| 69 | |||
| 70 | |||
| 71 | /* | ||
| 72 | * USB HS Host port (common to OHCI & EHCI) | ||
| 73 | */ | ||
| 74 | static struct at91_usbh_data __initdata ek_usbh_hs_data = { | ||
| 75 | .ports = 2, | ||
| 76 | .vbus_pin = {AT91_PIN_PD1, AT91_PIN_PD3}, | ||
| 77 | }; | ||
| 78 | |||
| 79 | |||
| 80 | /* | ||
| 81 | * USB HS Device port | ||
| 82 | */ | ||
| 83 | static struct usba_platform_data __initdata ek_usba_udc_data = { | ||
| 84 | .vbus_pin = AT91_PIN_PB19, | ||
| 85 | }; | ||
| 86 | |||
| 87 | |||
| 88 | /* | ||
| 89 | * SPI devices. | ||
| 90 | */ | ||
| 91 | static struct spi_board_info ek_spi_devices[] = { | ||
| 92 | { /* DataFlash chip */ | ||
| 93 | .modalias = "mtd_dataflash", | ||
| 94 | .chip_select = 0, | ||
| 95 | .max_speed_hz = 15 * 1000 * 1000, | ||
| 96 | .bus_num = 0, | ||
| 97 | }, | ||
| 98 | }; | ||
| 99 | |||
| 100 | |||
| 101 | /* | ||
| 102 | * MACB Ethernet device | ||
| 103 | */ | ||
| 104 | static struct at91_eth_data __initdata ek_macb_data = { | ||
| 105 | .phy_irq_pin = AT91_PIN_PD5, | ||
| 106 | .is_rmii = 1, | ||
| 107 | }; | ||
| 108 | |||
| 109 | |||
| 110 | /* | ||
| 111 | * NAND flash | ||
| 112 | */ | ||
| 113 | static struct mtd_partition __initdata ek_nand_partition[] = { | ||
| 114 | { | ||
| 115 | .name = "Partition 1", | ||
| 116 | .offset = 0, | ||
| 117 | .size = SZ_64M, | ||
| 118 | }, | ||
| 119 | { | ||
| 120 | .name = "Partition 2", | ||
| 121 | .offset = MTDPART_OFS_NXTBLK, | ||
| 122 | .size = MTDPART_SIZ_FULL, | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) | ||
| 127 | { | ||
| 128 | *num_partitions = ARRAY_SIZE(ek_nand_partition); | ||
| 129 | return ek_nand_partition; | ||
| 130 | } | ||
| 131 | |||
| 132 | /* det_pin is not connected */ | ||
| 133 | static struct atmel_nand_data __initdata ek_nand_data = { | ||
| 134 | .ale = 21, | ||
| 135 | .cle = 22, | ||
| 136 | .rdy_pin = AT91_PIN_PC8, | ||
| 137 | .enable_pin = AT91_PIN_PC14, | ||
| 138 | .partition_info = nand_partitions, | ||
| 139 | #if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16) | ||
| 140 | .bus_width_16 = 1, | ||
| 141 | #else | ||
| 142 | .bus_width_16 = 0, | ||
| 143 | #endif | ||
| 144 | }; | ||
| 145 | |||
| 146 | static struct sam9_smc_config __initdata ek_nand_smc_config = { | ||
| 147 | .ncs_read_setup = 0, | ||
| 148 | .nrd_setup = 2, | ||
| 149 | .ncs_write_setup = 0, | ||
| 150 | .nwe_setup = 2, | ||
| 151 | |||
| 152 | .ncs_read_pulse = 4, | ||
| 153 | .nrd_pulse = 4, | ||
| 154 | .ncs_write_pulse = 4, | ||
| 155 | .nwe_pulse = 4, | ||
| 156 | |||
| 157 | .read_cycle = 7, | ||
| 158 | .write_cycle = 7, | ||
| 159 | |||
| 160 | .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE, | ||
| 161 | .tdf_cycles = 3, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static void __init ek_add_device_nand(void) | ||
| 165 | { | ||
| 166 | /* setup bus-width (8 or 16) */ | ||
| 167 | if (ek_nand_data.bus_width_16) | ||
| 168 | ek_nand_smc_config.mode |= AT91_SMC_DBW_16; | ||
| 169 | else | ||
| 170 | ek_nand_smc_config.mode |= AT91_SMC_DBW_8; | ||
| 171 | |||
| 172 | /* configure chip-select 3 (NAND) */ | ||
| 173 | sam9_smc_configure(3, &ek_nand_smc_config); | ||
| 174 | |||
| 175 | at91_add_device_nand(&ek_nand_data); | ||
| 176 | } | ||
| 177 | |||
| 178 | |||
| 179 | /* | ||
| 180 | * LCD Controller | ||
| 181 | */ | ||
| 182 | #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE) | ||
| 183 | static struct fb_videomode at91_tft_vga_modes[] = { | ||
| 184 | { | ||
| 185 | .name = "LG", | ||
| 186 | .refresh = 60, | ||
| 187 | .xres = 480, .yres = 272, | ||
| 188 | .pixclock = KHZ2PICOS(9000), | ||
| 189 | |||
| 190 | .left_margin = 1, .right_margin = 1, | ||
| 191 | .upper_margin = 40, .lower_margin = 1, | ||
| 192 | .hsync_len = 45, .vsync_len = 1, | ||
| 193 | |||
| 194 | .sync = 0, | ||
| 195 | .vmode = FB_VMODE_NONINTERLACED, | ||
| 196 | }, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct fb_monspecs at91fb_default_monspecs = { | ||
| 200 | .manufacturer = "LG", | ||
| 201 | .monitor = "LB043WQ1", | ||
| 202 | |||
| 203 | .modedb = at91_tft_vga_modes, | ||
| 204 | .modedb_len = ARRAY_SIZE(at91_tft_vga_modes), | ||
| 205 | .hfmin = 15000, | ||
| 206 | .hfmax = 17640, | ||
| 207 | .vfmin = 57, | ||
| 208 | .vfmax = 67, | ||
| 209 | }; | ||
| 210 | |||
| 211 | #define AT91SAM9G45_DEFAULT_LCDCON2 (ATMEL_LCDC_MEMOR_LITTLE \ | ||
| 212 | | ATMEL_LCDC_DISTYPE_TFT \ | ||
| 213 | | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE) | ||
| 214 | |||
| 215 | /* Driver datas */ | ||
| 216 | static struct atmel_lcdfb_info __initdata ek_lcdc_data = { | ||
| 217 | .lcdcon_is_backlight = true, | ||
| 218 | .default_bpp = 32, | ||
| 219 | .default_dmacon = ATMEL_LCDC_DMAEN, | ||
| 220 | .default_lcdcon2 = AT91SAM9G45_DEFAULT_LCDCON2, | ||
| 221 | .default_monspecs = &at91fb_default_monspecs, | ||
| 222 | .guard_time = 9, | ||
| 223 | .lcd_wiring_mode = ATMEL_LCDC_WIRING_RGB, | ||
| 224 | }; | ||
| 225 | |||
| 226 | #else | ||
| 227 | static struct atmel_lcdfb_info __initdata ek_lcdc_data; | ||
| 228 | #endif | ||
| 229 | |||
| 230 | |||
| 231 | /* | ||
| 232 | * GPIO Buttons | ||
| 233 | */ | ||
| 234 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 235 | static struct gpio_keys_button ek_buttons[] = { | ||
| 236 | { /* BP1, "leftclic" */ | ||
| 237 | .code = BTN_LEFT, | ||
| 238 | .gpio = AT91_PIN_PB6, | ||
| 239 | .active_low = 1, | ||
| 240 | .desc = "left_click", | ||
| 241 | .wakeup = 1, | ||
| 242 | }, | ||
| 243 | { /* BP2, "rightclic" */ | ||
| 244 | .code = BTN_RIGHT, | ||
| 245 | .gpio = AT91_PIN_PB7, | ||
| 246 | .active_low = 1, | ||
| 247 | .desc = "right_click", | ||
| 248 | .wakeup = 1, | ||
| 249 | }, | ||
| 250 | /* BP3, "joystick" */ | ||
| 251 | { | ||
| 252 | .code = KEY_LEFT, | ||
| 253 | .gpio = AT91_PIN_PB14, | ||
| 254 | .active_low = 1, | ||
| 255 | .desc = "Joystick Left", | ||
| 256 | }, | ||
| 257 | { | ||
| 258 | .code = KEY_RIGHT, | ||
| 259 | .gpio = AT91_PIN_PB15, | ||
| 260 | .active_low = 1, | ||
| 261 | .desc = "Joystick Right", | ||
| 262 | }, | ||
| 263 | { | ||
| 264 | .code = KEY_UP, | ||
| 265 | .gpio = AT91_PIN_PB16, | ||
| 266 | .active_low = 1, | ||
| 267 | .desc = "Joystick Up", | ||
| 268 | }, | ||
| 269 | { | ||
| 270 | .code = KEY_DOWN, | ||
| 271 | .gpio = AT91_PIN_PB17, | ||
| 272 | .active_low = 1, | ||
| 273 | .desc = "Joystick Down", | ||
| 274 | }, | ||
| 275 | { | ||
| 276 | .code = KEY_ENTER, | ||
| 277 | .gpio = AT91_PIN_PB18, | ||
| 278 | .active_low = 1, | ||
| 279 | .desc = "Joystick Press", | ||
| 280 | }, | ||
| 281 | }; | ||
| 282 | |||
| 283 | static struct gpio_keys_platform_data ek_button_data = { | ||
| 284 | .buttons = ek_buttons, | ||
| 285 | .nbuttons = ARRAY_SIZE(ek_buttons), | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct platform_device ek_button_device = { | ||
| 289 | .name = "gpio-keys", | ||
| 290 | .id = -1, | ||
| 291 | .num_resources = 0, | ||
| 292 | .dev = { | ||
| 293 | .platform_data = &ek_button_data, | ||
| 294 | } | ||
| 295 | }; | ||
| 296 | |||
| 297 | static void __init ek_add_device_buttons(void) | ||
| 298 | { | ||
| 299 | int i; | ||
| 300 | |||
| 301 | for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) { | ||
| 302 | at91_set_GPIO_periph(ek_buttons[i].gpio, 1); | ||
| 303 | at91_set_deglitch(ek_buttons[i].gpio, 1); | ||
| 304 | } | ||
| 305 | |||
| 306 | platform_device_register(&ek_button_device); | ||
| 307 | } | ||
| 308 | #else | ||
| 309 | static void __init ek_add_device_buttons(void) {} | ||
| 310 | #endif | ||
| 311 | |||
| 312 | |||
| 313 | /* | ||
| 314 | * LEDs ... these could all be PWM-driven, for variable brightness | ||
| 315 | */ | ||
| 316 | static struct gpio_led ek_leds[] = { | ||
| 317 | { /* "top" led, red, powerled */ | ||
| 318 | .name = "d8", | ||
| 319 | .gpio = AT91_PIN_PD30, | ||
| 320 | .default_trigger = "heartbeat", | ||
| 321 | }, | ||
| 322 | { /* "left" led, green, userled2, pwm3 */ | ||
| 323 | .name = "d6", | ||
| 324 | .gpio = AT91_PIN_PD0, | ||
| 325 | .active_low = 1, | ||
| 326 | .default_trigger = "nand-disk", | ||
| 327 | }, | ||
| 328 | #if !(defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE)) | ||
| 329 | { /* "right" led, green, userled1, pwm1 */ | ||
| 330 | .name = "d7", | ||
| 331 | .gpio = AT91_PIN_PD31, | ||
| 332 | .active_low = 1, | ||
| 333 | .default_trigger = "mmc0", | ||
| 334 | }, | ||
| 335 | #endif | ||
| 336 | }; | ||
| 337 | |||
| 338 | |||
| 339 | /* | ||
| 340 | * PWM Leds | ||
| 341 | */ | ||
| 342 | static struct gpio_led ek_pwm_led[] = { | ||
| 343 | #if defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE) | ||
| 344 | { /* "right" led, green, userled1, pwm1 */ | ||
| 345 | .name = "d7", | ||
| 346 | .gpio = 1, /* is PWM channel number */ | ||
| 347 | .active_low = 1, | ||
| 348 | .default_trigger = "none", | ||
| 349 | }, | ||
| 350 | #endif | ||
| 351 | }; | ||
| 352 | |||
| 353 | |||
| 354 | |||
| 355 | static void __init ek_board_init(void) | ||
| 356 | { | ||
| 357 | /* Serial */ | ||
| 358 | at91_add_device_serial(); | ||
| 359 | /* USB HS Host */ | ||
| 360 | at91_add_device_usbh_ohci(&ek_usbh_hs_data); | ||
| 361 | /* USB HS Device */ | ||
| 362 | at91_add_device_usba(&ek_usba_udc_data); | ||
| 363 | /* SPI */ | ||
| 364 | at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); | ||
| 365 | /* Ethernet */ | ||
| 366 | at91_add_device_eth(&ek_macb_data); | ||
| 367 | /* NAND */ | ||
| 368 | ek_add_device_nand(); | ||
| 369 | /* I2C */ | ||
| 370 | at91_add_device_i2c(0, NULL, 0); | ||
| 371 | /* LCD Controller */ | ||
| 372 | at91_add_device_lcdc(&ek_lcdc_data); | ||
| 373 | /* Push Buttons */ | ||
| 374 | ek_add_device_buttons(); | ||
| 375 | /* LEDs */ | ||
| 376 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | ||
| 377 | at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led)); | ||
| 378 | } | ||
| 379 | |||
| 380 | MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES") | ||
| 381 | /* Maintainer: Atmel */ | ||
| 382 | .phys_io = AT91_BASE_SYS, | ||
| 383 | .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, | ||
| 384 | .boot_params = AT91_SDRAM_BASE + 0x100, | ||
| 385 | .timer = &at91sam926x_timer, | ||
| 386 | .map_io = ek_map_io, | ||
| 387 | .init_irq = ek_init_irq, | ||
| 388 | .init_machine = ek_board_init, | ||
| 389 | MACHINE_END | ||
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c index f6b5672cabd6..9d07679efce7 100644 --- a/arch/arm/mach-at91/board-sam9rlek.c +++ b/arch/arm/mach-at91/board-sam9rlek.c | |||
| @@ -15,6 +15,8 @@ | |||
| 15 | #include <linux/spi/spi.h> | 15 | #include <linux/spi/spi.h> |
| 16 | #include <linux/fb.h> | 16 | #include <linux/fb.h> |
| 17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
| 18 | #include <linux/input.h> | ||
| 19 | #include <linux/gpio_keys.h> | ||
| 18 | 20 | ||
| 19 | #include <video/atmel_lcdc.h> | 21 | #include <video/atmel_lcdc.h> |
| 20 | 22 | ||
| @@ -208,6 +210,79 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data; | |||
| 208 | #endif | 210 | #endif |
| 209 | 211 | ||
| 210 | 212 | ||
| 213 | /* | ||
| 214 | * LEDs | ||
| 215 | */ | ||
| 216 | static struct gpio_led ek_leds[] = { | ||
| 217 | { /* "bottom" led, green, userled1 to be defined */ | ||
| 218 | .name = "ds1", | ||
| 219 | .gpio = AT91_PIN_PD15, | ||
| 220 | .active_low = 1, | ||
| 221 | .default_trigger = "none", | ||
| 222 | }, | ||
| 223 | { /* "bottom" led, green, userled2 to be defined */ | ||
| 224 | .name = "ds2", | ||
| 225 | .gpio = AT91_PIN_PD16, | ||
| 226 | .active_low = 1, | ||
| 227 | .default_trigger = "none", | ||
| 228 | }, | ||
| 229 | { /* "power" led, yellow */ | ||
| 230 | .name = "ds3", | ||
| 231 | .gpio = AT91_PIN_PD14, | ||
| 232 | .default_trigger = "heartbeat", | ||
| 233 | } | ||
| 234 | }; | ||
| 235 | |||
| 236 | |||
| 237 | /* | ||
| 238 | * GPIO Buttons | ||
| 239 | */ | ||
| 240 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 241 | static struct gpio_keys_button ek_buttons[] = { | ||
| 242 | { | ||
| 243 | .gpio = AT91_PIN_PB0, | ||
| 244 | .code = BTN_2, | ||
| 245 | .desc = "Right Click", | ||
| 246 | .active_low = 1, | ||
| 247 | .wakeup = 1, | ||
| 248 | }, | ||
| 249 | { | ||
| 250 | .gpio = AT91_PIN_PB1, | ||
| 251 | .code = BTN_1, | ||
| 252 | .desc = "Left Click", | ||
| 253 | .active_low = 1, | ||
| 254 | .wakeup = 1, | ||
| 255 | } | ||
| 256 | }; | ||
| 257 | |||
| 258 | static struct gpio_keys_platform_data ek_button_data = { | ||
| 259 | .buttons = ek_buttons, | ||
| 260 | .nbuttons = ARRAY_SIZE(ek_buttons), | ||
| 261 | }; | ||
| 262 | |||
| 263 | static struct platform_device ek_button_device = { | ||
| 264 | .name = "gpio-keys", | ||
| 265 | .id = -1, | ||
| 266 | .num_resources = 0, | ||
| 267 | .dev = { | ||
| 268 | .platform_data = &ek_button_data, | ||
| 269 | } | ||
| 270 | }; | ||
| 271 | |||
| 272 | static void __init ek_add_device_buttons(void) | ||
| 273 | { | ||
| 274 | at91_set_gpio_input(AT91_PIN_PB1, 1); /* btn1 */ | ||
| 275 | at91_set_deglitch(AT91_PIN_PB1, 1); | ||
| 276 | at91_set_gpio_input(AT91_PIN_PB0, 1); /* btn2 */ | ||
| 277 | at91_set_deglitch(AT91_PIN_PB0, 1); | ||
| 278 | |||
| 279 | platform_device_register(&ek_button_device); | ||
| 280 | } | ||
| 281 | #else | ||
| 282 | static void __init ek_add_device_buttons(void) {} | ||
| 283 | #endif | ||
| 284 | |||
| 285 | |||
| 211 | static void __init ek_board_init(void) | 286 | static void __init ek_board_init(void) |
| 212 | { | 287 | { |
| 213 | /* Serial */ | 288 | /* Serial */ |
| @@ -226,6 +301,10 @@ static void __init ek_board_init(void) | |||
| 226 | at91_add_device_lcdc(&ek_lcdc_data); | 301 | at91_add_device_lcdc(&ek_lcdc_data); |
| 227 | /* Touch Screen Controller */ | 302 | /* Touch Screen Controller */ |
| 228 | at91_add_device_tsadcc(); | 303 | at91_add_device_tsadcc(); |
| 304 | /* LEDs */ | ||
| 305 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | ||
| 306 | /* Push Buttons */ | ||
| 307 | ek_add_device_buttons(); | ||
| 229 | } | 308 | } |
| 230 | 309 | ||
| 231 | MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") | 310 | MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK") |
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index bac578fe0d3d..c042dcf4725f 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c | |||
| @@ -47,20 +47,25 @@ | |||
| 47 | * Chips have some kind of clocks : group them by functionality | 47 | * Chips have some kind of clocks : group them by functionality |
| 48 | */ | 48 | */ |
| 49 | #define cpu_has_utmi() ( cpu_is_at91cap9() \ | 49 | #define cpu_has_utmi() ( cpu_is_at91cap9() \ |
| 50 | || cpu_is_at91sam9rl()) | 50 | || cpu_is_at91sam9rl() \ |
| 51 | || cpu_is_at91sam9g45()) | ||
| 51 | 52 | ||
| 52 | #define cpu_has_800M_plla() (cpu_is_at91sam9g20()) | 53 | #define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \ |
| 54 | || cpu_is_at91sam9g45()) | ||
| 53 | 55 | ||
| 54 | #define cpu_has_pllb() (!cpu_is_at91sam9rl()) | 56 | #define cpu_has_300M_plla() (cpu_is_at91sam9g10()) |
| 55 | 57 | ||
| 56 | #define cpu_has_upll() (0) | 58 | #define cpu_has_pllb() (!(cpu_is_at91sam9rl() \ |
| 59 | || cpu_is_at91sam9g45())) | ||
| 60 | |||
| 61 | #define cpu_has_upll() (cpu_is_at91sam9g45()) | ||
| 57 | 62 | ||
| 58 | /* USB host HS & FS */ | 63 | /* USB host HS & FS */ |
| 59 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) | 64 | #define cpu_has_uhp() (!cpu_is_at91sam9rl()) |
| 60 | 65 | ||
| 61 | /* USB device FS only */ | 66 | /* USB device FS only */ |
| 62 | #define cpu_has_udpfs() (!cpu_is_at91sam9rl()) | 67 | #define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \ |
| 63 | 68 | || cpu_is_at91sam9g45())) | |
| 64 | 69 | ||
| 65 | static LIST_HEAD(clocks); | 70 | static LIST_HEAD(clocks); |
| 66 | static DEFINE_SPINLOCK(clk_lock); | 71 | static DEFINE_SPINLOCK(clk_lock); |
| @@ -133,6 +138,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on) | |||
| 133 | { | 138 | { |
| 134 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); | 139 | unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR); |
| 135 | 140 | ||
| 141 | if (cpu_is_at91sam9g45()) { | ||
| 142 | if (is_on) | ||
| 143 | uckr |= AT91_PMC_BIASEN; | ||
| 144 | else | ||
| 145 | uckr &= ~AT91_PMC_BIASEN; | ||
| 146 | } | ||
| 147 | |||
| 136 | if (is_on) { | 148 | if (is_on) { |
| 137 | is_on = AT91_PMC_LOCKU; | 149 | is_on = AT91_PMC_LOCKU; |
| 138 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); | 150 | at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask); |
| @@ -310,6 +322,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate) | |||
| 310 | unsigned long flags; | 322 | unsigned long flags; |
| 311 | unsigned prescale; | 323 | unsigned prescale; |
| 312 | unsigned long actual; | 324 | unsigned long actual; |
| 325 | unsigned long prev = ULONG_MAX; | ||
| 313 | 326 | ||
| 314 | if (!clk_is_programmable(clk)) | 327 | if (!clk_is_programmable(clk)) |
| 315 | return -EINVAL; | 328 | return -EINVAL; |
| @@ -317,8 +330,16 @@ long clk_round_rate(struct clk *clk, unsigned long rate) | |||
| 317 | 330 | ||
| 318 | actual = clk->parent->rate_hz; | 331 | actual = clk->parent->rate_hz; |
| 319 | for (prescale = 0; prescale < 7; prescale++) { | 332 | for (prescale = 0; prescale < 7; prescale++) { |
| 320 | if (actual && actual <= rate) | 333 | if (actual > rate) |
| 334 | prev = actual; | ||
| 335 | |||
| 336 | if (actual && actual <= rate) { | ||
| 337 | if ((prev - rate) < (rate - actual)) { | ||
| 338 | actual = prev; | ||
| 339 | prescale--; | ||
| 340 | } | ||
| 321 | break; | 341 | break; |
| 342 | } | ||
| 322 | actual >>= 1; | 343 | actual >>= 1; |
| 323 | } | 344 | } |
| 324 | 345 | ||
| @@ -373,6 +394,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
| 373 | return -EBUSY; | 394 | return -EBUSY; |
| 374 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) | 395 | if (!clk_is_primary(parent) || !clk_is_programmable(clk)) |
| 375 | return -EINVAL; | 396 | return -EINVAL; |
| 397 | |||
| 398 | if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB) | ||
| 399 | return -EINVAL; | ||
| 400 | |||
| 376 | spin_lock_irqsave(&clk_lock, flags); | 401 | spin_lock_irqsave(&clk_lock, flags); |
| 377 | 402 | ||
| 378 | clk->rate_hz = parent->rate_hz; | 403 | clk->rate_hz = parent->rate_hz; |
| @@ -601,7 +626,9 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock) | |||
| 601 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; | 626 | uhpck.pmc_mask = AT91RM9200_PMC_UHP; |
| 602 | udpck.pmc_mask = AT91RM9200_PMC_UDP; | 627 | udpck.pmc_mask = AT91RM9200_PMC_UDP; |
| 603 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); | 628 | at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); |
| 604 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { | 629 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || |
| 630 | cpu_is_at91sam9263() || cpu_is_at91sam9g20() || | ||
| 631 | cpu_is_at91sam9g10()) { | ||
| 605 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; | 632 | uhpck.pmc_mask = AT91SAM926x_PMC_UHP; |
| 606 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; | 633 | udpck.pmc_mask = AT91SAM926x_PMC_UDP; |
| 607 | } else if (cpu_is_at91cap9()) { | 634 | } else if (cpu_is_at91cap9()) { |
| @@ -637,6 +664,7 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 637 | { | 664 | { |
| 638 | unsigned tmp, freq, mckr; | 665 | unsigned tmp, freq, mckr; |
| 639 | int i; | 666 | int i; |
| 667 | int pll_overclock = false; | ||
| 640 | 668 | ||
| 641 | /* | 669 | /* |
| 642 | * When the bootloader initialized the main oscillator correctly, | 670 | * When the bootloader initialized the main oscillator correctly, |
| @@ -654,12 +682,25 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 654 | 682 | ||
| 655 | /* report if PLLA is more than mildly overclocked */ | 683 | /* report if PLLA is more than mildly overclocked */ |
| 656 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); | 684 | plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); |
| 657 | if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000) | 685 | if (cpu_has_300M_plla()) { |
| 658 | || (cpu_has_800M_plla() && plla.rate_hz > 800000000)) | 686 | if (plla.rate_hz > 300000000) |
| 687 | pll_overclock = true; | ||
| 688 | } else if (cpu_has_800M_plla()) { | ||
| 689 | if (plla.rate_hz > 800000000) | ||
| 690 | pll_overclock = true; | ||
| 691 | } else { | ||
| 692 | if (plla.rate_hz > 209000000) | ||
| 693 | pll_overclock = true; | ||
| 694 | } | ||
| 695 | if (pll_overclock) | ||
| 659 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); | 696 | pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); |
| 660 | 697 | ||
| 698 | if (cpu_is_at91sam9g45()) { | ||
| 699 | mckr = at91_sys_read(AT91_PMC_MCKR); | ||
| 700 | plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */ | ||
| 701 | } | ||
| 661 | 702 | ||
| 662 | if (cpu_has_upll() && !cpu_has_pllb()) { | 703 | if (!cpu_has_pllb() && cpu_has_upll()) { |
| 663 | /* setup UTMI clock as the fourth primary clock | 704 | /* setup UTMI clock as the fourth primary clock |
| 664 | * (instead of pllb) */ | 705 | * (instead of pllb) */ |
| 665 | utmi_clk.type |= CLK_TYPE_PRIMARY; | 706 | utmi_clk.type |= CLK_TYPE_PRIMARY; |
| @@ -701,6 +742,9 @@ int __init at91_clock_init(unsigned long main_clock) | |||
| 701 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ | 742 | freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ |
| 702 | if (mckr & AT91_PMC_PDIV) | 743 | if (mckr & AT91_PMC_PDIV) |
| 703 | freq /= 2; /* processor clock division */ | 744 | freq /= 2; /* processor clock division */ |
| 745 | } else if (cpu_is_at91sam9g45()) { | ||
| 746 | mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? | ||
| 747 | freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | ||
| 704 | } else { | 748 | } else { |
| 705 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ | 749 | mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ |
| 706 | } | 750 | } |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index b5daf7f5e011..88e413b38480 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
| @@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock); | |||
| 14 | extern void __init at91sam9261_initialize(unsigned long main_clock); | 14 | extern void __init at91sam9261_initialize(unsigned long main_clock); |
| 15 | extern void __init at91sam9263_initialize(unsigned long main_clock); | 15 | extern void __init at91sam9263_initialize(unsigned long main_clock); |
| 16 | extern void __init at91sam9rl_initialize(unsigned long main_clock); | 16 | extern void __init at91sam9rl_initialize(unsigned long main_clock); |
| 17 | extern void __init at91sam9g45_initialize(unsigned long main_clock); | ||
| 17 | extern void __init at91x40_initialize(unsigned long main_clock); | 18 | extern void __init at91x40_initialize(unsigned long main_clock); |
| 18 | extern void __init at91cap9_initialize(unsigned long main_clock); | 19 | extern void __init at91cap9_initialize(unsigned long main_clock); |
| 19 | 20 | ||
| @@ -23,6 +24,7 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]); | |||
| 23 | extern void __init at91sam9261_init_interrupts(unsigned int priority[]); | 24 | extern void __init at91sam9261_init_interrupts(unsigned int priority[]); |
| 24 | extern void __init at91sam9263_init_interrupts(unsigned int priority[]); | 25 | extern void __init at91sam9263_init_interrupts(unsigned int priority[]); |
| 25 | extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); | 26 | extern void __init at91sam9rl_init_interrupts(unsigned int priority[]); |
| 27 | extern void __init at91sam9g45_init_interrupts(unsigned int priority[]); | ||
| 26 | extern void __init at91x40_init_interrupts(unsigned int priority[]); | 28 | extern void __init at91x40_init_interrupts(unsigned int priority[]); |
| 27 | extern void __init at91cap9_init_interrupts(unsigned int priority[]); | 29 | extern void __init at91cap9_init_interrupts(unsigned int priority[]); |
| 28 | extern void __init at91_aic_init(unsigned int priority[]); | 30 | extern void __init at91_aic_init(unsigned int priority[]); |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index f2236f0e101f..ae4772e744ac 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
| @@ -44,13 +44,11 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip, | |||
| 44 | unsigned offset, int val); | 44 | unsigned offset, int val); |
| 45 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | 45 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, |
| 46 | unsigned offset); | 46 | unsigned offset); |
| 47 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset); | ||
| 48 | 47 | ||
| 49 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ | 48 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ |
| 50 | { \ | 49 | { \ |
| 51 | .chip = { \ | 50 | .chip = { \ |
| 52 | .label = name, \ | 51 | .label = name, \ |
| 53 | .request = at91_gpiolib_request, \ | ||
| 54 | .direction_input = at91_gpiolib_direction_input, \ | 52 | .direction_input = at91_gpiolib_direction_input, \ |
| 55 | .direction_output = at91_gpiolib_direction_output, \ | 53 | .direction_output = at91_gpiolib_direction_output, \ |
| 56 | .get = at91_gpiolib_get, \ | 54 | .get = at91_gpiolib_get, \ |
| @@ -588,19 +586,6 @@ static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | |||
| 588 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | 586 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); |
| 589 | } | 587 | } |
| 590 | 588 | ||
| 591 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset) | ||
| 592 | { | ||
| 593 | unsigned pin = chip->base + offset; | ||
| 594 | void __iomem *pio = pin_to_controller(pin); | ||
| 595 | unsigned mask = pin_to_mask(pin); | ||
| 596 | |||
| 597 | /* Cannot request GPIOs that are in alternate function mode */ | ||
| 598 | if (!(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 599 | return -EPERM; | ||
| 600 | |||
| 601 | return 0; | ||
| 602 | } | ||
| 603 | |||
| 604 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) | 589 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
| 605 | { | 590 | { |
| 606 | int i; | 591 | int i; |
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h index 3a348ca20773..87de8be17484 100644 --- a/arch/arm/mach-at91/include/mach/at91sam9261.h +++ b/arch/arm/mach-at91/include/mach/at91sam9261.h | |||
| @@ -95,6 +95,9 @@ | |||
| 95 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | 95 | #define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
| 96 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ | 96 | #define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */ |
| 97 | 97 | ||
| 98 | #define AT91SAM9G10_SRAM_BASE AT91SAM9261_SRAM_BASE /* Internal SRAM base address */ | ||
| 99 | #define AT91SAM9G10_SRAM_SIZE 0x00004000 /* Internal SRAM size (16Kb) */ | ||
| 100 | |||
| 98 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ | 101 | #define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */ |
| 99 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ | 102 | #define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ |
| 100 | 103 | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h new file mode 100644 index 000000000000..a526869aee37 --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h | |||
| @@ -0,0 +1,155 @@ | |||
| 1 | /* | ||
| 2 | * Chip-specific header file for the AT91SAM9G45 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Common definitions. | ||
| 7 | * Based on AT91SAM9G45 preliminary datasheet. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9G45_H | ||
| 16 | #define AT91SAM9G45_H | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Peripheral identifiers/interrupts. | ||
| 20 | */ | ||
| 21 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ | ||
| 22 | #define AT91_ID_SYS 1 /* System Controller Interrupt */ | ||
| 23 | #define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */ | ||
| 24 | #define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */ | ||
| 25 | #define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */ | ||
| 26 | #define AT91SAM9G45_ID_PIODE 5 /* Parallel I/O Controller D and E */ | ||
| 27 | #define AT91SAM9G45_ID_TRNG 6 /* True Random Number Generator */ | ||
| 28 | #define AT91SAM9G45_ID_US0 7 /* USART 0 */ | ||
| 29 | #define AT91SAM9G45_ID_US1 8 /* USART 1 */ | ||
| 30 | #define AT91SAM9G45_ID_US2 9 /* USART 2 */ | ||
| 31 | #define AT91SAM9G45_ID_US3 10 /* USART 3 */ | ||
| 32 | #define AT91SAM9G45_ID_MCI0 11 /* High Speed Multimedia Card Interface 0 */ | ||
| 33 | #define AT91SAM9G45_ID_TWI0 12 /* Two-Wire Interface 0 */ | ||
| 34 | #define AT91SAM9G45_ID_TWI1 13 /* Two-Wire Interface 1 */ | ||
| 35 | #define AT91SAM9G45_ID_SPI0 14 /* Serial Peripheral Interface 0 */ | ||
| 36 | #define AT91SAM9G45_ID_SPI1 15 /* Serial Peripheral Interface 1 */ | ||
| 37 | #define AT91SAM9G45_ID_SSC0 16 /* Synchronous Serial Controller 0 */ | ||
| 38 | #define AT91SAM9G45_ID_SSC1 17 /* Synchronous Serial Controller 1 */ | ||
| 39 | #define AT91SAM9G45_ID_TCB 18 /* Timer Counter 0, 1, 2, 3, 4 and 5 */ | ||
| 40 | #define AT91SAM9G45_ID_PWMC 19 /* Pulse Width Modulation Controller */ | ||
| 41 | #define AT91SAM9G45_ID_TSC 20 /* Touch Screen ADC Controller */ | ||
| 42 | #define AT91SAM9G45_ID_DMA 21 /* DMA Controller */ | ||
| 43 | #define AT91SAM9G45_ID_UHPHS 22 /* USB Host High Speed */ | ||
| 44 | #define AT91SAM9G45_ID_LCDC 23 /* LCD Controller */ | ||
| 45 | #define AT91SAM9G45_ID_AC97C 24 /* AC97 Controller */ | ||
| 46 | #define AT91SAM9G45_ID_EMAC 25 /* Ethernet MAC */ | ||
| 47 | #define AT91SAM9G45_ID_ISI 26 /* Image Sensor Interface */ | ||
| 48 | #define AT91SAM9G45_ID_UDPHS 27 /* USB Device High Speed */ | ||
| 49 | #define AT91SAM9G45_ID_AESTDESSHA 28 /* AES + T-DES + SHA */ | ||
| 50 | #define AT91SAM9G45_ID_MCI1 29 /* High Speed Multimedia Card Interface 1 */ | ||
| 51 | #define AT91SAM9G45_ID_VDEC 30 /* Video Decoder */ | ||
| 52 | #define AT91SAM9G45_ID_IRQ0 31 /* Advanced Interrupt Controller */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * User Peripheral physical base addresses. | ||
| 56 | */ | ||
| 57 | #define AT91SAM9G45_BASE_UDPHS 0xfff78000 | ||
| 58 | #define AT91SAM9G45_BASE_TCB0 0xfff7c000 | ||
| 59 | #define AT91SAM9G45_BASE_TC0 0xfff7c000 | ||
| 60 | #define AT91SAM9G45_BASE_TC1 0xfff7c040 | ||
| 61 | #define AT91SAM9G45_BASE_TC2 0xfff7c080 | ||
| 62 | #define AT91SAM9G45_BASE_MCI0 0xfff80000 | ||
| 63 | #define AT91SAM9G45_BASE_TWI0 0xfff84000 | ||
| 64 | #define AT91SAM9G45_BASE_TWI1 0xfff88000 | ||
| 65 | #define AT91SAM9G45_BASE_US0 0xfff8c000 | ||
| 66 | #define AT91SAM9G45_BASE_US1 0xfff90000 | ||
| 67 | #define AT91SAM9G45_BASE_US2 0xfff94000 | ||
| 68 | #define AT91SAM9G45_BASE_US3 0xfff98000 | ||
| 69 | #define AT91SAM9G45_BASE_SSC0 0xfff9c000 | ||
| 70 | #define AT91SAM9G45_BASE_SSC1 0xfffa0000 | ||
| 71 | #define AT91SAM9G45_BASE_SPI0 0xfffa4000 | ||
| 72 | #define AT91SAM9G45_BASE_SPI1 0xfffa8000 | ||
| 73 | #define AT91SAM9G45_BASE_AC97C 0xfffac000 | ||
| 74 | #define AT91SAM9G45_BASE_TSC 0xfffb0000 | ||
| 75 | #define AT91SAM9G45_BASE_ISI 0xfffb4000 | ||
| 76 | #define AT91SAM9G45_BASE_PWMC 0xfffb8000 | ||
| 77 | #define AT91SAM9G45_BASE_EMAC 0xfffbc000 | ||
| 78 | #define AT91SAM9G45_BASE_AES 0xfffc0000 | ||
| 79 | #define AT91SAM9G45_BASE_TDES 0xfffc4000 | ||
| 80 | #define AT91SAM9G45_BASE_SHA 0xfffc8000 | ||
| 81 | #define AT91SAM9G45_BASE_TRNG 0xfffcc000 | ||
| 82 | #define AT91SAM9G45_BASE_MCI1 0xfffd0000 | ||
| 83 | #define AT91SAM9G45_BASE_TCB1 0xfffd4000 | ||
| 84 | #define AT91SAM9G45_BASE_TC3 0xfffd4000 | ||
| 85 | #define AT91SAM9G45_BASE_TC4 0xfffd4040 | ||
| 86 | #define AT91SAM9G45_BASE_TC5 0xfffd4080 | ||
| 87 | #define AT91_BASE_SYS 0xffffe200 | ||
| 88 | |||
| 89 | /* | ||
| 90 | * System Peripherals (offset from AT91_BASE_SYS) | ||
| 91 | */ | ||
| 92 | #define AT91_ECC (0xffffe200 - AT91_BASE_SYS) | ||
| 93 | #define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS) | ||
| 94 | #define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS) | ||
| 95 | #define AT91_SMC (0xffffe800 - AT91_BASE_SYS) | ||
| 96 | #define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS) | ||
| 97 | #define AT91_DMA (0xffffec00 - AT91_BASE_SYS) | ||
| 98 | #define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) | ||
| 99 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) | ||
| 100 | #define AT91_PIOA (0xfffff200 - AT91_BASE_SYS) | ||
| 101 | #define AT91_PIOB (0xfffff400 - AT91_BASE_SYS) | ||
| 102 | #define AT91_PIOC (0xfffff600 - AT91_BASE_SYS) | ||
| 103 | #define AT91_PIOD (0xfffff800 - AT91_BASE_SYS) | ||
| 104 | #define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS) | ||
| 105 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) | ||
| 106 | #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) | ||
| 107 | #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) | ||
| 108 | #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) | ||
| 109 | #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) | ||
| 110 | #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) | ||
| 111 | #define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) | ||
| 112 | #define AT91_RTC (0xfffffdb0 - AT91_BASE_SYS) | ||
| 113 | |||
| 114 | #define AT91_USART0 AT91SAM9G45_BASE_US0 | ||
| 115 | #define AT91_USART1 AT91SAM9G45_BASE_US1 | ||
| 116 | #define AT91_USART2 AT91SAM9G45_BASE_US2 | ||
| 117 | #define AT91_USART3 AT91SAM9G45_BASE_US3 | ||
| 118 | |||
| 119 | /* | ||
| 120 | * Internal Memory. | ||
| 121 | */ | ||
| 122 | #define AT91SAM9G45_SRAM_BASE 0x00300000 /* Internal SRAM base address */ | ||
| 123 | #define AT91SAM9G45_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ | ||
| 124 | |||
| 125 | #define AT91SAM9G45_ROM_BASE 0x00400000 /* Internal ROM base address */ | ||
| 126 | #define AT91SAM9G45_ROM_SIZE SZ_64K /* Internal ROM size (64Kb) */ | ||
| 127 | |||
| 128 | #define AT91SAM9G45_LCDC_BASE 0x00500000 /* LCD Controller */ | ||
| 129 | #define AT91SAM9G45_UDPHS_FIFO 0x00600000 /* USB Device HS controller */ | ||
| 130 | #define AT91SAM9G45_OHCI_BASE 0x00700000 /* USB Host controller (OHCI) */ | ||
| 131 | #define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ | ||
| 132 | #define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ | ||
| 133 | |||
| 134 | #define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 | ||
| 135 | |||
| 136 | #define CONSISTENT_DMA_SIZE SZ_4M | ||
| 137 | |||
| 138 | /* | ||
| 139 | * DMA peripheral identifiers | ||
| 140 | * for hardware handshaking interface | ||
| 141 | */ | ||
| 142 | #define AT_DMA_ID_MCI0 0 | ||
| 143 | #define AT_DMA_ID_SPI0_TX 1 | ||
| 144 | #define AT_DMA_ID_SPI0_RX 2 | ||
| 145 | #define AT_DMA_ID_SPI1_TX 3 | ||
| 146 | #define AT_DMA_ID_SPI1_RX 4 | ||
| 147 | #define AT_DMA_ID_SSC0_TX 5 | ||
| 148 | #define AT_DMA_ID_SSC0_RX 6 | ||
| 149 | #define AT_DMA_ID_SSC1_TX 7 | ||
| 150 | #define AT_DMA_ID_SSC1_RX 8 | ||
| 151 | #define AT_DMA_ID_AC97_TX 9 | ||
| 152 | #define AT_DMA_ID_AC97_RX 10 | ||
| 153 | #define AT_DMA_ID_MCI1 13 | ||
| 154 | |||
| 155 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h new file mode 100644 index 000000000000..c972d60e0aeb --- /dev/null +++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h | |||
| @@ -0,0 +1,153 @@ | |||
| 1 | /* | ||
| 2 | * Matrix-centric header file for the AT91SAM9G45 family | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Atmel Corporation. | ||
| 5 | * | ||
| 6 | * Memory Controllers (MATRIX, EBI) - System peripherals registers. | ||
| 7 | * Based on AT91SAM9G45 preliminary datasheet. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91SAM9G45_MATRIX_H | ||
| 16 | #define AT91SAM9G45_MATRIX_H | ||
| 17 | |||
| 18 | #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ | ||
| 19 | #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ | ||
| 20 | #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ | ||
| 21 | #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ | ||
| 22 | #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ | ||
| 23 | #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ | ||
| 24 | #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */ | ||
| 25 | #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */ | ||
| 26 | #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */ | ||
| 27 | #define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */ | ||
| 28 | #define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */ | ||
| 29 | #define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */ | ||
| 30 | #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ | ||
| 31 | #define AT91_MATRIX_ULBT_INFINITE (0 << 0) | ||
| 32 | #define AT91_MATRIX_ULBT_SINGLE (1 << 0) | ||
| 33 | #define AT91_MATRIX_ULBT_FOUR (2 << 0) | ||
| 34 | #define AT91_MATRIX_ULBT_EIGHT (3 << 0) | ||
| 35 | #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) | ||
| 36 | #define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0) | ||
| 37 | #define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0) | ||
| 38 | #define AT91_MATRIX_ULBT_128 (7 << 0) | ||
| 39 | |||
| 40 | #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ | ||
| 41 | #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ | ||
| 42 | #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ | ||
| 43 | #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ | ||
| 44 | #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ | ||
| 45 | #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ | ||
| 46 | #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */ | ||
| 47 | #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */ | ||
| 48 | #define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */ | ||
| 49 | #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ | ||
| 50 | #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) | ||
| 51 | #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) | ||
| 52 | #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) | ||
| 53 | #define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ | ||
| 54 | |||
| 55 | #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ | ||
| 56 | #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */ | ||
| 57 | #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ | ||
| 58 | #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */ | ||
| 59 | #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ | ||
| 60 | #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */ | ||
| 61 | #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ | ||
| 62 | #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */ | ||
| 63 | #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ | ||
| 64 | #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */ | ||
| 65 | #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ | ||
| 66 | #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */ | ||
| 67 | #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */ | ||
| 68 | #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */ | ||
| 69 | #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */ | ||
| 70 | #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */ | ||
| 71 | #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ | ||
| 72 | #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ | ||
| 73 | #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ | ||
| 74 | #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ | ||
| 75 | #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ | ||
| 76 | #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ | ||
| 77 | #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */ | ||
| 78 | #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */ | ||
| 79 | #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */ | ||
| 80 | #define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */ | ||
| 81 | #define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */ | ||
| 82 | #define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */ | ||
| 83 | |||
| 84 | #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ | ||
| 85 | #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ | ||
| 86 | #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ | ||
| 87 | #define AT91_MATRIX_RCB2 (1 << 2) | ||
| 88 | #define AT91_MATRIX_RCB3 (1 << 3) | ||
| 89 | #define AT91_MATRIX_RCB4 (1 << 4) | ||
| 90 | #define AT91_MATRIX_RCB5 (1 << 5) | ||
| 91 | #define AT91_MATRIX_RCB6 (1 << 6) | ||
| 92 | #define AT91_MATRIX_RCB7 (1 << 7) | ||
| 93 | #define AT91_MATRIX_RCB8 (1 << 8) | ||
| 94 | #define AT91_MATRIX_RCB9 (1 << 9) | ||
| 95 | #define AT91_MATRIX_RCB10 (1 << 10) | ||
| 96 | #define AT91_MATRIX_RCB11 (1 << 11) | ||
| 97 | |||
| 98 | #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */ | ||
| 99 | #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ | ||
| 100 | #define AT91_MATRIX_ITCM_0 (0 << 0) | ||
| 101 | #define AT91_MATRIX_ITCM_32 (6 << 0) | ||
| 102 | #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ | ||
| 103 | #define AT91_MATRIX_DTCM_0 (0 << 4) | ||
| 104 | #define AT91_MATRIX_DTCM_32 (6 << 4) | ||
| 105 | #define AT91_MATRIX_DTCM_64 (7 << 4) | ||
| 106 | #define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */ | ||
| 107 | #define AT91_MATRIX_TCM_NO_WS (0x0 << 11) | ||
| 108 | #define AT91_MATRIX_TCM_ONE_WS (0x1 << 11) | ||
| 109 | |||
| 110 | #define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */ | ||
| 111 | #define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */ | ||
| 112 | #define AT91C_VDEC_SEL_OFF (0 << 0) | ||
| 113 | #define AT91C_VDEC_SEL_ON (1 << 0) | ||
| 114 | |||
| 115 | #define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */ | ||
| 116 | #define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ | ||
| 117 | #define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) | ||
| 118 | #define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1) | ||
| 119 | #define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */ | ||
| 120 | #define AT91_MATRIX_EBI_CS3A_SMC (0 << 3) | ||
| 121 | #define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3) | ||
| 122 | #define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */ | ||
| 123 | #define AT91_MATRIX_EBI_CS4A_SMC (0 << 4) | ||
| 124 | #define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4) | ||
| 125 | #define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */ | ||
| 126 | #define AT91_MATRIX_EBI_CS5A_SMC (0 << 5) | ||
| 127 | #define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5) | ||
| 128 | #define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ | ||
| 129 | #define AT91_MATRIX_EBI_DBPU_ON (0 << 8) | ||
| 130 | #define AT91_MATRIX_EBI_DBPU_OFF (1 << 8) | ||
| 131 | #define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */ | ||
| 132 | #define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16) | ||
| 133 | #define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16) | ||
| 134 | #define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */ | ||
| 135 | #define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17) | ||
| 136 | #define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17) | ||
| 137 | #define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */ | ||
| 138 | #define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18) | ||
| 139 | #define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18) | ||
| 140 | |||
| 141 | #define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */ | ||
| 142 | #define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */ | ||
| 143 | #define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0) | ||
| 144 | #define AT91_MATRIX_WPMR_WP_WPEN (1 << 0) | ||
| 145 | #define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */ | ||
| 146 | |||
| 147 | #define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */ | ||
| 148 | #define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */ | ||
| 149 | #define AT91_MATRIX_WPSR_NO_WPV (0 << 0) | ||
| 150 | #define AT91_MATRIX_WPSR_WPV (1 << 0) | ||
| 151 | #define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */ | ||
| 152 | |||
| 153 | #endif | ||
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index e6afff849b85..13f27a4b882d 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
| @@ -37,6 +37,7 @@ | |||
| 37 | #include <linux/leds.h> | 37 | #include <linux/leds.h> |
| 38 | #include <linux/spi/spi.h> | 38 | #include <linux/spi/spi.h> |
| 39 | #include <linux/usb/atmel_usba_udc.h> | 39 | #include <linux/usb/atmel_usba_udc.h> |
| 40 | #include <sound/atmel-ac97c.h> | ||
| 40 | 41 | ||
| 41 | /* USB Device */ | 42 | /* USB Device */ |
| 42 | struct at91_udc_data { | 43 | struct at91_udc_data { |
| @@ -80,7 +81,8 @@ struct at91_eth_data { | |||
| 80 | }; | 81 | }; |
| 81 | extern void __init at91_add_device_eth(struct at91_eth_data *data); | 82 | extern void __init at91_add_device_eth(struct at91_eth_data *data); |
| 82 | 83 | ||
| 83 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) | 84 | #if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \ |
| 85 | || defined(CONFIG_ARCH_AT91SAM9G45) | ||
| 84 | #define eth_platform_data at91_eth_data | 86 | #define eth_platform_data at91_eth_data |
| 85 | #endif | 87 | #endif |
| 86 | 88 | ||
| @@ -90,6 +92,7 @@ struct at91_usbh_data { | |||
| 90 | u8 vbus_pin[2]; /* port power-control pin */ | 92 | u8 vbus_pin[2]; /* port power-control pin */ |
| 91 | }; | 93 | }; |
| 92 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); | 94 | extern void __init at91_add_device_usbh(struct at91_usbh_data *data); |
| 95 | extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data); | ||
| 93 | 96 | ||
| 94 | /* NAND / SmartMedia */ | 97 | /* NAND / SmartMedia */ |
| 95 | struct atmel_nand_data { | 98 | struct atmel_nand_data { |
| @@ -105,7 +108,11 @@ struct atmel_nand_data { | |||
| 105 | extern void __init at91_add_device_nand(struct atmel_nand_data *data); | 108 | extern void __init at91_add_device_nand(struct atmel_nand_data *data); |
| 106 | 109 | ||
| 107 | /* I2C*/ | 110 | /* I2C*/ |
| 111 | #if defined(CONFIG_ARCH_AT91SAM9G45) | ||
| 112 | extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices); | ||
| 113 | #else | ||
| 108 | extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); | 114 | extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices); |
| 115 | #endif | ||
| 109 | 116 | ||
| 110 | /* SPI */ | 117 | /* SPI */ |
| 111 | extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); | 118 | extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); |
| @@ -168,10 +175,7 @@ struct atmel_lcdfb_info; | |||
| 168 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); | 175 | extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); |
| 169 | 176 | ||
| 170 | /* AC97 */ | 177 | /* AC97 */ |
| 171 | struct atmel_ac97_data { | 178 | extern void __init at91_add_device_ac97(struct ac97c_platform_data *data); |
| 172 | u8 reset_pin; /* reset */ | ||
| 173 | }; | ||
| 174 | extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); | ||
| 175 | 179 | ||
| 176 | /* ISI */ | 180 | /* ISI */ |
| 177 | extern void __init at91_add_device_isi(void); | 181 | extern void __init at91_add_device_isi(void); |
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h index c554c3e4d553..34a9502c48bc 100644 --- a/arch/arm/mach-at91/include/mach/cpu.h +++ b/arch/arm/mach-at91/include/mach/cpu.h | |||
| @@ -21,8 +21,10 @@ | |||
| 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 | 21 | #define ARCH_ID_AT91SAM9260 0x019803a0 |
| 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 | 22 | #define ARCH_ID_AT91SAM9261 0x019703a0 |
| 23 | #define ARCH_ID_AT91SAM9263 0x019607a0 | 23 | #define ARCH_ID_AT91SAM9263 0x019607a0 |
| 24 | #define ARCH_ID_AT91SAM9G10 0x819903a0 | ||
| 24 | #define ARCH_ID_AT91SAM9G20 0x019905a0 | 25 | #define ARCH_ID_AT91SAM9G20 0x019905a0 |
| 25 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 | 26 | #define ARCH_ID_AT91SAM9RL64 0x019b03a0 |
| 27 | #define ARCH_ID_AT91SAM9G45 0x819b05a0 | ||
| 26 | #define ARCH_ID_AT91CAP9 0x039A03A0 | 28 | #define ARCH_ID_AT91CAP9 0x039A03A0 |
| 27 | 29 | ||
| 28 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 | 30 | #define ARCH_ID_AT91SAM9XE128 0x329973a0 |
| @@ -39,6 +41,15 @@ static inline unsigned long at91_cpu_identify(void) | |||
| 39 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); | 41 | return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); |
| 40 | } | 42 | } |
| 41 | 43 | ||
| 44 | #define ARCH_EXID_AT91SAM9M11 0x00000001 | ||
| 45 | #define ARCH_EXID_AT91SAM9M10 0x00000002 | ||
| 46 | #define ARCH_EXID_AT91SAM9G45 0x00000004 | ||
| 47 | |||
| 48 | static inline unsigned long at91_exid_identify(void) | ||
| 49 | { | ||
| 50 | return at91_sys_read(AT91_DBGU_EXID); | ||
| 51 | } | ||
| 52 | |||
| 42 | 53 | ||
| 43 | #define ARCH_FAMILY_AT91X92 0x09200000 | 54 | #define ARCH_FAMILY_AT91X92 0x09200000 |
| 44 | #define ARCH_FAMILY_AT91SAM9 0x01900000 | 55 | #define ARCH_FAMILY_AT91SAM9 0x01900000 |
| @@ -87,6 +98,12 @@ static inline unsigned long at91cap9_rev_identify(void) | |||
| 87 | #define cpu_is_at91sam9261() (0) | 98 | #define cpu_is_at91sam9261() (0) |
| 88 | #endif | 99 | #endif |
| 89 | 100 | ||
| 101 | #ifdef CONFIG_ARCH_AT91SAM9G10 | ||
| 102 | #define cpu_is_at91sam9g10() (at91_cpu_identify() == ARCH_ID_AT91SAM9G10) | ||
| 103 | #else | ||
| 104 | #define cpu_is_at91sam9g10() (0) | ||
| 105 | #endif | ||
| 106 | |||
| 90 | #ifdef CONFIG_ARCH_AT91SAM9263 | 107 | #ifdef CONFIG_ARCH_AT91SAM9263 |
| 91 | #define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) | 108 | #define cpu_is_at91sam9263() (at91_cpu_identify() == ARCH_ID_AT91SAM9263) |
| 92 | #else | 109 | #else |
| @@ -99,6 +116,12 @@ static inline unsigned long at91cap9_rev_identify(void) | |||
| 99 | #define cpu_is_at91sam9rl() (0) | 116 | #define cpu_is_at91sam9rl() (0) |
| 100 | #endif | 117 | #endif |
| 101 | 118 | ||
| 119 | #ifdef CONFIG_ARCH_AT91SAM9G45 | ||
| 120 | #define cpu_is_at91sam9g45() (at91_cpu_identify() == ARCH_ID_AT91SAM9G45) | ||
| 121 | #else | ||
| 122 | #define cpu_is_at91sam9g45() (0) | ||
| 123 | #endif | ||
| 124 | |||
| 102 | #ifdef CONFIG_ARCH_AT91CAP9 | 125 | #ifdef CONFIG_ARCH_AT91CAP9 |
| 103 | #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) | 126 | #define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9) |
| 104 | #define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) | 127 | #define cpu_is_at91cap9_revB() (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B) |
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h index da0b681c652c..a0df8b022df2 100644 --- a/arch/arm/mach-at91/include/mach/hardware.h +++ b/arch/arm/mach-at91/include/mach/hardware.h | |||
| @@ -20,12 +20,14 @@ | |||
| 20 | #include <mach/at91rm9200.h> | 20 | #include <mach/at91rm9200.h> |
| 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) | 21 | #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20) |
| 22 | #include <mach/at91sam9260.h> | 22 | #include <mach/at91sam9260.h> |
| 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) | 23 | #elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10) |
| 24 | #include <mach/at91sam9261.h> | 24 | #include <mach/at91sam9261.h> |
| 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) | 25 | #elif defined(CONFIG_ARCH_AT91SAM9263) |
| 26 | #include <mach/at91sam9263.h> | 26 | #include <mach/at91sam9263.h> |
| 27 | #elif defined(CONFIG_ARCH_AT91SAM9RL) | 27 | #elif defined(CONFIG_ARCH_AT91SAM9RL) |
| 28 | #include <mach/at91sam9rl.h> | 28 | #include <mach/at91sam9rl.h> |
| 29 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
| 30 | #include <mach/at91sam9g45.h> | ||
| 29 | #elif defined(CONFIG_ARCH_AT91CAP9) | 31 | #elif defined(CONFIG_ARCH_AT91CAP9) |
| 30 | #include <mach/at91cap9.h> | 32 | #include <mach/at91cap9.h> |
| 31 | #elif defined(CONFIG_ARCH_AT91X40) | 33 | #elif defined(CONFIG_ARCH_AT91X40) |
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h index d84c9948becf..31ac2d97f14c 100644 --- a/arch/arm/mach-at91/include/mach/timex.h +++ b/arch/arm/mach-at91/include/mach/timex.h | |||
| @@ -42,6 +42,11 @@ | |||
| 42 | #define AT91SAM9_MASTER_CLOCK 99300000 | 42 | #define AT91SAM9_MASTER_CLOCK 99300000 |
| 43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | 43 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) |
| 44 | 44 | ||
| 45 | #elif defined(CONFIG_ARCH_AT91SAM9G10) | ||
| 46 | |||
| 47 | #define AT91SAM9_MASTER_CLOCK 133000000 | ||
| 48 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 49 | |||
| 45 | #elif defined(CONFIG_ARCH_AT91SAM9263) | 50 | #elif defined(CONFIG_ARCH_AT91SAM9263) |
| 46 | 51 | ||
| 47 | #if defined(CONFIG_MACH_USB_A9263) | 52 | #if defined(CONFIG_MACH_USB_A9263) |
| @@ -62,6 +67,11 @@ | |||
| 62 | #define AT91SAM9_MASTER_CLOCK 132096000 | 67 | #define AT91SAM9_MASTER_CLOCK 132096000 |
| 63 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | 68 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) |
| 64 | 69 | ||
| 70 | #elif defined(CONFIG_ARCH_AT91SAM9G45) | ||
| 71 | |||
| 72 | #define AT91SAM9_MASTER_CLOCK 133333333 | ||
| 73 | #define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) | ||
| 74 | |||
| 65 | #elif defined(CONFIG_ARCH_AT91CAP9) | 75 | #elif defined(CONFIG_ARCH_AT91CAP9) |
| 66 | 76 | ||
| 67 | #define AT91CAP9_MASTER_CLOCK 100000000 | 77 | #define AT91CAP9_MASTER_CLOCK 100000000 |
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index e26c4fe61fae..4028724d490d 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c | |||
| @@ -201,7 +201,8 @@ static int at91_pm_verify_clocks(void) | |||
| 201 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); | 201 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
| 202 | return 0; | 202 | return 0; |
| 203 | } | 203 | } |
| 204 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) { | 204 | } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() |
| 205 | || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) { | ||
| 205 | if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { | 206 | if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { |
| 206 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); | 207 | pr_err("AT91: PM - Suspend-to-RAM with USB still active\n"); |
| 207 | return 0; | 208 | return 0; |
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig new file mode 100644 index 000000000000..457b4384913e --- /dev/null +++ b/arch/arm/mach-bcmring/Kconfig | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | choice | ||
| 2 | prompt "Processor selection in BCMRING family of devices" | ||
| 3 | depends on ARCH_BCMRING | ||
| 4 | default ARCH_BCM11107 | ||
| 5 | |||
| 6 | config ARCH_FPGA11107 | ||
| 7 | bool "FPGA11107" | ||
| 8 | |||
| 9 | config ARCH_BCM11107 | ||
| 10 | bool "BCM11107" | ||
| 11 | endchoice | ||
| 12 | |||
| 13 | menu "BCMRING Options" | ||
| 14 | depends on ARCH_BCMRING | ||
| 15 | |||
| 16 | config BCM_ZRELADDR | ||
| 17 | hex "Compressed ZREL ADDR" | ||
| 18 | |||
| 19 | endmenu | ||
| 20 | |||
| 21 | # source "drivers/char/bcmring/Kconfig" | ||
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile new file mode 100644 index 000000000000..f8d9fcedf917 --- /dev/null +++ b/arch/arm/mach-bcmring/Makefile | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | # | ||
| 2 | # Makefile for the linux kernel. | ||
| 3 | # | ||
| 4 | |||
| 5 | # Object file lists. | ||
| 6 | |||
| 7 | obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o | ||
| 8 | obj-y += csp/ | ||
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot new file mode 100644 index 000000000000..fb53b283bebb --- /dev/null +++ b/arch/arm/mach-bcmring/Makefile.boot | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | # Address where decompressor will be written and eventually executed. | ||
| 2 | # | ||
| 3 | # default to SDRAM | ||
| 4 | zreladdr-y := $(CONFIG_BCM_ZRELADDR) | ||
| 5 | params_phys-y := 0x00000800 | ||
| 6 | |||
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c new file mode 100644 index 000000000000..0da693b0f7e1 --- /dev/null +++ b/arch/arm/mach-bcmring/arch.c | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/sched.h> | ||
| 19 | #include <linux/interrupt.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/spinlock.h> | ||
| 23 | #include <linux/module.h> | ||
| 24 | |||
| 25 | #include <linux/proc_fs.h> | ||
| 26 | #include <linux/sysctl.h> | ||
| 27 | |||
| 28 | #include <asm/irq.h> | ||
| 29 | #include <asm/setup.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/time.h> | ||
| 32 | |||
| 33 | #include <asm/mach/arch.h> | ||
| 34 | #include <mach/dma.h> | ||
| 35 | #include <mach/hardware.h> | ||
| 36 | #include <mach/csp/mm_io.h> | ||
| 37 | #include <mach/csp/chipcHw_def.h> | ||
| 38 | #include <mach/csp/chipcHw_inline.h> | ||
| 39 | |||
| 40 | #include <cfg_global.h> | ||
| 41 | |||
| 42 | #include "core.h" | ||
| 43 | |||
| 44 | HW_DECLARE_SPINLOCK(arch) | ||
| 45 | HW_DECLARE_SPINLOCK(gpio) | ||
| 46 | #if defined(CONFIG_DEBUG_SPINLOCK) | ||
| 47 | EXPORT_SYMBOL(bcmring_gpio_reg_lock); | ||
| 48 | #endif | ||
| 49 | |||
| 50 | /* FIXME: temporary solution */ | ||
| 51 | #define BCM_SYSCTL_REBOOT_WARM 1 | ||
| 52 | #define CTL_BCM_REBOOT 112 | ||
| 53 | |||
| 54 | /* sysctl */ | ||
| 55 | int bcmring_arch_warm_reboot; /* do a warm reboot on hard reset */ | ||
| 56 | |||
| 57 | static struct ctl_table_header *bcmring_sysctl_header; | ||
| 58 | |||
| 59 | static struct ctl_table bcmring_sysctl_warm_reboot[] = { | ||
| 60 | { | ||
| 61 | .ctl_name = BCM_SYSCTL_REBOOT_WARM, | ||
| 62 | .procname = "warm", | ||
| 63 | .data = &bcmring_arch_warm_reboot, | ||
| 64 | .maxlen = sizeof(int), | ||
| 65 | .mode = 0644, | ||
| 66 | .proc_handler = &proc_dointvec}, | ||
| 67 | {} | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct ctl_table bcmring_sysctl_reboot[] = { | ||
| 71 | { | ||
| 72 | .ctl_name = CTL_BCM_REBOOT, | ||
| 73 | .procname = "reboot", | ||
| 74 | .mode = 0555, | ||
| 75 | .child = bcmring_sysctl_warm_reboot}, | ||
| 76 | {} | ||
| 77 | }; | ||
| 78 | |||
| 79 | static struct platform_device nand_device = { | ||
| 80 | .name = "bcm-nand", | ||
| 81 | .id = -1, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct platform_device *devices[] __initdata = { | ||
| 85 | &nand_device, | ||
| 86 | }; | ||
| 87 | |||
| 88 | /**************************************************************************** | ||
| 89 | * | ||
| 90 | * Called from the customize_machine function in arch/arm/kernel/setup.c | ||
| 91 | * | ||
| 92 | * The customize_machine function is tagged as an arch_initcall | ||
| 93 | * (see include/linux/init.h for the order that the various init sections | ||
| 94 | * are called in. | ||
| 95 | * | ||
| 96 | *****************************************************************************/ | ||
| 97 | static void __init bcmring_init_machine(void) | ||
| 98 | { | ||
| 99 | |||
| 100 | bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot); | ||
| 101 | |||
| 102 | /* Enable spread spectrum */ | ||
| 103 | chipcHw_enableSpreadSpectrum(); | ||
| 104 | |||
| 105 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 106 | |||
| 107 | bcmring_amba_init(); | ||
| 108 | |||
| 109 | dma_init(); | ||
| 110 | } | ||
| 111 | |||
| 112 | /**************************************************************************** | ||
| 113 | * | ||
| 114 | * Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags | ||
| 115 | * passed in by the boot loader. | ||
| 116 | * | ||
| 117 | *****************************************************************************/ | ||
| 118 | |||
| 119 | static void __init bcmring_fixup(struct machine_desc *desc, | ||
| 120 | struct tag *t, char **cmdline, struct meminfo *mi) { | ||
| 121 | #ifdef CONFIG_BLK_DEV_INITRD | ||
| 122 | printk(KERN_NOTICE "bcmring_fixup\n"); | ||
| 123 | t->hdr.tag = ATAG_CORE; | ||
| 124 | t->hdr.size = tag_size(tag_core); | ||
| 125 | t->u.core.flags = 0; | ||
| 126 | t->u.core.pagesize = PAGE_SIZE; | ||
| 127 | t->u.core.rootdev = 31 << 8 | 0; | ||
| 128 | t = tag_next(t); | ||
| 129 | |||
| 130 | t->hdr.tag = ATAG_MEM; | ||
| 131 | t->hdr.size = tag_size(tag_mem32); | ||
| 132 | t->u.mem.start = CFG_GLOBAL_RAM_BASE; | ||
| 133 | t->u.mem.size = CFG_GLOBAL_RAM_SIZE; | ||
| 134 | |||
| 135 | t = tag_next(t); | ||
| 136 | |||
| 137 | t->hdr.tag = ATAG_NONE; | ||
| 138 | t->hdr.size = 0; | ||
| 139 | #endif | ||
| 140 | } | ||
| 141 | |||
| 142 | /**************************************************************************** | ||
| 143 | * | ||
| 144 | * Machine Description | ||
| 145 | * | ||
| 146 | *****************************************************************************/ | ||
| 147 | |||
| 148 | MACHINE_START(BCMRING, "BCMRING") | ||
| 149 | /* Maintainer: Broadcom Corporation */ | ||
| 150 | .phys_io = MM_IO_START, | ||
| 151 | .io_pg_offst = (MM_IO_BASE >> 18) & 0xfffc, | ||
| 152 | .fixup = bcmring_fixup, | ||
| 153 | .map_io = bcmring_map_io, | ||
| 154 | .init_irq = bcmring_init_irq, | ||
| 155 | .timer = &bcmring_timer, | ||
| 156 | .init_machine = bcmring_init_machine | ||
| 157 | MACHINE_END | ||
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c new file mode 100644 index 000000000000..14bafc38f2dc --- /dev/null +++ b/arch/arm/mach-bcmring/clock.c | |||
| @@ -0,0 +1,224 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/device.h> | ||
| 18 | #include <linux/list.h> | ||
| 19 | #include <linux/errno.h> | ||
| 20 | #include <linux/err.h> | ||
| 21 | #include <linux/string.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/spinlock.h> | ||
| 24 | #include <mach/csp/hw_cfg.h> | ||
| 25 | #include <mach/csp/chipcHw_def.h> | ||
| 26 | #include <mach/csp/chipcHw_reg.h> | ||
| 27 | #include <mach/csp/chipcHw_inline.h> | ||
| 28 | |||
| 29 | #include <asm/clkdev.h> | ||
| 30 | |||
| 31 | #include "clock.h" | ||
| 32 | |||
| 33 | #define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY) | ||
| 34 | #define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1) | ||
| 35 | #define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2) | ||
| 36 | #define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE) | ||
| 37 | #define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE) | ||
| 38 | |||
| 39 | #define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL) | ||
| 40 | |||
| 41 | static DEFINE_SPINLOCK(clk_lock); | ||
| 42 | |||
| 43 | static void __clk_enable(struct clk *clk) | ||
| 44 | { | ||
| 45 | if (!clk) | ||
| 46 | return; | ||
| 47 | |||
| 48 | /* enable parent clock first */ | ||
| 49 | if (clk->parent) | ||
| 50 | __clk_enable(clk->parent); | ||
| 51 | |||
| 52 | if (clk->use_cnt++ == 0) { | ||
| 53 | if (clk_is_pll1(clk)) { /* PLL1 */ | ||
| 54 | chipcHw_pll1Enable(clk->rate_hz, 0); | ||
| 55 | } else if (clk_is_pll2(clk)) { /* PLL2 */ | ||
| 56 | chipcHw_pll2Enable(clk->rate_hz); | ||
| 57 | } else if (clk_is_using_xtal(clk)) { /* source is crystal */ | ||
| 58 | if (!clk_is_primary(clk)) | ||
| 59 | chipcHw_bypassClockEnable(clk->csp_id); | ||
| 60 | } else { /* source is PLL */ | ||
| 61 | chipcHw_setClockEnable(clk->csp_id); | ||
| 62 | } | ||
| 63 | } | ||
| 64 | } | ||
| 65 | |||
| 66 | int clk_enable(struct clk *clk) | ||
| 67 | { | ||
| 68 | unsigned long flags; | ||
| 69 | |||
| 70 | if (!clk) | ||
| 71 | return -EINVAL; | ||
| 72 | |||
| 73 | spin_lock_irqsave(&clk_lock, flags); | ||
| 74 | __clk_enable(clk); | ||
| 75 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | EXPORT_SYMBOL(clk_enable); | ||
| 80 | |||
| 81 | static void __clk_disable(struct clk *clk) | ||
| 82 | { | ||
| 83 | if (!clk) | ||
| 84 | return; | ||
| 85 | |||
| 86 | BUG_ON(clk->use_cnt == 0); | ||
| 87 | |||
| 88 | if (--clk->use_cnt == 0) { | ||
| 89 | if (clk_is_pll1(clk)) { /* PLL1 */ | ||
| 90 | chipcHw_pll1Disable(); | ||
| 91 | } else if (clk_is_pll2(clk)) { /* PLL2 */ | ||
| 92 | chipcHw_pll2Disable(); | ||
| 93 | } else if (clk_is_using_xtal(clk)) { /* source is crystal */ | ||
| 94 | if (!clk_is_primary(clk)) | ||
| 95 | chipcHw_bypassClockDisable(clk->csp_id); | ||
| 96 | } else { /* source is PLL */ | ||
| 97 | chipcHw_setClockDisable(clk->csp_id); | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 101 | if (clk->parent) | ||
| 102 | __clk_disable(clk->parent); | ||
| 103 | } | ||
| 104 | |||
| 105 | void clk_disable(struct clk *clk) | ||
| 106 | { | ||
| 107 | unsigned long flags; | ||
| 108 | |||
| 109 | if (!clk) | ||
| 110 | return; | ||
| 111 | |||
| 112 | spin_lock_irqsave(&clk_lock, flags); | ||
| 113 | __clk_disable(clk); | ||
| 114 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 115 | } | ||
| 116 | EXPORT_SYMBOL(clk_disable); | ||
| 117 | |||
| 118 | unsigned long clk_get_rate(struct clk *clk) | ||
| 119 | { | ||
| 120 | if (!clk) | ||
| 121 | return 0; | ||
| 122 | |||
| 123 | return clk->rate_hz; | ||
| 124 | } | ||
| 125 | EXPORT_SYMBOL(clk_get_rate); | ||
| 126 | |||
| 127 | long clk_round_rate(struct clk *clk, unsigned long rate) | ||
| 128 | { | ||
| 129 | unsigned long flags; | ||
| 130 | unsigned long actual; | ||
| 131 | unsigned long rate_hz; | ||
| 132 | |||
| 133 | if (!clk) | ||
| 134 | return -EINVAL; | ||
| 135 | |||
| 136 | if (!clk_is_programmable(clk)) | ||
| 137 | return -EINVAL; | ||
| 138 | |||
| 139 | if (clk->use_cnt) | ||
| 140 | return -EBUSY; | ||
| 141 | |||
| 142 | spin_lock_irqsave(&clk_lock, flags); | ||
| 143 | actual = clk->parent->rate_hz; | ||
| 144 | rate_hz = min(actual, rate); | ||
| 145 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 146 | |||
| 147 | return rate_hz; | ||
| 148 | } | ||
| 149 | EXPORT_SYMBOL(clk_round_rate); | ||
| 150 | |||
| 151 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 152 | { | ||
| 153 | unsigned long flags; | ||
| 154 | unsigned long actual; | ||
| 155 | unsigned long rate_hz; | ||
| 156 | |||
| 157 | if (!clk) | ||
| 158 | return -EINVAL; | ||
| 159 | |||
| 160 | if (!clk_is_programmable(clk)) | ||
| 161 | return -EINVAL; | ||
| 162 | |||
| 163 | if (clk->use_cnt) | ||
| 164 | return -EBUSY; | ||
| 165 | |||
| 166 | spin_lock_irqsave(&clk_lock, flags); | ||
| 167 | actual = clk->parent->rate_hz; | ||
| 168 | rate_hz = min(actual, rate); | ||
| 169 | rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz); | ||
| 170 | clk->rate_hz = rate_hz; | ||
| 171 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 172 | |||
| 173 | return 0; | ||
| 174 | } | ||
| 175 | EXPORT_SYMBOL(clk_set_rate); | ||
| 176 | |||
| 177 | struct clk *clk_get_parent(struct clk *clk) | ||
| 178 | { | ||
| 179 | if (!clk) | ||
| 180 | return NULL; | ||
| 181 | |||
| 182 | return clk->parent; | ||
| 183 | } | ||
| 184 | EXPORT_SYMBOL(clk_get_parent); | ||
| 185 | |||
| 186 | int clk_set_parent(struct clk *clk, struct clk *parent) | ||
| 187 | { | ||
| 188 | unsigned long flags; | ||
| 189 | struct clk *old_parent; | ||
| 190 | |||
| 191 | if (!clk || !parent) | ||
| 192 | return -EINVAL; | ||
| 193 | |||
| 194 | if (!clk_is_primary(parent) || !clk_is_bypassable(clk)) | ||
| 195 | return -EINVAL; | ||
| 196 | |||
| 197 | /* if more than one user, parent is not allowed */ | ||
| 198 | if (clk->use_cnt > 1) | ||
| 199 | return -EBUSY; | ||
| 200 | |||
| 201 | if (clk->parent == parent) | ||
| 202 | return 0; | ||
| 203 | |||
| 204 | spin_lock_irqsave(&clk_lock, flags); | ||
| 205 | old_parent = clk->parent; | ||
| 206 | clk->parent = parent; | ||
| 207 | if (clk_is_using_xtal(parent)) | ||
| 208 | clk->mode |= CLK_MODE_XTAL; | ||
| 209 | else | ||
| 210 | clk->mode &= (~CLK_MODE_XTAL); | ||
| 211 | |||
| 212 | /* if clock is active */ | ||
| 213 | if (clk->use_cnt != 0) { | ||
| 214 | clk->use_cnt--; | ||
| 215 | /* enable clock with the new parent */ | ||
| 216 | __clk_enable(clk); | ||
| 217 | /* disable the old parent */ | ||
| 218 | __clk_disable(old_parent); | ||
| 219 | } | ||
| 220 | spin_unlock_irqrestore(&clk_lock, flags); | ||
| 221 | |||
| 222 | return 0; | ||
| 223 | } | ||
| 224 | EXPORT_SYMBOL(clk_set_parent); | ||
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h new file mode 100644 index 000000000000..5e0b98138973 --- /dev/null +++ b/arch/arm/mach-bcmring/clock.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2001 - 2009 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | #include <mach/csp/chipcHw_def.h> | ||
| 15 | |||
| 16 | #define CLK_TYPE_PRIMARY 1 /* primary clock must NOT have a parent */ | ||
| 17 | #define CLK_TYPE_PLL1 2 /* PPL1 */ | ||
| 18 | #define CLK_TYPE_PLL2 4 /* PPL2 */ | ||
| 19 | #define CLK_TYPE_PROGRAMMABLE 8 /* programmable clock rate */ | ||
| 20 | #define CLK_TYPE_BYPASSABLE 16 /* parent can be changed */ | ||
| 21 | |||
| 22 | #define CLK_MODE_XTAL 1 /* clock source is from crystal */ | ||
| 23 | |||
| 24 | struct clk { | ||
| 25 | const char *name; /* clock name */ | ||
| 26 | unsigned int type; /* clock type */ | ||
| 27 | unsigned int mode; /* current mode */ | ||
| 28 | volatile int use_bypass; /* indicate if it's in bypass mode */ | ||
| 29 | chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */ | ||
| 30 | unsigned long rate_hz; /* clock rate in Hz */ | ||
| 31 | unsigned int use_cnt; /* usage count */ | ||
| 32 | struct clk *parent; /* parent clock */ | ||
| 33 | }; | ||
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c new file mode 100644 index 000000000000..492c649f451e --- /dev/null +++ b/arch/arm/mach-bcmring/core.c | |||
| @@ -0,0 +1,367 @@ | |||
| 1 | /* | ||
| 2 | * derived from linux/arch/arm/mach-versatile/core.c | ||
| 3 | * linux/arch/arm/mach-bcmring/core.c | ||
| 4 | * | ||
| 5 | * Copyright (C) 1999 - 2003 ARM Limited | ||
| 6 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | /* Portions copyright Broadcom 2008 */ | ||
| 23 | |||
| 24 | #include <linux/init.h> | ||
| 25 | #include <linux/device.h> | ||
| 26 | #include <linux/dma-mapping.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/sysdev.h> | ||
| 29 | #include <linux/interrupt.h> | ||
| 30 | #include <linux/amba/bus.h> | ||
| 31 | #include <linux/clocksource.h> | ||
| 32 | #include <linux/clockchips.h> | ||
| 33 | |||
| 34 | #include <linux/amba/bus.h> | ||
| 35 | #include <mach/csp/mm_addr.h> | ||
| 36 | #include <mach/hardware.h> | ||
| 37 | #include <asm/clkdev.h> | ||
| 38 | #include <linux/io.h> | ||
| 39 | #include <asm/irq.h> | ||
| 40 | #include <asm/hardware/arm_timer.h> | ||
| 41 | #include <asm/mach-types.h> | ||
| 42 | |||
| 43 | #include <asm/mach/arch.h> | ||
| 44 | #include <asm/mach/flash.h> | ||
| 45 | #include <asm/mach/irq.h> | ||
| 46 | #include <asm/mach/time.h> | ||
| 47 | #include <asm/mach/map.h> | ||
| 48 | #include <asm/mach/mmc.h> | ||
| 49 | |||
| 50 | #include <cfg_global.h> | ||
| 51 | |||
| 52 | #include "clock.h" | ||
| 53 | |||
| 54 | #include <csp/secHw.h> | ||
| 55 | #include <mach/csp/secHw_def.h> | ||
| 56 | #include <mach/csp/chipcHw_inline.h> | ||
| 57 | #include <mach/csp/tmrHw_reg.h> | ||
| 58 | |||
| 59 | #define AMBA_DEVICE(name, initname, base, plat, size) \ | ||
| 60 | static struct amba_device name##_device = { \ | ||
| 61 | .dev = { \ | ||
| 62 | .coherent_dma_mask = ~0, \ | ||
| 63 | .init_name = initname, \ | ||
| 64 | .platform_data = plat \ | ||
| 65 | }, \ | ||
| 66 | .res = { \ | ||
| 67 | .start = MM_ADDR_IO_##base, \ | ||
| 68 | .end = MM_ADDR_IO_##base + (size) - 1, \ | ||
| 69 | .flags = IORESOURCE_MEM \ | ||
| 70 | }, \ | ||
| 71 | .dma_mask = ~0, \ | ||
| 72 | .irq = { \ | ||
| 73 | IRQ_##base \ | ||
| 74 | } \ | ||
| 75 | } | ||
| 76 | |||
| 77 | |||
| 78 | AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K); | ||
| 79 | AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K); | ||
| 80 | |||
| 81 | static struct clk pll1_clk = { | ||
| 82 | .name = "PLL1", | ||
| 83 | .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1, | ||
| 84 | .rate_hz = 2000000000, | ||
| 85 | .use_cnt = 7, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct clk uart_clk = { | ||
| 89 | .name = "UART", | ||
| 90 | .type = CLK_TYPE_PROGRAMMABLE, | ||
| 91 | .csp_id = chipcHw_CLOCK_UART, | ||
| 92 | .rate_hz = HW_CFG_UART_CLK_HZ, | ||
| 93 | .parent = &pll1_clk, | ||
| 94 | }; | ||
| 95 | |||
| 96 | static struct clk_lookup lookups[] = { | ||
| 97 | { /* UART0 */ | ||
| 98 | .dev_id = "uarta", | ||
| 99 | .clk = &uart_clk, | ||
| 100 | }, { /* UART1 */ | ||
| 101 | .dev_id = "uartb", | ||
| 102 | .clk = &uart_clk, | ||
| 103 | } | ||
| 104 | }; | ||
| 105 | |||
| 106 | static struct amba_device *amba_devs[] __initdata = { | ||
| 107 | &uartA_device, | ||
| 108 | &uartB_device, | ||
| 109 | }; | ||
| 110 | |||
| 111 | void __init bcmring_amba_init(void) | ||
| 112 | { | ||
| 113 | int i; | ||
| 114 | u32 bus_clock; | ||
| 115 | |||
| 116 | /* Linux is run initially in non-secure mode. Secure peripherals */ | ||
| 117 | /* generate FIQ, and must be handled in secure mode. Until we have */ | ||
| 118 | /* a linux security monitor implementation, keep everything in */ | ||
| 119 | /* non-secure mode. */ | ||
| 120 | chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU); | ||
| 121 | secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL | | ||
| 122 | secHw_BLK_MASK_KEY_SCAN | | ||
| 123 | secHw_BLK_MASK_TOUCH_SCREEN | | ||
| 124 | secHw_BLK_MASK_UART0 | | ||
| 125 | secHw_BLK_MASK_UART1 | | ||
| 126 | secHw_BLK_MASK_WATCHDOG | | ||
| 127 | secHw_BLK_MASK_SPUM | | ||
| 128 | secHw_BLK_MASK_DDR2 | | ||
| 129 | secHw_BLK_MASK_SPU | | ||
| 130 | secHw_BLK_MASK_PKA | | ||
| 131 | secHw_BLK_MASK_RNG | | ||
| 132 | secHw_BLK_MASK_RTC | | ||
| 133 | secHw_BLK_MASK_OTP | | ||
| 134 | secHw_BLK_MASK_BOOT | | ||
| 135 | secHw_BLK_MASK_MPU | | ||
| 136 | secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR); | ||
| 137 | |||
| 138 | /* Only the devices attached to the AMBA bus are enabled just before the bus is */ | ||
| 139 | /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */ | ||
| 140 | /* driver to access these blocks. The bus is probed, and the drivers are loaded. */ | ||
| 141 | /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */ | ||
| 142 | bus_clock = chipcHw_REG_BUS_CLOCK_GE | ||
| 143 | | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1; | ||
| 144 | |||
| 145 | chipcHw_busInterfaceClockEnable(bus_clock); | ||
| 146 | |||
| 147 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | ||
| 148 | clkdev_add(&lookups[i]); | ||
| 149 | |||
| 150 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
| 151 | struct amba_device *d = amba_devs[i]; | ||
| 152 | amba_device_register(d, &iomem_resource); | ||
| 153 | } | ||
| 154 | } | ||
| 155 | |||
| 156 | /* | ||
| 157 | * Where is the timer (VA)? | ||
| 158 | */ | ||
| 159 | #define TIMER0_VA_BASE MM_IO_BASE_TMR | ||
| 160 | #define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20) | ||
| 161 | #define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40) | ||
| 162 | #define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60) | ||
| 163 | |||
| 164 | /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */ | ||
| 165 | #if defined(CONFIG_ARCH_FPGA11107) | ||
| 166 | /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */ | ||
| 167 | /* slow down Linux's sense of time */ | ||
| 168 | #define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) | ||
| 169 | #define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30) | ||
| 170 | #define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30) | ||
| 171 | #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30) | ||
| 172 | #else | ||
| 173 | #define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ | ||
| 174 | #define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ | ||
| 175 | #define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ | ||
| 176 | #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000) | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ | ||
| 180 | |||
| 181 | /* | ||
| 182 | * These are useconds NOT ticks. | ||
| 183 | * | ||
| 184 | */ | ||
| 185 | #define mSEC_1 1000 | ||
| 186 | #define mSEC_5 (mSEC_1 * 5) | ||
| 187 | #define mSEC_10 (mSEC_1 * 10) | ||
| 188 | #define mSEC_25 (mSEC_1 * 25) | ||
| 189 | #define SEC_1 (mSEC_1 * 1000) | ||
| 190 | |||
| 191 | /* | ||
| 192 | * How long is the timer interval? | ||
| 193 | */ | ||
| 194 | #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10) | ||
| 195 | #if TIMER_INTERVAL >= 0x100000 | ||
| 196 | #define TIMER_RELOAD (TIMER_INTERVAL >> 8) | ||
| 197 | #define TIMER_DIVISOR (TIMER_CTRL_DIV256) | ||
| 198 | #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC) | ||
| 199 | #elif TIMER_INTERVAL >= 0x10000 | ||
| 200 | #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */ | ||
| 201 | #define TIMER_DIVISOR (TIMER_CTRL_DIV16) | ||
| 202 | #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC) | ||
| 203 | #else | ||
| 204 | #define TIMER_RELOAD (TIMER_INTERVAL) | ||
| 205 | #define TIMER_DIVISOR (TIMER_CTRL_DIV1) | ||
| 206 | #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC) | ||
| 207 | #endif | ||
| 208 | |||
| 209 | static void timer_set_mode(enum clock_event_mode mode, | ||
| 210 | struct clock_event_device *clk) | ||
| 211 | { | ||
| 212 | unsigned long ctrl; | ||
| 213 | |||
| 214 | switch (mode) { | ||
| 215 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 216 | writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD); | ||
| 217 | |||
| 218 | ctrl = TIMER_CTRL_PERIODIC; | ||
| 219 | ctrl |= | ||
| 220 | TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE | | ||
| 221 | TIMER_CTRL_ENABLE; | ||
| 222 | break; | ||
| 223 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 224 | /* period set, and timer enabled in 'next_event' hook */ | ||
| 225 | ctrl = TIMER_CTRL_ONESHOT; | ||
| 226 | ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE; | ||
| 227 | break; | ||
| 228 | case CLOCK_EVT_MODE_UNUSED: | ||
| 229 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 230 | default: | ||
| 231 | ctrl = 0; | ||
| 232 | } | ||
| 233 | |||
| 234 | writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL); | ||
| 235 | } | ||
| 236 | |||
| 237 | static int timer_set_next_event(unsigned long evt, | ||
| 238 | struct clock_event_device *unused) | ||
| 239 | { | ||
| 240 | unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL); | ||
| 241 | |||
| 242 | writel(evt, TIMER0_VA_BASE + TIMER_LOAD); | ||
| 243 | writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL); | ||
| 244 | |||
| 245 | return 0; | ||
| 246 | } | ||
| 247 | |||
| 248 | static struct clock_event_device timer0_clockevent = { | ||
| 249 | .name = "timer0", | ||
| 250 | .shift = 32, | ||
| 251 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 252 | .set_mode = timer_set_mode, | ||
| 253 | .set_next_event = timer_set_next_event, | ||
| 254 | }; | ||
| 255 | |||
| 256 | /* | ||
| 257 | * IRQ handler for the timer | ||
| 258 | */ | ||
| 259 | static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id) | ||
| 260 | { | ||
| 261 | struct clock_event_device *evt = &timer0_clockevent; | ||
| 262 | |||
| 263 | writel(1, TIMER0_VA_BASE + TIMER_INTCLR); | ||
| 264 | |||
| 265 | evt->event_handler(evt); | ||
| 266 | |||
| 267 | return IRQ_HANDLED; | ||
| 268 | } | ||
| 269 | |||
| 270 | static struct irqaction bcmring_timer_irq = { | ||
| 271 | .name = "bcmring Timer Tick", | ||
| 272 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 273 | .handler = bcmring_timer_interrupt, | ||
| 274 | }; | ||
| 275 | |||
| 276 | static cycle_t bcmring_get_cycles_timer1(void) | ||
| 277 | { | ||
| 278 | return ~readl(TIMER1_VA_BASE + TIMER_VALUE); | ||
| 279 | } | ||
| 280 | |||
| 281 | static cycle_t bcmring_get_cycles_timer3(void) | ||
| 282 | { | ||
| 283 | return ~readl(TIMER3_VA_BASE + TIMER_VALUE); | ||
| 284 | } | ||
| 285 | |||
| 286 | static struct clocksource clocksource_bcmring_timer1 = { | ||
| 287 | .name = "timer1", | ||
| 288 | .rating = 200, | ||
| 289 | .read = bcmring_get_cycles_timer1, | ||
| 290 | .mask = CLOCKSOURCE_MASK(32), | ||
| 291 | .shift = 20, | ||
| 292 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static struct clocksource clocksource_bcmring_timer3 = { | ||
| 296 | .name = "timer3", | ||
| 297 | .rating = 100, | ||
| 298 | .read = bcmring_get_cycles_timer3, | ||
| 299 | .mask = CLOCKSOURCE_MASK(32), | ||
| 300 | .shift = 20, | ||
| 301 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 302 | }; | ||
| 303 | |||
| 304 | static int __init bcmring_clocksource_init(void) | ||
| 305 | { | ||
| 306 | /* setup timer1 as free-running clocksource */ | ||
| 307 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
| 308 | writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD); | ||
| 309 | writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE); | ||
| 310 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | ||
| 311 | TIMER1_VA_BASE + TIMER_CTRL); | ||
| 312 | |||
| 313 | clocksource_bcmring_timer1.mult = | ||
| 314 | clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000, | ||
| 315 | clocksource_bcmring_timer1.shift); | ||
| 316 | clocksource_register(&clocksource_bcmring_timer1); | ||
| 317 | |||
| 318 | /* setup timer3 as free-running clocksource */ | ||
| 319 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | ||
| 320 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD); | ||
| 321 | writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE); | ||
| 322 | writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, | ||
| 323 | TIMER3_VA_BASE + TIMER_CTRL); | ||
| 324 | |||
| 325 | clocksource_bcmring_timer3.mult = | ||
| 326 | clocksource_khz2mult(TIMER3_FREQUENCY_KHZ, | ||
| 327 | clocksource_bcmring_timer3.shift); | ||
| 328 | clocksource_register(&clocksource_bcmring_timer3); | ||
| 329 | |||
| 330 | return 0; | ||
| 331 | } | ||
| 332 | |||
| 333 | /* | ||
| 334 | * Set up timer interrupt, and return the current time in seconds. | ||
| 335 | */ | ||
| 336 | void __init bcmring_init_timer(void) | ||
| 337 | { | ||
| 338 | printk(KERN_INFO "bcmring_init_timer\n"); | ||
| 339 | /* | ||
| 340 | * Initialise to a known state (all timers off) | ||
| 341 | */ | ||
| 342 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
| 343 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
| 344 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
| 345 | writel(0, TIMER3_VA_BASE + TIMER_CTRL); | ||
| 346 | |||
| 347 | /* | ||
| 348 | * Make irqs happen for the system timer | ||
| 349 | */ | ||
| 350 | setup_irq(IRQ_TIMER0, &bcmring_timer_irq); | ||
| 351 | |||
| 352 | bcmring_clocksource_init(); | ||
| 353 | |||
| 354 | timer0_clockevent.mult = | ||
| 355 | div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); | ||
| 356 | timer0_clockevent.max_delta_ns = | ||
| 357 | clockevent_delta2ns(0xffffffff, &timer0_clockevent); | ||
| 358 | timer0_clockevent.min_delta_ns = | ||
| 359 | clockevent_delta2ns(0xf, &timer0_clockevent); | ||
| 360 | |||
| 361 | timer0_clockevent.cpumask = cpumask_of(0); | ||
| 362 | clockevents_register_device(&timer0_clockevent); | ||
| 363 | } | ||
| 364 | |||
| 365 | struct sys_timer bcmring_timer = { | ||
| 366 | .init = bcmring_init_timer, | ||
| 367 | }; | ||
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h new file mode 100644 index 000000000000..b197ba48e36e --- /dev/null +++ b/arch/arm/mach-bcmring/core.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-versatile/core.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2004 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | /* Portions copyright Broadcom 2008 */ | ||
| 22 | #ifndef __ASM_ARCH_BCMRING_H | ||
| 23 | #define __ASM_ARCH_BCMRING_H | ||
| 24 | |||
| 25 | void __init bcmring_amba_init(void); | ||
| 26 | void __init bcmring_map_io(void); | ||
| 27 | void __init bcmring_init_irq(void); | ||
| 28 | |||
| 29 | extern struct sys_timer bcmring_timer; | ||
| 30 | #endif | ||
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile new file mode 100644 index 000000000000..648c0377530e --- /dev/null +++ b/arch/arm/mach-bcmring/csp/Makefile | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | obj-y += dmac/ | ||
| 2 | obj-y += tmr/ | ||
| 3 | obj-y += chipc/ | ||
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile new file mode 100644 index 000000000000..673952768ee5 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/chipc/Makefile | |||
| @@ -0,0 +1 @@ | |||
| obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o | |||
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c new file mode 100644 index 000000000000..b3a61d860c65 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c | |||
| @@ -0,0 +1,776 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file chipcHw.c | ||
| 18 | * | ||
| 19 | * @brief Low level Various CHIP clock controlling routines | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * | ||
| 23 | * These routines provide basic clock controlling functionality only. | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 28 | |||
| 29 | #include <csp/errno.h> | ||
| 30 | #include <csp/stdint.h> | ||
| 31 | #include <csp/module.h> | ||
| 32 | |||
| 33 | #include <mach/csp/chipcHw_def.h> | ||
| 34 | #include <mach/csp/chipcHw_inline.h> | ||
| 35 | |||
| 36 | #include <csp/reg.h> | ||
| 37 | #include <csp/delay.h> | ||
| 38 | |||
| 39 | /* ---- Private Constants and Types --------------------------------------- */ | ||
| 40 | |||
| 41 | /* VPM alignment algorithm uses this */ | ||
| 42 | #define MAX_PHASE_ADJUST_COUNT 0xFFFF /* Max number of times allowed to adjust the phase */ | ||
| 43 | #define MAX_PHASE_ALIGN_ATTEMPTS 10 /* Max number of attempt to align the phase */ | ||
| 44 | |||
| 45 | /* Local definition of clock type */ | ||
| 46 | #define PLL_CLOCK 1 /* PLL Clock */ | ||
| 47 | #define NON_PLL_CLOCK 2 /* Divider clock */ | ||
| 48 | |||
| 49 | static int chipcHw_divide(int num, int denom) | ||
| 50 | __attribute__ ((section(".aramtext"))); | ||
| 51 | |||
| 52 | /****************************************************************************/ | ||
| 53 | /** | ||
| 54 | * @brief Set clock fequency for miscellaneous configurable clocks | ||
| 55 | * | ||
| 56 | * This function sets clock frequency | ||
| 57 | * | ||
| 58 | * @return Configured clock frequency in hertz | ||
| 59 | * | ||
| 60 | */ | ||
| 61 | /****************************************************************************/ | ||
| 62 | chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 63 | ) { | ||
| 64 | volatile uint32_t *pPLLReg = (uint32_t *) 0x0; | ||
| 65 | volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; | ||
| 66 | volatile uint32_t *pDependentClock = (uint32_t *) 0x0; | ||
| 67 | uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ | ||
| 68 | uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ | ||
| 69 | uint32_t dependentClockType = 0; | ||
| 70 | uint32_t vcoHz = 0; | ||
| 71 | |||
| 72 | /* Get VCO frequencies */ | ||
| 73 | if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { | ||
| 74 | uint64_t adjustFreq = 0; | ||
| 75 | |||
| 76 | vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * | ||
| 77 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 78 | ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 79 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 80 | |||
| 81 | /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ | ||
| 82 | adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz * | ||
| 83 | (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * | ||
| 84 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC)); | ||
| 85 | vcoFreqPll1Hz += (uint32_t) adjustFreq; | ||
| 86 | } else { | ||
| 87 | vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * | ||
| 88 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 89 | ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 90 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 91 | } | ||
| 92 | vcoFreqPll2Hz = | ||
| 93 | chipcHw_XTAL_FREQ_Hz * | ||
| 94 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 95 | ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 96 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 97 | |||
| 98 | switch (clock) { | ||
| 99 | case chipcHw_CLOCK_DDR: | ||
| 100 | pPLLReg = &pChipcHw->DDRClock; | ||
| 101 | vcoHz = vcoFreqPll1Hz; | ||
| 102 | break; | ||
| 103 | case chipcHw_CLOCK_ARM: | ||
| 104 | pPLLReg = &pChipcHw->ARMClock; | ||
| 105 | vcoHz = vcoFreqPll1Hz; | ||
| 106 | break; | ||
| 107 | case chipcHw_CLOCK_ESW: | ||
| 108 | pPLLReg = &pChipcHw->ESWClock; | ||
| 109 | vcoHz = vcoFreqPll1Hz; | ||
| 110 | break; | ||
| 111 | case chipcHw_CLOCK_VPM: | ||
| 112 | pPLLReg = &pChipcHw->VPMClock; | ||
| 113 | vcoHz = vcoFreqPll1Hz; | ||
| 114 | break; | ||
| 115 | case chipcHw_CLOCK_ESW125: | ||
| 116 | pPLLReg = &pChipcHw->ESW125Clock; | ||
| 117 | vcoHz = vcoFreqPll1Hz; | ||
| 118 | break; | ||
| 119 | case chipcHw_CLOCK_UART: | ||
| 120 | pPLLReg = &pChipcHw->UARTClock; | ||
| 121 | vcoHz = vcoFreqPll1Hz; | ||
| 122 | break; | ||
| 123 | case chipcHw_CLOCK_SDIO0: | ||
| 124 | pPLLReg = &pChipcHw->SDIO0Clock; | ||
| 125 | vcoHz = vcoFreqPll1Hz; | ||
| 126 | break; | ||
| 127 | case chipcHw_CLOCK_SDIO1: | ||
| 128 | pPLLReg = &pChipcHw->SDIO1Clock; | ||
| 129 | vcoHz = vcoFreqPll1Hz; | ||
| 130 | break; | ||
| 131 | case chipcHw_CLOCK_SPI: | ||
| 132 | pPLLReg = &pChipcHw->SPIClock; | ||
| 133 | vcoHz = vcoFreqPll1Hz; | ||
| 134 | break; | ||
| 135 | case chipcHw_CLOCK_ETM: | ||
| 136 | pPLLReg = &pChipcHw->ETMClock; | ||
| 137 | vcoHz = vcoFreqPll1Hz; | ||
| 138 | break; | ||
| 139 | case chipcHw_CLOCK_USB: | ||
| 140 | pPLLReg = &pChipcHw->USBClock; | ||
| 141 | vcoHz = vcoFreqPll2Hz; | ||
| 142 | break; | ||
| 143 | case chipcHw_CLOCK_LCD: | ||
| 144 | pPLLReg = &pChipcHw->LCDClock; | ||
| 145 | vcoHz = vcoFreqPll2Hz; | ||
| 146 | break; | ||
| 147 | case chipcHw_CLOCK_APM: | ||
| 148 | pPLLReg = &pChipcHw->APMClock; | ||
| 149 | vcoHz = vcoFreqPll2Hz; | ||
| 150 | break; | ||
| 151 | case chipcHw_CLOCK_BUS: | ||
| 152 | pClockCtrl = &pChipcHw->ACLKClock; | ||
| 153 | pDependentClock = &pChipcHw->ARMClock; | ||
| 154 | vcoHz = vcoFreqPll1Hz; | ||
| 155 | dependentClockType = PLL_CLOCK; | ||
| 156 | break; | ||
| 157 | case chipcHw_CLOCK_OTP: | ||
| 158 | pClockCtrl = &pChipcHw->OTPClock; | ||
| 159 | break; | ||
| 160 | case chipcHw_CLOCK_I2C: | ||
| 161 | pClockCtrl = &pChipcHw->I2CClock; | ||
| 162 | break; | ||
| 163 | case chipcHw_CLOCK_I2S0: | ||
| 164 | pClockCtrl = &pChipcHw->I2S0Clock; | ||
| 165 | break; | ||
| 166 | case chipcHw_CLOCK_RTBUS: | ||
| 167 | pClockCtrl = &pChipcHw->RTBUSClock; | ||
| 168 | pDependentClock = &pChipcHw->ACLKClock; | ||
| 169 | dependentClockType = NON_PLL_CLOCK; | ||
| 170 | break; | ||
| 171 | case chipcHw_CLOCK_APM100: | ||
| 172 | pClockCtrl = &pChipcHw->APM100Clock; | ||
| 173 | pDependentClock = &pChipcHw->APMClock; | ||
| 174 | vcoHz = vcoFreqPll2Hz; | ||
| 175 | dependentClockType = PLL_CLOCK; | ||
| 176 | break; | ||
| 177 | case chipcHw_CLOCK_TSC: | ||
| 178 | pClockCtrl = &pChipcHw->TSCClock; | ||
| 179 | break; | ||
| 180 | case chipcHw_CLOCK_LED: | ||
| 181 | pClockCtrl = &pChipcHw->LEDClock; | ||
| 182 | break; | ||
| 183 | case chipcHw_CLOCK_I2S1: | ||
| 184 | pClockCtrl = &pChipcHw->I2S1Clock; | ||
| 185 | break; | ||
| 186 | } | ||
| 187 | |||
| 188 | if (pPLLReg) { | ||
| 189 | /* Obtain PLL clock frequency */ | ||
| 190 | if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { | ||
| 191 | /* Return crystal clock frequency when bypassed */ | ||
| 192 | return chipcHw_XTAL_FREQ_Hz; | ||
| 193 | } else if (clock == chipcHw_CLOCK_DDR) { | ||
| 194 | /* DDR frequency is configured in PLLDivider register */ | ||
| 195 | return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); | ||
| 196 | } else { | ||
| 197 | /* From chip revision number B0, LCD clock is internally divided by 2 */ | ||
| 198 | if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { | ||
| 199 | vcoHz >>= 1; | ||
| 200 | } | ||
| 201 | /* Obtain PLL clock frequency using VCO dividers */ | ||
| 202 | return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); | ||
| 203 | } | ||
| 204 | } else if (pClockCtrl) { | ||
| 205 | /* Obtain divider clock frequency */ | ||
| 206 | uint32_t div; | ||
| 207 | uint32_t freq = 0; | ||
| 208 | |||
| 209 | if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { | ||
| 210 | /* Return crystal clock frequency when bypassed */ | ||
| 211 | return chipcHw_XTAL_FREQ_Hz; | ||
| 212 | } else if (pDependentClock) { | ||
| 213 | /* Identify the dependent clock frequency */ | ||
| 214 | switch (dependentClockType) { | ||
| 215 | case PLL_CLOCK: | ||
| 216 | if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) { | ||
| 217 | /* Use crystal clock frequency when dependent PLL clock is bypassed */ | ||
| 218 | freq = chipcHw_XTAL_FREQ_Hz; | ||
| 219 | } else { | ||
| 220 | /* Obtain PLL clock frequency using VCO dividers */ | ||
| 221 | div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK; | ||
| 222 | freq = div ? chipcHw_divide(vcoHz, div) : 0; | ||
| 223 | } | ||
| 224 | break; | ||
| 225 | case NON_PLL_CLOCK: | ||
| 226 | if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { | ||
| 227 | freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); | ||
| 228 | } else { | ||
| 229 | if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) { | ||
| 230 | /* Use crystal clock frequency when dependent divider clock is bypassed */ | ||
| 231 | freq = chipcHw_XTAL_FREQ_Hz; | ||
| 232 | } else { | ||
| 233 | /* Obtain divider clock frequency using XTAL dividers */ | ||
| 234 | div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; | ||
| 235 | freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256)); | ||
| 236 | } | ||
| 237 | } | ||
| 238 | break; | ||
| 239 | } | ||
| 240 | } else { | ||
| 241 | /* Dependent on crystal clock */ | ||
| 242 | freq = chipcHw_XTAL_FREQ_Hz; | ||
| 243 | } | ||
| 244 | |||
| 245 | div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK; | ||
| 246 | return chipcHw_divide(freq, (div ? div : 256)); | ||
| 247 | } | ||
| 248 | return 0; | ||
| 249 | } | ||
| 250 | |||
| 251 | /****************************************************************************/ | ||
| 252 | /** | ||
| 253 | * @brief Set clock fequency for miscellaneous configurable clocks | ||
| 254 | * | ||
| 255 | * This function sets clock frequency | ||
| 256 | * | ||
| 257 | * @return Configured clock frequency in Hz | ||
| 258 | * | ||
| 259 | */ | ||
| 260 | /****************************************************************************/ | ||
| 261 | chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ | ||
| 262 | uint32_t freq /* [ IN ] Clock frequency in Hz */ | ||
| 263 | ) { | ||
| 264 | volatile uint32_t *pPLLReg = (uint32_t *) 0x0; | ||
| 265 | volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; | ||
| 266 | volatile uint32_t *pDependentClock = (uint32_t *) 0x0; | ||
| 267 | uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */ | ||
| 268 | uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */ | ||
| 269 | uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */ | ||
| 270 | uint32_t dependentClockType = 0; | ||
| 271 | uint32_t vcoHz = 0; | ||
| 272 | uint32_t desVcoHz = 0; | ||
| 273 | |||
| 274 | /* Get VCO frequencies */ | ||
| 275 | if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { | ||
| 276 | uint64_t adjustFreq = 0; | ||
| 277 | |||
| 278 | vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * | ||
| 279 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 280 | ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 281 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 282 | |||
| 283 | /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */ | ||
| 284 | adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz * | ||
| 285 | (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS * | ||
| 286 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC)); | ||
| 287 | vcoFreqPll1Hz += (uint32_t) adjustFreq; | ||
| 288 | |||
| 289 | /* Desired VCO frequency */ | ||
| 290 | desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * | ||
| 291 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 292 | (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 293 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1); | ||
| 294 | } else { | ||
| 295 | vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz * | ||
| 296 | chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 297 | ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 298 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 299 | } | ||
| 300 | vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) * | ||
| 301 | ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >> | ||
| 302 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT); | ||
| 303 | |||
| 304 | switch (clock) { | ||
| 305 | case chipcHw_CLOCK_DDR: | ||
| 306 | /* Configure the DDR_ctrl:BUS ratio settings */ | ||
| 307 | { | ||
| 308 | REG_LOCAL_IRQ_SAVE; | ||
| 309 | /* Dvide DDR_phy by two to obtain DDR_ctrl clock */ | ||
| 310 | pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) | ||
| 311 | << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); | ||
| 312 | REG_LOCAL_IRQ_RESTORE; | ||
| 313 | } | ||
| 314 | pPLLReg = &pChipcHw->DDRClock; | ||
| 315 | vcoHz = vcoFreqPll1Hz; | ||
| 316 | desVcoHz = desVcoFreqPll1Hz; | ||
| 317 | break; | ||
| 318 | case chipcHw_CLOCK_ARM: | ||
| 319 | pPLLReg = &pChipcHw->ARMClock; | ||
| 320 | vcoHz = vcoFreqPll1Hz; | ||
| 321 | desVcoHz = desVcoFreqPll1Hz; | ||
| 322 | break; | ||
| 323 | case chipcHw_CLOCK_ESW: | ||
| 324 | pPLLReg = &pChipcHw->ESWClock; | ||
| 325 | vcoHz = vcoFreqPll1Hz; | ||
| 326 | desVcoHz = desVcoFreqPll1Hz; | ||
| 327 | break; | ||
| 328 | case chipcHw_CLOCK_VPM: | ||
| 329 | /* Configure the VPM:BUS ratio settings */ | ||
| 330 | { | ||
| 331 | REG_LOCAL_IRQ_SAVE; | ||
| 332 | pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) | ||
| 333 | << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT); | ||
| 334 | REG_LOCAL_IRQ_RESTORE; | ||
| 335 | } | ||
| 336 | pPLLReg = &pChipcHw->VPMClock; | ||
| 337 | vcoHz = vcoFreqPll1Hz; | ||
| 338 | desVcoHz = desVcoFreqPll1Hz; | ||
| 339 | break; | ||
| 340 | case chipcHw_CLOCK_ESW125: | ||
| 341 | pPLLReg = &pChipcHw->ESW125Clock; | ||
| 342 | vcoHz = vcoFreqPll1Hz; | ||
| 343 | desVcoHz = desVcoFreqPll1Hz; | ||
| 344 | break; | ||
| 345 | case chipcHw_CLOCK_UART: | ||
| 346 | pPLLReg = &pChipcHw->UARTClock; | ||
| 347 | vcoHz = vcoFreqPll1Hz; | ||
| 348 | desVcoHz = desVcoFreqPll1Hz; | ||
| 349 | break; | ||
| 350 | case chipcHw_CLOCK_SDIO0: | ||
| 351 | pPLLReg = &pChipcHw->SDIO0Clock; | ||
| 352 | vcoHz = vcoFreqPll1Hz; | ||
| 353 | desVcoHz = desVcoFreqPll1Hz; | ||
| 354 | break; | ||
| 355 | case chipcHw_CLOCK_SDIO1: | ||
| 356 | pPLLReg = &pChipcHw->SDIO1Clock; | ||
| 357 | vcoHz = vcoFreqPll1Hz; | ||
| 358 | desVcoHz = desVcoFreqPll1Hz; | ||
| 359 | break; | ||
| 360 | case chipcHw_CLOCK_SPI: | ||
| 361 | pPLLReg = &pChipcHw->SPIClock; | ||
| 362 | vcoHz = vcoFreqPll1Hz; | ||
| 363 | desVcoHz = desVcoFreqPll1Hz; | ||
| 364 | break; | ||
| 365 | case chipcHw_CLOCK_ETM: | ||
| 366 | pPLLReg = &pChipcHw->ETMClock; | ||
| 367 | vcoHz = vcoFreqPll1Hz; | ||
| 368 | desVcoHz = desVcoFreqPll1Hz; | ||
| 369 | break; | ||
| 370 | case chipcHw_CLOCK_USB: | ||
| 371 | pPLLReg = &pChipcHw->USBClock; | ||
| 372 | vcoHz = vcoFreqPll2Hz; | ||
| 373 | desVcoHz = vcoFreqPll2Hz; | ||
| 374 | break; | ||
| 375 | case chipcHw_CLOCK_LCD: | ||
| 376 | pPLLReg = &pChipcHw->LCDClock; | ||
| 377 | vcoHz = vcoFreqPll2Hz; | ||
| 378 | desVcoHz = vcoFreqPll2Hz; | ||
| 379 | break; | ||
| 380 | case chipcHw_CLOCK_APM: | ||
| 381 | pPLLReg = &pChipcHw->APMClock; | ||
| 382 | vcoHz = vcoFreqPll2Hz; | ||
| 383 | desVcoHz = vcoFreqPll2Hz; | ||
| 384 | break; | ||
| 385 | case chipcHw_CLOCK_BUS: | ||
| 386 | pClockCtrl = &pChipcHw->ACLKClock; | ||
| 387 | pDependentClock = &pChipcHw->ARMClock; | ||
| 388 | vcoHz = vcoFreqPll1Hz; | ||
| 389 | desVcoHz = desVcoFreqPll1Hz; | ||
| 390 | dependentClockType = PLL_CLOCK; | ||
| 391 | break; | ||
| 392 | case chipcHw_CLOCK_OTP: | ||
| 393 | pClockCtrl = &pChipcHw->OTPClock; | ||
| 394 | break; | ||
| 395 | case chipcHw_CLOCK_I2C: | ||
| 396 | pClockCtrl = &pChipcHw->I2CClock; | ||
| 397 | break; | ||
| 398 | case chipcHw_CLOCK_I2S0: | ||
| 399 | pClockCtrl = &pChipcHw->I2S0Clock; | ||
| 400 | break; | ||
| 401 | case chipcHw_CLOCK_RTBUS: | ||
| 402 | pClockCtrl = &pChipcHw->RTBUSClock; | ||
| 403 | pDependentClock = &pChipcHw->ACLKClock; | ||
| 404 | dependentClockType = NON_PLL_CLOCK; | ||
| 405 | break; | ||
| 406 | case chipcHw_CLOCK_APM100: | ||
| 407 | pClockCtrl = &pChipcHw->APM100Clock; | ||
| 408 | pDependentClock = &pChipcHw->APMClock; | ||
| 409 | vcoHz = vcoFreqPll2Hz; | ||
| 410 | desVcoHz = vcoFreqPll2Hz; | ||
| 411 | dependentClockType = PLL_CLOCK; | ||
| 412 | break; | ||
| 413 | case chipcHw_CLOCK_TSC: | ||
| 414 | pClockCtrl = &pChipcHw->TSCClock; | ||
| 415 | break; | ||
| 416 | case chipcHw_CLOCK_LED: | ||
| 417 | pClockCtrl = &pChipcHw->LEDClock; | ||
| 418 | break; | ||
| 419 | case chipcHw_CLOCK_I2S1: | ||
| 420 | pClockCtrl = &pChipcHw->I2S1Clock; | ||
| 421 | break; | ||
| 422 | } | ||
| 423 | |||
| 424 | if (pPLLReg) { | ||
| 425 | /* Select XTAL as bypass source */ | ||
| 426 | reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO); | ||
| 427 | reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); | ||
| 428 | /* For DDR settings use only the PLL divider clock */ | ||
| 429 | if (pPLLReg == &pChipcHw->DDRClock) { | ||
| 430 | /* Set M1DIV for PLL1, which controls the DDR clock */ | ||
| 431 | reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24)); | ||
| 432 | /* Calculate expected frequency */ | ||
| 433 | freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256)); | ||
| 434 | } else { | ||
| 435 | /* From chip revision number B0, LCD clock is internally divided by 2 */ | ||
| 436 | if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) { | ||
| 437 | desVcoHz >>= 1; | ||
| 438 | vcoHz >>= 1; | ||
| 439 | } | ||
| 440 | /* Set MDIV to change the frequency */ | ||
| 441 | reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK)); | ||
| 442 | reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq)); | ||
| 443 | /* Calculate expected frequency */ | ||
| 444 | freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256)); | ||
| 445 | } | ||
| 446 | /* Wait for for atleast 200ns as per the protocol to change frequency */ | ||
| 447 | udelay(1); | ||
| 448 | /* Do not bypass */ | ||
| 449 | reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); | ||
| 450 | /* Return the configured frequency */ | ||
| 451 | return freq; | ||
| 452 | } else if (pClockCtrl) { | ||
| 453 | uint32_t divider = 0; | ||
| 454 | |||
| 455 | /* Divider clock should not be bypassed */ | ||
| 456 | reg32_modify_and(pClockCtrl, | ||
| 457 | ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); | ||
| 458 | |||
| 459 | /* Identify the clock source */ | ||
| 460 | if (pDependentClock) { | ||
| 461 | switch (dependentClockType) { | ||
| 462 | case PLL_CLOCK: | ||
| 463 | divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq); | ||
| 464 | break; | ||
| 465 | case NON_PLL_CLOCK: | ||
| 466 | { | ||
| 467 | uint32_t sourceClock = 0; | ||
| 468 | |||
| 469 | if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) { | ||
| 470 | sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS); | ||
| 471 | } else { | ||
| 472 | uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK; | ||
| 473 | sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256)); | ||
| 474 | } | ||
| 475 | divider = chipcHw_divide(sourceClock, freq); | ||
| 476 | } | ||
| 477 | break; | ||
| 478 | } | ||
| 479 | } else { | ||
| 480 | divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq); | ||
| 481 | } | ||
| 482 | |||
| 483 | if (divider) { | ||
| 484 | REG_LOCAL_IRQ_SAVE; | ||
| 485 | /* Set the divider to obtain the required frequency */ | ||
| 486 | *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK); | ||
| 487 | REG_LOCAL_IRQ_RESTORE; | ||
| 488 | return freq; | ||
| 489 | } | ||
| 490 | } | ||
| 491 | |||
| 492 | return 0; | ||
| 493 | } | ||
| 494 | |||
| 495 | EXPORT_SYMBOL(chipcHw_setClockFrequency); | ||
| 496 | |||
| 497 | /****************************************************************************/ | ||
| 498 | /** | ||
| 499 | * @brief Set VPM clock in sync with BUS clock for Chip Rev #A0 | ||
| 500 | * | ||
| 501 | * This function does the phase adjustment between VPM and BUS clock | ||
| 502 | * | ||
| 503 | * @return >= 0 : On success (# of adjustment required) | ||
| 504 | * -1 : On failure | ||
| 505 | * | ||
| 506 | */ | ||
| 507 | /****************************************************************************/ | ||
| 508 | static int vpmPhaseAlignA0(void) | ||
| 509 | { | ||
| 510 | uint32_t phaseControl; | ||
| 511 | uint32_t phaseValue; | ||
| 512 | uint32_t prevPhaseComp; | ||
| 513 | int iter = 0; | ||
| 514 | int adjustCount = 0; | ||
| 515 | int count = 0; | ||
| 516 | |||
| 517 | for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) { | ||
| 518 | phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT; | ||
| 519 | phaseValue = 0; | ||
| 520 | prevPhaseComp = 0; | ||
| 521 | |||
| 522 | /* Step 1: Look for falling PH_COMP transition */ | ||
| 523 | |||
| 524 | /* Read the contents of VPM Clock resgister */ | ||
| 525 | phaseValue = pChipcHw->VPMClock; | ||
| 526 | do { | ||
| 527 | /* Store previous value of phase comparator */ | ||
| 528 | prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP; | ||
| 529 | /* Change the value of PH_CTRL. */ | ||
| 530 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 531 | /* Wait atleast 20 ns */ | ||
| 532 | udelay(1); | ||
| 533 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 534 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 535 | /* Read the contents of VPM Clock resgister. */ | ||
| 536 | phaseValue = pChipcHw->VPMClock; | ||
| 537 | |||
| 538 | if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { | ||
| 539 | phaseControl = (0x3F & (phaseControl - 1)); | ||
| 540 | } else { | ||
| 541 | /* Increment to the Phase count value for next write, if Phase is not stable. */ | ||
| 542 | phaseControl = (0x3F & (phaseControl + 1)); | ||
| 543 | } | ||
| 544 | /* Count number of adjustment made */ | ||
| 545 | adjustCount++; | ||
| 546 | } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */ | ||
| 547 | ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && /* Look for a falling edge */ | ||
| 548 | (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */ | ||
| 549 | ); | ||
| 550 | |||
| 551 | if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { | ||
| 552 | /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ | ||
| 553 | return -1; | ||
| 554 | } | ||
| 555 | |||
| 556 | /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */ | ||
| 557 | |||
| 558 | for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { | ||
| 559 | phaseControl = (0x3F & (phaseControl + 1)); | ||
| 560 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 561 | /* Wait atleast 20 ns */ | ||
| 562 | udelay(1); | ||
| 563 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 564 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 565 | phaseValue = pChipcHw->VPMClock; | ||
| 566 | /* Count number of adjustment made */ | ||
| 567 | adjustCount++; | ||
| 568 | } | ||
| 569 | |||
| 570 | if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { | ||
| 571 | /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ | ||
| 572 | return -1; | ||
| 573 | } | ||
| 574 | |||
| 575 | if (count != 5) { | ||
| 576 | /* Detected false transition */ | ||
| 577 | continue; | ||
| 578 | } | ||
| 579 | |||
| 580 | /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */ | ||
| 581 | |||
| 582 | for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) { | ||
| 583 | phaseControl = (0x3F & (phaseControl - 1)); | ||
| 584 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 585 | /* Wait atleast 20 ns */ | ||
| 586 | udelay(1); | ||
| 587 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 588 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 589 | phaseValue = pChipcHw->VPMClock; | ||
| 590 | /* Count number of adjustment made */ | ||
| 591 | adjustCount++; | ||
| 592 | } | ||
| 593 | |||
| 594 | if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { | ||
| 595 | /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ | ||
| 596 | return -1; | ||
| 597 | } | ||
| 598 | |||
| 599 | if (count != 3) { | ||
| 600 | /* Detected noisy transition */ | ||
| 601 | continue; | ||
| 602 | } | ||
| 603 | |||
| 604 | /* Step 4: Keep moving backward before the original transition took place. */ | ||
| 605 | |||
| 606 | for (count = 0; (count < 5); count++) { | ||
| 607 | phaseControl = (0x3F & (phaseControl - 1)); | ||
| 608 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 609 | /* Wait atleast 20 ns */ | ||
| 610 | udelay(1); | ||
| 611 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 612 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 613 | phaseValue = pChipcHw->VPMClock; | ||
| 614 | /* Count number of adjustment made */ | ||
| 615 | adjustCount++; | ||
| 616 | } | ||
| 617 | |||
| 618 | if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { | ||
| 619 | /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ | ||
| 620 | return -1; | ||
| 621 | } | ||
| 622 | |||
| 623 | if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) { | ||
| 624 | /* Detected false transition */ | ||
| 625 | continue; | ||
| 626 | } | ||
| 627 | |||
| 628 | /* Step 5: Re discover the valid transition */ | ||
| 629 | |||
| 630 | do { | ||
| 631 | /* Store previous value of phase comparator */ | ||
| 632 | prevPhaseComp = phaseValue; | ||
| 633 | /* Change the value of PH_CTRL. */ | ||
| 634 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 635 | /* Wait atleast 20 ns */ | ||
| 636 | udelay(1); | ||
| 637 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 638 | pChipcHw->VPMClock ^= | ||
| 639 | chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 640 | /* Read the contents of VPM Clock resgister. */ | ||
| 641 | phaseValue = pChipcHw->VPMClock; | ||
| 642 | |||
| 643 | if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) { | ||
| 644 | phaseControl = (0x3F & (phaseControl - 1)); | ||
| 645 | } else { | ||
| 646 | /* Increment to the Phase count value for next write, if Phase is not stable. */ | ||
| 647 | phaseControl = (0x3F & (phaseControl + 1)); | ||
| 648 | } | ||
| 649 | |||
| 650 | /* Count number of adjustment made */ | ||
| 651 | adjustCount++; | ||
| 652 | } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT)); | ||
| 653 | |||
| 654 | if (adjustCount >= MAX_PHASE_ADJUST_COUNT) { | ||
| 655 | /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */ | ||
| 656 | return -1; | ||
| 657 | } else { | ||
| 658 | /* Valid phase must have detected */ | ||
| 659 | break; | ||
| 660 | } | ||
| 661 | } | ||
| 662 | |||
| 663 | /* For VPM Phase should be perfectly aligned. */ | ||
| 664 | phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F); | ||
| 665 | { | ||
| 666 | REG_LOCAL_IRQ_SAVE; | ||
| 667 | |||
| 668 | pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT); | ||
| 669 | /* Load new phase value */ | ||
| 670 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 671 | |||
| 672 | REG_LOCAL_IRQ_RESTORE; | ||
| 673 | } | ||
| 674 | /* Return the status */ | ||
| 675 | return (int)adjustCount; | ||
| 676 | } | ||
| 677 | |||
| 678 | /****************************************************************************/ | ||
| 679 | /** | ||
| 680 | * @brief Set VPM clock in sync with BUS clock | ||
| 681 | * | ||
| 682 | * This function does the phase adjustment between VPM and BUS clock | ||
| 683 | * | ||
| 684 | * @return >= 0 : On success (# of adjustment required) | ||
| 685 | * -1 : On failure | ||
| 686 | * | ||
| 687 | */ | ||
| 688 | /****************************************************************************/ | ||
| 689 | int chipcHw_vpmPhaseAlign(void) | ||
| 690 | { | ||
| 691 | |||
| 692 | if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) { | ||
| 693 | return vpmPhaseAlignA0(); | ||
| 694 | } else { | ||
| 695 | uint32_t phaseControl = chipcHw_getVpmPhaseControl(); | ||
| 696 | uint32_t phaseValue = 0; | ||
| 697 | int adjustCount = 0; | ||
| 698 | |||
| 699 | /* Disable VPM access */ | ||
| 700 | pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; | ||
| 701 | /* Disable HW VPM phase alignment */ | ||
| 702 | chipcHw_vpmHwPhaseAlignDisable(); | ||
| 703 | /* Enable SW VPM phase alignment */ | ||
| 704 | chipcHw_vpmSwPhaseAlignEnable(); | ||
| 705 | /* Adjust VPM phase */ | ||
| 706 | while (adjustCount < MAX_PHASE_ADJUST_COUNT) { | ||
| 707 | phaseValue = chipcHw_getVpmHwPhaseAlignStatus(); | ||
| 708 | |||
| 709 | /* Adjust phase control value */ | ||
| 710 | if (phaseValue > 0xF) { | ||
| 711 | /* Increment phase control value */ | ||
| 712 | phaseControl++; | ||
| 713 | } else if (phaseValue < 0xF) { | ||
| 714 | /* Decrement phase control value */ | ||
| 715 | phaseControl--; | ||
| 716 | } else { | ||
| 717 | /* Enable VPM access */ | ||
| 718 | pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; | ||
| 719 | /* Return adjust count */ | ||
| 720 | return adjustCount; | ||
| 721 | } | ||
| 722 | /* Change the value of PH_CTRL. */ | ||
| 723 | reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT)); | ||
| 724 | /* Wait atleast 20 ns */ | ||
| 725 | udelay(1); | ||
| 726 | /* Toggle the LOAD_CH after phase control is written. */ | ||
| 727 | pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE; | ||
| 728 | /* Count adjustment */ | ||
| 729 | adjustCount++; | ||
| 730 | } | ||
| 731 | } | ||
| 732 | |||
| 733 | /* Disable VPM access */ | ||
| 734 | pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE; | ||
| 735 | return -1; | ||
| 736 | } | ||
| 737 | |||
| 738 | /****************************************************************************/ | ||
| 739 | /** | ||
| 740 | * @brief Local Divide function | ||
| 741 | * | ||
| 742 | * This function does the divide | ||
| 743 | * | ||
| 744 | * @return divide value | ||
| 745 | * | ||
| 746 | */ | ||
| 747 | /****************************************************************************/ | ||
| 748 | static int chipcHw_divide(int num, int denom) | ||
| 749 | { | ||
| 750 | int r; | ||
| 751 | int t = 1; | ||
| 752 | |||
| 753 | /* Shift denom and t up to the largest value to optimize algorithm */ | ||
| 754 | /* t contains the units of each divide */ | ||
| 755 | while ((denom & 0x40000000) == 0) { /* fails if denom=0 */ | ||
| 756 | denom = denom << 1; | ||
| 757 | t = t << 1; | ||
| 758 | } | ||
| 759 | |||
| 760 | /* Intialize the result */ | ||
| 761 | r = 0; | ||
| 762 | |||
| 763 | do { | ||
| 764 | /* Determine if there exists a positive remainder */ | ||
| 765 | if ((num - denom) >= 0) { | ||
| 766 | /* Accumlate t to the result and calculate a new remainder */ | ||
| 767 | num = num - denom; | ||
| 768 | r = r + t; | ||
| 769 | } | ||
| 770 | /* Continue to shift denom and shift t down to 0 */ | ||
| 771 | denom = denom >> 1; | ||
| 772 | t = t >> 1; | ||
| 773 | } while (t != 0); | ||
| 774 | |||
| 775 | return r; | ||
| 776 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c new file mode 100644 index 000000000000..367df75d4bb3 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c | |||
| @@ -0,0 +1,293 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file chipcHw_init.c | ||
| 18 | * | ||
| 19 | * @brief Low level CHIPC PLL configuration functions | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * | ||
| 23 | * These routines provide basic PLL controlling functionality only. | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 28 | |||
| 29 | #include <csp/errno.h> | ||
| 30 | #include <csp/stdint.h> | ||
| 31 | #include <csp/module.h> | ||
| 32 | |||
| 33 | #include <mach/csp/chipcHw_def.h> | ||
| 34 | #include <mach/csp/chipcHw_inline.h> | ||
| 35 | |||
| 36 | #include <csp/reg.h> | ||
| 37 | #include <csp/delay.h> | ||
| 38 | /* ---- Private Constants and Types --------------------------------------- */ | ||
| 39 | |||
| 40 | /* | ||
| 41 | Calculation for NDIV_i to obtain VCO frequency | ||
| 42 | ----------------------------------------------- | ||
| 43 | |||
| 44 | Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f) | ||
| 45 | for Freq_vco = VCO_FREQ_MHz | ||
| 46 | Freq_ref = chipcHw_XTAL_FREQ_Hz | ||
| 47 | PLL_P1 = PLL_P2 = 1 | ||
| 48 | and | ||
| 49 | PLL_NDIV_f = 0 | ||
| 50 | |||
| 51 | We get: | ||
| 52 | PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz | ||
| 53 | |||
| 54 | Calculation for PLL MDIV to obtain frequency Freq_x for channel x | ||
| 55 | ----------------------------------------------------------------- | ||
| 56 | Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x | ||
| 57 | |||
| 58 | PLL_MDIV_x = VCO_FREQ_MHz / Freq_x | ||
| 59 | */ | ||
| 60 | |||
| 61 | /* ---- Private Variables ------------------------------------------------- */ | ||
| 62 | /****************************************************************************/ | ||
| 63 | /** | ||
| 64 | * @brief Initializes the PLL2 | ||
| 65 | * | ||
| 66 | * This function initializes the PLL2 | ||
| 67 | * | ||
| 68 | */ | ||
| 69 | /****************************************************************************/ | ||
| 70 | void chipcHw_pll2Enable(uint32_t vcoFreqHz) | ||
| 71 | { | ||
| 72 | uint32_t pllPreDivider2 = 0; | ||
| 73 | |||
| 74 | { | ||
| 75 | REG_LOCAL_IRQ_SAVE; | ||
| 76 | pChipcHw->PLLConfig2 = | ||
| 77 | chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 78 | chipcHw_REG_PLL_CONFIG_A_RESET; | ||
| 79 | |||
| 80 | pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | | ||
| 81 | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | | ||
| 82 | (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) << | ||
| 83 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | | ||
| 84 | (chipcHw_REG_PLL_PREDIVIDER_P1 << | ||
| 85 | chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | | ||
| 86 | (chipcHw_REG_PLL_PREDIVIDER_P2 << | ||
| 87 | chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); | ||
| 88 | |||
| 89 | /* Enable CHIPC registers to control the PLL */ | ||
| 90 | pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; | ||
| 91 | |||
| 92 | /* Set pre divider to get desired VCO frequency */ | ||
| 93 | pChipcHw->PLLPreDivider2 = pllPreDivider2; | ||
| 94 | /* Set NDIV Frac */ | ||
| 95 | pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f; | ||
| 96 | |||
| 97 | /* This has to be removed once the default values are fixed for PLL2. */ | ||
| 98 | pChipcHw->PLLControl12 = 0x38000700; | ||
| 99 | pChipcHw->PLLControl22 = 0x00000015; | ||
| 100 | |||
| 101 | /* Reset PLL2 */ | ||
| 102 | if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { | ||
| 103 | pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 104 | chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 105 | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | | ||
| 106 | chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 107 | } else { | ||
| 108 | pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 109 | chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 110 | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | | ||
| 111 | chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 112 | } | ||
| 113 | REG_LOCAL_IRQ_RESTORE; | ||
| 114 | } | ||
| 115 | |||
| 116 | /* Insert certain amount of delay before deasserting ARESET. */ | ||
| 117 | udelay(1); | ||
| 118 | |||
| 119 | { | ||
| 120 | REG_LOCAL_IRQ_SAVE; | ||
| 121 | /* Remove analog reset and Power on the PLL */ | ||
| 122 | pChipcHw->PLLConfig2 &= | ||
| 123 | ~(chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 124 | chipcHw_REG_PLL_CONFIG_POWER_DOWN); | ||
| 125 | |||
| 126 | REG_LOCAL_IRQ_RESTORE; | ||
| 127 | |||
| 128 | } | ||
| 129 | |||
| 130 | /* Wait until PLL is locked */ | ||
| 131 | while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) | ||
| 132 | ; | ||
| 133 | |||
| 134 | { | ||
| 135 | REG_LOCAL_IRQ_SAVE; | ||
| 136 | /* Remove digital reset */ | ||
| 137 | pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET; | ||
| 138 | |||
| 139 | REG_LOCAL_IRQ_RESTORE; | ||
| 140 | } | ||
| 141 | } | ||
| 142 | |||
| 143 | EXPORT_SYMBOL(chipcHw_pll2Enable); | ||
| 144 | |||
| 145 | /****************************************************************************/ | ||
| 146 | /** | ||
| 147 | * @brief Initializes the PLL1 | ||
| 148 | * | ||
| 149 | * This function initializes the PLL1 | ||
| 150 | * | ||
| 151 | */ | ||
| 152 | /****************************************************************************/ | ||
| 153 | void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport) | ||
| 154 | { | ||
| 155 | uint32_t pllPreDivider = 0; | ||
| 156 | |||
| 157 | { | ||
| 158 | REG_LOCAL_IRQ_SAVE; | ||
| 159 | |||
| 160 | pChipcHw->PLLConfig = | ||
| 161 | chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 162 | chipcHw_REG_PLL_CONFIG_A_RESET; | ||
| 163 | /* Setting VCO frequency */ | ||
| 164 | if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { | ||
| 165 | pllPreDivider = | ||
| 166 | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 | | ||
| 167 | ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) - | ||
| 168 | 1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | | ||
| 169 | (chipcHw_REG_PLL_PREDIVIDER_P1 << | ||
| 170 | chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | | ||
| 171 | (chipcHw_REG_PLL_PREDIVIDER_P2 << | ||
| 172 | chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); | ||
| 173 | } else { | ||
| 174 | pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN | | ||
| 175 | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER | | ||
| 176 | (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) << | ||
| 177 | chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) | | ||
| 178 | (chipcHw_REG_PLL_PREDIVIDER_P1 << | ||
| 179 | chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) | | ||
| 180 | (chipcHw_REG_PLL_PREDIVIDER_P2 << | ||
| 181 | chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT); | ||
| 182 | } | ||
| 183 | |||
| 184 | /* Enable CHIPC registers to control the PLL */ | ||
| 185 | pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE; | ||
| 186 | |||
| 187 | /* Set pre divider to get desired VCO frequency */ | ||
| 188 | pChipcHw->PLLPreDivider = pllPreDivider; | ||
| 189 | /* Set NDIV Frac */ | ||
| 190 | if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) { | ||
| 191 | pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | | ||
| 192 | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS; | ||
| 193 | } else { | ||
| 194 | pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV | | ||
| 195 | chipcHw_REG_PLL_DIVIDER_NDIV_f; | ||
| 196 | } | ||
| 197 | |||
| 198 | /* Reset PLL1 */ | ||
| 199 | if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) { | ||
| 200 | pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 201 | chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 202 | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | | ||
| 203 | chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 204 | } else { | ||
| 205 | pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET | | ||
| 206 | chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 207 | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | | ||
| 208 | chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 209 | } | ||
| 210 | |||
| 211 | REG_LOCAL_IRQ_RESTORE; | ||
| 212 | |||
| 213 | /* Insert certain amount of delay before deasserting ARESET. */ | ||
| 214 | udelay(1); | ||
| 215 | |||
| 216 | { | ||
| 217 | REG_LOCAL_IRQ_SAVE; | ||
| 218 | /* Remove analog reset and Power on the PLL */ | ||
| 219 | pChipcHw->PLLConfig &= | ||
| 220 | ~(chipcHw_REG_PLL_CONFIG_A_RESET | | ||
| 221 | chipcHw_REG_PLL_CONFIG_POWER_DOWN); | ||
| 222 | REG_LOCAL_IRQ_RESTORE; | ||
| 223 | } | ||
| 224 | |||
| 225 | /* Wait until PLL is locked */ | ||
| 226 | while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED) | ||
| 227 | || !(pChipcHw-> | ||
| 228 | PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED)) | ||
| 229 | ; | ||
| 230 | |||
| 231 | /* Remove digital reset */ | ||
| 232 | { | ||
| 233 | REG_LOCAL_IRQ_SAVE; | ||
| 234 | pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET; | ||
| 235 | REG_LOCAL_IRQ_RESTORE; | ||
| 236 | } | ||
| 237 | } | ||
| 238 | } | ||
| 239 | |||
| 240 | EXPORT_SYMBOL(chipcHw_pll1Enable); | ||
| 241 | |||
| 242 | /****************************************************************************/ | ||
| 243 | /** | ||
| 244 | * @brief Initializes the chipc module | ||
| 245 | * | ||
| 246 | * This function initializes the PLLs and core system clocks | ||
| 247 | * | ||
| 248 | */ | ||
| 249 | /****************************************************************************/ | ||
| 250 | |||
| 251 | void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */ | ||
| 252 | ) { | ||
| 253 | #if !(defined(__KERNEL__) && !defined(STANDALONE)) | ||
| 254 | delay_init(); | ||
| 255 | #endif | ||
| 256 | |||
| 257 | /* Do not program PLL, when warm reset */ | ||
| 258 | if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) { | ||
| 259 | chipcHw_pll1Enable(initParam->pllVcoFreqHz, | ||
| 260 | initParam->ssSupport); | ||
| 261 | chipcHw_pll2Enable(initParam->pll2VcoFreqHz); | ||
| 262 | } else { | ||
| 263 | /* Clear sticky bits */ | ||
| 264 | chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET); | ||
| 265 | } | ||
| 266 | /* Clear sticky bits */ | ||
| 267 | chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET); | ||
| 268 | |||
| 269 | /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */ | ||
| 270 | pChipcHw->ACLKClock = | ||
| 271 | (pChipcHw-> | ||
| 272 | ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> | ||
| 273 | armBusRatio & | ||
| 274 | chipcHw_REG_ACLKClock_CLK_DIV_MASK); | ||
| 275 | |||
| 276 | /* Set various core component frequencies. The order in which this is done is important for some. */ | ||
| 277 | /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */ | ||
| 278 | /* frequency to find its ratio with the BUS. Hence we must set the ARM first, followed by the BUS, */ | ||
| 279 | /* then VPM and RTBUS. */ | ||
| 280 | |||
| 281 | chipcHw_setClockFrequency(chipcHw_CLOCK_ARM, | ||
| 282 | initParam->busClockFreqHz * | ||
| 283 | initParam->armBusRatio); | ||
| 284 | chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz); | ||
| 285 | chipcHw_setClockFrequency(chipcHw_CLOCK_VPM, | ||
| 286 | initParam->busClockFreqHz * | ||
| 287 | initParam->vpmBusRatio); | ||
| 288 | chipcHw_setClockFrequency(chipcHw_CLOCK_DDR, | ||
| 289 | initParam->busClockFreqHz * | ||
| 290 | initParam->ddrBusRatio); | ||
| 291 | chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS, | ||
| 292 | initParam->busClockFreqHz / 2); | ||
| 293 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c new file mode 100644 index 000000000000..2671d8896bbb --- /dev/null +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c | |||
| @@ -0,0 +1,124 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 16 | #include <csp/stdint.h> | ||
| 17 | #include <mach/csp/chipcHw_def.h> | ||
| 18 | #include <mach/csp/chipcHw_inline.h> | ||
| 19 | #include <csp/intcHw.h> | ||
| 20 | #include <csp/cache.h> | ||
| 21 | |||
| 22 | /* ---- Private Constants and Types --------------------------------------- */ | ||
| 23 | /* ---- Private Variables ------------------------------------------------- */ | ||
| 24 | void chipcHw_reset_run_from_aram(void); | ||
| 25 | |||
| 26 | typedef void (*RUNFUNC) (void); | ||
| 27 | |||
| 28 | /****************************************************************************/ | ||
| 29 | /** | ||
| 30 | * @brief warmReset | ||
| 31 | * | ||
| 32 | * @note warmReset configures the clocks which are not reset back to the state | ||
| 33 | * required to execute on reset. To do so we need to copy the code into internal | ||
| 34 | * memory to change the ARM clock while we are not executing from DDR. | ||
| 35 | */ | ||
| 36 | /****************************************************************************/ | ||
| 37 | void chipcHw_reset(uint32_t mask) | ||
| 38 | { | ||
| 39 | int i = 0; | ||
| 40 | RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM; | ||
| 41 | |||
| 42 | /* Disable all interrupts */ | ||
| 43 | intcHw_irq_disable(INTCHW_INTC0, 0xffffffff); | ||
| 44 | intcHw_irq_disable(INTCHW_INTC1, 0xffffffff); | ||
| 45 | intcHw_irq_disable(INTCHW_SINTC, 0xffffffff); | ||
| 46 | |||
| 47 | { | ||
| 48 | REG_LOCAL_IRQ_SAVE; | ||
| 49 | if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) { | ||
| 50 | chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); | ||
| 51 | } | ||
| 52 | /* Bypass the PLL clocks before reboot */ | ||
| 53 | pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; | ||
| 54 | pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT; | ||
| 55 | |||
| 56 | /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */ | ||
| 57 | do { | ||
| 58 | ((uint32_t *) MM_IO_BASE_ARAM)[i] = | ||
| 59 | ((uint32_t *) &chipcHw_reset_run_from_aram)[i]; | ||
| 60 | i++; | ||
| 61 | } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */ | ||
| 62 | |||
| 63 | CSP_CACHE_FLUSH_ALL; | ||
| 64 | |||
| 65 | /* run the function from ARAM */ | ||
| 66 | runFunc(); | ||
| 67 | |||
| 68 | /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */ | ||
| 69 | REG_LOCAL_IRQ_RESTORE; | ||
| 70 | } | ||
| 71 | } | ||
| 72 | |||
| 73 | /* This function must run from internal memory */ | ||
| 74 | void chipcHw_reset_run_from_aram(void) | ||
| 75 | { | ||
| 76 | /* Make sure, pipeline is filled with instructions coming from ARAM */ | ||
| 77 | __asm (" nop \n\t" | ||
| 78 | " nop \n\t" | ||
| 79 | #if defined(__KERNEL__) && !defined(STANDALONE) | ||
| 80 | " MRC p15,#0x0,r0,c1,c0,#0 \n\t" | ||
| 81 | " BIC r0,r0,#0xd \n\t" | ||
| 82 | " MCR p15,#0x0,r0,c1,c0,#0 \n\t" | ||
| 83 | " nop \n\t" | ||
| 84 | " nop \n\t" | ||
| 85 | " nop \n\t" | ||
| 86 | " nop \n\t" | ||
| 87 | " nop \n\t" | ||
| 88 | " nop \n\t" | ||
| 89 | #endif | ||
| 90 | " nop \n\t" | ||
| 91 | " nop \n\t" | ||
| 92 | /* Bypass the ARM clock and switch to XTAL clock */ | ||
| 93 | " MOV r2,#0x80000000 \n\t" | ||
| 94 | " LDR r3,[r2,#8] \n\t" | ||
| 95 | " ORR r3,r3,#0x20000 \n\t" | ||
| 96 | " STR r3,[r2,#8] \n\t" | ||
| 97 | |||
| 98 | " nop \n\t" | ||
| 99 | " nop \n\t" | ||
| 100 | " nop \n\t" | ||
| 101 | " nop \n\t" | ||
| 102 | " nop \n\t" | ||
| 103 | " nop \n\t" | ||
| 104 | " nop \n\t" | ||
| 105 | " nop \n\t" | ||
| 106 | " nop \n\t" | ||
| 107 | " nop \n\t" | ||
| 108 | " nop \n\t" | ||
| 109 | " nop \n\t" | ||
| 110 | " nop \n\t" | ||
| 111 | " nop \n\t" | ||
| 112 | " nop \n\t" | ||
| 113 | " nop \n\t" | ||
| 114 | " nop \n\t" | ||
| 115 | " nop \n\t" | ||
| 116 | " nop \n\t" | ||
| 117 | " nop \n\t" | ||
| 118 | /* Issue reset */ | ||
| 119 | " MOV r3,#0x2 \n\t" | ||
| 120 | " STR r3,[r2,#0x80] \n\t" | ||
| 121 | /* End here */ | ||
| 122 | " MOV pc,pc \n\t"); | ||
| 123 | /* 0xe1a0f00f == asm ("mov r15, r15"); */ | ||
| 124 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c new file mode 100644 index 000000000000..54ad964fe94c --- /dev/null +++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | /****************************************************************************/ | ||
| 15 | /** | ||
| 16 | * @file chipcHw_str.c | ||
| 17 | * | ||
| 18 | * @brief Contains strings which are useful to linux and csp | ||
| 19 | * | ||
| 20 | * @note | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | |||
| 24 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 25 | |||
| 26 | #include <mach/csp/chipcHw_inline.h> | ||
| 27 | |||
| 28 | /* ---- Private Constants and Types --------------------------------------- */ | ||
| 29 | |||
| 30 | static const char *gMuxStr[] = { | ||
| 31 | "GPIO", /* 0 */ | ||
| 32 | "KeyPad", /* 1 */ | ||
| 33 | "I2C-Host", /* 2 */ | ||
| 34 | "SPI", /* 3 */ | ||
| 35 | "Uart", /* 4 */ | ||
| 36 | "LED-Mtx-P", /* 5 */ | ||
| 37 | "LED-Mtx-S", /* 6 */ | ||
| 38 | "SDIO-0", /* 7 */ | ||
| 39 | "SDIO-1", /* 8 */ | ||
| 40 | "PCM", /* 9 */ | ||
| 41 | "I2S", /* 10 */ | ||
| 42 | "ETM", /* 11 */ | ||
| 43 | "Debug", /* 12 */ | ||
| 44 | "Misc", /* 13 */ | ||
| 45 | "0xE", /* 14 */ | ||
| 46 | "0xF", /* 15 */ | ||
| 47 | }; | ||
| 48 | |||
| 49 | /****************************************************************************/ | ||
| 50 | /** | ||
| 51 | * @brief Retrieves a string representation of the mux setting for a pin. | ||
| 52 | * | ||
| 53 | * @return Pointer to a character string. | ||
| 54 | */ | ||
| 55 | /****************************************************************************/ | ||
| 56 | |||
| 57 | const char *chipcHw_getGpioPinFunctionStr(int pin) | ||
| 58 | { | ||
| 59 | if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) { | ||
| 60 | return ""; | ||
| 61 | } | ||
| 62 | |||
| 63 | return gMuxStr[chipcHw_getGpioPinFunction(pin)]; | ||
| 64 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile new file mode 100644 index 000000000000..fb1104fe56b2 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/dmac/Makefile | |||
| @@ -0,0 +1 @@ | |||
| obj-y += dmacHw.o dmacHw_extra.o \ No newline at end of file | |||
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c new file mode 100644 index 000000000000..7b9bac2d79a5 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c | |||
| @@ -0,0 +1,917 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dmacHw.c | ||
| 18 | * | ||
| 19 | * @brief Low level DMA controller driver routines | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * | ||
| 23 | * These routines provide basic DMA functionality only. | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 28 | #include <csp/stdint.h> | ||
| 29 | #include <csp/string.h> | ||
| 30 | #include <stddef.h> | ||
| 31 | |||
| 32 | #include <csp/dmacHw.h> | ||
| 33 | #include <mach/csp/dmacHw_reg.h> | ||
| 34 | #include <mach/csp/dmacHw_priv.h> | ||
| 35 | #include <mach/csp/chipcHw_inline.h> | ||
| 36 | |||
| 37 | /* ---- External Function Prototypes ------------------------------------- */ | ||
| 38 | |||
| 39 | /* Allocate DMA control blocks */ | ||
| 40 | dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; | ||
| 41 | |||
| 42 | uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2; | ||
| 43 | uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2; | ||
| 44 | |||
| 45 | /****************************************************************************/ | ||
| 46 | /** | ||
| 47 | * @brief Get maximum FIFO for a DMA channel | ||
| 48 | * | ||
| 49 | * @return Maximum allowable FIFO size | ||
| 50 | * | ||
| 51 | * | ||
| 52 | */ | ||
| 53 | /****************************************************************************/ | ||
| 54 | static uint32_t GetFifoSize(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 55 | ) { | ||
| 56 | uint32_t val = 0; | ||
| 57 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 58 | dmacHw_MISC_t *pMiscReg = | ||
| 59 | (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module); | ||
| 60 | |||
| 61 | switch (pCblk->channel) { | ||
| 62 | case 0: | ||
| 63 | val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28; | ||
| 64 | break; | ||
| 65 | case 1: | ||
| 66 | val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28; | ||
| 67 | break; | ||
| 68 | case 2: | ||
| 69 | val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28; | ||
| 70 | break; | ||
| 71 | case 3: | ||
| 72 | val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28; | ||
| 73 | break; | ||
| 74 | case 4: | ||
| 75 | val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28; | ||
| 76 | break; | ||
| 77 | case 5: | ||
| 78 | val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28; | ||
| 79 | break; | ||
| 80 | case 6: | ||
| 81 | val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28; | ||
| 82 | break; | ||
| 83 | case 7: | ||
| 84 | val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28; | ||
| 85 | break; | ||
| 86 | } | ||
| 87 | |||
| 88 | if (val <= 0x4) { | ||
| 89 | return 8 << val; | ||
| 90 | } else { | ||
| 91 | dmacHw_ASSERT(0); | ||
| 92 | } | ||
| 93 | return 0; | ||
| 94 | } | ||
| 95 | |||
| 96 | /****************************************************************************/ | ||
| 97 | /** | ||
| 98 | * @brief Program channel register to initiate transfer | ||
| 99 | * | ||
| 100 | * @return void | ||
| 101 | * | ||
| 102 | * | ||
| 103 | * @note | ||
| 104 | * - Descriptor buffer MUST ALWAYS be flushed before calling this function | ||
| 105 | * - This function should also be called from ISR to program the channel with | ||
| 106 | * pending descriptors | ||
| 107 | */ | ||
| 108 | /****************************************************************************/ | ||
| 109 | void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 110 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 111 | void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 112 | ) { | ||
| 113 | dmacHw_DESC_RING_t *pRing; | ||
| 114 | dmacHw_DESC_t *pProg; | ||
| 115 | dmacHw_CBLK_t *pCblk; | ||
| 116 | |||
| 117 | pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 118 | pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 119 | |||
| 120 | if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) { | ||
| 121 | /* Not safe yet to program the channel */ | ||
| 122 | return; | ||
| 123 | } | ||
| 124 | |||
| 125 | if (pCblk->varDataStarted) { | ||
| 126 | if (pCblk->descUpdated) { | ||
| 127 | pCblk->descUpdated = 0; | ||
| 128 | pProg = | ||
| 129 | (dmacHw_DESC_t *) ((uint32_t) | ||
| 130 | dmacHw_REG_LLP(pCblk->module, | ||
| 131 | pCblk->channel) + | ||
| 132 | pRing->virt2PhyOffset); | ||
| 133 | |||
| 134 | /* Load descriptor if not loaded */ | ||
| 135 | if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) { | ||
| 136 | dmacHw_SET_SAR(pCblk->module, pCblk->channel, | ||
| 137 | pProg->sar); | ||
| 138 | dmacHw_SET_DAR(pCblk->module, pCblk->channel, | ||
| 139 | pProg->dar); | ||
| 140 | dmacHw_REG_CTL_LO(pCblk->module, | ||
| 141 | pCblk->channel) = | ||
| 142 | pProg->ctl.lo; | ||
| 143 | dmacHw_REG_CTL_HI(pCblk->module, | ||
| 144 | pCblk->channel) = | ||
| 145 | pProg->ctl.hi; | ||
| 146 | } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) { | ||
| 147 | /* Return as end descriptor is processed */ | ||
| 148 | return; | ||
| 149 | } else { | ||
| 150 | dmacHw_ASSERT(0); | ||
| 151 | } | ||
| 152 | } else { | ||
| 153 | return; | ||
| 154 | } | ||
| 155 | } else { | ||
| 156 | if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) { | ||
| 157 | /* Do not make a single chain, rather process one descriptor at a time */ | ||
| 158 | pProg = pRing->pHead; | ||
| 159 | /* Point to the next descriptor for next iteration */ | ||
| 160 | dmacHw_NEXT_DESC(pRing, pHead); | ||
| 161 | } else { | ||
| 162 | /* Return if no more pending descriptor */ | ||
| 163 | if (pRing->pEnd == NULL) { | ||
| 164 | return; | ||
| 165 | } | ||
| 166 | |||
| 167 | pProg = pRing->pProg; | ||
| 168 | if (pConfig->transferMode == | ||
| 169 | dmacHw_TRANSFER_MODE_CONTINUOUS) { | ||
| 170 | /* Make sure a complete ring can be formed */ | ||
| 171 | dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd-> | ||
| 172 | llp == pRing->pProg); | ||
| 173 | /* Make sure pProg pointing to the pHead */ | ||
| 174 | dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg == | ||
| 175 | pRing->pHead); | ||
| 176 | /* Make a complete ring */ | ||
| 177 | do { | ||
| 178 | pRing->pProg->ctl.lo |= | ||
| 179 | (dmacHw_REG_CTL_LLP_DST_EN | | ||
| 180 | dmacHw_REG_CTL_LLP_SRC_EN); | ||
| 181 | pRing->pProg = | ||
| 182 | (dmacHw_DESC_t *) pRing->pProg->llp; | ||
| 183 | } while (pRing->pProg != pRing->pHead); | ||
| 184 | } else { | ||
| 185 | /* Make a single long chain */ | ||
| 186 | while (pRing->pProg != pRing->pEnd) { | ||
| 187 | pRing->pProg->ctl.lo |= | ||
| 188 | (dmacHw_REG_CTL_LLP_DST_EN | | ||
| 189 | dmacHw_REG_CTL_LLP_SRC_EN); | ||
| 190 | pRing->pProg = | ||
| 191 | (dmacHw_DESC_t *) pRing->pProg->llp; | ||
| 192 | } | ||
| 193 | } | ||
| 194 | } | ||
| 195 | |||
| 196 | /* Program the channel registers */ | ||
| 197 | dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar); | ||
| 198 | dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar); | ||
| 199 | dmacHw_SET_LLP(pCblk->module, pCblk->channel, | ||
| 200 | (uint32_t) pProg - pRing->virt2PhyOffset); | ||
| 201 | dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) = | ||
| 202 | pProg->ctl.lo; | ||
| 203 | dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) = | ||
| 204 | pProg->ctl.hi; | ||
| 205 | if (pRing->pEnd) { | ||
| 206 | /* Remember the descriptor to use next */ | ||
| 207 | pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp; | ||
| 208 | } | ||
| 209 | /* Indicate no more pending descriptor */ | ||
| 210 | pRing->pEnd = (dmacHw_DESC_t *) NULL; | ||
| 211 | } | ||
| 212 | /* Start DMA operation */ | ||
| 213 | dmacHw_DMA_START(pCblk->module, pCblk->channel); | ||
| 214 | } | ||
| 215 | |||
| 216 | /****************************************************************************/ | ||
| 217 | /** | ||
| 218 | * @brief Initializes DMA | ||
| 219 | * | ||
| 220 | * This function initializes DMA CSP driver | ||
| 221 | * | ||
| 222 | * @note | ||
| 223 | * Must be called before using any DMA channel | ||
| 224 | */ | ||
| 225 | /****************************************************************************/ | ||
| 226 | void dmacHw_initDma(void) | ||
| 227 | { | ||
| 228 | |||
| 229 | uint32_t i = 0; | ||
| 230 | |||
| 231 | dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0); | ||
| 232 | dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1); | ||
| 233 | |||
| 234 | /* Enable access to the DMA block */ | ||
| 235 | chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0); | ||
| 236 | chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1); | ||
| 237 | |||
| 238 | if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) { | ||
| 239 | dmacHw_ASSERT(0); | ||
| 240 | } | ||
| 241 | |||
| 242 | memset((void *)dmacHw_gCblk, 0, | ||
| 243 | sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1)); | ||
| 244 | for (i = 0; i < dmaChannelCount_0; i++) { | ||
| 245 | dmacHw_gCblk[i].module = 0; | ||
| 246 | dmacHw_gCblk[i].channel = i; | ||
| 247 | } | ||
| 248 | for (i = 0; i < dmaChannelCount_1; i++) { | ||
| 249 | dmacHw_gCblk[i + dmaChannelCount_0].module = 1; | ||
| 250 | dmacHw_gCblk[i + dmaChannelCount_0].channel = i; | ||
| 251 | } | ||
| 252 | } | ||
| 253 | |||
| 254 | /****************************************************************************/ | ||
| 255 | /** | ||
| 256 | * @brief Exit function for DMA | ||
| 257 | * | ||
| 258 | * This function isolates DMA from the system | ||
| 259 | * | ||
| 260 | */ | ||
| 261 | /****************************************************************************/ | ||
| 262 | void dmacHw_exitDma(void) | ||
| 263 | { | ||
| 264 | /* Disable access to the DMA block */ | ||
| 265 | chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0); | ||
| 266 | chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1); | ||
| 267 | } | ||
| 268 | |||
| 269 | /****************************************************************************/ | ||
| 270 | /** | ||
| 271 | * @brief Gets a handle to a DMA channel | ||
| 272 | * | ||
| 273 | * This function returns a handle, representing a control block of a particular DMA channel | ||
| 274 | * | ||
| 275 | * @return -1 - On Failure | ||
| 276 | * handle - On Success, representing a channel control block | ||
| 277 | * | ||
| 278 | * @note | ||
| 279 | * None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro | ||
| 280 | */ | ||
| 281 | /****************************************************************************/ | ||
| 282 | dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ | ||
| 283 | ) { | ||
| 284 | int idx; | ||
| 285 | |||
| 286 | switch ((channelId >> 8)) { | ||
| 287 | case 0: | ||
| 288 | dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0); | ||
| 289 | idx = (channelId & 0xff); | ||
| 290 | break; | ||
| 291 | case 1: | ||
| 292 | dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1); | ||
| 293 | idx = dmaChannelCount_0 + (channelId & 0xff); | ||
| 294 | break; | ||
| 295 | default: | ||
| 296 | dmacHw_ASSERT(0); | ||
| 297 | return (dmacHw_HANDLE_t) -1; | ||
| 298 | } | ||
| 299 | |||
| 300 | return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]); | ||
| 301 | } | ||
| 302 | |||
| 303 | /****************************************************************************/ | ||
| 304 | /** | ||
| 305 | * @brief Initializes a DMA channel for use | ||
| 306 | * | ||
| 307 | * This function initializes and resets a DMA channel for use | ||
| 308 | * | ||
| 309 | * @return -1 - On Failure | ||
| 310 | * 0 - On Success | ||
| 311 | * | ||
| 312 | * @note | ||
| 313 | * None | ||
| 314 | */ | ||
| 315 | /****************************************************************************/ | ||
| 316 | int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 317 | ) { | ||
| 318 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 319 | int module = pCblk->module; | ||
| 320 | int channel = pCblk->channel; | ||
| 321 | |||
| 322 | /* Reinitialize the control block */ | ||
| 323 | memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t)); | ||
| 324 | pCblk->module = module; | ||
| 325 | pCblk->channel = channel; | ||
| 326 | |||
| 327 | /* Enable DMA controller */ | ||
| 328 | dmacHw_DMA_ENABLE(pCblk->module); | ||
| 329 | /* Reset DMA channel */ | ||
| 330 | dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel); | ||
| 331 | dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel); | ||
| 332 | dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel); | ||
| 333 | dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel); | ||
| 334 | |||
| 335 | /* Clear all raw interrupt status */ | ||
| 336 | dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 337 | dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 338 | dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 339 | |||
| 340 | /* Mask event specific interrupts */ | ||
| 341 | dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 342 | dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 343 | dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 344 | dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 345 | dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 346 | |||
| 347 | return 0; | ||
| 348 | } | ||
| 349 | |||
| 350 | /****************************************************************************/ | ||
| 351 | /** | ||
| 352 | * @brief Finds amount of memory required to form a descriptor ring | ||
| 353 | * | ||
| 354 | * | ||
| 355 | * @return Number of bytes required to form a descriptor ring | ||
| 356 | * | ||
| 357 | * | ||
| 358 | */ | ||
| 359 | /****************************************************************************/ | ||
| 360 | uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ | ||
| 361 | ) { | ||
| 362 | /* Need extra 4 byte to ensure 32 bit alignment */ | ||
| 363 | return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) + | ||
| 364 | sizeof(uint32_t); | ||
| 365 | } | ||
| 366 | |||
| 367 | /****************************************************************************/ | ||
| 368 | /** | ||
| 369 | * @brief Initializes descriptor ring | ||
| 370 | * | ||
| 371 | * This function will initializes the descriptor ring of a DMA channel | ||
| 372 | * | ||
| 373 | * | ||
| 374 | * @return -1 - On failure | ||
| 375 | * 0 - On success | ||
| 376 | * @note | ||
| 377 | * - "len" parameter should be obtained from "dmacHw_descriptorLen" | ||
| 378 | * - Descriptor buffer MUST be 32 bit aligned and uncached as it is | ||
| 379 | * accessed by ARM and DMA | ||
| 380 | */ | ||
| 381 | /****************************************************************************/ | ||
| 382 | int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ | ||
| 383 | uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ | ||
| 384 | uint32_t len, /* [ IN ] Size of the pBuf */ | ||
| 385 | uint32_t num /* [ IN ] Number of descriptor in the ring */ | ||
| 386 | ) { | ||
| 387 | uint32_t i; | ||
| 388 | dmacHw_DESC_RING_t *pRing; | ||
| 389 | dmacHw_DESC_t *pDesc; | ||
| 390 | |||
| 391 | /* Check the alignment of the descriptor */ | ||
| 392 | if ((uint32_t) pDescriptorVirt & 0x00000003) { | ||
| 393 | dmacHw_ASSERT(0); | ||
| 394 | return -1; | ||
| 395 | } | ||
| 396 | |||
| 397 | /* Check if enough space has been allocated for descriptor ring */ | ||
| 398 | if (len < dmacHw_descriptorLen(num)) { | ||
| 399 | return -1; | ||
| 400 | } | ||
| 401 | |||
| 402 | pRing = dmacHw_GET_DESC_RING(pDescriptorVirt); | ||
| 403 | pRing->pHead = | ||
| 404 | (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t)); | ||
| 405 | pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead; | ||
| 406 | pRing->pProg = dmacHw_DESC_INIT; | ||
| 407 | /* Initialize link item chain, starting from the head */ | ||
| 408 | pDesc = pRing->pHead; | ||
| 409 | /* Find the offset between virtual to physical address */ | ||
| 410 | pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr; | ||
| 411 | |||
| 412 | /* Form the descriptor ring */ | ||
| 413 | for (i = 0; i < num - 1; i++) { | ||
| 414 | /* Clear link list item */ | ||
| 415 | memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t)); | ||
| 416 | /* Point to the next item in the physical address */ | ||
| 417 | pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset; | ||
| 418 | /* Point to the next item in the virtual address */ | ||
| 419 | pDesc->llp = (uint32_t) (pDesc + 1); | ||
| 420 | /* Mark descriptor is ready to use */ | ||
| 421 | pDesc->ctl.hi = dmacHw_DESC_FREE; | ||
| 422 | /* Look into next link list item */ | ||
| 423 | pDesc++; | ||
| 424 | } | ||
| 425 | |||
| 426 | /* Clear last link list item */ | ||
| 427 | memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t)); | ||
| 428 | /* Last item pointing to the first item in the | ||
| 429 | physical address to complete the ring */ | ||
| 430 | pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset; | ||
| 431 | /* Last item pointing to the first item in the | ||
| 432 | virtual address to complete the ring | ||
| 433 | */ | ||
| 434 | pDesc->llp = (uint32_t) pRing->pHead; | ||
| 435 | /* Mark descriptor is ready to use */ | ||
| 436 | pDesc->ctl.hi = dmacHw_DESC_FREE; | ||
| 437 | /* Set the number of descriptors in the ring */ | ||
| 438 | pRing->num = num; | ||
| 439 | return 0; | ||
| 440 | } | ||
| 441 | |||
| 442 | /****************************************************************************/ | ||
| 443 | /** | ||
| 444 | * @brief Configure DMA channel | ||
| 445 | * | ||
| 446 | * @return 0 : On success | ||
| 447 | * -1 : On failure | ||
| 448 | */ | ||
| 449 | /****************************************************************************/ | ||
| 450 | int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 451 | dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ | ||
| 452 | ) { | ||
| 453 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 454 | uint32_t cfgHigh = 0; | ||
| 455 | int srcTrSize; | ||
| 456 | int dstTrSize; | ||
| 457 | |||
| 458 | pCblk->varDataStarted = 0; | ||
| 459 | pCblk->userData = NULL; | ||
| 460 | |||
| 461 | /* Configure | ||
| 462 | - Burst transaction when enough data in available in FIFO | ||
| 463 | - AHB Access protection 1 | ||
| 464 | - Source and destination peripheral ports | ||
| 465 | */ | ||
| 466 | cfgHigh = | ||
| 467 | dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 | | ||
| 468 | dmacHw_SRC_PERI_INTF(pConfig-> | ||
| 469 | srcPeripheralPort) | | ||
| 470 | dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort); | ||
| 471 | /* Set priority */ | ||
| 472 | dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel, | ||
| 473 | pConfig->channelPriority); | ||
| 474 | |||
| 475 | if (pConfig->dstStatusRegisterAddress != 0) { | ||
| 476 | /* Destination status update enable */ | ||
| 477 | cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT; | ||
| 478 | /* Configure status registers */ | ||
| 479 | dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel, | ||
| 480 | pConfig->dstStatusRegisterAddress); | ||
| 481 | } | ||
| 482 | |||
| 483 | if (pConfig->srcStatusRegisterAddress != 0) { | ||
| 484 | /* Source status update enable */ | ||
| 485 | cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT; | ||
| 486 | /* Source status update enable */ | ||
| 487 | dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel, | ||
| 488 | pConfig->srcStatusRegisterAddress); | ||
| 489 | } | ||
| 490 | /* Configure the config high register */ | ||
| 491 | dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh; | ||
| 492 | |||
| 493 | /* Clear all raw interrupt status */ | ||
| 494 | dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 495 | dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 496 | dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 497 | |||
| 498 | /* Configure block interrupt */ | ||
| 499 | if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) { | ||
| 500 | dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel); | ||
| 501 | } else { | ||
| 502 | dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 503 | } | ||
| 504 | /* Configure complete transfer interrupt */ | ||
| 505 | if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) { | ||
| 506 | dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel); | ||
| 507 | } else { | ||
| 508 | dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 509 | } | ||
| 510 | /* Configure error interrupt */ | ||
| 511 | if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) { | ||
| 512 | dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel); | ||
| 513 | } else { | ||
| 514 | dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel); | ||
| 515 | } | ||
| 516 | /* Configure gather register */ | ||
| 517 | if (pConfig->srcGatherWidth) { | ||
| 518 | srcTrSize = | ||
| 519 | dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); | ||
| 520 | if (! | ||
| 521 | ((pConfig->srcGatherWidth % srcTrSize) | ||
| 522 | && (pConfig->srcGatherJump % srcTrSize))) { | ||
| 523 | dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) = | ||
| 524 | ((pConfig->srcGatherWidth / | ||
| 525 | srcTrSize) << 20) | (pConfig->srcGatherJump / | ||
| 526 | srcTrSize); | ||
| 527 | } else { | ||
| 528 | return -1; | ||
| 529 | } | ||
| 530 | } | ||
| 531 | /* Configure scatter register */ | ||
| 532 | if (pConfig->dstScatterWidth) { | ||
| 533 | dstTrSize = | ||
| 534 | dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); | ||
| 535 | if (! | ||
| 536 | ((pConfig->dstScatterWidth % dstTrSize) | ||
| 537 | && (pConfig->dstScatterJump % dstTrSize))) { | ||
| 538 | dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) = | ||
| 539 | ((pConfig->dstScatterWidth / | ||
| 540 | dstTrSize) << 20) | (pConfig->dstScatterJump / | ||
| 541 | dstTrSize); | ||
| 542 | } else { | ||
| 543 | return -1; | ||
| 544 | } | ||
| 545 | } | ||
| 546 | return 0; | ||
| 547 | } | ||
| 548 | |||
| 549 | /****************************************************************************/ | ||
| 550 | /** | ||
| 551 | * @brief Indicates whether DMA transfer is in progress or completed | ||
| 552 | * | ||
| 553 | * @return DMA transfer status | ||
| 554 | * dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing | ||
| 555 | * dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed | ||
| 556 | * dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error | ||
| 557 | * | ||
| 558 | */ | ||
| 559 | /****************************************************************************/ | ||
| 560 | dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 561 | ) { | ||
| 562 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 563 | |||
| 564 | if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) { | ||
| 565 | return dmacHw_TRANSFER_STATUS_BUSY; | ||
| 566 | } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) & | ||
| 567 | (0x00000001 << pCblk->channel)) { | ||
| 568 | return dmacHw_TRANSFER_STATUS_ERROR; | ||
| 569 | } | ||
| 570 | |||
| 571 | return dmacHw_TRANSFER_STATUS_DONE; | ||
| 572 | } | ||
| 573 | |||
| 574 | /****************************************************************************/ | ||
| 575 | /** | ||
| 576 | * @brief Set descriptors for known data length | ||
| 577 | * | ||
| 578 | * When DMA has to work as a flow controller, this function prepares the | ||
| 579 | * descriptor chain to transfer data | ||
| 580 | * | ||
| 581 | * from: | ||
| 582 | * - Memory to memory | ||
| 583 | * - Peripheral to memory | ||
| 584 | * - Memory to Peripheral | ||
| 585 | * - Peripheral to Peripheral | ||
| 586 | * | ||
| 587 | * @return -1 - On failure | ||
| 588 | * 0 - On success | ||
| 589 | * | ||
| 590 | */ | ||
| 591 | /****************************************************************************/ | ||
| 592 | int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 593 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 594 | void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ | ||
| 595 | void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ | ||
| 596 | size_t dataLen /* [ IN ] Data length in bytes */ | ||
| 597 | ) { | ||
| 598 | dmacHw_TRANSACTION_WIDTH_e dstTrWidth; | ||
| 599 | dmacHw_TRANSACTION_WIDTH_e srcTrWidth; | ||
| 600 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 601 | dmacHw_DESC_t *pStart; | ||
| 602 | dmacHw_DESC_t *pProg; | ||
| 603 | int srcTs = 0; | ||
| 604 | int blkTs = 0; | ||
| 605 | int oddSize = 0; | ||
| 606 | int descCount = 0; | ||
| 607 | int count = 0; | ||
| 608 | int dstTrSize = 0; | ||
| 609 | int srcTrSize = 0; | ||
| 610 | uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE; | ||
| 611 | |||
| 612 | dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); | ||
| 613 | srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); | ||
| 614 | |||
| 615 | /* Skip Tx if buffer is NULL or length is unknown */ | ||
| 616 | if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) { | ||
| 617 | /* Do not initiate transfer */ | ||
| 618 | return -1; | ||
| 619 | } | ||
| 620 | |||
| 621 | /* Ensure scatter and gather are transaction aligned */ | ||
| 622 | if ((pConfig->srcGatherWidth % srcTrSize) | ||
| 623 | || (pConfig->dstScatterWidth % dstTrSize)) { | ||
| 624 | return -2; | ||
| 625 | } | ||
| 626 | |||
| 627 | /* | ||
| 628 | Background 1: DMAC can not perform DMA if source and destination addresses are | ||
| 629 | not properly aligned with the channel's transaction width. So, for successful | ||
| 630 | DMA transfer, transaction width must be set according to the alignment of the | ||
| 631 | source and destination address. | ||
| 632 | */ | ||
| 633 | |||
| 634 | /* Adjust destination transaction width if destination address is not aligned properly */ | ||
| 635 | dstTrWidth = pConfig->dstMaxTransactionWidth; | ||
| 636 | while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) { | ||
| 637 | dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth); | ||
| 638 | dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth); | ||
| 639 | } | ||
| 640 | |||
| 641 | /* Adjust source transaction width if source address is not aligned properly */ | ||
| 642 | srcTrWidth = pConfig->srcMaxTransactionWidth; | ||
| 643 | while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) { | ||
| 644 | srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth); | ||
| 645 | srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth); | ||
| 646 | } | ||
| 647 | |||
| 648 | /* Find the maximum transaction per descriptor */ | ||
| 649 | if (pConfig->maxDataPerBlock | ||
| 650 | && ((pConfig->maxDataPerBlock / srcTrSize) < | ||
| 651 | dmacHw_MAX_BLOCKSIZE)) { | ||
| 652 | maxBlockSize = pConfig->maxDataPerBlock / srcTrSize; | ||
| 653 | } | ||
| 654 | |||
| 655 | /* Find number of source transactions needed to complete the DMA transfer */ | ||
| 656 | srcTs = dataLen / srcTrSize; | ||
| 657 | /* Find the odd number of bytes that need to be transferred as single byte transaction width */ | ||
| 658 | if (srcTs && (dstTrSize > srcTrSize)) { | ||
| 659 | oddSize = dataLen % dstTrSize; | ||
| 660 | /* Adjust source transaction count due to "oddSize" */ | ||
| 661 | srcTs = srcTs - (oddSize / srcTrSize); | ||
| 662 | } else { | ||
| 663 | oddSize = dataLen % srcTrSize; | ||
| 664 | } | ||
| 665 | /* Adjust "descCount" due to "oddSize" */ | ||
| 666 | if (oddSize) { | ||
| 667 | descCount++; | ||
| 668 | } | ||
| 669 | /* Find the number of descriptor needed for total "srcTs" */ | ||
| 670 | if (srcTs) { | ||
| 671 | descCount += ((srcTs - 1) / maxBlockSize) + 1; | ||
| 672 | } | ||
| 673 | |||
| 674 | /* Check the availability of "descCount" discriptors in the ring */ | ||
| 675 | pProg = pRing->pHead; | ||
| 676 | for (count = 0; (descCount <= pRing->num) && (count < descCount); | ||
| 677 | count++) { | ||
| 678 | if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) { | ||
| 679 | /* Sufficient descriptors are not available */ | ||
| 680 | return -3; | ||
| 681 | } | ||
| 682 | pProg = (dmacHw_DESC_t *) pProg->llp; | ||
| 683 | } | ||
| 684 | |||
| 685 | /* Remember the link list item to program the channel registers */ | ||
| 686 | pStart = pProg = pRing->pHead; | ||
| 687 | /* Make a link list with "descCount(=count)" number of descriptors */ | ||
| 688 | while (count) { | ||
| 689 | /* Reset channel control information */ | ||
| 690 | pProg->ctl.lo = 0; | ||
| 691 | /* Enable source gather if configured */ | ||
| 692 | if (pConfig->srcGatherWidth) { | ||
| 693 | pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE; | ||
| 694 | } | ||
| 695 | /* Enable destination scatter if configured */ | ||
| 696 | if (pConfig->dstScatterWidth) { | ||
| 697 | pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE; | ||
| 698 | } | ||
| 699 | /* Set source and destination address */ | ||
| 700 | pProg->sar = (uint32_t) pSrcAddr; | ||
| 701 | pProg->dar = (uint32_t) pDstAddr; | ||
| 702 | /* Use "devCtl" to mark that user memory need to be freed later if needed */ | ||
| 703 | if (pProg == pRing->pHead) { | ||
| 704 | pProg->devCtl = dmacHw_FREE_USER_MEMORY; | ||
| 705 | } else { | ||
| 706 | pProg->devCtl = 0; | ||
| 707 | } | ||
| 708 | |||
| 709 | blkTs = srcTs; | ||
| 710 | |||
| 711 | /* Special treatmeant for last descriptor */ | ||
| 712 | if (count == 1) { | ||
| 713 | /* Mark the last descriptor */ | ||
| 714 | pProg->ctl.lo &= | ||
| 715 | ~(dmacHw_REG_CTL_LLP_DST_EN | | ||
| 716 | dmacHw_REG_CTL_LLP_SRC_EN); | ||
| 717 | /* Treatment for odd data bytes */ | ||
| 718 | if (oddSize) { | ||
| 719 | /* Adjust for single byte transaction width */ | ||
| 720 | switch (pConfig->transferType) { | ||
| 721 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: | ||
| 722 | dstTrWidth = | ||
| 723 | dmacHw_DST_TRANSACTION_WIDTH_8; | ||
| 724 | blkTs = | ||
| 725 | (oddSize / srcTrSize) + | ||
| 726 | ((oddSize % srcTrSize) ? 1 : 0); | ||
| 727 | break; | ||
| 728 | case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: | ||
| 729 | srcTrWidth = | ||
| 730 | dmacHw_SRC_TRANSACTION_WIDTH_8; | ||
| 731 | blkTs = oddSize; | ||
| 732 | break; | ||
| 733 | case dmacHw_TRANSFER_TYPE_MEM_TO_MEM: | ||
| 734 | srcTrWidth = | ||
| 735 | dmacHw_SRC_TRANSACTION_WIDTH_8; | ||
| 736 | dstTrWidth = | ||
| 737 | dmacHw_DST_TRANSACTION_WIDTH_8; | ||
| 738 | blkTs = oddSize; | ||
| 739 | break; | ||
| 740 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL: | ||
| 741 | /* Do not adjust the transaction width */ | ||
| 742 | break; | ||
| 743 | } | ||
| 744 | } else { | ||
| 745 | srcTs -= blkTs; | ||
| 746 | } | ||
| 747 | } else { | ||
| 748 | if (srcTs / maxBlockSize) { | ||
| 749 | blkTs = maxBlockSize; | ||
| 750 | } | ||
| 751 | /* Remaining source transactions for next iteration */ | ||
| 752 | srcTs -= blkTs; | ||
| 753 | } | ||
| 754 | /* Must have a valid source transactions */ | ||
| 755 | dmacHw_ASSERT(blkTs > 0); | ||
| 756 | /* Set control information */ | ||
| 757 | if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) { | ||
| 758 | pProg->ctl.lo |= pConfig->transferType | | ||
| 759 | pConfig->srcUpdate | | ||
| 760 | pConfig->dstUpdate | | ||
| 761 | srcTrWidth | | ||
| 762 | dstTrWidth | | ||
| 763 | pConfig->srcMaxBurstWidth | | ||
| 764 | pConfig->dstMaxBurstWidth | | ||
| 765 | pConfig->srcMasterInterface | | ||
| 766 | pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; | ||
| 767 | } else { | ||
| 768 | uint32_t transferType = 0; | ||
| 769 | switch (pConfig->transferType) { | ||
| 770 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: | ||
| 771 | transferType = dmacHw_REG_CTL_TTFC_PM_PERI; | ||
| 772 | break; | ||
| 773 | case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: | ||
| 774 | transferType = dmacHw_REG_CTL_TTFC_MP_PERI; | ||
| 775 | break; | ||
| 776 | default: | ||
| 777 | dmacHw_ASSERT(0); | ||
| 778 | } | ||
| 779 | pProg->ctl.lo |= transferType | | ||
| 780 | pConfig->srcUpdate | | ||
| 781 | pConfig->dstUpdate | | ||
| 782 | srcTrWidth | | ||
| 783 | dstTrWidth | | ||
| 784 | pConfig->srcMaxBurstWidth | | ||
| 785 | pConfig->dstMaxBurstWidth | | ||
| 786 | pConfig->srcMasterInterface | | ||
| 787 | pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; | ||
| 788 | } | ||
| 789 | |||
| 790 | /* Set block transaction size */ | ||
| 791 | pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK; | ||
| 792 | /* Look for next descriptor */ | ||
| 793 | if (count > 1) { | ||
| 794 | /* Point to the next descriptor */ | ||
| 795 | pProg = (dmacHw_DESC_t *) pProg->llp; | ||
| 796 | |||
| 797 | /* Update source and destination address for next iteration */ | ||
| 798 | switch (pConfig->transferType) { | ||
| 799 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: | ||
| 800 | if (pConfig->dstScatterWidth) { | ||
| 801 | pDstAddr = | ||
| 802 | (char *)pDstAddr + | ||
| 803 | blkTs * srcTrSize + | ||
| 804 | (((blkTs * srcTrSize) / | ||
| 805 | pConfig->dstScatterWidth) * | ||
| 806 | pConfig->dstScatterJump); | ||
| 807 | } else { | ||
| 808 | pDstAddr = | ||
| 809 | (char *)pDstAddr + | ||
| 810 | blkTs * srcTrSize; | ||
| 811 | } | ||
| 812 | break; | ||
| 813 | case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: | ||
| 814 | if (pConfig->srcGatherWidth) { | ||
| 815 | pSrcAddr = | ||
| 816 | (char *)pDstAddr + | ||
| 817 | blkTs * srcTrSize + | ||
| 818 | (((blkTs * srcTrSize) / | ||
| 819 | pConfig->srcGatherWidth) * | ||
| 820 | pConfig->srcGatherJump); | ||
| 821 | } else { | ||
| 822 | pSrcAddr = | ||
| 823 | (char *)pSrcAddr + | ||
| 824 | blkTs * srcTrSize; | ||
| 825 | } | ||
| 826 | break; | ||
| 827 | case dmacHw_TRANSFER_TYPE_MEM_TO_MEM: | ||
| 828 | if (pConfig->dstScatterWidth) { | ||
| 829 | pDstAddr = | ||
| 830 | (char *)pDstAddr + | ||
| 831 | blkTs * srcTrSize + | ||
| 832 | (((blkTs * srcTrSize) / | ||
| 833 | pConfig->dstScatterWidth) * | ||
| 834 | pConfig->dstScatterJump); | ||
| 835 | } else { | ||
| 836 | pDstAddr = | ||
| 837 | (char *)pDstAddr + | ||
| 838 | blkTs * srcTrSize; | ||
| 839 | } | ||
| 840 | |||
| 841 | if (pConfig->srcGatherWidth) { | ||
| 842 | pSrcAddr = | ||
| 843 | (char *)pDstAddr + | ||
| 844 | blkTs * srcTrSize + | ||
| 845 | (((blkTs * srcTrSize) / | ||
| 846 | pConfig->srcGatherWidth) * | ||
| 847 | pConfig->srcGatherJump); | ||
| 848 | } else { | ||
| 849 | pSrcAddr = | ||
| 850 | (char *)pSrcAddr + | ||
| 851 | blkTs * srcTrSize; | ||
| 852 | } | ||
| 853 | break; | ||
| 854 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL: | ||
| 855 | /* Do not adjust the address */ | ||
| 856 | break; | ||
| 857 | default: | ||
| 858 | dmacHw_ASSERT(0); | ||
| 859 | } | ||
| 860 | } else { | ||
| 861 | /* At the end of transfer "srcTs" must be zero */ | ||
| 862 | dmacHw_ASSERT(srcTs == 0); | ||
| 863 | } | ||
| 864 | count--; | ||
| 865 | } | ||
| 866 | |||
| 867 | /* Remember the descriptor to initialize the registers */ | ||
| 868 | if (pRing->pProg == dmacHw_DESC_INIT) { | ||
| 869 | pRing->pProg = pStart; | ||
| 870 | } | ||
| 871 | /* Indicate that the descriptor is updated */ | ||
| 872 | pRing->pEnd = pProg; | ||
| 873 | /* Head pointing to the next descriptor */ | ||
| 874 | pRing->pHead = (dmacHw_DESC_t *) pProg->llp; | ||
| 875 | /* Update Tail pointer if destination is a peripheral, | ||
| 876 | because no one is going to read from the pTail | ||
| 877 | */ | ||
| 878 | if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) { | ||
| 879 | pRing->pTail = pRing->pHead; | ||
| 880 | } | ||
| 881 | return 0; | ||
| 882 | } | ||
| 883 | |||
| 884 | /****************************************************************************/ | ||
| 885 | /** | ||
| 886 | * @brief Provides DMA controller attributes | ||
| 887 | * | ||
| 888 | * | ||
| 889 | * @return DMA controller attributes | ||
| 890 | * | ||
| 891 | * @note | ||
| 892 | * None | ||
| 893 | */ | ||
| 894 | /****************************************************************************/ | ||
| 895 | uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 896 | dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */ | ||
| 897 | ) { | ||
| 898 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 899 | |||
| 900 | switch (attr) { | ||
| 901 | case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM: | ||
| 902 | return dmacHw_GET_NUM_CHANNEL(pCblk->module); | ||
| 903 | case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE: | ||
| 904 | return (1 << | ||
| 905 | (dmacHw_GET_MAX_BLOCK_SIZE | ||
| 906 | (pCblk->module, pCblk->module) + 2)) - 8; | ||
| 907 | case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM: | ||
| 908 | return dmacHw_GET_NUM_INTERFACE(pCblk->module); | ||
| 909 | case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH: | ||
| 910 | return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module, | ||
| 911 | pCblk->channel); | ||
| 912 | case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE: | ||
| 913 | return GetFifoSize(handle); | ||
| 914 | } | ||
| 915 | dmacHw_ASSERT(0); | ||
| 916 | return 0; | ||
| 917 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c new file mode 100644 index 000000000000..ff7b436d0935 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c | |||
| @@ -0,0 +1,1017 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dmacHw_extra.c | ||
| 18 | * | ||
| 19 | * @brief Extra Low level DMA controller driver routines | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * | ||
| 23 | * These routines provide basic DMA functionality only. | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 28 | |||
| 29 | #include <csp/stdint.h> | ||
| 30 | #include <stddef.h> | ||
| 31 | |||
| 32 | #include <csp/dmacHw.h> | ||
| 33 | #include <mach/csp/dmacHw_reg.h> | ||
| 34 | #include <mach/csp/dmacHw_priv.h> | ||
| 35 | |||
| 36 | extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT]; /* Declared in dmacHw.c */ | ||
| 37 | |||
| 38 | /* ---- External Function Prototypes ------------------------------------- */ | ||
| 39 | |||
| 40 | /* ---- Internal Use Function Prototypes --------------------------------- */ | ||
| 41 | /****************************************************************************/ | ||
| 42 | /** | ||
| 43 | * @brief Overwrites data length in the descriptor | ||
| 44 | * | ||
| 45 | * This function overwrites data length in the descriptor | ||
| 46 | * | ||
| 47 | * | ||
| 48 | * @return void | ||
| 49 | * | ||
| 50 | * @note | ||
| 51 | * This is only used for PCM channel | ||
| 52 | */ | ||
| 53 | /****************************************************************************/ | ||
| 54 | void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 55 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 56 | size_t dataLen /* [ IN ] Data length in bytes */ | ||
| 57 | ); | ||
| 58 | |||
| 59 | /****************************************************************************/ | ||
| 60 | /** | ||
| 61 | * @brief Helper function to display DMA registers | ||
| 62 | * | ||
| 63 | * @return void | ||
| 64 | * | ||
| 65 | * | ||
| 66 | * @note | ||
| 67 | * None | ||
| 68 | */ | ||
| 69 | /****************************************************************************/ | ||
| 70 | static void DisplayRegisterContents(int module, /* [ IN ] DMA Controller unit (0-1) */ | ||
| 71 | int channel, /* [ IN ] DMA Channel (0-7) / -1(all) */ | ||
| 72 | int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */ | ||
| 73 | ) { | ||
| 74 | int chan; | ||
| 75 | |||
| 76 | (*fpPrint) ("Displaying register content \n\n"); | ||
| 77 | (*fpPrint) ("Module %d: Interrupt raw transfer 0x%X\n", | ||
| 78 | module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module))); | ||
| 79 | (*fpPrint) ("Module %d: Interrupt raw block 0x%X\n", | ||
| 80 | module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module))); | ||
| 81 | (*fpPrint) ("Module %d: Interrupt raw src transfer 0x%X\n", | ||
| 82 | module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module))); | ||
| 83 | (*fpPrint) ("Module %d: Interrupt raw dst transfer 0x%X\n", | ||
| 84 | module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module))); | ||
| 85 | (*fpPrint) ("Module %d: Interrupt raw error 0x%X\n", | ||
| 86 | module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module))); | ||
| 87 | (*fpPrint) ("--------------------------------------------------\n"); | ||
| 88 | (*fpPrint) ("Module %d: Interrupt stat transfer 0x%X\n", | ||
| 89 | module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module))); | ||
| 90 | (*fpPrint) ("Module %d: Interrupt stat block 0x%X\n", | ||
| 91 | module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module))); | ||
| 92 | (*fpPrint) ("Module %d: Interrupt stat src transfer 0x%X\n", | ||
| 93 | module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module))); | ||
| 94 | (*fpPrint) ("Module %d: Interrupt stat dst transfer 0x%X\n", | ||
| 95 | module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module))); | ||
| 96 | (*fpPrint) ("Module %d: Interrupt stat error 0x%X\n", | ||
| 97 | module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module))); | ||
| 98 | (*fpPrint) ("--------------------------------------------------\n"); | ||
| 99 | (*fpPrint) ("Module %d: Interrupt mask transfer 0x%X\n", | ||
| 100 | module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module))); | ||
| 101 | (*fpPrint) ("Module %d: Interrupt mask block 0x%X\n", | ||
| 102 | module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module))); | ||
| 103 | (*fpPrint) ("Module %d: Interrupt mask src transfer 0x%X\n", | ||
| 104 | module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module))); | ||
| 105 | (*fpPrint) ("Module %d: Interrupt mask dst transfer 0x%X\n", | ||
| 106 | module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module))); | ||
| 107 | (*fpPrint) ("Module %d: Interrupt mask error 0x%X\n", | ||
| 108 | module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module))); | ||
| 109 | (*fpPrint) ("--------------------------------------------------\n"); | ||
| 110 | (*fpPrint) ("Module %d: Interrupt clear transfer 0x%X\n", | ||
| 111 | module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module))); | ||
| 112 | (*fpPrint) ("Module %d: Interrupt clear block 0x%X\n", | ||
| 113 | module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module))); | ||
| 114 | (*fpPrint) ("Module %d: Interrupt clear src transfer 0x%X\n", | ||
| 115 | module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module))); | ||
| 116 | (*fpPrint) ("Module %d: Interrupt clear dst transfer 0x%X\n", | ||
| 117 | module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module))); | ||
| 118 | (*fpPrint) ("Module %d: Interrupt clear error 0x%X\n", | ||
| 119 | module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module))); | ||
| 120 | (*fpPrint) ("--------------------------------------------------\n"); | ||
| 121 | (*fpPrint) ("Module %d: SW source req 0x%X\n", | ||
| 122 | module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module))); | ||
| 123 | (*fpPrint) ("Module %d: SW dest req 0x%X\n", | ||
| 124 | module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module))); | ||
| 125 | (*fpPrint) ("Module %d: SW source signal 0x%X\n", | ||
| 126 | module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module))); | ||
| 127 | (*fpPrint) ("Module %d: SW dest signal 0x%X\n", | ||
| 128 | module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module))); | ||
| 129 | (*fpPrint) ("Module %d: SW source last 0x%X\n", | ||
| 130 | module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module))); | ||
| 131 | (*fpPrint) ("Module %d: SW dest last 0x%X\n", | ||
| 132 | module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module))); | ||
| 133 | (*fpPrint) ("--------------------------------------------------\n"); | ||
| 134 | (*fpPrint) ("Module %d: misc config 0x%X\n", | ||
| 135 | module, (uint32_t) (dmacHw_REG_MISC_CFG(module))); | ||
| 136 | (*fpPrint) ("Module %d: misc channel enable 0x%X\n", | ||
| 137 | module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module))); | ||
| 138 | (*fpPrint) ("Module %d: misc ID 0x%X\n", | ||
| 139 | module, (uint32_t) (dmacHw_REG_MISC_ID(module))); | ||
| 140 | (*fpPrint) ("Module %d: misc test 0x%X\n", | ||
| 141 | module, (uint32_t) (dmacHw_REG_MISC_TEST(module))); | ||
| 142 | |||
| 143 | if (channel == -1) { | ||
| 144 | for (chan = 0; chan < 8; chan++) { | ||
| 145 | (*fpPrint) | ||
| 146 | ("--------------------------------------------------\n"); | ||
| 147 | (*fpPrint) | ||
| 148 | ("Module %d: Channel %d Source 0x%X\n", | ||
| 149 | module, chan, | ||
| 150 | (uint32_t) (dmacHw_REG_SAR(module, chan))); | ||
| 151 | (*fpPrint) | ||
| 152 | ("Module %d: Channel %d Destination 0x%X\n", | ||
| 153 | module, chan, | ||
| 154 | (uint32_t) (dmacHw_REG_DAR(module, chan))); | ||
| 155 | (*fpPrint) | ||
| 156 | ("Module %d: Channel %d LLP 0x%X\n", | ||
| 157 | module, chan, | ||
| 158 | (uint32_t) (dmacHw_REG_LLP(module, chan))); | ||
| 159 | (*fpPrint) | ||
| 160 | ("Module %d: Channel %d Control (LO) 0x%X\n", | ||
| 161 | module, chan, | ||
| 162 | (uint32_t) (dmacHw_REG_CTL_LO(module, chan))); | ||
| 163 | (*fpPrint) | ||
| 164 | ("Module %d: Channel %d Control (HI) 0x%X\n", | ||
| 165 | module, chan, | ||
| 166 | (uint32_t) (dmacHw_REG_CTL_HI(module, chan))); | ||
| 167 | (*fpPrint) | ||
| 168 | ("Module %d: Channel %d Source Stats 0x%X\n", | ||
| 169 | module, chan, | ||
| 170 | (uint32_t) (dmacHw_REG_SSTAT(module, chan))); | ||
| 171 | (*fpPrint) | ||
| 172 | ("Module %d: Channel %d Dest Stats 0x%X\n", | ||
| 173 | module, chan, | ||
| 174 | (uint32_t) (dmacHw_REG_DSTAT(module, chan))); | ||
| 175 | (*fpPrint) | ||
| 176 | ("Module %d: Channel %d Source Stats Addr 0x%X\n", | ||
| 177 | module, chan, | ||
| 178 | (uint32_t) (dmacHw_REG_SSTATAR(module, chan))); | ||
| 179 | (*fpPrint) | ||
| 180 | ("Module %d: Channel %d Dest Stats Addr 0x%X\n", | ||
| 181 | module, chan, | ||
| 182 | (uint32_t) (dmacHw_REG_DSTATAR(module, chan))); | ||
| 183 | (*fpPrint) | ||
| 184 | ("Module %d: Channel %d Config (LO) 0x%X\n", | ||
| 185 | module, chan, | ||
| 186 | (uint32_t) (dmacHw_REG_CFG_LO(module, chan))); | ||
| 187 | (*fpPrint) | ||
| 188 | ("Module %d: Channel %d Config (HI) 0x%X\n", | ||
| 189 | module, chan, | ||
| 190 | (uint32_t) (dmacHw_REG_CFG_HI(module, chan))); | ||
| 191 | } | ||
| 192 | } else { | ||
| 193 | chan = channel; | ||
| 194 | (*fpPrint) | ||
| 195 | ("--------------------------------------------------\n"); | ||
| 196 | (*fpPrint) | ||
| 197 | ("Module %d: Channel %d Source 0x%X\n", | ||
| 198 | module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan))); | ||
| 199 | (*fpPrint) | ||
| 200 | ("Module %d: Channel %d Destination 0x%X\n", | ||
| 201 | module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan))); | ||
| 202 | (*fpPrint) | ||
| 203 | ("Module %d: Channel %d LLP 0x%X\n", | ||
| 204 | module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan))); | ||
| 205 | (*fpPrint) | ||
| 206 | ("Module %d: Channel %d Control (LO) 0x%X\n", | ||
| 207 | module, chan, | ||
| 208 | (uint32_t) (dmacHw_REG_CTL_LO(module, chan))); | ||
| 209 | (*fpPrint) | ||
| 210 | ("Module %d: Channel %d Control (HI) 0x%X\n", | ||
| 211 | module, chan, | ||
| 212 | (uint32_t) (dmacHw_REG_CTL_HI(module, chan))); | ||
| 213 | (*fpPrint) | ||
| 214 | ("Module %d: Channel %d Source Stats 0x%X\n", | ||
| 215 | module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan))); | ||
| 216 | (*fpPrint) | ||
| 217 | ("Module %d: Channel %d Dest Stats 0x%X\n", | ||
| 218 | module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan))); | ||
| 219 | (*fpPrint) | ||
| 220 | ("Module %d: Channel %d Source Stats Addr 0x%X\n", | ||
| 221 | module, chan, | ||
| 222 | (uint32_t) (dmacHw_REG_SSTATAR(module, chan))); | ||
| 223 | (*fpPrint) | ||
| 224 | ("Module %d: Channel %d Dest Stats Addr 0x%X\n", | ||
| 225 | module, chan, | ||
| 226 | (uint32_t) (dmacHw_REG_DSTATAR(module, chan))); | ||
| 227 | (*fpPrint) | ||
| 228 | ("Module %d: Channel %d Config (LO) 0x%X\n", | ||
| 229 | module, chan, | ||
| 230 | (uint32_t) (dmacHw_REG_CFG_LO(module, chan))); | ||
| 231 | (*fpPrint) | ||
| 232 | ("Module %d: Channel %d Config (HI) 0x%X\n", | ||
| 233 | module, chan, | ||
| 234 | (uint32_t) (dmacHw_REG_CFG_HI(module, chan))); | ||
| 235 | } | ||
| 236 | } | ||
| 237 | |||
| 238 | /****************************************************************************/ | ||
| 239 | /** | ||
| 240 | * @brief Helper function to display descriptor ring | ||
| 241 | * | ||
| 242 | * @return void | ||
| 243 | * | ||
| 244 | * | ||
| 245 | * @note | ||
| 246 | * None | ||
| 247 | */ | ||
| 248 | /****************************************************************************/ | ||
| 249 | static void DisplayDescRing(void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 250 | int (*fpPrint) (const char *, ...) /* [ IN ] Callback to the print function */ | ||
| 251 | ) { | ||
| 252 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 253 | dmacHw_DESC_t *pStart; | ||
| 254 | |||
| 255 | if (pRing->pHead == NULL) { | ||
| 256 | return; | ||
| 257 | } | ||
| 258 | |||
| 259 | pStart = pRing->pHead; | ||
| 260 | |||
| 261 | while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) { | ||
| 262 | if (pStart == pRing->pHead) { | ||
| 263 | (*fpPrint) ("Head\n"); | ||
| 264 | } | ||
| 265 | if (pStart == pRing->pTail) { | ||
| 266 | (*fpPrint) ("Tail\n"); | ||
| 267 | } | ||
| 268 | if (pStart == pRing->pProg) { | ||
| 269 | (*fpPrint) ("Prog\n"); | ||
| 270 | } | ||
| 271 | if (pStart == pRing->pEnd) { | ||
| 272 | (*fpPrint) ("End\n"); | ||
| 273 | } | ||
| 274 | if (pStart == pRing->pFree) { | ||
| 275 | (*fpPrint) ("Free\n"); | ||
| 276 | } | ||
| 277 | (*fpPrint) ("0x%X:\n", (uint32_t) pStart); | ||
| 278 | (*fpPrint) ("sar 0x%0X\n", pStart->sar); | ||
| 279 | (*fpPrint) ("dar 0x%0X\n", pStart->dar); | ||
| 280 | (*fpPrint) ("llp 0x%0X\n", pStart->llp); | ||
| 281 | (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); | ||
| 282 | (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); | ||
| 283 | (*fpPrint) ("sstat 0x%0X\n", pStart->sstat); | ||
| 284 | (*fpPrint) ("dstat 0x%0X\n", pStart->dstat); | ||
| 285 | (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl); | ||
| 286 | |||
| 287 | pStart = (dmacHw_DESC_t *) pStart->llp; | ||
| 288 | } | ||
| 289 | if (pStart == pRing->pHead) { | ||
| 290 | (*fpPrint) ("Head\n"); | ||
| 291 | } | ||
| 292 | if (pStart == pRing->pTail) { | ||
| 293 | (*fpPrint) ("Tail\n"); | ||
| 294 | } | ||
| 295 | if (pStart == pRing->pProg) { | ||
| 296 | (*fpPrint) ("Prog\n"); | ||
| 297 | } | ||
| 298 | if (pStart == pRing->pEnd) { | ||
| 299 | (*fpPrint) ("End\n"); | ||
| 300 | } | ||
| 301 | if (pStart == pRing->pFree) { | ||
| 302 | (*fpPrint) ("Free\n"); | ||
| 303 | } | ||
| 304 | (*fpPrint) ("0x%X:\n", (uint32_t) pStart); | ||
| 305 | (*fpPrint) ("sar 0x%0X\n", pStart->sar); | ||
| 306 | (*fpPrint) ("dar 0x%0X\n", pStart->dar); | ||
| 307 | (*fpPrint) ("llp 0x%0X\n", pStart->llp); | ||
| 308 | (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo); | ||
| 309 | (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi); | ||
| 310 | (*fpPrint) ("sstat 0x%0X\n", pStart->sstat); | ||
| 311 | (*fpPrint) ("dstat 0x%0X\n", pStart->dstat); | ||
| 312 | (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl); | ||
| 313 | } | ||
| 314 | |||
| 315 | /****************************************************************************/ | ||
| 316 | /** | ||
| 317 | * @brief Check if DMA channel is the flow controller | ||
| 318 | * | ||
| 319 | * @return 1 : If DMA is a flow controler | ||
| 320 | * 0 : Peripheral is the flow controller | ||
| 321 | * | ||
| 322 | * @note | ||
| 323 | * None | ||
| 324 | */ | ||
| 325 | /****************************************************************************/ | ||
| 326 | static inline int DmaIsFlowController(void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 327 | ) { | ||
| 328 | uint32_t ttfc = | ||
| 329 | (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl. | ||
| 330 | lo & dmacHw_REG_CTL_TTFC_MASK; | ||
| 331 | |||
| 332 | switch (ttfc) { | ||
| 333 | case dmacHw_REG_CTL_TTFC_MM_DMAC: | ||
| 334 | case dmacHw_REG_CTL_TTFC_MP_DMAC: | ||
| 335 | case dmacHw_REG_CTL_TTFC_PM_DMAC: | ||
| 336 | case dmacHw_REG_CTL_TTFC_PP_DMAC: | ||
| 337 | return 1; | ||
| 338 | } | ||
| 339 | |||
| 340 | return 0; | ||
| 341 | } | ||
| 342 | |||
| 343 | /****************************************************************************/ | ||
| 344 | /** | ||
| 345 | * @brief Overwrites data length in the descriptor | ||
| 346 | * | ||
| 347 | * This function overwrites data length in the descriptor | ||
| 348 | * | ||
| 349 | * | ||
| 350 | * @return void | ||
| 351 | * | ||
| 352 | * @note | ||
| 353 | * This is only used for PCM channel | ||
| 354 | */ | ||
| 355 | /****************************************************************************/ | ||
| 356 | void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 357 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 358 | size_t dataLen /* [ IN ] Data length in bytes */ | ||
| 359 | ) { | ||
| 360 | dmacHw_DESC_t *pProg; | ||
| 361 | dmacHw_DESC_t *pHead; | ||
| 362 | int srcTs = 0; | ||
| 363 | int srcTrSize = 0; | ||
| 364 | |||
| 365 | pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead; | ||
| 366 | pProg = pHead; | ||
| 367 | |||
| 368 | srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); | ||
| 369 | srcTs = dataLen / srcTrSize; | ||
| 370 | do { | ||
| 371 | pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK; | ||
| 372 | pProg = (dmacHw_DESC_t *) pProg->llp; | ||
| 373 | } while (pProg != pHead); | ||
| 374 | } | ||
| 375 | |||
| 376 | /****************************************************************************/ | ||
| 377 | /** | ||
| 378 | * @brief Clears the interrupt | ||
| 379 | * | ||
| 380 | * This function clears the DMA channel specific interrupt | ||
| 381 | * | ||
| 382 | * | ||
| 383 | * @return void | ||
| 384 | * | ||
| 385 | * @note | ||
| 386 | * Must be called under the context of ISR | ||
| 387 | */ | ||
| 388 | /****************************************************************************/ | ||
| 389 | void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 390 | ) { | ||
| 391 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 392 | |||
| 393 | dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 394 | dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 395 | dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel); | ||
| 396 | } | ||
| 397 | |||
| 398 | /****************************************************************************/ | ||
| 399 | /** | ||
| 400 | * @brief Returns the cause of channel specific DMA interrupt | ||
| 401 | * | ||
| 402 | * This function returns the cause of interrupt | ||
| 403 | * | ||
| 404 | * @return Interrupt status, each bit representing a specific type of interrupt | ||
| 405 | * | ||
| 406 | * @note | ||
| 407 | * Should be called under the context of ISR | ||
| 408 | */ | ||
| 409 | /****************************************************************************/ | ||
| 410 | dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 411 | ) { | ||
| 412 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 413 | dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE; | ||
| 414 | |||
| 415 | if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) & | ||
| 416 | ((0x00000001 << pCblk->channel))) { | ||
| 417 | status |= dmacHw_INTERRUPT_STATUS_TRANS; | ||
| 418 | } | ||
| 419 | if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) & | ||
| 420 | ((0x00000001 << pCblk->channel))) { | ||
| 421 | status |= dmacHw_INTERRUPT_STATUS_BLOCK; | ||
| 422 | } | ||
| 423 | if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) & | ||
| 424 | ((0x00000001 << pCblk->channel))) { | ||
| 425 | status |= dmacHw_INTERRUPT_STATUS_ERROR; | ||
| 426 | } | ||
| 427 | |||
| 428 | return status; | ||
| 429 | } | ||
| 430 | |||
| 431 | /****************************************************************************/ | ||
| 432 | /** | ||
| 433 | * @brief Indentifies a DMA channel causing interrupt | ||
| 434 | * | ||
| 435 | * This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e | ||
| 436 | * | ||
| 437 | * @return NULL : No channel causing DMA interrupt | ||
| 438 | * ! NULL : Handle to a channel causing DMA interrupt | ||
| 439 | * @note | ||
| 440 | * dmacHw_clearInterrupt() must be called with a valid handle after calling this function | ||
| 441 | */ | ||
| 442 | /****************************************************************************/ | ||
| 443 | dmacHw_HANDLE_t dmacHw_getInterruptSource(void) | ||
| 444 | { | ||
| 445 | uint32_t i; | ||
| 446 | |||
| 447 | for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) { | ||
| 448 | if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) & | ||
| 449 | ((0x00000001 << dmacHw_gCblk[i].channel))) | ||
| 450 | || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) & | ||
| 451 | ((0x00000001 << dmacHw_gCblk[i].channel))) | ||
| 452 | || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) & | ||
| 453 | ((0x00000001 << dmacHw_gCblk[i].channel))) | ||
| 454 | ) { | ||
| 455 | return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]); | ||
| 456 | } | ||
| 457 | } | ||
| 458 | return dmacHw_CBLK_TO_HANDLE(NULL); | ||
| 459 | } | ||
| 460 | |||
| 461 | /****************************************************************************/ | ||
| 462 | /** | ||
| 463 | * @brief Estimates number of descriptor needed to perform certain DMA transfer | ||
| 464 | * | ||
| 465 | * | ||
| 466 | * @return On failure : -1 | ||
| 467 | * On success : Number of descriptor count | ||
| 468 | * | ||
| 469 | * | ||
| 470 | */ | ||
| 471 | /****************************************************************************/ | ||
| 472 | int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 473 | void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ | ||
| 474 | void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ | ||
| 475 | size_t dataLen /* [ IN ] Data length in bytes */ | ||
| 476 | ) { | ||
| 477 | int srcTs = 0; | ||
| 478 | int oddSize = 0; | ||
| 479 | int descCount = 0; | ||
| 480 | int dstTrSize = 0; | ||
| 481 | int srcTrSize = 0; | ||
| 482 | uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE; | ||
| 483 | dmacHw_TRANSACTION_WIDTH_e dstTrWidth; | ||
| 484 | dmacHw_TRANSACTION_WIDTH_e srcTrWidth; | ||
| 485 | |||
| 486 | dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth); | ||
| 487 | srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth); | ||
| 488 | |||
| 489 | /* Skip Tx if buffer is NULL or length is unknown */ | ||
| 490 | if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) { | ||
| 491 | /* Do not initiate transfer */ | ||
| 492 | return -1; | ||
| 493 | } | ||
| 494 | |||
| 495 | /* Ensure scatter and gather are transaction aligned */ | ||
| 496 | if (pConfig->srcGatherWidth % srcTrSize | ||
| 497 | || pConfig->dstScatterWidth % dstTrSize) { | ||
| 498 | return -1; | ||
| 499 | } | ||
| 500 | |||
| 501 | /* | ||
| 502 | Background 1: DMAC can not perform DMA if source and destination addresses are | ||
| 503 | not properly aligned with the channel's transaction width. So, for successful | ||
| 504 | DMA transfer, transaction width must be set according to the alignment of the | ||
| 505 | source and destination address. | ||
| 506 | */ | ||
| 507 | |||
| 508 | /* Adjust destination transaction width if destination address is not aligned properly */ | ||
| 509 | dstTrWidth = pConfig->dstMaxTransactionWidth; | ||
| 510 | while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) { | ||
| 511 | dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth); | ||
| 512 | dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth); | ||
| 513 | } | ||
| 514 | |||
| 515 | /* Adjust source transaction width if source address is not aligned properly */ | ||
| 516 | srcTrWidth = pConfig->srcMaxTransactionWidth; | ||
| 517 | while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) { | ||
| 518 | srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth); | ||
| 519 | srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth); | ||
| 520 | } | ||
| 521 | |||
| 522 | /* Find the maximum transaction per descriptor */ | ||
| 523 | if (pConfig->maxDataPerBlock | ||
| 524 | && ((pConfig->maxDataPerBlock / srcTrSize) < | ||
| 525 | dmacHw_MAX_BLOCKSIZE)) { | ||
| 526 | maxBlockSize = pConfig->maxDataPerBlock / srcTrSize; | ||
| 527 | } | ||
| 528 | |||
| 529 | /* Find number of source transactions needed to complete the DMA transfer */ | ||
| 530 | srcTs = dataLen / srcTrSize; | ||
| 531 | /* Find the odd number of bytes that need to be transferred as single byte transaction width */ | ||
| 532 | if (srcTs && (dstTrSize > srcTrSize)) { | ||
| 533 | oddSize = dataLen % dstTrSize; | ||
| 534 | /* Adjust source transaction count due to "oddSize" */ | ||
| 535 | srcTs = srcTs - (oddSize / srcTrSize); | ||
| 536 | } else { | ||
| 537 | oddSize = dataLen % srcTrSize; | ||
| 538 | } | ||
| 539 | /* Adjust "descCount" due to "oddSize" */ | ||
| 540 | if (oddSize) { | ||
| 541 | descCount++; | ||
| 542 | } | ||
| 543 | |||
| 544 | /* Find the number of descriptor needed for total "srcTs" */ | ||
| 545 | if (srcTs) { | ||
| 546 | descCount += ((srcTs - 1) / maxBlockSize) + 1; | ||
| 547 | } | ||
| 548 | |||
| 549 | return descCount; | ||
| 550 | } | ||
| 551 | |||
| 552 | /****************************************************************************/ | ||
| 553 | /** | ||
| 554 | * @brief Check the existance of pending descriptor | ||
| 555 | * | ||
| 556 | * This function confirmes if there is any pending descriptor in the chain | ||
| 557 | * to program the channel | ||
| 558 | * | ||
| 559 | * @return 1 : Channel need to be programmed with pending descriptor | ||
| 560 | * 0 : No more pending descriptor to programe the channel | ||
| 561 | * | ||
| 562 | * @note | ||
| 563 | * - This function should be called from ISR in case there are pending | ||
| 564 | * descriptor to program the channel. | ||
| 565 | * | ||
| 566 | * Example: | ||
| 567 | * | ||
| 568 | * dmac_isr () | ||
| 569 | * { | ||
| 570 | * ... | ||
| 571 | * if (dmacHw_descriptorPending (handle)) | ||
| 572 | * { | ||
| 573 | * dmacHw_initiateTransfer (handle); | ||
| 574 | * } | ||
| 575 | * } | ||
| 576 | * | ||
| 577 | */ | ||
| 578 | /****************************************************************************/ | ||
| 579 | uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 580 | void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 581 | ) { | ||
| 582 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 583 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 584 | |||
| 585 | /* Make sure channel is not busy */ | ||
| 586 | if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) { | ||
| 587 | /* Check if pEnd is not processed */ | ||
| 588 | if (pRing->pEnd) { | ||
| 589 | /* Something left for processing */ | ||
| 590 | return 1; | ||
| 591 | } | ||
| 592 | } | ||
| 593 | return 0; | ||
| 594 | } | ||
| 595 | |||
| 596 | /****************************************************************************/ | ||
| 597 | /** | ||
| 598 | * @brief Program channel register to stop transfer | ||
| 599 | * | ||
| 600 | * Ensures the channel is not doing any transfer after calling this function | ||
| 601 | * | ||
| 602 | * @return void | ||
| 603 | * | ||
| 604 | */ | ||
| 605 | /****************************************************************************/ | ||
| 606 | void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 607 | ) { | ||
| 608 | dmacHw_CBLK_t *pCblk; | ||
| 609 | |||
| 610 | pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 611 | |||
| 612 | /* Stop the channel */ | ||
| 613 | dmacHw_DMA_STOP(pCblk->module, pCblk->channel); | ||
| 614 | } | ||
| 615 | |||
| 616 | /****************************************************************************/ | ||
| 617 | /** | ||
| 618 | * @brief Deallocates source or destination memory, allocated | ||
| 619 | * | ||
| 620 | * This function can be called to deallocate data memory that was DMAed successfully | ||
| 621 | * | ||
| 622 | * @return On failure : -1 | ||
| 623 | * On success : Number of buffer freed | ||
| 624 | * | ||
| 625 | * @note | ||
| 626 | * This function will be called ONLY, when source OR destination address is pointing | ||
| 627 | * to dynamic memory | ||
| 628 | */ | ||
| 629 | /****************************************************************************/ | ||
| 630 | int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 631 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 632 | void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ | ||
| 633 | ) { | ||
| 634 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 635 | uint32_t count = 0; | ||
| 636 | |||
| 637 | if (fpFree == NULL) { | ||
| 638 | return -1; | ||
| 639 | } | ||
| 640 | |||
| 641 | while ((pRing->pFree != pRing->pTail) | ||
| 642 | && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) { | ||
| 643 | if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) { | ||
| 644 | /* Identify, which memory to free */ | ||
| 645 | if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) { | ||
| 646 | (*fpFree) ((void *)pRing->pFree->dar); | ||
| 647 | } else { | ||
| 648 | /* Destination was a peripheral */ | ||
| 649 | (*fpFree) ((void *)pRing->pFree->sar); | ||
| 650 | } | ||
| 651 | /* Unmark user memory to indicate it is freed */ | ||
| 652 | pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY; | ||
| 653 | } | ||
| 654 | dmacHw_NEXT_DESC(pRing, pFree); | ||
| 655 | |||
| 656 | count++; | ||
| 657 | } | ||
| 658 | |||
| 659 | return count; | ||
| 660 | } | ||
| 661 | |||
| 662 | /****************************************************************************/ | ||
| 663 | /** | ||
| 664 | * @brief Prepares descriptor ring, when source peripheral working as a flow controller | ||
| 665 | * | ||
| 666 | * This function will update the discriptor ring by allocating buffers, when source peripheral | ||
| 667 | * has to work as a flow controller to transfer data from: | ||
| 668 | * - Peripheral to memory. | ||
| 669 | * | ||
| 670 | * @return On failure : -1 | ||
| 671 | * On success : Number of descriptor updated | ||
| 672 | * | ||
| 673 | * | ||
| 674 | * @note | ||
| 675 | * Channel must be configured for peripheral to memory transfer | ||
| 676 | * | ||
| 677 | */ | ||
| 678 | /****************************************************************************/ | ||
| 679 | int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 680 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 681 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 682 | uint32_t srcAddr, /* [ IN ] Source peripheral address */ | ||
| 683 | void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ | ||
| 684 | int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ | ||
| 685 | int num /* [ IN ] Number of descriptor to set */ | ||
| 686 | ) { | ||
| 687 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 688 | dmacHw_DESC_t *pProg = NULL; | ||
| 689 | dmacHw_DESC_t *pLast = NULL; | ||
| 690 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 691 | uint32_t dstAddr; | ||
| 692 | uint32_t controlParam; | ||
| 693 | int i; | ||
| 694 | |||
| 695 | dmacHw_ASSERT(pConfig->transferType == | ||
| 696 | dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM); | ||
| 697 | |||
| 698 | if (num > pRing->num) { | ||
| 699 | return -1; | ||
| 700 | } | ||
| 701 | |||
| 702 | pLast = pRing->pEnd; /* Last descriptor updated */ | ||
| 703 | pProg = pRing->pHead; /* First descriptor in the new list */ | ||
| 704 | |||
| 705 | controlParam = pConfig->srcUpdate | | ||
| 706 | pConfig->dstUpdate | | ||
| 707 | pConfig->srcMaxTransactionWidth | | ||
| 708 | pConfig->dstMaxTransactionWidth | | ||
| 709 | pConfig->srcMasterInterface | | ||
| 710 | pConfig->dstMasterInterface | | ||
| 711 | pConfig->srcMaxBurstWidth | | ||
| 712 | pConfig->dstMaxBurstWidth | | ||
| 713 | dmacHw_REG_CTL_TTFC_PM_PERI | | ||
| 714 | dmacHw_REG_CTL_LLP_DST_EN | | ||
| 715 | dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN; | ||
| 716 | |||
| 717 | for (i = 0; i < num; i++) { | ||
| 718 | /* Allocate Rx buffer only for idle descriptor */ | ||
| 719 | if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) || | ||
| 720 | ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail) | ||
| 721 | ) { | ||
| 722 | /* Rx descriptor is not idle */ | ||
| 723 | break; | ||
| 724 | } | ||
| 725 | /* Set source address */ | ||
| 726 | pRing->pHead->sar = srcAddr; | ||
| 727 | if (fpAlloc) { | ||
| 728 | /* Allocate memory for buffer in descriptor */ | ||
| 729 | dstAddr = (uint32_t) (*fpAlloc) (len); | ||
| 730 | /* Check the destination address */ | ||
| 731 | if (dstAddr == 0) { | ||
| 732 | if (i == 0) { | ||
| 733 | /* Not a single descriptor is available */ | ||
| 734 | return -1; | ||
| 735 | } | ||
| 736 | break; | ||
| 737 | } | ||
| 738 | /* Set destination address */ | ||
| 739 | pRing->pHead->dar = dstAddr; | ||
| 740 | } | ||
| 741 | /* Set control information */ | ||
| 742 | pRing->pHead->ctl.lo = controlParam; | ||
| 743 | /* Use "devCtl" to mark the memory that need to be freed later */ | ||
| 744 | pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY; | ||
| 745 | /* Descriptor is now owned by the channel */ | ||
| 746 | pRing->pHead->ctl.hi = 0; | ||
| 747 | /* Remember the descriptor last updated */ | ||
| 748 | pRing->pEnd = pRing->pHead; | ||
| 749 | /* Update next descriptor */ | ||
| 750 | dmacHw_NEXT_DESC(pRing, pHead); | ||
| 751 | } | ||
| 752 | |||
| 753 | /* Mark the end of the list */ | ||
| 754 | pRing->pEnd->ctl.lo &= | ||
| 755 | ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN); | ||
| 756 | /* Connect the list */ | ||
| 757 | if (pLast != pProg) { | ||
| 758 | pLast->ctl.lo |= | ||
| 759 | dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN; | ||
| 760 | } | ||
| 761 | /* Mark the descriptors are updated */ | ||
| 762 | pCblk->descUpdated = 1; | ||
| 763 | if (!pCblk->varDataStarted) { | ||
| 764 | /* LLP must be pointing to the first descriptor */ | ||
| 765 | dmacHw_SET_LLP(pCblk->module, pCblk->channel, | ||
| 766 | (uint32_t) pProg - pRing->virt2PhyOffset); | ||
| 767 | /* Channel, handling variable data started */ | ||
| 768 | pCblk->varDataStarted = 1; | ||
| 769 | } | ||
| 770 | |||
| 771 | return i; | ||
| 772 | } | ||
| 773 | |||
| 774 | /****************************************************************************/ | ||
| 775 | /** | ||
| 776 | * @brief Read data DMAed to memory | ||
| 777 | * | ||
| 778 | * This function will read data that has been DMAed to memory while transfering from: | ||
| 779 | * - Memory to memory | ||
| 780 | * - Peripheral to memory | ||
| 781 | * | ||
| 782 | * @param handle - | ||
| 783 | * @param ppBbuf - | ||
| 784 | * @param pLen - | ||
| 785 | * | ||
| 786 | * @return 0 - No more data is available to read | ||
| 787 | * 1 - More data might be available to read | ||
| 788 | * | ||
| 789 | */ | ||
| 790 | /****************************************************************************/ | ||
| 791 | int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 792 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 793 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 794 | void **ppBbuf, /* [ OUT ] Data received */ | ||
| 795 | size_t *pLlen /* [ OUT ] Length of the data received */ | ||
| 796 | ) { | ||
| 797 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 798 | |||
| 799 | (void)handle; | ||
| 800 | |||
| 801 | if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) { | ||
| 802 | if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) || | ||
| 803 | (pRing->pTail == pRing->pHead) | ||
| 804 | ) { | ||
| 805 | /* No receive data available */ | ||
| 806 | *ppBbuf = (char *)NULL; | ||
| 807 | *pLlen = 0; | ||
| 808 | |||
| 809 | return 0; | ||
| 810 | } | ||
| 811 | } | ||
| 812 | |||
| 813 | /* Return read buffer and length */ | ||
| 814 | *ppBbuf = (char *)pRing->pTail->dar; | ||
| 815 | |||
| 816 | /* Extract length of the received data */ | ||
| 817 | if (DmaIsFlowController(pDescriptor)) { | ||
| 818 | uint32_t srcTrSize = 0; | ||
| 819 | |||
| 820 | switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) { | ||
| 821 | case dmacHw_REG_CTL_SRC_TR_WIDTH_8: | ||
| 822 | srcTrSize = 1; | ||
| 823 | break; | ||
| 824 | case dmacHw_REG_CTL_SRC_TR_WIDTH_16: | ||
| 825 | srcTrSize = 2; | ||
| 826 | break; | ||
| 827 | case dmacHw_REG_CTL_SRC_TR_WIDTH_32: | ||
| 828 | srcTrSize = 4; | ||
| 829 | break; | ||
| 830 | case dmacHw_REG_CTL_SRC_TR_WIDTH_64: | ||
| 831 | srcTrSize = 8; | ||
| 832 | break; | ||
| 833 | default: | ||
| 834 | dmacHw_ASSERT(0); | ||
| 835 | } | ||
| 836 | /* Calculate length from the block size */ | ||
| 837 | *pLlen = | ||
| 838 | (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) * | ||
| 839 | srcTrSize; | ||
| 840 | } else { | ||
| 841 | /* Extract length from the source peripheral */ | ||
| 842 | *pLlen = pRing->pTail->sstat; | ||
| 843 | } | ||
| 844 | |||
| 845 | /* Advance tail to next descriptor */ | ||
| 846 | dmacHw_NEXT_DESC(pRing, pTail); | ||
| 847 | |||
| 848 | return 1; | ||
| 849 | } | ||
| 850 | |||
| 851 | /****************************************************************************/ | ||
| 852 | /** | ||
| 853 | * @brief Set descriptor carrying control information | ||
| 854 | * | ||
| 855 | * This function will be used to send specific control information to the device | ||
| 856 | * using the DMA channel | ||
| 857 | * | ||
| 858 | * | ||
| 859 | * @return -1 - On failure | ||
| 860 | * 0 - On success | ||
| 861 | * | ||
| 862 | * @note | ||
| 863 | * None | ||
| 864 | */ | ||
| 865 | /****************************************************************************/ | ||
| 866 | int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 867 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 868 | uint32_t ctlAddress, /* [ IN ] Address of the device control register */ | ||
| 869 | uint32_t control /* [ IN ] Device control information */ | ||
| 870 | ) { | ||
| 871 | dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 872 | |||
| 873 | if (ctlAddress == 0) { | ||
| 874 | return -1; | ||
| 875 | } | ||
| 876 | |||
| 877 | /* Check the availability of descriptors in the ring */ | ||
| 878 | if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) { | ||
| 879 | return -1; | ||
| 880 | } | ||
| 881 | /* Set control information */ | ||
| 882 | pRing->pHead->devCtl = control; | ||
| 883 | /* Set source and destination address */ | ||
| 884 | pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl; | ||
| 885 | pRing->pHead->dar = ctlAddress; | ||
| 886 | /* Set control parameters */ | ||
| 887 | if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) { | ||
| 888 | pRing->pHead->ctl.lo = pConfig->transferType | | ||
| 889 | dmacHw_SRC_ADDRESS_UPDATE_MODE_INC | | ||
| 890 | dmacHw_DST_ADDRESS_UPDATE_MODE_INC | | ||
| 891 | dmacHw_SRC_TRANSACTION_WIDTH_32 | | ||
| 892 | pConfig->dstMaxTransactionWidth | | ||
| 893 | dmacHw_SRC_BURST_WIDTH_0 | | ||
| 894 | dmacHw_DST_BURST_WIDTH_0 | | ||
| 895 | pConfig->srcMasterInterface | | ||
| 896 | pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN; | ||
| 897 | } else { | ||
| 898 | uint32_t transferType = 0; | ||
| 899 | switch (pConfig->transferType) { | ||
| 900 | case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM: | ||
| 901 | transferType = dmacHw_REG_CTL_TTFC_PM_PERI; | ||
| 902 | break; | ||
| 903 | case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL: | ||
| 904 | transferType = dmacHw_REG_CTL_TTFC_MP_PERI; | ||
| 905 | break; | ||
| 906 | default: | ||
| 907 | dmacHw_ASSERT(0); | ||
| 908 | } | ||
| 909 | pRing->pHead->ctl.lo = transferType | | ||
| 910 | dmacHw_SRC_ADDRESS_UPDATE_MODE_INC | | ||
| 911 | dmacHw_DST_ADDRESS_UPDATE_MODE_INC | | ||
| 912 | dmacHw_SRC_TRANSACTION_WIDTH_32 | | ||
| 913 | pConfig->dstMaxTransactionWidth | | ||
| 914 | dmacHw_SRC_BURST_WIDTH_0 | | ||
| 915 | dmacHw_DST_BURST_WIDTH_0 | | ||
| 916 | pConfig->srcMasterInterface | | ||
| 917 | pConfig->dstMasterInterface | | ||
| 918 | pConfig->flowControler | dmacHw_REG_CTL_INT_EN; | ||
| 919 | } | ||
| 920 | |||
| 921 | /* Set block transaction size to one 32 bit transaction */ | ||
| 922 | pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1; | ||
| 923 | |||
| 924 | /* Remember the descriptor to initialize the registers */ | ||
| 925 | if (pRing->pProg == dmacHw_DESC_INIT) { | ||
| 926 | pRing->pProg = pRing->pHead; | ||
| 927 | } | ||
| 928 | pRing->pEnd = pRing->pHead; | ||
| 929 | |||
| 930 | /* Advance the descriptor */ | ||
| 931 | dmacHw_NEXT_DESC(pRing, pHead); | ||
| 932 | |||
| 933 | /* Update Tail pointer if destination is a peripheral */ | ||
| 934 | if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) { | ||
| 935 | pRing->pTail = pRing->pHead; | ||
| 936 | } | ||
| 937 | return 0; | ||
| 938 | } | ||
| 939 | |||
| 940 | /****************************************************************************/ | ||
| 941 | /** | ||
| 942 | * @brief Sets channel specific user data | ||
| 943 | * | ||
| 944 | * This function associates user data to a specif DMA channel | ||
| 945 | * | ||
| 946 | */ | ||
| 947 | /****************************************************************************/ | ||
| 948 | void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 949 | void *userData /* [ IN ] User data */ | ||
| 950 | ) { | ||
| 951 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 952 | |||
| 953 | pCblk->userData = userData; | ||
| 954 | } | ||
| 955 | |||
| 956 | /****************************************************************************/ | ||
| 957 | /** | ||
| 958 | * @brief Gets channel specific user data | ||
| 959 | * | ||
| 960 | * This function returns user data specific to a DMA channel | ||
| 961 | * | ||
| 962 | * @return user data | ||
| 963 | */ | ||
| 964 | /****************************************************************************/ | ||
| 965 | void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 966 | ) { | ||
| 967 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 968 | |||
| 969 | return pCblk->userData; | ||
| 970 | } | ||
| 971 | |||
| 972 | /****************************************************************************/ | ||
| 973 | /** | ||
| 974 | * @brief Resets descriptor control information | ||
| 975 | * | ||
| 976 | * @return void | ||
| 977 | */ | ||
| 978 | /****************************************************************************/ | ||
| 979 | void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 980 | ) { | ||
| 981 | int i; | ||
| 982 | dmacHw_DESC_RING_t *pRing; | ||
| 983 | dmacHw_DESC_t *pDesc; | ||
| 984 | |||
| 985 | pRing = dmacHw_GET_DESC_RING(pDescriptor); | ||
| 986 | pDesc = pRing->pHead; | ||
| 987 | |||
| 988 | for (i = 0; i < pRing->num; i++) { | ||
| 989 | /* Mark descriptor is ready to use */ | ||
| 990 | pDesc->ctl.hi = dmacHw_DESC_FREE; | ||
| 991 | /* Look into next link list item */ | ||
| 992 | pDesc++; | ||
| 993 | } | ||
| 994 | pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead; | ||
| 995 | pRing->pProg = dmacHw_DESC_INIT; | ||
| 996 | } | ||
| 997 | |||
| 998 | /****************************************************************************/ | ||
| 999 | /** | ||
| 1000 | * @brief Displays channel specific registers and other control parameters | ||
| 1001 | * | ||
| 1002 | * @return void | ||
| 1003 | * | ||
| 1004 | * | ||
| 1005 | * @note | ||
| 1006 | * None | ||
| 1007 | */ | ||
| 1008 | /****************************************************************************/ | ||
| 1009 | void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 1010 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 1011 | int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ | ||
| 1012 | ) { | ||
| 1013 | dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle); | ||
| 1014 | |||
| 1015 | DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint); | ||
| 1016 | DisplayDescRing(pDescriptor, fpPrint); | ||
| 1017 | } | ||
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile new file mode 100644 index 000000000000..244a61ab7697 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/tmr/Makefile | |||
| @@ -0,0 +1 @@ | |||
| obj-y += tmrHw.o | |||
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c new file mode 100644 index 000000000000..5c1c9a0e5ed2 --- /dev/null +++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c | |||
| @@ -0,0 +1,576 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file tmrHw.c | ||
| 18 | * | ||
| 19 | * @brief Low level Timer driver routines | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * | ||
| 23 | * These routines provide basic timer functionality only. | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 28 | |||
| 29 | #include <csp/errno.h> | ||
| 30 | #include <csp/stdint.h> | ||
| 31 | |||
| 32 | #include <csp/tmrHw.h> | ||
| 33 | #include <mach/csp/tmrHw_reg.h> | ||
| 34 | |||
| 35 | #define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0 | ||
| 36 | #define tmrHw_MILLISEC_PER_SEC (1000) | ||
| 37 | |||
| 38 | #define tmrHw_LOW_1_RESOLUTION_COUNT (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC) | ||
| 39 | #define tmrHw_LOW_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT) | ||
| 40 | #define tmrHw_LOW_16_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 16) | ||
| 41 | #define tmrHw_LOW_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT) | ||
| 42 | #define tmrHw_LOW_256_RESOLUTION_COUNT (tmrHw_LOW_1_RESOLUTION_COUNT / 256) | ||
| 43 | #define tmrHw_LOW_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT) | ||
| 44 | |||
| 45 | #define tmrHw_HIGH_1_RESOLUTION_COUNT (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC) | ||
| 46 | #define tmrHw_HIGH_1_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT) | ||
| 47 | #define tmrHw_HIGH_16_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 16) | ||
| 48 | #define tmrHw_HIGH_16_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT) | ||
| 49 | #define tmrHw_HIGH_256_RESOLUTION_COUNT (tmrHw_HIGH_1_RESOLUTION_COUNT / 256) | ||
| 50 | #define tmrHw_HIGH_256_MAX_MILLISEC (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT) | ||
| 51 | |||
| 52 | static void ResetTimer(tmrHw_ID_t timerId) | ||
| 53 | __attribute__ ((section(".aramtext"))); | ||
| 54 | static int tmrHw_divide(int num, int denom) | ||
| 55 | __attribute__ ((section(".aramtext"))); | ||
| 56 | |||
| 57 | /****************************************************************************/ | ||
| 58 | /** | ||
| 59 | * @brief Get timer capability | ||
| 60 | * | ||
| 61 | * This function returns various capabilities/attributes of a timer | ||
| 62 | * | ||
| 63 | * @return Capability | ||
| 64 | * | ||
| 65 | */ | ||
| 66 | /****************************************************************************/ | ||
| 67 | uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 68 | tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ | ||
| 69 | ) { | ||
| 70 | switch (capability) { | ||
| 71 | case tmrHw_CAPABILITY_CLOCK: | ||
| 72 | return (timerId <= | ||
| 73 | 1) ? tmrHw_LOW_RESOLUTION_CLOCK : | ||
| 74 | tmrHw_HIGH_RESOLUTION_CLOCK; | ||
| 75 | case tmrHw_CAPABILITY_RESOLUTION: | ||
| 76 | return 32; | ||
| 77 | default: | ||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | return 0; | ||
| 81 | } | ||
| 82 | |||
| 83 | /****************************************************************************/ | ||
| 84 | /** | ||
| 85 | * @brief Resets a timer | ||
| 86 | * | ||
| 87 | * This function initializes timer | ||
| 88 | * | ||
| 89 | * @return void | ||
| 90 | * | ||
| 91 | */ | ||
| 92 | /****************************************************************************/ | ||
| 93 | static void ResetTimer(tmrHw_ID_t timerId /* [ IN ] Timer Id */ | ||
| 94 | ) { | ||
| 95 | /* Reset timer */ | ||
| 96 | pTmrHw[timerId].LoadValue = 0; | ||
| 97 | pTmrHw[timerId].CurrentValue = 0xFFFFFFFF; | ||
| 98 | pTmrHw[timerId].Control = 0; | ||
| 99 | pTmrHw[timerId].BackgroundLoad = 0; | ||
| 100 | /* Always configure as a 32 bit timer */ | ||
| 101 | pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT; | ||
| 102 | /* Clear interrupt only if raw status interrupt is set */ | ||
| 103 | if (pTmrHw[timerId].RawInterruptStatus) { | ||
| 104 | pTmrHw[timerId].InterruptClear = 0xFFFFFFFF; | ||
| 105 | } | ||
| 106 | } | ||
| 107 | |||
| 108 | /****************************************************************************/ | ||
| 109 | /** | ||
| 110 | * @brief Sets counter value for an interval in ms | ||
| 111 | * | ||
| 112 | * @return On success: Effective counter value set | ||
| 113 | * On failure: 0 | ||
| 114 | * | ||
| 115 | */ | ||
| 116 | /****************************************************************************/ | ||
| 117 | static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 118 | tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ | ||
| 119 | ) { | ||
| 120 | uint32_t scale = 0; | ||
| 121 | uint32_t count = 0; | ||
| 122 | |||
| 123 | if (timerId == 0 || timerId == 1) { | ||
| 124 | if (msec <= tmrHw_LOW_1_MAX_MILLISEC) { | ||
| 125 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; | ||
| 126 | scale = tmrHw_LOW_1_RESOLUTION_COUNT; | ||
| 127 | } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) { | ||
| 128 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; | ||
| 129 | scale = tmrHw_LOW_16_RESOLUTION_COUNT; | ||
| 130 | } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) { | ||
| 131 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; | ||
| 132 | scale = tmrHw_LOW_256_RESOLUTION_COUNT; | ||
| 133 | } else { | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | count = msec * scale; | ||
| 138 | /* Set counter value */ | ||
| 139 | pTmrHw[timerId].LoadValue = count; | ||
| 140 | pTmrHw[timerId].BackgroundLoad = count; | ||
| 141 | |||
| 142 | } else if (timerId == 2 || timerId == 3) { | ||
| 143 | if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) { | ||
| 144 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; | ||
| 145 | scale = tmrHw_HIGH_1_RESOLUTION_COUNT; | ||
| 146 | } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) { | ||
| 147 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; | ||
| 148 | scale = tmrHw_HIGH_16_RESOLUTION_COUNT; | ||
| 149 | } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) { | ||
| 150 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; | ||
| 151 | scale = tmrHw_HIGH_256_RESOLUTION_COUNT; | ||
| 152 | } else { | ||
| 153 | return 0; | ||
| 154 | } | ||
| 155 | |||
| 156 | count = msec * scale; | ||
| 157 | /* Set counter value */ | ||
| 158 | pTmrHw[timerId].LoadValue = count; | ||
| 159 | pTmrHw[timerId].BackgroundLoad = count; | ||
| 160 | } | ||
| 161 | return count / scale; | ||
| 162 | } | ||
| 163 | |||
| 164 | /****************************************************************************/ | ||
| 165 | /** | ||
| 166 | * @brief Configures a periodic timer in terms of timer interrupt rate | ||
| 167 | * | ||
| 168 | * This function initializes a periodic timer to generate specific number of | ||
| 169 | * timer interrupt per second | ||
| 170 | * | ||
| 171 | * @return On success: Effective timer frequency | ||
| 172 | * On failure: 0 | ||
| 173 | * | ||
| 174 | */ | ||
| 175 | /****************************************************************************/ | ||
| 176 | tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 177 | tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ | ||
| 178 | ) { | ||
| 179 | uint32_t resolution = 0; | ||
| 180 | uint32_t count = 0; | ||
| 181 | ResetTimer(timerId); | ||
| 182 | |||
| 183 | /* Set timer mode periodic */ | ||
| 184 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; | ||
| 185 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; | ||
| 186 | /* Set timer in highest resolution */ | ||
| 187 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; | ||
| 188 | |||
| 189 | if (rate && (timerId == 0 || timerId == 1)) { | ||
| 190 | if (rate > tmrHw_LOW_RESOLUTION_CLOCK) { | ||
| 191 | return 0; | ||
| 192 | } | ||
| 193 | resolution = tmrHw_LOW_RESOLUTION_CLOCK; | ||
| 194 | } else if (rate && (timerId == 2 || timerId == 3)) { | ||
| 195 | if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) { | ||
| 196 | return 0; | ||
| 197 | } else { | ||
| 198 | resolution = tmrHw_HIGH_RESOLUTION_CLOCK; | ||
| 199 | } | ||
| 200 | } else { | ||
| 201 | return 0; | ||
| 202 | } | ||
| 203 | /* Find the counter value */ | ||
| 204 | count = resolution / rate; | ||
| 205 | /* Set counter value */ | ||
| 206 | pTmrHw[timerId].LoadValue = count; | ||
| 207 | pTmrHw[timerId].BackgroundLoad = count; | ||
| 208 | |||
| 209 | return resolution / count; | ||
| 210 | } | ||
| 211 | |||
| 212 | /****************************************************************************/ | ||
| 213 | /** | ||
| 214 | * @brief Configures a periodic timer to generate timer interrupt after | ||
| 215 | * certain time interval | ||
| 216 | * | ||
| 217 | * This function initializes a periodic timer to generate timer interrupt | ||
| 218 | * after every time interval in millisecond | ||
| 219 | * | ||
| 220 | * @return On success: Effective interval set in milli-second | ||
| 221 | * On failure: 0 | ||
| 222 | * | ||
| 223 | */ | ||
| 224 | /****************************************************************************/ | ||
| 225 | tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 226 | tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ | ||
| 227 | ) { | ||
| 228 | ResetTimer(timerId); | ||
| 229 | |||
| 230 | /* Set timer mode periodic */ | ||
| 231 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; | ||
| 232 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; | ||
| 233 | |||
| 234 | return SetTimerPeriod(timerId, msec); | ||
| 235 | } | ||
| 236 | |||
| 237 | /****************************************************************************/ | ||
| 238 | /** | ||
| 239 | * @brief Configures a periodic timer to generate timer interrupt just once | ||
| 240 | * after certain time interval | ||
| 241 | * | ||
| 242 | * This function initializes a periodic timer to generate a single ticks after | ||
| 243 | * certain time interval in millisecond | ||
| 244 | * | ||
| 245 | * @return On success: Effective interval set in milli-second | ||
| 246 | * On failure: 0 | ||
| 247 | * | ||
| 248 | */ | ||
| 249 | /****************************************************************************/ | ||
| 250 | tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 251 | tmrHw_INTERVAL_t msec /* [ IN ] Interval in milli-second */ | ||
| 252 | ) { | ||
| 253 | ResetTimer(timerId); | ||
| 254 | |||
| 255 | /* Set timer mode oneshot */ | ||
| 256 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC; | ||
| 257 | pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT; | ||
| 258 | |||
| 259 | return SetTimerPeriod(timerId, msec); | ||
| 260 | } | ||
| 261 | |||
| 262 | /****************************************************************************/ | ||
| 263 | /** | ||
| 264 | * @brief Configures a timer to run as a free running timer | ||
| 265 | * | ||
| 266 | * This function initializes a timer to run as a free running timer | ||
| 267 | * | ||
| 268 | * @return Timer resolution (count / sec) | ||
| 269 | * | ||
| 270 | */ | ||
| 271 | /****************************************************************************/ | ||
| 272 | tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 273 | uint32_t divider /* [ IN ] Dividing the clock frequency */ | ||
| 274 | ) { | ||
| 275 | uint32_t scale = 0; | ||
| 276 | |||
| 277 | ResetTimer(timerId); | ||
| 278 | /* Set timer as free running mode */ | ||
| 279 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC; | ||
| 280 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT; | ||
| 281 | |||
| 282 | if (divider >= 64) { | ||
| 283 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256; | ||
| 284 | scale = 256; | ||
| 285 | } else if (divider >= 8) { | ||
| 286 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16; | ||
| 287 | scale = 16; | ||
| 288 | } else { | ||
| 289 | pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1; | ||
| 290 | scale = 1; | ||
| 291 | } | ||
| 292 | |||
| 293 | if (timerId == 0 || timerId == 1) { | ||
| 294 | return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale); | ||
| 295 | } else if (timerId == 2 || timerId == 3) { | ||
| 296 | return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale); | ||
| 297 | } | ||
| 298 | |||
| 299 | return 0; | ||
| 300 | } | ||
| 301 | |||
| 302 | /****************************************************************************/ | ||
| 303 | /** | ||
| 304 | * @brief Starts a timer | ||
| 305 | * | ||
| 306 | * This function starts a preconfigured timer | ||
| 307 | * | ||
| 308 | * @return -1 - On Failure | ||
| 309 | * 0 - On Success | ||
| 310 | * | ||
| 311 | */ | ||
| 312 | /****************************************************************************/ | ||
| 313 | int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 314 | ) { | ||
| 315 | pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE; | ||
| 316 | return 0; | ||
| 317 | } | ||
| 318 | |||
| 319 | /****************************************************************************/ | ||
| 320 | /** | ||
| 321 | * @brief Stops a timer | ||
| 322 | * | ||
| 323 | * This function stops a running timer | ||
| 324 | * | ||
| 325 | * @return -1 - On Failure | ||
| 326 | * 0 - On Success | ||
| 327 | * | ||
| 328 | */ | ||
| 329 | /****************************************************************************/ | ||
| 330 | int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 331 | ) { | ||
| 332 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE; | ||
| 333 | return 0; | ||
| 334 | } | ||
| 335 | |||
| 336 | /****************************************************************************/ | ||
| 337 | /** | ||
| 338 | * @brief Gets current timer count | ||
| 339 | * | ||
| 340 | * This function returns the current timer value | ||
| 341 | * | ||
| 342 | * @return Current downcounting timer value | ||
| 343 | * | ||
| 344 | */ | ||
| 345 | /****************************************************************************/ | ||
| 346 | uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 347 | ) { | ||
| 348 | /* return 32 bit timer value */ | ||
| 349 | switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) { | ||
| 350 | case tmrHw_CONTROL_FREE_RUNNING: | ||
| 351 | if (pTmrHw[timerId].CurrentValue) { | ||
| 352 | return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue; | ||
| 353 | } | ||
| 354 | break; | ||
| 355 | case tmrHw_CONTROL_PERIODIC: | ||
| 356 | case tmrHw_CONTROL_ONESHOT: | ||
| 357 | return pTmrHw[timerId].BackgroundLoad - | ||
| 358 | pTmrHw[timerId].CurrentValue; | ||
| 359 | } | ||
| 360 | return 0; | ||
| 361 | } | ||
| 362 | |||
| 363 | /****************************************************************************/ | ||
| 364 | /** | ||
| 365 | * @brief Gets timer count rate | ||
| 366 | * | ||
| 367 | * This function returns the number of counts per second | ||
| 368 | * | ||
| 369 | * @return Count rate | ||
| 370 | * | ||
| 371 | */ | ||
| 372 | /****************************************************************************/ | ||
| 373 | tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 374 | ) { | ||
| 375 | uint32_t divider = 0; | ||
| 376 | |||
| 377 | switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) { | ||
| 378 | case tmrHw_CONTROL_PRESCALE_1: | ||
| 379 | divider = 1; | ||
| 380 | break; | ||
| 381 | case tmrHw_CONTROL_PRESCALE_16: | ||
| 382 | divider = 16; | ||
| 383 | break; | ||
| 384 | case tmrHw_CONTROL_PRESCALE_256: | ||
| 385 | divider = 256; | ||
| 386 | break; | ||
| 387 | default: | ||
| 388 | tmrHw_ASSERT(0); | ||
| 389 | } | ||
| 390 | |||
| 391 | if (timerId == 0 || timerId == 1) { | ||
| 392 | return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider); | ||
| 393 | } else { | ||
| 394 | return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider); | ||
| 395 | } | ||
| 396 | return 0; | ||
| 397 | } | ||
| 398 | |||
| 399 | /****************************************************************************/ | ||
| 400 | /** | ||
| 401 | * @brief Enables timer interrupt | ||
| 402 | * | ||
| 403 | * This function enables the timer interrupt | ||
| 404 | * | ||
| 405 | * @return N/A | ||
| 406 | * | ||
| 407 | */ | ||
| 408 | /****************************************************************************/ | ||
| 409 | void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 410 | ) { | ||
| 411 | pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE; | ||
| 412 | } | ||
| 413 | |||
| 414 | /****************************************************************************/ | ||
| 415 | /** | ||
| 416 | * @brief Disables timer interrupt | ||
| 417 | * | ||
| 418 | * This function disable the timer interrupt | ||
| 419 | * | ||
| 420 | * @return N/A | ||
| 421 | * | ||
| 422 | */ | ||
| 423 | /****************************************************************************/ | ||
| 424 | void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 425 | ) { | ||
| 426 | pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE; | ||
| 427 | } | ||
| 428 | |||
| 429 | /****************************************************************************/ | ||
| 430 | /** | ||
| 431 | * @brief Clears the interrupt | ||
| 432 | * | ||
| 433 | * This function clears the timer interrupt | ||
| 434 | * | ||
| 435 | * @return N/A | ||
| 436 | * | ||
| 437 | * @note | ||
| 438 | * Must be called under the context of ISR | ||
| 439 | */ | ||
| 440 | /****************************************************************************/ | ||
| 441 | void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 442 | ) { | ||
| 443 | pTmrHw[timerId].InterruptClear = 0x1; | ||
| 444 | } | ||
| 445 | |||
| 446 | /****************************************************************************/ | ||
| 447 | /** | ||
| 448 | * @brief Gets the interrupt status | ||
| 449 | * | ||
| 450 | * This function returns timer interrupt status | ||
| 451 | * | ||
| 452 | * @return Interrupt status | ||
| 453 | */ | ||
| 454 | /****************************************************************************/ | ||
| 455 | tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 456 | ) { | ||
| 457 | if (pTmrHw[timerId].InterruptStatus) { | ||
| 458 | return tmrHw_INTERRUPT_STATUS_SET; | ||
| 459 | } else { | ||
| 460 | return tmrHw_INTERRUPT_STATUS_UNSET; | ||
| 461 | } | ||
| 462 | } | ||
| 463 | |||
| 464 | /****************************************************************************/ | ||
| 465 | /** | ||
| 466 | * @brief Indentifies a timer causing interrupt | ||
| 467 | * | ||
| 468 | * This functions returns a timer causing interrupt | ||
| 469 | * | ||
| 470 | * @return 0xFFFFFFFF : No timer causing an interrupt | ||
| 471 | * ! 0xFFFFFFFF : timer causing an interrupt | ||
| 472 | * @note | ||
| 473 | * tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function | ||
| 474 | */ | ||
| 475 | /****************************************************************************/ | ||
| 476 | tmrHw_ID_t tmrHw_getInterruptSource(void /* void */ | ||
| 477 | ) { | ||
| 478 | int i; | ||
| 479 | |||
| 480 | for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) { | ||
| 481 | if (pTmrHw[i].InterruptStatus) { | ||
| 482 | return i; | ||
| 483 | } | ||
| 484 | } | ||
| 485 | |||
| 486 | return 0xFFFFFFFF; | ||
| 487 | } | ||
| 488 | |||
| 489 | /****************************************************************************/ | ||
| 490 | /** | ||
| 491 | * @brief Displays specific timer registers | ||
| 492 | * | ||
| 493 | * | ||
| 494 | * @return void | ||
| 495 | * | ||
| 496 | */ | ||
| 497 | /****************************************************************************/ | ||
| 498 | void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ | ||
| 499 | int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ | ||
| 500 | ) { | ||
| 501 | (*fpPrint) ("Displaying register contents \n\n"); | ||
| 502 | (*fpPrint) ("Timer %d: Load value 0x%X\n", timerId, | ||
| 503 | pTmrHw[timerId].LoadValue); | ||
| 504 | (*fpPrint) ("Timer %d: Background load value 0x%X\n", timerId, | ||
| 505 | pTmrHw[timerId].BackgroundLoad); | ||
| 506 | (*fpPrint) ("Timer %d: Control 0x%X\n", timerId, | ||
| 507 | pTmrHw[timerId].Control); | ||
| 508 | (*fpPrint) ("Timer %d: Interrupt clear 0x%X\n", timerId, | ||
| 509 | pTmrHw[timerId].InterruptClear); | ||
| 510 | (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId, | ||
| 511 | pTmrHw[timerId].RawInterruptStatus); | ||
| 512 | (*fpPrint) ("Timer %d: Interrupt status 0x%X\n", timerId, | ||
| 513 | pTmrHw[timerId].InterruptStatus); | ||
| 514 | } | ||
| 515 | |||
| 516 | /****************************************************************************/ | ||
| 517 | /** | ||
| 518 | * @brief Use a timer to perform a busy wait delay for a number of usecs. | ||
| 519 | * | ||
| 520 | * @return N/A | ||
| 521 | */ | ||
| 522 | /****************************************************************************/ | ||
| 523 | void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ | ||
| 524 | unsigned long usecs /* [ IN ] usec to delay */ | ||
| 525 | ) { | ||
| 526 | tmrHw_RATE_t usec_tick_rate; | ||
| 527 | tmrHw_COUNT_t start_time; | ||
| 528 | tmrHw_COUNT_t delta_time; | ||
| 529 | |||
| 530 | start_time = tmrHw_GetCurrentCount(timerId); | ||
| 531 | usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000); | ||
| 532 | delta_time = usecs * usec_tick_rate; | ||
| 533 | |||
| 534 | /* Busy wait */ | ||
| 535 | while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time)) | ||
| 536 | ; | ||
| 537 | } | ||
| 538 | |||
| 539 | /****************************************************************************/ | ||
| 540 | /** | ||
| 541 | * @brief Local Divide function | ||
| 542 | * | ||
| 543 | * This function does the divide | ||
| 544 | * | ||
| 545 | * @return divide value | ||
| 546 | * | ||
| 547 | */ | ||
| 548 | /****************************************************************************/ | ||
| 549 | static int tmrHw_divide(int num, int denom) | ||
| 550 | { | ||
| 551 | int r; | ||
| 552 | int t = 1; | ||
| 553 | |||
| 554 | /* Shift denom and t up to the largest value to optimize algorithm */ | ||
| 555 | /* t contains the units of each divide */ | ||
| 556 | while ((denom & 0x40000000) == 0) { /* fails if denom=0 */ | ||
| 557 | denom = denom << 1; | ||
| 558 | t = t << 1; | ||
| 559 | } | ||
| 560 | |||
| 561 | /* Intialize the result */ | ||
| 562 | r = 0; | ||
| 563 | |||
| 564 | do { | ||
| 565 | /* Determine if there exists a positive remainder */ | ||
| 566 | if ((num - denom) >= 0) { | ||
| 567 | /* Accumlate t to the result and calculate a new remainder */ | ||
| 568 | num = num - denom; | ||
| 569 | r = r + t; | ||
| 570 | } | ||
| 571 | /* Continue to shift denom and shift t down to 0 */ | ||
| 572 | denom = denom >> 1; | ||
| 573 | t = t >> 1; | ||
| 574 | } while (t != 0); | ||
| 575 | return r; | ||
| 576 | } | ||
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c new file mode 100644 index 000000000000..7b20fccb9d4e --- /dev/null +++ b/arch/arm/mach-bcmring/dma.c | |||
| @@ -0,0 +1,2321 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dma.c | ||
| 18 | * | ||
| 19 | * @brief Implements the DMA interface. | ||
| 20 | */ | ||
| 21 | /****************************************************************************/ | ||
| 22 | |||
| 23 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 24 | |||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/device.h> | ||
| 27 | #include <linux/dma-mapping.h> | ||
| 28 | #include <linux/interrupt.h> | ||
| 29 | #include <linux/irqreturn.h> | ||
| 30 | #include <linux/proc_fs.h> | ||
| 31 | |||
| 32 | #include <mach/timer.h> | ||
| 33 | |||
| 34 | #include <linux/mm.h> | ||
| 35 | #include <linux/pfn.h> | ||
| 36 | #include <asm/atomic.h> | ||
| 37 | #include <mach/dma.h> | ||
| 38 | |||
| 39 | /* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */ | ||
| 40 | /* especially since dc4 doesn't use kmalloc'd memory. */ | ||
| 41 | |||
| 42 | #define ALLOW_MAP_OF_KMALLOC_MEMORY 0 | ||
| 43 | |||
| 44 | /* ---- Public Variables ------------------------------------------------- */ | ||
| 45 | |||
| 46 | /* ---- Private Constants and Types -------------------------------------- */ | ||
| 47 | |||
| 48 | #define MAKE_HANDLE(controllerIdx, channelIdx) (((controllerIdx) << 4) | (channelIdx)) | ||
| 49 | |||
| 50 | #define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f) | ||
| 51 | #define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f) | ||
| 52 | |||
| 53 | #define DMA_MAP_DEBUG 0 | ||
| 54 | |||
| 55 | #if DMA_MAP_DEBUG | ||
| 56 | # define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args) | ||
| 57 | #else | ||
| 58 | # define DMA_MAP_PRINT(fmt, args...) | ||
| 59 | #endif | ||
| 60 | |||
| 61 | /* ---- Private Variables ------------------------------------------------ */ | ||
| 62 | |||
| 63 | static DMA_Global_t gDMA; | ||
| 64 | static struct proc_dir_entry *gDmaDir; | ||
| 65 | |||
| 66 | static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0); | ||
| 67 | static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0); | ||
| 68 | static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0); | ||
| 69 | static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0); | ||
| 70 | |||
| 71 | #include "dma_device.c" | ||
| 72 | |||
| 73 | /* ---- Private Function Prototypes -------------------------------------- */ | ||
| 74 | |||
| 75 | /* ---- Functions ------------------------------------------------------- */ | ||
| 76 | |||
| 77 | /****************************************************************************/ | ||
| 78 | /** | ||
| 79 | * Displays information for /proc/dma/mem-type | ||
| 80 | */ | ||
| 81 | /****************************************************************************/ | ||
| 82 | |||
| 83 | static int dma_proc_read_mem_type(char *buf, char **start, off_t offset, | ||
| 84 | int count, int *eof, void *data) | ||
| 85 | { | ||
| 86 | int len = 0; | ||
| 87 | |||
| 88 | len += sprintf(buf + len, "dma_map_mem statistics\n"); | ||
| 89 | len += | ||
| 90 | sprintf(buf + len, "coherent: %d\n", | ||
| 91 | atomic_read(&gDmaStatMemTypeCoherent)); | ||
| 92 | len += | ||
| 93 | sprintf(buf + len, "kmalloc: %d\n", | ||
| 94 | atomic_read(&gDmaStatMemTypeKmalloc)); | ||
| 95 | len += | ||
| 96 | sprintf(buf + len, "vmalloc: %d\n", | ||
| 97 | atomic_read(&gDmaStatMemTypeVmalloc)); | ||
| 98 | len += | ||
| 99 | sprintf(buf + len, "user: %d\n", | ||
| 100 | atomic_read(&gDmaStatMemTypeUser)); | ||
| 101 | |||
| 102 | return len; | ||
| 103 | } | ||
| 104 | |||
| 105 | /****************************************************************************/ | ||
| 106 | /** | ||
| 107 | * Displays information for /proc/dma/channels | ||
| 108 | */ | ||
| 109 | /****************************************************************************/ | ||
| 110 | |||
| 111 | static int dma_proc_read_channels(char *buf, char **start, off_t offset, | ||
| 112 | int count, int *eof, void *data) | ||
| 113 | { | ||
| 114 | int controllerIdx; | ||
| 115 | int channelIdx; | ||
| 116 | int limit = count - 200; | ||
| 117 | int len = 0; | ||
| 118 | DMA_Channel_t *channel; | ||
| 119 | |||
| 120 | if (down_interruptible(&gDMA.lock) < 0) { | ||
| 121 | return -ERESTARTSYS; | ||
| 122 | } | ||
| 123 | |||
| 124 | for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; | ||
| 125 | controllerIdx++) { | ||
| 126 | for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; | ||
| 127 | channelIdx++) { | ||
| 128 | if (len >= limit) { | ||
| 129 | break; | ||
| 130 | } | ||
| 131 | |||
| 132 | channel = | ||
| 133 | &gDMA.controller[controllerIdx].channel[channelIdx]; | ||
| 134 | |||
| 135 | len += | ||
| 136 | sprintf(buf + len, "%d:%d ", controllerIdx, | ||
| 137 | channelIdx); | ||
| 138 | |||
| 139 | if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) != | ||
| 140 | 0) { | ||
| 141 | len += | ||
| 142 | sprintf(buf + len, "Dedicated for %s ", | ||
| 143 | DMA_gDeviceAttribute[channel-> | ||
| 144 | devType].name); | ||
| 145 | } else { | ||
| 146 | len += sprintf(buf + len, "Shared "); | ||
| 147 | } | ||
| 148 | |||
| 149 | if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) { | ||
| 150 | len += sprintf(buf + len, "No ISR "); | ||
| 151 | } | ||
| 152 | |||
| 153 | if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) { | ||
| 154 | len += sprintf(buf + len, "Fifo: 128 "); | ||
| 155 | } else { | ||
| 156 | len += sprintf(buf + len, "Fifo: 64 "); | ||
| 157 | } | ||
| 158 | |||
| 159 | if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) { | ||
| 160 | len += | ||
| 161 | sprintf(buf + len, "InUse by %s", | ||
| 162 | DMA_gDeviceAttribute[channel-> | ||
| 163 | devType].name); | ||
| 164 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 165 | len += | ||
| 166 | sprintf(buf + len, " (%s:%d)", | ||
| 167 | channel->fileName, | ||
| 168 | channel->lineNum); | ||
| 169 | #endif | ||
| 170 | } else { | ||
| 171 | len += sprintf(buf + len, "Avail "); | ||
| 172 | } | ||
| 173 | |||
| 174 | if (channel->lastDevType != DMA_DEVICE_NONE) { | ||
| 175 | len += | ||
| 176 | sprintf(buf + len, "Last use: %s ", | ||
| 177 | DMA_gDeviceAttribute[channel-> | ||
| 178 | lastDevType]. | ||
| 179 | name); | ||
| 180 | } | ||
| 181 | |||
| 182 | len += sprintf(buf + len, "\n"); | ||
| 183 | } | ||
| 184 | } | ||
| 185 | up(&gDMA.lock); | ||
| 186 | *eof = 1; | ||
| 187 | |||
| 188 | return len; | ||
| 189 | } | ||
| 190 | |||
| 191 | /****************************************************************************/ | ||
| 192 | /** | ||
| 193 | * Displays information for /proc/dma/devices | ||
| 194 | */ | ||
| 195 | /****************************************************************************/ | ||
| 196 | |||
| 197 | static int dma_proc_read_devices(char *buf, char **start, off_t offset, | ||
| 198 | int count, int *eof, void *data) | ||
| 199 | { | ||
| 200 | int limit = count - 200; | ||
| 201 | int len = 0; | ||
| 202 | int devIdx; | ||
| 203 | |||
| 204 | if (down_interruptible(&gDMA.lock) < 0) { | ||
| 205 | return -ERESTARTSYS; | ||
| 206 | } | ||
| 207 | |||
| 208 | for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) { | ||
| 209 | DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx]; | ||
| 210 | |||
| 211 | if (devAttr->name == NULL) { | ||
| 212 | continue; | ||
| 213 | } | ||
| 214 | |||
| 215 | if (len >= limit) { | ||
| 216 | break; | ||
| 217 | } | ||
| 218 | |||
| 219 | len += sprintf(buf + len, "%-12s ", devAttr->name); | ||
| 220 | |||
| 221 | if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { | ||
| 222 | len += | ||
| 223 | sprintf(buf + len, "Dedicated %d:%d ", | ||
| 224 | devAttr->dedicatedController, | ||
| 225 | devAttr->dedicatedChannel); | ||
| 226 | } else { | ||
| 227 | len += sprintf(buf + len, "Shared DMA:"); | ||
| 228 | if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) { | ||
| 229 | len += sprintf(buf + len, "0"); | ||
| 230 | } | ||
| 231 | if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) { | ||
| 232 | len += sprintf(buf + len, "1"); | ||
| 233 | } | ||
| 234 | len += sprintf(buf + len, " "); | ||
| 235 | } | ||
| 236 | if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) { | ||
| 237 | len += sprintf(buf + len, "NoISR "); | ||
| 238 | } | ||
| 239 | if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) { | ||
| 240 | len += sprintf(buf + len, "Allow-128 "); | ||
| 241 | } | ||
| 242 | |||
| 243 | len += | ||
| 244 | sprintf(buf + len, | ||
| 245 | "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n", | ||
| 246 | devAttr->numTransfers, devAttr->transferTicks, | ||
| 247 | devAttr->transferBytes, | ||
| 248 | devAttr->ring.bytesAllocated); | ||
| 249 | |||
| 250 | } | ||
| 251 | |||
| 252 | up(&gDMA.lock); | ||
| 253 | *eof = 1; | ||
| 254 | |||
| 255 | return len; | ||
| 256 | } | ||
| 257 | |||
| 258 | /****************************************************************************/ | ||
| 259 | /** | ||
| 260 | * Determines if a DMA_Device_t is "valid". | ||
| 261 | * | ||
| 262 | * @return | ||
| 263 | * TRUE - dma device is valid | ||
| 264 | * FALSE - dma device isn't valid | ||
| 265 | */ | ||
| 266 | /****************************************************************************/ | ||
| 267 | |||
| 268 | static inline int IsDeviceValid(DMA_Device_t device) | ||
| 269 | { | ||
| 270 | return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES); | ||
| 271 | } | ||
| 272 | |||
| 273 | /****************************************************************************/ | ||
| 274 | /** | ||
| 275 | * Translates a DMA handle into a pointer to a channel. | ||
| 276 | * | ||
| 277 | * @return | ||
| 278 | * non-NULL - pointer to DMA_Channel_t | ||
| 279 | * NULL - DMA Handle was invalid | ||
| 280 | */ | ||
| 281 | /****************************************************************************/ | ||
| 282 | |||
| 283 | static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle) | ||
| 284 | { | ||
| 285 | int controllerIdx; | ||
| 286 | int channelIdx; | ||
| 287 | |||
| 288 | controllerIdx = CONTROLLER_FROM_HANDLE(handle); | ||
| 289 | channelIdx = CHANNEL_FROM_HANDLE(handle); | ||
| 290 | |||
| 291 | if ((controllerIdx > DMA_NUM_CONTROLLERS) | ||
| 292 | || (channelIdx > DMA_NUM_CHANNELS)) { | ||
| 293 | return NULL; | ||
| 294 | } | ||
| 295 | return &gDMA.controller[controllerIdx].channel[channelIdx]; | ||
| 296 | } | ||
| 297 | |||
| 298 | /****************************************************************************/ | ||
| 299 | /** | ||
| 300 | * Interrupt handler which is called to process DMA interrupts. | ||
| 301 | */ | ||
| 302 | /****************************************************************************/ | ||
| 303 | |||
| 304 | static irqreturn_t dma_interrupt_handler(int irq, void *dev_id) | ||
| 305 | { | ||
| 306 | DMA_Channel_t *channel; | ||
| 307 | DMA_DeviceAttribute_t *devAttr; | ||
| 308 | int irqStatus; | ||
| 309 | |||
| 310 | channel = (DMA_Channel_t *) dev_id; | ||
| 311 | |||
| 312 | /* Figure out why we were called, and knock down the interrupt */ | ||
| 313 | |||
| 314 | irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle); | ||
| 315 | dmacHw_clearInterrupt(channel->dmacHwHandle); | ||
| 316 | |||
| 317 | if ((channel->devType < 0) | ||
| 318 | || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) { | ||
| 319 | printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n", | ||
| 320 | channel->devType); | ||
| 321 | return IRQ_NONE; | ||
| 322 | } | ||
| 323 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 324 | |||
| 325 | /* Update stats */ | ||
| 326 | |||
| 327 | if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) { | ||
| 328 | devAttr->transferTicks += | ||
| 329 | (timer_get_tick_count() - devAttr->transferStartTime); | ||
| 330 | } | ||
| 331 | |||
| 332 | if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) { | ||
| 333 | printk(KERN_ERR | ||
| 334 | "dma_interrupt_handler: devType :%d DMA error (%s)\n", | ||
| 335 | channel->devType, devAttr->name); | ||
| 336 | } else { | ||
| 337 | devAttr->numTransfers++; | ||
| 338 | devAttr->transferBytes += devAttr->numBytes; | ||
| 339 | } | ||
| 340 | |||
| 341 | /* Call any installed handler */ | ||
| 342 | |||
| 343 | if (devAttr->devHandler != NULL) { | ||
| 344 | devAttr->devHandler(channel->devType, irqStatus, | ||
| 345 | devAttr->userData); | ||
| 346 | } | ||
| 347 | |||
| 348 | return IRQ_HANDLED; | ||
| 349 | } | ||
| 350 | |||
| 351 | /****************************************************************************/ | ||
| 352 | /** | ||
| 353 | * Allocates memory to hold a descriptor ring. The descriptor ring then | ||
| 354 | * needs to be populated by making one or more calls to | ||
| 355 | * dna_add_descriptors. | ||
| 356 | * | ||
| 357 | * The returned descriptor ring will be automatically initialized. | ||
| 358 | * | ||
| 359 | * @return | ||
| 360 | * 0 Descriptor ring was allocated successfully | ||
| 361 | * -EINVAL Invalid parameters passed in | ||
| 362 | * -ENOMEM Unable to allocate memory for the desired number of descriptors. | ||
| 363 | */ | ||
| 364 | /****************************************************************************/ | ||
| 365 | |||
| 366 | int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */ | ||
| 367 | int numDescriptors /* Number of descriptors that need to be allocated. */ | ||
| 368 | ) { | ||
| 369 | size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors); | ||
| 370 | |||
| 371 | if ((ring == NULL) || (numDescriptors <= 0)) { | ||
| 372 | return -EINVAL; | ||
| 373 | } | ||
| 374 | |||
| 375 | ring->physAddr = 0; | ||
| 376 | ring->descriptorsAllocated = 0; | ||
| 377 | ring->bytesAllocated = 0; | ||
| 378 | |||
| 379 | ring->virtAddr = dma_alloc_writecombine(NULL, | ||
| 380 | bytesToAlloc, | ||
| 381 | &ring->physAddr, | ||
| 382 | GFP_KERNEL); | ||
| 383 | if (ring->virtAddr == NULL) { | ||
| 384 | return -ENOMEM; | ||
| 385 | } | ||
| 386 | |||
| 387 | ring->bytesAllocated = bytesToAlloc; | ||
| 388 | ring->descriptorsAllocated = numDescriptors; | ||
| 389 | |||
| 390 | return dma_init_descriptor_ring(ring, numDescriptors); | ||
| 391 | } | ||
| 392 | |||
| 393 | EXPORT_SYMBOL(dma_alloc_descriptor_ring); | ||
| 394 | |||
| 395 | /****************************************************************************/ | ||
| 396 | /** | ||
| 397 | * Releases the memory which was previously allocated for a descriptor ring. | ||
| 398 | */ | ||
| 399 | /****************************************************************************/ | ||
| 400 | |||
| 401 | void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */ | ||
| 402 | ) { | ||
| 403 | if (ring->virtAddr != NULL) { | ||
| 404 | dma_free_writecombine(NULL, | ||
| 405 | ring->bytesAllocated, | ||
| 406 | ring->virtAddr, ring->physAddr); | ||
| 407 | } | ||
| 408 | |||
| 409 | ring->bytesAllocated = 0; | ||
| 410 | ring->descriptorsAllocated = 0; | ||
| 411 | ring->virtAddr = NULL; | ||
| 412 | ring->physAddr = 0; | ||
| 413 | } | ||
| 414 | |||
| 415 | EXPORT_SYMBOL(dma_free_descriptor_ring); | ||
| 416 | |||
| 417 | /****************************************************************************/ | ||
| 418 | /** | ||
| 419 | * Initializes a descriptor ring, so that descriptors can be added to it. | ||
| 420 | * Once a descriptor ring has been allocated, it may be reinitialized for | ||
| 421 | * use with additional/different regions of memory. | ||
| 422 | * | ||
| 423 | * Note that if 7 descriptors are allocated, it's perfectly acceptable to | ||
| 424 | * initialize the ring with a smaller number of descriptors. The amount | ||
| 425 | * of memory allocated for the descriptor ring will not be reduced, and | ||
| 426 | * the descriptor ring may be reinitialized later | ||
| 427 | * | ||
| 428 | * @return | ||
| 429 | * 0 Descriptor ring was initialized successfully | ||
| 430 | * -ENOMEM The descriptor which was passed in has insufficient space | ||
| 431 | * to hold the desired number of descriptors. | ||
| 432 | */ | ||
| 433 | /****************************************************************************/ | ||
| 434 | |||
| 435 | int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */ | ||
| 436 | int numDescriptors /* Number of descriptors to initialize. */ | ||
| 437 | ) { | ||
| 438 | if (ring->virtAddr == NULL) { | ||
| 439 | return -EINVAL; | ||
| 440 | } | ||
| 441 | if (dmacHw_initDescriptor(ring->virtAddr, | ||
| 442 | ring->physAddr, | ||
| 443 | ring->bytesAllocated, numDescriptors) < 0) { | ||
| 444 | printk(KERN_ERR | ||
| 445 | "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n"); | ||
| 446 | return -ENOMEM; | ||
| 447 | } | ||
| 448 | |||
| 449 | return 0; | ||
| 450 | } | ||
| 451 | |||
| 452 | EXPORT_SYMBOL(dma_init_descriptor_ring); | ||
| 453 | |||
| 454 | /****************************************************************************/ | ||
| 455 | /** | ||
| 456 | * Determines the number of descriptors which would be required for a | ||
| 457 | * transfer of the indicated memory region. | ||
| 458 | * | ||
| 459 | * This function also needs to know which DMA device this transfer will | ||
| 460 | * be destined for, so that the appropriate DMA configuration can be retrieved. | ||
| 461 | * DMA parameters such as transfer width, and whether this is a memory-to-memory | ||
| 462 | * or memory-to-peripheral, etc can all affect the actual number of descriptors | ||
| 463 | * required. | ||
| 464 | * | ||
| 465 | * @return | ||
| 466 | * > 0 Returns the number of descriptors required for the indicated transfer | ||
| 467 | * -ENODEV - Device handed in is invalid. | ||
| 468 | * -EINVAL Invalid parameters | ||
| 469 | * -ENOMEM Memory exhausted | ||
| 470 | */ | ||
| 471 | /****************************************************************************/ | ||
| 472 | |||
| 473 | int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */ | ||
| 474 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 475 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 476 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 477 | ) { | ||
| 478 | int numDescriptors; | ||
| 479 | DMA_DeviceAttribute_t *devAttr; | ||
| 480 | |||
| 481 | if (!IsDeviceValid(device)) { | ||
| 482 | return -ENODEV; | ||
| 483 | } | ||
| 484 | devAttr = &DMA_gDeviceAttribute[device]; | ||
| 485 | |||
| 486 | numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config, | ||
| 487 | (void *)srcData, | ||
| 488 | (void *)dstData, | ||
| 489 | numBytes); | ||
| 490 | if (numDescriptors < 0) { | ||
| 491 | printk(KERN_ERR | ||
| 492 | "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n"); | ||
| 493 | return -EINVAL; | ||
| 494 | } | ||
| 495 | |||
| 496 | return numDescriptors; | ||
| 497 | } | ||
| 498 | |||
| 499 | EXPORT_SYMBOL(dma_calculate_descriptor_count); | ||
| 500 | |||
| 501 | /****************************************************************************/ | ||
| 502 | /** | ||
| 503 | * Adds a region of memory to the descriptor ring. Note that it may take | ||
| 504 | * multiple descriptors for each region of memory. It is the callers | ||
| 505 | * responsibility to allocate a sufficiently large descriptor ring. | ||
| 506 | * | ||
| 507 | * @return | ||
| 508 | * 0 Descriptors were added successfully | ||
| 509 | * -ENODEV Device handed in is invalid. | ||
| 510 | * -EINVAL Invalid parameters | ||
| 511 | * -ENOMEM Memory exhausted | ||
| 512 | */ | ||
| 513 | /****************************************************************************/ | ||
| 514 | |||
| 515 | int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */ | ||
| 516 | DMA_Device_t device, /* DMA Device that descriptors are for */ | ||
| 517 | dma_addr_t srcData, /* Place to get data (memory or device) */ | ||
| 518 | dma_addr_t dstData, /* Place to put data (memory or device) */ | ||
| 519 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 520 | ) { | ||
| 521 | int rc; | ||
| 522 | DMA_DeviceAttribute_t *devAttr; | ||
| 523 | |||
| 524 | if (!IsDeviceValid(device)) { | ||
| 525 | return -ENODEV; | ||
| 526 | } | ||
| 527 | devAttr = &DMA_gDeviceAttribute[device]; | ||
| 528 | |||
| 529 | rc = dmacHw_setDataDescriptor(&devAttr->config, | ||
| 530 | ring->virtAddr, | ||
| 531 | (void *)srcData, | ||
| 532 | (void *)dstData, numBytes); | ||
| 533 | if (rc < 0) { | ||
| 534 | printk(KERN_ERR | ||
| 535 | "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n", | ||
| 536 | rc); | ||
| 537 | return -ENOMEM; | ||
| 538 | } | ||
| 539 | |||
| 540 | return 0; | ||
| 541 | } | ||
| 542 | |||
| 543 | EXPORT_SYMBOL(dma_add_descriptors); | ||
| 544 | |||
| 545 | /****************************************************************************/ | ||
| 546 | /** | ||
| 547 | * Sets the descriptor ring associated with a device. | ||
| 548 | * | ||
| 549 | * Once set, the descriptor ring will be associated with the device, even | ||
| 550 | * across channel request/free calls. Passing in a NULL descriptor ring | ||
| 551 | * will release any descriptor ring currently associated with the device. | ||
| 552 | * | ||
| 553 | * Note: If you call dma_transfer, or one of the other dma_alloc_ functions | ||
| 554 | * the descriptor ring may be released and reallocated. | ||
| 555 | * | ||
| 556 | * Note: This function will release the descriptor memory for any current | ||
| 557 | * descriptor ring associated with this device. | ||
| 558 | * | ||
| 559 | * @return | ||
| 560 | * 0 Descriptors were added successfully | ||
| 561 | * -ENODEV Device handed in is invalid. | ||
| 562 | */ | ||
| 563 | /****************************************************************************/ | ||
| 564 | |||
| 565 | int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */ | ||
| 566 | DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */ | ||
| 567 | ) { | ||
| 568 | DMA_DeviceAttribute_t *devAttr; | ||
| 569 | |||
| 570 | if (!IsDeviceValid(device)) { | ||
| 571 | return -ENODEV; | ||
| 572 | } | ||
| 573 | devAttr = &DMA_gDeviceAttribute[device]; | ||
| 574 | |||
| 575 | /* Free the previously allocated descriptor ring */ | ||
| 576 | |||
| 577 | dma_free_descriptor_ring(&devAttr->ring); | ||
| 578 | |||
| 579 | if (ring != NULL) { | ||
| 580 | /* Copy in the new one */ | ||
| 581 | |||
| 582 | devAttr->ring = *ring; | ||
| 583 | } | ||
| 584 | |||
| 585 | /* Set things up so that if dma_transfer is called then this descriptor */ | ||
| 586 | /* ring will get freed. */ | ||
| 587 | |||
| 588 | devAttr->prevSrcData = 0; | ||
| 589 | devAttr->prevDstData = 0; | ||
| 590 | devAttr->prevNumBytes = 0; | ||
| 591 | |||
| 592 | return 0; | ||
| 593 | } | ||
| 594 | |||
| 595 | EXPORT_SYMBOL(dma_set_device_descriptor_ring); | ||
| 596 | |||
| 597 | /****************************************************************************/ | ||
| 598 | /** | ||
| 599 | * Retrieves the descriptor ring associated with a device. | ||
| 600 | * | ||
| 601 | * @return | ||
| 602 | * 0 Descriptors were added successfully | ||
| 603 | * -ENODEV Device handed in is invalid. | ||
| 604 | */ | ||
| 605 | /****************************************************************************/ | ||
| 606 | |||
| 607 | int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */ | ||
| 608 | DMA_DescriptorRing_t *ring /* Place to store retrieved ring */ | ||
| 609 | ) { | ||
| 610 | DMA_DeviceAttribute_t *devAttr; | ||
| 611 | |||
| 612 | memset(ring, 0, sizeof(*ring)); | ||
| 613 | |||
| 614 | if (!IsDeviceValid(device)) { | ||
| 615 | return -ENODEV; | ||
| 616 | } | ||
| 617 | devAttr = &DMA_gDeviceAttribute[device]; | ||
| 618 | |||
| 619 | *ring = devAttr->ring; | ||
| 620 | |||
| 621 | return 0; | ||
| 622 | } | ||
| 623 | |||
| 624 | EXPORT_SYMBOL(dma_get_device_descriptor_ring); | ||
| 625 | |||
| 626 | /****************************************************************************/ | ||
| 627 | /** | ||
| 628 | * Configures a DMA channel. | ||
| 629 | * | ||
| 630 | * @return | ||
| 631 | * >= 0 - Initialization was successfull. | ||
| 632 | * | ||
| 633 | * -EBUSY - Device is currently being used. | ||
| 634 | * -ENODEV - Device handed in is invalid. | ||
| 635 | */ | ||
| 636 | /****************************************************************************/ | ||
| 637 | |||
| 638 | static int ConfigChannel(DMA_Handle_t handle) | ||
| 639 | { | ||
| 640 | DMA_Channel_t *channel; | ||
| 641 | DMA_DeviceAttribute_t *devAttr; | ||
| 642 | int controllerIdx; | ||
| 643 | |||
| 644 | channel = HandleToChannel(handle); | ||
| 645 | if (channel == NULL) { | ||
| 646 | return -ENODEV; | ||
| 647 | } | ||
| 648 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 649 | controllerIdx = CONTROLLER_FROM_HANDLE(handle); | ||
| 650 | |||
| 651 | if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) { | ||
| 652 | if (devAttr->config.transferType == | ||
| 653 | dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) { | ||
| 654 | devAttr->config.dstPeripheralPort = | ||
| 655 | devAttr->dmacPort[controllerIdx]; | ||
| 656 | } else if (devAttr->config.transferType == | ||
| 657 | dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) { | ||
| 658 | devAttr->config.srcPeripheralPort = | ||
| 659 | devAttr->dmacPort[controllerIdx]; | ||
| 660 | } | ||
| 661 | } | ||
| 662 | |||
| 663 | if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) { | ||
| 664 | printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n"); | ||
| 665 | return -EIO; | ||
| 666 | } | ||
| 667 | |||
| 668 | return 0; | ||
| 669 | } | ||
| 670 | |||
| 671 | /****************************************************************************/ | ||
| 672 | /** | ||
| 673 | * Intializes all of the data structures associated with the DMA. | ||
| 674 | * @return | ||
| 675 | * >= 0 - Initialization was successfull. | ||
| 676 | * | ||
| 677 | * -EBUSY - Device is currently being used. | ||
| 678 | * -ENODEV - Device handed in is invalid. | ||
| 679 | */ | ||
| 680 | /****************************************************************************/ | ||
| 681 | |||
| 682 | int dma_init(void) | ||
| 683 | { | ||
| 684 | int rc = 0; | ||
| 685 | int controllerIdx; | ||
| 686 | int channelIdx; | ||
| 687 | DMA_Device_t devIdx; | ||
| 688 | DMA_Channel_t *channel; | ||
| 689 | DMA_Handle_t dedicatedHandle; | ||
| 690 | |||
| 691 | memset(&gDMA, 0, sizeof(gDMA)); | ||
| 692 | |||
| 693 | init_MUTEX_LOCKED(&gDMA.lock); | ||
| 694 | init_waitqueue_head(&gDMA.freeChannelQ); | ||
| 695 | |||
| 696 | /* Initialize the Hardware */ | ||
| 697 | |||
| 698 | dmacHw_initDma(); | ||
| 699 | |||
| 700 | /* Start off by marking all of the DMA channels as shared. */ | ||
| 701 | |||
| 702 | for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; | ||
| 703 | controllerIdx++) { | ||
| 704 | for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; | ||
| 705 | channelIdx++) { | ||
| 706 | channel = | ||
| 707 | &gDMA.controller[controllerIdx].channel[channelIdx]; | ||
| 708 | |||
| 709 | channel->flags = 0; | ||
| 710 | channel->devType = DMA_DEVICE_NONE; | ||
| 711 | channel->lastDevType = DMA_DEVICE_NONE; | ||
| 712 | |||
| 713 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 714 | channel->fileName = ""; | ||
| 715 | channel->lineNum = 0; | ||
| 716 | #endif | ||
| 717 | |||
| 718 | channel->dmacHwHandle = | ||
| 719 | dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID | ||
| 720 | (controllerIdx, | ||
| 721 | channelIdx)); | ||
| 722 | dmacHw_initChannel(channel->dmacHwHandle); | ||
| 723 | } | ||
| 724 | } | ||
| 725 | |||
| 726 | /* Record any special attributes that channels may have */ | ||
| 727 | |||
| 728 | gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; | ||
| 729 | gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; | ||
| 730 | gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; | ||
| 731 | gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO; | ||
| 732 | |||
| 733 | /* Now walk through and record the dedicated channels. */ | ||
| 734 | |||
| 735 | for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) { | ||
| 736 | DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx]; | ||
| 737 | |||
| 738 | if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) | ||
| 739 | && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) { | ||
| 740 | printk(KERN_ERR | ||
| 741 | "DMA Device: %s Can only request NO_ISR for dedicated devices\n", | ||
| 742 | devAttr->name); | ||
| 743 | rc = -EINVAL; | ||
| 744 | goto out; | ||
| 745 | } | ||
| 746 | |||
| 747 | if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { | ||
| 748 | /* This is a dedicated device. Mark the channel as being reserved. */ | ||
| 749 | |||
| 750 | if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) { | ||
| 751 | printk(KERN_ERR | ||
| 752 | "DMA Device: %s DMA Controller %d is out of range\n", | ||
| 753 | devAttr->name, | ||
| 754 | devAttr->dedicatedController); | ||
| 755 | rc = -EINVAL; | ||
| 756 | goto out; | ||
| 757 | } | ||
| 758 | |||
| 759 | if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) { | ||
| 760 | printk(KERN_ERR | ||
| 761 | "DMA Device: %s DMA Channel %d is out of range\n", | ||
| 762 | devAttr->name, | ||
| 763 | devAttr->dedicatedChannel); | ||
| 764 | rc = -EINVAL; | ||
| 765 | goto out; | ||
| 766 | } | ||
| 767 | |||
| 768 | dedicatedHandle = | ||
| 769 | MAKE_HANDLE(devAttr->dedicatedController, | ||
| 770 | devAttr->dedicatedChannel); | ||
| 771 | channel = HandleToChannel(dedicatedHandle); | ||
| 772 | |||
| 773 | if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) != | ||
| 774 | 0) { | ||
| 775 | printk | ||
| 776 | ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n", | ||
| 777 | devAttr->name, | ||
| 778 | devAttr->dedicatedController, | ||
| 779 | devAttr->dedicatedChannel, | ||
| 780 | DMA_gDeviceAttribute[channel->devType]. | ||
| 781 | name); | ||
| 782 | rc = -EBUSY; | ||
| 783 | goto out; | ||
| 784 | } | ||
| 785 | |||
| 786 | channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED; | ||
| 787 | channel->devType = devIdx; | ||
| 788 | |||
| 789 | if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) { | ||
| 790 | channel->flags |= DMA_CHANNEL_FLAG_NO_ISR; | ||
| 791 | } | ||
| 792 | |||
| 793 | /* For dedicated channels, we can go ahead and configure the DMA channel now */ | ||
| 794 | /* as well. */ | ||
| 795 | |||
| 796 | ConfigChannel(dedicatedHandle); | ||
| 797 | } | ||
| 798 | } | ||
| 799 | |||
| 800 | /* Go through and register the interrupt handlers */ | ||
| 801 | |||
| 802 | for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS; | ||
| 803 | controllerIdx++) { | ||
| 804 | for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS; | ||
| 805 | channelIdx++) { | ||
| 806 | channel = | ||
| 807 | &gDMA.controller[controllerIdx].channel[channelIdx]; | ||
| 808 | |||
| 809 | if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) { | ||
| 810 | snprintf(channel->name, sizeof(channel->name), | ||
| 811 | "dma %d:%d %s", controllerIdx, | ||
| 812 | channelIdx, | ||
| 813 | channel->devType == | ||
| 814 | DMA_DEVICE_NONE ? "" : | ||
| 815 | DMA_gDeviceAttribute[channel->devType]. | ||
| 816 | name); | ||
| 817 | |||
| 818 | rc = | ||
| 819 | request_irq(IRQ_DMA0C0 + | ||
| 820 | (controllerIdx * | ||
| 821 | DMA_NUM_CHANNELS) + | ||
| 822 | channelIdx, | ||
| 823 | dma_interrupt_handler, | ||
| 824 | IRQF_DISABLED, channel->name, | ||
| 825 | channel); | ||
| 826 | if (rc != 0) { | ||
| 827 | printk(KERN_ERR | ||
| 828 | "request_irq for IRQ_DMA%dC%d failed\n", | ||
| 829 | controllerIdx, channelIdx); | ||
| 830 | } | ||
| 831 | } | ||
| 832 | } | ||
| 833 | } | ||
| 834 | |||
| 835 | /* Create /proc/dma/channels and /proc/dma/devices */ | ||
| 836 | |||
| 837 | gDmaDir = create_proc_entry("dma", S_IFDIR | S_IRUGO | S_IXUGO, NULL); | ||
| 838 | |||
| 839 | if (gDmaDir == NULL) { | ||
| 840 | printk(KERN_ERR "Unable to create /proc/dma\n"); | ||
| 841 | } else { | ||
| 842 | create_proc_read_entry("channels", 0, gDmaDir, | ||
| 843 | dma_proc_read_channels, NULL); | ||
| 844 | create_proc_read_entry("devices", 0, gDmaDir, | ||
| 845 | dma_proc_read_devices, NULL); | ||
| 846 | create_proc_read_entry("mem-type", 0, gDmaDir, | ||
| 847 | dma_proc_read_mem_type, NULL); | ||
| 848 | } | ||
| 849 | |||
| 850 | out: | ||
| 851 | |||
| 852 | up(&gDMA.lock); | ||
| 853 | |||
| 854 | return rc; | ||
| 855 | } | ||
| 856 | |||
| 857 | /****************************************************************************/ | ||
| 858 | /** | ||
| 859 | * Reserves a channel for use with @a dev. If the device is setup to use | ||
| 860 | * a shared channel, then this function will block until a free channel | ||
| 861 | * becomes available. | ||
| 862 | * | ||
| 863 | * @return | ||
| 864 | * >= 0 - A valid DMA Handle. | ||
| 865 | * -EBUSY - Device is currently being used. | ||
| 866 | * -ENODEV - Device handed in is invalid. | ||
| 867 | */ | ||
| 868 | /****************************************************************************/ | ||
| 869 | |||
| 870 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 871 | DMA_Handle_t dma_request_channel_dbg | ||
| 872 | (DMA_Device_t dev, const char *fileName, int lineNum) | ||
| 873 | #else | ||
| 874 | DMA_Handle_t dma_request_channel(DMA_Device_t dev) | ||
| 875 | #endif | ||
| 876 | { | ||
| 877 | DMA_Handle_t handle; | ||
| 878 | DMA_DeviceAttribute_t *devAttr; | ||
| 879 | DMA_Channel_t *channel; | ||
| 880 | int controllerIdx; | ||
| 881 | int controllerIdx2; | ||
| 882 | int channelIdx; | ||
| 883 | |||
| 884 | if (down_interruptible(&gDMA.lock) < 0) { | ||
| 885 | return -ERESTARTSYS; | ||
| 886 | } | ||
| 887 | |||
| 888 | if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) { | ||
| 889 | handle = -ENODEV; | ||
| 890 | goto out; | ||
| 891 | } | ||
| 892 | devAttr = &DMA_gDeviceAttribute[dev]; | ||
| 893 | |||
| 894 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 895 | { | ||
| 896 | char *s; | ||
| 897 | |||
| 898 | s = strrchr(fileName, '/'); | ||
| 899 | if (s != NULL) { | ||
| 900 | fileName = s + 1; | ||
| 901 | } | ||
| 902 | } | ||
| 903 | #endif | ||
| 904 | if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) { | ||
| 905 | /* This device has already been requested and not been freed */ | ||
| 906 | |||
| 907 | printk(KERN_ERR "%s: device %s is already requested\n", | ||
| 908 | __func__, devAttr->name); | ||
| 909 | handle = -EBUSY; | ||
| 910 | goto out; | ||
| 911 | } | ||
| 912 | |||
| 913 | if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) { | ||
| 914 | /* This device has a dedicated channel. */ | ||
| 915 | |||
| 916 | channel = | ||
| 917 | &gDMA.controller[devAttr->dedicatedController]. | ||
| 918 | channel[devAttr->dedicatedChannel]; | ||
| 919 | if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) { | ||
| 920 | handle = -EBUSY; | ||
| 921 | goto out; | ||
| 922 | } | ||
| 923 | |||
| 924 | channel->flags |= DMA_CHANNEL_FLAG_IN_USE; | ||
| 925 | devAttr->flags |= DMA_DEVICE_FLAG_IN_USE; | ||
| 926 | |||
| 927 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 928 | channel->fileName = fileName; | ||
| 929 | channel->lineNum = lineNum; | ||
| 930 | #endif | ||
| 931 | handle = | ||
| 932 | MAKE_HANDLE(devAttr->dedicatedController, | ||
| 933 | devAttr->dedicatedChannel); | ||
| 934 | goto out; | ||
| 935 | } | ||
| 936 | |||
| 937 | /* This device needs to use one of the shared channels. */ | ||
| 938 | |||
| 939 | handle = DMA_INVALID_HANDLE; | ||
| 940 | while (handle == DMA_INVALID_HANDLE) { | ||
| 941 | /* Scan through the shared channels and see if one is available */ | ||
| 942 | |||
| 943 | for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS; | ||
| 944 | controllerIdx2++) { | ||
| 945 | /* Check to see if we should try on controller 1 first. */ | ||
| 946 | |||
| 947 | controllerIdx = controllerIdx2; | ||
| 948 | if ((devAttr-> | ||
| 949 | flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) { | ||
| 950 | controllerIdx = 1 - controllerIdx; | ||
| 951 | } | ||
| 952 | |||
| 953 | /* See if the device is available on the controller being tested */ | ||
| 954 | |||
| 955 | if ((devAttr-> | ||
| 956 | flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx)) | ||
| 957 | != 0) { | ||
| 958 | for (channelIdx = 0; | ||
| 959 | channelIdx < DMA_NUM_CHANNELS; | ||
| 960 | channelIdx++) { | ||
| 961 | channel = | ||
| 962 | &gDMA.controller[controllerIdx]. | ||
| 963 | channel[channelIdx]; | ||
| 964 | |||
| 965 | if (((channel-> | ||
| 966 | flags & | ||
| 967 | DMA_CHANNEL_FLAG_IS_DEDICATED) == | ||
| 968 | 0) | ||
| 969 | && | ||
| 970 | ((channel-> | ||
| 971 | flags & DMA_CHANNEL_FLAG_IN_USE) | ||
| 972 | == 0)) { | ||
| 973 | if (((channel-> | ||
| 974 | flags & | ||
| 975 | DMA_CHANNEL_FLAG_LARGE_FIFO) | ||
| 976 | != 0) | ||
| 977 | && | ||
| 978 | ((devAttr-> | ||
| 979 | flags & | ||
| 980 | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) | ||
| 981 | == 0)) { | ||
| 982 | /* This channel is a large fifo - don't tie it up */ | ||
| 983 | /* with devices that we don't want using it. */ | ||
| 984 | |||
| 985 | continue; | ||
| 986 | } | ||
| 987 | |||
| 988 | channel->flags |= | ||
| 989 | DMA_CHANNEL_FLAG_IN_USE; | ||
| 990 | channel->devType = dev; | ||
| 991 | devAttr->flags |= | ||
| 992 | DMA_DEVICE_FLAG_IN_USE; | ||
| 993 | |||
| 994 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 995 | channel->fileName = fileName; | ||
| 996 | channel->lineNum = lineNum; | ||
| 997 | #endif | ||
| 998 | handle = | ||
| 999 | MAKE_HANDLE(controllerIdx, | ||
| 1000 | channelIdx); | ||
| 1001 | |||
| 1002 | /* Now that we've reserved the channel - we can go ahead and configure it */ | ||
| 1003 | |||
| 1004 | if (ConfigChannel(handle) != 0) { | ||
| 1005 | handle = -EIO; | ||
| 1006 | printk(KERN_ERR | ||
| 1007 | "dma_request_channel: ConfigChannel failed\n"); | ||
| 1008 | } | ||
| 1009 | goto out; | ||
| 1010 | } | ||
| 1011 | } | ||
| 1012 | } | ||
| 1013 | } | ||
| 1014 | |||
| 1015 | /* No channels are currently available. Let's wait for one to free up. */ | ||
| 1016 | |||
| 1017 | { | ||
| 1018 | DEFINE_WAIT(wait); | ||
| 1019 | |||
| 1020 | prepare_to_wait(&gDMA.freeChannelQ, &wait, | ||
| 1021 | TASK_INTERRUPTIBLE); | ||
| 1022 | up(&gDMA.lock); | ||
| 1023 | schedule(); | ||
| 1024 | finish_wait(&gDMA.freeChannelQ, &wait); | ||
| 1025 | |||
| 1026 | if (signal_pending(current)) { | ||
| 1027 | /* We don't currently hold gDMA.lock, so we return directly */ | ||
| 1028 | |||
| 1029 | return -ERESTARTSYS; | ||
| 1030 | } | ||
| 1031 | } | ||
| 1032 | |||
| 1033 | if (down_interruptible(&gDMA.lock)) { | ||
| 1034 | return -ERESTARTSYS; | ||
| 1035 | } | ||
| 1036 | } | ||
| 1037 | |||
| 1038 | out: | ||
| 1039 | up(&gDMA.lock); | ||
| 1040 | |||
| 1041 | return handle; | ||
| 1042 | } | ||
| 1043 | |||
| 1044 | /* Create both _dbg and non _dbg functions for modules. */ | ||
| 1045 | |||
| 1046 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 1047 | #undef dma_request_channel | ||
| 1048 | DMA_Handle_t dma_request_channel(DMA_Device_t dev) | ||
| 1049 | { | ||
| 1050 | return dma_request_channel_dbg(dev, __FILE__, __LINE__); | ||
| 1051 | } | ||
| 1052 | |||
| 1053 | EXPORT_SYMBOL(dma_request_channel_dbg); | ||
| 1054 | #endif | ||
| 1055 | EXPORT_SYMBOL(dma_request_channel); | ||
| 1056 | |||
| 1057 | /****************************************************************************/ | ||
| 1058 | /** | ||
| 1059 | * Frees a previously allocated DMA Handle. | ||
| 1060 | */ | ||
| 1061 | /****************************************************************************/ | ||
| 1062 | |||
| 1063 | int dma_free_channel(DMA_Handle_t handle /* DMA handle. */ | ||
| 1064 | ) { | ||
| 1065 | int rc = 0; | ||
| 1066 | DMA_Channel_t *channel; | ||
| 1067 | DMA_DeviceAttribute_t *devAttr; | ||
| 1068 | |||
| 1069 | if (down_interruptible(&gDMA.lock) < 0) { | ||
| 1070 | return -ERESTARTSYS; | ||
| 1071 | } | ||
| 1072 | |||
| 1073 | channel = HandleToChannel(handle); | ||
| 1074 | if (channel == NULL) { | ||
| 1075 | rc = -EINVAL; | ||
| 1076 | goto out; | ||
| 1077 | } | ||
| 1078 | |||
| 1079 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 1080 | |||
| 1081 | if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) { | ||
| 1082 | channel->lastDevType = channel->devType; | ||
| 1083 | channel->devType = DMA_DEVICE_NONE; | ||
| 1084 | } | ||
| 1085 | channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE; | ||
| 1086 | devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE; | ||
| 1087 | |||
| 1088 | out: | ||
| 1089 | up(&gDMA.lock); | ||
| 1090 | |||
| 1091 | wake_up_interruptible(&gDMA.freeChannelQ); | ||
| 1092 | |||
| 1093 | return rc; | ||
| 1094 | } | ||
| 1095 | |||
| 1096 | EXPORT_SYMBOL(dma_free_channel); | ||
| 1097 | |||
| 1098 | /****************************************************************************/ | ||
| 1099 | /** | ||
| 1100 | * Determines if a given device has been configured as using a shared | ||
| 1101 | * channel. | ||
| 1102 | * | ||
| 1103 | * @return | ||
| 1104 | * 0 Device uses a dedicated channel | ||
| 1105 | * > zero Device uses a shared channel | ||
| 1106 | * < zero Error code | ||
| 1107 | */ | ||
| 1108 | /****************************************************************************/ | ||
| 1109 | |||
| 1110 | int dma_device_is_channel_shared(DMA_Device_t device /* Device to check. */ | ||
| 1111 | ) { | ||
| 1112 | DMA_DeviceAttribute_t *devAttr; | ||
| 1113 | |||
| 1114 | if (!IsDeviceValid(device)) { | ||
| 1115 | return -ENODEV; | ||
| 1116 | } | ||
| 1117 | devAttr = &DMA_gDeviceAttribute[device]; | ||
| 1118 | |||
| 1119 | return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0); | ||
| 1120 | } | ||
| 1121 | |||
| 1122 | EXPORT_SYMBOL(dma_device_is_channel_shared); | ||
| 1123 | |||
| 1124 | /****************************************************************************/ | ||
| 1125 | /** | ||
| 1126 | * Allocates buffers for the descriptors. This is normally done automatically | ||
| 1127 | * but needs to be done explicitly when initiating a dma from interrupt | ||
| 1128 | * context. | ||
| 1129 | * | ||
| 1130 | * @return | ||
| 1131 | * 0 Descriptors were allocated successfully | ||
| 1132 | * -EINVAL Invalid device type for this kind of transfer | ||
| 1133 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 1134 | * -ENOMEM Memory exhausted | ||
| 1135 | */ | ||
| 1136 | /****************************************************************************/ | ||
| 1137 | |||
| 1138 | int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */ | ||
| 1139 | dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ | ||
| 1140 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 1141 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 1142 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 1143 | ) { | ||
| 1144 | DMA_Channel_t *channel; | ||
| 1145 | DMA_DeviceAttribute_t *devAttr; | ||
| 1146 | int numDescriptors; | ||
| 1147 | size_t ringBytesRequired; | ||
| 1148 | int rc = 0; | ||
| 1149 | |||
| 1150 | channel = HandleToChannel(handle); | ||
| 1151 | if (channel == NULL) { | ||
| 1152 | return -ENODEV; | ||
| 1153 | } | ||
| 1154 | |||
| 1155 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 1156 | |||
| 1157 | if (devAttr->config.transferType != transferType) { | ||
| 1158 | return -EINVAL; | ||
| 1159 | } | ||
| 1160 | |||
| 1161 | /* Figure out how many descriptors we need. */ | ||
| 1162 | |||
| 1163 | /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */ | ||
| 1164 | /* srcData, dstData, numBytes); */ | ||
| 1165 | |||
| 1166 | numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config, | ||
| 1167 | (void *)srcData, | ||
| 1168 | (void *)dstData, | ||
| 1169 | numBytes); | ||
| 1170 | if (numDescriptors < 0) { | ||
| 1171 | printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n", | ||
| 1172 | __func__); | ||
| 1173 | return -EINVAL; | ||
| 1174 | } | ||
| 1175 | |||
| 1176 | /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */ | ||
| 1177 | /* a new one. */ | ||
| 1178 | |||
| 1179 | ringBytesRequired = dmacHw_descriptorLen(numDescriptors); | ||
| 1180 | |||
| 1181 | /* printk("ringBytesRequired: %d\n", ringBytesRequired); */ | ||
| 1182 | |||
| 1183 | if (ringBytesRequired > devAttr->ring.bytesAllocated) { | ||
| 1184 | /* Make sure that this code path is never taken from interrupt context. */ | ||
| 1185 | /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */ | ||
| 1186 | /* allocation needs to have already been done. */ | ||
| 1187 | |||
| 1188 | might_sleep(); | ||
| 1189 | |||
| 1190 | /* Free the old descriptor ring and allocate a new one. */ | ||
| 1191 | |||
| 1192 | dma_free_descriptor_ring(&devAttr->ring); | ||
| 1193 | |||
| 1194 | /* And allocate a new one. */ | ||
| 1195 | |||
| 1196 | rc = | ||
| 1197 | dma_alloc_descriptor_ring(&devAttr->ring, | ||
| 1198 | numDescriptors); | ||
| 1199 | if (rc < 0) { | ||
| 1200 | printk(KERN_ERR | ||
| 1201 | "%s: dma_alloc_descriptor_ring(%d) failed\n", | ||
| 1202 | __func__, numDescriptors); | ||
| 1203 | return rc; | ||
| 1204 | } | ||
| 1205 | /* Setup the descriptor for this transfer */ | ||
| 1206 | |||
| 1207 | if (dmacHw_initDescriptor(devAttr->ring.virtAddr, | ||
| 1208 | devAttr->ring.physAddr, | ||
| 1209 | devAttr->ring.bytesAllocated, | ||
| 1210 | numDescriptors) < 0) { | ||
| 1211 | printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", | ||
| 1212 | __func__); | ||
| 1213 | return -EINVAL; | ||
| 1214 | } | ||
| 1215 | } else { | ||
| 1216 | /* We've already got enough ring buffer allocated. All we need to do is reset */ | ||
| 1217 | /* any control information, just in case the previous DMA was stopped. */ | ||
| 1218 | |||
| 1219 | dmacHw_resetDescriptorControl(devAttr->ring.virtAddr); | ||
| 1220 | } | ||
| 1221 | |||
| 1222 | /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */ | ||
| 1223 | /* as last time, then we don't need to call setDataDescriptor again. */ | ||
| 1224 | |||
| 1225 | if (dmacHw_setDataDescriptor(&devAttr->config, | ||
| 1226 | devAttr->ring.virtAddr, | ||
| 1227 | (void *)srcData, | ||
| 1228 | (void *)dstData, numBytes) < 0) { | ||
| 1229 | printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n", | ||
| 1230 | __func__); | ||
| 1231 | return -EINVAL; | ||
| 1232 | } | ||
| 1233 | |||
| 1234 | /* Remember the critical information for this transfer so that we can eliminate */ | ||
| 1235 | /* another call to dma_alloc_descriptors if the caller reuses the same buffers */ | ||
| 1236 | |||
| 1237 | devAttr->prevSrcData = srcData; | ||
| 1238 | devAttr->prevDstData = dstData; | ||
| 1239 | devAttr->prevNumBytes = numBytes; | ||
| 1240 | |||
| 1241 | return 0; | ||
| 1242 | } | ||
| 1243 | |||
| 1244 | EXPORT_SYMBOL(dma_alloc_descriptors); | ||
| 1245 | |||
| 1246 | /****************************************************************************/ | ||
| 1247 | /** | ||
| 1248 | * Allocates and sets up descriptors for a double buffered circular buffer. | ||
| 1249 | * | ||
| 1250 | * This is primarily intended to be used for things like the ingress samples | ||
| 1251 | * from a microphone. | ||
| 1252 | * | ||
| 1253 | * @return | ||
| 1254 | * > 0 Number of descriptors actually allocated. | ||
| 1255 | * -EINVAL Invalid device type for this kind of transfer | ||
| 1256 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 1257 | * -ENOMEM Memory exhausted | ||
| 1258 | */ | ||
| 1259 | /****************************************************************************/ | ||
| 1260 | |||
| 1261 | int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ | ||
| 1262 | dma_addr_t srcData, /* Physical address of source data */ | ||
| 1263 | dma_addr_t dstData1, /* Physical address of first destination buffer */ | ||
| 1264 | dma_addr_t dstData2, /* Physical address of second destination buffer */ | ||
| 1265 | size_t numBytes /* Number of bytes in each destination buffer */ | ||
| 1266 | ) { | ||
| 1267 | DMA_Channel_t *channel; | ||
| 1268 | DMA_DeviceAttribute_t *devAttr; | ||
| 1269 | int numDst1Descriptors; | ||
| 1270 | int numDst2Descriptors; | ||
| 1271 | int numDescriptors; | ||
| 1272 | size_t ringBytesRequired; | ||
| 1273 | int rc = 0; | ||
| 1274 | |||
| 1275 | channel = HandleToChannel(handle); | ||
| 1276 | if (channel == NULL) { | ||
| 1277 | return -ENODEV; | ||
| 1278 | } | ||
| 1279 | |||
| 1280 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 1281 | |||
| 1282 | /* Figure out how many descriptors we need. */ | ||
| 1283 | |||
| 1284 | /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */ | ||
| 1285 | /* srcData, dstData, numBytes); */ | ||
| 1286 | |||
| 1287 | numDst1Descriptors = | ||
| 1288 | dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData, | ||
| 1289 | (void *)dstData1, numBytes); | ||
| 1290 | if (numDst1Descriptors < 0) { | ||
| 1291 | return -EINVAL; | ||
| 1292 | } | ||
| 1293 | numDst2Descriptors = | ||
| 1294 | dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData, | ||
| 1295 | (void *)dstData2, numBytes); | ||
| 1296 | if (numDst2Descriptors < 0) { | ||
| 1297 | return -EINVAL; | ||
| 1298 | } | ||
| 1299 | numDescriptors = numDst1Descriptors + numDst2Descriptors; | ||
| 1300 | /* printk("numDescriptors: %d\n", numDescriptors); */ | ||
| 1301 | |||
| 1302 | /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */ | ||
| 1303 | /* a new one. */ | ||
| 1304 | |||
| 1305 | ringBytesRequired = dmacHw_descriptorLen(numDescriptors); | ||
| 1306 | |||
| 1307 | /* printk("ringBytesRequired: %d\n", ringBytesRequired); */ | ||
| 1308 | |||
| 1309 | if (ringBytesRequired > devAttr->ring.bytesAllocated) { | ||
| 1310 | /* Make sure that this code path is never taken from interrupt context. */ | ||
| 1311 | /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */ | ||
| 1312 | /* allocation needs to have already been done. */ | ||
| 1313 | |||
| 1314 | might_sleep(); | ||
| 1315 | |||
| 1316 | /* Free the old descriptor ring and allocate a new one. */ | ||
| 1317 | |||
| 1318 | dma_free_descriptor_ring(&devAttr->ring); | ||
| 1319 | |||
| 1320 | /* And allocate a new one. */ | ||
| 1321 | |||
| 1322 | rc = | ||
| 1323 | dma_alloc_descriptor_ring(&devAttr->ring, | ||
| 1324 | numDescriptors); | ||
| 1325 | if (rc < 0) { | ||
| 1326 | printk(KERN_ERR | ||
| 1327 | "%s: dma_alloc_descriptor_ring(%d) failed\n", | ||
| 1328 | __func__, ringBytesRequired); | ||
| 1329 | return rc; | ||
| 1330 | } | ||
| 1331 | } | ||
| 1332 | |||
| 1333 | /* Setup the descriptor for this transfer. Since this function is used with */ | ||
| 1334 | /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */ | ||
| 1335 | /* setDataDescriptor will keep trying to append onto the end. */ | ||
| 1336 | |||
| 1337 | if (dmacHw_initDescriptor(devAttr->ring.virtAddr, | ||
| 1338 | devAttr->ring.physAddr, | ||
| 1339 | devAttr->ring.bytesAllocated, | ||
| 1340 | numDescriptors) < 0) { | ||
| 1341 | printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__); | ||
| 1342 | return -EINVAL; | ||
| 1343 | } | ||
| 1344 | |||
| 1345 | /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */ | ||
| 1346 | /* as last time, then we don't need to call setDataDescriptor again. */ | ||
| 1347 | |||
| 1348 | if (dmacHw_setDataDescriptor(&devAttr->config, | ||
| 1349 | devAttr->ring.virtAddr, | ||
| 1350 | (void *)srcData, | ||
| 1351 | (void *)dstData1, numBytes) < 0) { | ||
| 1352 | printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n", | ||
| 1353 | __func__); | ||
| 1354 | return -EINVAL; | ||
| 1355 | } | ||
| 1356 | if (dmacHw_setDataDescriptor(&devAttr->config, | ||
| 1357 | devAttr->ring.virtAddr, | ||
| 1358 | (void *)srcData, | ||
| 1359 | (void *)dstData2, numBytes) < 0) { | ||
| 1360 | printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n", | ||
| 1361 | __func__); | ||
| 1362 | return -EINVAL; | ||
| 1363 | } | ||
| 1364 | |||
| 1365 | /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */ | ||
| 1366 | /* try to make the 'prev' variables right. */ | ||
| 1367 | |||
| 1368 | devAttr->prevSrcData = 0; | ||
| 1369 | devAttr->prevDstData = 0; | ||
| 1370 | devAttr->prevNumBytes = 0; | ||
| 1371 | |||
| 1372 | return numDescriptors; | ||
| 1373 | } | ||
| 1374 | |||
| 1375 | EXPORT_SYMBOL(dma_alloc_double_dst_descriptors); | ||
| 1376 | |||
| 1377 | /****************************************************************************/ | ||
| 1378 | /** | ||
| 1379 | * Initiates a transfer when the descriptors have already been setup. | ||
| 1380 | * | ||
| 1381 | * This is a special case, and normally, the dma_transfer_xxx functions should | ||
| 1382 | * be used. | ||
| 1383 | * | ||
| 1384 | * @return | ||
| 1385 | * 0 Transfer was started successfully | ||
| 1386 | * -ENODEV Invalid handle | ||
| 1387 | */ | ||
| 1388 | /****************************************************************************/ | ||
| 1389 | |||
| 1390 | int dma_start_transfer(DMA_Handle_t handle) | ||
| 1391 | { | ||
| 1392 | DMA_Channel_t *channel; | ||
| 1393 | DMA_DeviceAttribute_t *devAttr; | ||
| 1394 | |||
| 1395 | channel = HandleToChannel(handle); | ||
| 1396 | if (channel == NULL) { | ||
| 1397 | return -ENODEV; | ||
| 1398 | } | ||
| 1399 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 1400 | |||
| 1401 | dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config, | ||
| 1402 | devAttr->ring.virtAddr); | ||
| 1403 | |||
| 1404 | /* Since we got this far, everything went successfully */ | ||
| 1405 | |||
| 1406 | return 0; | ||
| 1407 | } | ||
| 1408 | |||
| 1409 | EXPORT_SYMBOL(dma_start_transfer); | ||
| 1410 | |||
| 1411 | /****************************************************************************/ | ||
| 1412 | /** | ||
| 1413 | * Stops a previously started DMA transfer. | ||
| 1414 | * | ||
| 1415 | * @return | ||
| 1416 | * 0 Transfer was stopped successfully | ||
| 1417 | * -ENODEV Invalid handle | ||
| 1418 | */ | ||
| 1419 | /****************************************************************************/ | ||
| 1420 | |||
| 1421 | int dma_stop_transfer(DMA_Handle_t handle) | ||
| 1422 | { | ||
| 1423 | DMA_Channel_t *channel; | ||
| 1424 | |||
| 1425 | channel = HandleToChannel(handle); | ||
| 1426 | if (channel == NULL) { | ||
| 1427 | return -ENODEV; | ||
| 1428 | } | ||
| 1429 | |||
| 1430 | dmacHw_stopTransfer(channel->dmacHwHandle); | ||
| 1431 | |||
| 1432 | return 0; | ||
| 1433 | } | ||
| 1434 | |||
| 1435 | EXPORT_SYMBOL(dma_stop_transfer); | ||
| 1436 | |||
| 1437 | /****************************************************************************/ | ||
| 1438 | /** | ||
| 1439 | * Waits for a DMA to complete by polling. This function is only intended | ||
| 1440 | * to be used for testing. Interrupts should be used for most DMA operations. | ||
| 1441 | */ | ||
| 1442 | /****************************************************************************/ | ||
| 1443 | |||
| 1444 | int dma_wait_transfer_done(DMA_Handle_t handle) | ||
| 1445 | { | ||
| 1446 | DMA_Channel_t *channel; | ||
| 1447 | dmacHw_TRANSFER_STATUS_e status; | ||
| 1448 | |||
| 1449 | channel = HandleToChannel(handle); | ||
| 1450 | if (channel == NULL) { | ||
| 1451 | return -ENODEV; | ||
| 1452 | } | ||
| 1453 | |||
| 1454 | while ((status = | ||
| 1455 | dmacHw_transferCompleted(channel->dmacHwHandle)) == | ||
| 1456 | dmacHw_TRANSFER_STATUS_BUSY) { | ||
| 1457 | ; | ||
| 1458 | } | ||
| 1459 | |||
| 1460 | if (status == dmacHw_TRANSFER_STATUS_ERROR) { | ||
| 1461 | printk(KERN_ERR "%s: DMA transfer failed\n", __func__); | ||
| 1462 | return -EIO; | ||
| 1463 | } | ||
| 1464 | return 0; | ||
| 1465 | } | ||
| 1466 | |||
| 1467 | EXPORT_SYMBOL(dma_wait_transfer_done); | ||
| 1468 | |||
| 1469 | /****************************************************************************/ | ||
| 1470 | /** | ||
| 1471 | * Initiates a DMA, allocating the descriptors as required. | ||
| 1472 | * | ||
| 1473 | * @return | ||
| 1474 | * 0 Transfer was started successfully | ||
| 1475 | * -EINVAL Invalid device type for this kind of transfer | ||
| 1476 | * (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV) | ||
| 1477 | */ | ||
| 1478 | /****************************************************************************/ | ||
| 1479 | |||
| 1480 | int dma_transfer(DMA_Handle_t handle, /* DMA Handle */ | ||
| 1481 | dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ | ||
| 1482 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 1483 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 1484 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 1485 | ) { | ||
| 1486 | DMA_Channel_t *channel; | ||
| 1487 | DMA_DeviceAttribute_t *devAttr; | ||
| 1488 | int rc = 0; | ||
| 1489 | |||
| 1490 | channel = HandleToChannel(handle); | ||
| 1491 | if (channel == NULL) { | ||
| 1492 | return -ENODEV; | ||
| 1493 | } | ||
| 1494 | |||
| 1495 | devAttr = &DMA_gDeviceAttribute[channel->devType]; | ||
| 1496 | |||
| 1497 | if (devAttr->config.transferType != transferType) { | ||
| 1498 | return -EINVAL; | ||
| 1499 | } | ||
| 1500 | |||
| 1501 | /* We keep track of the information about the previous request for this */ | ||
| 1502 | /* device, and if the attributes match, then we can use the descriptors we setup */ | ||
| 1503 | /* the last time, and not have to reinitialize everything. */ | ||
| 1504 | |||
| 1505 | { | ||
| 1506 | rc = | ||
| 1507 | dma_alloc_descriptors(handle, transferType, srcData, | ||
| 1508 | dstData, numBytes); | ||
| 1509 | if (rc != 0) { | ||
| 1510 | return rc; | ||
| 1511 | } | ||
| 1512 | } | ||
| 1513 | |||
| 1514 | /* And kick off the transfer */ | ||
| 1515 | |||
| 1516 | devAttr->numBytes = numBytes; | ||
| 1517 | devAttr->transferStartTime = timer_get_tick_count(); | ||
| 1518 | |||
| 1519 | dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config, | ||
| 1520 | devAttr->ring.virtAddr); | ||
| 1521 | |||
| 1522 | /* Since we got this far, everything went successfully */ | ||
| 1523 | |||
| 1524 | return 0; | ||
| 1525 | } | ||
| 1526 | |||
| 1527 | EXPORT_SYMBOL(dma_transfer); | ||
| 1528 | |||
| 1529 | /****************************************************************************/ | ||
| 1530 | /** | ||
| 1531 | * Set the callback function which will be called when a transfer completes. | ||
| 1532 | * If a NULL callback function is set, then no callback will occur. | ||
| 1533 | * | ||
| 1534 | * @note @a devHandler will be called from IRQ context. | ||
| 1535 | * | ||
| 1536 | * @return | ||
| 1537 | * 0 - Success | ||
| 1538 | * -ENODEV - Device handed in is invalid. | ||
| 1539 | */ | ||
| 1540 | /****************************************************************************/ | ||
| 1541 | |||
| 1542 | int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */ | ||
| 1543 | DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */ | ||
| 1544 | void *userData /* Pointer which will be passed to devHandler. */ | ||
| 1545 | ) { | ||
| 1546 | DMA_DeviceAttribute_t *devAttr; | ||
| 1547 | unsigned long flags; | ||
| 1548 | |||
| 1549 | if (!IsDeviceValid(dev)) { | ||
| 1550 | return -ENODEV; | ||
| 1551 | } | ||
| 1552 | devAttr = &DMA_gDeviceAttribute[dev]; | ||
| 1553 | |||
| 1554 | local_irq_save(flags); | ||
| 1555 | |||
| 1556 | devAttr->userData = userData; | ||
| 1557 | devAttr->devHandler = devHandler; | ||
| 1558 | |||
| 1559 | local_irq_restore(flags); | ||
| 1560 | |||
| 1561 | return 0; | ||
| 1562 | } | ||
| 1563 | |||
| 1564 | EXPORT_SYMBOL(dma_set_device_handler); | ||
| 1565 | |||
| 1566 | /****************************************************************************/ | ||
| 1567 | /** | ||
| 1568 | * Initializes a memory mapping structure | ||
| 1569 | */ | ||
| 1570 | /****************************************************************************/ | ||
| 1571 | |||
| 1572 | int dma_init_mem_map(DMA_MemMap_t *memMap) | ||
| 1573 | { | ||
| 1574 | memset(memMap, 0, sizeof(*memMap)); | ||
| 1575 | |||
| 1576 | init_MUTEX(&memMap->lock); | ||
| 1577 | |||
| 1578 | return 0; | ||
| 1579 | } | ||
| 1580 | |||
| 1581 | EXPORT_SYMBOL(dma_init_mem_map); | ||
| 1582 | |||
| 1583 | /****************************************************************************/ | ||
| 1584 | /** | ||
| 1585 | * Releases any memory currently being held by a memory mapping structure. | ||
| 1586 | */ | ||
| 1587 | /****************************************************************************/ | ||
| 1588 | |||
| 1589 | int dma_term_mem_map(DMA_MemMap_t *memMap) | ||
| 1590 | { | ||
| 1591 | down(&memMap->lock); /* Just being paranoid */ | ||
| 1592 | |||
| 1593 | /* Free up any allocated memory */ | ||
| 1594 | |||
| 1595 | up(&memMap->lock); | ||
| 1596 | memset(memMap, 0, sizeof(*memMap)); | ||
| 1597 | |||
| 1598 | return 0; | ||
| 1599 | } | ||
| 1600 | |||
| 1601 | EXPORT_SYMBOL(dma_term_mem_map); | ||
| 1602 | |||
| 1603 | /****************************************************************************/ | ||
| 1604 | /** | ||
| 1605 | * Looks at a memory address and categorizes it. | ||
| 1606 | * | ||
| 1607 | * @return One of the values from the DMA_MemType_t enumeration. | ||
| 1608 | */ | ||
| 1609 | /****************************************************************************/ | ||
| 1610 | |||
| 1611 | DMA_MemType_t dma_mem_type(void *addr) | ||
| 1612 | { | ||
| 1613 | unsigned long addrVal = (unsigned long)addr; | ||
| 1614 | |||
| 1615 | if (addrVal >= VMALLOC_END) { | ||
| 1616 | /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */ | ||
| 1617 | |||
| 1618 | /* dma_alloc_xxx pages are physically and virtually contiguous */ | ||
| 1619 | |||
| 1620 | return DMA_MEM_TYPE_DMA; | ||
| 1621 | } | ||
| 1622 | |||
| 1623 | /* Technically, we could add one more classification. Addresses between VMALLOC_END */ | ||
| 1624 | /* and the beginning of the DMA virtual address could be considered to be I/O space. */ | ||
| 1625 | /* Right now, nobody cares about this particular classification, so we ignore it. */ | ||
| 1626 | |||
| 1627 | if (is_vmalloc_addr(addr)) { | ||
| 1628 | /* Address comes from the vmalloc'd region. Pages are virtually */ | ||
| 1629 | /* contiguous but NOT physically contiguous */ | ||
| 1630 | |||
| 1631 | return DMA_MEM_TYPE_VMALLOC; | ||
| 1632 | } | ||
| 1633 | |||
| 1634 | if (addrVal >= PAGE_OFFSET) { | ||
| 1635 | /* PAGE_OFFSET is typically 0xC0000000 */ | ||
| 1636 | |||
| 1637 | /* kmalloc'd pages are physically contiguous */ | ||
| 1638 | |||
| 1639 | return DMA_MEM_TYPE_KMALLOC; | ||
| 1640 | } | ||
| 1641 | |||
| 1642 | return DMA_MEM_TYPE_USER; | ||
| 1643 | } | ||
| 1644 | |||
| 1645 | EXPORT_SYMBOL(dma_mem_type); | ||
| 1646 | |||
| 1647 | /****************************************************************************/ | ||
| 1648 | /** | ||
| 1649 | * Looks at a memory address and determines if we support DMA'ing to/from | ||
| 1650 | * that type of memory. | ||
| 1651 | * | ||
| 1652 | * @return boolean - | ||
| 1653 | * return value != 0 means dma supported | ||
| 1654 | * return value == 0 means dma not supported | ||
| 1655 | */ | ||
| 1656 | /****************************************************************************/ | ||
| 1657 | |||
| 1658 | int dma_mem_supports_dma(void *addr) | ||
| 1659 | { | ||
| 1660 | DMA_MemType_t memType = dma_mem_type(addr); | ||
| 1661 | |||
| 1662 | return (memType == DMA_MEM_TYPE_DMA) | ||
| 1663 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
| 1664 | || (memType == DMA_MEM_TYPE_KMALLOC) | ||
| 1665 | #endif | ||
| 1666 | || (memType == DMA_MEM_TYPE_USER); | ||
| 1667 | } | ||
| 1668 | |||
| 1669 | EXPORT_SYMBOL(dma_mem_supports_dma); | ||
| 1670 | |||
| 1671 | /****************************************************************************/ | ||
| 1672 | /** | ||
| 1673 | * Maps in a memory region such that it can be used for performing a DMA. | ||
| 1674 | * | ||
| 1675 | * @return | ||
| 1676 | */ | ||
| 1677 | /****************************************************************************/ | ||
| 1678 | |||
| 1679 | int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 1680 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
| 1681 | ) { | ||
| 1682 | int rc; | ||
| 1683 | |||
| 1684 | down(&memMap->lock); | ||
| 1685 | |||
| 1686 | DMA_MAP_PRINT("memMap: %p\n", memMap); | ||
| 1687 | |||
| 1688 | if (memMap->inUse) { | ||
| 1689 | printk(KERN_ERR "%s: memory map %p is already being used\n", | ||
| 1690 | __func__, memMap); | ||
| 1691 | rc = -EBUSY; | ||
| 1692 | goto out; | ||
| 1693 | } | ||
| 1694 | |||
| 1695 | memMap->inUse = 1; | ||
| 1696 | memMap->dir = dir; | ||
| 1697 | memMap->numRegionsUsed = 0; | ||
| 1698 | |||
| 1699 | rc = 0; | ||
| 1700 | |||
| 1701 | out: | ||
| 1702 | |||
| 1703 | DMA_MAP_PRINT("returning %d", rc); | ||
| 1704 | |||
| 1705 | up(&memMap->lock); | ||
| 1706 | |||
| 1707 | return rc; | ||
| 1708 | } | ||
| 1709 | |||
| 1710 | EXPORT_SYMBOL(dma_map_start); | ||
| 1711 | |||
| 1712 | /****************************************************************************/ | ||
| 1713 | /** | ||
| 1714 | * Adds a segment of memory to a memory map. Each segment is both | ||
| 1715 | * physically and virtually contiguous. | ||
| 1716 | * | ||
| 1717 | * @return 0 on success, error code otherwise. | ||
| 1718 | */ | ||
| 1719 | /****************************************************************************/ | ||
| 1720 | |||
| 1721 | static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 1722 | DMA_Region_t *region, /* Region that the segment belongs to */ | ||
| 1723 | void *virtAddr, /* Virtual address of the segment being added */ | ||
| 1724 | dma_addr_t physAddr, /* Physical address of the segment being added */ | ||
| 1725 | size_t numBytes /* Number of bytes of the segment being added */ | ||
| 1726 | ) { | ||
| 1727 | DMA_Segment_t *segment; | ||
| 1728 | |||
| 1729 | DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr, | ||
| 1730 | physAddr, numBytes); | ||
| 1731 | |||
| 1732 | /* Sanity check */ | ||
| 1733 | |||
| 1734 | if (((unsigned long)virtAddr < (unsigned long)region->virtAddr) | ||
| 1735 | || (((unsigned long)virtAddr + numBytes)) > | ||
| 1736 | ((unsigned long)region->virtAddr + region->numBytes)) { | ||
| 1737 | printk(KERN_ERR | ||
| 1738 | "%s: virtAddr %p is outside region @ %p len: %d\n", | ||
| 1739 | __func__, virtAddr, region->virtAddr, region->numBytes); | ||
| 1740 | return -EINVAL; | ||
| 1741 | } | ||
| 1742 | |||
| 1743 | if (region->numSegmentsUsed > 0) { | ||
| 1744 | /* Check to see if this segment is physically contiguous with the previous one */ | ||
| 1745 | |||
| 1746 | segment = ®ion->segment[region->numSegmentsUsed - 1]; | ||
| 1747 | |||
| 1748 | if ((segment->physAddr + segment->numBytes) == physAddr) { | ||
| 1749 | /* It is - just add on to the end */ | ||
| 1750 | |||
| 1751 | DMA_MAP_PRINT("appending %d bytes to last segment\n", | ||
| 1752 | numBytes); | ||
| 1753 | |||
| 1754 | segment->numBytes += numBytes; | ||
| 1755 | |||
| 1756 | return 0; | ||
| 1757 | } | ||
| 1758 | } | ||
| 1759 | |||
| 1760 | /* Reallocate to hold more segments, if required. */ | ||
| 1761 | |||
| 1762 | if (region->numSegmentsUsed >= region->numSegmentsAllocated) { | ||
| 1763 | DMA_Segment_t *newSegment; | ||
| 1764 | size_t oldSize = | ||
| 1765 | region->numSegmentsAllocated * sizeof(*newSegment); | ||
| 1766 | int newAlloc = region->numSegmentsAllocated + 4; | ||
| 1767 | size_t newSize = newAlloc * sizeof(*newSegment); | ||
| 1768 | |||
| 1769 | newSegment = kmalloc(newSize, GFP_KERNEL); | ||
| 1770 | if (newSegment == NULL) { | ||
| 1771 | return -ENOMEM; | ||
| 1772 | } | ||
| 1773 | memcpy(newSegment, region->segment, oldSize); | ||
| 1774 | memset(&((uint8_t *) newSegment)[oldSize], 0, | ||
| 1775 | newSize - oldSize); | ||
| 1776 | kfree(region->segment); | ||
| 1777 | |||
| 1778 | region->numSegmentsAllocated = newAlloc; | ||
| 1779 | region->segment = newSegment; | ||
| 1780 | } | ||
| 1781 | |||
| 1782 | segment = ®ion->segment[region->numSegmentsUsed]; | ||
| 1783 | region->numSegmentsUsed++; | ||
| 1784 | |||
| 1785 | segment->virtAddr = virtAddr; | ||
| 1786 | segment->physAddr = physAddr; | ||
| 1787 | segment->numBytes = numBytes; | ||
| 1788 | |||
| 1789 | DMA_MAP_PRINT("returning success\n"); | ||
| 1790 | |||
| 1791 | return 0; | ||
| 1792 | } | ||
| 1793 | |||
| 1794 | /****************************************************************************/ | ||
| 1795 | /** | ||
| 1796 | * Adds a region of memory to a memory map. Each region is virtually | ||
| 1797 | * contiguous, but not necessarily physically contiguous. | ||
| 1798 | * | ||
| 1799 | * @return 0 on success, error code otherwise. | ||
| 1800 | */ | ||
| 1801 | /****************************************************************************/ | ||
| 1802 | |||
| 1803 | int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 1804 | void *mem, /* Virtual address that we want to get a map of */ | ||
| 1805 | size_t numBytes /* Number of bytes being mapped */ | ||
| 1806 | ) { | ||
| 1807 | unsigned long addr = (unsigned long)mem; | ||
| 1808 | unsigned int offset; | ||
| 1809 | int rc = 0; | ||
| 1810 | DMA_Region_t *region; | ||
| 1811 | dma_addr_t physAddr; | ||
| 1812 | |||
| 1813 | down(&memMap->lock); | ||
| 1814 | |||
| 1815 | DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes); | ||
| 1816 | |||
| 1817 | if (!memMap->inUse) { | ||
| 1818 | printk(KERN_ERR "%s: Make sure you call dma_map_start first\n", | ||
| 1819 | __func__); | ||
| 1820 | rc = -EINVAL; | ||
| 1821 | goto out; | ||
| 1822 | } | ||
| 1823 | |||
| 1824 | /* Reallocate to hold more regions. */ | ||
| 1825 | |||
| 1826 | if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) { | ||
| 1827 | DMA_Region_t *newRegion; | ||
| 1828 | size_t oldSize = | ||
| 1829 | memMap->numRegionsAllocated * sizeof(*newRegion); | ||
| 1830 | int newAlloc = memMap->numRegionsAllocated + 4; | ||
| 1831 | size_t newSize = newAlloc * sizeof(*newRegion); | ||
| 1832 | |||
| 1833 | newRegion = kmalloc(newSize, GFP_KERNEL); | ||
| 1834 | if (newRegion == NULL) { | ||
| 1835 | rc = -ENOMEM; | ||
| 1836 | goto out; | ||
| 1837 | } | ||
| 1838 | memcpy(newRegion, memMap->region, oldSize); | ||
| 1839 | memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize); | ||
| 1840 | |||
| 1841 | kfree(memMap->region); | ||
| 1842 | |||
| 1843 | memMap->numRegionsAllocated = newAlloc; | ||
| 1844 | memMap->region = newRegion; | ||
| 1845 | } | ||
| 1846 | |||
| 1847 | region = &memMap->region[memMap->numRegionsUsed]; | ||
| 1848 | memMap->numRegionsUsed++; | ||
| 1849 | |||
| 1850 | offset = addr & ~PAGE_MASK; | ||
| 1851 | |||
| 1852 | region->memType = dma_mem_type(mem); | ||
| 1853 | region->virtAddr = mem; | ||
| 1854 | region->numBytes = numBytes; | ||
| 1855 | region->numSegmentsUsed = 0; | ||
| 1856 | region->numLockedPages = 0; | ||
| 1857 | region->lockedPages = NULL; | ||
| 1858 | |||
| 1859 | switch (region->memType) { | ||
| 1860 | case DMA_MEM_TYPE_VMALLOC: | ||
| 1861 | { | ||
| 1862 | atomic_inc(&gDmaStatMemTypeVmalloc); | ||
| 1863 | |||
| 1864 | /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */ | ||
| 1865 | |||
| 1866 | /* vmalloc'd pages are not physically contiguous */ | ||
| 1867 | |||
| 1868 | rc = -EINVAL; | ||
| 1869 | break; | ||
| 1870 | } | ||
| 1871 | |||
| 1872 | case DMA_MEM_TYPE_KMALLOC: | ||
| 1873 | { | ||
| 1874 | atomic_inc(&gDmaStatMemTypeKmalloc); | ||
| 1875 | |||
| 1876 | /* kmalloc'd pages are physically contiguous, so they'll have exactly */ | ||
| 1877 | /* one segment */ | ||
| 1878 | |||
| 1879 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
| 1880 | physAddr = | ||
| 1881 | dma_map_single(NULL, mem, numBytes, memMap->dir); | ||
| 1882 | rc = dma_map_add_segment(memMap, region, mem, physAddr, | ||
| 1883 | numBytes); | ||
| 1884 | #else | ||
| 1885 | rc = -EINVAL; | ||
| 1886 | #endif | ||
| 1887 | break; | ||
| 1888 | } | ||
| 1889 | |||
| 1890 | case DMA_MEM_TYPE_DMA: | ||
| 1891 | { | ||
| 1892 | /* dma_alloc_xxx pages are physically contiguous */ | ||
| 1893 | |||
| 1894 | atomic_inc(&gDmaStatMemTypeCoherent); | ||
| 1895 | |||
| 1896 | physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset; | ||
| 1897 | |||
| 1898 | dma_sync_single_for_cpu(NULL, physAddr, numBytes, | ||
| 1899 | memMap->dir); | ||
| 1900 | rc = dma_map_add_segment(memMap, region, mem, physAddr, | ||
| 1901 | numBytes); | ||
| 1902 | break; | ||
| 1903 | } | ||
| 1904 | |||
| 1905 | case DMA_MEM_TYPE_USER: | ||
| 1906 | { | ||
| 1907 | size_t firstPageOffset; | ||
| 1908 | size_t firstPageSize; | ||
| 1909 | struct page **pages; | ||
| 1910 | struct task_struct *userTask; | ||
| 1911 | |||
| 1912 | atomic_inc(&gDmaStatMemTypeUser); | ||
| 1913 | |||
| 1914 | #if 1 | ||
| 1915 | /* If the pages are user pages, then the dma_mem_map_set_user_task function */ | ||
| 1916 | /* must have been previously called. */ | ||
| 1917 | |||
| 1918 | if (memMap->userTask == NULL) { | ||
| 1919 | printk(KERN_ERR | ||
| 1920 | "%s: must call dma_mem_map_set_user_task when using user-mode memory\n", | ||
| 1921 | __func__); | ||
| 1922 | return -EINVAL; | ||
| 1923 | } | ||
| 1924 | |||
| 1925 | /* User pages need to be locked. */ | ||
| 1926 | |||
| 1927 | firstPageOffset = | ||
| 1928 | (unsigned long)region->virtAddr & (PAGE_SIZE - 1); | ||
| 1929 | firstPageSize = PAGE_SIZE - firstPageOffset; | ||
| 1930 | |||
| 1931 | region->numLockedPages = (firstPageOffset | ||
| 1932 | + region->numBytes + | ||
| 1933 | PAGE_SIZE - 1) / PAGE_SIZE; | ||
| 1934 | pages = | ||
| 1935 | kmalloc(region->numLockedPages * | ||
| 1936 | sizeof(struct page *), GFP_KERNEL); | ||
| 1937 | |||
| 1938 | if (pages == NULL) { | ||
| 1939 | region->numLockedPages = 0; | ||
| 1940 | return -ENOMEM; | ||
| 1941 | } | ||
| 1942 | |||
| 1943 | userTask = memMap->userTask; | ||
| 1944 | |||
| 1945 | down_read(&userTask->mm->mmap_sem); | ||
| 1946 | rc = get_user_pages(userTask, /* task */ | ||
| 1947 | userTask->mm, /* mm */ | ||
| 1948 | (unsigned long)region->virtAddr, /* start */ | ||
| 1949 | region->numLockedPages, /* len */ | ||
| 1950 | memMap->dir == DMA_FROM_DEVICE, /* write */ | ||
| 1951 | 0, /* force */ | ||
| 1952 | pages, /* pages (array of pointers to page) */ | ||
| 1953 | NULL); /* vmas */ | ||
| 1954 | up_read(&userTask->mm->mmap_sem); | ||
| 1955 | |||
| 1956 | if (rc != region->numLockedPages) { | ||
| 1957 | kfree(pages); | ||
| 1958 | region->numLockedPages = 0; | ||
| 1959 | |||
| 1960 | if (rc >= 0) { | ||
| 1961 | rc = -EINVAL; | ||
| 1962 | } | ||
| 1963 | } else { | ||
| 1964 | uint8_t *virtAddr = region->virtAddr; | ||
| 1965 | size_t bytesRemaining; | ||
| 1966 | int pageIdx; | ||
| 1967 | |||
| 1968 | rc = 0; /* Since get_user_pages returns +ve number */ | ||
| 1969 | |||
| 1970 | region->lockedPages = pages; | ||
| 1971 | |||
| 1972 | /* We've locked the user pages. Now we need to walk them and figure */ | ||
| 1973 | /* out the physical addresses. */ | ||
| 1974 | |||
| 1975 | /* The first page may be partial */ | ||
| 1976 | |||
| 1977 | dma_map_add_segment(memMap, | ||
| 1978 | region, | ||
| 1979 | virtAddr, | ||
| 1980 | PFN_PHYS(page_to_pfn | ||
| 1981 | (pages[0])) + | ||
| 1982 | firstPageOffset, | ||
| 1983 | firstPageSize); | ||
| 1984 | |||
| 1985 | virtAddr += firstPageSize; | ||
| 1986 | bytesRemaining = | ||
| 1987 | region->numBytes - firstPageSize; | ||
| 1988 | |||
| 1989 | for (pageIdx = 1; | ||
| 1990 | pageIdx < region->numLockedPages; | ||
| 1991 | pageIdx++) { | ||
| 1992 | size_t bytesThisPage = | ||
| 1993 | (bytesRemaining > | ||
| 1994 | PAGE_SIZE ? PAGE_SIZE : | ||
| 1995 | bytesRemaining); | ||
| 1996 | |||
| 1997 | DMA_MAP_PRINT | ||
| 1998 | ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n", | ||
| 1999 | pageIdx, pages[pageIdx], | ||
| 2000 | page_to_pfn(pages[pageIdx]), | ||
| 2001 | PFN_PHYS(page_to_pfn | ||
| 2002 | (pages[pageIdx]))); | ||
| 2003 | |||
| 2004 | dma_map_add_segment(memMap, | ||
| 2005 | region, | ||
| 2006 | virtAddr, | ||
| 2007 | PFN_PHYS(page_to_pfn | ||
| 2008 | (pages | ||
| 2009 | [pageIdx])), | ||
| 2010 | bytesThisPage); | ||
| 2011 | |||
| 2012 | virtAddr += bytesThisPage; | ||
| 2013 | bytesRemaining -= bytesThisPage; | ||
| 2014 | } | ||
| 2015 | } | ||
| 2016 | #else | ||
| 2017 | printk(KERN_ERR | ||
| 2018 | "%s: User mode pages are not yet supported\n", | ||
| 2019 | __func__); | ||
| 2020 | |||
| 2021 | /* user pages are not physically contiguous */ | ||
| 2022 | |||
| 2023 | rc = -EINVAL; | ||
| 2024 | #endif | ||
| 2025 | break; | ||
| 2026 | } | ||
| 2027 | |||
| 2028 | default: | ||
| 2029 | { | ||
| 2030 | printk(KERN_ERR "%s: Unsupported memory type: %d\n", | ||
| 2031 | __func__, region->memType); | ||
| 2032 | |||
| 2033 | rc = -EINVAL; | ||
| 2034 | break; | ||
| 2035 | } | ||
| 2036 | } | ||
| 2037 | |||
| 2038 | if (rc != 0) { | ||
| 2039 | memMap->numRegionsUsed--; | ||
| 2040 | } | ||
| 2041 | |||
| 2042 | out: | ||
| 2043 | |||
| 2044 | DMA_MAP_PRINT("returning %d\n", rc); | ||
| 2045 | |||
| 2046 | up(&memMap->lock); | ||
| 2047 | |||
| 2048 | return rc; | ||
| 2049 | } | ||
| 2050 | |||
| 2051 | EXPORT_SYMBOL(dma_map_add_segment); | ||
| 2052 | |||
| 2053 | /****************************************************************************/ | ||
| 2054 | /** | ||
| 2055 | * Maps in a memory region such that it can be used for performing a DMA. | ||
| 2056 | * | ||
| 2057 | * @return 0 on success, error code otherwise. | ||
| 2058 | */ | ||
| 2059 | /****************************************************************************/ | ||
| 2060 | |||
| 2061 | int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 2062 | void *mem, /* Virtual address that we want to get a map of */ | ||
| 2063 | size_t numBytes, /* Number of bytes being mapped */ | ||
| 2064 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
| 2065 | ) { | ||
| 2066 | int rc; | ||
| 2067 | |||
| 2068 | rc = dma_map_start(memMap, dir); | ||
| 2069 | if (rc == 0) { | ||
| 2070 | rc = dma_map_add_region(memMap, mem, numBytes); | ||
| 2071 | if (rc < 0) { | ||
| 2072 | /* Since the add fails, this function will fail, and the caller won't */ | ||
| 2073 | /* call unmap, so we need to do it here. */ | ||
| 2074 | |||
| 2075 | dma_unmap(memMap, 0); | ||
| 2076 | } | ||
| 2077 | } | ||
| 2078 | |||
| 2079 | return rc; | ||
| 2080 | } | ||
| 2081 | |||
| 2082 | EXPORT_SYMBOL(dma_map_mem); | ||
| 2083 | |||
| 2084 | /****************************************************************************/ | ||
| 2085 | /** | ||
| 2086 | * Setup a descriptor ring for a given memory map. | ||
| 2087 | * | ||
| 2088 | * It is assumed that the descriptor ring has already been initialized, and | ||
| 2089 | * this routine will only reallocate a new descriptor ring if the existing | ||
| 2090 | * one is too small. | ||
| 2091 | * | ||
| 2092 | * @return 0 on success, error code otherwise. | ||
| 2093 | */ | ||
| 2094 | /****************************************************************************/ | ||
| 2095 | |||
| 2096 | int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | ||
| 2097 | DMA_MemMap_t *memMap, /* Memory map that will be used */ | ||
| 2098 | dma_addr_t devPhysAddr /* Physical address of device */ | ||
| 2099 | ) { | ||
| 2100 | int rc; | ||
| 2101 | int numDescriptors; | ||
| 2102 | DMA_DeviceAttribute_t *devAttr; | ||
| 2103 | DMA_Region_t *region; | ||
| 2104 | DMA_Segment_t *segment; | ||
| 2105 | dma_addr_t srcPhysAddr; | ||
| 2106 | dma_addr_t dstPhysAddr; | ||
| 2107 | int regionIdx; | ||
| 2108 | int segmentIdx; | ||
| 2109 | |||
| 2110 | devAttr = &DMA_gDeviceAttribute[dev]; | ||
| 2111 | |||
| 2112 | down(&memMap->lock); | ||
| 2113 | |||
| 2114 | /* Figure out how many descriptors we need */ | ||
| 2115 | |||
| 2116 | numDescriptors = 0; | ||
| 2117 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
| 2118 | region = &memMap->region[regionIdx]; | ||
| 2119 | |||
| 2120 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
| 2121 | segmentIdx++) { | ||
| 2122 | segment = ®ion->segment[segmentIdx]; | ||
| 2123 | |||
| 2124 | if (memMap->dir == DMA_TO_DEVICE) { | ||
| 2125 | srcPhysAddr = segment->physAddr; | ||
| 2126 | dstPhysAddr = devPhysAddr; | ||
| 2127 | } else { | ||
| 2128 | srcPhysAddr = devPhysAddr; | ||
| 2129 | dstPhysAddr = segment->physAddr; | ||
| 2130 | } | ||
| 2131 | |||
| 2132 | rc = | ||
| 2133 | dma_calculate_descriptor_count(dev, srcPhysAddr, | ||
| 2134 | dstPhysAddr, | ||
| 2135 | segment-> | ||
| 2136 | numBytes); | ||
| 2137 | if (rc < 0) { | ||
| 2138 | printk(KERN_ERR | ||
| 2139 | "%s: dma_calculate_descriptor_count failed: %d\n", | ||
| 2140 | __func__, rc); | ||
| 2141 | goto out; | ||
| 2142 | } | ||
| 2143 | numDescriptors += rc; | ||
| 2144 | } | ||
| 2145 | } | ||
| 2146 | |||
| 2147 | /* Adjust the size of the ring, if it isn't big enough */ | ||
| 2148 | |||
| 2149 | if (numDescriptors > devAttr->ring.descriptorsAllocated) { | ||
| 2150 | dma_free_descriptor_ring(&devAttr->ring); | ||
| 2151 | rc = | ||
| 2152 | dma_alloc_descriptor_ring(&devAttr->ring, | ||
| 2153 | numDescriptors); | ||
| 2154 | if (rc < 0) { | ||
| 2155 | printk(KERN_ERR | ||
| 2156 | "%s: dma_alloc_descriptor_ring failed: %d\n", | ||
| 2157 | __func__, rc); | ||
| 2158 | goto out; | ||
| 2159 | } | ||
| 2160 | } else { | ||
| 2161 | rc = | ||
| 2162 | dma_init_descriptor_ring(&devAttr->ring, | ||
| 2163 | numDescriptors); | ||
| 2164 | if (rc < 0) { | ||
| 2165 | printk(KERN_ERR | ||
| 2166 | "%s: dma_init_descriptor_ring failed: %d\n", | ||
| 2167 | __func__, rc); | ||
| 2168 | goto out; | ||
| 2169 | } | ||
| 2170 | } | ||
| 2171 | |||
| 2172 | /* Populate the descriptors */ | ||
| 2173 | |||
| 2174 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
| 2175 | region = &memMap->region[regionIdx]; | ||
| 2176 | |||
| 2177 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
| 2178 | segmentIdx++) { | ||
| 2179 | segment = ®ion->segment[segmentIdx]; | ||
| 2180 | |||
| 2181 | if (memMap->dir == DMA_TO_DEVICE) { | ||
| 2182 | srcPhysAddr = segment->physAddr; | ||
| 2183 | dstPhysAddr = devPhysAddr; | ||
| 2184 | } else { | ||
| 2185 | srcPhysAddr = devPhysAddr; | ||
| 2186 | dstPhysAddr = segment->physAddr; | ||
| 2187 | } | ||
| 2188 | |||
| 2189 | rc = | ||
| 2190 | dma_add_descriptors(&devAttr->ring, dev, | ||
| 2191 | srcPhysAddr, dstPhysAddr, | ||
| 2192 | segment->numBytes); | ||
| 2193 | if (rc < 0) { | ||
| 2194 | printk(KERN_ERR | ||
| 2195 | "%s: dma_add_descriptors failed: %d\n", | ||
| 2196 | __func__, rc); | ||
| 2197 | goto out; | ||
| 2198 | } | ||
| 2199 | } | ||
| 2200 | } | ||
| 2201 | |||
| 2202 | rc = 0; | ||
| 2203 | |||
| 2204 | out: | ||
| 2205 | |||
| 2206 | up(&memMap->lock); | ||
| 2207 | return rc; | ||
| 2208 | } | ||
| 2209 | |||
| 2210 | EXPORT_SYMBOL(dma_map_create_descriptor_ring); | ||
| 2211 | |||
| 2212 | /****************************************************************************/ | ||
| 2213 | /** | ||
| 2214 | * Maps in a memory region such that it can be used for performing a DMA. | ||
| 2215 | * | ||
| 2216 | * @return | ||
| 2217 | */ | ||
| 2218 | /****************************************************************************/ | ||
| 2219 | |||
| 2220 | int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 2221 | int dirtied /* non-zero if any of the pages were modified */ | ||
| 2222 | ) { | ||
| 2223 | int regionIdx; | ||
| 2224 | int segmentIdx; | ||
| 2225 | DMA_Region_t *region; | ||
| 2226 | DMA_Segment_t *segment; | ||
| 2227 | |||
| 2228 | for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) { | ||
| 2229 | region = &memMap->region[regionIdx]; | ||
| 2230 | |||
| 2231 | for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed; | ||
| 2232 | segmentIdx++) { | ||
| 2233 | segment = ®ion->segment[segmentIdx]; | ||
| 2234 | |||
| 2235 | switch (region->memType) { | ||
| 2236 | case DMA_MEM_TYPE_VMALLOC: | ||
| 2237 | { | ||
| 2238 | printk(KERN_ERR | ||
| 2239 | "%s: vmalloc'd pages are not yet supported\n", | ||
| 2240 | __func__); | ||
| 2241 | return -EINVAL; | ||
| 2242 | } | ||
| 2243 | |||
| 2244 | case DMA_MEM_TYPE_KMALLOC: | ||
| 2245 | { | ||
| 2246 | #if ALLOW_MAP_OF_KMALLOC_MEMORY | ||
| 2247 | dma_unmap_single(NULL, | ||
| 2248 | segment->physAddr, | ||
| 2249 | segment->numBytes, | ||
| 2250 | memMap->dir); | ||
| 2251 | #endif | ||
| 2252 | break; | ||
| 2253 | } | ||
| 2254 | |||
| 2255 | case DMA_MEM_TYPE_DMA: | ||
| 2256 | { | ||
| 2257 | dma_sync_single_for_cpu(NULL, | ||
| 2258 | segment-> | ||
| 2259 | physAddr, | ||
| 2260 | segment-> | ||
| 2261 | numBytes, | ||
| 2262 | memMap->dir); | ||
| 2263 | break; | ||
| 2264 | } | ||
| 2265 | |||
| 2266 | case DMA_MEM_TYPE_USER: | ||
| 2267 | { | ||
| 2268 | /* Nothing to do here. */ | ||
| 2269 | |||
| 2270 | break; | ||
| 2271 | } | ||
| 2272 | |||
| 2273 | default: | ||
| 2274 | { | ||
| 2275 | printk(KERN_ERR | ||
| 2276 | "%s: Unsupported memory type: %d\n", | ||
| 2277 | __func__, region->memType); | ||
| 2278 | return -EINVAL; | ||
| 2279 | } | ||
| 2280 | } | ||
| 2281 | |||
| 2282 | segment->virtAddr = NULL; | ||
| 2283 | segment->physAddr = 0; | ||
| 2284 | segment->numBytes = 0; | ||
| 2285 | } | ||
| 2286 | |||
| 2287 | if (region->numLockedPages > 0) { | ||
| 2288 | int pageIdx; | ||
| 2289 | |||
| 2290 | /* Some user pages were locked. We need to go and unlock them now. */ | ||
| 2291 | |||
| 2292 | for (pageIdx = 0; pageIdx < region->numLockedPages; | ||
| 2293 | pageIdx++) { | ||
| 2294 | struct page *page = | ||
| 2295 | region->lockedPages[pageIdx]; | ||
| 2296 | |||
| 2297 | if (memMap->dir == DMA_FROM_DEVICE) { | ||
| 2298 | SetPageDirty(page); | ||
| 2299 | } | ||
| 2300 | page_cache_release(page); | ||
| 2301 | } | ||
| 2302 | kfree(region->lockedPages); | ||
| 2303 | region->numLockedPages = 0; | ||
| 2304 | region->lockedPages = NULL; | ||
| 2305 | } | ||
| 2306 | |||
| 2307 | region->memType = DMA_MEM_TYPE_NONE; | ||
| 2308 | region->virtAddr = NULL; | ||
| 2309 | region->numBytes = 0; | ||
| 2310 | region->numSegmentsUsed = 0; | ||
| 2311 | } | ||
| 2312 | memMap->userTask = NULL; | ||
| 2313 | memMap->numRegionsUsed = 0; | ||
| 2314 | memMap->inUse = 0; | ||
| 2315 | |||
| 2316 | up(&memMap->lock); | ||
| 2317 | |||
| 2318 | return 0; | ||
| 2319 | } | ||
| 2320 | |||
| 2321 | EXPORT_SYMBOL(dma_unmap); | ||
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c new file mode 100644 index 000000000000..ca0ad736870b --- /dev/null +++ b/arch/arm/mach-bcmring/dma_device.c | |||
| @@ -0,0 +1,593 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dma_device.c | ||
| 18 | * | ||
| 19 | * @brief private array of DMA_DeviceAttribute_t | ||
| 20 | */ | ||
| 21 | /****************************************************************************/ | ||
| 22 | |||
| 23 | DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = { | ||
| 24 | [DMA_DEVICE_MEM_TO_MEM] = /* MEM 2 MEM */ | ||
| 25 | { | ||
| 26 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 27 | .name = "mem-to-mem", | ||
| 28 | .config = { | ||
| 29 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 30 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 31 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, | ||
| 32 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 33 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 34 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 35 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 36 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 37 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 38 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 39 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 40 | |||
| 41 | }, | ||
| 42 | }, | ||
| 43 | [DMA_DEVICE_VPM_MEM_TO_MEM] = /* VPM */ | ||
| 44 | { | ||
| 45 | .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR, | ||
| 46 | .name = "vpm", | ||
| 47 | .dedicatedController = 0, | ||
| 48 | .dedicatedChannel = 0, | ||
| 49 | /* reserve DMA0:0 for VPM */ | ||
| 50 | }, | ||
| 51 | [DMA_DEVICE_NAND_MEM_TO_MEM] = /* NAND */ | ||
| 52 | { | ||
| 53 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 54 | .name = "nand", | ||
| 55 | .config = { | ||
| 56 | .srcPeripheralPort = 0, | ||
| 57 | .dstPeripheralPort = 0, | ||
| 58 | .srcStatusRegisterAddress = 0x00000000, | ||
| 59 | .dstStatusRegisterAddress = 0x00000000, | ||
| 60 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, | ||
| 61 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 62 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 63 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 64 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 65 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 66 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 67 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 68 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 69 | .channelPriority = dmacHw_CHANNEL_PRIORITY_6, | ||
| 70 | }, | ||
| 71 | }, | ||
| 72 | [DMA_DEVICE_PIF_MEM_TO_DEV] = /* PIF TX */ | ||
| 73 | { | ||
| 74 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1 | ||
| 75 | | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO | ||
| 76 | | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC, | ||
| 77 | .name = "pif_tx", | ||
| 78 | .dmacPort = {14, 5}, | ||
| 79 | .config = { | ||
| 80 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 81 | /* dstPeripheralPort = 5 or 14 */ | ||
| 82 | .srcStatusRegisterAddress = 0x00000000, | ||
| 83 | .dstStatusRegisterAddress = 0x00000000, | ||
| 84 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 85 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 86 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 87 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 88 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 89 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 90 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 91 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 92 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 93 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 94 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 95 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 96 | .maxDataPerBlock = 16256, | ||
| 97 | }, | ||
| 98 | }, | ||
| 99 | [DMA_DEVICE_PIF_DEV_TO_MEM] = /* PIF RX */ | ||
| 100 | { | ||
| 101 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1 | ||
| 102 | | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO | ||
| 103 | /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */ | ||
| 104 | | DMA_DEVICE_FLAG_PORT_PER_DMAC, | ||
| 105 | .name = "pif_rx", | ||
| 106 | .dmacPort = {14, 5}, | ||
| 107 | .config = { | ||
| 108 | /* srcPeripheralPort = 5 or 14 */ | ||
| 109 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 110 | .srcStatusRegisterAddress = 0x00000000, | ||
| 111 | .dstStatusRegisterAddress = 0x00000000, | ||
| 112 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 113 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 114 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 115 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 116 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 117 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 118 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 119 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 120 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 121 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 122 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 123 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 124 | .maxDataPerBlock = 16256, | ||
| 125 | }, | ||
| 126 | }, | ||
| 127 | [DMA_DEVICE_I2S0_DEV_TO_MEM] = /* I2S RX */ | ||
| 128 | { | ||
| 129 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 130 | .name = "i2s0_rx", | ||
| 131 | .config = { | ||
| 132 | .srcPeripheralPort = 0, /* SRC: I2S0 */ | ||
| 133 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 134 | .srcStatusRegisterAddress = 0, | ||
| 135 | .dstStatusRegisterAddress = 0, | ||
| 136 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 137 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 138 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 139 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16, | ||
| 140 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 141 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 142 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, | ||
| 143 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 144 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 145 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 146 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 147 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 148 | }, | ||
| 149 | }, | ||
| 150 | [DMA_DEVICE_I2S0_MEM_TO_DEV] = /* I2S TX */ | ||
| 151 | { | ||
| 152 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 153 | .name = "i2s0_tx", | ||
| 154 | .config = { | ||
| 155 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 156 | .dstPeripheralPort = 1, /* DST: I2S0 */ | ||
| 157 | .srcStatusRegisterAddress = 0, | ||
| 158 | .dstStatusRegisterAddress = 0, | ||
| 159 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 160 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 161 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 162 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 163 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16, | ||
| 164 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, | ||
| 165 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 166 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 167 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 168 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 169 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 170 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 171 | }, | ||
| 172 | }, | ||
| 173 | [DMA_DEVICE_I2S1_DEV_TO_MEM] = /* I2S1 RX */ | ||
| 174 | { | ||
| 175 | .flags = DMA_DEVICE_FLAG_ON_DMA1, | ||
| 176 | .name = "i2s1_rx", | ||
| 177 | .config = { | ||
| 178 | .srcPeripheralPort = 2, /* SRC: I2S1 */ | ||
| 179 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 180 | .srcStatusRegisterAddress = 0, | ||
| 181 | .dstStatusRegisterAddress = 0, | ||
| 182 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 183 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 184 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 185 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16, | ||
| 186 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 187 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 188 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, | ||
| 189 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 190 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 191 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 192 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 193 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 194 | }, | ||
| 195 | }, | ||
| 196 | [DMA_DEVICE_I2S1_MEM_TO_DEV] = /* I2S1 TX */ | ||
| 197 | { | ||
| 198 | .flags = DMA_DEVICE_FLAG_ON_DMA1, | ||
| 199 | .name = "i2s1_tx", | ||
| 200 | .config = { | ||
| 201 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 202 | .dstPeripheralPort = 3, /* DST: I2S1 */ | ||
| 203 | .srcStatusRegisterAddress = 0, | ||
| 204 | .dstStatusRegisterAddress = 0, | ||
| 205 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 206 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 207 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 208 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 209 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16, | ||
| 210 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, | ||
| 211 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 212 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 213 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 214 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 215 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 216 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 217 | }, | ||
| 218 | }, | ||
| 219 | [DMA_DEVICE_ESW_MEM_TO_DEV] = /* ESW TX */ | ||
| 220 | { | ||
| 221 | .name = "esw_tx", | ||
| 222 | .flags = DMA_DEVICE_FLAG_IS_DEDICATED, | ||
| 223 | .dedicatedController = 1, | ||
| 224 | .dedicatedChannel = 3, | ||
| 225 | .config = { | ||
| 226 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 227 | .dstPeripheralPort = 1, /* DST: ESW (MTP) */ | ||
| 228 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 229 | .errorInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 230 | /* DMAx_AHB_SSTATARy */ | ||
| 231 | .srcStatusRegisterAddress = 0x00000000, | ||
| 232 | /* DMAx_AHB_DSTATARy */ | ||
| 233 | .dstStatusRegisterAddress = 0x30490010, | ||
| 234 | /* DMAx_AHB_CFGy */ | ||
| 235 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 236 | /* DMAx_AHB_CTLy */ | ||
| 237 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 238 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 239 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 240 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0, | ||
| 241 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 242 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 243 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 244 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 245 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 246 | }, | ||
| 247 | }, | ||
| 248 | [DMA_DEVICE_ESW_DEV_TO_MEM] = /* ESW RX */ | ||
| 249 | { | ||
| 250 | .name = "esw_rx", | ||
| 251 | .flags = DMA_DEVICE_FLAG_IS_DEDICATED, | ||
| 252 | .dedicatedController = 1, | ||
| 253 | .dedicatedChannel = 2, | ||
| 254 | .config = { | ||
| 255 | .srcPeripheralPort = 0, /* SRC: ESW (PTM) */ | ||
| 256 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 257 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 258 | .errorInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 259 | /* DMAx_AHB_SSTATARy */ | ||
| 260 | .srcStatusRegisterAddress = 0x30480010, | ||
| 261 | /* DMAx_AHB_DSTATARy */ | ||
| 262 | .dstStatusRegisterAddress = 0x00000000, | ||
| 263 | /* DMAx_AHB_CFGy */ | ||
| 264 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 265 | /* DMAx_AHB_CTLy */ | ||
| 266 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 267 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 268 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 269 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 270 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0, | ||
| 271 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 272 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 273 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 274 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 275 | }, | ||
| 276 | }, | ||
| 277 | [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] = /* APM Codec A Ingress */ | ||
| 278 | { | ||
| 279 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 280 | .name = "apm_a_rx", | ||
| 281 | .config = { | ||
| 282 | .srcPeripheralPort = 2, /* SRC: Codec A Ingress FIFO */ | ||
| 283 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 284 | .srcStatusRegisterAddress = 0x00000000, | ||
| 285 | .dstStatusRegisterAddress = 0x00000000, | ||
| 286 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 287 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 288 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 289 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 290 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 291 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 292 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 293 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 294 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 295 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 296 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 297 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 298 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 299 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 300 | }, | ||
| 301 | }, | ||
| 302 | [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] = /* APM Codec A Egress */ | ||
| 303 | { | ||
| 304 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 305 | .name = "apm_a_tx", | ||
| 306 | .config = { | ||
| 307 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 308 | .dstPeripheralPort = 3, /* DST: Codec A Egress FIFO */ | ||
| 309 | .srcStatusRegisterAddress = 0x00000000, | ||
| 310 | .dstStatusRegisterAddress = 0x00000000, | ||
| 311 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 312 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 313 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 314 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 315 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 316 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 317 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 318 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 319 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 320 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 321 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 322 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 323 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 324 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 325 | }, | ||
| 326 | }, | ||
| 327 | [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] = /* APM Codec B Ingress */ | ||
| 328 | { | ||
| 329 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 330 | .name = "apm_b_rx", | ||
| 331 | .config = { | ||
| 332 | .srcPeripheralPort = 4, /* SRC: Codec B Ingress FIFO */ | ||
| 333 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 334 | .srcStatusRegisterAddress = 0x00000000, | ||
| 335 | .dstStatusRegisterAddress = 0x00000000, | ||
| 336 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 337 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 338 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 339 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 340 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 341 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 342 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 343 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 344 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 345 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 346 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 347 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 348 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 349 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 350 | }, | ||
| 351 | }, | ||
| 352 | [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] = /* APM Codec B Egress */ | ||
| 353 | { | ||
| 354 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 355 | .name = "apm_b_tx", | ||
| 356 | .config = { | ||
| 357 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 358 | .dstPeripheralPort = 5, /* DST: Codec B Egress FIFO */ | ||
| 359 | .srcStatusRegisterAddress = 0x00000000, | ||
| 360 | .dstStatusRegisterAddress = 0x00000000, | ||
| 361 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 362 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 363 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 364 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 365 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 366 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 367 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 368 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 369 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 370 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 371 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 372 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 373 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 374 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 375 | }, | ||
| 376 | }, | ||
| 377 | [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] = /* APM Codec C Ingress */ | ||
| 378 | { | ||
| 379 | .flags = DMA_DEVICE_FLAG_ON_DMA1, | ||
| 380 | .name = "apm_c_rx", | ||
| 381 | .config = { | ||
| 382 | .srcPeripheralPort = 4, /* SRC: Codec C Ingress FIFO */ | ||
| 383 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 384 | .srcStatusRegisterAddress = 0x00000000, | ||
| 385 | .dstStatusRegisterAddress = 0x00000000, | ||
| 386 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 387 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 388 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 389 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 390 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 391 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 392 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 393 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 394 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 395 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 396 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 397 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 398 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 399 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 400 | }, | ||
| 401 | }, | ||
| 402 | [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] = /* PCM0 RX */ | ||
| 403 | { | ||
| 404 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 405 | .name = "pcm0_rx", | ||
| 406 | .config = { | ||
| 407 | .srcPeripheralPort = 12, /* SRC: PCM0 */ | ||
| 408 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 409 | .srcStatusRegisterAddress = 0, | ||
| 410 | .dstStatusRegisterAddress = 0, | ||
| 411 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 412 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 413 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 414 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 415 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 416 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 417 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 418 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 419 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 420 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 421 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 422 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 423 | }, | ||
| 424 | }, | ||
| 425 | [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] = /* PCM0 TX */ | ||
| 426 | { | ||
| 427 | .flags = DMA_DEVICE_FLAG_ON_DMA0, | ||
| 428 | .name = "pcm0_tx", | ||
| 429 | .config = { | ||
| 430 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 431 | .dstPeripheralPort = 13, /* DST: PCM0 */ | ||
| 432 | .srcStatusRegisterAddress = 0, | ||
| 433 | .dstStatusRegisterAddress = 0, | ||
| 434 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 435 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 436 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 437 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 438 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 439 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 440 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 441 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 442 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 443 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 444 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 445 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 446 | }, | ||
| 447 | }, | ||
| 448 | [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] = /* PCM1 RX */ | ||
| 449 | { | ||
| 450 | .flags = DMA_DEVICE_FLAG_ON_DMA1, | ||
| 451 | .name = "pcm1_rx", | ||
| 452 | .config = { | ||
| 453 | .srcPeripheralPort = 14, /* SRC: PCM1 */ | ||
| 454 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 455 | .srcStatusRegisterAddress = 0, | ||
| 456 | .dstStatusRegisterAddress = 0, | ||
| 457 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 458 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 459 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 460 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 461 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 462 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 463 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4, | ||
| 464 | .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 465 | .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 466 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 467 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 468 | .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS, | ||
| 469 | }, | ||
| 470 | }, | ||
| 471 | [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] = /* PCM1 TX */ | ||
| 472 | { | ||
| 473 | .flags = DMA_DEVICE_FLAG_ON_DMA1, | ||
| 474 | .name = "pcm1_tx", | ||
| 475 | .config = { | ||
| 476 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 477 | .dstPeripheralPort = 15, /* DST: PCM1 */ | ||
| 478 | .srcStatusRegisterAddress = 0, | ||
| 479 | .dstStatusRegisterAddress = 0, | ||
| 480 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 481 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 482 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 483 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 484 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 485 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4, | ||
| 486 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 487 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 488 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 489 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 490 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 491 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 492 | }, | ||
| 493 | }, | ||
| 494 | [DMA_DEVICE_SPUM_DEV_TO_MEM] = /* SPUM RX */ | ||
| 495 | { | ||
| 496 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 497 | .name = "spum_rx", | ||
| 498 | .config = { | ||
| 499 | .srcPeripheralPort = 6, /* SRC: Codec A Ingress FIFO */ | ||
| 500 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 501 | .srcStatusRegisterAddress = 0x00000000, | ||
| 502 | .dstStatusRegisterAddress = 0x00000000, | ||
| 503 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 504 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 505 | .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 506 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 507 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 508 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 509 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 510 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 511 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 512 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 513 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 514 | /* Busrt size **MUST** be 16 for SPUM to work */ | ||
| 515 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16, | ||
| 516 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16, | ||
| 517 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 518 | /* on the RX side, SPU needs to be the flow controller */ | ||
| 519 | .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL, | ||
| 520 | }, | ||
| 521 | }, | ||
| 522 | [DMA_DEVICE_SPUM_MEM_TO_DEV] = /* SPUM TX */ | ||
| 523 | { | ||
| 524 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 525 | .name = "spum_tx", | ||
| 526 | .config = { | ||
| 527 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 528 | .dstPeripheralPort = 7, /* DST: SPUM */ | ||
| 529 | .srcStatusRegisterAddress = 0x00000000, | ||
| 530 | .dstStatusRegisterAddress = 0x00000000, | ||
| 531 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 532 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 533 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 534 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 535 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 536 | .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE, | ||
| 537 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 538 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 539 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 540 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32, | ||
| 541 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32, | ||
| 542 | /* Busrt size **MUST** be 16 for SPUM to work */ | ||
| 543 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16, | ||
| 544 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16, | ||
| 545 | .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST, | ||
| 546 | }, | ||
| 547 | }, | ||
| 548 | [DMA_DEVICE_MEM_TO_VRAM] = /* MEM 2 VRAM */ | ||
| 549 | { | ||
| 550 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 551 | .name = "mem-to-vram", | ||
| 552 | .config = { | ||
| 553 | .srcPeripheralPort = 0, /* SRC: memory */ | ||
| 554 | .srcStatusRegisterAddress = 0x00000000, | ||
| 555 | .dstStatusRegisterAddress = 0x00000000, | ||
| 556 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 557 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 558 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, | ||
| 559 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1, | ||
| 560 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2, | ||
| 561 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 562 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 563 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 564 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 565 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 566 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 567 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 568 | }, | ||
| 569 | }, | ||
| 570 | [DMA_DEVICE_VRAM_TO_MEM] = /* VRAM 2 MEM */ | ||
| 571 | { | ||
| 572 | .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1, | ||
| 573 | .name = "vram-to-mem", | ||
| 574 | .config = { | ||
| 575 | .dstPeripheralPort = 0, /* DST: memory */ | ||
| 576 | .srcStatusRegisterAddress = 0x00000000, | ||
| 577 | .dstStatusRegisterAddress = 0x00000000, | ||
| 578 | .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC, | ||
| 579 | .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC, | ||
| 580 | .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM, | ||
| 581 | .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2, | ||
| 582 | .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1, | ||
| 583 | .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 584 | .errorInterrupt = dmacHw_INTERRUPT_ENABLE, | ||
| 585 | .channelPriority = dmacHw_CHANNEL_PRIORITY_7, | ||
| 586 | .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64, | ||
| 587 | .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64, | ||
| 588 | .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8, | ||
| 589 | .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8, | ||
| 590 | }, | ||
| 591 | }, | ||
| 592 | }; | ||
| 593 | EXPORT_SYMBOL(DMA_gDeviceAttribute); /* primarily for dma-test.c */ | ||
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h new file mode 100644 index 000000000000..f01da877148e --- /dev/null +++ b/arch/arm/mach-bcmring/include/cfg_global.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef _CFG_GLOBAL_H_ | ||
| 2 | #define _CFG_GLOBAL_H_ | ||
| 3 | |||
| 4 | #include <cfg_global_defines.h> | ||
| 5 | |||
| 6 | #define CFG_GLOBAL_CHIP BCM11107 | ||
| 7 | #define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING | ||
| 8 | #define CFG_GLOBAL_CHIP_REV 0xB0 | ||
| 9 | #define CFG_GLOBAL_RAM_SIZE 0x10000000 | ||
| 10 | #define CFG_GLOBAL_RAM_BASE 0x00000000 | ||
| 11 | #define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000 | ||
| 12 | |||
| 13 | #endif /* _CFG_GLOBAL_H_ */ | ||
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h new file mode 100644 index 000000000000..b5beb0b30734 --- /dev/null +++ b/arch/arm/mach-bcmring/include/cfg_global_defines.h | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CFG_GLOBAL_DEFINES_H | ||
| 16 | #define CFG_GLOBAL_DEFINES_H | ||
| 17 | |||
| 18 | /* CHIP */ | ||
| 19 | #define BCM1103 1 | ||
| 20 | |||
| 21 | #define BCM1191 4 | ||
| 22 | #define BCM2153 5 | ||
| 23 | #define BCM2820 6 | ||
| 24 | |||
| 25 | #define BCM2826 8 | ||
| 26 | #define FPGA11107 9 | ||
| 27 | #define BCM11107 10 | ||
| 28 | #define BCM11109 11 | ||
| 29 | #define BCM11170 12 | ||
| 30 | #define BCM11110 13 | ||
| 31 | #define BCM11211 14 | ||
| 32 | |||
| 33 | /* CFG_GLOBAL_CHIP_FAMILY types */ | ||
| 34 | #define CFG_GLOBAL_CHIP_FAMILY_NONE 0 | ||
| 35 | #define CFG_GLOBAL_CHIP_FAMILY_BCM116X 2 | ||
| 36 | #define CFG_GLOBAL_CHIP_FAMILY_BCMRING 4 | ||
| 37 | #define CFG_GLOBAL_CHIP_FAMILY_BCM1103 8 | ||
| 38 | |||
| 39 | #define IMAGE_HEADER_SIZE_CHECKSUM 4 | ||
| 40 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h new file mode 100644 index 000000000000..caa20e59db99 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/cache.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CSP_CACHE_H | ||
| 16 | #define CSP_CACHE_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 19 | |||
| 20 | #include <csp/stdint.h> | ||
| 21 | |||
| 22 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 23 | |||
| 24 | #if defined(__KERNEL__) && !defined(STANDALONE) | ||
| 25 | #include <asm/cacheflush.h> | ||
| 26 | |||
| 27 | #define CSP_CACHE_FLUSH_ALL flush_cache_all() | ||
| 28 | |||
| 29 | #else | ||
| 30 | |||
| 31 | #define CSP_CACHE_FLUSH_ALL | ||
| 32 | |||
| 33 | #endif | ||
| 34 | |||
| 35 | #endif /* CSP_CACHE_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h new file mode 100644 index 000000000000..8b3d80367293 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/delay.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | #ifndef CSP_DELAY_H | ||
| 17 | #define CSP_DELAY_H | ||
| 18 | |||
| 19 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 20 | |||
| 21 | /* Some CSP routines require use of the following delay routines. Use the OS */ | ||
| 22 | /* version if available, otherwise use a CSP specific definition. */ | ||
| 23 | /* void udelay(unsigned long usecs); */ | ||
| 24 | /* void mdelay(unsigned long msecs); */ | ||
| 25 | |||
| 26 | #if defined(__KERNEL__) && !defined(STANDALONE) | ||
| 27 | #include <linux/delay.h> | ||
| 28 | #else | ||
| 29 | #include <mach/csp/delay.h> | ||
| 30 | #endif | ||
| 31 | |||
| 32 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 33 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 34 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 35 | |||
| 36 | #endif /* CSP_DELAY_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h new file mode 100644 index 000000000000..5d510130a25f --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h | |||
| @@ -0,0 +1,596 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dmacHw.h | ||
| 18 | * | ||
| 19 | * @brief API definitions for low level DMA controller driver | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | #ifndef _DMACHW_H | ||
| 24 | #define _DMACHW_H | ||
| 25 | |||
| 26 | #include <stddef.h> | ||
| 27 | |||
| 28 | #include <csp/stdint.h> | ||
| 29 | #include <mach/csp/dmacHw_reg.h> | ||
| 30 | |||
| 31 | /* Define DMA Channel ID using DMA controller number (m) and channel number (c). | ||
| 32 | |||
| 33 | System specific channel ID should be defined as follows | ||
| 34 | |||
| 35 | For example: | ||
| 36 | |||
| 37 | #include <dmacHw.h> | ||
| 38 | ... | ||
| 39 | #define systemHw_LCD_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,5) | ||
| 40 | #define systemHw_SWITCH_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,0) | ||
| 41 | #define systemHw_SWITCH_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,1) | ||
| 42 | #define systemHw_APM_RX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,3) | ||
| 43 | #define systemHw_APM_TX_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,4) | ||
| 44 | ... | ||
| 45 | #define systemHw_SHARED1_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,4) | ||
| 46 | #define systemHw_SHARED2_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(1,5) | ||
| 47 | #define systemHw_SHARED3_CHANNEL_ID dmacHw_MAKE_CHANNEL_ID(0,6) | ||
| 48 | ... | ||
| 49 | */ | ||
| 50 | #define dmacHw_MAKE_CHANNEL_ID(m, c) (m << 8 | c) | ||
| 51 | |||
| 52 | typedef enum { | ||
| 53 | dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0, /* Channel priority 0. Lowest priority DMA channel */ | ||
| 54 | dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1, /* Channel priority 1 */ | ||
| 55 | dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2, /* Channel priority 2 */ | ||
| 56 | dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3, /* Channel priority 3 */ | ||
| 57 | dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4, /* Channel priority 4 */ | ||
| 58 | dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5, /* Channel priority 5 */ | ||
| 59 | dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6, /* Channel priority 6 */ | ||
| 60 | dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7 /* Channel priority 7. Highest priority DMA channel */ | ||
| 61 | } dmacHw_CHANNEL_PRIORITY_e; | ||
| 62 | |||
| 63 | /* Source destination master interface */ | ||
| 64 | typedef enum { | ||
| 65 | dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1, /* Source DMA master interface 1 */ | ||
| 66 | dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2, /* Source DMA master interface 2 */ | ||
| 67 | dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1, /* Destination DMA master interface 1 */ | ||
| 68 | dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2 /* Destination DMA master interface 2 */ | ||
| 69 | } dmacHw_MASTER_INTERFACE_e; | ||
| 70 | |||
| 71 | typedef enum { | ||
| 72 | dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit (1 byte) per transaction */ | ||
| 73 | dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16, /* Source 16 bit (2 byte) per transaction */ | ||
| 74 | dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32, /* Source 32 bit (4 byte) per transaction */ | ||
| 75 | dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64, /* Source 64 bit (8 byte) per transaction */ | ||
| 76 | dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit (1 byte) per transaction */ | ||
| 77 | dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16, /* Destination 16 bit (2 byte) per transaction */ | ||
| 78 | dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32, /* Destination 32 bit (4 byte) per transaction */ | ||
| 79 | dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64 /* Destination 64 bit (8 byte) per transaction */ | ||
| 80 | } dmacHw_TRANSACTION_WIDTH_e; | ||
| 81 | |||
| 82 | typedef enum { | ||
| 83 | dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0, /* Source No burst */ | ||
| 84 | dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4, /* Source 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 85 | dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8, /* Source 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 86 | dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16, /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 87 | dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0, /* Destination No burst */ | ||
| 88 | dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4, /* Destination 4 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 89 | dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8, /* Destination 8 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 90 | dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */ | ||
| 91 | } dmacHw_BURST_WIDTH_e; | ||
| 92 | |||
| 93 | typedef enum { | ||
| 94 | dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC, /* Memory to memory transfer */ | ||
| 95 | dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC, /* Peripheral to memory transfer */ | ||
| 96 | dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC, /* Memory to peripheral transfer */ | ||
| 97 | dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC /* Peripheral to peripheral transfer */ | ||
| 98 | } dmacHw_TRANSFER_TYPE_e; | ||
| 99 | |||
| 100 | typedef enum { | ||
| 101 | dmacHw_TRANSFER_MODE_PERREQUEST, /* Block transfer per DMA request */ | ||
| 102 | dmacHw_TRANSFER_MODE_CONTINUOUS, /* Continuous transfer of streaming data */ | ||
| 103 | dmacHw_TRANSFER_MODE_PERIODIC /* Periodic transfer of streaming data */ | ||
| 104 | } dmacHw_TRANSFER_MODE_e; | ||
| 105 | |||
| 106 | typedef enum { | ||
| 107 | dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC, /* Increment source address after every transaction */ | ||
| 108 | dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC, /* Decrement source address after every transaction */ | ||
| 109 | dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC, /* Increment destination address after every transaction */ | ||
| 110 | dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC, /* Decrement destination address after every transaction */ | ||
| 111 | dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC, /* No change in source address after every transaction */ | ||
| 112 | dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC /* No change in destination address after every transaction */ | ||
| 113 | } dmacHw_ADDRESS_UPDATE_MODE_e; | ||
| 114 | |||
| 115 | typedef enum { | ||
| 116 | dmacHw_FLOW_CONTROL_DMA, /* DMA working as flow controller (default) */ | ||
| 117 | dmacHw_FLOW_CONTROL_PERIPHERAL /* Peripheral working as flow controller */ | ||
| 118 | } dmacHw_FLOW_CONTROL_e; | ||
| 119 | |||
| 120 | typedef enum { | ||
| 121 | dmacHw_TRANSFER_STATUS_BUSY, /* DMA Transfer ongoing */ | ||
| 122 | dmacHw_TRANSFER_STATUS_DONE, /* DMA Transfer completed */ | ||
| 123 | dmacHw_TRANSFER_STATUS_ERROR /* DMA Transfer error */ | ||
| 124 | } dmacHw_TRANSFER_STATUS_e; | ||
| 125 | |||
| 126 | typedef enum { | ||
| 127 | dmacHw_INTERRUPT_DISABLE, /* Interrupt disable */ | ||
| 128 | dmacHw_INTERRUPT_ENABLE /* Interrupt enable */ | ||
| 129 | } dmacHw_INTERRUPT_e; | ||
| 130 | |||
| 131 | typedef enum { | ||
| 132 | dmacHw_INTERRUPT_STATUS_NONE = 0x0, /* No DMA interrupt */ | ||
| 133 | dmacHw_INTERRUPT_STATUS_TRANS = 0x1, /* End of DMA transfer interrupt */ | ||
| 134 | dmacHw_INTERRUPT_STATUS_BLOCK = 0x2, /* End of block transfer interrupt */ | ||
| 135 | dmacHw_INTERRUPT_STATUS_ERROR = 0x4 /* Error interrupt */ | ||
| 136 | } dmacHw_INTERRUPT_STATUS_e; | ||
| 137 | |||
| 138 | typedef enum { | ||
| 139 | dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM, /* Number of DMA channel */ | ||
| 140 | dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE, /* Maximum channel burst size */ | ||
| 141 | dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM, /* Number of DMA master interface */ | ||
| 142 | dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH, /* Channel Data bus width */ | ||
| 143 | dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE /* Channel FIFO size */ | ||
| 144 | } dmacHw_CONTROLLER_ATTRIB_e; | ||
| 145 | |||
| 146 | typedef unsigned long dmacHw_HANDLE_t; /* DMA channel handle */ | ||
| 147 | typedef uint32_t dmacHw_ID_t; /* DMA channel Id. Must be created using | ||
| 148 | "dmacHw_MAKE_CHANNEL_ID" macro | ||
| 149 | */ | ||
| 150 | /* DMA channel configuration parameters */ | ||
| 151 | typedef struct { | ||
| 152 | uint32_t srcPeripheralPort; /* Source peripheral port */ | ||
| 153 | uint32_t dstPeripheralPort; /* Destination peripheral port */ | ||
| 154 | uint32_t srcStatusRegisterAddress; /* Source status register address */ | ||
| 155 | uint32_t dstStatusRegisterAddress; /* Destination status register address of type */ | ||
| 156 | |||
| 157 | uint32_t srcGatherWidth; /* Number of bytes gathered before successive gather opearation */ | ||
| 158 | uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */ | ||
| 159 | uint32_t dstScatterWidth; /* Number of bytes sacattered before successive scatter opearation */ | ||
| 160 | uint32_t dstScatterJump; /* Number of bytes jumpped before successive scatter opearation */ | ||
| 161 | uint32_t maxDataPerBlock; /* Maximum number of bytes to be transferred per block/descrptor. | ||
| 162 | 0 = Maximum possible. | ||
| 163 | */ | ||
| 164 | |||
| 165 | dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */ | ||
| 166 | dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */ | ||
| 167 | dmacHw_TRANSFER_TYPE_e transferType; /* DMA transfer type */ | ||
| 168 | dmacHw_TRANSFER_MODE_e transferMode; /* DMA transfer mode */ | ||
| 169 | dmacHw_MASTER_INTERFACE_e srcMasterInterface; /* DMA source interface */ | ||
| 170 | dmacHw_MASTER_INTERFACE_e dstMasterInterface; /* DMA destination interface */ | ||
| 171 | dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth; /* Source transaction width */ | ||
| 172 | dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth; /* Destination transaction width */ | ||
| 173 | dmacHw_BURST_WIDTH_e srcMaxBurstWidth; /* Source burst width */ | ||
| 174 | dmacHw_BURST_WIDTH_e dstMaxBurstWidth; /* Destination burst width */ | ||
| 175 | dmacHw_INTERRUPT_e blockTransferInterrupt; /* Block trsnafer interrupt */ | ||
| 176 | dmacHw_INTERRUPT_e completeTransferInterrupt; /* Complete DMA trsnafer interrupt */ | ||
| 177 | dmacHw_INTERRUPT_e errorInterrupt; /* Error interrupt */ | ||
| 178 | dmacHw_CHANNEL_PRIORITY_e channelPriority; /* Channel priority */ | ||
| 179 | dmacHw_FLOW_CONTROL_e flowControler; /* Data flow controller */ | ||
| 180 | } dmacHw_CONFIG_t; | ||
| 181 | |||
| 182 | /****************************************************************************/ | ||
| 183 | /** | ||
| 184 | * @brief Initializes DMA | ||
| 185 | * | ||
| 186 | * This function initializes DMA CSP driver | ||
| 187 | * | ||
| 188 | * @note | ||
| 189 | * Must be called before using any DMA channel | ||
| 190 | */ | ||
| 191 | /****************************************************************************/ | ||
| 192 | void dmacHw_initDma(void); | ||
| 193 | |||
| 194 | /****************************************************************************/ | ||
| 195 | /** | ||
| 196 | * @brief Exit function for DMA | ||
| 197 | * | ||
| 198 | * This function isolates DMA from the system | ||
| 199 | * | ||
| 200 | */ | ||
| 201 | /****************************************************************************/ | ||
| 202 | void dmacHw_exitDma(void); | ||
| 203 | |||
| 204 | /****************************************************************************/ | ||
| 205 | /** | ||
| 206 | * @brief Gets a handle to a DMA channel | ||
| 207 | * | ||
| 208 | * This function returns a handle, representing a control block of a particular DMA channel | ||
| 209 | * | ||
| 210 | * @return -1 - On Failure | ||
| 211 | * handle - On Success, representing a channel control block | ||
| 212 | * | ||
| 213 | * @note | ||
| 214 | * None Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro | ||
| 215 | */ | ||
| 216 | /****************************************************************************/ | ||
| 217 | dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId /* [ IN ] DMA Channel Id */ | ||
| 218 | ); | ||
| 219 | |||
| 220 | /****************************************************************************/ | ||
| 221 | /** | ||
| 222 | * @brief Initializes a DMA channel for use | ||
| 223 | * | ||
| 224 | * This function initializes and resets a DMA channel for use | ||
| 225 | * | ||
| 226 | * @return -1 - On Failure | ||
| 227 | * 0 - On Success | ||
| 228 | * | ||
| 229 | * @note | ||
| 230 | * None | ||
| 231 | */ | ||
| 232 | /****************************************************************************/ | ||
| 233 | int dmacHw_initChannel(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 234 | ); | ||
| 235 | |||
| 236 | /****************************************************************************/ | ||
| 237 | /** | ||
| 238 | * @brief Estimates number of descriptor needed to perform certain DMA transfer | ||
| 239 | * | ||
| 240 | * | ||
| 241 | * @return On failure : -1 | ||
| 242 | * On success : Number of descriptor count | ||
| 243 | * | ||
| 244 | * | ||
| 245 | */ | ||
| 246 | /****************************************************************************/ | ||
| 247 | int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 248 | void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ | ||
| 249 | void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ | ||
| 250 | size_t dataLen /* [ IN ] Data length in bytes */ | ||
| 251 | ); | ||
| 252 | |||
| 253 | /****************************************************************************/ | ||
| 254 | /** | ||
| 255 | * @brief Initializes descriptor ring | ||
| 256 | * | ||
| 257 | * This function will initializes the descriptor ring of a DMA channel | ||
| 258 | * | ||
| 259 | * | ||
| 260 | * @return -1 - On failure | ||
| 261 | * 0 - On success | ||
| 262 | * @note | ||
| 263 | * - "len" parameter should be obtained from "dmacHw_descriptorLen" | ||
| 264 | * - Descriptor buffer MUST be 32 bit aligned and uncached as it | ||
| 265 | * is accessed by ARM and DMA | ||
| 266 | */ | ||
| 267 | /****************************************************************************/ | ||
| 268 | int dmacHw_initDescriptor(void *pDescriptorVirt, /* [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */ | ||
| 269 | uint32_t descriptorPhyAddr, /* [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */ | ||
| 270 | uint32_t len, /* [ IN ] Size of the pBuf */ | ||
| 271 | uint32_t num /* [ IN ] Number of descriptor in the ring */ | ||
| 272 | ); | ||
| 273 | |||
| 274 | /****************************************************************************/ | ||
| 275 | /** | ||
| 276 | * @brief Finds amount of memory required to form a descriptor ring | ||
| 277 | * | ||
| 278 | * | ||
| 279 | * @return Number of bytes required to form a descriptor ring | ||
| 280 | * | ||
| 281 | * | ||
| 282 | * @note | ||
| 283 | * None | ||
| 284 | */ | ||
| 285 | /****************************************************************************/ | ||
| 286 | uint32_t dmacHw_descriptorLen(uint32_t descCnt /* [ IN ] Number of descriptor in the ring */ | ||
| 287 | ); | ||
| 288 | |||
| 289 | /****************************************************************************/ | ||
| 290 | /** | ||
| 291 | * @brief Configure DMA channel | ||
| 292 | * | ||
| 293 | * @return 0 : On success | ||
| 294 | * -1 : On failure | ||
| 295 | */ | ||
| 296 | /****************************************************************************/ | ||
| 297 | int dmacHw_configChannel(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 298 | dmacHw_CONFIG_t *pConfig /* [ IN ] Configuration settings */ | ||
| 299 | ); | ||
| 300 | |||
| 301 | /****************************************************************************/ | ||
| 302 | /** | ||
| 303 | * @brief Set descriptors for known data length | ||
| 304 | * | ||
| 305 | * When DMA has to work as a flow controller, this function prepares the | ||
| 306 | * descriptor chain to transfer data | ||
| 307 | * | ||
| 308 | * from: | ||
| 309 | * - Memory to memory | ||
| 310 | * - Peripheral to memory | ||
| 311 | * - Memory to Peripheral | ||
| 312 | * - Peripheral to Peripheral | ||
| 313 | * | ||
| 314 | * @return -1 - On failure | ||
| 315 | * 0 - On success | ||
| 316 | * | ||
| 317 | */ | ||
| 318 | /****************************************************************************/ | ||
| 319 | int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 320 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 321 | void *pSrcAddr, /* [ IN ] Source (Peripheral/Memory) address */ | ||
| 322 | void *pDstAddr, /* [ IN ] Destination (Peripheral/Memory) address */ | ||
| 323 | size_t dataLen /* [ IN ] Length in bytes */ | ||
| 324 | ); | ||
| 325 | |||
| 326 | /****************************************************************************/ | ||
| 327 | /** | ||
| 328 | * @brief Indicates whether DMA transfer is in progress or completed | ||
| 329 | * | ||
| 330 | * @return DMA transfer status | ||
| 331 | * dmacHw_TRANSFER_STATUS_BUSY: DMA Transfer ongoing | ||
| 332 | * dmacHw_TRANSFER_STATUS_DONE: DMA Transfer completed | ||
| 333 | * dmacHw_TRANSFER_STATUS_ERROR: DMA Transfer error | ||
| 334 | * | ||
| 335 | */ | ||
| 336 | /****************************************************************************/ | ||
| 337 | dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 338 | ); | ||
| 339 | |||
| 340 | /****************************************************************************/ | ||
| 341 | /** | ||
| 342 | * @brief Set descriptor carrying control information | ||
| 343 | * | ||
| 344 | * This function will be used to send specific control information to the device | ||
| 345 | * using the DMA channel | ||
| 346 | * | ||
| 347 | * | ||
| 348 | * @return -1 - On failure | ||
| 349 | * 0 - On success | ||
| 350 | * | ||
| 351 | * @note | ||
| 352 | * None | ||
| 353 | */ | ||
| 354 | /****************************************************************************/ | ||
| 355 | int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 356 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 357 | uint32_t ctlAddress, /* [ IN ] Address of the device control register */ | ||
| 358 | uint32_t control /* [ IN ] Device control information */ | ||
| 359 | ); | ||
| 360 | |||
| 361 | /****************************************************************************/ | ||
| 362 | /** | ||
| 363 | * @brief Read data DMA transferred to memory | ||
| 364 | * | ||
| 365 | * This function will read data that has been DMAed to memory while transfering from: | ||
| 366 | * - Memory to memory | ||
| 367 | * - Peripheral to memory | ||
| 368 | * | ||
| 369 | * @return 0 - No more data is available to read | ||
| 370 | * 1 - More data might be available to read | ||
| 371 | * | ||
| 372 | */ | ||
| 373 | /****************************************************************************/ | ||
| 374 | int dmacHw_readTransferredData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 375 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 376 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 377 | void **ppBbuf, /* [ OUT ] Data received */ | ||
| 378 | size_t *pLlen /* [ OUT ] Length of the data received */ | ||
| 379 | ); | ||
| 380 | |||
| 381 | /****************************************************************************/ | ||
| 382 | /** | ||
| 383 | * @brief Prepares descriptor ring, when source peripheral working as a flow controller | ||
| 384 | * | ||
| 385 | * This function will form the descriptor ring by allocating buffers, when source peripheral | ||
| 386 | * has to work as a flow controller to transfer data from: | ||
| 387 | * - Peripheral to memory. | ||
| 388 | * | ||
| 389 | * @return -1 - On failure | ||
| 390 | * 0 - On success | ||
| 391 | * | ||
| 392 | * | ||
| 393 | * @note | ||
| 394 | * None | ||
| 395 | */ | ||
| 396 | /****************************************************************************/ | ||
| 397 | int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 398 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 399 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 400 | uint32_t srcAddr, /* [ IN ] Source peripheral address */ | ||
| 401 | void *(*fpAlloc) (int len), /* [ IN ] Function pointer that provides destination memory */ | ||
| 402 | int len, /* [ IN ] Number of bytes "fpAlloc" will allocate for destination */ | ||
| 403 | int num /* [ IN ] Number of descriptor to set */ | ||
| 404 | ); | ||
| 405 | |||
| 406 | /****************************************************************************/ | ||
| 407 | /** | ||
| 408 | * @brief Program channel register to initiate transfer | ||
| 409 | * | ||
| 410 | * @return void | ||
| 411 | * | ||
| 412 | * | ||
| 413 | * @note | ||
| 414 | * - Descriptor buffer MUST ALWAYS be flushed before calling this function | ||
| 415 | * - This function should also be called from ISR to program the channel with | ||
| 416 | * pending descriptors | ||
| 417 | */ | ||
| 418 | /****************************************************************************/ | ||
| 419 | void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 420 | dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 421 | void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 422 | ); | ||
| 423 | |||
| 424 | /****************************************************************************/ | ||
| 425 | /** | ||
| 426 | * @brief Resets descriptor control information | ||
| 427 | * | ||
| 428 | * @return void | ||
| 429 | */ | ||
| 430 | /****************************************************************************/ | ||
| 431 | void dmacHw_resetDescriptorControl(void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 432 | ); | ||
| 433 | |||
| 434 | /****************************************************************************/ | ||
| 435 | /** | ||
| 436 | * @brief Program channel register to stop transfer | ||
| 437 | * | ||
| 438 | * Ensures the channel is not doing any transfer after calling this function | ||
| 439 | * | ||
| 440 | * @return void | ||
| 441 | * | ||
| 442 | */ | ||
| 443 | /****************************************************************************/ | ||
| 444 | void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 445 | ); | ||
| 446 | |||
| 447 | /****************************************************************************/ | ||
| 448 | /** | ||
| 449 | * @brief Check the existance of pending descriptor | ||
| 450 | * | ||
| 451 | * This function confirmes if there is any pending descriptor in the chain | ||
| 452 | * to program the channel | ||
| 453 | * | ||
| 454 | * @return 1 : Channel need to be programmed with pending descriptor | ||
| 455 | * 0 : No more pending descriptor to programe the channel | ||
| 456 | * | ||
| 457 | * @note | ||
| 458 | * - This function should be called from ISR in case there are pending | ||
| 459 | * descriptor to program the channel. | ||
| 460 | * | ||
| 461 | * Example: | ||
| 462 | * | ||
| 463 | * dmac_isr () | ||
| 464 | * { | ||
| 465 | * ... | ||
| 466 | * if (dmacHw_descriptorPending (handle)) | ||
| 467 | * { | ||
| 468 | * dmacHw_initiateTransfer (handle); | ||
| 469 | * } | ||
| 470 | * } | ||
| 471 | * | ||
| 472 | */ | ||
| 473 | /****************************************************************************/ | ||
| 474 | uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 475 | void *pDescriptor /* [ IN ] Descriptor buffer */ | ||
| 476 | ); | ||
| 477 | |||
| 478 | /****************************************************************************/ | ||
| 479 | /** | ||
| 480 | * @brief Deallocates source or destination memory, allocated | ||
| 481 | * | ||
| 482 | * This function can be called to deallocate data memory that was DMAed successfully | ||
| 483 | * | ||
| 484 | * @return -1 - On failure | ||
| 485 | * 0 - On success | ||
| 486 | * | ||
| 487 | * @note | ||
| 488 | * This function will be called ONLY, when source OR destination address is pointing | ||
| 489 | * to dynamic memory | ||
| 490 | */ | ||
| 491 | /****************************************************************************/ | ||
| 492 | int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig, /* [ IN ] Configuration settings */ | ||
| 493 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 494 | void (*fpFree) (void *) /* [ IN ] Function pointer to free data memory */ | ||
| 495 | ); | ||
| 496 | |||
| 497 | /****************************************************************************/ | ||
| 498 | /** | ||
| 499 | * @brief Clears the interrupt | ||
| 500 | * | ||
| 501 | * This function clears the DMA channel specific interrupt | ||
| 502 | * | ||
| 503 | * @return N/A | ||
| 504 | * | ||
| 505 | * @note | ||
| 506 | * Must be called under the context of ISR | ||
| 507 | */ | ||
| 508 | /****************************************************************************/ | ||
| 509 | void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 510 | ); | ||
| 511 | |||
| 512 | /****************************************************************************/ | ||
| 513 | /** | ||
| 514 | * @brief Returns the cause of channel specific DMA interrupt | ||
| 515 | * | ||
| 516 | * This function returns the cause of interrupt | ||
| 517 | * | ||
| 518 | * @return Interrupt status, each bit representing a specific type of interrupt | ||
| 519 | * of type dmacHw_INTERRUPT_STATUS_e | ||
| 520 | * @note | ||
| 521 | * This function should be called under the context of ISR | ||
| 522 | */ | ||
| 523 | /****************************************************************************/ | ||
| 524 | dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 525 | ); | ||
| 526 | |||
| 527 | /****************************************************************************/ | ||
| 528 | /** | ||
| 529 | * @brief Indentifies a DMA channel causing interrupt | ||
| 530 | * | ||
| 531 | * This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e | ||
| 532 | * | ||
| 533 | * @return NULL : No channel causing DMA interrupt | ||
| 534 | * ! NULL : Handle to a channel causing DMA interrupt | ||
| 535 | * @note | ||
| 536 | * dmacHw_clearInterrupt() must be called with a valid handle after calling this function | ||
| 537 | */ | ||
| 538 | /****************************************************************************/ | ||
| 539 | dmacHw_HANDLE_t dmacHw_getInterruptSource(void); | ||
| 540 | |||
| 541 | /****************************************************************************/ | ||
| 542 | /** | ||
| 543 | * @brief Sets channel specific user data | ||
| 544 | * | ||
| 545 | * This function associates user data to a specif DMA channel | ||
| 546 | * | ||
| 547 | */ | ||
| 548 | /****************************************************************************/ | ||
| 549 | void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 550 | void *userData /* [ IN ] User data */ | ||
| 551 | ); | ||
| 552 | |||
| 553 | /****************************************************************************/ | ||
| 554 | /** | ||
| 555 | * @brief Gets channel specific user data | ||
| 556 | * | ||
| 557 | * This function returns user data specific to a DMA channel | ||
| 558 | * | ||
| 559 | * @return user data | ||
| 560 | */ | ||
| 561 | /****************************************************************************/ | ||
| 562 | void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle /* [ IN ] DMA Channel handle */ | ||
| 563 | ); | ||
| 564 | |||
| 565 | /****************************************************************************/ | ||
| 566 | /** | ||
| 567 | * @brief Displays channel specific registers and other control parameters | ||
| 568 | * | ||
| 569 | * | ||
| 570 | * @return void | ||
| 571 | * | ||
| 572 | * @note | ||
| 573 | * None | ||
| 574 | */ | ||
| 575 | /****************************************************************************/ | ||
| 576 | void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 577 | void *pDescriptor, /* [ IN ] Descriptor buffer */ | ||
| 578 | int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ | ||
| 579 | ); | ||
| 580 | |||
| 581 | /****************************************************************************/ | ||
| 582 | /** | ||
| 583 | * @brief Provides DMA controller attributes | ||
| 584 | * | ||
| 585 | * | ||
| 586 | * @return DMA controller attributes | ||
| 587 | * | ||
| 588 | * @note | ||
| 589 | * None | ||
| 590 | */ | ||
| 591 | /****************************************************************************/ | ||
| 592 | uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle, /* [ IN ] DMA Channel handle */ | ||
| 593 | dmacHw_CONTROLLER_ATTRIB_e attr /* [ IN ] DMA Controler attribute of type dmacHw_CONTROLLER_ATTRIB_e */ | ||
| 594 | ); | ||
| 595 | |||
| 596 | #endif /* _DMACHW_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h new file mode 100644 index 000000000000..51357dd5b666 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/errno.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CSP_ERRNO_H | ||
| 16 | #define CSP_ERRNO_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 19 | |||
| 20 | #if defined(__KERNEL__) | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #elif defined(CSP_SIMULATION) | ||
| 23 | #include <asm-generic/errno.h> | ||
| 24 | #else | ||
| 25 | #include <errno.h> | ||
| 26 | #endif | ||
| 27 | |||
| 28 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 29 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 30 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 31 | |||
| 32 | #endif /* CSP_ERRNO_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h new file mode 100644 index 000000000000..1c639c8ee08f --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/intcHw.h | |||
| @@ -0,0 +1,40 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | /****************************************************************************/ | ||
| 17 | /** | ||
| 18 | * @file intcHw.h | ||
| 19 | * | ||
| 20 | * @brief generic interrupt controller API | ||
| 21 | * | ||
| 22 | * @note | ||
| 23 | * None | ||
| 24 | */ | ||
| 25 | /****************************************************************************/ | ||
| 26 | |||
| 27 | #ifndef _INTCHW_H | ||
| 28 | #define _INTCHW_H | ||
| 29 | |||
| 30 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 31 | #include <mach/csp/intcHw_reg.h> | ||
| 32 | |||
| 33 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 34 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 35 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 36 | static inline void intcHw_irq_disable(void *basep, uint32_t mask); | ||
| 37 | static inline void intcHw_irq_enable(void *basep, uint32_t mask); | ||
| 38 | |||
| 39 | #endif /* _INTCHW_H */ | ||
| 40 | |||
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h new file mode 100644 index 000000000000..c30d2a5975a6 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/module.h | |||
| @@ -0,0 +1,32 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | #ifndef CSP_MODULE_H | ||
| 17 | #define CSP_MODULE_H | ||
| 18 | |||
| 19 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 20 | |||
| 21 | #ifdef __KERNEL__ | ||
| 22 | #include <linux/module.h> | ||
| 23 | #else | ||
| 24 | #define EXPORT_SYMBOL(symbol) | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 28 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 29 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 30 | |||
| 31 | |||
| 32 | #endif /* CSP_MODULE_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h new file mode 100644 index 000000000000..e5f60bf5a1f3 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/reg.h | |||
| @@ -0,0 +1,114 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file reg.h | ||
| 18 | * | ||
| 19 | * @brief Generic register defintions used in CSP | ||
| 20 | */ | ||
| 21 | /****************************************************************************/ | ||
| 22 | |||
| 23 | #ifndef CSP_REG_H | ||
| 24 | #define CSP_REG_H | ||
| 25 | |||
| 26 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 27 | |||
| 28 | #include <csp/stdint.h> | ||
| 29 | |||
| 30 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 31 | |||
| 32 | #define __REG32(x) (*((volatile uint32_t *)(x))) | ||
| 33 | #define __REG16(x) (*((volatile uint16_t *)(x))) | ||
| 34 | #define __REG8(x) (*((volatile uint8_t *) (x))) | ||
| 35 | |||
| 36 | /* Macros used to define a sequence of reserved registers. The start / end */ | ||
| 37 | /* are byte offsets in the particular register definition, with the "end" */ | ||
| 38 | /* being the offset of the next un-reserved register. E.g. if offsets */ | ||
| 39 | /* 0x10 through to 0x1f are reserved, then this reserved area could be */ | ||
| 40 | /* specified as follows. */ | ||
| 41 | /* typedef struct */ | ||
| 42 | /* { */ | ||
| 43 | /* uint32_t reg1; offset 0x00 */ | ||
| 44 | /* uint32_t reg2; offset 0x04 */ | ||
| 45 | /* uint32_t reg3; offset 0x08 */ | ||
| 46 | /* uint32_t reg4; offset 0x0c */ | ||
| 47 | /* REG32_RSVD(0x10, 0x20); */ | ||
| 48 | /* uint32_t reg5; offset 0x20 */ | ||
| 49 | /* ... */ | ||
| 50 | /* } EXAMPLE_REG_t; */ | ||
| 51 | #define REG8_RSVD(start, end) uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)] | ||
| 52 | #define REG16_RSVD(start, end) uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)] | ||
| 53 | #define REG32_RSVD(start, end) uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)] | ||
| 54 | |||
| 55 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 56 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 57 | |||
| 58 | /* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */ | ||
| 59 | /* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the */ | ||
| 60 | /* flags variable to be declared locally. */ | ||
| 61 | /* e.g. */ | ||
| 62 | /* statement1; */ | ||
| 63 | /* { */ | ||
| 64 | /* REG_LOCAL_IRQ_SAVE; */ | ||
| 65 | /* <multiple statements here> */ | ||
| 66 | /* REG_LOCAL_IRQ_RESTORE; */ | ||
| 67 | /* } */ | ||
| 68 | /* statement2; */ | ||
| 69 | /* */ | ||
| 70 | |||
| 71 | #if defined(__KERNEL__) && !defined(STANDALONE) | ||
| 72 | #include <mach/hardware.h> | ||
| 73 | #include <linux/interrupt.h> | ||
| 74 | |||
| 75 | #define REG_LOCAL_IRQ_SAVE HW_DECLARE_SPINLOCK(reg32) \ | ||
| 76 | unsigned long flags; HW_IRQ_SAVE(reg32, flags) | ||
| 77 | |||
| 78 | #define REG_LOCAL_IRQ_RESTORE HW_IRQ_RESTORE(reg32, flags) | ||
| 79 | |||
| 80 | #else | ||
| 81 | |||
| 82 | #define REG_LOCAL_IRQ_SAVE | ||
| 83 | #define REG_LOCAL_IRQ_RESTORE | ||
| 84 | |||
| 85 | #endif | ||
| 86 | |||
| 87 | static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value) | ||
| 88 | { | ||
| 89 | REG_LOCAL_IRQ_SAVE; | ||
| 90 | *reg &= value; | ||
| 91 | REG_LOCAL_IRQ_RESTORE; | ||
| 92 | } | ||
| 93 | |||
| 94 | static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value) | ||
| 95 | { | ||
| 96 | REG_LOCAL_IRQ_SAVE; | ||
| 97 | *reg |= value; | ||
| 98 | REG_LOCAL_IRQ_RESTORE; | ||
| 99 | } | ||
| 100 | |||
| 101 | static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask, | ||
| 102 | uint32_t value) | ||
| 103 | { | ||
| 104 | REG_LOCAL_IRQ_SAVE; | ||
| 105 | *reg = (*reg & mask) | value; | ||
| 106 | REG_LOCAL_IRQ_RESTORE; | ||
| 107 | } | ||
| 108 | |||
| 109 | static inline void reg32_write(volatile uint32_t *reg, uint32_t value) | ||
| 110 | { | ||
| 111 | *reg = value; | ||
| 112 | } | ||
| 113 | |||
| 114 | #endif /* CSP_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h new file mode 100644 index 000000000000..b9d7e0732dfc --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/secHw.h | |||
| @@ -0,0 +1,65 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file secHw.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for accessing low level security features | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | #ifndef SECHW_H | ||
| 24 | #define SECHW_H | ||
| 25 | |||
| 26 | typedef void (*secHw_FUNC_t) (void); | ||
| 27 | |||
| 28 | typedef enum { | ||
| 29 | secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */ | ||
| 30 | secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */ | ||
| 31 | } secHw_MODE; | ||
| 32 | |||
| 33 | /****************************************************************************/ | ||
| 34 | /** | ||
| 35 | * @brief Requesting to execute the function in secure mode | ||
| 36 | * | ||
| 37 | * This function requests the given function to run in secure mode | ||
| 38 | * | ||
| 39 | */ | ||
| 40 | /****************************************************************************/ | ||
| 41 | void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */ | ||
| 42 | ); | ||
| 43 | |||
| 44 | /****************************************************************************/ | ||
| 45 | /** | ||
| 46 | * @brief Sets the mode | ||
| 47 | * | ||
| 48 | * his function sets the processor mode (secure/non-secure) | ||
| 49 | * | ||
| 50 | */ | ||
| 51 | /****************************************************************************/ | ||
| 52 | void secHw_SetMode(secHw_MODE /* Processor mode */ | ||
| 53 | ); | ||
| 54 | |||
| 55 | /****************************************************************************/ | ||
| 56 | /** | ||
| 57 | * @brief Get the current mode | ||
| 58 | * | ||
| 59 | * This function retieves the processor mode (secure/non-secure) | ||
| 60 | * | ||
| 61 | */ | ||
| 62 | /****************************************************************************/ | ||
| 63 | void secHw_GetMode(secHw_MODE *); | ||
| 64 | |||
| 65 | #endif /* SECHW_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h new file mode 100644 index 000000000000..3a8718bbf700 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/stdint.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CSP_STDINT_H | ||
| 16 | #define CSP_STDINT_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 19 | |||
| 20 | #ifdef __KERNEL__ | ||
| 21 | #include <linux/types.h> | ||
| 22 | #else | ||
| 23 | #include <stdint.h> | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 27 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 28 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 29 | |||
| 30 | #endif /* CSP_STDINT_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h new file mode 100644 index 000000000000..ad9e4005f141 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/string.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | |||
| 17 | #ifndef CSP_STRING_H | ||
| 18 | #define CSP_STRING_H | ||
| 19 | |||
| 20 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 21 | |||
| 22 | #ifdef __KERNEL__ | ||
| 23 | #include <linux/string.h> | ||
| 24 | #else | ||
| 25 | #include <string.h> | ||
| 26 | #endif | ||
| 27 | |||
| 28 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 29 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 30 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 31 | |||
| 32 | |||
| 33 | #endif /* CSP_STRING_H */ | ||
| 34 | |||
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h new file mode 100644 index 000000000000..f1236d00cb97 --- /dev/null +++ b/arch/arm/mach-bcmring/include/csp/tmrHw.h | |||
| @@ -0,0 +1,263 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file tmrHw.h | ||
| 18 | * | ||
| 19 | * @brief API definitions for low level Timer driver | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | #ifndef _TMRHW_H | ||
| 24 | #define _TMRHW_H | ||
| 25 | |||
| 26 | #include <csp/stdint.h> | ||
| 27 | |||
| 28 | typedef uint32_t tmrHw_ID_t; /* Timer ID */ | ||
| 29 | typedef uint32_t tmrHw_COUNT_t; /* Timer count */ | ||
| 30 | typedef uint32_t tmrHw_INTERVAL_t; /* Timer interval */ | ||
| 31 | typedef uint32_t tmrHw_RATE_t; /* Timer event (count/interrupt) rate */ | ||
| 32 | |||
| 33 | typedef enum { | ||
| 34 | tmrHw_INTERRUPT_STATUS_SET, /* Interrupted */ | ||
| 35 | tmrHw_INTERRUPT_STATUS_UNSET /* No Interrupt */ | ||
| 36 | } tmrHw_INTERRUPT_STATUS_e; | ||
| 37 | |||
| 38 | typedef enum { | ||
| 39 | tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */ | ||
| 40 | tmrHw_CAPABILITY_RESOLUTION /* Timer resolution in bits */ | ||
| 41 | } tmrHw_CAPABILITY_e; | ||
| 42 | |||
| 43 | /****************************************************************************/ | ||
| 44 | /** | ||
| 45 | * @brief Get timer capability | ||
| 46 | * | ||
| 47 | * This function returns various capabilities/attributes of a timer | ||
| 48 | * | ||
| 49 | * @return Numeric capability | ||
| 50 | * | ||
| 51 | */ | ||
| 52 | /****************************************************************************/ | ||
| 53 | uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 54 | tmrHw_CAPABILITY_e capability /* [ IN ] Timer capability */ | ||
| 55 | ); | ||
| 56 | |||
| 57 | /****************************************************************************/ | ||
| 58 | /** | ||
| 59 | * @brief Configures a periodic timer in terms of timer interrupt rate | ||
| 60 | * | ||
| 61 | * This function initializes a periodic timer to generate specific number of | ||
| 62 | * timer interrupt per second | ||
| 63 | * | ||
| 64 | * @return On success: Effective timer frequency | ||
| 65 | * On failure: 0 | ||
| 66 | * | ||
| 67 | */ | ||
| 68 | /****************************************************************************/ | ||
| 69 | tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 70 | tmrHw_RATE_t rate /* [ IN ] Number of timer interrupt per second */ | ||
| 71 | ); | ||
| 72 | |||
| 73 | /****************************************************************************/ | ||
| 74 | /** | ||
| 75 | * @brief Configures a periodic timer to generate timer interrupt after | ||
| 76 | * certain time interval | ||
| 77 | * | ||
| 78 | * This function initializes a periodic timer to generate timer interrupt | ||
| 79 | * after every time interval in milisecond | ||
| 80 | * | ||
| 81 | * @return On success: Effective interval set in mili-second | ||
| 82 | * On failure: 0 | ||
| 83 | * | ||
| 84 | */ | ||
| 85 | /****************************************************************************/ | ||
| 86 | tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 87 | tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ | ||
| 88 | ); | ||
| 89 | |||
| 90 | /****************************************************************************/ | ||
| 91 | /** | ||
| 92 | * @brief Configures a periodic timer to generate timer interrupt just once | ||
| 93 | * after certain time interval | ||
| 94 | * | ||
| 95 | * This function initializes a periodic timer to generate a single ticks after | ||
| 96 | * certain time interval in milisecond | ||
| 97 | * | ||
| 98 | * @return On success: Effective interval set in mili-second | ||
| 99 | * On failure: 0 | ||
| 100 | * | ||
| 101 | */ | ||
| 102 | /****************************************************************************/ | ||
| 103 | tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 104 | tmrHw_INTERVAL_t msec /* [ IN ] Interval in mili-second */ | ||
| 105 | ); | ||
| 106 | |||
| 107 | /****************************************************************************/ | ||
| 108 | /** | ||
| 109 | * @brief Configures a timer to run as a free running timer | ||
| 110 | * | ||
| 111 | * This function initializes a timer to run as a free running timer | ||
| 112 | * | ||
| 113 | * @return Timer resolution (count / sec) | ||
| 114 | * | ||
| 115 | */ | ||
| 116 | /****************************************************************************/ | ||
| 117 | tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId, /* [ IN ] Timer Id */ | ||
| 118 | uint32_t divider /* [ IN ] Dividing the clock frequency */ | ||
| 119 | ) __attribute__ ((section(".aramtext"))); | ||
| 120 | |||
| 121 | /****************************************************************************/ | ||
| 122 | /** | ||
| 123 | * @brief Starts a timer | ||
| 124 | * | ||
| 125 | * This function starts a preconfigured timer | ||
| 126 | * | ||
| 127 | * @return -1 - On Failure | ||
| 128 | * 0 - On Success | ||
| 129 | */ | ||
| 130 | /****************************************************************************/ | ||
| 131 | int tmrHw_startTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 132 | ) __attribute__ ((section(".aramtext"))); | ||
| 133 | |||
| 134 | /****************************************************************************/ | ||
| 135 | /** | ||
| 136 | * @brief Stops a timer | ||
| 137 | * | ||
| 138 | * This function stops a running timer | ||
| 139 | * | ||
| 140 | * @return -1 - On Failure | ||
| 141 | * 0 - On Success | ||
| 142 | */ | ||
| 143 | /****************************************************************************/ | ||
| 144 | int tmrHw_stopTimer(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 145 | ); | ||
| 146 | |||
| 147 | /****************************************************************************/ | ||
| 148 | /** | ||
| 149 | * @brief Gets current timer count | ||
| 150 | * | ||
| 151 | * This function returns the current timer value | ||
| 152 | * | ||
| 153 | * @return Current downcounting timer value | ||
| 154 | * | ||
| 155 | */ | ||
| 156 | /****************************************************************************/ | ||
| 157 | tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 158 | ) __attribute__ ((section(".aramtext"))); | ||
| 159 | |||
| 160 | /****************************************************************************/ | ||
| 161 | /** | ||
| 162 | * @brief Gets timer count rate | ||
| 163 | * | ||
| 164 | * This function returns the number of counts per second | ||
| 165 | * | ||
| 166 | * @return Count rate | ||
| 167 | * | ||
| 168 | */ | ||
| 169 | /****************************************************************************/ | ||
| 170 | tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 171 | ) __attribute__ ((section(".aramtext"))); | ||
| 172 | |||
| 173 | /****************************************************************************/ | ||
| 174 | /** | ||
| 175 | * @brief Enables timer interrupt | ||
| 176 | * | ||
| 177 | * This function enables the timer interrupt | ||
| 178 | * | ||
| 179 | * @return N/A | ||
| 180 | * | ||
| 181 | */ | ||
| 182 | /****************************************************************************/ | ||
| 183 | void tmrHw_enableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 184 | ); | ||
| 185 | |||
| 186 | /****************************************************************************/ | ||
| 187 | /** | ||
| 188 | * @brief Disables timer interrupt | ||
| 189 | * | ||
| 190 | * This function disable the timer interrupt | ||
| 191 | * | ||
| 192 | * @return N/A | ||
| 193 | */ | ||
| 194 | /****************************************************************************/ | ||
| 195 | void tmrHw_disableInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 196 | ); | ||
| 197 | |||
| 198 | /****************************************************************************/ | ||
| 199 | /** | ||
| 200 | * @brief Clears the interrupt | ||
| 201 | * | ||
| 202 | * This function clears the timer interrupt | ||
| 203 | * | ||
| 204 | * @return N/A | ||
| 205 | * | ||
| 206 | * @note | ||
| 207 | * Must be called under the context of ISR | ||
| 208 | */ | ||
| 209 | /****************************************************************************/ | ||
| 210 | void tmrHw_clearInterrupt(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 211 | ); | ||
| 212 | |||
| 213 | /****************************************************************************/ | ||
| 214 | /** | ||
| 215 | * @brief Gets the interrupt status | ||
| 216 | * | ||
| 217 | * This function returns timer interrupt status | ||
| 218 | * | ||
| 219 | * @return Interrupt status | ||
| 220 | */ | ||
| 221 | /****************************************************************************/ | ||
| 222 | tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId /* [ IN ] Timer id */ | ||
| 223 | ); | ||
| 224 | |||
| 225 | /****************************************************************************/ | ||
| 226 | /** | ||
| 227 | * @brief Indentifies a timer causing interrupt | ||
| 228 | * | ||
| 229 | * This functions returns a timer causing interrupt | ||
| 230 | * | ||
| 231 | * @return 0xFFFFFFFF : No timer causing an interrupt | ||
| 232 | * ! 0xFFFFFFFF : timer causing an interrupt | ||
| 233 | * @note | ||
| 234 | * tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function | ||
| 235 | */ | ||
| 236 | /****************************************************************************/ | ||
| 237 | tmrHw_ID_t tmrHw_getInterruptSource(void); | ||
| 238 | |||
| 239 | /****************************************************************************/ | ||
| 240 | /** | ||
| 241 | * @brief Displays specific timer registers | ||
| 242 | * | ||
| 243 | * | ||
| 244 | * @return void | ||
| 245 | * | ||
| 246 | */ | ||
| 247 | /****************************************************************************/ | ||
| 248 | void tmrHw_printDebugInfo(tmrHw_ID_t timerId, /* [ IN ] Timer id */ | ||
| 249 | int (*fpPrint) (const char *, ...) /* [ IN ] Print callback function */ | ||
| 250 | ); | ||
| 251 | |||
| 252 | /****************************************************************************/ | ||
| 253 | /** | ||
| 254 | * @brief Use a timer to perform a busy wait delay for a number of usecs. | ||
| 255 | * | ||
| 256 | * @return N/A | ||
| 257 | */ | ||
| 258 | /****************************************************************************/ | ||
| 259 | void tmrHw_udelay(tmrHw_ID_t timerId, /* [ IN ] Timer id */ | ||
| 260 | unsigned long usecs /* [ IN ] usec to delay */ | ||
| 261 | ) __attribute__ ((section(".aramtext"))); | ||
| 262 | |||
| 263 | #endif /* _TMRHW_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/clkdev.h b/arch/arm/mach-bcmring/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h new file mode 100644 index 000000000000..30fa2d540630 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/cap.h | |||
| @@ -0,0 +1,63 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2009 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CAP_H | ||
| 16 | #define CAP_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 19 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 20 | typedef enum { | ||
| 21 | CAP_NOT_PRESENT = 0, | ||
| 22 | CAP_PRESENT | ||
| 23 | } CAP_RC_T; | ||
| 24 | |||
| 25 | typedef enum { | ||
| 26 | CAP_VPM, | ||
| 27 | CAP_ETH_PHY, | ||
| 28 | CAP_ETH_GMII, | ||
| 29 | CAP_ETH_SGMII, | ||
| 30 | CAP_USB, | ||
| 31 | CAP_TSC, | ||
| 32 | CAP_EHSS, | ||
| 33 | CAP_SDIO, | ||
| 34 | CAP_UARTB, | ||
| 35 | CAP_KEYPAD, | ||
| 36 | CAP_CLCD, | ||
| 37 | CAP_GE, | ||
| 38 | CAP_LEDM, | ||
| 39 | CAP_BBL, | ||
| 40 | CAP_VDEC, | ||
| 41 | CAP_PIF, | ||
| 42 | CAP_APM, | ||
| 43 | CAP_SPU, | ||
| 44 | CAP_PKA, | ||
| 45 | CAP_RNG, | ||
| 46 | } CAP_CAPABILITY_T; | ||
| 47 | |||
| 48 | typedef enum { | ||
| 49 | CAP_LCD_WVGA = 0, | ||
| 50 | CAP_LCD_VGA = 0x1, | ||
| 51 | CAP_LCD_WQVGA = 0x2, | ||
| 52 | CAP_LCD_QVGA = 0x3 | ||
| 53 | } CAP_LCD_RES_T; | ||
| 54 | |||
| 55 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 56 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 57 | |||
| 58 | static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index); | ||
| 59 | static inline uint32_t cap_getMaxArmSpeedHz(void); | ||
| 60 | static inline uint32_t cap_getMaxVpmSpeedHz(void); | ||
| 61 | static inline CAP_LCD_RES_T cap_getMaxLcdRes(void); | ||
| 62 | |||
| 63 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h new file mode 100644 index 000000000000..933ce68ed90b --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h | |||
| @@ -0,0 +1,409 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2009 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CAP_INLINE_H | ||
| 16 | #define CAP_INLINE_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 19 | #include <mach/csp/cap.h> | ||
| 20 | #include <cfg_global.h> | ||
| 21 | |||
| 22 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 23 | #define CAP_CONFIG0_VPM_DIS 0x00000001 | ||
| 24 | #define CAP_CONFIG0_ETH_PHY0_DIS 0x00000002 | ||
| 25 | #define CAP_CONFIG0_ETH_PHY1_DIS 0x00000004 | ||
| 26 | #define CAP_CONFIG0_ETH_GMII0_DIS 0x00000008 | ||
| 27 | #define CAP_CONFIG0_ETH_GMII1_DIS 0x00000010 | ||
| 28 | #define CAP_CONFIG0_ETH_SGMII0_DIS 0x00000020 | ||
| 29 | #define CAP_CONFIG0_ETH_SGMII1_DIS 0x00000040 | ||
| 30 | #define CAP_CONFIG0_USB0_DIS 0x00000080 | ||
| 31 | #define CAP_CONFIG0_USB1_DIS 0x00000100 | ||
| 32 | #define CAP_CONFIG0_TSC_DIS 0x00000200 | ||
| 33 | #define CAP_CONFIG0_EHSS0_DIS 0x00000400 | ||
| 34 | #define CAP_CONFIG0_EHSS1_DIS 0x00000800 | ||
| 35 | #define CAP_CONFIG0_SDIO0_DIS 0x00001000 | ||
| 36 | #define CAP_CONFIG0_SDIO1_DIS 0x00002000 | ||
| 37 | #define CAP_CONFIG0_UARTB_DIS 0x00004000 | ||
| 38 | #define CAP_CONFIG0_KEYPAD_DIS 0x00008000 | ||
| 39 | #define CAP_CONFIG0_CLCD_DIS 0x00010000 | ||
| 40 | #define CAP_CONFIG0_GE_DIS 0x00020000 | ||
| 41 | #define CAP_CONFIG0_LEDM_DIS 0x00040000 | ||
| 42 | #define CAP_CONFIG0_BBL_DIS 0x00080000 | ||
| 43 | #define CAP_CONFIG0_VDEC_DIS 0x00100000 | ||
| 44 | #define CAP_CONFIG0_PIF_DIS 0x00200000 | ||
| 45 | #define CAP_CONFIG0_RESERVED1_DIS 0x00400000 | ||
| 46 | #define CAP_CONFIG0_RESERVED2_DIS 0x00800000 | ||
| 47 | |||
| 48 | #define CAP_CONFIG1_APMA_DIS 0x00000001 | ||
| 49 | #define CAP_CONFIG1_APMB_DIS 0x00000002 | ||
| 50 | #define CAP_CONFIG1_APMC_DIS 0x00000004 | ||
| 51 | #define CAP_CONFIG1_CLCD_RES_MASK 0x00000600 | ||
| 52 | #define CAP_CONFIG1_CLCD_RES_SHIFT 9 | ||
| 53 | #define CAP_CONFIG1_CLCD_RES_WVGA (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT) | ||
| 54 | #define CAP_CONFIG1_CLCD_RES_VGA (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT) | ||
| 55 | #define CAP_CONFIG1_CLCD_RES_WQVGA (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT) | ||
| 56 | #define CAP_CONFIG1_CLCD_RES_QVGA (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT) | ||
| 57 | |||
| 58 | #define CAP_CONFIG2_SPU_DIS 0x00000010 | ||
| 59 | #define CAP_CONFIG2_PKA_DIS 0x00000020 | ||
| 60 | #define CAP_CONFIG2_RNG_DIS 0x00000080 | ||
| 61 | |||
| 62 | #if (CFG_GLOBAL_CHIP == BCM11107) | ||
| 63 | #define capConfig0 0 | ||
| 64 | #define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA | ||
| 65 | #define capConfig2 0 | ||
| 66 | #define CAP_APM_MAX_NUM_CHANS 3 | ||
| 67 | #elif (CFG_GLOBAL_CHIP == FPGA11107) | ||
| 68 | #define capConfig0 0 | ||
| 69 | #define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA | ||
| 70 | #define capConfig2 0 | ||
| 71 | #define CAP_APM_MAX_NUM_CHANS 3 | ||
| 72 | #elif (CFG_GLOBAL_CHIP == BCM11109) | ||
| 73 | #define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) | ||
| 74 | #define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) | ||
| 75 | #define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) | ||
| 76 | #define CAP_APM_MAX_NUM_CHANS 2 | ||
| 77 | #elif (CFG_GLOBAL_CHIP == BCM11170) | ||
| 78 | #define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) | ||
| 79 | #define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA) | ||
| 80 | #define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) | ||
| 81 | #define CAP_APM_MAX_NUM_CHANS 2 | ||
| 82 | #elif (CFG_GLOBAL_CHIP == BCM11110) | ||
| 83 | #define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS) | ||
| 84 | #define capConfig1 CAP_CONFIG1_APMC_DIS | ||
| 85 | #define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS) | ||
| 86 | #define CAP_APM_MAX_NUM_CHANS 2 | ||
| 87 | #elif (CFG_GLOBAL_CHIP == BCM11211) | ||
| 88 | #define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS) | ||
| 89 | #define capConfig1 CAP_CONFIG1_APMC_DIS | ||
| 90 | #define capConfig2 0 | ||
| 91 | #define CAP_APM_MAX_NUM_CHANS 2 | ||
| 92 | #else | ||
| 93 | #error CFG_GLOBAL_CHIP type capabilities not defined | ||
| 94 | #endif | ||
| 95 | |||
| 96 | #if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) | ||
| 97 | #define CAP_HW_CFG_ARM_CLK_HZ 500000000 | ||
| 98 | #elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) | ||
| 99 | #define CAP_HW_CFG_ARM_CLK_HZ 300000000 | ||
| 100 | #elif (CFG_GLOBAL_CHIP == BCM11211) | ||
| 101 | #define CAP_HW_CFG_ARM_CLK_HZ 666666666 | ||
| 102 | #else | ||
| 103 | #error CFG_GLOBAL_CHIP type capabilities not defined | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) | ||
| 107 | #define CAP_HW_CFG_VPM_CLK_HZ 333333333 | ||
| 108 | #elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) | ||
| 109 | #define CAP_HW_CFG_VPM_CLK_HZ 200000000 | ||
| 110 | #else | ||
| 111 | #error CFG_GLOBAL_CHIP type capabilities not defined | ||
| 112 | #endif | ||
| 113 | |||
| 114 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 115 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 116 | |||
| 117 | /**************************************************************************** | ||
| 118 | * cap_isPresent - | ||
| 119 | * | ||
| 120 | * PURPOSE: | ||
| 121 | * Determines if the chip has a certain capability present | ||
| 122 | * | ||
| 123 | * PARAMETERS: | ||
| 124 | * capability - type of capability to determine if present | ||
| 125 | * | ||
| 126 | * RETURNS: | ||
| 127 | * CAP_PRESENT or CAP_NOT_PRESENT | ||
| 128 | ****************************************************************************/ | ||
| 129 | static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index) | ||
| 130 | { | ||
| 131 | CAP_RC_T returnVal = CAP_NOT_PRESENT; | ||
| 132 | |||
| 133 | switch (capability) { | ||
| 134 | case CAP_VPM: | ||
| 135 | { | ||
| 136 | if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) { | ||
| 137 | returnVal = CAP_PRESENT; | ||
| 138 | } | ||
| 139 | } | ||
| 140 | break; | ||
| 141 | |||
| 142 | case CAP_ETH_PHY: | ||
| 143 | { | ||
| 144 | if ((index == 0) | ||
| 145 | && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) { | ||
| 146 | returnVal = CAP_PRESENT; | ||
| 147 | } | ||
| 148 | if ((index == 1) | ||
| 149 | && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) { | ||
| 150 | returnVal = CAP_PRESENT; | ||
| 151 | } | ||
| 152 | } | ||
| 153 | break; | ||
| 154 | |||
| 155 | case CAP_ETH_GMII: | ||
| 156 | { | ||
| 157 | if ((index == 0) | ||
| 158 | && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) { | ||
| 159 | returnVal = CAP_PRESENT; | ||
| 160 | } | ||
| 161 | if ((index == 1) | ||
| 162 | && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) { | ||
| 163 | returnVal = CAP_PRESENT; | ||
| 164 | } | ||
| 165 | } | ||
| 166 | break; | ||
| 167 | |||
| 168 | case CAP_ETH_SGMII: | ||
| 169 | { | ||
| 170 | if ((index == 0) | ||
| 171 | && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) { | ||
| 172 | returnVal = CAP_PRESENT; | ||
| 173 | } | ||
| 174 | if ((index == 1) | ||
| 175 | && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) { | ||
| 176 | returnVal = CAP_PRESENT; | ||
| 177 | } | ||
| 178 | } | ||
| 179 | break; | ||
| 180 | |||
| 181 | case CAP_USB: | ||
| 182 | { | ||
| 183 | if ((index == 0) | ||
| 184 | && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) { | ||
| 185 | returnVal = CAP_PRESENT; | ||
| 186 | } | ||
| 187 | if ((index == 1) | ||
| 188 | && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) { | ||
| 189 | returnVal = CAP_PRESENT; | ||
| 190 | } | ||
| 191 | } | ||
| 192 | break; | ||
| 193 | |||
| 194 | case CAP_TSC: | ||
| 195 | { | ||
| 196 | if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) { | ||
| 197 | returnVal = CAP_PRESENT; | ||
| 198 | } | ||
| 199 | } | ||
| 200 | break; | ||
| 201 | |||
| 202 | case CAP_EHSS: | ||
| 203 | { | ||
| 204 | if ((index == 0) | ||
| 205 | && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) { | ||
| 206 | returnVal = CAP_PRESENT; | ||
| 207 | } | ||
| 208 | if ((index == 1) | ||
| 209 | && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) { | ||
| 210 | returnVal = CAP_PRESENT; | ||
| 211 | } | ||
| 212 | } | ||
| 213 | break; | ||
| 214 | |||
| 215 | case CAP_SDIO: | ||
| 216 | { | ||
| 217 | if ((index == 0) | ||
| 218 | && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) { | ||
| 219 | returnVal = CAP_PRESENT; | ||
| 220 | } | ||
| 221 | if ((index == 1) | ||
| 222 | && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) { | ||
| 223 | returnVal = CAP_PRESENT; | ||
| 224 | } | ||
| 225 | } | ||
| 226 | break; | ||
| 227 | |||
| 228 | case CAP_UARTB: | ||
| 229 | { | ||
| 230 | if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) { | ||
| 231 | returnVal = CAP_PRESENT; | ||
| 232 | } | ||
| 233 | } | ||
| 234 | break; | ||
| 235 | |||
| 236 | case CAP_KEYPAD: | ||
| 237 | { | ||
| 238 | if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) { | ||
| 239 | returnVal = CAP_PRESENT; | ||
| 240 | } | ||
| 241 | } | ||
| 242 | break; | ||
| 243 | |||
| 244 | case CAP_CLCD: | ||
| 245 | { | ||
| 246 | if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) { | ||
| 247 | returnVal = CAP_PRESENT; | ||
| 248 | } | ||
| 249 | } | ||
| 250 | break; | ||
| 251 | |||
| 252 | case CAP_GE: | ||
| 253 | { | ||
| 254 | if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) { | ||
| 255 | returnVal = CAP_PRESENT; | ||
| 256 | } | ||
| 257 | } | ||
| 258 | break; | ||
| 259 | |||
| 260 | case CAP_LEDM: | ||
| 261 | { | ||
| 262 | if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) { | ||
| 263 | returnVal = CAP_PRESENT; | ||
| 264 | } | ||
| 265 | } | ||
| 266 | break; | ||
| 267 | |||
| 268 | case CAP_BBL: | ||
| 269 | { | ||
| 270 | if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) { | ||
| 271 | returnVal = CAP_PRESENT; | ||
| 272 | } | ||
| 273 | } | ||
| 274 | break; | ||
| 275 | |||
| 276 | case CAP_VDEC: | ||
| 277 | { | ||
| 278 | if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) { | ||
| 279 | returnVal = CAP_PRESENT; | ||
| 280 | } | ||
| 281 | } | ||
| 282 | break; | ||
| 283 | |||
| 284 | case CAP_PIF: | ||
| 285 | { | ||
| 286 | if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) { | ||
| 287 | returnVal = CAP_PRESENT; | ||
| 288 | } | ||
| 289 | } | ||
| 290 | break; | ||
| 291 | |||
| 292 | case CAP_APM: | ||
| 293 | { | ||
| 294 | if ((index == 0) | ||
| 295 | && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) { | ||
| 296 | returnVal = CAP_PRESENT; | ||
| 297 | } | ||
| 298 | if ((index == 1) | ||
| 299 | && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) { | ||
| 300 | returnVal = CAP_PRESENT; | ||
| 301 | } | ||
| 302 | if ((index == 2) | ||
| 303 | && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) { | ||
| 304 | returnVal = CAP_PRESENT; | ||
| 305 | } | ||
| 306 | } | ||
| 307 | break; | ||
| 308 | |||
| 309 | case CAP_SPU: | ||
| 310 | { | ||
| 311 | if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) { | ||
| 312 | returnVal = CAP_PRESENT; | ||
| 313 | } | ||
| 314 | } | ||
| 315 | break; | ||
| 316 | |||
| 317 | case CAP_PKA: | ||
| 318 | { | ||
| 319 | if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) { | ||
| 320 | returnVal = CAP_PRESENT; | ||
| 321 | } | ||
| 322 | } | ||
| 323 | break; | ||
| 324 | |||
| 325 | case CAP_RNG: | ||
| 326 | { | ||
| 327 | if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) { | ||
| 328 | returnVal = CAP_PRESENT; | ||
| 329 | } | ||
| 330 | } | ||
| 331 | break; | ||
| 332 | |||
| 333 | default: | ||
| 334 | { | ||
| 335 | } | ||
| 336 | break; | ||
| 337 | } | ||
| 338 | return returnVal; | ||
| 339 | } | ||
| 340 | |||
| 341 | /**************************************************************************** | ||
| 342 | * cap_getMaxArmSpeedHz - | ||
| 343 | * | ||
| 344 | * PURPOSE: | ||
| 345 | * Determines the maximum speed of the ARM CPU | ||
| 346 | * | ||
| 347 | * PARAMETERS: | ||
| 348 | * none | ||
| 349 | * | ||
| 350 | * RETURNS: | ||
| 351 | * clock speed in Hz that the ARM processor is able to run at | ||
| 352 | ****************************************************************************/ | ||
| 353 | static inline uint32_t cap_getMaxArmSpeedHz(void) | ||
| 354 | { | ||
| 355 | #if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107)) | ||
| 356 | return 500000000; | ||
| 357 | #elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) | ||
| 358 | return 300000000; | ||
| 359 | #elif (CFG_GLOBAL_CHIP == BCM11211) | ||
| 360 | return 666666666; | ||
| 361 | #else | ||
| 362 | #error CFG_GLOBAL_CHIP type capabilities not defined | ||
| 363 | #endif | ||
| 364 | } | ||
| 365 | |||
| 366 | /**************************************************************************** | ||
| 367 | * cap_getMaxVpmSpeedHz - | ||
| 368 | * | ||
| 369 | * PURPOSE: | ||
| 370 | * Determines the maximum speed of the VPM | ||
| 371 | * | ||
| 372 | * PARAMETERS: | ||
| 373 | * none | ||
| 374 | * | ||
| 375 | * RETURNS: | ||
| 376 | * clock speed in Hz that the VPM is able to run at | ||
| 377 | ****************************************************************************/ | ||
| 378 | static inline uint32_t cap_getMaxVpmSpeedHz(void) | ||
| 379 | { | ||
| 380 | #if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107)) | ||
| 381 | return 333333333; | ||
| 382 | #elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110)) | ||
| 383 | return 200000000; | ||
| 384 | #else | ||
| 385 | #error CFG_GLOBAL_CHIP type capabilities not defined | ||
| 386 | #endif | ||
| 387 | } | ||
| 388 | |||
| 389 | /**************************************************************************** | ||
| 390 | * cap_getMaxLcdRes - | ||
| 391 | * | ||
| 392 | * PURPOSE: | ||
| 393 | * Determines the maximum LCD resolution capabilities | ||
| 394 | * | ||
| 395 | * PARAMETERS: | ||
| 396 | * none | ||
| 397 | * | ||
| 398 | * RETURNS: | ||
| 399 | * CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA | ||
| 400 | * | ||
| 401 | ****************************************************************************/ | ||
| 402 | static inline CAP_LCD_RES_T cap_getMaxLcdRes(void) | ||
| 403 | { | ||
| 404 | return (CAP_LCD_RES_T) | ||
| 405 | ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >> | ||
| 406 | CAP_CONFIG1_CLCD_RES_SHIFT); | ||
| 407 | } | ||
| 408 | |||
| 409 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h new file mode 100644 index 000000000000..70eaea866cfe --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h | |||
| @@ -0,0 +1,1123 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CHIPC_DEF_H | ||
| 16 | #define CHIPC_DEF_H | ||
| 17 | |||
| 18 | /* ---- Include Files ----------------------------------------------------- */ | ||
| 19 | |||
| 20 | #include <csp/stdint.h> | ||
| 21 | #include <csp/errno.h> | ||
| 22 | #include <csp/reg.h> | ||
| 23 | #include <mach/csp/chipcHw_reg.h> | ||
| 24 | |||
| 25 | /* ---- Public Constants and Types ---------------------------------------- */ | ||
| 26 | |||
| 27 | /* Set 1 to configure DDR/VPM phase alignment by HW */ | ||
| 28 | #define chipcHw_DDR_HW_PHASE_ALIGN 0 | ||
| 29 | #define chipcHw_VPM_HW_PHASE_ALIGN 0 | ||
| 30 | |||
| 31 | typedef uint32_t chipcHw_freq; | ||
| 32 | |||
| 33 | /* Configurable miscellaneous clocks */ | ||
| 34 | typedef enum { | ||
| 35 | chipcHw_CLOCK_DDR, /* DDR PHY Clock */ | ||
| 36 | chipcHw_CLOCK_ARM, /* ARM Clock */ | ||
| 37 | chipcHw_CLOCK_ESW, /* Ethernet Switch Clock */ | ||
| 38 | chipcHw_CLOCK_VPM, /* VPM Clock */ | ||
| 39 | chipcHw_CLOCK_ESW125, /* Ethernet MII Clock */ | ||
| 40 | chipcHw_CLOCK_UART, /* UART Clock */ | ||
| 41 | chipcHw_CLOCK_SDIO0, /* SDIO 0 Clock */ | ||
| 42 | chipcHw_CLOCK_SDIO1, /* SDIO 1 Clock */ | ||
| 43 | chipcHw_CLOCK_SPI, /* SPI Clock */ | ||
| 44 | chipcHw_CLOCK_ETM, /* ARM ETM Clock */ | ||
| 45 | |||
| 46 | chipcHw_CLOCK_BUS, /* BUS Clock */ | ||
| 47 | chipcHw_CLOCK_OTP, /* OTP Clock */ | ||
| 48 | chipcHw_CLOCK_I2C, /* I2C Host Clock */ | ||
| 49 | chipcHw_CLOCK_I2S0, /* I2S 0 Host Clock */ | ||
| 50 | chipcHw_CLOCK_RTBUS, /* DDR PHY Configuration Clock */ | ||
| 51 | chipcHw_CLOCK_APM100, /* APM100 Clock */ | ||
| 52 | chipcHw_CLOCK_TSC, /* Touch screen Clock */ | ||
| 53 | chipcHw_CLOCK_LED, /* LED Clock */ | ||
| 54 | |||
| 55 | chipcHw_CLOCK_USB, /* USB Clock */ | ||
| 56 | chipcHw_CLOCK_LCD, /* LCD CLock */ | ||
| 57 | chipcHw_CLOCK_APM, /* APM Clock */ | ||
| 58 | |||
| 59 | chipcHw_CLOCK_I2S1, /* I2S 1 Host Clock */ | ||
| 60 | } chipcHw_CLOCK_e; | ||
| 61 | |||
| 62 | /* System booting strap options */ | ||
| 63 | typedef enum { | ||
| 64 | chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART, | ||
| 65 | chipcHw_BOOT_DEVICE_SERIAL_FLASH = | ||
| 66 | chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH, | ||
| 67 | chipcHw_BOOT_DEVICE_NOR_FLASH_16 = | ||
| 68 | chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16, | ||
| 69 | chipcHw_BOOT_DEVICE_NAND_FLASH_8 = | ||
| 70 | chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8, | ||
| 71 | chipcHw_BOOT_DEVICE_NAND_FLASH_16 = | ||
| 72 | chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 | ||
| 73 | } chipcHw_BOOT_DEVICE_e; | ||
| 74 | |||
| 75 | /* System booting modes */ | ||
| 76 | typedef enum { | ||
| 77 | chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL, | ||
| 78 | chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW, | ||
| 79 | chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT, | ||
| 80 | chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET | ||
| 81 | } chipcHw_BOOT_MODE_e; | ||
| 82 | |||
| 83 | /* NAND Flash page size strap options */ | ||
| 84 | typedef enum { | ||
| 85 | chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512, | ||
| 86 | chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048, | ||
| 87 | chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096, | ||
| 88 | chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT | ||
| 89 | } chipcHw_NAND_PAGESIZE_e; | ||
| 90 | |||
| 91 | /* GPIO Pin function */ | ||
| 92 | typedef enum { | ||
| 93 | chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD, | ||
| 94 | chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH, | ||
| 95 | chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI, | ||
| 96 | chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART, | ||
| 97 | chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP, | ||
| 98 | chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS, | ||
| 99 | chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0, | ||
| 100 | chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1, | ||
| 101 | chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM, | ||
| 102 | chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S, | ||
| 103 | chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM, | ||
| 104 | chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG, | ||
| 105 | chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC, | ||
| 106 | chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO | ||
| 107 | } chipcHw_GPIO_FUNCTION_e; | ||
| 108 | |||
| 109 | /* PIN Output slew rate */ | ||
| 110 | typedef enum { | ||
| 111 | chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH, | ||
| 112 | chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL | ||
| 113 | } chipcHw_PIN_SLEW_RATE_e; | ||
| 114 | |||
| 115 | /* PIN Current drive strength */ | ||
| 116 | typedef enum { | ||
| 117 | chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA, | ||
| 118 | chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA, | ||
| 119 | chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA, | ||
| 120 | chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA, | ||
| 121 | chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA, | ||
| 122 | chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA | ||
| 123 | } chipcHw_PIN_CURRENT_STRENGTH_e; | ||
| 124 | |||
| 125 | /* PIN Pull up register settings */ | ||
| 126 | typedef enum { | ||
| 127 | chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE, | ||
| 128 | chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP, | ||
| 129 | chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN | ||
| 130 | } chipcHw_PIN_PULL_e; | ||
| 131 | |||
| 132 | /* PIN input type settings */ | ||
| 133 | typedef enum { | ||
| 134 | chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS, | ||
| 135 | chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST | ||
| 136 | } chipcHw_PIN_INPUTTYPE_e; | ||
| 137 | |||
| 138 | /* Allow/Disalow the support of spread spectrum */ | ||
| 139 | typedef enum { | ||
| 140 | chipcHw_SPREAD_SPECTRUM_DISALLOW, /* Spread spectrum support is not allowed */ | ||
| 141 | chipcHw_SPREAD_SPECTRUM_ALLOW /* Spread spectrum support is allowed */ | ||
| 142 | } chipcHw_SPREAD_SPECTRUM_e; | ||
| 143 | |||
| 144 | typedef struct { | ||
| 145 | chipcHw_SPREAD_SPECTRUM_e ssSupport; /* Allow/Disalow to support spread spectrum. | ||
| 146 | If supported, call chipcHw_enableSpreadSpectrum () | ||
| 147 | to activate the spread spectrum with desired spread. */ | ||
| 148 | uint32_t pllVcoFreqHz; /* PLL VCO frequency in Hz */ | ||
| 149 | uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */ | ||
| 150 | uint32_t busClockFreqHz; /* Bus clock frequency in Hz */ | ||
| 151 | uint32_t armBusRatio; /* ARM clock : Bus clock */ | ||
| 152 | uint32_t vpmBusRatio; /* VPM clock : Bus clock */ | ||
| 153 | uint32_t ddrBusRatio; /* DDR clock : Bus clock */ | ||
| 154 | } chipcHw_INIT_PARAM_t; | ||
| 155 | |||
| 156 | /* CHIP revision number */ | ||
| 157 | typedef enum { | ||
| 158 | chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0, | ||
| 159 | chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0 | ||
| 160 | } chipcHw_REV_NUMBER_e; | ||
| 161 | |||
| 162 | typedef enum { | ||
| 163 | chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE, | ||
| 164 | chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST, | ||
| 165 | chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM, | ||
| 166 | chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW | ||
| 167 | } chipcHw_VPM_HW_PHASE_INTR_e; | ||
| 168 | |||
| 169 | typedef enum { | ||
| 170 | chipcHw_DDR_HW_PHASE_MARGIN_STRICT, /* Strict margin for DDR phase align condition */ | ||
| 171 | chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for DDR phase align condition */ | ||
| 172 | chipcHw_DDR_HW_PHASE_MARGIN_WIDE /* Wider margin for DDR phase align condition */ | ||
| 173 | } chipcHw_DDR_HW_PHASE_MARGIN_e; | ||
| 174 | |||
| 175 | typedef enum { | ||
| 176 | chipcHw_VPM_HW_PHASE_MARGIN_STRICT, /* Strict margin for VPM phase align condition */ | ||
| 177 | chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM, /* Medium margin for VPM phase align condition */ | ||
| 178 | chipcHw_VPM_HW_PHASE_MARGIN_WIDE /* Wider margin for VPM phase align condition */ | ||
| 179 | } chipcHw_VPM_HW_PHASE_MARGIN_e; | ||
| 180 | |||
| 181 | #define chipcHw_XTAL_FREQ_Hz 25000000 /* Reference clock frequency in Hz */ | ||
| 182 | |||
| 183 | /* Programable pin defines */ | ||
| 184 | #define chipcHw_PIN_GPIO(n) ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF) | ||
| 185 | /* GPIO pin 0 - 60 */ | ||
| 186 | #define chipcHw_PIN_UARTTXD (chipcHw_GPIO_COUNT + 0) /* UART Transmit */ | ||
| 187 | #define chipcHw_PIN_NVI_A (chipcHw_GPIO_COUNT + 1) /* NVI Interface */ | ||
| 188 | #define chipcHw_PIN_NVI_D (chipcHw_GPIO_COUNT + 2) /* NVI Interface */ | ||
| 189 | #define chipcHw_PIN_NVI_OEB (chipcHw_GPIO_COUNT + 3) /* NVI Interface */ | ||
| 190 | #define chipcHw_PIN_NVI_WEB (chipcHw_GPIO_COUNT + 4) /* NVI Interface */ | ||
| 191 | #define chipcHw_PIN_NVI_CS (chipcHw_GPIO_COUNT + 5) /* NVI Interface */ | ||
| 192 | #define chipcHw_PIN_NVI_NAND_CSB (chipcHw_GPIO_COUNT + 6) /* NVI Interface */ | ||
| 193 | #define chipcHw_PIN_NVI_FLASHWP (chipcHw_GPIO_COUNT + 7) /* NVI Interface */ | ||
| 194 | #define chipcHw_PIN_NVI_NAND_RDYB (chipcHw_GPIO_COUNT + 8) /* NVI Interface */ | ||
| 195 | #define chipcHw_PIN_CL_DATA_0_17 (chipcHw_GPIO_COUNT + 9) /* LCD Data 0 - 17 */ | ||
| 196 | #define chipcHw_PIN_CL_DATA_18_20 (chipcHw_GPIO_COUNT + 10) /* LCD Data 18 - 20 */ | ||
| 197 | #define chipcHw_PIN_CL_DATA_21_23 (chipcHw_GPIO_COUNT + 11) /* LCD Data 21 - 23 */ | ||
| 198 | #define chipcHw_PIN_CL_POWER (chipcHw_GPIO_COUNT + 12) /* LCD Power */ | ||
| 199 | #define chipcHw_PIN_CL_ACK (chipcHw_GPIO_COUNT + 13) /* LCD Ack */ | ||
| 200 | #define chipcHw_PIN_CL_FP (chipcHw_GPIO_COUNT + 14) /* LCD FP */ | ||
| 201 | #define chipcHw_PIN_CL_LP (chipcHw_GPIO_COUNT + 15) /* LCD LP */ | ||
| 202 | #define chipcHw_PIN_UARTRXD (chipcHw_GPIO_COUNT + 16) /* UART Receive */ | ||
| 203 | |||
| 204 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 205 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 206 | |||
| 207 | /****************************************************************************/ | ||
| 208 | /** | ||
| 209 | * @brief Initializes the clock module | ||
| 210 | * | ||
| 211 | */ | ||
| 212 | /****************************************************************************/ | ||
| 213 | void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam /* [ IN ] Misc chip initialization parameter */ | ||
| 214 | ) __attribute__ ((section(".aramtext"))); | ||
| 215 | |||
| 216 | /****************************************************************************/ | ||
| 217 | /** | ||
| 218 | * @brief Enables the PLL1 | ||
| 219 | * | ||
| 220 | * This function enables the PLL1 | ||
| 221 | * | ||
| 222 | */ | ||
| 223 | /****************************************************************************/ | ||
| 224 | void chipcHw_pll1Enable(uint32_t vcoFreqHz, /* [ IN ] VCO frequency in Hz */ | ||
| 225 | chipcHw_SPREAD_SPECTRUM_e ssSupport /* [ IN ] SS status */ | ||
| 226 | ) __attribute__ ((section(".aramtext"))); | ||
| 227 | |||
| 228 | /****************************************************************************/ | ||
| 229 | /** | ||
| 230 | * @brief Enables the PLL2 | ||
| 231 | * | ||
| 232 | * This function enables the PLL2 | ||
| 233 | * | ||
| 234 | */ | ||
| 235 | /****************************************************************************/ | ||
| 236 | void chipcHw_pll2Enable(uint32_t vcoFreqHz /* [ IN ] VCO frequency in Hz */ | ||
| 237 | ) __attribute__ ((section(".aramtext"))); | ||
| 238 | |||
| 239 | /****************************************************************************/ | ||
| 240 | /** | ||
| 241 | * @brief Disable the PLL1 | ||
| 242 | * | ||
| 243 | */ | ||
| 244 | /****************************************************************************/ | ||
| 245 | static inline void chipcHw_pll1Disable(void); | ||
| 246 | |||
| 247 | /****************************************************************************/ | ||
| 248 | /** | ||
| 249 | * @brief Disable the PLL2 | ||
| 250 | * | ||
| 251 | */ | ||
| 252 | /****************************************************************************/ | ||
| 253 | static inline void chipcHw_pll2Disable(void); | ||
| 254 | |||
| 255 | /****************************************************************************/ | ||
| 256 | /** | ||
| 257 | * @brief Set clock fequency for miscellaneous configurable clocks | ||
| 258 | * | ||
| 259 | * This function sets clock frequency | ||
| 260 | * | ||
| 261 | * @return Configured clock frequency in KHz | ||
| 262 | * | ||
| 263 | */ | ||
| 264 | /****************************************************************************/ | ||
| 265 | chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 266 | ) __attribute__ ((section(".aramtext"))); | ||
| 267 | |||
| 268 | /****************************************************************************/ | ||
| 269 | /** | ||
| 270 | * @brief Set clock fequency for miscellaneous configurable clocks | ||
| 271 | * | ||
| 272 | * This function sets clock frequency | ||
| 273 | * | ||
| 274 | * @return Configured clock frequency in Hz | ||
| 275 | * | ||
| 276 | */ | ||
| 277 | /****************************************************************************/ | ||
| 278 | chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */ | ||
| 279 | uint32_t freq /* [ IN ] Clock frequency in Hz */ | ||
| 280 | ) __attribute__ ((section(".aramtext"))); | ||
| 281 | |||
| 282 | /****************************************************************************/ | ||
| 283 | /** | ||
| 284 | * @brief Set VPM clock in sync with BUS clock | ||
| 285 | * | ||
| 286 | * This function does the phase adjustment between VPM and BUS clock | ||
| 287 | * | ||
| 288 | * @return >= 0 : On success ( # of adjustment required ) | ||
| 289 | * -1 : On failure | ||
| 290 | */ | ||
| 291 | /****************************************************************************/ | ||
| 292 | int chipcHw_vpmPhaseAlign(void); | ||
| 293 | |||
| 294 | /****************************************************************************/ | ||
| 295 | /** | ||
| 296 | * @brief Enables core a clock of a certain device | ||
| 297 | * | ||
| 298 | * This function enables a core clock | ||
| 299 | * | ||
| 300 | * @return void | ||
| 301 | * | ||
| 302 | * @note Doesnot affect the bus interface clock | ||
| 303 | */ | ||
| 304 | /****************************************************************************/ | ||
| 305 | static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 306 | ); | ||
| 307 | |||
| 308 | /****************************************************************************/ | ||
| 309 | /** | ||
| 310 | * @brief Disabled a core clock of a certain device | ||
| 311 | * | ||
| 312 | * This function disables a core clock | ||
| 313 | * | ||
| 314 | * @return void | ||
| 315 | * | ||
| 316 | * @note Doesnot affect the bus interface clock | ||
| 317 | */ | ||
| 318 | /****************************************************************************/ | ||
| 319 | static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 320 | ); | ||
| 321 | |||
| 322 | /****************************************************************************/ | ||
| 323 | /** | ||
| 324 | * @brief Enables bypass clock of a certain device | ||
| 325 | * | ||
| 326 | * This function enables bypass clock | ||
| 327 | * | ||
| 328 | * @note Doesnot affect the bus interface clock | ||
| 329 | */ | ||
| 330 | /****************************************************************************/ | ||
| 331 | static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 332 | ); | ||
| 333 | |||
| 334 | /****************************************************************************/ | ||
| 335 | /** | ||
| 336 | * @brief Disabled bypass clock of a certain device | ||
| 337 | * | ||
| 338 | * This function disables bypass clock | ||
| 339 | * | ||
| 340 | * @note Doesnot affect the bus interface clock | ||
| 341 | */ | ||
| 342 | /****************************************************************************/ | ||
| 343 | static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */ | ||
| 344 | ); | ||
| 345 | |||
| 346 | /****************************************************************************/ | ||
| 347 | /** | ||
| 348 | * @brief Get Numeric Chip ID | ||
| 349 | * | ||
| 350 | * This function returns Chip ID that includes the revison number | ||
| 351 | * | ||
| 352 | * @return Complete numeric Chip ID | ||
| 353 | * | ||
| 354 | */ | ||
| 355 | /****************************************************************************/ | ||
| 356 | static inline uint32_t chipcHw_getChipId(void); | ||
| 357 | |||
| 358 | /****************************************************************************/ | ||
| 359 | /** | ||
| 360 | * @brief Get Chip Product ID | ||
| 361 | * | ||
| 362 | * This function returns Chip Product ID | ||
| 363 | * | ||
| 364 | * @return Chip Product ID | ||
| 365 | */ | ||
| 366 | /****************************************************************************/ | ||
| 367 | static inline uint32_t chipcHw_getChipProductId(void); | ||
| 368 | |||
| 369 | /****************************************************************************/ | ||
| 370 | /** | ||
| 371 | * @brief Get revision number | ||
| 372 | * | ||
| 373 | * This function returns revision number of the chip | ||
| 374 | * | ||
| 375 | * @return Revision number | ||
| 376 | */ | ||
| 377 | /****************************************************************************/ | ||
| 378 | static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void); | ||
| 379 | |||
| 380 | /****************************************************************************/ | ||
| 381 | /** | ||
| 382 | * @brief Enables bus interface clock | ||
| 383 | * | ||
| 384 | * Enables bus interface clock of various device | ||
| 385 | * | ||
| 386 | * @return void | ||
| 387 | * | ||
| 388 | * @note use chipcHw_REG_BUS_CLOCK_XXXX | ||
| 389 | */ | ||
| 390 | /****************************************************************************/ | ||
| 391 | static inline void chipcHw_busInterfaceClockEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */ | ||
| 392 | ); | ||
| 393 | |||
| 394 | /****************************************************************************/ | ||
| 395 | /** | ||
| 396 | * @brief Disables bus interface clock | ||
| 397 | * | ||
| 398 | * Disables bus interface clock of various device | ||
| 399 | * | ||
| 400 | * @return void | ||
| 401 | * | ||
| 402 | * @note use chipcHw_REG_BUS_CLOCK_XXXX | ||
| 403 | */ | ||
| 404 | /****************************************************************************/ | ||
| 405 | static inline void chipcHw_busInterfaceClockDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_BUS_CLOCK_XXXXX */ | ||
| 406 | ); | ||
| 407 | |||
| 408 | /****************************************************************************/ | ||
| 409 | /** | ||
| 410 | * @brief Enables various audio channels | ||
| 411 | * | ||
| 412 | * Enables audio channel | ||
| 413 | * | ||
| 414 | * @return void | ||
| 415 | * | ||
| 416 | * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX | ||
| 417 | */ | ||
| 418 | /****************************************************************************/ | ||
| 419 | static inline void chipcHw_audioChannelEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */ | ||
| 420 | ); | ||
| 421 | |||
| 422 | /****************************************************************************/ | ||
| 423 | /** | ||
| 424 | * @brief Disables various audio channels | ||
| 425 | * | ||
| 426 | * Disables audio channel | ||
| 427 | * | ||
| 428 | * @return void | ||
| 429 | * | ||
| 430 | * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX | ||
| 431 | */ | ||
| 432 | /****************************************************************************/ | ||
| 433 | static inline void chipcHw_audioChannelDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_AUDIO_CHANNEL_XXXXXX */ | ||
| 434 | ); | ||
| 435 | |||
| 436 | /****************************************************************************/ | ||
| 437 | /** | ||
| 438 | * @brief Soft resets devices | ||
| 439 | * | ||
| 440 | * Soft resets various devices | ||
| 441 | * | ||
| 442 | * @return void | ||
| 443 | * | ||
| 444 | * @note use chipcHw_REG_SOFT_RESET_XXXXXX defines | ||
| 445 | */ | ||
| 446 | /****************************************************************************/ | ||
| 447 | static inline void chipcHw_softReset(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ | ||
| 448 | ); | ||
| 449 | |||
| 450 | static inline void chipcHw_softResetDisable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ | ||
| 451 | ); | ||
| 452 | |||
| 453 | static inline void chipcHw_softResetEnable(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */ | ||
| 454 | ); | ||
| 455 | |||
| 456 | /****************************************************************************/ | ||
| 457 | /** | ||
| 458 | * @brief Configures misc CHIP functionality | ||
| 459 | * | ||
| 460 | * Configures CHIP functionality | ||
| 461 | * | ||
| 462 | * @return void | ||
| 463 | * | ||
| 464 | * @note use chipcHw_REG_MISC_CTRL_XXXXXX | ||
| 465 | */ | ||
| 466 | /****************************************************************************/ | ||
| 467 | static inline void chipcHw_miscControl(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ | ||
| 468 | ); | ||
| 469 | |||
| 470 | static inline void chipcHw_miscControlDisable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ | ||
| 471 | ); | ||
| 472 | |||
| 473 | static inline void chipcHw_miscControlEnable(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */ | ||
| 474 | ); | ||
| 475 | |||
| 476 | /****************************************************************************/ | ||
| 477 | /** | ||
| 478 | * @brief Set OTP options | ||
| 479 | * | ||
| 480 | * Set OTP options | ||
| 481 | * | ||
| 482 | * @return void | ||
| 483 | * | ||
| 484 | * @note use chipcHw_REG_OTP_XXXXXX | ||
| 485 | */ | ||
| 486 | /****************************************************************************/ | ||
| 487 | static inline void chipcHw_setOTPOption(uint64_t mask /* [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */ | ||
| 488 | ); | ||
| 489 | |||
| 490 | /****************************************************************************/ | ||
| 491 | /** | ||
| 492 | * @brief Get sticky bits | ||
| 493 | * | ||
| 494 | * @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX | ||
| 495 | * | ||
| 496 | */ | ||
| 497 | /****************************************************************************/ | ||
| 498 | static inline uint32_t chipcHw_getStickyBits(void); | ||
| 499 | |||
| 500 | /****************************************************************************/ | ||
| 501 | /** | ||
| 502 | * @brief Set sticky bits | ||
| 503 | * | ||
| 504 | * @return void | ||
| 505 | * | ||
| 506 | * @note use chipcHw_REG_STICKY_XXXXXX | ||
| 507 | */ | ||
| 508 | /****************************************************************************/ | ||
| 509 | static inline void chipcHw_setStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */ | ||
| 510 | ); | ||
| 511 | |||
| 512 | /****************************************************************************/ | ||
| 513 | /** | ||
| 514 | * @brief Clear sticky bits | ||
| 515 | * | ||
| 516 | * @return void | ||
| 517 | * | ||
| 518 | * @note use chipcHw_REG_STICKY_XXXXXX | ||
| 519 | */ | ||
| 520 | /****************************************************************************/ | ||
| 521 | static inline void chipcHw_clearStickyBits(uint32_t mask /* [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */ | ||
| 522 | ); | ||
| 523 | |||
| 524 | /****************************************************************************/ | ||
| 525 | /** | ||
| 526 | * @brief Get software override strap options | ||
| 527 | * | ||
| 528 | * Retrieves software override strap options | ||
| 529 | * | ||
| 530 | * @return Software override strap value | ||
| 531 | * | ||
| 532 | */ | ||
| 533 | /****************************************************************************/ | ||
| 534 | static inline uint32_t chipcHw_getSoftStraps(void); | ||
| 535 | |||
| 536 | /****************************************************************************/ | ||
| 537 | /** | ||
| 538 | * @brief Set software override strap options | ||
| 539 | * | ||
| 540 | * set software override strap options | ||
| 541 | * | ||
| 542 | * @return nothing | ||
| 543 | * | ||
| 544 | */ | ||
| 545 | /****************************************************************************/ | ||
| 546 | static inline void chipcHw_setSoftStraps(uint32_t strapOptions); | ||
| 547 | |||
| 548 | /****************************************************************************/ | ||
| 549 | /** | ||
| 550 | * @brief Get pin strap options | ||
| 551 | * | ||
| 552 | * Retrieves pin strap options | ||
| 553 | * | ||
| 554 | * @return Pin strap value | ||
| 555 | * | ||
| 556 | */ | ||
| 557 | /****************************************************************************/ | ||
| 558 | static inline uint32_t chipcHw_getPinStraps(void); | ||
| 559 | |||
| 560 | /****************************************************************************/ | ||
| 561 | /** | ||
| 562 | * @brief Get valid pin strap options | ||
| 563 | * | ||
| 564 | * Retrieves valid pin strap options | ||
| 565 | * | ||
| 566 | * @return valid Pin strap value | ||
| 567 | * | ||
| 568 | */ | ||
| 569 | /****************************************************************************/ | ||
| 570 | static inline uint32_t chipcHw_getValidStraps(void); | ||
| 571 | |||
| 572 | /****************************************************************************/ | ||
| 573 | /** | ||
| 574 | * @brief Initialize valid pin strap options | ||
| 575 | * | ||
| 576 | * Retrieves valid pin strap options by copying HW strap options to soft register | ||
| 577 | * (if chipcHw_STRAPS_SOFT_OVERRIDE not set) | ||
| 578 | * | ||
| 579 | * @return nothing | ||
| 580 | * | ||
| 581 | */ | ||
| 582 | /****************************************************************************/ | ||
| 583 | static inline void chipcHw_initValidStraps(void); | ||
| 584 | |||
| 585 | /****************************************************************************/ | ||
| 586 | /** | ||
| 587 | * @brief Get status (enabled/disabled) of bus interface clock | ||
| 588 | * | ||
| 589 | * This function returns the status of devices' bus interface clock | ||
| 590 | * | ||
| 591 | * @return Bus interface clock | ||
| 592 | * | ||
| 593 | */ | ||
| 594 | /****************************************************************************/ | ||
| 595 | static inline uint32_t chipcHw_getBusInterfaceClockStatus(void); | ||
| 596 | |||
| 597 | /****************************************************************************/ | ||
| 598 | /** | ||
| 599 | * @brief Get boot device | ||
| 600 | * | ||
| 601 | * This function returns the device type used in booting the system | ||
| 602 | * | ||
| 603 | * @return Boot device of type chipcHw_BOOT_DEVICE_e | ||
| 604 | * | ||
| 605 | */ | ||
| 606 | /****************************************************************************/ | ||
| 607 | static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void); | ||
| 608 | |||
| 609 | /****************************************************************************/ | ||
| 610 | /** | ||
| 611 | * @brief Get boot mode | ||
| 612 | * | ||
| 613 | * This function returns the way the system was booted | ||
| 614 | * | ||
| 615 | * @return Boot mode of type chipcHw_BOOT_MODE_e | ||
| 616 | * | ||
| 617 | */ | ||
| 618 | /****************************************************************************/ | ||
| 619 | static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void); | ||
| 620 | |||
| 621 | /****************************************************************************/ | ||
| 622 | /** | ||
| 623 | * @brief Get NAND flash page size | ||
| 624 | * | ||
| 625 | * This function returns the NAND device page size | ||
| 626 | * | ||
| 627 | * @return Boot NAND device page size | ||
| 628 | * | ||
| 629 | */ | ||
| 630 | /****************************************************************************/ | ||
| 631 | static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void); | ||
| 632 | |||
| 633 | /****************************************************************************/ | ||
| 634 | /** | ||
| 635 | * @brief Get NAND flash address cycle configuration | ||
| 636 | * | ||
| 637 | * This function returns the NAND flash address cycle configuration | ||
| 638 | * | ||
| 639 | * @return 0 = Do not extra address cycle, 1 = Add extra cycle | ||
| 640 | * | ||
| 641 | */ | ||
| 642 | /****************************************************************************/ | ||
| 643 | static inline int chipcHw_getNandExtraCycle(void); | ||
| 644 | |||
| 645 | /****************************************************************************/ | ||
| 646 | /** | ||
| 647 | * @brief Activates PIF interface | ||
| 648 | * | ||
| 649 | * This function activates PIF interface by taking control of LCD pins | ||
| 650 | * | ||
| 651 | * @note | ||
| 652 | * When activated, LCD pins will be defined as follows for PIF operation | ||
| 653 | * | ||
| 654 | * CLD[17:0] = pif_data[17:0] | ||
| 655 | * CLD[23:18] = pif_address[5:0] | ||
| 656 | * CLPOWER = pif_wr_str | ||
| 657 | * CLCP = pif_rd_str | ||
| 658 | * CLAC = pif_hat1 | ||
| 659 | * CLFP = pif_hrdy1 | ||
| 660 | * CLLP = pif_hat2 | ||
| 661 | * GPIO[42] = pif_hrdy2 | ||
| 662 | * | ||
| 663 | * In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin | ||
| 664 | * | ||
| 665 | */ | ||
| 666 | /****************************************************************************/ | ||
| 667 | static inline void chipcHw_activatePifInterface(void); | ||
| 668 | |||
| 669 | /****************************************************************************/ | ||
| 670 | /** | ||
| 671 | * @brief Activates LCD interface | ||
| 672 | * | ||
| 673 | * This function activates LCD interface | ||
| 674 | * | ||
| 675 | * @note | ||
| 676 | * When activated, LCD pins will be defined as follows | ||
| 677 | * | ||
| 678 | * CLD[17:0] = LCD data | ||
| 679 | * CLD[23:18] = LCD data | ||
| 680 | * CLPOWER = LCD power | ||
| 681 | * CLCP = | ||
| 682 | * CLAC = LCD ack | ||
| 683 | * CLFP = | ||
| 684 | * CLLP = | ||
| 685 | */ | ||
| 686 | /****************************************************************************/ | ||
| 687 | static inline void chipcHw_activateLcdInterface(void); | ||
| 688 | |||
| 689 | /****************************************************************************/ | ||
| 690 | /** | ||
| 691 | * @brief Deactivates PIF/LCD interface | ||
| 692 | * | ||
| 693 | * This function deactivates PIF/LCD interface | ||
| 694 | * | ||
| 695 | * @note | ||
| 696 | * When deactivated LCD pins will be in rti-stated | ||
| 697 | * | ||
| 698 | */ | ||
| 699 | /****************************************************************************/ | ||
| 700 | static inline void chipcHw_deactivatePifLcdInterface(void); | ||
| 701 | |||
| 702 | /****************************************************************************/ | ||
| 703 | /** | ||
| 704 | * @brief Get to know the configuration of GPIO pin | ||
| 705 | * | ||
| 706 | */ | ||
| 707 | /****************************************************************************/ | ||
| 708 | static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin /* GPIO Pin number */ | ||
| 709 | ); | ||
| 710 | |||
| 711 | /****************************************************************************/ | ||
| 712 | /** | ||
| 713 | * @brief Configure GPIO pin function | ||
| 714 | * | ||
| 715 | */ | ||
| 716 | /****************************************************************************/ | ||
| 717 | static inline void chipcHw_setGpioPinFunction(int pin, /* GPIO Pin number */ | ||
| 718 | chipcHw_GPIO_FUNCTION_e func /* Configuration function */ | ||
| 719 | ); | ||
| 720 | |||
| 721 | /****************************************************************************/ | ||
| 722 | /** | ||
| 723 | * @brief Set Pin slew rate | ||
| 724 | * | ||
| 725 | * This function sets the slew of individual pin | ||
| 726 | * | ||
| 727 | */ | ||
| 728 | /****************************************************************************/ | ||
| 729 | static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ | ||
| 730 | chipcHw_PIN_SLEW_RATE_e slewRate /* Pin slew rate */ | ||
| 731 | ); | ||
| 732 | |||
| 733 | /****************************************************************************/ | ||
| 734 | /** | ||
| 735 | * @brief Set Pin output drive current | ||
| 736 | * | ||
| 737 | * This function sets output drive current of individual pin | ||
| 738 | * | ||
| 739 | * Note: Avoid the use of the word 'current' since linux headers define this | ||
| 740 | * to be the current task. | ||
| 741 | */ | ||
| 742 | /****************************************************************************/ | ||
| 743 | static inline void chipcHw_setPinOutputCurrent(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ | ||
| 744 | chipcHw_PIN_CURRENT_STRENGTH_e curr /* Pin current rating */ | ||
| 745 | ); | ||
| 746 | |||
| 747 | /****************************************************************************/ | ||
| 748 | /** | ||
| 749 | * @brief Set Pin pullup register | ||
| 750 | * | ||
| 751 | * This function sets pullup register of individual pin | ||
| 752 | * | ||
| 753 | */ | ||
| 754 | /****************************************************************************/ | ||
| 755 | static inline void chipcHw_setPinPullup(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ | ||
| 756 | chipcHw_PIN_PULL_e pullup /* Pullup register settings */ | ||
| 757 | ); | ||
| 758 | |||
| 759 | /****************************************************************************/ | ||
| 760 | /** | ||
| 761 | * @brief Set Pin input type | ||
| 762 | * | ||
| 763 | * This function sets input type of individual Pin | ||
| 764 | * | ||
| 765 | */ | ||
| 766 | /****************************************************************************/ | ||
| 767 | static inline void chipcHw_setPinInputType(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */ | ||
| 768 | chipcHw_PIN_INPUTTYPE_e inputType /* Pin input type */ | ||
| 769 | ); | ||
| 770 | |||
| 771 | /****************************************************************************/ | ||
| 772 | /** | ||
| 773 | * @brief Retrieves a string representation of the mux setting for a pin. | ||
| 774 | * | ||
| 775 | * @return Pointer to a character string. | ||
| 776 | */ | ||
| 777 | /****************************************************************************/ | ||
| 778 | |||
| 779 | const char *chipcHw_getGpioPinFunctionStr(int pin); | ||
| 780 | |||
| 781 | /****************************************************************************/ | ||
| 782 | /** @brief issue warmReset | ||
| 783 | */ | ||
| 784 | /****************************************************************************/ | ||
| 785 | void chipcHw_reset(uint32_t mask); | ||
| 786 | |||
| 787 | /****************************************************************************/ | ||
| 788 | /** @brief clock reconfigure | ||
| 789 | */ | ||
| 790 | /****************************************************************************/ | ||
| 791 | void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio, | ||
| 792 | uint32_t ddrRatio); | ||
| 793 | |||
| 794 | /****************************************************************************/ | ||
| 795 | /** | ||
| 796 | * @brief Enable Spread Spectrum | ||
| 797 | * | ||
| 798 | * @note chipcHw_Init() must be called earlier | ||
| 799 | */ | ||
| 800 | /****************************************************************************/ | ||
| 801 | static inline void chipcHw_enableSpreadSpectrum(void); | ||
| 802 | |||
| 803 | /****************************************************************************/ | ||
| 804 | /** | ||
| 805 | * @brief Disable Spread Spectrum | ||
| 806 | * | ||
| 807 | */ | ||
| 808 | /****************************************************************************/ | ||
| 809 | static inline void chipcHw_disableSpreadSpectrum(void); | ||
| 810 | |||
| 811 | /****************************************************************************/ | ||
| 812 | /** @brief Checks if software strap is enabled | ||
| 813 | * | ||
| 814 | * @return 1 : When enable | ||
| 815 | * 0 : When disable | ||
| 816 | */ | ||
| 817 | /****************************************************************************/ | ||
| 818 | static inline int chipcHw_isSoftwareStrapsEnable(void); | ||
| 819 | |||
| 820 | /****************************************************************************/ | ||
| 821 | /** @brief Enable software strap | ||
| 822 | */ | ||
| 823 | /****************************************************************************/ | ||
| 824 | static inline void chipcHw_softwareStrapsEnable(void); | ||
| 825 | |||
| 826 | /****************************************************************************/ | ||
| 827 | /** @brief Disable software strap | ||
| 828 | */ | ||
| 829 | /****************************************************************************/ | ||
| 830 | static inline void chipcHw_softwareStrapsDisable(void); | ||
| 831 | |||
| 832 | /****************************************************************************/ | ||
| 833 | /** @brief PLL test enable | ||
| 834 | */ | ||
| 835 | /****************************************************************************/ | ||
| 836 | static inline void chipcHw_pllTestEnable(void); | ||
| 837 | |||
| 838 | /****************************************************************************/ | ||
| 839 | /** @brief PLL2 test enable | ||
| 840 | */ | ||
| 841 | /****************************************************************************/ | ||
| 842 | static inline void chipcHw_pll2TestEnable(void); | ||
| 843 | |||
| 844 | /****************************************************************************/ | ||
| 845 | /** @brief PLL test disable | ||
| 846 | */ | ||
| 847 | /****************************************************************************/ | ||
| 848 | static inline void chipcHw_pllTestDisable(void); | ||
| 849 | |||
| 850 | /****************************************************************************/ | ||
| 851 | /** @brief PLL2 test disable | ||
| 852 | */ | ||
| 853 | /****************************************************************************/ | ||
| 854 | static inline void chipcHw_pll2TestDisable(void); | ||
| 855 | |||
| 856 | /****************************************************************************/ | ||
| 857 | /** @brief Get PLL test status | ||
| 858 | */ | ||
| 859 | /****************************************************************************/ | ||
| 860 | static inline int chipcHw_isPllTestEnable(void); | ||
| 861 | |||
| 862 | /****************************************************************************/ | ||
| 863 | /** @brief Get PLL2 test status | ||
| 864 | */ | ||
| 865 | /****************************************************************************/ | ||
| 866 | static inline int chipcHw_isPll2TestEnable(void); | ||
| 867 | |||
| 868 | /****************************************************************************/ | ||
| 869 | /** @brief PLL test select | ||
| 870 | */ | ||
| 871 | /****************************************************************************/ | ||
| 872 | static inline void chipcHw_pllTestSelect(uint32_t val); | ||
| 873 | |||
| 874 | /****************************************************************************/ | ||
| 875 | /** @brief PLL2 test select | ||
| 876 | */ | ||
| 877 | /****************************************************************************/ | ||
| 878 | static inline void chipcHw_pll2TestSelect(uint32_t val); | ||
| 879 | |||
| 880 | /****************************************************************************/ | ||
| 881 | /** @brief Get PLL test selected option | ||
| 882 | */ | ||
| 883 | /****************************************************************************/ | ||
| 884 | static inline uint8_t chipcHw_getPllTestSelected(void); | ||
| 885 | |||
| 886 | /****************************************************************************/ | ||
| 887 | /** @brief Get PLL2 test selected option | ||
| 888 | */ | ||
| 889 | /****************************************************************************/ | ||
| 890 | static inline uint8_t chipcHw_getPll2TestSelected(void); | ||
| 891 | |||
| 892 | /****************************************************************************/ | ||
| 893 | /** | ||
| 894 | * @brief Enables DDR SW phase alignment interrupt | ||
| 895 | */ | ||
| 896 | /****************************************************************************/ | ||
| 897 | static inline void chipcHw_ddrPhaseAlignInterruptEnable(void); | ||
| 898 | |||
| 899 | /****************************************************************************/ | ||
| 900 | /** | ||
| 901 | * @brief Disables DDR SW phase alignment interrupt | ||
| 902 | */ | ||
| 903 | /****************************************************************************/ | ||
| 904 | static inline void chipcHw_ddrPhaseAlignInterruptDisable(void); | ||
| 905 | |||
| 906 | /****************************************************************************/ | ||
| 907 | /** | ||
| 908 | * @brief Set VPM SW phase alignment interrupt mode | ||
| 909 | * | ||
| 910 | * This function sets VPM phase alignment interrupt | ||
| 911 | * | ||
| 912 | */ | ||
| 913 | /****************************************************************************/ | ||
| 914 | static inline void | ||
| 915 | chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode); | ||
| 916 | |||
| 917 | /****************************************************************************/ | ||
| 918 | /** | ||
| 919 | * @brief Enable DDR phase alignment in software | ||
| 920 | * | ||
| 921 | */ | ||
| 922 | /****************************************************************************/ | ||
| 923 | static inline void chipcHw_ddrSwPhaseAlignEnable(void); | ||
| 924 | |||
| 925 | /****************************************************************************/ | ||
| 926 | /** | ||
| 927 | * @brief Disable DDR phase alignment in software | ||
| 928 | * | ||
| 929 | */ | ||
| 930 | /****************************************************************************/ | ||
| 931 | static inline void chipcHw_ddrSwPhaseAlignDisable(void); | ||
| 932 | |||
| 933 | /****************************************************************************/ | ||
| 934 | /** | ||
| 935 | * @brief Enable DDR phase alignment in hardware | ||
| 936 | * | ||
| 937 | */ | ||
| 938 | /****************************************************************************/ | ||
| 939 | static inline void chipcHw_ddrHwPhaseAlignEnable(void); | ||
| 940 | |||
| 941 | /****************************************************************************/ | ||
| 942 | /** | ||
| 943 | * @brief Disable DDR phase alignment in hardware | ||
| 944 | * | ||
| 945 | */ | ||
| 946 | /****************************************************************************/ | ||
| 947 | static inline void chipcHw_ddrHwPhaseAlignDisable(void); | ||
| 948 | |||
| 949 | /****************************************************************************/ | ||
| 950 | /** | ||
| 951 | * @brief Enable VPM phase alignment in software | ||
| 952 | * | ||
| 953 | */ | ||
| 954 | /****************************************************************************/ | ||
| 955 | static inline void chipcHw_vpmSwPhaseAlignEnable(void); | ||
| 956 | |||
| 957 | /****************************************************************************/ | ||
| 958 | /** | ||
| 959 | * @brief Disable VPM phase alignment in software | ||
| 960 | * | ||
| 961 | */ | ||
| 962 | /****************************************************************************/ | ||
| 963 | static inline void chipcHw_vpmSwPhaseAlignDisable(void); | ||
| 964 | |||
| 965 | /****************************************************************************/ | ||
| 966 | /** | ||
| 967 | * @brief Enable VPM phase alignment in hardware | ||
| 968 | * | ||
| 969 | */ | ||
| 970 | /****************************************************************************/ | ||
| 971 | static inline void chipcHw_vpmHwPhaseAlignEnable(void); | ||
| 972 | |||
| 973 | /****************************************************************************/ | ||
| 974 | /** | ||
| 975 | * @brief Disable VPM phase alignment in hardware | ||
| 976 | * | ||
| 977 | */ | ||
| 978 | /****************************************************************************/ | ||
| 979 | static inline void chipcHw_vpmHwPhaseAlignDisable(void); | ||
| 980 | |||
| 981 | /****************************************************************************/ | ||
| 982 | /** | ||
| 983 | * @brief Set DDR phase alignment margin in hardware | ||
| 984 | * | ||
| 985 | */ | ||
| 986 | /****************************************************************************/ | ||
| 987 | static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin /* Margin alinging DDR phase */ | ||
| 988 | ); | ||
| 989 | |||
| 990 | /****************************************************************************/ | ||
| 991 | /** | ||
| 992 | * @brief Set VPM phase alignment margin in hardware | ||
| 993 | * | ||
| 994 | */ | ||
| 995 | /****************************************************************************/ | ||
| 996 | static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin /* Margin alinging VPM phase */ | ||
| 997 | ); | ||
| 998 | |||
| 999 | /****************************************************************************/ | ||
| 1000 | /** | ||
| 1001 | * @brief Checks DDR phase aligned status done by HW | ||
| 1002 | * | ||
| 1003 | * @return 1: When aligned | ||
| 1004 | * 0: When not aligned | ||
| 1005 | */ | ||
| 1006 | /****************************************************************************/ | ||
| 1007 | static inline uint32_t chipcHw_isDdrHwPhaseAligned(void); | ||
| 1008 | |||
| 1009 | /****************************************************************************/ | ||
| 1010 | /** | ||
| 1011 | * @brief Checks VPM phase aligned status done by HW | ||
| 1012 | * | ||
| 1013 | * @return 1: When aligned | ||
| 1014 | * 0: When not aligned | ||
| 1015 | */ | ||
| 1016 | /****************************************************************************/ | ||
| 1017 | static inline uint32_t chipcHw_isVpmHwPhaseAligned(void); | ||
| 1018 | |||
| 1019 | /****************************************************************************/ | ||
| 1020 | /** | ||
| 1021 | * @brief Get DDR phase aligned status done by HW | ||
| 1022 | * | ||
| 1023 | */ | ||
| 1024 | /****************************************************************************/ | ||
| 1025 | static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void); | ||
| 1026 | |||
| 1027 | /****************************************************************************/ | ||
| 1028 | /** | ||
| 1029 | * @brief Get VPM phase aligned status done by HW | ||
| 1030 | * | ||
| 1031 | */ | ||
| 1032 | /****************************************************************************/ | ||
| 1033 | static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void); | ||
| 1034 | |||
| 1035 | /****************************************************************************/ | ||
| 1036 | /** | ||
| 1037 | * @brief Get DDR phase control value | ||
| 1038 | * | ||
| 1039 | */ | ||
| 1040 | /****************************************************************************/ | ||
| 1041 | static inline uint32_t chipcHw_getDdrPhaseControl(void); | ||
| 1042 | |||
| 1043 | /****************************************************************************/ | ||
| 1044 | /** | ||
| 1045 | * @brief Get VPM phase control value | ||
| 1046 | * | ||
| 1047 | */ | ||
| 1048 | /****************************************************************************/ | ||
| 1049 | static inline uint32_t chipcHw_getVpmPhaseControl(void); | ||
| 1050 | |||
| 1051 | /****************************************************************************/ | ||
| 1052 | /** | ||
| 1053 | * @brief DDR phase alignment timeout count | ||
| 1054 | * | ||
| 1055 | * @note If HW fails to perform the phase alignment, it will trigger | ||
| 1056 | * a DDR phase alignment timeout interrupt. | ||
| 1057 | */ | ||
| 1058 | /****************************************************************************/ | ||
| 1059 | static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */ | ||
| 1060 | ); | ||
| 1061 | |||
| 1062 | /****************************************************************************/ | ||
| 1063 | /** | ||
| 1064 | * @brief VPM phase alignment timeout count | ||
| 1065 | * | ||
| 1066 | * @note If HW fails to perform the phase alignment, it will trigger | ||
| 1067 | * a VPM phase alignment timeout interrupt. | ||
| 1068 | */ | ||
| 1069 | /****************************************************************************/ | ||
| 1070 | static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle /* Timeout in bus cycle */ | ||
| 1071 | ); | ||
| 1072 | |||
| 1073 | /****************************************************************************/ | ||
| 1074 | /** | ||
| 1075 | * @brief DDR phase alignment timeout interrupt enable | ||
| 1076 | * | ||
| 1077 | */ | ||
| 1078 | /****************************************************************************/ | ||
| 1079 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void); | ||
| 1080 | |||
| 1081 | /****************************************************************************/ | ||
| 1082 | /** | ||
| 1083 | * @brief VPM phase alignment timeout interrupt enable | ||
| 1084 | * | ||
| 1085 | */ | ||
| 1086 | /****************************************************************************/ | ||
| 1087 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void); | ||
| 1088 | |||
| 1089 | /****************************************************************************/ | ||
| 1090 | /** | ||
| 1091 | * @brief DDR phase alignment timeout interrupt disable | ||
| 1092 | * | ||
| 1093 | */ | ||
| 1094 | /****************************************************************************/ | ||
| 1095 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void); | ||
| 1096 | |||
| 1097 | /****************************************************************************/ | ||
| 1098 | /** | ||
| 1099 | * @brief VPM phase alignment timeout interrupt disable | ||
| 1100 | * | ||
| 1101 | */ | ||
| 1102 | /****************************************************************************/ | ||
| 1103 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void); | ||
| 1104 | |||
| 1105 | /****************************************************************************/ | ||
| 1106 | /** | ||
| 1107 | * @brief Clear DDR phase alignment timeout interrupt | ||
| 1108 | * | ||
| 1109 | */ | ||
| 1110 | /****************************************************************************/ | ||
| 1111 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void); | ||
| 1112 | |||
| 1113 | /****************************************************************************/ | ||
| 1114 | /** | ||
| 1115 | * @brief Clear VPM phase alignment timeout interrupt | ||
| 1116 | * | ||
| 1117 | */ | ||
| 1118 | /****************************************************************************/ | ||
| 1119 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void); | ||
| 1120 | |||
| 1121 | /* ---- Private Constants and Types -------------------------------------- */ | ||
| 1122 | |||
| 1123 | #endif /* CHIPC_DEF_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h new file mode 100644 index 000000000000..c78833acb37a --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h | |||
| @@ -0,0 +1,1673 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef CHIPC_INLINE_H | ||
| 16 | #define CHIPC_INLINE_H | ||
| 17 | |||
| 18 | /* ---- Include Files ----------------------------------------------------- */ | ||
| 19 | |||
| 20 | #include <csp/errno.h> | ||
| 21 | #include <csp/reg.h> | ||
| 22 | #include <mach/csp/chipcHw_reg.h> | ||
| 23 | #include <mach/csp/chipcHw_def.h> | ||
| 24 | |||
| 25 | /* ---- Private Constants and Types --------------------------------------- */ | ||
| 26 | typedef enum { | ||
| 27 | chipcHw_OPTYPE_BYPASS, /* Bypass operation */ | ||
| 28 | chipcHw_OPTYPE_OUTPUT /* Output operation */ | ||
| 29 | } chipcHw_OPTYPE_e; | ||
| 30 | |||
| 31 | /* ---- Public Constants and Types ---------------------------------------- */ | ||
| 32 | /* ---- Public Variable Externs ------------------------------------------- */ | ||
| 33 | /* ---- Public Function Prototypes ---------------------------------------- */ | ||
| 34 | /* ---- Private Function Prototypes --------------------------------------- */ | ||
| 35 | static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, | ||
| 36 | chipcHw_OPTYPE_e type, int mode); | ||
| 37 | |||
| 38 | /****************************************************************************/ | ||
| 39 | /** | ||
| 40 | * @brief Get Numeric Chip ID | ||
| 41 | * | ||
| 42 | * This function returns Chip ID that includes the revison number | ||
| 43 | * | ||
| 44 | * @return Complete numeric Chip ID | ||
| 45 | * | ||
| 46 | */ | ||
| 47 | /****************************************************************************/ | ||
| 48 | static inline uint32_t chipcHw_getChipId(void) | ||
| 49 | { | ||
| 50 | return pChipcHw->ChipId; | ||
| 51 | } | ||
| 52 | |||
| 53 | /****************************************************************************/ | ||
| 54 | /** | ||
| 55 | * @brief Enable Spread Spectrum | ||
| 56 | * | ||
| 57 | * @note chipcHw_Init() must be called earlier | ||
| 58 | */ | ||
| 59 | /****************************************************************************/ | ||
| 60 | static inline void chipcHw_enableSpreadSpectrum(void) | ||
| 61 | { | ||
| 62 | if ((pChipcHw-> | ||
| 63 | PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != | ||
| 64 | chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) { | ||
| 65 | ddrcReg_PHY_ADDR_CTL_REGP->ssCfg = | ||
| 66 | (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) | | ||
| 67 | (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK << | ||
| 68 | ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT); | ||
| 69 | ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |= | ||
| 70 | ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; | ||
| 71 | } | ||
| 72 | } | ||
| 73 | |||
| 74 | /****************************************************************************/ | ||
| 75 | /** | ||
| 76 | * @brief Disable Spread Spectrum | ||
| 77 | * | ||
| 78 | */ | ||
| 79 | /****************************************************************************/ | ||
| 80 | static inline void chipcHw_disableSpreadSpectrum(void) | ||
| 81 | { | ||
| 82 | ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE; | ||
| 83 | } | ||
| 84 | |||
| 85 | /****************************************************************************/ | ||
| 86 | /** | ||
| 87 | * @brief Get Chip Product ID | ||
| 88 | * | ||
| 89 | * This function returns Chip Product ID | ||
| 90 | * | ||
| 91 | * @return Chip Product ID | ||
| 92 | */ | ||
| 93 | /****************************************************************************/ | ||
| 94 | static inline uint32_t chipcHw_getChipProductId(void) | ||
| 95 | { | ||
| 96 | return (pChipcHw-> | ||
| 97 | ChipId & chipcHw_REG_CHIPID_BASE_MASK) >> | ||
| 98 | chipcHw_REG_CHIPID_BASE_SHIFT; | ||
| 99 | } | ||
| 100 | |||
| 101 | /****************************************************************************/ | ||
| 102 | /** | ||
| 103 | * @brief Get revision number | ||
| 104 | * | ||
| 105 | * This function returns revision number of the chip | ||
| 106 | * | ||
| 107 | * @return Revision number | ||
| 108 | */ | ||
| 109 | /****************************************************************************/ | ||
| 110 | static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void) | ||
| 111 | { | ||
| 112 | return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK; | ||
| 113 | } | ||
| 114 | |||
| 115 | /****************************************************************************/ | ||
| 116 | /** | ||
| 117 | * @brief Enables bus interface clock | ||
| 118 | * | ||
| 119 | * Enables bus interface clock of various device | ||
| 120 | * | ||
| 121 | * @return void | ||
| 122 | * | ||
| 123 | * @note use chipcHw_REG_BUS_CLOCK_XXXX for mask | ||
| 124 | */ | ||
| 125 | /****************************************************************************/ | ||
| 126 | static inline void chipcHw_busInterfaceClockEnable(uint32_t mask) | ||
| 127 | { | ||
| 128 | reg32_modify_or(&pChipcHw->BusIntfClock, mask); | ||
| 129 | } | ||
| 130 | |||
| 131 | /****************************************************************************/ | ||
| 132 | /** | ||
| 133 | * @brief Disables bus interface clock | ||
| 134 | * | ||
| 135 | * Disables bus interface clock of various device | ||
| 136 | * | ||
| 137 | * @return void | ||
| 138 | * | ||
| 139 | * @note use chipcHw_REG_BUS_CLOCK_XXXX | ||
| 140 | */ | ||
| 141 | /****************************************************************************/ | ||
| 142 | static inline void chipcHw_busInterfaceClockDisable(uint32_t mask) | ||
| 143 | { | ||
| 144 | reg32_modify_and(&pChipcHw->BusIntfClock, ~mask); | ||
| 145 | } | ||
| 146 | |||
| 147 | /****************************************************************************/ | ||
| 148 | /** | ||
| 149 | * @brief Get status (enabled/disabled) of bus interface clock | ||
| 150 | * | ||
| 151 | * This function returns the status of devices' bus interface clock | ||
| 152 | * | ||
| 153 | * @return Bus interface clock | ||
| 154 | * | ||
| 155 | */ | ||
| 156 | /****************************************************************************/ | ||
| 157 | static inline uint32_t chipcHw_getBusInterfaceClockStatus(void) | ||
| 158 | { | ||
| 159 | return pChipcHw->BusIntfClock; | ||
| 160 | } | ||
| 161 | |||
| 162 | /****************************************************************************/ | ||
| 163 | /** | ||
| 164 | * @brief Enables various audio channels | ||
| 165 | * | ||
| 166 | * Enables audio channel | ||
| 167 | * | ||
| 168 | * @return void | ||
| 169 | * | ||
| 170 | * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX | ||
| 171 | */ | ||
| 172 | /****************************************************************************/ | ||
| 173 | static inline void chipcHw_audioChannelEnable(uint32_t mask) | ||
| 174 | { | ||
| 175 | reg32_modify_or(&pChipcHw->AudioEnable, mask); | ||
| 176 | } | ||
| 177 | |||
| 178 | /****************************************************************************/ | ||
| 179 | /** | ||
| 180 | * @brief Disables various audio channels | ||
| 181 | * | ||
| 182 | * Disables audio channel | ||
| 183 | * | ||
| 184 | * @return void | ||
| 185 | * | ||
| 186 | * @note use chipcHw_REG_AUDIO_CHANNEL_XXXXXX | ||
| 187 | */ | ||
| 188 | /****************************************************************************/ | ||
| 189 | static inline void chipcHw_audioChannelDisable(uint32_t mask) | ||
| 190 | { | ||
| 191 | reg32_modify_and(&pChipcHw->AudioEnable, ~mask); | ||
| 192 | } | ||
| 193 | |||
| 194 | /****************************************************************************/ | ||
| 195 | /** | ||
| 196 | * @brief Soft resets devices | ||
| 197 | * | ||
| 198 | * Soft resets various devices | ||
| 199 | * | ||
| 200 | * @return void | ||
| 201 | * | ||
| 202 | * @note use chipcHw_REG_SOFT_RESET_XXXXXX defines | ||
| 203 | */ | ||
| 204 | /****************************************************************************/ | ||
| 205 | static inline void chipcHw_softReset(uint64_t mask) | ||
| 206 | { | ||
| 207 | chipcHw_softResetEnable(mask); | ||
| 208 | chipcHw_softResetDisable(mask); | ||
| 209 | } | ||
| 210 | |||
| 211 | static inline void chipcHw_softResetDisable(uint64_t mask) | ||
| 212 | { | ||
| 213 | uint32_t ctrl1 = (uint32_t) mask; | ||
| 214 | uint32_t ctrl2 = (uint32_t) (mask >> 32); | ||
| 215 | |||
| 216 | /* Deassert module soft reset */ | ||
| 217 | REG_LOCAL_IRQ_SAVE; | ||
| 218 | pChipcHw->SoftReset1 ^= ctrl1; | ||
| 219 | pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); | ||
| 220 | REG_LOCAL_IRQ_RESTORE; | ||
| 221 | } | ||
| 222 | |||
| 223 | static inline void chipcHw_softResetEnable(uint64_t mask) | ||
| 224 | { | ||
| 225 | uint32_t ctrl1 = (uint32_t) mask; | ||
| 226 | uint32_t ctrl2 = (uint32_t) (mask >> 32); | ||
| 227 | uint32_t unhold = 0; | ||
| 228 | |||
| 229 | REG_LOCAL_IRQ_SAVE; | ||
| 230 | pChipcHw->SoftReset1 |= ctrl1; | ||
| 231 | /* Mask out unhold request bits */ | ||
| 232 | pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)); | ||
| 233 | |||
| 234 | /* Process unhold requests */ | ||
| 235 | if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) { | ||
| 236 | unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD; | ||
| 237 | } | ||
| 238 | |||
| 239 | if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) { | ||
| 240 | unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD; | ||
| 241 | } | ||
| 242 | |||
| 243 | if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) { | ||
| 244 | unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD; | ||
| 245 | } | ||
| 246 | |||
| 247 | if (unhold) { | ||
| 248 | /* Make sure unhold request is effective */ | ||
| 249 | pChipcHw->SoftReset1 &= ~unhold; | ||
| 250 | } | ||
| 251 | REG_LOCAL_IRQ_RESTORE; | ||
| 252 | } | ||
| 253 | |||
| 254 | /****************************************************************************/ | ||
| 255 | /** | ||
| 256 | * @brief Configures misc CHIP functionality | ||
| 257 | * | ||
| 258 | * Configures CHIP functionality | ||
| 259 | * | ||
| 260 | * @return void | ||
| 261 | * | ||
| 262 | * @note use chipcHw_REG_MISC_CTRL_XXXXXX | ||
| 263 | */ | ||
| 264 | /****************************************************************************/ | ||
| 265 | static inline void chipcHw_miscControl(uint32_t mask) | ||
| 266 | { | ||
| 267 | reg32_write(&pChipcHw->MiscCtrl, mask); | ||
| 268 | } | ||
| 269 | |||
| 270 | static inline void chipcHw_miscControlDisable(uint32_t mask) | ||
| 271 | { | ||
| 272 | reg32_modify_and(&pChipcHw->MiscCtrl, ~mask); | ||
| 273 | } | ||
| 274 | |||
| 275 | static inline void chipcHw_miscControlEnable(uint32_t mask) | ||
| 276 | { | ||
| 277 | reg32_modify_or(&pChipcHw->MiscCtrl, mask); | ||
| 278 | } | ||
| 279 | |||
| 280 | /****************************************************************************/ | ||
| 281 | /** | ||
| 282 | * @brief Set OTP options | ||
| 283 | * | ||
| 284 | * Set OTP options | ||
| 285 | * | ||
| 286 | * @return void | ||
| 287 | * | ||
| 288 | * @note use chipcHw_REG_OTP_XXXXXX | ||
| 289 | */ | ||
| 290 | /****************************************************************************/ | ||
| 291 | static inline void chipcHw_setOTPOption(uint64_t mask) | ||
| 292 | { | ||
| 293 | uint32_t ctrl1 = (uint32_t) mask; | ||
| 294 | uint32_t ctrl2 = (uint32_t) (mask >> 32); | ||
| 295 | |||
| 296 | reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1); | ||
| 297 | reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2); | ||
| 298 | } | ||
| 299 | |||
| 300 | /****************************************************************************/ | ||
| 301 | /** | ||
| 302 | * @brief Get sticky bits | ||
| 303 | * | ||
| 304 | * @return Sticky bit options of type chipcHw_REG_STICKY_XXXXXX | ||
| 305 | * | ||
| 306 | */ | ||
| 307 | /****************************************************************************/ | ||
| 308 | static inline uint32_t chipcHw_getStickyBits(void) | ||
| 309 | { | ||
| 310 | return pChipcHw->Sticky; | ||
| 311 | } | ||
| 312 | |||
| 313 | /****************************************************************************/ | ||
| 314 | /** | ||
| 315 | * @brief Set sticky bits | ||
| 316 | * | ||
| 317 | * @return void | ||
| 318 | * | ||
| 319 | * @note use chipcHw_REG_STICKY_XXXXXX | ||
| 320 | */ | ||
| 321 | /****************************************************************************/ | ||
| 322 | static inline void chipcHw_setStickyBits(uint32_t mask) | ||
| 323 | { | ||
| 324 | uint32_t bits = 0; | ||
| 325 | |||
| 326 | REG_LOCAL_IRQ_SAVE; | ||
| 327 | if (mask & chipcHw_REG_STICKY_POR_BROM) { | ||
| 328 | bits |= chipcHw_REG_STICKY_POR_BROM; | ||
| 329 | } else { | ||
| 330 | uint32_t sticky; | ||
| 331 | sticky = pChipcHw->Sticky; | ||
| 332 | |||
| 333 | if ((mask & chipcHw_REG_STICKY_BOOT_DONE) | ||
| 334 | && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) { | ||
| 335 | bits |= chipcHw_REG_STICKY_BOOT_DONE; | ||
| 336 | } | ||
| 337 | if ((mask & chipcHw_REG_STICKY_GENERAL_1) | ||
| 338 | && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) { | ||
| 339 | bits |= chipcHw_REG_STICKY_GENERAL_1; | ||
| 340 | } | ||
| 341 | if ((mask & chipcHw_REG_STICKY_GENERAL_2) | ||
| 342 | && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) { | ||
| 343 | bits |= chipcHw_REG_STICKY_GENERAL_2; | ||
| 344 | } | ||
| 345 | if ((mask & chipcHw_REG_STICKY_GENERAL_3) | ||
| 346 | && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) { | ||
| 347 | bits |= chipcHw_REG_STICKY_GENERAL_3; | ||
| 348 | } | ||
| 349 | if ((mask & chipcHw_REG_STICKY_GENERAL_4) | ||
| 350 | && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) { | ||
| 351 | bits |= chipcHw_REG_STICKY_GENERAL_4; | ||
| 352 | } | ||
| 353 | if ((mask & chipcHw_REG_STICKY_GENERAL_5) | ||
| 354 | && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) { | ||
| 355 | bits |= chipcHw_REG_STICKY_GENERAL_5; | ||
| 356 | } | ||
| 357 | } | ||
| 358 | pChipcHw->Sticky = bits; | ||
| 359 | REG_LOCAL_IRQ_RESTORE; | ||
| 360 | } | ||
| 361 | |||
| 362 | /****************************************************************************/ | ||
| 363 | /** | ||
| 364 | * @brief Clear sticky bits | ||
| 365 | * | ||
| 366 | * @return void | ||
| 367 | * | ||
| 368 | * @note use chipcHw_REG_STICKY_XXXXXX | ||
| 369 | */ | ||
| 370 | /****************************************************************************/ | ||
| 371 | static inline void chipcHw_clearStickyBits(uint32_t mask) | ||
| 372 | { | ||
| 373 | uint32_t bits = 0; | ||
| 374 | |||
| 375 | REG_LOCAL_IRQ_SAVE; | ||
| 376 | if (mask & | ||
| 377 | (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 | | ||
| 378 | chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 | | ||
| 379 | chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) { | ||
| 380 | uint32_t sticky = pChipcHw->Sticky; | ||
| 381 | |||
| 382 | if ((mask & chipcHw_REG_STICKY_BOOT_DONE) | ||
| 383 | && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) { | ||
| 384 | bits = chipcHw_REG_STICKY_BOOT_DONE; | ||
| 385 | mask &= ~chipcHw_REG_STICKY_BOOT_DONE; | ||
| 386 | } | ||
| 387 | if ((mask & chipcHw_REG_STICKY_GENERAL_1) | ||
| 388 | && (sticky & chipcHw_REG_STICKY_GENERAL_1)) { | ||
| 389 | bits |= chipcHw_REG_STICKY_GENERAL_1; | ||
| 390 | mask &= ~chipcHw_REG_STICKY_GENERAL_1; | ||
| 391 | } | ||
| 392 | if ((mask & chipcHw_REG_STICKY_GENERAL_2) | ||
| 393 | && (sticky & chipcHw_REG_STICKY_GENERAL_2)) { | ||
| 394 | bits |= chipcHw_REG_STICKY_GENERAL_2; | ||
| 395 | mask &= ~chipcHw_REG_STICKY_GENERAL_2; | ||
| 396 | } | ||
| 397 | if ((mask & chipcHw_REG_STICKY_GENERAL_3) | ||
| 398 | && (sticky & chipcHw_REG_STICKY_GENERAL_3)) { | ||
| 399 | bits |= chipcHw_REG_STICKY_GENERAL_3; | ||
| 400 | mask &= ~chipcHw_REG_STICKY_GENERAL_3; | ||
| 401 | } | ||
| 402 | if ((mask & chipcHw_REG_STICKY_GENERAL_4) | ||
| 403 | && (sticky & chipcHw_REG_STICKY_GENERAL_4)) { | ||
| 404 | bits |= chipcHw_REG_STICKY_GENERAL_4; | ||
| 405 | mask &= ~chipcHw_REG_STICKY_GENERAL_4; | ||
| 406 | } | ||
| 407 | if ((mask & chipcHw_REG_STICKY_GENERAL_5) | ||
| 408 | && (sticky & chipcHw_REG_STICKY_GENERAL_5)) { | ||
| 409 | bits |= chipcHw_REG_STICKY_GENERAL_5; | ||
| 410 | mask &= ~chipcHw_REG_STICKY_GENERAL_5; | ||
| 411 | } | ||
| 412 | } | ||
| 413 | pChipcHw->Sticky = bits | mask; | ||
| 414 | REG_LOCAL_IRQ_RESTORE; | ||
| 415 | } | ||
| 416 | |||
| 417 | /****************************************************************************/ | ||
| 418 | /** | ||
| 419 | * @brief Get software strap value | ||
| 420 | * | ||
| 421 | * Retrieves software strap value | ||
| 422 | * | ||
| 423 | * @return Software strap value | ||
| 424 | * | ||
| 425 | */ | ||
| 426 | /****************************************************************************/ | ||
| 427 | static inline uint32_t chipcHw_getSoftStraps(void) | ||
| 428 | { | ||
| 429 | return pChipcHw->SoftStraps; | ||
| 430 | } | ||
| 431 | |||
| 432 | /****************************************************************************/ | ||
| 433 | /** | ||
| 434 | * @brief Set software override strap options | ||
| 435 | * | ||
| 436 | * set software override strap options | ||
| 437 | * | ||
| 438 | * @return nothing | ||
| 439 | * | ||
| 440 | */ | ||
| 441 | /****************************************************************************/ | ||
| 442 | static inline void chipcHw_setSoftStraps(uint32_t strapOptions) | ||
| 443 | { | ||
| 444 | reg32_write(&pChipcHw->SoftStraps, strapOptions); | ||
| 445 | } | ||
| 446 | |||
| 447 | /****************************************************************************/ | ||
| 448 | /** | ||
| 449 | * @brief Get Pin Strap Options | ||
| 450 | * | ||
| 451 | * This function returns the raw boot strap options | ||
| 452 | * | ||
| 453 | * @return strap options | ||
| 454 | * | ||
| 455 | */ | ||
| 456 | /****************************************************************************/ | ||
| 457 | static inline uint32_t chipcHw_getPinStraps(void) | ||
| 458 | { | ||
| 459 | return pChipcHw->PinStraps; | ||
| 460 | } | ||
| 461 | |||
| 462 | /****************************************************************************/ | ||
| 463 | /** | ||
| 464 | * @brief Get Valid Strap Options | ||
| 465 | * | ||
| 466 | * This function returns the valid raw boot strap options | ||
| 467 | * | ||
| 468 | * @return strap options | ||
| 469 | * | ||
| 470 | */ | ||
| 471 | /****************************************************************************/ | ||
| 472 | static inline uint32_t chipcHw_getValidStraps(void) | ||
| 473 | { | ||
| 474 | uint32_t softStraps; | ||
| 475 | |||
| 476 | /* | ||
| 477 | ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps | ||
| 478 | ** which copies HW straps to soft straps if there is no override | ||
| 479 | */ | ||
| 480 | softStraps = chipcHw_getSoftStraps(); | ||
| 481 | |||
| 482 | return softStraps; | ||
| 483 | } | ||
| 484 | |||
| 485 | /****************************************************************************/ | ||
| 486 | /** | ||
| 487 | * @brief Initialize valid pin strap options | ||
| 488 | * | ||
| 489 | * Retrieves valid pin strap options by copying HW strap options to soft register | ||
| 490 | * (if chipcHw_STRAPS_SOFT_OVERRIDE not set) | ||
| 491 | * | ||
| 492 | * @return nothing | ||
| 493 | * | ||
| 494 | */ | ||
| 495 | /****************************************************************************/ | ||
| 496 | static inline void chipcHw_initValidStraps(void) | ||
| 497 | { | ||
| 498 | uint32_t softStraps; | ||
| 499 | |||
| 500 | REG_LOCAL_IRQ_SAVE; | ||
| 501 | softStraps = chipcHw_getSoftStraps(); | ||
| 502 | |||
| 503 | if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) { | ||
| 504 | /* Copy HW straps to software straps */ | ||
| 505 | chipcHw_setSoftStraps(chipcHw_getPinStraps()); | ||
| 506 | } | ||
| 507 | REG_LOCAL_IRQ_RESTORE; | ||
| 508 | } | ||
| 509 | |||
| 510 | /****************************************************************************/ | ||
| 511 | /** | ||
| 512 | * @brief Get boot device | ||
| 513 | * | ||
| 514 | * This function returns the device type used in booting the system | ||
| 515 | * | ||
| 516 | * @return Boot device of type chipcHw_BOOT_DEVICE | ||
| 517 | * | ||
| 518 | */ | ||
| 519 | /****************************************************************************/ | ||
| 520 | static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void) | ||
| 521 | { | ||
| 522 | return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK; | ||
| 523 | } | ||
| 524 | |||
| 525 | /****************************************************************************/ | ||
| 526 | /** | ||
| 527 | * @brief Get boot mode | ||
| 528 | * | ||
| 529 | * This function returns the way the system was booted | ||
| 530 | * | ||
| 531 | * @return Boot mode of type chipcHw_BOOT_MODE | ||
| 532 | * | ||
| 533 | */ | ||
| 534 | /****************************************************************************/ | ||
| 535 | static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void) | ||
| 536 | { | ||
| 537 | return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK; | ||
| 538 | } | ||
| 539 | |||
| 540 | /****************************************************************************/ | ||
| 541 | /** | ||
| 542 | * @brief Get NAND flash page size | ||
| 543 | * | ||
| 544 | * This function returns the NAND device page size | ||
| 545 | * | ||
| 546 | * @return Boot NAND device page size | ||
| 547 | * | ||
| 548 | */ | ||
| 549 | /****************************************************************************/ | ||
| 550 | static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void) | ||
| 551 | { | ||
| 552 | return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK; | ||
| 553 | } | ||
| 554 | |||
| 555 | /****************************************************************************/ | ||
| 556 | /** | ||
| 557 | * @brief Get NAND flash address cycle configuration | ||
| 558 | * | ||
| 559 | * This function returns the NAND flash address cycle configuration | ||
| 560 | * | ||
| 561 | * @return 0 = Do not extra address cycle, 1 = Add extra cycle | ||
| 562 | * | ||
| 563 | */ | ||
| 564 | /****************************************************************************/ | ||
| 565 | static inline int chipcHw_getNandExtraCycle(void) | ||
| 566 | { | ||
| 567 | if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) { | ||
| 568 | return 1; | ||
| 569 | } else { | ||
| 570 | return 0; | ||
| 571 | } | ||
| 572 | } | ||
| 573 | |||
| 574 | /****************************************************************************/ | ||
| 575 | /** | ||
| 576 | * @brief Activates PIF interface | ||
| 577 | * | ||
| 578 | * This function activates PIF interface by taking control of LCD pins | ||
| 579 | * | ||
| 580 | * @note | ||
| 581 | * When activated, LCD pins will be defined as follows for PIF operation | ||
| 582 | * | ||
| 583 | * CLD[17:0] = pif_data[17:0] | ||
| 584 | * CLD[23:18] = pif_address[5:0] | ||
| 585 | * CLPOWER = pif_wr_str | ||
| 586 | * CLCP = pif_rd_str | ||
| 587 | * CLAC = pif_hat1 | ||
| 588 | * CLFP = pif_hrdy1 | ||
| 589 | * CLLP = pif_hat2 | ||
| 590 | * GPIO[42] = pif_hrdy2 | ||
| 591 | * | ||
| 592 | * In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin | ||
| 593 | * | ||
| 594 | */ | ||
| 595 | /****************************************************************************/ | ||
| 596 | static inline void chipcHw_activatePifInterface(void) | ||
| 597 | { | ||
| 598 | reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE); | ||
| 599 | } | ||
| 600 | |||
| 601 | /****************************************************************************/ | ||
| 602 | /** | ||
| 603 | * @brief Activates LCD interface | ||
| 604 | * | ||
| 605 | * This function activates LCD interface | ||
| 606 | * | ||
| 607 | * @note | ||
| 608 | * When activated, LCD pins will be defined as follows | ||
| 609 | * | ||
| 610 | * CLD[17:0] = LCD data | ||
| 611 | * CLD[23:18] = LCD data | ||
| 612 | * CLPOWER = LCD power | ||
| 613 | * CLCP = | ||
| 614 | * CLAC = LCD ack | ||
| 615 | * CLFP = | ||
| 616 | * CLLP = | ||
| 617 | */ | ||
| 618 | /****************************************************************************/ | ||
| 619 | static inline void chipcHw_activateLcdInterface(void) | ||
| 620 | { | ||
| 621 | reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE); | ||
| 622 | } | ||
| 623 | |||
| 624 | /****************************************************************************/ | ||
| 625 | /** | ||
| 626 | * @brief Deactivates PIF/LCD interface | ||
| 627 | * | ||
| 628 | * This function deactivates PIF/LCD interface | ||
| 629 | * | ||
| 630 | * @note | ||
| 631 | * When deactivated LCD pins will be in rti-stated | ||
| 632 | * | ||
| 633 | */ | ||
| 634 | /****************************************************************************/ | ||
| 635 | static inline void chipcHw_deactivatePifLcdInterface(void) | ||
| 636 | { | ||
| 637 | reg32_write(&pChipcHw->LcdPifMode, 0); | ||
| 638 | } | ||
| 639 | |||
| 640 | /****************************************************************************/ | ||
| 641 | /** | ||
| 642 | * @brief Select GE2 | ||
| 643 | * | ||
| 644 | * This function select GE2 as the graphic engine | ||
| 645 | * | ||
| 646 | */ | ||
| 647 | /****************************************************************************/ | ||
| 648 | static inline void chipcHw_selectGE2(void) | ||
| 649 | { | ||
| 650 | reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL); | ||
| 651 | } | ||
| 652 | |||
| 653 | /****************************************************************************/ | ||
| 654 | /** | ||
| 655 | * @brief Select GE3 | ||
| 656 | * | ||
| 657 | * This function select GE3 as the graphic engine | ||
| 658 | * | ||
| 659 | */ | ||
| 660 | /****************************************************************************/ | ||
| 661 | static inline void chipcHw_selectGE3(void) | ||
| 662 | { | ||
| 663 | reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL); | ||
| 664 | } | ||
| 665 | |||
| 666 | /****************************************************************************/ | ||
| 667 | /** | ||
| 668 | * @brief Get to know the configuration of GPIO pin | ||
| 669 | * | ||
| 670 | */ | ||
| 671 | /****************************************************************************/ | ||
| 672 | static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin) | ||
| 673 | { | ||
| 674 | return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) & | ||
| 675 | (chipcHw_REG_GPIO_MUX_MASK << | ||
| 676 | chipcHw_REG_GPIO_MUX_POSITION(pin))) >> | ||
| 677 | chipcHw_REG_GPIO_MUX_POSITION(pin); | ||
| 678 | } | ||
| 679 | |||
| 680 | /****************************************************************************/ | ||
| 681 | /** | ||
| 682 | * @brief Configure GPIO pin function | ||
| 683 | * | ||
| 684 | */ | ||
| 685 | /****************************************************************************/ | ||
| 686 | static inline void chipcHw_setGpioPinFunction(int pin, | ||
| 687 | chipcHw_GPIO_FUNCTION_e func) | ||
| 688 | { | ||
| 689 | REG_LOCAL_IRQ_SAVE; | ||
| 690 | *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &= | ||
| 691 | ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin)); | ||
| 692 | *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |= | ||
| 693 | func << chipcHw_REG_GPIO_MUX_POSITION(pin); | ||
| 694 | REG_LOCAL_IRQ_RESTORE; | ||
| 695 | } | ||
| 696 | |||
| 697 | /****************************************************************************/ | ||
| 698 | /** | ||
| 699 | * @brief Set Pin slew rate | ||
| 700 | * | ||
| 701 | * This function sets the slew of individual pin | ||
| 702 | * | ||
| 703 | */ | ||
| 704 | /****************************************************************************/ | ||
| 705 | static inline void chipcHw_setPinSlewRate(uint32_t pin, | ||
| 706 | chipcHw_PIN_SLEW_RATE_e slewRate) | ||
| 707 | { | ||
| 708 | REG_LOCAL_IRQ_SAVE; | ||
| 709 | *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &= | ||
| 710 | ~(chipcHw_REG_SLEW_RATE_MASK << | ||
| 711 | chipcHw_REG_SLEW_RATE_POSITION(pin)); | ||
| 712 | *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |= | ||
| 713 | (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin); | ||
| 714 | REG_LOCAL_IRQ_RESTORE; | ||
| 715 | } | ||
| 716 | |||
| 717 | /****************************************************************************/ | ||
| 718 | /** | ||
| 719 | * @brief Set Pin output drive current | ||
| 720 | * | ||
| 721 | * This function sets output drive current of individual pin | ||
| 722 | * | ||
| 723 | * Note: Avoid the use of the word 'current' since linux headers define this | ||
| 724 | * to be the current task. | ||
| 725 | */ | ||
| 726 | /****************************************************************************/ | ||
| 727 | static inline void chipcHw_setPinOutputCurrent(uint32_t pin, | ||
| 728 | chipcHw_PIN_CURRENT_STRENGTH_e | ||
| 729 | curr) | ||
| 730 | { | ||
| 731 | REG_LOCAL_IRQ_SAVE; | ||
| 732 | *((uint32_t *) chipcHw_REG_CURRENT(pin)) &= | ||
| 733 | ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin)); | ||
| 734 | *((uint32_t *) chipcHw_REG_CURRENT(pin)) |= | ||
| 735 | (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin); | ||
| 736 | REG_LOCAL_IRQ_RESTORE; | ||
| 737 | } | ||
| 738 | |||
| 739 | /****************************************************************************/ | ||
| 740 | /** | ||
| 741 | * @brief Set Pin pullup register | ||
| 742 | * | ||
| 743 | * This function sets pullup register of individual pin | ||
| 744 | * | ||
| 745 | */ | ||
| 746 | /****************************************************************************/ | ||
| 747 | static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup) | ||
| 748 | { | ||
| 749 | REG_LOCAL_IRQ_SAVE; | ||
| 750 | *((uint32_t *) chipcHw_REG_PULLUP(pin)) &= | ||
| 751 | ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin)); | ||
| 752 | *((uint32_t *) chipcHw_REG_PULLUP(pin)) |= | ||
| 753 | (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin); | ||
| 754 | REG_LOCAL_IRQ_RESTORE; | ||
| 755 | } | ||
| 756 | |||
| 757 | /****************************************************************************/ | ||
| 758 | /** | ||
| 759 | * @brief Set Pin input type | ||
| 760 | * | ||
| 761 | * This function sets input type of individual pin | ||
| 762 | * | ||
| 763 | */ | ||
| 764 | /****************************************************************************/ | ||
| 765 | static inline void chipcHw_setPinInputType(uint32_t pin, | ||
| 766 | chipcHw_PIN_INPUTTYPE_e inputType) | ||
| 767 | { | ||
| 768 | REG_LOCAL_IRQ_SAVE; | ||
| 769 | *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &= | ||
| 770 | ~(chipcHw_REG_INPUTTYPE_MASK << | ||
| 771 | chipcHw_REG_INPUTTYPE_POSITION(pin)); | ||
| 772 | *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |= | ||
| 773 | (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin); | ||
| 774 | REG_LOCAL_IRQ_RESTORE; | ||
| 775 | } | ||
| 776 | |||
| 777 | /****************************************************************************/ | ||
| 778 | /** | ||
| 779 | * @brief Power up the USB PHY | ||
| 780 | * | ||
| 781 | * This function powers up the USB PHY | ||
| 782 | * | ||
| 783 | */ | ||
| 784 | /****************************************************************************/ | ||
| 785 | static inline void chipcHw_powerUpUsbPhy(void) | ||
| 786 | { | ||
| 787 | reg32_modify_and(&pChipcHw->MiscCtrl, | ||
| 788 | chipcHw_REG_MISC_CTRL_USB_POWERON); | ||
| 789 | } | ||
| 790 | |||
| 791 | /****************************************************************************/ | ||
| 792 | /** | ||
| 793 | * @brief Power down the USB PHY | ||
| 794 | * | ||
| 795 | * This function powers down the USB PHY | ||
| 796 | * | ||
| 797 | */ | ||
| 798 | /****************************************************************************/ | ||
| 799 | static inline void chipcHw_powerDownUsbPhy(void) | ||
| 800 | { | ||
| 801 | reg32_modify_or(&pChipcHw->MiscCtrl, | ||
| 802 | chipcHw_REG_MISC_CTRL_USB_POWEROFF); | ||
| 803 | } | ||
| 804 | |||
| 805 | /****************************************************************************/ | ||
| 806 | /** | ||
| 807 | * @brief Set the 2nd USB as host | ||
| 808 | * | ||
| 809 | * This function sets the 2nd USB as host | ||
| 810 | * | ||
| 811 | */ | ||
| 812 | /****************************************************************************/ | ||
| 813 | static inline void chipcHw_setUsbHost(void) | ||
| 814 | { | ||
| 815 | reg32_modify_or(&pChipcHw->MiscCtrl, | ||
| 816 | chipcHw_REG_MISC_CTRL_USB_MODE_HOST); | ||
| 817 | } | ||
| 818 | |||
| 819 | /****************************************************************************/ | ||
| 820 | /** | ||
| 821 | * @brief Set the 2nd USB as device | ||
| 822 | * | ||
| 823 | * This function sets the 2nd USB as device | ||
| 824 | * | ||
| 825 | */ | ||
| 826 | /****************************************************************************/ | ||
| 827 | static inline void chipcHw_setUsbDevice(void) | ||
| 828 | { | ||
| 829 | reg32_modify_and(&pChipcHw->MiscCtrl, | ||
| 830 | chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE); | ||
| 831 | } | ||
| 832 | |||
| 833 | /****************************************************************************/ | ||
| 834 | /** | ||
| 835 | * @brief Lower layer funtion to enable/disable a clock of a certain device | ||
| 836 | * | ||
| 837 | * This function enables/disables a core clock | ||
| 838 | * | ||
| 839 | */ | ||
| 840 | /****************************************************************************/ | ||
| 841 | static inline void chipcHw_setClock(chipcHw_CLOCK_e clock, | ||
| 842 | chipcHw_OPTYPE_e type, int mode) | ||
| 843 | { | ||
| 844 | volatile uint32_t *pPLLReg = (uint32_t *) 0x0; | ||
| 845 | volatile uint32_t *pClockCtrl = (uint32_t *) 0x0; | ||
| 846 | |||
| 847 | switch (clock) { | ||
| 848 | case chipcHw_CLOCK_DDR: | ||
| 849 | pPLLReg = &pChipcHw->DDRClock; | ||
| 850 | break; | ||
| 851 | case chipcHw_CLOCK_ARM: | ||
| 852 | pPLLReg = &pChipcHw->ARMClock; | ||
| 853 | break; | ||
| 854 | case chipcHw_CLOCK_ESW: | ||
| 855 | pPLLReg = &pChipcHw->ESWClock; | ||
| 856 | break; | ||
| 857 | case chipcHw_CLOCK_VPM: | ||
| 858 | pPLLReg = &pChipcHw->VPMClock; | ||
| 859 | break; | ||
| 860 | case chipcHw_CLOCK_ESW125: | ||
| 861 | pPLLReg = &pChipcHw->ESW125Clock; | ||
| 862 | break; | ||
| 863 | case chipcHw_CLOCK_UART: | ||
| 864 | pPLLReg = &pChipcHw->UARTClock; | ||
| 865 | break; | ||
| 866 | case chipcHw_CLOCK_SDIO0: | ||
| 867 | pPLLReg = &pChipcHw->SDIO0Clock; | ||
| 868 | break; | ||
| 869 | case chipcHw_CLOCK_SDIO1: | ||
| 870 | pPLLReg = &pChipcHw->SDIO1Clock; | ||
| 871 | break; | ||
| 872 | case chipcHw_CLOCK_SPI: | ||
| 873 | pPLLReg = &pChipcHw->SPIClock; | ||
| 874 | break; | ||
| 875 | case chipcHw_CLOCK_ETM: | ||
| 876 | pPLLReg = &pChipcHw->ETMClock; | ||
| 877 | break; | ||
| 878 | case chipcHw_CLOCK_USB: | ||
| 879 | pPLLReg = &pChipcHw->USBClock; | ||
| 880 | if (type == chipcHw_OPTYPE_OUTPUT) { | ||
| 881 | if (mode) { | ||
| 882 | reg32_modify_and(pPLLReg, | ||
| 883 | ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 884 | } else { | ||
| 885 | reg32_modify_or(pPLLReg, | ||
| 886 | chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 887 | } | ||
| 888 | } | ||
| 889 | break; | ||
| 890 | case chipcHw_CLOCK_LCD: | ||
| 891 | pPLLReg = &pChipcHw->LCDClock; | ||
| 892 | if (type == chipcHw_OPTYPE_OUTPUT) { | ||
| 893 | if (mode) { | ||
| 894 | reg32_modify_and(pPLLReg, | ||
| 895 | ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 896 | } else { | ||
| 897 | reg32_modify_or(pPLLReg, | ||
| 898 | chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 899 | } | ||
| 900 | } | ||
| 901 | break; | ||
| 902 | case chipcHw_CLOCK_APM: | ||
| 903 | pPLLReg = &pChipcHw->APMClock; | ||
| 904 | if (type == chipcHw_OPTYPE_OUTPUT) { | ||
| 905 | if (mode) { | ||
| 906 | reg32_modify_and(pPLLReg, | ||
| 907 | ~chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 908 | } else { | ||
| 909 | reg32_modify_or(pPLLReg, | ||
| 910 | chipcHw_REG_PLL_CLOCK_POWER_DOWN); | ||
| 911 | } | ||
| 912 | } | ||
| 913 | break; | ||
| 914 | case chipcHw_CLOCK_BUS: | ||
| 915 | pClockCtrl = &pChipcHw->ACLKClock; | ||
| 916 | break; | ||
| 917 | case chipcHw_CLOCK_OTP: | ||
| 918 | pClockCtrl = &pChipcHw->OTPClock; | ||
| 919 | break; | ||
| 920 | case chipcHw_CLOCK_I2C: | ||
| 921 | pClockCtrl = &pChipcHw->I2CClock; | ||
| 922 | break; | ||
| 923 | case chipcHw_CLOCK_I2S0: | ||
| 924 | pClockCtrl = &pChipcHw->I2S0Clock; | ||
| 925 | break; | ||
| 926 | case chipcHw_CLOCK_RTBUS: | ||
| 927 | pClockCtrl = &pChipcHw->RTBUSClock; | ||
| 928 | break; | ||
| 929 | case chipcHw_CLOCK_APM100: | ||
| 930 | pClockCtrl = &pChipcHw->APM100Clock; | ||
| 931 | break; | ||
| 932 | case chipcHw_CLOCK_TSC: | ||
| 933 | pClockCtrl = &pChipcHw->TSCClock; | ||
| 934 | break; | ||
| 935 | case chipcHw_CLOCK_LED: | ||
| 936 | pClockCtrl = &pChipcHw->LEDClock; | ||
| 937 | break; | ||
| 938 | case chipcHw_CLOCK_I2S1: | ||
| 939 | pClockCtrl = &pChipcHw->I2S1Clock; | ||
| 940 | break; | ||
| 941 | } | ||
| 942 | |||
| 943 | if (pPLLReg) { | ||
| 944 | switch (type) { | ||
| 945 | case chipcHw_OPTYPE_OUTPUT: | ||
| 946 | /* PLL clock output enable/disable */ | ||
| 947 | if (mode) { | ||
| 948 | if (clock == chipcHw_CLOCK_DDR) { | ||
| 949 | /* DDR clock enable is inverted */ | ||
| 950 | reg32_modify_and(pPLLReg, | ||
| 951 | ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); | ||
| 952 | } else { | ||
| 953 | reg32_modify_or(pPLLReg, | ||
| 954 | chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); | ||
| 955 | } | ||
| 956 | } else { | ||
| 957 | if (clock == chipcHw_CLOCK_DDR) { | ||
| 958 | /* DDR clock disable is inverted */ | ||
| 959 | reg32_modify_or(pPLLReg, | ||
| 960 | chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); | ||
| 961 | } else { | ||
| 962 | reg32_modify_and(pPLLReg, | ||
| 963 | ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE); | ||
| 964 | } | ||
| 965 | } | ||
| 966 | break; | ||
| 967 | case chipcHw_OPTYPE_BYPASS: | ||
| 968 | /* PLL clock bypass enable/disable */ | ||
| 969 | if (mode) { | ||
| 970 | reg32_modify_or(pPLLReg, | ||
| 971 | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); | ||
| 972 | } else { | ||
| 973 | reg32_modify_and(pPLLReg, | ||
| 974 | ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT); | ||
| 975 | } | ||
| 976 | break; | ||
| 977 | } | ||
| 978 | } else if (pClockCtrl) { | ||
| 979 | switch (type) { | ||
| 980 | case chipcHw_OPTYPE_OUTPUT: | ||
| 981 | if (mode) { | ||
| 982 | reg32_modify_or(pClockCtrl, | ||
| 983 | chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE); | ||
| 984 | } else { | ||
| 985 | reg32_modify_and(pClockCtrl, | ||
| 986 | ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE); | ||
| 987 | } | ||
| 988 | break; | ||
| 989 | case chipcHw_OPTYPE_BYPASS: | ||
| 990 | if (mode) { | ||
| 991 | reg32_modify_or(pClockCtrl, | ||
| 992 | chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); | ||
| 993 | } else { | ||
| 994 | reg32_modify_and(pClockCtrl, | ||
| 995 | ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT); | ||
| 996 | } | ||
| 997 | break; | ||
| 998 | } | ||
| 999 | } | ||
| 1000 | } | ||
| 1001 | |||
| 1002 | /****************************************************************************/ | ||
| 1003 | /** | ||
| 1004 | * @brief Disables a core clock of a certain device | ||
| 1005 | * | ||
| 1006 | * This function disables a core clock | ||
| 1007 | * | ||
| 1008 | * @note no change in power consumption | ||
| 1009 | */ | ||
| 1010 | /****************************************************************************/ | ||
| 1011 | static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock) | ||
| 1012 | { | ||
| 1013 | |||
| 1014 | /* Disable output of the clock */ | ||
| 1015 | chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0); | ||
| 1016 | } | ||
| 1017 | |||
| 1018 | /****************************************************************************/ | ||
| 1019 | /** | ||
| 1020 | * @brief Enable a core clock of a certain device | ||
| 1021 | * | ||
| 1022 | * This function enables a core clock | ||
| 1023 | * | ||
| 1024 | * @note no change in power consumption | ||
| 1025 | */ | ||
| 1026 | /****************************************************************************/ | ||
| 1027 | static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock) | ||
| 1028 | { | ||
| 1029 | |||
| 1030 | /* Enable output of the clock */ | ||
| 1031 | chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1); | ||
| 1032 | } | ||
| 1033 | |||
| 1034 | /****************************************************************************/ | ||
| 1035 | /** | ||
| 1036 | * @brief Enables bypass clock of a certain device | ||
| 1037 | * | ||
| 1038 | * This function enables bypass clock | ||
| 1039 | * | ||
| 1040 | * @note Doesnot affect the bus interface clock | ||
| 1041 | */ | ||
| 1042 | /****************************************************************************/ | ||
| 1043 | static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock) | ||
| 1044 | { | ||
| 1045 | /* Enable bypass clock */ | ||
| 1046 | chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1); | ||
| 1047 | } | ||
| 1048 | |||
| 1049 | /****************************************************************************/ | ||
| 1050 | /** | ||
| 1051 | * @brief Disabled bypass clock of a certain device | ||
| 1052 | * | ||
| 1053 | * This function disables bypass clock | ||
| 1054 | * | ||
| 1055 | * @note Doesnot affect the bus interface clock | ||
| 1056 | */ | ||
| 1057 | /****************************************************************************/ | ||
| 1058 | static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock) | ||
| 1059 | { | ||
| 1060 | /* Disable bypass clock */ | ||
| 1061 | chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0); | ||
| 1062 | |||
| 1063 | } | ||
| 1064 | |||
| 1065 | /****************************************************************************/ | ||
| 1066 | /** @brief Checks if software strap is enabled | ||
| 1067 | * | ||
| 1068 | * @return 1 : When enable | ||
| 1069 | * 0 : When disable | ||
| 1070 | */ | ||
| 1071 | /****************************************************************************/ | ||
| 1072 | static inline int chipcHw_isSoftwareStrapsEnable(void) | ||
| 1073 | { | ||
| 1074 | return pChipcHw->SoftStraps & 0x00000001; | ||
| 1075 | } | ||
| 1076 | |||
| 1077 | /****************************************************************************/ | ||
| 1078 | /** @brief Enable software strap | ||
| 1079 | */ | ||
| 1080 | /****************************************************************************/ | ||
| 1081 | static inline void chipcHw_softwareStrapsEnable(void) | ||
| 1082 | { | ||
| 1083 | reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001); | ||
| 1084 | } | ||
| 1085 | |||
| 1086 | /****************************************************************************/ | ||
| 1087 | /** @brief Disable software strap | ||
| 1088 | */ | ||
| 1089 | /****************************************************************************/ | ||
| 1090 | static inline void chipcHw_softwareStrapsDisable(void) | ||
| 1091 | { | ||
| 1092 | reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001)); | ||
| 1093 | } | ||
| 1094 | |||
| 1095 | /****************************************************************************/ | ||
| 1096 | /** @brief PLL test enable | ||
| 1097 | */ | ||
| 1098 | /****************************************************************************/ | ||
| 1099 | static inline void chipcHw_pllTestEnable(void) | ||
| 1100 | { | ||
| 1101 | reg32_modify_or(&pChipcHw->PLLConfig, | ||
| 1102 | chipcHw_REG_PLL_CONFIG_TEST_ENABLE); | ||
| 1103 | } | ||
| 1104 | |||
| 1105 | /****************************************************************************/ | ||
| 1106 | /** @brief PLL2 test enable | ||
| 1107 | */ | ||
| 1108 | /****************************************************************************/ | ||
| 1109 | static inline void chipcHw_pll2TestEnable(void) | ||
| 1110 | { | ||
| 1111 | reg32_modify_or(&pChipcHw->PLLConfig2, | ||
| 1112 | chipcHw_REG_PLL_CONFIG_TEST_ENABLE); | ||
| 1113 | } | ||
| 1114 | |||
| 1115 | /****************************************************************************/ | ||
| 1116 | /** @brief PLL test disable | ||
| 1117 | */ | ||
| 1118 | /****************************************************************************/ | ||
| 1119 | static inline void chipcHw_pllTestDisable(void) | ||
| 1120 | { | ||
| 1121 | reg32_modify_and(&pChipcHw->PLLConfig, | ||
| 1122 | ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE); | ||
| 1123 | } | ||
| 1124 | |||
| 1125 | /****************************************************************************/ | ||
| 1126 | /** @brief PLL2 test disable | ||
| 1127 | */ | ||
| 1128 | /****************************************************************************/ | ||
| 1129 | static inline void chipcHw_pll2TestDisable(void) | ||
| 1130 | { | ||
| 1131 | reg32_modify_and(&pChipcHw->PLLConfig2, | ||
| 1132 | ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE); | ||
| 1133 | } | ||
| 1134 | |||
| 1135 | /****************************************************************************/ | ||
| 1136 | /** @brief Get PLL test status | ||
| 1137 | */ | ||
| 1138 | /****************************************************************************/ | ||
| 1139 | static inline int chipcHw_isPllTestEnable(void) | ||
| 1140 | { | ||
| 1141 | return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; | ||
| 1142 | } | ||
| 1143 | |||
| 1144 | /****************************************************************************/ | ||
| 1145 | /** @brief Get PLL2 test status | ||
| 1146 | */ | ||
| 1147 | /****************************************************************************/ | ||
| 1148 | static inline int chipcHw_isPll2TestEnable(void) | ||
| 1149 | { | ||
| 1150 | return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE; | ||
| 1151 | } | ||
| 1152 | |||
| 1153 | /****************************************************************************/ | ||
| 1154 | /** @brief PLL test select | ||
| 1155 | */ | ||
| 1156 | /****************************************************************************/ | ||
| 1157 | static inline void chipcHw_pllTestSelect(uint32_t val) | ||
| 1158 | { | ||
| 1159 | REG_LOCAL_IRQ_SAVE; | ||
| 1160 | pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK; | ||
| 1161 | pChipcHw->PLLConfig |= | ||
| 1162 | (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT; | ||
| 1163 | REG_LOCAL_IRQ_RESTORE; | ||
| 1164 | } | ||
| 1165 | |||
| 1166 | /****************************************************************************/ | ||
| 1167 | /** @brief PLL2 test select | ||
| 1168 | */ | ||
| 1169 | /****************************************************************************/ | ||
| 1170 | static inline void chipcHw_pll2TestSelect(uint32_t val) | ||
| 1171 | { | ||
| 1172 | |||
| 1173 | REG_LOCAL_IRQ_SAVE; | ||
| 1174 | pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK; | ||
| 1175 | pChipcHw->PLLConfig2 |= | ||
| 1176 | (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT; | ||
| 1177 | REG_LOCAL_IRQ_RESTORE; | ||
| 1178 | } | ||
| 1179 | |||
| 1180 | /****************************************************************************/ | ||
| 1181 | /** @brief Get PLL test selected option | ||
| 1182 | */ | ||
| 1183 | /****************************************************************************/ | ||
| 1184 | static inline uint8_t chipcHw_getPllTestSelected(void) | ||
| 1185 | { | ||
| 1186 | return (uint8_t) ((pChipcHw-> | ||
| 1187 | PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) | ||
| 1188 | >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); | ||
| 1189 | } | ||
| 1190 | |||
| 1191 | /****************************************************************************/ | ||
| 1192 | /** @brief Get PLL2 test selected option | ||
| 1193 | */ | ||
| 1194 | /****************************************************************************/ | ||
| 1195 | static inline uint8_t chipcHw_getPll2TestSelected(void) | ||
| 1196 | { | ||
| 1197 | return (uint8_t) ((pChipcHw-> | ||
| 1198 | PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK) | ||
| 1199 | >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT); | ||
| 1200 | } | ||
| 1201 | |||
| 1202 | /****************************************************************************/ | ||
| 1203 | /** | ||
| 1204 | * @brief Disable the PLL1 | ||
| 1205 | * | ||
| 1206 | */ | ||
| 1207 | /****************************************************************************/ | ||
| 1208 | static inline void chipcHw_pll1Disable(void) | ||
| 1209 | { | ||
| 1210 | REG_LOCAL_IRQ_SAVE; | ||
| 1211 | pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 1212 | REG_LOCAL_IRQ_RESTORE; | ||
| 1213 | } | ||
| 1214 | |||
| 1215 | /****************************************************************************/ | ||
| 1216 | /** | ||
| 1217 | * @brief Disable the PLL2 | ||
| 1218 | * | ||
| 1219 | */ | ||
| 1220 | /****************************************************************************/ | ||
| 1221 | static inline void chipcHw_pll2Disable(void) | ||
| 1222 | { | ||
| 1223 | REG_LOCAL_IRQ_SAVE; | ||
| 1224 | pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN; | ||
| 1225 | REG_LOCAL_IRQ_RESTORE; | ||
| 1226 | } | ||
| 1227 | |||
| 1228 | /****************************************************************************/ | ||
| 1229 | /** | ||
| 1230 | * @brief Enables DDR SW phase alignment interrupt | ||
| 1231 | */ | ||
| 1232 | /****************************************************************************/ | ||
| 1233 | static inline void chipcHw_ddrPhaseAlignInterruptEnable(void) | ||
| 1234 | { | ||
| 1235 | REG_LOCAL_IRQ_SAVE; | ||
| 1236 | pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; | ||
| 1237 | REG_LOCAL_IRQ_RESTORE; | ||
| 1238 | } | ||
| 1239 | |||
| 1240 | /****************************************************************************/ | ||
| 1241 | /** | ||
| 1242 | * @brief Disables DDR SW phase alignment interrupt | ||
| 1243 | */ | ||
| 1244 | /****************************************************************************/ | ||
| 1245 | static inline void chipcHw_ddrPhaseAlignInterruptDisable(void) | ||
| 1246 | { | ||
| 1247 | REG_LOCAL_IRQ_SAVE; | ||
| 1248 | pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE; | ||
| 1249 | REG_LOCAL_IRQ_RESTORE; | ||
| 1250 | } | ||
| 1251 | |||
| 1252 | /****************************************************************************/ | ||
| 1253 | /** | ||
| 1254 | * @brief Set VPM SW phase alignment interrupt mode | ||
| 1255 | * | ||
| 1256 | * This function sets VPM phase alignment interrupt | ||
| 1257 | */ | ||
| 1258 | /****************************************************************************/ | ||
| 1259 | static inline void | ||
| 1260 | chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode) | ||
| 1261 | { | ||
| 1262 | REG_LOCAL_IRQ_SAVE; | ||
| 1263 | if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) { | ||
| 1264 | pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; | ||
| 1265 | } else { | ||
| 1266 | pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE; | ||
| 1267 | } | ||
| 1268 | pChipcHw->VPMPhaseCtrl2 = | ||
| 1269 | (pChipcHw-> | ||
| 1270 | VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK << | ||
| 1271 | chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode; | ||
| 1272 | REG_LOCAL_IRQ_RESTORE; | ||
| 1273 | } | ||
| 1274 | |||
| 1275 | /****************************************************************************/ | ||
| 1276 | /** | ||
| 1277 | * @brief Enable DDR phase alignment in software | ||
| 1278 | * | ||
| 1279 | */ | ||
| 1280 | /****************************************************************************/ | ||
| 1281 | static inline void chipcHw_ddrSwPhaseAlignEnable(void) | ||
| 1282 | { | ||
| 1283 | REG_LOCAL_IRQ_SAVE; | ||
| 1284 | pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; | ||
| 1285 | REG_LOCAL_IRQ_RESTORE; | ||
| 1286 | } | ||
| 1287 | |||
| 1288 | /****************************************************************************/ | ||
| 1289 | /** | ||
| 1290 | * @brief Disable DDR phase alignment in software | ||
| 1291 | * | ||
| 1292 | */ | ||
| 1293 | /****************************************************************************/ | ||
| 1294 | static inline void chipcHw_ddrSwPhaseAlignDisable(void) | ||
| 1295 | { | ||
| 1296 | REG_LOCAL_IRQ_SAVE; | ||
| 1297 | pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE; | ||
| 1298 | REG_LOCAL_IRQ_RESTORE; | ||
| 1299 | } | ||
| 1300 | |||
| 1301 | /****************************************************************************/ | ||
| 1302 | /** | ||
| 1303 | * @brief Enable DDR phase alignment in hardware | ||
| 1304 | * | ||
| 1305 | */ | ||
| 1306 | /****************************************************************************/ | ||
| 1307 | static inline void chipcHw_ddrHwPhaseAlignEnable(void) | ||
| 1308 | { | ||
| 1309 | REG_LOCAL_IRQ_SAVE; | ||
| 1310 | pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; | ||
| 1311 | REG_LOCAL_IRQ_RESTORE; | ||
| 1312 | } | ||
| 1313 | |||
| 1314 | /****************************************************************************/ | ||
| 1315 | /** | ||
| 1316 | * @brief Disable DDR phase alignment in hardware | ||
| 1317 | * | ||
| 1318 | */ | ||
| 1319 | /****************************************************************************/ | ||
| 1320 | static inline void chipcHw_ddrHwPhaseAlignDisable(void) | ||
| 1321 | { | ||
| 1322 | REG_LOCAL_IRQ_SAVE; | ||
| 1323 | pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE; | ||
| 1324 | REG_LOCAL_IRQ_RESTORE; | ||
| 1325 | } | ||
| 1326 | |||
| 1327 | /****************************************************************************/ | ||
| 1328 | /** | ||
| 1329 | * @brief Enable VPM phase alignment in software | ||
| 1330 | * | ||
| 1331 | */ | ||
| 1332 | /****************************************************************************/ | ||
| 1333 | static inline void chipcHw_vpmSwPhaseAlignEnable(void) | ||
| 1334 | { | ||
| 1335 | REG_LOCAL_IRQ_SAVE; | ||
| 1336 | pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; | ||
| 1337 | REG_LOCAL_IRQ_RESTORE; | ||
| 1338 | } | ||
| 1339 | |||
| 1340 | /****************************************************************************/ | ||
| 1341 | /** | ||
| 1342 | * @brief Disable VPM phase alignment in software | ||
| 1343 | * | ||
| 1344 | */ | ||
| 1345 | /****************************************************************************/ | ||
| 1346 | static inline void chipcHw_vpmSwPhaseAlignDisable(void) | ||
| 1347 | { | ||
| 1348 | REG_LOCAL_IRQ_SAVE; | ||
| 1349 | pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE; | ||
| 1350 | REG_LOCAL_IRQ_RESTORE; | ||
| 1351 | } | ||
| 1352 | |||
| 1353 | /****************************************************************************/ | ||
| 1354 | /** | ||
| 1355 | * @brief Enable VPM phase alignment in hardware | ||
| 1356 | * | ||
| 1357 | */ | ||
| 1358 | /****************************************************************************/ | ||
| 1359 | static inline void chipcHw_vpmHwPhaseAlignEnable(void) | ||
| 1360 | { | ||
| 1361 | REG_LOCAL_IRQ_SAVE; | ||
| 1362 | pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; | ||
| 1363 | REG_LOCAL_IRQ_RESTORE; | ||
| 1364 | } | ||
| 1365 | |||
| 1366 | /****************************************************************************/ | ||
| 1367 | /** | ||
| 1368 | * @brief Disable VPM phase alignment in hardware | ||
| 1369 | * | ||
| 1370 | */ | ||
| 1371 | /****************************************************************************/ | ||
| 1372 | static inline void chipcHw_vpmHwPhaseAlignDisable(void) | ||
| 1373 | { | ||
| 1374 | REG_LOCAL_IRQ_SAVE; | ||
| 1375 | pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE; | ||
| 1376 | REG_LOCAL_IRQ_RESTORE; | ||
| 1377 | } | ||
| 1378 | |||
| 1379 | /****************************************************************************/ | ||
| 1380 | /** | ||
| 1381 | * @brief Set DDR phase alignment margin in hardware | ||
| 1382 | * | ||
| 1383 | */ | ||
| 1384 | /****************************************************************************/ | ||
| 1385 | static inline void | ||
| 1386 | chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin) | ||
| 1387 | { | ||
| 1388 | uint32_t ge = 0; | ||
| 1389 | uint32_t le = 0; | ||
| 1390 | |||
| 1391 | switch (margin) { | ||
| 1392 | case chipcHw_DDR_HW_PHASE_MARGIN_STRICT: | ||
| 1393 | ge = 0x0F; | ||
| 1394 | le = 0x0F; | ||
| 1395 | break; | ||
| 1396 | case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM: | ||
| 1397 | ge = 0x03; | ||
| 1398 | le = 0x3F; | ||
| 1399 | break; | ||
| 1400 | case chipcHw_DDR_HW_PHASE_MARGIN_WIDE: | ||
| 1401 | ge = 0x01; | ||
| 1402 | le = 0x7F; | ||
| 1403 | break; | ||
| 1404 | } | ||
| 1405 | |||
| 1406 | { | ||
| 1407 | REG_LOCAL_IRQ_SAVE; | ||
| 1408 | |||
| 1409 | pChipcHw->DDRPhaseCtrl1 &= | ||
| 1410 | ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK << | ||
| 1411 | chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT) | ||
| 1412 | || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK << | ||
| 1413 | chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT)); | ||
| 1414 | |||
| 1415 | pChipcHw->DDRPhaseCtrl1 |= | ||
| 1416 | ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT) | ||
| 1417 | || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT)); | ||
| 1418 | |||
| 1419 | REG_LOCAL_IRQ_RESTORE; | ||
| 1420 | } | ||
| 1421 | } | ||
| 1422 | |||
| 1423 | /****************************************************************************/ | ||
| 1424 | /** | ||
| 1425 | * @brief Set VPM phase alignment margin in hardware | ||
| 1426 | * | ||
| 1427 | */ | ||
| 1428 | /****************************************************************************/ | ||
| 1429 | static inline void | ||
| 1430 | chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin) | ||
| 1431 | { | ||
| 1432 | uint32_t ge = 0; | ||
| 1433 | uint32_t le = 0; | ||
| 1434 | |||
| 1435 | switch (margin) { | ||
| 1436 | case chipcHw_VPM_HW_PHASE_MARGIN_STRICT: | ||
| 1437 | ge = 0x0F; | ||
| 1438 | le = 0x0F; | ||
| 1439 | break; | ||
| 1440 | case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM: | ||
| 1441 | ge = 0x03; | ||
| 1442 | le = 0x3F; | ||
| 1443 | break; | ||
| 1444 | case chipcHw_VPM_HW_PHASE_MARGIN_WIDE: | ||
| 1445 | ge = 0x01; | ||
| 1446 | le = 0x7F; | ||
| 1447 | break; | ||
| 1448 | } | ||
| 1449 | |||
| 1450 | { | ||
| 1451 | REG_LOCAL_IRQ_SAVE; | ||
| 1452 | |||
| 1453 | pChipcHw->VPMPhaseCtrl1 &= | ||
| 1454 | ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK << | ||
| 1455 | chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT) | ||
| 1456 | || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK << | ||
| 1457 | chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT)); | ||
| 1458 | |||
| 1459 | pChipcHw->VPMPhaseCtrl1 |= | ||
| 1460 | ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT) | ||
| 1461 | || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT)); | ||
| 1462 | |||
| 1463 | REG_LOCAL_IRQ_RESTORE; | ||
| 1464 | } | ||
| 1465 | } | ||
| 1466 | |||
| 1467 | /****************************************************************************/ | ||
| 1468 | /** | ||
| 1469 | * @brief Checks DDR phase aligned status done by HW | ||
| 1470 | * | ||
| 1471 | * @return 1: When aligned | ||
| 1472 | * 0: When not aligned | ||
| 1473 | */ | ||
| 1474 | /****************************************************************************/ | ||
| 1475 | static inline uint32_t chipcHw_isDdrHwPhaseAligned(void) | ||
| 1476 | { | ||
| 1477 | return (pChipcHw-> | ||
| 1478 | PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0; | ||
| 1479 | } | ||
| 1480 | |||
| 1481 | /****************************************************************************/ | ||
| 1482 | /** | ||
| 1483 | * @brief Checks VPM phase aligned status done by HW | ||
| 1484 | * | ||
| 1485 | * @return 1: When aligned | ||
| 1486 | * 0: When not aligned | ||
| 1487 | */ | ||
| 1488 | /****************************************************************************/ | ||
| 1489 | static inline uint32_t chipcHw_isVpmHwPhaseAligned(void) | ||
| 1490 | { | ||
| 1491 | return (pChipcHw-> | ||
| 1492 | PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0; | ||
| 1493 | } | ||
| 1494 | |||
| 1495 | /****************************************************************************/ | ||
| 1496 | /** | ||
| 1497 | * @brief Get DDR phase aligned status done by HW | ||
| 1498 | * | ||
| 1499 | */ | ||
| 1500 | /****************************************************************************/ | ||
| 1501 | static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void) | ||
| 1502 | { | ||
| 1503 | return (pChipcHw-> | ||
| 1504 | PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >> | ||
| 1505 | chipcHw_REG_DDR_PHASE_STATUS_SHIFT; | ||
| 1506 | } | ||
| 1507 | |||
| 1508 | /****************************************************************************/ | ||
| 1509 | /** | ||
| 1510 | * @brief Get VPM phase aligned status done by HW | ||
| 1511 | * | ||
| 1512 | */ | ||
| 1513 | /****************************************************************************/ | ||
| 1514 | static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void) | ||
| 1515 | { | ||
| 1516 | return (pChipcHw-> | ||
| 1517 | PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >> | ||
| 1518 | chipcHw_REG_VPM_PHASE_STATUS_SHIFT; | ||
| 1519 | } | ||
| 1520 | |||
| 1521 | /****************************************************************************/ | ||
| 1522 | /** | ||
| 1523 | * @brief Get DDR phase control value | ||
| 1524 | * | ||
| 1525 | */ | ||
| 1526 | /****************************************************************************/ | ||
| 1527 | static inline uint32_t chipcHw_getDdrPhaseControl(void) | ||
| 1528 | { | ||
| 1529 | return (pChipcHw-> | ||
| 1530 | PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >> | ||
| 1531 | chipcHw_REG_DDR_PHASE_CTRL_SHIFT; | ||
| 1532 | } | ||
| 1533 | |||
| 1534 | /****************************************************************************/ | ||
| 1535 | /** | ||
| 1536 | * @brief Get VPM phase control value | ||
| 1537 | * | ||
| 1538 | */ | ||
| 1539 | /****************************************************************************/ | ||
| 1540 | static inline uint32_t chipcHw_getVpmPhaseControl(void) | ||
| 1541 | { | ||
| 1542 | return (pChipcHw-> | ||
| 1543 | PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >> | ||
| 1544 | chipcHw_REG_VPM_PHASE_CTRL_SHIFT; | ||
| 1545 | } | ||
| 1546 | |||
| 1547 | /****************************************************************************/ | ||
| 1548 | /** | ||
| 1549 | * @brief DDR phase alignment timeout count | ||
| 1550 | * | ||
| 1551 | * @note If HW fails to perform the phase alignment, it will trigger | ||
| 1552 | * a DDR phase alignment timeout interrupt. | ||
| 1553 | */ | ||
| 1554 | /****************************************************************************/ | ||
| 1555 | static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle) | ||
| 1556 | { | ||
| 1557 | REG_LOCAL_IRQ_SAVE; | ||
| 1558 | pChipcHw->DDRPhaseCtrl2 &= | ||
| 1559 | ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK << | ||
| 1560 | chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT); | ||
| 1561 | pChipcHw->DDRPhaseCtrl2 |= | ||
| 1562 | (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) << | ||
| 1563 | chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT; | ||
| 1564 | REG_LOCAL_IRQ_RESTORE; | ||
| 1565 | } | ||
| 1566 | |||
| 1567 | /****************************************************************************/ | ||
| 1568 | /** | ||
| 1569 | * @brief VPM phase alignment timeout count | ||
| 1570 | * | ||
| 1571 | * @note If HW fails to perform the phase alignment, it will trigger | ||
| 1572 | * a VPM phase alignment timeout interrupt. | ||
| 1573 | */ | ||
| 1574 | /****************************************************************************/ | ||
| 1575 | static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle) | ||
| 1576 | { | ||
| 1577 | REG_LOCAL_IRQ_SAVE; | ||
| 1578 | pChipcHw->VPMPhaseCtrl2 &= | ||
| 1579 | ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK << | ||
| 1580 | chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT); | ||
| 1581 | pChipcHw->VPMPhaseCtrl2 |= | ||
| 1582 | (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) << | ||
| 1583 | chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT; | ||
| 1584 | REG_LOCAL_IRQ_RESTORE; | ||
| 1585 | } | ||
| 1586 | |||
| 1587 | /****************************************************************************/ | ||
| 1588 | /** | ||
| 1589 | * @brief Clear DDR phase alignment timeout interrupt | ||
| 1590 | * | ||
| 1591 | */ | ||
| 1592 | /****************************************************************************/ | ||
| 1593 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void) | ||
| 1594 | { | ||
| 1595 | REG_LOCAL_IRQ_SAVE; | ||
| 1596 | /* Clear timeout interrupt service bit */ | ||
| 1597 | pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED; | ||
| 1598 | pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED; | ||
| 1599 | REG_LOCAL_IRQ_RESTORE; | ||
| 1600 | } | ||
| 1601 | |||
| 1602 | /****************************************************************************/ | ||
| 1603 | /** | ||
| 1604 | * @brief Clear VPM phase alignment timeout interrupt | ||
| 1605 | * | ||
| 1606 | */ | ||
| 1607 | /****************************************************************************/ | ||
| 1608 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void) | ||
| 1609 | { | ||
| 1610 | REG_LOCAL_IRQ_SAVE; | ||
| 1611 | /* Clear timeout interrupt service bit */ | ||
| 1612 | pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED; | ||
| 1613 | pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED; | ||
| 1614 | REG_LOCAL_IRQ_RESTORE; | ||
| 1615 | } | ||
| 1616 | |||
| 1617 | /****************************************************************************/ | ||
| 1618 | /** | ||
| 1619 | * @brief DDR phase alignment timeout interrupt enable | ||
| 1620 | * | ||
| 1621 | */ | ||
| 1622 | /****************************************************************************/ | ||
| 1623 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void) | ||
| 1624 | { | ||
| 1625 | REG_LOCAL_IRQ_SAVE; | ||
| 1626 | chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */ | ||
| 1627 | /* Enable timeout interrupt */ | ||
| 1628 | pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; | ||
| 1629 | REG_LOCAL_IRQ_RESTORE; | ||
| 1630 | } | ||
| 1631 | |||
| 1632 | /****************************************************************************/ | ||
| 1633 | /** | ||
| 1634 | * @brief VPM phase alignment timeout interrupt enable | ||
| 1635 | * | ||
| 1636 | */ | ||
| 1637 | /****************************************************************************/ | ||
| 1638 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void) | ||
| 1639 | { | ||
| 1640 | REG_LOCAL_IRQ_SAVE; | ||
| 1641 | chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */ | ||
| 1642 | /* Enable timeout interrupt */ | ||
| 1643 | pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE; | ||
| 1644 | REG_LOCAL_IRQ_RESTORE; | ||
| 1645 | } | ||
| 1646 | |||
| 1647 | /****************************************************************************/ | ||
| 1648 | /** | ||
| 1649 | * @brief DDR phase alignment timeout interrupt disable | ||
| 1650 | * | ||
| 1651 | */ | ||
| 1652 | /****************************************************************************/ | ||
| 1653 | static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void) | ||
| 1654 | { | ||
| 1655 | REG_LOCAL_IRQ_SAVE; | ||
| 1656 | pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE; | ||
| 1657 | REG_LOCAL_IRQ_RESTORE; | ||
| 1658 | } | ||
| 1659 | |||
| 1660 | /****************************************************************************/ | ||
| 1661 | /** | ||
| 1662 | * @brief VPM phase alignment timeout interrupt disable | ||
| 1663 | * | ||
| 1664 | */ | ||
| 1665 | /****************************************************************************/ | ||
| 1666 | static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void) | ||
| 1667 | { | ||
| 1668 | REG_LOCAL_IRQ_SAVE; | ||
| 1669 | pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE; | ||
| 1670 | REG_LOCAL_IRQ_RESTORE; | ||
| 1671 | } | ||
| 1672 | |||
| 1673 | #endif /* CHIPC_INLINE_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h new file mode 100644 index 000000000000..b162448f613c --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h | |||
| @@ -0,0 +1,530 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file chipcHw_reg.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for low level chip control registers | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | #ifndef CHIPCHW_REG_H | ||
| 24 | #define CHIPCHW_REG_H | ||
| 25 | |||
| 26 | #include <mach/csp/mm_io.h> | ||
| 27 | #include <csp/reg.h> | ||
| 28 | #include <mach/csp/ddrcReg.h> | ||
| 29 | |||
| 30 | #define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC | ||
| 31 | |||
| 32 | typedef struct { | ||
| 33 | uint32_t ChipId; /* Chip ID */ | ||
| 34 | uint32_t DDRClock; /* PLL1 Channel 1 for DDR clock */ | ||
| 35 | uint32_t ARMClock; /* PLL1 Channel 2 for ARM clock */ | ||
| 36 | uint32_t ESWClock; /* PLL1 Channel 3 for ESW system clock */ | ||
| 37 | uint32_t VPMClock; /* PLL1 Channel 4 for VPM clock */ | ||
| 38 | uint32_t ESW125Clock; /* PLL1 Channel 5 for ESW 125MHz clock */ | ||
| 39 | uint32_t UARTClock; /* PLL1 Channel 6 for UART clock */ | ||
| 40 | uint32_t SDIO0Clock; /* PLL1 Channel 7 for SDIO 0 clock */ | ||
| 41 | uint32_t SDIO1Clock; /* PLL1 Channel 8 for SDIO 1 clock */ | ||
| 42 | uint32_t SPIClock; /* PLL1 Channel 9 for SPI master Clock */ | ||
| 43 | uint32_t ETMClock; /* PLL1 Channel 10 for ARM ETM Clock */ | ||
| 44 | |||
| 45 | uint32_t ACLKClock; /* ACLK Clock (Divider) */ | ||
| 46 | uint32_t OTPClock; /* OTP Clock (Divider) */ | ||
| 47 | uint32_t I2CClock; /* I2C Clock (CK_13m) (Divider) */ | ||
| 48 | uint32_t I2S0Clock; /* I2S0 Clock (Divider) */ | ||
| 49 | uint32_t RTBUSClock; /* RTBUS (DDR PHY Config.) Clock (Divider) */ | ||
| 50 | uint32_t pad1; | ||
| 51 | uint32_t APM100Clock; /* APM 100MHz CLK Clock (Divider) */ | ||
| 52 | uint32_t TSCClock; /* TSC Clock (Divider) */ | ||
| 53 | uint32_t LEDClock; /* LED Clock (Divider) */ | ||
| 54 | |||
| 55 | uint32_t USBClock; /* PLL2 Channel 1 for USB clock */ | ||
| 56 | uint32_t LCDClock; /* PLL2 Channel 2 for LCD clock */ | ||
| 57 | uint32_t APMClock; /* PLL2 Channel 3 for APM 200 MHz clock */ | ||
| 58 | |||
| 59 | uint32_t BusIntfClock; /* Bus interface clock */ | ||
| 60 | |||
| 61 | uint32_t PLLStatus; /* PLL status register (PLL1) */ | ||
| 62 | uint32_t PLLConfig; /* PLL configuration register (PLL1) */ | ||
| 63 | uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */ | ||
| 64 | uint32_t PLLDivider; /* PLL divider control register (PLL1) */ | ||
| 65 | uint32_t PLLControl1; /* PLL analog control register #1 (PLL1) */ | ||
| 66 | uint32_t PLLControl2; /* PLL analog control register #2 (PLL1) */ | ||
| 67 | |||
| 68 | uint32_t I2S1Clock; /* I2S1 Clock */ | ||
| 69 | uint32_t AudioEnable; /* Enable/ disable audio channel */ | ||
| 70 | uint32_t SoftReset1; /* Reset blocks */ | ||
| 71 | uint32_t SoftReset2; /* Reset blocks */ | ||
| 72 | uint32_t Spare1; /* Phase align interrupts */ | ||
| 73 | uint32_t Sticky; /* Sticky bits */ | ||
| 74 | uint32_t MiscCtrl; /* Misc. control */ | ||
| 75 | uint32_t pad3[3]; | ||
| 76 | |||
| 77 | uint32_t PLLStatus2; /* PLL status register (PLL2) */ | ||
| 78 | uint32_t PLLConfig2; /* PLL configuration register (PLL2) */ | ||
| 79 | uint32_t PLLPreDivider2; /* PLL pre-divider control register (PLL2) */ | ||
| 80 | uint32_t PLLDivider2; /* PLL divider control register (PLL2) */ | ||
| 81 | uint32_t PLLControl12; /* PLL analog control register #1 (PLL2) */ | ||
| 82 | uint32_t PLLControl22; /* PLL analog control register #2 (PLL2) */ | ||
| 83 | |||
| 84 | uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */ | ||
| 85 | uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */ | ||
| 86 | uint32_t PhaseAlignStatus; /* DDR/VPM Clock Phase Alignment Status */ | ||
| 87 | uint32_t PhaseCtrlStatus; /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */ | ||
| 88 | uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */ | ||
| 89 | uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */ | ||
| 90 | uint32_t pad4[9]; | ||
| 91 | |||
| 92 | uint32_t SoftOTP1; /* Software OTP control */ | ||
| 93 | uint32_t SoftOTP2; /* Software OTP control */ | ||
| 94 | uint32_t SoftStraps; /* Software strap */ | ||
| 95 | uint32_t PinStraps; /* Pin Straps */ | ||
| 96 | uint32_t DiffOscCtrl; /* Diff oscillator control */ | ||
| 97 | uint32_t DiagsCtrl; /* Diagnostic control */ | ||
| 98 | uint32_t DiagsOutputCtrl; /* Diagnostic output enable */ | ||
| 99 | uint32_t DiagsReadBackCtrl; /* Diagnostic read back control */ | ||
| 100 | |||
| 101 | uint32_t LcdPifMode; /* LCD/PIF Pin Sharing MUX Mode */ | ||
| 102 | |||
| 103 | uint32_t GpioMux_0_7; /* Pin Sharing MUX0 Control */ | ||
| 104 | uint32_t GpioMux_8_15; /* Pin Sharing MUX1 Control */ | ||
| 105 | uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */ | ||
| 106 | uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */ | ||
| 107 | uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */ | ||
| 108 | uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */ | ||
| 109 | uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */ | ||
| 110 | uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */ | ||
| 111 | |||
| 112 | uint32_t GpioSR_0_7; /* Slew rate for GPIO 0 - 7 */ | ||
| 113 | uint32_t GpioSR_8_15; /* Slew rate for GPIO 8 - 15 */ | ||
| 114 | uint32_t GpioSR_16_23; /* Slew rate for GPIO 16 - 23 */ | ||
| 115 | uint32_t GpioSR_24_31; /* Slew rate for GPIO 24 - 31 */ | ||
| 116 | uint32_t GpioSR_32_39; /* Slew rate for GPIO 32 - 39 */ | ||
| 117 | uint32_t GpioSR_40_47; /* Slew rate for GPIO 40 - 47 */ | ||
| 118 | uint32_t GpioSR_48_55; /* Slew rate for GPIO 48 - 55 */ | ||
| 119 | uint32_t GpioSR_56_63; /* Slew rate for GPIO 56 - 63 */ | ||
| 120 | uint32_t MiscSR_0_7; /* Slew rate for MISC 0 - 7 */ | ||
| 121 | uint32_t MiscSR_8_15; /* Slew rate for MISC 8 - 15 */ | ||
| 122 | |||
| 123 | uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */ | ||
| 124 | uint32_t GpioPull_16_31; /* Pull up registers for GPIO 16 - 31 */ | ||
| 125 | uint32_t GpioPull_32_47; /* Pull up registers for GPIO 32 - 47 */ | ||
| 126 | uint32_t GpioPull_48_63; /* Pull up registers for GPIO 48 - 63 */ | ||
| 127 | uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */ | ||
| 128 | |||
| 129 | uint32_t GpioInput_0_31; /* Input type for GPIO 0 - 31 */ | ||
| 130 | uint32_t GpioInput_32_63; /* Input type for GPIO 32 - 63 */ | ||
| 131 | uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */ | ||
| 132 | } chipcHw_REG_t; | ||
| 133 | |||
| 134 | #define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS) | ||
| 135 | #define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC) | ||
| 136 | |||
| 137 | #define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000 | ||
| 138 | #define chipcHw_REG_CHIPID_BASE_SHIFT 12 | ||
| 139 | #define chipcHw_REG_CHIPID_REV_MASK 0x00000FFF | ||
| 140 | #define chipcHw_REG_REV_A0 0xA00 | ||
| 141 | #define chipcHw_REG_REV_B0 0x0B0 | ||
| 142 | |||
| 143 | #define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE 0x80000000 /* Allow controlling PLL registers */ | ||
| 144 | #define chipcHw_REG_PLL_STATUS_LOCKED 0x00000001 /* PLL is settled */ | ||
| 145 | #define chipcHw_REG_PLL_CONFIG_D_RESET 0x00000008 /* Digital reset */ | ||
| 146 | #define chipcHw_REG_PLL_CONFIG_A_RESET 0x00000004 /* Analog reset */ | ||
| 147 | #define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE 0x00000020 /* Bypass enable */ | ||
| 148 | #define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE 0x00000010 /* Output enable */ | ||
| 149 | #define chipcHw_REG_PLL_CONFIG_POWER_DOWN 0x00000001 /* Power down */ | ||
| 150 | #define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ 1600000000 /* 1.6GHz VCO split frequency */ | ||
| 151 | #define chipcHw_REG_PLL_CONFIG_VCO_800_1600 0x00000000 /* VCO range 800-1600 MHz */ | ||
| 152 | #define chipcHw_REG_PLL_CONFIG_VCO_1601_3200 0x00000080 /* VCO range 1601-3200 MHz */ | ||
| 153 | #define chipcHw_REG_PLL_CONFIG_TEST_ENABLE 0x00010000 /* PLL test output enable */ | ||
| 154 | #define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK 0x003E0000 /* Mask to set test values */ | ||
| 155 | #define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT 17 | ||
| 156 | |||
| 157 | #define chipcHw_REG_PLL_CLOCK_PHASE_COMP 0x00800000 /* Phase comparator output */ | ||
| 158 | #define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK 0x00300000 /* Clock to bus ratio mask */ | ||
| 159 | #define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT 20 /* Number of bits to be shifted */ | ||
| 160 | #define chipcHw_REG_PLL_CLOCK_POWER_DOWN 0x00080000 /* PLL channel power down */ | ||
| 161 | #define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO 0x00040000 /* Use GPIO as source */ | ||
| 162 | #define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT 0x00020000 /* Select bypass clock */ | ||
| 163 | #define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE 0x00010000 /* Clock gated ON */ | ||
| 164 | #define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE 0x00008000 /* Clock phase update enable */ | ||
| 165 | #define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT 8 /* Number of bits to be shifted */ | ||
| 166 | #define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK 0x00003F00 /* Phase control mask */ | ||
| 167 | #define chipcHw_REG_PLL_CLOCK_MDIV_MASK 0x000000FF /* Clock post divider mask | ||
| 168 | |||
| 169 | 00000000 = divide-by-256 | ||
| 170 | 00000001 = divide-by-1 | ||
| 171 | 00000010 = divide-by-2 | ||
| 172 | 00000011 = divide-by-3 | ||
| 173 | 00000100 = divide-by-4 | ||
| 174 | 00000101 = divide-by-5 | ||
| 175 | 00000110 = divide-by-6 | ||
| 176 | . | ||
| 177 | . | ||
| 178 | 11111011 = divide-by-251 | ||
| 179 | 11111100 = divide-by-252 | ||
| 180 | 11111101 = divide-by-253 | ||
| 181 | 11111110 = divide-by-254 | ||
| 182 | */ | ||
| 183 | |||
| 184 | #define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER 0x00040000 /* NON-PLL clock source select */ | ||
| 185 | #define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT 0x00020000 /* NON-PLL clock bypass enable */ | ||
| 186 | #define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE 0x00010000 /* NON-PLL clock output enable */ | ||
| 187 | #define chipcHw_REG_DIV_CLOCK_DIV_MASK 0x000000FF /* NON-PLL clock post-divide mask */ | ||
| 188 | #define chipcHw_REG_DIV_CLOCK_DIV_256 0x00000000 /* NON-PLL clock post-divide by 256 */ | ||
| 189 | |||
| 190 | #define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT 0 | ||
| 191 | #define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT 4 | ||
| 192 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT 8 | ||
| 193 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK 0x0001FF00 | ||
| 194 | #define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN 0x02000000 | ||
| 195 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK 0x00700000 /* Divider mask */ | ||
| 196 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER 0x00000000 /* Integer-N Mode */ | ||
| 197 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT 0x00100000 /* MASH Sigma-Delta Modulator Unit Mode */ | ||
| 198 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT 0x00200000 /* MFB Sigma-Delta Modulator Unit Mode */ | ||
| 199 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 0x00300000 /* MASH Sigma-Delta Modulator 1/8 Mode */ | ||
| 200 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8 0x00400000 /* MFB Sigma-Delta Modulator 1/8 Mode */ | ||
| 201 | |||
| 202 | #define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco) ((vco) / chipcHw_XTAL_FREQ_Hz) | ||
| 203 | #define chipcHw_REG_PLL_PREDIVIDER_P1 1 | ||
| 204 | #define chipcHw_REG_PLL_PREDIVIDER_P2 1 | ||
| 205 | |||
| 206 | #define chipcHw_REG_PLL_DIVIDER_M1DIV 0x03000000 | ||
| 207 | #define chipcHw_REG_PLL_DIVIDER_FRAC 0x00FFFFFF /* Fractional divider */ | ||
| 208 | |||
| 209 | #define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS (0x00FFFFFF) /* To attain spread with max frequency */ | ||
| 210 | |||
| 211 | #define chipcHw_REG_PLL_DIVIDER_NDIV_f 0 /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f / | ||
| 212 | chipcHw_REG_PLL_DIVIDER_FRAC | ||
| 213 | = 0, when SS is disable | ||
| 214 | */ | ||
| 215 | |||
| 216 | #define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz) ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz))) | ||
| 217 | |||
| 218 | #define chipcHw_REG_ACLKClock_CLK_DIV_MASK 0x3 | ||
| 219 | |||
| 220 | /* System booting strap options */ | ||
| 221 | #define chipcHw_STRAPS_SOFT_OVERRIDE 0x00000001 /* Software Strap Override */ | ||
| 222 | |||
| 223 | #define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8 0x00000000 /* 8 bit NAND FLASH Boot */ | ||
| 224 | #define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16 0x00000002 /* 16 bit NOR FLASH Boot */ | ||
| 225 | #define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH 0x00000004 /* Serial FLASH Boot */ | ||
| 226 | #define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16 0x00000006 /* 16 bit NAND FLASH Boot */ | ||
| 227 | #define chipcHw_STRAPS_BOOT_DEVICE_UART 0x00000008 /* UART Boot */ | ||
| 228 | #define chipcHw_STRAPS_BOOT_DEVICE_MASK 0x0000000E /* Mask */ | ||
| 229 | |||
| 230 | /* System boot option */ | ||
| 231 | #define chipcHw_STRAPS_BOOT_OPTION_BROM 0x00000000 /* Boot from Boot ROM */ | ||
| 232 | #define chipcHw_STRAPS_BOOT_OPTION_ARAM 0x00000020 /* Boot from ARAM */ | ||
| 233 | #define chipcHw_STRAPS_BOOT_OPTION_NOR 0x00000030 /* Boot from NOR flash */ | ||
| 234 | |||
| 235 | /* NAND Flash page size strap options */ | ||
| 236 | #define chipcHw_STRAPS_NAND_PAGESIZE_512 0x00000000 /* NAND FLASH page size of 512 bytes */ | ||
| 237 | #define chipcHw_STRAPS_NAND_PAGESIZE_2048 0x00000040 /* NAND FLASH page size of 2048 bytes */ | ||
| 238 | #define chipcHw_STRAPS_NAND_PAGESIZE_4096 0x00000080 /* NAND FLASH page size of 4096 bytes */ | ||
| 239 | #define chipcHw_STRAPS_NAND_PAGESIZE_EXT 0x000000C0 /* NAND FLASH page of extened size */ | ||
| 240 | #define chipcHw_STRAPS_NAND_PAGESIZE_MASK 0x000000C0 /* Mask */ | ||
| 241 | |||
| 242 | #define chipcHw_STRAPS_NAND_EXTRA_CYCLE 0x00000400 /* NAND FLASH address cycle configuration */ | ||
| 243 | #define chipcHw_STRAPS_REBOOT_TO_UART 0x00000800 /* Reboot to UART on error */ | ||
| 244 | |||
| 245 | /* Secure boot mode strap options */ | ||
| 246 | #define chipcHw_STRAPS_BOOT_MODE_NORMAL 0x00000000 /* Normal Boot */ | ||
| 247 | #define chipcHw_STRAPS_BOOT_MODE_DBG_SW 0x00000100 /* Software debugging Boot */ | ||
| 248 | #define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT 0x00000200 /* Boot rom debugging Boot */ | ||
| 249 | #define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET 0x00000300 /* Normal Boot (Quiet BootRom) */ | ||
| 250 | #define chipcHw_STRAPS_BOOT_MODE_MASK 0x00000300 /* Mask */ | ||
| 251 | |||
| 252 | /* Slave Mode straps */ | ||
| 253 | #define chipcHw_STRAPS_I2CS 0x02000000 /* I2C Slave */ | ||
| 254 | #define chipcHw_STRAPS_SPIS 0x01000000 /* SPI Slave */ | ||
| 255 | |||
| 256 | /* Strap pin options */ | ||
| 257 | #define chipcHw_REG_SW_STRAPS ((pChipcHw->PinStraps & 0x0000FC00) >> 10) | ||
| 258 | |||
| 259 | /* PIF/LCD pin sharing defines */ | ||
| 260 | #define chipcHw_REG_LCD_PIN_ENABLE 0x00000001 /* LCD Controller is used and the pins have LCD functions */ | ||
| 261 | #define chipcHw_REG_PIF_PIN_ENABLE 0x00000002 /* LCD pins are used to perform PIF functions */ | ||
| 262 | |||
| 263 | #define chipcHw_GPIO_COUNT 61 /* Number of GPIO pin accessible thorugh CHIPC */ | ||
| 264 | |||
| 265 | /* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */ | ||
| 266 | #define chipcHw_REG_GPIO_MUX_KEYPAD 0x00000001 /* GPIO mux for Keypad */ | ||
| 267 | #define chipcHw_REG_GPIO_MUX_I2CH 0x00000002 /* GPIO mux for I2CH */ | ||
| 268 | #define chipcHw_REG_GPIO_MUX_SPI 0x00000003 /* GPIO mux for SPI */ | ||
| 269 | #define chipcHw_REG_GPIO_MUX_UART 0x00000004 /* GPIO mux for UART */ | ||
| 270 | #define chipcHw_REG_GPIO_MUX_LEDMTXP 0x00000005 /* GPIO mux for LEDMTXP */ | ||
| 271 | #define chipcHw_REG_GPIO_MUX_LEDMTXS 0x00000006 /* GPIO mux for LEDMTXS */ | ||
| 272 | #define chipcHw_REG_GPIO_MUX_SDIO0 0x00000007 /* GPIO mux for SDIO0 */ | ||
| 273 | #define chipcHw_REG_GPIO_MUX_SDIO1 0x00000008 /* GPIO mux for SDIO1 */ | ||
| 274 | #define chipcHw_REG_GPIO_MUX_PCM 0x00000009 /* GPIO mux for PCM */ | ||
| 275 | #define chipcHw_REG_GPIO_MUX_I2S 0x0000000A /* GPIO mux for I2S */ | ||
| 276 | #define chipcHw_REG_GPIO_MUX_ETM 0x0000000B /* GPIO mux for ETM */ | ||
| 277 | #define chipcHw_REG_GPIO_MUX_DEBUG 0x0000000C /* GPIO mux for DEBUG */ | ||
| 278 | #define chipcHw_REG_GPIO_MUX_MISC 0x0000000D /* GPIO mux for MISC */ | ||
| 279 | #define chipcHw_REG_GPIO_MUX_GPIO 0x00000000 /* GPIO mux for GPIO */ | ||
| 280 | #define chipcHw_REG_GPIO_MUX(pin) (&pChipcHw->GpioMux_0_7 + ((pin) >> 3)) | ||
| 281 | #define chipcHw_REG_GPIO_MUX_POSITION(pin) (((pin) & 0x00000007) << 2) | ||
| 282 | #define chipcHw_REG_GPIO_MUX_MASK 0x0000000F /* Mask */ | ||
| 283 | |||
| 284 | #define chipcHw_REG_SLEW_RATE_HIGH 0x00000000 /* High speed slew rate */ | ||
| 285 | #define chipcHw_REG_SLEW_RATE_NORMAL 0x00000008 /* Normal slew rate */ | ||
| 286 | /* Pins beyond 42 are defined by skipping 8 bits within the register */ | ||
| 287 | #define chipcHw_REG_SLEW_RATE(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) | ||
| 288 | #define chipcHw_REG_SLEW_RATE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) | ||
| 289 | #define chipcHw_REG_SLEW_RATE_MASK 0x00000008 /* Mask */ | ||
| 290 | |||
| 291 | #define chipcHw_REG_CURRENT_STRENGTH_2mA 0x00000001 /* Current driving strength 2 milli ampere */ | ||
| 292 | #define chipcHw_REG_CURRENT_STRENGTH_4mA 0x00000002 /* Current driving strength 4 milli ampere */ | ||
| 293 | #define chipcHw_REG_CURRENT_STRENGTH_6mA 0x00000004 /* Current driving strength 6 milli ampere */ | ||
| 294 | #define chipcHw_REG_CURRENT_STRENGTH_8mA 0x00000005 /* Current driving strength 8 milli ampere */ | ||
| 295 | #define chipcHw_REG_CURRENT_STRENGTH_10mA 0x00000006 /* Current driving strength 10 milli ampere */ | ||
| 296 | #define chipcHw_REG_CURRENT_STRENGTH_12mA 0x00000007 /* Current driving strength 12 milli ampere */ | ||
| 297 | #define chipcHw_REG_CURRENT_MASK 0x00000007 /* Mask */ | ||
| 298 | /* Pins beyond 42 are defined by skipping 8 bits */ | ||
| 299 | #define chipcHw_REG_CURRENT(pin) (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3))) | ||
| 300 | #define chipcHw_REG_CURRENT_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2)) | ||
| 301 | |||
| 302 | #define chipcHw_REG_PULL_NONE 0x00000000 /* No pull up register */ | ||
| 303 | #define chipcHw_REG_PULL_UP 0x00000001 /* Pull up register enable */ | ||
| 304 | #define chipcHw_REG_PULL_DOWN 0x00000002 /* Pull down register enable */ | ||
| 305 | #define chipcHw_REG_PULLUP_MASK 0x00000003 /* Mask */ | ||
| 306 | /* Pins beyond 42 are defined by skipping 4 bits */ | ||
| 307 | #define chipcHw_REG_PULLUP(pin) (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4))) | ||
| 308 | #define chipcHw_REG_PULLUP_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1)) | ||
| 309 | |||
| 310 | #define chipcHw_REG_INPUTTYPE_CMOS 0x00000000 /* Normal CMOS logic */ | ||
| 311 | #define chipcHw_REG_INPUTTYPE_ST 0x00000001 /* High speed Schmitt Trigger */ | ||
| 312 | #define chipcHw_REG_INPUTTYPE_MASK 0x00000001 /* Mask */ | ||
| 313 | /* Pins beyond 42 are defined by skipping 2 bits */ | ||
| 314 | #define chipcHw_REG_INPUTTYPE(pin) (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5))) | ||
| 315 | #define chipcHw_REG_INPUTTYPE_POSITION(pin) (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F))) | ||
| 316 | |||
| 317 | /* Device connected to the bus clock */ | ||
| 318 | #define chipcHw_REG_BUS_CLOCK_ARM 0x00000001 /* Bus interface clock for ARM */ | ||
| 319 | #define chipcHw_REG_BUS_CLOCK_VDEC 0x00000002 /* Bus interface clock for VDEC */ | ||
| 320 | #define chipcHw_REG_BUS_CLOCK_ARAM 0x00000004 /* Bus interface clock for ARAM */ | ||
| 321 | #define chipcHw_REG_BUS_CLOCK_HPM 0x00000008 /* Bus interface clock for HPM */ | ||
| 322 | #define chipcHw_REG_BUS_CLOCK_DDRC 0x00000010 /* Bus interface clock for DDRC */ | ||
| 323 | #define chipcHw_REG_BUS_CLOCK_DMAC0 0x00000020 /* Bus interface clock for DMAC0 */ | ||
| 324 | #define chipcHw_REG_BUS_CLOCK_DMAC1 0x00000040 /* Bus interface clock for DMAC1 */ | ||
| 325 | #define chipcHw_REG_BUS_CLOCK_NVI 0x00000080 /* Bus interface clock for NVI */ | ||
| 326 | #define chipcHw_REG_BUS_CLOCK_ESW 0x00000100 /* Bus interface clock for ESW */ | ||
| 327 | #define chipcHw_REG_BUS_CLOCK_GE 0x00000200 /* Bus interface clock for GE */ | ||
| 328 | #define chipcHw_REG_BUS_CLOCK_I2CH 0x00000400 /* Bus interface clock for I2CH */ | ||
| 329 | #define chipcHw_REG_BUS_CLOCK_I2S0 0x00000800 /* Bus interface clock for I2S0 */ | ||
| 330 | #define chipcHw_REG_BUS_CLOCK_I2S1 0x00001000 /* Bus interface clock for I2S1 */ | ||
| 331 | #define chipcHw_REG_BUS_CLOCK_VRAM 0x00002000 /* Bus interface clock for VRAM */ | ||
| 332 | #define chipcHw_REG_BUS_CLOCK_CLCD 0x00004000 /* Bus interface clock for CLCD */ | ||
| 333 | #define chipcHw_REG_BUS_CLOCK_LDK 0x00008000 /* Bus interface clock for LDK */ | ||
| 334 | #define chipcHw_REG_BUS_CLOCK_LED 0x00010000 /* Bus interface clock for LED */ | ||
| 335 | #define chipcHw_REG_BUS_CLOCK_OTP 0x00020000 /* Bus interface clock for OTP */ | ||
| 336 | #define chipcHw_REG_BUS_CLOCK_PIF 0x00040000 /* Bus interface clock for PIF */ | ||
| 337 | #define chipcHw_REG_BUS_CLOCK_SPU 0x00080000 /* Bus interface clock for SPU */ | ||
| 338 | #define chipcHw_REG_BUS_CLOCK_SDIO0 0x00100000 /* Bus interface clock for SDIO0 */ | ||
| 339 | #define chipcHw_REG_BUS_CLOCK_SDIO1 0x00200000 /* Bus interface clock for SDIO1 */ | ||
| 340 | #define chipcHw_REG_BUS_CLOCK_SPIH 0x00400000 /* Bus interface clock for SPIH */ | ||
| 341 | #define chipcHw_REG_BUS_CLOCK_SPIS 0x00800000 /* Bus interface clock for SPIS */ | ||
| 342 | #define chipcHw_REG_BUS_CLOCK_UART0 0x01000000 /* Bus interface clock for UART0 */ | ||
| 343 | #define chipcHw_REG_BUS_CLOCK_UART1 0x02000000 /* Bus interface clock for UART1 */ | ||
| 344 | #define chipcHw_REG_BUS_CLOCK_BBL 0x04000000 /* Bus interface clock for BBL */ | ||
| 345 | #define chipcHw_REG_BUS_CLOCK_I2CS 0x08000000 /* Bus interface clock for I2CS */ | ||
| 346 | #define chipcHw_REG_BUS_CLOCK_USBH 0x10000000 /* Bus interface clock for USB Host */ | ||
| 347 | #define chipcHw_REG_BUS_CLOCK_USBD 0x20000000 /* Bus interface clock for USB Device */ | ||
| 348 | #define chipcHw_REG_BUS_CLOCK_BROM 0x40000000 /* Bus interface clock for Boot ROM */ | ||
| 349 | #define chipcHw_REG_BUS_CLOCK_TSC 0x80000000 /* Bus interface clock for Touch screen */ | ||
| 350 | |||
| 351 | /* Software resets defines */ | ||
| 352 | #define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD 0x0000000080000000ULL /* Reset Global VPM and hold */ | ||
| 353 | #define chipcHw_REG_SOFT_RESET_VPM_HOLD 0x0000000040000000ULL /* Reset VPM and hold */ | ||
| 354 | #define chipcHw_REG_SOFT_RESET_VPM_GLOBAL 0x0000000020000000ULL /* Reset Global VPM */ | ||
| 355 | #define chipcHw_REG_SOFT_RESET_VPM 0x0000000010000000ULL /* Reset VPM */ | ||
| 356 | #define chipcHw_REG_SOFT_RESET_KEYPAD 0x0000000008000000ULL /* Reset Key pad */ | ||
| 357 | #define chipcHw_REG_SOFT_RESET_LED 0x0000000004000000ULL /* Reset LED */ | ||
| 358 | #define chipcHw_REG_SOFT_RESET_SPU 0x0000000002000000ULL /* Reset SPU */ | ||
| 359 | #define chipcHw_REG_SOFT_RESET_RNG 0x0000000001000000ULL /* Reset RNG */ | ||
| 360 | #define chipcHw_REG_SOFT_RESET_PKA 0x0000000000800000ULL /* Reset PKA */ | ||
| 361 | #define chipcHw_REG_SOFT_RESET_LCD 0x0000000000400000ULL /* Reset LCD */ | ||
| 362 | #define chipcHw_REG_SOFT_RESET_PIF 0x0000000000200000ULL /* Reset PIF */ | ||
| 363 | #define chipcHw_REG_SOFT_RESET_I2CS 0x0000000000100000ULL /* Reset I2C Slave */ | ||
| 364 | #define chipcHw_REG_SOFT_RESET_I2CH 0x0000000000080000ULL /* Reset I2C Host */ | ||
| 365 | #define chipcHw_REG_SOFT_RESET_SDIO1 0x0000000000040000ULL /* Reset SDIO 1 */ | ||
| 366 | #define chipcHw_REG_SOFT_RESET_SDIO0 0x0000000000020000ULL /* Reset SDIO 0 */ | ||
| 367 | #define chipcHw_REG_SOFT_RESET_BBL 0x0000000000010000ULL /* Reset BBL */ | ||
| 368 | #define chipcHw_REG_SOFT_RESET_I2S1 0x0000000000008000ULL /* Reset I2S1 */ | ||
| 369 | #define chipcHw_REG_SOFT_RESET_I2S0 0x0000000000004000ULL /* Reset I2S0 */ | ||
| 370 | #define chipcHw_REG_SOFT_RESET_SPIS 0x0000000000002000ULL /* Reset SPI Slave */ | ||
| 371 | #define chipcHw_REG_SOFT_RESET_SPIH 0x0000000000001000ULL /* Reset SPI Host */ | ||
| 372 | #define chipcHw_REG_SOFT_RESET_GPIO1 0x0000000000000800ULL /* Reset GPIO block 1 */ | ||
| 373 | #define chipcHw_REG_SOFT_RESET_GPIO0 0x0000000000000400ULL /* Reset GPIO block 0 */ | ||
| 374 | #define chipcHw_REG_SOFT_RESET_UART1 0x0000000000000200ULL /* Reset UART 1 */ | ||
| 375 | #define chipcHw_REG_SOFT_RESET_UART0 0x0000000000000100ULL /* Reset UART 0 */ | ||
| 376 | #define chipcHw_REG_SOFT_RESET_NVI 0x0000000000000080ULL /* Reset NVI */ | ||
| 377 | #define chipcHw_REG_SOFT_RESET_WDOG 0x0000000000000040ULL /* Reset Watch dog */ | ||
| 378 | #define chipcHw_REG_SOFT_RESET_TMR 0x0000000000000020ULL /* Reset Timer */ | ||
| 379 | #define chipcHw_REG_SOFT_RESET_ETM 0x0000000000000010ULL /* Reset ETM */ | ||
| 380 | #define chipcHw_REG_SOFT_RESET_ARM_HOLD 0x0000000000000008ULL /* Reset ARM and HOLD */ | ||
| 381 | #define chipcHw_REG_SOFT_RESET_ARM 0x0000000000000004ULL /* Reset ARM */ | ||
| 382 | #define chipcHw_REG_SOFT_RESET_CHIP_WARM 0x0000000000000002ULL /* Chip warm reset */ | ||
| 383 | #define chipcHw_REG_SOFT_RESET_CHIP_SOFT 0x0000000000000001ULL /* Chip soft reset */ | ||
| 384 | #define chipcHw_REG_SOFT_RESET_VDEC 0x0000100000000000ULL /* Video decoder */ | ||
| 385 | #define chipcHw_REG_SOFT_RESET_GE 0x0000080000000000ULL /* Graphics engine */ | ||
| 386 | #define chipcHw_REG_SOFT_RESET_OTP 0x0000040000000000ULL /* Reset OTP */ | ||
| 387 | #define chipcHw_REG_SOFT_RESET_USB2 0x0000020000000000ULL /* Reset USB2 */ | ||
| 388 | #define chipcHw_REG_SOFT_RESET_USB1 0x0000010000000000ULL /* Reset USB 1 */ | ||
| 389 | #define chipcHw_REG_SOFT_RESET_USB 0x0000008000000000ULL /* Reset USB 1 and USB2 soft reset */ | ||
| 390 | #define chipcHw_REG_SOFT_RESET_ESW 0x0000004000000000ULL /* Reset Ethernet switch */ | ||
| 391 | #define chipcHw_REG_SOFT_RESET_ESWCLK 0x0000002000000000ULL /* Reset Ethernet switch clock */ | ||
| 392 | #define chipcHw_REG_SOFT_RESET_DDRPHY 0x0000001000000000ULL /* Reset DDR Physical */ | ||
| 393 | #define chipcHw_REG_SOFT_RESET_DDR 0x0000000800000000ULL /* Reset DDR Controller */ | ||
| 394 | #define chipcHw_REG_SOFT_RESET_TSC 0x0000000400000000ULL /* Reset Touch screen */ | ||
| 395 | #define chipcHw_REG_SOFT_RESET_PCM 0x0000000200000000ULL /* Reset PCM device */ | ||
| 396 | #define chipcHw_REG_SOFT_RESET_APM 0x0000200100000000ULL /* Reset APM device */ | ||
| 397 | |||
| 398 | #define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD 0x8000000000000000ULL /* Unhold Global VPM */ | ||
| 399 | #define chipcHw_REG_SOFT_RESET_VPM_UNHOLD 0x4000000000000000ULL /* Unhold VPM */ | ||
| 400 | #define chipcHw_REG_SOFT_RESET_ARM_UNHOLD 0x2000000000000000ULL /* Unhold ARM reset */ | ||
| 401 | #define chipcHw_REG_SOFT_RESET_UNHOLD_MASK 0xF000000000000000ULL /* Mask to handle unhold request */ | ||
| 402 | |||
| 403 | /* Audio channel control defines */ | ||
| 404 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL 0x00000001 /* Enable all audio channel */ | ||
| 405 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A 0x00000002 /* Enable channel A */ | ||
| 406 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B 0x00000004 /* Enable channel B */ | ||
| 407 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C 0x00000008 /* Enable channel C */ | ||
| 408 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK 0x00000010 /* Enable NTP clock */ | ||
| 409 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK 0x00000020 /* Enable PCM0 clock */ | ||
| 410 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK 0x00000040 /* Enable PCM1 clock */ | ||
| 411 | #define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK 0x00000080 /* Enable APM clock */ | ||
| 412 | |||
| 413 | /* Misc. chip control defines */ | ||
| 414 | #define chipcHw_REG_MISC_CTRL_GE_SEL 0x00040000 /* Select GE2/GE3 */ | ||
| 415 | #define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S1 */ | ||
| 416 | #define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO 0x00020000 /* Use external clock via GPIO pin 26 for I2S1 */ | ||
| 417 | #define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP 0x00000000 /* Use on chip clock for I2S0 */ | ||
| 418 | #define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO 0x00010000 /* Use external clock via GPIO pin 45 for I2S0 */ | ||
| 419 | #define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE 0x00008000 /* Disable ARM CP15 bit */ | ||
| 420 | #define chipcHw_REG_MISC_CTRL_RTC_DISABLE 0x00000008 /* Disable RTC registers */ | ||
| 421 | #define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE 0x00000004 /* Disable Battery Backed RAM */ | ||
| 422 | #define chipcHw_REG_MISC_CTRL_USB_MODE_HOST 0x00000002 /* Set USB as host */ | ||
| 423 | #define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE 0xFFFFFFFD /* Set USB as device */ | ||
| 424 | #define chipcHw_REG_MISC_CTRL_USB_POWERON 0xFFFFFFFE /* Power up USB */ | ||
| 425 | #define chipcHw_REG_MISC_CTRL_USB_POWEROFF 0x00000001 /* Power down USB */ | ||
| 426 | |||
| 427 | /* OTP configuration defines */ | ||
| 428 | #define chipcHw_REG_OTP_SECURITY_OFF 0x0000020000000000ULL /* Security support is OFF */ | ||
| 429 | #define chipcHw_REG_OTP_SPU_SLOW 0x0000010000000000ULL /* Limited SPU throughput */ | ||
| 430 | #define chipcHw_REG_OTP_LCD_SPEED 0x0000000600000000ULL /* Set VPM speed one */ | ||
| 431 | #define chipcHw_REG_OTP_VPM_SPEED_1 0x0000000100000000ULL /* Set VPM speed one */ | ||
| 432 | #define chipcHw_REG_OTP_VPM_SPEED_0 0x0000000080000000ULL /* Set VPM speed zero */ | ||
| 433 | #define chipcHw_REG_OTP_AXI_SPEED 0x0000000060000000ULL /* Set maximum AXI bus speed */ | ||
| 434 | #define chipcHw_REG_OTP_APM_DISABLE 0x000000001F000000ULL /* Disable APM */ | ||
| 435 | #define chipcHw_REG_OTP_PIF_DISABLE 0x0000000000200000ULL /* Disable PIF */ | ||
| 436 | #define chipcHw_REG_OTP_VDEC_DISABLE 0x0000000000100000ULL /* Disable Video decoder */ | ||
| 437 | #define chipcHw_REG_OTP_BBL_DISABLE 0x0000000000080000ULL /* Disable RTC and BBRAM */ | ||
| 438 | #define chipcHw_REG_OTP_LED_DISABLE 0x0000000000040000ULL /* Disable LED */ | ||
| 439 | #define chipcHw_REG_OTP_GE_DISABLE 0x0000000000020000ULL /* Disable Graphics Engine */ | ||
| 440 | #define chipcHw_REG_OTP_LCD_DISABLE 0x0000000000010000ULL /* Disable LCD */ | ||
| 441 | #define chipcHw_REG_OTP_KEYPAD_DISABLE 0x0000000000008000ULL /* Disable keypad */ | ||
| 442 | #define chipcHw_REG_OTP_UART_DISABLE 0x0000000000004000ULL /* Disable UART */ | ||
| 443 | #define chipcHw_REG_OTP_SDIOH_DISABLE 0x0000000000003000ULL /* Disable SDIO host */ | ||
| 444 | #define chipcHw_REG_OTP_HSS_DISABLE 0x0000000000000C00ULL /* Disable HSS */ | ||
| 445 | #define chipcHw_REG_OTP_TSC_DISABLE 0x0000000000000200ULL /* Disable touch screen */ | ||
| 446 | #define chipcHw_REG_OTP_USB_DISABLE 0x0000000000000180ULL /* Disable USB */ | ||
| 447 | #define chipcHw_REG_OTP_SGMII_DISABLE 0x0000000000000060ULL /* Disable SGMII */ | ||
| 448 | #define chipcHw_REG_OTP_ETH_DISABLE 0x0000000000000018ULL /* Disable gigabit ethernet */ | ||
| 449 | #define chipcHw_REG_OTP_ETH_PHY_DISABLE 0x0000000000000006ULL /* Disable ethernet PHY */ | ||
| 450 | #define chipcHw_REG_OTP_VPM_DISABLE 0x0000000000000001ULL /* Disable VPM */ | ||
| 451 | |||
| 452 | /* Sticky bit defines */ | ||
| 453 | #define chipcHw_REG_STICKY_BOOT_DONE 0x00000001 /* Boot done */ | ||
| 454 | #define chipcHw_REG_STICKY_SOFT_RESET 0x00000002 /* ARM soft reset */ | ||
| 455 | #define chipcHw_REG_STICKY_GENERAL_1 0x00000004 /* General purpose bit 1 */ | ||
| 456 | #define chipcHw_REG_STICKY_GENERAL_2 0x00000008 /* General purpose bit 2 */ | ||
| 457 | #define chipcHw_REG_STICKY_GENERAL_3 0x00000010 /* General purpose bit 3 */ | ||
| 458 | #define chipcHw_REG_STICKY_GENERAL_4 0x00000020 /* General purpose bit 4 */ | ||
| 459 | #define chipcHw_REG_STICKY_GENERAL_5 0x00000040 /* General purpose bit 5 */ | ||
| 460 | #define chipcHw_REG_STICKY_POR_BROM 0x00000080 /* Special sticky bit for security - set in BROM to avoid other modes being entered */ | ||
| 461 | #define chipcHw_REG_STICKY_ARM_RESET 0x00000100 /* ARM reset */ | ||
| 462 | #define chipcHw_REG_STICKY_CHIP_SOFT_RESET 0x00000200 /* Chip soft reset */ | ||
| 463 | #define chipcHw_REG_STICKY_CHIP_WARM_RESET 0x00000400 /* Chip warm reset */ | ||
| 464 | #define chipcHw_REG_STICKY_WDOG_RESET 0x00000800 /* Watchdog reset */ | ||
| 465 | #define chipcHw_REG_STICKY_OTP_RESET 0x00001000 /* OTP reset */ | ||
| 466 | |||
| 467 | /* HW phase alignment defines *//* Spare1 register definitions */ | ||
| 468 | #define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE 0x80000000 /* Enable DDR phase align panic interrupt */ | ||
| 469 | #define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE 0x40000000 /* Enable VPM phase align panic interrupt */ | ||
| 470 | #define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE 0x00000002 /* Enable access to VPM using system BUS */ | ||
| 471 | #define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE 0x00000001 /* Enable access to DDR using system BUS */ | ||
| 472 | /* DDRPhaseCtrl1 register definitions */ | ||
| 473 | #define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable DDR SW phase alignment */ | ||
| 474 | #define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable DDR HW phase alignment */ | ||
| 475 | #define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK 0x0000007F /* DDR lower threshold for phase alignment */ | ||
| 476 | #define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT 23 | ||
| 477 | #define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK 0x0000007F /* DDR upper threshold for phase alignment */ | ||
| 478 | #define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT 16 | ||
| 479 | #define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to run next DDR phase alignment */ | ||
| 480 | #define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 | ||
| 481 | /* VPMPhaseCtrl1 register definitions */ | ||
| 482 | #define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE 0x80000000 /* Enable VPM SW phase alignment */ | ||
| 483 | #define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE 0x40000000 /* Enable VPM HW phase alignment */ | ||
| 484 | #define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK 0x0000007F /* VPM lower threshold for phase alignment */ | ||
| 485 | #define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT 23 | ||
| 486 | #define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK 0x0000007F /* VPM upper threshold for phase alignment */ | ||
| 487 | #define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT 16 | ||
| 488 | #define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK 0x0000FFFF /* BUS Cycle to wait to complete the VPM phase alignment */ | ||
| 489 | #define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT 0 | ||
| 490 | /* PhaseAlignStatus register definitions */ | ||
| 491 | #define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS 0x80000000 /* DDR time out interrupt status */ | ||
| 492 | #define chipcHw_REG_DDR_PHASE_STATUS_MASK 0x0000007F /* DDR phase status value */ | ||
| 493 | #define chipcHw_REG_DDR_PHASE_STATUS_SHIFT 24 | ||
| 494 | #define chipcHw_REG_DDR_PHASE_ALIGNED 0x00800000 /* DDR Phase aligned status */ | ||
| 495 | #define chipcHw_REG_DDR_LOAD 0x00400000 /* Load DDR phase status */ | ||
| 496 | #define chipcHw_REG_DDR_PHASE_CTRL_MASK 0x0000003F /* DDR phase control value */ | ||
| 497 | #define chipcHw_REG_DDR_PHASE_CTRL_SHIFT 16 | ||
| 498 | #define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS 0x80000000 /* VPM time out interrupt status */ | ||
| 499 | #define chipcHw_REG_VPM_PHASE_STATUS_MASK 0x0000007F /* VPM phase status value */ | ||
| 500 | #define chipcHw_REG_VPM_PHASE_STATUS_SHIFT 8 | ||
| 501 | #define chipcHw_REG_VPM_PHASE_ALIGNED 0x00000080 /* VPM Phase aligned status */ | ||
| 502 | #define chipcHw_REG_VPM_LOAD 0x00000040 /* Load VPM phase status */ | ||
| 503 | #define chipcHw_REG_VPM_PHASE_CTRL_MASK 0x0000003F /* VPM phase control value */ | ||
| 504 | #define chipcHw_REG_VPM_PHASE_CTRL_SHIFT 0 | ||
| 505 | /* DDRPhaseCtrl2 register definitions */ | ||
| 506 | #define chipcHw_REG_DDR_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ | ||
| 507 | #define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ | ||
| 508 | #define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ | ||
| 509 | #define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT 20 | ||
| 510 | #define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait to settle ph_ctrl and load_ch */ | ||
| 511 | #define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 | ||
| 512 | #define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for DDR HW phase alignment */ | ||
| 513 | #define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT 0 | ||
| 514 | /* VPMPhaseCtrl2 register definitions */ | ||
| 515 | #define chipcHw_REG_VPM_INTR_SELECT_MASK 0x00000003 /* Interrupt select */ | ||
| 516 | #define chipcHw_REG_VPM_INTR_SELECT_SHIFT 26 | ||
| 517 | #define chipcHw_REG_VPM_INTR_DISABLE 0x00000000 | ||
| 518 | #define chipcHw_REG_VPM_INTR_FAST (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) | ||
| 519 | #define chipcHw_REG_VPM_INTR_MEDIUM (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) | ||
| 520 | #define chipcHw_REG_VPM_INTR_SLOW (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT) | ||
| 521 | #define chipcHw_REG_VPM_INTR_SERVICED 0x02000000 /* Acknowledge that interrupt was serviced */ | ||
| 522 | #define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE 0x01000000 /* Enable time out interrupt */ | ||
| 523 | #define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK 0x0000000F /* Wait before toggling load_ch */ | ||
| 524 | #define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT 20 | ||
| 525 | #define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK 0x0000000F /* Total wait cycle to settle ph_ctrl and load_ch */ | ||
| 526 | #define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT 16 | ||
| 527 | #define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK 0x0000FFFF /* Time out value for VPM HW phase alignment */ | ||
| 528 | #define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT 0 | ||
| 529 | |||
| 530 | #endif /* CHIPCHW_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h new file mode 100644 index 000000000000..f1b68e26fa6d --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h | |||
| @@ -0,0 +1,872 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file ddrcReg.h | ||
| 18 | * | ||
| 19 | * @brief Register definitions for BCMRING DDR2 Controller and PHY | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | |||
| 24 | #ifndef DDRC_REG_H | ||
| 25 | #define DDRC_REG_H | ||
| 26 | |||
| 27 | #ifdef __cplusplus | ||
| 28 | extern "C" { | ||
| 29 | #endif | ||
| 30 | |||
| 31 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 32 | |||
| 33 | #include <csp/reg.h> | ||
| 34 | #include <csp/stdint.h> | ||
| 35 | |||
| 36 | #include <mach/csp/mm_io.h> | ||
| 37 | |||
| 38 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 39 | |||
| 40 | /*********************************************************************/ | ||
| 41 | /* DDR2 Controller (ARM PL341) register definitions */ | ||
| 42 | /*********************************************************************/ | ||
| 43 | |||
| 44 | /* -------------------------------------------------------------------- */ | ||
| 45 | /* -------------------------------------------------------------------- */ | ||
| 46 | /* ARM PL341 DDR2 configuration registers, offset 0x000 */ | ||
| 47 | /* -------------------------------------------------------------------- */ | ||
| 48 | /* -------------------------------------------------------------------- */ | ||
| 49 | |||
| 50 | typedef struct { | ||
| 51 | uint32_t memcStatus; | ||
| 52 | uint32_t memcCmd; | ||
| 53 | uint32_t directCmd; | ||
| 54 | uint32_t memoryCfg; | ||
| 55 | uint32_t refreshPrd; | ||
| 56 | uint32_t casLatency; | ||
| 57 | uint32_t writeLatency; | ||
| 58 | uint32_t tMrd; | ||
| 59 | uint32_t tRas; | ||
| 60 | uint32_t tRc; | ||
| 61 | uint32_t tRcd; | ||
| 62 | uint32_t tRfc; | ||
| 63 | uint32_t tRp; | ||
| 64 | uint32_t tRrd; | ||
| 65 | uint32_t tWr; | ||
| 66 | uint32_t tWtr; | ||
| 67 | uint32_t tXp; | ||
| 68 | uint32_t tXsr; | ||
| 69 | uint32_t tEsr; | ||
| 70 | uint32_t memoryCfg2; | ||
| 71 | uint32_t memoryCfg3; | ||
| 72 | uint32_t tFaw; | ||
| 73 | } ddrcReg_CTLR_MEMC_REG_t; | ||
| 74 | |||
| 75 | #define ddrcReg_CTLR_MEMC_REG_OFFSET 0x0000 | ||
| 76 | #define ddrcReg_CTLR_MEMC_REGP ((volatile ddrcReg_CTLR_MEMC_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET)) | ||
| 77 | |||
| 78 | /* ----------------------------------------------------- */ | ||
| 79 | |||
| 80 | #define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK (0x3 << 12) | ||
| 81 | #define ddrcReg_CTLR_MEMC_STATUS_BANKS_4 (0x0 << 12) | ||
| 82 | #define ddrcReg_CTLR_MEMC_STATUS_BANKS_8 (0x3 << 12) | ||
| 83 | |||
| 84 | #define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK (0x3 << 10) | ||
| 85 | #define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0 (0x0 << 10) | ||
| 86 | #define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1 (0x1 << 10) | ||
| 87 | #define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2 (0x2 << 10) | ||
| 88 | #define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4 (0x3 << 10) | ||
| 89 | |||
| 90 | #define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK (0x3 << 7) | ||
| 91 | #define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1 (0x0 << 7) | ||
| 92 | #define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2 (0x1 << 7) | ||
| 93 | #define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3 (0x2 << 7) | ||
| 94 | #define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4 (0x3 << 7) | ||
| 95 | |||
| 96 | #define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK (0x7 << 4) | ||
| 97 | #define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2 (0x5 << 4) | ||
| 98 | |||
| 99 | #define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK (0x3 << 2) | ||
| 100 | #define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16 (0x0 << 2) | ||
| 101 | #define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32 (0x1 << 2) | ||
| 102 | #define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64 (0x2 << 2) | ||
| 103 | #define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128 (0x3 << 2) | ||
| 104 | |||
| 105 | #define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK (0x3 << 0) | ||
| 106 | #define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG (0x0 << 0) | ||
| 107 | #define ddrcReg_CTLR_MEMC_STATUS_STATE_READY (0x1 << 0) | ||
| 108 | #define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED (0x2 << 0) | ||
| 109 | #define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR (0x3 << 0) | ||
| 110 | |||
| 111 | /* ----------------------------------------------------- */ | ||
| 112 | |||
| 113 | #define ddrcReg_CTLR_MEMC_CMD_MASK (0x7 << 0) | ||
| 114 | #define ddrcReg_CTLR_MEMC_CMD_GO (0x0 << 0) | ||
| 115 | #define ddrcReg_CTLR_MEMC_CMD_SLEEP (0x1 << 0) | ||
| 116 | #define ddrcReg_CTLR_MEMC_CMD_WAKEUP (0x2 << 0) | ||
| 117 | #define ddrcReg_CTLR_MEMC_CMD_PAUSE (0x3 << 0) | ||
| 118 | #define ddrcReg_CTLR_MEMC_CMD_CONFIGURE (0x4 << 0) | ||
| 119 | #define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE (0x7 << 0) | ||
| 120 | |||
| 121 | /* ----------------------------------------------------- */ | ||
| 122 | |||
| 123 | #define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT 20 | ||
| 124 | #define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT) | ||
| 125 | |||
| 126 | #define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL (0x0 << 18) | ||
| 127 | #define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH (0x1 << 18) | ||
| 128 | #define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG (0x2 << 18) | ||
| 129 | #define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP (0x3 << 18) | ||
| 130 | |||
| 131 | #define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT 16 | ||
| 132 | #define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT) | ||
| 133 | |||
| 134 | #define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT 0 | ||
| 135 | #define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT) | ||
| 136 | |||
| 137 | /* ----------------------------------------------------- */ | ||
| 138 | |||
| 139 | #define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK (0x3 << 21) | ||
| 140 | #define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1 (0x0 << 21) | ||
| 141 | #define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2 (0x1 << 21) | ||
| 142 | #define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3 (0x2 << 21) | ||
| 143 | #define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4 (0x3 << 21) | ||
| 144 | |||
| 145 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK (0x7 << 18) | ||
| 146 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0 (0x0 << 18) | ||
| 147 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1 (0x1 << 18) | ||
| 148 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2 (0x2 << 18) | ||
| 149 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3 (0x3 << 18) | ||
| 150 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4 (0x4 << 18) | ||
| 151 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5 (0x5 << 18) | ||
| 152 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6 (0x6 << 18) | ||
| 153 | #define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7 (0x7 << 18) | ||
| 154 | |||
| 155 | #define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK (0x7 << 15) | ||
| 156 | #define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4 (0x2 << 15) | ||
| 157 | #define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8 (0x3 << 15) /* @note Not supported in PL341 */ | ||
| 158 | |||
| 159 | #define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE (0x1 << 13) | ||
| 160 | |||
| 161 | #define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT 7 | ||
| 162 | #define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT) | ||
| 163 | |||
| 164 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK (0x7 << 3) | ||
| 165 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11 (0x0 << 3) | ||
| 166 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12 (0x1 << 3) | ||
| 167 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13 (0x2 << 3) | ||
| 168 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14 (0x3 << 3) | ||
| 169 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15 (0x4 << 3) | ||
| 170 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16 (0x5 << 3) | ||
| 171 | |||
| 172 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK (0x7 << 0) | ||
| 173 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9 (0x1 << 0) | ||
| 174 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10 (0x2 << 0) | ||
| 175 | #define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11 (0x3 << 0) | ||
| 176 | |||
| 177 | /* ----------------------------------------------------- */ | ||
| 178 | |||
| 179 | #define ddrcReg_CTLR_REFRESH_PRD_SHIFT 0 | ||
| 180 | #define ddrcReg_CTLR_REFRESH_PRD_MASK (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT) | ||
| 181 | |||
| 182 | /* ----------------------------------------------------- */ | ||
| 183 | |||
| 184 | #define ddrcReg_CTLR_CAS_LATENCY_SHIFT 1 | ||
| 185 | #define ddrcReg_CTLR_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT) | ||
| 186 | |||
| 187 | /* ----------------------------------------------------- */ | ||
| 188 | |||
| 189 | #define ddrcReg_CTLR_WRITE_LATENCY_SHIFT 0 | ||
| 190 | #define ddrcReg_CTLR_WRITE_LATENCY_MASK (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT) | ||
| 191 | |||
| 192 | /* ----------------------------------------------------- */ | ||
| 193 | |||
| 194 | #define ddrcReg_CTLR_T_MRD_SHIFT 0 | ||
| 195 | #define ddrcReg_CTLR_T_MRD_MASK (0x7f << ddrcReg_CTLR_T_MRD_SHIFT) | ||
| 196 | |||
| 197 | /* ----------------------------------------------------- */ | ||
| 198 | |||
| 199 | #define ddrcReg_CTLR_T_RAS_SHIFT 0 | ||
| 200 | #define ddrcReg_CTLR_T_RAS_MASK (0x1f << ddrcReg_CTLR_T_RAS_SHIFT) | ||
| 201 | |||
| 202 | /* ----------------------------------------------------- */ | ||
| 203 | |||
| 204 | #define ddrcReg_CTLR_T_RC_SHIFT 0 | ||
| 205 | #define ddrcReg_CTLR_T_RC_MASK (0x1f << ddrcReg_CTLR_T_RC_SHIFT) | ||
| 206 | |||
| 207 | /* ----------------------------------------------------- */ | ||
| 208 | |||
| 209 | #define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT 8 | ||
| 210 | #define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT) | ||
| 211 | |||
| 212 | #define ddrcReg_CTLR_T_RCD_SHIFT 0 | ||
| 213 | #define ddrcReg_CTLR_T_RCD_MASK (0x7 << ddrcReg_CTLR_T_RCD_SHIFT) | ||
| 214 | |||
| 215 | /* ----------------------------------------------------- */ | ||
| 216 | |||
| 217 | #define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT 8 | ||
| 218 | #define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT) | ||
| 219 | |||
| 220 | #define ddrcReg_CTLR_T_RFC_SHIFT 0 | ||
| 221 | #define ddrcReg_CTLR_T_RFC_MASK (0x7f << ddrcReg_CTLR_T_RFC_SHIFT) | ||
| 222 | |||
| 223 | /* ----------------------------------------------------- */ | ||
| 224 | |||
| 225 | #define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT 8 | ||
| 226 | #define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT) | ||
| 227 | |||
| 228 | #define ddrcReg_CTLR_T_RP_SHIFT 0 | ||
| 229 | #define ddrcReg_CTLR_T_RP_MASK (0xf << ddrcReg_CTLR_T_RP_SHIFT) | ||
| 230 | |||
| 231 | /* ----------------------------------------------------- */ | ||
| 232 | |||
| 233 | #define ddrcReg_CTLR_T_RRD_SHIFT 0 | ||
| 234 | #define ddrcReg_CTLR_T_RRD_MASK (0xf << ddrcReg_CTLR_T_RRD_SHIFT) | ||
| 235 | |||
| 236 | /* ----------------------------------------------------- */ | ||
| 237 | |||
| 238 | #define ddrcReg_CTLR_T_WR_SHIFT 0 | ||
| 239 | #define ddrcReg_CTLR_T_WR_MASK (0x7 << ddrcReg_CTLR_T_WR_SHIFT) | ||
| 240 | |||
| 241 | /* ----------------------------------------------------- */ | ||
| 242 | |||
| 243 | #define ddrcReg_CTLR_T_WTR_SHIFT 0 | ||
| 244 | #define ddrcReg_CTLR_T_WTR_MASK (0x7 << ddrcReg_CTLR_T_WTR_SHIFT) | ||
| 245 | |||
| 246 | /* ----------------------------------------------------- */ | ||
| 247 | |||
| 248 | #define ddrcReg_CTLR_T_XP_SHIFT 0 | ||
| 249 | #define ddrcReg_CTLR_T_XP_MASK (0xff << ddrcReg_CTLR_T_XP_SHIFT) | ||
| 250 | |||
| 251 | /* ----------------------------------------------------- */ | ||
| 252 | |||
| 253 | #define ddrcReg_CTLR_T_XSR_SHIFT 0 | ||
| 254 | #define ddrcReg_CTLR_T_XSR_MASK (0xff << ddrcReg_CTLR_T_XSR_SHIFT) | ||
| 255 | |||
| 256 | /* ----------------------------------------------------- */ | ||
| 257 | |||
| 258 | #define ddrcReg_CTLR_T_ESR_SHIFT 0 | ||
| 259 | #define ddrcReg_CTLR_T_ESR_MASK (0xff << ddrcReg_CTLR_T_ESR_SHIFT) | ||
| 260 | |||
| 261 | /* ----------------------------------------------------- */ | ||
| 262 | |||
| 263 | #define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK (0x3 << 6) | ||
| 264 | #define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS (0 << 6) | ||
| 265 | #define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS (1 << 6) | ||
| 266 | #define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS (2 << 6) | ||
| 267 | |||
| 268 | #define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK (0x3 << 4) | ||
| 269 | #define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2 (0 << 4) | ||
| 270 | #define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3 (3 << 4) | ||
| 271 | |||
| 272 | #define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW (0 << 3) | ||
| 273 | #define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH (1 << 3) | ||
| 274 | |||
| 275 | #define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW (0 << 2) | ||
| 276 | #define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH (1 << 2) | ||
| 277 | |||
| 278 | #define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK (0x3 << 0) | ||
| 279 | #define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC (0 << 0) | ||
| 280 | #define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M (1 << 0) | ||
| 281 | #define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M (3 << 0) | ||
| 282 | |||
| 283 | /* ----------------------------------------------------- */ | ||
| 284 | |||
| 285 | #define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT 0 | ||
| 286 | #define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT) | ||
| 287 | |||
| 288 | /* ----------------------------------------------------- */ | ||
| 289 | |||
| 290 | #define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT 8 | ||
| 291 | #define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT) | ||
| 292 | |||
| 293 | #define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT 0 | ||
| 294 | #define ddrcReg_CTLR_T_FAW_PERIOD_MASK (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT) | ||
| 295 | |||
| 296 | /* -------------------------------------------------------------------- */ | ||
| 297 | /* -------------------------------------------------------------------- */ | ||
| 298 | /* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */ | ||
| 299 | /* -------------------------------------------------------------------- */ | ||
| 300 | /* -------------------------------------------------------------------- */ | ||
| 301 | |||
| 302 | #define ddrcReg_CTLR_QOS_CNT 16 | ||
| 303 | #define ddrcReg_CTLR_QOS_MAX (ddrcReg_CTLR_QOS_CNT - 1) | ||
| 304 | |||
| 305 | typedef struct { | ||
| 306 | uint32_t cfg[ddrcReg_CTLR_QOS_CNT]; | ||
| 307 | } ddrcReg_CTLR_QOS_REG_t; | ||
| 308 | |||
| 309 | #define ddrcReg_CTLR_QOS_REG_OFFSET 0x100 | ||
| 310 | #define ddrcReg_CTLR_QOS_REGP ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET)) | ||
| 311 | |||
| 312 | /* ----------------------------------------------------- */ | ||
| 313 | |||
| 314 | #define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT 2 | ||
| 315 | #define ddrcReg_CTLR_QOS_CFG_MAX_MASK (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT) | ||
| 316 | |||
| 317 | #define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT 1 | ||
| 318 | #define ddrcReg_CTLR_QOS_CFG_MIN_MASK (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT) | ||
| 319 | |||
| 320 | #define ddrcReg_CTLR_QOS_CFG_ENABLE (1 << 0) | ||
| 321 | |||
| 322 | /* -------------------------------------------------------------------- */ | ||
| 323 | /* -------------------------------------------------------------------- */ | ||
| 324 | /* ARM PL341 Memory chip configuration registers, offset 0x200 */ | ||
| 325 | /* -------------------------------------------------------------------- */ | ||
| 326 | /* -------------------------------------------------------------------- */ | ||
| 327 | |||
| 328 | #define ddrcReg_CTLR_CHIP_CNT 4 | ||
| 329 | #define ddrcReg_CTLR_CHIP_MAX (ddrcReg_CTLR_CHIP_CNT - 1) | ||
| 330 | |||
| 331 | typedef struct { | ||
| 332 | uint32_t cfg[ddrcReg_CTLR_CHIP_CNT]; | ||
| 333 | } ddrcReg_CTLR_CHIP_REG_t; | ||
| 334 | |||
| 335 | #define ddrcReg_CTLR_CHIP_REG_OFFSET 0x200 | ||
| 336 | #define ddrcReg_CTLR_CHIP_REGP ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET)) | ||
| 337 | |||
| 338 | /* ----------------------------------------------------- */ | ||
| 339 | |||
| 340 | #define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK (1 << 16) | ||
| 341 | #define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL (0 << 16) | ||
| 342 | #define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL (1 << 16) | ||
| 343 | |||
| 344 | #define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT 8 | ||
| 345 | #define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT) | ||
| 346 | |||
| 347 | #define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT 0 | ||
| 348 | #define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT) | ||
| 349 | |||
| 350 | /* -------------------------------------------------------------------- */ | ||
| 351 | /* -------------------------------------------------------------------- */ | ||
| 352 | /* ARM PL341 User configuration registers, offset 0x300 */ | ||
| 353 | /* -------------------------------------------------------------------- */ | ||
| 354 | /* -------------------------------------------------------------------- */ | ||
| 355 | |||
| 356 | #define ddrcReg_CTLR_USER_OUTPUT_CNT 2 | ||
| 357 | |||
| 358 | typedef struct { | ||
| 359 | uint32_t input; | ||
| 360 | uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT]; | ||
| 361 | uint32_t feature; | ||
| 362 | } ddrcReg_CTLR_USER_REG_t; | ||
| 363 | |||
| 364 | #define ddrcReg_CTLR_USER_REG_OFFSET 0x300 | ||
| 365 | #define ddrcReg_CTLR_USER_REGP ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET)) | ||
| 366 | |||
| 367 | /* ----------------------------------------------------- */ | ||
| 368 | |||
| 369 | #define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT 0 | ||
| 370 | #define ddrcReg_CTLR_USER_INPUT_STATUS_MASK (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT) | ||
| 371 | |||
| 372 | /* ----------------------------------------------------- */ | ||
| 373 | |||
| 374 | #define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT 0 | ||
| 375 | #define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT) | ||
| 376 | |||
| 377 | #define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT 1 | ||
| 378 | #define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) | ||
| 379 | #define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) | ||
| 380 | #define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT) | ||
| 381 | #define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301 | ||
| 382 | |||
| 383 | /* ----------------------------------------------------- */ | ||
| 384 | |||
| 385 | #define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE (1 << 2) | ||
| 386 | #define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE (1 << 0) | ||
| 387 | |||
| 388 | /*********************************************************************/ | ||
| 389 | /* Broadcom DDR23 PHY register definitions */ | ||
| 390 | /*********************************************************************/ | ||
| 391 | |||
| 392 | /* -------------------------------------------------------------------- */ | ||
| 393 | /* -------------------------------------------------------------------- */ | ||
| 394 | /* Broadcom DDR23 PHY Address and Control register definitions */ | ||
| 395 | /* -------------------------------------------------------------------- */ | ||
| 396 | /* -------------------------------------------------------------------- */ | ||
| 397 | |||
| 398 | typedef struct { | ||
| 399 | uint32_t revision; | ||
| 400 | uint32_t pmCtl; | ||
| 401 | REG32_RSVD(0x0008, 0x0010); | ||
| 402 | uint32_t pllStatus; | ||
| 403 | uint32_t pllCfg; | ||
| 404 | uint32_t pllPreDiv; | ||
| 405 | uint32_t pllDiv; | ||
| 406 | uint32_t pllCtl1; | ||
| 407 | uint32_t pllCtl2; | ||
| 408 | uint32_t ssCtl; | ||
| 409 | uint32_t ssCfg; | ||
| 410 | uint32_t vdlStatic; | ||
| 411 | uint32_t vdlDynamic; | ||
| 412 | uint32_t padIdle; | ||
| 413 | uint32_t pvtComp; | ||
| 414 | uint32_t padDrive; | ||
| 415 | uint32_t clkRgltrCtl; | ||
| 416 | } ddrcReg_PHY_ADDR_CTL_REG_t; | ||
| 417 | |||
| 418 | #define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400 | ||
| 419 | #define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET)) | ||
| 420 | |||
| 421 | /* @todo These SS definitions are duplicates of ones below */ | ||
| 422 | |||
| 423 | #define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE 0x00000001 | ||
| 424 | #define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK 0xFFFF0000 | ||
| 425 | #define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT 16 | ||
| 426 | #define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK 10 /* Higher the value, lower the SS modulation frequency */ | ||
| 427 | #define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK 0x0000FFFF | ||
| 428 | #define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT 0 | ||
| 429 | |||
| 430 | /* ----------------------------------------------------- */ | ||
| 431 | |||
| 432 | #define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT 8 | ||
| 433 | #define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT) | ||
| 434 | |||
| 435 | #define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT 0 | ||
| 436 | #define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT) | ||
| 437 | |||
| 438 | /* ----------------------------------------------------- */ | ||
| 439 | |||
| 440 | #define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0) | ||
| 441 | |||
| 442 | /* ----------------------------------------------------- */ | ||
| 443 | |||
| 444 | #define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED (1 << 0) | ||
| 445 | |||
| 446 | /* ----------------------------------------------------- */ | ||
| 447 | |||
| 448 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET (1 << 31) | ||
| 449 | |||
| 450 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT 17 | ||
| 451 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT) | ||
| 452 | |||
| 453 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE (1 << 16) | ||
| 454 | |||
| 455 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT 12 | ||
| 456 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT) | ||
| 457 | |||
| 458 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG (1 << 7) | ||
| 459 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN (1 << 6) | ||
| 460 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE (1 << 5) | ||
| 461 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE (1 << 4) | ||
| 462 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET (1 << 3) | ||
| 463 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET (1 << 2) | ||
| 464 | #define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN (1 << 0) | ||
| 465 | |||
| 466 | /* ----------------------------------------------------- */ | ||
| 467 | |||
| 468 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB (1 << 26) | ||
| 469 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN (1 << 25) | ||
| 470 | |||
| 471 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT 20 | ||
| 472 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT) | ||
| 473 | |||
| 474 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT 8 | ||
| 475 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT) | ||
| 476 | |||
| 477 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT 4 | ||
| 478 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT) | ||
| 479 | |||
| 480 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT 0 | ||
| 481 | #define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT) | ||
| 482 | |||
| 483 | /* ----------------------------------------------------- */ | ||
| 484 | |||
| 485 | #define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT 24 | ||
| 486 | #define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT) | ||
| 487 | |||
| 488 | #define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT 0 | ||
| 489 | #define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT) | ||
| 490 | |||
| 491 | /* ----------------------------------------------------- */ | ||
| 492 | |||
| 493 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT 30 | ||
| 494 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT) | ||
| 495 | |||
| 496 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT 27 | ||
| 497 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT) | ||
| 498 | |||
| 499 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT 24 | ||
| 500 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT) | ||
| 501 | |||
| 502 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT 22 | ||
| 503 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT) | ||
| 504 | |||
| 505 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER (0x1 << 21) | ||
| 506 | |||
| 507 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT 19 | ||
| 508 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT) | ||
| 509 | |||
| 510 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT 17 | ||
| 511 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT) | ||
| 512 | |||
| 513 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT 15 | ||
| 514 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT) | ||
| 515 | |||
| 516 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT 13 | ||
| 517 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT) | ||
| 518 | |||
| 519 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT 10 | ||
| 520 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT) | ||
| 521 | |||
| 522 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT 5 | ||
| 523 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT) | ||
| 524 | |||
| 525 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT 0 | ||
| 526 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT) | ||
| 527 | |||
| 528 | /* ----------------------------------------------------- */ | ||
| 529 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT 4 | ||
| 530 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT) | ||
| 531 | |||
| 532 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT 2 | ||
| 533 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT) | ||
| 534 | |||
| 535 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE (0x1 << 1) | ||
| 536 | #define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE (0x1 << 0) | ||
| 537 | |||
| 538 | /* ----------------------------------------------------- */ | ||
| 539 | |||
| 540 | #define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE (0x1 << 0) | ||
| 541 | |||
| 542 | /* ----------------------------------------------------- */ | ||
| 543 | |||
| 544 | #define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT 16 | ||
| 545 | #define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT) | ||
| 546 | |||
| 547 | #define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT 0 | ||
| 548 | #define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT) | ||
| 549 | |||
| 550 | /* ----------------------------------------------------- */ | ||
| 551 | |||
| 552 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE (1 << 20) | ||
| 553 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE (1 << 16) | ||
| 554 | |||
| 555 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT 12 | ||
| 556 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT) | ||
| 557 | |||
| 558 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT 8 | ||
| 559 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT) | ||
| 560 | |||
| 561 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT 0 | ||
| 562 | #define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT) | ||
| 563 | |||
| 564 | /* ----------------------------------------------------- */ | ||
| 565 | |||
| 566 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE (1 << 16) | ||
| 567 | |||
| 568 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT 12 | ||
| 569 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT) | ||
| 570 | |||
| 571 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT 8 | ||
| 572 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT) | ||
| 573 | |||
| 574 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT 0 | ||
| 575 | #define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT) | ||
| 576 | |||
| 577 | /* ----------------------------------------------------- */ | ||
| 578 | |||
| 579 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE (1u << 31) | ||
| 580 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE (1 << 8) | ||
| 581 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE (1 << 6) | ||
| 582 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE (1 << 5) | ||
| 583 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE (1 << 4) | ||
| 584 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE (1 << 2) | ||
| 585 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE (1 << 1) | ||
| 586 | #define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE (1 << 0) | ||
| 587 | |||
| 588 | /* ----------------------------------------------------- */ | ||
| 589 | |||
| 590 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE (1 << 30) | ||
| 591 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE (1 << 29) | ||
| 592 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE (1 << 28) | ||
| 593 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE (1 << 27) | ||
| 594 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE (1 << 26) | ||
| 595 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE (1 << 25) | ||
| 596 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE (1 << 24) | ||
| 597 | |||
| 598 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT 20 | ||
| 599 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT) | ||
| 600 | |||
| 601 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT 16 | ||
| 602 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT) | ||
| 603 | |||
| 604 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT 12 | ||
| 605 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT) | ||
| 606 | |||
| 607 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT 8 | ||
| 608 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT) | ||
| 609 | |||
| 610 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT 4 | ||
| 611 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT) | ||
| 612 | |||
| 613 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT 0 | ||
| 614 | #define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT) | ||
| 615 | |||
| 616 | /* ----------------------------------------------------- */ | ||
| 617 | |||
| 618 | #define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B (1 << 4) | ||
| 619 | #define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18 (1 << 3) | ||
| 620 | #define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI (1 << 2) | ||
| 621 | #define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV (1 << 1) | ||
| 622 | #define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW (1 << 0) | ||
| 623 | |||
| 624 | /* ----------------------------------------------------- */ | ||
| 625 | |||
| 626 | #define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF (1 << 1) | ||
| 627 | #define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF (1 << 0) | ||
| 628 | |||
| 629 | /* -------------------------------------------------------------------- */ | ||
| 630 | /* -------------------------------------------------------------------- */ | ||
| 631 | /* Broadcom DDR23 PHY Byte Lane register definitions */ | ||
| 632 | /* -------------------------------------------------------------------- */ | ||
| 633 | /* -------------------------------------------------------------------- */ | ||
| 634 | |||
| 635 | #define ddrcReg_PHY_BYTE_LANE_CNT 2 | ||
| 636 | #define ddrcReg_PHY_BYTE_LANE_MAX (ddrcReg_CTLR_BYTE_LANE_CNT - 1) | ||
| 637 | |||
| 638 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT 8 | ||
| 639 | |||
| 640 | typedef struct { | ||
| 641 | uint32_t revision; | ||
| 642 | uint32_t vdlCalibrate; | ||
| 643 | uint32_t vdlStatus; | ||
| 644 | REG32_RSVD(0x000c, 0x0010); | ||
| 645 | uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT]; | ||
| 646 | uint32_t readCtl; | ||
| 647 | uint32_t readStatus; | ||
| 648 | uint32_t readClear; | ||
| 649 | uint32_t padIdleCtl; | ||
| 650 | uint32_t padDriveCtl; | ||
| 651 | uint32_t padClkCtl; | ||
| 652 | uint32_t writeCtl; | ||
| 653 | uint32_t clkRegCtl; | ||
| 654 | } ddrcReg_PHY_BYTE_LANE_REG_t; | ||
| 655 | |||
| 656 | /* There are 2 instances of the byte Lane registers, one for each byte lane. */ | ||
| 657 | #define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET 0x0500 | ||
| 658 | #define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET 0x0600 | ||
| 659 | |||
| 660 | #define ddrcReg_PHY_BYTE_LANE_1_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET)) | ||
| 661 | #define ddrcReg_PHY_BYTE_LANE_2_REGP ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET)) | ||
| 662 | |||
| 663 | /* ----------------------------------------------------- */ | ||
| 664 | |||
| 665 | #define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT 8 | ||
| 666 | #define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT) | ||
| 667 | |||
| 668 | #define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT 0 | ||
| 669 | #define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT) | ||
| 670 | |||
| 671 | /* ----------------------------------------------------- */ | ||
| 672 | |||
| 673 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE (1 << 4) | ||
| 674 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE (0 << 4) | ||
| 675 | |||
| 676 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST (1 << 3) | ||
| 677 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS (1 << 2) | ||
| 678 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE (1 << 1) | ||
| 679 | #define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST (1 << 0) | ||
| 680 | |||
| 681 | /* ----------------------------------------------------- */ | ||
| 682 | |||
| 683 | /* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */ | ||
| 684 | /* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */ | ||
| 685 | /* register. The fine rise and fall are no longer used, so add some definitions for just */ | ||
| 686 | /* the step setting to simplify things. */ | ||
| 687 | |||
| 688 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT 8 | ||
| 689 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT) | ||
| 690 | |||
| 691 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT 4 | ||
| 692 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT) | ||
| 693 | |||
| 694 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK (1 << 1) | ||
| 695 | #define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE (1 << 0) | ||
| 696 | |||
| 697 | /* ----------------------------------------------------- */ | ||
| 698 | |||
| 699 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE (1 << 16) | ||
| 700 | |||
| 701 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT 12 | ||
| 702 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT) | ||
| 703 | |||
| 704 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT 8 | ||
| 705 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT) | ||
| 706 | |||
| 707 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT 0 | ||
| 708 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT) | ||
| 709 | |||
| 710 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P 0 | ||
| 711 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N 1 | ||
| 712 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN 2 | ||
| 713 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM 3 | ||
| 714 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P 4 | ||
| 715 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N 5 | ||
| 716 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN 6 | ||
| 717 | #define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM 7 | ||
| 718 | |||
| 719 | /* ----------------------------------------------------- */ | ||
| 720 | |||
| 721 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT 8 | ||
| 722 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT) | ||
| 723 | |||
| 724 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE (1 << 3) | ||
| 725 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST (1 << 2) | ||
| 726 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE (1 << 1) | ||
| 727 | #define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST (1 << 0) | ||
| 728 | |||
| 729 | /* ----------------------------------------------------- */ | ||
| 730 | |||
| 731 | #define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT 0 | ||
| 732 | #define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT) | ||
| 733 | |||
| 734 | /* ----------------------------------------------------- */ | ||
| 735 | |||
| 736 | #define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS (1 << 0) | ||
| 737 | |||
| 738 | /* ----------------------------------------------------- */ | ||
| 739 | |||
| 740 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE (1u << 31) | ||
| 741 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE (1 << 19) | ||
| 742 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE (1 << 18) | ||
| 743 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE (1 << 17) | ||
| 744 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE (1 << 16) | ||
| 745 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE (1 << 15) | ||
| 746 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE (1 << 14) | ||
| 747 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE (1 << 13) | ||
| 748 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE (1 << 12) | ||
| 749 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE (1 << 11) | ||
| 750 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE (1 << 10) | ||
| 751 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE (1 << 9) | ||
| 752 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE (1 << 8) | ||
| 753 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE (1 << 7) | ||
| 754 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE (1 << 6) | ||
| 755 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE (1 << 5) | ||
| 756 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE (1 << 4) | ||
| 757 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE (1 << 3) | ||
| 758 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE (1 << 2) | ||
| 759 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE (1 << 1) | ||
| 760 | #define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE (1 << 0) | ||
| 761 | |||
| 762 | /* ----------------------------------------------------- */ | ||
| 763 | |||
| 764 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB (1 << 5) | ||
| 765 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B (1 << 4) | ||
| 766 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18 (1 << 3) | ||
| 767 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI (1 << 2) | ||
| 768 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV (1 << 1) | ||
| 769 | #define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW (1 << 0) | ||
| 770 | |||
| 771 | /* ----------------------------------------------------- */ | ||
| 772 | |||
| 773 | #define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE (1 << 0) | ||
| 774 | |||
| 775 | /* ----------------------------------------------------- */ | ||
| 776 | |||
| 777 | #define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3 (1 << 0) | ||
| 778 | |||
| 779 | /* ----------------------------------------------------- */ | ||
| 780 | |||
| 781 | #define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF (1 << 1) | ||
| 782 | #define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF (1 << 0) | ||
| 783 | |||
| 784 | /*********************************************************************/ | ||
| 785 | /* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */ | ||
| 786 | /*********************************************************************/ | ||
| 787 | |||
| 788 | typedef struct { | ||
| 789 | uint32_t cfg; | ||
| 790 | uint32_t actMonCnt; | ||
| 791 | uint32_t ctl; | ||
| 792 | uint32_t lbistCtl; | ||
| 793 | uint32_t lbistSeed; | ||
| 794 | uint32_t lbistStatus; | ||
| 795 | uint32_t tieOff; | ||
| 796 | uint32_t actMonClear; | ||
| 797 | uint32_t status; | ||
| 798 | uint32_t user; | ||
| 799 | } ddrcReg_CTLR_PHY_GLUE_REG_t; | ||
| 800 | |||
| 801 | #define ddrcReg_CTLR_PHY_GLUE_OFFSET 0x0700 | ||
| 802 | #define ddrcReg_CTLR_PHY_GLUE_REGP ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET)) | ||
| 803 | |||
| 804 | /* ----------------------------------------------------- */ | ||
| 805 | |||
| 806 | /* DDR2 / AXI block phase alignment interrupt control */ | ||
| 807 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT 18 | ||
| 808 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) | ||
| 809 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) | ||
| 810 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) | ||
| 811 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) | ||
| 812 | #define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT) | ||
| 813 | |||
| 814 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT 17 | ||
| 815 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) | ||
| 816 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) | ||
| 817 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT) | ||
| 818 | |||
| 819 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT 16 | ||
| 820 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) | ||
| 821 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) | ||
| 822 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT) | ||
| 823 | #define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW | ||
| 824 | |||
| 825 | #define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT 15 | ||
| 826 | #define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) | ||
| 827 | #define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) | ||
| 828 | #define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT) | ||
| 829 | #define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301 | ||
| 830 | |||
| 831 | /* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */ | ||
| 832 | /* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */ | ||
| 833 | /* controller. If 2 chips selects are being used, then software control must be enabled. */ | ||
| 834 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD (1 << 14) | ||
| 835 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE (1 << 13) | ||
| 836 | |||
| 837 | /* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */ | ||
| 838 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12) | ||
| 839 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11) | ||
| 840 | #define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10) | ||
| 841 | |||
| 842 | /* Chip select count */ | ||
| 843 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT 9 | ||
| 844 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) | ||
| 845 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1 (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) | ||
| 846 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT) | ||
| 847 | |||
| 848 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT 8 | ||
| 849 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT) | ||
| 850 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT) | ||
| 851 | |||
| 852 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT 7 | ||
| 853 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT) | ||
| 854 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT) | ||
| 855 | |||
| 856 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT 6 | ||
| 857 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT) | ||
| 858 | #define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT) | ||
| 859 | |||
| 860 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT 0 | ||
| 861 | #define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT) | ||
| 862 | |||
| 863 | /* ----------------------------------------------------- */ | ||
| 864 | #define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT 0 | ||
| 865 | #define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT) | ||
| 866 | |||
| 867 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 868 | |||
| 869 | #ifdef __cplusplus | ||
| 870 | } /* end extern "C" */ | ||
| 871 | #endif | ||
| 872 | #endif /* DDRC_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h new file mode 100644 index 000000000000..375066ad0186 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h | |||
| @@ -0,0 +1,145 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dmacHw_priv.h | ||
| 18 | * | ||
| 19 | * @brief Private Definitions for low level DMA driver | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | |||
| 24 | #ifndef _DMACHW_PRIV_H | ||
| 25 | #define _DMACHW_PRIV_H | ||
| 26 | |||
| 27 | #include <csp/stdint.h> | ||
| 28 | |||
| 29 | /* Data type for DMA Link List Item */ | ||
| 30 | typedef struct { | ||
| 31 | uint32_t sar; /* Source Adress Register. | ||
| 32 | Address must be aligned to CTLx.SRC_TR_WIDTH. */ | ||
| 33 | uint32_t dar; /* Destination Address Register. | ||
| 34 | Address must be aligned to CTLx.DST_TR_WIDTH. */ | ||
| 35 | uint32_t llpPhy; /* LLP contains the physical address of the next descriptor for block chaining using linked lists. | ||
| 36 | Address MUST be aligned to a 32-bit boundary. */ | ||
| 37 | dmacHw_REG64_t ctl; /* Control Register. 64 bits */ | ||
| 38 | uint32_t sstat; /* Source Status Register */ | ||
| 39 | uint32_t dstat; /* Destination Status Register */ | ||
| 40 | uint32_t devCtl; /* Device specific control information */ | ||
| 41 | uint32_t llp; /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */ | ||
| 42 | } dmacHw_DESC_t; | ||
| 43 | |||
| 44 | /* | ||
| 45 | * Descriptor ring pointers | ||
| 46 | */ | ||
| 47 | typedef struct { | ||
| 48 | int num; /* Number of link items */ | ||
| 49 | dmacHw_DESC_t *pHead; /* Head of descriptor ring (for writing) */ | ||
| 50 | dmacHw_DESC_t *pTail; /* Tail of descriptor ring (for reading) */ | ||
| 51 | dmacHw_DESC_t *pProg; /* Descriptor to program the channel (for programming the channel register) */ | ||
| 52 | dmacHw_DESC_t *pEnd; /* End of current descriptor chain */ | ||
| 53 | dmacHw_DESC_t *pFree; /* Descriptor to free memory (freeing dynamic memory) */ | ||
| 54 | uint32_t virt2PhyOffset; /* Virtual to physical address offset for the descriptor ring */ | ||
| 55 | } dmacHw_DESC_RING_t; | ||
| 56 | |||
| 57 | /* | ||
| 58 | * DMA channel control block | ||
| 59 | */ | ||
| 60 | typedef struct { | ||
| 61 | uint32_t module; /* DMA controller module (0-1) */ | ||
| 62 | uint32_t channel; /* DMA channel (0-7) */ | ||
| 63 | volatile uint32_t varDataStarted; /* Flag indicating variable data channel is enabled */ | ||
| 64 | volatile uint32_t descUpdated; /* Flag to indicate descriptor update is complete */ | ||
| 65 | void *userData; /* Channel specifc user data */ | ||
| 66 | } dmacHw_CBLK_t; | ||
| 67 | |||
| 68 | #define dmacHw_ASSERT(a) if (!(a)) while (1) | ||
| 69 | #define dmacHw_MAX_CHANNEL_COUNT 16 | ||
| 70 | #define dmacHw_FREE_USER_MEMORY 0xFFFFFFFF | ||
| 71 | #define dmacHw_DESC_FREE dmacHw_REG_CTL_DONE | ||
| 72 | #define dmacHw_DESC_INIT ((dmacHw_DESC_t *) 0xFFFFFFFF) | ||
| 73 | #define dmacHw_MAX_BLOCKSIZE 4064 | ||
| 74 | #define dmacHw_GET_DESC_RING(addr) (dmacHw_DESC_RING_t *)(addr) | ||
| 75 | #define dmacHw_ADDRESS_MASK(byte) ((byte) - 1) | ||
| 76 | #define dmacHw_NEXT_DESC(rp, dp) ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp) | ||
| 77 | #define dmacHw_HANDLE_TO_CBLK(handle) ((dmacHw_CBLK_t *) (handle)) | ||
| 78 | #define dmacHw_CBLK_TO_HANDLE(cblkp) ((dmacHw_HANDLE_t) (cblkp)) | ||
| 79 | #define dmacHw_DST_IS_MEMORY(tt) (((tt) == dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0 | ||
| 80 | |||
| 81 | /****************************************************************************/ | ||
| 82 | /** | ||
| 83 | * @brief Get next available transaction width | ||
| 84 | * | ||
| 85 | * | ||
| 86 | * @return On sucess : Next avail able transaction width | ||
| 87 | * On failure : dmacHw_TRANSACTION_WIDTH_8 | ||
| 88 | * | ||
| 89 | * @note | ||
| 90 | * None | ||
| 91 | */ | ||
| 92 | /****************************************************************************/ | ||
| 93 | static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Current transaction width */ | ||
| 94 | ) { | ||
| 95 | if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) { | ||
| 96 | return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) - | ||
| 97 | 1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT; | ||
| 98 | } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) { | ||
| 99 | return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) - | ||
| 100 | 1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT; | ||
| 101 | } | ||
| 102 | |||
| 103 | /* Default return */ | ||
| 104 | return dmacHw_SRC_TRANSACTION_WIDTH_8; | ||
| 105 | } | ||
| 106 | |||
| 107 | /****************************************************************************/ | ||
| 108 | /** | ||
| 109 | * @brief Get number of bytes per transaction | ||
| 110 | * | ||
| 111 | * @return Number of bytes per transaction | ||
| 112 | * | ||
| 113 | * | ||
| 114 | * @note | ||
| 115 | * None | ||
| 116 | */ | ||
| 117 | /****************************************************************************/ | ||
| 118 | static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw /* [ IN ] Transaction width */ | ||
| 119 | ) { | ||
| 120 | int width = 1; | ||
| 121 | switch (tw) { | ||
| 122 | case dmacHw_SRC_TRANSACTION_WIDTH_8: | ||
| 123 | width = 1; | ||
| 124 | break; | ||
| 125 | case dmacHw_SRC_TRANSACTION_WIDTH_16: | ||
| 126 | case dmacHw_DST_TRANSACTION_WIDTH_16: | ||
| 127 | width = 2; | ||
| 128 | break; | ||
| 129 | case dmacHw_SRC_TRANSACTION_WIDTH_32: | ||
| 130 | case dmacHw_DST_TRANSACTION_WIDTH_32: | ||
| 131 | width = 4; | ||
| 132 | break; | ||
| 133 | case dmacHw_SRC_TRANSACTION_WIDTH_64: | ||
| 134 | case dmacHw_DST_TRANSACTION_WIDTH_64: | ||
| 135 | width = 8; | ||
| 136 | break; | ||
| 137 | default: | ||
| 138 | dmacHw_ASSERT(0); | ||
| 139 | } | ||
| 140 | |||
| 141 | /* Default transaction width */ | ||
| 142 | return width; | ||
| 143 | } | ||
| 144 | |||
| 145 | #endif /* _DMACHW_PRIV_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h new file mode 100644 index 000000000000..891cea87e333 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h | |||
| @@ -0,0 +1,406 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dmacHw_reg.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for low level DMA registers | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | |||
| 24 | #ifndef _DMACHW_REG_H | ||
| 25 | #define _DMACHW_REG_H | ||
| 26 | |||
| 27 | #include <csp/stdint.h> | ||
| 28 | #include <mach/csp/mm_io.h> | ||
| 29 | |||
| 30 | /* Data type for 64 bit little endian register */ | ||
| 31 | typedef struct { | ||
| 32 | volatile uint32_t lo; /* Lower 32 bit in little endian mode */ | ||
| 33 | volatile uint32_t hi; /* Upper 32 bit in little endian mode */ | ||
| 34 | } dmacHw_REG64_t; | ||
| 35 | |||
| 36 | /* Data type representing DMA channel registers */ | ||
| 37 | typedef struct { | ||
| 38 | dmacHw_REG64_t ChannelSar; /* Source Adress Register. 64 bits (upper 32 bits are reserved) | ||
| 39 | Address must be aligned to CTLx.SRC_TR_WIDTH. | ||
| 40 | */ | ||
| 41 | dmacHw_REG64_t ChannelDar; /* Destination Address Register.64 bits (upper 32 bits are reserved) | ||
| 42 | Address must be aligned to CTLx.DST_TR_WIDTH. | ||
| 43 | */ | ||
| 44 | dmacHw_REG64_t ChannelLlp; /* Link List Pointer.64 bits (upper 32 bits are reserved) | ||
| 45 | LLP contains the pointer to the next LLI for block chaining using linked lists. | ||
| 46 | If LLPis set to 0x0, then transfers using linked lists are not enabled. | ||
| 47 | Address MUST be aligned to a 32-bit boundary. | ||
| 48 | */ | ||
| 49 | dmacHw_REG64_t ChannelCtl; /* Control Register. 64 bits */ | ||
| 50 | dmacHw_REG64_t ChannelSstat; /* Source Status Register */ | ||
| 51 | dmacHw_REG64_t ChannelDstat; /* Destination Status Register */ | ||
| 52 | dmacHw_REG64_t ChannelSstatAddr; /* Source Status Address Register */ | ||
| 53 | dmacHw_REG64_t ChannelDstatAddr; /* Destination Status Address Register */ | ||
| 54 | dmacHw_REG64_t ChannelConfig; /* Channel Configuration Register */ | ||
| 55 | dmacHw_REG64_t SrcGather; /* Source gather register */ | ||
| 56 | dmacHw_REG64_t DstScatter; /* Destination scatter register */ | ||
| 57 | } dmacHw_CH_REG_t; | ||
| 58 | |||
| 59 | /* Data type for RAW interrupt status registers */ | ||
| 60 | typedef struct { | ||
| 61 | dmacHw_REG64_t RawTfr; /* Raw Status for IntTfr Interrupt */ | ||
| 62 | dmacHw_REG64_t RawBlock; /* Raw Status for IntBlock Interrupt */ | ||
| 63 | dmacHw_REG64_t RawSrcTran; /* Raw Status for IntSrcTran Interrupt */ | ||
| 64 | dmacHw_REG64_t RawDstTran; /* Raw Status for IntDstTran Interrupt */ | ||
| 65 | dmacHw_REG64_t RawErr; /* Raw Status for IntErr Interrupt */ | ||
| 66 | } dmacHw_INT_RAW_t; | ||
| 67 | |||
| 68 | /* Data type for interrupt status registers */ | ||
| 69 | typedef struct { | ||
| 70 | dmacHw_REG64_t StatusTfr; /* Status for IntTfr Interrupt */ | ||
| 71 | dmacHw_REG64_t StatusBlock; /* Status for IntBlock Interrupt */ | ||
| 72 | dmacHw_REG64_t StatusSrcTran; /* Status for IntSrcTran Interrupt */ | ||
| 73 | dmacHw_REG64_t StatusDstTran; /* Status for IntDstTran Interrupt */ | ||
| 74 | dmacHw_REG64_t StatusErr; /* Status for IntErr Interrupt */ | ||
| 75 | } dmacHw_INT_STATUS_t; | ||
| 76 | |||
| 77 | /* Data type for interrupt mask registers*/ | ||
| 78 | typedef struct { | ||
| 79 | dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */ | ||
| 80 | dmacHw_REG64_t MaskBlock; /* Mask for IntBlock Interrupt */ | ||
| 81 | dmacHw_REG64_t MaskSrcTran; /* Mask for IntSrcTran Interrupt */ | ||
| 82 | dmacHw_REG64_t MaskDstTran; /* Mask for IntDstTran Interrupt */ | ||
| 83 | dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */ | ||
| 84 | } dmacHw_INT_MASK_t; | ||
| 85 | |||
| 86 | /* Data type for interrupt clear registers */ | ||
| 87 | typedef struct { | ||
| 88 | dmacHw_REG64_t ClearTfr; /* Clear for IntTfr Interrupt */ | ||
| 89 | dmacHw_REG64_t ClearBlock; /* Clear for IntBlock Interrupt */ | ||
| 90 | dmacHw_REG64_t ClearSrcTran; /* Clear for IntSrcTran Interrupt */ | ||
| 91 | dmacHw_REG64_t ClearDstTran; /* Clear for IntDstTran Interrupt */ | ||
| 92 | dmacHw_REG64_t ClearErr; /* Clear for IntErr Interrupt */ | ||
| 93 | dmacHw_REG64_t StatusInt; /* Status for each interrupt type */ | ||
| 94 | } dmacHw_INT_CLEAR_t; | ||
| 95 | |||
| 96 | /* Data type for software handshaking registers */ | ||
| 97 | typedef struct { | ||
| 98 | dmacHw_REG64_t ReqSrcReg; /* Source Software Transaction Request Register */ | ||
| 99 | dmacHw_REG64_t ReqDstReg; /* Destination Software Transaction Request Register */ | ||
| 100 | dmacHw_REG64_t SglReqSrcReg; /* Single Source Transaction Request Register */ | ||
| 101 | dmacHw_REG64_t SglReqDstReg; /* Single Destination Transaction Request Register */ | ||
| 102 | dmacHw_REG64_t LstSrcReg; /* Last Source Transaction Request Register */ | ||
| 103 | dmacHw_REG64_t LstDstReg; /* Last Destination Transaction Request Register */ | ||
| 104 | } dmacHw_SW_HANDSHAKE_t; | ||
| 105 | |||
| 106 | /* Data type for misc. registers */ | ||
| 107 | typedef struct { | ||
| 108 | dmacHw_REG64_t DmaCfgReg; /* DMA Configuration Register */ | ||
| 109 | dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */ | ||
| 110 | dmacHw_REG64_t DmaIdReg; /* DMA ID Register */ | ||
| 111 | dmacHw_REG64_t DmaTestReg; /* DMA Test Register */ | ||
| 112 | dmacHw_REG64_t Reserved0; /* Reserved */ | ||
| 113 | dmacHw_REG64_t Reserved1; /* Reserved */ | ||
| 114 | dmacHw_REG64_t CompParm6; /* Component Parameter 6 */ | ||
| 115 | dmacHw_REG64_t CompParm5; /* Component Parameter 5 */ | ||
| 116 | dmacHw_REG64_t CompParm4; /* Component Parameter 4 */ | ||
| 117 | dmacHw_REG64_t CompParm3; /* Component Parameter 3 */ | ||
| 118 | dmacHw_REG64_t CompParm2; /* Component Parameter 2 */ | ||
| 119 | dmacHw_REG64_t CompParm1; /* Component Parameter 1 */ | ||
| 120 | dmacHw_REG64_t CompId; /* Compoent ID */ | ||
| 121 | } dmacHw_MISC_t; | ||
| 122 | |||
| 123 | /* Base registers */ | ||
| 124 | #define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */ | ||
| 125 | #define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */ | ||
| 126 | |||
| 127 | extern uint32_t dmaChannelCount_0; | ||
| 128 | extern uint32_t dmaChannelCount_1; | ||
| 129 | |||
| 130 | /* Define channel specific registers */ | ||
| 131 | #define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t)))) | ||
| 132 | |||
| 133 | /* Raw interrupt status registers */ | ||
| 134 | #define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0))) | ||
| 135 | #define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo) | ||
| 136 | #define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo) | ||
| 137 | #define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo) | ||
| 138 | #define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo) | ||
| 139 | #define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo) | ||
| 140 | |||
| 141 | /* Interrupt status registers */ | ||
| 142 | #define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t))) | ||
| 143 | #define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo) | ||
| 144 | #define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo) | ||
| 145 | #define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo) | ||
| 146 | #define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo) | ||
| 147 | #define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo) | ||
| 148 | |||
| 149 | /* Interrupt status registers */ | ||
| 150 | #define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t))) | ||
| 151 | #define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo) | ||
| 152 | #define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo) | ||
| 153 | #define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo) | ||
| 154 | #define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo) | ||
| 155 | #define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo) | ||
| 156 | |||
| 157 | /* Interrupt clear registers */ | ||
| 158 | #define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t))) | ||
| 159 | #define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo) | ||
| 160 | #define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo) | ||
| 161 | #define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo) | ||
| 162 | #define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo) | ||
| 163 | #define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo) | ||
| 164 | #define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo) | ||
| 165 | |||
| 166 | /* Software handshaking registers */ | ||
| 167 | #define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t))) | ||
| 168 | #define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo) | ||
| 169 | #define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo) | ||
| 170 | #define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo) | ||
| 171 | #define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo) | ||
| 172 | #define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo) | ||
| 173 | #define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo) | ||
| 174 | |||
| 175 | /* Miscellaneous registers */ | ||
| 176 | #define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t))) | ||
| 177 | #define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo) | ||
| 178 | #define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo) | ||
| 179 | #define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo) | ||
| 180 | #define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo) | ||
| 181 | #define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo) | ||
| 182 | #define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi) | ||
| 183 | #define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo) | ||
| 184 | #define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi) | ||
| 185 | #define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo) | ||
| 186 | #define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi) | ||
| 187 | #define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo) | ||
| 188 | #define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi) | ||
| 189 | #define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo) | ||
| 190 | #define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi) | ||
| 191 | #define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo) | ||
| 192 | #define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi) | ||
| 193 | |||
| 194 | /* Channel control registers */ | ||
| 195 | #define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo) | ||
| 196 | #define dmacHw_REG_DAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo) | ||
| 197 | #define dmacHw_REG_LLP(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo) | ||
| 198 | |||
| 199 | #define dmacHw_REG_CTL_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo) | ||
| 200 | #define dmacHw_REG_CTL_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi) | ||
| 201 | |||
| 202 | #define dmacHw_REG_SSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo) | ||
| 203 | #define dmacHw_REG_DSTAT(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo) | ||
| 204 | #define dmacHw_REG_SSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo) | ||
| 205 | #define dmacHw_REG_DSTATAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo) | ||
| 206 | |||
| 207 | #define dmacHw_REG_CFG_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo) | ||
| 208 | #define dmacHw_REG_CFG_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi) | ||
| 209 | |||
| 210 | #define dmacHw_REG_SGR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo) | ||
| 211 | #define dmacHw_REG_SGR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi) | ||
| 212 | |||
| 213 | #define dmacHw_REG_DSR_LO(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo) | ||
| 214 | #define dmacHw_REG_DSR_HI(module, chan) (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi) | ||
| 215 | |||
| 216 | #define INT_STATUS_MASK(channel) (0x00000001 << (channel)) | ||
| 217 | #define CHANNEL_BUSY(mod, channel) (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel))) | ||
| 218 | |||
| 219 | /* Bit mask for REG_DMACx_CTL_LO */ | ||
| 220 | |||
| 221 | #define dmacHw_REG_CTL_INT_EN 0x00000001 /* Channel interrupt enable */ | ||
| 222 | |||
| 223 | #define dmacHw_REG_CTL_DST_TR_WIDTH_MASK 0x0000000E /* Destination transaction width mask */ | ||
| 224 | #define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT 1 | ||
| 225 | #define dmacHw_REG_CTL_DST_TR_WIDTH_8 0x00000000 /* Destination transaction width 8 bit */ | ||
| 226 | #define dmacHw_REG_CTL_DST_TR_WIDTH_16 0x00000002 /* Destination transaction width 16 bit */ | ||
| 227 | #define dmacHw_REG_CTL_DST_TR_WIDTH_32 0x00000004 /* Destination transaction width 32 bit */ | ||
| 228 | #define dmacHw_REG_CTL_DST_TR_WIDTH_64 0x00000006 /* Destination transaction width 64 bit */ | ||
| 229 | |||
| 230 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK 0x00000070 /* Source transaction width mask */ | ||
| 231 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT 4 | ||
| 232 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_8 0x00000000 /* Source transaction width 8 bit */ | ||
| 233 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_16 0x00000010 /* Source transaction width 16 bit */ | ||
| 234 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_32 0x00000020 /* Source transaction width 32 bit */ | ||
| 235 | #define dmacHw_REG_CTL_SRC_TR_WIDTH_64 0x00000030 /* Source transaction width 64 bit */ | ||
| 236 | |||
| 237 | #define dmacHw_REG_CTL_DS_ENABLE 0x00040000 /* Destination scatter enable */ | ||
| 238 | #define dmacHw_REG_CTL_SG_ENABLE 0x00020000 /* Source gather enable */ | ||
| 239 | |||
| 240 | #define dmacHw_REG_CTL_DINC_MASK 0x00000180 /* Destination address inc/dec mask */ | ||
| 241 | #define dmacHw_REG_CTL_DINC_INC 0x00000000 /* Destination address increment */ | ||
| 242 | #define dmacHw_REG_CTL_DINC_DEC 0x00000080 /* Destination address decrement */ | ||
| 243 | #define dmacHw_REG_CTL_DINC_NC 0x00000100 /* Destination address no change */ | ||
| 244 | |||
| 245 | #define dmacHw_REG_CTL_SINC_MASK 0x00000600 /* Source address inc/dec mask */ | ||
| 246 | #define dmacHw_REG_CTL_SINC_INC 0x00000000 /* Source address increment */ | ||
| 247 | #define dmacHw_REG_CTL_SINC_DEC 0x00000200 /* Source address decrement */ | ||
| 248 | #define dmacHw_REG_CTL_SINC_NC 0x00000400 /* Source address no change */ | ||
| 249 | |||
| 250 | #define dmacHw_REG_CTL_DST_MSIZE_MASK 0x00003800 /* Destination burst transaction length */ | ||
| 251 | #define dmacHw_REG_CTL_DST_MSIZE_0 0x00000000 /* No Destination burst */ | ||
| 252 | #define dmacHw_REG_CTL_DST_MSIZE_4 0x00000800 /* Destination burst transaction length 4 */ | ||
| 253 | #define dmacHw_REG_CTL_DST_MSIZE_8 0x00001000 /* Destination burst transaction length 8 */ | ||
| 254 | #define dmacHw_REG_CTL_DST_MSIZE_16 0x00001800 /* Destination burst transaction length 16 */ | ||
| 255 | |||
| 256 | #define dmacHw_REG_CTL_SRC_MSIZE_MASK 0x0001C000 /* Source burst transaction length */ | ||
| 257 | #define dmacHw_REG_CTL_SRC_MSIZE_0 0x00000000 /* No Source burst */ | ||
| 258 | #define dmacHw_REG_CTL_SRC_MSIZE_4 0x00004000 /* Source burst transaction length 4 */ | ||
| 259 | #define dmacHw_REG_CTL_SRC_MSIZE_8 0x00008000 /* Source burst transaction length 8 */ | ||
| 260 | #define dmacHw_REG_CTL_SRC_MSIZE_16 0x0000C000 /* Source burst transaction length 16 */ | ||
| 261 | |||
| 262 | #define dmacHw_REG_CTL_TTFC_MASK 0x00700000 /* Transfer type and flow controller */ | ||
| 263 | #define dmacHw_REG_CTL_TTFC_MM_DMAC 0x00000000 /* Memory to Memory with DMAC as flow controller */ | ||
| 264 | #define dmacHw_REG_CTL_TTFC_MP_DMAC 0x00100000 /* Memory to Peripheral with DMAC as flow controller */ | ||
| 265 | #define dmacHw_REG_CTL_TTFC_PM_DMAC 0x00200000 /* Peripheral to Memory with DMAC as flow controller */ | ||
| 266 | #define dmacHw_REG_CTL_TTFC_PP_DMAC 0x00300000 /* Peripheral to Peripheral with DMAC as flow controller */ | ||
| 267 | #define dmacHw_REG_CTL_TTFC_PM_PERI 0x00400000 /* Peripheral to Memory with Peripheral as flow controller */ | ||
| 268 | #define dmacHw_REG_CTL_TTFC_PP_SPERI 0x00500000 /* Peripheral to Peripheral with Source Peripheral as flow controller */ | ||
| 269 | #define dmacHw_REG_CTL_TTFC_MP_PERI 0x00600000 /* Memory to Peripheral with Peripheral as flow controller */ | ||
| 270 | #define dmacHw_REG_CTL_TTFC_PP_DPERI 0x00700000 /* Peripheral to Peripheral with Destination Peripheral as flow controller */ | ||
| 271 | |||
| 272 | #define dmacHw_REG_CTL_DMS_MASK 0x01800000 /* Destination AHB master interface */ | ||
| 273 | #define dmacHw_REG_CTL_DMS_1 0x00000000 /* Destination AHB master interface 1 */ | ||
| 274 | #define dmacHw_REG_CTL_DMS_2 0x00800000 /* Destination AHB master interface 2 */ | ||
| 275 | |||
| 276 | #define dmacHw_REG_CTL_SMS_MASK 0x06000000 /* Source AHB master interface */ | ||
| 277 | #define dmacHw_REG_CTL_SMS_1 0x00000000 /* Source AHB master interface 1 */ | ||
| 278 | #define dmacHw_REG_CTL_SMS_2 0x02000000 /* Source AHB master interface 2 */ | ||
| 279 | |||
| 280 | #define dmacHw_REG_CTL_LLP_DST_EN 0x08000000 /* Block chaining enable for destination side */ | ||
| 281 | #define dmacHw_REG_CTL_LLP_SRC_EN 0x10000000 /* Block chaining enable for source side */ | ||
| 282 | |||
| 283 | /* Bit mask for REG_DMACx_CTL_HI */ | ||
| 284 | #define dmacHw_REG_CTL_BLOCK_TS_MASK 0x00000FFF /* Block transfer size */ | ||
| 285 | #define dmacHw_REG_CTL_DONE 0x00001000 /* Block trasnfer done */ | ||
| 286 | |||
| 287 | /* Bit mask for REG_DMACx_CFG_LO */ | ||
| 288 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT 5 /* Channel priority shift */ | ||
| 289 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK 0x000000E0 /* Channel priority mask */ | ||
| 290 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_0 0x00000000 /* Channel priority 0 */ | ||
| 291 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_1 0x00000020 /* Channel priority 1 */ | ||
| 292 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_2 0x00000040 /* Channel priority 2 */ | ||
| 293 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_3 0x00000060 /* Channel priority 3 */ | ||
| 294 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_4 0x00000080 /* Channel priority 4 */ | ||
| 295 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_5 0x000000A0 /* Channel priority 5 */ | ||
| 296 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_6 0x000000C0 /* Channel priority 6 */ | ||
| 297 | #define dmacHw_REG_CFG_LO_CH_PRIORITY_7 0x000000E0 /* Channel priority 7 */ | ||
| 298 | |||
| 299 | #define dmacHw_REG_CFG_LO_CH_SUSPEND 0x00000100 /* Channel suspend */ | ||
| 300 | #define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY 0x00000200 /* Channel FIFO empty */ | ||
| 301 | #define dmacHw_REG_CFG_LO_DST_CH_SW_HS 0x00000400 /* Destination channel SW handshaking */ | ||
| 302 | #define dmacHw_REG_CFG_LO_SRC_CH_SW_HS 0x00000800 /* Source channel SW handshaking */ | ||
| 303 | |||
| 304 | #define dmacHw_REG_CFG_LO_CH_LOCK_MASK 0x00003000 /* Channel locking mask */ | ||
| 305 | #define dmacHw_REG_CFG_LO_CH_LOCK_DMA 0x00000000 /* Channel lock over the entire DMA transfer operation */ | ||
| 306 | #define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK 0x00001000 /* Channel lock over the block transfer operation */ | ||
| 307 | #define dmacHw_REG_CFG_LO_CH_LOCK_TRANS 0x00002000 /* Channel lock over the transaction */ | ||
| 308 | #define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE 0x00010000 /* Channel lock enable */ | ||
| 309 | |||
| 310 | #define dmacHw_REG_CFG_LO_BUS_LOCK_MASK 0x0000C000 /* Bus locking mask */ | ||
| 311 | #define dmacHw_REG_CFG_LO_BUS_LOCK_DMA 0x00000000 /* Bus lock over the entire DMA transfer operation */ | ||
| 312 | #define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK 0x00004000 /* Bus lock over the block transfer operation */ | ||
| 313 | #define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS 0x00008000 /* Bus lock over the transaction */ | ||
| 314 | #define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE 0x00020000 /* Bus lock enable */ | ||
| 315 | |||
| 316 | #define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW 0x00040000 /* Destination channel handshaking signal polarity low */ | ||
| 317 | #define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW 0x00080000 /* Source channel handshaking signal polarity low */ | ||
| 318 | |||
| 319 | #define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK 0x3FF00000 /* Maximum AMBA burst length */ | ||
| 320 | |||
| 321 | #define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC 0x40000000 /* Source address auto reload */ | ||
| 322 | #define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST 0x80000000 /* Destination address auto reload */ | ||
| 323 | |||
| 324 | /* Bit mask for REG_DMACx_CFG_HI */ | ||
| 325 | #define dmacHw_REG_CFG_HI_FC_DST_READY 0x00000001 /* Source transaction request is serviced when destination is ready */ | ||
| 326 | #define dmacHw_REG_CFG_HI_FIFO_ENOUGH 0x00000002 /* Initiate burst transaction when enough data in available in FIFO */ | ||
| 327 | |||
| 328 | #define dmacHw_REG_CFG_HI_AHB_HPROT_MASK 0x0000001C /* AHB protection mask */ | ||
| 329 | #define dmacHw_REG_CFG_HI_AHB_HPROT_1 0x00000004 /* AHB protection 1 */ | ||
| 330 | #define dmacHw_REG_CFG_HI_AHB_HPROT_2 0x00000008 /* AHB protection 2 */ | ||
| 331 | #define dmacHw_REG_CFG_HI_AHB_HPROT_3 0x00000010 /* AHB protection 3 */ | ||
| 332 | |||
| 333 | #define dmacHw_REG_CFG_HI_UPDATE_DST_STAT 0x00000020 /* Destination status update enable */ | ||
| 334 | #define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT 0x00000040 /* Source status update enable */ | ||
| 335 | |||
| 336 | #define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK 0x00000780 /* Source peripheral hardware interface mask */ | ||
| 337 | #define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK 0x00007800 /* Destination peripheral hardware interface mask */ | ||
| 338 | |||
| 339 | /* DMA Configuration Parameters */ | ||
| 340 | #define dmacHw_REG_COMP_PARAM_NUM_CHANNELS 0x00000700 /* Number of channels */ | ||
| 341 | #define dmacHw_REG_COMP_PARAM_NUM_INTERFACE 0x00001800 /* Number of master interface */ | ||
| 342 | #define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE 0x0000000f /* Maximum brust size */ | ||
| 343 | #define dmacHw_REG_COMP_PARAM_DATA_WIDTH 0x00006000 /* Data transfer width */ | ||
| 344 | |||
| 345 | /* Define GET/SET macros to program the registers */ | ||
| 346 | #define dmacHw_SET_SAR(module, channel, addr) (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr)) | ||
| 347 | #define dmacHw_SET_DAR(module, channel, addr) (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr)) | ||
| 348 | #define dmacHw_SET_LLP(module, channel, ptr) (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr)) | ||
| 349 | |||
| 350 | #define dmacHw_GET_SSTAT(module, channel) (dmacHw_REG_SSTAT((module), (channel))) | ||
| 351 | #define dmacHw_GET_DSTAT(module, channel) (dmacHw_REG_DSTAT((module), (channel))) | ||
| 352 | |||
| 353 | #define dmacHw_SET_SSTATAR(module, channel, addr) (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr)) | ||
| 354 | #define dmacHw_SET_DSTATAR(module, channel, addr) (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr)) | ||
| 355 | |||
| 356 | #define dmacHw_SET_CONTROL_LO(module, channel, ctl) (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl)) | ||
| 357 | #define dmacHw_RESET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel)) = 0) | ||
| 358 | #define dmacHw_GET_CONTROL_LO(module, channel) (dmacHw_REG_CTL_LO((module), (channel))) | ||
| 359 | |||
| 360 | #define dmacHw_SET_CONTROL_HI(module, channel, ctl) (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl)) | ||
| 361 | #define dmacHw_RESET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) = 0) | ||
| 362 | #define dmacHw_GET_CONTROL_HI(module, channel) (dmacHw_REG_CTL_HI((module), (channel))) | ||
| 363 | |||
| 364 | #define dmacHw_GET_BLOCK_SIZE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK) | ||
| 365 | #define dmacHw_DMA_COMPLETE(module, channel) (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE) | ||
| 366 | |||
| 367 | #define dmacHw_SET_CONFIG_LO(module, channel, cfg) (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg)) | ||
| 368 | #define dmacHw_RESET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel)) = 0) | ||
| 369 | #define dmacHw_GET_CONFIG_LO(module, channel) (dmacHw_REG_CFG_LO((module), (channel))) | ||
| 370 | #define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | ||
| 371 | #define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio)) | ||
| 372 | #define dmacHw_SET_AHB_HPROT(module, channel, protect) (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect)) | ||
| 373 | |||
| 374 | #define dmacHw_SET_CONFIG_HI(module, channel, cfg) (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg)) | ||
| 375 | #define dmacHw_RESET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel)) = 0) | ||
| 376 | #define dmacHw_GET_CONFIG_HI(module, channel) (dmacHw_REG_CFG_HI((module), (channel))) | ||
| 377 | #define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | ||
| 378 | #define dmacHw_SRC_PERI_INTF(intf) (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK) | ||
| 379 | #define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | ||
| 380 | #define dmacHw_DST_PERI_INTF(intf) (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK) | ||
| 381 | |||
| 382 | #define dmacHw_DMA_START(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) | ||
| 383 | #define dmacHw_DMA_STOP(module, channel) (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8))) | ||
| 384 | #define dmacHw_DMA_ENABLE(module) (dmacHw_REG_MISC_CFG((module)) = 1) | ||
| 385 | #define dmacHw_DMA_DISABLE(module) (dmacHw_REG_MISC_CFG((module)) = 0) | ||
| 386 | |||
| 387 | #define dmacHw_TRAN_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) | ||
| 388 | #define dmacHw_BLOCK_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) | ||
| 389 | #define dmacHw_ERROR_INT_ENABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel))) | ||
| 390 | |||
| 391 | #define dmacHw_TRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8))) | ||
| 392 | #define dmacHw_BLOCK_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8))) | ||
| 393 | #define dmacHw_ERROR_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8))) | ||
| 394 | #define dmacHw_STRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8))) | ||
| 395 | #define dmacHw_DTRAN_INT_DISABLE(module, channel) (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8))) | ||
| 396 | |||
| 397 | #define dmacHw_TRAN_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel))) | ||
| 398 | #define dmacHw_BLOCK_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel))) | ||
| 399 | #define dmacHw_ERROR_INT_CLEAR(module, channel) (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel))) | ||
| 400 | |||
| 401 | #define dmacHw_GET_NUM_CHANNEL(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1) | ||
| 402 | #define dmacHw_GET_NUM_INTERFACE(module) (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1) | ||
| 403 | #define dmacHw_GET_MAX_BLOCK_SIZE(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE) | ||
| 404 | #define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13) | ||
| 405 | |||
| 406 | #endif /* _DMACHW_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h new file mode 100644 index 000000000000..cfa91bed9d34 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | |||
| 16 | #ifndef CSP_HW_CFG_H | ||
| 17 | #define CSP_HW_CFG_H | ||
| 18 | |||
| 19 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 20 | |||
| 21 | #include <cfg_global.h> | ||
| 22 | #include <mach/csp/cap_inline.h> | ||
| 23 | |||
| 24 | #if defined(__KERNEL__) | ||
| 25 | #include <mach/memory_settings.h> | ||
| 26 | #else | ||
| 27 | #include <hw_cfg.h> | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* Some items that can be defined externally, but will be set to default values */ | ||
| 31 | /* if they are not defined. */ | ||
| 32 | /* HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE Default undefined and SS is enabled. */ | ||
| 33 | /* HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ | ||
| 34 | /* HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ | ||
| 35 | /* HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ | ||
| 36 | /* HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ | ||
| 37 | /* HW_CFG_SDRAM_ADDR_BRC Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */ | ||
| 38 | /* HW_CFG_SDRAM_CLK_ASYNC Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */ | ||
| 39 | |||
| 40 | #if defined(CFG_GLOBAL_CHIP) | ||
| 41 | #if (CFG_GLOBAL_CHIP == FPGA11107) | ||
| 42 | #define HW_CFG_BUS_CLK_HZ 5000000 | ||
| 43 | #define HW_CFG_DDR_CTLR_CLK_HZ 10000000 | ||
| 44 | #define HW_CFG_DDR_PHY_OMIT | ||
| 45 | #define HW_CFG_UART_CLK_HZ 7500000 | ||
| 46 | #else | ||
| 47 | #define HW_CFG_PLL_VCO_HZ 2000000000 | ||
| 48 | #define HW_CFG_PLL2_VCO_HZ 1800000000 | ||
| 49 | #define HW_CFG_ARM_CLK_HZ CAP_HW_CFG_ARM_CLK_HZ | ||
| 50 | #define HW_CFG_BUS_CLK_HZ 166666666 | ||
| 51 | #define HW_CFG_DDR_CTLR_CLK_HZ 333333333 | ||
| 52 | #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) | ||
| 53 | #define HW_CFG_UART_CLK_HZ 142857142 | ||
| 54 | #define HW_CFG_VPM_CLK_HZ CAP_HW_CFG_VPM_CLK_HZ | ||
| 55 | #endif | ||
| 56 | #else | ||
| 57 | #define HW_CFG_PLL_VCO_HZ 1800000000 | ||
| 58 | #define HW_CFG_PLL2_VCO_HZ 1800000000 | ||
| 59 | #define HW_CFG_ARM_CLK_HZ 450000000 | ||
| 60 | #define HW_CFG_BUS_CLK_HZ 150000000 | ||
| 61 | #define HW_CFG_DDR_CTLR_CLK_HZ 300000000 | ||
| 62 | #define HW_CFG_DDR_PHY_CLK_HZ (2 * HW_CFG_DDR_CTLR_CLK_HZ) | ||
| 63 | #define HW_CFG_UART_CLK_HZ 150000000 | ||
| 64 | #define HW_CFG_VPM_CLK_HZ 300000000 | ||
| 65 | #endif | ||
| 66 | |||
| 67 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 68 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 69 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 70 | |||
| 71 | |||
| 72 | #endif /* CSP_HW_CFG_H */ | ||
| 73 | |||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h new file mode 100644 index 000000000000..e01fc4607c91 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h | |||
| @@ -0,0 +1,246 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file intcHw_reg.h | ||
| 18 | * | ||
| 19 | * @brief platform specific interrupt controller bit assignments | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * None | ||
| 23 | */ | ||
| 24 | /****************************************************************************/ | ||
| 25 | |||
| 26 | #ifndef _INTCHW_REG_H | ||
| 27 | #define _INTCHW_REG_H | ||
| 28 | |||
| 29 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 30 | #include <csp/stdint.h> | ||
| 31 | #include <csp/reg.h> | ||
| 32 | #include <mach/csp/mm_io.h> | ||
| 33 | |||
| 34 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 35 | |||
| 36 | #define INTCHW_NUM_IRQ_PER_INTC 32 /* Maximum number of interrupt controllers */ | ||
| 37 | #define INTCHW_NUM_INTC 3 | ||
| 38 | |||
| 39 | /* Defines for interrupt controllers. This simplifies and cleans up the function calls. */ | ||
| 40 | #define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0) | ||
| 41 | #define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1) | ||
| 42 | #define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC) | ||
| 43 | |||
| 44 | /* INTC0 - interrupt controller 0 */ | ||
| 45 | #define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */ | ||
| 46 | #define INTCHW_INTC0_CLCD_BITNUM 30 /* LCD Controller interrupt */ | ||
| 47 | #define INTCHW_INTC0_GE_BITNUM 29 /* Graphic engine interrupt */ | ||
| 48 | #define INTCHW_INTC0_APM_BITNUM 28 /* Audio process module interrupt */ | ||
| 49 | #define INTCHW_INTC0_ESW_BITNUM 27 /* Ethernet switch interrupt */ | ||
| 50 | #define INTCHW_INTC0_SPIH_BITNUM 26 /* SPI host interrupt */ | ||
| 51 | #define INTCHW_INTC0_TIMER3_BITNUM 25 /* Timer3 interrupt */ | ||
| 52 | #define INTCHW_INTC0_TIMER2_BITNUM 24 /* Timer2 interrupt */ | ||
| 53 | #define INTCHW_INTC0_TIMER1_BITNUM 23 /* Timer1 interrupt */ | ||
| 54 | #define INTCHW_INTC0_TIMER0_BITNUM 22 /* Timer0 interrupt */ | ||
| 55 | #define INTCHW_INTC0_SDIOH1_BITNUM 21 /* SDIO1 host interrupt */ | ||
| 56 | #define INTCHW_INTC0_SDIOH0_BITNUM 20 /* SDIO0 host interrupt */ | ||
| 57 | #define INTCHW_INTC0_USBD_BITNUM 19 /* USB device interrupt */ | ||
| 58 | #define INTCHW_INTC0_USBH1_BITNUM 18 /* USB1 host interrupt */ | ||
| 59 | #define INTCHW_INTC0_USBHD2_BITNUM 17 /* USB host2/device2 interrupt */ | ||
| 60 | #define INTCHW_INTC0_VPM_BITNUM 16 /* Voice process module interrupt */ | ||
| 61 | #define INTCHW_INTC0_DMA1C7_BITNUM 15 /* DMA1 channel 7 interrupt */ | ||
| 62 | #define INTCHW_INTC0_DMA1C6_BITNUM 14 /* DMA1 channel 6 interrupt */ | ||
| 63 | #define INTCHW_INTC0_DMA1C5_BITNUM 13 /* DMA1 channel 5 interrupt */ | ||
| 64 | #define INTCHW_INTC0_DMA1C4_BITNUM 12 /* DMA1 channel 4 interrupt */ | ||
| 65 | #define INTCHW_INTC0_DMA1C3_BITNUM 11 /* DMA1 channel 3 interrupt */ | ||
| 66 | #define INTCHW_INTC0_DMA1C2_BITNUM 10 /* DMA1 channel 2 interrupt */ | ||
| 67 | #define INTCHW_INTC0_DMA1C1_BITNUM 9 /* DMA1 channel 1 interrupt */ | ||
| 68 | #define INTCHW_INTC0_DMA1C0_BITNUM 8 /* DMA1 channel 0 interrupt */ | ||
| 69 | #define INTCHW_INTC0_DMA0C7_BITNUM 7 /* DMA0 channel 7 interrupt */ | ||
| 70 | #define INTCHW_INTC0_DMA0C6_BITNUM 6 /* DMA0 channel 6 interrupt */ | ||
| 71 | #define INTCHW_INTC0_DMA0C5_BITNUM 5 /* DMA0 channel 5 interrupt */ | ||
| 72 | #define INTCHW_INTC0_DMA0C4_BITNUM 4 /* DMA0 channel 4 interrupt */ | ||
| 73 | #define INTCHW_INTC0_DMA0C3_BITNUM 3 /* DMA0 channel 3 interrupt */ | ||
| 74 | #define INTCHW_INTC0_DMA0C2_BITNUM 2 /* DMA0 channel 2 interrupt */ | ||
| 75 | #define INTCHW_INTC0_DMA0C1_BITNUM 1 /* DMA0 channel 1 interrupt */ | ||
| 76 | #define INTCHW_INTC0_DMA0C0_BITNUM 0 /* DMA0 channel 0 interrupt */ | ||
| 77 | |||
| 78 | #define INTCHW_INTC0_PIF (1<<INTCHW_INTC0_PIF_BITNUM) | ||
| 79 | #define INTCHW_INTC0_CLCD (1<<INTCHW_INTC0_CLCD_BITNUM) | ||
| 80 | #define INTCHW_INTC0_GE (1<<INTCHW_INTC0_GE_BITNUM) | ||
| 81 | #define INTCHW_INTC0_APM (1<<INTCHW_INTC0_APM_BITNUM) | ||
| 82 | #define INTCHW_INTC0_ESW (1<<INTCHW_INTC0_ESW_BITNUM) | ||
| 83 | #define INTCHW_INTC0_SPIH (1<<INTCHW_INTC0_SPIH_BITNUM) | ||
| 84 | #define INTCHW_INTC0_TIMER3 (1<<INTCHW_INTC0_TIMER3_BITNUM) | ||
| 85 | #define INTCHW_INTC0_TIMER2 (1<<INTCHW_INTC0_TIMER2_BITNUM) | ||
| 86 | #define INTCHW_INTC0_TIMER1 (1<<INTCHW_INTC0_TIMER1_BITNUM) | ||
| 87 | #define INTCHW_INTC0_TIMER0 (1<<INTCHW_INTC0_TIMER0_BITNUM) | ||
| 88 | #define INTCHW_INTC0_SDIOH1 (1<<INTCHW_INTC0_SDIOH1_BITNUM) | ||
| 89 | #define INTCHW_INTC0_SDIOH0 (1<<INTCHW_INTC0_SDIOH0_BITNUM) | ||
| 90 | #define INTCHW_INTC0_USBD (1<<INTCHW_INTC0_USBD_BITNUM) | ||
| 91 | #define INTCHW_INTC0_USBH1 (1<<INTCHW_INTC0_USBH1_BITNUM) | ||
| 92 | #define INTCHW_INTC0_USBHD2 (1<<INTCHW_INTC0_USBHD2_BITNUM) | ||
| 93 | #define INTCHW_INTC0_VPM (1<<INTCHW_INTC0_VPM_BITNUM) | ||
| 94 | #define INTCHW_INTC0_DMA1C7 (1<<INTCHW_INTC0_DMA1C7_BITNUM) | ||
| 95 | #define INTCHW_INTC0_DMA1C6 (1<<INTCHW_INTC0_DMA1C6_BITNUM) | ||
| 96 | #define INTCHW_INTC0_DMA1C5 (1<<INTCHW_INTC0_DMA1C5_BITNUM) | ||
| 97 | #define INTCHW_INTC0_DMA1C4 (1<<INTCHW_INTC0_DMA1C4_BITNUM) | ||
| 98 | #define INTCHW_INTC0_DMA1C3 (1<<INTCHW_INTC0_DMA1C3_BITNUM) | ||
| 99 | #define INTCHW_INTC0_DMA1C2 (1<<INTCHW_INTC0_DMA1C2_BITNUM) | ||
| 100 | #define INTCHW_INTC0_DMA1C1 (1<<INTCHW_INTC0_DMA1C1_BITNUM) | ||
| 101 | #define INTCHW_INTC0_DMA1C0 (1<<INTCHW_INTC0_DMA1C0_BITNUM) | ||
| 102 | #define INTCHW_INTC0_DMA0C7 (1<<INTCHW_INTC0_DMA0C7_BITNUM) | ||
| 103 | #define INTCHW_INTC0_DMA0C6 (1<<INTCHW_INTC0_DMA0C6_BITNUM) | ||
| 104 | #define INTCHW_INTC0_DMA0C5 (1<<INTCHW_INTC0_DMA0C5_BITNUM) | ||
| 105 | #define INTCHW_INTC0_DMA0C4 (1<<INTCHW_INTC0_DMA0C4_BITNUM) | ||
| 106 | #define INTCHW_INTC0_DMA0C3 (1<<INTCHW_INTC0_DMA0C3_BITNUM) | ||
| 107 | #define INTCHW_INTC0_DMA0C2 (1<<INTCHW_INTC0_DMA0C2_BITNUM) | ||
| 108 | #define INTCHW_INTC0_DMA0C1 (1<<INTCHW_INTC0_DMA0C1_BITNUM) | ||
| 109 | #define INTCHW_INTC0_DMA0C0 (1<<INTCHW_INTC0_DMA0C0_BITNUM) | ||
| 110 | |||
| 111 | /* INTC1 - interrupt controller 1 */ | ||
| 112 | #define INTCHW_INTC1_DDRVPMP_BITNUM 27 /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */ | ||
| 113 | #define INTCHW_INTC1_DDRVPMT_BITNUM 26 /* DDR and VPM HW phase align timeout interrupt (Not for A0) */ | ||
| 114 | #define INTCHW_INTC1_DDRP_BITNUM 26 /* DDR and PLL clock phase relationship interupt (For A0 only)) */ | ||
| 115 | #define INTCHW_INTC1_RTC2_BITNUM 25 /* Real time clock tamper interrupt */ | ||
| 116 | #define INTCHW_INTC1_VDEC_BITNUM 24 /* Hantro Video Decoder interrupt */ | ||
| 117 | /* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */ | ||
| 118 | #define INTCHW_INTC1_SPUM_BITNUM 23 /* Secure process module interrupt */ | ||
| 119 | #define INTCHW_INTC1_RTC1_BITNUM 22 /* Real time clock one-shot interrupt */ | ||
| 120 | #define INTCHW_INTC1_RTC0_BITNUM 21 /* Real time clock periodic interrupt */ | ||
| 121 | #define INTCHW_INTC1_RNG_BITNUM 20 /* Random number generator interrupt */ | ||
| 122 | #define INTCHW_INTC1_FMPU_BITNUM 19 /* Flash memory parition unit interrupt */ | ||
| 123 | #define INTCHW_INTC1_VMPU_BITNUM 18 /* VRAM memory partition interrupt */ | ||
| 124 | #define INTCHW_INTC1_DMPU_BITNUM 17 /* DDR2 memory partition interrupt */ | ||
| 125 | #define INTCHW_INTC1_KEYC_BITNUM 16 /* Key pad controller interrupt */ | ||
| 126 | #define INTCHW_INTC1_TSC_BITNUM 15 /* Touch screen controller interrupt */ | ||
| 127 | #define INTCHW_INTC1_UART0_BITNUM 14 /* UART 0 */ | ||
| 128 | #define INTCHW_INTC1_WDOG_BITNUM 13 /* Watchdog timer interrupt */ | ||
| 129 | |||
| 130 | #define INTCHW_INTC1_UART1_BITNUM 12 /* UART 1 */ | ||
| 131 | #define INTCHW_INTC1_PMUIRQ_BITNUM 11 /* ARM performance monitor interrupt */ | ||
| 132 | #define INTCHW_INTC1_COMMRX_BITNUM 10 /* ARM DDC receive interrupt */ | ||
| 133 | #define INTCHW_INTC1_COMMTX_BITNUM 9 /* ARM DDC transmit interrupt */ | ||
| 134 | #define INTCHW_INTC1_FLASHC_BITNUM 8 /* Flash controller interrupt */ | ||
| 135 | #define INTCHW_INTC1_GPHY_BITNUM 7 /* Gigabit Phy interrupt */ | ||
| 136 | #define INTCHW_INTC1_SPIS_BITNUM 6 /* SPI slave interrupt */ | ||
| 137 | #define INTCHW_INTC1_I2CS_BITNUM 5 /* I2C slave interrupt */ | ||
| 138 | #define INTCHW_INTC1_I2CH_BITNUM 4 /* I2C host interrupt */ | ||
| 139 | #define INTCHW_INTC1_I2S1_BITNUM 3 /* I2S1 interrupt */ | ||
| 140 | #define INTCHW_INTC1_I2S0_BITNUM 2 /* I2S0 interrupt */ | ||
| 141 | #define INTCHW_INTC1_GPIO1_BITNUM 1 /* GPIO bit 64//32 combined interrupt */ | ||
| 142 | #define INTCHW_INTC1_GPIO0_BITNUM 0 /* GPIO bit 31//0 combined interrupt */ | ||
| 143 | |||
| 144 | #define INTCHW_INTC1_DDRVPMT (1<<INTCHW_INTC1_DDRVPMT_BITNUM) | ||
| 145 | #define INTCHW_INTC1_DDRVPMP (1<<INTCHW_INTC1_DDRVPMP_BITNUM) | ||
| 146 | #define INTCHW_INTC1_DDRP (1<<INTCHW_INTC1_DDRP_BITNUM) | ||
| 147 | #define INTCHW_INTC1_VDEC (1<<INTCHW_INTC1_VDEC_BITNUM) | ||
| 148 | #define INTCHW_INTC1_SPUM (1<<INTCHW_INTC1_SPUM_BITNUM) | ||
| 149 | #define INTCHW_INTC1_RTC2 (1<<INTCHW_INTC1_RTC2_BITNUM) | ||
| 150 | #define INTCHW_INTC1_RTC1 (1<<INTCHW_INTC1_RTC1_BITNUM) | ||
| 151 | #define INTCHW_INTC1_RTC0 (1<<INTCHW_INTC1_RTC0_BITNUM) | ||
| 152 | #define INTCHW_INTC1_RNG (1<<INTCHW_INTC1_RNG_BITNUM) | ||
| 153 | #define INTCHW_INTC1_FMPU (1<<INTCHW_INTC1_FMPU_BITNUM) | ||
| 154 | #define INTCHW_INTC1_IMPU (1<<INTCHW_INTC1_IMPU_BITNUM) | ||
| 155 | #define INTCHW_INTC1_DMPU (1<<INTCHW_INTC1_DMPU_BITNUM) | ||
| 156 | #define INTCHW_INTC1_KEYC (1<<INTCHW_INTC1_KEYC_BITNUM) | ||
| 157 | #define INTCHW_INTC1_TSC (1<<INTCHW_INTC1_TSC_BITNUM) | ||
| 158 | #define INTCHW_INTC1_UART0 (1<<INTCHW_INTC1_UART0_BITNUM) | ||
| 159 | #define INTCHW_INTC1_WDOG (1<<INTCHW_INTC1_WDOG_BITNUM) | ||
| 160 | #define INTCHW_INTC1_UART1 (1<<INTCHW_INTC1_UART1_BITNUM) | ||
| 161 | #define INTCHW_INTC1_PMUIRQ (1<<INTCHW_INTC1_PMUIRQ_BITNUM) | ||
| 162 | #define INTCHW_INTC1_COMMRX (1<<INTCHW_INTC1_COMMRX_BITNUM) | ||
| 163 | #define INTCHW_INTC1_COMMTX (1<<INTCHW_INTC1_COMMTX_BITNUM) | ||
| 164 | #define INTCHW_INTC1_FLASHC (1<<INTCHW_INTC1_FLASHC_BITNUM) | ||
| 165 | #define INTCHW_INTC1_GPHY (1<<INTCHW_INTC1_GPHY_BITNUM) | ||
| 166 | #define INTCHW_INTC1_SPIS (1<<INTCHW_INTC1_SPIS_BITNUM) | ||
| 167 | #define INTCHW_INTC1_I2CS (1<<INTCHW_INTC1_I2CS_BITNUM) | ||
| 168 | #define INTCHW_INTC1_I2CH (1<<INTCHW_INTC1_I2CH_BITNUM) | ||
| 169 | #define INTCHW_INTC1_I2S1 (1<<INTCHW_INTC1_I2S1_BITNUM) | ||
| 170 | #define INTCHW_INTC1_I2S0 (1<<INTCHW_INTC1_I2S0_BITNUM) | ||
| 171 | #define INTCHW_INTC1_GPIO1 (1<<INTCHW_INTC1_GPIO1_BITNUM) | ||
| 172 | #define INTCHW_INTC1_GPIO0 (1<<INTCHW_INTC1_GPIO0_BITNUM) | ||
| 173 | |||
| 174 | /* SINTC secure int controller */ | ||
| 175 | #define INTCHW_SINTC_RTC2_BITNUM 15 /* Real time clock tamper interrupt */ | ||
| 176 | #define INTCHW_SINTC_TIMER3_BITNUM 14 /* Secure timer3 interrupt */ | ||
| 177 | #define INTCHW_SINTC_TIMER2_BITNUM 13 /* Secure timer2 interrupt */ | ||
| 178 | #define INTCHW_SINTC_TIMER1_BITNUM 12 /* Secure timer1 interrupt */ | ||
| 179 | #define INTCHW_SINTC_TIMER0_BITNUM 11 /* Secure timer0 interrupt */ | ||
| 180 | #define INTCHW_SINTC_SPUM_BITNUM 10 /* Secure process module interrupt */ | ||
| 181 | #define INTCHW_SINTC_RTC1_BITNUM 9 /* Real time clock one-shot interrupt */ | ||
| 182 | #define INTCHW_SINTC_RTC0_BITNUM 8 /* Real time clock periodic interrupt */ | ||
| 183 | #define INTCHW_SINTC_RNG_BITNUM 7 /* Random number generator interrupt */ | ||
| 184 | #define INTCHW_SINTC_FMPU_BITNUM 6 /* Flash memory parition unit interrupt */ | ||
| 185 | #define INTCHW_SINTC_VMPU_BITNUM 5 /* VRAM memory partition interrupt */ | ||
| 186 | #define INTCHW_SINTC_DMPU_BITNUM 4 /* DDR2 memory partition interrupt */ | ||
| 187 | #define INTCHW_SINTC_KEYC_BITNUM 3 /* Key pad controller interrupt */ | ||
| 188 | #define INTCHW_SINTC_TSC_BITNUM 2 /* Touch screen controller interrupt */ | ||
| 189 | #define INTCHW_SINTC_UART0_BITNUM 1 /* UART0 interrupt */ | ||
| 190 | #define INTCHW_SINTC_WDOG_BITNUM 0 /* Watchdog timer interrupt */ | ||
| 191 | |||
| 192 | #define INTCHW_SINTC_TIMER3 (1<<INTCHW_SINTC_TIMER3_BITNUM) | ||
| 193 | #define INTCHW_SINTC_TIMER2 (1<<INTCHW_SINTC_TIMER2_BITNUM) | ||
| 194 | #define INTCHW_SINTC_TIMER1 (1<<INTCHW_SINTC_TIMER1_BITNUM) | ||
| 195 | #define INTCHW_SINTC_TIMER0 (1<<INTCHW_SINTC_TIMER0_BITNUM) | ||
| 196 | #define INTCHW_SINTC_SPUM (1<<INTCHW_SINTC_SPUM_BITNUM) | ||
| 197 | #define INTCHW_SINTC_RTC2 (1<<INTCHW_SINTC_RTC2_BITNUM) | ||
| 198 | #define INTCHW_SINTC_RTC1 (1<<INTCHW_SINTC_RTC1_BITNUM) | ||
| 199 | #define INTCHW_SINTC_RTC0 (1<<INTCHW_SINTC_RTC0_BITNUM) | ||
| 200 | #define INTCHW_SINTC_RNG (1<<INTCHW_SINTC_RNG_BITNUM) | ||
| 201 | #define INTCHW_SINTC_FMPU (1<<INTCHW_SINTC_FMPU_BITNUM) | ||
| 202 | #define INTCHW_SINTC_IMPU (1<<INTCHW_SINTC_IMPU_BITNUM) | ||
| 203 | #define INTCHW_SINTC_DMPU (1<<INTCHW_SINTC_DMPU_BITNUM) | ||
| 204 | #define INTCHW_SINTC_KEYC (1<<INTCHW_SINTC_KEYC_BITNUM) | ||
| 205 | #define INTCHW_SINTC_TSC (1<<INTCHW_SINTC_TSC_BITNUM) | ||
| 206 | #define INTCHW_SINTC_UART0 (1<<INTCHW_SINTC_UART0_BITNUM) | ||
| 207 | #define INTCHW_SINTC_WDOG (1<<INTCHW_SINTC_WDOG_BITNUM) | ||
| 208 | |||
| 209 | /* PL192 Vectored Interrupt Controller (VIC) layout */ | ||
| 210 | #define INTCHW_IRQSTATUS 0x00 /* IRQ status register */ | ||
| 211 | #define INTCHW_FIQSTATUS 0x04 /* FIQ status register */ | ||
| 212 | #define INTCHW_RAWINTR 0x08 /* Raw Interrupt Status register */ | ||
| 213 | #define INTCHW_INTSELECT 0x0c /* Interrupt Select Register */ | ||
| 214 | #define INTCHW_INTENABLE 0x10 /* Interrupt Enable Register */ | ||
| 215 | #define INTCHW_INTENCLEAR 0x14 /* Interrupt Enable Clear Register */ | ||
| 216 | #define INTCHW_SOFTINT 0x18 /* Soft Interrupt Register */ | ||
| 217 | #define INTCHW_SOFTINTCLEAR 0x1c /* Soft Interrupt Clear Register */ | ||
| 218 | #define INTCHW_PROTECTION 0x20 /* Protection Enable Register */ | ||
| 219 | #define INTCHW_SWPRIOMASK 0x24 /* Software Priority Mask Register */ | ||
| 220 | #define INTCHW_PRIODAISY 0x28 /* Priority Daisy Chain Register */ | ||
| 221 | #define INTCHW_VECTADDR0 0x100 /* Vector Address Registers */ | ||
| 222 | #define INTCHW_VECTPRIO0 0x200 /* Vector Priority Registers 0-31 */ | ||
| 223 | #define INTCHW_ADDRESS 0xf00 /* Vector Address Register 0-31 */ | ||
| 224 | #define INTCHW_PID 0xfe0 /* Peripheral ID Register 0-3 */ | ||
| 225 | #define INTCHW_PCELLID 0xff0 /* PrimeCell ID Register 0-3 */ | ||
| 226 | |||
| 227 | /* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */ | ||
| 228 | /* intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */ | ||
| 229 | /* uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */ | ||
| 230 | /* uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */ | ||
| 231 | |||
| 232 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 233 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 234 | /* Clear one or more IRQ interrupts. */ | ||
| 235 | static inline void intcHw_irq_disable(void *basep, uint32_t mask) | ||
| 236 | { | ||
| 237 | __REG32(basep + INTCHW_INTENCLEAR) = mask; | ||
| 238 | } | ||
| 239 | |||
| 240 | /* Enables one or more IRQ interrupts. */ | ||
| 241 | static inline void intcHw_irq_enable(void *basep, uint32_t mask) | ||
| 242 | { | ||
| 243 | __REG32(basep + INTCHW_INTENABLE) = mask; | ||
| 244 | } | ||
| 245 | |||
| 246 | #endif /* _INTCHW_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h new file mode 100644 index 000000000000..86bb58d4f58c --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h | |||
| @@ -0,0 +1,101 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file mm_addr.h | ||
| 18 | * | ||
| 19 | * @brief Memory Map address defintions | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * None | ||
| 23 | */ | ||
| 24 | /****************************************************************************/ | ||
| 25 | |||
| 26 | #ifndef _MM_ADDR_H | ||
| 27 | #define _MM_ADDR_H | ||
| 28 | |||
| 29 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 30 | |||
| 31 | #if !defined(CSP_SIMULATION) | ||
| 32 | #include <cfg_global.h> | ||
| 33 | #endif | ||
| 34 | |||
| 35 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 36 | |||
| 37 | /* Memory Map address definitions */ | ||
| 38 | |||
| 39 | #define MM_ADDR_DDR 0x00000000 | ||
| 40 | |||
| 41 | #define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000 /* 16 MB - Reserved external memory for VPM use */ | ||
| 42 | |||
| 43 | #define MM_ADDR_IO_FLASHC 0x20000000 | ||
| 44 | #define MM_ADDR_IO_BROM 0x30000000 | ||
| 45 | #define MM_ADDR_IO_ARAM 0x30100000 /* 64 KB - extra cycle latency - WS switch */ | ||
| 46 | #define MM_ADDR_IO_DMA0 0x30200000 | ||
| 47 | #define MM_ADDR_IO_DMA1 0x30300000 | ||
| 48 | #define MM_ADDR_IO_ESW 0x30400000 | ||
| 49 | #define MM_ADDR_IO_CLCD 0x30500000 | ||
| 50 | #define MM_ADDR_IO_PIF 0x30580000 | ||
| 51 | #define MM_ADDR_IO_APM 0x30600000 | ||
| 52 | #define MM_ADDR_IO_SPUM 0x30700000 | ||
| 53 | #define MM_ADDR_IO_VPM_PROG 0x30800000 | ||
| 54 | #define MM_ADDR_IO_VPM_DATA 0x30A00000 | ||
| 55 | #define MM_ADDR_IO_VRAM 0x40000000 /* 64 KB - security block in front of it */ | ||
| 56 | #define MM_ADDR_IO_CHIPC 0x80000000 | ||
| 57 | #define MM_ADDR_IO_UMI 0x80001000 | ||
| 58 | #define MM_ADDR_IO_NAND 0x80001800 | ||
| 59 | #define MM_ADDR_IO_LEDM 0x80002000 | ||
| 60 | #define MM_ADDR_IO_PWM 0x80002040 | ||
| 61 | #define MM_ADDR_IO_VINTC 0x80003000 | ||
| 62 | #define MM_ADDR_IO_GPIO0 0x80004000 | ||
| 63 | #define MM_ADDR_IO_GPIO1 0x80004800 | ||
| 64 | #define MM_ADDR_IO_I2CS 0x80005000 | ||
| 65 | #define MM_ADDR_IO_SPIS 0x80006000 | ||
| 66 | #define MM_ADDR_IO_HPM 0x80007400 | ||
| 67 | #define MM_ADDR_IO_HPM_REMAP 0x80007800 | ||
| 68 | #define MM_ADDR_IO_TZPC 0x80008000 | ||
| 69 | #define MM_ADDR_IO_MPU 0x80009000 | ||
| 70 | #define MM_ADDR_IO_SPUMP 0x8000a000 | ||
| 71 | #define MM_ADDR_IO_PKA 0x8000b000 | ||
| 72 | #define MM_ADDR_IO_RNG 0x8000c000 | ||
| 73 | #define MM_ADDR_IO_KEYC 0x8000d000 | ||
| 74 | #define MM_ADDR_IO_BBL 0x8000e000 | ||
| 75 | #define MM_ADDR_IO_OTP 0x8000f000 | ||
| 76 | #define MM_ADDR_IO_I2S0 0x80010000 | ||
| 77 | #define MM_ADDR_IO_I2S1 0x80011000 | ||
| 78 | #define MM_ADDR_IO_UARTA 0x80012000 | ||
| 79 | #define MM_ADDR_IO_UARTB 0x80013000 | ||
| 80 | #define MM_ADDR_IO_I2CH 0x80014020 | ||
| 81 | #define MM_ADDR_IO_SPIH 0x80015000 | ||
| 82 | #define MM_ADDR_IO_TSC 0x80016000 | ||
| 83 | #define MM_ADDR_IO_TMR 0x80017000 | ||
| 84 | #define MM_ADDR_IO_WATCHDOG 0x80017800 | ||
| 85 | #define MM_ADDR_IO_ETM 0x80018000 | ||
| 86 | #define MM_ADDR_IO_DDRC 0x80019000 | ||
| 87 | #define MM_ADDR_IO_SINTC 0x80100000 | ||
| 88 | #define MM_ADDR_IO_INTC0 0x80200000 | ||
| 89 | #define MM_ADDR_IO_INTC1 0x80201000 | ||
| 90 | #define MM_ADDR_IO_GE 0x80300000 | ||
| 91 | #define MM_ADDR_IO_USB_CTLR0 0x80400000 | ||
| 92 | #define MM_ADDR_IO_USB_CTLR1 0x80410000 | ||
| 93 | #define MM_ADDR_IO_USB_PHY 0x80420000 | ||
| 94 | #define MM_ADDR_IO_SDIOH0 0x80500000 | ||
| 95 | #define MM_ADDR_IO_SDIOH1 0x80600000 | ||
| 96 | #define MM_ADDR_IO_VDEC 0x80700000 | ||
| 97 | |||
| 98 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 99 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 100 | |||
| 101 | #endif /* _MM_ADDR_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h new file mode 100644 index 000000000000..de92ec6a01aa --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h | |||
| @@ -0,0 +1,147 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file mm_io.h | ||
| 18 | * | ||
| 19 | * @brief Memory Map I/O definitions | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * None | ||
| 23 | */ | ||
| 24 | /****************************************************************************/ | ||
| 25 | |||
| 26 | #ifndef _MM_IO_H | ||
| 27 | #define _MM_IO_H | ||
| 28 | |||
| 29 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 30 | #include <mach/csp/mm_addr.h> | ||
| 31 | |||
| 32 | #if !defined(CSP_SIMULATION) | ||
| 33 | #include <cfg_global.h> | ||
| 34 | #endif | ||
| 35 | |||
| 36 | /* ---- Public Constants and Types --------------------------------------- */ | ||
| 37 | |||
| 38 | #if defined(CONFIG_MMU) | ||
| 39 | |||
| 40 | /* This macro is referenced in <mach/io.h> | ||
| 41 | * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx | ||
| 42 | * This macro is referenced in <asm/arch/io.h> | ||
| 43 | * | ||
| 44 | * Assume VPM address is the last x MB of memory. For VPM, map to | ||
| 45 | * 0xf0000000 and up. | ||
| 46 | */ | ||
| 47 | |||
| 48 | #ifndef MM_IO_PHYS_TO_VIRT | ||
| 49 | #ifdef __ASSEMBLY__ | ||
| 50 | #define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)) | ||
| 51 | #else | ||
| 52 | #define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \ | ||
| 53 | (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))) | ||
| 54 | #endif | ||
| 55 | #endif | ||
| 56 | |||
| 57 | /* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */ | ||
| 58 | |||
| 59 | #ifndef MM_IO_VIRT_TO_PHYS | ||
| 60 | #ifdef __ASSEMBLY__ | ||
| 61 | #define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)) | ||
| 62 | #else | ||
| 63 | #define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \ | ||
| 64 | ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))) | ||
| 65 | #endif | ||
| 66 | #endif | ||
| 67 | |||
| 68 | #else | ||
| 69 | |||
| 70 | #ifndef MM_IO_PHYS_TO_VIRT | ||
| 71 | #define MM_IO_PHYS_TO_VIRT(phys) (phys) | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #ifndef MM_IO_VIRT_TO_PHYS | ||
| 75 | #define MM_IO_VIRT_TO_PHYS(virt) (virt) | ||
| 76 | #endif | ||
| 77 | |||
| 78 | #endif | ||
| 79 | |||
| 80 | /* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */ | ||
| 81 | #define MM_IO_BASE_FLASHC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC) | ||
| 82 | #define MM_IO_BASE_NAND MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND) | ||
| 83 | #define MM_IO_BASE_UMI MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI) | ||
| 84 | |||
| 85 | #define MM_IO_START MM_ADDR_IO_FLASHC /* Physical beginning of IO mapped memory */ | ||
| 86 | #define MM_IO_BASE MM_IO_BASE_FLASHC /* Virtual beginning of IO mapped memory */ | ||
| 87 | |||
| 88 | #define MM_IO_BASE_BROM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM) | ||
| 89 | #define MM_IO_BASE_ARAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM) | ||
| 90 | #define MM_IO_BASE_DMA0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0) | ||
| 91 | #define MM_IO_BASE_DMA1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1) | ||
| 92 | #define MM_IO_BASE_ESW MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW) | ||
| 93 | #define MM_IO_BASE_CLCD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD) | ||
| 94 | #define MM_IO_BASE_PIF MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF) | ||
| 95 | #define MM_IO_BASE_APM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM) | ||
| 96 | #define MM_IO_BASE_SPUM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM) | ||
| 97 | #define MM_IO_BASE_VPM_PROG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG) | ||
| 98 | #define MM_IO_BASE_VPM_DATA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA) | ||
| 99 | |||
| 100 | #define MM_IO_BASE_VRAM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM) | ||
| 101 | |||
| 102 | #define MM_IO_BASE_CHIPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC) | ||
| 103 | #define MM_IO_BASE_DDRC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC) | ||
| 104 | #define MM_IO_BASE_LEDM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM) | ||
| 105 | #define MM_IO_BASE_PWM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM) | ||
| 106 | #define MM_IO_BASE_VINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC) | ||
| 107 | #define MM_IO_BASE_GPIO0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0) | ||
| 108 | #define MM_IO_BASE_GPIO1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1) | ||
| 109 | #define MM_IO_BASE_TMR MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR) | ||
| 110 | #define MM_IO_BASE_WATCHDOG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG) | ||
| 111 | #define MM_IO_BASE_ETM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM) | ||
| 112 | #define MM_IO_BASE_HPM MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM) | ||
| 113 | #define MM_IO_BASE_HPM_REMAP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP) | ||
| 114 | #define MM_IO_BASE_TZPC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC) | ||
| 115 | #define MM_IO_BASE_MPU MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU) | ||
| 116 | #define MM_IO_BASE_SPUMP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP) | ||
| 117 | #define MM_IO_BASE_PKA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA) | ||
| 118 | #define MM_IO_BASE_RNG MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG) | ||
| 119 | #define MM_IO_BASE_KEYC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC) | ||
| 120 | #define MM_IO_BASE_BBL MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL) | ||
| 121 | #define MM_IO_BASE_OTP MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP) | ||
| 122 | #define MM_IO_BASE_I2S0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0) | ||
| 123 | #define MM_IO_BASE_I2S1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1) | ||
| 124 | #define MM_IO_BASE_UARTA MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA) | ||
| 125 | #define MM_IO_BASE_UARTB MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB) | ||
| 126 | #define MM_IO_BASE_I2CH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH) | ||
| 127 | #define MM_IO_BASE_SPIH MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH) | ||
| 128 | #define MM_IO_BASE_TSC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC) | ||
| 129 | #define MM_IO_BASE_I2CS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS) | ||
| 130 | #define MM_IO_BASE_SPIS MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS) | ||
| 131 | #define MM_IO_BASE_SINTC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC) | ||
| 132 | #define MM_IO_BASE_INTC0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0) | ||
| 133 | #define MM_IO_BASE_INTC1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1) | ||
| 134 | #define MM_IO_BASE_GE MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE) | ||
| 135 | #define MM_IO_BASE_USB_CTLR0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0) | ||
| 136 | #define MM_IO_BASE_USB_CTLR1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1) | ||
| 137 | #define MM_IO_BASE_USB_PHY MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY) | ||
| 138 | #define MM_IO_BASE_SDIOH0 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0) | ||
| 139 | #define MM_IO_BASE_SDIOH1 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1) | ||
| 140 | #define MM_IO_BASE_VDEC MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC) | ||
| 141 | |||
| 142 | #define MM_IO_BASE_VPM_EXTMEM_RSVD MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD) | ||
| 143 | |||
| 144 | /* ---- Public Variable Externs ------------------------------------------ */ | ||
| 145 | /* ---- Public Function Prototypes --------------------------------------- */ | ||
| 146 | |||
| 147 | #endif /* _MM_IO_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h new file mode 100644 index 000000000000..d15f5f3ec2d8 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h | |||
| @@ -0,0 +1,100 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file secHw_def.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for configuring/testing secure blocks | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * None | ||
| 23 | */ | ||
| 24 | /****************************************************************************/ | ||
| 25 | |||
| 26 | #ifndef SECHW_DEF_H | ||
| 27 | #define SECHW_DEF_H | ||
| 28 | |||
| 29 | #include <mach/csp/mm_io.h> | ||
| 30 | |||
| 31 | /* Bit mask for various secure device */ | ||
| 32 | #define secHw_BLK_MASK_CHIP_CONTROL 0x00000001 | ||
| 33 | #define secHw_BLK_MASK_KEY_SCAN 0x00000002 | ||
| 34 | #define secHw_BLK_MASK_TOUCH_SCREEN 0x00000004 | ||
| 35 | #define secHw_BLK_MASK_UART0 0x00000008 | ||
| 36 | #define secHw_BLK_MASK_UART1 0x00000010 | ||
| 37 | #define secHw_BLK_MASK_WATCHDOG 0x00000020 | ||
| 38 | #define secHw_BLK_MASK_SPUM 0x00000040 | ||
| 39 | #define secHw_BLK_MASK_DDR2 0x00000080 | ||
| 40 | #define secHw_BLK_MASK_EXT_MEM 0x00000100 | ||
| 41 | #define secHw_BLK_MASK_ESW 0x00000200 | ||
| 42 | #define secHw_BLK_MASK_SPU 0x00010000 | ||
| 43 | #define secHw_BLK_MASK_PKA 0x00020000 | ||
| 44 | #define secHw_BLK_MASK_RNG 0x00040000 | ||
| 45 | #define secHw_BLK_MASK_RTC 0x00080000 | ||
| 46 | #define secHw_BLK_MASK_OTP 0x00100000 | ||
| 47 | #define secHw_BLK_MASK_BOOT 0x00200000 | ||
| 48 | #define secHw_BLK_MASK_MPU 0x00400000 | ||
| 49 | #define secHw_BLK_MASK_TZCTRL 0x00800000 | ||
| 50 | #define secHw_BLK_MASK_INTR 0x01000000 | ||
| 51 | |||
| 52 | /* Trustzone register set */ | ||
| 53 | typedef struct { | ||
| 54 | volatile uint32_t status; /* read only - reflects status of writes of 2 write registers */ | ||
| 55 | volatile uint32_t setUnsecure; /* write only. reads back as 0 */ | ||
| 56 | volatile uint32_t setSecure; /* write only. reads back as 0 */ | ||
| 57 | } secHw_TZREG_t; | ||
| 58 | |||
| 59 | /* There are 2 register sets. The first is for the lower 16 bits, the 2nd */ | ||
| 60 | /* is for the higher 16 bits. */ | ||
| 61 | |||
| 62 | typedef enum { | ||
| 63 | secHw_IDX_LS = 0, | ||
| 64 | secHw_IDX_MS = 1, | ||
| 65 | secHw_IDX_NUM | ||
| 66 | } secHw_IDX_e; | ||
| 67 | |||
| 68 | typedef struct { | ||
| 69 | volatile secHw_TZREG_t reg[secHw_IDX_NUM]; | ||
| 70 | } secHw_REGS_t; | ||
| 71 | |||
| 72 | /****************************************************************************/ | ||
| 73 | /** | ||
| 74 | * @brief Configures a device as a secure device | ||
| 75 | * | ||
| 76 | */ | ||
| 77 | /****************************************************************************/ | ||
| 78 | static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ | ||
| 79 | ); | ||
| 80 | |||
| 81 | /****************************************************************************/ | ||
| 82 | /** | ||
| 83 | * @brief Configures a device as a non-secure device | ||
| 84 | * | ||
| 85 | */ | ||
| 86 | /****************************************************************************/ | ||
| 87 | static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ | ||
| 88 | ); | ||
| 89 | |||
| 90 | /****************************************************************************/ | ||
| 91 | /** | ||
| 92 | * @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure | ||
| 93 | * | ||
| 94 | */ | ||
| 95 | /****************************************************************************/ | ||
| 96 | static inline uint32_t secHw_getStatus(void); | ||
| 97 | |||
| 98 | #include <mach/csp/secHw_inline.h> | ||
| 99 | |||
| 100 | #endif /* SECHW_DEF_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h new file mode 100644 index 000000000000..9cd6a032ab71 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h | |||
| @@ -0,0 +1,79 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file secHw_inline.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for configuring/testing secure blocks | ||
| 20 | * | ||
| 21 | * @note | ||
| 22 | * None | ||
| 23 | */ | ||
| 24 | /****************************************************************************/ | ||
| 25 | |||
| 26 | #ifndef SECHW_INLINE_H | ||
| 27 | #define SECHW_INLINE_H | ||
| 28 | |||
| 29 | /****************************************************************************/ | ||
| 30 | /** | ||
| 31 | * @brief Configures a device as a secure device | ||
| 32 | * | ||
| 33 | */ | ||
| 34 | /****************************************************************************/ | ||
| 35 | static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ | ||
| 36 | ) { | ||
| 37 | secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; | ||
| 38 | |||
| 39 | if (mask & 0x0000FFFF) { | ||
| 40 | regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF; | ||
| 41 | } | ||
| 42 | |||
| 43 | if (mask & 0xFFFF0000) { | ||
| 44 | regp->reg[secHw_IDX_MS].setSecure = mask >> 16; | ||
| 45 | } | ||
| 46 | } | ||
| 47 | |||
| 48 | /****************************************************************************/ | ||
| 49 | /** | ||
| 50 | * @brief Configures a device as a non-secure device | ||
| 51 | * | ||
| 52 | */ | ||
| 53 | /****************************************************************************/ | ||
| 54 | static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */ | ||
| 55 | ) { | ||
| 56 | secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; | ||
| 57 | |||
| 58 | if (mask & 0x0000FFFF) { | ||
| 59 | regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF; | ||
| 60 | } | ||
| 61 | if (mask & 0xFFFF0000) { | ||
| 62 | regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16; | ||
| 63 | } | ||
| 64 | } | ||
| 65 | |||
| 66 | /****************************************************************************/ | ||
| 67 | /** | ||
| 68 | * @brief Get the trustzone status for all components. 1 = non-secure, 0 = secure | ||
| 69 | * | ||
| 70 | */ | ||
| 71 | /****************************************************************************/ | ||
| 72 | static inline uint32_t secHw_getStatus(void) | ||
| 73 | { | ||
| 74 | secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC; | ||
| 75 | |||
| 76 | return (regp->reg[1].status << 16) + regp->reg[0].status; | ||
| 77 | } | ||
| 78 | |||
| 79 | #endif /* SECHW_INLINE_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h new file mode 100644 index 000000000000..3080ac7239a1 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h | |||
| @@ -0,0 +1,82 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file tmrHw_reg.h | ||
| 18 | * | ||
| 19 | * @brief Definitions for low level Timer registers | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | /****************************************************************************/ | ||
| 23 | #ifndef _TMRHW_REG_H | ||
| 24 | #define _TMRHW_REG_H | ||
| 25 | |||
| 26 | #include <mach/csp/mm_io.h> | ||
| 27 | #include <mach/csp/hw_cfg.h> | ||
| 28 | /* Base address */ | ||
| 29 | #define tmrHw_MODULE_BASE_ADDR MM_IO_BASE_TMR | ||
| 30 | |||
| 31 | /* | ||
| 32 | This platform has four different timers running at different clock speed | ||
| 33 | |||
| 34 | Timer one (Timer ID 0) runs at 25 MHz | ||
| 35 | Timer two (Timer ID 1) runs at 25 MHz | ||
| 36 | Timer three (Timer ID 2) runs at 150 MHz | ||
| 37 | Timer four (Timer ID 3) runs at 150 MHz | ||
| 38 | */ | ||
| 39 | #define tmrHw_LOW_FREQUENCY_MHZ 25 /* Always 25MHz from XTAL */ | ||
| 40 | #define tmrHw_LOW_FREQUENCY_HZ 25000000 | ||
| 41 | |||
| 42 | #if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107) | ||
| 43 | #define tmrHw_HIGH_FREQUENCY_MHZ 150 /* Always 150MHz for FPGA */ | ||
| 44 | #define tmrHw_HIGH_FREQUENCY_HZ 150000000 | ||
| 45 | #else | ||
| 46 | #define tmrHw_HIGH_FREQUENCY_HZ HW_CFG_BUS_CLK_HZ | ||
| 47 | #define tmrHw_HIGH_FREQUENCY_MHZ (HW_CFG_BUS_CLK_HZ / 1000000) | ||
| 48 | #endif | ||
| 49 | |||
| 50 | #define tmrHw_LOW_RESOLUTION_CLOCK tmrHw_LOW_FREQUENCY_HZ | ||
| 51 | #define tmrHw_HIGH_RESOLUTION_CLOCK tmrHw_HIGH_FREQUENCY_HZ | ||
| 52 | #define tmrHw_MAX_COUNT (0xFFFFFFFF) /* maximum number of count a timer can count */ | ||
| 53 | #define tmrHw_TIMER_NUM_COUNT (4) /* Number of timer module supported */ | ||
| 54 | |||
| 55 | typedef struct { | ||
| 56 | uint32_t LoadValue; /* Load value for timer */ | ||
| 57 | uint32_t CurrentValue; /* Current value for timer */ | ||
| 58 | uint32_t Control; /* Control register */ | ||
| 59 | uint32_t InterruptClear; /* Interrupt clear register */ | ||
| 60 | uint32_t RawInterruptStatus; /* Raw interrupt status */ | ||
| 61 | uint32_t InterruptStatus; /* Masked interrupt status */ | ||
| 62 | uint32_t BackgroundLoad; /* Background load value */ | ||
| 63 | uint32_t padding; /* Padding register */ | ||
| 64 | } tmrHw_REG_t; | ||
| 65 | |||
| 66 | /* Control bot masks */ | ||
| 67 | #define tmrHw_CONTROL_TIMER_ENABLE 0x00000080 | ||
| 68 | #define tmrHw_CONTROL_PERIODIC 0x00000040 | ||
| 69 | #define tmrHw_CONTROL_INTERRUPT_ENABLE 0x00000020 | ||
| 70 | #define tmrHw_CONTROL_PRESCALE_MASK 0x0000000C | ||
| 71 | #define tmrHw_CONTROL_PRESCALE_1 0x00000000 | ||
| 72 | #define tmrHw_CONTROL_PRESCALE_16 0x00000004 | ||
| 73 | #define tmrHw_CONTROL_PRESCALE_256 0x00000008 | ||
| 74 | #define tmrHw_CONTROL_32BIT 0x00000002 | ||
| 75 | #define tmrHw_CONTROL_ONESHOT 0x00000001 | ||
| 76 | #define tmrHw_CONTROL_FREE_RUNNING 0x00000000 | ||
| 77 | |||
| 78 | #define tmrHw_CONTROL_MODE_MASK (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT) | ||
| 79 | |||
| 80 | #define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR) | ||
| 81 | |||
| 82 | #endif /* _TMRHW_REG_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h new file mode 100644 index 000000000000..847980c85c88 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/dma.h | |||
| @@ -0,0 +1,826 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /****************************************************************************/ | ||
| 16 | /** | ||
| 17 | * @file dma.h | ||
| 18 | * | ||
| 19 | * @brief API definitions for the linux DMA interface. | ||
| 20 | */ | ||
| 21 | /****************************************************************************/ | ||
| 22 | |||
| 23 | #if !defined(ASM_ARM_ARCH_BCMRING_DMA_H) | ||
| 24 | #define ASM_ARM_ARCH_BCMRING_DMA_H | ||
| 25 | |||
| 26 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 27 | |||
| 28 | #include <linux/kernel.h> | ||
| 29 | #include <linux/wait.h> | ||
| 30 | #include <linux/semaphore.h> | ||
| 31 | #include <csp/dmacHw.h> | ||
| 32 | #include <mach/timer.h> | ||
| 33 | #include <linux/scatterlist.h> | ||
| 34 | #include <linux/dma-mapping.h> | ||
| 35 | #include <linux/mm.h> | ||
| 36 | #include <linux/vmalloc.h> | ||
| 37 | #include <linux/pagemap.h> | ||
| 38 | |||
| 39 | /* ---- Constants and Types ---------------------------------------------- */ | ||
| 40 | |||
| 41 | /* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */ | ||
| 42 | /* and line number of the reservation request will be recorded in the channel table */ | ||
| 43 | |||
| 44 | #define DMA_DEBUG_TRACK_RESERVATION 1 | ||
| 45 | |||
| 46 | #define DMA_NUM_CONTROLLERS 2 | ||
| 47 | #define DMA_NUM_CHANNELS 8 /* per controller */ | ||
| 48 | |||
| 49 | typedef enum { | ||
| 50 | DMA_DEVICE_MEM_TO_MEM, /* For memory to memory transfers */ | ||
| 51 | DMA_DEVICE_I2S0_DEV_TO_MEM, | ||
| 52 | DMA_DEVICE_I2S0_MEM_TO_DEV, | ||
| 53 | DMA_DEVICE_I2S1_DEV_TO_MEM, | ||
| 54 | DMA_DEVICE_I2S1_MEM_TO_DEV, | ||
| 55 | DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM, | ||
| 56 | DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV, | ||
| 57 | DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM, | ||
| 58 | DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV, | ||
| 59 | DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM, /* Additional mic input for beam-forming */ | ||
| 60 | DMA_DEVICE_APM_PCM0_DEV_TO_MEM, | ||
| 61 | DMA_DEVICE_APM_PCM0_MEM_TO_DEV, | ||
| 62 | DMA_DEVICE_APM_PCM1_DEV_TO_MEM, | ||
| 63 | DMA_DEVICE_APM_PCM1_MEM_TO_DEV, | ||
| 64 | DMA_DEVICE_SPUM_DEV_TO_MEM, | ||
| 65 | DMA_DEVICE_SPUM_MEM_TO_DEV, | ||
| 66 | DMA_DEVICE_SPIH_DEV_TO_MEM, | ||
| 67 | DMA_DEVICE_SPIH_MEM_TO_DEV, | ||
| 68 | DMA_DEVICE_UART_A_DEV_TO_MEM, | ||
| 69 | DMA_DEVICE_UART_A_MEM_TO_DEV, | ||
| 70 | DMA_DEVICE_UART_B_DEV_TO_MEM, | ||
| 71 | DMA_DEVICE_UART_B_MEM_TO_DEV, | ||
| 72 | DMA_DEVICE_PIF_MEM_TO_DEV, | ||
| 73 | DMA_DEVICE_PIF_DEV_TO_MEM, | ||
| 74 | DMA_DEVICE_ESW_DEV_TO_MEM, | ||
| 75 | DMA_DEVICE_ESW_MEM_TO_DEV, | ||
| 76 | DMA_DEVICE_VPM_MEM_TO_MEM, | ||
| 77 | DMA_DEVICE_CLCD_MEM_TO_MEM, | ||
| 78 | DMA_DEVICE_NAND_MEM_TO_MEM, | ||
| 79 | DMA_DEVICE_MEM_TO_VRAM, | ||
| 80 | DMA_DEVICE_VRAM_TO_MEM, | ||
| 81 | |||
| 82 | /* Add new entries before this line. */ | ||
| 83 | |||
| 84 | DMA_NUM_DEVICE_ENTRIES, | ||
| 85 | DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */ | ||
| 86 | |||
| 87 | } DMA_Device_t; | ||
| 88 | |||
| 89 | /**************************************************************************** | ||
| 90 | * | ||
| 91 | * The DMA_Handle_t is the primary object used by callers of the API. | ||
| 92 | * | ||
| 93 | *****************************************************************************/ | ||
| 94 | |||
| 95 | #define DMA_INVALID_HANDLE ((DMA_Handle_t) -1) | ||
| 96 | |||
| 97 | typedef int DMA_Handle_t; | ||
| 98 | |||
| 99 | /**************************************************************************** | ||
| 100 | * | ||
| 101 | * The DMA_DescriptorRing_t contains a ring of descriptors which is used | ||
| 102 | * to point to regions of memory. | ||
| 103 | * | ||
| 104 | *****************************************************************************/ | ||
| 105 | |||
| 106 | typedef struct { | ||
| 107 | void *virtAddr; /* Virtual Address of the descriptor ring */ | ||
| 108 | dma_addr_t physAddr; /* Physical address of the descriptor ring */ | ||
| 109 | int descriptorsAllocated; /* Number of descriptors allocated in the descriptor ring */ | ||
| 110 | size_t bytesAllocated; /* Number of bytes allocated in the descriptor ring */ | ||
| 111 | |||
| 112 | } DMA_DescriptorRing_t; | ||
| 113 | |||
| 114 | /**************************************************************************** | ||
| 115 | * | ||
| 116 | * The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup | ||
| 117 | * DMA chains from a variety of memory sources. | ||
| 118 | * | ||
| 119 | *****************************************************************************/ | ||
| 120 | |||
| 121 | #define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */ | ||
| 122 | /* off not being DMA'd. */ | ||
| 123 | |||
| 124 | typedef enum { | ||
| 125 | DMA_MEM_TYPE_NONE, /* Not a valid setting */ | ||
| 126 | DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */ | ||
| 127 | DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */ | ||
| 128 | DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */ | ||
| 129 | DMA_MEM_TYPE_USER, /* Memory came from user space. */ | ||
| 130 | |||
| 131 | } DMA_MemType_t; | ||
| 132 | |||
| 133 | /* A segment represents a physically and virtually contiguous chunk of memory. */ | ||
| 134 | /* i.e. each segment can be DMA'd */ | ||
| 135 | /* A user of the DMA code will add memory regions. Each region may need to be */ | ||
| 136 | /* represented by one or more segments. */ | ||
| 137 | |||
| 138 | typedef struct { | ||
| 139 | void *virtAddr; /* Virtual address used for this segment */ | ||
| 140 | dma_addr_t physAddr; /* Physical address this segment maps to */ | ||
| 141 | size_t numBytes; /* Size of the segment, in bytes */ | ||
| 142 | |||
| 143 | } DMA_Segment_t; | ||
| 144 | |||
| 145 | /* A region represents a virtually contiguous chunk of memory, which may be */ | ||
| 146 | /* made up of multiple segments. */ | ||
| 147 | |||
| 148 | typedef struct { | ||
| 149 | DMA_MemType_t memType; | ||
| 150 | void *virtAddr; | ||
| 151 | size_t numBytes; | ||
| 152 | |||
| 153 | /* Each region (virtually contiguous) consists of one or more segments. Each */ | ||
| 154 | /* segment is virtually and physically contiguous. */ | ||
| 155 | |||
| 156 | int numSegmentsUsed; | ||
| 157 | int numSegmentsAllocated; | ||
| 158 | DMA_Segment_t *segment; | ||
| 159 | |||
| 160 | /* When a region corresponds to user memory, we need to lock all of the pages */ | ||
| 161 | /* down before we can figure out the physical addresses. The lockedPage array contains */ | ||
| 162 | /* the pages that were locked, and which subsequently need to be unlocked once the */ | ||
| 163 | /* memory is unmapped. */ | ||
| 164 | |||
| 165 | unsigned numLockedPages; | ||
| 166 | struct page **lockedPages; | ||
| 167 | |||
| 168 | } DMA_Region_t; | ||
| 169 | |||
| 170 | typedef struct { | ||
| 171 | int inUse; /* Is this mapping currently being used? */ | ||
| 172 | struct semaphore lock; /* Acquired when using this structure */ | ||
| 173 | enum dma_data_direction dir; /* Direction this transfer is intended for */ | ||
| 174 | |||
| 175 | /* In the event that we're mapping user memory, we need to know which task */ | ||
| 176 | /* the memory is for, so that we can obtain the correct mm locks. */ | ||
| 177 | |||
| 178 | struct task_struct *userTask; | ||
| 179 | |||
| 180 | int numRegionsUsed; | ||
| 181 | int numRegionsAllocated; | ||
| 182 | DMA_Region_t *region; | ||
| 183 | |||
| 184 | } DMA_MemMap_t; | ||
| 185 | |||
| 186 | /**************************************************************************** | ||
| 187 | * | ||
| 188 | * The DMA_DeviceAttribute_t contains information which describes a | ||
| 189 | * particular DMA device (or peripheral). | ||
| 190 | * | ||
| 191 | * It is anticipated that the arrary of DMA_DeviceAttribute_t's will be | ||
| 192 | * statically initialized. | ||
| 193 | * | ||
| 194 | *****************************************************************************/ | ||
| 195 | |||
| 196 | /* The device handler is called whenever a DMA operation completes. The reaon */ | ||
| 197 | /* for it to be called will be a bitmask with one or more of the following bits */ | ||
| 198 | /* set. */ | ||
| 199 | |||
| 200 | #define DMA_HANDLER_REASON_BLOCK_COMPLETE dmacHw_INTERRUPT_STATUS_BLOCK | ||
| 201 | #define DMA_HANDLER_REASON_TRANSFER_COMPLETE dmacHw_INTERRUPT_STATUS_TRANS | ||
| 202 | #define DMA_HANDLER_REASON_ERROR dmacHw_INTERRUPT_STATUS_ERROR | ||
| 203 | |||
| 204 | typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason, | ||
| 205 | void *userData); | ||
| 206 | |||
| 207 | #define DMA_DEVICE_FLAG_ON_DMA0 0x00000001 | ||
| 208 | #define DMA_DEVICE_FLAG_ON_DMA1 0x00000002 | ||
| 209 | #define DMA_DEVICE_FLAG_PORT_PER_DMAC 0x00000004 /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */ | ||
| 210 | #define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST 0x00000008 /* If set, allocate from DMA1 before allocating from DMA0 */ | ||
| 211 | #define DMA_DEVICE_FLAG_IS_DEDICATED 0x00000100 | ||
| 212 | #define DMA_DEVICE_FLAG_NO_ISR 0x00000200 | ||
| 213 | #define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO 0x00000400 | ||
| 214 | #define DMA_DEVICE_FLAG_IN_USE 0x00000800 /* If set, device is in use on a channel */ | ||
| 215 | |||
| 216 | /* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */ | ||
| 217 | /* determine which DMA controllers a given device can be used from, and the interface */ | ||
| 218 | /* array determeines the actual interface number to use for a given controller. */ | ||
| 219 | |||
| 220 | typedef struct { | ||
| 221 | uint32_t flags; /* Bitmask of DMA_DEVICE_FLAG_xxx constants */ | ||
| 222 | uint8_t dedicatedController; /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */ | ||
| 223 | uint8_t dedicatedChannel; /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */ | ||
| 224 | const char *name; /* Will show up in the /proc entry */ | ||
| 225 | |||
| 226 | uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */ | ||
| 227 | |||
| 228 | dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */ | ||
| 229 | |||
| 230 | void *userData; /* Passed to the devHandler */ | ||
| 231 | DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */ | ||
| 232 | |||
| 233 | timer_tick_count_t transferStartTime; /* Time the current transfer was started */ | ||
| 234 | |||
| 235 | /* The following statistical information will be collected and presented in a proc entry. */ | ||
| 236 | /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */ | ||
| 237 | /* a 64 bit counter. */ | ||
| 238 | |||
| 239 | uint64_t numTransfers; /* Number of DMA transfers performed */ | ||
| 240 | uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */ | ||
| 241 | uint64_t transferBytes; /* Total bytes transferred */ | ||
| 242 | uint32_t timesBlocked; /* Number of times a channel was unavailable */ | ||
| 243 | uint32_t numBytes; /* Last transfer size */ | ||
| 244 | |||
| 245 | /* It's not possible to free memory which is allocated for the descriptors from within */ | ||
| 246 | /* the ISR. So make the presumption that a given device will tend to use the */ | ||
| 247 | /* same sized buffers over and over again, and we keep them around. */ | ||
| 248 | |||
| 249 | DMA_DescriptorRing_t ring; /* Ring of descriptors allocated for this device */ | ||
| 250 | |||
| 251 | /* We stash away some of the information from the previous transfer. If back-to-back */ | ||
| 252 | /* transfers are performed from the same buffer, then we don't have to keep re-initializing */ | ||
| 253 | /* the descriptor buffers. */ | ||
| 254 | |||
| 255 | uint32_t prevNumBytes; | ||
| 256 | dma_addr_t prevSrcData; | ||
| 257 | dma_addr_t prevDstData; | ||
| 258 | |||
| 259 | } DMA_DeviceAttribute_t; | ||
| 260 | |||
| 261 | /**************************************************************************** | ||
| 262 | * | ||
| 263 | * DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal | ||
| 264 | * data structures and don't belong in this header file, but are included | ||
| 265 | * merely for discussion. | ||
| 266 | * | ||
| 267 | * By the time this is implemented, these structures will be moved out into | ||
| 268 | * the appropriate C source file instead. | ||
| 269 | * | ||
| 270 | *****************************************************************************/ | ||
| 271 | |||
| 272 | /**************************************************************************** | ||
| 273 | * | ||
| 274 | * The DMA_Channel_t contains state information about each DMA channel. Some | ||
| 275 | * of the channels are dedicated. Non-dedicated channels are shared | ||
| 276 | * amongst the other devices. | ||
| 277 | * | ||
| 278 | *****************************************************************************/ | ||
| 279 | |||
| 280 | #define DMA_CHANNEL_FLAG_IN_USE 0x00000001 | ||
| 281 | #define DMA_CHANNEL_FLAG_IS_DEDICATED 0x00000002 | ||
| 282 | #define DMA_CHANNEL_FLAG_NO_ISR 0x00000004 | ||
| 283 | #define DMA_CHANNEL_FLAG_LARGE_FIFO 0x00000008 | ||
| 284 | |||
| 285 | typedef struct { | ||
| 286 | uint32_t flags; /* bitmask of DMA_CHANNEL_FLAG_xxx constants */ | ||
| 287 | DMA_Device_t devType; /* Device this channel is currently reserved for */ | ||
| 288 | DMA_Device_t lastDevType; /* Device type that used this previously */ | ||
| 289 | char name[20]; /* Name passed onto request_irq */ | ||
| 290 | |||
| 291 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 292 | const char *fileName; /* Place where channel reservation took place */ | ||
| 293 | int lineNum; /* Place where channel reservation took place */ | ||
| 294 | #endif | ||
| 295 | dmacHw_HANDLE_t dmacHwHandle; /* low level channel handle. */ | ||
| 296 | |||
| 297 | } DMA_Channel_t; | ||
| 298 | |||
| 299 | /**************************************************************************** | ||
| 300 | * | ||
| 301 | * The DMA_Controller_t contains state information about each DMA controller. | ||
| 302 | * | ||
| 303 | * The freeChannelQ is stored in the controller data structure rather than | ||
| 304 | * the channel data structure since several of the devices are accessible | ||
| 305 | * from multiple controllers, and there is no way to know which controller | ||
| 306 | * will become available first. | ||
| 307 | * | ||
| 308 | *****************************************************************************/ | ||
| 309 | |||
| 310 | typedef struct { | ||
| 311 | DMA_Channel_t channel[DMA_NUM_CHANNELS]; | ||
| 312 | |||
| 313 | } DMA_Controller_t; | ||
| 314 | |||
| 315 | /**************************************************************************** | ||
| 316 | * | ||
| 317 | * The DMA_Global_t contains all of the global state information used by | ||
| 318 | * the DMA code. | ||
| 319 | * | ||
| 320 | * Callers which need to allocate a shared channel will be queued up | ||
| 321 | * on the freeChannelQ until a channel becomes available. | ||
| 322 | * | ||
| 323 | *****************************************************************************/ | ||
| 324 | |||
| 325 | typedef struct { | ||
| 326 | struct semaphore lock; /* acquired when manipulating table entries */ | ||
| 327 | wait_queue_head_t freeChannelQ; | ||
| 328 | |||
| 329 | DMA_Controller_t controller[DMA_NUM_CONTROLLERS]; | ||
| 330 | |||
| 331 | } DMA_Global_t; | ||
| 332 | |||
| 333 | /* ---- Variable Externs ------------------------------------------------- */ | ||
| 334 | |||
| 335 | extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES]; | ||
| 336 | |||
| 337 | /* ---- Function Prototypes ---------------------------------------------- */ | ||
| 338 | |||
| 339 | #if defined(__KERNEL__) | ||
| 340 | |||
| 341 | /****************************************************************************/ | ||
| 342 | /** | ||
| 343 | * Initializes the DMA module. | ||
| 344 | * | ||
| 345 | * @return | ||
| 346 | * 0 - Success | ||
| 347 | * < 0 - Error | ||
| 348 | */ | ||
| 349 | /****************************************************************************/ | ||
| 350 | |||
| 351 | int dma_init(void); | ||
| 352 | |||
| 353 | #if (DMA_DEBUG_TRACK_RESERVATION) | ||
| 354 | DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName, | ||
| 355 | int lineNum); | ||
| 356 | #define dma_request_channel(dev) dma_request_channel_dbg(dev, __FILE__, __LINE__) | ||
| 357 | #else | ||
| 358 | |||
| 359 | /****************************************************************************/ | ||
| 360 | /** | ||
| 361 | * Reserves a channel for use with @a dev. If the device is setup to use | ||
| 362 | * a shared channel, then this function will block until a free channel | ||
| 363 | * becomes available. | ||
| 364 | * | ||
| 365 | * @return | ||
| 366 | * >= 0 - A valid DMA Handle. | ||
| 367 | * -EBUSY - Device is currently being used. | ||
| 368 | * -ENODEV - Device handed in is invalid. | ||
| 369 | */ | ||
| 370 | /****************************************************************************/ | ||
| 371 | |||
| 372 | DMA_Handle_t dma_request_channel(DMA_Device_t dev /* Device to use with the allocated channel. */ | ||
| 373 | ); | ||
| 374 | #endif | ||
| 375 | |||
| 376 | /****************************************************************************/ | ||
| 377 | /** | ||
| 378 | * Frees a previously allocated DMA Handle. | ||
| 379 | * | ||
| 380 | * @return | ||
| 381 | * 0 - DMA Handle was released successfully. | ||
| 382 | * -EINVAL - Invalid DMA handle | ||
| 383 | */ | ||
| 384 | /****************************************************************************/ | ||
| 385 | |||
| 386 | int dma_free_channel(DMA_Handle_t channel /* DMA handle. */ | ||
| 387 | ); | ||
| 388 | |||
| 389 | /****************************************************************************/ | ||
| 390 | /** | ||
| 391 | * Determines if a given device has been configured as using a shared | ||
| 392 | * channel. | ||
| 393 | * | ||
| 394 | * @return boolean | ||
| 395 | * 0 Device uses a dedicated channel | ||
| 396 | * non-zero Device uses a shared channel | ||
| 397 | */ | ||
| 398 | /****************************************************************************/ | ||
| 399 | |||
| 400 | int dma_device_is_channel_shared(DMA_Device_t dev /* Device to check. */ | ||
| 401 | ); | ||
| 402 | |||
| 403 | /****************************************************************************/ | ||
| 404 | /** | ||
| 405 | * Allocates memory to hold a descriptor ring. The descriptor ring then | ||
| 406 | * needs to be populated by making one or more calls to | ||
| 407 | * dna_add_descriptors. | ||
| 408 | * | ||
| 409 | * The returned descriptor ring will be automatically initialized. | ||
| 410 | * | ||
| 411 | * @return | ||
| 412 | * 0 Descriptor ring was allocated successfully | ||
| 413 | * -ENOMEM Unable to allocate memory for the desired number of descriptors. | ||
| 414 | */ | ||
| 415 | /****************************************************************************/ | ||
| 416 | |||
| 417 | int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to populate */ | ||
| 418 | int numDescriptors /* Number of descriptors that need to be allocated. */ | ||
| 419 | ); | ||
| 420 | |||
| 421 | /****************************************************************************/ | ||
| 422 | /** | ||
| 423 | * Releases the memory which was previously allocated for a descriptor ring. | ||
| 424 | */ | ||
| 425 | /****************************************************************************/ | ||
| 426 | |||
| 427 | void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring /* Descriptor to release */ | ||
| 428 | ); | ||
| 429 | |||
| 430 | /****************************************************************************/ | ||
| 431 | /** | ||
| 432 | * Initializes a descriptor ring, so that descriptors can be added to it. | ||
| 433 | * Once a descriptor ring has been allocated, it may be reinitialized for | ||
| 434 | * use with additional/different regions of memory. | ||
| 435 | * | ||
| 436 | * Note that if 7 descriptors are allocated, it's perfectly acceptable to | ||
| 437 | * initialize the ring with a smaller number of descriptors. The amount | ||
| 438 | * of memory allocated for the descriptor ring will not be reduced, and | ||
| 439 | * the descriptor ring may be reinitialized later | ||
| 440 | * | ||
| 441 | * @return | ||
| 442 | * 0 Descriptor ring was initialized successfully | ||
| 443 | * -ENOMEM The descriptor which was passed in has insufficient space | ||
| 444 | * to hold the desired number of descriptors. | ||
| 445 | */ | ||
| 446 | /****************************************************************************/ | ||
| 447 | |||
| 448 | int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring, /* Descriptor ring to initialize */ | ||
| 449 | int numDescriptors /* Number of descriptors to initialize. */ | ||
| 450 | ); | ||
| 451 | |||
| 452 | /****************************************************************************/ | ||
| 453 | /** | ||
| 454 | * Determines the number of descriptors which would be required for a | ||
| 455 | * transfer of the indicated memory region. | ||
| 456 | * | ||
| 457 | * This function also needs to know which DMA device this transfer will | ||
| 458 | * be destined for, so that the appropriate DMA configuration can be retrieved. | ||
| 459 | * DMA parameters such as transfer width, and whether this is a memory-to-memory | ||
| 460 | * or memory-to-peripheral, etc can all affect the actual number of descriptors | ||
| 461 | * required. | ||
| 462 | * | ||
| 463 | * @return | ||
| 464 | * > 0 Returns the number of descriptors required for the indicated transfer | ||
| 465 | * -EINVAL Invalid device type for this kind of transfer | ||
| 466 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 467 | * -ENOMEM Memory exhausted | ||
| 468 | */ | ||
| 469 | /****************************************************************************/ | ||
| 470 | |||
| 471 | int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */ | ||
| 472 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 473 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 474 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 475 | ); | ||
| 476 | |||
| 477 | /****************************************************************************/ | ||
| 478 | /** | ||
| 479 | * Adds a region of memory to the descriptor ring. Note that it may take | ||
| 480 | * multiple descriptors for each region of memory. It is the callers | ||
| 481 | * responsibility to allocate a sufficiently large descriptor ring. | ||
| 482 | * | ||
| 483 | * @return | ||
| 484 | * 0 Descriptors were added successfully | ||
| 485 | * -EINVAL Invalid device type for this kind of transfer | ||
| 486 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 487 | * -ENOMEM Memory exhausted | ||
| 488 | */ | ||
| 489 | /****************************************************************************/ | ||
| 490 | |||
| 491 | int dma_add_descriptors(DMA_DescriptorRing_t *ring, /* Descriptor ring to add descriptors to */ | ||
| 492 | DMA_Device_t device, /* DMA Device that descriptors are for */ | ||
| 493 | dma_addr_t srcData, /* Place to get data (memory or device) */ | ||
| 494 | dma_addr_t dstData, /* Place to put data (memory or device) */ | ||
| 495 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 496 | ); | ||
| 497 | |||
| 498 | /****************************************************************************/ | ||
| 499 | /** | ||
| 500 | * Sets the descriptor ring associated with a device. | ||
| 501 | * | ||
| 502 | * Once set, the descriptor ring will be associated with the device, even | ||
| 503 | * across channel request/free calls. Passing in a NULL descriptor ring | ||
| 504 | * will release any descriptor ring currently associated with the device. | ||
| 505 | * | ||
| 506 | * Note: If you call dma_transfer, or one of the other dma_alloc_ functions | ||
| 507 | * the descriptor ring may be released and reallocated. | ||
| 508 | * | ||
| 509 | * Note: This function will release the descriptor memory for any current | ||
| 510 | * descriptor ring associated with this device. | ||
| 511 | */ | ||
| 512 | /****************************************************************************/ | ||
| 513 | |||
| 514 | int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */ | ||
| 515 | DMA_DescriptorRing_t *ring /* Descriptor ring to add descriptors to */ | ||
| 516 | ); | ||
| 517 | |||
| 518 | /****************************************************************************/ | ||
| 519 | /** | ||
| 520 | * Retrieves the descriptor ring associated with a device. | ||
| 521 | */ | ||
| 522 | /****************************************************************************/ | ||
| 523 | |||
| 524 | int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */ | ||
| 525 | DMA_DescriptorRing_t *ring /* Place to store retrieved ring */ | ||
| 526 | ); | ||
| 527 | |||
| 528 | /****************************************************************************/ | ||
| 529 | /** | ||
| 530 | * Allocates buffers for the descriptors. This is normally done automatically | ||
| 531 | * but needs to be done explicitly when initiating a dma from interrupt | ||
| 532 | * context. | ||
| 533 | * | ||
| 534 | * @return | ||
| 535 | * 0 Descriptors were allocated successfully | ||
| 536 | * -EINVAL Invalid device type for this kind of transfer | ||
| 537 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 538 | * -ENOMEM Memory exhausted | ||
| 539 | */ | ||
| 540 | /****************************************************************************/ | ||
| 541 | |||
| 542 | int dma_alloc_descriptors(DMA_Handle_t handle, /* DMA Handle */ | ||
| 543 | dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ | ||
| 544 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 545 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 546 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 547 | ); | ||
| 548 | |||
| 549 | /****************************************************************************/ | ||
| 550 | /** | ||
| 551 | * Allocates and sets up descriptors for a double buffered circular buffer. | ||
| 552 | * | ||
| 553 | * This is primarily intended to be used for things like the ingress samples | ||
| 554 | * from a microphone. | ||
| 555 | * | ||
| 556 | * @return | ||
| 557 | * > 0 Number of descriptors actually allocated. | ||
| 558 | * -EINVAL Invalid device type for this kind of transfer | ||
| 559 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 560 | * -ENOMEM Memory exhausted | ||
| 561 | */ | ||
| 562 | /****************************************************************************/ | ||
| 563 | |||
| 564 | int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */ | ||
| 565 | dma_addr_t srcData, /* Physical address of source data */ | ||
| 566 | dma_addr_t dstData1, /* Physical address of first destination buffer */ | ||
| 567 | dma_addr_t dstData2, /* Physical address of second destination buffer */ | ||
| 568 | size_t numBytes /* Number of bytes in each destination buffer */ | ||
| 569 | ); | ||
| 570 | |||
| 571 | /****************************************************************************/ | ||
| 572 | /** | ||
| 573 | * Initializes a DMA_MemMap_t data structure | ||
| 574 | */ | ||
| 575 | /****************************************************************************/ | ||
| 576 | |||
| 577 | int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | ||
| 578 | ); | ||
| 579 | |||
| 580 | /****************************************************************************/ | ||
| 581 | /** | ||
| 582 | * Releases any memory currently being held by a memory mapping structure. | ||
| 583 | */ | ||
| 584 | /****************************************************************************/ | ||
| 585 | |||
| 586 | int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */ | ||
| 587 | ); | ||
| 588 | |||
| 589 | /****************************************************************************/ | ||
| 590 | /** | ||
| 591 | * Looks at a memory address and categorizes it. | ||
| 592 | * | ||
| 593 | * @return One of the values from the DMA_MemType_t enumeration. | ||
| 594 | */ | ||
| 595 | /****************************************************************************/ | ||
| 596 | |||
| 597 | DMA_MemType_t dma_mem_type(void *addr); | ||
| 598 | |||
| 599 | /****************************************************************************/ | ||
| 600 | /** | ||
| 601 | * Sets the process (aka userTask) associated with a mem map. This is | ||
| 602 | * required if user-mode segments will be added to the mapping. | ||
| 603 | */ | ||
| 604 | /****************************************************************************/ | ||
| 605 | |||
| 606 | static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap, | ||
| 607 | struct task_struct *task) | ||
| 608 | { | ||
| 609 | memMap->userTask = task; | ||
| 610 | } | ||
| 611 | |||
| 612 | /****************************************************************************/ | ||
| 613 | /** | ||
| 614 | * Looks at a memory address and determines if we support DMA'ing to/from | ||
| 615 | * that type of memory. | ||
| 616 | * | ||
| 617 | * @return boolean - | ||
| 618 | * return value != 0 means dma supported | ||
| 619 | * return value == 0 means dma not supported | ||
| 620 | */ | ||
| 621 | /****************************************************************************/ | ||
| 622 | |||
| 623 | int dma_mem_supports_dma(void *addr); | ||
| 624 | |||
| 625 | /****************************************************************************/ | ||
| 626 | /** | ||
| 627 | * Initializes a memory map for use. Since this function acquires a | ||
| 628 | * sempaphore within the memory map, it is VERY important that dma_unmap | ||
| 629 | * be called when you're finished using the map. | ||
| 630 | */ | ||
| 631 | /****************************************************************************/ | ||
| 632 | |||
| 633 | int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 634 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
| 635 | ); | ||
| 636 | |||
| 637 | /****************************************************************************/ | ||
| 638 | /** | ||
| 639 | * Adds a segment of memory to a memory map. | ||
| 640 | * | ||
| 641 | * @return 0 on success, error code otherwise. | ||
| 642 | */ | ||
| 643 | /****************************************************************************/ | ||
| 644 | |||
| 645 | int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 646 | void *mem, /* Virtual address that we want to get a map of */ | ||
| 647 | size_t numBytes /* Number of bytes being mapped */ | ||
| 648 | ); | ||
| 649 | |||
| 650 | /****************************************************************************/ | ||
| 651 | /** | ||
| 652 | * Creates a descriptor ring from a memory mapping. | ||
| 653 | * | ||
| 654 | * @return 0 on sucess, error code otherwise. | ||
| 655 | */ | ||
| 656 | /****************************************************************************/ | ||
| 657 | |||
| 658 | int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */ | ||
| 659 | DMA_MemMap_t *memMap, /* Memory map that will be used */ | ||
| 660 | dma_addr_t devPhysAddr /* Physical address of device */ | ||
| 661 | ); | ||
| 662 | |||
| 663 | /****************************************************************************/ | ||
| 664 | /** | ||
| 665 | * Maps in a memory region such that it can be used for performing a DMA. | ||
| 666 | * | ||
| 667 | * @return | ||
| 668 | */ | ||
| 669 | /****************************************************************************/ | ||
| 670 | |||
| 671 | int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 672 | void *addr, /* Virtual address that we want to get a map of */ | ||
| 673 | size_t count, /* Number of bytes being mapped */ | ||
| 674 | enum dma_data_direction dir /* Direction that the mapping will be going */ | ||
| 675 | ); | ||
| 676 | |||
| 677 | /****************************************************************************/ | ||
| 678 | /** | ||
| 679 | * Maps in a memory region such that it can be used for performing a DMA. | ||
| 680 | * | ||
| 681 | * @return | ||
| 682 | */ | ||
| 683 | /****************************************************************************/ | ||
| 684 | |||
| 685 | int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */ | ||
| 686 | int dirtied /* non-zero if any of the pages were modified */ | ||
| 687 | ); | ||
| 688 | |||
| 689 | /****************************************************************************/ | ||
| 690 | /** | ||
| 691 | * Initiates a transfer when the descriptors have already been setup. | ||
| 692 | * | ||
| 693 | * This is a special case, and normally, the dma_transfer_xxx functions should | ||
| 694 | * be used. | ||
| 695 | * | ||
| 696 | * @return | ||
| 697 | * 0 Transfer was started successfully | ||
| 698 | * -ENODEV Invalid handle | ||
| 699 | */ | ||
| 700 | /****************************************************************************/ | ||
| 701 | |||
| 702 | int dma_start_transfer(DMA_Handle_t handle); | ||
| 703 | |||
| 704 | /****************************************************************************/ | ||
| 705 | /** | ||
| 706 | * Stops a previously started DMA transfer. | ||
| 707 | * | ||
| 708 | * @return | ||
| 709 | * 0 Transfer was stopped successfully | ||
| 710 | * -ENODEV Invalid handle | ||
| 711 | */ | ||
| 712 | /****************************************************************************/ | ||
| 713 | |||
| 714 | int dma_stop_transfer(DMA_Handle_t handle); | ||
| 715 | |||
| 716 | /****************************************************************************/ | ||
| 717 | /** | ||
| 718 | * Waits for a DMA to complete by polling. This function is only intended | ||
| 719 | * to be used for testing. Interrupts should be used for most DMA operations. | ||
| 720 | */ | ||
| 721 | /****************************************************************************/ | ||
| 722 | |||
| 723 | int dma_wait_transfer_done(DMA_Handle_t handle); | ||
| 724 | |||
| 725 | /****************************************************************************/ | ||
| 726 | /** | ||
| 727 | * Initiates a DMA transfer | ||
| 728 | * | ||
| 729 | * @return | ||
| 730 | * 0 Transfer was started successfully | ||
| 731 | * -EINVAL Invalid device type for this kind of transfer | ||
| 732 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 733 | */ | ||
| 734 | /****************************************************************************/ | ||
| 735 | |||
| 736 | int dma_transfer(DMA_Handle_t handle, /* DMA Handle */ | ||
| 737 | dmacHw_TRANSFER_TYPE_e transferType, /* Type of transfer being performed */ | ||
| 738 | dma_addr_t srcData, /* Place to get data to write to device */ | ||
| 739 | dma_addr_t dstData, /* Pointer to device data address */ | ||
| 740 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 741 | ); | ||
| 742 | |||
| 743 | /****************************************************************************/ | ||
| 744 | /** | ||
| 745 | * Initiates a transfer from memory to a device. | ||
| 746 | * | ||
| 747 | * @return | ||
| 748 | * 0 Transfer was started successfully | ||
| 749 | * -EINVAL Invalid device type for this kind of transfer | ||
| 750 | * (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV) | ||
| 751 | */ | ||
| 752 | /****************************************************************************/ | ||
| 753 | |||
| 754 | static inline int dma_transfer_to_device(DMA_Handle_t handle, /* DMA Handle */ | ||
| 755 | dma_addr_t srcData, /* Place to get data to write to device (physical address) */ | ||
| 756 | dma_addr_t dstData, /* Pointer to device data address (physical address) */ | ||
| 757 | size_t numBytes /* Number of bytes to transfer to the device */ | ||
| 758 | ) { | ||
| 759 | return dma_transfer(handle, | ||
| 760 | dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL, | ||
| 761 | srcData, dstData, numBytes); | ||
| 762 | } | ||
| 763 | |||
| 764 | /****************************************************************************/ | ||
| 765 | /** | ||
| 766 | * Initiates a transfer from a device to memory. | ||
| 767 | * | ||
| 768 | * @return | ||
| 769 | * 0 Transfer was started successfully | ||
| 770 | * -EINVAL Invalid device type for this kind of transfer | ||
| 771 | * (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM) | ||
| 772 | */ | ||
| 773 | /****************************************************************************/ | ||
| 774 | |||
| 775 | static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */ | ||
| 776 | dma_addr_t srcData, /* Pointer to the device data address (physical address) */ | ||
| 777 | dma_addr_t dstData, /* Place to store data retrieved from the device (physical address) */ | ||
| 778 | size_t numBytes /* Number of bytes to retrieve from the device */ | ||
| 779 | ) { | ||
| 780 | return dma_transfer(handle, | ||
| 781 | dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM, | ||
| 782 | srcData, dstData, numBytes); | ||
| 783 | } | ||
| 784 | |||
| 785 | /****************************************************************************/ | ||
| 786 | /** | ||
| 787 | * Initiates a memory to memory transfer. | ||
| 788 | * | ||
| 789 | * @return | ||
| 790 | * 0 Transfer was started successfully | ||
| 791 | * -EINVAL Invalid device type for this kind of transfer | ||
| 792 | * (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM) | ||
| 793 | */ | ||
| 794 | /****************************************************************************/ | ||
| 795 | |||
| 796 | static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle, /* DMA Handle */ | ||
| 797 | dma_addr_t srcData, /* Place to transfer data from (physical address) */ | ||
| 798 | dma_addr_t dstData, /* Place to transfer data to (physical address) */ | ||
| 799 | size_t numBytes /* Number of bytes to transfer */ | ||
| 800 | ) { | ||
| 801 | return dma_transfer(handle, | ||
| 802 | dmacHw_TRANSFER_TYPE_MEM_TO_MEM, | ||
| 803 | srcData, dstData, numBytes); | ||
| 804 | } | ||
| 805 | |||
| 806 | /****************************************************************************/ | ||
| 807 | /** | ||
| 808 | * Set the callback function which will be called when a transfer completes. | ||
| 809 | * If a NULL callback function is set, then no callback will occur. | ||
| 810 | * | ||
| 811 | * @note @a devHandler will be called from IRQ context. | ||
| 812 | * | ||
| 813 | * @return | ||
| 814 | * 0 - Success | ||
| 815 | * -ENODEV - Device handed in is invalid. | ||
| 816 | */ | ||
| 817 | /****************************************************************************/ | ||
| 818 | |||
| 819 | int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for. */ | ||
| 820 | DMA_DeviceHandler_t devHandler, /* Function to call when the DMA completes */ | ||
| 821 | void *userData /* Pointer which will be passed to devHandler. */ | ||
| 822 | ); | ||
| 823 | |||
| 824 | #endif | ||
| 825 | |||
| 826 | #endif /* ASM_ARM_ARCH_BCMRING_DMA_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S new file mode 100644 index 000000000000..7d393ca010ac --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S | |||
| @@ -0,0 +1,86 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * | ||
| 17 | * Low-level IRQ helper macros for BCMRing-based platforms | ||
| 18 | * | ||
| 19 | */ | ||
| 20 | #include <mach/irqs.h> | ||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <mach/csp/mm_io.h> | ||
| 23 | |||
| 24 | .macro disable_fiq | ||
| 25 | .endm | ||
| 26 | |||
| 27 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 28 | ldr \base, =(MM_IO_BASE_INTC0) | ||
| 29 | ldr \irqstat, [\base, #0] @ get status | ||
| 30 | ldr \irqnr, [\base, #0x10] @ mask with enable register | ||
| 31 | ands \irqstat, \irqstat, \irqnr | ||
| 32 | mov \irqnr, #IRQ_INTC0_START | ||
| 33 | cmp \irqstat, #0 | ||
| 34 | bne 1001f | ||
| 35 | |||
| 36 | ldr \base, =(MM_IO_BASE_INTC1) | ||
| 37 | ldr \irqstat, [\base, #0] @ get status | ||
| 38 | ldr \irqnr, [\base, #0x10] @ mask with enable register | ||
| 39 | ands \irqstat, \irqstat, \irqnr | ||
| 40 | mov \irqnr, #IRQ_INTC1_START | ||
| 41 | cmp \irqstat, #0 | ||
| 42 | bne 1001f | ||
| 43 | |||
| 44 | ldr \base, =(MM_IO_BASE_SINTC) | ||
| 45 | ldr \irqstat, [\base, #0] @ get status | ||
| 46 | ldr \irqnr, [\base, #0x10] @ mask with enable register | ||
| 47 | ands \irqstat, \irqstat, \irqnr | ||
| 48 | mov \irqnr, #0xffffffff @ code meaning no interrupt bits set | ||
| 49 | cmp \irqstat, #0 | ||
| 50 | beq 1002f | ||
| 51 | |||
| 52 | mov \irqnr, #IRQ_SINTC_START @ something is set, so fixup return value | ||
| 53 | |||
| 54 | 1001: | ||
| 55 | movs \tmp, \irqstat, lsl #16 | ||
| 56 | movne \irqstat, \tmp | ||
| 57 | addeq \irqnr, \irqnr, #16 | ||
| 58 | |||
| 59 | movs \tmp, \irqstat, lsl #8 | ||
| 60 | movne \irqstat, \tmp | ||
| 61 | addeq \irqnr, \irqnr, #8 | ||
| 62 | |||
| 63 | movs \tmp, \irqstat, lsl #4 | ||
| 64 | movne \irqstat, \tmp | ||
| 65 | addeq \irqnr, \irqnr, #4 | ||
| 66 | |||
| 67 | movs \tmp, \irqstat, lsl #2 | ||
| 68 | movne \irqstat, \tmp | ||
| 69 | addeq \irqnr, \irqnr, #2 | ||
| 70 | |||
| 71 | movs \tmp, \irqstat, lsl #1 | ||
| 72 | addeq \irqnr, \irqnr, #1 | ||
| 73 | orrs \base, \base, #1 | ||
| 74 | |||
| 75 | 1002: @ irqnr will be set to 0xffffffff if no irq bits are set | ||
| 76 | .endm | ||
| 77 | |||
| 78 | .macro get_irqnr_preamble, base, tmp | ||
| 79 | .endm | ||
| 80 | |||
| 81 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 82 | .endm | ||
| 83 | |||
| 84 | .macro irq_prio_table | ||
| 85 | .endm | ||
| 86 | |||
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h new file mode 100644 index 000000000000..447eb340c611 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/hardware.h | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * This file contains the hardware definitions of the BCMRing. | ||
| 4 | * | ||
| 5 | * Copyright (C) 1999 ARM Limited. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 22 | #define __ASM_ARCH_HARDWARE_H | ||
| 23 | |||
| 24 | #include <asm/sizes.h> | ||
| 25 | #include <mach/memory.h> | ||
| 26 | #include <cfg_global.h> | ||
| 27 | #include <mach/csp/mm_io.h> | ||
| 28 | |||
| 29 | /* Hardware addresses of major areas. | ||
| 30 | * *_START is the physical address | ||
| 31 | * *_SIZE is the size of the region | ||
| 32 | * *_BASE is the virtual address | ||
| 33 | */ | ||
| 34 | #define RAM_START PHYS_OFFSET | ||
| 35 | |||
| 36 | #define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) | ||
| 37 | #define RAM_BASE PAGE_OFFSET | ||
| 38 | |||
| 39 | #define pcibios_assign_all_busses() 1 | ||
| 40 | |||
| 41 | /* Macros to make managing spinlocks a bit more controlled in terms of naming. */ | ||
| 42 | /* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */ | ||
| 43 | #if defined(__KERNEL__) | ||
| 44 | #define HW_DECLARE_SPINLOCK(name) DEFINE_SPINLOCK(bcmring_##name##_reg_lock); | ||
| 45 | #define HW_EXTERN_SPINLOCK(name) extern spinlock_t bcmring_##name##_reg_lock; | ||
| 46 | #define HW_IRQ_SAVE(name, val) spin_lock_irqsave(&bcmring_##name##_reg_lock, (val)) | ||
| 47 | #define HW_IRQ_RESTORE(name, val) spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val)) | ||
| 48 | #else | ||
| 49 | #define HW_DECLARE_SPINLOCK(name) | ||
| 50 | #define HW_EXTERN_SPINLOCK(name) | ||
| 51 | #define HW_IRQ_SAVE(name, val) {(void)(name); (void)(val); } | ||
| 52 | #define HW_IRQ_RESTORE(name, val) {(void)(name); (void)(val); } | ||
| 53 | #endif | ||
| 54 | |||
| 55 | #ifndef HW_IO_PHYS_TO_VIRT | ||
| 56 | #define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT | ||
| 57 | #endif | ||
| 58 | #define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS | ||
| 59 | |||
| 60 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h new file mode 100644 index 000000000000..4db0eff90357 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/io.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright (C) 1999 ARM Limited | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 20 | #define __ASM_ARM_ARCH_IO_H | ||
| 21 | |||
| 22 | #include <mach/hardware.h> | ||
| 23 | |||
| 24 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 25 | |||
| 26 | #define __io(a) ((void __iomem *)HW_IO_PHYS_TO_VIRT(a)) | ||
| 27 | |||
| 28 | /* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */ | ||
| 29 | /* happen in readw/writew etc. */ | ||
| 30 | |||
| 31 | #define readb(c) __raw_readb(c) | ||
| 32 | #define readw(c) __raw_readw(c) | ||
| 33 | #define readl(c) __raw_readl(c) | ||
| 34 | #define readb_relaxed(addr) readb(addr) | ||
| 35 | #define readw_relaxed(addr) readw(addr) | ||
| 36 | #define readl_relaxed(addr) readl(addr) | ||
| 37 | |||
| 38 | #define readsb(p, d, l) __raw_readsb(p, d, l) | ||
| 39 | #define readsw(p, d, l) __raw_readsw(p, d, l) | ||
| 40 | #define readsl(p, d, l) __raw_readsl(p, d, l) | ||
| 41 | |||
| 42 | #define writeb(v, c) __raw_writeb(v, c) | ||
| 43 | #define writew(v, c) __raw_writew(v, c) | ||
| 44 | #define writel(v, c) __raw_writel(v, c) | ||
| 45 | |||
| 46 | #define writesb(p, d, l) __raw_writesb(p, d, l) | ||
| 47 | #define writesw(p, d, l) __raw_writesw(p, d, l) | ||
| 48 | #define writesl(p, d, l) __raw_writesl(p, d, l) | ||
| 49 | |||
| 50 | #define memset_io(c, v, l) _memset_io((c), (v), (l)) | ||
| 51 | #define memcpy_fromio(a, c, l) _memcpy_fromio((a), (c), (l)) | ||
| 52 | #define memcpy_toio(c, a, l) _memcpy_toio((c), (a), (l)) | ||
| 53 | |||
| 54 | #define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b)) | ||
| 55 | |||
| 56 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h new file mode 100644 index 000000000000..b279b825d4a7 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/irqs.h | |||
| @@ -0,0 +1,132 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2007 Broadcom | ||
| 3 | * Copyright (C) 1999 ARM Limited | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #if !defined(ARCH_BCMRING_IRQS_H) | ||
| 21 | #define ARCH_BCMRING_IRQS_H | ||
| 22 | |||
| 23 | /* INTC0 - interrupt controller 0 */ | ||
| 24 | #define IRQ_INTC0_START 0 | ||
| 25 | #define IRQ_DMA0C0 0 /* DMA0 channel 0 interrupt */ | ||
| 26 | #define IRQ_DMA0C1 1 /* DMA0 channel 1 interrupt */ | ||
| 27 | #define IRQ_DMA0C2 2 /* DMA0 channel 2 interrupt */ | ||
| 28 | #define IRQ_DMA0C3 3 /* DMA0 channel 3 interrupt */ | ||
| 29 | #define IRQ_DMA0C4 4 /* DMA0 channel 4 interrupt */ | ||
| 30 | #define IRQ_DMA0C5 5 /* DMA0 channel 5 interrupt */ | ||
| 31 | #define IRQ_DMA0C6 6 /* DMA0 channel 6 interrupt */ | ||
| 32 | #define IRQ_DMA0C7 7 /* DMA0 channel 7 interrupt */ | ||
| 33 | #define IRQ_DMA1C0 8 /* DMA1 channel 0 interrupt */ | ||
| 34 | #define IRQ_DMA1C1 9 /* DMA1 channel 1 interrupt */ | ||
| 35 | #define IRQ_DMA1C2 10 /* DMA1 channel 2 interrupt */ | ||
| 36 | #define IRQ_DMA1C3 11 /* DMA1 channel 3 interrupt */ | ||
| 37 | #define IRQ_DMA1C4 12 /* DMA1 channel 4 interrupt */ | ||
| 38 | #define IRQ_DMA1C5 13 /* DMA1 channel 5 interrupt */ | ||
| 39 | #define IRQ_DMA1C6 14 /* DMA1 channel 6 interrupt */ | ||
| 40 | #define IRQ_DMA1C7 15 /* DMA1 channel 7 interrupt */ | ||
| 41 | #define IRQ_VPM 16 /* Voice process module interrupt */ | ||
| 42 | #define IRQ_USBHD2 17 /* USB host2/device2 interrupt */ | ||
| 43 | #define IRQ_USBH1 18 /* USB1 host interrupt */ | ||
| 44 | #define IRQ_USBD 19 /* USB device interrupt */ | ||
| 45 | #define IRQ_SDIOH0 20 /* SDIO0 host interrupt */ | ||
| 46 | #define IRQ_SDIOH1 21 /* SDIO1 host interrupt */ | ||
| 47 | #define IRQ_TIMER0 22 /* Timer0 interrupt */ | ||
| 48 | #define IRQ_TIMER1 23 /* Timer1 interrupt */ | ||
| 49 | #define IRQ_TIMER2 24 /* Timer2 interrupt */ | ||
| 50 | #define IRQ_TIMER3 25 /* Timer3 interrupt */ | ||
| 51 | #define IRQ_SPIH 26 /* SPI host interrupt */ | ||
| 52 | #define IRQ_ESW 27 /* Ethernet switch interrupt */ | ||
| 53 | #define IRQ_APM 28 /* Audio process module interrupt */ | ||
| 54 | #define IRQ_GE 29 /* Graphic engine interrupt */ | ||
| 55 | #define IRQ_CLCD 30 /* LCD Controller interrupt */ | ||
| 56 | #define IRQ_PIF 31 /* Peripheral interface interrupt */ | ||
| 57 | #define IRQ_INTC0_END 31 | ||
| 58 | |||
| 59 | /* INTC1 - interrupt controller 1 */ | ||
| 60 | #define IRQ_INTC1_START 32 | ||
| 61 | #define IRQ_GPIO0 32 /* 0 GPIO bit 31//0 combined interrupt */ | ||
| 62 | #define IRQ_GPIO1 33 /* 1 GPIO bit 64//32 combined interrupt */ | ||
| 63 | #define IRQ_I2S0 34 /* 2 I2S0 interrupt */ | ||
| 64 | #define IRQ_I2S1 35 /* 3 I2S1 interrupt */ | ||
| 65 | #define IRQ_I2CH 36 /* 4 I2C host interrupt */ | ||
| 66 | #define IRQ_I2CS 37 /* 5 I2C slave interrupt */ | ||
| 67 | #define IRQ_SPIS 38 /* 6 SPI slave interrupt */ | ||
| 68 | #define IRQ_GPHY 39 /* 7 Gigabit Phy interrupt */ | ||
| 69 | #define IRQ_FLASHC 40 /* 8 Flash controller interrupt */ | ||
| 70 | #define IRQ_COMMTX 41 /* 9 ARM DDC transmit interrupt */ | ||
| 71 | #define IRQ_COMMRX 42 /* 10 ARM DDC receive interrupt */ | ||
| 72 | #define IRQ_PMUIRQ 43 /* 11 ARM performance monitor interrupt */ | ||
| 73 | #define IRQ_UARTB 44 /* 12 UARTB */ | ||
| 74 | #define IRQ_WATCHDOG 45 /* 13 Watchdog timer interrupt */ | ||
| 75 | #define IRQ_UARTA 46 /* 14 UARTA */ | ||
| 76 | #define IRQ_TSC 47 /* 15 Touch screen controller interrupt */ | ||
| 77 | #define IRQ_KEYC 48 /* 16 Key pad controller interrupt */ | ||
| 78 | #define IRQ_DMPU 49 /* 17 DDR2 memory partition interrupt */ | ||
| 79 | #define IRQ_VMPU 50 /* 18 VRAM memory partition interrupt */ | ||
| 80 | #define IRQ_FMPU 51 /* 19 Flash memory parition unit interrupt */ | ||
| 81 | #define IRQ_RNG 52 /* 20 Random number generator interrupt */ | ||
| 82 | #define IRQ_RTC0 53 /* 21 Real time clock periodic interrupt */ | ||
| 83 | #define IRQ_RTC1 54 /* 22 Real time clock one-shot interrupt */ | ||
| 84 | #define IRQ_SPUM 55 /* 23 Secure process module interrupt */ | ||
| 85 | #define IRQ_VDEC 56 /* 24 Hantro video decoder interrupt */ | ||
| 86 | #define IRQ_RTC2 57 /* 25 Real time clock tamper interrupt */ | ||
| 87 | #define IRQ_DDRP 58 /* 26 DDR Panic interrupt */ | ||
| 88 | #define IRQ_INTC1_END 58 | ||
| 89 | |||
| 90 | /* SINTC secure int controller */ | ||
| 91 | #define IRQ_SINTC_START 59 | ||
| 92 | #define IRQ_SEC_WATCHDOG 59 /* 0 Watchdog timer interrupt */ | ||
| 93 | #define IRQ_SEC_UARTA 60 /* 1 UARTA interrupt */ | ||
| 94 | #define IRQ_SEC_TSC 61 /* 2 Touch screen controller interrupt */ | ||
| 95 | #define IRQ_SEC_KEYC 62 /* 3 Key pad controller interrupt */ | ||
| 96 | #define IRQ_SEC_DMPU 63 /* 4 DDR2 memory partition interrupt */ | ||
| 97 | #define IRQ_SEC_VMPU 64 /* 5 VRAM memory partition interrupt */ | ||
| 98 | #define IRQ_SEC_FMPU 65 /* 6 Flash memory parition unit interrupt */ | ||
| 99 | #define IRQ_SEC_RNG 66 /* 7 Random number generator interrupt */ | ||
| 100 | #define IRQ_SEC_RTC0 67 /* 8 Real time clock periodic interrupt */ | ||
| 101 | #define IRQ_SEC_RTC1 68 /* 9 Real time clock one-shot interrupt */ | ||
| 102 | #define IRQ_SEC_SPUM 69 /* 10 Secure process module interrupt */ | ||
| 103 | #define IRQ_SEC_TIMER0 70 /* 11 Secure timer0 interrupt */ | ||
| 104 | #define IRQ_SEC_TIMER1 71 /* 12 Secure timer1 interrupt */ | ||
| 105 | #define IRQ_SEC_TIMER2 72 /* 13 Secure timer2 interrupt */ | ||
| 106 | #define IRQ_SEC_TIMER3 73 /* 14 Secure timer3 interrupt */ | ||
| 107 | #define IRQ_SEC_RTC2 74 /* 15 Real time clock tamper interrupt */ | ||
| 108 | |||
| 109 | #define IRQ_SINTC_END 74 | ||
| 110 | |||
| 111 | /* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */ | ||
| 112 | /* Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */ | ||
| 113 | /* to make the mapping easy for humans to decipher. */ | ||
| 114 | |||
| 115 | #define IRQ_GPIO_0 100 | ||
| 116 | |||
| 117 | #define NUM_INTERNAL_IRQS (IRQ_SINTC_END+1) | ||
| 118 | |||
| 119 | /* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */ | ||
| 120 | /* define NUM_GPIO_IRQS GPIOHW_TOTAL_NUM_PINS */ | ||
| 121 | #define NUM_GPIO_IRQS 62 | ||
| 122 | |||
| 123 | #define NR_IRQS (IRQ_GPIO_0 + NUM_GPIO_IRQS) | ||
| 124 | |||
| 125 | #define IRQ_UNKNOWN -1 | ||
| 126 | |||
| 127 | /* Tune these bits to preclude noisy or unsupported interrupt sources as required. */ | ||
| 128 | #define IRQ_INTC0_VALID_MASK 0xffffffff | ||
| 129 | #define IRQ_INTC1_VALID_MASK 0x07ffffff | ||
| 130 | #define IRQ_SINTC_VALID_MASK 0x0000ffff | ||
| 131 | |||
| 132 | #endif /* ARCH_BCMRING_IRQS_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h new file mode 100644 index 000000000000..114f942bb4f3 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/memory.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 16 | #define __ASM_ARCH_MEMORY_H | ||
| 17 | |||
| 18 | #include <cfg_global.h> | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Physical vs virtual RAM address space conversion. These are | ||
| 22 | * private definitions which should NOT be used outside memory.h | ||
| 23 | * files. Use virt_to_phys/phys_to_virt/__pa/__va instead. | ||
| 24 | */ | ||
| 25 | |||
| 26 | #define PHYS_OFFSET CFG_GLOBAL_RAM_BASE | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Maximum DMA memory allowed is 14M | ||
| 30 | */ | ||
| 31 | #define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M) | ||
| 32 | |||
| 33 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h new file mode 100644 index 000000000000..ce5cd16f2ac4 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/memory_settings.h | |||
| @@ -0,0 +1,67 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #ifndef MEMORY_SETTINGS_H | ||
| 16 | #define MEMORY_SETTINGS_H | ||
| 17 | |||
| 18 | /* ---- Include Files ---------------------------------------- */ | ||
| 19 | /* ---- Constants and Types ---------------------------------- */ | ||
| 20 | |||
| 21 | /* Memory devices */ | ||
| 22 | /* NAND Flash timing for 166 MHz setting */ | ||
| 23 | #define HW_CFG_NAND_tBTA (5 << 16) /* Bus turnaround cycle (n) 0-7 (30 ns) */ | ||
| 24 | #define HW_CFG_NAND_tWP (4 << 11) /* Write pulse width cycle (n+1) 0-31 (25 ns) */ | ||
| 25 | #define HW_CFG_NAND_tWR (1 << 9) /* Write recovery cycle (n+1) 0-3 (10 ns) */ | ||
| 26 | #define HW_CFG_NAND_tAS (0 << 7) /* Write address setup cycle (n+1) 0-3 ( 0 ns) */ | ||
| 27 | #define HW_CFG_NAND_tOE (3 << 5) /* Output enable delay cycle (n) 0-3 (15 ns) */ | ||
| 28 | #define HW_CFG_NAND_tRC (7 << 0) /* Read access cycle (n+2) 0-31 (50 ns) */ | ||
| 29 | |||
| 30 | #define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \ | ||
| 31 | | HW_CFG_NAND_tWP \ | ||
| 32 | | HW_CFG_NAND_tWR \ | ||
| 33 | | HW_CFG_NAND_tAS \ | ||
| 34 | | HW_CFG_NAND_tOE \ | ||
| 35 | | HW_CFG_NAND_tRC) | ||
| 36 | |||
| 37 | /* NOR Flash timing for 166 MHz setting */ | ||
| 38 | #define HW_CFG_NOR_TPRC_TWLC (0 << 19) /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */ | ||
| 39 | #define HW_CFG_NOR_TBTA (0 << 16) /* Bus turnaround cycle (n) (DNA) */ | ||
| 40 | #define HW_CFG_NOR_TWP (6 << 11) /* Write pulse width cycle (n+1) (35ns) */ | ||
| 41 | #define HW_CFG_NOR_TWR (0 << 9) /* Write recovery cycle (n+1) (0ns) */ | ||
| 42 | #define HW_CFG_NOR_TAS (0 << 7) /* Write address setup cycle (n+1) (0ns) */ | ||
| 43 | #define HW_CFG_NOR_TOE (0 << 5) /* Output enable delay cycle (n) (max 25ns) */ | ||
| 44 | #define HW_CFG_NOR_TRC_TLC (0x10 << 0) /* Read access cycle / Burst read latency (n+2 / n+1) (100ns) */ | ||
| 45 | |||
| 46 | #define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \ | ||
| 47 | | HW_CFG_NOR_TBTA \ | ||
| 48 | | HW_CFG_NOR_TWP \ | ||
| 49 | | HW_CFG_NOR_TWR \ | ||
| 50 | | HW_CFG_NOR_TAS \ | ||
| 51 | | HW_CFG_NOR_TOE \ | ||
| 52 | | HW_CFG_NOR_TRC_TLC) | ||
| 53 | |||
| 54 | #define HW_CFG_FLASH1_TCR HW_CFG_FLASH0_TCR | ||
| 55 | #define HW_CFG_FLASH2_TCR HW_CFG_FLASH0_TCR | ||
| 56 | |||
| 57 | /* SDRAM Settings */ | ||
| 58 | /* #define HW_CFG_SDRAM_CAS_LATENCY 5 Default 5, Values [3..6] */ | ||
| 59 | /* #define HW_CFG_SDRAM_CHIP_SELECT_CNT 1 Default 1, Vaules [1..2] */ | ||
| 60 | /* #define HW_CFG_SDRAM_SPEED_GRADE 667 Default 667, Values [400,533,667,800] */ | ||
| 61 | /* #define HW_CFG_SDRAM_WIDTH_BITS 16 Default 16, Vaules [8,16] */ | ||
| 62 | #define HW_CFG_SDRAM_SIZE_BYTES 0x10000000 /* Total memory, not per device size */ | ||
| 63 | |||
| 64 | /* ---- Variable Externs ------------------------------------- */ | ||
| 65 | /* ---- Function Prototypes ---------------------------------- */ | ||
| 66 | |||
| 67 | #endif /* MEMORY_SETTINGS_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h new file mode 100644 index 000000000000..cdbf93c694a6 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/system.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright (C) 1999 ARM Limited | ||
| 4 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 21 | #define __ASM_ARCH_SYSTEM_H | ||
| 22 | |||
| 23 | #include <mach/csp/chipcHw_inline.h> | ||
| 24 | |||
| 25 | extern int bcmring_arch_warm_reboot; | ||
| 26 | |||
| 27 | static inline void arch_idle(void) | ||
| 28 | { | ||
| 29 | cpu_do_idle(); | ||
| 30 | } | ||
| 31 | |||
| 32 | static inline void arch_reset(char mode, char *cmd) | ||
| 33 | { | ||
| 34 | printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot); | ||
| 35 | |||
| 36 | if (mode == 'h') { | ||
| 37 | /* Reboot configured in proc entry */ | ||
| 38 | if (bcmring_arch_warm_reboot) { | ||
| 39 | printk("warm reset\n"); | ||
| 40 | /* Issue Warm reset (do not reset ethernet switch, keep alive) */ | ||
| 41 | chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM); | ||
| 42 | } else { | ||
| 43 | /* Force reset of everything */ | ||
| 44 | printk("force reset\n"); | ||
| 45 | chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); | ||
| 46 | } | ||
| 47 | } else { | ||
| 48 | /* Force reset of everything */ | ||
| 49 | printk("force reset\n"); | ||
| 50 | chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT); | ||
| 51 | } | ||
| 52 | } | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h new file mode 100644 index 000000000000..5a94bbb032b6 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/timer.h | |||
| @@ -0,0 +1,77 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2004 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * | ||
| 17 | ***************************************************************************** | ||
| 18 | * | ||
| 19 | * timer.h | ||
| 20 | * | ||
| 21 | * PURPOSE: | ||
| 22 | * | ||
| 23 | * | ||
| 24 | * | ||
| 25 | * NOTES: | ||
| 26 | * | ||
| 27 | *****************************************************************************/ | ||
| 28 | |||
| 29 | #if !defined(BCM_LINUX_TIMER_H) | ||
| 30 | #define BCM_LINUX_TIMER_H | ||
| 31 | |||
| 32 | #if defined(__KERNEL__) | ||
| 33 | |||
| 34 | /* ---- Include Files ---------------------------------------------------- */ | ||
| 35 | /* ---- Constants and Types ---------------------------------------------- */ | ||
| 36 | |||
| 37 | typedef unsigned int timer_tick_count_t; | ||
| 38 | typedef unsigned int timer_tick_rate_t; | ||
| 39 | typedef unsigned int timer_msec_t; | ||
| 40 | |||
| 41 | /* ---- Variable Externs ------------------------------------------------- */ | ||
| 42 | /* ---- Function Prototypes ---------------------------------------------- */ | ||
| 43 | |||
| 44 | /**************************************************************************** | ||
| 45 | * | ||
| 46 | * timer_get_tick_count | ||
| 47 | * | ||
| 48 | * | ||
| 49 | ***************************************************************************/ | ||
| 50 | timer_tick_count_t timer_get_tick_count(void); | ||
| 51 | |||
| 52 | /**************************************************************************** | ||
| 53 | * | ||
| 54 | * timer_get_tick_rate | ||
| 55 | * | ||
| 56 | * | ||
| 57 | ***************************************************************************/ | ||
| 58 | timer_tick_rate_t timer_get_tick_rate(void); | ||
| 59 | |||
| 60 | /**************************************************************************** | ||
| 61 | * | ||
| 62 | * timer_get_msec | ||
| 63 | * | ||
| 64 | * | ||
| 65 | ***************************************************************************/ | ||
| 66 | timer_msec_t timer_get_msec(void); | ||
| 67 | |||
| 68 | /**************************************************************************** | ||
| 69 | * | ||
| 70 | * timer_ticks_to_msec | ||
| 71 | * | ||
| 72 | * | ||
| 73 | ***************************************************************************/ | ||
| 74 | timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks); | ||
| 75 | |||
| 76 | #endif /* __KERNEL__ */ | ||
| 77 | #endif /* BCM_LINUX_TIMER_H */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h new file mode 100644 index 000000000000..40d033ec5892 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/timex.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Integrator architecture timex specifications | ||
| 4 | * | ||
| 5 | * Copyright (C) 1999 ARM Limited | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | |||
| 22 | /* | ||
| 23 | * Specifies the number of ticks per second | ||
| 24 | */ | ||
| 25 | #define CLOCK_TICK_RATE 100000 /* REG_SMT_TICKS_PER_SEC */ | ||
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h new file mode 100644 index 000000000000..9c9821b77977 --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/uncompress.h | |||
| @@ -0,0 +1,43 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2005 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | #include <mach/csp/mm_addr.h> | ||
| 15 | |||
| 16 | #define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA) | ||
| 17 | #define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18)) | ||
| 18 | /* | ||
| 19 | * This does not append a newline | ||
| 20 | */ | ||
| 21 | static inline void putc(int c) | ||
| 22 | { | ||
| 23 | /* Send out UARTA */ | ||
| 24 | while (BCMRING_UART_0_FR & (1 << 5)) | ||
| 25 | ; | ||
| 26 | |||
| 27 | BCMRING_UART_0_DR = c; | ||
| 28 | } | ||
| 29 | |||
| 30 | |||
| 31 | static inline void flush(void) | ||
| 32 | { | ||
| 33 | /* Wait for the tx fifo to be empty */ | ||
| 34 | while ((BCMRING_UART_0_FR & (1 << 7)) == 0) | ||
| 35 | ; | ||
| 36 | |||
| 37 | /* Wait for the final character to be sent on the txd line */ | ||
| 38 | while (BCMRING_UART_0_FR & (1 << 3)) | ||
| 39 | ; | ||
| 40 | } | ||
| 41 | |||
| 42 | #define arch_decomp_setup() | ||
| 43 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h new file mode 100644 index 000000000000..35e2ead8395c --- /dev/null +++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright (C) 2000 Russell King. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Move VMALLOC_END to 0xf0000000 so that the vm space can range from | ||
| 22 | * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles | ||
| 23 | * larger physical memory designs better. | ||
| 24 | */ | ||
| 25 | #define VMALLOC_END (PAGE_OFFSET + 0x30000000) | ||
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c new file mode 100644 index 000000000000..dc1c4939b0ce --- /dev/null +++ b/arch/arm/mach-bcmring/irq.c | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * Copyright (C) 1999 ARM Limited | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or modify | ||
| 6 | * it under the terms of the GNU General Public License as published by | ||
| 7 | * the Free Software Foundation; either version 2 of the License, or | ||
| 8 | * (at your option) any later version. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/stddef.h> | ||
| 21 | #include <linux/list.h> | ||
| 22 | #include <linux/timer.h> | ||
| 23 | #include <linux/version.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | |||
| 26 | #include <mach/hardware.h> | ||
| 27 | #include <asm/irq.h> | ||
| 28 | |||
| 29 | #include <asm/mach/irq.h> | ||
| 30 | #include <mach/csp/intcHw_reg.h> | ||
| 31 | #include <mach/csp/mm_io.h> | ||
| 32 | |||
| 33 | static void bcmring_mask_irq0(unsigned int irq) | ||
| 34 | { | ||
| 35 | writel(1 << (irq - IRQ_INTC0_START), | ||
| 36 | MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR); | ||
| 37 | } | ||
| 38 | |||
| 39 | static void bcmring_unmask_irq0(unsigned int irq) | ||
| 40 | { | ||
| 41 | writel(1 << (irq - IRQ_INTC0_START), | ||
| 42 | MM_IO_BASE_INTC0 + INTCHW_INTENABLE); | ||
| 43 | } | ||
| 44 | |||
| 45 | static void bcmring_mask_irq1(unsigned int irq) | ||
| 46 | { | ||
| 47 | writel(1 << (irq - IRQ_INTC1_START), | ||
| 48 | MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR); | ||
| 49 | } | ||
| 50 | |||
| 51 | static void bcmring_unmask_irq1(unsigned int irq) | ||
| 52 | { | ||
| 53 | writel(1 << (irq - IRQ_INTC1_START), | ||
| 54 | MM_IO_BASE_INTC1 + INTCHW_INTENABLE); | ||
| 55 | } | ||
| 56 | |||
| 57 | static void bcmring_mask_irq2(unsigned int irq) | ||
| 58 | { | ||
| 59 | writel(1 << (irq - IRQ_SINTC_START), | ||
| 60 | MM_IO_BASE_SINTC + INTCHW_INTENCLEAR); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void bcmring_unmask_irq2(unsigned int irq) | ||
| 64 | { | ||
| 65 | writel(1 << (irq - IRQ_SINTC_START), | ||
| 66 | MM_IO_BASE_SINTC + INTCHW_INTENABLE); | ||
| 67 | } | ||
| 68 | |||
| 69 | static struct irq_chip bcmring_irq0_chip = { | ||
| 70 | .typename = "ARM-INTC0", | ||
| 71 | .ack = bcmring_mask_irq0, | ||
| 72 | .mask = bcmring_mask_irq0, /* mask a specific interrupt, blocking its delivery. */ | ||
| 73 | .unmask = bcmring_unmask_irq0, /* unmaks an interrupt */ | ||
| 74 | }; | ||
| 75 | |||
| 76 | static struct irq_chip bcmring_irq1_chip = { | ||
| 77 | .typename = "ARM-INTC1", | ||
| 78 | .ack = bcmring_mask_irq1, | ||
| 79 | .mask = bcmring_mask_irq1, | ||
| 80 | .unmask = bcmring_unmask_irq1, | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct irq_chip bcmring_irq2_chip = { | ||
| 84 | .typename = "ARM-SINTC", | ||
| 85 | .ack = bcmring_mask_irq2, | ||
| 86 | .mask = bcmring_mask_irq2, | ||
| 87 | .unmask = bcmring_unmask_irq2, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static void vic_init(void __iomem *base, struct irq_chip *chip, | ||
| 91 | unsigned int irq_start, unsigned int vic_sources) | ||
| 92 | { | ||
| 93 | unsigned int i; | ||
| 94 | for (i = 0; i < 32; i++) { | ||
| 95 | unsigned int irq = irq_start + i; | ||
| 96 | set_irq_chip(irq, chip); | ||
| 97 | set_irq_chip_data(irq, base); | ||
| 98 | |||
| 99 | if (vic_sources & (1 << i)) { | ||
| 100 | set_irq_handler(irq, handle_level_irq); | ||
| 101 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 102 | } | ||
| 103 | } | ||
| 104 | writel(0, base + INTCHW_INTSELECT); | ||
| 105 | writel(0, base + INTCHW_INTENABLE); | ||
| 106 | writel(~0, base + INTCHW_INTENCLEAR); | ||
| 107 | writel(0, base + INTCHW_IRQSTATUS); | ||
| 108 | writel(~0, base + INTCHW_SOFTINTCLEAR); | ||
| 109 | } | ||
| 110 | |||
| 111 | void __init bcmring_init_irq(void) | ||
| 112 | { | ||
| 113 | vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip, | ||
| 114 | IRQ_INTC0_START, IRQ_INTC0_VALID_MASK); | ||
| 115 | vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip, | ||
| 116 | IRQ_INTC1_START, IRQ_INTC1_VALID_MASK); | ||
| 117 | vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip, | ||
| 118 | IRQ_SINTC_START, IRQ_SINTC_VALID_MASK); | ||
| 119 | |||
| 120 | /* special cases */ | ||
| 121 | if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { | ||
| 122 | set_irq_handler(IRQ_GPIO0, handle_simple_irq); | ||
| 123 | } | ||
| 124 | if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { | ||
| 125 | set_irq_handler(IRQ_GPIO1, handle_simple_irq); | ||
| 126 | } | ||
| 127 | } | ||
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c new file mode 100644 index 000000000000..0f1c37e4523a --- /dev/null +++ b/arch/arm/mach-bcmring/mm.c | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <asm/mach/map.h> | ||
| 17 | |||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <mach/csp/mm_io.h> | ||
| 20 | |||
| 21 | #define IO_DESC(va, sz) { .virtual = va, \ | ||
| 22 | .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ | ||
| 23 | .length = sz, \ | ||
| 24 | .type = MT_DEVICE } | ||
| 25 | |||
| 26 | #define MEM_DESC(va, sz) { .virtual = va, \ | ||
| 27 | .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \ | ||
| 28 | .length = sz, \ | ||
| 29 | .type = MT_MEMORY } | ||
| 30 | |||
| 31 | static struct map_desc bcmring_io_desc[] __initdata = { | ||
| 32 | IO_DESC(MM_IO_BASE_NAND, SZ_64K), /* phys:0x28000000-0x28000FFF virt:0xE8000000-0xE8000FFF size:0x00010000 */ | ||
| 33 | IO_DESC(MM_IO_BASE_UMI, SZ_64K), /* phys:0x2C000000-0x2C000FFF virt:0xEC000000-0xEC000FFF size:0x00010000 */ | ||
| 34 | |||
| 35 | IO_DESC(MM_IO_BASE_BROM, SZ_64K), /* phys:0x30000000-0x3000FFFF virt:0xF3000000-0xF300FFFF size:0x00010000 */ | ||
| 36 | MEM_DESC(MM_IO_BASE_ARAM, SZ_1M), /* phys:0x31000000-0x31FFFFFF virt:0xF3100000-0xF31FFFFF size:0x01000000 */ | ||
| 37 | IO_DESC(MM_IO_BASE_DMA0, SZ_1M), /* phys:0x32000000-0x32FFFFFF virt:0xF3200000-0xF32FFFFF size:0x01000000 */ | ||
| 38 | IO_DESC(MM_IO_BASE_DMA1, SZ_1M), /* phys:0x33000000-0x33FFFFFF virt:0xF3300000-0xF33FFFFF size:0x01000000 */ | ||
| 39 | IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF virt:0xF3400000-0xF34FFFFF size:0x01000000 */ | ||
| 40 | IO_DESC(MM_IO_BASE_CLCD, SZ_1M), /* phys:0x35000000-0x35FFFFFF virt:0xF3500000-0xF35FFFFF size:0x01000000 */ | ||
| 41 | IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF virt:0xF3600000-0xF36FFFFF size:0x01000000 */ | ||
| 42 | IO_DESC(MM_IO_BASE_SPUM, SZ_1M), /* phys:0x37000000-0x37FFFFFF virt:0xF3700000-0xF37FFFFF size:0x01000000 */ | ||
| 43 | IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M), /* phys:0x38000000-0x38FFFFFF virt:0xF3800000-0xF38FFFFF size:0x01000000 */ | ||
| 44 | IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M), /* phys:0x3A000000-0x3AFFFFFF virt:0xF3A00000-0xF3AFFFFF size:0x01000000 */ | ||
| 45 | |||
| 46 | IO_DESC(MM_IO_BASE_VRAM, SZ_64K), /* phys:0x40000000-0x4000FFFF virt:0xF4000000-0xF400FFFF size:0x00010000 */ | ||
| 47 | IO_DESC(MM_IO_BASE_CHIPC, SZ_16M), /* phys:0x80000000-0x80FFFFFF virt:0xF8000000-0xF8FFFFFF size:0x01000000 */ | ||
| 48 | IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD, | ||
| 49 | SZ_16M), /* phys:0x0F000000-0x0FFFFFFF virt:0xF0000000-0xF0FFFFFF size:0x01000000 */ | ||
| 50 | }; | ||
| 51 | |||
| 52 | void __init bcmring_map_io(void) | ||
| 53 | { | ||
| 54 | |||
| 55 | iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc)); | ||
| 56 | } | ||
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c new file mode 100644 index 000000000000..2d415d2a8e68 --- /dev/null +++ b/arch/arm/mach-bcmring/timer.c | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | /***************************************************************************** | ||
| 2 | * Copyright 2003 - 2008 Broadcom Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * Unless you and Broadcom execute a separate written software license | ||
| 5 | * agreement governing use of this software, this software is licensed to you | ||
| 6 | * under the terms of the GNU General Public License version 2, available at | ||
| 7 | * http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). | ||
| 8 | * | ||
| 9 | * Notwithstanding the above, under no circumstances may you combine this | ||
| 10 | * software in any way with any other Broadcom software provided under a | ||
| 11 | * license other than the GPL, without Broadcom's express prior written | ||
| 12 | * consent. | ||
| 13 | *****************************************************************************/ | ||
| 14 | |||
| 15 | #include <linux/version.h> | ||
| 16 | #include <linux/types.h> | ||
| 17 | #include <linux/module.h> | ||
| 18 | #include <csp/tmrHw.h> | ||
| 19 | |||
| 20 | #include <mach/timer.h> | ||
| 21 | /* The core.c file initializes timers 1 and 3 as a linux clocksource. */ | ||
| 22 | /* The real time clock should probably be the real linux clocksource. */ | ||
| 23 | /* In the meantime, this file should agree with core.c as to the */ | ||
| 24 | /* profiling timer. If the clocksource is moved to rtc later, then */ | ||
| 25 | /* we can init the profiling timer here instead. */ | ||
| 26 | |||
| 27 | /* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */ | ||
| 28 | /* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */ | ||
| 29 | /* affect synchronization with scheduling and APM timing. */ | ||
| 30 | |||
| 31 | #define PROF_TIMER 1 | ||
| 32 | |||
| 33 | timer_tick_rate_t timer_get_tick_rate(void) | ||
| 34 | { | ||
| 35 | return tmrHw_getCountRate(PROF_TIMER); | ||
| 36 | } | ||
| 37 | |||
| 38 | timer_tick_count_t timer_get_tick_count(void) | ||
| 39 | { | ||
| 40 | return tmrHw_GetCurrentCount(PROF_TIMER); /* change downcounter to upcounter */ | ||
| 41 | } | ||
| 42 | |||
| 43 | timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks) | ||
| 44 | { | ||
| 45 | static int tickRateMsec; | ||
| 46 | |||
| 47 | if (tickRateMsec == 0) { | ||
| 48 | tickRateMsec = timer_get_tick_rate() / 1000; | ||
| 49 | } | ||
| 50 | |||
| 51 | return ticks / tickRateMsec; | ||
| 52 | } | ||
| 53 | |||
| 54 | timer_msec_t timer_get_msec(void) | ||
| 55 | { | ||
| 56 | return timer_ticks_to_msec(timer_get_tick_count()); | ||
| 57 | } | ||
| 58 | |||
| 59 | EXPORT_SYMBOL(timer_get_tick_count); | ||
| 60 | EXPORT_SYMBOL(timer_ticks_to_msec); | ||
| 61 | EXPORT_SYMBOL(timer_get_tick_rate); | ||
| 62 | EXPORT_SYMBOL(timer_get_msec); | ||
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c index 3fbd9b0fbe24..caf6d5154aec 100644 --- a/arch/arm/mach-ep93xx/adssphere.c +++ b/arch/arm/mach-ep93xx/adssphere.c | |||
| @@ -12,18 +12,15 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/mm.h> | ||
| 16 | #include <linux/sched.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/ioport.h> | ||
| 19 | #include <linux/mtd/physmap.h> | ||
| 20 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 21 | #include <linux/io.h> | 16 | #include <linux/mtd/physmap.h> |
| 22 | #include <linux/i2c.h> | 17 | |
| 23 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 19 | |||
| 24 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 26 | 22 | ||
| 23 | |||
| 27 | static struct physmap_flash_data adssphere_flash_data = { | 24 | static struct physmap_flash_data adssphere_flash_data = { |
| 28 | .width = 4, | 25 | .width = 4, |
| 29 | }; | 26 | }; |
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 6c4c1633ed12..3dd0e2a23095 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
| @@ -22,48 +22,39 @@ | |||
| 22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | 23 | ||
| 24 | 24 | ||
| 25 | /* | ||
| 26 | * The EP93xx has two external crystal oscillators. To generate the | ||
| 27 | * required high-frequency clocks, the processor uses two phase-locked- | ||
| 28 | * loops (PLLs) to multiply the incoming external clock signal to much | ||
| 29 | * higher frequencies that are then divided down by programmable dividers | ||
| 30 | * to produce the needed clocks. The PLLs operate independently of one | ||
| 31 | * another. | ||
| 32 | */ | ||
| 33 | #define EP93XX_EXT_CLK_RATE 14745600 | ||
| 34 | #define EP93XX_EXT_RTC_RATE 32768 | ||
| 35 | |||
| 36 | |||
| 37 | struct clk { | 25 | struct clk { |
| 38 | unsigned long rate; | 26 | unsigned long rate; |
| 39 | int users; | 27 | int users; |
| 40 | int sw_locked; | 28 | int sw_locked; |
| 41 | u32 enable_reg; | 29 | void __iomem *enable_reg; |
| 42 | u32 enable_mask; | 30 | u32 enable_mask; |
| 43 | 31 | ||
| 44 | unsigned long (*get_rate)(struct clk *clk); | 32 | unsigned long (*get_rate)(struct clk *clk); |
| 33 | int (*set_rate)(struct clk *clk, unsigned long rate); | ||
| 45 | }; | 34 | }; |
| 46 | 35 | ||
| 47 | 36 | ||
| 48 | static unsigned long get_uart_rate(struct clk *clk); | 37 | static unsigned long get_uart_rate(struct clk *clk); |
| 49 | 38 | ||
| 39 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate); | ||
| 40 | |||
| 50 | 41 | ||
| 51 | static struct clk clk_uart1 = { | 42 | static struct clk clk_uart1 = { |
| 52 | .sw_locked = 1, | 43 | .sw_locked = 1, |
| 53 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | 44 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 54 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U1EN, | 45 | .enable_mask = EP93XX_SYSCON_DEVCFG_U1EN, |
| 55 | .get_rate = get_uart_rate, | 46 | .get_rate = get_uart_rate, |
| 56 | }; | 47 | }; |
| 57 | static struct clk clk_uart2 = { | 48 | static struct clk clk_uart2 = { |
| 58 | .sw_locked = 1, | 49 | .sw_locked = 1, |
| 59 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | 50 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 60 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U2EN, | 51 | .enable_mask = EP93XX_SYSCON_DEVCFG_U2EN, |
| 61 | .get_rate = get_uart_rate, | 52 | .get_rate = get_uart_rate, |
| 62 | }; | 53 | }; |
| 63 | static struct clk clk_uart3 = { | 54 | static struct clk clk_uart3 = { |
| 64 | .sw_locked = 1, | 55 | .sw_locked = 1, |
| 65 | .enable_reg = EP93XX_SYSCON_DEVICE_CONFIG, | 56 | .enable_reg = EP93XX_SYSCON_DEVCFG, |
| 66 | .enable_mask = EP93XX_SYSCON_DEVICE_CONFIG_U3EN, | 57 | .enable_mask = EP93XX_SYSCON_DEVCFG_U3EN, |
| 67 | .get_rate = get_uart_rate, | 58 | .get_rate = get_uart_rate, |
| 68 | }; | 59 | }; |
| 69 | static struct clk clk_pll1; | 60 | static struct clk clk_pll1; |
| @@ -75,6 +66,15 @@ static struct clk clk_usb_host = { | |||
| 75 | .enable_reg = EP93XX_SYSCON_PWRCNT, | 66 | .enable_reg = EP93XX_SYSCON_PWRCNT, |
| 76 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, | 67 | .enable_mask = EP93XX_SYSCON_PWRCNT_USH_EN, |
| 77 | }; | 68 | }; |
| 69 | static struct clk clk_keypad = { | ||
| 70 | .sw_locked = 1, | ||
| 71 | .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV, | ||
| 72 | .enable_mask = EP93XX_SYSCON_KEYTCHCLKDIV_KEN, | ||
| 73 | .set_rate = set_keytchclk_rate, | ||
| 74 | }; | ||
| 75 | static struct clk clk_pwm = { | ||
| 76 | .rate = EP93XX_EXT_CLK_RATE, | ||
| 77 | }; | ||
| 78 | 78 | ||
| 79 | /* DMA Clocks */ | 79 | /* DMA Clocks */ |
| 80 | static struct clk clk_m2p0 = { | 80 | static struct clk clk_m2p0 = { |
| @@ -130,27 +130,29 @@ static struct clk clk_m2m1 = { | |||
| 130 | { .dev_id = dev, .con_id = con, .clk = ck } | 130 | { .dev_id = dev, .con_id = con, .clk = ck } |
| 131 | 131 | ||
| 132 | static struct clk_lookup clocks[] = { | 132 | static struct clk_lookup clocks[] = { |
| 133 | INIT_CK("apb:uart1", NULL, &clk_uart1), | 133 | INIT_CK("apb:uart1", NULL, &clk_uart1), |
| 134 | INIT_CK("apb:uart2", NULL, &clk_uart2), | 134 | INIT_CK("apb:uart2", NULL, &clk_uart2), |
| 135 | INIT_CK("apb:uart3", NULL, &clk_uart3), | 135 | INIT_CK("apb:uart3", NULL, &clk_uart3), |
| 136 | INIT_CK(NULL, "pll1", &clk_pll1), | 136 | INIT_CK(NULL, "pll1", &clk_pll1), |
| 137 | INIT_CK(NULL, "fclk", &clk_f), | 137 | INIT_CK(NULL, "fclk", &clk_f), |
| 138 | INIT_CK(NULL, "hclk", &clk_h), | 138 | INIT_CK(NULL, "hclk", &clk_h), |
| 139 | INIT_CK(NULL, "pclk", &clk_p), | 139 | INIT_CK(NULL, "pclk", &clk_p), |
| 140 | INIT_CK(NULL, "pll2", &clk_pll2), | 140 | INIT_CK(NULL, "pll2", &clk_pll2), |
| 141 | INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), | 141 | INIT_CK("ep93xx-ohci", NULL, &clk_usb_host), |
| 142 | INIT_CK(NULL, "m2p0", &clk_m2p0), | 142 | INIT_CK("ep93xx-keypad", NULL, &clk_keypad), |
| 143 | INIT_CK(NULL, "m2p1", &clk_m2p1), | 143 | INIT_CK(NULL, "pwm_clk", &clk_pwm), |
| 144 | INIT_CK(NULL, "m2p2", &clk_m2p2), | 144 | INIT_CK(NULL, "m2p0", &clk_m2p0), |
| 145 | INIT_CK(NULL, "m2p3", &clk_m2p3), | 145 | INIT_CK(NULL, "m2p1", &clk_m2p1), |
| 146 | INIT_CK(NULL, "m2p4", &clk_m2p4), | 146 | INIT_CK(NULL, "m2p2", &clk_m2p2), |
| 147 | INIT_CK(NULL, "m2p5", &clk_m2p5), | 147 | INIT_CK(NULL, "m2p3", &clk_m2p3), |
| 148 | INIT_CK(NULL, "m2p6", &clk_m2p6), | 148 | INIT_CK(NULL, "m2p4", &clk_m2p4), |
| 149 | INIT_CK(NULL, "m2p7", &clk_m2p7), | 149 | INIT_CK(NULL, "m2p5", &clk_m2p5), |
| 150 | INIT_CK(NULL, "m2p8", &clk_m2p8), | 150 | INIT_CK(NULL, "m2p6", &clk_m2p6), |
| 151 | INIT_CK(NULL, "m2p9", &clk_m2p9), | 151 | INIT_CK(NULL, "m2p7", &clk_m2p7), |
| 152 | INIT_CK(NULL, "m2m0", &clk_m2m0), | 152 | INIT_CK(NULL, "m2p8", &clk_m2p8), |
| 153 | INIT_CK(NULL, "m2m1", &clk_m2m1), | 153 | INIT_CK(NULL, "m2p9", &clk_m2p9), |
| 154 | INIT_CK(NULL, "m2m0", &clk_m2m0), | ||
| 155 | INIT_CK(NULL, "m2m1", &clk_m2m1), | ||
| 154 | }; | 156 | }; |
| 155 | 157 | ||
| 156 | 158 | ||
| @@ -160,9 +162,11 @@ int clk_enable(struct clk *clk) | |||
| 160 | u32 value; | 162 | u32 value; |
| 161 | 163 | ||
| 162 | value = __raw_readl(clk->enable_reg); | 164 | value = __raw_readl(clk->enable_reg); |
| 165 | value |= clk->enable_mask; | ||
| 163 | if (clk->sw_locked) | 166 | if (clk->sw_locked) |
| 164 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 167 | ep93xx_syscon_swlocked_write(value, clk->enable_reg); |
| 165 | __raw_writel(value | clk->enable_mask, clk->enable_reg); | 168 | else |
| 169 | __raw_writel(value, clk->enable_reg); | ||
| 166 | } | 170 | } |
| 167 | 171 | ||
| 168 | return 0; | 172 | return 0; |
| @@ -175,9 +179,11 @@ void clk_disable(struct clk *clk) | |||
| 175 | u32 value; | 179 | u32 value; |
| 176 | 180 | ||
| 177 | value = __raw_readl(clk->enable_reg); | 181 | value = __raw_readl(clk->enable_reg); |
| 182 | value &= ~clk->enable_mask; | ||
| 178 | if (clk->sw_locked) | 183 | if (clk->sw_locked) |
| 179 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 184 | ep93xx_syscon_swlocked_write(value, clk->enable_reg); |
| 180 | __raw_writel(value & ~clk->enable_mask, clk->enable_reg); | 185 | else |
| 186 | __raw_writel(value, clk->enable_reg); | ||
| 181 | } | 187 | } |
| 182 | } | 188 | } |
| 183 | EXPORT_SYMBOL(clk_disable); | 189 | EXPORT_SYMBOL(clk_disable); |
| @@ -202,6 +208,43 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 202 | } | 208 | } |
| 203 | EXPORT_SYMBOL(clk_get_rate); | 209 | EXPORT_SYMBOL(clk_get_rate); |
| 204 | 210 | ||
| 211 | static int set_keytchclk_rate(struct clk *clk, unsigned long rate) | ||
| 212 | { | ||
| 213 | u32 val; | ||
| 214 | u32 div_bit; | ||
| 215 | |||
| 216 | val = __raw_readl(clk->enable_reg); | ||
| 217 | |||
| 218 | /* | ||
| 219 | * The Key Matrix and ADC clocks are configured using the same | ||
| 220 | * System Controller register. The clock used will be either | ||
| 221 | * 1/4 or 1/16 the external clock rate depending on the | ||
| 222 | * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV | ||
| 223 | * bit being set or cleared. | ||
| 224 | */ | ||
| 225 | div_bit = clk->enable_mask >> 15; | ||
| 226 | |||
| 227 | if (rate == EP93XX_KEYTCHCLK_DIV4) | ||
| 228 | val |= div_bit; | ||
| 229 | else if (rate == EP93XX_KEYTCHCLK_DIV16) | ||
| 230 | val &= ~div_bit; | ||
| 231 | else | ||
| 232 | return -EINVAL; | ||
| 233 | |||
| 234 | ep93xx_syscon_swlocked_write(val, clk->enable_reg); | ||
| 235 | clk->rate = rate; | ||
| 236 | return 0; | ||
| 237 | } | ||
| 238 | |||
| 239 | int clk_set_rate(struct clk *clk, unsigned long rate) | ||
| 240 | { | ||
| 241 | if (clk->set_rate) | ||
| 242 | return clk->set_rate(clk, rate); | ||
| 243 | |||
| 244 | return -EINVAL; | ||
| 245 | } | ||
| 246 | EXPORT_SYMBOL(clk_set_rate); | ||
| 247 | |||
| 205 | 248 | ||
| 206 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; | 249 | static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 }; |
| 207 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; | 250 | static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 }; |
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c index 204dc5cbd0b8..16b92c37ec99 100644 --- a/arch/arm/mach-ep93xx/core.c +++ b/arch/arm/mach-ep93xx/core.c | |||
| @@ -16,40 +16,24 @@ | |||
| 16 | 16 | ||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/spinlock.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/sched.h> | ||
| 21 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
| 22 | #include <linux/serial.h> | ||
| 23 | #include <linux/tty.h> | ||
| 24 | #include <linux/bitops.h> | ||
| 25 | #include <linux/serial_8250.h> | ||
| 26 | #include <linux/serial_core.h> | ||
| 27 | #include <linux/device.h> | ||
| 28 | #include <linux/mm.h> | ||
| 29 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
| 30 | #include <linux/time.h> | ||
| 31 | #include <linux/timex.h> | 22 | #include <linux/timex.h> |
| 32 | #include <linux/delay.h> | 23 | #include <linux/io.h> |
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/leds.h> | ||
| 33 | #include <linux/termios.h> | 26 | #include <linux/termios.h> |
| 34 | #include <linux/amba/bus.h> | 27 | #include <linux/amba/bus.h> |
| 35 | #include <linux/amba/serial.h> | 28 | #include <linux/amba/serial.h> |
| 36 | #include <linux/io.h> | ||
| 37 | #include <linux/i2c.h> | 29 | #include <linux/i2c.h> |
| 38 | #include <linux/i2c-gpio.h> | 30 | #include <linux/i2c-gpio.h> |
| 39 | 31 | ||
| 40 | #include <asm/types.h> | ||
| 41 | #include <asm/setup.h> | ||
| 42 | #include <asm/memory.h> | ||
| 43 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 44 | #include <asm/irq.h> | ||
| 45 | #include <asm/system.h> | ||
| 46 | #include <asm/tlbflush.h> | ||
| 47 | #include <asm/pgtable.h> | ||
| 48 | 33 | ||
| 49 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 50 | #include <asm/mach/time.h> | 35 | #include <asm/mach/time.h> |
| 51 | #include <asm/mach/irq.h> | 36 | #include <asm/mach/irq.h> |
| 52 | #include <mach/gpio.h> | ||
| 53 | 37 | ||
| 54 | #include <asm/hardware/vic.h> | 38 | #include <asm/hardware/vic.h> |
| 55 | 39 | ||
| @@ -98,7 +82,7 @@ void __init ep93xx_map_io(void) | |||
| 98 | */ | 82 | */ |
| 99 | static unsigned int last_jiffy_time; | 83 | static unsigned int last_jiffy_time; |
| 100 | 84 | ||
| 101 | #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ) | 85 | #define TIMER4_TICKS_PER_JIFFY DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ) |
| 102 | 86 | ||
| 103 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) | 87 | static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id) |
| 104 | { | 88 | { |
| @@ -362,8 +346,8 @@ void __init ep93xx_init_irq(void) | |||
| 362 | { | 346 | { |
| 363 | int gpio_irq; | 347 | int gpio_irq; |
| 364 | 348 | ||
| 365 | vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); | 349 | vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0); |
| 366 | vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); | 350 | vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0); |
| 367 | 351 | ||
| 368 | for (gpio_irq = gpio_to_irq(0); | 352 | for (gpio_irq = gpio_to_irq(0); |
| 369 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { | 353 | gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { |
| @@ -385,6 +369,47 @@ void __init ep93xx_init_irq(void) | |||
| 385 | 369 | ||
| 386 | 370 | ||
| 387 | /************************************************************************* | 371 | /************************************************************************* |
| 372 | * EP93xx System Controller Software Locked register handling | ||
| 373 | *************************************************************************/ | ||
| 374 | |||
| 375 | /* | ||
| 376 | * syscon_swlock prevents anything else from writing to the syscon | ||
| 377 | * block while a software locked register is being written. | ||
| 378 | */ | ||
| 379 | static DEFINE_SPINLOCK(syscon_swlock); | ||
| 380 | |||
| 381 | void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg) | ||
| 382 | { | ||
| 383 | unsigned long flags; | ||
| 384 | |||
| 385 | spin_lock_irqsave(&syscon_swlock, flags); | ||
| 386 | |||
| 387 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
| 388 | __raw_writel(val, reg); | ||
| 389 | |||
| 390 | spin_unlock_irqrestore(&syscon_swlock, flags); | ||
| 391 | } | ||
| 392 | EXPORT_SYMBOL(ep93xx_syscon_swlocked_write); | ||
| 393 | |||
| 394 | void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits) | ||
| 395 | { | ||
| 396 | unsigned long flags; | ||
| 397 | unsigned int val; | ||
| 398 | |||
| 399 | spin_lock_irqsave(&syscon_swlock, flags); | ||
| 400 | |||
| 401 | val = __raw_readl(EP93XX_SYSCON_DEVCFG); | ||
| 402 | val |= set_bits; | ||
| 403 | val &= ~clear_bits; | ||
| 404 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
| 405 | __raw_writel(val, EP93XX_SYSCON_DEVCFG); | ||
| 406 | |||
| 407 | spin_unlock_irqrestore(&syscon_swlock, flags); | ||
| 408 | } | ||
| 409 | EXPORT_SYMBOL(ep93xx_devcfg_set_clear); | ||
| 410 | |||
| 411 | |||
| 412 | /************************************************************************* | ||
| 388 | * EP93xx peripheral handling | 413 | * EP93xx peripheral handling |
| 389 | *************************************************************************/ | 414 | *************************************************************************/ |
| 390 | #define EP93XX_UART_MCR_OFFSET (0x0100) | 415 | #define EP93XX_UART_MCR_OFFSET (0x0100) |
| @@ -517,10 +542,8 @@ static struct platform_device ep93xx_eth_device = { | |||
| 517 | 542 | ||
| 518 | void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) | 543 | void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr) |
| 519 | { | 544 | { |
| 520 | if (copy_addr) { | 545 | if (copy_addr) |
| 521 | memcpy(data->dev_addr, | 546 | memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6); |
| 522 | (void *)(EP93XX_ETHERNET_BASE + 0x50), 6); | ||
| 523 | } | ||
| 524 | 547 | ||
| 525 | ep93xx_eth_data = *data; | 548 | ep93xx_eth_data = *data; |
| 526 | platform_device_register(&ep93xx_eth_device); | 549 | platform_device_register(&ep93xx_eth_device); |
| @@ -546,19 +569,125 @@ void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num) | |||
| 546 | platform_device_register(&ep93xx_i2c_device); | 569 | platform_device_register(&ep93xx_i2c_device); |
| 547 | } | 570 | } |
| 548 | 571 | ||
| 572 | |||
| 573 | /************************************************************************* | ||
| 574 | * EP93xx LEDs | ||
| 575 | *************************************************************************/ | ||
| 576 | static struct gpio_led ep93xx_led_pins[] = { | ||
| 577 | { | ||
| 578 | .name = "platform:grled", | ||
| 579 | .gpio = EP93XX_GPIO_LINE_GRLED, | ||
| 580 | }, { | ||
| 581 | .name = "platform:rdled", | ||
| 582 | .gpio = EP93XX_GPIO_LINE_RDLED, | ||
| 583 | }, | ||
| 584 | }; | ||
| 585 | |||
| 586 | static struct gpio_led_platform_data ep93xx_led_data = { | ||
| 587 | .num_leds = ARRAY_SIZE(ep93xx_led_pins), | ||
| 588 | .leds = ep93xx_led_pins, | ||
| 589 | }; | ||
| 590 | |||
| 591 | static struct platform_device ep93xx_leds = { | ||
| 592 | .name = "leds-gpio", | ||
| 593 | .id = -1, | ||
| 594 | .dev = { | ||
| 595 | .platform_data = &ep93xx_led_data, | ||
| 596 | }, | ||
| 597 | }; | ||
| 598 | |||
| 599 | |||
| 600 | /************************************************************************* | ||
| 601 | * EP93xx pwm peripheral handling | ||
| 602 | *************************************************************************/ | ||
| 603 | static struct resource ep93xx_pwm0_resource[] = { | ||
| 604 | { | ||
| 605 | .start = EP93XX_PWM_PHYS_BASE, | ||
| 606 | .end = EP93XX_PWM_PHYS_BASE + 0x10 - 1, | ||
| 607 | .flags = IORESOURCE_MEM, | ||
| 608 | }, | ||
| 609 | }; | ||
| 610 | |||
| 611 | static struct platform_device ep93xx_pwm0_device = { | ||
| 612 | .name = "ep93xx-pwm", | ||
| 613 | .id = 0, | ||
| 614 | .num_resources = ARRAY_SIZE(ep93xx_pwm0_resource), | ||
| 615 | .resource = ep93xx_pwm0_resource, | ||
| 616 | }; | ||
| 617 | |||
| 618 | static struct resource ep93xx_pwm1_resource[] = { | ||
| 619 | { | ||
| 620 | .start = EP93XX_PWM_PHYS_BASE + 0x20, | ||
| 621 | .end = EP93XX_PWM_PHYS_BASE + 0x30 - 1, | ||
| 622 | .flags = IORESOURCE_MEM, | ||
| 623 | }, | ||
| 624 | }; | ||
| 625 | |||
| 626 | static struct platform_device ep93xx_pwm1_device = { | ||
| 627 | .name = "ep93xx-pwm", | ||
| 628 | .id = 1, | ||
| 629 | .num_resources = ARRAY_SIZE(ep93xx_pwm1_resource), | ||
| 630 | .resource = ep93xx_pwm1_resource, | ||
| 631 | }; | ||
| 632 | |||
| 633 | void __init ep93xx_register_pwm(int pwm0, int pwm1) | ||
| 634 | { | ||
| 635 | if (pwm0) | ||
| 636 | platform_device_register(&ep93xx_pwm0_device); | ||
| 637 | |||
| 638 | /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */ | ||
| 639 | if (pwm1) | ||
| 640 | platform_device_register(&ep93xx_pwm1_device); | ||
| 641 | } | ||
| 642 | |||
| 643 | int ep93xx_pwm_acquire_gpio(struct platform_device *pdev) | ||
| 644 | { | ||
| 645 | int err; | ||
| 646 | |||
| 647 | if (pdev->id == 0) { | ||
| 648 | err = 0; | ||
| 649 | } else if (pdev->id == 1) { | ||
| 650 | err = gpio_request(EP93XX_GPIO_LINE_EGPIO14, | ||
| 651 | dev_name(&pdev->dev)); | ||
| 652 | if (err) | ||
| 653 | return err; | ||
| 654 | err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0); | ||
| 655 | if (err) | ||
| 656 | goto fail; | ||
| 657 | |||
| 658 | /* PWM 1 output on EGPIO[14] */ | ||
| 659 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG); | ||
| 660 | } else { | ||
| 661 | err = -ENODEV; | ||
| 662 | } | ||
| 663 | |||
| 664 | return err; | ||
| 665 | |||
| 666 | fail: | ||
| 667 | gpio_free(EP93XX_GPIO_LINE_EGPIO14); | ||
| 668 | return err; | ||
| 669 | } | ||
| 670 | EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio); | ||
| 671 | |||
| 672 | void ep93xx_pwm_release_gpio(struct platform_device *pdev) | ||
| 673 | { | ||
| 674 | if (pdev->id == 1) { | ||
| 675 | gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14); | ||
| 676 | gpio_free(EP93XX_GPIO_LINE_EGPIO14); | ||
| 677 | |||
| 678 | /* EGPIO[14] used for GPIO */ | ||
| 679 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG); | ||
| 680 | } | ||
| 681 | } | ||
| 682 | EXPORT_SYMBOL(ep93xx_pwm_release_gpio); | ||
| 683 | |||
| 684 | |||
| 549 | extern void ep93xx_gpio_init(void); | 685 | extern void ep93xx_gpio_init(void); |
| 550 | 686 | ||
| 551 | void __init ep93xx_init_devices(void) | 687 | void __init ep93xx_init_devices(void) |
| 552 | { | 688 | { |
| 553 | unsigned int v; | 689 | /* Disallow access to MaverickCrunch initially */ |
| 554 | 690 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA); | |
| 555 | /* | ||
| 556 | * Disallow access to MaverickCrunch initially. | ||
| 557 | */ | ||
| 558 | v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); | ||
| 559 | v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE; | ||
| 560 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | ||
| 561 | __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG); | ||
| 562 | 691 | ||
| 563 | ep93xx_gpio_init(); | 692 | ep93xx_gpio_init(); |
| 564 | 693 | ||
| @@ -568,4 +697,5 @@ void __init ep93xx_init_devices(void) | |||
| 568 | 697 | ||
| 569 | platform_device_register(&ep93xx_rtc_device); | 698 | platform_device_register(&ep93xx_rtc_device); |
| 570 | platform_device_register(&ep93xx_ohci_device); | 699 | platform_device_register(&ep93xx_ohci_device); |
| 700 | platform_device_register(&ep93xx_leds); | ||
| 571 | } | 701 | } |
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c index e9e45b92457e..73145ae5d3fa 100644 --- a/arch/arm/mach-ep93xx/edb93xx.c +++ b/arch/arm/mach-ep93xx/edb93xx.c | |||
| @@ -26,18 +26,16 @@ | |||
| 26 | 26 | ||
| 27 | #include <linux/kernel.h> | 27 | #include <linux/kernel.h> |
| 28 | #include <linux/init.h> | 28 | #include <linux/init.h> |
| 29 | #include <linux/mm.h> | ||
| 30 | #include <linux/sched.h> | ||
| 31 | #include <linux/interrupt.h> | ||
| 32 | #include <linux/ioport.h> | ||
| 33 | #include <linux/mtd/physmap.h> | ||
| 34 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 35 | #include <linux/io.h> | ||
| 36 | #include <linux/i2c.h> | 30 | #include <linux/i2c.h> |
| 31 | #include <linux/mtd/physmap.h> | ||
| 32 | |||
| 37 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 34 | |||
| 38 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 39 | #include <asm/mach/arch.h> | 36 | #include <asm/mach/arch.h> |
| 40 | 37 | ||
| 38 | |||
| 41 | static struct physmap_flash_data edb93xx_flash_data; | 39 | static struct physmap_flash_data edb93xx_flash_data; |
| 42 | 40 | ||
| 43 | static struct resource edb93xx_flash_resource = { | 41 | static struct resource edb93xx_flash_resource = { |
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c index 3bad500b71b6..3da7ca816d19 100644 --- a/arch/arm/mach-ep93xx/gesbc9312.c +++ b/arch/arm/mach-ep93xx/gesbc9312.c | |||
| @@ -12,18 +12,15 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/mm.h> | ||
| 16 | #include <linux/sched.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/ioport.h> | ||
| 19 | #include <linux/mtd/physmap.h> | ||
| 20 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 21 | #include <linux/io.h> | 16 | #include <linux/mtd/physmap.h> |
| 22 | #include <linux/i2c.h> | 17 | |
| 23 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 19 | |||
| 24 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 26 | 22 | ||
| 23 | |||
| 27 | static struct physmap_flash_data gesbc9312_flash_data = { | 24 | static struct physmap_flash_data gesbc9312_flash_data = { |
| 28 | .width = 4, | 25 | .width = 4, |
| 29 | }; | 26 | }; |
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c index 482cf3d2fbcd..1ea8871e03a9 100644 --- a/arch/arm/mach-ep93xx/gpio.c +++ b/arch/arm/mach-ep93xx/gpio.c | |||
| @@ -17,15 +17,16 @@ | |||
| 17 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 18 | #include <linux/seq_file.h> | 18 | #include <linux/seq_file.h> |
| 19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
| 20 | #include <linux/gpio.h> | ||
| 21 | #include <linux/irq.h> | ||
| 20 | 22 | ||
| 21 | #include <mach/ep93xx-regs.h> | 23 | #include <mach/hardware.h> |
| 22 | #include <asm/gpio.h> | ||
| 23 | 24 | ||
| 24 | struct ep93xx_gpio_chip { | 25 | struct ep93xx_gpio_chip { |
| 25 | struct gpio_chip chip; | 26 | struct gpio_chip chip; |
| 26 | 27 | ||
| 27 | unsigned int data_reg; | 28 | void __iomem *data_reg; |
| 28 | unsigned int data_dir_reg; | 29 | void __iomem *data_dir_reg; |
| 29 | }; | 30 | }; |
| 30 | 31 | ||
| 31 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) | 32 | #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip) |
| @@ -111,15 +112,61 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |||
| 111 | { | 112 | { |
| 112 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); | 113 | struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip); |
| 113 | u8 data_reg, data_dir_reg; | 114 | u8 data_reg, data_dir_reg; |
| 114 | int i; | 115 | int gpio, i; |
| 115 | 116 | ||
| 116 | data_reg = __raw_readb(ep93xx_chip->data_reg); | 117 | data_reg = __raw_readb(ep93xx_chip->data_reg); |
| 117 | data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); | 118 | data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg); |
| 118 | 119 | ||
| 119 | for (i = 0; i < chip->ngpio; i++) | 120 | gpio = ep93xx_chip->chip.base; |
| 120 | seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i, | 121 | for (i = 0; i < chip->ngpio; i++, gpio++) { |
| 121 | (data_reg & (1 << i)) ? "set" : "clear", | 122 | int is_out = data_dir_reg & (1 << i); |
| 122 | (data_dir_reg & (1 << i)) ? "out" : "in"); | 123 | |
| 124 | seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s", | ||
| 125 | chip->label, i, gpio, | ||
| 126 | gpiochip_is_requested(chip, i) ? : "", | ||
| 127 | is_out ? "out" : "in ", | ||
| 128 | (data_reg & (1 << i)) ? "hi" : "lo"); | ||
| 129 | |||
| 130 | if (!is_out) { | ||
| 131 | int irq = gpio_to_irq(gpio); | ||
| 132 | struct irq_desc *desc = irq_desc + irq; | ||
| 133 | |||
| 134 | if (irq >= 0 && desc->action) { | ||
| 135 | char *trigger; | ||
| 136 | |||
| 137 | switch (desc->status & IRQ_TYPE_SENSE_MASK) { | ||
| 138 | case IRQ_TYPE_NONE: | ||
| 139 | trigger = "(default)"; | ||
| 140 | break; | ||
| 141 | case IRQ_TYPE_EDGE_FALLING: | ||
| 142 | trigger = "edge-falling"; | ||
| 143 | break; | ||
| 144 | case IRQ_TYPE_EDGE_RISING: | ||
| 145 | trigger = "edge-rising"; | ||
| 146 | break; | ||
| 147 | case IRQ_TYPE_EDGE_BOTH: | ||
| 148 | trigger = "edge-both"; | ||
| 149 | break; | ||
| 150 | case IRQ_TYPE_LEVEL_HIGH: | ||
| 151 | trigger = "level-high"; | ||
| 152 | break; | ||
| 153 | case IRQ_TYPE_LEVEL_LOW: | ||
| 154 | trigger = "level-low"; | ||
| 155 | break; | ||
| 156 | default: | ||
| 157 | trigger = "?trigger?"; | ||
| 158 | break; | ||
| 159 | } | ||
| 160 | |||
| 161 | seq_printf(s, " irq-%d %s%s", | ||
| 162 | irq, trigger, | ||
| 163 | (desc->status & IRQ_WAKEUP) | ||
| 164 | ? " wakeup" : ""); | ||
| 165 | } | ||
| 166 | } | ||
| 167 | |||
| 168 | seq_printf(s, "\n"); | ||
| 169 | } | ||
| 123 | } | 170 | } |
| 124 | 171 | ||
| 125 | #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ | 172 | #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \ |
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 967c079180db..ea78e908fc82 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | |||
| @@ -52,40 +52,43 @@ | |||
| 52 | #define EP93XX_AHB_VIRT_BASE 0xfef00000 | 52 | #define EP93XX_AHB_VIRT_BASE 0xfef00000 |
| 53 | #define EP93XX_AHB_SIZE 0x00100000 | 53 | #define EP93XX_AHB_SIZE 0x00100000 |
| 54 | 54 | ||
| 55 | #define EP93XX_AHB_IOMEM(x) IOMEM(EP93XX_AHB_VIRT_BASE + (x)) | ||
| 56 | |||
| 55 | #define EP93XX_APB_PHYS_BASE 0x80800000 | 57 | #define EP93XX_APB_PHYS_BASE 0x80800000 |
| 56 | #define EP93XX_APB_VIRT_BASE 0xfed00000 | 58 | #define EP93XX_APB_VIRT_BASE 0xfed00000 |
| 57 | #define EP93XX_APB_SIZE 0x00200000 | 59 | #define EP93XX_APB_SIZE 0x00200000 |
| 58 | 60 | ||
| 61 | #define EP93XX_APB_IOMEM(x) IOMEM(EP93XX_APB_VIRT_BASE + (x)) | ||
| 62 | |||
| 59 | 63 | ||
| 60 | /* AHB peripherals */ | 64 | /* AHB peripherals */ |
| 61 | #define EP93XX_DMA_BASE ((void __iomem *) \ | 65 | #define EP93XX_DMA_BASE EP93XX_AHB_IOMEM(0x00000000) |
| 62 | (EP93XX_AHB_VIRT_BASE + 0x00000000)) | ||
| 63 | 66 | ||
| 64 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) | ||
| 65 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) | 67 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) |
| 68 | #define EP93XX_ETHERNET_BASE EP93XX_AHB_IOMEM(0x00010000) | ||
| 66 | 69 | ||
| 67 | #define EP93XX_USB_BASE (EP93XX_AHB_VIRT_BASE + 0x00020000) | ||
| 68 | #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) | 70 | #define EP93XX_USB_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00020000) |
| 71 | #define EP93XX_USB_BASE EP93XX_AHB_IOMEM(0x00020000) | ||
| 69 | 72 | ||
| 70 | #define EP93XX_RASTER_BASE (EP93XX_AHB_VIRT_BASE + 0x00030000) | 73 | #define EP93XX_RASTER_BASE EP93XX_AHB_IOMEM(0x00030000) |
| 71 | 74 | ||
| 72 | #define EP93XX_GRAPHICS_ACCEL_BASE (EP93XX_AHB_VIRT_BASE + 0x00040000) | 75 | #define EP93XX_GRAPHICS_ACCEL_BASE EP93XX_AHB_IOMEM(0x00040000) |
| 73 | 76 | ||
| 74 | #define EP93XX_SDRAM_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00060000) | 77 | #define EP93XX_SDRAM_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00060000) |
| 75 | 78 | ||
| 76 | #define EP93XX_PCMCIA_CONTROLLER_BASE (EP93XX_AHB_VIRT_BASE + 0x00080000) | 79 | #define EP93XX_PCMCIA_CONTROLLER_BASE EP93XX_AHB_IOMEM(0x00080000) |
| 77 | 80 | ||
| 78 | #define EP93XX_BOOT_ROM_BASE (EP93XX_AHB_VIRT_BASE + 0x00090000) | 81 | #define EP93XX_BOOT_ROM_BASE EP93XX_AHB_IOMEM(0x00090000) |
| 79 | 82 | ||
| 80 | #define EP93XX_IDE_BASE (EP93XX_AHB_VIRT_BASE + 0x000a0000) | 83 | #define EP93XX_IDE_BASE EP93XX_AHB_IOMEM(0x000a0000) |
| 81 | 84 | ||
| 82 | #define EP93XX_VIC1_BASE (EP93XX_AHB_VIRT_BASE + 0x000b0000) | 85 | #define EP93XX_VIC1_BASE EP93XX_AHB_IOMEM(0x000b0000) |
| 83 | 86 | ||
| 84 | #define EP93XX_VIC2_BASE (EP93XX_AHB_VIRT_BASE + 0x000c0000) | 87 | #define EP93XX_VIC2_BASE EP93XX_AHB_IOMEM(0x000c0000) |
| 85 | 88 | ||
| 86 | 89 | ||
| 87 | /* APB peripherals */ | 90 | /* APB peripherals */ |
| 88 | #define EP93XX_TIMER_BASE (EP93XX_APB_VIRT_BASE + 0x00010000) | 91 | #define EP93XX_TIMER_BASE EP93XX_APB_IOMEM(0x00010000) |
| 89 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) | 92 | #define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x)) |
| 90 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) | 93 | #define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00) |
| 91 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) | 94 | #define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04) |
| @@ -102,11 +105,11 @@ | |||
| 102 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) | 105 | #define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88) |
| 103 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) | 106 | #define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c) |
| 104 | 107 | ||
| 105 | #define EP93XX_I2S_BASE (EP93XX_APB_VIRT_BASE + 0x00020000) | 108 | #define EP93XX_I2S_BASE EP93XX_APB_IOMEM(0x00020000) |
| 106 | 109 | ||
| 107 | #define EP93XX_SECURITY_BASE (EP93XX_APB_VIRT_BASE + 0x00030000) | 110 | #define EP93XX_SECURITY_BASE EP93XX_APB_IOMEM(0x00030000) |
| 108 | 111 | ||
| 109 | #define EP93XX_GPIO_BASE (EP93XX_APB_VIRT_BASE + 0x00040000) | 112 | #define EP93XX_GPIO_BASE EP93XX_APB_IOMEM(0x00040000) |
| 110 | #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) | 113 | #define EP93XX_GPIO_REG(x) (EP93XX_GPIO_BASE + (x)) |
| 111 | #define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) | 114 | #define EP93XX_GPIO_F_INT_TYPE1 EP93XX_GPIO_REG(0x4c) |
| 112 | #define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) | 115 | #define EP93XX_GPIO_F_INT_TYPE2 EP93XX_GPIO_REG(0x50) |
| @@ -124,32 +127,33 @@ | |||
| 124 | #define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) | 127 | #define EP93XX_GPIO_B_INT_ENABLE EP93XX_GPIO_REG(0xb8) |
| 125 | #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) | 128 | #define EP93XX_GPIO_B_INT_STATUS EP93XX_GPIO_REG(0xbc) |
| 126 | 129 | ||
| 127 | #define EP93XX_AAC_BASE (EP93XX_APB_VIRT_BASE + 0x00080000) | 130 | #define EP93XX_AAC_BASE EP93XX_APB_IOMEM(0x00080000) |
| 128 | 131 | ||
| 129 | #define EP93XX_SPI_BASE (EP93XX_APB_VIRT_BASE + 0x000a0000) | 132 | #define EP93XX_SPI_BASE EP93XX_APB_IOMEM(0x000a0000) |
| 130 | 133 | ||
| 131 | #define EP93XX_IRDA_BASE (EP93XX_APB_VIRT_BASE + 0x000b0000) | 134 | #define EP93XX_IRDA_BASE EP93XX_APB_IOMEM(0x000b0000) |
| 132 | 135 | ||
| 133 | #define EP93XX_UART1_BASE (EP93XX_APB_VIRT_BASE + 0x000c0000) | ||
| 134 | #define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) | 136 | #define EP93XX_UART1_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000c0000) |
| 137 | #define EP93XX_UART1_BASE EP93XX_APB_IOMEM(0x000c0000) | ||
| 135 | 138 | ||
| 136 | #define EP93XX_UART2_BASE (EP93XX_APB_VIRT_BASE + 0x000d0000) | ||
| 137 | #define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) | 139 | #define EP93XX_UART2_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000d0000) |
| 140 | #define EP93XX_UART2_BASE EP93XX_APB_IOMEM(0x000d0000) | ||
| 138 | 141 | ||
| 139 | #define EP93XX_UART3_BASE (EP93XX_APB_VIRT_BASE + 0x000e0000) | ||
| 140 | #define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) | 142 | #define EP93XX_UART3_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x000e0000) |
| 143 | #define EP93XX_UART3_BASE EP93XX_APB_IOMEM(0x000e0000) | ||
| 141 | 144 | ||
| 142 | #define EP93XX_KEY_MATRIX_BASE (EP93XX_APB_VIRT_BASE + 0x000f0000) | 145 | #define EP93XX_KEY_MATRIX_BASE EP93XX_APB_IOMEM(0x000f0000) |
| 143 | 146 | ||
| 144 | #define EP93XX_ADC_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) | 147 | #define EP93XX_ADC_BASE EP93XX_APB_IOMEM(0x00100000) |
| 145 | #define EP93XX_TOUCHSCREEN_BASE (EP93XX_APB_VIRT_BASE + 0x00100000) | 148 | #define EP93XX_TOUCHSCREEN_BASE EP93XX_APB_IOMEM(0x00100000) |
| 146 | 149 | ||
| 147 | #define EP93XX_PWM_BASE (EP93XX_APB_VIRT_BASE + 0x00110000) | 150 | #define EP93XX_PWM_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00110000) |
| 151 | #define EP93XX_PWM_BASE EP93XX_APB_IOMEM(0x00110000) | ||
| 148 | 152 | ||
| 149 | #define EP93XX_RTC_BASE (EP93XX_APB_VIRT_BASE + 0x00120000) | ||
| 150 | #define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) | 153 | #define EP93XX_RTC_PHYS_BASE (EP93XX_APB_PHYS_BASE + 0x00120000) |
| 154 | #define EP93XX_RTC_BASE EP93XX_APB_IOMEM(0x00120000) | ||
| 151 | 155 | ||
| 152 | #define EP93XX_SYSCON_BASE (EP93XX_APB_VIRT_BASE + 0x00130000) | 156 | #define EP93XX_SYSCON_BASE EP93XX_APB_IOMEM(0x00130000) |
| 153 | #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) | 157 | #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x)) |
| 154 | #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) | 158 | #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00) |
| 155 | #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) | 159 | #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04) |
| @@ -172,14 +176,45 @@ | |||
| 172 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) | 176 | #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c) |
| 173 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) | 177 | #define EP93XX_SYSCON_CLOCK_SET1 EP93XX_SYSCON_REG(0x20) |
| 174 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) | 178 | #define EP93XX_SYSCON_CLOCK_SET2 EP93XX_SYSCON_REG(0x24) |
| 175 | #define EP93XX_SYSCON_DEVICE_CONFIG EP93XX_SYSCON_REG(0x80) | 179 | #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80) |
| 176 | #define EP93XX_SYSCON_DEVICE_CONFIG_U3EN (1<<24) | 180 | #define EP93XX_SYSCON_DEVCFG_SWRST (1<<31) |
| 177 | #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE (1<<23) | 181 | #define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30) |
| 178 | #define EP93XX_SYSCON_DEVICE_CONFIG_U2EN (1<<20) | 182 | #define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29) |
| 179 | #define EP93XX_SYSCON_DEVICE_CONFIG_U1EN (1<<18) | 183 | #define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28) |
| 184 | #define EP93XX_SYSCON_DEVCFG_GONK (1<<27) | ||
| 185 | #define EP93XX_SYSCON_DEVCFG_TONG (1<<26) | ||
| 186 | #define EP93XX_SYSCON_DEVCFG_MONG (1<<25) | ||
| 187 | #define EP93XX_SYSCON_DEVCFG_U3EN (1<<24) | ||
| 188 | #define EP93XX_SYSCON_DEVCFG_CPENA (1<<23) | ||
| 189 | #define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22) | ||
| 190 | #define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21) | ||
| 191 | #define EP93XX_SYSCON_DEVCFG_U2EN (1<<20) | ||
| 192 | #define EP93XX_SYSCON_DEVCFG_EXVC (1<<19) | ||
| 193 | #define EP93XX_SYSCON_DEVCFG_U1EN (1<<18) | ||
| 194 | #define EP93XX_SYSCON_DEVCFG_TIN (1<<17) | ||
| 195 | #define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15) | ||
| 196 | #define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14) | ||
| 197 | #define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13) | ||
| 198 | #define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12) | ||
| 199 | #define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11) | ||
| 200 | #define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10) | ||
| 201 | #define EP93XX_SYSCON_DEVCFG_PONG (1<<9) | ||
| 202 | #define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8) | ||
| 203 | #define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7) | ||
| 204 | #define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6) | ||
| 205 | #define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4) | ||
| 206 | #define EP93XX_SYSCON_DEVCFG_RAS (1<<3) | ||
| 207 | #define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2) | ||
| 208 | #define EP93XX_SYSCON_DEVCFG_KEYS (1<<1) | ||
| 209 | #define EP93XX_SYSCON_DEVCFG_SHENA (1<<0) | ||
| 210 | #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90) | ||
| 211 | #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31) | ||
| 212 | #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16) | ||
| 213 | #define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15) | ||
| 214 | #define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0) | ||
| 180 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) | 215 | #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0) |
| 181 | 216 | ||
| 182 | #define EP93XX_WATCHDOG_BASE (EP93XX_APB_VIRT_BASE + 0x00140000) | 217 | #define EP93XX_WATCHDOG_BASE EP93XX_APB_IOMEM(0x00140000) |
| 183 | 218 | ||
| 184 | 219 | ||
| 185 | #endif | 220 | #endif |
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h index 2866297310b7..349fa7cb72d5 100644 --- a/arch/arm/mach-ep93xx/include/mach/hardware.h +++ b/arch/arm/mach-ep93xx/include/mach/hardware.h | |||
| @@ -4,12 +4,23 @@ | |||
| 4 | #ifndef __ASM_ARCH_HARDWARE_H | 4 | #ifndef __ASM_ARCH_HARDWARE_H |
| 5 | #define __ASM_ARCH_HARDWARE_H | 5 | #define __ASM_ARCH_HARDWARE_H |
| 6 | 6 | ||
| 7 | #include "ep93xx-regs.h" | 7 | #include <mach/ep93xx-regs.h> |
| 8 | #include <mach/platform.h> | ||
| 8 | 9 | ||
| 9 | #define pcibios_assign_all_busses() 0 | 10 | #define pcibios_assign_all_busses() 0 |
| 10 | 11 | ||
| 11 | #include "platform.h" | 12 | /* |
| 13 | * The EP93xx has two external crystal oscillators. To generate the | ||
| 14 | * required high-frequency clocks, the processor uses two phase-locked- | ||
| 15 | * loops (PLLs) to multiply the incoming external clock signal to much | ||
| 16 | * higher frequencies that are then divided down by programmable dividers | ||
| 17 | * to produce the needed clocks. The PLLs operate independently of one | ||
| 18 | * another. | ||
| 19 | */ | ||
| 20 | #define EP93XX_EXT_CLK_RATE 14745600 | ||
| 21 | #define EP93XX_EXT_RTC_RATE 32768 | ||
| 12 | 22 | ||
| 13 | #include "ts72xx.h" | 23 | #define EP93XX_KEYTCHCLK_DIV4 (EP93XX_EXT_CLK_RATE / 4) |
| 24 | #define EP93XX_KEYTCHCLK_DIV16 (EP93XX_EXT_CLK_RATE / 16) | ||
| 14 | 25 | ||
| 15 | #endif | 26 | #endif |
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h index fd5f081cc8b7..cebcc1c53d63 100644 --- a/arch/arm/mach-ep93xx/include/mach/io.h +++ b/arch/arm/mach-ep93xx/include/mach/io.h | |||
| @@ -1,8 +1,21 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/mach-ep93xx/include/mach/io.h | 2 | * arch/arm/mach-ep93xx/include/mach/io.h |
| 3 | */ | 3 | */ |
| 4 | #ifndef __ASM_MACH_IO_H | ||
| 5 | #define __ASM_MACH_IO_H | ||
| 4 | 6 | ||
| 5 | #define IO_SPACE_LIMIT 0xffffffff | 7 | #define IO_SPACE_LIMIT 0xffffffff |
| 6 | 8 | ||
| 7 | #define __io(p) __typesafe_io(p) | 9 | #define __io(p) __typesafe_io(p) |
| 8 | #define __mem_pci(p) (p) | 10 | #define __mem_pci(p) (p) |
| 11 | |||
| 12 | /* | ||
| 13 | * A typesafe __io() variation for variable initialisers | ||
| 14 | */ | ||
| 15 | #ifdef __ASSEMBLER__ | ||
| 16 | #define IOMEM(p) p | ||
| 17 | #else | ||
| 18 | #define IOMEM(p) ((void __iomem __force *)(p)) | ||
| 19 | #endif | ||
| 20 | |||
| 21 | #endif /* __ASM_MACH_IO_H */ | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 05f0f4f2f3ce..5f5fa6574d34 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h | |||
| @@ -5,6 +5,7 @@ | |||
| 5 | #ifndef __ASSEMBLY__ | 5 | #ifndef __ASSEMBLY__ |
| 6 | 6 | ||
| 7 | struct i2c_board_info; | 7 | struct i2c_board_info; |
| 8 | struct platform_device; | ||
| 8 | 9 | ||
| 9 | struct ep93xx_eth_data | 10 | struct ep93xx_eth_data |
| 10 | { | 11 | { |
| @@ -15,8 +16,27 @@ struct ep93xx_eth_data | |||
| 15 | void ep93xx_map_io(void); | 16 | void ep93xx_map_io(void); |
| 16 | void ep93xx_init_irq(void); | 17 | void ep93xx_init_irq(void); |
| 17 | void ep93xx_init_time(unsigned long); | 18 | void ep93xx_init_time(unsigned long); |
| 19 | |||
| 20 | /* EP93xx System Controller software locked register write */ | ||
| 21 | void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg); | ||
| 22 | void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits); | ||
| 23 | |||
| 24 | static inline void ep93xx_devcfg_set_bits(unsigned int bits) | ||
| 25 | { | ||
| 26 | ep93xx_devcfg_set_clear(bits, 0x00); | ||
| 27 | } | ||
| 28 | |||
| 29 | static inline void ep93xx_devcfg_clear_bits(unsigned int bits) | ||
| 30 | { | ||
| 31 | ep93xx_devcfg_set_clear(0x00, bits); | ||
| 32 | } | ||
| 33 | |||
| 18 | void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); | 34 | void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr); |
| 19 | void ep93xx_register_i2c(struct i2c_board_info *devices, int num); | 35 | void ep93xx_register_i2c(struct i2c_board_info *devices, int num); |
| 36 | void ep93xx_register_pwm(int pwm0, int pwm1); | ||
| 37 | int ep93xx_pwm_acquire_gpio(struct platform_device *pdev); | ||
| 38 | void ep93xx_pwm_release_gpio(struct platform_device *pdev); | ||
| 39 | |||
| 20 | void ep93xx_init_devices(void); | 40 | void ep93xx_init_devices(void); |
| 21 | extern struct sys_timer ep93xx_timer; | 41 | extern struct sys_timer ep93xx_timer; |
| 22 | 42 | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index ed8f35e4f068..6d661fe9d66c 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h | |||
| @@ -11,15 +11,13 @@ static inline void arch_idle(void) | |||
| 11 | 11 | ||
| 12 | static inline void arch_reset(char mode, const char *cmd) | 12 | static inline void arch_reset(char mode, const char *cmd) |
| 13 | { | 13 | { |
| 14 | u32 devicecfg; | ||
| 15 | |||
| 16 | local_irq_disable(); | 14 | local_irq_disable(); |
| 17 | 15 | ||
| 18 | devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG); | 16 | /* |
| 19 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 17 | * Set then clear the SWRST bit to initiate a software reset |
| 20 | __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); | 18 | */ |
| 21 | __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); | 19 | ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST); |
| 22 | __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG); | 20 | ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST); |
| 23 | 21 | ||
| 24 | while (1) | 22 | while (1) |
| 25 | ; | 23 | ; |
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h index 34ddec081c40..2737666e800e 100644 --- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h +++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h | |||
| @@ -70,7 +70,6 @@ | |||
| 70 | 70 | ||
| 71 | 71 | ||
| 72 | #ifndef __ASSEMBLY__ | 72 | #ifndef __ASSEMBLY__ |
| 73 | #include <linux/io.h> | ||
| 74 | 73 | ||
| 75 | static inline int board_is_ts7200(void) | 74 | static inline int board_is_ts7200(void) |
| 76 | { | 75 | { |
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c index 15d6815d78c4..0a313e82fb74 100644 --- a/arch/arm/mach-ep93xx/micro9.c +++ b/arch/arm/mach-ep93xx/micro9.c | |||
| @@ -9,21 +9,16 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/interrupt.h> | ||
| 14 | #include <linux/ioport.h> | ||
| 15 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
| 16 | #include <linux/mm.h> | 13 | #include <linux/init.h> |
| 17 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 18 | #include <linux/sched.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/mtd/physmap.h> | 15 | #include <linux/mtd/physmap.h> |
| 22 | 16 | ||
| 23 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 24 | 18 | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 20 | #include <asm/mach/arch.h> | ||
| 21 | |||
| 27 | 22 | ||
| 28 | static struct ep93xx_eth_data micro9_eth_data = { | 23 | static struct ep93xx_eth_data micro9_eth_data = { |
| 29 | .phy_id = 0x1f, | 24 | .phy_id = 0x1f, |
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c index 7ee024d34829..5255dddd3067 100644 --- a/arch/arm/mach-ep93xx/ts72xx.c +++ b/arch/arm/mach-ep93xx/ts72xx.c | |||
| @@ -12,19 +12,18 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/init.h> | 14 | #include <linux/init.h> |
| 15 | #include <linux/mm.h> | ||
| 16 | #include <linux/sched.h> | ||
| 17 | #include <linux/interrupt.h> | ||
| 18 | #include <linux/ioport.h> | ||
| 19 | #include <linux/mtd/physmap.h> | ||
| 20 | #include <linux/platform_device.h> | 15 | #include <linux/platform_device.h> |
| 21 | #include <linux/m48t86.h> | ||
| 22 | #include <linux/io.h> | 16 | #include <linux/io.h> |
| 23 | #include <linux/i2c.h> | 17 | #include <linux/m48t86.h> |
| 18 | #include <linux/mtd/physmap.h> | ||
| 19 | |||
| 24 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 21 | #include <mach/ts72xx.h> | ||
| 22 | |||
| 25 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 26 | #include <asm/mach/arch.h> | ||
| 27 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
| 25 | #include <asm/mach/arch.h> | ||
| 26 | |||
| 28 | 27 | ||
| 29 | static struct map_desc ts72xx_io_desc[] __initdata = { | 28 | static struct map_desc ts72xx_io_desc[] __initdata = { |
| 30 | { | 29 | { |
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 452931b2690e..2a318eba1b07 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
| @@ -403,6 +403,8 @@ static unsigned int mmc_status(struct device *dev) | |||
| 403 | static struct mmc_platform_data mmc_data = { | 403 | static struct mmc_platform_data mmc_data = { |
| 404 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | 404 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 405 | .status = mmc_status, | 405 | .status = mmc_status, |
| 406 | .gpio_wp = -1, | ||
| 407 | .gpio_cd = -1, | ||
| 406 | }; | 408 | }; |
| 407 | 409 | ||
| 408 | static struct amba_device mmc_device = { | 410 | static struct amba_device mmc_device = { |
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index a2d7814896be..505d98cfe508 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | 19 | ||
| 20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
| 21 | #include <mach/dma.h> | 21 | #include <mach/dma.h> |
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/mux.h> | 22 | #include <mach/mux.h> |
| 24 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
| 25 | #include <mach/mcbsp.h> | 24 | #include <mach/mcbsp.h> |
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index d49dfb5e931f..d7288f1dc64f 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -19,7 +19,6 @@ | |||
| 19 | 19 | ||
| 20 | #include <mach/irqs.h> | 20 | #include <mach/irqs.h> |
| 21 | #include <mach/dma.h> | 21 | #include <mach/dma.h> |
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/mux.h> | 22 | #include <mach/mux.h> |
| 24 | #include <mach/cpu.h> | 23 | #include <mach/cpu.h> |
| 25 | #include <mach/mcbsp.h> | 24 | #include <mach/mcbsp.h> |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index facbd49eec67..dc3519c50ab2 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -221,6 +221,9 @@ arch_initcall(realview_i2c_init); | |||
| 221 | 221 | ||
| 222 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) | 222 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
| 223 | 223 | ||
| 224 | /* | ||
| 225 | * This is only used if GPIOLIB support is disabled | ||
| 226 | */ | ||
| 224 | static unsigned int realview_mmc_status(struct device *dev) | 227 | static unsigned int realview_mmc_status(struct device *dev) |
| 225 | { | 228 | { |
| 226 | struct amba_device *adev = container_of(dev, struct amba_device, dev); | 229 | struct amba_device *adev = container_of(dev, struct amba_device, dev); |
| @@ -237,11 +240,15 @@ static unsigned int realview_mmc_status(struct device *dev) | |||
| 237 | struct mmc_platform_data realview_mmc0_plat_data = { | 240 | struct mmc_platform_data realview_mmc0_plat_data = { |
| 238 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | 241 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 239 | .status = realview_mmc_status, | 242 | .status = realview_mmc_status, |
| 243 | .gpio_wp = 17, | ||
| 244 | .gpio_cd = 16, | ||
| 240 | }; | 245 | }; |
| 241 | 246 | ||
| 242 | struct mmc_platform_data realview_mmc1_plat_data = { | 247 | struct mmc_platform_data realview_mmc1_plat_data = { |
| 243 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | 248 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 244 | .status = realview_mmc_status, | 249 | .status = realview_mmc_status, |
| 250 | .gpio_wp = 19, | ||
| 251 | .gpio_cd = 18, | ||
| 245 | }; | 252 | }; |
| 246 | 253 | ||
| 247 | /* | 254 | /* |
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h new file mode 100644 index 000000000000..94ff27678a46 --- /dev/null +++ b/arch/arm/mach-realview/include/mach/gpio.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #include <asm-generic/gpio.h> | ||
| 2 | |||
| 3 | #define gpio_get_value __gpio_get_value | ||
| 4 | #define gpio_set_value __gpio_set_value | ||
| 5 | #define gpio_cansleep __gpio_cansleep | ||
| 6 | #define gpio_to_irq __gpio_to_irq | ||
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index 8dfa44e08a94..abd13b448671 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/amba/bus.h> | 25 | #include <linux/amba/bus.h> |
| 26 | #include <linux/amba/pl061.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -113,6 +114,21 @@ static void __init realview_eb_map_io(void) | |||
| 113 | iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); | 114 | iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc)); |
| 114 | } | 115 | } |
| 115 | 116 | ||
| 117 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 118 | .gpio_base = 0, | ||
| 119 | .irq_base = -1, | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 123 | .gpio_base = 8, | ||
| 124 | .irq_base = -1, | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 128 | .gpio_base = 16, | ||
| 129 | .irq_base = -1, | ||
| 130 | }; | ||
| 131 | |||
| 116 | /* | 132 | /* |
| 117 | * RealView EB AMBA devices | 133 | * RealView EB AMBA devices |
| 118 | */ | 134 | */ |
| @@ -189,9 +205,9 @@ AMBA_DEVICE(clcd, "dev:20", EB_CLCD, &clcd_plat_data); | |||
| 189 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); | 205 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); |
| 190 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 206 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 191 | AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); | 207 | AMBA_DEVICE(wdog, "dev:e1", EB_WATCHDOG, NULL); |
| 192 | AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, NULL); | 208 | AMBA_DEVICE(gpio0, "dev:e4", EB_GPIO0, &gpio0_plat_data); |
| 193 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 209 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 194 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 210 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 195 | AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); | 211 | AMBA_DEVICE(rtc, "dev:e8", EB_RTC, NULL); |
| 196 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 212 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 197 | AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); | 213 | AMBA_DEVICE(uart0, "dev:f1", EB_UART0, NULL); |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 25efe71a67c7..17fbb0e889b6 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/amba/bus.h> | 25 | #include <linux/amba/bus.h> |
| 26 | #include <linux/amba/pl061.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -107,6 +108,21 @@ static void __init realview_pb1176_map_io(void) | |||
| 107 | iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc)); | 108 | iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc)); |
| 108 | } | 109 | } |
| 109 | 110 | ||
| 111 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 112 | .gpio_base = 0, | ||
| 113 | .irq_base = -1, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 117 | .gpio_base = 8, | ||
| 118 | .irq_base = -1, | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 122 | .gpio_base = 16, | ||
| 123 | .irq_base = -1, | ||
| 124 | }; | ||
| 125 | |||
| 110 | /* | 126 | /* |
| 111 | * RealView PB1176 AMBA devices | 127 | * RealView PB1176 AMBA devices |
| 112 | */ | 128 | */ |
| @@ -164,9 +180,9 @@ AMBA_DEVICE(uart3, "fpga:09", PB1176_UART3, NULL); | |||
| 164 | AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL); | 180 | AMBA_DEVICE(smc, "dev:00", PB1176_SMC, NULL); |
| 165 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 181 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 166 | AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL); | 182 | AMBA_DEVICE(wdog, "dev:e1", PB1176_WATCHDOG, NULL); |
| 167 | AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, NULL); | 183 | AMBA_DEVICE(gpio0, "dev:e4", PB1176_GPIO0, &gpio0_plat_data); |
| 168 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 184 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 169 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 185 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 170 | AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL); | 186 | AMBA_DEVICE(rtc, "dev:e8", PB1176_RTC, NULL); |
| 171 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 187 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 172 | AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL); | 188 | AMBA_DEVICE(uart0, "dev:f1", PB1176_UART0, NULL); |
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index dc4b16943907..fdd042b85f40 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/amba/bus.h> | 25 | #include <linux/amba/bus.h> |
| 26 | #include <linux/amba/pl061.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -108,6 +109,21 @@ static void __init realview_pb11mp_map_io(void) | |||
| 108 | iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); | 109 | iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc)); |
| 109 | } | 110 | } |
| 110 | 111 | ||
| 112 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 113 | .gpio_base = 0, | ||
| 114 | .irq_base = -1, | ||
| 115 | }; | ||
| 116 | |||
| 117 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 118 | .gpio_base = 8, | ||
| 119 | .irq_base = -1, | ||
| 120 | }; | ||
| 121 | |||
| 122 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 123 | .gpio_base = 16, | ||
| 124 | .irq_base = -1, | ||
| 125 | }; | ||
| 126 | |||
| 111 | /* | 127 | /* |
| 112 | * RealView PB11MPCore AMBA devices | 128 | * RealView PB11MPCore AMBA devices |
| 113 | */ | 129 | */ |
| @@ -166,9 +182,9 @@ AMBA_DEVICE(uart3, "fpga:09", PB11MP_UART3, NULL); | |||
| 166 | AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL); | 182 | AMBA_DEVICE(smc, "dev:00", PB11MP_SMC, NULL); |
| 167 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 183 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 168 | AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL); | 184 | AMBA_DEVICE(wdog, "dev:e1", PB11MP_WATCHDOG, NULL); |
| 169 | AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, NULL); | 185 | AMBA_DEVICE(gpio0, "dev:e4", PB11MP_GPIO0, &gpio0_plat_data); |
| 170 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 186 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 171 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 187 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 172 | AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL); | 188 | AMBA_DEVICE(rtc, "dev:e8", PB11MP_RTC, NULL); |
| 173 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 189 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 174 | AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL); | 190 | AMBA_DEVICE(uart0, "dev:f1", PB11MP_UART0, NULL); |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index d6ac1eb86576..70bba9900d97 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/platform_device.h> | 23 | #include <linux/platform_device.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/amba/bus.h> | 25 | #include <linux/amba/bus.h> |
| 26 | #include <linux/amba/pl061.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| 28 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
| @@ -98,6 +99,21 @@ static void __init realview_pba8_map_io(void) | |||
| 98 | iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc)); | 99 | iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc)); |
| 99 | } | 100 | } |
| 100 | 101 | ||
| 102 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 103 | .gpio_base = 0, | ||
| 104 | .irq_base = -1, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 108 | .gpio_base = 8, | ||
| 109 | .irq_base = -1, | ||
| 110 | }; | ||
| 111 | |||
| 112 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 113 | .gpio_base = 16, | ||
| 114 | .irq_base = -1, | ||
| 115 | }; | ||
| 116 | |||
| 101 | /* | 117 | /* |
| 102 | * RealView PBA8Core AMBA devices | 118 | * RealView PBA8Core AMBA devices |
| 103 | */ | 119 | */ |
| @@ -156,9 +172,9 @@ AMBA_DEVICE(uart3, "fpga:09", PBA8_UART3, NULL); | |||
| 156 | AMBA_DEVICE(smc, "dev:00", PBA8_SMC, NULL); | 172 | AMBA_DEVICE(smc, "dev:00", PBA8_SMC, NULL); |
| 157 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 173 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 158 | AMBA_DEVICE(wdog, "dev:e1", PBA8_WATCHDOG, NULL); | 174 | AMBA_DEVICE(wdog, "dev:e1", PBA8_WATCHDOG, NULL); |
| 159 | AMBA_DEVICE(gpio0, "dev:e4", PBA8_GPIO0, NULL); | 175 | AMBA_DEVICE(gpio0, "dev:e4", PBA8_GPIO0, &gpio0_plat_data); |
| 160 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 176 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 161 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 177 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 162 | AMBA_DEVICE(rtc, "dev:e8", PBA8_RTC, NULL); | 178 | AMBA_DEVICE(rtc, "dev:e8", PBA8_RTC, NULL); |
| 163 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 179 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 164 | AMBA_DEVICE(uart0, "dev:f1", PBA8_UART0, NULL); | 180 | AMBA_DEVICE(uart0, "dev:f1", PBA8_UART0, NULL); |
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c index ede2a57240a3..ce6c5d25fbef 100644 --- a/arch/arm/mach-realview/realview_pbx.c +++ b/arch/arm/mach-realview/realview_pbx.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/sysdev.h> | 23 | #include <linux/sysdev.h> |
| 24 | #include <linux/amba/bus.h> | 24 | #include <linux/amba/bus.h> |
| 25 | #include <linux/amba/pl061.h> | ||
| 25 | #include <linux/io.h> | 26 | #include <linux/io.h> |
| 26 | 27 | ||
| 27 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| @@ -118,6 +119,21 @@ static void __init realview_pbx_map_io(void) | |||
| 118 | iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc)); | 119 | iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc)); |
| 119 | } | 120 | } |
| 120 | 121 | ||
| 122 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 123 | .gpio_base = 0, | ||
| 124 | .irq_base = -1, | ||
| 125 | }; | ||
| 126 | |||
| 127 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 128 | .gpio_base = 8, | ||
| 129 | .irq_base = -1, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 133 | .gpio_base = 16, | ||
| 134 | .irq_base = -1, | ||
| 135 | }; | ||
| 136 | |||
| 121 | /* | 137 | /* |
| 122 | * RealView PBXCore AMBA devices | 138 | * RealView PBXCore AMBA devices |
| 123 | */ | 139 | */ |
| @@ -176,9 +192,9 @@ AMBA_DEVICE(uart3, "fpga:09", PBX_UART3, NULL); | |||
| 176 | AMBA_DEVICE(smc, "dev:00", PBX_SMC, NULL); | 192 | AMBA_DEVICE(smc, "dev:00", PBX_SMC, NULL); |
| 177 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 193 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 178 | AMBA_DEVICE(wdog, "dev:e1", PBX_WATCHDOG, NULL); | 194 | AMBA_DEVICE(wdog, "dev:e1", PBX_WATCHDOG, NULL); |
| 179 | AMBA_DEVICE(gpio0, "dev:e4", PBX_GPIO0, NULL); | 195 | AMBA_DEVICE(gpio0, "dev:e4", PBX_GPIO0, &gpio0_plat_data); |
| 180 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 196 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 181 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 197 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 182 | AMBA_DEVICE(rtc, "dev:e8", PBX_RTC, NULL); | 198 | AMBA_DEVICE(rtc, "dev:e8", PBX_RTC, NULL); |
| 183 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 199 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 184 | AMBA_DEVICE(uart0, "dev:f1", PBX_UART0, NULL); | 200 | AMBA_DEVICE(uart0, "dev:f1", PBX_UART0, NULL); |
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c index 3138d3955c9e..585cc013639d 100644 --- a/arch/arm/mach-u300/mmc.c +++ b/arch/arm/mach-u300/mmc.c | |||
| @@ -156,6 +156,8 @@ int __devinit mmc_init(struct amba_device *adev) | |||
| 156 | mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29; | 156 | mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29; |
| 157 | mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd; | 157 | mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd; |
| 158 | mmci_card->mmc0_plat_data.status = mmc_status; | 158 | mmci_card->mmc0_plat_data.status = mmc_status; |
| 159 | mmci_card->mmc0_plat_data.gpio_wp = -1; | ||
| 160 | mmci_card->mmc0_plat_data.gpio_cd = -1; | ||
| 159 | 161 | ||
| 160 | mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; | 162 | mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; |
| 161 | 163 | ||
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 31093af7d052..975eae41ee66 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
| @@ -26,6 +26,7 @@ | |||
| 26 | #include <linux/interrupt.h> | 26 | #include <linux/interrupt.h> |
| 27 | #include <linux/amba/bus.h> | 27 | #include <linux/amba/bus.h> |
| 28 | #include <linux/amba/clcd.h> | 28 | #include <linux/amba/clcd.h> |
| 29 | #include <linux/amba/pl061.h> | ||
| 29 | #include <linux/clocksource.h> | 30 | #include <linux/clocksource.h> |
| 30 | #include <linux/clockchips.h> | 31 | #include <linux/clockchips.h> |
| 31 | #include <linux/cnt32_to_63.h> | 32 | #include <linux/cnt32_to_63.h> |
| @@ -371,6 +372,8 @@ unsigned int mmc_status(struct device *dev) | |||
| 371 | static struct mmc_platform_data mmc0_plat_data = { | 372 | static struct mmc_platform_data mmc0_plat_data = { |
| 372 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | 373 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 373 | .status = mmc_status, | 374 | .status = mmc_status, |
| 375 | .gpio_wp = -1, | ||
| 376 | .gpio_cd = -1, | ||
| 374 | }; | 377 | }; |
| 375 | 378 | ||
| 376 | /* | 379 | /* |
| @@ -705,6 +708,16 @@ static struct clcd_board clcd_plat_data = { | |||
| 705 | .remove = versatile_clcd_remove, | 708 | .remove = versatile_clcd_remove, |
| 706 | }; | 709 | }; |
| 707 | 710 | ||
| 711 | static struct pl061_platform_data gpio0_plat_data = { | ||
| 712 | .gpio_base = 0, | ||
| 713 | .irq_base = IRQ_GPIO0_START, | ||
| 714 | }; | ||
| 715 | |||
| 716 | static struct pl061_platform_data gpio1_plat_data = { | ||
| 717 | .gpio_base = 8, | ||
| 718 | .irq_base = IRQ_GPIO1_START, | ||
| 719 | }; | ||
| 720 | |||
| 708 | #define AACI_IRQ { IRQ_AACI, NO_IRQ } | 721 | #define AACI_IRQ { IRQ_AACI, NO_IRQ } |
| 709 | #define AACI_DMA { 0x80, 0x81 } | 722 | #define AACI_DMA { 0x80, 0x81 } |
| 710 | #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } | 723 | #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B } |
| @@ -767,8 +780,8 @@ AMBA_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data); | |||
| 767 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); | 780 | AMBA_DEVICE(dmac, "dev:30", DMAC, NULL); |
| 768 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); | 781 | AMBA_DEVICE(sctl, "dev:e0", SCTL, NULL); |
| 769 | AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); | 782 | AMBA_DEVICE(wdog, "dev:e1", WATCHDOG, NULL); |
| 770 | AMBA_DEVICE(gpio0, "dev:e4", GPIO0, NULL); | 783 | AMBA_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data); |
| 771 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, NULL); | 784 | AMBA_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data); |
| 772 | AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); | 785 | AMBA_DEVICE(rtc, "dev:e8", RTC, NULL); |
| 773 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); | 786 | AMBA_DEVICE(sci0, "dev:f0", SCI, NULL); |
| 774 | AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); | 787 | AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); |
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h new file mode 100644 index 000000000000..94ff27678a46 --- /dev/null +++ b/arch/arm/mach-versatile/include/mach/gpio.h | |||
| @@ -0,0 +1,6 @@ | |||
| 1 | #include <asm-generic/gpio.h> | ||
| 2 | |||
| 3 | #define gpio_get_value __gpio_get_value | ||
| 4 | #define gpio_set_value __gpio_set_value | ||
| 5 | #define gpio_cansleep __gpio_cansleep | ||
| 6 | #define gpio_to_irq __gpio_to_irq | ||
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h index 9bfdb30e1f3f..bf44c61bd1f6 100644 --- a/arch/arm/mach-versatile/include/mach/irqs.h +++ b/arch/arm/mach-versatile/include/mach/irqs.h | |||
| @@ -122,4 +122,13 @@ | |||
| 122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | 122 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) |
| 123 | #define IRQ_SIC_END 63 | 123 | #define IRQ_SIC_END 63 |
| 124 | 124 | ||
| 125 | #define NR_IRQS 64 | 125 | #define IRQ_GPIO0_START (IRQ_SIC_END + 1) |
| 126 | #define IRQ_GPIO0_END (IRQ_GPIO0_START + 31) | ||
| 127 | #define IRQ_GPIO1_START (IRQ_GPIO0_END + 1) | ||
| 128 | #define IRQ_GPIO1_END (IRQ_GPIO1_START + 31) | ||
| 129 | #define IRQ_GPIO2_START (IRQ_GPIO1_END + 1) | ||
| 130 | #define IRQ_GPIO2_END (IRQ_GPIO2_START + 31) | ||
| 131 | #define IRQ_GPIO3_START (IRQ_GPIO2_END + 1) | ||
| 132 | #define IRQ_GPIO3_END (IRQ_GPIO3_START + 31) | ||
| 133 | |||
| 134 | #define NR_IRQS (IRQ_GPIO3_END + 1) | ||
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c index aa051c0884f8..9af8d8154df5 100644 --- a/arch/arm/mach-versatile/versatile_pb.c +++ b/arch/arm/mach-versatile/versatile_pb.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/device.h> | 23 | #include <linux/device.h> |
| 24 | #include <linux/sysdev.h> | 24 | #include <linux/sysdev.h> |
| 25 | #include <linux/amba/bus.h> | 25 | #include <linux/amba/bus.h> |
| 26 | #include <linux/amba/pl061.h> | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| 28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -43,6 +44,18 @@ | |||
| 43 | static struct mmc_platform_data mmc1_plat_data = { | 44 | static struct mmc_platform_data mmc1_plat_data = { |
| 44 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | 45 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, |
| 45 | .status = mmc_status, | 46 | .status = mmc_status, |
| 47 | .gpio_wp = -1, | ||
| 48 | .gpio_cd = -1, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct pl061_platform_data gpio2_plat_data = { | ||
| 52 | .gpio_base = 16, | ||
| 53 | .irq_base = IRQ_GPIO2_START, | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct pl061_platform_data gpio3_plat_data = { | ||
| 57 | .gpio_base = 24, | ||
| 58 | .irq_base = IRQ_GPIO3_START, | ||
| 46 | }; | 59 | }; |
| 47 | 60 | ||
| 48 | #define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } | 61 | #define UART3_IRQ { IRQ_SIC_UART3, NO_IRQ } |
| @@ -70,8 +83,8 @@ AMBA_DEVICE(sci1, "fpga:0a", SCI1, NULL); | |||
| 70 | AMBA_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); | 83 | AMBA_DEVICE(mmc1, "fpga:0b", MMCI1, &mmc1_plat_data); |
| 71 | 84 | ||
| 72 | /* DevChip Primecells */ | 85 | /* DevChip Primecells */ |
| 73 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, NULL); | 86 | AMBA_DEVICE(gpio2, "dev:e6", GPIO2, &gpio2_plat_data); |
| 74 | AMBA_DEVICE(gpio3, "dev:e7", GPIO3, NULL); | 87 | AMBA_DEVICE(gpio3, "dev:e7", GPIO3, &gpio3_plat_data); |
| 75 | 88 | ||
| 76 | static struct amba_device *amba_devs[] __initdata = { | 89 | static struct amba_device *amba_devs[] __initdata = { |
| 77 | &uart3_device, | 90 | &uart3_device, |
diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig index 8e4178fe5ec2..69bab32a8bc2 100644 --- a/arch/arm/mach-w90x900/Kconfig +++ b/arch/arm/mach-w90x900/Kconfig | |||
| @@ -5,6 +5,16 @@ config CPU_W90P910 | |||
| 5 | help | 5 | help |
| 6 | Support for W90P910 of Nuvoton W90X900 CPUs. | 6 | Support for W90P910 of Nuvoton W90X900 CPUs. |
| 7 | 7 | ||
| 8 | config CPU_NUC950 | ||
| 9 | bool | ||
| 10 | help | ||
| 11 | Support for NUCP950 of Nuvoton NUC900 CPUs. | ||
| 12 | |||
| 13 | config CPU_NUC960 | ||
| 14 | bool | ||
| 15 | help | ||
| 16 | Support for NUCP960 of Nuvoton NUC900 CPUs. | ||
| 17 | |||
| 8 | menu "W90P910 Machines" | 18 | menu "W90P910 Machines" |
| 9 | 19 | ||
| 10 | config MACH_W90P910EVB | 20 | config MACH_W90P910EVB |
| @@ -16,4 +26,24 @@ config MACH_W90P910EVB | |||
| 16 | 26 | ||
| 17 | endmenu | 27 | endmenu |
| 18 | 28 | ||
| 29 | menu "NUC950 Machines" | ||
| 30 | |||
| 31 | config MACH_W90P950EVB | ||
| 32 | bool "Nuvoton NUC950 Evaluation Board" | ||
| 33 | select CPU_NUC950 | ||
| 34 | help | ||
| 35 | Say Y here if you are using the Nuvoton NUC950EVB | ||
| 36 | |||
| 37 | endmenu | ||
| 38 | |||
| 39 | menu "NUC960 Machines" | ||
| 40 | |||
| 41 | config MACH_W90N960EVB | ||
| 42 | bool "Nuvoton NUC960 Evaluation Board" | ||
| 43 | select CPU_NUC960 | ||
| 44 | help | ||
| 45 | Say Y here if you are using the Nuvoton NUC960EVB | ||
| 46 | |||
| 47 | endmenu | ||
| 48 | |||
| 19 | endif | 49 | endif |
diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile index d50c94f4dbdf..828c0326441e 100644 --- a/arch/arm/mach-w90x900/Makefile +++ b/arch/arm/mach-w90x900/Makefile | |||
| @@ -4,12 +4,16 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := irq.o time.o mfp-w90p910.o gpio.o clock.o | 7 | obj-y := irq.o time.o mfp.o gpio.o clock.o |
| 8 | 8 | obj-y += clksel.o dev.o cpu.o | |
| 9 | # W90X900 CPU support files | 9 | # W90X900 CPU support files |
| 10 | 10 | ||
| 11 | obj-$(CONFIG_CPU_W90P910) += w90p910.o | 11 | obj-$(CONFIG_CPU_W90P910) += nuc910.o |
| 12 | obj-$(CONFIG_CPU_NUC950) += nuc950.o | ||
| 13 | obj-$(CONFIG_CPU_NUC960) += nuc960.o | ||
| 12 | 14 | ||
| 13 | # machine support | 15 | # machine support |
| 14 | 16 | ||
| 15 | obj-$(CONFIG_MACH_W90P910EVB) += mach-w90p910evb.o | 17 | obj-$(CONFIG_MACH_W90P910EVB) += mach-nuc910evb.o |
| 18 | obj-$(CONFIG_MACH_W90P950EVB) += mach-nuc950evb.o | ||
| 19 | obj-$(CONFIG_MACH_W90N960EVB) += mach-nuc960evb.o | ||
diff --git a/arch/arm/mach-w90x900/clksel.c b/arch/arm/mach-w90x900/clksel.c new file mode 100644 index 000000000000..3de4a5211c3b --- /dev/null +++ b/arch/arm/mach-w90x900/clksel.c | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/clksel.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation;version 2 of the License. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/device.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/string.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | #include <linux/mutex.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/regs-clock.h> | ||
| 26 | |||
| 27 | #define PLL0 0x00 | ||
| 28 | #define PLL1 0x01 | ||
| 29 | #define OTHER 0x02 | ||
| 30 | #define EXT 0x03 | ||
| 31 | #define MSOFFSET 0x0C | ||
| 32 | #define ATAOFFSET 0x0a | ||
| 33 | #define LCDOFFSET 0x06 | ||
| 34 | #define AUDOFFSET 0x04 | ||
| 35 | #define CPUOFFSET 0x00 | ||
| 36 | |||
| 37 | static DEFINE_MUTEX(clksel_sem); | ||
| 38 | |||
| 39 | static void clock_source_select(const char *dev_id, unsigned int clkval) | ||
| 40 | { | ||
| 41 | unsigned int clksel, offset; | ||
| 42 | |||
| 43 | clksel = __raw_readl(REG_CLKSEL); | ||
| 44 | |||
| 45 | if (strcmp(dev_id, "nuc900-ms") == 0) | ||
| 46 | offset = MSOFFSET; | ||
| 47 | else if (strcmp(dev_id, "nuc900-atapi") == 0) | ||
| 48 | offset = ATAOFFSET; | ||
| 49 | else if (strcmp(dev_id, "nuc900-lcd") == 0) | ||
| 50 | offset = LCDOFFSET; | ||
| 51 | else if (strcmp(dev_id, "nuc900-audio") == 0) | ||
| 52 | offset = AUDOFFSET; | ||
| 53 | else | ||
| 54 | offset = CPUOFFSET; | ||
| 55 | |||
| 56 | clksel &= ~(0x03 << offset); | ||
| 57 | clksel |= (clkval << offset); | ||
| 58 | |||
| 59 | __raw_writel(clksel, REG_CLKSEL); | ||
| 60 | } | ||
| 61 | |||
| 62 | void nuc900_clock_source(struct device *dev, unsigned char *src) | ||
| 63 | { | ||
| 64 | unsigned int clkval; | ||
| 65 | const char *dev_id; | ||
| 66 | |||
| 67 | BUG_ON(!src); | ||
| 68 | clkval = 0; | ||
| 69 | |||
| 70 | mutex_lock(&clksel_sem); | ||
| 71 | |||
| 72 | if (dev) | ||
| 73 | dev_id = dev_name(dev); | ||
| 74 | else | ||
| 75 | dev_id = "cpufreq"; | ||
| 76 | |||
| 77 | if (strcmp(src, "pll0") == 0) | ||
| 78 | clkval = PLL0; | ||
| 79 | else if (strcmp(src, "pll1") == 0) | ||
| 80 | clkval = PLL1; | ||
| 81 | else if (strcmp(src, "ext") == 0) | ||
| 82 | clkval = EXT; | ||
| 83 | else if (strcmp(src, "oth") == 0) | ||
| 84 | clkval = OTHER; | ||
| 85 | |||
| 86 | clock_source_select(dev_id, clkval); | ||
| 87 | |||
| 88 | mutex_unlock(&clksel_sem); | ||
| 89 | } | ||
| 90 | EXPORT_SYMBOL(nuc900_clock_source); | ||
| 91 | |||
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c index f420613cd395..b785994bab0a 100644 --- a/arch/arm/mach-w90x900/clock.c +++ b/arch/arm/mach-w90x900/clock.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | 25 | ||
| 26 | #include "clock.h" | 26 | #include "clock.h" |
| 27 | 27 | ||
| 28 | #define SUBCLK 0x24 | ||
| 29 | |||
| 28 | static DEFINE_SPINLOCK(clocks_lock); | 30 | static DEFINE_SPINLOCK(clocks_lock); |
| 29 | 31 | ||
| 30 | int clk_enable(struct clk *clk) | 32 | int clk_enable(struct clk *clk) |
| @@ -53,7 +55,13 @@ void clk_disable(struct clk *clk) | |||
| 53 | } | 55 | } |
| 54 | EXPORT_SYMBOL(clk_disable); | 56 | EXPORT_SYMBOL(clk_disable); |
| 55 | 57 | ||
| 56 | void w90x900_clk_enable(struct clk *clk, int enable) | 58 | unsigned long clk_get_rate(struct clk *clk) |
| 59 | { | ||
| 60 | return 15000000; | ||
| 61 | } | ||
| 62 | EXPORT_SYMBOL(clk_get_rate); | ||
| 63 | |||
| 64 | void nuc900_clk_enable(struct clk *clk, int enable) | ||
| 57 | { | 65 | { |
| 58 | unsigned int clocks = clk->cken; | 66 | unsigned int clocks = clk->cken; |
| 59 | unsigned long clken; | 67 | unsigned long clken; |
| @@ -68,6 +76,22 @@ void w90x900_clk_enable(struct clk *clk, int enable) | |||
| 68 | __raw_writel(clken, W90X900_VA_CLKPWR); | 76 | __raw_writel(clken, W90X900_VA_CLKPWR); |
| 69 | } | 77 | } |
| 70 | 78 | ||
| 79 | void nuc900_subclk_enable(struct clk *clk, int enable) | ||
| 80 | { | ||
| 81 | unsigned int clocks = clk->cken; | ||
| 82 | unsigned long clken; | ||
| 83 | |||
| 84 | clken = __raw_readl(W90X900_VA_CLKPWR + SUBCLK); | ||
| 85 | |||
| 86 | if (enable) | ||
| 87 | clken |= clocks; | ||
| 88 | else | ||
| 89 | clken &= ~clocks; | ||
| 90 | |||
| 91 | __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK); | ||
| 92 | } | ||
| 93 | |||
| 94 | |||
| 71 | void clks_register(struct clk_lookup *clks, size_t num) | 95 | void clks_register(struct clk_lookup *clks, size_t num) |
| 72 | { | 96 | { |
| 73 | int i; | 97 | int i; |
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h index 4f27bda76d56..f5816a06eed6 100644 --- a/arch/arm/mach-w90x900/clock.h +++ b/arch/arm/mach-w90x900/clock.h | |||
| @@ -12,7 +12,8 @@ | |||
| 12 | 12 | ||
| 13 | #include <asm/clkdev.h> | 13 | #include <asm/clkdev.h> |
| 14 | 14 | ||
| 15 | void w90x900_clk_enable(struct clk *clk, int enable); | 15 | void nuc900_clk_enable(struct clk *clk, int enable); |
| 16 | void nuc900_subclk_enable(struct clk *clk, int enable); | ||
| 16 | void clks_register(struct clk_lookup *clks, size_t num); | 17 | void clks_register(struct clk_lookup *clks, size_t num); |
| 17 | 18 | ||
| 18 | struct clk { | 19 | struct clk { |
| @@ -23,10 +24,17 @@ struct clk { | |||
| 23 | 24 | ||
| 24 | #define DEFINE_CLK(_name, _ctrlbit) \ | 25 | #define DEFINE_CLK(_name, _ctrlbit) \ |
| 25 | struct clk clk_##_name = { \ | 26 | struct clk clk_##_name = { \ |
| 26 | .enable = w90x900_clk_enable, \ | 27 | .enable = nuc900_clk_enable, \ |
| 27 | .cken = (1 << _ctrlbit), \ | 28 | .cken = (1 << _ctrlbit), \ |
| 28 | } | 29 | } |
| 29 | 30 | ||
| 31 | #define DEFINE_SUBCLK(_name, _ctrlbit) \ | ||
| 32 | struct clk clk_##_name = { \ | ||
| 33 | .enable = nuc900_subclk_enable, \ | ||
| 34 | .cken = (1 << _ctrlbit), \ | ||
| 35 | } | ||
| 36 | |||
| 37 | |||
| 30 | #define DEF_CLKLOOK(_clk, _devname, _conname) \ | 38 | #define DEF_CLKLOOK(_clk, _devname, _conname) \ |
| 31 | { \ | 39 | { \ |
| 32 | .clk = _clk, \ | 40 | .clk = _clk, \ |
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c new file mode 100644 index 000000000000..921cef991bf0 --- /dev/null +++ b/arch/arm/mach-w90x900/cpu.c | |||
| @@ -0,0 +1,212 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/cpu.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Nuvoton corporation. | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * NUC900 series cpu common support | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/list.h> | ||
| 20 | #include <linux/timer.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/serial_8250.h> | ||
| 25 | #include <linux/delay.h> | ||
| 26 | |||
| 27 | #include <asm/mach/arch.h> | ||
| 28 | #include <asm/mach/map.h> | ||
| 29 | #include <asm/mach/irq.h> | ||
| 30 | #include <asm/irq.h> | ||
| 31 | |||
| 32 | #include <mach/hardware.h> | ||
| 33 | #include <mach/regs-serial.h> | ||
| 34 | #include <mach/regs-clock.h> | ||
| 35 | #include <mach/regs-ebi.h> | ||
| 36 | |||
| 37 | #include "cpu.h" | ||
| 38 | #include "clock.h" | ||
| 39 | |||
| 40 | /* Initial IO mappings */ | ||
| 41 | |||
| 42 | static struct map_desc nuc900_iodesc[] __initdata = { | ||
| 43 | IODESC_ENT(IRQ), | ||
| 44 | IODESC_ENT(GCR), | ||
| 45 | IODESC_ENT(UART), | ||
| 46 | IODESC_ENT(TIMER), | ||
| 47 | IODESC_ENT(EBI), | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* Initial clock declarations. */ | ||
| 51 | static DEFINE_CLK(lcd, 0); | ||
| 52 | static DEFINE_CLK(audio, 1); | ||
| 53 | static DEFINE_CLK(fmi, 4); | ||
| 54 | static DEFINE_SUBCLK(ms, 0); | ||
| 55 | static DEFINE_SUBCLK(sd, 1); | ||
| 56 | static DEFINE_CLK(dmac, 5); | ||
| 57 | static DEFINE_CLK(atapi, 6); | ||
| 58 | static DEFINE_CLK(emc, 7); | ||
| 59 | static DEFINE_SUBCLK(rmii, 2); | ||
| 60 | static DEFINE_CLK(usbd, 8); | ||
| 61 | static DEFINE_CLK(usbh, 9); | ||
| 62 | static DEFINE_CLK(g2d, 10);; | ||
| 63 | static DEFINE_CLK(pwm, 18); | ||
| 64 | static DEFINE_CLK(ps2, 24); | ||
| 65 | static DEFINE_CLK(kpi, 25); | ||
| 66 | static DEFINE_CLK(wdt, 26); | ||
| 67 | static DEFINE_CLK(gdma, 27); | ||
| 68 | static DEFINE_CLK(adc, 28); | ||
| 69 | static DEFINE_CLK(usi, 29); | ||
| 70 | static DEFINE_CLK(ext, 0); | ||
| 71 | |||
| 72 | static struct clk_lookup nuc900_clkregs[] = { | ||
| 73 | DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL), | ||
| 74 | DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL), | ||
| 75 | DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL), | ||
| 76 | DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"), | ||
| 77 | DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"), | ||
| 78 | DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL), | ||
| 79 | DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL), | ||
| 80 | DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL), | ||
| 81 | DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"), | ||
| 82 | DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL), | ||
| 83 | DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL), | ||
| 84 | DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL), | ||
| 85 | DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL), | ||
| 86 | DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL), | ||
| 87 | DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL), | ||
| 88 | DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL), | ||
| 89 | DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL), | ||
| 90 | DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL), | ||
| 91 | DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL), | ||
| 92 | DEF_CLKLOOK(&clk_ext, NULL, "ext"), | ||
| 93 | }; | ||
| 94 | |||
| 95 | /* Initial serial platform data */ | ||
| 96 | |||
| 97 | struct plat_serial8250_port nuc900_uart_data[] = { | ||
| 98 | NUC900_8250PORT(UART0), | ||
| 99 | }; | ||
| 100 | |||
| 101 | struct platform_device nuc900_serial_device = { | ||
| 102 | .name = "serial8250", | ||
| 103 | .id = PLAT8250_DEV_PLATFORM, | ||
| 104 | .dev = { | ||
| 105 | .platform_data = nuc900_uart_data, | ||
| 106 | }, | ||
| 107 | }; | ||
| 108 | |||
| 109 | /*Set NUC900 series cpu frequence*/ | ||
| 110 | static int __init nuc900_set_clkval(unsigned int cpufreq) | ||
| 111 | { | ||
| 112 | unsigned int pllclk, ahbclk, apbclk, val; | ||
| 113 | |||
| 114 | pllclk = 0; | ||
| 115 | ahbclk = 0; | ||
| 116 | apbclk = 0; | ||
| 117 | |||
| 118 | switch (cpufreq) { | ||
| 119 | case 66: | ||
| 120 | pllclk = PLL_66MHZ; | ||
| 121 | ahbclk = AHB_CPUCLK_1_1; | ||
| 122 | apbclk = APB_AHB_1_2; | ||
| 123 | break; | ||
| 124 | |||
| 125 | case 100: | ||
| 126 | pllclk = PLL_100MHZ; | ||
| 127 | ahbclk = AHB_CPUCLK_1_1; | ||
| 128 | apbclk = APB_AHB_1_2; | ||
| 129 | break; | ||
| 130 | |||
| 131 | case 120: | ||
| 132 | pllclk = PLL_120MHZ; | ||
| 133 | ahbclk = AHB_CPUCLK_1_2; | ||
| 134 | apbclk = APB_AHB_1_2; | ||
| 135 | break; | ||
| 136 | |||
| 137 | case 166: | ||
| 138 | pllclk = PLL_166MHZ; | ||
| 139 | ahbclk = AHB_CPUCLK_1_2; | ||
| 140 | apbclk = APB_AHB_1_2; | ||
| 141 | break; | ||
| 142 | |||
| 143 | case 200: | ||
| 144 | pllclk = PLL_200MHZ; | ||
| 145 | ahbclk = AHB_CPUCLK_1_2; | ||
| 146 | apbclk = APB_AHB_1_2; | ||
| 147 | break; | ||
| 148 | } | ||
| 149 | |||
| 150 | __raw_writel(pllclk, REG_PLLCON0); | ||
| 151 | |||
| 152 | val = __raw_readl(REG_CLKDIV); | ||
| 153 | val &= ~(0x03 << 24 | 0x03 << 26); | ||
| 154 | val |= (ahbclk << 24 | apbclk << 26); | ||
| 155 | __raw_writel(val, REG_CLKDIV); | ||
| 156 | |||
| 157 | return 0; | ||
| 158 | } | ||
| 159 | static int __init nuc900_set_cpufreq(char *str) | ||
| 160 | { | ||
| 161 | unsigned long cpufreq, val; | ||
| 162 | |||
| 163 | if (!*str) | ||
| 164 | return 0; | ||
| 165 | |||
| 166 | strict_strtoul(str, 0, &cpufreq); | ||
| 167 | |||
| 168 | nuc900_clock_source(NULL, "ext"); | ||
| 169 | |||
| 170 | nuc900_set_clkval(cpufreq); | ||
| 171 | |||
| 172 | mdelay(1); | ||
| 173 | |||
| 174 | val = __raw_readl(REG_CKSKEW); | ||
| 175 | val &= ~0xff; | ||
| 176 | val |= DEFAULTSKEW; | ||
| 177 | __raw_writel(val, REG_CKSKEW); | ||
| 178 | |||
| 179 | nuc900_clock_source(NULL, "pll0"); | ||
| 180 | |||
| 181 | return 1; | ||
| 182 | } | ||
| 183 | |||
| 184 | __setup("cpufreq=", nuc900_set_cpufreq); | ||
| 185 | |||
| 186 | /*Init NUC900 evb io*/ | ||
| 187 | |||
| 188 | void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size) | ||
| 189 | { | ||
| 190 | unsigned long idcode = 0x0; | ||
| 191 | |||
| 192 | iotable_init(mach_desc, mach_size); | ||
| 193 | iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc)); | ||
| 194 | |||
| 195 | idcode = __raw_readl(NUC900PDID); | ||
| 196 | if (idcode == NUC910_CPUID) | ||
| 197 | printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode); | ||
| 198 | else if (idcode == NUC920_CPUID) | ||
| 199 | printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode); | ||
| 200 | else if (idcode == NUC950_CPUID) | ||
| 201 | printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode); | ||
| 202 | else if (idcode == NUC960_CPUID) | ||
| 203 | printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode); | ||
| 204 | } | ||
| 205 | |||
| 206 | /*Init NUC900 clock*/ | ||
| 207 | |||
| 208 | void __init nuc900_init_clocks(void) | ||
| 209 | { | ||
| 210 | clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs)); | ||
| 211 | } | ||
| 212 | |||
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h index 57b5dbabeb41..4d58ba164e25 100644 --- a/arch/arm/mach-w90x900/cpu.h +++ b/arch/arm/mach-w90x900/cpu.h | |||
| @@ -6,7 +6,7 @@ | |||
| 6 | * Copyright (c) 2008 Nuvoton technology corporation | 6 | * Copyright (c) 2008 Nuvoton technology corporation |
| 7 | * All rights reserved. | 7 | * All rights reserved. |
| 8 | * | 8 | * |
| 9 | * Header file for W90X900 CPU support | 9 | * Header file for NUC900 CPU support |
| 10 | * | 10 | * |
| 11 | * Wan ZongShun <mcuos.com@gmail.com> | 11 | * Wan ZongShun <mcuos.com@gmail.com> |
| 12 | * | 12 | * |
| @@ -24,29 +24,7 @@ | |||
| 24 | .type = MT_DEVICE, \ | 24 | .type = MT_DEVICE, \ |
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | /*Cpu identifier register*/ | 27 | #define NUC900_8250PORT(name) \ |
| 28 | |||
| 29 | #define W90X900PDID W90X900_VA_GCR | ||
| 30 | #define W90P910_CPUID 0x02900910 | ||
| 31 | #define W90P920_CPUID 0x02900920 | ||
| 32 | #define W90P950_CPUID 0x02900950 | ||
| 33 | #define W90N960_CPUID 0x02900960 | ||
| 34 | |||
| 35 | struct w90x900_uartcfg; | ||
| 36 | struct map_desc; | ||
| 37 | struct sys_timer; | ||
| 38 | |||
| 39 | /* core initialisation functions */ | ||
| 40 | |||
| 41 | extern void w90x900_init_irq(void); | ||
| 42 | extern void w90p910_init_io(struct map_desc *mach_desc, int size); | ||
| 43 | extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); | ||
| 44 | extern void w90p910_init_clocks(void); | ||
| 45 | extern void w90p910_map_io(struct map_desc *mach_desc, int size); | ||
| 46 | extern struct platform_device w90p910_serial_device; | ||
| 47 | extern struct sys_timer w90x900_timer; | ||
| 48 | |||
| 49 | #define W90X900_8250PORT(name) \ | ||
| 50 | { \ | 28 | { \ |
| 51 | .membase = name##_BA, \ | 29 | .membase = name##_BA, \ |
| 52 | .mapbase = name##_PA, \ | 30 | .mapbase = name##_PA, \ |
| @@ -56,3 +34,26 @@ extern struct sys_timer w90x900_timer; | |||
| 56 | .iotype = UPIO_MEM, \ | 34 | .iotype = UPIO_MEM, \ |
| 57 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ | 35 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ |
| 58 | } | 36 | } |
| 37 | |||
| 38 | /*Cpu identifier register*/ | ||
| 39 | |||
| 40 | #define NUC900PDID W90X900_VA_GCR | ||
| 41 | #define NUC910_CPUID 0x02900910 | ||
| 42 | #define NUC920_CPUID 0x02900920 | ||
| 43 | #define NUC950_CPUID 0x02900950 | ||
| 44 | #define NUC960_CPUID 0x02900960 | ||
| 45 | |||
| 46 | /* extern file from cpu.c */ | ||
| 47 | |||
| 48 | extern void nuc900_clock_source(struct device *dev, unsigned char *src); | ||
| 49 | extern void nuc900_init_clocks(void); | ||
| 50 | extern void nuc900_map_io(struct map_desc *mach_desc, int mach_size); | ||
| 51 | extern void nuc900_board_init(struct platform_device **device, int size); | ||
| 52 | |||
| 53 | /* for either public between 910 and 920, or between 920 and 950 */ | ||
| 54 | |||
| 55 | extern struct platform_device nuc900_serial_device; | ||
| 56 | extern struct platform_device nuc900_device_fmi; | ||
| 57 | extern struct platform_device nuc900_device_kpi; | ||
| 58 | extern struct platform_device nuc900_device_rtc; | ||
| 59 | extern struct platform_device nuc900_device_ts; | ||
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c new file mode 100644 index 000000000000..2a6f98de48d2 --- /dev/null +++ b/arch/arm/mach-w90x900/dev.c | |||
| @@ -0,0 +1,389 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/dev.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2009 Nuvoton corporation. | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License as | ||
| 10 | * published by the Free Software Foundation;version 2 of the License. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/list.h> | ||
| 18 | #include <linux/timer.h> | ||
| 19 | #include <linux/init.h> | ||
| 20 | #include <linux/platform_device.h> | ||
| 21 | |||
| 22 | #include <linux/mtd/physmap.h> | ||
| 23 | #include <linux/mtd/mtd.h> | ||
| 24 | #include <linux/mtd/partitions.h> | ||
| 25 | |||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/spi/flash.h> | ||
| 28 | |||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | #include <asm/mach/irq.h> | ||
| 32 | #include <asm/mach-types.h> | ||
| 33 | |||
| 34 | #include <mach/regs-serial.h> | ||
| 35 | #include <mach/map.h> | ||
| 36 | |||
| 37 | #include "cpu.h" | ||
| 38 | |||
| 39 | /*NUC900 evb norflash driver data */ | ||
| 40 | |||
| 41 | #define NUC900_FLASH_BASE 0xA0000000 | ||
| 42 | #define NUC900_FLASH_SIZE 0x400000 | ||
| 43 | #define SPIOFFSET 0x200 | ||
| 44 | #define SPIOREG_SIZE 0x100 | ||
| 45 | |||
| 46 | static struct mtd_partition nuc900_flash_partitions[] = { | ||
| 47 | { | ||
| 48 | .name = "NOR Partition 1 for kernel (960K)", | ||
| 49 | .size = 0xF0000, | ||
| 50 | .offset = 0x10000, | ||
| 51 | }, | ||
| 52 | { | ||
| 53 | .name = "NOR Partition 2 for image (1M)", | ||
| 54 | .size = 0x100000, | ||
| 55 | .offset = 0x100000, | ||
| 56 | }, | ||
| 57 | { | ||
| 58 | .name = "NOR Partition 3 for user (2M)", | ||
| 59 | .size = 0x200000, | ||
| 60 | .offset = 0x00200000, | ||
| 61 | } | ||
| 62 | }; | ||
| 63 | |||
| 64 | static struct physmap_flash_data nuc900_flash_data = { | ||
| 65 | .width = 2, | ||
| 66 | .parts = nuc900_flash_partitions, | ||
| 67 | .nr_parts = ARRAY_SIZE(nuc900_flash_partitions), | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct resource nuc900_flash_resources[] = { | ||
| 71 | { | ||
| 72 | .start = NUC900_FLASH_BASE, | ||
| 73 | .end = NUC900_FLASH_BASE + NUC900_FLASH_SIZE - 1, | ||
| 74 | .flags = IORESOURCE_MEM, | ||
| 75 | } | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct platform_device nuc900_flash_device = { | ||
| 79 | .name = "physmap-flash", | ||
| 80 | .id = 0, | ||
| 81 | .dev = { | ||
| 82 | .platform_data = &nuc900_flash_data, | ||
| 83 | }, | ||
| 84 | .resource = nuc900_flash_resources, | ||
| 85 | .num_resources = ARRAY_SIZE(nuc900_flash_resources), | ||
| 86 | }; | ||
| 87 | |||
| 88 | /* USB EHCI Host Controller */ | ||
| 89 | |||
| 90 | static struct resource nuc900_usb_ehci_resource[] = { | ||
| 91 | [0] = { | ||
| 92 | .start = W90X900_PA_USBEHCIHOST, | ||
| 93 | .end = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1, | ||
| 94 | .flags = IORESOURCE_MEM, | ||
| 95 | }, | ||
| 96 | [1] = { | ||
| 97 | .start = IRQ_USBH, | ||
| 98 | .end = IRQ_USBH, | ||
| 99 | .flags = IORESOURCE_IRQ, | ||
| 100 | } | ||
| 101 | }; | ||
| 102 | |||
| 103 | static u64 nuc900_device_usb_ehci_dmamask = 0xffffffffUL; | ||
| 104 | |||
| 105 | static struct platform_device nuc900_device_usb_ehci = { | ||
| 106 | .name = "nuc900-ehci", | ||
| 107 | .id = -1, | ||
| 108 | .num_resources = ARRAY_SIZE(nuc900_usb_ehci_resource), | ||
| 109 | .resource = nuc900_usb_ehci_resource, | ||
| 110 | .dev = { | ||
| 111 | .dma_mask = &nuc900_device_usb_ehci_dmamask, | ||
| 112 | .coherent_dma_mask = 0xffffffffUL | ||
| 113 | } | ||
| 114 | }; | ||
| 115 | |||
| 116 | /* USB OHCI Host Controller */ | ||
| 117 | |||
| 118 | static struct resource nuc900_usb_ohci_resource[] = { | ||
| 119 | [0] = { | ||
| 120 | .start = W90X900_PA_USBOHCIHOST, | ||
| 121 | .end = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1, | ||
| 122 | .flags = IORESOURCE_MEM, | ||
| 123 | }, | ||
| 124 | [1] = { | ||
| 125 | .start = IRQ_USBH, | ||
| 126 | .end = IRQ_USBH, | ||
| 127 | .flags = IORESOURCE_IRQ, | ||
| 128 | } | ||
| 129 | }; | ||
| 130 | |||
| 131 | static u64 nuc900_device_usb_ohci_dmamask = 0xffffffffUL; | ||
| 132 | static struct platform_device nuc900_device_usb_ohci = { | ||
| 133 | .name = "nuc900-ohci", | ||
| 134 | .id = -1, | ||
| 135 | .num_resources = ARRAY_SIZE(nuc900_usb_ohci_resource), | ||
| 136 | .resource = nuc900_usb_ohci_resource, | ||
| 137 | .dev = { | ||
| 138 | .dma_mask = &nuc900_device_usb_ohci_dmamask, | ||
| 139 | .coherent_dma_mask = 0xffffffffUL | ||
| 140 | } | ||
| 141 | }; | ||
| 142 | |||
| 143 | /* USB Device (Gadget)*/ | ||
| 144 | |||
| 145 | static struct resource nuc900_usbgadget_resource[] = { | ||
| 146 | [0] = { | ||
| 147 | .start = W90X900_PA_USBDEV, | ||
| 148 | .end = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1, | ||
| 149 | .flags = IORESOURCE_MEM, | ||
| 150 | }, | ||
| 151 | [1] = { | ||
| 152 | .start = IRQ_USBD, | ||
| 153 | .end = IRQ_USBD, | ||
| 154 | .flags = IORESOURCE_IRQ, | ||
| 155 | } | ||
| 156 | }; | ||
| 157 | |||
| 158 | static struct platform_device nuc900_device_usbgadget = { | ||
| 159 | .name = "nuc900-usbgadget", | ||
| 160 | .id = -1, | ||
| 161 | .num_resources = ARRAY_SIZE(nuc900_usbgadget_resource), | ||
| 162 | .resource = nuc900_usbgadget_resource, | ||
| 163 | }; | ||
| 164 | |||
| 165 | /* MAC device */ | ||
| 166 | |||
| 167 | static struct resource nuc900_emc_resource[] = { | ||
| 168 | [0] = { | ||
| 169 | .start = W90X900_PA_EMC, | ||
| 170 | .end = W90X900_PA_EMC + W90X900_SZ_EMC - 1, | ||
| 171 | .flags = IORESOURCE_MEM, | ||
| 172 | }, | ||
| 173 | [1] = { | ||
| 174 | .start = IRQ_EMCTX, | ||
| 175 | .end = IRQ_EMCTX, | ||
| 176 | .flags = IORESOURCE_IRQ, | ||
| 177 | }, | ||
| 178 | [2] = { | ||
| 179 | .start = IRQ_EMCRX, | ||
| 180 | .end = IRQ_EMCRX, | ||
| 181 | .flags = IORESOURCE_IRQ, | ||
| 182 | } | ||
| 183 | }; | ||
| 184 | |||
| 185 | static u64 nuc900_device_emc_dmamask = 0xffffffffUL; | ||
| 186 | static struct platform_device nuc900_device_emc = { | ||
| 187 | .name = "nuc900-emc", | ||
| 188 | .id = -1, | ||
| 189 | .num_resources = ARRAY_SIZE(nuc900_emc_resource), | ||
| 190 | .resource = nuc900_emc_resource, | ||
| 191 | .dev = { | ||
| 192 | .dma_mask = &nuc900_device_emc_dmamask, | ||
| 193 | .coherent_dma_mask = 0xffffffffUL | ||
| 194 | } | ||
| 195 | }; | ||
| 196 | |||
| 197 | /* SPI device */ | ||
| 198 | |||
| 199 | static struct resource nuc900_spi_resource[] = { | ||
| 200 | [0] = { | ||
| 201 | .start = W90X900_PA_I2C + SPIOFFSET, | ||
| 202 | .end = W90X900_PA_I2C + SPIOFFSET + SPIOREG_SIZE - 1, | ||
| 203 | .flags = IORESOURCE_MEM, | ||
| 204 | }, | ||
| 205 | [1] = { | ||
| 206 | .start = IRQ_SSP, | ||
| 207 | .end = IRQ_SSP, | ||
| 208 | .flags = IORESOURCE_IRQ, | ||
| 209 | } | ||
| 210 | }; | ||
| 211 | |||
| 212 | static struct platform_device nuc900_device_spi = { | ||
| 213 | .name = "nuc900-spi", | ||
| 214 | .id = -1, | ||
| 215 | .num_resources = ARRAY_SIZE(nuc900_spi_resource), | ||
| 216 | .resource = nuc900_spi_resource, | ||
| 217 | }; | ||
| 218 | |||
| 219 | /* spi device, spi flash info */ | ||
| 220 | |||
| 221 | static struct mtd_partition nuc900_spi_flash_partitions[] = { | ||
| 222 | { | ||
| 223 | .name = "bootloader(spi)", | ||
| 224 | .size = 0x0100000, | ||
| 225 | .offset = 0, | ||
| 226 | }, | ||
| 227 | }; | ||
| 228 | |||
| 229 | static struct flash_platform_data nuc900_spi_flash_data = { | ||
| 230 | .name = "m25p80", | ||
| 231 | .parts = nuc900_spi_flash_partitions, | ||
| 232 | .nr_parts = ARRAY_SIZE(nuc900_spi_flash_partitions), | ||
| 233 | .type = "w25x16", | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct spi_board_info nuc900_spi_board_info[] __initdata = { | ||
| 237 | { | ||
| 238 | .modalias = "m25p80", | ||
| 239 | .max_speed_hz = 20000000, | ||
| 240 | .bus_num = 0, | ||
| 241 | .chip_select = 1, | ||
| 242 | .platform_data = &nuc900_spi_flash_data, | ||
| 243 | .mode = SPI_MODE_0, | ||
| 244 | }, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /* WDT Device */ | ||
| 248 | |||
| 249 | static struct resource nuc900_wdt_resource[] = { | ||
| 250 | [0] = { | ||
| 251 | .start = W90X900_PA_TIMER, | ||
| 252 | .end = W90X900_PA_TIMER + W90X900_SZ_TIMER - 1, | ||
| 253 | .flags = IORESOURCE_MEM, | ||
| 254 | }, | ||
| 255 | [1] = { | ||
| 256 | .start = IRQ_WDT, | ||
| 257 | .end = IRQ_WDT, | ||
| 258 | .flags = IORESOURCE_IRQ, | ||
| 259 | } | ||
| 260 | }; | ||
| 261 | |||
| 262 | static struct platform_device nuc900_device_wdt = { | ||
| 263 | .name = "nuc900-wdt", | ||
| 264 | .id = -1, | ||
| 265 | .num_resources = ARRAY_SIZE(nuc900_wdt_resource), | ||
| 266 | .resource = nuc900_wdt_resource, | ||
| 267 | }; | ||
| 268 | |||
| 269 | /* | ||
| 270 | * public device definition between 910 and 920, or 910 | ||
| 271 | * and 950 or 950 and 960...,their dev platform register | ||
| 272 | * should be in specific file such as nuc950, nuc960 c | ||
| 273 | * files rather than the public dev.c file here. so the | ||
| 274 | * corresponding platform_device definition should not be | ||
| 275 | * static. | ||
| 276 | */ | ||
| 277 | |||
| 278 | /* RTC controller*/ | ||
| 279 | |||
| 280 | static struct resource nuc900_rtc_resource[] = { | ||
| 281 | [0] = { | ||
| 282 | .start = W90X900_PA_RTC, | ||
| 283 | .end = W90X900_PA_RTC + 0xff, | ||
| 284 | .flags = IORESOURCE_MEM, | ||
| 285 | }, | ||
| 286 | [1] = { | ||
| 287 | .start = IRQ_RTC, | ||
| 288 | .end = IRQ_RTC, | ||
| 289 | .flags = IORESOURCE_IRQ, | ||
| 290 | }, | ||
| 291 | }; | ||
| 292 | |||
| 293 | struct platform_device nuc900_device_rtc = { | ||
| 294 | .name = "nuc900-rtc", | ||
| 295 | .id = -1, | ||
| 296 | .num_resources = ARRAY_SIZE(nuc900_rtc_resource), | ||
| 297 | .resource = nuc900_rtc_resource, | ||
| 298 | }; | ||
| 299 | |||
| 300 | /*TouchScreen controller*/ | ||
| 301 | |||
| 302 | static struct resource nuc900_ts_resource[] = { | ||
| 303 | [0] = { | ||
| 304 | .start = W90X900_PA_ADC, | ||
| 305 | .end = W90X900_PA_ADC + W90X900_SZ_ADC-1, | ||
| 306 | .flags = IORESOURCE_MEM, | ||
| 307 | }, | ||
| 308 | [1] = { | ||
| 309 | .start = IRQ_ADC, | ||
| 310 | .end = IRQ_ADC, | ||
| 311 | .flags = IORESOURCE_IRQ, | ||
| 312 | }, | ||
| 313 | }; | ||
| 314 | |||
| 315 | struct platform_device nuc900_device_ts = { | ||
| 316 | .name = "nuc900-ts", | ||
| 317 | .id = -1, | ||
| 318 | .resource = nuc900_ts_resource, | ||
| 319 | .num_resources = ARRAY_SIZE(nuc900_ts_resource), | ||
| 320 | }; | ||
| 321 | |||
| 322 | /* FMI Device */ | ||
| 323 | |||
| 324 | static struct resource nuc900_fmi_resource[] = { | ||
| 325 | [0] = { | ||
| 326 | .start = W90X900_PA_FMI, | ||
| 327 | .end = W90X900_PA_FMI + W90X900_SZ_FMI - 1, | ||
| 328 | .flags = IORESOURCE_MEM, | ||
| 329 | }, | ||
| 330 | [1] = { | ||
| 331 | .start = IRQ_FMI, | ||
| 332 | .end = IRQ_FMI, | ||
| 333 | .flags = IORESOURCE_IRQ, | ||
| 334 | } | ||
| 335 | }; | ||
| 336 | |||
| 337 | struct platform_device nuc900_device_fmi = { | ||
| 338 | .name = "nuc900-fmi", | ||
| 339 | .id = -1, | ||
| 340 | .num_resources = ARRAY_SIZE(nuc900_fmi_resource), | ||
| 341 | .resource = nuc900_fmi_resource, | ||
| 342 | }; | ||
| 343 | |||
| 344 | /* KPI controller*/ | ||
| 345 | |||
| 346 | static struct resource nuc900_kpi_resource[] = { | ||
| 347 | [0] = { | ||
| 348 | .start = W90X900_PA_KPI, | ||
| 349 | .end = W90X900_PA_KPI + W90X900_SZ_KPI - 1, | ||
| 350 | .flags = IORESOURCE_MEM, | ||
| 351 | }, | ||
| 352 | [1] = { | ||
| 353 | .start = IRQ_KPI, | ||
| 354 | .end = IRQ_KPI, | ||
| 355 | .flags = IORESOURCE_IRQ, | ||
| 356 | } | ||
| 357 | |||
| 358 | }; | ||
| 359 | |||
| 360 | struct platform_device nuc900_device_kpi = { | ||
| 361 | .name = "nuc900-kpi", | ||
| 362 | .id = -1, | ||
| 363 | .num_resources = ARRAY_SIZE(nuc900_kpi_resource), | ||
| 364 | .resource = nuc900_kpi_resource, | ||
| 365 | }; | ||
| 366 | |||
| 367 | /*Here should be your evb resourse,such as LCD*/ | ||
| 368 | |||
| 369 | static struct platform_device *nuc900_public_dev[] __initdata = { | ||
| 370 | &nuc900_serial_device, | ||
| 371 | &nuc900_flash_device, | ||
| 372 | &nuc900_device_usb_ehci, | ||
| 373 | &nuc900_device_usb_ohci, | ||
| 374 | &nuc900_device_usbgadget, | ||
| 375 | &nuc900_device_emc, | ||
| 376 | &nuc900_device_spi, | ||
| 377 | &nuc900_device_wdt, | ||
| 378 | }; | ||
| 379 | |||
| 380 | /* Provide adding specific CPU platform devices API */ | ||
| 381 | |||
| 382 | void __init nuc900_board_init(struct platform_device **device, int size) | ||
| 383 | { | ||
| 384 | platform_add_devices(device, size); | ||
| 385 | platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev)); | ||
| 386 | spi_register_board_info(nuc900_spi_board_info, | ||
| 387 | ARRAY_SIZE(nuc900_spi_board_info)); | ||
| 388 | } | ||
| 389 | |||
diff --git a/arch/arm/mach-w90x900/gpio.c b/arch/arm/mach-w90x900/gpio.c index c72e0dfa1825..ba05aec7ea4b 100644 --- a/arch/arm/mach-w90x900/gpio.c +++ b/arch/arm/mach-w90x900/gpio.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-w90p910/gpio.c | 2 | * linux/arch/arm/mach-w90x900/gpio.c |
| 3 | * | 3 | * |
| 4 | * Generic w90p910 GPIO handling | 4 | * Generic nuc900 GPIO handling |
| 5 | * | 5 | * |
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | 6 | * Wan ZongShun <mcuos.com@gmail.com> |
| 7 | * | 7 | * |
| @@ -30,31 +30,31 @@ | |||
| 30 | #define GPIO_IN (0x0C) | 30 | #define GPIO_IN (0x0C) |
| 31 | #define GROUPINERV (0x10) | 31 | #define GROUPINERV (0x10) |
| 32 | #define GPIO_GPIO(Nb) (0x00000001 << (Nb)) | 32 | #define GPIO_GPIO(Nb) (0x00000001 << (Nb)) |
| 33 | #define to_w90p910_gpio_chip(c) container_of(c, struct w90p910_gpio_chip, chip) | 33 | #define to_nuc900_gpio_chip(c) container_of(c, struct nuc900_gpio_chip, chip) |
| 34 | 34 | ||
| 35 | #define W90P910_GPIO_CHIP(name, base_gpio, nr_gpio) \ | 35 | #define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio) \ |
| 36 | { \ | 36 | { \ |
| 37 | .chip = { \ | 37 | .chip = { \ |
| 38 | .label = name, \ | 38 | .label = name, \ |
| 39 | .direction_input = w90p910_dir_input, \ | 39 | .direction_input = nuc900_dir_input, \ |
| 40 | .direction_output = w90p910_dir_output, \ | 40 | .direction_output = nuc900_dir_output, \ |
| 41 | .get = w90p910_gpio_get, \ | 41 | .get = nuc900_gpio_get, \ |
| 42 | .set = w90p910_gpio_set, \ | 42 | .set = nuc900_gpio_set, \ |
| 43 | .base = base_gpio, \ | 43 | .base = base_gpio, \ |
| 44 | .ngpio = nr_gpio, \ | 44 | .ngpio = nr_gpio, \ |
| 45 | } \ | 45 | } \ |
| 46 | } | 46 | } |
| 47 | 47 | ||
| 48 | struct w90p910_gpio_chip { | 48 | struct nuc900_gpio_chip { |
| 49 | struct gpio_chip chip; | 49 | struct gpio_chip chip; |
| 50 | void __iomem *regbase; /* Base of group register*/ | 50 | void __iomem *regbase; /* Base of group register*/ |
| 51 | spinlock_t gpio_lock; | 51 | spinlock_t gpio_lock; |
| 52 | }; | 52 | }; |
| 53 | 53 | ||
| 54 | static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset) | 54 | static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset) |
| 55 | { | 55 | { |
| 56 | struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip); | 56 | struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip); |
| 57 | void __iomem *pio = w90p910_gpio->regbase + GPIO_IN; | 57 | void __iomem *pio = nuc900_gpio->regbase + GPIO_IN; |
| 58 | unsigned int regval; | 58 | unsigned int regval; |
| 59 | 59 | ||
| 60 | regval = __raw_readl(pio); | 60 | regval = __raw_readl(pio); |
| @@ -63,14 +63,14 @@ static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
| 63 | return (regval != 0); | 63 | return (regval != 0); |
| 64 | } | 64 | } |
| 65 | 65 | ||
| 66 | static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | 66 | static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
| 67 | { | 67 | { |
| 68 | struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip); | 68 | struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip); |
| 69 | void __iomem *pio = w90p910_gpio->regbase + GPIO_OUT; | 69 | void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT; |
| 70 | unsigned int regval; | 70 | unsigned int regval; |
| 71 | unsigned long flags; | 71 | unsigned long flags; |
| 72 | 72 | ||
| 73 | spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags); | 73 | spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); |
| 74 | 74 | ||
| 75 | regval = __raw_readl(pio); | 75 | regval = __raw_readl(pio); |
| 76 | 76 | ||
| @@ -81,36 +81,36 @@ static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val) | |||
| 81 | 81 | ||
| 82 | __raw_writel(regval, pio); | 82 | __raw_writel(regval, pio); |
| 83 | 83 | ||
| 84 | spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags); | 84 | spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); |
| 85 | } | 85 | } |
| 86 | 86 | ||
| 87 | static int w90p910_dir_input(struct gpio_chip *chip, unsigned offset) | 87 | static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset) |
| 88 | { | 88 | { |
| 89 | struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip); | 89 | struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip); |
| 90 | void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR; | 90 | void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR; |
| 91 | unsigned int regval; | 91 | unsigned int regval; |
| 92 | unsigned long flags; | 92 | unsigned long flags; |
| 93 | 93 | ||
| 94 | spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags); | 94 | spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); |
| 95 | 95 | ||
| 96 | regval = __raw_readl(pio); | 96 | regval = __raw_readl(pio); |
| 97 | regval &= ~GPIO_GPIO(offset); | 97 | regval &= ~GPIO_GPIO(offset); |
| 98 | __raw_writel(regval, pio); | 98 | __raw_writel(regval, pio); |
| 99 | 99 | ||
| 100 | spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags); | 100 | spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); |
| 101 | 101 | ||
| 102 | return 0; | 102 | return 0; |
| 103 | } | 103 | } |
| 104 | 104 | ||
| 105 | static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val) | 105 | static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val) |
| 106 | { | 106 | { |
| 107 | struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip); | 107 | struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip); |
| 108 | void __iomem *outreg = w90p910_gpio->regbase + GPIO_OUT; | 108 | void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT; |
| 109 | void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR; | 109 | void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR; |
| 110 | unsigned int regval; | 110 | unsigned int regval; |
| 111 | unsigned long flags; | 111 | unsigned long flags; |
| 112 | 112 | ||
| 113 | spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags); | 113 | spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags); |
| 114 | 114 | ||
| 115 | regval = __raw_readl(pio); | 115 | regval = __raw_readl(pio); |
| 116 | regval |= GPIO_GPIO(offset); | 116 | regval |= GPIO_GPIO(offset); |
| @@ -125,28 +125,28 @@ static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val) | |||
| 125 | 125 | ||
| 126 | __raw_writel(regval, outreg); | 126 | __raw_writel(regval, outreg); |
| 127 | 127 | ||
| 128 | spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags); | 128 | spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags); |
| 129 | 129 | ||
| 130 | return 0; | 130 | return 0; |
| 131 | } | 131 | } |
| 132 | 132 | ||
| 133 | static struct w90p910_gpio_chip w90p910_gpio[] = { | 133 | static struct nuc900_gpio_chip nuc900_gpio[] = { |
| 134 | W90P910_GPIO_CHIP("GROUPC", 0, 16), | 134 | NUC900_GPIO_CHIP("GROUPC", 0, 16), |
| 135 | W90P910_GPIO_CHIP("GROUPD", 16, 10), | 135 | NUC900_GPIO_CHIP("GROUPD", 16, 10), |
| 136 | W90P910_GPIO_CHIP("GROUPE", 26, 14), | 136 | NUC900_GPIO_CHIP("GROUPE", 26, 14), |
| 137 | W90P910_GPIO_CHIP("GROUPF", 40, 10), | 137 | NUC900_GPIO_CHIP("GROUPF", 40, 10), |
| 138 | W90P910_GPIO_CHIP("GROUPG", 50, 17), | 138 | NUC900_GPIO_CHIP("GROUPG", 50, 17), |
| 139 | W90P910_GPIO_CHIP("GROUPH", 67, 8), | 139 | NUC900_GPIO_CHIP("GROUPH", 67, 8), |
| 140 | W90P910_GPIO_CHIP("GROUPI", 75, 17), | 140 | NUC900_GPIO_CHIP("GROUPI", 75, 17), |
| 141 | }; | 141 | }; |
| 142 | 142 | ||
| 143 | void __init w90p910_init_gpio(int nr_group) | 143 | void __init nuc900_init_gpio(int nr_group) |
| 144 | { | 144 | { |
| 145 | unsigned i; | 145 | unsigned i; |
| 146 | struct w90p910_gpio_chip *gpio_chip; | 146 | struct nuc900_gpio_chip *gpio_chip; |
| 147 | 147 | ||
| 148 | for (i = 0; i < nr_group; i++) { | 148 | for (i = 0; i < nr_group; i++) { |
| 149 | gpio_chip = &w90p910_gpio[i]; | 149 | gpio_chip = &nuc900_gpio[i]; |
| 150 | spin_lock_init(&gpio_chip->gpio_lock); | 150 | spin_lock_init(&gpio_chip->gpio_lock); |
| 151 | gpio_chip->regbase = GPIO_BASE + i * GROUPINERV; | 151 | gpio_chip->regbase = GPIO_BASE + i * GROUPINERV; |
| 152 | gpiochip_add(&gpio_chip->chip); | 152 | gpiochip_add(&gpio_chip->chip); |
diff --git a/arch/arm/mach-w90x900/include/mach/regs-clock.h b/arch/arm/mach-w90x900/include/mach/regs-clock.h index f10b6a8dc069..516d6b477b61 100644 --- a/arch/arm/mach-w90x900/include/mach/regs-clock.h +++ b/arch/arm/mach-w90x900/include/mach/regs-clock.h | |||
| @@ -28,4 +28,26 @@ | |||
| 28 | #define REG_CLKEN1 (CLK_BA + 0x24) | 28 | #define REG_CLKEN1 (CLK_BA + 0x24) |
| 29 | #define REG_CLKDIV1 (CLK_BA + 0x28) | 29 | #define REG_CLKDIV1 (CLK_BA + 0x28) |
| 30 | 30 | ||
| 31 | /* Define PLL freq setting */ | ||
| 32 | #define PLL_DISABLE 0x12B63 | ||
| 33 | #define PLL_66MHZ 0x2B63 | ||
| 34 | #define PLL_100MHZ 0x4F64 | ||
| 35 | #define PLL_120MHZ 0x4F63 | ||
| 36 | #define PLL_166MHZ 0x4124 | ||
| 37 | #define PLL_200MHZ 0x4F24 | ||
| 38 | |||
| 39 | /* Define AHB:CPUFREQ ratio */ | ||
| 40 | #define AHB_CPUCLK_1_1 0x00 | ||
| 41 | #define AHB_CPUCLK_1_2 0x01 | ||
| 42 | #define AHB_CPUCLK_1_4 0x02 | ||
| 43 | #define AHB_CPUCLK_1_8 0x03 | ||
| 44 | |||
| 45 | /* Define APB:AHB ratio */ | ||
| 46 | #define APB_AHB_1_2 0x01 | ||
| 47 | #define APB_AHB_1_4 0x02 | ||
| 48 | #define APB_AHB_1_8 0x03 | ||
| 49 | |||
| 50 | /* Define clock skew */ | ||
| 51 | #define DEFAULTSKEW 0x48 | ||
| 52 | |||
| 31 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | 53 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ |
diff --git a/arch/arm/mach-w90x900/include/mach/regs-ebi.h b/arch/arm/mach-w90x900/include/mach/regs-ebi.h new file mode 100644 index 000000000000..b68455e7f88b --- /dev/null +++ b/arch/arm/mach-w90x900/include/mach/regs-ebi.h | |||
| @@ -0,0 +1,33 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/include/mach/regs-ebi.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2009 Nuvoton technology corporation. | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation;version 2 of the License. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_REGS_EBI_H | ||
| 15 | #define __ASM_ARCH_REGS_EBI_H | ||
| 16 | |||
| 17 | /* EBI Control Registers */ | ||
| 18 | |||
| 19 | #define EBI_BA W90X900_VA_EBI | ||
| 20 | #define REG_EBICON (EBI_BA + 0x00) | ||
| 21 | #define REG_ROMCON (EBI_BA + 0x04) | ||
| 22 | #define REG_SDCONF0 (EBI_BA + 0x08) | ||
| 23 | #define REG_SDCONF1 (EBI_BA + 0x0C) | ||
| 24 | #define REG_SDTIME0 (EBI_BA + 0x10) | ||
| 25 | #define REG_SDTIME1 (EBI_BA + 0x14) | ||
| 26 | #define REG_EXT0CON (EBI_BA + 0x18) | ||
| 27 | #define REG_EXT1CON (EBI_BA + 0x1C) | ||
| 28 | #define REG_EXT2CON (EBI_BA + 0x20) | ||
| 29 | #define REG_EXT3CON (EBI_BA + 0x24) | ||
| 30 | #define REG_EXT4CON (EBI_BA + 0x28) | ||
| 31 | #define REG_CKSKEW (EBI_BA + 0x2C) | ||
| 32 | |||
| 33 | #endif /* __ASM_ARCH_REGS_EBI_H */ | ||
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c index 0b4fc194729c..0ce9d8e867eb 100644 --- a/arch/arm/mach-w90x900/irq.c +++ b/arch/arm/mach-w90x900/irq.c | |||
| @@ -10,8 +10,7 @@ | |||
| 10 | * | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify | 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License as published by | 12 | * it under the terms of the GNU General Public License as published by |
| 13 | * the Free Software Foundation; either version 2 of the License, or | 13 | * the Free Software Foundation;version 2 of the License. |
| 14 | * (at your option) any later version. | ||
| 15 | * | 14 | * |
| 16 | */ | 15 | */ |
| 17 | 16 | ||
| @@ -29,9 +28,114 @@ | |||
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | #include <mach/regs-irq.h> | 29 | #include <mach/regs-irq.h> |
| 31 | 30 | ||
| 32 | static void w90x900_irq_mask(unsigned int irq) | 31 | struct group_irq { |
| 32 | unsigned long gpen; | ||
| 33 | unsigned int enabled; | ||
| 34 | void (*enable)(struct group_irq *, int enable); | ||
| 35 | }; | ||
| 36 | |||
| 37 | static DEFINE_SPINLOCK(groupirq_lock); | ||
| 38 | |||
| 39 | #define DEFINE_GROUP(_name, _ctrlbit, _num) \ | ||
| 40 | struct group_irq group_##_name = { \ | ||
| 41 | .enable = nuc900_group_enable, \ | ||
| 42 | .gpen = ((1 << _num) - 1) << _ctrlbit, \ | ||
| 43 | } | ||
| 44 | |||
| 45 | static void nuc900_group_enable(struct group_irq *gpirq, int enable); | ||
| 46 | |||
| 47 | static DEFINE_GROUP(nirq0, 0, 4); | ||
| 48 | static DEFINE_GROUP(nirq1, 4, 4); | ||
| 49 | static DEFINE_GROUP(usbh, 8, 2); | ||
| 50 | static DEFINE_GROUP(ottimer, 16, 3); | ||
| 51 | static DEFINE_GROUP(gdma, 20, 2); | ||
| 52 | static DEFINE_GROUP(sc, 24, 2); | ||
| 53 | static DEFINE_GROUP(i2c, 26, 2); | ||
| 54 | static DEFINE_GROUP(ps2, 28, 2); | ||
| 55 | |||
| 56 | static int group_irq_enable(struct group_irq *group_irq) | ||
| 57 | { | ||
| 58 | unsigned long flags; | ||
| 59 | |||
| 60 | spin_lock_irqsave(&groupirq_lock, flags); | ||
| 61 | if (group_irq->enabled++ == 0) | ||
| 62 | (group_irq->enable)(group_irq, 1); | ||
| 63 | spin_unlock_irqrestore(&groupirq_lock, flags); | ||
| 64 | |||
| 65 | return 0; | ||
| 66 | } | ||
| 67 | |||
| 68 | static void group_irq_disable(struct group_irq *group_irq) | ||
| 33 | { | 69 | { |
| 70 | unsigned long flags; | ||
| 71 | |||
| 72 | WARN_ON(group_irq->enabled == 0); | ||
| 73 | |||
| 74 | spin_lock_irqsave(&groupirq_lock, flags); | ||
| 75 | if (--group_irq->enabled == 0) | ||
| 76 | (group_irq->enable)(group_irq, 0); | ||
| 77 | spin_unlock_irqrestore(&groupirq_lock, flags); | ||
| 78 | } | ||
| 79 | |||
| 80 | static void nuc900_group_enable(struct group_irq *gpirq, int enable) | ||
| 81 | { | ||
| 82 | unsigned int groupen = gpirq->gpen; | ||
| 83 | unsigned long regval; | ||
| 84 | |||
| 85 | regval = __raw_readl(REG_AIC_GEN); | ||
| 86 | |||
| 87 | if (enable) | ||
| 88 | regval |= groupen; | ||
| 89 | else | ||
| 90 | regval &= ~groupen; | ||
| 91 | |||
| 92 | __raw_writel(regval, REG_AIC_GEN); | ||
| 93 | } | ||
| 94 | |||
| 95 | static void nuc900_irq_mask(unsigned int irq) | ||
| 96 | { | ||
| 97 | struct group_irq *group_irq; | ||
| 98 | |||
| 99 | group_irq = NULL; | ||
| 100 | |||
| 34 | __raw_writel(1 << irq, REG_AIC_MDCR); | 101 | __raw_writel(1 << irq, REG_AIC_MDCR); |
| 102 | |||
| 103 | switch (irq) { | ||
| 104 | case IRQ_GROUP0: | ||
| 105 | group_irq = &group_nirq0; | ||
| 106 | break; | ||
| 107 | |||
| 108 | case IRQ_GROUP1: | ||
| 109 | group_irq = &group_nirq1; | ||
| 110 | break; | ||
| 111 | |||
| 112 | case IRQ_USBH: | ||
| 113 | group_irq = &group_usbh; | ||
| 114 | break; | ||
| 115 | |||
| 116 | case IRQ_T_INT_GROUP: | ||
| 117 | group_irq = &group_ottimer; | ||
| 118 | break; | ||
| 119 | |||
| 120 | case IRQ_GDMAGROUP: | ||
| 121 | group_irq = &group_gdma; | ||
| 122 | break; | ||
| 123 | |||
| 124 | case IRQ_SCGROUP: | ||
| 125 | group_irq = &group_sc; | ||
| 126 | break; | ||
| 127 | |||
| 128 | case IRQ_I2CGROUP: | ||
| 129 | group_irq = &group_i2c; | ||
| 130 | break; | ||
| 131 | |||
| 132 | case IRQ_P2SGROUP: | ||
| 133 | group_irq = &group_ps2; | ||
| 134 | break; | ||
| 135 | } | ||
| 136 | |||
| 137 | if (group_irq) | ||
| 138 | group_irq_disable(group_irq); | ||
| 35 | } | 139 | } |
| 36 | 140 | ||
| 37 | /* | 141 | /* |
| @@ -39,37 +143,71 @@ static void w90x900_irq_mask(unsigned int irq) | |||
| 39 | * to REG_AIC_EOSCR for ACK | 143 | * to REG_AIC_EOSCR for ACK |
| 40 | */ | 144 | */ |
| 41 | 145 | ||
| 42 | static void w90x900_irq_ack(unsigned int irq) | 146 | static void nuc900_irq_ack(unsigned int irq) |
| 43 | { | 147 | { |
| 44 | __raw_writel(0x01, REG_AIC_EOSCR); | 148 | __raw_writel(0x01, REG_AIC_EOSCR); |
| 45 | } | 149 | } |
| 46 | 150 | ||
| 47 | static void w90x900_irq_unmask(unsigned int irq) | 151 | static void nuc900_irq_unmask(unsigned int irq) |
| 48 | { | 152 | { |
| 49 | unsigned long mask; | 153 | struct group_irq *group_irq; |
| 154 | |||
| 155 | group_irq = NULL; | ||
| 50 | 156 | ||
| 51 | if (irq == IRQ_T_INT_GROUP) { | ||
| 52 | mask = __raw_readl(REG_AIC_GEN); | ||
| 53 | __raw_writel(TIME_GROUP_IRQ | mask, REG_AIC_GEN); | ||
| 54 | __raw_writel(1 << IRQ_T_INT_GROUP, REG_AIC_MECR); | ||
| 55 | } | ||
| 56 | __raw_writel(1 << irq, REG_AIC_MECR); | 157 | __raw_writel(1 << irq, REG_AIC_MECR); |
| 158 | |||
| 159 | switch (irq) { | ||
| 160 | case IRQ_GROUP0: | ||
| 161 | group_irq = &group_nirq0; | ||
| 162 | break; | ||
| 163 | |||
| 164 | case IRQ_GROUP1: | ||
| 165 | group_irq = &group_nirq1; | ||
| 166 | break; | ||
| 167 | |||
| 168 | case IRQ_USBH: | ||
| 169 | group_irq = &group_usbh; | ||
| 170 | break; | ||
| 171 | |||
| 172 | case IRQ_T_INT_GROUP: | ||
| 173 | group_irq = &group_ottimer; | ||
| 174 | break; | ||
| 175 | |||
| 176 | case IRQ_GDMAGROUP: | ||
| 177 | group_irq = &group_gdma; | ||
| 178 | break; | ||
| 179 | |||
| 180 | case IRQ_SCGROUP: | ||
| 181 | group_irq = &group_sc; | ||
| 182 | break; | ||
| 183 | |||
| 184 | case IRQ_I2CGROUP: | ||
| 185 | group_irq = &group_i2c; | ||
| 186 | break; | ||
| 187 | |||
| 188 | case IRQ_P2SGROUP: | ||
| 189 | group_irq = &group_ps2; | ||
| 190 | break; | ||
| 191 | } | ||
| 192 | |||
| 193 | if (group_irq) | ||
| 194 | group_irq_enable(group_irq); | ||
| 57 | } | 195 | } |
| 58 | 196 | ||
| 59 | static struct irq_chip w90x900_irq_chip = { | 197 | static struct irq_chip nuc900_irq_chip = { |
| 60 | .ack = w90x900_irq_ack, | 198 | .ack = nuc900_irq_ack, |
| 61 | .mask = w90x900_irq_mask, | 199 | .mask = nuc900_irq_mask, |
| 62 | .unmask = w90x900_irq_unmask, | 200 | .unmask = nuc900_irq_unmask, |
| 63 | }; | 201 | }; |
| 64 | 202 | ||
| 65 | void __init w90x900_init_irq(void) | 203 | void __init nuc900_init_irq(void) |
| 66 | { | 204 | { |
| 67 | int irqno; | 205 | int irqno; |
| 68 | 206 | ||
| 69 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); | 207 | __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); |
| 70 | 208 | ||
| 71 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { | 209 | for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) { |
| 72 | set_irq_chip(irqno, &w90x900_irq_chip); | 210 | set_irq_chip(irqno, &nuc900_irq_chip); |
| 73 | set_irq_handler(irqno, handle_level_irq); | 211 | set_irq_handler(irqno, handle_level_irq); |
| 74 | set_irq_flags(irqno, IRQF_VALID); | 212 | set_irq_flags(irqno, IRQF_VALID); |
| 75 | } | 213 | } |
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c new file mode 100644 index 000000000000..ec05bda946f3 --- /dev/null +++ b/arch/arm/mach-w90x900/mach-nuc910evb.c | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mach-nuc910evb.c | ||
| 3 | * | ||
| 4 | * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License as | ||
| 12 | * published by the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <asm/mach/map.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | #include "nuc910.h" | ||
| 23 | |||
| 24 | static void __init nuc910evb_map_io(void) | ||
| 25 | { | ||
| 26 | nuc910_map_io(); | ||
| 27 | nuc910_init_clocks(); | ||
| 28 | } | ||
| 29 | |||
| 30 | static void __init nuc910evb_init(void) | ||
| 31 | { | ||
| 32 | nuc910_board_init(); | ||
| 33 | } | ||
| 34 | |||
| 35 | MACHINE_START(W90P910EVB, "W90P910EVB") | ||
| 36 | /* Maintainer: Wan ZongShun */ | ||
| 37 | .phys_io = W90X900_PA_UART, | ||
| 38 | .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc, | ||
| 39 | .boot_params = 0, | ||
| 40 | .map_io = nuc910evb_map_io, | ||
| 41 | .init_irq = nuc900_init_irq, | ||
| 42 | .init_machine = nuc910evb_init, | ||
| 43 | .timer = &nuc900_timer, | ||
| 44 | MACHINE_END | ||
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c new file mode 100644 index 000000000000..cef903bcccd1 --- /dev/null +++ b/arch/arm/mach-w90x900/mach-nuc950evb.c | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mach-nuc950evb.c | ||
| 3 | * | ||
| 4 | * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License as | ||
| 12 | * published by the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <asm/mach/map.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | #include "nuc950.h" | ||
| 23 | |||
| 24 | static void __init nuc950evb_map_io(void) | ||
| 25 | { | ||
| 26 | nuc950_map_io(); | ||
| 27 | nuc950_init_clocks(); | ||
| 28 | } | ||
| 29 | |||
| 30 | static void __init nuc950evb_init(void) | ||
| 31 | { | ||
| 32 | nuc950_board_init(); | ||
| 33 | } | ||
| 34 | |||
| 35 | MACHINE_START(W90P950EVB, "W90P950EVB") | ||
| 36 | /* Maintainer: Wan ZongShun */ | ||
| 37 | .phys_io = W90X900_PA_UART, | ||
| 38 | .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc, | ||
| 39 | .boot_params = 0, | ||
| 40 | .map_io = nuc950evb_map_io, | ||
| 41 | .init_irq = nuc900_init_irq, | ||
| 42 | .init_machine = nuc950evb_init, | ||
| 43 | .timer = &nuc900_timer, | ||
| 44 | MACHINE_END | ||
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c new file mode 100644 index 000000000000..e3a46f19f2bc --- /dev/null +++ b/arch/arm/mach-w90x900/mach-nuc960evb.c | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mach-nuc960evb.c | ||
| 3 | * | ||
| 4 | * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License as | ||
| 12 | * published by the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <asm/mach/map.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <mach/map.h> | ||
| 21 | |||
| 22 | #include "nuc960.h" | ||
| 23 | |||
| 24 | static void __init nuc960evb_map_io(void) | ||
| 25 | { | ||
| 26 | nuc960_map_io(); | ||
| 27 | nuc960_init_clocks(); | ||
| 28 | } | ||
| 29 | |||
| 30 | static void __init nuc960evb_init(void) | ||
| 31 | { | ||
| 32 | nuc960_board_init(); | ||
| 33 | } | ||
| 34 | |||
| 35 | MACHINE_START(W90N960EVB, "W90N960EVB") | ||
| 36 | /* Maintainer: Wan ZongShun */ | ||
| 37 | .phys_io = W90X900_PA_UART, | ||
| 38 | .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc, | ||
| 39 | .boot_params = 0, | ||
| 40 | .map_io = nuc960evb_map_io, | ||
| 41 | .init_irq = nuc900_init_irq, | ||
| 42 | .init_machine = nuc960evb_init, | ||
| 43 | .timer = &nuc900_timer, | ||
| 44 | MACHINE_END | ||
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c deleted file mode 100644 index 7a62bd348e80..000000000000 --- a/arch/arm/mach-w90x900/mach-w90p910evb.c +++ /dev/null | |||
| @@ -1,267 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mach-w90p910evb.c | ||
| 3 | * | ||
| 4 | * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License as | ||
| 12 | * published by the Free Software Foundation;version 2 of the License. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/kernel.h> | ||
| 17 | #include <linux/types.h> | ||
| 18 | #include <linux/interrupt.h> | ||
| 19 | #include <linux/list.h> | ||
| 20 | #include <linux/timer.h> | ||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/mtd/physmap.h> | ||
| 24 | |||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | #include <asm/mach/map.h> | ||
| 27 | #include <asm/mach/irq.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | |||
| 30 | #include <mach/regs-serial.h> | ||
| 31 | #include <mach/map.h> | ||
| 32 | |||
| 33 | #include "cpu.h" | ||
| 34 | /*w90p910 evb norflash driver data */ | ||
| 35 | |||
| 36 | #define W90P910_FLASH_BASE 0xA0000000 | ||
| 37 | #define W90P910_FLASH_SIZE 0x400000 | ||
| 38 | |||
| 39 | static struct mtd_partition w90p910_flash_partitions[] = { | ||
| 40 | { | ||
| 41 | .name = "NOR Partition 1 for kernel (960K)", | ||
| 42 | .size = 0xF0000, | ||
| 43 | .offset = 0x10000, | ||
| 44 | }, | ||
| 45 | { | ||
| 46 | .name = "NOR Partition 2 for image (1M)", | ||
| 47 | .size = 0x100000, | ||
| 48 | .offset = 0x100000, | ||
| 49 | }, | ||
| 50 | { | ||
| 51 | .name = "NOR Partition 3 for user (2M)", | ||
| 52 | .size = 0x200000, | ||
| 53 | .offset = 0x00200000, | ||
| 54 | } | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct physmap_flash_data w90p910_flash_data = { | ||
| 58 | .width = 2, | ||
| 59 | .parts = w90p910_flash_partitions, | ||
| 60 | .nr_parts = ARRAY_SIZE(w90p910_flash_partitions), | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct resource w90p910_flash_resources[] = { | ||
| 64 | { | ||
| 65 | .start = W90P910_FLASH_BASE, | ||
| 66 | .end = W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1, | ||
| 67 | .flags = IORESOURCE_MEM, | ||
| 68 | } | ||
| 69 | }; | ||
| 70 | |||
| 71 | static struct platform_device w90p910_flash_device = { | ||
| 72 | .name = "physmap-flash", | ||
| 73 | .id = 0, | ||
| 74 | .dev = { | ||
| 75 | .platform_data = &w90p910_flash_data, | ||
| 76 | }, | ||
| 77 | .resource = w90p910_flash_resources, | ||
| 78 | .num_resources = ARRAY_SIZE(w90p910_flash_resources), | ||
| 79 | }; | ||
| 80 | |||
| 81 | /* USB EHCI Host Controller */ | ||
| 82 | |||
| 83 | static struct resource w90x900_usb_ehci_resource[] = { | ||
| 84 | [0] = { | ||
| 85 | .start = W90X900_PA_USBEHCIHOST, | ||
| 86 | .end = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1, | ||
| 87 | .flags = IORESOURCE_MEM, | ||
| 88 | }, | ||
| 89 | [1] = { | ||
| 90 | .start = IRQ_USBH, | ||
| 91 | .end = IRQ_USBH, | ||
| 92 | .flags = IORESOURCE_IRQ, | ||
| 93 | } | ||
| 94 | }; | ||
| 95 | |||
| 96 | static u64 w90x900_device_usb_ehci_dmamask = 0xffffffffUL; | ||
| 97 | |||
| 98 | struct platform_device w90x900_device_usb_ehci = { | ||
| 99 | .name = "w90x900-ehci", | ||
| 100 | .id = -1, | ||
| 101 | .num_resources = ARRAY_SIZE(w90x900_usb_ehci_resource), | ||
| 102 | .resource = w90x900_usb_ehci_resource, | ||
| 103 | .dev = { | ||
| 104 | .dma_mask = &w90x900_device_usb_ehci_dmamask, | ||
| 105 | .coherent_dma_mask = 0xffffffffUL | ||
| 106 | } | ||
| 107 | }; | ||
| 108 | EXPORT_SYMBOL(w90x900_device_usb_ehci); | ||
| 109 | |||
| 110 | /* USB OHCI Host Controller */ | ||
| 111 | |||
| 112 | static struct resource w90x900_usb_ohci_resource[] = { | ||
| 113 | [0] = { | ||
| 114 | .start = W90X900_PA_USBOHCIHOST, | ||
| 115 | .end = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1, | ||
| 116 | .flags = IORESOURCE_MEM, | ||
| 117 | }, | ||
| 118 | [1] = { | ||
| 119 | .start = IRQ_USBH, | ||
| 120 | .end = IRQ_USBH, | ||
| 121 | .flags = IORESOURCE_IRQ, | ||
| 122 | } | ||
| 123 | }; | ||
| 124 | |||
| 125 | static u64 w90x900_device_usb_ohci_dmamask = 0xffffffffUL; | ||
| 126 | struct platform_device w90x900_device_usb_ohci = { | ||
| 127 | .name = "w90x900-ohci", | ||
| 128 | .id = -1, | ||
| 129 | .num_resources = ARRAY_SIZE(w90x900_usb_ohci_resource), | ||
| 130 | .resource = w90x900_usb_ohci_resource, | ||
| 131 | .dev = { | ||
| 132 | .dma_mask = &w90x900_device_usb_ohci_dmamask, | ||
| 133 | .coherent_dma_mask = 0xffffffffUL | ||
| 134 | } | ||
| 135 | }; | ||
| 136 | EXPORT_SYMBOL(w90x900_device_usb_ohci); | ||
| 137 | |||
| 138 | /*TouchScreen controller*/ | ||
| 139 | |||
| 140 | static struct resource w90x900_ts_resource[] = { | ||
| 141 | [0] = { | ||
| 142 | .start = W90X900_PA_ADC, | ||
| 143 | .end = W90X900_PA_ADC + W90X900_SZ_ADC-1, | ||
| 144 | .flags = IORESOURCE_MEM, | ||
| 145 | }, | ||
| 146 | [1] = { | ||
| 147 | .start = IRQ_ADC, | ||
| 148 | .end = IRQ_ADC, | ||
| 149 | .flags = IORESOURCE_IRQ, | ||
| 150 | }, | ||
| 151 | }; | ||
| 152 | |||
| 153 | struct platform_device w90x900_device_ts = { | ||
| 154 | .name = "w90x900-ts", | ||
| 155 | .id = -1, | ||
| 156 | .resource = w90x900_ts_resource, | ||
| 157 | .num_resources = ARRAY_SIZE(w90x900_ts_resource), | ||
| 158 | }; | ||
| 159 | EXPORT_SYMBOL(w90x900_device_ts); | ||
| 160 | |||
| 161 | /* RTC controller*/ | ||
| 162 | |||
| 163 | static struct resource w90x900_rtc_resource[] = { | ||
| 164 | [0] = { | ||
| 165 | .start = W90X900_PA_RTC, | ||
| 166 | .end = W90X900_PA_RTC + 0xff, | ||
| 167 | .flags = IORESOURCE_MEM, | ||
| 168 | }, | ||
| 169 | [1] = { | ||
| 170 | .start = IRQ_RTC, | ||
| 171 | .end = IRQ_RTC, | ||
| 172 | .flags = IORESOURCE_IRQ, | ||
| 173 | }, | ||
| 174 | }; | ||
| 175 | |||
| 176 | struct platform_device w90x900_device_rtc = { | ||
| 177 | .name = "w90x900-rtc", | ||
| 178 | .id = -1, | ||
| 179 | .num_resources = ARRAY_SIZE(w90x900_rtc_resource), | ||
| 180 | .resource = w90x900_rtc_resource, | ||
| 181 | }; | ||
| 182 | EXPORT_SYMBOL(w90x900_device_rtc); | ||
| 183 | |||
| 184 | /* KPI controller*/ | ||
| 185 | |||
| 186 | static struct resource w90x900_kpi_resource[] = { | ||
| 187 | [0] = { | ||
| 188 | .start = W90X900_PA_KPI, | ||
| 189 | .end = W90X900_PA_KPI + W90X900_SZ_KPI - 1, | ||
| 190 | .flags = IORESOURCE_MEM, | ||
| 191 | }, | ||
| 192 | [1] = { | ||
| 193 | .start = IRQ_KPI, | ||
| 194 | .end = IRQ_KPI, | ||
| 195 | .flags = IORESOURCE_IRQ, | ||
| 196 | } | ||
| 197 | |||
| 198 | }; | ||
| 199 | |||
| 200 | struct platform_device w90x900_device_kpi = { | ||
| 201 | .name = "w90x900-kpi", | ||
| 202 | .id = -1, | ||
| 203 | .num_resources = ARRAY_SIZE(w90x900_kpi_resource), | ||
| 204 | .resource = w90x900_kpi_resource, | ||
| 205 | }; | ||
| 206 | EXPORT_SYMBOL(w90x900_device_kpi); | ||
| 207 | |||
| 208 | /* USB Device (Gadget)*/ | ||
| 209 | |||
| 210 | static struct resource w90x900_usbgadget_resource[] = { | ||
| 211 | [0] = { | ||
| 212 | .start = W90X900_PA_USBDEV, | ||
| 213 | .end = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1, | ||
| 214 | .flags = IORESOURCE_MEM, | ||
| 215 | }, | ||
| 216 | [1] = { | ||
| 217 | .start = IRQ_USBD, | ||
| 218 | .end = IRQ_USBD, | ||
| 219 | .flags = IORESOURCE_IRQ, | ||
| 220 | } | ||
| 221 | }; | ||
| 222 | |||
| 223 | struct platform_device w90x900_device_usbgadget = { | ||
| 224 | .name = "w90x900-usbgadget", | ||
| 225 | .id = -1, | ||
| 226 | .num_resources = ARRAY_SIZE(w90x900_usbgadget_resource), | ||
| 227 | .resource = w90x900_usbgadget_resource, | ||
| 228 | }; | ||
| 229 | EXPORT_SYMBOL(w90x900_device_usbgadget); | ||
| 230 | |||
| 231 | static struct map_desc w90p910_iodesc[] __initdata = { | ||
| 232 | }; | ||
| 233 | |||
| 234 | /*Here should be your evb resourse,such as LCD*/ | ||
| 235 | |||
| 236 | static struct platform_device *w90p910evb_dev[] __initdata = { | ||
| 237 | &w90p910_serial_device, | ||
| 238 | &w90p910_flash_device, | ||
| 239 | &w90x900_device_usb_ehci, | ||
| 240 | &w90x900_device_usb_ohci, | ||
| 241 | &w90x900_device_ts, | ||
| 242 | &w90x900_device_rtc, | ||
| 243 | &w90x900_device_kpi, | ||
| 244 | &w90x900_device_usbgadget, | ||
| 245 | }; | ||
| 246 | |||
| 247 | static void __init w90p910evb_map_io(void) | ||
| 248 | { | ||
| 249 | w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); | ||
| 250 | w90p910_init_clocks(); | ||
| 251 | } | ||
| 252 | |||
| 253 | static void __init w90p910evb_init(void) | ||
| 254 | { | ||
| 255 | platform_add_devices(w90p910evb_dev, ARRAY_SIZE(w90p910evb_dev)); | ||
| 256 | } | ||
| 257 | |||
| 258 | MACHINE_START(W90P910EVB, "W90P910EVB") | ||
| 259 | /* Maintainer: Wan ZongShun */ | ||
| 260 | .phys_io = W90X900_PA_UART, | ||
| 261 | .io_pg_offst = (((u32)W90X900_VA_UART) >> 18) & 0xfffc, | ||
| 262 | .boot_params = 0, | ||
| 263 | .map_io = w90p910evb_map_io, | ||
| 264 | .init_irq = w90x900_init_irq, | ||
| 265 | .init_machine = w90p910evb_init, | ||
| 266 | .timer = &w90x900_timer, | ||
| 267 | MACHINE_END | ||
diff --git a/arch/arm/mach-w90x900/mfp-w90p910.c b/arch/arm/mach-w90x900/mfp-w90p910.c deleted file mode 100644 index a3520fefb5e7..000000000000 --- a/arch/arm/mach-w90x900/mfp-w90p910.c +++ /dev/null | |||
| @@ -1,116 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mfp-w90p910.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation;version 2 of the License. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/device.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/string.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | #include <linux/mutex.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | |||
| 26 | #define REG_MFSEL (W90X900_VA_GCR + 0xC) | ||
| 27 | |||
| 28 | #define GPSELF (0x01 << 1) | ||
| 29 | |||
| 30 | #define GPSELC (0x03 << 2) | ||
| 31 | #define ENKPI (0x02 << 2) | ||
| 32 | #define ENNAND (0x01 << 2) | ||
| 33 | |||
| 34 | #define GPSELEI0 (0x01 << 26) | ||
| 35 | #define GPSELEI1 (0x01 << 27) | ||
| 36 | |||
| 37 | static DECLARE_MUTEX(mfp_sem); | ||
| 38 | |||
| 39 | void mfp_set_groupf(struct device *dev) | ||
| 40 | { | ||
| 41 | unsigned long mfpen; | ||
| 42 | const char *dev_id; | ||
| 43 | |||
| 44 | BUG_ON(!dev); | ||
| 45 | |||
| 46 | down(&mfp_sem); | ||
| 47 | |||
| 48 | dev_id = dev_name(dev); | ||
| 49 | |||
| 50 | mfpen = __raw_readl(REG_MFSEL); | ||
| 51 | |||
| 52 | if (strcmp(dev_id, "w90p910-emc") == 0) | ||
| 53 | mfpen |= GPSELF;/*enable mac*/ | ||
| 54 | else | ||
| 55 | mfpen &= ~GPSELF;/*GPIOF[9:0]*/ | ||
| 56 | |||
| 57 | __raw_writel(mfpen, REG_MFSEL); | ||
| 58 | |||
| 59 | up(&mfp_sem); | ||
| 60 | } | ||
| 61 | EXPORT_SYMBOL(mfp_set_groupf); | ||
| 62 | |||
| 63 | void mfp_set_groupc(struct device *dev) | ||
| 64 | { | ||
| 65 | unsigned long mfpen; | ||
| 66 | const char *dev_id; | ||
| 67 | |||
| 68 | BUG_ON(!dev); | ||
| 69 | |||
| 70 | down(&mfp_sem); | ||
| 71 | |||
| 72 | dev_id = dev_name(dev); | ||
| 73 | |||
| 74 | mfpen = __raw_readl(REG_MFSEL); | ||
| 75 | |||
| 76 | if (strcmp(dev_id, "w90p910-lcd") == 0) | ||
| 77 | mfpen |= GPSELC;/*enable lcd*/ | ||
| 78 | else if (strcmp(dev_id, "w90p910-kpi") == 0) { | ||
| 79 | mfpen &= (~GPSELC);/*enable kpi*/ | ||
| 80 | mfpen |= ENKPI; | ||
| 81 | } else if (strcmp(dev_id, "w90p910-nand") == 0) { | ||
| 82 | mfpen &= (~GPSELC);/*enable nand*/ | ||
| 83 | mfpen |= ENNAND; | ||
| 84 | } else | ||
| 85 | mfpen &= (~GPSELC);/*GPIOC[14:0]*/ | ||
| 86 | |||
| 87 | __raw_writel(mfpen, REG_MFSEL); | ||
| 88 | |||
| 89 | up(&mfp_sem); | ||
| 90 | } | ||
| 91 | EXPORT_SYMBOL(mfp_set_groupc); | ||
| 92 | |||
| 93 | void mfp_set_groupi(struct device *dev, int gpio) | ||
| 94 | { | ||
| 95 | unsigned long mfpen; | ||
| 96 | const char *dev_id; | ||
| 97 | |||
| 98 | BUG_ON(!dev); | ||
| 99 | |||
| 100 | down(&mfp_sem); | ||
| 101 | |||
| 102 | dev_id = dev_name(dev); | ||
| 103 | |||
| 104 | mfpen = __raw_readl(REG_MFSEL); | ||
| 105 | |||
| 106 | if (strcmp(dev_id, "w90p910-wdog") == 0) | ||
| 107 | mfpen |= GPSELEI1;/*enable wdog*/ | ||
| 108 | else if (strcmp(dev_id, "w90p910-atapi") == 0) | ||
| 109 | mfpen |= GPSELEI0;/*enable atapi*/ | ||
| 110 | |||
| 111 | __raw_writel(mfpen, REG_MFSEL); | ||
| 112 | |||
| 113 | up(&mfp_sem); | ||
| 114 | } | ||
| 115 | EXPORT_SYMBOL(mfp_set_groupi); | ||
| 116 | |||
diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c new file mode 100644 index 000000000000..a47dc9a708ee --- /dev/null +++ b/arch/arm/mach-w90x900/mfp.c | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/mfp.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton technology corporation | ||
| 5 | * | ||
| 6 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation;version 2 of the License. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/device.h> | ||
| 16 | #include <linux/list.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/err.h> | ||
| 19 | #include <linux/string.h> | ||
| 20 | #include <linux/clk.h> | ||
| 21 | #include <linux/mutex.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | |||
| 26 | #define REG_MFSEL (W90X900_VA_GCR + 0xC) | ||
| 27 | |||
| 28 | #define GPSELF (0x01 << 1) | ||
| 29 | |||
| 30 | #define GPSELC (0x03 << 2) | ||
| 31 | #define ENKPI (0x02 << 2) | ||
| 32 | #define ENNAND (0x01 << 2) | ||
| 33 | |||
| 34 | #define GPSELEI0 (0x01 << 26) | ||
| 35 | #define GPSELEI1 (0x01 << 27) | ||
| 36 | |||
| 37 | #define GPIOG0TO1 (0x03 << 14) | ||
| 38 | #define GPIOG2TO3 (0x03 << 16) | ||
| 39 | #define ENSPI (0x0a << 14) | ||
| 40 | #define ENI2C0 (0x01 << 14) | ||
| 41 | #define ENI2C1 (0x01 << 16) | ||
| 42 | |||
| 43 | static DEFINE_MUTEX(mfp_mutex); | ||
| 44 | |||
| 45 | void mfp_set_groupf(struct device *dev) | ||
| 46 | { | ||
| 47 | unsigned long mfpen; | ||
| 48 | const char *dev_id; | ||
| 49 | |||
| 50 | BUG_ON(!dev); | ||
| 51 | |||
| 52 | mutex_lock(&mfp_mutex); | ||
| 53 | |||
| 54 | dev_id = dev_name(dev); | ||
| 55 | |||
| 56 | mfpen = __raw_readl(REG_MFSEL); | ||
| 57 | |||
| 58 | if (strcmp(dev_id, "nuc900-emc") == 0) | ||
| 59 | mfpen |= GPSELF;/*enable mac*/ | ||
| 60 | else | ||
| 61 | mfpen &= ~GPSELF;/*GPIOF[9:0]*/ | ||
| 62 | |||
| 63 | __raw_writel(mfpen, REG_MFSEL); | ||
| 64 | |||
| 65 | mutex_unlock(&mfp_mutex); | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL(mfp_set_groupf); | ||
| 68 | |||
| 69 | void mfp_set_groupc(struct device *dev) | ||
| 70 | { | ||
| 71 | unsigned long mfpen; | ||
| 72 | const char *dev_id; | ||
| 73 | |||
| 74 | BUG_ON(!dev); | ||
| 75 | |||
| 76 | mutex_lock(&mfp_mutex); | ||
| 77 | |||
| 78 | dev_id = dev_name(dev); | ||
| 79 | |||
| 80 | mfpen = __raw_readl(REG_MFSEL); | ||
| 81 | |||
| 82 | if (strcmp(dev_id, "nuc900-lcd") == 0) | ||
| 83 | mfpen |= GPSELC;/*enable lcd*/ | ||
| 84 | else if (strcmp(dev_id, "nuc900-kpi") == 0) { | ||
| 85 | mfpen &= (~GPSELC);/*enable kpi*/ | ||
| 86 | mfpen |= ENKPI; | ||
| 87 | } else if (strcmp(dev_id, "nuc900-nand") == 0) { | ||
| 88 | mfpen &= (~GPSELC);/*enable nand*/ | ||
| 89 | mfpen |= ENNAND; | ||
| 90 | } else | ||
| 91 | mfpen &= (~GPSELC);/*GPIOC[14:0]*/ | ||
| 92 | |||
| 93 | __raw_writel(mfpen, REG_MFSEL); | ||
| 94 | |||
| 95 | mutex_unlock(&mfp_mutex); | ||
| 96 | } | ||
| 97 | EXPORT_SYMBOL(mfp_set_groupc); | ||
| 98 | |||
| 99 | void mfp_set_groupi(struct device *dev) | ||
| 100 | { | ||
| 101 | unsigned long mfpen; | ||
| 102 | const char *dev_id; | ||
| 103 | |||
| 104 | BUG_ON(!dev); | ||
| 105 | |||
| 106 | mutex_lock(&mfp_mutex); | ||
| 107 | |||
| 108 | dev_id = dev_name(dev); | ||
| 109 | |||
| 110 | mfpen = __raw_readl(REG_MFSEL); | ||
| 111 | |||
| 112 | mfpen &= ~GPSELEI1;/*default gpio16*/ | ||
| 113 | |||
| 114 | if (strcmp(dev_id, "nuc900-wdog") == 0) | ||
| 115 | mfpen |= GPSELEI1;/*enable wdog*/ | ||
| 116 | else if (strcmp(dev_id, "nuc900-atapi") == 0) | ||
| 117 | mfpen |= GPSELEI0;/*enable atapi*/ | ||
| 118 | else if (strcmp(dev_id, "nuc900-keypad") == 0) | ||
| 119 | mfpen &= ~GPSELEI0;/*enable keypad*/ | ||
| 120 | |||
| 121 | __raw_writel(mfpen, REG_MFSEL); | ||
| 122 | |||
| 123 | mutex_unlock(&mfp_mutex); | ||
| 124 | } | ||
| 125 | EXPORT_SYMBOL(mfp_set_groupi); | ||
| 126 | |||
| 127 | void mfp_set_groupg(struct device *dev) | ||
| 128 | { | ||
| 129 | unsigned long mfpen; | ||
| 130 | const char *dev_id; | ||
| 131 | |||
| 132 | BUG_ON(!dev); | ||
| 133 | |||
| 134 | mutex_lock(&mfp_mutex); | ||
| 135 | |||
| 136 | dev_id = dev_name(dev); | ||
| 137 | |||
| 138 | mfpen = __raw_readl(REG_MFSEL); | ||
| 139 | |||
| 140 | if (strcmp(dev_id, "nuc900-spi") == 0) { | ||
| 141 | mfpen &= ~(GPIOG0TO1 | GPIOG2TO3); | ||
| 142 | mfpen |= ENSPI;/*enable spi*/ | ||
| 143 | } else if (strcmp(dev_id, "nuc900-i2c0") == 0) { | ||
| 144 | mfpen &= ~(GPIOG0TO1); | ||
| 145 | mfpen |= ENI2C0;/*enable i2c0*/ | ||
| 146 | } else if (strcmp(dev_id, "nuc900-i2c1") == 0) { | ||
| 147 | mfpen &= ~(GPIOG2TO3); | ||
| 148 | mfpen |= ENI2C1;/*enable i2c1*/ | ||
| 149 | } else { | ||
| 150 | mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/ | ||
| 151 | } | ||
| 152 | |||
| 153 | __raw_writel(mfpen, REG_MFSEL); | ||
| 154 | |||
| 155 | mutex_unlock(&mfp_mutex); | ||
| 156 | } | ||
| 157 | EXPORT_SYMBOL(mfp_set_groupg); | ||
| 158 | |||
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c new file mode 100644 index 000000000000..656f03b3b629 --- /dev/null +++ b/arch/arm/mach-w90x900/nuc910.c | |||
| @@ -0,0 +1,60 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/nuc910.c | ||
| 3 | * | ||
| 4 | * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks | ||
| 5 | * | ||
| 6 | * Copyright (c) 2009 Nuvoton corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * NUC910 cpu support | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation;version 2 of the License. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <asm/mach/map.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include "cpu.h" | ||
| 22 | #include "clock.h" | ||
| 23 | |||
| 24 | /* define specific CPU platform device */ | ||
| 25 | |||
| 26 | static struct platform_device *nuc910_dev[] __initdata = { | ||
| 27 | &nuc900_device_ts, | ||
| 28 | &nuc900_device_rtc, | ||
| 29 | }; | ||
| 30 | |||
| 31 | /* define specific CPU platform io map */ | ||
| 32 | |||
| 33 | static struct map_desc nuc910evb_iodesc[] __initdata = { | ||
| 34 | IODESC_ENT(USBEHCIHOST), | ||
| 35 | IODESC_ENT(USBOHCIHOST), | ||
| 36 | IODESC_ENT(KPI), | ||
| 37 | IODESC_ENT(USBDEV), | ||
| 38 | IODESC_ENT(ADC), | ||
| 39 | }; | ||
| 40 | |||
| 41 | /*Init NUC910 evb io*/ | ||
| 42 | |||
| 43 | void __init nuc910_map_io(void) | ||
| 44 | { | ||
| 45 | nuc900_map_io(nuc910evb_iodesc, ARRAY_SIZE(nuc910evb_iodesc)); | ||
| 46 | } | ||
| 47 | |||
| 48 | /*Init NUC910 clock*/ | ||
| 49 | |||
| 50 | void __init nuc910_init_clocks(void) | ||
| 51 | { | ||
| 52 | nuc900_init_clocks(); | ||
| 53 | } | ||
| 54 | |||
| 55 | /*Init NUC910 board info*/ | ||
| 56 | |||
| 57 | void __init nuc910_board_init(void) | ||
| 58 | { | ||
| 59 | nuc900_board_init(nuc910_dev, ARRAY_SIZE(nuc910_dev)); | ||
| 60 | } | ||
diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h new file mode 100644 index 000000000000..83e9ba5fc26c --- /dev/null +++ b/arch/arm/mach-w90x900/nuc910.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/nuc910.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton corporation | ||
| 5 | * | ||
| 6 | * Header file for NUC900 CPU support | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct map_desc; | ||
| 17 | struct sys_timer; | ||
| 18 | |||
| 19 | /* core initialisation functions */ | ||
| 20 | |||
| 21 | extern void nuc900_init_irq(void); | ||
| 22 | extern struct sys_timer nuc900_timer; | ||
| 23 | |||
| 24 | /* extern file from nuc910.c */ | ||
| 25 | |||
| 26 | extern void nuc910_board_init(void); | ||
| 27 | extern void nuc910_init_clocks(void); | ||
| 28 | extern void nuc910_map_io(void); | ||
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c new file mode 100644 index 000000000000..149508116d18 --- /dev/null +++ b/arch/arm/mach-w90x900/nuc950.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/nuc950.c | ||
| 3 | * | ||
| 4 | * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * NUC950 cpu support | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation;version 2 of the License. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <asm/mach/map.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include "cpu.h" | ||
| 22 | |||
| 23 | /* define specific CPU platform device */ | ||
| 24 | |||
| 25 | static struct platform_device *nuc950_dev[] __initdata = { | ||
| 26 | &nuc900_device_kpi, | ||
| 27 | &nuc900_device_fmi, | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* define specific CPU platform io map */ | ||
| 31 | |||
| 32 | static struct map_desc nuc950evb_iodesc[] __initdata = { | ||
| 33 | }; | ||
| 34 | |||
| 35 | /*Init NUC950 evb io*/ | ||
| 36 | |||
| 37 | void __init nuc950_map_io(void) | ||
| 38 | { | ||
| 39 | nuc900_map_io(nuc950evb_iodesc, ARRAY_SIZE(nuc950evb_iodesc)); | ||
| 40 | } | ||
| 41 | |||
| 42 | /*Init NUC950 clock*/ | ||
| 43 | |||
| 44 | void __init nuc950_init_clocks(void) | ||
| 45 | { | ||
| 46 | nuc900_init_clocks(); | ||
| 47 | } | ||
| 48 | |||
| 49 | /*Init NUC950 board info*/ | ||
| 50 | |||
| 51 | void __init nuc950_board_init(void) | ||
| 52 | { | ||
| 53 | nuc900_board_init(nuc950_dev, ARRAY_SIZE(nuc950_dev)); | ||
| 54 | } | ||
diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h new file mode 100644 index 000000000000..98a1148bc5ae --- /dev/null +++ b/arch/arm/mach-w90x900/nuc950.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/nuc950.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton corporation | ||
| 5 | * | ||
| 6 | * Header file for NUC900 CPU support | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct map_desc; | ||
| 17 | struct sys_timer; | ||
| 18 | |||
| 19 | /* core initialisation functions */ | ||
| 20 | |||
| 21 | extern void nuc900_init_irq(void); | ||
| 22 | extern struct sys_timer nuc900_timer; | ||
| 23 | |||
| 24 | /* extern file from nuc950.c */ | ||
| 25 | |||
| 26 | extern void nuc950_board_init(void); | ||
| 27 | extern void nuc950_init_clocks(void); | ||
| 28 | extern void nuc950_map_io(void); | ||
diff --git a/arch/arm/mach-w90x900/nuc960.c b/arch/arm/mach-w90x900/nuc960.c new file mode 100644 index 000000000000..8851a3a27ce2 --- /dev/null +++ b/arch/arm/mach-w90x900/nuc960.c | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/nuc960.c | ||
| 3 | * | ||
| 4 | * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * NUC960 cpu support | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation;version 2 of the License. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/platform_device.h> | ||
| 19 | #include <asm/mach/map.h> | ||
| 20 | #include <mach/hardware.h> | ||
| 21 | #include "cpu.h" | ||
| 22 | |||
| 23 | /* define specific CPU platform device */ | ||
| 24 | |||
| 25 | static struct platform_device *nuc960_dev[] __initdata = { | ||
| 26 | &nuc900_device_kpi, | ||
| 27 | &nuc900_device_fmi, | ||
| 28 | }; | ||
| 29 | |||
| 30 | /* define specific CPU platform io map */ | ||
| 31 | |||
| 32 | static struct map_desc nuc960evb_iodesc[] __initdata = { | ||
| 33 | }; | ||
| 34 | |||
| 35 | /*Init NUC960 evb io*/ | ||
| 36 | |||
| 37 | void __init nuc960_map_io(void) | ||
| 38 | { | ||
| 39 | nuc900_map_io(nuc960evb_iodesc, ARRAY_SIZE(nuc960evb_iodesc)); | ||
| 40 | } | ||
| 41 | |||
| 42 | /*Init NUC960 clock*/ | ||
| 43 | |||
| 44 | void __init nuc960_init_clocks(void) | ||
| 45 | { | ||
| 46 | nuc900_init_clocks(); | ||
| 47 | } | ||
| 48 | |||
| 49 | /*Init NUC960 board info*/ | ||
| 50 | |||
| 51 | void __init nuc960_board_init(void) | ||
| 52 | { | ||
| 53 | nuc900_board_init(nuc960_dev, ARRAY_SIZE(nuc960_dev)); | ||
| 54 | } | ||
diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h new file mode 100644 index 000000000000..f0c07cbe3a82 --- /dev/null +++ b/arch/arm/mach-w90x900/nuc960.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-w90x900/nuc960.h | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Nuvoton corporation | ||
| 5 | * | ||
| 6 | * Header file for NUC900 CPU support | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | * | ||
| 14 | */ | ||
| 15 | |||
| 16 | struct map_desc; | ||
| 17 | struct sys_timer; | ||
| 18 | |||
| 19 | /* core initialisation functions */ | ||
| 20 | |||
| 21 | extern void nuc900_init_irq(void); | ||
| 22 | extern struct sys_timer nuc900_timer; | ||
| 23 | |||
| 24 | /* extern file from nuc960.c */ | ||
| 25 | |||
| 26 | extern void nuc960_board_init(void); | ||
| 27 | extern void nuc960_init_clocks(void); | ||
| 28 | extern void nuc960_map_io(void); | ||
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c index bcc838f6b393..4128af870b41 100644 --- a/arch/arm/mach-w90x900/time.c +++ b/arch/arm/mach-w90x900/time.c | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * | 3 | * |
| 4 | * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks | 4 | * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks |
| 5 | * | 5 | * |
| 6 | * Copyright (c) 2008 Nuvoton technology corporation | 6 | * Copyright (c) 2009 Nuvoton technology corporation |
| 7 | * All rights reserved. | 7 | * All rights reserved. |
| 8 | * | 8 | * |
| 9 | * Wan ZongShun <mcuos.com@gmail.com> | 9 | * Wan ZongShun <mcuos.com@gmail.com> |
| @@ -23,6 +23,8 @@ | |||
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
| 25 | #include <linux/leds.h> | 25 | #include <linux/leds.h> |
| 26 | #include <linux/clocksource.h> | ||
| 27 | #include <linux/clockchips.h> | ||
| 26 | 28 | ||
| 27 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
| @@ -31,49 +33,150 @@ | |||
| 31 | #include <mach/map.h> | 33 | #include <mach/map.h> |
| 32 | #include <mach/regs-timer.h> | 34 | #include <mach/regs-timer.h> |
| 33 | 35 | ||
| 34 | static unsigned long w90x900_gettimeoffset(void) | 36 | #define RESETINT 0x1f |
| 37 | #define PERIOD (0x01 << 27) | ||
| 38 | #define ONESHOT (0x00 << 27) | ||
| 39 | #define COUNTEN (0x01 << 30) | ||
| 40 | #define INTEN (0x01 << 29) | ||
| 41 | |||
| 42 | #define TICKS_PER_SEC 100 | ||
| 43 | #define PRESCALE 0x63 /* Divider = prescale + 1 */ | ||
| 44 | |||
| 45 | unsigned int timer0_load; | ||
| 46 | |||
| 47 | static void nuc900_clockevent_setmode(enum clock_event_mode mode, | ||
| 48 | struct clock_event_device *clk) | ||
| 35 | { | 49 | { |
| 50 | unsigned int val; | ||
| 51 | |||
| 52 | val = __raw_readl(REG_TCSR0); | ||
| 53 | val &= ~(0x03 << 27); | ||
| 54 | |||
| 55 | switch (mode) { | ||
| 56 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 57 | __raw_writel(timer0_load, REG_TICR0); | ||
| 58 | val |= (PERIOD | COUNTEN | INTEN | PRESCALE); | ||
| 59 | break; | ||
| 60 | |||
| 61 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 62 | val |= (ONESHOT | COUNTEN | INTEN | PRESCALE); | ||
| 63 | break; | ||
| 64 | |||
| 65 | case CLOCK_EVT_MODE_UNUSED: | ||
| 66 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 67 | case CLOCK_EVT_MODE_RESUME: | ||
| 68 | break; | ||
| 69 | } | ||
| 70 | |||
| 71 | __raw_writel(val, REG_TCSR0); | ||
| 72 | } | ||
| 73 | |||
| 74 | static int nuc900_clockevent_setnextevent(unsigned long evt, | ||
| 75 | struct clock_event_device *clk) | ||
| 76 | { | ||
| 77 | unsigned int val; | ||
| 78 | |||
| 79 | __raw_writel(evt, REG_TICR0); | ||
| 80 | |||
| 81 | val = __raw_readl(REG_TCSR0); | ||
| 82 | val |= (COUNTEN | INTEN | PRESCALE); | ||
| 83 | __raw_writel(val, REG_TCSR0); | ||
| 84 | |||
| 36 | return 0; | 85 | return 0; |
| 37 | } | 86 | } |
| 38 | 87 | ||
| 88 | static struct clock_event_device nuc900_clockevent_device = { | ||
| 89 | .name = "nuc900-timer0", | ||
| 90 | .shift = 32, | ||
| 91 | .features = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | ||
| 92 | .set_mode = nuc900_clockevent_setmode, | ||
| 93 | .set_next_event = nuc900_clockevent_setnextevent, | ||
| 94 | .rating = 300, | ||
| 95 | }; | ||
| 96 | |||
| 39 | /*IRQ handler for the timer*/ | 97 | /*IRQ handler for the timer*/ |
| 40 | 98 | ||
| 41 | static irqreturn_t | 99 | static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id) |
| 42 | w90x900_timer_interrupt(int irq, void *dev_id) | ||
| 43 | { | 100 | { |
| 44 | timer_tick(); | 101 | struct clock_event_device *evt = &nuc900_clockevent_device; |
| 102 | |||
| 45 | __raw_writel(0x01, REG_TISR); /* clear TIF0 */ | 103 | __raw_writel(0x01, REG_TISR); /* clear TIF0 */ |
| 104 | |||
| 105 | evt->event_handler(evt); | ||
| 46 | return IRQ_HANDLED; | 106 | return IRQ_HANDLED; |
| 47 | } | 107 | } |
| 48 | 108 | ||
| 49 | static struct irqaction w90x900_timer_irq = { | 109 | static struct irqaction nuc900_timer0_irq = { |
| 50 | .name = "w90x900 Timer Tick", | 110 | .name = "nuc900-timer0", |
| 51 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | 111 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
| 52 | .handler = w90x900_timer_interrupt, | 112 | .handler = nuc900_timer0_interrupt, |
| 53 | }; | 113 | }; |
| 54 | 114 | ||
| 55 | /*Set up timer reg.*/ | 115 | static void __init nuc900_clockevents_init(unsigned int rate) |
| 116 | { | ||
| 117 | nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC, | ||
| 118 | nuc900_clockevent_device.shift); | ||
| 119 | nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff, | ||
| 120 | &nuc900_clockevent_device); | ||
| 121 | nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf, | ||
| 122 | &nuc900_clockevent_device); | ||
| 123 | nuc900_clockevent_device.cpumask = cpumask_of(0); | ||
| 56 | 124 | ||
| 57 | static void w90x900_timer_setup(void) | 125 | clockevents_register_device(&nuc900_clockevent_device); |
| 126 | } | ||
| 127 | |||
| 128 | static cycle_t nuc900_get_cycles(struct clocksource *cs) | ||
| 58 | { | 129 | { |
| 59 | __raw_writel(0, REG_TCSR0); | 130 | return ~__raw_readl(REG_TDR1); |
| 60 | __raw_writel(0, REG_TCSR1); | ||
| 61 | __raw_writel(0, REG_TCSR2); | ||
| 62 | __raw_writel(0, REG_TCSR3); | ||
| 63 | __raw_writel(0, REG_TCSR4); | ||
| 64 | __raw_writel(0x1F, REG_TISR); | ||
| 65 | __raw_writel(15000000/(100 * 100), REG_TICR0); | ||
| 66 | __raw_writel(0x68000063, REG_TCSR0); | ||
| 67 | } | 131 | } |
| 68 | 132 | ||
| 69 | static void __init w90x900_timer_init(void) | 133 | static struct clocksource clocksource_nuc900 = { |
| 134 | .name = "nuc900-timer1", | ||
| 135 | .rating = 200, | ||
| 136 | .read = nuc900_get_cycles, | ||
| 137 | .mask = CLOCKSOURCE_MASK(32), | ||
| 138 | .shift = 20, | ||
| 139 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 140 | }; | ||
| 141 | |||
| 142 | static void __init nuc900_clocksource_init(unsigned int rate) | ||
| 70 | { | 143 | { |
| 71 | w90x900_timer_setup(); | 144 | unsigned int val; |
| 72 | setup_irq(IRQ_TIMER0, &w90x900_timer_irq); | 145 | |
| 146 | __raw_writel(0xffffffff, REG_TICR1); | ||
| 147 | |||
| 148 | val = __raw_readl(REG_TCSR1); | ||
| 149 | val |= (COUNTEN | PERIOD); | ||
| 150 | __raw_writel(val, REG_TCSR1); | ||
| 151 | |||
| 152 | clocksource_nuc900.mult = | ||
| 153 | clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift); | ||
| 154 | clocksource_register(&clocksource_nuc900); | ||
| 155 | } | ||
| 156 | |||
| 157 | static void __init nuc900_timer_init(void) | ||
| 158 | { | ||
| 159 | struct clk *ck_ext = clk_get(NULL, "ext"); | ||
| 160 | unsigned int rate; | ||
| 161 | |||
| 162 | BUG_ON(IS_ERR(ck_ext)); | ||
| 163 | |||
| 164 | rate = clk_get_rate(ck_ext); | ||
| 165 | clk_put(ck_ext); | ||
| 166 | rate = rate / (PRESCALE + 0x01); | ||
| 167 | |||
| 168 | /* set a known state */ | ||
| 169 | __raw_writel(0x00, REG_TCSR0); | ||
| 170 | __raw_writel(0x00, REG_TCSR1); | ||
| 171 | __raw_writel(RESETINT, REG_TISR); | ||
| 172 | timer0_load = (rate / TICKS_PER_SEC); | ||
| 173 | |||
| 174 | setup_irq(IRQ_TIMER0, &nuc900_timer0_irq); | ||
| 175 | |||
| 176 | nuc900_clocksource_init(rate); | ||
| 177 | nuc900_clockevents_init(rate); | ||
| 73 | } | 178 | } |
| 74 | 179 | ||
| 75 | struct sys_timer w90x900_timer = { | 180 | struct sys_timer nuc900_timer = { |
| 76 | .init = w90x900_timer_init, | 181 | .init = nuc900_timer_init, |
| 77 | .offset = w90x900_gettimeoffset, | ||
| 78 | .resume = w90x900_timer_setup | ||
| 79 | }; | 182 | }; |
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c deleted file mode 100644 index 1c97e4930b7a..000000000000 --- a/arch/arm/mach-w90x900/w90p910.c +++ /dev/null | |||
| @@ -1,136 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-w90x900/w90p910.c | ||
| 3 | * | ||
| 4 | * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks | ||
| 5 | * | ||
| 6 | * Copyright (c) 2008 Nuvoton technology corporation. | ||
| 7 | * | ||
| 8 | * Wan ZongShun <mcuos.com@gmail.com> | ||
| 9 | * | ||
| 10 | * W90P910 cpu support | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License as published by | ||
| 14 | * the Free Software Foundation;version 2 of the License. | ||
| 15 | * | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/interrupt.h> | ||
| 21 | #include <linux/list.h> | ||
| 22 | #include <linux/timer.h> | ||
| 23 | #include <linux/init.h> | ||
| 24 | #include <linux/platform_device.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | #include <linux/serial_8250.h> | ||
| 27 | |||
| 28 | #include <asm/mach/arch.h> | ||
| 29 | #include <asm/mach/map.h> | ||
| 30 | #include <asm/mach/irq.h> | ||
| 31 | #include <asm/irq.h> | ||
| 32 | |||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <mach/regs-serial.h> | ||
| 35 | |||
| 36 | #include "cpu.h" | ||
| 37 | #include "clock.h" | ||
| 38 | |||
| 39 | /* Initial IO mappings */ | ||
| 40 | |||
| 41 | static struct map_desc w90p910_iodesc[] __initdata = { | ||
| 42 | IODESC_ENT(IRQ), | ||
| 43 | IODESC_ENT(GCR), | ||
| 44 | IODESC_ENT(UART), | ||
| 45 | IODESC_ENT(TIMER), | ||
| 46 | IODESC_ENT(EBI), | ||
| 47 | IODESC_ENT(USBEHCIHOST), | ||
| 48 | IODESC_ENT(USBOHCIHOST), | ||
| 49 | IODESC_ENT(ADC), | ||
| 50 | IODESC_ENT(RTC), | ||
| 51 | IODESC_ENT(KPI), | ||
| 52 | IODESC_ENT(USBDEV), | ||
| 53 | /*IODESC_ENT(LCD),*/ | ||
| 54 | }; | ||
| 55 | |||
| 56 | /* Initial clock declarations. */ | ||
| 57 | static DEFINE_CLK(lcd, 0); | ||
| 58 | static DEFINE_CLK(audio, 1); | ||
| 59 | static DEFINE_CLK(fmi, 4); | ||
| 60 | static DEFINE_CLK(dmac, 5); | ||
| 61 | static DEFINE_CLK(atapi, 6); | ||
| 62 | static DEFINE_CLK(emc, 7); | ||
| 63 | static DEFINE_CLK(usbd, 8); | ||
| 64 | static DEFINE_CLK(usbh, 9); | ||
| 65 | static DEFINE_CLK(g2d, 10);; | ||
| 66 | static DEFINE_CLK(pwm, 18); | ||
| 67 | static DEFINE_CLK(ps2, 24); | ||
| 68 | static DEFINE_CLK(kpi, 25); | ||
| 69 | static DEFINE_CLK(wdt, 26); | ||
| 70 | static DEFINE_CLK(gdma, 27); | ||
| 71 | static DEFINE_CLK(adc, 28); | ||
| 72 | static DEFINE_CLK(usi, 29); | ||
| 73 | |||
| 74 | static struct clk_lookup w90p910_clkregs[] = { | ||
| 75 | DEF_CLKLOOK(&clk_lcd, "w90p910-lcd", NULL), | ||
| 76 | DEF_CLKLOOK(&clk_audio, "w90p910-audio", NULL), | ||
| 77 | DEF_CLKLOOK(&clk_fmi, "w90p910-fmi", NULL), | ||
| 78 | DEF_CLKLOOK(&clk_dmac, "w90p910-dmac", NULL), | ||
| 79 | DEF_CLKLOOK(&clk_atapi, "w90p910-atapi", NULL), | ||
| 80 | DEF_CLKLOOK(&clk_emc, "w90p910-emc", NULL), | ||
| 81 | DEF_CLKLOOK(&clk_usbd, "w90p910-usbd", NULL), | ||
| 82 | DEF_CLKLOOK(&clk_usbh, "w90p910-usbh", NULL), | ||
| 83 | DEF_CLKLOOK(&clk_g2d, "w90p910-g2d", NULL), | ||
| 84 | DEF_CLKLOOK(&clk_pwm, "w90p910-pwm", NULL), | ||
| 85 | DEF_CLKLOOK(&clk_ps2, "w90p910-ps2", NULL), | ||
| 86 | DEF_CLKLOOK(&clk_kpi, "w90p910-kpi", NULL), | ||
| 87 | DEF_CLKLOOK(&clk_wdt, "w90p910-wdt", NULL), | ||
| 88 | DEF_CLKLOOK(&clk_gdma, "w90p910-gdma", NULL), | ||
| 89 | DEF_CLKLOOK(&clk_adc, "w90p910-adc", NULL), | ||
| 90 | DEF_CLKLOOK(&clk_usi, "w90p910-usi", NULL), | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* Initial serial platform data */ | ||
| 94 | |||
| 95 | struct plat_serial8250_port w90p910_uart_data[] = { | ||
| 96 | W90X900_8250PORT(UART0), | ||
| 97 | }; | ||
| 98 | |||
| 99 | struct platform_device w90p910_serial_device = { | ||
| 100 | .name = "serial8250", | ||
| 101 | .id = PLAT8250_DEV_PLATFORM, | ||
| 102 | .dev = { | ||
| 103 | .platform_data = w90p910_uart_data, | ||
| 104 | }, | ||
| 105 | }; | ||
| 106 | |||
| 107 | /*Init W90P910 evb io*/ | ||
| 108 | |||
| 109 | void __init w90p910_map_io(struct map_desc *mach_desc, int mach_size) | ||
| 110 | { | ||
| 111 | unsigned long idcode = 0x0; | ||
| 112 | |||
| 113 | iotable_init(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); | ||
| 114 | |||
| 115 | idcode = __raw_readl(W90X900PDID); | ||
| 116 | if (idcode != W90P910_CPUID) | ||
| 117 | printk(KERN_ERR "CPU type 0x%08lx is not W90P910\n", idcode); | ||
| 118 | } | ||
| 119 | |||
| 120 | /*Init W90P910 clock*/ | ||
| 121 | |||
| 122 | void __init w90p910_init_clocks(void) | ||
| 123 | { | ||
| 124 | clks_register(w90p910_clkregs, ARRAY_SIZE(w90p910_clkregs)); | ||
| 125 | } | ||
| 126 | |||
| 127 | static int __init w90p910_init_cpu(void) | ||
| 128 | { | ||
| 129 | return 0; | ||
| 130 | } | ||
| 131 | |||
| 132 | static int __init w90x900_arch_init(void) | ||
| 133 | { | ||
| 134 | return w90p910_init_cpu(); | ||
| 135 | } | ||
| 136 | arch_initcall(w90x900_arch_init); | ||
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 556c8daf087d..cc8829d7e116 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/uaccess.h> | 17 | #include <linux/uaccess.h> |
| 18 | #include <linux/page-flags.h> | 18 | #include <linux/page-flags.h> |
| 19 | #include <linux/sched.h> | 19 | #include <linux/sched.h> |
| 20 | #include <linux/highmem.h> | ||
| 20 | 21 | ||
| 21 | #include <asm/system.h> | 22 | #include <asm/system.h> |
| 22 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S index f1559c227784..7d63beaf9745 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S | |||
| @@ -81,12 +81,6 @@ | |||
| 81 | #if L_PTE_SHARED != PTE_EXT_SHARED | 81 | #if L_PTE_SHARED != PTE_EXT_SHARED |
| 82 | #error PTE shared bit mismatch | 82 | #error PTE shared bit mismatch |
| 83 | #endif | 83 | #endif |
| 84 | #if L_PTE_BUFFERABLE != PTE_BUFFERABLE | ||
| 85 | #error PTE bufferable bit mismatch | ||
| 86 | #endif | ||
| 87 | #if L_PTE_CACHEABLE != PTE_CACHEABLE | ||
| 88 | #error PTE cacheable bit mismatch | ||
| 89 | #endif | ||
| 90 | #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\ | 84 | #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\ |
| 91 | L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED | 85 | L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED |
| 92 | #error Invalid Linux PTE bit settings | 86 | #error Invalid Linux PTE bit settings |
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c index d41200382208..6d6b1a468eda 100644 --- a/arch/arm/plat-stmp3xxx/pinmux.c +++ b/arch/arm/plat-stmp3xxx/pinmux.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/sysdev.h> | 22 | #include <linux/sysdev.h> |
| 23 | #include <linux/string.h> | 23 | #include <linux/string.h> |
| 24 | #include <linux/bitops.h> | 24 | #include <linux/bitops.h> |
| 25 | #include <linux/sysdev.h> | ||
| 26 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
| 27 | 26 | ||
| 28 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index 33026eff2aa4..c8c55b469342 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | # | 12 | # |
| 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new | 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new |
| 14 | # | 14 | # |
| 15 | # Last update: Sat Jun 20 22:28:39 2009 | 15 | # Last update: Sat Sep 12 12:00:16 2009 |
| 16 | # | 16 | # |
| 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number | 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number |
| 18 | # | 18 | # |
| @@ -1769,7 +1769,7 @@ mx31cicada MACH_MX31CICADA MX31CICADA 1777 | |||
| 1769 | mi424wr MACH_MI424WR MI424WR 1778 | 1769 | mi424wr MACH_MI424WR MI424WR 1778 |
| 1770 | axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 | 1770 | axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779 |
| 1771 | at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 | 1771 | at572d940deb MACH_AT572D940DEB AT572D940DEB 1780 |
| 1772 | davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781 | 1772 | davinci_da830_evm MACH_DAVINCI_DA830_EVM DAVINCI_DA830_EVM 1781 |
| 1773 | ep9302 MACH_EP9302 EP9302 1782 | 1773 | ep9302 MACH_EP9302 EP9302 1782 |
| 1774 | at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 | 1774 | at572d940hfek MACH_AT572D940HFEB AT572D940HFEB 1783 |
| 1775 | cybook3 MACH_CYBOOK3 CYBOOK3 1784 | 1775 | cybook3 MACH_CYBOOK3 CYBOOK3 1784 |
| @@ -1962,7 +1962,7 @@ ethernut5 MACH_ETHERNUT5 ETHERNUT5 1971 | |||
| 1962 | arm11 MACH_ARM11 ARM11 1972 | 1962 | arm11 MACH_ARM11 ARM11 1972 |
| 1963 | cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 | 1963 | cpuat9260 MACH_CPUAT9260 CPUAT9260 1973 |
| 1964 | cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 | 1964 | cpupxa255 MACH_CPUPXA255 CPUPXA255 1974 |
| 1965 | cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 | 1965 | eukrea_cpuimx27 MACH_CPUIMX27 CPUIMX27 1975 |
| 1966 | cheflux MACH_CHEFLUX CHEFLUX 1976 | 1966 | cheflux MACH_CHEFLUX CHEFLUX 1976 |
| 1967 | eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 | 1967 | eb_cpux9k2 MACH_EB_CPUX9K2 EB_CPUX9K2 1977 |
| 1968 | opcotec MACH_OPCOTEC OPCOTEC 1978 | 1968 | opcotec MACH_OPCOTEC OPCOTEC 1978 |
| @@ -2249,14 +2249,14 @@ omap3_phrazer MACH_OMAP3_PHRAZER OMAP3_PHRAZER 2261 | |||
| 2249 | darwin MACH_DARWIN DARWIN 2262 | 2249 | darwin MACH_DARWIN DARWIN 2262 |
| 2250 | oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 | 2250 | oratiscomu MACH_ORATISCOMU ORATISCOMU 2263 |
| 2251 | rtsbc20 MACH_RTSBC20 RTSBC20 2264 | 2251 | rtsbc20 MACH_RTSBC20 RTSBC20 2264 |
| 2252 | i780 MACH_I780 I780 2265 | 2252 | sgh_i780 MACH_I780 I780 2265 |
| 2253 | gemini324 MACH_GEMINI324 GEMINI324 2266 | 2253 | gemini324 MACH_GEMINI324 GEMINI324 2266 |
| 2254 | oratislan MACH_ORATISLAN ORATISLAN 2267 | 2254 | oratislan MACH_ORATISLAN ORATISLAN 2267 |
| 2255 | oratisalog MACH_ORATISALOG ORATISALOG 2268 | 2255 | oratisalog MACH_ORATISALOG ORATISALOG 2268 |
| 2256 | oratismadi MACH_ORATISMADI ORATISMADI 2269 | 2256 | oratismadi MACH_ORATISMADI ORATISMADI 2269 |
| 2257 | oratisot16 MACH_ORATISOT16 ORATISOT16 2270 | 2257 | oratisot16 MACH_ORATISOT16 ORATISOT16 2270 |
| 2258 | oratisdesk MACH_ORATISDESK ORATISDESK 2271 | 2258 | oratisdesk MACH_ORATISDESK ORATISDESK 2271 |
| 2259 | v2p_ca9 MACH_V2P_CA9 V2P_CA9 2272 | 2259 | v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 |
| 2260 | sintexo MACH_SINTEXO SINTEXO 2273 | 2260 | sintexo MACH_SINTEXO SINTEXO 2273 |
| 2261 | cm3389 MACH_CM3389 CM3389 2274 | 2261 | cm3389 MACH_CM3389 CM3389 2274 |
| 2262 | omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 | 2262 | omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 |
| @@ -2280,3 +2280,132 @@ htcrhodium MACH_HTCRHODIUM HTCRHODIUM 2292 | |||
| 2280 | htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 | 2280 | htctopaz MACH_HTCTOPAZ HTCTOPAZ 2293 |
| 2281 | matrix504 MACH_MATRIX504 MATRIX504 2294 | 2281 | matrix504 MACH_MATRIX504 MATRIX504 2294 |
| 2282 | mrfsa MACH_MRFSA MRFSA 2295 | 2282 | mrfsa MACH_MRFSA MRFSA 2295 |
| 2283 | sc_p270 MACH_SC_P270 SC_P270 2296 | ||
| 2284 | atlas5_evb MACH_ATLAS5_EVB ATLAS5_EVB 2297 | ||
| 2285 | pelco_lobox MACH_PELCO_LOBOX PELCO_LOBOX 2298 | ||
| 2286 | dilax_pcu200 MACH_DILAX_PCU200 DILAX_PCU200 2299 | ||
| 2287 | leonardo MACH_LEONARDO LEONARDO 2300 | ||
| 2288 | zoran_approach7 MACH_ZORAN_APPROACH7 ZORAN_APPROACH7 2301 | ||
| 2289 | dp6xx MACH_DP6XX DP6XX 2302 | ||
| 2290 | bcm2153_vesper MACH_BCM2153_VESPER BCM2153_VESPER 2303 | ||
| 2291 | mahimahi MACH_MAHIMAHI MAHIMAHI 2304 | ||
| 2292 | clickc MACH_CLICKC CLICKC 2305 | ||
| 2293 | zb_gateway MACH_ZB_GATEWAY ZB_GATEWAY 2306 | ||
| 2294 | tazcard MACH_TAZCARD TAZCARD 2307 | ||
| 2295 | tazdev MACH_TAZDEV TAZDEV 2308 | ||
| 2296 | annax_cb_arm MACH_ANNAX_CB_ARM ANNAX_CB_ARM 2309 | ||
| 2297 | annax_dm3 MACH_ANNAX_DM3 ANNAX_DM3 2310 | ||
| 2298 | cerebric MACH_CEREBRIC CEREBRIC 2311 | ||
| 2299 | orca MACH_ORCA ORCA 2312 | ||
| 2300 | pc9260 MACH_PC9260 PC9260 2313 | ||
| 2301 | ems285a MACH_EMS285A EMS285A 2314 | ||
| 2302 | gec2410 MACH_GEC2410 GEC2410 2315 | ||
| 2303 | gec2440 MACH_GEC2440 GEC2440 2316 | ||
| 2304 | mw903 MACH_ARCH_MW903 ARCH_MW903 2317 | ||
| 2305 | mw2440 MACH_MW2440 MW2440 2318 | ||
| 2306 | ecac2378 MACH_ECAC2378 ECAC2378 2319 | ||
| 2307 | tazkiosk MACH_TAZKIOSK TAZKIOSK 2320 | ||
| 2308 | whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321 | ||
| 2309 | sbox9263 MACH_SBOX9263 SBOX9263 2322 | ||
| 2310 | oreo MACH_OREO OREO 2323 | ||
| 2311 | smdk6442 MACH_SMDK6442 SMDK6442 2324 | ||
| 2312 | openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 | ||
| 2313 | incredible MACH_INCREDIBLE INCREDIBLE 2326 | ||
| 2314 | incrediblec MACH_INCREDIBLEC INCREDIBLEC 2327 | ||
| 2315 | heroct MACH_HEROCT HEROCT 2328 | ||
| 2316 | mmnet1000 MACH_MMNET1000 MMNET1000 2329 | ||
| 2317 | devkit8000 MACH_DEVKIT8000 DEVKIT8000 2330 | ||
| 2318 | devkit9000 MACH_DEVKIT9000 DEVKIT9000 2331 | ||
| 2319 | mx31txtr MACH_MX31TXTR MX31TXTR 2332 | ||
| 2320 | u380 MACH_U380 U380 2333 | ||
| 2321 | oamp3_hualu MACH_HUALU_BOARD HUALU_BOARD 2334 | ||
| 2322 | npcmx50 MACH_NPCMX50 NPCMX50 2335 | ||
| 2323 | mx51_lange51 MACH_MX51_LANGE51 MX51_LANGE51 2336 | ||
| 2324 | mx51_lange52 MACH_MX51_LANGE52 MX51_LANGE52 2337 | ||
| 2325 | riom MACH_RIOM RIOM 2338 | ||
| 2326 | comcas MACH_COMCAS COMCAS 2339 | ||
| 2327 | wsi_mx27 MACH_WSI_MX27 WSI_MX27 2340 | ||
| 2328 | cm_t35 MACH_CM_T35 CM_T35 2341 | ||
| 2329 | net2big MACH_NET2BIG NET2BIG 2342 | ||
| 2330 | motorola_a1600 MACH_MOTOROLA_A1600 MOTOROLA_A1600 2343 | ||
| 2331 | igep0020 MACH_IGEP0020 IGEP0020 2344 | ||
| 2332 | igep0010 MACH_IGEP0010 IGEP0010 2345 | ||
| 2333 | mv6281gtwge2 MACH_MV6281GTWGE2 MV6281GTWGE2 2346 | ||
| 2334 | scat100 MACH_SCAT100 SCAT100 2347 | ||
| 2335 | sanmina MACH_SANMINA SANMINA 2348 | ||
| 2336 | momento MACH_MOMENTO MOMENTO 2349 | ||
| 2337 | nuc9xx MACH_NUC9XX NUC9XX 2350 | ||
| 2338 | nuc910evb MACH_NUC910EVB NUC910EVB 2351 | ||
| 2339 | nuc920evb MACH_NUC920EVB NUC920EVB 2352 | ||
| 2340 | nuc950evb MACH_NUC950EVB NUC950EVB 2353 | ||
| 2341 | nuc945evb MACH_NUC945EVB NUC945EVB 2354 | ||
| 2342 | nuc960evb MACH_NUC960EVB NUC960EVB 2355 | ||
| 2343 | nuc932evb MACH_NUC932EVB NUC932EVB 2356 | ||
| 2344 | nuc900 MACH_NUC900 NUC900 2357 | ||
| 2345 | sd1soc MACH_SD1SOC SD1SOC 2358 | ||
| 2346 | ln2440bc MACH_LN2440BC LN2440BC 2359 | ||
| 2347 | rsbc MACH_RSBC RSBC 2360 | ||
| 2348 | openrd_client MACH_OPENRD_CLIENT OPENRD_CLIENT 2361 | ||
| 2349 | hpipaq11x MACH_HPIPAQ11X HPIPAQ11X 2362 | ||
| 2350 | wayland MACH_WAYLAND WAYLAND 2363 | ||
| 2351 | acnbsx102 MACH_ACNBSX102 ACNBSX102 2364 | ||
| 2352 | hwat91 MACH_HWAT91 HWAT91 2365 | ||
| 2353 | at91sam9263cs MACH_AT91SAM9263CS AT91SAM9263CS 2366 | ||
| 2354 | csb732 MACH_CSB732 CSB732 2367 | ||
| 2355 | u8500 MACH_U8500 U8500 2368 | ||
| 2356 | huqiu MACH_HUQIU HUQIU 2369 | ||
| 2357 | mx51_kunlun MACH_MX51_KUNLUN MX51_KUNLUN 2370 | ||
| 2358 | pmt1g MACH_PMT1G PMT1G 2371 | ||
| 2359 | htcelf MACH_HTCELF HTCELF 2372 | ||
| 2360 | armadillo420 MACH_ARMADILLO420 ARMADILLO420 2373 | ||
| 2361 | armadillo440 MACH_ARMADILLO440 ARMADILLO440 2374 | ||
| 2362 | u_chip_dual_arm MACH_U_CHIP_DUAL_ARM U_CHIP_DUAL_ARM 2375 | ||
| 2363 | csr_bdb3 MACH_CSR_BDB3 CSR_BDB3 2376 | ||
| 2364 | dolby_cat1018 MACH_DOLBY_CAT1018 DOLBY_CAT1018 2377 | ||
| 2365 | hy9307 MACH_HY9307 HY9307 2378 | ||
| 2366 | aspire_easystore MACH_A_ES A_ES 2379 | ||
| 2367 | davinci_irif MACH_DAVINCI_IRIF DAVINCI_IRIF 2380 | ||
| 2368 | agama9263 MACH_AGAMA9263 AGAMA9263 2381 | ||
| 2369 | marvell_jasper MACH_MARVELL_JASPER MARVELL_JASPER 2382 | ||
| 2370 | flint MACH_FLINT FLINT 2383 | ||
| 2371 | tavorevb3 MACH_TAVOREVB3 TAVOREVB3 2384 | ||
| 2372 | sch_m490 MACH_SCH_M490 SCH_M490 2386 | ||
| 2373 | rbl01 MACH_RBL01 RBL01 2387 | ||
| 2374 | omnifi MACH_OMNIFI OMNIFI 2388 | ||
| 2375 | otavalo MACH_OTAVALO OTAVALO 2389 | ||
| 2376 | sienna MACH_SIENNA SIENNA 2390 | ||
| 2377 | htc_excalibur_s620 MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620 2391 | ||
| 2378 | htc_opal MACH_HTC_OPAL HTC_OPAL 2392 | ||
| 2379 | touchbook MACH_TOUCHBOOK TOUCHBOOK 2393 | ||
| 2380 | latte MACH_LATTE LATTE 2394 | ||
| 2381 | xa200 MACH_XA200 XA200 2395 | ||
| 2382 | nimrod MACH_NIMROD NIMROD 2396 | ||
| 2383 | cc9p9215_3g MACH_CC9P9215_3G CC9P9215_3G 2397 | ||
| 2384 | cc9p9215_3gjs MACH_CC9P9215_3GJS CC9P9215_3GJS 2398 | ||
| 2385 | tk71 MACH_TK71 TK71 2399 | ||
| 2386 | comham3525 MACH_COMHAM3525 COMHAM3525 2400 | ||
| 2387 | mx31erebus MACH_MX31EREBUS MX31EREBUS 2401 | ||
| 2388 | mcardmx27 MACH_MCARDMX27 MCARDMX27 2402 | ||
| 2389 | paradise MACH_PARADISE PARADISE 2403 | ||
| 2390 | tide MACH_TIDE TIDE 2404 | ||
| 2391 | wzl2440 MACH_WZL2440 WZL2440 2405 | ||
| 2392 | sdrdemo MACH_SDRDEMO SDRDEMO 2406 | ||
| 2393 | ethercan2 MACH_ETHERCAN2 ETHERCAN2 2407 | ||
| 2394 | ecmimg20 MACH_ECMIMG20 ECMIMG20 2408 | ||
| 2395 | omap_dragon MACH_OMAP_DRAGON OMAP_DRAGON 2409 | ||
| 2396 | halo MACH_HALO HALO 2410 | ||
| 2397 | huangshan MACH_HUANGSHAN HUANGSHAN 2411 | ||
| 2398 | vl_ma2sc MACH_VL_MA2SC VL_MA2SC 2412 | ||
| 2399 | raumfeld_rc MACH_RAUMFELD_RC RAUMFELD_RC 2413 | ||
| 2400 | raumfeld_connector MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR 2414 | ||
| 2401 | raumfeld_speaker MACH_RAUMFELD_SPEAKER RAUMFELD_SPEAKER 2415 | ||
| 2402 | multibus_master MACH_MULTIBUS_MASTER MULTIBUS_MASTER 2416 | ||
| 2403 | multibus_pbk MACH_MULTIBUS_PBK MULTIBUS_PBK 2417 | ||
| 2404 | tnetv107x MACH_TNETV107X TNETV107X 2418 | ||
| 2405 | snake MACH_SNAKE SNAKE 2419 | ||
| 2406 | cwmx27 MACH_CWMX27 CWMX27 2420 | ||
| 2407 | sch_m480 MACH_SCH_M480 SCH_M480 2421 | ||
| 2408 | platypus MACH_PLATYPUS PLATYPUS 2422 | ||
| 2409 | pss2 MACH_PSS2 PSS2 2423 | ||
| 2410 | davinci_apm150 MACH_DAVINCI_APM150 DAVINCI_APM150 2424 | ||
| 2411 | str9100 MACH_STR9100 STR9100 2425 | ||