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-rw-r--r--arch/mips/Kconfig99
-rw-r--r--arch/mips/Makefile48
-rw-r--r--arch/mips/au1000/common/dbdma.c6
-rw-r--r--arch/mips/au1000/common/dbg_io.c2
-rw-r--r--arch/mips/au1000/common/irq.c15
-rw-r--r--arch/mips/au1000/common/power.c2
-rw-r--r--arch/mips/au1000/common/reset.c2
-rw-r--r--arch/mips/au1000/common/setup.c2
-rw-r--r--arch/mips/au1000/common/time.c46
-rw-r--r--arch/mips/au1000/db1x00/board_setup.c2
-rw-r--r--arch/mips/au1000/db1x00/init.c8
-rw-r--r--arch/mips/au1000/mtx-1/board_setup.c2
-rw-r--r--arch/mips/au1000/mtx-1/init.c1
-rw-r--r--arch/mips/au1000/pb1000/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1000/init.c1
-rw-r--r--arch/mips/au1000/pb1100/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1100/init.c1
-rw-r--r--arch/mips/au1000/pb1200/board_setup.c8
-rw-r--r--arch/mips/au1000/pb1200/init.c1
-rw-r--r--arch/mips/au1000/pb1200/irqmap.c2
-rw-r--r--arch/mips/au1000/pb1500/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1500/init.c1
-rw-r--r--arch/mips/au1000/pb1550/board_setup.c2
-rw-r--r--arch/mips/au1000/pb1550/init.c1
-rw-r--r--arch/mips/au1000/xxs1500/board_setup.c2
-rw-r--r--arch/mips/au1000/xxs1500/init.c1
-rw-r--r--arch/mips/basler/excite/excite_prom.c1
-rw-r--r--arch/mips/basler/excite/excite_setup.c17
-rw-r--r--arch/mips/bcm47xx/Makefile6
-rw-r--r--arch/mips/bcm47xx/gpio.c79
-rw-r--r--arch/mips/bcm47xx/irq.c55
-rw-r--r--arch/mips/bcm47xx/prom.c158
-rw-r--r--arch/mips/bcm47xx/serial.c52
-rw-r--r--arch/mips/bcm47xx/setup.c123
-rw-r--r--arch/mips/bcm47xx/time.c55
-rw-r--r--arch/mips/bcm47xx/wgt634u.c64
-rw-r--r--arch/mips/boot/addinitrd.c60
-rw-r--r--arch/mips/boot/elf2ecoff.c2
-rw-r--r--arch/mips/cobalt/Makefile2
-rw-r--r--arch/mips/cobalt/console.c9
-rw-r--r--arch/mips/cobalt/irq.c116
-rw-r--r--arch/mips/cobalt/led.c62
-rw-r--r--arch/mips/cobalt/reset.c39
-rw-r--r--arch/mips/cobalt/rtc.c5
-rw-r--r--arch/mips/cobalt/serial.c7
-rw-r--r--arch/mips/cobalt/setup.c20
-rw-r--r--arch/mips/configs/bigsur_defconfig1
-rw-r--r--arch/mips/configs/cobalt_defconfig23
-rw-r--r--arch/mips/configs/lasat_defconfig828
-rw-r--r--arch/mips/configs/mtx1_defconfig3115
-rw-r--r--arch/mips/configs/sb1250-swarm_defconfig1
-rw-r--r--arch/mips/dec/ecc-berr.c2
-rw-r--r--arch/mips/dec/kn02xa-berr.c2
-rw-r--r--arch/mips/dec/prom/identify.c3
-rw-r--r--arch/mips/dec/prom/init.c8
-rw-r--r--arch/mips/dec/setup.c4
-rw-r--r--arch/mips/dec/time.c13
-rw-r--r--arch/mips/emma2rh/common/prom.c2
-rw-r--r--arch/mips/emma2rh/markeins/setup.c4
-rw-r--r--arch/mips/fw/arc/Makefile (renamed from arch/mips/arc/Makefile)0
-rw-r--r--arch/mips/fw/arc/arc_con.c (renamed from arch/mips/arc/arc_con.c)0
-rw-r--r--arch/mips/fw/arc/cmdline.c (renamed from arch/mips/arc/cmdline.c)0
-rw-r--r--arch/mips/fw/arc/env.c (renamed from arch/mips/arc/env.c)2
-rw-r--r--arch/mips/fw/arc/file.c (renamed from arch/mips/arc/file.c)2
-rw-r--r--arch/mips/fw/arc/identify.c (renamed from arch/mips/arc/identify.c)82
-rw-r--r--arch/mips/fw/arc/init.c (renamed from arch/mips/arc/init.c)0
-rw-r--r--arch/mips/fw/arc/memory.c (renamed from arch/mips/arc/memory.c)6
-rw-r--r--arch/mips/fw/arc/misc.c (renamed from arch/mips/arc/misc.c)2
-rw-r--r--arch/mips/fw/arc/promlib.c (renamed from arch/mips/arc/promlib.c)0
-rw-r--r--arch/mips/fw/arc/salone.c (renamed from arch/mips/arc/salone.c)0
-rw-r--r--arch/mips/fw/arc/time.c (renamed from arch/mips/arc/time.c)2
-rw-r--r--arch/mips/fw/arc/tree.c (renamed from arch/mips/arc/tree.c)2
-rw-r--r--arch/mips/fw/cfe/Makefile5
-rw-r--r--arch/mips/fw/cfe/cfe_api.c (renamed from arch/mips/sibyte/cfe/cfe_api.c)2
-rw-r--r--arch/mips/fw/cfe/cfe_api_int.h (renamed from arch/mips/sibyte/cfe/cfe_api_int.h)0
-rw-r--r--arch/mips/gt64120/wrppmc/Makefile2
-rw-r--r--arch/mips/gt64120/wrppmc/irq.c23
-rw-r--r--arch/mips/gt64120/wrppmc/pci.c3
-rw-r--r--arch/mips/gt64120/wrppmc/reset.c10
-rw-r--r--arch/mips/gt64120/wrppmc/serial.c80
-rw-r--r--arch/mips/gt64120/wrppmc/setup.c39
-rw-r--r--arch/mips/gt64120/wrppmc/time.c13
-rw-r--r--arch/mips/jazz/Makefile2
-rw-r--r--arch/mips/jazz/irq.c142
-rw-r--r--arch/mips/jazz/jazz-platform.c60
-rw-r--r--arch/mips/jazz/jazzdma.c47
-rw-r--r--arch/mips/jazz/reset.c4
-rw-r--r--arch/mips/jazz/setup.c134
-rw-r--r--arch/mips/jmr3927/rbhma3100/init.c1
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c8
-rw-r--r--arch/mips/jmr3927/rbhma3100/setup.c4
-rw-r--r--arch/mips/kernel/Makefile2
-rw-r--r--arch/mips/kernel/binfmt_elfo32.c2
-rw-r--r--arch/mips/kernel/cpu-bugs64.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c129
-rw-r--r--arch/mips/kernel/gdb-stub.c26
-rw-r--r--arch/mips/kernel/i8253.c213
-rw-r--r--arch/mips/kernel/i8259.c37
-rw-r--r--arch/mips/kernel/irixelf.c40
-rw-r--r--arch/mips/kernel/irixinv.c42
-rw-r--r--arch/mips/kernel/irixioctl.c2
-rw-r--r--arch/mips/kernel/irixsig.c8
-rw-r--r--arch/mips/kernel/irq-gt641xx.c131
-rw-r--r--arch/mips/kernel/irq-msc01.c4
-rw-r--r--arch/mips/kernel/irq.c4
-rw-r--r--arch/mips/kernel/kspd.c12
-rw-r--r--arch/mips/kernel/linux32.c24
-rw-r--r--arch/mips/kernel/mips-mt.c2
-rw-r--r--arch/mips/kernel/proc.c73
-rw-r--r--arch/mips/kernel/process.c11
-rw-r--r--arch/mips/kernel/ptrace.c50
-rw-r--r--arch/mips/kernel/ptrace32.c16
-rw-r--r--arch/mips/kernel/setup.c2
-rw-r--r--arch/mips/kernel/signal.c4
-rw-r--r--arch/mips/kernel/signal32.c44
-rw-r--r--arch/mips/kernel/signal_n32.c4
-rw-r--r--arch/mips/kernel/smp-mt.c2
-rw-r--r--arch/mips/kernel/smp.c123
-rw-r--r--arch/mips/kernel/smtc.c146
-rw-r--r--arch/mips/kernel/syscall.c60
-rw-r--r--arch/mips/kernel/sysirix.c22
-rw-r--r--arch/mips/kernel/time.c416
-rw-r--r--arch/mips/kernel/traps.c45
-rw-r--r--arch/mips/kernel/unaligned.c2
-rw-r--r--arch/mips/kernel/vmlinux.lds.S339
-rw-r--r--arch/mips/kernel/vpe.c47
-rw-r--r--arch/mips/lasat/Kconfig15
-rw-r--r--arch/mips/lasat/Makefile16
-rw-r--r--arch/mips/lasat/at93c.c149
-rw-r--r--arch/mips/lasat/at93c.h18
-rw-r--r--arch/mips/lasat/ds1603.c183
-rw-r--r--arch/mips/lasat/ds1603.h31
-rw-r--r--arch/mips/lasat/image/Makefile54
-rw-r--r--arch/mips/lasat/image/head.S31
-rw-r--r--arch/mips/lasat/image/romscript.normal23
-rw-r--r--arch/mips/lasat/interrupt.c130
-rw-r--r--arch/mips/lasat/lasat_board.c280
-rw-r--r--arch/mips/lasat/lasat_models.h67
-rw-r--r--arch/mips/lasat/picvue.c244
-rw-r--r--arch/mips/lasat/picvue.h48
-rw-r--r--arch/mips/lasat/picvue_proc.c191
-rw-r--r--arch/mips/lasat/prom.c126
-rw-r--r--arch/mips/lasat/prom.h7
-rw-r--r--arch/mips/lasat/reset.c61
-rw-r--r--arch/mips/lasat/serial.c94
-rw-r--r--arch/mips/lasat/setup.c154
-rw-r--r--arch/mips/lasat/sysctl.c456
-rw-r--r--arch/mips/lasat/sysctl.h24
-rw-r--r--arch/mips/lemote/lm2e/Makefile1
-rw-r--r--arch/mips/lemote/lm2e/prom.c1
-rw-r--r--arch/mips/lemote/lm2e/setup.c7
-rw-r--r--arch/mips/lib/ucmpdi2.c2
-rw-r--r--arch/mips/math-emu/cp1emu.c32
-rw-r--r--arch/mips/math-emu/dp_mul.c2
-rw-r--r--arch/mips/math-emu/ieee754.c12
-rw-r--r--arch/mips/math-emu/ieee754dp.h12
-rw-r--r--arch/mips/math-emu/ieee754int.h30
-rw-r--r--arch/mips/math-emu/ieee754sp.h12
-rw-r--r--arch/mips/mips-boards/atlas/atlas_gdb.c2
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c22
-rw-r--r--arch/mips/mips-boards/atlas/atlas_setup.c7
-rw-r--r--arch/mips/mips-boards/generic/init.c12
-rw-r--r--arch/mips/mips-boards/generic/memory.c4
-rw-r--r--arch/mips/mips-boards/generic/pci.c2
-rw-r--r--arch/mips/mips-boards/generic/time.c149
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c36
-rw-r--r--arch/mips/mips-boards/malta/malta_setup.c16
-rw-r--r--arch/mips/mips-boards/malta/malta_smtc.c50
-rw-r--r--arch/mips/mips-boards/sead/sead_int.c2
-rw-r--r--arch/mips/mips-boards/sead/sead_setup.c5
-rw-r--r--arch/mips/mipssim/sim_int.c2
-rw-r--r--arch/mips/mipssim/sim_mem.c4
-rw-r--r--arch/mips/mipssim/sim_setup.c2
-rw-r--r--arch/mips/mipssim/sim_time.c76
-rw-r--r--arch/mips/mm/Makefile2
-rw-r--r--arch/mips/mm/c-r3k.c12
-rw-r--r--arch/mips/mm/c-r4k.c116
-rw-r--r--arch/mips/mm/c-sb1.c535
-rw-r--r--arch/mips/mm/c-tx39.c6
-rw-r--r--arch/mips/mm/cache.c9
-rw-r--r--arch/mips/mm/cerr-sb1.c24
-rw-r--r--arch/mips/mm/dma-default.c4
-rw-r--r--arch/mips/mm/pg-r4k.c22
-rw-r--r--arch/mips/mm/pg-sb1.c12
-rw-r--r--arch/mips/mm/pgtable.c8
-rw-r--r--arch/mips/mm/sc-mips.c2
-rw-r--r--arch/mips/mm/tlb-r4k.c2
-rw-r--r--arch/mips/mm/tlb-r8k.c2
-rw-r--r--arch/mips/mm/tlbex.c210
-rw-r--r--arch/mips/oprofile/common.c2
-rw-r--r--arch/mips/oprofile/op_model_mipsxx.c6
-rw-r--r--arch/mips/oprofile/op_model_rm9000.c2
-rw-r--r--arch/mips/pci/Makefile2
-rw-r--r--arch/mips/pci/fixup-atlas.c6
-rw-r--r--arch/mips/pci/fixup-cobalt.c40
-rw-r--r--arch/mips/pci/ops-au1000.c2
-rw-r--r--arch/mips/pci/ops-nile4.c147
-rw-r--r--arch/mips/pci/ops-sni.c22
-rw-r--r--arch/mips/pci/pci-bcm1480.c6
-rw-r--r--arch/mips/pci/pci-bcm1480ht.c4
-rw-r--r--arch/mips/pci/pci-lasat.c91
-rw-r--r--arch/mips/pci/pci-sb1250.c4
-rw-r--r--arch/mips/pci/pci-vr41xx.c2
-rw-r--r--arch/mips/philips/pnx8550/common/proc.c36
-rw-r--r--arch/mips/philips/pnx8550/common/setup.c3
-rw-r--r--arch/mips/philips/pnx8550/common/time.c7
-rw-r--r--arch/mips/philips/pnx8550/jbs/init.c1
-rw-r--r--arch/mips/philips/pnx8550/stb810/prom_init.c1
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c2
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_serial.c8
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_setup.c18
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_time.c3
-rw-r--r--arch/mips/pmc-sierra/msp71xx/msp_usb.c8
-rw-r--r--arch/mips/pmc-sierra/yosemite/ht.c2
-rw-r--r--arch/mips/pmc-sierra/yosemite/prom.c1
-rw-r--r--arch/mips/pmc-sierra/yosemite/setup.c26
-rw-r--r--arch/mips/qemu/q-firmware.c2
-rw-r--r--arch/mips/qemu/q-irq.c4
-rw-r--r--arch/mips/qemu/q-setup.c10
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c7
-rw-r--r--arch/mips/sgi-ip22/ip22-setup.c2
-rw-r--r--arch/mips/sgi-ip22/ip22-time.c35
-rw-r--r--arch/mips/sgi-ip27/ip27-berr.c2
-rw-r--r--arch/mips/sgi-ip27/ip27-init.c6
-rw-r--r--arch/mips/sgi-ip27/ip27-smp.c4
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c38
-rw-r--r--arch/mips/sgi-ip32/crime.c6
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c44
-rw-r--r--arch/mips/sgi-ip32/ip32-memory.c4
-rw-r--r--arch/mips/sgi-ip32/ip32-setup.c12
-rw-r--r--arch/mips/sibyte/Kconfig13
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c21
-rw-r--r--arch/mips/sibyte/bcm1480/setup.c78
-rw-r--r--arch/mips/sibyte/bcm1480/time.c118
-rw-r--r--arch/mips/sibyte/cfe/Makefile2
-rw-r--r--arch/mips/sibyte/cfe/cfe_api.h185
-rw-r--r--arch/mips/sibyte/cfe/cfe_error.h85
-rw-r--r--arch/mips/sibyte/cfe/console.c6
-rw-r--r--arch/mips/sibyte/cfe/setup.c7
-rw-r--r--arch/mips/sibyte/cfe/smp.c4
-rw-r--r--arch/mips/sibyte/common/Makefile1
-rw-r--r--arch/mips/sibyte/common/sb_tbprof.c4
-rw-r--r--arch/mips/sibyte/sb1250/irq.c58
-rw-r--r--arch/mips/sibyte/sb1250/prom.c3
-rw-r--r--arch/mips/sibyte/sb1250/setup.c74
-rw-r--r--arch/mips/sibyte/sb1250/time.c198
-rw-r--r--arch/mips/sibyte/swarm/dbg_io.c4
-rw-r--r--arch/mips/sibyte/swarm/rtc_m41t81.c3
-rw-r--r--arch/mips/sibyte/swarm/rtc_xicor1241.c3
-rw-r--r--arch/mips/sibyte/swarm/setup.c56
-rw-r--r--arch/mips/sni/a20r.c6
-rw-r--r--arch/mips/sni/pcimt.c5
-rw-r--r--arch/mips/sni/pcit.c27
-rw-r--r--arch/mips/sni/reset.c2
-rw-r--r--arch/mips/sni/rm200.c11
-rw-r--r--arch/mips/sni/setup.c8
-rw-r--r--arch/mips/sni/sniprom.c8
-rw-r--r--arch/mips/sni/time.c27
-rw-r--r--arch/mips/tx4927/common/tx4927_dbgio.c1
-rw-r--r--arch/mips/tx4927/common/tx4927_prom.c12
-rw-r--r--arch/mips/tx4927/common/tx4927_setup.c20
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c33
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c2
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c36
-rw-r--r--arch/mips/tx4938/common/setup.c9
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/prom.c1
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/setup.c7
-rw-r--r--arch/mips/vr41xx/common/bcu.c8
-rw-r--r--arch/mips/vr41xx/common/cmu.c16
-rw-r--r--arch/mips/vr41xx/common/giu.c2
-rw-r--r--arch/mips/vr41xx/common/icu.c76
-rw-r--r--arch/mips/vr41xx/common/init.c8
-rw-r--r--arch/mips/vr41xx/common/pmu.c40
-rw-r--r--arch/mips/vr41xx/common/rtc.c2
-rw-r--r--arch/mips/vr41xx/common/siu.c2
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/init.c6
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c6
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/setup.c1
279 files changed, 10402 insertions, 3365 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3b807b4bc7cd..f943736541cb 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -3,6 +3,7 @@ config MIPS
3 default y 3 default y
4 # Horrible source of confusion. Die, die, die ... 4 # Horrible source of confusion. Die, die, die ...
5 select EMBEDDED 5 select EMBEDDED
6 select RTC_LIB
6 7
7mainmenu "Linux/MIPS Kernel Configuration" 8mainmenu "Linux/MIPS Kernel Configuration"
8 9
@@ -44,12 +45,30 @@ config BASLER_EXCITE_PROTOTYPE
44 note that a kernel built with this option selected will not be 45 note that a kernel built with this option selected will not be
45 able to run on normal units. 46 able to run on normal units.
46 47
48config BCM47XX
49 bool "BCM47XX based boards"
50 select DMA_NONCOHERENT
51 select HW_HAS_PCI
52 select IRQ_CPU
53 select SYS_HAS_CPU_MIPS32_R1
54 select SYS_SUPPORTS_32BIT_KERNEL
55 select SYS_SUPPORTS_LITTLE_ENDIAN
56 select SSB
57 select SSB_DRIVER_MIPS
58 select GENERIC_GPIO
59 select SYS_HAS_EARLY_PRINTK
60 select CFE
61 help
62 Support for BCM47XX based boards
63
47config MIPS_COBALT 64config MIPS_COBALT
48 bool "Cobalt Server" 65 bool "Cobalt Server"
49 select DMA_NONCOHERENT 66 select DMA_NONCOHERENT
50 select HW_HAS_PCI 67 select HW_HAS_PCI
68 select I8253
51 select I8259 69 select I8259
52 select IRQ_CPU 70 select IRQ_CPU
71 select IRQ_GT641XX
53 select PCI_GT64XXX_PCI0 72 select PCI_GT64XXX_PCI0
54 select SYS_HAS_CPU_NEVADA 73 select SYS_HAS_CPU_NEVADA
55 select SYS_HAS_EARLY_PRINTK 74 select SYS_HAS_EARLY_PRINTK
@@ -93,6 +112,8 @@ config MACH_JAZZ
93 select ARC32 112 select ARC32
94 select ARCH_MAY_HAVE_PC_FDC 113 select ARCH_MAY_HAVE_PC_FDC
95 select GENERIC_ISA_DMA 114 select GENERIC_ISA_DMA
115 select IRQ_CPU
116 select I8253
96 select I8259 117 select I8259
97 select ISA 118 select ISA
98 select PCSPEAKER 119 select PCSPEAKER
@@ -107,6 +128,20 @@ config MACH_JAZZ
107 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and 128 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
108 Olivetti M700-10 workstations. 129 Olivetti M700-10 workstations.
109 130
131config LASAT
132 bool "LASAT Networks platforms"
133 select DMA_NONCOHERENT
134 select SYS_HAS_EARLY_PRINTK
135 select HW_HAS_PCI
136 select PCI_GT64XXX_PCI0
137 select MIPS_NILE4
138 select R5000_CPU_SCACHE
139 select SYS_HAS_CPU_R5000
140 select SYS_SUPPORTS_32BIT_KERNEL
141 select SYS_SUPPORTS_64BIT_KERNEL if BROKEN
142 select SYS_SUPPORTS_LITTLE_ENDIAN
143 select GENERIC_HARDIRQS_NO__DO_IRQ
144
110config LEMOTE_FULONG 145config LEMOTE_FULONG
111 bool "Lemote Fulong mini-PC" 146 bool "Lemote Fulong mini-PC"
112 select ARCH_SPARSEMEM_ENABLE 147 select ARCH_SPARSEMEM_ENABLE
@@ -168,6 +203,7 @@ config MIPS_MALTA
168 select GENERIC_ISA_DMA 203 select GENERIC_ISA_DMA
169 select IRQ_CPU 204 select IRQ_CPU
170 select HW_HAS_PCI 205 select HW_HAS_PCI
206 select I8253
171 select I8259 207 select I8259
172 select MIPS_BOARDS_GEN 208 select MIPS_BOARDS_GEN
173 select MIPS_BONITO64 209 select MIPS_BONITO64
@@ -301,7 +337,9 @@ config QEMU
301 select DMA_COHERENT 337 select DMA_COHERENT
302 select GENERIC_ISA_DMA 338 select GENERIC_ISA_DMA
303 select HAVE_STD_PC_SERIAL_PORT 339 select HAVE_STD_PC_SERIAL_PORT
340 select I8253
304 select I8259 341 select I8259
342 select IRQ_CPU
305 select ISA 343 select ISA
306 select PCSPEAKER 344 select PCSPEAKER
307 select SWAP_IO_SPACE 345 select SWAP_IO_SPACE
@@ -328,6 +366,7 @@ config SGI_IP22
328 select BOOT_ELF32 366 select BOOT_ELF32
329 select DMA_NONCOHERENT 367 select DMA_NONCOHERENT
330 select HW_HAS_EISA 368 select HW_HAS_EISA
369 select I8253
331 select IP22_CPU_SCACHE 370 select IP22_CPU_SCACHE
332 select IRQ_CPU 371 select IRQ_CPU
333 select GENERIC_ISA_DMA_SUPPORT_BROKEN 372 select GENERIC_ISA_DMA_SUPPORT_BROKEN
@@ -352,7 +391,6 @@ config SGI_IP27
352 select SYS_HAS_EARLY_PRINTK 391 select SYS_HAS_EARLY_PRINTK
353 select HW_HAS_PCI 392 select HW_HAS_PCI
354 select NR_CPUS_DEFAULT_64 393 select NR_CPUS_DEFAULT_64
355 select PCI_DOMAINS
356 select SYS_HAS_CPU_R10000 394 select SYS_HAS_CPU_R10000
357 select SYS_SUPPORTS_64BIT_KERNEL 395 select SYS_SUPPORTS_64BIT_KERNEL
358 select SYS_SUPPORTS_BIG_ENDIAN 396 select SYS_SUPPORTS_BIG_ENDIAN
@@ -484,7 +522,6 @@ config SIBYTE_BIGSUR
484 select BOOT_ELF32 522 select BOOT_ELF32
485 select DMA_COHERENT 523 select DMA_COHERENT
486 select NR_CPUS_DEFAULT_4 524 select NR_CPUS_DEFAULT_4
487 select PCI_DOMAINS
488 select SIBYTE_BCM1x80 525 select SIBYTE_BCM1x80
489 select SWAP_IO_SPACE 526 select SWAP_IO_SPACE
490 select SYS_HAS_CPU_SB1 527 select SYS_HAS_CPU_SB1
@@ -502,6 +539,7 @@ config SNI_RM
502 select HW_HAS_EISA 539 select HW_HAS_EISA
503 select HW_HAS_PCI 540 select HW_HAS_PCI
504 select IRQ_CPU 541 select IRQ_CPU
542 select I8253
505 select I8259 543 select I8259
506 select ISA 544 select ISA
507 select PCSPEAKER 545 select PCSPEAKER
@@ -599,6 +637,7 @@ endchoice
599 637
600source "arch/mips/au1000/Kconfig" 638source "arch/mips/au1000/Kconfig"
601source "arch/mips/jazz/Kconfig" 639source "arch/mips/jazz/Kconfig"
640source "arch/mips/lasat/Kconfig"
602source "arch/mips/pmc-sierra/Kconfig" 641source "arch/mips/pmc-sierra/Kconfig"
603source "arch/mips/sgi-ip27/Kconfig" 642source "arch/mips/sgi-ip27/Kconfig"
604source "arch/mips/sibyte/Kconfig" 643source "arch/mips/sibyte/Kconfig"
@@ -635,10 +674,18 @@ config GENERIC_CALIBRATE_DELAY
635 bool 674 bool
636 default y 675 default y
637 676
677config GENERIC_CLOCKEVENTS
678 bool
679 default y
680
638config GENERIC_TIME 681config GENERIC_TIME
639 bool 682 bool
640 default y 683 default y
641 684
685config GENERIC_CMOS_UPDATE
686 bool
687 default y
688
642config SCHED_NO_NO_OMIT_FRAME_POINTER 689config SCHED_NO_NO_OMIT_FRAME_POINTER
643 bool 690 bool
644 default y 691 default y
@@ -659,6 +706,9 @@ config ARCH_MAY_HAVE_PC_FDC
659config BOOT_RAW 706config BOOT_RAW
660 bool 707 bool
661 708
709config CFE
710 bool
711
662config DMA_COHERENT 712config DMA_COHERENT
663 bool 713 bool
664 714
@@ -706,6 +756,9 @@ config MIPS_BONITO64
706config MIPS_MSC 756config MIPS_MSC
707 bool 757 bool
708 758
759config MIPS_NILE4
760 bool
761
709config MIPS_DISABLE_OBSOLETE_IDE 762config MIPS_DISABLE_OBSOLETE_IDE
710 bool 763 bool
711 764
@@ -775,6 +828,9 @@ config IRQ_MSP_CIC
775config IRQ_TXX9 828config IRQ_TXX9
776 bool 829 bool
777 830
831config IRQ_GT641XX
832 bool
833
778config MIPS_BOARDS_GEN 834config MIPS_BOARDS_GEN
779 bool 835 bool
780 836
@@ -856,6 +912,8 @@ config BOOT_ELF64
856 912
857menu "CPU selection" 913menu "CPU selection"
858 914
915source "kernel/time/Kconfig"
916
859choice 917choice
860 prompt "CPU type" 918 prompt "CPU type"
861 default CPU_R4X00 919 default CPU_R4X00
@@ -1316,6 +1374,7 @@ config MIPS_MT_SMTC
1316 depends on CPU_MIPS32_R2 1374 depends on CPU_MIPS32_R2
1317 #depends on CPU_MIPS64_R2 # once there is hardware ... 1375 #depends on CPU_MIPS64_R2 # once there is hardware ...
1318 depends on SYS_SUPPORTS_MULTITHREADING 1376 depends on SYS_SUPPORTS_MULTITHREADING
1377 select GENERIC_CLOCKEVENTS_BROADCAST
1319 select CPU_MIPSR2_IRQ_VI 1378 select CPU_MIPSR2_IRQ_VI
1320 select CPU_MIPSR2_IRQ_EI 1379 select CPU_MIPSR2_IRQ_EI
1321 select CPU_MIPSR2_SRS 1380 select CPU_MIPSR2_SRS
@@ -1378,6 +1437,19 @@ config MIPS_MT_SMTC_IM_BACKSTOP
1378 impact on interrupt service overhead. Disable it only if you know 1437 impact on interrupt service overhead. Disable it only if you know
1379 what you are doing. 1438 what you are doing.
1380 1439
1440config MIPS_MT_SMTC_IRQAFF
1441 bool "Support IRQ affinity API"
1442 depends on MIPS_MT_SMTC
1443 default n
1444 help
1445 Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
1446 for SMTC Linux kernel. Requires platform support, of which
1447 an example can be found in the MIPS kernel i8259 and Malta
1448 platform code. It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
1449 be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
1450 interrupt dispatch, and should be used only if you know what
1451 you are doing.
1452
1381config MIPS_VPE_LOADER_TOM 1453config MIPS_VPE_LOADER_TOM
1382 bool "Load VPE program into memory hidden from linux" 1454 bool "Load VPE program into memory hidden from linux"
1383 depends on MIPS_VPE_LOADER 1455 depends on MIPS_VPE_LOADER
@@ -1472,6 +1544,9 @@ config CPU_HAS_SYNC
1472 depends on !CPU_R3000 1544 depends on !CPU_R3000
1473 default y 1545 default y
1474 1546
1547config GENERIC_CLOCKEVENTS_BROADCAST
1548 bool
1549
1475# 1550#
1476# Use the generic interrupt handling code in kernel/irq/: 1551# Use the generic interrupt handling code in kernel/irq/:
1477# 1552#
@@ -1762,6 +1837,7 @@ config HW_HAS_PCI
1762config PCI 1837config PCI
1763 bool "Support for PCI controller" 1838 bool "Support for PCI controller"
1764 depends on HW_HAS_PCI 1839 depends on HW_HAS_PCI
1840 select PCI_DOMAINS
1765 help 1841 help
1766 Find out whether you have a PCI motherboard. PCI is the name of a 1842 Find out whether you have a PCI motherboard. PCI is the name of a
1767 bus system, i.e. the way the CPU talks to the other stuff inside 1843 bus system, i.e. the way the CPU talks to the other stuff inside
@@ -1775,7 +1851,6 @@ config PCI
1775 1851
1776config PCI_DOMAINS 1852config PCI_DOMAINS
1777 bool 1853 bool
1778 depends on PCI
1779 1854
1780source "drivers/pci/Kconfig" 1855source "drivers/pci/Kconfig"
1781 1856
@@ -1824,6 +1899,9 @@ config MMU
1824 bool 1899 bool
1825 default y 1900 default y
1826 1901
1902config I8253
1903 bool
1904
1827config PCSPEAKER 1905config PCSPEAKER
1828 bool 1906 bool
1829 1907
@@ -1840,21 +1918,6 @@ source "fs/Kconfig.binfmt"
1840config TRAD_SIGNALS 1918config TRAD_SIGNALS
1841 bool 1919 bool
1842 1920
1843config BUILD_ELF64
1844 bool "Use 64-bit ELF format for building"
1845 depends on 64BIT
1846 help
1847 A 64-bit kernel is usually built using the 64-bit ELF binary object
1848 format as it's one that allows arbitrary 64-bit constructs. For
1849 kernels that are loaded within the KSEG compatibility segments the
1850 32-bit ELF format can optionally be used resulting in a somewhat
1851 smaller binary, but this option is not explicitly supported by the
1852 toolchain and since binutils 2.14 it does not even work at all.
1853
1854 Say Y to use the 64-bit format or N to use the 32-bit one.
1855
1856 If unsure say Y.
1857
1858config BINFMT_IRIX 1921config BINFMT_IRIX
1859 bool "Include IRIX binary compatibility" 1922 bool "Include IRIX binary compatibility"
1860 depends on CPU_BIG_ENDIAN && 32BIT && BROKEN 1923 depends on CPU_BIG_ENDIAN && 32BIT && BROKEN
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 32c1c8fb6f98..ebd5d02a7d78 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -60,11 +60,6 @@ vmlinux-32 = vmlinux.32
60vmlinux-64 = vmlinux 60vmlinux-64 = vmlinux
61 61
62cflags-y += -mabi=64 62cflags-y += -mabi=64
63ifdef CONFIG_BUILD_ELF64
64cflags-y += $(call cc-option,-mno-explicit-relocs)
65else
66cflags-y += $(call cc-option,-msym32)
67endif
68endif 63endif
69 64
70all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32) 65all-$(CONFIG_BOOT_ELF32) := $(vmlinux-32)
@@ -153,7 +148,8 @@ endif
153# 148#
154# Firmware support 149# Firmware support
155# 150#
156libs-$(CONFIG_ARC) += arch/mips/arc/ 151libs-$(CONFIG_ARC) += arch/mips/fw/arc/
152libs-$(CONFIG_CFE) += arch/mips/fw/cfe/
157libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ 153libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/
158 154
159# 155#
@@ -367,6 +363,13 @@ cflags-$(CONFIG_BASLER_EXCITE) += -Iinclude/asm-mips/mach-excite
367load-$(CONFIG_BASLER_EXCITE) += 0x80100000 363load-$(CONFIG_BASLER_EXCITE) += 0x80100000
368 364
369# 365#
366# LASAT platforms
367#
368core-$(CONFIG_LASAT) += arch/mips/lasat/
369cflags-$(CONFIG_LASAT) += -Iinclude/asm-mips/mach-lasat
370load-$(CONFIG_LASAT) += 0xffffffff80000000
371
372#
370# Common VR41xx 373# Common VR41xx
371# 374#
372core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/ 375core-$(CONFIG_MACH_VR41XX) += arch/mips/vr41xx/common/
@@ -533,6 +536,13 @@ libs-$(CONFIG_SIBYTE_BIGSUR) += arch/mips/sibyte/swarm/
533load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000 536load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
534 537
535# 538#
539# Broadcom BCM47XX boards
540#
541core-$(CONFIG_BCM47XX) += arch/mips/bcm47xx/
542cflags-$(CONFIG_BCM47XX) += -Iinclude/asm-mips/mach-bcm47xx
543load-$(CONFIG_BCM47XX) := 0xffffffff80001000
544
545#
536# SNI RM 546# SNI RM
537# 547#
538core-$(CONFIG_SNI_RM) += arch/mips/sni/ 548core-$(CONFIG_SNI_RM) += arch/mips/sni/
@@ -578,6 +588,26 @@ else
578JIFFIES = jiffies_64 588JIFFIES = jiffies_64
579endif 589endif
580 590
591#
592# Automatically detect the build format. By default we choose
593# the elf format according to the load address.
594# We can always force a build with a 64-bits symbol format by
595# passing 'KBUILD_SYM32=no' option to the make's command line.
596#
597ifdef CONFIG_64BIT
598 ifndef KBUILD_SYM32
599 ifeq ($(shell expr $(load-y) \< 0xffffffff80000000), 0)
600 KBUILD_SYM32 = y
601 endif
602 endif
603
604 ifeq ($(KBUILD_SYM32), y)
605 ifeq ($(call cc-option-yn,-msym32), y)
606 cflags-y += -msym32 -DKBUILD_64BIT_SYM32
607 endif
608 endif
609endif
610
581AFLAGS += $(cflags-y) 611AFLAGS += $(cflags-y)
582CFLAGS += $(cflags-y) \ 612CFLAGS += $(cflags-y) \
583 -D"VMLINUX_LOAD_ADDRESS=$(load-y)" 613 -D"VMLINUX_LOAD_ADDRESS=$(load-y)"
@@ -615,6 +645,11 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
615 645
616drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 646drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
617 647
648ifdef CONFIG_LASAT
649rom.bin rom.sw: vmlinux
650 $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
651endif
652
618# 653#
619# Some machines like the Indy need 32-bit ELF binaries for booting purposes. 654# Some machines like the Indy need 32-bit ELF binaries for booting purposes.
620# Other need ECOFF, so we build a 32-bit ELF binary for them which we then 655# Other need ECOFF, so we build a 32-bit ELF binary for them which we then
@@ -658,6 +693,7 @@ endif
658 693
659archclean: 694archclean:
660 @$(MAKE) $(clean)=arch/mips/boot 695 @$(MAKE) $(clean)=arch/mips/boot
696 @$(MAKE) $(clean)=arch/mips/lasat
661 697
662define archhelp 698define archhelp
663 echo ' vmlinux.ecoff - ECOFF boot image' 699 echo ' vmlinux.ecoff - ECOFF boot image'
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
index 626de44bd888..461cf0139737 100644
--- a/arch/mips/au1000/common/dbdma.c
+++ b/arch/mips/au1000/common/dbdma.c
@@ -184,7 +184,7 @@ static dbdev_tab_t dbdev_tab[] = {
184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 184static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
185 185
186static dbdev_tab_t * 186static dbdev_tab_t *
187find_dbdev_id (u32 id) 187find_dbdev_id(u32 id)
188{ 188{
189 int i; 189 int i;
190 dbdev_tab_t *p; 190 dbdev_tab_t *p;
@@ -213,7 +213,7 @@ au1xxx_ddma_add_device(dbdev_tab_t *dev)
213 if ( NULL != p ) 213 if ( NULL != p )
214 { 214 {
215 memcpy(p, dev, sizeof(dbdev_tab_t)); 215 memcpy(p, dev, sizeof(dbdev_tab_t));
216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id); 216 p->dev_id = DSCR_DEV2CUSTOM_ID(new_id, dev->dev_id);
217 ret = p->dev_id; 217 ret = p->dev_id;
218 new_id++; 218 new_id++;
219#if 0 219#if 0
@@ -671,7 +671,7 @@ _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
671 * parts. If it is fixedin the future, these dma_cache_inv will just 671 * parts. If it is fixedin the future, these dma_cache_inv will just
672 * be nothing more than empty macros. See io.h. 672 * be nothing more than empty macros. See io.h.
673 * */ 673 * */
674 dma_cache_inv((unsigned long)buf,nbytes); 674 dma_cache_inv((unsigned long)buf, nbytes);
675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 675 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
676 au_sync(); 676 au_sync();
677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp)); 677 dma_cache_wback_inv((unsigned long)dp, sizeof(dp));
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
index 0a50af7f34b8..79e0b0a51ace 100644
--- a/arch/mips/au1000/common/dbg_io.c
+++ b/arch/mips/au1000/common/dbg_io.c
@@ -53,7 +53,7 @@ typedef unsigned int uint32;
53 53
54/* memory-mapped read/write of the port */ 54/* memory-mapped read/write of the port */
55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff) 55#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
56#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y)) 56#define UART16550_WRITE(y, z) (au_writel(z&0xff, DEBUG_BASE + y))
57 57
58extern unsigned long get_au1x00_uart_baud_base(void); 58extern unsigned long get_au1x00_uart_baud_base(void);
59extern unsigned long cal_r4koff(void); 59extern unsigned long cal_r4koff(void);
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index ea6e99fbe2f7..a6640b998c6e 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -65,19 +65,6 @@
65#define EXT_INTC1_REQ1 5 /* IP 5 */ 65#define EXT_INTC1_REQ1 5 /* IP 5 */
66#define MIPS_TIMER_IP 7 /* IP 7 */ 66#define MIPS_TIMER_IP 7 /* IP 7 */
67 67
68extern void set_debug_traps(void);
69extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void);
71
72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static void end_irq(unsigned int irq_nr);
74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
76static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
77static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
78inline void local_enable_irq(unsigned int irq_nr);
79inline void local_disable_irq(unsigned int irq_nr);
80
81void (*board_init_irq)(void); 68void (*board_init_irq)(void);
82 69
83static DEFINE_SPINLOCK(irq_lock); 70static DEFINE_SPINLOCK(irq_lock);
@@ -646,7 +633,7 @@ asmlinkage void plat_irq_dispatch(void)
646 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; 633 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
647 634
648 if (pending & CAUSEF_IP7) 635 if (pending & CAUSEF_IP7)
649 mips_timer_interrupt(); 636 do_IRQ(63);
650 else if (pending & CAUSEF_IP2) 637 else if (pending & CAUSEF_IP2)
651 intc0_req0_irqdispatch(); 638 intc0_req0_irqdispatch();
652 else if (pending & CAUSEF_IP3) 639 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
index 3901e8e04755..6f57f72a7d57 100644
--- a/arch/mips/au1000/common/power.c
+++ b/arch/mips/au1000/common/power.c
@@ -211,7 +211,7 @@ int au_sleep(void)
211 unsigned long wakeup, flags; 211 unsigned long wakeup, flags;
212 extern void save_and_sleep(void); 212 extern void save_and_sleep(void);
213 213
214 spin_lock_irqsave(&pm_lock,flags); 214 spin_lock_irqsave(&pm_lock, flags);
215 215
216 save_core_regs(); 216 save_core_regs();
217 217
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
index de5447e83849..b8638d293cf9 100644
--- a/arch/mips/au1000/common/reset.c
+++ b/arch/mips/au1000/common/reset.c
@@ -42,7 +42,7 @@ extern void (*flush_cache_all)(void);
42void au1000_restart(char *command) 42void au1000_restart(char *command)
43{ 43{
44 /* Set all integrated peripherals to disabled states */ 44 /* Set all integrated peripherals to disabled states */
45 extern void board_reset (void); 45 extern void board_reset(void);
46 u32 prid = read_c0_prid(); 46 u32 prid = read_c0_prid();
47 47
48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n"); 48 printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
index a95b37773196..b212c0726125 100644
--- a/arch/mips/au1000/common/setup.c
+++ b/arch/mips/au1000/common/setup.c
@@ -50,7 +50,6 @@ extern void au1000_halt(void);
50extern void au1000_power_off(void); 50extern void au1000_power_off(void);
51extern void au1x_time_init(void); 51extern void au1x_time_init(void);
52extern void au1x_timer_setup(struct irqaction *irq); 52extern void au1x_timer_setup(struct irqaction *irq);
53extern void au1xxx_time_init(void);
54extern void set_cpuspec(void); 53extern void set_cpuspec(void);
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
@@ -112,7 +111,6 @@ void __init plat_mem_setup(void)
112 _machine_restart = au1000_restart; 111 _machine_restart = au1000_restart;
113 _machine_halt = au1000_halt; 112 _machine_halt = au1000_halt;
114 pm_power_off = au1000_power_off; 113 pm_power_off = au1000_power_off;
115 board_time_init = au1xxx_time_init;
116 114
117 /* IO/MEM resources. */ 115 /* IO/MEM resources. */
118 set_io_port_base(0); 116 set_io_port_base(0);
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
index 8fc29982d700..2556399708ba 100644
--- a/arch/mips/au1000/common/time.c
+++ b/arch/mips/au1000/common/time.c
@@ -64,48 +64,8 @@ static unsigned long last_pc0, last_match20;
64 64
65static DEFINE_SPINLOCK(time_lock); 65static DEFINE_SPINLOCK(time_lock);
66 66
67static inline void ack_r4ktimer(unsigned long newval)
68{
69 write_c0_compare(newval);
70}
71
72/*
73 * There are a lot of conceptually broken versions of the MIPS timer interrupt
74 * handler floating around. This one is rather different, but the algorithm
75 * is provably more robust.
76 */
77unsigned long wtimer; 67unsigned long wtimer;
78 68
79void mips_timer_interrupt(void)
80{
81 int irq = 63;
82
83 irq_enter();
84 kstat_this_cpu.irqs[irq]++;
85
86 if (r4k_offset == 0)
87 goto null;
88
89 do {
90 kstat_this_cpu.irqs[irq]++;
91 do_timer(1);
92#ifndef CONFIG_SMP
93 update_process_times(user_mode(get_irq_regs()));
94#endif
95 r4k_cur += r4k_offset;
96 ack_r4ktimer(r4k_cur);
97
98 } while (((unsigned long)read_c0_count()
99 - r4k_cur) < 0x7fffffff);
100
101 irq_exit();
102 return;
103
104null:
105 ack_r4ktimer(0);
106 irq_exit();
107}
108
109#ifdef CONFIG_PM 69#ifdef CONFIG_PM
110irqreturn_t counter0_irq(int irq, void *dev_id) 70irqreturn_t counter0_irq(int irq, void *dev_id)
111{ 71{
@@ -240,7 +200,7 @@ unsigned long cal_r4koff(void)
240 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); 200 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
241 201
242 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 202 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
243 au_writel (0, SYS_TOYWRITE); 203 au_writel(0, SYS_TOYWRITE);
244 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 204 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
245 205
246 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * 206 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
@@ -329,7 +289,3 @@ void __init plat_timer_setup(struct irqaction *irq)
329 289
330#endif 290#endif
331} 291}
332
333void __init au1xxx_time_init(void)
334{
335}
diff --git a/arch/mips/au1000/db1x00/board_setup.c b/arch/mips/au1000/db1x00/board_setup.c
index 8b08edb977be..99eafeada518 100644
--- a/arch/mips/au1000/db1x00/board_setup.c
+++ b/arch/mips/au1000/db1x00/board_setup.c
@@ -46,7 +46,7 @@
46 46
47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 47static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 bcsr->swreset = 0x0000; 52 bcsr->swreset = 0x0000;
diff --git a/arch/mips/au1000/db1x00/init.c b/arch/mips/au1000/db1x00/init.c
index 0a3f025eb023..4d7bcfc8cf73 100644
--- a/arch/mips/au1000/db1x00/init.c
+++ b/arch/mips/au1000/db1x00/init.c
@@ -59,14 +59,12 @@ void __init prom_init(void)
59 prom_argv = (char **) fw_arg1; 59 prom_argv = (char **) fw_arg1;
60 prom_envp = (char **) fw_arg2; 60 prom_envp = (char **) fw_arg2;
61 61
62 mips_machgroup = MACH_GROUP_ALCHEMY;
63
64 /* Set the platform # */ 62 /* Set the platform # */
65#if defined (CONFIG_MIPS_DB1550) 63#if defined(CONFIG_MIPS_DB1550)
66 mips_machtype = MACH_DB1550; 64 mips_machtype = MACH_DB1550;
67#elif defined (CONFIG_MIPS_DB1500) 65#elif defined(CONFIG_MIPS_DB1500)
68 mips_machtype = MACH_DB1500; 66 mips_machtype = MACH_DB1500;
69#elif defined (CONFIG_MIPS_DB1100) 67#elif defined(CONFIG_MIPS_DB1100)
70 mips_machtype = MACH_DB1100; 68 mips_machtype = MACH_DB1100;
71#else 69#else
72 mips_machtype = MACH_DB1000; 70 mips_machtype = MACH_DB1000;
diff --git a/arch/mips/au1000/mtx-1/board_setup.c b/arch/mips/au1000/mtx-1/board_setup.c
index 2c460c116570..abfc4bcddf7a 100644
--- a/arch/mips/au1000/mtx-1/board_setup.c
+++ b/arch/mips/au1000/mtx-1/board_setup.c
@@ -46,7 +46,7 @@
46extern int (*board_pci_idsel)(unsigned int devsel, int assert); 46extern int (*board_pci_idsel)(unsigned int devsel, int assert);
47int mtx1_pci_idsel(unsigned int devsel, int assert); 47int mtx1_pci_idsel(unsigned int devsel, int assert);
48 48
49void board_reset (void) 49void board_reset(void)
50{ 50{
51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 51 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
52 au_writel(0x00000000, 0xAE00001C); 52 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/mtx-1/init.c b/arch/mips/au1000/mtx-1/init.c
index 88f2b6d97281..2aa7b2ed6a8c 100644
--- a/arch/mips/au1000/mtx-1/init.c
+++ b/arch/mips/au1000/mtx-1/init.c
@@ -56,7 +56,6 @@ void __init prom_init(void)
56 prom_argv = (char **) fw_arg1; 56 prom_argv = (char **) fw_arg1;
57 prom_envp = (char **) fw_arg2; 57 prom_envp = (char **) fw_arg2;
58 58
59 mips_machgroup = MACH_GROUP_ALCHEMY;
60 mips_machtype = MACH_MTX1; /* set the platform # */ 59 mips_machtype = MACH_MTX1; /* set the platform # */
61 60
62 prom_init_cmdline(); 61 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1000/board_setup.c b/arch/mips/au1000/pb1000/board_setup.c
index 0aed89114bfc..5198c4f98b43 100644
--- a/arch/mips/au1000/pb1000/board_setup.c
+++ b/arch/mips/au1000/pb1000/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1000.h> 40#include <asm/mach-pb1x00/pb1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44} 44}
45 45
diff --git a/arch/mips/au1000/pb1000/init.c b/arch/mips/au1000/pb1000/init.c
index e9fa1bab81f3..4535f7208e18 100644
--- a/arch/mips/au1000/pb1000/init.c
+++ b/arch/mips/au1000/pb1000/init.c
@@ -54,7 +54,6 @@ void __init prom_init(void)
54 prom_argv = (char **) fw_arg1; 54 prom_argv = (char **) fw_arg1;
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_PB1000; 57 mips_machtype = MACH_PB1000;
59 58
60 prom_init_cmdline(); 59 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c
index 259ca05860c3..42874a6b31d1 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/au1000/pb1100/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1100.h> 40#include <asm/mach-pb1x00/pb1100.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index 6131b56f41b5..7ba6852de7cd 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg3; 56 prom_envp = (char **) fw_arg3;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1100; 58 mips_machtype = MACH_PB1100;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c
index eea2092bde8d..2122515f79d7 100644
--- a/arch/mips/au1000/pb1200/board_setup.c
+++ b/arch/mips/au1000/pb1200/board_setup.c
@@ -57,7 +57,7 @@
57extern void _board_init_irq(void); 57extern void _board_init_irq(void);
58extern void (*board_init_irq)(void); 58extern void (*board_init_irq)(void);
59 59
60void board_reset (void) 60void board_reset(void)
61{ 61{
62 bcsr->resets = 0; 62 bcsr->resets = 0;
63 bcsr->system = 0; 63 bcsr->system = 0;
@@ -148,7 +148,7 @@ void __init board_setup(void)
148} 148}
149 149
150int 150int
151board_au1200fb_panel (void) 151board_au1200fb_panel(void)
152{ 152{
153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 153 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
154 int p; 154 int p;
@@ -160,7 +160,7 @@ board_au1200fb_panel (void)
160} 160}
161 161
162int 162int
163board_au1200fb_panel_init (void) 163board_au1200fb_panel_init(void)
164{ 164{
165 /* Apply power */ 165 /* Apply power */
166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 166 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
@@ -170,7 +170,7 @@ board_au1200fb_panel_init (void)
170} 170}
171 171
172int 172int
173board_au1200fb_panel_shutdown (void) 173board_au1200fb_panel_shutdown(void)
174{ 174{
175 /* Remove power */ 175 /* Remove power */
176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR; 176 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
diff --git a/arch/mips/au1000/pb1200/init.c b/arch/mips/au1000/pb1200/init.c
index 27f09e374e15..5a70029d5388 100644
--- a/arch/mips/au1000/pb1200/init.c
+++ b/arch/mips/au1000/pb1200/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1200; 58 mips_machtype = MACH_PB1200;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c
index b73b2d18bf56..7c708db04a88 100644
--- a/arch/mips/au1000/pb1200/irqmap.c
+++ b/arch/mips/au1000/pb1200/irqmap.c
@@ -132,7 +132,7 @@ static void pb1200_shutdown_irq( unsigned int irq_nr )
132 pb1200_disable_irq(irq_nr); 132 pb1200_disable_irq(irq_nr);
133 if (--pb1200_cascade_en == 0) 133 if (--pb1200_cascade_en == 0)
134 { 134 {
135 free_irq(AU1000_GPIO_7,&pb1200_cascade_handler ); 135 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler );
136 } 136 }
137 return; 137 return;
138} 138}
diff --git a/arch/mips/au1000/pb1500/board_setup.c b/arch/mips/au1000/pb1500/board_setup.c
index a2d850db8902..5446836869d6 100644
--- a/arch/mips/au1000/pb1500/board_setup.c
+++ b/arch/mips/au1000/pb1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/mach-au1x00/au1000.h> 39#include <asm/mach-au1x00/au1000.h>
40#include <asm/mach-pb1x00/pb1500.h> 40#include <asm/mach-pb1x00/pb1500.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/pb1500/init.c b/arch/mips/au1000/pb1500/init.c
index 733d2e469db2..e58a9d6c5021 100644
--- a/arch/mips/au1000/pb1500/init.c
+++ b/arch/mips/au1000/pb1500/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1500; 58 mips_machtype = MACH_PB1500;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/pb1550/board_setup.c b/arch/mips/au1000/pb1550/board_setup.c
index 05fd27dc24e6..e3cfb0d73180 100644
--- a/arch/mips/au1000/pb1550/board_setup.c
+++ b/arch/mips/au1000/pb1550/board_setup.c
@@ -44,7 +44,7 @@
44#include <asm/mach-au1x00/au1000.h> 44#include <asm/mach-au1x00/au1000.h>
45#include <asm/mach-pb1x00/pb1550.h> 45#include <asm/mach-pb1x00/pb1550.h>
46 46
47void board_reset (void) 47void board_reset(void)
48{ 48{
49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 49 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C); 50 au_writew(au_readw(0xAF00001C) & ~(1<<15), 0xAF00001C);
diff --git a/arch/mips/au1000/pb1550/init.c b/arch/mips/au1000/pb1550/init.c
index 41daa3371be3..fad53bf5aad1 100644
--- a/arch/mips/au1000/pb1550/init.c
+++ b/arch/mips/au1000/pb1550/init.c
@@ -55,7 +55,6 @@ void __init prom_init(void)
55 prom_argv = (char **) fw_arg1; 55 prom_argv = (char **) fw_arg1;
56 prom_envp = (char **) fw_arg2; 56 prom_envp = (char **) fw_arg2;
57 57
58 mips_machgroup = MACH_GROUP_ALCHEMY;
59 mips_machtype = MACH_PB1550; 58 mips_machtype = MACH_PB1550;
60 59
61 prom_init_cmdline(); 60 prom_init_cmdline();
diff --git a/arch/mips/au1000/xxs1500/board_setup.c b/arch/mips/au1000/xxs1500/board_setup.c
index ae3d6b19e94d..a9237f41933d 100644
--- a/arch/mips/au1000/xxs1500/board_setup.c
+++ b/arch/mips/au1000/xxs1500/board_setup.c
@@ -39,7 +39,7 @@
39#include <asm/pgtable.h> 39#include <asm/pgtable.h>
40#include <asm/au1000.h> 40#include <asm/au1000.h>
41 41
42void board_reset (void) 42void board_reset(void)
43{ 43{
44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 44 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
45 au_writel(0x00000000, 0xAE00001C); 45 au_writel(0x00000000, 0xAE00001C);
diff --git a/arch/mips/au1000/xxs1500/init.c b/arch/mips/au1000/xxs1500/init.c
index f1c76533b6fc..9f839c36f69e 100644
--- a/arch/mips/au1000/xxs1500/init.c
+++ b/arch/mips/au1000/xxs1500/init.c
@@ -54,7 +54,6 @@ void __init prom_init(void)
54 prom_argv = (char **) fw_arg1; 54 prom_argv = (char **) fw_arg1;
55 prom_envp = (char **) fw_arg2; 55 prom_envp = (char **) fw_arg2;
56 56
57 mips_machgroup = MACH_GROUP_ALCHEMY;
58 mips_machtype = MACH_XXS1500; /* set the platform # */ 57 mips_machtype = MACH_XXS1500; /* set the platform # */
59 58
60 prom_init_cmdline(); 59 prom_init_cmdline();
diff --git a/arch/mips/basler/excite/excite_prom.c b/arch/mips/basler/excite/excite_prom.c
index 6ecd512b999d..2d752c2f6e59 100644
--- a/arch/mips/basler/excite/excite_prom.c
+++ b/arch/mips/basler/excite/excite_prom.c
@@ -136,7 +136,6 @@ void __init prom_init(void)
136# error 64 bit support not implemented 136# error 64 bit support not implemented
137#endif /* CONFIG_64BIT */ 137#endif /* CONFIG_64BIT */
138 138
139 mips_machgroup = MACH_GROUP_TITAN;
140 mips_machtype = MACH_TITAN_EXCITE; 139 mips_machtype = MACH_TITAN_EXCITE;
141} 140}
142 141
diff --git a/arch/mips/basler/excite/excite_setup.c b/arch/mips/basler/excite/excite_setup.c
index 56003188f17c..404ca9284b30 100644
--- a/arch/mips/basler/excite/excite_setup.c
+++ b/arch/mips/basler/excite/excite_setup.c
@@ -68,7 +68,7 @@ DEFINE_SPINLOCK(titan_lock);
68int titan_irqflags; 68int titan_irqflags;
69 69
70 70
71static void excite_timer_init(void) 71void __init plat_time_init(void)
72{ 72{
73 const u32 modebit5 = ocd_readl(0x00e4); 73 const u32 modebit5 = ocd_readl(0x00e4);
74 unsigned int 74 unsigned int
@@ -216,7 +216,7 @@ static int __init excite_platform_init(void)
216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */ 216 titan_writel(0x80021dff, GXCFG); /* XDMA reset */
217 titan_writel(0x00000000, CPXCISRA); 217 titan_writel(0x00000000, CPXCISRA);
218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */ 218 titan_writel(0x00000000, CPXCISRB); /* clear pending interrupts */
219#if defined (CONFIG_HIGHMEM) 219#if defined(CONFIG_HIGHMEM)
220# error change for HIGHMEM support! 220# error change for HIGHMEM support!
221#else 221#else
222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */ 222 titan_writel(0x00000000, GXDMADRPFX); /* buffer address prefix */
@@ -261,16 +261,13 @@ void __init plat_mem_setup(void)
261 /* Announce RAM to system */ 261 /* Announce RAM to system */
262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); 262 add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
263 263
264 /* Set up timer initialization hooks */
265 board_time_init = excite_timer_init;
266
267 /* Set up the peripheral address map */ 264 /* Set up the peripheral address map */
268 *(boot_ocd_base + (LKB9 / sizeof (u32))) = 0; 265 *(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
269 *(boot_ocd_base + (LKB10 / sizeof (u32))) = 0; 266 *(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
270 *(boot_ocd_base + (LKB11 / sizeof (u32))) = 0; 267 *(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
271 *(boot_ocd_base + (LKB12 / sizeof (u32))) = 0; 268 *(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
272 wmb(); 269 wmb();
273 *(boot_ocd_base + (LKB0 / sizeof (u32))) = EXCITE_PHYS_OCD >> 4; 270 *(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
274 wmb(); 271 wmb();
275 272
276 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5); 273 ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
diff --git a/arch/mips/bcm47xx/Makefile b/arch/mips/bcm47xx/Makefile
new file mode 100644
index 000000000000..35294b12d638
--- /dev/null
+++ b/arch/mips/bcm47xx/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for the BCM47XX specific kernel interface routines
3# under Linux.
4#
5
6obj-y := gpio.o irq.o prom.o serial.o setup.o time.o wgt634u.o
diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c
new file mode 100644
index 000000000000..f5a53acf995a
--- /dev/null
+++ b/arch/mips/bcm47xx/gpio.c
@@ -0,0 +1,79 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/ssb/ssb.h>
10#include <linux/ssb/ssb_driver_chipcommon.h>
11#include <linux/ssb/ssb_driver_extif.h>
12#include <asm/mach-bcm47xx/bcm47xx.h>
13#include <asm/mach-bcm47xx/gpio.h>
14
15int bcm47xx_gpio_to_irq(unsigned gpio)
16{
17 if (ssb_bcm47xx.chipco.dev)
18 return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
19 else if (ssb_bcm47xx.extif.dev)
20 return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
21 else
22 return -EINVAL;
23}
24EXPORT_SYMBOL_GPL(bcm47xx_gpio_to_irq);
25
26int bcm47xx_gpio_get_value(unsigned gpio)
27{
28 if (ssb_bcm47xx.chipco.dev)
29 return ssb_chipco_gpio_in(&ssb_bcm47xx.chipco, 1 << gpio);
30 else if (ssb_bcm47xx.extif.dev)
31 return ssb_extif_gpio_in(&ssb_bcm47xx.extif, 1 << gpio);
32 else
33 return 0;
34}
35EXPORT_SYMBOL_GPL(bcm47xx_gpio_get_value);
36
37void bcm47xx_gpio_set_value(unsigned gpio, int value)
38{
39 if (ssb_bcm47xx.chipco.dev)
40 ssb_chipco_gpio_out(&ssb_bcm47xx.chipco,
41 1 << gpio,
42 value ? 1 << gpio : 0);
43 else if (ssb_bcm47xx.extif.dev)
44 ssb_extif_gpio_out(&ssb_bcm47xx.extif,
45 1 << gpio,
46 value ? 1 << gpio : 0);
47}
48EXPORT_SYMBOL_GPL(bcm47xx_gpio_set_value);
49
50int bcm47xx_gpio_direction_input(unsigned gpio)
51{
52 if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
53 ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
54 1 << gpio, 0);
55 else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
56 ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
57 1 << gpio, 0);
58 else
59 return -EINVAL;
60 return 0;
61}
62EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_input);
63
64int bcm47xx_gpio_direction_output(unsigned gpio, int value)
65{
66 bcm47xx_gpio_set_value(gpio, value);
67
68 if (ssb_bcm47xx.chipco.dev && (gpio < BCM47XX_CHIPCO_GPIO_LINES))
69 ssb_chipco_gpio_outen(&ssb_bcm47xx.chipco,
70 1 << gpio, 1 << gpio);
71 else if (ssb_bcm47xx.extif.dev && (gpio < BCM47XX_EXTIF_GPIO_LINES))
72 ssb_extif_gpio_outen(&ssb_bcm47xx.extif,
73 1 << gpio, 1 << gpio);
74 else
75 return -EINVAL;
76 return 0;
77}
78EXPORT_SYMBOL_GPL(bcm47xx_gpio_direction_output);
79
diff --git a/arch/mips/bcm47xx/irq.c b/arch/mips/bcm47xx/irq.c
new file mode 100644
index 000000000000..325757acd020
--- /dev/null
+++ b/arch/mips/bcm47xx/irq.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/irq.h>
28#include <asm/irq_cpu.h>
29
30void plat_irq_dispatch(void)
31{
32 u32 cause;
33
34 cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
35
36 clear_c0_status(cause);
37
38 if (cause & CAUSEF_IP7)
39 do_IRQ(7);
40 if (cause & CAUSEF_IP2)
41 do_IRQ(2);
42 if (cause & CAUSEF_IP3)
43 do_IRQ(3);
44 if (cause & CAUSEF_IP4)
45 do_IRQ(4);
46 if (cause & CAUSEF_IP5)
47 do_IRQ(5);
48 if (cause & CAUSEF_IP6)
49 do_IRQ(6);
50}
51
52void __init arch_init_irq(void)
53{
54 mips_cpu_irq_init();
55}
diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c
new file mode 100644
index 000000000000..079e33d52783
--- /dev/null
+++ b/arch/mips/bcm47xx/prom.c
@@ -0,0 +1,158 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/types.h>
28#include <linux/kernel.h>
29#include <linux/spinlock.h>
30#include <asm/bootinfo.h>
31#include <asm/fw/cfe/cfe_api.h>
32#include <asm/fw/cfe/cfe_error.h>
33
34static int cfe_cons_handle;
35
36const char *get_system_type(void)
37{
38 return "Broadcom BCM47XX";
39}
40
41void prom_putchar(char c)
42{
43 while (cfe_write(cfe_cons_handle, &c, 1) == 0)
44 ;
45}
46
47static __init void prom_init_cfe(void)
48{
49 uint32_t cfe_ept;
50 uint32_t cfe_handle;
51 uint32_t cfe_eptseal;
52 int argc = fw_arg0;
53 char **envp = (char **) fw_arg2;
54 int *prom_vec = (int *) fw_arg3;
55
56 /*
57 * Check if a loader was used; if NOT, the 4 arguments are
58 * what CFE gives us (handle, 0, EPT and EPTSEAL)
59 */
60 if (argc < 0) {
61 cfe_handle = (uint32_t)argc;
62 cfe_ept = (uint32_t)envp;
63 cfe_eptseal = (uint32_t)prom_vec;
64 } else {
65 if ((int)prom_vec < 0) {
66 /*
67 * Old loader; all it gives us is the handle,
68 * so use the "known" entrypoint and assume
69 * the seal.
70 */
71 cfe_handle = (uint32_t)prom_vec;
72 cfe_ept = 0xBFC00500;
73 cfe_eptseal = CFE_EPTSEAL;
74 } else {
75 /*
76 * Newer loaders bundle the handle/ept/eptseal
77 * Note: prom_vec is in the loader's useg
78 * which is still alive in the TLB.
79 */
80 cfe_handle = prom_vec[0];
81 cfe_ept = prom_vec[2];
82 cfe_eptseal = prom_vec[3];
83 }
84 }
85
86 if (cfe_eptseal != CFE_EPTSEAL) {
87 /* too early for panic to do any good */
88 printk(KERN_ERR "CFE's entrypoint seal doesn't match.");
89 while (1) ;
90 }
91
92 cfe_init(cfe_handle, cfe_ept);
93}
94
95static __init void prom_init_console(void)
96{
97 /* Initialize CFE console */
98 cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
99}
100
101static __init void prom_init_cmdline(void)
102{
103 char buf[CL_SIZE];
104
105 /* Get the kernel command line from CFE */
106 if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) {
107 buf[CL_SIZE-1] = 0;
108 strcpy(arcs_cmdline, buf);
109 }
110
111 /* Force a console handover by adding a console= argument if needed,
112 * as CFE is not available anymore later in the boot process. */
113 if ((strstr(arcs_cmdline, "console=")) == NULL) {
114 /* Try to read the default serial port used by CFE */
115 if ((cfe_getenv("BOOT_CONSOLE", buf, CL_SIZE) < 0)
116 || (strncmp("uart", buf, 4)))
117 /* Default to uart0 */
118 strcpy(buf, "uart0");
119
120 /* Compute the new command line */
121 snprintf(arcs_cmdline, CL_SIZE, "%s console=ttyS%c,115200",
122 arcs_cmdline, buf[4]);
123 }
124}
125
126static __init void prom_init_mem(void)
127{
128 unsigned long mem;
129
130 /* Figure out memory size by finding aliases.
131 *
132 * We should theoretically use the mapping from CFE using cfe_enummem().
133 * However as the BCM47XX is mostly used on low-memory systems, we
134 * want to reuse the memory used by CFE (around 4MB). That means cfe_*
135 * functions stop to work at some point during the boot, we should only
136 * call them at the beginning of the boot.
137 */
138 for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
139 if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
140 *(unsigned long *)(prom_init))
141 break;
142 }
143
144 add_memory_region(0, mem, BOOT_MEM_RAM);
145}
146
147void __init prom_init(void)
148{
149 prom_init_cfe();
150 prom_init_console();
151 prom_init_cmdline();
152 prom_init_mem();
153}
154
155void __init prom_free_prom_memory(void)
156{
157}
158
diff --git a/arch/mips/bcm47xx/serial.c b/arch/mips/bcm47xx/serial.c
new file mode 100644
index 000000000000..59c11afdb2ab
--- /dev/null
+++ b/arch/mips/bcm47xx/serial.c
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/serial.h>
12#include <linux/serial_8250.h>
13#include <linux/ssb/ssb.h>
14#include <bcm47xx.h>
15
16static struct plat_serial8250_port uart8250_data[5];
17
18static struct platform_device uart8250_device = {
19 .name = "serial8250",
20 .id = PLAT8250_DEV_PLATFORM,
21 .dev = {
22 .platform_data = uart8250_data,
23 },
24};
25
26static int __init uart8250_init(void)
27{
28 int i;
29 struct ssb_mipscore *mcore = &(ssb_bcm47xx.mipscore);
30
31 memset(&uart8250_data, 0, sizeof(uart8250_data));
32
33 for (i = 0; i < mcore->nr_serial_ports; i++) {
34 struct plat_serial8250_port *p = &(uart8250_data[i]);
35 struct ssb_serial_port *ssb_port = &(mcore->serial_ports[i]);
36
37 p->mapbase = (unsigned int) ssb_port->regs;
38 p->membase = (void *) ssb_port->regs;
39 p->irq = ssb_port->irq + 2;
40 p->uartclk = ssb_port->baud_base;
41 p->regshift = ssb_port->reg_shift;
42 p->iotype = UPIO_MEM;
43 p->flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
44 }
45 return platform_device_register(&uart8250_device);
46}
47
48module_init(uart8250_init);
49
50MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
51MODULE_LICENSE("GPL");
52MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
diff --git a/arch/mips/bcm47xx/setup.c b/arch/mips/bcm47xx/setup.c
new file mode 100644
index 000000000000..1b6b0fa5028f
--- /dev/null
+++ b/arch/mips/bcm47xx/setup.c
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
4 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2006 Michael Buesch <mb@bu3sch.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
13 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
15 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
18 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
20 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 *
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28#include <linux/types.h>
29#include <linux/ssb/ssb.h>
30#include <asm/bootinfo.h>
31#include <asm/reboot.h>
32#include <asm/time.h>
33#include <bcm47xx.h>
34#include <asm/fw/cfe/cfe_api.h>
35
36struct ssb_bus ssb_bcm47xx;
37EXPORT_SYMBOL(ssb_bcm47xx);
38
39static void bcm47xx_machine_restart(char *command)
40{
41 printk(KERN_ALERT "Please stand by while rebooting the system...\n");
42 local_irq_disable();
43 /* Set the watchdog timer to reset immediately */
44 ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 1);
45 while (1)
46 cpu_relax();
47}
48
49static void bcm47xx_machine_halt(void)
50{
51 /* Disable interrupts and watchdog and spin forever */
52 local_irq_disable();
53 ssb_chipco_watchdog_timer_set(&ssb_bcm47xx.chipco, 0);
54 while (1)
55 cpu_relax();
56}
57
58static void str2eaddr(char *str, char *dest)
59{
60 int i = 0;
61
62 if (str == NULL) {
63 memset(dest, 0, 6);
64 return;
65 }
66
67 for (;;) {
68 dest[i++] = (char) simple_strtoul(str, NULL, 16);
69 str += 2;
70 if (!*str++ || i == 6)
71 break;
72 }
73}
74
75static int bcm47xx_get_invariants(struct ssb_bus *bus,
76 struct ssb_init_invariants *iv)
77{
78 char buf[100];
79
80 /* Fill boardinfo structure */
81 memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
82
83 if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0)
84 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
85 if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0)
86 iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
87 if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0)
88 iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
89
90 /* Fill sprom structure */
91 memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
92 iv->sprom.revision = 3;
93
94 if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
95 str2eaddr(buf, iv->sprom.r1.et0mac);
96 if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
97 str2eaddr(buf, iv->sprom.r1.et1mac);
98 if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
99 iv->sprom.r1.et0phyaddr = simple_strtoul(buf, NULL, 10);
100 if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
101 iv->sprom.r1.et1phyaddr = simple_strtoul(buf, NULL, 10);
102 if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
103 iv->sprom.r1.et0mdcport = simple_strtoul(buf, NULL, 10);
104 if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
105 iv->sprom.r1.et1mdcport = simple_strtoul(buf, NULL, 10);
106
107 return 0;
108}
109
110void __init plat_mem_setup(void)
111{
112 int err;
113
114 err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
115 bcm47xx_get_invariants);
116 if (err)
117 panic("Failed to initialize SSB bus (err %d)\n", err);
118
119 _machine_restart = bcm47xx_machine_restart;
120 _machine_halt = bcm47xx_machine_halt;
121 pm_power_off = bcm47xx_machine_halt;
122}
123
diff --git a/arch/mips/bcm47xx/time.c b/arch/mips/bcm47xx/time.c
new file mode 100644
index 000000000000..0ab4676c8bd3
--- /dev/null
+++ b/arch/mips/bcm47xx/time.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (C) 2004 Florian Schirmer <jolt@tuxbox.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25
26#include <linux/init.h>
27#include <linux/ssb/ssb.h>
28#include <asm/time.h>
29#include <bcm47xx.h>
30
31void __init plat_time_init(void)
32{
33 unsigned long hz;
34
35 /*
36 * Use deterministic values for initial counter interrupt
37 * so that calibrate delay avoids encountering a counter wrap.
38 */
39 write_c0_count(0);
40 write_c0_compare(0xffff);
41
42 hz = ssb_cpu_clock(&ssb_bcm47xx.mipscore) / 2;
43 if (!hz)
44 hz = 100000000;
45
46 /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
47 mips_hpt_frequency = hz;
48}
49
50void __init
51plat_timer_setup(struct irqaction *irq)
52{
53 /* Enable the timer interrupt */
54 setup_irq(7, irq);
55}
diff --git a/arch/mips/bcm47xx/wgt634u.c b/arch/mips/bcm47xx/wgt634u.c
new file mode 100644
index 000000000000..5a017eaee712
--- /dev/null
+++ b/arch/mips/bcm47xx/wgt634u.c
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
7 */
8
9#include <linux/platform_device.h>
10#include <linux/module.h>
11#include <linux/leds.h>
12#include <linux/ssb/ssb.h>
13#include <asm/mach-bcm47xx/bcm47xx.h>
14
15/* GPIO definitions for the WGT634U */
16#define WGT634U_GPIO_LED 3
17#define WGT634U_GPIO_RESET 2
18#define WGT634U_GPIO_TP1 7
19#define WGT634U_GPIO_TP2 6
20#define WGT634U_GPIO_TP3 5
21#define WGT634U_GPIO_TP4 4
22#define WGT634U_GPIO_TP5 1
23
24static struct gpio_led wgt634u_leds[] = {
25 {
26 .name = "power",
27 .gpio = WGT634U_GPIO_LED,
28 .active_low = 1,
29 .default_trigger = "heartbeat",
30 },
31};
32
33static struct gpio_led_platform_data wgt634u_led_data = {
34 .num_leds = ARRAY_SIZE(wgt634u_leds),
35 .leds = wgt634u_leds,
36};
37
38static struct platform_device wgt634u_gpio_leds = {
39 .name = "leds-gpio",
40 .id = -1,
41 .dev = {
42 .platform_data = &wgt634u_led_data,
43 }
44};
45
46static int __init wgt634u_init(void)
47{
48 /* There is no easy way to detect that we are running on a WGT634U
49 * machine. Use the MAC address as an heuristic. Netgear Inc. has
50 * been allocated ranges 00:09:5b:xx:xx:xx and 00:0f:b5:xx:xx:xx.
51 */
52
53 u8 *et0mac = ssb_bcm47xx.sprom.r1.et0mac;
54
55 if (et0mac[0] == 0x00 &&
56 ((et0mac[1] == 0x09 && et0mac[2] == 0x5b) ||
57 (et0mac[1] == 0x0f && et0mac[2] == 0xb5)))
58 return platform_device_register(&wgt634u_gpio_leds);
59 else
60 return -ENODEV;
61}
62
63module_init(wgt634u_init);
64
diff --git a/arch/mips/boot/addinitrd.c b/arch/mips/boot/addinitrd.c
index 8b3033304770..b5b3febc10cc 100644
--- a/arch/mips/boot/addinitrd.c
+++ b/arch/mips/boot/addinitrd.c
@@ -32,15 +32,15 @@
32 32
33#define SWAB(a) (swab ? swab32(a) : (a)) 33#define SWAB(a) (swab ? swab32(a) : (a))
34 34
35void die (char *s) 35void die(char *s)
36{ 36{
37 perror (s); 37 perror(s);
38 exit (1); 38 exit(1);
39} 39}
40 40
41int main (int argc, char *argv[]) 41int main(int argc, char *argv[])
42{ 42{
43 int fd_vmlinux,fd_initrd,fd_outfile; 43 int fd_vmlinux, fd_initrd, fd_outfile;
44 FILHDR efile; 44 FILHDR efile;
45 AOUTHDR eaout; 45 AOUTHDR eaout;
46 SCNHDR esecs[3]; 46 SCNHDR esecs[3];
@@ -48,22 +48,22 @@ int main (int argc, char *argv[])
48 char buf[1024]; 48 char buf[1024];
49 unsigned long loadaddr; 49 unsigned long loadaddr;
50 unsigned long initrd_header[2]; 50 unsigned long initrd_header[2];
51 int i,cnt; 51 int i, cnt;
52 int swab = 0; 52 int swab = 0;
53 53
54 if (argc != 4) { 54 if (argc != 4) {
55 printf ("Usage: %s <vmlinux> <initrd> <outfile>\n",argv[0]); 55 printf("Usage: %s <vmlinux> <initrd> <outfile>\n", argv[0]);
56 exit (1); 56 exit(1);
57 } 57 }
58 58
59 if ((fd_vmlinux = open (argv[1],O_RDONLY)) < 0) 59 if ((fd_vmlinux = open (argv[1], O_RDONLY)) < 0)
60 die ("open vmlinux"); 60 die("open vmlinux");
61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile) 61 if (read (fd_vmlinux, &efile, sizeof efile) != sizeof efile)
62 die ("read file header"); 62 die("read file header");
63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout) 63 if (read (fd_vmlinux, &eaout, sizeof eaout) != sizeof eaout)
64 die ("read aout header"); 64 die("read aout header");
65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs) 65 if (read (fd_vmlinux, esecs, sizeof esecs) != sizeof esecs)
66 die ("read section headers"); 66 die("read section headers");
67 /* 67 /*
68 * check whether the file is good for us 68 * check whether the file is good for us
69 */ 69 */
@@ -82,13 +82,13 @@ int main (int argc, char *argv[])
82 82
83 /* make sure we have an empty data segment for the initrd */ 83 /* make sure we have an empty data segment for the initrd */
84 if (eaout.dsize || esecs[1].s_size) { 84 if (eaout.dsize || esecs[1].s_size) {
85 fprintf (stderr, "Data segment not empty. Giving up!\n"); 85 fprintf(stderr, "Data segment not empty. Giving up!\n");
86 exit (1); 86 exit(1);
87 } 87 }
88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0) 88 if ((fd_initrd = open (argv[2], O_RDONLY)) < 0)
89 die ("open initrd"); 89 die("open initrd");
90 if (fstat (fd_initrd, &st) < 0) 90 if (fstat (fd_initrd, &st) < 0)
91 die ("fstat initrd"); 91 die("fstat initrd");
92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size) 92 loadaddr = ((SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)
93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8; 93 + MIPS_PAGE_SIZE-1) & ~MIPS_PAGE_MASK) - 8;
94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size))) 94 if (loadaddr < (SWAB(esecs[2].s_vaddr) + SWAB(esecs[2].s_size)))
@@ -98,34 +98,34 @@ int main (int argc, char *argv[])
98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8); 98 eaout.dsize = esecs[1].s_size = initrd_header[1] = SWAB(st.st_size+8);
99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr); 99 eaout.data_start = esecs[1].s_vaddr = esecs[1].s_paddr = SWAB(loadaddr);
100 100
101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC,0666)) < 0) 101 if ((fd_outfile = open (argv[3], O_RDWR|O_CREAT|O_TRUNC, 0666)) < 0)
102 die ("open outfile"); 102 die("open outfile");
103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile) 103 if (write (fd_outfile, &efile, sizeof efile) != sizeof efile)
104 die ("write file header"); 104 die("write file header");
105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout) 105 if (write (fd_outfile, &eaout, sizeof eaout) != sizeof eaout)
106 die ("write aout header"); 106 die("write aout header");
107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs) 107 if (write (fd_outfile, esecs, sizeof esecs) != sizeof esecs)
108 die ("write section headers"); 108 die("write section headers");
109 /* skip padding */ 109 /* skip padding */
110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 110 if(lseek(fd_vmlinux, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
111 die ("lseek vmlinux"); 111 die("lseek vmlinux");
112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1) 112 if(lseek(fd_outfile, SWAB(esecs[0].s_scnptr), SEEK_SET) == (off_t)-1)
113 die ("lseek outfile"); 113 die("lseek outfile");
114 /* copy text segment */ 114 /* copy text segment */
115 cnt = SWAB(eaout.tsize); 115 cnt = SWAB(eaout.tsize);
116 while (cnt) { 116 while (cnt) {
117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0) 117 if ((i = read (fd_vmlinux, buf, sizeof buf)) <= 0)
118 die ("read vmlinux"); 118 die("read vmlinux");
119 if (write (fd_outfile, buf, i) != i) 119 if (write (fd_outfile, buf, i) != i)
120 die ("write vmlinux"); 120 die("write vmlinux");
121 cnt -= i; 121 cnt -= i;
122 } 122 }
123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header) 123 if (write (fd_outfile, initrd_header, sizeof initrd_header) != sizeof initrd_header)
124 die ("write initrd header"); 124 die("write initrd header");
125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0) 125 while ((i = read (fd_initrd, buf, sizeof buf)) > 0)
126 if (write (fd_outfile, buf, i) != i) 126 if (write (fd_outfile, buf, i) != i)
127 die ("write initrd"); 127 die("write initrd");
128 close (fd_vmlinux); 128 close(fd_vmlinux);
129 close (fd_initrd); 129 close(fd_initrd);
130 return 0; 130 return 0;
131} 131}
diff --git a/arch/mips/boot/elf2ecoff.c b/arch/mips/boot/elf2ecoff.c
index c3543d9eb266..c5a7f308c405 100644
--- a/arch/mips/boot/elf2ecoff.c
+++ b/arch/mips/boot/elf2ecoff.c
@@ -467,7 +467,7 @@ int main(int argc, char *argv[])
467 esecs[0].s_scnptr = N_TXTOFF(efh, eah); 467 esecs[0].s_scnptr = N_TXTOFF(efh, eah);
468 esecs[1].s_scnptr = N_DATOFF(efh, eah); 468 esecs[1].s_scnptr = N_DATOFF(efh, eah);
469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10 469#define ECOFF_SEGMENT_ALIGNMENT(a) 0x10
470#define ECOFF_ROUND(s,a) (((s)+(a)-1)&~((a)-1)) 470#define ECOFF_ROUND(s, a) (((s)+(a)-1)&~((a)-1))
471 esecs[2].s_scnptr = esecs[1].s_scnptr + 471 esecs[2].s_scnptr = esecs[1].s_scnptr +
472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah)); 472 ECOFF_ROUND(esecs[1].s_size, ECOFF_SEGMENT_ALIGNMENT(&eah));
473 if (addflag) { 473 if (addflag) {
diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile
index a043f93f7d08..6b83f4ddc8fc 100644
--- a/arch/mips/cobalt/Makefile
+++ b/arch/mips/cobalt/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the Cobalt micro systems family specific parts of the kernel 2# Makefile for the Cobalt micro systems family specific parts of the kernel
3# 3#
4 4
5obj-y := buttons.o irq.o reset.o rtc.o serial.o setup.o 5obj-y := buttons.o irq.o led.o reset.o rtc.o serial.o setup.o
6 6
7obj-$(CONFIG_PCI) += pci.o 7obj-$(CONFIG_PCI) += pci.o
8obj-$(CONFIG_EARLY_PRINTK) += console.o 8obj-$(CONFIG_EARLY_PRINTK) += console.o
diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c
index 0485d51f7216..db330e811025 100644
--- a/arch/mips/cobalt/console.c
+++ b/arch/mips/cobalt/console.c
@@ -1,16 +1,15 @@
1/* 1/*
2 * (C) P. Horton 2006 2 * (C) P. Horton 2006
3 */ 3 */
4#include <linux/io.h>
4#include <linux/serial_reg.h> 5#include <linux/serial_reg.h>
5 6
6#include <asm/addrspace.h> 7#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000))
7
8#include <cobalt.h>
9 8
10void prom_putchar(char c) 9void prom_putchar(char c)
11{ 10{
12 while(!(COBALT_UART[UART_LSR] & UART_LSR_THRE)) 11 while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE))
13 ; 12 ;
14 13
15 COBALT_UART[UART_TX] = c; 14 writeb(c, UART_BASE + UART_TX);
16} 15}
diff --git a/arch/mips/cobalt/irq.c b/arch/mips/cobalt/irq.c
index 950ad1e8be44..ac4fb912649d 100644
--- a/arch/mips/cobalt/irq.c
+++ b/arch/mips/cobalt/irq.c
@@ -15,102 +15,48 @@
15 15
16#include <asm/i8259.h> 16#include <asm/i8259.h>
17#include <asm/irq_cpu.h> 17#include <asm/irq_cpu.h>
18#include <asm/irq_gt641xx.h>
18#include <asm/gt64120.h> 19#include <asm/gt64120.h>
19 20
20#include <cobalt.h> 21#include <irq.h>
21
22/*
23 * We have two types of interrupts that we handle, ones that come in through
24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
25 * mappings are:
26 *
27 * 16 - Software interrupt 0 (unused) IE_SW0
28 * 17 - Software interrupt 1 (unused) IE_SW1
29 * 18 - Galileo chip (timer) IE_IRQ0
30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
31 * 20 - Tulip 1 IE_IRQ2
32 * 21 - 16550 UART IE_IRQ3
33 * 22 - VIA southbridge PIC IE_IRQ4
34 * 23 - unused IE_IRQ5
35 *
36 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
37 *
38 * 8 - RTC
39 * 9 - PCI
40 * 14 - IDE0
41 * 15 - IDE1
42 */
43
44static inline void galileo_irq(void)
45{
46 unsigned int mask, pending, devfn;
47
48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50
51 if (pending & GT_INTR_T0EXP_MSK) {
52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 do_IRQ(COBALT_GALILEO_IRQ);
54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
57 printk(KERN_WARNING
58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
59 PCI_SLOT(devfn), PCI_FUNC(devfn));
60 } else {
61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
62 printk(KERN_WARNING
63 "Galileo: masking unexpected interrupt %08x\n", pending);
64 }
65}
66
67static inline void via_pic_irq(void)
68{
69 int irq;
70
71 irq = i8259_irq();
72 if (irq >= 0)
73 do_IRQ(irq);
74}
75 22
76asmlinkage void plat_irq_dispatch(void) 23asmlinkage void plat_irq_dispatch(void)
77{ 24{
78 unsigned pending = read_c0_status() & read_c0_cause(); 25 unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
26 int irq;
79 27
80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */ 28 if (pending & CAUSEF_IP2)
81 galileo_irq(); 29 gt641xx_irq_dispatch();
82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */ 30 else if (pending & CAUSEF_IP6) {
83 via_pic_irq(); 31 irq = i8259_irq();
84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */ 32 if (irq < 0)
85 do_IRQ(COBALT_CPU_IRQ + 3); 33 spurious_interrupt();
86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */ 34 else
87 do_IRQ(COBALT_CPU_IRQ + 4); 35 do_IRQ(irq);
88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */ 36 } else if (pending & CAUSEF_IP3)
89 do_IRQ(COBALT_CPU_IRQ + 5); 37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
90 else if (pending & CAUSEF_IP7) /* IRQ 23 */ 38 else if (pending & CAUSEF_IP4)
91 do_IRQ(COBALT_CPU_IRQ + 7); 39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
40 else if (pending & CAUSEF_IP5)
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
42 else if (pending & CAUSEF_IP7)
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
44 else
45 spurious_interrupt();
92} 46}
93 47
94static struct irqaction irq_via = { 48static struct irqaction cascade = {
95 no_action, 0, { { 0, } }, "cascade", NULL, NULL 49 .handler = no_action,
50 .mask = CPU_MASK_NONE,
51 .name = "cascade",
96}; 52};
97 53
98void __init arch_init_irq(void) 54void __init arch_init_irq(void)
99{ 55{
100 /* 56 mips_cpu_irq_init();
101 * Mask all Galileo interrupts. The Galileo 57 gt641xx_irq_init();
102 * handler is set in cobalt_timer_setup() 58 init_i8259_irqs();
103 */
104 GT_WRITE(GT_INTRMASK_OFS, 0);
105
106 init_i8259_irqs(); /* 0 ... 15 */
107 mips_cpu_irq_init(); /* 16 ... 23 */
108
109 /*
110 * Mask all cpu interrupts
111 * (except IE4, we already masked those at VIA level)
112 */
113 change_c0_status(ST0_IM, IE_IRQ4);
114 59
115 setup_irq(COBALT_VIA_IRQ, &irq_via); 60 setup_irq(GT641XX_CASCADE_IRQ, &cascade);
61 setup_irq(I8259_CASCADE_IRQ, &cascade);
116} 62}
diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c
new file mode 100644
index 000000000000..1c6ebd468b07
--- /dev/null
+++ b/arch/mips/cobalt/led.c
@@ -0,0 +1,62 @@
1/*
2 * Registration of Cobalt LED platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24
25#include <cobalt.h>
26
27static struct resource cobalt_led_resource __initdata = {
28 .start = 0x1c000000,
29 .end = 0x1c000000,
30 .flags = IORESOURCE_MEM,
31};
32
33static __init int cobalt_led_add(void)
34{
35 struct platform_device *pdev;
36 int retval;
37
38 if (cobalt_board_id == COBALT_BRD_ID_QUBE1 ||
39 cobalt_board_id == COBALT_BRD_ID_QUBE2)
40 pdev = platform_device_alloc("cobalt-qube-leds", -1);
41 else
42 pdev = platform_device_alloc("cobalt-raq-leds", -1);
43
44 if (!pdev)
45 return -ENOMEM;
46
47 retval = platform_device_add_resources(pdev, &cobalt_led_resource, 1);
48 if (retval)
49 goto err_free_device;
50
51 retval = platform_device_add(pdev);
52 if (retval)
53 goto err_free_device;
54
55 return 0;
56
57err_free_device:
58 platform_device_put(pdev);
59
60 return retval;
61}
62device_initcall(cobalt_led_add);
diff --git a/arch/mips/cobalt/reset.c b/arch/mips/cobalt/reset.c
index 43cca21fdbc0..71eb4ccc4bc1 100644
--- a/arch/mips/cobalt/reset.c
+++ b/arch/mips/cobalt/reset.c
@@ -8,36 +8,46 @@
8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle 8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9 * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv) 9 * Copyright (C) 2001 by Liam Davies (ldavies@agile.tv)
10 */ 10 */
11#include <linux/init.h>
12#include <linux/io.h>
11#include <linux/jiffies.h> 13#include <linux/jiffies.h>
12 14#include <linux/leds.h>
13#include <asm/io.h>
14#include <asm/reboot.h>
15 15
16#include <cobalt.h> 16#include <cobalt.h>
17 17
18#define RESET_PORT ((void __iomem *)CKSEG1ADDR(0x1c000000))
19#define RESET 0x0f
20
21DEFINE_LED_TRIGGER(power_off_led_trigger);
22
23static int __init ledtrig_power_off_init(void)
24{
25 led_trigger_register_simple("power-off", &power_off_led_trigger);
26 return 0;
27}
28device_initcall(ledtrig_power_off_init);
29
18void cobalt_machine_halt(void) 30void cobalt_machine_halt(void)
19{ 31{
20 int state, last, diff; 32 int state, last, diff;
21 unsigned long mark; 33 unsigned long mark;
22 34
23 /* 35 /*
24 * turn off bar on Qube, flash power off LED on RaQ (0.5Hz) 36 * turn on power off LED on RaQ
25 * 37 *
26 * restart if ENTER and SELECT are pressed 38 * restart if ENTER and SELECT are pressed
27 */ 39 */
28 40
29 last = COBALT_KEY_PORT; 41 last = COBALT_KEY_PORT;
30 42
31 for (state = 0;;) { 43 led_trigger_event(power_off_led_trigger, LED_FULL);
32
33 state ^= COBALT_LED_POWER_OFF;
34 COBALT_LED_PORT = state;
35 44
45 for (state = 0;;) {
36 diff = COBALT_KEY_PORT ^ last; 46 diff = COBALT_KEY_PORT ^ last;
37 last ^= diff; 47 last ^= diff;
38 48
39 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT))) 49 if((diff & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)) && !(~last & (COBALT_KEY_ENTER | COBALT_KEY_SELECT)))
40 COBALT_LED_PORT = COBALT_LED_RESET; 50 writeb(RESET, RESET_PORT);
41 51
42 for (mark = jiffies; jiffies - mark < HZ;) 52 for (mark = jiffies; jiffies - mark < HZ;)
43 ; 53 ;
@@ -46,17 +56,8 @@ void cobalt_machine_halt(void)
46 56
47void cobalt_machine_restart(char *command) 57void cobalt_machine_restart(char *command)
48{ 58{
49 COBALT_LED_PORT = COBALT_LED_RESET; 59 writeb(RESET, RESET_PORT);
50 60
51 /* we should never get here */ 61 /* we should never get here */
52 cobalt_machine_halt(); 62 cobalt_machine_halt();
53} 63}
54
55/*
56 * This triggers the luser mode device driver for the power switch ;-)
57 */
58void cobalt_machine_power_off(void)
59{
60 printk("You can switch the machine off now.\n");
61 cobalt_machine_halt();
62}
diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c
index 284daefc5c55..e70794b8bcba 100644
--- a/arch/mips/cobalt/rtc.c
+++ b/arch/mips/cobalt/rtc.c
@@ -20,6 +20,7 @@
20#include <linux/errno.h> 20#include <linux/errno.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/mc146818rtc.h>
23#include <linux/platform_device.h> 24#include <linux/platform_device.h>
24 25
25static struct resource cobalt_rtc_resource[] __initdata = { 26static struct resource cobalt_rtc_resource[] __initdata = {
@@ -29,8 +30,8 @@ static struct resource cobalt_rtc_resource[] __initdata = {
29 .flags = IORESOURCE_IO, 30 .flags = IORESOURCE_IO,
30 }, 31 },
31 { 32 {
32 .start = 8, 33 .start = RTC_IRQ,
33 .end = 8, 34 .end = RTC_IRQ,
34 .flags = IORESOURCE_IRQ, 35 .flags = IORESOURCE_IRQ,
35 }, 36 },
36}; 37};
diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c
index 08e739704cc9..53b8d0d6da90 100644
--- a/arch/mips/cobalt/serial.c
+++ b/arch/mips/cobalt/serial.c
@@ -24,6 +24,7 @@
24#include <linux/serial_8250.h> 24#include <linux/serial_8250.h>
25 25
26#include <cobalt.h> 26#include <cobalt.h>
27#include <irq.h>
27 28
28static struct resource cobalt_uart_resource[] __initdata = { 29static struct resource cobalt_uart_resource[] __initdata = {
29 { 30 {
@@ -32,15 +33,15 @@ static struct resource cobalt_uart_resource[] __initdata = {
32 .flags = IORESOURCE_MEM, 33 .flags = IORESOURCE_MEM,
33 }, 34 },
34 { 35 {
35 .start = COBALT_SERIAL_IRQ, 36 .start = SERIAL_IRQ,
36 .end = COBALT_SERIAL_IRQ, 37 .end = SERIAL_IRQ,
37 .flags = IORESOURCE_IRQ, 38 .flags = IORESOURCE_IRQ,
38 }, 39 },
39}; 40};
40 41
41static struct plat_serial8250_port cobalt_serial8250_port[] = { 42static struct plat_serial8250_port cobalt_serial8250_port[] = {
42 { 43 {
43 .irq = COBALT_SERIAL_IRQ, 44 .irq = SERIAL_IRQ,
44 .uartclk = 18432000, 45 .uartclk = 18432000,
45 .iotype = UPIO_MEM, 46 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, 47 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c
index 7abe45e78425..d11bb1bc7b6b 100644
--- a/arch/mips/cobalt/setup.c
+++ b/arch/mips/cobalt/setup.c
@@ -15,15 +15,16 @@
15 15
16#include <asm/bootinfo.h> 16#include <asm/bootinfo.h>
17#include <asm/time.h> 17#include <asm/time.h>
18#include <asm/i8253.h>
18#include <asm/io.h> 19#include <asm/io.h>
19#include <asm/reboot.h> 20#include <asm/reboot.h>
20#include <asm/gt64120.h> 21#include <asm/gt64120.h>
21 22
22#include <cobalt.h> 23#include <cobalt.h>
24#include <irq.h>
23 25
24extern void cobalt_machine_restart(char *command); 26extern void cobalt_machine_restart(char *command);
25extern void cobalt_machine_halt(void); 27extern void cobalt_machine_halt(void);
26extern void cobalt_machine_power_off(void);
27 28
28const char *get_system_type(void) 29const char *get_system_type(void)
29{ 30{
@@ -45,14 +46,10 @@ void __init plat_timer_setup(struct irqaction *irq)
45 /* Load timer value for HZ (TCLK is 50MHz) */ 46 /* Load timer value for HZ (TCLK is 50MHz) */
46 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ); 47 GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
47 48
48 /* Enable timer */ 49 /* Enable timer0 */
49 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK); 50 GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
50 51
51 /* Register interrupt */ 52 setup_irq(GT641XX_TIMER0_IRQ, irq);
52 setup_irq(COBALT_GALILEO_IRQ, irq);
53
54 /* Enable interrupt */
55 GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
56} 53}
57 54
58/* 55/*
@@ -87,13 +84,18 @@ static struct resource cobalt_reserved_resources[] = {
87 }, 84 },
88}; 85};
89 86
87void __init plat_time_init(void)
88{
89 setup_pit_timer();
90}
91
90void __init plat_mem_setup(void) 92void __init plat_mem_setup(void)
91{ 93{
92 int i; 94 int i;
93 95
94 _machine_restart = cobalt_machine_restart; 96 _machine_restart = cobalt_machine_restart;
95 _machine_halt = cobalt_machine_halt; 97 _machine_halt = cobalt_machine_halt;
96 pm_power_off = cobalt_machine_power_off; 98 pm_power_off = cobalt_machine_halt;
97 99
98 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); 100 set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
99 101
@@ -117,8 +119,6 @@ void __init prom_init(void)
117 unsigned long memsz; 119 unsigned long memsz;
118 char **argv; 120 char **argv;
119 121
120 mips_machgroup = MACH_GROUP_COBALT;
121
122 memsz = fw_arg0 & 0x7fff0000; 122 memsz = fw_arg0 & 0x7fff0000;
123 narg = fw_arg0 & 0x0000ffff; 123 narg = fw_arg0 & 0x0000ffff;
124 124
diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig
index 700a3a2d688e..30f3e9a2466f 100644
--- a/arch/mips/configs/bigsur_defconfig
+++ b/arch/mips/configs/bigsur_defconfig
@@ -69,7 +69,6 @@ CONFIG_SIBYTE_SB1xxx_SOC=y
69CONFIG_SIBYTE_CFE=y 69CONFIG_SIBYTE_CFE=y
70# CONFIG_SIBYTE_CFE_CONSOLE is not set 70# CONFIG_SIBYTE_CFE_CONSOLE is not set
71# CONFIG_SIBYTE_BUS_WATCHER is not set 71# CONFIG_SIBYTE_BUS_WATCHER is not set
72# CONFIG_SIBYTE_SB1250_PROF is not set
73# CONFIG_SIBYTE_TBPROF is not set 72# CONFIG_SIBYTE_TBPROF is not set
74CONFIG_RWSEM_GENERIC_SPINLOCK=y 73CONFIG_RWSEM_GENERIC_SPINLOCK=y
75# CONFIG_ARCH_HAS_ILOG2_U32 is not set 74# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig
index ebcb7ad8814b..36c13039e237 100644
--- a/arch/mips/configs/cobalt_defconfig
+++ b/arch/mips/configs/cobalt_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc2 3# Linux kernel version: 2.6.23-rc5
4# Tue Aug 7 22:12:54 2007 4# Thu Sep 6 13:14:29 2007
5# 5#
6CONFIG_MIPS=y 6CONFIG_MIPS=y
7 7
@@ -55,12 +55,14 @@ CONFIG_DMA_NONCOHERENT=y
55CONFIG_DMA_NEED_PCI_MAP_STATE=y 55CONFIG_DMA_NEED_PCI_MAP_STATE=y
56CONFIG_EARLY_PRINTK=y 56CONFIG_EARLY_PRINTK=y
57CONFIG_SYS_HAS_EARLY_PRINTK=y 57CONFIG_SYS_HAS_EARLY_PRINTK=y
58# CONFIG_HOTPLUG_CPU is not set
58CONFIG_I8259=y 59CONFIG_I8259=y
59# CONFIG_NO_IOPORT is not set 60# CONFIG_NO_IOPORT is not set
60# CONFIG_CPU_BIG_ENDIAN is not set 61# CONFIG_CPU_BIG_ENDIAN is not set
61CONFIG_CPU_LITTLE_ENDIAN=y 62CONFIG_CPU_LITTLE_ENDIAN=y
62CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y 63CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
63CONFIG_IRQ_CPU=y 64CONFIG_IRQ_CPU=y
65CONFIG_IRQ_GT641XX=y
64CONFIG_PCI_GT64XXX_PCI0=y 66CONFIG_PCI_GT64XXX_PCI0=y
65CONFIG_MIPS_L1_CACHE_SHIFT=5 67CONFIG_MIPS_L1_CACHE_SHIFT=5
66 68
@@ -235,6 +237,7 @@ CONFIG_TRAD_SIGNALS=y
235# Power management options 237# Power management options
236# 238#
237# CONFIG_PM is not set 239# CONFIG_PM is not set
240CONFIG_SUSPEND_UP_POSSIBLE=y
238 241
239# 242#
240# Networking 243# Networking
@@ -844,7 +847,21 @@ CONFIG_USB_MON=y
844# 847#
845# CONFIG_USB_GADGET is not set 848# CONFIG_USB_GADGET is not set
846# CONFIG_MMC is not set 849# CONFIG_MMC is not set
847# CONFIG_NEW_LEDS is not set 850CONFIG_NEW_LEDS=y
851CONFIG_LEDS_CLASS=y
852
853#
854# LED drivers
855#
856CONFIG_LEDS_COBALT_QUBE=y
857CONFIG_LEDS_COBALT_RAQ=y
858
859#
860# LED Triggers
861#
862CONFIG_LEDS_TRIGGERS=y
863# CONFIG_LEDS_TRIGGER_TIMER is not set
864# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
848# CONFIG_INFINIBAND is not set 865# CONFIG_INFINIBAND is not set
849CONFIG_RTC_LIB=y 866CONFIG_RTC_LIB=y
850CONFIG_RTC_CLASS=y 867CONFIG_RTC_CLASS=y
diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig
new file mode 100644
index 000000000000..2c665fcef089
--- /dev/null
+++ b/arch/mips/configs/lasat_defconfig
@@ -0,0 +1,828 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc3
4# Sat Aug 18 17:37:58 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set
16CONFIG_LASAT=y
17# CONFIG_LEMOTE_FULONG is not set
18# CONFIG_MIPS_ATLAS is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SEAD is not set
21# CONFIG_MIPS_SIM is not set
22# CONFIG_MARKEINS is not set
23# CONFIG_MACH_VR41XX is not set
24# CONFIG_PNX8550_JBS is not set
25# CONFIG_PNX8550_STB810 is not set
26# CONFIG_PMC_MSP is not set
27# CONFIG_PMC_YOSEMITE is not set
28# CONFIG_QEMU is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP32 is not set
32# CONFIG_SIBYTE_CRHINE is not set
33# CONFIG_SIBYTE_CARMEL is not set
34# CONFIG_SIBYTE_CRHONE is not set
35# CONFIG_SIBYTE_RHONE is not set
36# CONFIG_SIBYTE_SWARM is not set
37# CONFIG_SIBYTE_LITTLESUR is not set
38# CONFIG_SIBYTE_SENTOSA is not set
39# CONFIG_SIBYTE_PTSWARM is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_TOSHIBA_JMR3927 is not set
43# CONFIG_TOSHIBA_RBTX4927 is not set
44# CONFIG_TOSHIBA_RBTX4938 is not set
45# CONFIG_WR_PPMC is not set
46CONFIG_PICVUE=y
47CONFIG_PICVUE_PROC=y
48CONFIG_DS1603=y
49CONFIG_LASAT_SYSCTL=y
50CONFIG_RWSEM_GENERIC_SPINLOCK=y
51# CONFIG_ARCH_HAS_ILOG2_U32 is not set
52# CONFIG_ARCH_HAS_ILOG2_U64 is not set
53CONFIG_GENERIC_FIND_NEXT_BIT=y
54CONFIG_GENERIC_HWEIGHT=y
55CONFIG_GENERIC_CALIBRATE_DELAY=y
56CONFIG_GENERIC_TIME=y
57CONFIG_GENERIC_CMOS_UPDATE=y
58CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
59CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
60CONFIG_DMA_NONCOHERENT=y
61CONFIG_DMA_NEED_PCI_MAP_STATE=y
62CONFIG_EARLY_PRINTK=y
63CONFIG_SYS_HAS_EARLY_PRINTK=y
64# CONFIG_HOTPLUG_CPU is not set
65CONFIG_MIPS_NILE4=y
66# CONFIG_NO_IOPORT is not set
67# CONFIG_CPU_BIG_ENDIAN is not set
68CONFIG_CPU_LITTLE_ENDIAN=y
69CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
70CONFIG_PCI_GT64XXX_PCI0=y
71CONFIG_MIPS_L1_CACHE_SHIFT=5
72
73#
74# CPU selection
75#
76# CONFIG_CPU_LOONGSON2 is not set
77# CONFIG_CPU_MIPS32_R1 is not set
78# CONFIG_CPU_MIPS32_R2 is not set
79# CONFIG_CPU_MIPS64_R1 is not set
80# CONFIG_CPU_MIPS64_R2 is not set
81# CONFIG_CPU_R3000 is not set
82# CONFIG_CPU_TX39XX is not set
83# CONFIG_CPU_VR41XX is not set
84# CONFIG_CPU_R4300 is not set
85# CONFIG_CPU_R4X00 is not set
86# CONFIG_CPU_TX49XX is not set
87CONFIG_CPU_R5000=y
88# CONFIG_CPU_R5432 is not set
89# CONFIG_CPU_R6000 is not set
90# CONFIG_CPU_NEVADA is not set
91# CONFIG_CPU_R8000 is not set
92# CONFIG_CPU_R10000 is not set
93# CONFIG_CPU_RM7000 is not set
94# CONFIG_CPU_RM9000 is not set
95# CONFIG_CPU_SB1 is not set
96CONFIG_SYS_HAS_CPU_R5000=y
97CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
98CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
99CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
100
101#
102# Kernel type
103#
104CONFIG_32BIT=y
105# CONFIG_64BIT is not set
106CONFIG_PAGE_SIZE_4KB=y
107# CONFIG_PAGE_SIZE_8KB is not set
108# CONFIG_PAGE_SIZE_16KB is not set
109# CONFIG_PAGE_SIZE_64KB is not set
110CONFIG_BOARD_SCACHE=y
111CONFIG_R5000_CPU_SCACHE=y
112CONFIG_MIPS_MT_DISABLED=y
113# CONFIG_MIPS_MT_SMP is not set
114# CONFIG_MIPS_MT_SMTC is not set
115CONFIG_CPU_HAS_LLSC=y
116CONFIG_CPU_HAS_SYNC=y
117CONFIG_GENERIC_HARDIRQS=y
118CONFIG_GENERIC_IRQ_PROBE=y
119CONFIG_ARCH_FLATMEM_ENABLE=y
120CONFIG_SELECT_MEMORY_MODEL=y
121CONFIG_FLATMEM_MANUAL=y
122# CONFIG_DISCONTIGMEM_MANUAL is not set
123# CONFIG_SPARSEMEM_MANUAL is not set
124CONFIG_FLATMEM=y
125CONFIG_FLAT_NODE_MEM_MAP=y
126# CONFIG_SPARSEMEM_STATIC is not set
127CONFIG_SPLIT_PTLOCK_CPUS=4
128# CONFIG_RESOURCES_64BIT is not set
129CONFIG_ZONE_DMA_FLAG=0
130CONFIG_VIRT_TO_BUS=y
131# CONFIG_HZ_48 is not set
132# CONFIG_HZ_100 is not set
133# CONFIG_HZ_128 is not set
134# CONFIG_HZ_250 is not set
135# CONFIG_HZ_256 is not set
136CONFIG_HZ_1000=y
137# CONFIG_HZ_1024 is not set
138CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
139CONFIG_HZ=1000
140CONFIG_PREEMPT_NONE=y
141# CONFIG_PREEMPT_VOLUNTARY is not set
142# CONFIG_PREEMPT is not set
143# CONFIG_KEXEC is not set
144# CONFIG_SECCOMP is not set
145CONFIG_LOCKDEP_SUPPORT=y
146CONFIG_STACKTRACE_SUPPORT=y
147CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
148
149#
150# General setup
151#
152CONFIG_EXPERIMENTAL=y
153CONFIG_BROKEN_ON_SMP=y
154CONFIG_INIT_ENV_ARG_LIMIT=32
155CONFIG_LOCALVERSION=""
156CONFIG_LOCALVERSION_AUTO=y
157CONFIG_SWAP=y
158CONFIG_SYSVIPC=y
159CONFIG_SYSVIPC_SYSCTL=y
160# CONFIG_POSIX_MQUEUE is not set
161# CONFIG_BSD_PROCESS_ACCT is not set
162# CONFIG_TASKSTATS is not set
163# CONFIG_USER_NS is not set
164# CONFIG_AUDIT is not set
165# CONFIG_IKCONFIG is not set
166CONFIG_LOG_BUF_SHIFT=14
167# CONFIG_SYSFS_DEPRECATED is not set
168# CONFIG_RELAY is not set
169# CONFIG_BLK_DEV_INITRD is not set
170CONFIG_CC_OPTIMIZE_FOR_SIZE=y
171CONFIG_SYSCTL=y
172CONFIG_EMBEDDED=y
173# CONFIG_SYSCTL_SYSCALL is not set
174# CONFIG_KALLSYMS is not set
175# CONFIG_HOTPLUG is not set
176CONFIG_PRINTK=y
177CONFIG_BUG=y
178CONFIG_ELF_CORE=y
179CONFIG_BASE_FULL=y
180CONFIG_FUTEX=y
181# CONFIG_EPOLL is not set
182# CONFIG_SIGNALFD is not set
183# CONFIG_TIMERFD is not set
184# CONFIG_EVENTFD is not set
185CONFIG_SHMEM=y
186CONFIG_VM_EVENT_COUNTERS=y
187CONFIG_SLAB=y
188# CONFIG_SLUB is not set
189# CONFIG_SLOB is not set
190CONFIG_RT_MUTEXES=y
191# CONFIG_TINY_SHMEM is not set
192CONFIG_BASE_SMALL=0
193# CONFIG_MODULES is not set
194CONFIG_BLOCK=y
195# CONFIG_LBD is not set
196# CONFIG_BLK_DEV_IO_TRACE is not set
197# CONFIG_LSF is not set
198# CONFIG_BLK_DEV_BSG is not set
199
200#
201# IO Schedulers
202#
203CONFIG_IOSCHED_NOOP=y
204CONFIG_IOSCHED_AS=y
205# CONFIG_IOSCHED_DEADLINE is not set
206# CONFIG_IOSCHED_CFQ is not set
207CONFIG_DEFAULT_AS=y
208# CONFIG_DEFAULT_DEADLINE is not set
209# CONFIG_DEFAULT_CFQ is not set
210# CONFIG_DEFAULT_NOOP is not set
211CONFIG_DEFAULT_IOSCHED="anticipatory"
212
213#
214# Bus options (PCI, PCMCIA, EISA, ISA, TC)
215#
216CONFIG_HW_HAS_PCI=y
217CONFIG_PCI=y
218# CONFIG_ARCH_SUPPORTS_MSI is not set
219CONFIG_MMU=y
220
221#
222# PCCARD (PCMCIA/CardBus) support
223#
224
225#
226# Executable file formats
227#
228CONFIG_BINFMT_ELF=y
229# CONFIG_BINFMT_MISC is not set
230CONFIG_TRAD_SIGNALS=y
231
232#
233# Power management options
234#
235# CONFIG_PM is not set
236
237#
238# Networking
239#
240CONFIG_NET=y
241
242#
243# Networking options
244#
245CONFIG_PACKET=y
246CONFIG_PACKET_MMAP=y
247CONFIG_UNIX=y
248# CONFIG_NET_KEY is not set
249CONFIG_INET=y
250# CONFIG_IP_MULTICAST is not set
251# CONFIG_IP_ADVANCED_ROUTER is not set
252CONFIG_IP_FIB_HASH=y
253# CONFIG_IP_PNP is not set
254# CONFIG_NET_IPIP is not set
255# CONFIG_NET_IPGRE is not set
256# CONFIG_ARPD is not set
257# CONFIG_SYN_COOKIES is not set
258# CONFIG_INET_AH is not set
259# CONFIG_INET_ESP is not set
260# CONFIG_INET_IPCOMP is not set
261# CONFIG_INET_XFRM_TUNNEL is not set
262# CONFIG_INET_TUNNEL is not set
263# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
264# CONFIG_INET_XFRM_MODE_TUNNEL is not set
265# CONFIG_INET_XFRM_MODE_BEET is not set
266# CONFIG_INET_DIAG is not set
267# CONFIG_TCP_CONG_ADVANCED is not set
268CONFIG_TCP_CONG_CUBIC=y
269CONFIG_DEFAULT_TCP_CONG="cubic"
270# CONFIG_TCP_MD5SIG is not set
271# CONFIG_IPV6 is not set
272# CONFIG_INET6_XFRM_TUNNEL is not set
273# CONFIG_INET6_TUNNEL is not set
274# CONFIG_NETWORK_SECMARK is not set
275# CONFIG_NETFILTER is not set
276# CONFIG_IP_DCCP is not set
277# CONFIG_IP_SCTP is not set
278# CONFIG_TIPC is not set
279# CONFIG_ATM is not set
280# CONFIG_BRIDGE is not set
281# CONFIG_VLAN_8021Q is not set
282# CONFIG_DECNET is not set
283# CONFIG_LLC2 is not set
284# CONFIG_IPX is not set
285# CONFIG_ATALK is not set
286# CONFIG_X25 is not set
287# CONFIG_LAPB is not set
288# CONFIG_ECONET is not set
289# CONFIG_WAN_ROUTER is not set
290
291#
292# QoS and/or fair queueing
293#
294# CONFIG_NET_SCHED is not set
295
296#
297# Network testing
298#
299# CONFIG_NET_PKTGEN is not set
300# CONFIG_HAMRADIO is not set
301# CONFIG_IRDA is not set
302# CONFIG_BT is not set
303# CONFIG_AF_RXRPC is not set
304
305#
306# Wireless
307#
308# CONFIG_CFG80211 is not set
309# CONFIG_WIRELESS_EXT is not set
310# CONFIG_MAC80211 is not set
311# CONFIG_IEEE80211 is not set
312# CONFIG_RFKILL is not set
313# CONFIG_NET_9P is not set
314
315#
316# Device Drivers
317#
318
319#
320# Generic Driver Options
321#
322CONFIG_STANDALONE=y
323CONFIG_PREVENT_FIRMWARE_BUILD=y
324# CONFIG_SYS_HYPERVISOR is not set
325# CONFIG_CONNECTOR is not set
326CONFIG_MTD=y
327# CONFIG_MTD_DEBUG is not set
328# CONFIG_MTD_CONCAT is not set
329CONFIG_MTD_PARTITIONS=y
330# CONFIG_MTD_REDBOOT_PARTS is not set
331# CONFIG_MTD_CMDLINE_PARTS is not set
332
333#
334# User Modules And Translation Layers
335#
336CONFIG_MTD_CHAR=y
337CONFIG_MTD_BLKDEVS=y
338CONFIG_MTD_BLOCK=y
339# CONFIG_FTL is not set
340# CONFIG_NFTL is not set
341# CONFIG_INFTL is not set
342# CONFIG_RFD_FTL is not set
343# CONFIG_SSFDC is not set
344
345#
346# RAM/ROM/Flash chip drivers
347#
348CONFIG_MTD_CFI=y
349# CONFIG_MTD_JEDECPROBE is not set
350CONFIG_MTD_GEN_PROBE=y
351# CONFIG_MTD_CFI_ADV_OPTIONS is not set
352CONFIG_MTD_MAP_BANK_WIDTH_1=y
353CONFIG_MTD_MAP_BANK_WIDTH_2=y
354CONFIG_MTD_MAP_BANK_WIDTH_4=y
355# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
356# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
357# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
358CONFIG_MTD_CFI_I1=y
359CONFIG_MTD_CFI_I2=y
360# CONFIG_MTD_CFI_I4 is not set
361# CONFIG_MTD_CFI_I8 is not set
362# CONFIG_MTD_CFI_INTELEXT is not set
363CONFIG_MTD_CFI_AMDSTD=y
364# CONFIG_MTD_CFI_STAA is not set
365CONFIG_MTD_CFI_UTIL=y
366# CONFIG_MTD_RAM is not set
367# CONFIG_MTD_ROM is not set
368# CONFIG_MTD_ABSENT is not set
369
370#
371# Mapping drivers for chip access
372#
373# CONFIG_MTD_COMPLEX_MAPPINGS is not set
374# CONFIG_MTD_PHYSMAP is not set
375CONFIG_MTD_LASAT=y
376# CONFIG_MTD_PLATRAM is not set
377
378#
379# Self-contained MTD device drivers
380#
381# CONFIG_MTD_PMC551 is not set
382# CONFIG_MTD_SLRAM is not set
383# CONFIG_MTD_PHRAM is not set
384# CONFIG_MTD_MTDRAM is not set
385# CONFIG_MTD_BLOCK2MTD is not set
386
387#
388# Disk-On-Chip Device Drivers
389#
390# CONFIG_MTD_DOC2000 is not set
391# CONFIG_MTD_DOC2001 is not set
392# CONFIG_MTD_DOC2001PLUS is not set
393# CONFIG_MTD_NAND is not set
394# CONFIG_MTD_ONENAND is not set
395
396#
397# UBI - Unsorted block images
398#
399# CONFIG_MTD_UBI is not set
400# CONFIG_PARPORT is not set
401CONFIG_BLK_DEV=y
402# CONFIG_BLK_CPQ_DA is not set
403# CONFIG_BLK_CPQ_CISS_DA is not set
404# CONFIG_BLK_DEV_DAC960 is not set
405# CONFIG_BLK_DEV_UMEM is not set
406# CONFIG_BLK_DEV_COW_COMMON is not set
407# CONFIG_BLK_DEV_LOOP is not set
408# CONFIG_BLK_DEV_NBD is not set
409# CONFIG_BLK_DEV_SX8 is not set
410# CONFIG_BLK_DEV_RAM is not set
411# CONFIG_CDROM_PKTCDVD is not set
412# CONFIG_ATA_OVER_ETH is not set
413# CONFIG_MISC_DEVICES is not set
414CONFIG_IDE=y
415CONFIG_IDE_MAX_HWIFS=4
416CONFIG_BLK_DEV_IDE=y
417
418#
419# Please see Documentation/ide.txt for help/info on IDE drives
420#
421# CONFIG_BLK_DEV_IDE_SATA is not set
422CONFIG_BLK_DEV_IDEDISK=y
423CONFIG_IDEDISK_MULTI_MODE=y
424# CONFIG_BLK_DEV_IDECD is not set
425# CONFIG_BLK_DEV_IDETAPE is not set
426# CONFIG_BLK_DEV_IDEFLOPPY is not set
427# CONFIG_IDE_TASK_IOCTL is not set
428CONFIG_IDE_PROC_FS=y
429
430#
431# IDE chipset support/bugfixes
432#
433CONFIG_IDE_GENERIC=y
434CONFIG_BLK_DEV_IDEPCI=y
435# CONFIG_IDEPCI_SHARE_IRQ is not set
436CONFIG_IDEPCI_PCIBUS_ORDER=y
437# CONFIG_BLK_DEV_OFFBOARD is not set
438CONFIG_BLK_DEV_GENERIC=y
439# CONFIG_BLK_DEV_OPTI621 is not set
440CONFIG_BLK_DEV_IDEDMA_PCI=y
441# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
442# CONFIG_IDEDMA_ONLYDISK is not set
443# CONFIG_BLK_DEV_AEC62XX is not set
444# CONFIG_BLK_DEV_ALI15X3 is not set
445# CONFIG_BLK_DEV_AMD74XX is not set
446CONFIG_BLK_DEV_CMD64X=y
447# CONFIG_BLK_DEV_TRIFLEX is not set
448# CONFIG_BLK_DEV_CY82C693 is not set
449# CONFIG_BLK_DEV_CS5520 is not set
450# CONFIG_BLK_DEV_CS5530 is not set
451# CONFIG_BLK_DEV_HPT34X is not set
452# CONFIG_BLK_DEV_HPT366 is not set
453# CONFIG_BLK_DEV_JMICRON is not set
454# CONFIG_BLK_DEV_SC1200 is not set
455# CONFIG_BLK_DEV_PIIX is not set
456# CONFIG_BLK_DEV_IT8213 is not set
457# CONFIG_BLK_DEV_IT821X is not set
458# CONFIG_BLK_DEV_NS87415 is not set
459# CONFIG_BLK_DEV_PDC202XX_OLD is not set
460# CONFIG_BLK_DEV_PDC202XX_NEW is not set
461# CONFIG_BLK_DEV_SVWKS is not set
462# CONFIG_BLK_DEV_SIIMAGE is not set
463# CONFIG_BLK_DEV_SLC90E66 is not set
464# CONFIG_BLK_DEV_TRM290 is not set
465# CONFIG_BLK_DEV_VIA82CXXX is not set
466# CONFIG_BLK_DEV_TC86C001 is not set
467# CONFIG_IDE_ARM is not set
468CONFIG_BLK_DEV_IDEDMA=y
469# CONFIG_IDEDMA_IVB is not set
470# CONFIG_BLK_DEV_HD is not set
471
472#
473# SCSI device support
474#
475# CONFIG_RAID_ATTRS is not set
476# CONFIG_SCSI is not set
477# CONFIG_SCSI_DMA is not set
478# CONFIG_SCSI_NETLINK is not set
479# CONFIG_ATA is not set
480# CONFIG_MD is not set
481
482#
483# Fusion MPT device support
484#
485# CONFIG_FUSION is not set
486
487#
488# IEEE 1394 (FireWire) support
489#
490# CONFIG_FIREWIRE is not set
491# CONFIG_IEEE1394 is not set
492# CONFIG_I2O is not set
493CONFIG_NETDEVICES=y
494# CONFIG_NETDEVICES_MULTIQUEUE is not set
495# CONFIG_DUMMY is not set
496# CONFIG_BONDING is not set
497# CONFIG_MACVLAN is not set
498# CONFIG_EQUALIZER is not set
499# CONFIG_TUN is not set
500# CONFIG_ARCNET is not set
501# CONFIG_PHYLIB is not set
502CONFIG_NET_ETHERNET=y
503CONFIG_MII=y
504# CONFIG_AX88796 is not set
505# CONFIG_HAPPYMEAL is not set
506# CONFIG_SUNGEM is not set
507# CONFIG_CASSINI is not set
508# CONFIG_NET_VENDOR_3COM is not set
509# CONFIG_DM9000 is not set
510# CONFIG_NET_TULIP is not set
511# CONFIG_HP100 is not set
512CONFIG_NET_PCI=y
513CONFIG_PCNET32=y
514# CONFIG_PCNET32_NAPI is not set
515# CONFIG_AMD8111_ETH is not set
516# CONFIG_ADAPTEC_STARFIRE is not set
517# CONFIG_B44 is not set
518# CONFIG_FORCEDETH is not set
519# CONFIG_TC35815 is not set
520# CONFIG_DGRS is not set
521# CONFIG_EEPRO100 is not set
522# CONFIG_E100 is not set
523# CONFIG_FEALNX is not set
524# CONFIG_NATSEMI is not set
525# CONFIG_NE2K_PCI is not set
526# CONFIG_8139CP is not set
527# CONFIG_8139TOO is not set
528# CONFIG_SIS900 is not set
529# CONFIG_EPIC100 is not set
530# CONFIG_SUNDANCE is not set
531# CONFIG_TLAN is not set
532# CONFIG_VIA_RHINE is not set
533# CONFIG_SC92031 is not set
534# CONFIG_NETDEV_1000 is not set
535# CONFIG_NETDEV_10000 is not set
536# CONFIG_TR is not set
537
538#
539# Wireless LAN
540#
541# CONFIG_WLAN_PRE80211 is not set
542# CONFIG_WLAN_80211 is not set
543# CONFIG_WAN is not set
544# CONFIG_FDDI is not set
545# CONFIG_HIPPI is not set
546# CONFIG_PPP is not set
547# CONFIG_SLIP is not set
548# CONFIG_SHAPER is not set
549# CONFIG_NETCONSOLE is not set
550# CONFIG_NETPOLL is not set
551# CONFIG_NET_POLL_CONTROLLER is not set
552# CONFIG_ISDN is not set
553# CONFIG_PHONE is not set
554
555#
556# Input device support
557#
558CONFIG_INPUT=y
559# CONFIG_INPUT_FF_MEMLESS is not set
560# CONFIG_INPUT_POLLDEV is not set
561
562#
563# Userland interfaces
564#
565# CONFIG_INPUT_MOUSEDEV is not set
566# CONFIG_INPUT_JOYDEV is not set
567# CONFIG_INPUT_TSDEV is not set
568# CONFIG_INPUT_EVDEV is not set
569# CONFIG_INPUT_EVBUG is not set
570
571#
572# Input Device Drivers
573#
574# CONFIG_INPUT_KEYBOARD is not set
575# CONFIG_INPUT_MOUSE is not set
576# CONFIG_INPUT_JOYSTICK is not set
577# CONFIG_INPUT_TABLET is not set
578# CONFIG_INPUT_TOUCHSCREEN is not set
579# CONFIG_INPUT_MISC is not set
580
581#
582# Hardware I/O ports
583#
584CONFIG_SERIO=y
585CONFIG_SERIO_I8042=y
586CONFIG_SERIO_SERPORT=y
587# CONFIG_SERIO_PCIPS2 is not set
588# CONFIG_SERIO_LIBPS2 is not set
589CONFIG_SERIO_RAW=y
590# CONFIG_GAMEPORT is not set
591
592#
593# Character devices
594#
595# CONFIG_VT is not set
596# CONFIG_SERIAL_NONSTANDARD is not set
597
598#
599# Serial drivers
600#
601CONFIG_SERIAL_8250=y
602CONFIG_SERIAL_8250_CONSOLE=y
603# CONFIG_SERIAL_8250_PCI is not set
604CONFIG_SERIAL_8250_NR_UARTS=4
605CONFIG_SERIAL_8250_RUNTIME_UARTS=4
606# CONFIG_SERIAL_8250_EXTENDED is not set
607
608#
609# Non-8250 serial port support
610#
611CONFIG_SERIAL_CORE=y
612CONFIG_SERIAL_CORE_CONSOLE=y
613# CONFIG_SERIAL_JSM is not set
614CONFIG_UNIX98_PTYS=y
615CONFIG_LEGACY_PTYS=y
616CONFIG_LEGACY_PTY_COUNT=256
617# CONFIG_IPMI_HANDLER is not set
618# CONFIG_WATCHDOG is not set
619# CONFIG_HW_RANDOM is not set
620# CONFIG_RTC is not set
621# CONFIG_R3964 is not set
622# CONFIG_APPLICOM is not set
623# CONFIG_DRM is not set
624# CONFIG_RAW_DRIVER is not set
625# CONFIG_TCG_TPM is not set
626CONFIG_DEVPORT=y
627# CONFIG_I2C is not set
628
629#
630# SPI support
631#
632# CONFIG_SPI is not set
633# CONFIG_SPI_MASTER is not set
634# CONFIG_W1 is not set
635# CONFIG_POWER_SUPPLY is not set
636# CONFIG_HWMON is not set
637
638#
639# Multifunction device drivers
640#
641# CONFIG_MFD_SM501 is not set
642
643#
644# Multimedia devices
645#
646# CONFIG_VIDEO_DEV is not set
647# CONFIG_DVB_CORE is not set
648# CONFIG_DAB is not set
649
650#
651# Graphics support
652#
653# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
654
655#
656# Display device support
657#
658# CONFIG_DISPLAY_SUPPORT is not set
659# CONFIG_VGASTATE is not set
660# CONFIG_VIDEO_OUTPUT_CONTROL is not set
661# CONFIG_FB is not set
662
663#
664# Sound
665#
666# CONFIG_SOUND is not set
667# CONFIG_HID_SUPPORT is not set
668# CONFIG_USB_SUPPORT is not set
669# CONFIG_MMC is not set
670# CONFIG_NEW_LEDS is not set
671# CONFIG_INFINIBAND is not set
672# CONFIG_RTC_CLASS is not set
673
674#
675# DMA Engine support
676#
677# CONFIG_DMA_ENGINE is not set
678
679#
680# DMA Clients
681#
682
683#
684# DMA Devices
685#
686
687#
688# Userspace I/O
689#
690# CONFIG_UIO is not set
691
692#
693# File systems
694#
695CONFIG_EXT2_FS=y
696# CONFIG_EXT2_FS_XATTR is not set
697# CONFIG_EXT2_FS_XIP is not set
698CONFIG_EXT3_FS=y
699# CONFIG_EXT3_FS_XATTR is not set
700# CONFIG_EXT4DEV_FS is not set
701CONFIG_JBD=y
702# CONFIG_JBD_DEBUG is not set
703# CONFIG_REISERFS_FS is not set
704# CONFIG_JFS_FS is not set
705# CONFIG_FS_POSIX_ACL is not set
706# CONFIG_XFS_FS is not set
707# CONFIG_GFS2_FS is not set
708# CONFIG_OCFS2_FS is not set
709# CONFIG_MINIX_FS is not set
710# CONFIG_ROMFS_FS is not set
711# CONFIG_INOTIFY is not set
712# CONFIG_QUOTA is not set
713# CONFIG_DNOTIFY is not set
714# CONFIG_AUTOFS_FS is not set
715# CONFIG_AUTOFS4_FS is not set
716# CONFIG_FUSE_FS is not set
717
718#
719# CD-ROM/DVD Filesystems
720#
721# CONFIG_ISO9660_FS is not set
722# CONFIG_UDF_FS is not set
723
724#
725# DOS/FAT/NT Filesystems
726#
727# CONFIG_MSDOS_FS is not set
728# CONFIG_VFAT_FS is not set
729# CONFIG_NTFS_FS is not set
730
731#
732# Pseudo filesystems
733#
734CONFIG_PROC_FS=y
735CONFIG_PROC_KCORE=y
736CONFIG_PROC_SYSCTL=y
737CONFIG_SYSFS=y
738CONFIG_TMPFS=y
739# CONFIG_TMPFS_POSIX_ACL is not set
740# CONFIG_HUGETLB_PAGE is not set
741CONFIG_RAMFS=y
742CONFIG_CONFIGFS_FS=y
743
744#
745# Miscellaneous filesystems
746#
747# CONFIG_ADFS_FS is not set
748# CONFIG_AFFS_FS is not set
749# CONFIG_HFS_FS is not set
750# CONFIG_HFSPLUS_FS is not set
751# CONFIG_BEFS_FS is not set
752# CONFIG_BFS_FS is not set
753# CONFIG_EFS_FS is not set
754# CONFIG_JFFS2_FS is not set
755# CONFIG_CRAMFS is not set
756# CONFIG_VXFS_FS is not set
757# CONFIG_HPFS_FS is not set
758# CONFIG_QNX4FS_FS is not set
759# CONFIG_SYSV_FS is not set
760# CONFIG_UFS_FS is not set
761
762#
763# Network File Systems
764#
765# CONFIG_NFS_FS is not set
766# CONFIG_NFSD is not set
767# CONFIG_SMB_FS is not set
768# CONFIG_CIFS is not set
769# CONFIG_NCP_FS is not set
770# CONFIG_CODA_FS is not set
771# CONFIG_AFS_FS is not set
772
773#
774# Partition Types
775#
776# CONFIG_PARTITION_ADVANCED is not set
777CONFIG_MSDOS_PARTITION=y
778
779#
780# Native Language Support
781#
782# CONFIG_NLS is not set
783
784#
785# Distributed Lock Manager
786#
787# CONFIG_DLM is not set
788
789#
790# Profiling support
791#
792# CONFIG_PROFILING is not set
793
794#
795# Kernel hacking
796#
797CONFIG_TRACE_IRQFLAGS_SUPPORT=y
798# CONFIG_PRINTK_TIME is not set
799CONFIG_ENABLE_MUST_CHECK=y
800CONFIG_MAGIC_SYSRQ=y
801# CONFIG_UNUSED_SYMBOLS is not set
802# CONFIG_DEBUG_FS is not set
803# CONFIG_HEADERS_CHECK is not set
804# CONFIG_DEBUG_KERNEL is not set
805CONFIG_CROSSCOMPILE=y
806CONFIG_CMDLINE=""
807
808#
809# Security options
810#
811# CONFIG_KEYS is not set
812# CONFIG_SECURITY is not set
813# CONFIG_CRYPTO is not set
814
815#
816# Library routines
817#
818CONFIG_BITREVERSE=y
819# CONFIG_CRC_CCITT is not set
820# CONFIG_CRC16 is not set
821# CONFIG_CRC_ITU_T is not set
822CONFIG_CRC32=y
823# CONFIG_CRC7 is not set
824# CONFIG_LIBCRC32C is not set
825CONFIG_PLIST=y
826CONFIG_HAS_IOMEM=y
827CONFIG_HAS_IOPORT=y
828CONFIG_HAS_DMA=y
diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig
new file mode 100644
index 000000000000..0280ef389d8d
--- /dev/null
+++ b/arch/mips/configs/mtx1_defconfig
@@ -0,0 +1,3115 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.23-rc8
4# Sun Sep 30 12:56:10 2007
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11CONFIG_MACH_ALCHEMY=y
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_MIPS_COBALT is not set
14# CONFIG_MACH_DECSTATION is not set
15# CONFIG_MACH_JAZZ is not set
16# CONFIG_LEMOTE_FULONG is not set
17# CONFIG_MIPS_ATLAS is not set
18# CONFIG_MIPS_MALTA is not set
19# CONFIG_MIPS_SEAD is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_MARKEINS is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_PNX8550_JBS is not set
24# CONFIG_PNX8550_STB810 is not set
25# CONFIG_PMC_MSP is not set
26# CONFIG_PMC_YOSEMITE is not set
27# CONFIG_QEMU is not set
28# CONFIG_SGI_IP22 is not set
29# CONFIG_SGI_IP27 is not set
30# CONFIG_SGI_IP32 is not set
31# CONFIG_SIBYTE_CRHINE is not set
32# CONFIG_SIBYTE_CARMEL is not set
33# CONFIG_SIBYTE_CRHONE is not set
34# CONFIG_SIBYTE_RHONE is not set
35# CONFIG_SIBYTE_SWARM is not set
36# CONFIG_SIBYTE_LITTLESUR is not set
37# CONFIG_SIBYTE_SENTOSA is not set
38# CONFIG_SIBYTE_PTSWARM is not set
39# CONFIG_SIBYTE_BIGSUR is not set
40# CONFIG_SNI_RM is not set
41# CONFIG_TOSHIBA_JMR3927 is not set
42# CONFIG_TOSHIBA_RBTX4927 is not set
43# CONFIG_TOSHIBA_RBTX4938 is not set
44# CONFIG_WR_PPMC is not set
45CONFIG_MIPS_MTX1=y
46# CONFIG_MIPS_BOSPORUS is not set
47# CONFIG_MIPS_DB1000 is not set
48# CONFIG_MIPS_DB1100 is not set
49# CONFIG_MIPS_DB1200 is not set
50# CONFIG_MIPS_DB1500 is not set
51# CONFIG_MIPS_DB1550 is not set
52# CONFIG_MIPS_MIRAGE is not set
53# CONFIG_MIPS_PB1000 is not set
54# CONFIG_MIPS_PB1100 is not set
55# CONFIG_MIPS_PB1200 is not set
56# CONFIG_MIPS_PB1500 is not set
57# CONFIG_MIPS_PB1550 is not set
58# CONFIG_MIPS_XXS1500 is not set
59CONFIG_SOC_AU1500=y
60CONFIG_SOC_AU1X00=y
61CONFIG_RWSEM_GENERIC_SPINLOCK=y
62# CONFIG_ARCH_HAS_ILOG2_U32 is not set
63# CONFIG_ARCH_HAS_ILOG2_U64 is not set
64CONFIG_GENERIC_FIND_NEXT_BIT=y
65CONFIG_GENERIC_HWEIGHT=y
66CONFIG_GENERIC_CALIBRATE_DELAY=y
67CONFIG_GENERIC_TIME=y
68CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
69# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
70CONFIG_DMA_NONCOHERENT=y
71CONFIG_DMA_NEED_PCI_MAP_STATE=y
72# CONFIG_HOTPLUG_CPU is not set
73# CONFIG_NO_IOPORT is not set
74# CONFIG_CPU_BIG_ENDIAN is not set
75CONFIG_CPU_LITTLE_ENDIAN=y
76CONFIG_SYS_SUPPORTS_APM_EMULATION=y
77CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
78CONFIG_MIPS_L1_CACHE_SHIFT=5
79
80#
81# CPU selection
82#
83# CONFIG_CPU_LOONGSON2 is not set
84CONFIG_CPU_MIPS32_R1=y
85# CONFIG_CPU_MIPS32_R2 is not set
86# CONFIG_CPU_MIPS64_R1 is not set
87# CONFIG_CPU_MIPS64_R2 is not set
88# CONFIG_CPU_R3000 is not set
89# CONFIG_CPU_TX39XX is not set
90# CONFIG_CPU_VR41XX is not set
91# CONFIG_CPU_R4300 is not set
92# CONFIG_CPU_R4X00 is not set
93# CONFIG_CPU_TX49XX is not set
94# CONFIG_CPU_R5000 is not set
95# CONFIG_CPU_R5432 is not set
96# CONFIG_CPU_R6000 is not set
97# CONFIG_CPU_NEVADA is not set
98# CONFIG_CPU_R8000 is not set
99# CONFIG_CPU_R10000 is not set
100# CONFIG_CPU_RM7000 is not set
101# CONFIG_CPU_RM9000 is not set
102# CONFIG_CPU_SB1 is not set
103CONFIG_SYS_HAS_CPU_MIPS32_R1=y
104CONFIG_CPU_MIPS32=y
105CONFIG_CPU_MIPSR1=y
106CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
107CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
108
109#
110# Kernel type
111#
112CONFIG_32BIT=y
113# CONFIG_64BIT is not set
114CONFIG_PAGE_SIZE_4KB=y
115# CONFIG_PAGE_SIZE_8KB is not set
116# CONFIG_PAGE_SIZE_16KB is not set
117# CONFIG_PAGE_SIZE_64KB is not set
118CONFIG_CPU_HAS_PREFETCH=y
119CONFIG_MIPS_MT_DISABLED=y
120# CONFIG_MIPS_MT_SMP is not set
121# CONFIG_MIPS_MT_SMTC is not set
122CONFIG_64BIT_PHYS_ADDR=y
123CONFIG_CPU_HAS_LLSC=y
124CONFIG_CPU_HAS_SYNC=y
125CONFIG_GENERIC_HARDIRQS=y
126CONFIG_GENERIC_IRQ_PROBE=y
127CONFIG_CPU_SUPPORTS_HIGHMEM=y
128CONFIG_ARCH_FLATMEM_ENABLE=y
129CONFIG_SELECT_MEMORY_MODEL=y
130CONFIG_FLATMEM_MANUAL=y
131# CONFIG_DISCONTIGMEM_MANUAL is not set
132# CONFIG_SPARSEMEM_MANUAL is not set
133CONFIG_FLATMEM=y
134CONFIG_FLAT_NODE_MEM_MAP=y
135# CONFIG_SPARSEMEM_STATIC is not set
136CONFIG_SPLIT_PTLOCK_CPUS=4
137CONFIG_RESOURCES_64BIT=y
138CONFIG_ZONE_DMA_FLAG=0
139CONFIG_VIRT_TO_BUS=y
140# CONFIG_HZ_48 is not set
141# CONFIG_HZ_100 is not set
142# CONFIG_HZ_128 is not set
143CONFIG_HZ_250=y
144# CONFIG_HZ_256 is not set
145# CONFIG_HZ_1000 is not set
146# CONFIG_HZ_1024 is not set
147CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
148CONFIG_HZ=250
149# CONFIG_PREEMPT_NONE is not set
150CONFIG_PREEMPT_VOLUNTARY=y
151# CONFIG_PREEMPT is not set
152# CONFIG_KEXEC is not set
153CONFIG_SECCOMP=y
154CONFIG_LOCKDEP_SUPPORT=y
155CONFIG_STACKTRACE_SUPPORT=y
156CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
157
158#
159# General setup
160#
161CONFIG_EXPERIMENTAL=y
162CONFIG_BROKEN_ON_SMP=y
163CONFIG_INIT_ENV_ARG_LIMIT=32
164CONFIG_LOCALVERSION=""
165# CONFIG_LOCALVERSION_AUTO is not set
166CONFIG_SWAP=y
167CONFIG_SYSVIPC=y
168CONFIG_SYSVIPC_SYSCTL=y
169CONFIG_POSIX_MQUEUE=y
170CONFIG_BSD_PROCESS_ACCT=y
171CONFIG_BSD_PROCESS_ACCT_V3=y
172# CONFIG_TASKSTATS is not set
173# CONFIG_USER_NS is not set
174CONFIG_AUDIT=y
175# CONFIG_IKCONFIG is not set
176CONFIG_LOG_BUF_SHIFT=17
177CONFIG_SYSFS_DEPRECATED=y
178CONFIG_RELAY=y
179CONFIG_BLK_DEV_INITRD=y
180CONFIG_INITRAMFS_SOURCE=""
181# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
182CONFIG_SYSCTL=y
183CONFIG_EMBEDDED=y
184CONFIG_SYSCTL_SYSCALL=y
185CONFIG_KALLSYMS=y
186# CONFIG_KALLSYMS_EXTRA_PASS is not set
187CONFIG_HOTPLUG=y
188CONFIG_PRINTK=y
189CONFIG_BUG=y
190CONFIG_ELF_CORE=y
191CONFIG_BASE_FULL=y
192CONFIG_FUTEX=y
193CONFIG_ANON_INODES=y
194CONFIG_EPOLL=y
195CONFIG_SIGNALFD=y
196CONFIG_EVENTFD=y
197CONFIG_SHMEM=y
198CONFIG_VM_EVENT_COUNTERS=y
199CONFIG_SLAB=y
200# CONFIG_SLUB is not set
201# CONFIG_SLOB is not set
202CONFIG_RT_MUTEXES=y
203# CONFIG_TINY_SHMEM is not set
204CONFIG_BASE_SMALL=0
205CONFIG_MODULES=y
206CONFIG_MODULE_UNLOAD=y
207# CONFIG_MODULE_FORCE_UNLOAD is not set
208CONFIG_MODVERSIONS=y
209CONFIG_MODULE_SRCVERSION_ALL=y
210CONFIG_KMOD=y
211CONFIG_BLOCK=y
212CONFIG_LBD=y
213# CONFIG_BLK_DEV_IO_TRACE is not set
214# CONFIG_LSF is not set
215# CONFIG_BLK_DEV_BSG is not set
216
217#
218# IO Schedulers
219#
220CONFIG_IOSCHED_NOOP=y
221CONFIG_IOSCHED_AS=y
222CONFIG_IOSCHED_DEADLINE=y
223CONFIG_IOSCHED_CFQ=y
224# CONFIG_DEFAULT_AS is not set
225# CONFIG_DEFAULT_DEADLINE is not set
226CONFIG_DEFAULT_CFQ=y
227# CONFIG_DEFAULT_NOOP is not set
228CONFIG_DEFAULT_IOSCHED="cfq"
229
230#
231# Bus options (PCI, PCMCIA, EISA, ISA, TC)
232#
233CONFIG_HW_HAS_PCI=y
234CONFIG_PCI=y
235# CONFIG_ARCH_SUPPORTS_MSI is not set
236CONFIG_MMU=y
237
238#
239# PCCARD (PCMCIA/CardBus) support
240#
241CONFIG_PCCARD=m
242# CONFIG_PCMCIA_DEBUG is not set
243CONFIG_PCMCIA=m
244CONFIG_PCMCIA_LOAD_CIS=y
245CONFIG_PCMCIA_IOCTL=y
246CONFIG_CARDBUS=y
247
248#
249# PC-card bridges
250#
251CONFIG_YENTA=m
252CONFIG_YENTA_O2=y
253CONFIG_YENTA_RICOH=y
254CONFIG_YENTA_TI=y
255CONFIG_YENTA_ENE_TUNE=y
256CONFIG_YENTA_TOSHIBA=y
257CONFIG_PD6729=m
258CONFIG_I82092=m
259# CONFIG_PCMCIA_AU1X00 is not set
260CONFIG_PCCARD_NONSTATIC=m
261# CONFIG_HOTPLUG_PCI is not set
262
263#
264# Executable file formats
265#
266CONFIG_BINFMT_ELF=y
267CONFIG_BINFMT_MISC=m
268CONFIG_TRAD_SIGNALS=y
269
270#
271# Power management options
272#
273CONFIG_PM=y
274# CONFIG_PM_LEGACY is not set
275# CONFIG_PM_DEBUG is not set
276CONFIG_PM_SLEEP=y
277CONFIG_SUSPEND_UP_POSSIBLE=y
278CONFIG_SUSPEND=y
279# CONFIG_APM_EMULATION is not set
280
281#
282# Networking
283#
284CONFIG_NET=y
285
286#
287# Networking options
288#
289CONFIG_PACKET=m
290CONFIG_PACKET_MMAP=y
291CONFIG_UNIX=y
292CONFIG_XFRM=y
293CONFIG_XFRM_USER=m
294# CONFIG_XFRM_SUB_POLICY is not set
295# CONFIG_XFRM_MIGRATE is not set
296CONFIG_NET_KEY=m
297# CONFIG_NET_KEY_MIGRATE is not set
298CONFIG_INET=y
299CONFIG_IP_MULTICAST=y
300CONFIG_IP_ADVANCED_ROUTER=y
301CONFIG_ASK_IP_FIB_HASH=y
302# CONFIG_IP_FIB_TRIE is not set
303CONFIG_IP_FIB_HASH=y
304CONFIG_IP_MULTIPLE_TABLES=y
305CONFIG_IP_ROUTE_MULTIPATH=y
306CONFIG_IP_ROUTE_VERBOSE=y
307# CONFIG_IP_PNP is not set
308CONFIG_NET_IPIP=m
309CONFIG_NET_IPGRE=m
310CONFIG_NET_IPGRE_BROADCAST=y
311CONFIG_IP_MROUTE=y
312CONFIG_IP_PIMSM_V1=y
313CONFIG_IP_PIMSM_V2=y
314# CONFIG_ARPD is not set
315CONFIG_SYN_COOKIES=y
316CONFIG_INET_AH=m
317CONFIG_INET_ESP=m
318CONFIG_INET_IPCOMP=m
319CONFIG_INET_XFRM_TUNNEL=m
320CONFIG_INET_TUNNEL=m
321CONFIG_INET_XFRM_MODE_TRANSPORT=m
322CONFIG_INET_XFRM_MODE_TUNNEL=m
323CONFIG_INET_XFRM_MODE_BEET=m
324CONFIG_INET_DIAG=y
325CONFIG_INET_TCP_DIAG=y
326# CONFIG_TCP_CONG_ADVANCED is not set
327CONFIG_TCP_CONG_CUBIC=y
328CONFIG_DEFAULT_TCP_CONG="cubic"
329# CONFIG_TCP_MD5SIG is not set
330CONFIG_IP_VS=m
331# CONFIG_IP_VS_DEBUG is not set
332CONFIG_IP_VS_TAB_BITS=12
333
334#
335# IPVS transport protocol load balancing support
336#
337CONFIG_IP_VS_PROTO_TCP=y
338CONFIG_IP_VS_PROTO_UDP=y
339CONFIG_IP_VS_PROTO_ESP=y
340CONFIG_IP_VS_PROTO_AH=y
341
342#
343# IPVS scheduler
344#
345CONFIG_IP_VS_RR=m
346CONFIG_IP_VS_WRR=m
347CONFIG_IP_VS_LC=m
348CONFIG_IP_VS_WLC=m
349CONFIG_IP_VS_LBLC=m
350CONFIG_IP_VS_LBLCR=m
351CONFIG_IP_VS_DH=m
352CONFIG_IP_VS_SH=m
353CONFIG_IP_VS_SED=m
354CONFIG_IP_VS_NQ=m
355
356#
357# IPVS application helper
358#
359CONFIG_IP_VS_FTP=m
360CONFIG_IPV6=m
361CONFIG_IPV6_PRIVACY=y
362# CONFIG_IPV6_ROUTER_PREF is not set
363# CONFIG_IPV6_OPTIMISTIC_DAD is not set
364CONFIG_INET6_AH=m
365CONFIG_INET6_ESP=m
366CONFIG_INET6_IPCOMP=m
367# CONFIG_IPV6_MIP6 is not set
368CONFIG_INET6_XFRM_TUNNEL=m
369CONFIG_INET6_TUNNEL=m
370CONFIG_INET6_XFRM_MODE_TRANSPORT=m
371CONFIG_INET6_XFRM_MODE_TUNNEL=m
372CONFIG_INET6_XFRM_MODE_BEET=m
373CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
374CONFIG_IPV6_SIT=m
375CONFIG_IPV6_TUNNEL=m
376# CONFIG_IPV6_MULTIPLE_TABLES is not set
377# CONFIG_NETLABEL is not set
378CONFIG_NETWORK_SECMARK=y
379CONFIG_NETFILTER=y
380# CONFIG_NETFILTER_DEBUG is not set
381CONFIG_BRIDGE_NETFILTER=y
382
383#
384# Core Netfilter Configuration
385#
386CONFIG_NETFILTER_NETLINK=m
387CONFIG_NETFILTER_NETLINK_QUEUE=m
388CONFIG_NETFILTER_NETLINK_LOG=m
389# CONFIG_NF_CONNTRACK_ENABLED is not set
390# CONFIG_NF_CONNTRACK is not set
391CONFIG_NETFILTER_XTABLES=m
392CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
393CONFIG_NETFILTER_XT_TARGET_DSCP=m
394CONFIG_NETFILTER_XT_TARGET_MARK=m
395CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
396# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
397# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
398CONFIG_NETFILTER_XT_TARGET_SECMARK=m
399# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
400CONFIG_NETFILTER_XT_MATCH_COMMENT=m
401CONFIG_NETFILTER_XT_MATCH_DCCP=m
402CONFIG_NETFILTER_XT_MATCH_DSCP=m
403CONFIG_NETFILTER_XT_MATCH_ESP=m
404CONFIG_NETFILTER_XT_MATCH_LENGTH=m
405CONFIG_NETFILTER_XT_MATCH_LIMIT=m
406CONFIG_NETFILTER_XT_MATCH_MAC=m
407CONFIG_NETFILTER_XT_MATCH_MARK=m
408CONFIG_NETFILTER_XT_MATCH_POLICY=m
409CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
410CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
411CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
412CONFIG_NETFILTER_XT_MATCH_QUOTA=m
413CONFIG_NETFILTER_XT_MATCH_REALM=m
414CONFIG_NETFILTER_XT_MATCH_SCTP=m
415CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
416CONFIG_NETFILTER_XT_MATCH_STRING=m
417CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
418# CONFIG_NETFILTER_XT_MATCH_U32 is not set
419# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
420
421#
422# IP: Netfilter Configuration
423#
424CONFIG_IP_NF_QUEUE=m
425CONFIG_IP_NF_IPTABLES=m
426CONFIG_IP_NF_MATCH_IPRANGE=m
427CONFIG_IP_NF_MATCH_TOS=m
428CONFIG_IP_NF_MATCH_RECENT=m
429CONFIG_IP_NF_MATCH_ECN=m
430CONFIG_IP_NF_MATCH_AH=m
431CONFIG_IP_NF_MATCH_TTL=m
432CONFIG_IP_NF_MATCH_OWNER=m
433CONFIG_IP_NF_MATCH_ADDRTYPE=m
434CONFIG_IP_NF_FILTER=m
435CONFIG_IP_NF_TARGET_REJECT=m
436CONFIG_IP_NF_TARGET_LOG=m
437CONFIG_IP_NF_TARGET_ULOG=m
438CONFIG_IP_NF_MANGLE=m
439CONFIG_IP_NF_TARGET_TOS=m
440CONFIG_IP_NF_TARGET_ECN=m
441CONFIG_IP_NF_TARGET_TTL=m
442CONFIG_IP_NF_RAW=m
443CONFIG_IP_NF_ARPTABLES=m
444CONFIG_IP_NF_ARPFILTER=m
445CONFIG_IP_NF_ARP_MANGLE=m
446
447#
448# IPv6: Netfilter Configuration (EXPERIMENTAL)
449#
450CONFIG_IP6_NF_QUEUE=m
451CONFIG_IP6_NF_IPTABLES=m
452CONFIG_IP6_NF_MATCH_RT=m
453CONFIG_IP6_NF_MATCH_OPTS=m
454CONFIG_IP6_NF_MATCH_FRAG=m
455CONFIG_IP6_NF_MATCH_HL=m
456CONFIG_IP6_NF_MATCH_OWNER=m
457CONFIG_IP6_NF_MATCH_IPV6HEADER=m
458CONFIG_IP6_NF_MATCH_AH=m
459# CONFIG_IP6_NF_MATCH_MH is not set
460CONFIG_IP6_NF_MATCH_EUI64=m
461CONFIG_IP6_NF_FILTER=m
462CONFIG_IP6_NF_TARGET_LOG=m
463CONFIG_IP6_NF_TARGET_REJECT=m
464CONFIG_IP6_NF_MANGLE=m
465CONFIG_IP6_NF_TARGET_HL=m
466CONFIG_IP6_NF_RAW=m
467
468#
469# DECnet: Netfilter Configuration
470#
471CONFIG_DECNET_NF_GRABULATOR=m
472
473#
474# Bridge: Netfilter Configuration
475#
476CONFIG_BRIDGE_NF_EBTABLES=m
477CONFIG_BRIDGE_EBT_BROUTE=m
478CONFIG_BRIDGE_EBT_T_FILTER=m
479CONFIG_BRIDGE_EBT_T_NAT=m
480CONFIG_BRIDGE_EBT_802_3=m
481CONFIG_BRIDGE_EBT_AMONG=m
482CONFIG_BRIDGE_EBT_ARP=m
483CONFIG_BRIDGE_EBT_IP=m
484CONFIG_BRIDGE_EBT_LIMIT=m
485CONFIG_BRIDGE_EBT_MARK=m
486CONFIG_BRIDGE_EBT_PKTTYPE=m
487CONFIG_BRIDGE_EBT_STP=m
488CONFIG_BRIDGE_EBT_VLAN=m
489CONFIG_BRIDGE_EBT_ARPREPLY=m
490CONFIG_BRIDGE_EBT_DNAT=m
491CONFIG_BRIDGE_EBT_MARK_T=m
492CONFIG_BRIDGE_EBT_REDIRECT=m
493CONFIG_BRIDGE_EBT_SNAT=m
494CONFIG_BRIDGE_EBT_LOG=m
495CONFIG_BRIDGE_EBT_ULOG=m
496CONFIG_IP_DCCP=m
497CONFIG_INET_DCCP_DIAG=m
498CONFIG_IP_DCCP_ACKVEC=y
499
500#
501# DCCP CCIDs Configuration (EXPERIMENTAL)
502#
503CONFIG_IP_DCCP_CCID2=m
504# CONFIG_IP_DCCP_CCID2_DEBUG is not set
505CONFIG_IP_DCCP_CCID3=m
506CONFIG_IP_DCCP_TFRC_LIB=m
507# CONFIG_IP_DCCP_CCID3_DEBUG is not set
508CONFIG_IP_DCCP_CCID3_RTO=100
509CONFIG_IP_SCTP=m
510# CONFIG_SCTP_DBG_MSG is not set
511# CONFIG_SCTP_DBG_OBJCNT is not set
512# CONFIG_SCTP_HMAC_NONE is not set
513# CONFIG_SCTP_HMAC_SHA1 is not set
514CONFIG_SCTP_HMAC_MD5=y
515CONFIG_TIPC=m
516# CONFIG_TIPC_ADVANCED is not set
517# CONFIG_TIPC_DEBUG is not set
518CONFIG_ATM=y
519CONFIG_ATM_CLIP=y
520# CONFIG_ATM_CLIP_NO_ICMP is not set
521CONFIG_ATM_LANE=m
522CONFIG_ATM_MPOA=m
523CONFIG_ATM_BR2684=m
524# CONFIG_ATM_BR2684_IPFILTER is not set
525CONFIG_BRIDGE=m
526CONFIG_VLAN_8021Q=m
527CONFIG_DECNET=m
528# CONFIG_DECNET_ROUTER is not set
529CONFIG_LLC=y
530CONFIG_LLC2=m
531CONFIG_IPX=m
532# CONFIG_IPX_INTERN is not set
533CONFIG_ATALK=m
534CONFIG_DEV_APPLETALK=m
535CONFIG_IPDDP=m
536CONFIG_IPDDP_ENCAP=y
537CONFIG_IPDDP_DECAP=y
538CONFIG_X25=m
539CONFIG_LAPB=m
540CONFIG_ECONET=m
541CONFIG_ECONET_AUNUDP=y
542CONFIG_ECONET_NATIVE=y
543CONFIG_WAN_ROUTER=m
544
545#
546# QoS and/or fair queueing
547#
548CONFIG_NET_SCHED=y
549CONFIG_NET_SCH_FIFO=y
550
551#
552# Queueing/Scheduling
553#
554CONFIG_NET_SCH_CBQ=m
555CONFIG_NET_SCH_HTB=m
556CONFIG_NET_SCH_HFSC=m
557CONFIG_NET_SCH_ATM=m
558CONFIG_NET_SCH_PRIO=m
559# CONFIG_NET_SCH_RR is not set
560CONFIG_NET_SCH_RED=m
561CONFIG_NET_SCH_SFQ=m
562CONFIG_NET_SCH_TEQL=m
563CONFIG_NET_SCH_TBF=m
564CONFIG_NET_SCH_GRED=m
565CONFIG_NET_SCH_DSMARK=m
566CONFIG_NET_SCH_NETEM=m
567CONFIG_NET_SCH_INGRESS=m
568
569#
570# Classification
571#
572CONFIG_NET_CLS=y
573CONFIG_NET_CLS_BASIC=m
574CONFIG_NET_CLS_TCINDEX=m
575CONFIG_NET_CLS_ROUTE4=m
576CONFIG_NET_CLS_ROUTE=y
577CONFIG_NET_CLS_FW=m
578CONFIG_NET_CLS_U32=m
579# CONFIG_CLS_U32_PERF is not set
580CONFIG_CLS_U32_MARK=y
581CONFIG_NET_CLS_RSVP=m
582CONFIG_NET_CLS_RSVP6=m
583CONFIG_NET_EMATCH=y
584CONFIG_NET_EMATCH_STACK=32
585CONFIG_NET_EMATCH_CMP=m
586CONFIG_NET_EMATCH_NBYTE=m
587CONFIG_NET_EMATCH_U32=m
588CONFIG_NET_EMATCH_META=m
589CONFIG_NET_EMATCH_TEXT=m
590CONFIG_NET_CLS_ACT=y
591CONFIG_NET_ACT_POLICE=y
592# CONFIG_NET_ACT_GACT is not set
593# CONFIG_NET_ACT_MIRRED is not set
594# CONFIG_NET_ACT_IPT is not set
595# CONFIG_NET_ACT_PEDIT is not set
596# CONFIG_NET_ACT_SIMP is not set
597CONFIG_NET_CLS_POLICE=y
598# CONFIG_NET_CLS_IND is not set
599
600#
601# Network testing
602#
603CONFIG_NET_PKTGEN=m
604CONFIG_HAMRADIO=y
605
606#
607# Packet Radio protocols
608#
609CONFIG_AX25=m
610# CONFIG_AX25_DAMA_SLAVE is not set
611CONFIG_NETROM=m
612CONFIG_ROSE=m
613
614#
615# AX.25 network device drivers
616#
617CONFIG_MKISS=m
618CONFIG_6PACK=m
619CONFIG_BPQETHER=m
620CONFIG_BAYCOM_SER_FDX=m
621CONFIG_BAYCOM_SER_HDX=m
622CONFIG_BAYCOM_PAR=m
623CONFIG_BAYCOM_EPP=m
624CONFIG_YAM=m
625CONFIG_IRDA=m
626
627#
628# IrDA protocols
629#
630CONFIG_IRLAN=m
631CONFIG_IRNET=m
632CONFIG_IRCOMM=m
633CONFIG_IRDA_ULTRA=y
634
635#
636# IrDA options
637#
638CONFIG_IRDA_CACHE_LAST_LSAP=y
639CONFIG_IRDA_FAST_RR=y
640CONFIG_IRDA_DEBUG=y
641
642#
643# Infrared-port device drivers
644#
645
646#
647# SIR device drivers
648#
649CONFIG_IRTTY_SIR=m
650
651#
652# Dongle support
653#
654CONFIG_DONGLE=y
655CONFIG_ESI_DONGLE=m
656CONFIG_ACTISYS_DONGLE=m
657CONFIG_TEKRAM_DONGLE=m
658# CONFIG_TOIM3232_DONGLE is not set
659CONFIG_LITELINK_DONGLE=m
660CONFIG_MA600_DONGLE=m
661CONFIG_GIRBIL_DONGLE=m
662CONFIG_MCP2120_DONGLE=m
663CONFIG_OLD_BELKIN_DONGLE=m
664CONFIG_ACT200L_DONGLE=m
665# CONFIG_KINGSUN_DONGLE is not set
666
667#
668# Old SIR device drivers
669#
670# CONFIG_IRPORT_SIR is not set
671
672#
673# Old Serial dongle support
674#
675
676#
677# FIR device drivers
678#
679CONFIG_USB_IRDA=m
680CONFIG_SIGMATEL_FIR=m
681CONFIG_TOSHIBA_FIR=m
682CONFIG_VLSI_FIR=m
683CONFIG_MCS_FIR=m
684CONFIG_BT=m
685CONFIG_BT_L2CAP=m
686CONFIG_BT_SCO=m
687CONFIG_BT_RFCOMM=m
688CONFIG_BT_RFCOMM_TTY=y
689CONFIG_BT_BNEP=m
690CONFIG_BT_BNEP_MC_FILTER=y
691CONFIG_BT_BNEP_PROTO_FILTER=y
692CONFIG_BT_CMTP=m
693CONFIG_BT_HIDP=m
694
695#
696# Bluetooth device drivers
697#
698CONFIG_BT_HCIUSB=m
699CONFIG_BT_HCIUSB_SCO=y
700CONFIG_BT_HCIUART=m
701CONFIG_BT_HCIUART_H4=y
702CONFIG_BT_HCIUART_BCSP=y
703CONFIG_BT_HCIBCM203X=m
704CONFIG_BT_HCIBPA10X=m
705CONFIG_BT_HCIBFUSB=m
706CONFIG_BT_HCIDTL1=m
707CONFIG_BT_HCIBT3C=m
708CONFIG_BT_HCIBLUECARD=m
709CONFIG_BT_HCIBTUART=m
710CONFIG_BT_HCIVHCI=m
711CONFIG_AF_RXRPC=m
712# CONFIG_AF_RXRPC_DEBUG is not set
713# CONFIG_RXKAD is not set
714CONFIG_FIB_RULES=y
715
716#
717# Wireless
718#
719# CONFIG_CFG80211 is not set
720CONFIG_WIRELESS_EXT=y
721# CONFIG_MAC80211 is not set
722CONFIG_IEEE80211=m
723# CONFIG_IEEE80211_DEBUG is not set
724CONFIG_IEEE80211_CRYPT_WEP=m
725CONFIG_IEEE80211_CRYPT_CCMP=m
726CONFIG_IEEE80211_CRYPT_TKIP=m
727CONFIG_IEEE80211_SOFTMAC=m
728# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
729# CONFIG_RFKILL is not set
730# CONFIG_NET_9P is not set
731
732#
733# Device Drivers
734#
735
736#
737# Generic Driver Options
738#
739CONFIG_STANDALONE=y
740CONFIG_PREVENT_FIRMWARE_BUILD=y
741CONFIG_FW_LOADER=y
742# CONFIG_SYS_HYPERVISOR is not set
743CONFIG_CONNECTOR=m
744CONFIG_MTD=m
745# CONFIG_MTD_DEBUG is not set
746CONFIG_MTD_CONCAT=m
747CONFIG_MTD_PARTITIONS=y
748CONFIG_MTD_REDBOOT_PARTS=m
749CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
750# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
751# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
752
753#
754# User Modules And Translation Layers
755#
756CONFIG_MTD_CHAR=m
757CONFIG_MTD_BLKDEVS=m
758CONFIG_MTD_BLOCK=m
759CONFIG_MTD_BLOCK_RO=m
760CONFIG_FTL=m
761CONFIG_NFTL=m
762CONFIG_NFTL_RW=y
763CONFIG_INFTL=m
764CONFIG_RFD_FTL=m
765CONFIG_SSFDC=m
766
767#
768# RAM/ROM/Flash chip drivers
769#
770CONFIG_MTD_CFI=m
771CONFIG_MTD_JEDECPROBE=m
772CONFIG_MTD_GEN_PROBE=m
773# CONFIG_MTD_CFI_ADV_OPTIONS is not set
774CONFIG_MTD_MAP_BANK_WIDTH_1=y
775CONFIG_MTD_MAP_BANK_WIDTH_2=y
776CONFIG_MTD_MAP_BANK_WIDTH_4=y
777# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
778# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
779# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
780CONFIG_MTD_CFI_I1=y
781CONFIG_MTD_CFI_I2=y
782# CONFIG_MTD_CFI_I4 is not set
783# CONFIG_MTD_CFI_I8 is not set
784CONFIG_MTD_CFI_INTELEXT=m
785CONFIG_MTD_CFI_AMDSTD=m
786CONFIG_MTD_CFI_STAA=m
787CONFIG_MTD_CFI_UTIL=m
788CONFIG_MTD_RAM=m
789CONFIG_MTD_ROM=m
790CONFIG_MTD_ABSENT=m
791
792#
793# Mapping drivers for chip access
794#
795CONFIG_MTD_COMPLEX_MAPPINGS=y
796CONFIG_MTD_PHYSMAP=m
797CONFIG_MTD_PHYSMAP_START=0x8000000
798CONFIG_MTD_PHYSMAP_LEN=0x4000000
799CONFIG_MTD_PHYSMAP_BANKWIDTH=2
800# CONFIG_MTD_ALCHEMY is not set
801# CONFIG_MTD_MTX1 is not set
802CONFIG_MTD_PCI=m
803CONFIG_MTD_PLATRAM=m
804
805#
806# Self-contained MTD device drivers
807#
808CONFIG_MTD_PMC551=m
809# CONFIG_MTD_PMC551_BUGFIX is not set
810# CONFIG_MTD_PMC551_DEBUG is not set
811CONFIG_MTD_DATAFLASH=m
812CONFIG_MTD_M25P80=m
813CONFIG_MTD_SLRAM=m
814CONFIG_MTD_PHRAM=m
815CONFIG_MTD_MTDRAM=m
816CONFIG_MTDRAM_TOTAL_SIZE=4096
817CONFIG_MTDRAM_ERASE_SIZE=128
818CONFIG_MTD_BLOCK2MTD=m
819
820#
821# Disk-On-Chip Device Drivers
822#
823CONFIG_MTD_DOC2000=m
824CONFIG_MTD_DOC2001=m
825CONFIG_MTD_DOC2001PLUS=m
826CONFIG_MTD_DOCPROBE=m
827CONFIG_MTD_DOCECC=m
828# CONFIG_MTD_DOCPROBE_ADVANCED is not set
829CONFIG_MTD_DOCPROBE_ADDRESS=0
830CONFIG_MTD_NAND=m
831# CONFIG_MTD_NAND_VERIFY_WRITE is not set
832# CONFIG_MTD_NAND_ECC_SMC is not set
833# CONFIG_MTD_NAND_MUSEUM_IDS is not set
834CONFIG_MTD_NAND_IDS=m
835CONFIG_MTD_NAND_DISKONCHIP=m
836# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
837CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
838# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
839# CONFIG_MTD_NAND_CAFE is not set
840CONFIG_MTD_NAND_NANDSIM=m
841# CONFIG_MTD_NAND_PLATFORM is not set
842CONFIG_MTD_ONENAND=m
843CONFIG_MTD_ONENAND_VERIFY_WRITE=y
844# CONFIG_MTD_ONENAND_OTP is not set
845
846#
847# UBI - Unsorted block images
848#
849# CONFIG_MTD_UBI is not set
850CONFIG_PARPORT=m
851CONFIG_PARPORT_PC=m
852CONFIG_PARPORT_SERIAL=m
853CONFIG_PARPORT_PC_FIFO=y
854CONFIG_PARPORT_PC_SUPERIO=y
855CONFIG_PARPORT_PC_PCMCIA=m
856# CONFIG_PARPORT_GSC is not set
857CONFIG_PARPORT_AX88796=m
858CONFIG_PARPORT_1284=y
859CONFIG_PARPORT_NOT_PC=y
860CONFIG_BLK_DEV=y
861CONFIG_PARIDE=m
862
863#
864# Parallel IDE high-level drivers
865#
866CONFIG_PARIDE_PD=m
867CONFIG_PARIDE_PCD=m
868CONFIG_PARIDE_PF=m
869CONFIG_PARIDE_PT=m
870CONFIG_PARIDE_PG=m
871
872#
873# Parallel IDE protocol modules
874#
875CONFIG_PARIDE_ATEN=m
876CONFIG_PARIDE_BPCK=m
877CONFIG_PARIDE_BPCK6=m
878CONFIG_PARIDE_COMM=m
879CONFIG_PARIDE_DSTR=m
880CONFIG_PARIDE_FIT2=m
881CONFIG_PARIDE_FIT3=m
882CONFIG_PARIDE_EPAT=m
883CONFIG_PARIDE_EPATC8=y
884CONFIG_PARIDE_EPIA=m
885CONFIG_PARIDE_FRIQ=m
886CONFIG_PARIDE_FRPW=m
887CONFIG_PARIDE_KBIC=m
888CONFIG_PARIDE_KTTI=m
889CONFIG_PARIDE_ON20=m
890CONFIG_PARIDE_ON26=m
891CONFIG_BLK_CPQ_DA=m
892CONFIG_BLK_CPQ_CISS_DA=m
893CONFIG_CISS_SCSI_TAPE=y
894CONFIG_BLK_DEV_DAC960=m
895CONFIG_BLK_DEV_UMEM=m
896# CONFIG_BLK_DEV_COW_COMMON is not set
897CONFIG_BLK_DEV_LOOP=m
898CONFIG_BLK_DEV_CRYPTOLOOP=m
899CONFIG_BLK_DEV_NBD=m
900CONFIG_BLK_DEV_SX8=m
901# CONFIG_BLK_DEV_UB is not set
902CONFIG_BLK_DEV_RAM=y
903CONFIG_BLK_DEV_RAM_COUNT=16
904CONFIG_BLK_DEV_RAM_SIZE=65536
905CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
906CONFIG_CDROM_PKTCDVD=m
907CONFIG_CDROM_PKTCDVD_BUFFERS=8
908# CONFIG_CDROM_PKTCDVD_WCACHE is not set
909CONFIG_ATA_OVER_ETH=m
910CONFIG_MISC_DEVICES=y
911# CONFIG_PHANTOM is not set
912# CONFIG_EEPROM_93CX6 is not set
913CONFIG_SGI_IOC4=m
914CONFIG_TIFM_CORE=m
915CONFIG_TIFM_7XX1=m
916CONFIG_IDE=y
917CONFIG_IDE_MAX_HWIFS=4
918CONFIG_BLK_DEV_IDE=y
919
920#
921# Please see Documentation/ide.txt for help/info on IDE drives
922#
923# CONFIG_BLK_DEV_IDE_SATA is not set
924CONFIG_BLK_DEV_IDEDISK=m
925# CONFIG_IDEDISK_MULTI_MODE is not set
926CONFIG_BLK_DEV_IDECS=m
927# CONFIG_BLK_DEV_DELKIN is not set
928CONFIG_BLK_DEV_IDECD=m
929CONFIG_BLK_DEV_IDETAPE=m
930CONFIG_BLK_DEV_IDEFLOPPY=m
931CONFIG_BLK_DEV_IDESCSI=m
932# CONFIG_IDE_TASK_IOCTL is not set
933CONFIG_IDE_PROC_FS=y
934
935#
936# IDE chipset support/bugfixes
937#
938CONFIG_IDE_GENERIC=m
939CONFIG_BLK_DEV_IDEPCI=y
940CONFIG_IDEPCI_SHARE_IRQ=y
941CONFIG_IDEPCI_PCIBUS_ORDER=y
942# CONFIG_BLK_DEV_OFFBOARD is not set
943CONFIG_BLK_DEV_GENERIC=m
944CONFIG_BLK_DEV_OPTI621=m
945CONFIG_BLK_DEV_IDEDMA_PCI=y
946# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
947# CONFIG_IDEDMA_ONLYDISK is not set
948CONFIG_BLK_DEV_AEC62XX=m
949CONFIG_BLK_DEV_ALI15X3=m
950# CONFIG_WDC_ALI15X3 is not set
951CONFIG_BLK_DEV_AMD74XX=m
952CONFIG_BLK_DEV_CMD64X=m
953CONFIG_BLK_DEV_TRIFLEX=m
954CONFIG_BLK_DEV_CY82C693=m
955# CONFIG_BLK_DEV_CS5520 is not set
956CONFIG_BLK_DEV_CS5530=m
957CONFIG_BLK_DEV_HPT34X=m
958# CONFIG_HPT34X_AUTODMA is not set
959CONFIG_BLK_DEV_HPT366=m
960# CONFIG_BLK_DEV_JMICRON is not set
961CONFIG_BLK_DEV_SC1200=m
962CONFIG_BLK_DEV_PIIX=m
963# CONFIG_BLK_DEV_IT8213 is not set
964CONFIG_BLK_DEV_IT821X=m
965CONFIG_BLK_DEV_NS87415=m
966CONFIG_BLK_DEV_PDC202XX_OLD=m
967CONFIG_PDC202XX_BURST=y
968CONFIG_BLK_DEV_PDC202XX_NEW=m
969CONFIG_BLK_DEV_SVWKS=m
970CONFIG_BLK_DEV_SIIMAGE=m
971# CONFIG_BLK_DEV_SLC90E66 is not set
972CONFIG_BLK_DEV_TRM290=m
973# CONFIG_BLK_DEV_VIA82CXXX is not set
974# CONFIG_BLK_DEV_TC86C001 is not set
975# CONFIG_IDE_ARM is not set
976CONFIG_BLK_DEV_IDEDMA=y
977# CONFIG_IDEDMA_IVB is not set
978# CONFIG_BLK_DEV_HD is not set
979
980#
981# SCSI device support
982#
983CONFIG_RAID_ATTRS=m
984CONFIG_SCSI=m
985CONFIG_SCSI_DMA=y
986# CONFIG_SCSI_TGT is not set
987CONFIG_SCSI_NETLINK=y
988CONFIG_SCSI_PROC_FS=y
989
990#
991# SCSI support type (disk, tape, CD-ROM)
992#
993CONFIG_BLK_DEV_SD=m
994CONFIG_CHR_DEV_ST=m
995CONFIG_CHR_DEV_OSST=m
996CONFIG_BLK_DEV_SR=m
997# CONFIG_BLK_DEV_SR_VENDOR is not set
998CONFIG_CHR_DEV_SG=m
999CONFIG_CHR_DEV_SCH=m
1000
1001#
1002# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
1003#
1004CONFIG_SCSI_MULTI_LUN=y
1005CONFIG_SCSI_CONSTANTS=y
1006CONFIG_SCSI_LOGGING=y
1007# CONFIG_SCSI_SCAN_ASYNC is not set
1008CONFIG_SCSI_WAIT_SCAN=m
1009
1010#
1011# SCSI Transports
1012#
1013CONFIG_SCSI_SPI_ATTRS=m
1014CONFIG_SCSI_FC_ATTRS=m
1015CONFIG_SCSI_ISCSI_ATTRS=m
1016CONFIG_SCSI_SAS_ATTRS=m
1017CONFIG_SCSI_SAS_LIBSAS=m
1018# CONFIG_SCSI_SAS_ATA is not set
1019# CONFIG_SCSI_SAS_LIBSAS_DEBUG is not set
1020CONFIG_SCSI_LOWLEVEL=y
1021CONFIG_ISCSI_TCP=m
1022CONFIG_BLK_DEV_3W_XXXX_RAID=m
1023CONFIG_SCSI_3W_9XXX=m
1024CONFIG_SCSI_ACARD=m
1025CONFIG_SCSI_AACRAID=m
1026CONFIG_SCSI_AIC7XXX=m
1027CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
1028CONFIG_AIC7XXX_RESET_DELAY_MS=15000
1029CONFIG_AIC7XXX_DEBUG_ENABLE=y
1030CONFIG_AIC7XXX_DEBUG_MASK=0
1031CONFIG_AIC7XXX_REG_PRETTY_PRINT=y
1032# CONFIG_SCSI_AIC7XXX_OLD is not set
1033CONFIG_SCSI_AIC79XX=m
1034CONFIG_AIC79XX_CMDS_PER_DEVICE=32
1035CONFIG_AIC79XX_RESET_DELAY_MS=15000
1036CONFIG_AIC79XX_DEBUG_ENABLE=y
1037CONFIG_AIC79XX_DEBUG_MASK=0
1038CONFIG_AIC79XX_REG_PRETTY_PRINT=y
1039CONFIG_SCSI_AIC94XX=m
1040# CONFIG_AIC94XX_DEBUG is not set
1041CONFIG_SCSI_DPT_I2O=m
1042CONFIG_SCSI_ARCMSR=m
1043CONFIG_MEGARAID_NEWGEN=y
1044CONFIG_MEGARAID_MM=m
1045CONFIG_MEGARAID_MAILBOX=m
1046CONFIG_MEGARAID_LEGACY=m
1047CONFIG_MEGARAID_SAS=m
1048CONFIG_SCSI_HPTIOP=m
1049CONFIG_SCSI_DMX3191D=m
1050CONFIG_SCSI_FUTURE_DOMAIN=m
1051CONFIG_SCSI_IPS=m
1052CONFIG_SCSI_INITIO=m
1053# CONFIG_SCSI_INIA100 is not set
1054CONFIG_SCSI_PPA=m
1055CONFIG_SCSI_IMM=m
1056# CONFIG_SCSI_IZIP_EPP16 is not set
1057# CONFIG_SCSI_IZIP_SLOW_CTR is not set
1058CONFIG_SCSI_STEX=m
1059CONFIG_SCSI_SYM53C8XX_2=m
1060CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1
1061CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16
1062CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64
1063CONFIG_SCSI_SYM53C8XX_MMIO=y
1064CONFIG_SCSI_IPR=m
1065# CONFIG_SCSI_IPR_TRACE is not set
1066# CONFIG_SCSI_IPR_DUMP is not set
1067CONFIG_SCSI_QLOGIC_1280=m
1068CONFIG_SCSI_QLA_FC=m
1069CONFIG_SCSI_QLA_ISCSI=m
1070CONFIG_SCSI_LPFC=m
1071CONFIG_SCSI_DC395x=m
1072CONFIG_SCSI_DC390T=m
1073CONFIG_SCSI_NSP32=m
1074CONFIG_SCSI_DEBUG=m
1075# CONFIG_SCSI_SRP is not set
1076# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
1077CONFIG_ATA=m
1078# CONFIG_ATA_NONSTANDARD is not set
1079CONFIG_SATA_AHCI=m
1080CONFIG_SATA_SVW=m
1081CONFIG_ATA_PIIX=m
1082CONFIG_SATA_MV=m
1083CONFIG_SATA_NV=m
1084CONFIG_PDC_ADMA=m
1085CONFIG_SATA_QSTOR=m
1086CONFIG_SATA_PROMISE=m
1087CONFIG_SATA_SX4=m
1088CONFIG_SATA_SIL=m
1089CONFIG_SATA_SIL24=m
1090CONFIG_SATA_SIS=m
1091CONFIG_SATA_ULI=m
1092CONFIG_SATA_VIA=m
1093CONFIG_SATA_VITESSE=m
1094# CONFIG_SATA_INIC162X is not set
1095# CONFIG_PATA_ALI is not set
1096# CONFIG_PATA_AMD is not set
1097# CONFIG_PATA_ARTOP is not set
1098# CONFIG_PATA_ATIIXP is not set
1099# CONFIG_PATA_CMD640_PCI is not set
1100# CONFIG_PATA_CMD64X is not set
1101CONFIG_PATA_CS5520=m
1102# CONFIG_PATA_CS5530 is not set
1103# CONFIG_PATA_CYPRESS is not set
1104CONFIG_PATA_EFAR=m
1105CONFIG_ATA_GENERIC=m
1106# CONFIG_PATA_HPT366 is not set
1107# CONFIG_PATA_HPT37X is not set
1108# CONFIG_PATA_HPT3X2N is not set
1109# CONFIG_PATA_HPT3X3 is not set
1110# CONFIG_PATA_IT821X is not set
1111# CONFIG_PATA_IT8213 is not set
1112CONFIG_PATA_JMICRON=m
1113CONFIG_PATA_TRIFLEX=m
1114# CONFIG_PATA_MARVELL is not set
1115CONFIG_PATA_MPIIX=m
1116# CONFIG_PATA_OLDPIIX is not set
1117CONFIG_PATA_NETCELL=m
1118# CONFIG_PATA_NS87410 is not set
1119# CONFIG_PATA_OPTI is not set
1120# CONFIG_PATA_OPTIDMA is not set
1121CONFIG_PATA_PCMCIA=m
1122# CONFIG_PATA_PDC_OLD is not set
1123# CONFIG_PATA_RADISYS is not set
1124CONFIG_PATA_RZ1000=m
1125# CONFIG_PATA_SC1200 is not set
1126# CONFIG_PATA_SERVERWORKS is not set
1127CONFIG_PATA_PDC2027X=m
1128CONFIG_PATA_SIL680=m
1129CONFIG_PATA_SIS=m
1130CONFIG_PATA_VIA=m
1131CONFIG_PATA_WINBOND=m
1132# CONFIG_PATA_PLATFORM is not set
1133CONFIG_MD=y
1134CONFIG_BLK_DEV_MD=m
1135CONFIG_MD_LINEAR=m
1136CONFIG_MD_RAID0=m
1137CONFIG_MD_RAID1=m
1138CONFIG_MD_RAID10=m
1139CONFIG_MD_RAID456=m
1140# CONFIG_MD_RAID5_RESHAPE is not set
1141CONFIG_MD_MULTIPATH=m
1142CONFIG_MD_FAULTY=m
1143CONFIG_BLK_DEV_DM=m
1144# CONFIG_DM_DEBUG is not set
1145CONFIG_DM_CRYPT=m
1146CONFIG_DM_SNAPSHOT=m
1147CONFIG_DM_MIRROR=m
1148CONFIG_DM_ZERO=m
1149CONFIG_DM_MULTIPATH=m
1150CONFIG_DM_MULTIPATH_EMC=m
1151# CONFIG_DM_MULTIPATH_RDAC is not set
1152# CONFIG_DM_DELAY is not set
1153
1154#
1155# Fusion MPT device support
1156#
1157CONFIG_FUSION=y
1158CONFIG_FUSION_SPI=m
1159CONFIG_FUSION_FC=m
1160CONFIG_FUSION_SAS=m
1161CONFIG_FUSION_MAX_SGE=128
1162CONFIG_FUSION_CTL=m
1163CONFIG_FUSION_LAN=m
1164# CONFIG_FUSION_LOGGING is not set
1165
1166#
1167# IEEE 1394 (FireWire) support
1168#
1169# CONFIG_FIREWIRE is not set
1170CONFIG_IEEE1394=m
1171
1172#
1173# Subsystem Options
1174#
1175# CONFIG_IEEE1394_VERBOSEDEBUG is not set
1176
1177#
1178# Controllers
1179#
1180CONFIG_IEEE1394_PCILYNX=m
1181CONFIG_IEEE1394_OHCI1394=m
1182
1183#
1184# Protocols
1185#
1186CONFIG_IEEE1394_VIDEO1394=m
1187CONFIG_IEEE1394_SBP2=m
1188# CONFIG_IEEE1394_SBP2_PHYS_DMA is not set
1189CONFIG_IEEE1394_ETH1394_ROM_ENTRY=y
1190CONFIG_IEEE1394_ETH1394=m
1191CONFIG_IEEE1394_DV1394=m
1192CONFIG_IEEE1394_RAWIO=m
1193CONFIG_I2O=m
1194CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y
1195CONFIG_I2O_EXT_ADAPTEC=y
1196CONFIG_I2O_CONFIG=m
1197CONFIG_I2O_CONFIG_OLD_IOCTL=y
1198CONFIG_I2O_BUS=m
1199CONFIG_I2O_BLOCK=m
1200CONFIG_I2O_SCSI=m
1201CONFIG_I2O_PROC=m
1202CONFIG_NETDEVICES=y
1203# CONFIG_NETDEVICES_MULTIQUEUE is not set
1204# CONFIG_IFB is not set
1205CONFIG_DUMMY=m
1206CONFIG_BONDING=m
1207# CONFIG_MACVLAN is not set
1208CONFIG_EQUALIZER=m
1209CONFIG_TUN=m
1210CONFIG_ARCNET=m
1211CONFIG_ARCNET_1201=m
1212CONFIG_ARCNET_1051=m
1213CONFIG_ARCNET_RAW=m
1214CONFIG_ARCNET_CAP=m
1215CONFIG_ARCNET_COM90xx=m
1216CONFIG_ARCNET_COM90xxIO=m
1217CONFIG_ARCNET_RIM_I=m
1218CONFIG_ARCNET_COM20020=m
1219CONFIG_ARCNET_COM20020_PCI=m
1220CONFIG_PHYLIB=m
1221
1222#
1223# MII PHY device drivers
1224#
1225CONFIG_MARVELL_PHY=m
1226CONFIG_DAVICOM_PHY=m
1227CONFIG_QSEMI_PHY=m
1228CONFIG_LXT_PHY=m
1229CONFIG_CICADA_PHY=m
1230CONFIG_VITESSE_PHY=m
1231CONFIG_SMSC_PHY=m
1232# CONFIG_BROADCOM_PHY is not set
1233# CONFIG_ICPLUS_PHY is not set
1234CONFIG_FIXED_PHY=m
1235# CONFIG_FIXED_MII_10_FDX is not set
1236# CONFIG_FIXED_MII_100_FDX is not set
1237CONFIG_NET_ETHERNET=y
1238CONFIG_MII=m
1239# CONFIG_AX88796 is not set
1240# CONFIG_MIPS_AU1X00_ENET is not set
1241CONFIG_HAPPYMEAL=m
1242CONFIG_SUNGEM=m
1243CONFIG_CASSINI=m
1244CONFIG_NET_VENDOR_3COM=y
1245CONFIG_VORTEX=m
1246CONFIG_TYPHOON=m
1247# CONFIG_SMC91X is not set
1248# CONFIG_DM9000 is not set
1249CONFIG_NET_TULIP=y
1250CONFIG_DE2104X=m
1251CONFIG_TULIP=m
1252# CONFIG_TULIP_MWI is not set
1253# CONFIG_TULIP_MMIO is not set
1254# CONFIG_TULIP_NAPI is not set
1255CONFIG_DE4X5=m
1256CONFIG_WINBOND_840=m
1257CONFIG_DM9102=m
1258CONFIG_ULI526X=m
1259CONFIG_PCMCIA_XIRCOM=m
1260# CONFIG_PCMCIA_XIRTULIP is not set
1261CONFIG_HP100=m
1262CONFIG_NET_PCI=y
1263CONFIG_PCNET32=m
1264# CONFIG_PCNET32_NAPI is not set
1265CONFIG_AMD8111_ETH=m
1266# CONFIG_AMD8111E_NAPI is not set
1267CONFIG_ADAPTEC_STARFIRE=m
1268# CONFIG_ADAPTEC_STARFIRE_NAPI is not set
1269CONFIG_B44=m
1270CONFIG_FORCEDETH=m
1271# CONFIG_FORCEDETH_NAPI is not set
1272# CONFIG_TC35815 is not set
1273CONFIG_DGRS=m
1274CONFIG_EEPRO100=m
1275CONFIG_E100=m
1276CONFIG_FEALNX=m
1277CONFIG_NATSEMI=m
1278CONFIG_NE2K_PCI=m
1279CONFIG_8139CP=m
1280CONFIG_8139TOO=m
1281# CONFIG_8139TOO_PIO is not set
1282# CONFIG_8139TOO_TUNE_TWISTER is not set
1283CONFIG_8139TOO_8129=y
1284# CONFIG_8139_OLD_RX_RESET is not set
1285CONFIG_SIS900=m
1286CONFIG_EPIC100=m
1287CONFIG_SUNDANCE=m
1288# CONFIG_SUNDANCE_MMIO is not set
1289CONFIG_TLAN=m
1290CONFIG_VIA_RHINE=m
1291# CONFIG_VIA_RHINE_MMIO is not set
1292# CONFIG_VIA_RHINE_NAPI is not set
1293# CONFIG_SC92031 is not set
1294CONFIG_NET_POCKET=y
1295CONFIG_DE600=m
1296CONFIG_DE620=m
1297CONFIG_NETDEV_1000=y
1298CONFIG_ACENIC=m
1299# CONFIG_ACENIC_OMIT_TIGON_I is not set
1300CONFIG_DL2K=m
1301CONFIG_E1000=m
1302# CONFIG_E1000_NAPI is not set
1303# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
1304CONFIG_NS83820=m
1305CONFIG_HAMACHI=m
1306CONFIG_YELLOWFIN=m
1307CONFIG_R8169=m
1308# CONFIG_R8169_NAPI is not set
1309CONFIG_R8169_VLAN=y
1310CONFIG_SIS190=m
1311CONFIG_SKGE=m
1312CONFIG_SKY2=m
1313CONFIG_SK98LIN=m
1314CONFIG_VIA_VELOCITY=m
1315CONFIG_TIGON3=m
1316CONFIG_BNX2=m
1317CONFIG_QLA3XXX=m
1318# CONFIG_ATL1 is not set
1319CONFIG_NETDEV_10000=y
1320CONFIG_CHELSIO_T1=m
1321# CONFIG_CHELSIO_T1_1G is not set
1322CONFIG_CHELSIO_T1_NAPI=y
1323# CONFIG_CHELSIO_T3 is not set
1324CONFIG_IXGB=m
1325# CONFIG_IXGB_NAPI is not set
1326CONFIG_S2IO=m
1327# CONFIG_S2IO_NAPI is not set
1328CONFIG_MYRI10GE=m
1329# CONFIG_NETXEN_NIC is not set
1330# CONFIG_MLX4_CORE is not set
1331CONFIG_TR=y
1332CONFIG_IBMOL=m
1333CONFIG_IBMLS=m
1334CONFIG_3C359=m
1335CONFIG_TMS380TR=m
1336CONFIG_TMSPCI=m
1337CONFIG_ABYSS=m
1338
1339#
1340# Wireless LAN
1341#
1342# CONFIG_WLAN_PRE80211 is not set
1343# CONFIG_WLAN_80211 is not set
1344
1345#
1346# USB Network Adapters
1347#
1348CONFIG_USB_CATC=m
1349CONFIG_USB_KAWETH=m
1350CONFIG_USB_PEGASUS=m
1351CONFIG_USB_RTL8150=m
1352CONFIG_USB_USBNET_MII=m
1353CONFIG_USB_USBNET=m
1354CONFIG_USB_NET_AX8817X=m
1355CONFIG_USB_NET_CDCETHER=m
1356# CONFIG_USB_NET_DM9601 is not set
1357CONFIG_USB_NET_GL620A=m
1358CONFIG_USB_NET_NET1080=m
1359CONFIG_USB_NET_PLUSB=m
1360CONFIG_USB_NET_MCS7830=m
1361CONFIG_USB_NET_RNDIS_HOST=m
1362CONFIG_USB_NET_CDC_SUBSET=m
1363CONFIG_USB_ALI_M5632=y
1364CONFIG_USB_AN2720=y
1365CONFIG_USB_BELKIN=y
1366CONFIG_USB_ARMLINUX=y
1367CONFIG_USB_EPSON2888=y
1368# CONFIG_USB_KC2190 is not set
1369CONFIG_USB_NET_ZAURUS=m
1370CONFIG_NET_PCMCIA=y
1371CONFIG_PCMCIA_3C589=m
1372CONFIG_PCMCIA_3C574=m
1373CONFIG_PCMCIA_FMVJ18X=m
1374CONFIG_PCMCIA_PCNET=m
1375CONFIG_PCMCIA_NMCLAN=m
1376CONFIG_PCMCIA_SMC91C92=m
1377CONFIG_PCMCIA_XIRC2PS=m
1378CONFIG_PCMCIA_AXNET=m
1379CONFIG_ARCNET_COM20020_CS=m
1380CONFIG_PCMCIA_IBMTR=m
1381CONFIG_WAN=y
1382CONFIG_LANMEDIA=m
1383CONFIG_HDLC=m
1384CONFIG_HDLC_RAW=m
1385CONFIG_HDLC_RAW_ETH=m
1386CONFIG_HDLC_CISCO=m
1387CONFIG_HDLC_FR=m
1388CONFIG_HDLC_PPP=m
1389CONFIG_HDLC_X25=m
1390CONFIG_PCI200SYN=m
1391CONFIG_WANXL=m
1392CONFIG_PC300=m
1393CONFIG_PC300_MLPPP=y
1394
1395#
1396# Cyclades-PC300 MLPPP support is disabled.
1397#
1398
1399#
1400# Refer to the file README.mlppp, provided by PC300 package.
1401#
1402# CONFIG_PC300TOO is not set
1403CONFIG_FARSYNC=m
1404CONFIG_DSCC4=m
1405CONFIG_DSCC4_PCISYNC=y
1406CONFIG_DSCC4_PCI_RST=y
1407CONFIG_DLCI=m
1408CONFIG_DLCI_MAX=8
1409CONFIG_WAN_ROUTER_DRIVERS=m
1410CONFIG_CYCLADES_SYNC=m
1411CONFIG_CYCLOMX_X25=y
1412CONFIG_LAPBETHER=m
1413CONFIG_X25_ASY=m
1414CONFIG_ATM_DRIVERS=y
1415# CONFIG_ATM_DUMMY is not set
1416CONFIG_ATM_TCP=m
1417CONFIG_ATM_LANAI=m
1418CONFIG_ATM_ENI=m
1419# CONFIG_ATM_ENI_DEBUG is not set
1420# CONFIG_ATM_ENI_TUNE_BURST is not set
1421CONFIG_ATM_FIRESTREAM=m
1422CONFIG_ATM_ZATM=m
1423# CONFIG_ATM_ZATM_DEBUG is not set
1424CONFIG_ATM_NICSTAR=m
1425# CONFIG_ATM_NICSTAR_USE_SUNI is not set
1426# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set
1427CONFIG_ATM_IDT77252=m
1428# CONFIG_ATM_IDT77252_DEBUG is not set
1429# CONFIG_ATM_IDT77252_RCV_ALL is not set
1430CONFIG_ATM_IDT77252_USE_SUNI=y
1431CONFIG_ATM_AMBASSADOR=m
1432# CONFIG_ATM_AMBASSADOR_DEBUG is not set
1433CONFIG_ATM_HORIZON=m
1434# CONFIG_ATM_HORIZON_DEBUG is not set
1435CONFIG_ATM_IA=m
1436# CONFIG_ATM_IA_DEBUG is not set
1437CONFIG_ATM_FORE200E_MAYBE=m
1438CONFIG_ATM_FORE200E_PCA=y
1439CONFIG_ATM_FORE200E_PCA_DEFAULT_FW=y
1440# CONFIG_ATM_FORE200E_USE_TASKLET is not set
1441CONFIG_ATM_FORE200E_TX_RETRY=16
1442CONFIG_ATM_FORE200E_DEBUG=0
1443CONFIG_ATM_FORE200E=m
1444CONFIG_ATM_HE=m
1445CONFIG_ATM_HE_USE_SUNI=y
1446CONFIG_FDDI=y
1447CONFIG_DEFXX=m
1448# CONFIG_DEFXX_MMIO is not set
1449CONFIG_SKFP=m
1450CONFIG_HIPPI=y
1451CONFIG_ROADRUNNER=m
1452# CONFIG_ROADRUNNER_LARGE_RINGS is not set
1453CONFIG_PLIP=m
1454CONFIG_PPP=m
1455CONFIG_PPP_MULTILINK=y
1456CONFIG_PPP_FILTER=y
1457CONFIG_PPP_ASYNC=m
1458CONFIG_PPP_SYNC_TTY=m
1459CONFIG_PPP_DEFLATE=m
1460CONFIG_PPP_BSDCOMP=m
1461CONFIG_PPP_MPPE=m
1462CONFIG_PPPOE=m
1463CONFIG_PPPOATM=m
1464# CONFIG_PPPOL2TP is not set
1465CONFIG_SLIP=m
1466CONFIG_SLIP_COMPRESSED=y
1467CONFIG_SLHC=m
1468CONFIG_SLIP_SMART=y
1469CONFIG_SLIP_MODE_SLIP6=y
1470CONFIG_NET_FC=y
1471CONFIG_SHAPER=m
1472CONFIG_NETCONSOLE=m
1473CONFIG_NETPOLL=y
1474# CONFIG_NETPOLL_TRAP is not set
1475CONFIG_NET_POLL_CONTROLLER=y
1476CONFIG_ISDN=m
1477CONFIG_ISDN_I4L=m
1478CONFIG_ISDN_PPP=y
1479CONFIG_ISDN_PPP_VJ=y
1480CONFIG_ISDN_MPP=y
1481CONFIG_IPPP_FILTER=y
1482CONFIG_ISDN_PPP_BSDCOMP=m
1483CONFIG_ISDN_AUDIO=y
1484CONFIG_ISDN_TTY_FAX=y
1485CONFIG_ISDN_X25=y
1486
1487#
1488# ISDN feature submodules
1489#
1490# CONFIG_ISDN_DRV_LOOP is not set
1491CONFIG_ISDN_DIVERSION=m
1492
1493#
1494# ISDN4Linux hardware drivers
1495#
1496
1497#
1498# Passive cards
1499#
1500CONFIG_ISDN_DRV_HISAX=m
1501
1502#
1503# D-channel protocol features
1504#
1505CONFIG_HISAX_EURO=y
1506CONFIG_DE_AOC=y
1507# CONFIG_HISAX_NO_SENDCOMPLETE is not set
1508# CONFIG_HISAX_NO_LLC is not set
1509# CONFIG_HISAX_NO_KEYPAD is not set
1510CONFIG_HISAX_1TR6=y
1511CONFIG_HISAX_NI1=y
1512CONFIG_HISAX_MAX_CARDS=8
1513
1514#
1515# HiSax supported cards
1516#
1517CONFIG_HISAX_16_3=y
1518CONFIG_HISAX_TELESPCI=y
1519CONFIG_HISAX_S0BOX=y
1520CONFIG_HISAX_FRITZPCI=y
1521CONFIG_HISAX_AVM_A1_PCMCIA=y
1522CONFIG_HISAX_ELSA=y
1523CONFIG_HISAX_DIEHLDIVA=y
1524CONFIG_HISAX_SEDLBAUER=y
1525CONFIG_HISAX_NETJET=y
1526CONFIG_HISAX_NETJET_U=y
1527CONFIG_HISAX_NICCY=y
1528CONFIG_HISAX_BKM_A4T=y
1529CONFIG_HISAX_SCT_QUADRO=y
1530CONFIG_HISAX_GAZEL=y
1531CONFIG_HISAX_HFC_PCI=y
1532CONFIG_HISAX_W6692=y
1533CONFIG_HISAX_HFC_SX=y
1534CONFIG_HISAX_ENTERNOW_PCI=y
1535# CONFIG_HISAX_DEBUG is not set
1536
1537#
1538# HiSax PCMCIA card service modules
1539#
1540CONFIG_HISAX_SEDLBAUER_CS=m
1541CONFIG_HISAX_ELSA_CS=m
1542CONFIG_HISAX_AVM_A1_CS=m
1543CONFIG_HISAX_TELES_CS=m
1544
1545#
1546# HiSax sub driver modules
1547#
1548CONFIG_HISAX_ST5481=m
1549CONFIG_HISAX_HFCUSB=m
1550CONFIG_HISAX_HFC4S8S=m
1551CONFIG_HISAX_FRITZ_PCIPNP=m
1552CONFIG_HISAX_HDLC=y
1553
1554#
1555# Active cards
1556#
1557# CONFIG_HYSDN is not set
1558CONFIG_ISDN_DRV_GIGASET=m
1559CONFIG_GIGASET_BASE=m
1560CONFIG_GIGASET_M105=m
1561# CONFIG_GIGASET_M101 is not set
1562# CONFIG_GIGASET_DEBUG is not set
1563# CONFIG_GIGASET_UNDOCREQ is not set
1564CONFIG_ISDN_CAPI=m
1565CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
1566CONFIG_CAPI_TRACE=y
1567CONFIG_ISDN_CAPI_MIDDLEWARE=y
1568CONFIG_ISDN_CAPI_CAPI20=m
1569CONFIG_ISDN_CAPI_CAPIFS_BOOL=y
1570CONFIG_ISDN_CAPI_CAPIFS=m
1571CONFIG_ISDN_CAPI_CAPIDRV=m
1572
1573#
1574# CAPI hardware drivers
1575#
1576CONFIG_CAPI_AVM=y
1577CONFIG_ISDN_DRV_AVMB1_B1PCI=m
1578CONFIG_ISDN_DRV_AVMB1_B1PCIV4=y
1579CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
1580CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
1581CONFIG_ISDN_DRV_AVMB1_T1PCI=m
1582CONFIG_ISDN_DRV_AVMB1_C4=m
1583CONFIG_CAPI_EICON=y
1584CONFIG_ISDN_DIVAS=m
1585CONFIG_ISDN_DIVAS_BRIPCI=y
1586CONFIG_ISDN_DIVAS_PRIPCI=y
1587CONFIG_ISDN_DIVAS_DIVACAPI=m
1588CONFIG_ISDN_DIVAS_USERIDI=m
1589CONFIG_ISDN_DIVAS_MAINT=m
1590CONFIG_PHONE=m
1591CONFIG_PHONE_IXJ=m
1592CONFIG_PHONE_IXJ_PCMCIA=m
1593
1594#
1595# Input device support
1596#
1597CONFIG_INPUT=y
1598CONFIG_INPUT_FF_MEMLESS=m
1599# CONFIG_INPUT_POLLDEV is not set
1600
1601#
1602# Userland interfaces
1603#
1604CONFIG_INPUT_MOUSEDEV=y
1605CONFIG_INPUT_MOUSEDEV_PSAUX=y
1606CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1607CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1608CONFIG_INPUT_JOYDEV=m
1609CONFIG_INPUT_TSDEV=m
1610CONFIG_INPUT_TSDEV_SCREEN_X=240
1611CONFIG_INPUT_TSDEV_SCREEN_Y=320
1612CONFIG_INPUT_EVDEV=m
1613CONFIG_INPUT_EVBUG=m
1614
1615#
1616# Input Device Drivers
1617#
1618CONFIG_INPUT_KEYBOARD=y
1619CONFIG_KEYBOARD_ATKBD=y
1620CONFIG_KEYBOARD_SUNKBD=m
1621CONFIG_KEYBOARD_LKKBD=m
1622CONFIG_KEYBOARD_XTKBD=m
1623CONFIG_KEYBOARD_NEWTON=m
1624CONFIG_KEYBOARD_STOWAWAY=m
1625CONFIG_INPUT_MOUSE=y
1626CONFIG_MOUSE_PS2=m
1627CONFIG_MOUSE_PS2_ALPS=y
1628CONFIG_MOUSE_PS2_LOGIPS2PP=y
1629CONFIG_MOUSE_PS2_SYNAPTICS=y
1630CONFIG_MOUSE_PS2_LIFEBOOK=y
1631CONFIG_MOUSE_PS2_TRACKPOINT=y
1632# CONFIG_MOUSE_PS2_TOUCHKIT is not set
1633CONFIG_MOUSE_SERIAL=m
1634# CONFIG_MOUSE_APPLETOUCH is not set
1635CONFIG_MOUSE_VSXXXAA=m
1636CONFIG_INPUT_JOYSTICK=y
1637CONFIG_JOYSTICK_ANALOG=m
1638CONFIG_JOYSTICK_A3D=m
1639CONFIG_JOYSTICK_ADI=m
1640CONFIG_JOYSTICK_COBRA=m
1641CONFIG_JOYSTICK_GF2K=m
1642CONFIG_JOYSTICK_GRIP=m
1643CONFIG_JOYSTICK_GRIP_MP=m
1644CONFIG_JOYSTICK_GUILLEMOT=m
1645CONFIG_JOYSTICK_INTERACT=m
1646CONFIG_JOYSTICK_SIDEWINDER=m
1647CONFIG_JOYSTICK_TMDC=m
1648CONFIG_JOYSTICK_IFORCE=m
1649CONFIG_JOYSTICK_IFORCE_USB=y
1650CONFIG_JOYSTICK_IFORCE_232=y
1651CONFIG_JOYSTICK_WARRIOR=m
1652CONFIG_JOYSTICK_MAGELLAN=m
1653CONFIG_JOYSTICK_SPACEORB=m
1654CONFIG_JOYSTICK_SPACEBALL=m
1655CONFIG_JOYSTICK_STINGER=m
1656CONFIG_JOYSTICK_TWIDJOY=m
1657CONFIG_JOYSTICK_DB9=m
1658CONFIG_JOYSTICK_GAMECON=m
1659CONFIG_JOYSTICK_TURBOGRAFX=m
1660CONFIG_JOYSTICK_JOYDUMP=m
1661# CONFIG_JOYSTICK_XPAD is not set
1662# CONFIG_INPUT_TABLET is not set
1663CONFIG_INPUT_TOUCHSCREEN=y
1664CONFIG_TOUCHSCREEN_ADS7846=m
1665# CONFIG_TOUCHSCREEN_FUJITSU is not set
1666CONFIG_TOUCHSCREEN_GUNZE=m
1667CONFIG_TOUCHSCREEN_ELO=m
1668CONFIG_TOUCHSCREEN_MTOUCH=m
1669CONFIG_TOUCHSCREEN_MK712=m
1670CONFIG_TOUCHSCREEN_PENMOUNT=m
1671CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
1672CONFIG_TOUCHSCREEN_TOUCHWIN=m
1673# CONFIG_TOUCHSCREEN_UCB1400 is not set
1674# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
1675CONFIG_INPUT_MISC=y
1676CONFIG_INPUT_PCSPKR=m
1677# CONFIG_INPUT_ATI_REMOTE is not set
1678# CONFIG_INPUT_ATI_REMOTE2 is not set
1679# CONFIG_INPUT_KEYSPAN_REMOTE is not set
1680# CONFIG_INPUT_POWERMATE is not set
1681# CONFIG_INPUT_YEALINK is not set
1682CONFIG_INPUT_UINPUT=m
1683
1684#
1685# Hardware I/O ports
1686#
1687CONFIG_SERIO=y
1688CONFIG_SERIO_I8042=y
1689CONFIG_SERIO_SERPORT=m
1690CONFIG_SERIO_PARKBD=m
1691CONFIG_SERIO_PCIPS2=m
1692CONFIG_SERIO_LIBPS2=y
1693CONFIG_SERIO_RAW=m
1694CONFIG_GAMEPORT=m
1695CONFIG_GAMEPORT_NS558=m
1696CONFIG_GAMEPORT_L4=m
1697CONFIG_GAMEPORT_EMU10K1=m
1698CONFIG_GAMEPORT_FM801=m
1699
1700#
1701# Character devices
1702#
1703CONFIG_VT=y
1704CONFIG_VT_CONSOLE=y
1705CONFIG_HW_CONSOLE=y
1706CONFIG_VT_HW_CONSOLE_BINDING=y
1707CONFIG_SERIAL_NONSTANDARD=y
1708# CONFIG_COMPUTONE is not set
1709CONFIG_ROCKETPORT=m
1710CONFIG_CYCLADES=m
1711# CONFIG_CYZ_INTR is not set
1712CONFIG_DIGIEPCA=m
1713# CONFIG_MOXA_INTELLIO is not set
1714CONFIG_MOXA_SMARTIO=m
1715# CONFIG_MOXA_SMARTIO_NEW is not set
1716# CONFIG_ISI is not set
1717CONFIG_SYNCLINKMP=m
1718CONFIG_SYNCLINK_GT=m
1719CONFIG_N_HDLC=m
1720# CONFIG_RISCOM8 is not set
1721CONFIG_SPECIALIX=m
1722# CONFIG_SPECIALIX_RTSCTS is not set
1723CONFIG_SX=m
1724# CONFIG_RIO is not set
1725CONFIG_STALDRV=y
1726# CONFIG_STALLION is not set
1727# CONFIG_ISTALLION is not set
1728
1729#
1730# Serial drivers
1731#
1732CONFIG_SERIAL_8250=m
1733CONFIG_SERIAL_8250_PCI=m
1734CONFIG_SERIAL_8250_CS=m
1735CONFIG_SERIAL_8250_NR_UARTS=48
1736CONFIG_SERIAL_8250_RUNTIME_UARTS=4
1737CONFIG_SERIAL_8250_EXTENDED=y
1738CONFIG_SERIAL_8250_MANY_PORTS=y
1739CONFIG_SERIAL_8250_SHARE_IRQ=y
1740# CONFIG_SERIAL_8250_DETECT_IRQ is not set
1741CONFIG_SERIAL_8250_RSA=y
1742# CONFIG_SERIAL_8250_AU1X00 is not set
1743
1744#
1745# Non-8250 serial port support
1746#
1747CONFIG_SERIAL_CORE=m
1748CONFIG_SERIAL_JSM=m
1749CONFIG_UNIX98_PTYS=y
1750CONFIG_LEGACY_PTYS=y
1751CONFIG_LEGACY_PTY_COUNT=256
1752CONFIG_PRINTER=m
1753# CONFIG_LP_CONSOLE is not set
1754CONFIG_PPDEV=m
1755CONFIG_TIPAR=m
1756CONFIG_IPMI_HANDLER=m
1757# CONFIG_IPMI_PANIC_EVENT is not set
1758CONFIG_IPMI_DEVICE_INTERFACE=m
1759CONFIG_IPMI_SI=m
1760CONFIG_IPMI_WATCHDOG=m
1761CONFIG_IPMI_POWEROFF=m
1762CONFIG_WATCHDOG=y
1763# CONFIG_WATCHDOG_NOWAYOUT is not set
1764
1765#
1766# Watchdog Device Drivers
1767#
1768CONFIG_SOFT_WATCHDOG=m
1769# CONFIG_WDT_MTX1 is not set
1770
1771#
1772# PCI-based Watchdog Cards
1773#
1774CONFIG_PCIPCWATCHDOG=m
1775CONFIG_WDTPCI=m
1776CONFIG_WDT_501_PCI=y
1777
1778#
1779# USB-based Watchdog Cards
1780#
1781CONFIG_USBPCWATCHDOG=m
1782CONFIG_HW_RANDOM=y
1783CONFIG_RTC=y
1784CONFIG_R3964=m
1785CONFIG_APPLICOM=m
1786CONFIG_DRM=m
1787CONFIG_DRM_TDFX=m
1788CONFIG_DRM_R128=m
1789CONFIG_DRM_RADEON=m
1790CONFIG_DRM_MGA=m
1791CONFIG_DRM_VIA=m
1792CONFIG_DRM_SAVAGE=m
1793
1794#
1795# PCMCIA character devices
1796#
1797CONFIG_SYNCLINK_CS=m
1798CONFIG_CARDMAN_4000=m
1799CONFIG_CARDMAN_4040=m
1800CONFIG_RAW_DRIVER=m
1801CONFIG_MAX_RAW_DEVS=256
1802CONFIG_TCG_TPM=m
1803CONFIG_TCG_ATMEL=m
1804CONFIG_DEVPORT=y
1805CONFIG_I2C=m
1806CONFIG_I2C_BOARDINFO=y
1807CONFIG_I2C_CHARDEV=m
1808
1809#
1810# I2C Algorithms
1811#
1812CONFIG_I2C_ALGOBIT=m
1813CONFIG_I2C_ALGOPCF=m
1814CONFIG_I2C_ALGOPCA=m
1815
1816#
1817# I2C Hardware Bus support
1818#
1819CONFIG_I2C_ALI1535=m
1820CONFIG_I2C_ALI1563=m
1821CONFIG_I2C_ALI15X3=m
1822CONFIG_I2C_AMD756=m
1823CONFIG_I2C_AMD756_S4882=m
1824CONFIG_I2C_AMD8111=m
1825CONFIG_I2C_I801=m
1826CONFIG_I2C_I810=m
1827CONFIG_I2C_PIIX4=m
1828CONFIG_I2C_NFORCE2=m
1829CONFIG_I2C_OCORES=m
1830CONFIG_I2C_PARPORT=m
1831CONFIG_I2C_PARPORT_LIGHT=m
1832CONFIG_I2C_PROSAVAGE=m
1833CONFIG_I2C_SAVAGE4=m
1834# CONFIG_I2C_SIMTEC is not set
1835CONFIG_I2C_SIS5595=m
1836CONFIG_I2C_SIS630=m
1837CONFIG_I2C_SIS96X=m
1838# CONFIG_I2C_TAOS_EVM is not set
1839CONFIG_I2C_STUB=m
1840# CONFIG_I2C_TINY_USB is not set
1841CONFIG_I2C_VIA=m
1842CONFIG_I2C_VIAPRO=m
1843CONFIG_I2C_VOODOO3=m
1844
1845#
1846# Miscellaneous I2C Chip support
1847#
1848CONFIG_SENSORS_DS1337=m
1849CONFIG_SENSORS_DS1374=m
1850# CONFIG_DS1682 is not set
1851CONFIG_SENSORS_EEPROM=m
1852CONFIG_SENSORS_PCF8574=m
1853CONFIG_SENSORS_PCA9539=m
1854CONFIG_SENSORS_PCF8591=m
1855CONFIG_SENSORS_MAX6875=m
1856# CONFIG_SENSORS_TSL2550 is not set
1857# CONFIG_I2C_DEBUG_CORE is not set
1858# CONFIG_I2C_DEBUG_ALGO is not set
1859# CONFIG_I2C_DEBUG_BUS is not set
1860# CONFIG_I2C_DEBUG_CHIP is not set
1861
1862#
1863# SPI support
1864#
1865CONFIG_SPI=y
1866CONFIG_SPI_MASTER=y
1867
1868#
1869# SPI Master Controller Drivers
1870#
1871CONFIG_SPI_BITBANG=m
1872CONFIG_SPI_BUTTERFLY=m
1873# CONFIG_SPI_LM70_LLP is not set
1874
1875#
1876# SPI Protocol Masters
1877#
1878# CONFIG_SPI_AT25 is not set
1879# CONFIG_SPI_SPIDEV is not set
1880# CONFIG_SPI_TLE62X0 is not set
1881CONFIG_W1=m
1882CONFIG_W1_CON=y
1883
1884#
1885# 1-wire Bus Masters
1886#
1887CONFIG_W1_MASTER_MATROX=m
1888CONFIG_W1_MASTER_DS2490=m
1889CONFIG_W1_MASTER_DS2482=m
1890
1891#
1892# 1-wire Slaves
1893#
1894CONFIG_W1_SLAVE_THERM=m
1895CONFIG_W1_SLAVE_SMEM=m
1896CONFIG_W1_SLAVE_DS2433=m
1897# CONFIG_W1_SLAVE_DS2433_CRC is not set
1898# CONFIG_W1_SLAVE_DS2760 is not set
1899# CONFIG_POWER_SUPPLY is not set
1900CONFIG_HWMON=y
1901CONFIG_HWMON_VID=m
1902CONFIG_SENSORS_ABITUGURU=m
1903# CONFIG_SENSORS_ABITUGURU3 is not set
1904# CONFIG_SENSORS_AD7418 is not set
1905CONFIG_SENSORS_ADM1021=m
1906CONFIG_SENSORS_ADM1025=m
1907CONFIG_SENSORS_ADM1026=m
1908# CONFIG_SENSORS_ADM1029 is not set
1909CONFIG_SENSORS_ADM1031=m
1910CONFIG_SENSORS_ADM9240=m
1911CONFIG_SENSORS_ASB100=m
1912CONFIG_SENSORS_ATXP1=m
1913CONFIG_SENSORS_DS1621=m
1914CONFIG_SENSORS_F71805F=m
1915CONFIG_SENSORS_FSCHER=m
1916CONFIG_SENSORS_FSCPOS=m
1917CONFIG_SENSORS_GL518SM=m
1918CONFIG_SENSORS_GL520SM=m
1919CONFIG_SENSORS_IT87=m
1920CONFIG_SENSORS_LM63=m
1921CONFIG_SENSORS_LM70=m
1922CONFIG_SENSORS_LM75=m
1923CONFIG_SENSORS_LM77=m
1924CONFIG_SENSORS_LM78=m
1925CONFIG_SENSORS_LM80=m
1926CONFIG_SENSORS_LM83=m
1927CONFIG_SENSORS_LM85=m
1928CONFIG_SENSORS_LM87=m
1929CONFIG_SENSORS_LM90=m
1930CONFIG_SENSORS_LM92=m
1931# CONFIG_SENSORS_LM93 is not set
1932CONFIG_SENSORS_MAX1619=m
1933# CONFIG_SENSORS_MAX6650 is not set
1934CONFIG_SENSORS_PC87360=m
1935# CONFIG_SENSORS_PC87427 is not set
1936CONFIG_SENSORS_SIS5595=m
1937# CONFIG_SENSORS_DME1737 is not set
1938CONFIG_SENSORS_SMSC47M1=m
1939CONFIG_SENSORS_SMSC47M192=m
1940CONFIG_SENSORS_SMSC47B397=m
1941# CONFIG_SENSORS_THMC50 is not set
1942CONFIG_SENSORS_VIA686A=m
1943CONFIG_SENSORS_VT1211=m
1944CONFIG_SENSORS_VT8231=m
1945CONFIG_SENSORS_W83781D=m
1946CONFIG_SENSORS_W83791D=m
1947CONFIG_SENSORS_W83792D=m
1948# CONFIG_SENSORS_W83793 is not set
1949CONFIG_SENSORS_W83L785TS=m
1950CONFIG_SENSORS_W83627HF=m
1951CONFIG_SENSORS_W83627EHF=m
1952# CONFIG_HWMON_DEBUG_CHIP is not set
1953
1954#
1955# Multifunction device drivers
1956#
1957# CONFIG_MFD_SM501 is not set
1958
1959#
1960# Multimedia devices
1961#
1962CONFIG_VIDEO_DEV=m
1963CONFIG_VIDEO_V4L1=y
1964CONFIG_VIDEO_V4L1_COMPAT=y
1965CONFIG_VIDEO_V4L2=y
1966CONFIG_VIDEO_CAPTURE_DRIVERS=y
1967# CONFIG_VIDEO_ADV_DEBUG is not set
1968CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
1969CONFIG_VIDEO_TVAUDIO=m
1970CONFIG_VIDEO_TDA7432=m
1971CONFIG_VIDEO_TDA9840=m
1972CONFIG_VIDEO_TDA9875=m
1973CONFIG_VIDEO_TEA6415C=m
1974CONFIG_VIDEO_TEA6420=m
1975CONFIG_VIDEO_MSP3400=m
1976CONFIG_VIDEO_WM8775=m
1977CONFIG_VIDEO_BT819=m
1978CONFIG_VIDEO_BT856=m
1979CONFIG_VIDEO_KS0127=m
1980CONFIG_VIDEO_SAA7110=m
1981CONFIG_VIDEO_SAA7111=m
1982CONFIG_VIDEO_SAA7114=m
1983CONFIG_VIDEO_SAA711X=m
1984CONFIG_VIDEO_TVP5150=m
1985CONFIG_VIDEO_VPX3220=m
1986CONFIG_VIDEO_CX25840=m
1987CONFIG_VIDEO_CX2341X=m
1988CONFIG_VIDEO_SAA7185=m
1989CONFIG_VIDEO_ADV7170=m
1990CONFIG_VIDEO_ADV7175=m
1991CONFIG_VIDEO_VIVI=m
1992CONFIG_VIDEO_BT848=m
1993CONFIG_VIDEO_BT848_DVB=y
1994CONFIG_VIDEO_SAA6588=m
1995CONFIG_VIDEO_BWQCAM=m
1996CONFIG_VIDEO_CQCAM=m
1997CONFIG_VIDEO_W9966=m
1998CONFIG_VIDEO_CPIA=m
1999CONFIG_VIDEO_CPIA_PP=m
2000CONFIG_VIDEO_CPIA_USB=m
2001CONFIG_VIDEO_CPIA2=m
2002CONFIG_VIDEO_SAA5246A=m
2003CONFIG_VIDEO_SAA5249=m
2004CONFIG_TUNER_3036=m
2005# CONFIG_TUNER_TEA5761 is not set
2006CONFIG_VIDEO_STRADIS=m
2007CONFIG_VIDEO_ZORAN_ZR36060=m
2008CONFIG_VIDEO_ZORAN=m
2009CONFIG_VIDEO_ZORAN_BUZ=m
2010CONFIG_VIDEO_ZORAN_DC10=m
2011CONFIG_VIDEO_ZORAN_DC30=m
2012CONFIG_VIDEO_ZORAN_LML33=m
2013CONFIG_VIDEO_ZORAN_LML33R10=m
2014CONFIG_VIDEO_ZORAN_AVS6EYES=m
2015CONFIG_VIDEO_SAA7134=m
2016CONFIG_VIDEO_SAA7134_ALSA=m
2017CONFIG_VIDEO_SAA7134_OSS=m
2018CONFIG_VIDEO_SAA7134_DVB=m
2019CONFIG_VIDEO_MXB=m
2020CONFIG_VIDEO_DPC=m
2021CONFIG_VIDEO_HEXIUM_ORION=m
2022CONFIG_VIDEO_HEXIUM_GEMINI=m
2023CONFIG_VIDEO_CX88=m
2024CONFIG_VIDEO_CX88_ALSA=m
2025CONFIG_VIDEO_CX88_BLACKBIRD=m
2026CONFIG_VIDEO_CX88_DVB=m
2027CONFIG_VIDEO_CX88_VP3054=m
2028# CONFIG_VIDEO_IVTV is not set
2029# CONFIG_VIDEO_CAFE_CCIC is not set
2030CONFIG_V4L_USB_DRIVERS=y
2031CONFIG_VIDEO_PVRUSB2=m
2032CONFIG_VIDEO_PVRUSB2_29XXX=y
2033CONFIG_VIDEO_PVRUSB2_24XXX=y
2034CONFIG_VIDEO_PVRUSB2_SYSFS=y
2035# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
2036CONFIG_VIDEO_EM28XX=m
2037# CONFIG_VIDEO_USBVISION is not set
2038CONFIG_VIDEO_USBVIDEO=m
2039CONFIG_USB_VICAM=m
2040CONFIG_USB_IBMCAM=m
2041CONFIG_USB_KONICAWC=m
2042CONFIG_USB_QUICKCAM_MESSENGER=m
2043CONFIG_USB_ET61X251=m
2044CONFIG_VIDEO_OVCAMCHIP=m
2045CONFIG_USB_W9968CF=m
2046# CONFIG_USB_OV511 is not set
2047CONFIG_USB_SE401=m
2048CONFIG_USB_SN9C102=m
2049CONFIG_USB_STV680=m
2050CONFIG_USB_ZC0301=m
2051CONFIG_USB_PWC=m
2052# CONFIG_USB_PWC_DEBUG is not set
2053# CONFIG_USB_ZR364XX is not set
2054CONFIG_RADIO_ADAPTERS=y
2055CONFIG_RADIO_GEMTEK_PCI=m
2056CONFIG_RADIO_MAXIRADIO=m
2057CONFIG_RADIO_MAESTRO=m
2058CONFIG_USB_DSBR=m
2059CONFIG_DVB_CORE=m
2060CONFIG_DVB_CORE_ATTACH=y
2061CONFIG_DVB_CAPTURE_DRIVERS=y
2062
2063#
2064# Supported SAA7146 based PCI Adapters
2065#
2066CONFIG_DVB_AV7110=m
2067CONFIG_DVB_AV7110_OSD=y
2068CONFIG_DVB_BUDGET=m
2069CONFIG_DVB_BUDGET_CI=m
2070CONFIG_DVB_BUDGET_AV=m
2071CONFIG_DVB_BUDGET_PATCH=m
2072
2073#
2074# Supported USB Adapters
2075#
2076CONFIG_DVB_USB=m
2077# CONFIG_DVB_USB_DEBUG is not set
2078CONFIG_DVB_USB_A800=m
2079CONFIG_DVB_USB_DIBUSB_MB=m
2080CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
2081CONFIG_DVB_USB_DIBUSB_MC=m
2082CONFIG_DVB_USB_DIB0700=m
2083CONFIG_DVB_USB_UMT_010=m
2084CONFIG_DVB_USB_CXUSB=m
2085# CONFIG_DVB_USB_M920X is not set
2086# CONFIG_DVB_USB_GL861 is not set
2087# CONFIG_DVB_USB_AU6610 is not set
2088CONFIG_DVB_USB_DIGITV=m
2089CONFIG_DVB_USB_VP7045=m
2090CONFIG_DVB_USB_VP702X=m
2091CONFIG_DVB_USB_GP8PSK=m
2092CONFIG_DVB_USB_NOVA_T_USB2=m
2093# CONFIG_DVB_USB_TTUSB2 is not set
2094CONFIG_DVB_USB_DTT200U=m
2095# CONFIG_DVB_USB_OPERA1 is not set
2096# CONFIG_DVB_USB_AF9005 is not set
2097CONFIG_DVB_TTUSB_BUDGET=m
2098CONFIG_DVB_TTUSB_DEC=m
2099CONFIG_DVB_CINERGYT2=m
2100CONFIG_DVB_CINERGYT2_TUNING=y
2101CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32
2102CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512
2103CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250
2104CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y
2105CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100
2106
2107#
2108# Supported FlexCopII (B2C2) Adapters
2109#
2110CONFIG_DVB_B2C2_FLEXCOP=m
2111CONFIG_DVB_B2C2_FLEXCOP_PCI=m
2112CONFIG_DVB_B2C2_FLEXCOP_USB=m
2113# CONFIG_DVB_B2C2_FLEXCOP_DEBUG is not set
2114
2115#
2116# Supported BT878 Adapters
2117#
2118CONFIG_DVB_BT8XX=m
2119
2120#
2121# Supported Pluto2 Adapters
2122#
2123CONFIG_DVB_PLUTO2=m
2124
2125#
2126# Supported DVB Frontends
2127#
2128
2129#
2130# Customise DVB Frontends
2131#
2132# CONFIG_DVB_FE_CUSTOMISE is not set
2133
2134#
2135# DVB-S (satellite) frontends
2136#
2137CONFIG_DVB_STV0299=m
2138CONFIG_DVB_CX24110=m
2139CONFIG_DVB_CX24123=m
2140CONFIG_DVB_TDA8083=m
2141CONFIG_DVB_MT312=m
2142CONFIG_DVB_VES1X93=m
2143CONFIG_DVB_S5H1420=m
2144CONFIG_DVB_TDA10086=m
2145
2146#
2147# DVB-T (terrestrial) frontends
2148#
2149CONFIG_DVB_SP8870=m
2150CONFIG_DVB_SP887X=m
2151CONFIG_DVB_CX22700=m
2152CONFIG_DVB_CX22702=m
2153CONFIG_DVB_L64781=m
2154CONFIG_DVB_TDA1004X=m
2155CONFIG_DVB_NXT6000=m
2156CONFIG_DVB_MT352=m
2157CONFIG_DVB_ZL10353=m
2158CONFIG_DVB_DIB3000MB=m
2159CONFIG_DVB_DIB3000MC=m
2160CONFIG_DVB_DIB7000M=m
2161CONFIG_DVB_DIB7000P=m
2162
2163#
2164# DVB-C (cable) frontends
2165#
2166CONFIG_DVB_VES1820=m
2167CONFIG_DVB_TDA10021=m
2168CONFIG_DVB_TDA10023=m
2169CONFIG_DVB_STV0297=m
2170
2171#
2172# ATSC (North American/Korean Terrestrial/Cable DTV) frontends
2173#
2174CONFIG_DVB_NXT200X=m
2175CONFIG_DVB_OR51211=m
2176CONFIG_DVB_OR51132=m
2177CONFIG_DVB_BCM3510=m
2178CONFIG_DVB_LGDT330X=m
2179
2180#
2181# Tuners/PLL support
2182#
2183CONFIG_DVB_PLL=m
2184CONFIG_DVB_TDA826X=m
2185CONFIG_DVB_TDA827X=m
2186# CONFIG_DVB_TUNER_QT1010 is not set
2187CONFIG_DVB_TUNER_MT2060=m
2188
2189#
2190# Miscellaneous devices
2191#
2192CONFIG_DVB_LNBP21=m
2193CONFIG_DVB_ISL6421=m
2194CONFIG_DVB_TUA6100=m
2195CONFIG_VIDEO_SAA7146=m
2196CONFIG_VIDEO_SAA7146_VV=m
2197CONFIG_VIDEO_TUNER=m
2198CONFIG_VIDEO_BUF=m
2199CONFIG_VIDEO_BUF_DVB=m
2200CONFIG_VIDEO_BTCX=m
2201CONFIG_VIDEO_IR_I2C=m
2202CONFIG_VIDEO_IR=m
2203CONFIG_VIDEO_TVEEPROM=m
2204CONFIG_DAB=y
2205CONFIG_USB_DABUSB=m
2206
2207#
2208# Graphics support
2209#
2210CONFIG_BACKLIGHT_LCD_SUPPORT=y
2211CONFIG_LCD_CLASS_DEVICE=m
2212CONFIG_BACKLIGHT_CLASS_DEVICE=y
2213
2214#
2215# Display device support
2216#
2217# CONFIG_DISPLAY_SUPPORT is not set
2218CONFIG_VGASTATE=m
2219CONFIG_VIDEO_OUTPUT_CONTROL=m
2220CONFIG_FB=y
2221CONFIG_FIRMWARE_EDID=y
2222CONFIG_FB_DDC=m
2223CONFIG_FB_CFB_FILLRECT=m
2224CONFIG_FB_CFB_COPYAREA=m
2225CONFIG_FB_CFB_IMAGEBLIT=m
2226# CONFIG_FB_SYS_FILLRECT is not set
2227# CONFIG_FB_SYS_COPYAREA is not set
2228# CONFIG_FB_SYS_IMAGEBLIT is not set
2229# CONFIG_FB_SYS_FOPS is not set
2230CONFIG_FB_DEFERRED_IO=y
2231# CONFIG_FB_SVGALIB is not set
2232# CONFIG_FB_MACMODES is not set
2233CONFIG_FB_BACKLIGHT=y
2234CONFIG_FB_MODE_HELPERS=y
2235CONFIG_FB_TILEBLITTING=y
2236
2237#
2238# Frame buffer hardware drivers
2239#
2240CONFIG_FB_CIRRUS=m
2241CONFIG_FB_PM2=m
2242CONFIG_FB_PM2_FIFO_DISCONNECT=y
2243CONFIG_FB_CYBER2000=m
2244# CONFIG_FB_ASILIANT is not set
2245# CONFIG_FB_IMSTT is not set
2246CONFIG_FB_S1D13XXX=m
2247CONFIG_FB_NVIDIA=m
2248CONFIG_FB_NVIDIA_I2C=y
2249# CONFIG_FB_NVIDIA_DEBUG is not set
2250CONFIG_FB_NVIDIA_BACKLIGHT=y
2251CONFIG_FB_RIVA=m
2252CONFIG_FB_RIVA_I2C=y
2253# CONFIG_FB_RIVA_DEBUG is not set
2254CONFIG_FB_RIVA_BACKLIGHT=y
2255CONFIG_FB_MATROX=m
2256CONFIG_FB_MATROX_MILLENIUM=y
2257CONFIG_FB_MATROX_MYSTIQUE=y
2258CONFIG_FB_MATROX_G=y
2259CONFIG_FB_MATROX_I2C=m
2260CONFIG_FB_MATROX_MAVEN=m
2261CONFIG_FB_MATROX_MULTIHEAD=y
2262CONFIG_FB_RADEON=m
2263CONFIG_FB_RADEON_I2C=y
2264CONFIG_FB_RADEON_BACKLIGHT=y
2265# CONFIG_FB_RADEON_DEBUG is not set
2266CONFIG_FB_ATY128=m
2267CONFIG_FB_ATY128_BACKLIGHT=y
2268CONFIG_FB_ATY=m
2269CONFIG_FB_ATY_CT=y
2270CONFIG_FB_ATY_GENERIC_LCD=y
2271CONFIG_FB_ATY_GX=y
2272CONFIG_FB_ATY_BACKLIGHT=y
2273# CONFIG_FB_S3 is not set
2274CONFIG_FB_SAVAGE=m
2275CONFIG_FB_SAVAGE_I2C=y
2276CONFIG_FB_SAVAGE_ACCEL=y
2277CONFIG_FB_SIS=m
2278CONFIG_FB_SIS_300=y
2279CONFIG_FB_SIS_315=y
2280CONFIG_FB_NEOMAGIC=m
2281CONFIG_FB_KYRO=m
2282CONFIG_FB_3DFX=m
2283# CONFIG_FB_3DFX_ACCEL is not set
2284CONFIG_FB_VOODOO1=m
2285# CONFIG_FB_VT8623 is not set
2286CONFIG_FB_TRIDENT=m
2287# CONFIG_FB_TRIDENT_ACCEL is not set
2288# CONFIG_FB_ARK is not set
2289# CONFIG_FB_PM3 is not set
2290# CONFIG_FB_VIRTUAL is not set
2291
2292#
2293# Console display driver support
2294#
2295CONFIG_VGA_CONSOLE=y
2296# CONFIG_VGACON_SOFT_SCROLLBACK is not set
2297CONFIG_DUMMY_CONSOLE=y
2298CONFIG_FRAMEBUFFER_CONSOLE=m
2299# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
2300# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
2301# CONFIG_FONTS is not set
2302CONFIG_FONT_8x8=y
2303CONFIG_FONT_8x16=y
2304# CONFIG_LOGO is not set
2305
2306#
2307# Sound
2308#
2309CONFIG_SOUND=m
2310
2311#
2312# Advanced Linux Sound Architecture
2313#
2314CONFIG_SND=m
2315CONFIG_SND_TIMER=m
2316CONFIG_SND_PCM=m
2317CONFIG_SND_HWDEP=m
2318CONFIG_SND_RAWMIDI=m
2319CONFIG_SND_SEQUENCER=m
2320CONFIG_SND_SEQ_DUMMY=m
2321CONFIG_SND_OSSEMUL=y
2322CONFIG_SND_MIXER_OSS=m
2323CONFIG_SND_PCM_OSS=m
2324CONFIG_SND_PCM_OSS_PLUGINS=y
2325CONFIG_SND_SEQUENCER_OSS=y
2326CONFIG_SND_RTCTIMER=m
2327CONFIG_SND_SEQ_RTCTIMER_DEFAULT=y
2328CONFIG_SND_DYNAMIC_MINORS=y
2329CONFIG_SND_SUPPORT_OLD_API=y
2330CONFIG_SND_VERBOSE_PROCFS=y
2331# CONFIG_SND_VERBOSE_PRINTK is not set
2332# CONFIG_SND_DEBUG is not set
2333
2334#
2335# Generic devices
2336#
2337CONFIG_SND_MPU401_UART=m
2338CONFIG_SND_OPL3_LIB=m
2339CONFIG_SND_VX_LIB=m
2340CONFIG_SND_AC97_CODEC=m
2341CONFIG_SND_DUMMY=m
2342CONFIG_SND_VIRMIDI=m
2343CONFIG_SND_MTPAV=m
2344CONFIG_SND_MTS64=m
2345CONFIG_SND_SERIAL_U16550=m
2346CONFIG_SND_MPU401=m
2347# CONFIG_SND_PORTMAN2X4 is not set
2348
2349#
2350# PCI devices
2351#
2352CONFIG_SND_AD1889=m
2353CONFIG_SND_ALS300=m
2354CONFIG_SND_ALI5451=m
2355CONFIG_SND_ATIIXP=m
2356CONFIG_SND_ATIIXP_MODEM=m
2357CONFIG_SND_AU8810=m
2358CONFIG_SND_AU8820=m
2359CONFIG_SND_AU8830=m
2360CONFIG_SND_AZT3328=m
2361CONFIG_SND_BT87X=m
2362# CONFIG_SND_BT87X_OVERCLOCK is not set
2363CONFIG_SND_CA0106=m
2364CONFIG_SND_CMIPCI=m
2365CONFIG_SND_CS4281=m
2366CONFIG_SND_CS46XX=m
2367CONFIG_SND_CS46XX_NEW_DSP=y
2368CONFIG_SND_DARLA20=m
2369CONFIG_SND_GINA20=m
2370CONFIG_SND_LAYLA20=m
2371CONFIG_SND_DARLA24=m
2372CONFIG_SND_GINA24=m
2373CONFIG_SND_LAYLA24=m
2374CONFIG_SND_MONA=m
2375CONFIG_SND_MIA=m
2376CONFIG_SND_ECHO3G=m
2377CONFIG_SND_INDIGO=m
2378CONFIG_SND_INDIGOIO=m
2379CONFIG_SND_INDIGODJ=m
2380CONFIG_SND_EMU10K1=m
2381CONFIG_SND_EMU10K1X=m
2382CONFIG_SND_ENS1370=m
2383CONFIG_SND_ENS1371=m
2384CONFIG_SND_ES1938=m
2385CONFIG_SND_ES1968=m
2386CONFIG_SND_FM801=m
2387CONFIG_SND_FM801_TEA575X_BOOL=y
2388CONFIG_SND_FM801_TEA575X=m
2389CONFIG_SND_HDA_INTEL=m
2390CONFIG_SND_HDSP=m
2391CONFIG_SND_HDSPM=m
2392CONFIG_SND_ICE1712=m
2393CONFIG_SND_ICE1724=m
2394CONFIG_SND_INTEL8X0=m
2395CONFIG_SND_INTEL8X0M=m
2396CONFIG_SND_KORG1212=m
2397CONFIG_SND_KORG1212_FIRMWARE_IN_KERNEL=y
2398CONFIG_SND_MAESTRO3=m
2399CONFIG_SND_MAESTRO3_FIRMWARE_IN_KERNEL=y
2400CONFIG_SND_MIXART=m
2401CONFIG_SND_NM256=m
2402CONFIG_SND_PCXHR=m
2403CONFIG_SND_RIPTIDE=m
2404CONFIG_SND_RME32=m
2405CONFIG_SND_RME96=m
2406CONFIG_SND_RME9652=m
2407CONFIG_SND_SONICVIBES=m
2408CONFIG_SND_TRIDENT=m
2409CONFIG_SND_VIA82XX=m
2410CONFIG_SND_VIA82XX_MODEM=m
2411CONFIG_SND_VX222=m
2412CONFIG_SND_YMFPCI=m
2413CONFIG_SND_YMFPCI_FIRMWARE_IN_KERNEL=y
2414# CONFIG_SND_AC97_POWER_SAVE is not set
2415
2416#
2417# ALSA MIPS devices
2418#
2419# CONFIG_SND_AU1X00 is not set
2420
2421#
2422# USB devices
2423#
2424CONFIG_SND_USB_AUDIO=m
2425# CONFIG_SND_USB_CAIAQ is not set
2426
2427#
2428# PCMCIA devices
2429#
2430CONFIG_SND_VXPOCKET=m
2431CONFIG_SND_PDAUDIOCF=m
2432
2433#
2434# System on Chip audio support
2435#
2436# CONFIG_SND_SOC is not set
2437
2438#
2439# SoC Audio support for SuperH
2440#
2441
2442#
2443# Open Sound System
2444#
2445CONFIG_SOUND_PRIME=m
2446CONFIG_SOUND_TRIDENT=m
2447# CONFIG_SOUND_MSNDCLAS is not set
2448# CONFIG_SOUND_MSNDPIN is not set
2449CONFIG_AC97_BUS=m
2450CONFIG_HID_SUPPORT=y
2451CONFIG_HID=y
2452# CONFIG_HID_DEBUG is not set
2453
2454#
2455# USB Input Devices
2456#
2457CONFIG_USB_HID=m
2458CONFIG_USB_HIDINPUT_POWERBOOK=y
2459# CONFIG_HID_FF is not set
2460CONFIG_USB_HIDDEV=y
2461
2462#
2463# USB HID Boot Protocol drivers
2464#
2465CONFIG_USB_KBD=m
2466CONFIG_USB_MOUSE=m
2467CONFIG_USB_SUPPORT=y
2468CONFIG_USB_ARCH_HAS_HCD=y
2469CONFIG_USB_ARCH_HAS_OHCI=y
2470CONFIG_USB_ARCH_HAS_EHCI=y
2471CONFIG_USB=m
2472# CONFIG_USB_DEBUG is not set
2473
2474#
2475# Miscellaneous USB options
2476#
2477CONFIG_USB_DEVICEFS=y
2478CONFIG_USB_DEVICE_CLASS=y
2479# CONFIG_USB_DYNAMIC_MINORS is not set
2480CONFIG_USB_SUSPEND=y
2481# CONFIG_USB_PERSIST is not set
2482# CONFIG_USB_OTG is not set
2483
2484#
2485# USB Host Controller Drivers
2486#
2487CONFIG_USB_EHCI_HCD=m
2488CONFIG_USB_EHCI_SPLIT_ISO=y
2489CONFIG_USB_EHCI_ROOT_HUB_TT=y
2490CONFIG_USB_EHCI_TT_NEWSCHED=y
2491# CONFIG_USB_ISP116X_HCD is not set
2492CONFIG_USB_OHCI_HCD=m
2493# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
2494# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
2495CONFIG_USB_OHCI_LITTLE_ENDIAN=y
2496CONFIG_USB_UHCI_HCD=m
2497CONFIG_USB_U132_HCD=m
2498CONFIG_USB_SL811_HCD=m
2499CONFIG_USB_SL811_CS=m
2500# CONFIG_USB_R8A66597_HCD is not set
2501
2502#
2503# USB Device Class drivers
2504#
2505CONFIG_USB_ACM=m
2506CONFIG_USB_PRINTER=m
2507
2508#
2509# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
2510#
2511
2512#
2513# may also be needed; see USB_STORAGE Help for more information
2514#
2515CONFIG_USB_STORAGE=m
2516# CONFIG_USB_STORAGE_DEBUG is not set
2517CONFIG_USB_STORAGE_DATAFAB=y
2518CONFIG_USB_STORAGE_FREECOM=y
2519CONFIG_USB_STORAGE_ISD200=y
2520CONFIG_USB_STORAGE_DPCM=y
2521CONFIG_USB_STORAGE_USBAT=y
2522CONFIG_USB_STORAGE_SDDR09=y
2523CONFIG_USB_STORAGE_SDDR55=y
2524CONFIG_USB_STORAGE_JUMPSHOT=y
2525CONFIG_USB_STORAGE_ALAUDA=y
2526CONFIG_USB_STORAGE_KARMA=y
2527CONFIG_USB_LIBUSUAL=y
2528
2529#
2530# USB Imaging devices
2531#
2532CONFIG_USB_MDC800=m
2533CONFIG_USB_MICROTEK=m
2534CONFIG_USB_MON=y
2535
2536#
2537# USB port drivers
2538#
2539CONFIG_USB_USS720=m
2540
2541#
2542# USB Serial Converter support
2543#
2544CONFIG_USB_SERIAL=m
2545CONFIG_USB_SERIAL_GENERIC=y
2546CONFIG_USB_SERIAL_AIRCABLE=m
2547CONFIG_USB_SERIAL_AIRPRIME=m
2548CONFIG_USB_SERIAL_ARK3116=m
2549CONFIG_USB_SERIAL_BELKIN=m
2550CONFIG_USB_SERIAL_WHITEHEAT=m
2551CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
2552CONFIG_USB_SERIAL_CP2101=m
2553CONFIG_USB_SERIAL_CYPRESS_M8=m
2554CONFIG_USB_SERIAL_EMPEG=m
2555CONFIG_USB_SERIAL_FTDI_SIO=m
2556CONFIG_USB_SERIAL_FUNSOFT=m
2557CONFIG_USB_SERIAL_VISOR=m
2558CONFIG_USB_SERIAL_IPAQ=m
2559CONFIG_USB_SERIAL_IR=m
2560CONFIG_USB_SERIAL_EDGEPORT=m
2561CONFIG_USB_SERIAL_EDGEPORT_TI=m
2562CONFIG_USB_SERIAL_GARMIN=m
2563CONFIG_USB_SERIAL_IPW=m
2564CONFIG_USB_SERIAL_KEYSPAN_PDA=m
2565CONFIG_USB_SERIAL_KEYSPAN=m
2566# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
2567# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
2568# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
2569# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
2570# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
2571# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
2572# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
2573# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
2574# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
2575# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
2576# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
2577# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
2578CONFIG_USB_SERIAL_KLSI=m
2579CONFIG_USB_SERIAL_KOBIL_SCT=m
2580CONFIG_USB_SERIAL_MCT_U232=m
2581CONFIG_USB_SERIAL_MOS7720=m
2582CONFIG_USB_SERIAL_MOS7840=m
2583CONFIG_USB_SERIAL_NAVMAN=m
2584CONFIG_USB_SERIAL_PL2303=m
2585# CONFIG_USB_SERIAL_OTI6858 is not set
2586CONFIG_USB_SERIAL_HP4X=m
2587CONFIG_USB_SERIAL_SAFE=m
2588# CONFIG_USB_SERIAL_SAFE_PADDED is not set
2589CONFIG_USB_SERIAL_SIERRAWIRELESS=m
2590CONFIG_USB_SERIAL_TI=m
2591CONFIG_USB_SERIAL_CYBERJACK=m
2592CONFIG_USB_SERIAL_XIRCOM=m
2593CONFIG_USB_SERIAL_OPTION=m
2594CONFIG_USB_SERIAL_OMNINET=m
2595# CONFIG_USB_SERIAL_DEBUG is not set
2596CONFIG_USB_EZUSB=y
2597
2598#
2599# USB Miscellaneous drivers
2600#
2601CONFIG_USB_EMI62=m
2602CONFIG_USB_EMI26=m
2603CONFIG_USB_ADUTUX=m
2604CONFIG_USB_AUERSWALD=m
2605CONFIG_USB_RIO500=m
2606CONFIG_USB_LEGOTOWER=m
2607CONFIG_USB_LCD=m
2608# CONFIG_USB_BERRY_CHARGE is not set
2609CONFIG_USB_LED=m
2610CONFIG_USB_CYPRESS_CY7C63=m
2611CONFIG_USB_CYTHERM=m
2612CONFIG_USB_PHIDGET=m
2613CONFIG_USB_PHIDGETKIT=m
2614CONFIG_USB_PHIDGETMOTORCONTROL=m
2615CONFIG_USB_PHIDGETSERVO=m
2616CONFIG_USB_IDMOUSE=m
2617CONFIG_USB_FTDI_ELAN=m
2618CONFIG_USB_APPLEDISPLAY=m
2619CONFIG_USB_SISUSBVGA=m
2620# CONFIG_USB_SISUSBVGA_CON is not set
2621CONFIG_USB_LD=m
2622CONFIG_USB_TRANCEVIBRATOR=m
2623# CONFIG_USB_IOWARRIOR is not set
2624CONFIG_USB_TEST=m
2625
2626#
2627# USB DSL modem support
2628#
2629CONFIG_USB_ATM=m
2630CONFIG_USB_SPEEDTOUCH=m
2631CONFIG_USB_CXACRU=m
2632CONFIG_USB_UEAGLEATM=m
2633CONFIG_USB_XUSBATM=m
2634
2635#
2636# USB Gadget Support
2637#
2638CONFIG_USB_GADGET=m
2639# CONFIG_USB_GADGET_DEBUG_FILES is not set
2640CONFIG_USB_GADGET_SELECTED=y
2641# CONFIG_USB_GADGET_AMD5536UDC is not set
2642# CONFIG_USB_GADGET_FSL_USB2 is not set
2643CONFIG_USB_GADGET_NET2280=y
2644CONFIG_USB_NET2280=m
2645# CONFIG_USB_GADGET_PXA2XX is not set
2646# CONFIG_USB_GADGET_M66592 is not set
2647# CONFIG_USB_GADGET_GOKU is not set
2648# CONFIG_USB_GADGET_LH7A40X is not set
2649# CONFIG_USB_GADGET_OMAP is not set
2650# CONFIG_USB_GADGET_S3C2410 is not set
2651# CONFIG_USB_GADGET_AT91 is not set
2652# CONFIG_USB_GADGET_DUMMY_HCD is not set
2653CONFIG_USB_GADGET_DUALSPEED=y
2654CONFIG_USB_ZERO=m
2655CONFIG_USB_ETH=m
2656CONFIG_USB_ETH_RNDIS=y
2657CONFIG_USB_GADGETFS=m
2658CONFIG_USB_FILE_STORAGE=m
2659# CONFIG_USB_FILE_STORAGE_TEST is not set
2660CONFIG_USB_G_SERIAL=m
2661CONFIG_USB_MIDI_GADGET=m
2662CONFIG_MMC=m
2663# CONFIG_MMC_DEBUG is not set
2664# CONFIG_MMC_UNSAFE_RESUME is not set
2665
2666#
2667# MMC/SD Card Drivers
2668#
2669CONFIG_MMC_BLOCK=m
2670CONFIG_MMC_BLOCK_BOUNCE=y
2671
2672#
2673# MMC/SD Host Controller Drivers
2674#
2675CONFIG_MMC_SDHCI=m
2676CONFIG_MMC_TIFM_SD=m
2677CONFIG_NEW_LEDS=y
2678CONFIG_LEDS_CLASS=m
2679
2680#
2681# LED drivers
2682#
2683
2684#
2685# LED Triggers
2686#
2687# CONFIG_LEDS_TRIGGERS is not set
2688CONFIG_INFINIBAND=m
2689CONFIG_INFINIBAND_USER_MAD=m
2690CONFIG_INFINIBAND_USER_ACCESS=m
2691CONFIG_INFINIBAND_USER_MEM=y
2692CONFIG_INFINIBAND_ADDR_TRANS=y
2693CONFIG_INFINIBAND_MTHCA=m
2694CONFIG_INFINIBAND_MTHCA_DEBUG=y
2695CONFIG_INFINIBAND_AMSO1100=m
2696CONFIG_INFINIBAND_AMSO1100_DEBUG=y
2697# CONFIG_MLX4_INFINIBAND is not set
2698CONFIG_INFINIBAND_IPOIB=m
2699# CONFIG_INFINIBAND_IPOIB_CM is not set
2700CONFIG_INFINIBAND_IPOIB_DEBUG=y
2701# CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set
2702CONFIG_INFINIBAND_SRP=m
2703CONFIG_INFINIBAND_ISER=m
2704CONFIG_RTC_LIB=m
2705CONFIG_RTC_CLASS=m
2706
2707#
2708# RTC interfaces
2709#
2710CONFIG_RTC_INTF_SYSFS=y
2711CONFIG_RTC_INTF_PROC=y
2712CONFIG_RTC_INTF_DEV=y
2713CONFIG_RTC_INTF_DEV_UIE_EMUL=y
2714CONFIG_RTC_DRV_TEST=m
2715
2716#
2717# I2C RTC drivers
2718#
2719CONFIG_RTC_DRV_DS1307=m
2720CONFIG_RTC_DRV_DS1672=m
2721# CONFIG_RTC_DRV_MAX6900 is not set
2722CONFIG_RTC_DRV_RS5C372=m
2723CONFIG_RTC_DRV_ISL1208=m
2724CONFIG_RTC_DRV_X1205=m
2725CONFIG_RTC_DRV_PCF8563=m
2726CONFIG_RTC_DRV_PCF8583=m
2727# CONFIG_RTC_DRV_M41T80 is not set
2728
2729#
2730# SPI RTC drivers
2731#
2732CONFIG_RTC_DRV_RS5C348=m
2733CONFIG_RTC_DRV_MAX6902=m
2734
2735#
2736# Platform RTC drivers
2737#
2738# CONFIG_RTC_DRV_CMOS is not set
2739CONFIG_RTC_DRV_DS1553=m
2740# CONFIG_RTC_DRV_STK17TA8 is not set
2741CONFIG_RTC_DRV_DS1742=m
2742CONFIG_RTC_DRV_M48T86=m
2743# CONFIG_RTC_DRV_M48T59 is not set
2744CONFIG_RTC_DRV_V3020=m
2745
2746#
2747# on-CPU RTC drivers
2748#
2749
2750#
2751# DMA Engine support
2752#
2753CONFIG_DMA_ENGINE=y
2754
2755#
2756# DMA Clients
2757#
2758CONFIG_NET_DMA=y
2759
2760#
2761# DMA Devices
2762#
2763CONFIG_INTEL_IOATDMA=m
2764# CONFIG_AUXDISPLAY is not set
2765
2766#
2767# Userspace I/O
2768#
2769# CONFIG_UIO is not set
2770
2771#
2772# File systems
2773#
2774CONFIG_EXT2_FS=m
2775CONFIG_EXT2_FS_XATTR=y
2776CONFIG_EXT2_FS_POSIX_ACL=y
2777CONFIG_EXT2_FS_SECURITY=y
2778# CONFIG_EXT2_FS_XIP is not set
2779CONFIG_EXT3_FS=m
2780CONFIG_EXT3_FS_XATTR=y
2781CONFIG_EXT3_FS_POSIX_ACL=y
2782CONFIG_EXT3_FS_SECURITY=y
2783# CONFIG_EXT4DEV_FS is not set
2784CONFIG_JBD=m
2785# CONFIG_JBD_DEBUG is not set
2786CONFIG_FS_MBCACHE=m
2787CONFIG_REISERFS_FS=m
2788# CONFIG_REISERFS_CHECK is not set
2789# CONFIG_REISERFS_PROC_INFO is not set
2790CONFIG_REISERFS_FS_XATTR=y
2791CONFIG_REISERFS_FS_POSIX_ACL=y
2792CONFIG_REISERFS_FS_SECURITY=y
2793CONFIG_JFS_FS=m
2794CONFIG_JFS_POSIX_ACL=y
2795CONFIG_JFS_SECURITY=y
2796# CONFIG_JFS_DEBUG is not set
2797CONFIG_JFS_STATISTICS=y
2798CONFIG_FS_POSIX_ACL=y
2799CONFIG_XFS_FS=m
2800CONFIG_XFS_QUOTA=y
2801CONFIG_XFS_SECURITY=y
2802CONFIG_XFS_POSIX_ACL=y
2803CONFIG_XFS_RT=y
2804# CONFIG_GFS2_FS is not set
2805# CONFIG_OCFS2_FS is not set
2806CONFIG_MINIX_FS=m
2807CONFIG_ROMFS_FS=m
2808CONFIG_INOTIFY=y
2809CONFIG_INOTIFY_USER=y
2810CONFIG_QUOTA=y
2811CONFIG_QFMT_V1=m
2812CONFIG_QFMT_V2=m
2813CONFIG_QUOTACTL=y
2814CONFIG_DNOTIFY=y
2815CONFIG_AUTOFS_FS=m
2816CONFIG_AUTOFS4_FS=m
2817CONFIG_FUSE_FS=m
2818
2819#
2820# CD-ROM/DVD Filesystems
2821#
2822CONFIG_ISO9660_FS=m
2823CONFIG_JOLIET=y
2824CONFIG_ZISOFS=y
2825CONFIG_UDF_FS=m
2826CONFIG_UDF_NLS=y
2827
2828#
2829# DOS/FAT/NT Filesystems
2830#
2831CONFIG_FAT_FS=m
2832CONFIG_MSDOS_FS=m
2833CONFIG_VFAT_FS=m
2834CONFIG_FAT_DEFAULT_CODEPAGE=437
2835CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
2836CONFIG_NTFS_FS=m
2837# CONFIG_NTFS_DEBUG is not set
2838# CONFIG_NTFS_RW is not set
2839
2840#
2841# Pseudo filesystems
2842#
2843CONFIG_PROC_FS=y
2844CONFIG_PROC_KCORE=y
2845CONFIG_PROC_SYSCTL=y
2846CONFIG_SYSFS=y
2847CONFIG_TMPFS=y
2848# CONFIG_TMPFS_POSIX_ACL is not set
2849# CONFIG_HUGETLB_PAGE is not set
2850CONFIG_RAMFS=y
2851CONFIG_CONFIGFS_FS=m
2852
2853#
2854# Miscellaneous filesystems
2855#
2856CONFIG_ADFS_FS=m
2857# CONFIG_ADFS_FS_RW is not set
2858CONFIG_AFFS_FS=m
2859CONFIG_ECRYPT_FS=m
2860CONFIG_HFS_FS=m
2861CONFIG_HFSPLUS_FS=m
2862CONFIG_BEFS_FS=m
2863# CONFIG_BEFS_DEBUG is not set
2864CONFIG_BFS_FS=m
2865CONFIG_EFS_FS=m
2866CONFIG_JFFS2_FS=m
2867CONFIG_JFFS2_FS_DEBUG=0
2868CONFIG_JFFS2_FS_WRITEBUFFER=y
2869# CONFIG_JFFS2_SUMMARY is not set
2870# CONFIG_JFFS2_FS_XATTR is not set
2871# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
2872CONFIG_JFFS2_ZLIB=y
2873CONFIG_JFFS2_RTIME=y
2874# CONFIG_JFFS2_RUBIN is not set
2875CONFIG_CRAMFS=y
2876CONFIG_VXFS_FS=m
2877CONFIG_HPFS_FS=m
2878CONFIG_QNX4FS_FS=m
2879CONFIG_SYSV_FS=m
2880CONFIG_UFS_FS=m
2881# CONFIG_UFS_FS_WRITE is not set
2882# CONFIG_UFS_DEBUG is not set
2883
2884#
2885# Network File Systems
2886#
2887CONFIG_NFS_FS=m
2888CONFIG_NFS_V3=y
2889# CONFIG_NFS_V3_ACL is not set
2890CONFIG_NFS_V4=y
2891CONFIG_NFS_DIRECTIO=y
2892CONFIG_NFSD=m
2893CONFIG_NFSD_V3=y
2894# CONFIG_NFSD_V3_ACL is not set
2895CONFIG_NFSD_V4=y
2896CONFIG_NFSD_TCP=y
2897CONFIG_LOCKD=m
2898CONFIG_LOCKD_V4=y
2899CONFIG_EXPORTFS=m
2900CONFIG_NFS_COMMON=y
2901CONFIG_SUNRPC=m
2902CONFIG_SUNRPC_GSS=m
2903# CONFIG_SUNRPC_BIND34 is not set
2904CONFIG_RPCSEC_GSS_KRB5=m
2905CONFIG_RPCSEC_GSS_SPKM3=m
2906CONFIG_SMB_FS=m
2907# CONFIG_SMB_NLS_DEFAULT is not set
2908CONFIG_CIFS=m
2909# CONFIG_CIFS_STATS is not set
2910# CONFIG_CIFS_WEAK_PW_HASH is not set
2911# CONFIG_CIFS_XATTR is not set
2912# CONFIG_CIFS_DEBUG2 is not set
2913# CONFIG_CIFS_EXPERIMENTAL is not set
2914CONFIG_NCP_FS=m
2915CONFIG_NCPFS_PACKET_SIGNING=y
2916CONFIG_NCPFS_IOCTL_LOCKING=y
2917CONFIG_NCPFS_STRONG=y
2918CONFIG_NCPFS_NFS_NS=y
2919CONFIG_NCPFS_OS2_NS=y
2920# CONFIG_NCPFS_SMALLDOS is not set
2921CONFIG_NCPFS_NLS=y
2922CONFIG_NCPFS_EXTRAS=y
2923CONFIG_CODA_FS=m
2924# CONFIG_CODA_FS_OLD_API is not set
2925CONFIG_AFS_FS=m
2926# CONFIG_AFS_DEBUG is not set
2927
2928#
2929# Partition Types
2930#
2931CONFIG_PARTITION_ADVANCED=y
2932CONFIG_ACORN_PARTITION=y
2933# CONFIG_ACORN_PARTITION_CUMANA is not set
2934# CONFIG_ACORN_PARTITION_EESOX is not set
2935CONFIG_ACORN_PARTITION_ICS=y
2936# CONFIG_ACORN_PARTITION_ADFS is not set
2937# CONFIG_ACORN_PARTITION_POWERTEC is not set
2938CONFIG_ACORN_PARTITION_RISCIX=y
2939CONFIG_OSF_PARTITION=y
2940CONFIG_AMIGA_PARTITION=y
2941CONFIG_ATARI_PARTITION=y
2942CONFIG_MAC_PARTITION=y
2943CONFIG_MSDOS_PARTITION=y
2944CONFIG_BSD_DISKLABEL=y
2945CONFIG_MINIX_SUBPARTITION=y
2946CONFIG_SOLARIS_X86_PARTITION=y
2947CONFIG_UNIXWARE_DISKLABEL=y
2948CONFIG_LDM_PARTITION=y
2949# CONFIG_LDM_DEBUG is not set
2950CONFIG_SGI_PARTITION=y
2951CONFIG_ULTRIX_PARTITION=y
2952CONFIG_SUN_PARTITION=y
2953CONFIG_KARMA_PARTITION=y
2954CONFIG_EFI_PARTITION=y
2955# CONFIG_SYSV68_PARTITION is not set
2956
2957#
2958# Native Language Support
2959#
2960CONFIG_NLS=y
2961CONFIG_NLS_DEFAULT="cp437"
2962CONFIG_NLS_CODEPAGE_437=m
2963CONFIG_NLS_CODEPAGE_737=m
2964CONFIG_NLS_CODEPAGE_775=m
2965CONFIG_NLS_CODEPAGE_850=m
2966CONFIG_NLS_CODEPAGE_852=m
2967CONFIG_NLS_CODEPAGE_855=m
2968CONFIG_NLS_CODEPAGE_857=m
2969CONFIG_NLS_CODEPAGE_860=m
2970CONFIG_NLS_CODEPAGE_861=m
2971CONFIG_NLS_CODEPAGE_862=m
2972CONFIG_NLS_CODEPAGE_863=m
2973CONFIG_NLS_CODEPAGE_864=m
2974CONFIG_NLS_CODEPAGE_865=m
2975CONFIG_NLS_CODEPAGE_866=m
2976CONFIG_NLS_CODEPAGE_869=m
2977CONFIG_NLS_CODEPAGE_936=m
2978CONFIG_NLS_CODEPAGE_950=m
2979CONFIG_NLS_CODEPAGE_932=m
2980CONFIG_NLS_CODEPAGE_949=m
2981CONFIG_NLS_CODEPAGE_874=m
2982CONFIG_NLS_ISO8859_8=m
2983CONFIG_NLS_CODEPAGE_1250=m
2984CONFIG_NLS_CODEPAGE_1251=m
2985CONFIG_NLS_ASCII=m
2986CONFIG_NLS_ISO8859_1=m
2987CONFIG_NLS_ISO8859_2=m
2988CONFIG_NLS_ISO8859_3=m
2989CONFIG_NLS_ISO8859_4=m
2990CONFIG_NLS_ISO8859_5=m
2991CONFIG_NLS_ISO8859_6=m
2992CONFIG_NLS_ISO8859_7=m
2993CONFIG_NLS_ISO8859_9=m
2994CONFIG_NLS_ISO8859_13=m
2995CONFIG_NLS_ISO8859_14=m
2996CONFIG_NLS_ISO8859_15=m
2997CONFIG_NLS_KOI8_R=m
2998CONFIG_NLS_KOI8_U=m
2999CONFIG_NLS_UTF8=m
3000
3001#
3002# Distributed Lock Manager
3003#
3004CONFIG_DLM=m
3005# CONFIG_DLM_DEBUG is not set
3006
3007#
3008# Profiling support
3009#
3010CONFIG_PROFILING=y
3011CONFIG_OPROFILE=m
3012
3013#
3014# Kernel hacking
3015#
3016CONFIG_TRACE_IRQFLAGS_SUPPORT=y
3017# CONFIG_PRINTK_TIME is not set
3018# CONFIG_ENABLE_MUST_CHECK is not set
3019CONFIG_MAGIC_SYSRQ=y
3020# CONFIG_UNUSED_SYMBOLS is not set
3021# CONFIG_DEBUG_FS is not set
3022# CONFIG_HEADERS_CHECK is not set
3023# CONFIG_DEBUG_KERNEL is not set
3024# CONFIG_CROSSCOMPILE is not set
3025CONFIG_CMDLINE=""
3026CONFIG_SYS_SUPPORTS_KGDB=y
3027
3028#
3029# Security options
3030#
3031CONFIG_KEYS=y
3032# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
3033CONFIG_SECURITY=y
3034CONFIG_SECURITY_NETWORK=y
3035# CONFIG_SECURITY_NETWORK_XFRM is not set
3036CONFIG_SECURITY_CAPABILITIES=m
3037CONFIG_SECURITY_ROOTPLUG=m
3038CONFIG_SECURITY_SELINUX=y
3039CONFIG_SECURITY_SELINUX_BOOTPARAM=y
3040CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0
3041CONFIG_SECURITY_SELINUX_DISABLE=y
3042CONFIG_SECURITY_SELINUX_DEVELOP=y
3043CONFIG_SECURITY_SELINUX_AVC_STATS=y
3044CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
3045# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
3046# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
3047CONFIG_XOR_BLOCKS=m
3048CONFIG_ASYNC_CORE=m
3049CONFIG_ASYNC_MEMCPY=m
3050CONFIG_ASYNC_XOR=m
3051CONFIG_CRYPTO=y
3052CONFIG_CRYPTO_ALGAPI=y
3053CONFIG_CRYPTO_BLKCIPHER=m
3054CONFIG_CRYPTO_HASH=y
3055CONFIG_CRYPTO_MANAGER=y
3056CONFIG_CRYPTO_HMAC=y
3057# CONFIG_CRYPTO_XCBC is not set
3058CONFIG_CRYPTO_NULL=m
3059CONFIG_CRYPTO_MD4=m
3060CONFIG_CRYPTO_MD5=y
3061CONFIG_CRYPTO_SHA1=m
3062CONFIG_CRYPTO_SHA256=m
3063CONFIG_CRYPTO_SHA512=m
3064CONFIG_CRYPTO_WP512=m
3065CONFIG_CRYPTO_TGR192=m
3066# CONFIG_CRYPTO_GF128MUL is not set
3067CONFIG_CRYPTO_ECB=m
3068CONFIG_CRYPTO_CBC=m
3069CONFIG_CRYPTO_PCBC=m
3070# CONFIG_CRYPTO_LRW is not set
3071# CONFIG_CRYPTO_CRYPTD is not set
3072CONFIG_CRYPTO_DES=m
3073# CONFIG_CRYPTO_FCRYPT is not set
3074CONFIG_CRYPTO_BLOWFISH=m
3075CONFIG_CRYPTO_TWOFISH=m
3076CONFIG_CRYPTO_TWOFISH_COMMON=m
3077CONFIG_CRYPTO_SERPENT=m
3078CONFIG_CRYPTO_AES=m
3079CONFIG_CRYPTO_CAST5=m
3080CONFIG_CRYPTO_CAST6=m
3081CONFIG_CRYPTO_TEA=m
3082CONFIG_CRYPTO_ARC4=m
3083CONFIG_CRYPTO_KHAZAD=m
3084CONFIG_CRYPTO_ANUBIS=m
3085CONFIG_CRYPTO_DEFLATE=m
3086CONFIG_CRYPTO_MICHAEL_MIC=m
3087CONFIG_CRYPTO_CRC32C=m
3088# CONFIG_CRYPTO_CAMELLIA is not set
3089CONFIG_CRYPTO_TEST=m
3090CONFIG_CRYPTO_HW=y
3091
3092#
3093# Library routines
3094#
3095CONFIG_BITREVERSE=y
3096CONFIG_CRC_CCITT=m
3097CONFIG_CRC16=m
3098# CONFIG_CRC_ITU_T is not set
3099CONFIG_CRC32=y
3100# CONFIG_CRC7 is not set
3101CONFIG_LIBCRC32C=m
3102CONFIG_AUDIT_GENERIC=y
3103CONFIG_ZLIB_INFLATE=y
3104CONFIG_ZLIB_DEFLATE=m
3105CONFIG_REED_SOLOMON=m
3106CONFIG_REED_SOLOMON_DEC16=y
3107CONFIG_TEXTSEARCH=y
3108CONFIG_TEXTSEARCH_KMP=m
3109CONFIG_TEXTSEARCH_BM=m
3110CONFIG_TEXTSEARCH_FSM=m
3111CONFIG_PLIST=y
3112CONFIG_HAS_IOMEM=y
3113CONFIG_HAS_IOPORT=y
3114CONFIG_HAS_DMA=y
3115CONFIG_CHECK_SIGNATURE=y
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
index 93f9e8331ad7..3d1b6281d887 100644
--- a/arch/mips/configs/sb1250-swarm_defconfig
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -70,7 +70,6 @@ CONFIG_SIBYTE_HAS_LDT=y
70CONFIG_SIBYTE_CFE=y 70CONFIG_SIBYTE_CFE=y
71# CONFIG_SIBYTE_CFE_CONSOLE is not set 71# CONFIG_SIBYTE_CFE_CONSOLE is not set
72# CONFIG_SIBYTE_BUS_WATCHER is not set 72# CONFIG_SIBYTE_BUS_WATCHER is not set
73# CONFIG_SIBYTE_SB1250_PROF is not set
74# CONFIG_SIBYTE_TBPROF is not set 73# CONFIG_SIBYTE_TBPROF is not set
75CONFIG_RWSEM_GENERIC_SPINLOCK=y 74CONFIG_RWSEM_GENERIC_SPINLOCK=y
76# CONFIG_ARCH_HAS_ILOG2_U32 is not set 75# CONFIG_ARCH_HAS_ILOG2_U32 is not set
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 6d55e8aab668..6a17c9b508ea 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void)
263 */ 263 */
264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) | 264 *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
265 KN03_MCR_CORRECT; 265 KN03_MCR_CORRECT;
266 if (current_cpu_data.cputype == CPU_R4400SC) 266 if (current_cpu_type() == CPU_R4400SC)
267 *mbcs |= KN4K_MB_CSR_EE; 267 *mbcs |= KN4K_MB_CSR_EE;
268 fast_iob(); 268 fast_iob();
269} 269}
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index 7a053aadcd3a..5f04545c3606 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void)
132 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR); 132 volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
133 133
134 /* For KN04 we need to make sure EE (?) is enabled in the MB. */ 134 /* For KN04 we need to make sure EE (?) is enabled in the MB. */
135 if (current_cpu_data.cputype == CPU_R4000SC) 135 if (current_cpu_type() == CPU_R4000SC)
136 *mbcs |= KN4K_MB_CSR_EE; 136 *mbcs |= KN4K_MB_CSR_EE;
137 fast_iob(); 137 fast_iob();
138 138
diff --git a/arch/mips/dec/prom/identify.c b/arch/mips/dec/prom/identify.c
index cd85924e2572..95e26f4bb38f 100644
--- a/arch/mips/dec/prom/identify.c
+++ b/arch/mips/dec/prom/identify.c
@@ -133,9 +133,6 @@ void __init prom_identify_arch(u32 magic)
133 dec_firmrev = (dec_sysid & 0xff00) >> 8; 133 dec_firmrev = (dec_sysid & 0xff00) >> 8;
134 dec_etc = dec_sysid & 0xff; 134 dec_etc = dec_sysid & 0xff;
135 135
136 /* We're obviously one of the DEC machines */
137 mips_machgroup = MACH_GROUP_DEC;
138
139 /* 136 /*
140 * FIXME: This may not be an exhaustive list of DECStations/Servers! 137 * FIXME: This may not be an exhaustive list of DECStations/Servers!
141 * Put all model-specific initialisation calls here. 138 * Put all model-specific initialisation calls here.
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 808c182fd3fa..93f1239af524 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -108,8 +108,8 @@ void __init prom_init(void)
108 108
109 /* Were we compiled with the right CPU option? */ 109 /* Were we compiled with the right CPU option? */
110#if defined(CONFIG_CPU_R3000) 110#if defined(CONFIG_CPU_R3000)
111 if ((current_cpu_data.cputype == CPU_R4000SC) || 111 if ((current_cpu_type() == CPU_R4000SC) ||
112 (current_cpu_data.cputype == CPU_R4400SC)) { 112 (current_cpu_type() == CPU_R4400SC)) {
113 static char r4k_msg[] __initdata = 113 static char r4k_msg[] __initdata =
114 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n"; 114 "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
115 printk(cpu_msg); 115 printk(cpu_msg);
@@ -119,8 +119,8 @@ void __init prom_init(void)
119#endif 119#endif
120 120
121#if defined(CONFIG_CPU_R4X00) 121#if defined(CONFIG_CPU_R4X00)
122 if ((current_cpu_data.cputype == CPU_R3000) || 122 if ((current_cpu_type() == CPU_R3000) ||
123 (current_cpu_data.cputype == CPU_R3000A)) { 123 (current_cpu_type() == CPU_R3000A)) {
124 static char r3k_msg[] __initdata = 124 static char r3k_msg[] __initdata =
125 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n"; 125 "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
126 printk(cpu_msg); 126 printk(cpu_msg);
diff --git a/arch/mips/dec/setup.c b/arch/mips/dec/setup.c
index 3e634f2f5443..bd5431e1f408 100644
--- a/arch/mips/dec/setup.c
+++ b/arch/mips/dec/setup.c
@@ -145,13 +145,9 @@ static void __init dec_be_init(void)
145 } 145 }
146} 146}
147 147
148
149extern void dec_time_init(void);
150
151void __init plat_mem_setup(void) 148void __init plat_mem_setup(void)
152{ 149{
153 board_be_init = dec_be_init; 150 board_be_init = dec_be_init;
154 board_time_init = dec_time_init;
155 151
156 wbflush_setup(); 152 wbflush_setup();
157 153
diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 8b7e0c17ac35..820e5331205f 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -24,7 +24,6 @@
24 24
25#include <asm/bootinfo.h> 25#include <asm/bootinfo.h>
26#include <asm/cpu.h> 26#include <asm/cpu.h>
27#include <asm/div64.h>
28#include <asm/io.h> 27#include <asm/io.h>
29#include <asm/irq.h> 28#include <asm/irq.h>
30#include <asm/mipsregs.h> 29#include <asm/mipsregs.h>
@@ -36,7 +35,7 @@
36#include <asm/dec/ioasic_addrs.h> 35#include <asm/dec/ioasic_addrs.h>
37#include <asm/dec/machtype.h> 36#include <asm/dec/machtype.h>
38 37
39static unsigned long dec_rtc_get_time(void) 38unsigned long read_persistent_clock(void)
40{ 39{
41 unsigned int year, mon, day, hour, min, sec, real_year; 40 unsigned int year, mon, day, hour, min, sec, real_year;
42 unsigned long flags; 41 unsigned long flags;
@@ -75,13 +74,13 @@ static unsigned long dec_rtc_get_time(void)
75} 74}
76 75
77/* 76/*
78 * In order to set the CMOS clock precisely, dec_rtc_set_mmss has to 77 * In order to set the CMOS clock precisely, rtc_mips_set_mmss has to
79 * be called 500 ms after the second nowtime has started, because when 78 * be called 500 ms after the second nowtime has started, because when
80 * nowtime is written into the registers of the CMOS clock, it will 79 * nowtime is written into the registers of the CMOS clock, it will
81 * jump to the next second precisely 500 ms later. Check the Dallas 80 * jump to the next second precisely 500 ms later. Check the Dallas
82 * DS1287 data sheet for details. 81 * DS1287 data sheet for details.
83 */ 82 */
84static int dec_rtc_set_mmss(unsigned long nowtime) 83int rtc_mips_set_mmss(unsigned long nowtime)
85{ 84{
86 int retval = 0; 85 int retval = 0;
87 int real_seconds, real_minutes, cmos_minutes; 86 int real_seconds, real_minutes, cmos_minutes;
@@ -140,7 +139,6 @@ static int dec_rtc_set_mmss(unsigned long nowtime)
140 return retval; 139 return retval;
141} 140}
142 141
143
144static int dec_timer_state(void) 142static int dec_timer_state(void)
145{ 143{
146 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0; 144 return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
@@ -161,11 +159,8 @@ static cycle_t dec_ioasic_hpt_read(void)
161} 159}
162 160
163 161
164void __init dec_time_init(void) 162void __init plat_time_init(void)
165{ 163{
166 rtc_mips_get_time = dec_rtc_get_time;
167 rtc_mips_set_mmss = dec_rtc_set_mmss;
168
169 mips_timer_state = dec_timer_state; 164 mips_timer_state = dec_timer_state;
170 mips_timer_ack = dec_timer_ack; 165 mips_timer_ack = dec_timer_ack;
171 166
diff --git a/arch/mips/emma2rh/common/prom.c b/arch/mips/emma2rh/common/prom.c
index 7433bd8e5562..0f791eb6bb66 100644
--- a/arch/mips/emma2rh/common/prom.c
+++ b/arch/mips/emma2rh/common/prom.c
@@ -62,8 +62,6 @@ void __init prom_init(void)
62 strcat(arcs_cmdline, " "); 62 strcat(arcs_cmdline, " ");
63 } 63 }
64 64
65 mips_machgroup = MACH_GROUP_NEC_EMMA2RH;
66
67#if defined(CONFIG_MARKEINS) 65#if defined(CONFIG_MARKEINS)
68 mips_machtype = MACH_NEC_MARKEINS; 66 mips_machtype = MACH_NEC_MARKEINS;
69 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM); 67 add_memory_region(0, EMMA2RH_RAM_SIZE, BOOT_MEM_RAM);
diff --git a/arch/mips/emma2rh/markeins/setup.c b/arch/mips/emma2rh/markeins/setup.c
index 2f060e1ed36c..5e1da53b04a7 100644
--- a/arch/mips/emma2rh/markeins/setup.c
+++ b/arch/mips/emma2rh/markeins/setup.c
@@ -88,7 +88,7 @@ static unsigned int __init detect_bus_frequency(unsigned long rtc_base)
88 return clock[reg]; 88 return clock[reg];
89} 89}
90 90
91static void __init emma2rh_time_init(void) 91void __init plat_time_init(void)
92{ 92{
93 u32 reg; 93 u32 reg;
94 if (bus_frequency == 0) 94 if (bus_frequency == 0)
@@ -124,8 +124,6 @@ void __init plat_mem_setup(void)
124 124
125 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE)); 125 set_io_port_base(KSEG1ADDR(EMMA2RH_PCI_IO_BASE));
126 126
127 board_time_init = emma2rh_time_init;
128
129 _machine_restart = markeins_machine_restart; 127 _machine_restart = markeins_machine_restart;
130 _machine_halt = markeins_machine_halt; 128 _machine_halt = markeins_machine_halt;
131 pm_power_off = markeins_machine_power_off; 129 pm_power_off = markeins_machine_power_off;
diff --git a/arch/mips/arc/Makefile b/arch/mips/fw/arc/Makefile
index 4f349ec1ea2d..4f349ec1ea2d 100644
--- a/arch/mips/arc/Makefile
+++ b/arch/mips/fw/arc/Makefile
diff --git a/arch/mips/arc/arc_con.c b/arch/mips/fw/arc/arc_con.c
index bc32fe64f42a..bc32fe64f42a 100644
--- a/arch/mips/arc/arc_con.c
+++ b/arch/mips/fw/arc/arc_con.c
diff --git a/arch/mips/arc/cmdline.c b/arch/mips/fw/arc/cmdline.c
index fd604ef28823..fd604ef28823 100644
--- a/arch/mips/arc/cmdline.c
+++ b/arch/mips/fw/arc/cmdline.c
diff --git a/arch/mips/arc/env.c b/arch/mips/fw/arc/env.c
index e521a6e010aa..6f5dd42b96e2 100644
--- a/arch/mips/arc/env.c
+++ b/arch/mips/fw/arc/env.c
@@ -11,7 +11,7 @@
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/string.h> 12#include <linux/string.h>
13 13
14#include <asm/arc/types.h> 14#include <asm/fw/arc/types.h>
15#include <asm/sgialib.h> 15#include <asm/sgialib.h>
16 16
17PCHAR __init 17PCHAR __init
diff --git a/arch/mips/arc/file.c b/arch/mips/fw/arc/file.c
index cb0127cf5bc1..30335341b447 100644
--- a/arch/mips/arc/file.c
+++ b/arch/mips/fw/arc/file.c
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12 12
13#include <asm/arc/types.h> 13#include <asm/fw/arc/types.h>
14#include <asm/sgialib.h> 14#include <asm/sgialib.h>
15 15
16LONG 16LONG
diff --git a/arch/mips/arc/identify.c b/arch/mips/fw/arc/identify.c
index 4b907369b0f9..28dfd2e2989a 100644
--- a/arch/mips/arc/identify.c
+++ b/arch/mips/fw/arc/identify.c
@@ -22,52 +22,51 @@
22struct smatch { 22struct smatch {
23 char *arcname; 23 char *arcname;
24 char *liname; 24 char *liname;
25 int group;
26 int type; 25 int type;
27 int flags; 26 int flags;
28}; 27};
29 28
30static struct smatch mach_table[] = { 29static struct smatch mach_table[] = {
31 { "SGI-IP22", 30 {
32 "SGI Indy", 31 .arcname = "SGI-IP22",
33 MACH_GROUP_SGI, 32 .liname = "SGI Indy",
34 MACH_SGI_IP22, 33 .type = MACH_SGI_IP22,
35 PROM_FLAG_ARCS 34 .flags = PROM_FLAG_ARCS,
36 }, { "SGI-IP27", 35 }, {
37 "SGI Origin", 36 .arcname = "SGI-IP27",
38 MACH_GROUP_SGI, 37 .liname = "SGI Origin",
39 MACH_SGI_IP27, 38 .type = MACH_SGI_IP27,
40 PROM_FLAG_ARCS 39 .flags = PROM_FLAG_ARCS,
41 }, { "SGI-IP28", 40 }, {
42 "SGI IP28", 41 .arcname = "SGI-IP28",
43 MACH_GROUP_SGI, 42 .liname = "SGI IP28",
44 MACH_SGI_IP28, 43 .type = MACH_SGI_IP28,
45 PROM_FLAG_ARCS 44 .flags = PROM_FLAG_ARCS,
46 }, { "SGI-IP30", 45 }, {
47 "SGI Octane", 46 .arcname = "SGI-IP30",
48 MACH_GROUP_SGI, 47 .liname = "SGI Octane",
49 MACH_SGI_IP30, 48 .type = MACH_SGI_IP30,
50 PROM_FLAG_ARCS 49 .flags = PROM_FLAG_ARCS,
51 }, { "SGI-IP32", 50 }, {
52 "SGI O2", 51 .arcname = "SGI-IP32",
53 MACH_GROUP_SGI, 52 .liname = "SGI O2",
54 MACH_SGI_IP32, 53 .type = MACH_SGI_IP32,
55 PROM_FLAG_ARCS 54 .flags = PROM_FLAG_ARCS,
56 }, { "Microsoft-Jazz", 55 }, {
57 "Jazz MIPS_Magnum_4000", 56 .arcname = "Microsoft-Jazz",
58 MACH_GROUP_JAZZ, 57 .liname = "Jazz MIPS_Magnum_4000",
59 MACH_MIPS_MAGNUM_4000, 58 .type = MACH_MIPS_MAGNUM_4000,
60 0 59 .flags = 0,
61 }, { "PICA-61", 60 }, {
62 "Jazz Acer_PICA_61", 61 .arcname = "PICA-61",
63 MACH_GROUP_JAZZ, 62 .liname = "Jazz Acer_PICA_61",
64 MACH_ACER_PICA_61, 63 .type = MACH_ACER_PICA_61,
65 0 64 .flags = 0,
66 }, { "RM200PCI", 65 }, {
67 "SNI RM200_PCI", 66 .arcname = "RM200PCI",
68 MACH_GROUP_SNI_RM, 67 .liname = "SNI RM200_PCI",
69 MACH_SNI_RM200_PCI, 68 .type = MACH_SNI_RM200_PCI,
70 PROM_FLAG_DONT_FREE_TEMP 69 .flags = PROM_FLAG_DONT_FREE_TEMP,
71 } 70 }
72}; 71};
73 72
@@ -117,7 +116,6 @@ void __init prom_identify_arch(void)
117 mach = string_to_mach(iname); 116 mach = string_to_mach(iname);
118 system_type = mach->liname; 117 system_type = mach->liname;
119 118
120 mips_machgroup = mach->group;
121 mips_machtype = mach->type; 119 mips_machtype = mach->type;
122 prom_flags = mach->flags; 120 prom_flags = mach->flags;
123} 121}
diff --git a/arch/mips/arc/init.c b/arch/mips/fw/arc/init.c
index e2f75b13312f..e2f75b13312f 100644
--- a/arch/mips/arc/init.c
+++ b/arch/mips/fw/arc/init.c
diff --git a/arch/mips/arc/memory.c b/arch/mips/fw/arc/memory.c
index 83d15791ef6a..8b8eea2b6cf6 100644
--- a/arch/mips/arc/memory.c
+++ b/arch/mips/fw/arc/memory.c
@@ -63,7 +63,7 @@ static char *arc_mtypes[8] = {
63 : arc_mtypes[a.arc] 63 : arc_mtypes[a.arc]
64#endif 64#endif
65 65
66static inline int memtype_classify_arcs (union linux_memtypes type) 66static inline int memtype_classify_arcs(union linux_memtypes type)
67{ 67{
68 switch (type.arcs) { 68 switch (type.arcs) {
69 case arcs_fcontig: 69 case arcs_fcontig:
@@ -83,7 +83,7 @@ static inline int memtype_classify_arcs (union linux_memtypes type)
83 while(1); /* Nuke warning. */ 83 while(1); /* Nuke warning. */
84} 84}
85 85
86static inline int memtype_classify_arc (union linux_memtypes type) 86static inline int memtype_classify_arc(union linux_memtypes type)
87{ 87{
88 switch (type.arc) { 88 switch (type.arc) {
89 case arc_free: 89 case arc_free:
@@ -103,7 +103,7 @@ static inline int memtype_classify_arc (union linux_memtypes type)
103 while(1); /* Nuke warning. */ 103 while(1); /* Nuke warning. */
104} 104}
105 105
106static int __init prom_memtype_classify (union linux_memtypes type) 106static int __init prom_memtype_classify(union linux_memtypes type)
107{ 107{
108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */ 108 if (prom_flags & PROM_FLAG_ARCS) /* SGI is ``different'' ... */
109 return memtype_classify_arcs(type); 109 return memtype_classify_arcs(type);
diff --git a/arch/mips/arc/misc.c b/arch/mips/fw/arc/misc.c
index b2e10b9e9452..e527c5fd5a32 100644
--- a/arch/mips/arc/misc.c
+++ b/arch/mips/fw/arc/misc.c
@@ -14,7 +14,7 @@
14 14
15#include <asm/bcache.h> 15#include <asm/bcache.h>
16 16
17#include <asm/arc/types.h> 17#include <asm/fw/arc/types.h>
18#include <asm/sgialib.h> 18#include <asm/sgialib.h>
19#include <asm/bootinfo.h> 19#include <asm/bootinfo.h>
20#include <asm/system.h> 20#include <asm/system.h>
diff --git a/arch/mips/arc/promlib.c b/arch/mips/fw/arc/promlib.c
index c508c00dbb64..c508c00dbb64 100644
--- a/arch/mips/arc/promlib.c
+++ b/arch/mips/fw/arc/promlib.c
diff --git a/arch/mips/arc/salone.c b/arch/mips/fw/arc/salone.c
index e6afb64723d0..e6afb64723d0 100644
--- a/arch/mips/arc/salone.c
+++ b/arch/mips/fw/arc/salone.c
diff --git a/arch/mips/arc/time.c b/arch/mips/fw/arc/time.c
index 299ff2c5c0b5..42138c837d48 100644
--- a/arch/mips/arc/time.c
+++ b/arch/mips/fw/arc/time.c
@@ -9,7 +9,7 @@
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11 11
12#include <asm/arc/types.h> 12#include <asm/fw/arc/types.h>
13#include <asm/sgialib.h> 13#include <asm/sgialib.h>
14 14
15struct linux_tinfo * __init 15struct linux_tinfo * __init
diff --git a/arch/mips/arc/tree.c b/arch/mips/fw/arc/tree.c
index abd1786ea09b..d68e5a59c1f6 100644
--- a/arch/mips/arc/tree.c
+++ b/arch/mips/fw/arc/tree.c
@@ -10,7 +10,7 @@
10 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 1999 Silicon Graphics, Inc.
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/arc/types.h> 13#include <asm/fw/arc/types.h>
14#include <asm/sgialib.h> 14#include <asm/sgialib.h>
15 15
16#undef DEBUG_PROM_TREE 16#undef DEBUG_PROM_TREE
diff --git a/arch/mips/fw/cfe/Makefile b/arch/mips/fw/cfe/Makefile
new file mode 100644
index 000000000000..8f20044c0adf
--- /dev/null
+++ b/arch/mips/fw/cfe/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the Broadcom Common Firmware Environment support
3#
4
5lib-y += cfe_api.o
diff --git a/arch/mips/sibyte/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
index c0213605e18a..a9f69e4e40ac 100644
--- a/arch/mips/sibyte/cfe/cfe_api.c
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -30,7 +30,7 @@
30 * 30 *
31 ********************************************************************* */ 31 ********************************************************************* */
32 32
33#include "cfe_api.h" 33#include <asm/fw/cfe/cfe_api.h>
34#include "cfe_api_int.h" 34#include "cfe_api_int.h"
35 35
36/* Cast from a native pointer to a cfe_xptr_t and back. */ 36/* Cast from a native pointer to a cfe_xptr_t and back. */
diff --git a/arch/mips/sibyte/cfe/cfe_api_int.h b/arch/mips/fw/cfe/cfe_api_int.h
index f7e5a64b55f3..f7e5a64b55f3 100644
--- a/arch/mips/sibyte/cfe/cfe_api_int.h
+++ b/arch/mips/fw/cfe/cfe_api_int.h
diff --git a/arch/mips/gt64120/wrppmc/Makefile b/arch/mips/gt64120/wrppmc/Makefile
index bef15c90ae15..b49d282bee8a 100644
--- a/arch/mips/gt64120/wrppmc/Makefile
+++ b/arch/mips/gt64120/wrppmc/Makefile
@@ -9,6 +9,6 @@
9# Makefile for the Wind River MIPS 4KC PPMC Eval Board 9# Makefile for the Wind River MIPS 4KC PPMC Eval Board
10# 10#
11 11
12obj-y += irq.o reset.o setup.o time.o pci.o 12obj-y += irq.o pci.o reset.o serial.o setup.o time.o
13 13
14EXTRA_CFLAGS += -Werror 14EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/gt64120/wrppmc/irq.c b/arch/mips/gt64120/wrppmc/irq.c
index 06177bf5b1d6..c6e706274db4 100644
--- a/arch/mips/gt64120/wrppmc/irq.c
+++ b/arch/mips/gt64120/wrppmc/irq.c
@@ -9,26 +9,13 @@
9 * Free Software Foundation; either version 2 of the License, or (at your 9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version. 10 * option) any later version.
11 */ 11 */
12#include <linux/errno.h> 12#include <linux/hardirq.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel_stat.h> 14#include <linux/irq.h>
15#include <linux/module.h> 15
16#include <linux/signal.h>
17#include <linux/sched.h>
18#include <linux/types.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/timex.h>
22#include <linux/slab.h>
23#include <linux/random.h>
24#include <linux/bitops.h>
25#include <asm/bootinfo.h>
26#include <asm/io.h>
27#include <asm/bitops.h>
28#include <asm/mipsregs.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/gt64120.h> 16#include <asm/gt64120.h>
17#include <asm/irq_cpu.h>
18#include <asm/mipsregs.h>
32 19
33asmlinkage void plat_irq_dispatch(void) 20asmlinkage void plat_irq_dispatch(void)
34{ 21{
diff --git a/arch/mips/gt64120/wrppmc/pci.c b/arch/mips/gt64120/wrppmc/pci.c
index 0d5289bc1804..d06192faeb7c 100644
--- a/arch/mips/gt64120/wrppmc/pci.c
+++ b/arch/mips/gt64120/wrppmc/pci.c
@@ -8,9 +8,10 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/ioport.h>
11#include <linux/types.h> 12#include <linux/types.h>
12#include <linux/pci.h> 13#include <linux/pci.h>
13#include <linux/kernel.h> 14
14#include <asm/gt64120.h> 15#include <asm/gt64120.h>
15 16
16extern struct pci_ops gt64xxx_pci0_ops; 17extern struct pci_ops gt64xxx_pci0_ops;
diff --git a/arch/mips/gt64120/wrppmc/reset.c b/arch/mips/gt64120/wrppmc/reset.c
index b97039c6d3db..c355cff38f6c 100644
--- a/arch/mips/gt64120/wrppmc/reset.c
+++ b/arch/mips/gt64120/wrppmc/reset.c
@@ -5,14 +5,10 @@
5 * 5 *
6 * Copyright (C) 1997 Ralf Baechle 6 * Copyright (C) 1997 Ralf Baechle
7 */ 7 */
8#include <linux/sched.h> 8#include <linux/kernel.h>
9#include <linux/mm.h> 9
10#include <asm/io.h>
11#include <asm/pgtable.h>
12#include <asm/processor.h>
13#include <asm/reboot.h>
14#include <asm/system.h>
15#include <asm/cacheflush.h> 10#include <asm/cacheflush.h>
11#include <asm/mipsregs.h>
16 12
17void wrppmc_machine_restart(char *command) 13void wrppmc_machine_restart(char *command)
18{ 14{
diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/gt64120/wrppmc/serial.c
new file mode 100644
index 000000000000..5ec1c2ffd3a5
--- /dev/null
+++ b/arch/mips/gt64120/wrppmc/serial.c
@@ -0,0 +1,80 @@
1/*
2 * Registration of WRPPMC UART platform device.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/gt64120.h>
27
28static struct resource wrppmc_uart_resource[] __initdata = {
29 {
30 .start = WRPPMC_UART16550_BASE,
31 .end = WRPPMC_UART16550_BASE + 7,
32 .flags = IORESOURCE_MEM,
33 },
34 {
35 .start = WRPPMC_UART16550_IRQ,
36 .end = WRPPMC_UART16550_IRQ,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct plat_serial8250_port wrppmc_serial8250_port[] = {
42 {
43 .irq = WRPPMC_UART16550_IRQ,
44 .uartclk = WRPPMC_UART16550_CLOCK,
45 .iotype = UPIO_MEM,
46 .flags = UPF_IOREMAP | UPF_SKIP_TEST,
47 .mapbase = WRPPMC_UART16550_BASE,
48 },
49 {},
50};
51
52static __init int wrppmc_uart_add(void)
53{
54 struct platform_device *pdev;
55 int retval;
56
57 pdev = platform_device_alloc("serial8250", -1);
58 if (!pdev)
59 return -ENOMEM;
60
61 pdev->id = PLAT8250_DEV_PLATFORM;
62 pdev->dev.platform_data = wrppmc_serial8250_port;
63
64 retval = platform_device_add_resources(pdev, wrppmc_uart_resource,
65 ARRAY_SIZE(wrppmc_uart_resource));
66 if (retval)
67 goto err_free_device;
68
69 retval = platform_device_add(pdev);
70 if (retval)
71 goto err_free_device;
72
73 return 0;
74
75err_free_device:
76 platform_device_put(pdev);
77
78 return retval;
79}
80device_initcall(wrppmc_uart_add);
diff --git a/arch/mips/gt64120/wrppmc/setup.c b/arch/mips/gt64120/wrppmc/setup.c
index ed58c13b6032..51f6b7862460 100644
--- a/arch/mips/gt64120/wrppmc/setup.c
+++ b/arch/mips/gt64120/wrppmc/setup.c
@@ -11,10 +11,6 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/string.h> 12#include <linux/string.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/tty.h>
15#include <linux/serial.h>
16#include <linux/serial_core.h>
17#include <linux/serial_8250.h>
18#include <linux/pm.h> 14#include <linux/pm.h>
19 15
20#include <asm/io.h> 16#include <asm/io.h>
@@ -98,35 +94,8 @@ void __init prom_free_prom_memory(void)
98{ 94{
99} 95}
100 96
101#ifdef CONFIG_SERIAL_8250
102static void wrppmc_setup_serial(void)
103{
104 struct uart_port up;
105
106 memset(&up, 0x00, sizeof(struct uart_port));
107
108 /*
109 * A note about mapbase/membase
110 * -) mapbase is the physical address of the IO port.
111 * -) membase is an 'ioremapped' cookie.
112 */
113 up.line = 0;
114 up.type = PORT_16550;
115 up.iotype = UPIO_MEM;
116 up.mapbase = WRPPMC_UART16550_BASE;
117 up.membase = ioremap(up.mapbase, 8);
118 up.irq = WRPPMC_UART16550_IRQ;
119 up.uartclk = WRPPMC_UART16550_CLOCK;
120 up.flags = UPF_SKIP_TEST/* | UPF_BOOT_AUTOCONF */;
121 up.regshift = 0;
122
123 early_serial_setup(&up);
124}
125#endif
126
127void __init plat_mem_setup(void) 97void __init plat_mem_setup(void)
128{ 98{
129 extern void wrppmc_time_init(void);
130 extern void wrppmc_machine_restart(char *command); 99 extern void wrppmc_machine_restart(char *command);
131 extern void wrppmc_machine_halt(void); 100 extern void wrppmc_machine_halt(void);
132 extern void wrppmc_machine_power_off(void); 101 extern void wrppmc_machine_power_off(void);
@@ -135,17 +104,10 @@ void __init plat_mem_setup(void)
135 _machine_halt = wrppmc_machine_halt; 104 _machine_halt = wrppmc_machine_halt;
136 pm_power_off = wrppmc_machine_power_off; 105 pm_power_off = wrppmc_machine_power_off;
137 106
138 /* Use MIPS Count/Compare Timer */
139 board_time_init = wrppmc_time_init;
140
141 /* This makes the operations of 'in/out[bwl]' to the 107 /* This makes the operations of 'in/out[bwl]' to the
142 * physical address ( < KSEG0) can work via KSEG1 108 * physical address ( < KSEG0) can work via KSEG1
143 */ 109 */
144 set_io_port_base(KSEG1); 110 set_io_port_base(KSEG1);
145
146#ifdef CONFIG_SERIAL_8250
147 wrppmc_setup_serial();
148#endif
149} 111}
150 112
151const char *get_system_type(void) 113const char *get_system_type(void)
@@ -159,7 +121,6 @@ const char *get_system_type(void)
159 */ 121 */
160void __init prom_init(void) 122void __init prom_init(void)
161{ 123{
162 mips_machgroup = MACH_GROUP_WINDRIVER;
163 mips_machtype = MACH_WRPPMC; 124 mips_machtype = MACH_WRPPMC;
164 125
165 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM); 126 add_memory_region(WRPPMC_SDRAM_SCS0_BASE, WRPPMC_SDRAM_SCS0_SIZE, BOOT_MEM_RAM);
diff --git a/arch/mips/gt64120/wrppmc/time.c b/arch/mips/gt64120/wrppmc/time.c
index 5b440859bcee..b207e7f1417a 100644
--- a/arch/mips/gt64120/wrppmc/time.c
+++ b/arch/mips/gt64120/wrppmc/time.c
@@ -11,18 +11,11 @@
11 * Copyright (C) 2006, Wind River System Inc. 11 * Copyright (C) 2006, Wind River System Inc.
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/string.h>
15#include <linux/kernel.h>
16#include <linux/param.h> /* for HZ */
17#include <linux/irq.h>
18#include <linux/timex.h>
19#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/irq.h>
20 16
21#include <asm/reboot.h>
22#include <asm/time.h>
23#include <asm/io.h>
24#include <asm/bootinfo.h>
25#include <asm/gt64120.h> 17#include <asm/gt64120.h>
18#include <asm/time.h>
26 19
27#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */ 20#define WRPPMC_CPU_CLK_FREQ 40000000 /* 40MHZ */
28 21
@@ -38,7 +31,7 @@ void __init plat_timer_setup(struct irqaction *irq)
38 * NOTE: We disable all GT64120 timers, and use MIPS processor internal 31 * NOTE: We disable all GT64120 timers, and use MIPS processor internal
39 * timer as the source of kernel clock tick. 32 * timer as the source of kernel clock tick.
40 */ 33 */
41void __init wrppmc_time_init(void) 34void __init plat_time_init(void)
42{ 35{
43 /* Disable GT64120 timers */ 36 /* Disable GT64120 timers */
44 GT_WRITE(GT_TC_CONTROL_OFS, 0x00); 37 GT_WRITE(GT_TC_CONTROL_OFS, 0x00);
diff --git a/arch/mips/jazz/Makefile b/arch/mips/jazz/Makefile
index 575a9442bc82..5aee0c266d18 100644
--- a/arch/mips/jazz/Makefile
+++ b/arch/mips/jazz/Makefile
@@ -2,6 +2,6 @@
2# Makefile for the Jazz family specific parts of the kernel 2# Makefile for the Jazz family specific parts of the kernel
3# 3#
4 4
5obj-y := irq.o jazzdma.o jazz-platform.o reset.o setup.o 5obj-y := irq.o jazzdma.o reset.o setup.o
6 6
7EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 015cf4bb51dd..835b056cea36 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -6,20 +6,23 @@
6 * Copyright (C) 1992 Linus Torvalds 6 * Copyright (C) 1992 Linus Torvalds
7 * Copyright (C) 1994 - 2001, 2003 Ralf Baechle 7 * Copyright (C) 1994 - 2001, 2003 Ralf Baechle
8 */ 8 */
9#include <linux/clockchips.h>
9#include <linux/init.h> 10#include <linux/init.h>
10#include <linux/interrupt.h> 11#include <linux/interrupt.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/spinlock.h> 13#include <linux/spinlock.h>
13 14
15#include <asm/irq_cpu.h>
14#include <asm/i8259.h> 16#include <asm/i8259.h>
15#include <asm/io.h> 17#include <asm/io.h>
16#include <asm/jazz.h> 18#include <asm/jazz.h>
19#include <asm/pgtable.h>
17 20
18static DEFINE_SPINLOCK(r4030_lock); 21static DEFINE_SPINLOCK(r4030_lock);
19 22
20static void enable_r4030_irq(unsigned int irq) 23static void enable_r4030_irq(unsigned int irq)
21{ 24{
22 unsigned int mask = 1 << (irq - JAZZ_PARALLEL_IRQ); 25 unsigned int mask = 1 << (irq - JAZZ_IRQ_START);
23 unsigned long flags; 26 unsigned long flags;
24 27
25 spin_lock_irqsave(&r4030_lock, flags); 28 spin_lock_irqsave(&r4030_lock, flags);
@@ -30,7 +33,7 @@ static void enable_r4030_irq(unsigned int irq)
30 33
31void disable_r4030_irq(unsigned int irq) 34void disable_r4030_irq(unsigned int irq)
32{ 35{
33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 36 unsigned int mask = ~(1 << (irq - JAZZ_IRQ_START));
34 unsigned long flags; 37 unsigned long flags;
35 38
36 spin_lock_irqsave(&r4030_lock, flags); 39 spin_lock_irqsave(&r4030_lock, flags);
@@ -51,7 +54,7 @@ void __init init_r4030_ints(void)
51{ 54{
52 int i; 55 int i;
53 56
54 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) 57 for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
55 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq); 58 set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
56 59
57 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 60 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
@@ -66,82 +69,87 @@ void __init init_r4030_ints(void)
66 */ 69 */
67void __init arch_init_irq(void) 70void __init arch_init_irq(void)
68{ 71{
72 /*
73 * this is a hack to get back the still needed wired mapping
74 * killed by init_mm()
75 */
76
77 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
78 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
79 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
80 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
81 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
82 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
83
69 init_i8259_irqs(); /* Integrated i8259 */ 84 init_i8259_irqs(); /* Integrated i8259 */
85 mips_cpu_irq_init();
70 init_r4030_ints(); 86 init_r4030_ints();
71 87
72 change_c0_status(ST0_IM, IE_IRQ4 | IE_IRQ3 | IE_IRQ2 | IE_IRQ1); 88 change_c0_status(ST0_IM, IE_IRQ2 | IE_IRQ1);
73}
74
75static void loc_call(unsigned int irq, unsigned int mask)
76{
77 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
78 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) & mask);
79 do_IRQ(irq);
80 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE,
81 r4030_read_reg16(JAZZ_IO_IRQ_ENABLE) | mask);
82}
83
84static void ll_local_dev(void)
85{
86 switch (r4030_read_reg32(JAZZ_IO_IRQ_SOURCE)) {
87 case 0:
88 panic("Unimplemented loc_no_irq handler");
89 break;
90 case 4:
91 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_PARALLEL);
92 break;
93 case 8:
94 loc_call(JAZZ_PARALLEL_IRQ, JAZZ_IE_FLOPPY);
95 break;
96 case 12:
97 panic("Unimplemented loc_sound handler");
98 break;
99 case 16:
100 panic("Unimplemented loc_video handler");
101 break;
102 case 20:
103 loc_call(JAZZ_ETHERNET_IRQ, JAZZ_IE_ETHERNET);
104 break;
105 case 24:
106 loc_call(JAZZ_SCSI_IRQ, JAZZ_IE_SCSI);
107 break;
108 case 28:
109 loc_call(JAZZ_KEYBOARD_IRQ, JAZZ_IE_KEYBOARD);
110 break;
111 case 32:
112 loc_call(JAZZ_MOUSE_IRQ, JAZZ_IE_MOUSE);
113 break;
114 case 36:
115 loc_call(JAZZ_SERIAL1_IRQ, JAZZ_IE_SERIAL1);
116 break;
117 case 40:
118 loc_call(JAZZ_SERIAL2_IRQ, JAZZ_IE_SERIAL2);
119 break;
120 }
121} 89}
122 90
123asmlinkage void plat_irq_dispatch(void) 91asmlinkage void plat_irq_dispatch(void)
124{ 92{
125 unsigned int pending = read_c0_cause() & read_c0_status(); 93 unsigned int pending = read_c0_cause() & read_c0_status();
94 unsigned int irq;
126 95
127 if (pending & IE_IRQ5) 96 if (pending & IE_IRQ4) {
128 write_c0_compare(0);
129 else if (pending & IE_IRQ4) {
130 r4030_read_reg32(JAZZ_TIMER_REGISTER); 97 r4030_read_reg32(JAZZ_TIMER_REGISTER);
131 do_IRQ(JAZZ_TIMER_IRQ); 98 do_IRQ(JAZZ_TIMER_IRQ);
132 } else if (pending & IE_IRQ3) 99 } else if (pending & IE_IRQ2)
133 panic("Unimplemented ISA NMI handler");
134 else if (pending & IE_IRQ2)
135 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK)); 100 do_IRQ(r4030_read_reg32(JAZZ_EISA_IRQ_ACK));
136 else if (pending & IE_IRQ1) { 101 else if (pending & IE_IRQ1) {
137 ll_local_dev(); 102 irq = *(volatile u8 *)JAZZ_IO_IRQ_SOURCE >> 2;
138 } else if (unlikely(pending & IE_IRQ0)) 103 if (likely(irq > 0))
139 panic("Unimplemented local_dma handler"); 104 do_IRQ(irq + JAZZ_IRQ_START - 1);
140 else if (pending & IE_SW1) { 105 else
141 clear_c0_cause(IE_SW1); 106 panic("Unimplemented loc_no_irq handler");
142 panic("Unimplemented sw1 handler");
143 } else if (pending & IE_SW0) {
144 clear_c0_cause(IE_SW0);
145 panic("Unimplemented sw0 handler");
146 } 107 }
147} 108}
109
110static void r4030_set_mode(enum clock_event_mode mode,
111 struct clock_event_device *evt)
112{
113 /* Nothing to do ... */
114}
115
116struct clock_event_device r4030_clockevent = {
117 .name = "r4030",
118 .features = CLOCK_EVT_FEAT_PERIODIC,
119 .rating = 100,
120 .irq = JAZZ_TIMER_IRQ,
121 .cpumask = CPU_MASK_CPU0,
122 .set_mode = r4030_set_mode,
123};
124
125static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
126{
127 r4030_clockevent.event_handler(&r4030_clockevent);
128
129 return IRQ_HANDLED;
130}
131
132static struct irqaction r4030_timer_irqaction = {
133 .handler = r4030_timer_interrupt,
134 .flags = IRQF_DISABLED,
135 .mask = CPU_MASK_CPU0,
136 .name = "timer",
137};
138
139void __init plat_timer_setup(struct irqaction *ignored)
140{
141 struct irqaction *irq = &r4030_timer_irqaction;
142
143 BUG_ON(HZ != 100);
144
145 /*
146 * Set clock to 100Hz.
147 *
148 * The R4030 timer receives an input clock of 1kHz which is divieded by
149 * a programmable 4-bit divider. This makes it fairly inflexible.
150 */
151 r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
152 setup_irq(JAZZ_TIMER_IRQ, irq);
153
154 clockevents_register_device(&r4030_clockevent);
155}
diff --git a/arch/mips/jazz/jazz-platform.c b/arch/mips/jazz/jazz-platform.c
deleted file mode 100644
index fd736703eef2..000000000000
--- a/arch/mips/jazz/jazz-platform.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/init.h>
9#include <linux/module.h>
10#include <linux/serial_8250.h>
11
12#include <asm/jazz.h>
13
14/*
15 * Confusion ... It seems the original Microsoft Jazz machine used to have a
16 * 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems
17 * had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs.
18 */
19#ifdef CONFIG_OLIVETTI_M700
20#define JAZZ_BASE_BAUD 1843200
21#else
22#define JAZZ_BASE_BAUD 8000000 /* 3072000 */
23#endif
24
25#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
26
27#define JAZZ_PORT(base, int) \
28{ \
29 .mapbase = base, \
30 .irq = int, \
31 .uartclk = JAZZ_BASE_BAUD, \
32 .iotype = UPIO_MEM, \
33 .flags = JAZZ_UART_FLAGS, \
34 .regshift = 0, \
35}
36
37static struct plat_serial8250_port uart8250_data[] = {
38 JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
39 JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
40 { },
41};
42
43static struct platform_device uart8250_device = {
44 .name = "serial8250",
45 .id = PLAT8250_DEV_PLATFORM,
46 .dev = {
47 .platform_data = uart8250_data,
48 },
49};
50
51static int __init uart8250_init(void)
52{
53 return platform_device_register(&uart8250_device);
54}
55
56module_init(uart8250_init);
57
58MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
59MODULE_LICENSE("GPL");
60MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family");
diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c
index e8e0ffb9354d..c672c08d49e5 100644
--- a/arch/mips/jazz/jazzdma.c
+++ b/arch/mips/jazz/jazzdma.c
@@ -27,7 +27,7 @@
27 */ 27 */
28#define CONF_DEBUG_VDMA 0 28#define CONF_DEBUG_VDMA 0
29 29
30static unsigned long vdma_pagetable_start; 30static VDMA_PGTBL_ENTRY *pgtbl;
31 31
32static DEFINE_SPINLOCK(vdma_lock); 32static DEFINE_SPINLOCK(vdma_lock);
33 33
@@ -46,7 +46,6 @@ static int debuglvl = 3;
46 */ 46 */
47static inline void vdma_pgtbl_init(void) 47static inline void vdma_pgtbl_init(void)
48{ 48{
49 VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
50 unsigned long paddr = 0; 49 unsigned long paddr = 0;
51 int i; 50 int i;
52 51
@@ -60,31 +59,31 @@ static inline void vdma_pgtbl_init(void)
60/* 59/*
61 * Initialize the Jazz R4030 dma controller 60 * Initialize the Jazz R4030 dma controller
62 */ 61 */
63void __init vdma_init(void) 62static int __init vdma_init(void)
64{ 63{
65 /* 64 /*
66 * Allocate 32k of memory for DMA page tables. This needs to be page 65 * Allocate 32k of memory for DMA page tables. This needs to be page
67 * aligned and should be uncached to avoid cache flushing after every 66 * aligned and should be uncached to avoid cache flushing after every
68 * update. 67 * update.
69 */ 68 */
70 vdma_pagetable_start = 69 pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA,
71 (unsigned long) alloc_bootmem_low_pages(VDMA_PGTBL_SIZE); 70 get_order(VDMA_PGTBL_SIZE));
72 if (!vdma_pagetable_start) 71 if (!pgtbl)
73 BUG(); 72 BUG();
74 dma_cache_wback_inv(vdma_pagetable_start, VDMA_PGTBL_SIZE); 73 dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE);
75 vdma_pagetable_start = KSEG1ADDR(vdma_pagetable_start); 74 pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl);
76 75
77 /* 76 /*
78 * Clear the R4030 translation table 77 * Clear the R4030 translation table
79 */ 78 */
80 vdma_pgtbl_init(); 79 vdma_pgtbl_init();
81 80
82 r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, 81 r4030_write_reg32(JAZZ_R4030_TRSTBL_BASE, CPHYSADDR(pgtbl));
83 CPHYSADDR(vdma_pagetable_start));
84 r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE); 82 r4030_write_reg32(JAZZ_R4030_TRSTBL_LIM, VDMA_PGTBL_SIZE);
85 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0); 83 r4030_write_reg32(JAZZ_R4030_TRSTBL_INV, 0);
86 84
87 printk("VDMA: R4030 DMA pagetables initialized.\n"); 85 printk(KERN_INFO "VDMA: R4030 DMA pagetables initialized.\n");
86 return 0;
88} 87}
89 88
90/* 89/*
@@ -92,7 +91,6 @@ void __init vdma_init(void)
92 */ 91 */
93unsigned long vdma_alloc(unsigned long paddr, unsigned long size) 92unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
94{ 93{
95 VDMA_PGTBL_ENTRY *entry = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
96 int first, last, pages, frame, i; 94 int first, last, pages, frame, i;
97 unsigned long laddr, flags; 95 unsigned long laddr, flags;
98 96
@@ -114,10 +112,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
114 /* 112 /*
115 * Find free chunk 113 * Find free chunk
116 */ 114 */
117 pages = (size + 4095) >> 12; /* no. of pages to allocate */ 115 pages = VDMA_PAGE(paddr + size) - VDMA_PAGE(paddr) + 1;
118 first = 0; 116 first = 0;
119 while (1) { 117 while (1) {
120 while (entry[first].owner != VDMA_PAGE_EMPTY && 118 while (pgtbl[first].owner != VDMA_PAGE_EMPTY &&
121 first < VDMA_PGTBL_ENTRIES) first++; 119 first < VDMA_PGTBL_ENTRIES) first++;
122 if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */ 120 if (first + pages > VDMA_PGTBL_ENTRIES) { /* nothing free */
123 spin_unlock_irqrestore(&vdma_lock, flags); 121 spin_unlock_irqrestore(&vdma_lock, flags);
@@ -125,12 +123,13 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
125 } 123 }
126 124
127 last = first + 1; 125 last = first + 1;
128 while (entry[last].owner == VDMA_PAGE_EMPTY 126 while (pgtbl[last].owner == VDMA_PAGE_EMPTY
129 && last - first < pages) 127 && last - first < pages)
130 last++; 128 last++;
131 129
132 if (last - first == pages) 130 if (last - first == pages)
133 break; /* found */ 131 break; /* found */
132 first = last + 1;
134 } 133 }
135 134
136 /* 135 /*
@@ -140,8 +139,8 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
140 frame = paddr & ~(VDMA_PAGESIZE - 1); 139 frame = paddr & ~(VDMA_PAGESIZE - 1);
141 140
142 for (i = first; i < last; i++) { 141 for (i = first; i < last; i++) {
143 entry[i].frame = frame; 142 pgtbl[i].frame = frame;
144 entry[i].owner = laddr; 143 pgtbl[i].owner = laddr;
145 frame += VDMA_PAGESIZE; 144 frame += VDMA_PAGESIZE;
146 } 145 }
147 146
@@ -160,10 +159,10 @@ unsigned long vdma_alloc(unsigned long paddr, unsigned long size)
160 printk("%08x ", i << 12); 159 printk("%08x ", i << 12);
161 printk("\nPADDR: "); 160 printk("\nPADDR: ");
162 for (i = first; i < last; i++) 161 for (i = first; i < last; i++)
163 printk("%08x ", entry[i].frame); 162 printk("%08x ", pgtbl[i].frame);
164 printk("\nOWNER: "); 163 printk("\nOWNER: ");
165 for (i = first; i < last; i++) 164 for (i = first; i < last; i++)
166 printk("%08x ", entry[i].owner); 165 printk("%08x ", pgtbl[i].owner);
167 printk("\n"); 166 printk("\n");
168 } 167 }
169 168
@@ -181,7 +180,6 @@ EXPORT_SYMBOL(vdma_alloc);
181 */ 180 */
182int vdma_free(unsigned long laddr) 181int vdma_free(unsigned long laddr)
183{ 182{
184 VDMA_PGTBL_ENTRY *pgtbl = (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
185 int i; 183 int i;
186 184
187 i = laddr >> 12; 185 i = laddr >> 12;
@@ -213,8 +211,6 @@ EXPORT_SYMBOL(vdma_free);
213 */ 211 */
214int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size) 212int vdma_remap(unsigned long laddr, unsigned long paddr, unsigned long size)
215{ 213{
216 VDMA_PGTBL_ENTRY *pgtbl =
217 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
218 int first, pages, npages; 214 int first, pages, npages;
219 215
220 if (laddr > 0xffffff) { 216 if (laddr > 0xffffff) {
@@ -289,8 +285,6 @@ unsigned long vdma_phys2log(unsigned long paddr)
289{ 285{
290 int i; 286 int i;
291 int frame; 287 int frame;
292 VDMA_PGTBL_ENTRY *pgtbl =
293 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
294 288
295 frame = paddr & ~(VDMA_PAGESIZE - 1); 289 frame = paddr & ~(VDMA_PAGESIZE - 1);
296 290
@@ -312,9 +306,6 @@ EXPORT_SYMBOL(vdma_phys2log);
312 */ 306 */
313unsigned long vdma_log2phys(unsigned long laddr) 307unsigned long vdma_log2phys(unsigned long laddr)
314{ 308{
315 VDMA_PGTBL_ENTRY *pgtbl =
316 (VDMA_PGTBL_ENTRY *) vdma_pagetable_start;
317
318 return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1)); 309 return pgtbl[laddr >> 12].frame + (laddr & (VDMA_PAGESIZE - 1));
319} 310}
320 311
@@ -564,3 +555,5 @@ int vdma_get_enable(int channel)
564 555
565 return enable; 556 return enable;
566} 557}
558
559arch_initcall(vdma_init);
diff --git a/arch/mips/jazz/reset.c b/arch/mips/jazz/reset.c
index d8ade85060b3..dd889fe86bd1 100644
--- a/arch/mips/jazz/reset.c
+++ b/arch/mips/jazz/reset.c
@@ -49,8 +49,8 @@ void jazz_machine_restart(char *command)
49{ 49{
50 while(1) { 50 while(1) {
51 kb_wait(); 51 kb_wait();
52 jazz_write_command (0xd1); 52 jazz_write_command(0xd1);
53 kb_wait(); 53 kb_wait();
54 jazz_write_output (0x00); 54 jazz_write_output(0x00);
55 } 55 }
56} 56}
diff --git a/arch/mips/jazz/setup.c b/arch/mips/jazz/setup.c
index 798279e06691..cfc7dce78dab 100644
--- a/arch/mips/jazz/setup.c
+++ b/arch/mips/jazz/setup.c
@@ -7,6 +7,7 @@
7 * 7 *
8 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle 8 * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
9 * Copyright (C) 2001 MIPS Technologies, Inc. 9 * Copyright (C) 2001 MIPS Technologies, Inc.
10 * Copyright (C) 2007 by Thomas Bogendoerfer
10 */ 11 */
11#include <linux/eisa.h> 12#include <linux/eisa.h>
12#include <linux/hdreg.h> 13#include <linux/hdreg.h>
@@ -20,8 +21,11 @@
20#include <linux/ide.h> 21#include <linux/ide.h>
21#include <linux/pm.h> 22#include <linux/pm.h>
22#include <linux/screen_info.h> 23#include <linux/screen_info.h>
24#include <linux/platform_device.h>
25#include <linux/serial_8250.h>
23 26
24#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/i8253.h>
25#include <asm/irq.h> 29#include <asm/irq.h>
26#include <asm/jazz.h> 30#include <asm/jazz.h>
27#include <asm/jazzdma.h> 31#include <asm/jazzdma.h>
@@ -30,18 +34,12 @@
30#include <asm/pgtable.h> 34#include <asm/pgtable.h>
31#include <asm/time.h> 35#include <asm/time.h>
32#include <asm/traps.h> 36#include <asm/traps.h>
37#include <asm/mc146818-time.h>
33 38
34extern asmlinkage void jazz_handle_int(void); 39extern asmlinkage void jazz_handle_int(void);
35 40
36extern void jazz_machine_restart(char *command); 41extern void jazz_machine_restart(char *command);
37 42
38void __init plat_timer_setup(struct irqaction *irq)
39{
40 /* set the clock to 100 Hz */
41 r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
42 setup_irq(JAZZ_TIMER_IRQ, irq);
43}
44
45static struct resource jazz_io_resources[] = { 43static struct resource jazz_io_resources[] = {
46 { 44 {
47 .start = 0x00, 45 .start = 0x00,
@@ -66,18 +64,21 @@ static struct resource jazz_io_resources[] = {
66 } 64 }
67}; 65};
68 66
67void __init plat_time_init(void)
68{
69 setup_pit_timer();
70}
71
69void __init plat_mem_setup(void) 72void __init plat_mem_setup(void)
70{ 73{
71 int i; 74 int i;
72 75
73 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */ 76 /* Map 0xe0000000 -> 0x0:800005C0, 0xe0010000 -> 0x1:30000580 */
74 add_wired_entry (0x02000017, 0x03c00017, 0xe0000000, PM_64K); 77 add_wired_entry(0x02000017, 0x03c00017, 0xe0000000, PM_64K);
75
76 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */ 78 /* Map 0xe2000000 -> 0x0:900005C0, 0xe3010000 -> 0x0:910005C0 */
77 add_wired_entry (0x02400017, 0x02440017, 0xe2000000, PM_16M); 79 add_wired_entry(0x02400017, 0x02440017, 0xe2000000, PM_16M);
78
79 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */ 80 /* Map 0xe4000000 -> 0x0:600005C0, 0xe4100000 -> 400005C0 */
80 add_wired_entry (0x01800017, 0x01000017, 0xe4000000, PM_4M); 81 add_wired_entry(0x01800017, 0x01000017, 0xe4000000, PM_4M);
81 82
82 set_io_port_base(JAZZ_PORT_BASE); 83 set_io_port_base(JAZZ_PORT_BASE);
83#ifdef CONFIG_EISA 84#ifdef CONFIG_EISA
@@ -94,6 +95,7 @@ void __init plat_mem_setup(void)
94 95
95 _machine_restart = jazz_machine_restart; 96 _machine_restart = jazz_machine_restart;
96 97
98#ifdef CONFIG_VT
97 screen_info = (struct screen_info) { 99 screen_info = (struct screen_info) {
98 0, 0, /* orig-x, orig-y */ 100 0, 0, /* orig-x, orig-y */
99 0, /* unused */ 101 0, /* unused */
@@ -105,6 +107,112 @@ void __init plat_mem_setup(void)
105 0, /* orig_video_isVGA */ 107 0, /* orig_video_isVGA */
106 16 /* orig_video_points */ 108 16 /* orig_video_points */
107 }; 109 };
110#endif
108 111
109 vdma_init(); 112 add_preferred_console("ttyS", 0, "9600");
110} 113}
114
115#ifdef CONFIG_OLIVETTI_M700
116#define UART_CLK 1843200
117#else
118/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
119 exactly which ones ... XXX */
120#define UART_CLK (8000000 / 16) /* ( 3072000 / 16) */
121#endif
122
123#define MEMPORT(_base, _irq) \
124 { \
125 .mapbase = (_base), \
126 .membase = (void *)(_base), \
127 .irq = (_irq), \
128 .uartclk = UART_CLK, \
129 .iotype = UPIO_MEM, \
130 .flags = UPF_BOOT_AUTOCONF, \
131 }
132
133static struct plat_serial8250_port jazz_serial_data[] = {
134 MEMPORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
135 MEMPORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
136 { },
137};
138
139static struct platform_device jazz_serial8250_device = {
140 .name = "serial8250",
141 .id = PLAT8250_DEV_PLATFORM,
142 .dev = {
143 .platform_data = jazz_serial_data,
144 },
145};
146
147static struct resource jazz_esp_rsrc[] = {
148 {
149 .start = JAZZ_SCSI_BASE,
150 .end = JAZZ_SCSI_BASE + 31,
151 .flags = IORESOURCE_MEM
152 },
153 {
154 .start = JAZZ_SCSI_DMA,
155 .end = JAZZ_SCSI_DMA,
156 .flags = IORESOURCE_MEM
157 },
158 {
159 .start = JAZZ_SCSI_IRQ,
160 .end = JAZZ_SCSI_IRQ,
161 .flags = IORESOURCE_IRQ
162 }
163};
164
165static struct platform_device jazz_esp_pdev = {
166 .name = "jazz_esp",
167 .num_resources = ARRAY_SIZE(jazz_esp_rsrc),
168 .resource = jazz_esp_rsrc
169};
170
171static struct resource jazz_sonic_rsrc[] = {
172 {
173 .start = JAZZ_ETHERNET_BASE,
174 .end = JAZZ_ETHERNET_BASE + 0xff,
175 .flags = IORESOURCE_MEM
176 },
177 {
178 .start = JAZZ_ETHERNET_IRQ,
179 .end = JAZZ_ETHERNET_IRQ,
180 .flags = IORESOURCE_IRQ
181 }
182};
183
184static struct platform_device jazz_sonic_pdev = {
185 .name = "jazzsonic",
186 .num_resources = ARRAY_SIZE(jazz_sonic_rsrc),
187 .resource = jazz_sonic_rsrc
188};
189
190static struct resource jazz_cmos_rsrc[] = {
191 {
192 .start = 0x70,
193 .end = 0x71,
194 .flags = IORESOURCE_IO
195 },
196 {
197 .start = 8,
198 .end = 8,
199 .flags = IORESOURCE_IRQ
200 }
201};
202
203static struct platform_device jazz_cmos_pdev = {
204 .name = "rtc_cmos",
205 .num_resources = ARRAY_SIZE(jazz_cmos_rsrc),
206 .resource = jazz_cmos_rsrc
207};
208
209static int __init jazz_setup_devinit(void)
210{
211 platform_device_register(&jazz_serial8250_device);
212 platform_device_register(&jazz_esp_pdev);
213 platform_device_register(&jazz_sonic_pdev);
214 platform_device_register(&jazz_cmos_pdev);
215 return 0;
216}
217
218device_initcall(jazz_setup_devinit);
diff --git a/arch/mips/jmr3927/rbhma3100/init.c b/arch/mips/jmr3927/rbhma3100/init.c
index 9169fab1773a..b643f75ec9a5 100644
--- a/arch/mips/jmr3927/rbhma3100/init.c
+++ b/arch/mips/jmr3927/rbhma3100/init.c
@@ -51,7 +51,6 @@ void __init prom_init(void)
51 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0) 51 if ((tx3927_ccfgptr->ccfg & TX3927_CCFG_TLBOFF) == 0)
52 puts("Warning: TX3927 TLB off\n"); 52 puts("Warning: TX3927 TLB off\n");
53#endif 53#endif
54 mips_machgroup = MACH_GROUP_TOSHIBA;
55 54
56#ifdef CONFIG_TOSHIBA_JMR3927 55#ifdef CONFIG_TOSHIBA_JMR3927
57 mips_machtype = MACH_TOSHIBA_JMR3927; 56 mips_machtype = MACH_TOSHIBA_JMR3927;
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index d9efe692e551..3a47e8ce1196 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -104,7 +104,9 @@ static irqreturn_t jmr3927_ioc_interrupt(int irq, void *dev_id)
104} 104}
105 105
106static struct irqaction ioc_action = { 106static struct irqaction ioc_action = {
107 jmr3927_ioc_interrupt, 0, CPU_MASK_NONE, "IOC", NULL, NULL, 107 .handler = jmr3927_ioc_interrupt,
108 .mask = CPU_MASK_NONE,
109 .name = "IOC",
108}; 110};
109 111
110static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 112static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
@@ -116,7 +118,9 @@ static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
116 return IRQ_HANDLED; 118 return IRQ_HANDLED;
117} 119}
118static struct irqaction pcierr_action = { 120static struct irqaction pcierr_action = {
119 jmr3927_pcierr_interrupt, 0, CPU_MASK_NONE, "PCI error", NULL, NULL, 121 .handler = jmr3927_pcierr_interrupt,
122 .mask = CPU_MASK_NONE,
123 .name = "PCI error",
120}; 124};
121 125
122static void __init jmr3927_irq_init(void); 126static void __init jmr3927_irq_init(void);
diff --git a/arch/mips/jmr3927/rbhma3100/setup.c b/arch/mips/jmr3927/rbhma3100/setup.c
index fde56e86c2ab..7f14f70a1b88 100644
--- a/arch/mips/jmr3927/rbhma3100/setup.c
+++ b/arch/mips/jmr3927/rbhma3100/setup.c
@@ -109,7 +109,7 @@ static void jmr3927_timer_ack(void)
109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */ 109 jmr3927_tmrptr->tisr = 0; /* ack interrupt */
110} 110}
111 111
112static void __init jmr3927_time_init(void) 112void __init plat_time_init(void)
113{ 113{
114 clocksource_mips.read = jmr3927_hpt_read; 114 clocksource_mips.read = jmr3927_hpt_read;
115 mips_timer_ack = jmr3927_timer_ack; 115 mips_timer_ack = jmr3927_timer_ack;
@@ -141,8 +141,6 @@ void __init plat_mem_setup(void)
141 141
142 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); 142 set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO);
143 143
144 board_time_init = jmr3927_time_init;
145
146 _machine_restart = jmr3927_machine_restart; 144 _machine_restart = jmr3927_machine_restart;
147 _machine_halt = jmr3927_machine_halt; 145 _machine_halt = jmr3927_machine_halt;
148 pm_power_off = jmr3927_machine_power_off; 146 pm_power_off = jmr3927_machine_power_off;
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 2fd96d95a39c..a2689f93c160 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o 51obj-$(CONFIG_IRQ_CPU_RM9K) += irq-rm9000.o
52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o 52obj-$(CONFIG_MIPS_BOARDS_GEN) += irq-msc01.o
53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o 53obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
54obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
54 55
55obj-$(CONFIG_32BIT) += scall32-o32.o 56obj-$(CONFIG_32BIT) += scall32-o32.o
56obj-$(CONFIG_64BIT) += scall64-64.o 57obj-$(CONFIG_64BIT) += scall64-64.o
@@ -64,6 +65,7 @@ obj-$(CONFIG_PROC_FS) += proc.o
64 65
65obj-$(CONFIG_64BIT) += cpu-bugs64.o 66obj-$(CONFIG_64BIT) += cpu-bugs64.o
66 67
68obj-$(CONFIG_I8253) += i8253.o
67obj-$(CONFIG_PCSPEAKER) += pcspeaker.o 69obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
68 70
69obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o 71obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c
index 993f7ec70f35..da41eac195ca 100644
--- a/arch/mips/kernel/binfmt_elfo32.c
+++ b/arch/mips/kernel/binfmt_elfo32.c
@@ -110,7 +110,7 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value)
110} 110}
111 111
112#undef ELF_CORE_COPY_REGS 112#undef ELF_CORE_COPY_REGS
113#define ELF_CORE_COPY_REGS(_dest,_regs) elf32_core_copy_regs(_dest,_regs); 113#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs);
114 114
115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) 115void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs)
116{ 116{
diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c
index 6648fde20b96..af78456d4138 100644
--- a/arch/mips/kernel/cpu-bugs64.c
+++ b/arch/mips/kernel/cpu-bugs64.c
@@ -29,7 +29,7 @@ static inline void align_mod(const int align, const int mod)
29 ".endr\n\t" 29 ".endr\n\t"
30 ".set pop" 30 ".set pop"
31 : 31 :
32 : GCC_IMM_ASM (align), GCC_IMM_ASM (mod)); 32 : GCC_IMM_ASM(align), GCC_IMM_ASM(mod));
33} 33}
34 34
35static inline void mult_sh_align_mod(long *v1, long *v2, long *w, 35static inline void mult_sh_align_mod(long *v1, long *v2, long *w,
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 3e004161ebd5..c8c47a2d1972 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -159,6 +159,7 @@ static inline void check_wait(void)
159 case CPU_5KC: 159 case CPU_5KC:
160 case CPU_25KF: 160 case CPU_25KF:
161 case CPU_PR4450: 161 case CPU_PR4450:
162 case CPU_BCM3302:
162 cpu_wait = r4k_wait; 163 cpu_wait = r4k_wait;
163 break; 164 break;
164 165
@@ -745,14 +746,6 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
745{ 746{
746 decode_configs(c); 747 decode_configs(c);
747 748
748 /*
749 * For historical reasons the SB1 comes with it's own variant of
750 * cache code which eventually will be folded into c-r4k.c. Until
751 * then we pretend it's got it's own cache architecture.
752 */
753 c->options &= ~MIPS_CPU_4K_CACHE;
754 c->options |= MIPS_CPU_SB1_CACHE;
755
756 switch (c->processor_id & 0xff00) { 749 switch (c->processor_id & 0xff00) {
757 case PRID_IMP_SB1: 750 case PRID_IMP_SB1:
758 c->cputype = CPU_SB1; 751 c->cputype = CPU_SB1;
@@ -793,9 +786,111 @@ static inline void cpu_probe_philips(struct cpuinfo_mips *c)
793} 786}
794 787
795 788
789static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
790{
791 decode_configs(c);
792 switch (c->processor_id & 0xff00) {
793 case PRID_IMP_BCM3302:
794 c->cputype = CPU_BCM3302;
795 break;
796 case PRID_IMP_BCM4710:
797 c->cputype = CPU_BCM4710;
798 break;
799 default:
800 c->cputype = CPU_UNKNOWN;
801 break;
802 }
803}
804
805const char *__cpu_name[NR_CPUS];
806
807/*
808 * Name a CPU
809 */
810static __init const char *cpu_to_name(struct cpuinfo_mips *c)
811{
812 const char *name = NULL;
813
814 switch (c->cputype) {
815 case CPU_UNKNOWN: name = "unknown"; break;
816 case CPU_R2000: name = "R2000"; break;
817 case CPU_R3000: name = "R3000"; break;
818 case CPU_R3000A: name = "R3000A"; break;
819 case CPU_R3041: name = "R3041"; break;
820 case CPU_R3051: name = "R3051"; break;
821 case CPU_R3052: name = "R3052"; break;
822 case CPU_R3081: name = "R3081"; break;
823 case CPU_R3081E: name = "R3081E"; break;
824 case CPU_R4000PC: name = "R4000PC"; break;
825 case CPU_R4000SC: name = "R4000SC"; break;
826 case CPU_R4000MC: name = "R4000MC"; break;
827 case CPU_R4200: name = "R4200"; break;
828 case CPU_R4400PC: name = "R4400PC"; break;
829 case CPU_R4400SC: name = "R4400SC"; break;
830 case CPU_R4400MC: name = "R4400MC"; break;
831 case CPU_R4600: name = "R4600"; break;
832 case CPU_R6000: name = "R6000"; break;
833 case CPU_R6000A: name = "R6000A"; break;
834 case CPU_R8000: name = "R8000"; break;
835 case CPU_R10000: name = "R10000"; break;
836 case CPU_R12000: name = "R12000"; break;
837 case CPU_R14000: name = "R14000"; break;
838 case CPU_R4300: name = "R4300"; break;
839 case CPU_R4650: name = "R4650"; break;
840 case CPU_R4700: name = "R4700"; break;
841 case CPU_R5000: name = "R5000"; break;
842 case CPU_R5000A: name = "R5000A"; break;
843 case CPU_R4640: name = "R4640"; break;
844 case CPU_NEVADA: name = "Nevada"; break;
845 case CPU_RM7000: name = "RM7000"; break;
846 case CPU_RM9000: name = "RM9000"; break;
847 case CPU_R5432: name = "R5432"; break;
848 case CPU_4KC: name = "MIPS 4Kc"; break;
849 case CPU_5KC: name = "MIPS 5Kc"; break;
850 case CPU_R4310: name = "R4310"; break;
851 case CPU_SB1: name = "SiByte SB1"; break;
852 case CPU_SB1A: name = "SiByte SB1A"; break;
853 case CPU_TX3912: name = "TX3912"; break;
854 case CPU_TX3922: name = "TX3922"; break;
855 case CPU_TX3927: name = "TX3927"; break;
856 case CPU_AU1000: name = "Au1000"; break;
857 case CPU_AU1500: name = "Au1500"; break;
858 case CPU_AU1100: name = "Au1100"; break;
859 case CPU_AU1550: name = "Au1550"; break;
860 case CPU_AU1200: name = "Au1200"; break;
861 case CPU_4KEC: name = "MIPS 4KEc"; break;
862 case CPU_4KSC: name = "MIPS 4KSc"; break;
863 case CPU_VR41XX: name = "NEC Vr41xx"; break;
864 case CPU_R5500: name = "R5500"; break;
865 case CPU_TX49XX: name = "TX49xx"; break;
866 case CPU_20KC: name = "MIPS 20Kc"; break;
867 case CPU_24K: name = "MIPS 24K"; break;
868 case CPU_25KF: name = "MIPS 25Kf"; break;
869 case CPU_34K: name = "MIPS 34K"; break;
870 case CPU_74K: name = "MIPS 74K"; break;
871 case CPU_VR4111: name = "NEC VR4111"; break;
872 case CPU_VR4121: name = "NEC VR4121"; break;
873 case CPU_VR4122: name = "NEC VR4122"; break;
874 case CPU_VR4131: name = "NEC VR4131"; break;
875 case CPU_VR4133: name = "NEC VR4133"; break;
876 case CPU_VR4181: name = "NEC VR4181"; break;
877 case CPU_VR4181A: name = "NEC VR4181A"; break;
878 case CPU_SR71000: name = "Sandcraft SR71000"; break;
879 case CPU_BCM3302: name = "Broadcom BCM3302"; break;
880 case CPU_BCM4710: name = "Broadcom BCM4710"; break;
881 case CPU_PR4450: name = "Philips PR4450"; break;
882 case CPU_LOONGSON2: name = "ICT Loongson-2"; break;
883 default:
884 BUG();
885 }
886
887 return name;
888}
889
796__init void cpu_probe(void) 890__init void cpu_probe(void)
797{ 891{
798 struct cpuinfo_mips *c = &current_cpu_data; 892 struct cpuinfo_mips *c = &current_cpu_data;
893 unsigned int cpu = smp_processor_id();
799 894
800 c->processor_id = PRID_IMP_UNKNOWN; 895 c->processor_id = PRID_IMP_UNKNOWN;
801 c->fpu_id = FPIR_IMP_NONE; 896 c->fpu_id = FPIR_IMP_NONE;
@@ -815,6 +910,9 @@ __init void cpu_probe(void)
815 case PRID_COMP_SIBYTE: 910 case PRID_COMP_SIBYTE:
816 cpu_probe_sibyte(c); 911 cpu_probe_sibyte(c);
817 break; 912 break;
913 case PRID_COMP_BROADCOM:
914 cpu_probe_broadcom(c);
915 break;
818 case PRID_COMP_SANDCRAFT: 916 case PRID_COMP_SANDCRAFT:
819 cpu_probe_sandcraft(c); 917 cpu_probe_sandcraft(c);
820 break; 918 break;
@@ -824,6 +922,14 @@ __init void cpu_probe(void)
824 default: 922 default:
825 c->cputype = CPU_UNKNOWN; 923 c->cputype = CPU_UNKNOWN;
826 } 924 }
925
926 /*
927 * Platform code can force the cpu type to optimize code
928 * generation. In that case be sure the cpu type is correctly
929 * manually setup otherwise it could trigger some nasty bugs.
930 */
931 BUG_ON(current_cpu_type() != c->cputype);
932
827 if (c->options & MIPS_CPU_FPU) { 933 if (c->options & MIPS_CPU_FPU) {
828 c->fpu_id = cpu_get_fpu_id(); 934 c->fpu_id = cpu_get_fpu_id();
829 935
@@ -835,13 +941,16 @@ __init void cpu_probe(void)
835 c->ases |= MIPS_ASE_MIPS3D; 941 c->ases |= MIPS_ASE_MIPS3D;
836 } 942 }
837 } 943 }
944
945 __cpu_name[cpu] = cpu_to_name(c);
838} 946}
839 947
840__init void cpu_report(void) 948__init void cpu_report(void)
841{ 949{
842 struct cpuinfo_mips *c = &current_cpu_data; 950 struct cpuinfo_mips *c = &current_cpu_data;
843 951
844 printk("CPU revision is: %08x\n", c->processor_id); 952 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
953 c->processor_id, cpu_name_string());
845 if (c->options & MIPS_CPU_FPU) 954 if (c->options & MIPS_CPU_FPU)
846 printk("FPU revision is: %08x\n", c->fpu_id); 955 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
847} 956}
diff --git a/arch/mips/kernel/gdb-stub.c b/arch/mips/kernel/gdb-stub.c
index cb5623aad552..3191afa29ad8 100644
--- a/arch/mips/kernel/gdb-stub.c
+++ b/arch/mips/kernel/gdb-stub.c
@@ -676,15 +676,18 @@ static void kgdb_wait(void *arg)
676static int kgdb_smp_call_kgdb_wait(void) 676static int kgdb_smp_call_kgdb_wait(void)
677{ 677{
678#ifdef CONFIG_SMP 678#ifdef CONFIG_SMP
679 cpumask_t mask = cpu_online_map;
679 struct call_data_struct data; 680 struct call_data_struct data;
680 int i, cpus = num_online_cpus() - 1;
681 int cpu = smp_processor_id(); 681 int cpu = smp_processor_id();
682 int cpus;
682 683
683 /* 684 /*
684 * Can die spectacularly if this CPU isn't yet marked online 685 * Can die spectacularly if this CPU isn't yet marked online
685 */ 686 */
686 BUG_ON(!cpu_online(cpu)); 687 BUG_ON(!cpu_online(cpu));
687 688
689 cpu_clear(cpu, mask);
690 cpus = cpus_weight(mask);
688 if (!cpus) 691 if (!cpus)
689 return 0; 692 return 0;
690 693
@@ -711,10 +714,7 @@ static int kgdb_smp_call_kgdb_wait(void)
711 call_data = &data; 714 call_data = &data;
712 mb(); 715 mb();
713 716
714 /* Send a message to all other CPUs and wait for them to respond */ 717 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
715 for (i = 0; i < NR_CPUS; i++)
716 if (cpu_online(i) && i != cpu)
717 core_send_ipi(i, SMP_CALL_FUNCTION);
718 718
719 /* Wait for response */ 719 /* Wait for response */
720 /* FIXME: lock-up detection, backtrace on lock-up */ 720 /* FIXME: lock-up detection, backtrace on lock-up */
@@ -733,7 +733,7 @@ static int kgdb_smp_call_kgdb_wait(void)
733 * returns 1 if you should skip the instruction at the trap address, 0 733 * returns 1 if you should skip the instruction at the trap address, 0
734 * otherwise. 734 * otherwise.
735 */ 735 */
736void handle_exception (struct gdb_regs *regs) 736void handle_exception(struct gdb_regs *regs)
737{ 737{
738 int trap; /* Trap type */ 738 int trap; /* Trap type */
739 int sigval; 739 int sigval;
@@ -769,7 +769,7 @@ void handle_exception (struct gdb_regs *regs)
769 /* 769 /*
770 * acquire the CPU spinlocks 770 * acquire the CPU spinlocks
771 */ 771 */
772 for (i = num_online_cpus()-1; i >= 0; i--) 772 for_each_online_cpu(i)
773 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0) 773 if (__raw_spin_trylock(&kgdb_cpulock[i]) == 0)
774 panic("kgdb: couldn't get cpulock %d\n", i); 774 panic("kgdb: couldn't get cpulock %d\n", i);
775 775
@@ -902,7 +902,7 @@ void handle_exception (struct gdb_regs *regs)
902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0); 902 hex2mem(ptr, (char *)&regs->frame_ptr, 2*sizeof(long), 0, 0);
903 ptr += 2*(2*sizeof(long)); 903 ptr += 2*(2*sizeof(long));
904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0); 904 hex2mem(ptr, (char *)&regs->cp0_index, 16*sizeof(long), 0, 0);
905 strcpy(output_buffer,"OK"); 905 strcpy(output_buffer, "OK");
906 } 906 }
907 break; 907 break;
908 908
@@ -917,9 +917,9 @@ void handle_exception (struct gdb_regs *regs)
917 && hexToInt(&ptr, &length)) { 917 && hexToInt(&ptr, &length)) {
918 if (mem2hex((char *)addr, output_buffer, length, 1)) 918 if (mem2hex((char *)addr, output_buffer, length, 1))
919 break; 919 break;
920 strcpy (output_buffer, "E03"); 920 strcpy(output_buffer, "E03");
921 } else 921 } else
922 strcpy(output_buffer,"E01"); 922 strcpy(output_buffer, "E01");
923 break; 923 break;
924 924
925 /* 925 /*
@@ -996,7 +996,7 @@ void handle_exception (struct gdb_regs *regs)
996 ptr = &input_buffer[1]; 996 ptr = &input_buffer[1];
997 if (!hexToInt(&ptr, &baudrate)) 997 if (!hexToInt(&ptr, &baudrate))
998 { 998 {
999 strcpy(output_buffer,"B01"); 999 strcpy(output_buffer, "B01");
1000 break; 1000 break;
1001 } 1001 }
1002 1002
@@ -1015,7 +1015,7 @@ void handle_exception (struct gdb_regs *regs)
1015 break; 1015 break;
1016 default: 1016 default:
1017 baudrate = 0; 1017 baudrate = 0;
1018 strcpy(output_buffer,"B02"); 1018 strcpy(output_buffer, "B02");
1019 goto x1; 1019 goto x1;
1020 } 1020 }
1021 1021
@@ -1044,7 +1044,7 @@ finish_kgdb:
1044 1044
1045exit_kgdb_exception: 1045exit_kgdb_exception:
1046 /* release locks so other CPUs can go */ 1046 /* release locks so other CPUs can go */
1047 for (i = num_online_cpus()-1; i >= 0; i--) 1047 for_each_online_cpu(i)
1048 __raw_spin_unlock(&kgdb_cpulock[i]); 1048 __raw_spin_unlock(&kgdb_cpulock[i]);
1049 spin_unlock(&kgdb_lock); 1049 spin_unlock(&kgdb_lock);
1050 1050
diff --git a/arch/mips/kernel/i8253.c b/arch/mips/kernel/i8253.c
new file mode 100644
index 000000000000..5d9830df3595
--- /dev/null
+++ b/arch/mips/kernel/i8253.c
@@ -0,0 +1,213 @@
1/*
2 * i8253.c 8253/PIT functions
3 *
4 */
5#include <linux/clockchips.h>
6#include <linux/init.h>
7#include <linux/interrupt.h>
8#include <linux/jiffies.h>
9#include <linux/module.h>
10#include <linux/spinlock.h>
11
12#include <asm/delay.h>
13#include <asm/i8253.h>
14#include <asm/io.h>
15
16static DEFINE_SPINLOCK(i8253_lock);
17
18/*
19 * Initialize the PIT timer.
20 *
21 * This is also called after resume to bring the PIT into operation again.
22 */
23static void init_pit_timer(enum clock_event_mode mode,
24 struct clock_event_device *evt)
25{
26 unsigned long flags;
27
28 spin_lock_irqsave(&i8253_lock, flags);
29
30 switch(mode) {
31 case CLOCK_EVT_MODE_PERIODIC:
32 /* binary, mode 2, LSB/MSB, ch 0 */
33 outb_p(0x34, PIT_MODE);
34 outb_p(LATCH & 0xff , PIT_CH0); /* LSB */
35 outb(LATCH >> 8 , PIT_CH0); /* MSB */
36 break;
37
38 case CLOCK_EVT_MODE_SHUTDOWN:
39 case CLOCK_EVT_MODE_UNUSED:
40 if (evt->mode == CLOCK_EVT_MODE_PERIODIC ||
41 evt->mode == CLOCK_EVT_MODE_ONESHOT) {
42 outb_p(0x30, PIT_MODE);
43 outb_p(0, PIT_CH0);
44 outb_p(0, PIT_CH0);
45 }
46 break;
47
48 case CLOCK_EVT_MODE_ONESHOT:
49 /* One shot setup */
50 outb_p(0x38, PIT_MODE);
51 break;
52
53 case CLOCK_EVT_MODE_RESUME:
54 /* Nothing to do here */
55 break;
56 }
57 spin_unlock_irqrestore(&i8253_lock, flags);
58}
59
60/*
61 * Program the next event in oneshot mode
62 *
63 * Delta is given in PIT ticks
64 */
65static int pit_next_event(unsigned long delta, struct clock_event_device *evt)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&i8253_lock, flags);
70 outb_p(delta & 0xff , PIT_CH0); /* LSB */
71 outb(delta >> 8 , PIT_CH0); /* MSB */
72 spin_unlock_irqrestore(&i8253_lock, flags);
73
74 return 0;
75}
76
77/*
78 * On UP the PIT can serve all of the possible timer functions. On SMP systems
79 * it can be solely used for the global tick.
80 *
81 * The profiling and update capabilites are switched off once the local apic is
82 * registered. This mechanism replaces the previous #ifdef LOCAL_APIC -
83 * !using_apic_timer decisions in do_timer_interrupt_hook()
84 */
85struct clock_event_device pit_clockevent = {
86 .name = "pit",
87 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
88 .set_mode = init_pit_timer,
89 .set_next_event = pit_next_event,
90 .shift = 32,
91 .irq = 0,
92};
93
94irqreturn_t timer_interrupt(int irq, void *dev_id)
95{
96 pit_clockevent.event_handler(&pit_clockevent);
97
98 return IRQ_HANDLED;
99}
100
101static struct irqaction irq0 = {
102 .handler = timer_interrupt,
103 .flags = IRQF_DISABLED | IRQF_NOBALANCING,
104 .mask = CPU_MASK_NONE,
105 .name = "timer"
106};
107
108/*
109 * Initialize the conversion factor and the min/max deltas of the clock event
110 * structure and register the clock event source with the framework.
111 */
112void __init setup_pit_timer(void)
113{
114 /*
115 * Start pit with the boot cpu mask and make it global after the
116 * IO_APIC has been initialized.
117 */
118 pit_clockevent.cpumask = cpumask_of_cpu(0);
119 pit_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, 32);
120 pit_clockevent.max_delta_ns =
121 clockevent_delta2ns(0x7FFF, &pit_clockevent);
122 pit_clockevent.min_delta_ns =
123 clockevent_delta2ns(0xF, &pit_clockevent);
124 clockevents_register_device(&pit_clockevent);
125
126 irq0.mask = cpumask_of_cpu(0);
127 setup_irq(0, &irq0);
128}
129
130/*
131 * Since the PIT overflows every tick, its not very useful
132 * to just read by itself. So use jiffies to emulate a free
133 * running counter:
134 */
135static cycle_t pit_read(void)
136{
137 unsigned long flags;
138 int count;
139 u32 jifs;
140 static int old_count;
141 static u32 old_jifs;
142
143 spin_lock_irqsave(&i8253_lock, flags);
144 /*
145 * Although our caller may have the read side of xtime_lock,
146 * this is now a seqlock, and we are cheating in this routine
147 * by having side effects on state that we cannot undo if
148 * there is a collision on the seqlock and our caller has to
149 * retry. (Namely, old_jifs and old_count.) So we must treat
150 * jiffies as volatile despite the lock. We read jiffies
151 * before latching the timer count to guarantee that although
152 * the jiffies value might be older than the count (that is,
153 * the counter may underflow between the last point where
154 * jiffies was incremented and the point where we latch the
155 * count), it cannot be newer.
156 */
157 jifs = jiffies;
158 outb_p(0x00, PIT_MODE); /* latch the count ASAP */
159 count = inb_p(PIT_CH0); /* read the latched count */
160 count |= inb_p(PIT_CH0) << 8;
161
162 /* VIA686a test code... reset the latch if count > max + 1 */
163 if (count > LATCH) {
164 outb_p(0x34, PIT_MODE);
165 outb_p(LATCH & 0xff, PIT_CH0);
166 outb(LATCH >> 8, PIT_CH0);
167 count = LATCH - 1;
168 }
169
170 /*
171 * It's possible for count to appear to go the wrong way for a
172 * couple of reasons:
173 *
174 * 1. The timer counter underflows, but we haven't handled the
175 * resulting interrupt and incremented jiffies yet.
176 * 2. Hardware problem with the timer, not giving us continuous time,
177 * the counter does small "jumps" upwards on some Pentium systems,
178 * (see c't 95/10 page 335 for Neptun bug.)
179 *
180 * Previous attempts to handle these cases intelligently were
181 * buggy, so we just do the simple thing now.
182 */
183 if (count > old_count && jifs == old_jifs) {
184 count = old_count;
185 }
186 old_count = count;
187 old_jifs = jifs;
188
189 spin_unlock_irqrestore(&i8253_lock, flags);
190
191 count = (LATCH - 1) - count;
192
193 return (cycle_t)(jifs * LATCH) + count;
194}
195
196static struct clocksource clocksource_pit = {
197 .name = "pit",
198 .rating = 110,
199 .read = pit_read,
200 .mask = CLOCKSOURCE_MASK(32),
201 .mult = 0,
202 .shift = 20,
203};
204
205static int __init init_pit_clocksource(void)
206{
207 if (num_possible_cpus() > 1) /* PIT does not scale! */
208 return 0;
209
210 clocksource_pit.mult = clocksource_hz2mult(CLOCK_TICK_RATE, 20);
211 return clocksource_register(&clocksource_pit);
212}
213arch_initcall(init_pit_clocksource);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 3a2d255361bc..471013577108 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -30,8 +30,10 @@
30 30
31static int i8259A_auto_eoi = -1; 31static int i8259A_auto_eoi = -1;
32DEFINE_SPINLOCK(i8259A_lock); 32DEFINE_SPINLOCK(i8259A_lock);
33/* some platforms call this... */ 33static void disable_8259A_irq(unsigned int irq);
34void mask_and_ack_8259A(unsigned int); 34static void enable_8259A_irq(unsigned int irq);
35static void mask_and_ack_8259A(unsigned int irq);
36static void init_8259A(int auto_eoi);
35 37
36static struct irq_chip i8259A_chip = { 38static struct irq_chip i8259A_chip = {
37 .name = "XT-PIC", 39 .name = "XT-PIC",
@@ -39,6 +41,9 @@ static struct irq_chip i8259A_chip = {
39 .disable = disable_8259A_irq, 41 .disable = disable_8259A_irq,
40 .unmask = enable_8259A_irq, 42 .unmask = enable_8259A_irq,
41 .mask_ack = mask_and_ack_8259A, 43 .mask_ack = mask_and_ack_8259A,
44#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
45 .set_affinity = plat_set_irq_affinity,
46#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
42}; 47};
43 48
44/* 49/*
@@ -53,7 +58,7 @@ static unsigned int cached_irq_mask = 0xffff;
53#define cached_master_mask (cached_irq_mask) 58#define cached_master_mask (cached_irq_mask)
54#define cached_slave_mask (cached_irq_mask >> 8) 59#define cached_slave_mask (cached_irq_mask >> 8)
55 60
56void disable_8259A_irq(unsigned int irq) 61static void disable_8259A_irq(unsigned int irq)
57{ 62{
58 unsigned int mask; 63 unsigned int mask;
59 unsigned long flags; 64 unsigned long flags;
@@ -69,7 +74,7 @@ void disable_8259A_irq(unsigned int irq)
69 spin_unlock_irqrestore(&i8259A_lock, flags); 74 spin_unlock_irqrestore(&i8259A_lock, flags);
70} 75}
71 76
72void enable_8259A_irq(unsigned int irq) 77static void enable_8259A_irq(unsigned int irq)
73{ 78{
74 unsigned int mask; 79 unsigned int mask;
75 unsigned long flags; 80 unsigned long flags;
@@ -122,14 +127,14 @@ static inline int i8259A_irq_real(unsigned int irq)
122 int irqmask = 1 << irq; 127 int irqmask = 1 << irq;
123 128
124 if (irq < 8) { 129 if (irq < 8) {
125 outb(0x0B,PIC_MASTER_CMD); /* ISR register */ 130 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
126 value = inb(PIC_MASTER_CMD) & irqmask; 131 value = inb(PIC_MASTER_CMD) & irqmask;
127 outb(0x0A,PIC_MASTER_CMD); /* back to the IRR register */ 132 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
128 return value; 133 return value;
129 } 134 }
130 outb(0x0B,PIC_SLAVE_CMD); /* ISR register */ 135 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
131 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8); 136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
132 outb(0x0A,PIC_SLAVE_CMD); /* back to the IRR register */ 137 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
133 return value; 138 return value;
134} 139}
135 140
@@ -139,7 +144,7 @@ static inline int i8259A_irq_real(unsigned int irq)
139 * first, _then_ send the EOI, and the order of EOI 144 * first, _then_ send the EOI, and the order of EOI
140 * to the two 8259s is important! 145 * to the two 8259s is important!
141 */ 146 */
142void mask_and_ack_8259A(unsigned int irq) 147static void mask_and_ack_8259A(unsigned int irq)
143{ 148{
144 unsigned int irqmask; 149 unsigned int irqmask;
145 unsigned long flags; 150 unsigned long flags;
@@ -170,12 +175,12 @@ handle_real_irq:
170 if (irq & 8) { 175 if (irq & 8) {
171 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */ 176 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
172 outb(cached_slave_mask, PIC_SLAVE_IMR); 177 outb(cached_slave_mask, PIC_SLAVE_IMR);
173 outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */ 178 outb(0x60+(irq&7), PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
174 outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */ 179 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD); /* 'Specific EOI' to master-IRQ2 */
175 } else { 180 } else {
176 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */ 181 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
177 outb(cached_master_mask, PIC_MASTER_IMR); 182 outb(cached_master_mask, PIC_MASTER_IMR);
178 outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */ 183 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
179 } 184 }
180 smtc_im_ack_irq(irq); 185 smtc_im_ack_irq(irq);
181 spin_unlock_irqrestore(&i8259A_lock, flags); 186 spin_unlock_irqrestore(&i8259A_lock, flags);
@@ -253,7 +258,7 @@ static int __init i8259A_init_sysfs(void)
253 258
254device_initcall(i8259A_init_sysfs); 259device_initcall(i8259A_init_sysfs);
255 260
256void init_8259A(int auto_eoi) 261static void init_8259A(int auto_eoi)
257{ 262{
258 unsigned long flags; 263 unsigned long flags;
259 264
@@ -300,7 +305,9 @@ void init_8259A(int auto_eoi)
300 * IRQ2 is cascade interrupt to second interrupt controller 305 * IRQ2 is cascade interrupt to second interrupt controller
301 */ 306 */
302static struct irqaction irq2 = { 307static struct irqaction irq2 = {
303 no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL 308 .handler = no_action,
309 .mask = CPU_MASK_NONE,
310 .name = "cascade",
304}; 311};
305 312
306static struct resource pic1_io_resource = { 313static struct resource pic1_io_resource = {
@@ -322,7 +329,7 @@ static struct resource pic2_io_resource = {
322 * driver compatibility reasons interrupts 0 - 15 to be the i8259 329 * driver compatibility reasons interrupts 0 - 15 to be the i8259
323 * interrupts even if the hardware uses a different interrupt numbering. 330 * interrupts even if the hardware uses a different interrupt numbering.
324 */ 331 */
325void __init init_i8259_irqs (void) 332void __init init_i8259_irqs(void)
326{ 333{
327 int i; 334 int i;
328 335
diff --git a/arch/mips/kernel/irixelf.c b/arch/mips/kernel/irixelf.c
index 403d96f99e77..8ef5cf4cc423 100644
--- a/arch/mips/kernel/irixelf.c
+++ b/arch/mips/kernel/irixelf.c
@@ -203,8 +203,8 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
203 * Put the ELF interpreter info on the stack 203 * Put the ELF interpreter info on the stack
204 */ 204 */
205#define NEW_AUX_ENT(nr, id, val) \ 205#define NEW_AUX_ENT(nr, id, val) \
206 __put_user ((id), sp+(nr*2)); \ 206 __put_user((id), sp+(nr*2)); \
207 __put_user ((val), sp+(nr*2+1)); \ 207 __put_user((val), sp+(nr*2+1)); \
208 208
209 sp -= 2; 209 sp -= 2;
210 NEW_AUX_ENT(0, AT_NULL, 0); 210 NEW_AUX_ENT(0, AT_NULL, 0);
@@ -212,17 +212,17 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
212 if (exec) { 212 if (exec) {
213 sp -= 11*2; 213 sp -= 11*2;
214 214
215 NEW_AUX_ENT (0, AT_PHDR, load_addr + exec->e_phoff); 215 NEW_AUX_ENT(0, AT_PHDR, load_addr + exec->e_phoff);
216 NEW_AUX_ENT (1, AT_PHENT, sizeof (struct elf_phdr)); 216 NEW_AUX_ENT(1, AT_PHENT, sizeof(struct elf_phdr));
217 NEW_AUX_ENT (2, AT_PHNUM, exec->e_phnum); 217 NEW_AUX_ENT(2, AT_PHNUM, exec->e_phnum);
218 NEW_AUX_ENT (3, AT_PAGESZ, ELF_EXEC_PAGESIZE); 218 NEW_AUX_ENT(3, AT_PAGESZ, ELF_EXEC_PAGESIZE);
219 NEW_AUX_ENT (4, AT_BASE, interp_load_addr); 219 NEW_AUX_ENT(4, AT_BASE, interp_load_addr);
220 NEW_AUX_ENT (5, AT_FLAGS, 0); 220 NEW_AUX_ENT(5, AT_FLAGS, 0);
221 NEW_AUX_ENT (6, AT_ENTRY, (elf_addr_t) exec->e_entry); 221 NEW_AUX_ENT(6, AT_ENTRY, (elf_addr_t) exec->e_entry);
222 NEW_AUX_ENT (7, AT_UID, (elf_addr_t) current->uid); 222 NEW_AUX_ENT(7, AT_UID, (elf_addr_t) current->uid);
223 NEW_AUX_ENT (8, AT_EUID, (elf_addr_t) current->euid); 223 NEW_AUX_ENT(8, AT_EUID, (elf_addr_t) current->euid);
224 NEW_AUX_ENT (9, AT_GID, (elf_addr_t) current->gid); 224 NEW_AUX_ENT(9, AT_GID, (elf_addr_t) current->gid);
225 NEW_AUX_ENT (10, AT_EGID, (elf_addr_t) current->egid); 225 NEW_AUX_ENT(10, AT_EGID, (elf_addr_t) current->egid);
226 } 226 }
227#undef NEW_AUX_ENT 227#undef NEW_AUX_ENT
228 228
@@ -231,16 +231,16 @@ static unsigned long * create_irix_tables(char * p, int argc, int envc,
231 sp -= argc+1; 231 sp -= argc+1;
232 argv = sp; 232 argv = sp;
233 233
234 __put_user((elf_addr_t)argc,--sp); 234 __put_user((elf_addr_t)argc, --sp);
235 current->mm->arg_start = (unsigned long) p; 235 current->mm->arg_start = (unsigned long) p;
236 while (argc-->0) { 236 while (argc-->0) {
237 __put_user((unsigned long)p,argv++); 237 __put_user((unsigned long)p, argv++);
238 p += strlen_user(p); 238 p += strlen_user(p);
239 } 239 }
240 __put_user((unsigned long) NULL, argv); 240 __put_user((unsigned long) NULL, argv);
241 current->mm->arg_end = current->mm->env_start = (unsigned long) p; 241 current->mm->arg_end = current->mm->env_start = (unsigned long) p;
242 while (envc-->0) { 242 while (envc-->0) {
243 __put_user((unsigned long)p,envp++); 243 __put_user((unsigned long)p, envp++);
244 p += strlen_user(p); 244 p += strlen_user(p);
245 } 245 }
246 __put_user((unsigned long) NULL, envp); 246 __put_user((unsigned long) NULL, envp);
@@ -581,7 +581,7 @@ static void irix_map_prda_page(void)
581 struct prda *pp; 581 struct prda *pp;
582 582
583 down_write(&current->mm->mmap_sem); 583 down_write(&current->mm->mmap_sem);
584 v = do_brk (PRDA_ADDRESS, PAGE_SIZE); 584 v = do_brk(PRDA_ADDRESS, PAGE_SIZE);
585 up_write(&current->mm->mmap_sem); 585 up_write(&current->mm->mmap_sem);
586 586
587 if (v < 0) 587 if (v < 0)
@@ -815,7 +815,7 @@ out_free_interp:
815 kfree(elf_interpreter); 815 kfree(elf_interpreter);
816out_free_file: 816out_free_file:
817out_free_ph: 817out_free_ph:
818 kfree (elf_phdata); 818 kfree(elf_phdata);
819 goto out; 819 goto out;
820} 820}
821 821
@@ -831,7 +831,7 @@ static int load_irix_library(struct file *file)
831 int retval; 831 int retval;
832 unsigned int bss; 832 unsigned int bss;
833 int error; 833 int error;
834 int i,j, k; 834 int i, j, k;
835 835
836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex)); 836 error = kernel_read(file, 0, (char *) &elf_ex, sizeof(elf_ex));
837 if (error != sizeof(elf_ex)) 837 if (error != sizeof(elf_ex))
@@ -1232,7 +1232,7 @@ static int irix_core_dump(long signr, struct pt_regs * regs, struct file *file)
1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname)); 1232 strlcpy(psinfo.pr_fname, current->comm, sizeof(psinfo.pr_fname));
1233 1233
1234 /* Try to dump the FPU. */ 1234 /* Try to dump the FPU. */
1235 prstatus.pr_fpvalid = dump_fpu (regs, &fpu); 1235 prstatus.pr_fpvalid = dump_fpu(regs, &fpu);
1236 if (!prstatus.pr_fpvalid) { 1236 if (!prstatus.pr_fpvalid) {
1237 numnote--; 1237 numnote--;
1238 } else { 1238 } else {
diff --git a/arch/mips/kernel/irixinv.c b/arch/mips/kernel/irixinv.c
index de8584f62311..cf2dcd3d6a93 100644
--- a/arch/mips/kernel/irixinv.c
+++ b/arch/mips/kernel/irixinv.c
@@ -14,7 +14,7 @@ int inventory_items = 0;
14 14
15static inventory_t inventory [MAX_INVENTORY]; 15static inventory_t inventory [MAX_INVENTORY];
16 16
17void add_to_inventory (int class, int type, int controller, int unit, int state) 17void add_to_inventory(int class, int type, int controller, int unit, int state)
18{ 18{
19 inventory_t *ni = &inventory [inventory_items]; 19 inventory_t *ni = &inventory [inventory_items];
20 20
@@ -30,7 +30,7 @@ void add_to_inventory (int class, int type, int controller, int unit, int state)
30 inventory_items++; 30 inventory_items++;
31} 31}
32 32
33int dump_inventory_to_user (void __user *userbuf, int size) 33int dump_inventory_to_user(void __user *userbuf, int size)
34{ 34{
35 inventory_t *inv = &inventory [0]; 35 inventory_t *inv = &inventory [0];
36 inventory_t __user *user = userbuf; 36 inventory_t __user *user = userbuf;
@@ -45,7 +45,7 @@ int dump_inventory_to_user (void __user *userbuf, int size)
45 return -EFAULT; 45 return -EFAULT;
46 user++; 46 user++;
47 } 47 }
48 return inventory_items * sizeof (inventory_t); 48 return inventory_items * sizeof(inventory_t);
49} 49}
50 50
51int __init init_inventory(void) 51int __init init_inventory(void)
@@ -55,24 +55,24 @@ int __init init_inventory(void)
55 * most likely this will not let just anyone run the X server 55 * most likely this will not let just anyone run the X server
56 * until we put the right values all over the place 56 * until we put the right values all over the place
57 */ 57 */
58 add_to_inventory (10, 3, 0, 0, 16400); 58 add_to_inventory(10, 3, 0, 0, 16400);
59 add_to_inventory (1, 1, 150, -1, 12); 59 add_to_inventory(1, 1, 150, -1, 12);
60 add_to_inventory (1, 3, 0, 0, 8976); 60 add_to_inventory(1, 3, 0, 0, 8976);
61 add_to_inventory (1, 2, 0, 0, 8976); 61 add_to_inventory(1, 2, 0, 0, 8976);
62 add_to_inventory (4, 8, 0, 0, 2); 62 add_to_inventory(4, 8, 0, 0, 2);
63 add_to_inventory (5, 5, 0, 0, 1); 63 add_to_inventory(5, 5, 0, 0, 1);
64 add_to_inventory (3, 3, 0, 0, 32768); 64 add_to_inventory(3, 3, 0, 0, 32768);
65 add_to_inventory (3, 4, 0, 0, 32768); 65 add_to_inventory(3, 4, 0, 0, 32768);
66 add_to_inventory (3, 8, 0, 0, 524288); 66 add_to_inventory(3, 8, 0, 0, 524288);
67 add_to_inventory (3, 9, 0, 0, 64); 67 add_to_inventory(3, 9, 0, 0, 64);
68 add_to_inventory (3, 1, 0, 0, 67108864); 68 add_to_inventory(3, 1, 0, 0, 67108864);
69 add_to_inventory (12, 3, 0, 0, 16); 69 add_to_inventory(12, 3, 0, 0, 16);
70 add_to_inventory (8, 7, 17, 0, 16777472); 70 add_to_inventory(8, 7, 17, 0, 16777472);
71 add_to_inventory (8, 0, 0, 0, 1); 71 add_to_inventory(8, 0, 0, 0, 1);
72 add_to_inventory (2, 1, 0, 13, 2); 72 add_to_inventory(2, 1, 0, 13, 2);
73 add_to_inventory (2, 2, 0, 2, 0); 73 add_to_inventory(2, 2, 0, 2, 0);
74 add_to_inventory (2, 2, 0, 1, 0); 74 add_to_inventory(2, 2, 0, 1, 0);
75 add_to_inventory (7, 14, 0, 0, 6); 75 add_to_inventory(7, 14, 0, 0, 6);
76 76
77 return 0; 77 return 0;
78} 78}
diff --git a/arch/mips/kernel/irixioctl.c b/arch/mips/kernel/irixioctl.c
index 30f9eb09db3f..2bde200d5ad0 100644
--- a/arch/mips/kernel/irixioctl.c
+++ b/arch/mips/kernel/irixioctl.c
@@ -238,7 +238,7 @@ asmlinkage int irix_ioctl(int fd, unsigned long cmd, unsigned long arg)
238 current->comm, current->pid, cmd); 238 current->comm, current->pid, cmd);
239 do_exit(255); 239 do_exit(255);
240#else 240#else
241 error = sys_ioctl (fd, cmd, arg); 241 error = sys_ioctl(fd, cmd, arg);
242#endif 242#endif
243 } 243 }
244 244
diff --git a/arch/mips/kernel/irixsig.c b/arch/mips/kernel/irixsig.c
index 28b2a8f00911..85c2e389edd6 100644
--- a/arch/mips/kernel/irixsig.c
+++ b/arch/mips/kernel/irixsig.c
@@ -163,9 +163,9 @@ static inline int handle_signal(unsigned long sig, siginfo_t *info,
163 ret = setup_irix_frame(ka, regs, sig, oldset); 163 ret = setup_irix_frame(ka, regs, sig, oldset);
164 164
165 spin_lock_irq(&current->sighand->siglock); 165 spin_lock_irq(&current->sighand->siglock);
166 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 166 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
167 if (!(ka->sa.sa_flags & SA_NODEFER)) 167 if (!(ka->sa.sa_flags & SA_NODEFER))
168 sigaddset(&current->blocked,sig); 168 sigaddset(&current->blocked, sig);
169 recalc_sigpending(); 169 recalc_sigpending();
170 spin_unlock_irq(&current->sighand->siglock); 170 spin_unlock_irq(&current->sighand->siglock);
171 171
@@ -605,8 +605,8 @@ repeat:
605 current->state = TASK_INTERRUPTIBLE; 605 current->state = TASK_INTERRUPTIBLE;
606 read_lock(&tasklist_lock); 606 read_lock(&tasklist_lock);
607 tsk = current; 607 tsk = current;
608 list_for_each(_p,&tsk->children) { 608 list_for_each(_p, &tsk->children) {
609 p = list_entry(_p,struct task_struct,sibling); 609 p = list_entry(_p, struct task_struct, sibling);
610 if ((type == IRIX_P_PID) && p->pid != pid) 610 if ((type == IRIX_P_PID) && p->pid != pid)
611 continue; 611 continue;
612 if ((type == IRIX_P_PGID) && process_group(p) != pid) 612 if ((type == IRIX_P_PGID) && process_group(p) != pid)
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
new file mode 100644
index 000000000000..1b81b131f43c
--- /dev/null
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -0,0 +1,131 @@
1/*
2 * GT641xx IRQ routines.
3 *
4 * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/hardirq.h>
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/spinlock.h>
24#include <linux/types.h>
25
26#include <asm/gt64120.h>
27
28#define GT641XX_IRQ_TO_BIT(irq) (1U << (irq - GT641XX_IRQ_BASE))
29
30static DEFINE_SPINLOCK(gt641xx_irq_lock);
31
32static void ack_gt641xx_irq(unsigned int irq)
33{
34 unsigned long flags;
35 u32 cause;
36
37 spin_lock_irqsave(&gt641xx_irq_lock, flags);
38 cause = GT_READ(GT_INTRCAUSE_OFS);
39 cause &= ~GT641XX_IRQ_TO_BIT(irq);
40 GT_WRITE(GT_INTRCAUSE_OFS, cause);
41 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
42}
43
44static void mask_gt641xx_irq(unsigned int irq)
45{
46 unsigned long flags;
47 u32 mask;
48
49 spin_lock_irqsave(&gt641xx_irq_lock, flags);
50 mask = GT_READ(GT_INTRMASK_OFS);
51 mask &= ~GT641XX_IRQ_TO_BIT(irq);
52 GT_WRITE(GT_INTRMASK_OFS, mask);
53 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
54}
55
56static void mask_ack_gt641xx_irq(unsigned int irq)
57{
58 unsigned long flags;
59 u32 cause, mask;
60
61 spin_lock_irqsave(&gt641xx_irq_lock, flags);
62 mask = GT_READ(GT_INTRMASK_OFS);
63 mask &= ~GT641XX_IRQ_TO_BIT(irq);
64 GT_WRITE(GT_INTRMASK_OFS, mask);
65
66 cause = GT_READ(GT_INTRCAUSE_OFS);
67 cause &= ~GT641XX_IRQ_TO_BIT(irq);
68 GT_WRITE(GT_INTRCAUSE_OFS, cause);
69 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
70}
71
72static void unmask_gt641xx_irq(unsigned int irq)
73{
74 unsigned long flags;
75 u32 mask;
76
77 spin_lock_irqsave(&gt641xx_irq_lock, flags);
78 mask = GT_READ(GT_INTRMASK_OFS);
79 mask |= GT641XX_IRQ_TO_BIT(irq);
80 GT_WRITE(GT_INTRMASK_OFS, mask);
81 spin_unlock_irqrestore(&gt641xx_irq_lock, flags);
82}
83
84static struct irq_chip gt641xx_irq_chip = {
85 .name = "GT641xx",
86 .ack = ack_gt641xx_irq,
87 .mask = mask_gt641xx_irq,
88 .mask_ack = mask_ack_gt641xx_irq,
89 .unmask = unmask_gt641xx_irq,
90};
91
92void gt641xx_irq_dispatch(void)
93{
94 u32 cause, mask;
95 int i;
96
97 cause = GT_READ(GT_INTRCAUSE_OFS);
98 mask = GT_READ(GT_INTRMASK_OFS);
99 cause &= mask;
100
101 /*
102 * bit0 : logical or of all the interrupt bits.
103 * bit30: logical or of bits[29:26,20:1].
104 * bit31: logical or of bits[25:1].
105 */
106 for (i = 1; i < 30; i++) {
107 if (cause & (1U << i)) {
108 do_IRQ(GT641XX_IRQ_BASE + i);
109 return;
110 }
111 }
112
113 atomic_inc(&irq_err_count);
114}
115
116void __init gt641xx_irq_init(void)
117{
118 int i;
119
120 GT_WRITE(GT_INTRMASK_OFS, 0);
121 GT_WRITE(GT_INTRCAUSE_OFS, 0);
122
123 /*
124 * bit0 : logical or of all the interrupt bits.
125 * bit30: logical or of bits[29:26,20:1].
126 * bit31: logical or of bits[25:1].
127 */
128 for (i = 1; i < 30; i++)
129 set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
130 &gt641xx_irq_chip, handle_level_irq);
131}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 1ecdd50bfc60..4edc7e451d91 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -99,7 +99,7 @@ void ll_msc_irq(void)
99} 99}
100 100
101void 101void
102msc_bind_eic_interrupt (unsigned int irq, unsigned int set) 102msc_bind_eic_interrupt(unsigned int irq, unsigned int set)
103{ 103{
104 MSCIC_WRITE(MSC01_IC_RAMW, 104 MSCIC_WRITE(MSC01_IC_RAMW,
105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 105 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
@@ -130,7 +130,7 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
130{ 130{
131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset); 131 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
132 132
133 _icctrl_msc = (unsigned long) ioremap (icubase, 0x40000); 133 _icctrl_msc = (unsigned long) ioremap(icubase, 0x40000);
134 134
135 /* Reset interrupt controller - initialises all registers to 0 */ 135 /* Reset interrupt controller - initialises all registers to 0 */
136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT); 136 MSCIC_WRITE(MSC01_IC_RST, MSC01_IC_RST_RST_BIT);
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index a990aad2f049..d06e9c9af790 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -93,7 +93,7 @@ int show_interrupts(struct seq_file *p, void *v)
93 if (i == 0) { 93 if (i == 0) {
94 seq_printf(p, " "); 94 seq_printf(p, " ");
95 for_each_online_cpu(j) 95 for_each_online_cpu(j)
96 seq_printf(p, "CPU%d ",j); 96 seq_printf(p, "CPU%d ", j);
97 seq_putc(p, '\n'); 97 seq_putc(p, '\n');
98 } 98 }
99 99
@@ -102,7 +102,7 @@ int show_interrupts(struct seq_file *p, void *v)
102 action = irq_desc[i].action; 102 action = irq_desc[i].action;
103 if (!action) 103 if (!action)
104 goto skip; 104 goto skip;
105 seq_printf(p, "%3d: ",i); 105 seq_printf(p, "%3d: ", i);
106#ifndef CONFIG_SMP 106#ifndef CONFIG_SMP
107 seq_printf(p, "%10u ", kstat_irqs(i)); 107 seq_printf(p, "%10u ", kstat_irqs(i));
108#else 108#else
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
index cb9a14a1ca5b..d2c2e00e5864 100644
--- a/arch/mips/kernel/kspd.c
+++ b/arch/mips/kernel/kspd.c
@@ -118,11 +118,11 @@ struct apsp_table syscall_command_table[] = {
118 118
119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3) 119static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3)
120{ 120{
121 register long int _num __asm__ ("$2") = num; 121 register long int _num __asm__("$2") = num;
122 register long int _arg0 __asm__ ("$4") = arg0; 122 register long int _arg0 __asm__("$4") = arg0;
123 register long int _arg1 __asm__ ("$5") = arg1; 123 register long int _arg1 __asm__("$5") = arg1;
124 register long int _arg2 __asm__ ("$6") = arg2; 124 register long int _arg2 __asm__("$6") = arg2;
125 register long int _arg3 __asm__ ("$7") = arg3; 125 register long int _arg3 __asm__("$7") = arg3;
126 126
127 mm_segment_t old_fs; 127 mm_segment_t old_fs;
128 128
@@ -239,7 +239,7 @@ void sp_work_handle_request(void)
239 case MTSP_SYSCALL_GETTOD: 239 case MTSP_SYSCALL_GETTOD:
240 memset(&tz, 0, sizeof(tz)); 240 memset(&tz, 0, sizeof(tz));
241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv, 241 if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
242 (int)&tz, 0,0)) == 0) 242 (int)&tz, 0, 0)) == 0)
243 ret.retval = tv.tv_sec; 243 ret.retval = tv.tv_sec;
244 break; 244 break;
245 245
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c
index 135d9a5fe337..d6e01215fb2b 100644
--- a/arch/mips/kernel/linux32.c
+++ b/arch/mips/kernel/linux32.c
@@ -58,10 +58,10 @@
58#define AA(__x) ((unsigned long)((int)__x)) 58#define AA(__x) ((unsigned long)((int)__x))
59 59
60#ifdef __MIPSEB__ 60#ifdef __MIPSEB__
61#define merge_64(r1,r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL)) 61#define merge_64(r1, r2) ((((r1) & 0xffffffffUL) << 32) + ((r2) & 0xffffffffUL))
62#endif 62#endif
63#ifdef __MIPSEL__ 63#ifdef __MIPSEL__
64#define merge_64(r1,r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL)) 64#define merge_64(r1, r2) ((((r2) & 0xffffffffUL) << 32) + ((r1) & 0xffffffffUL))
65#endif 65#endif
66 66
67/* 67/*
@@ -96,7 +96,7 @@ int cp_compat_stat(struct kstat *stat, struct compat_stat __user *statbuf)
96#endif 96#endif
97 tmp.st_blocks = stat->blocks; 97 tmp.st_blocks = stat->blocks;
98 tmp.st_blksize = stat->blksize; 98 tmp.st_blksize = stat->blksize;
99 return copy_to_user(statbuf,&tmp,sizeof(tmp)) ? -EFAULT : 0; 99 return copy_to_user(statbuf, &tmp, sizeof(tmp)) ? -EFAULT : 0;
100} 100}
101 101
102asmlinkage unsigned long 102asmlinkage unsigned long
@@ -300,13 +300,13 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
300{ 300{
301 struct timespec t; 301 struct timespec t;
302 int ret; 302 int ret;
303 mm_segment_t old_fs = get_fs (); 303 mm_segment_t old_fs = get_fs();
304 304
305 set_fs (KERNEL_DS); 305 set_fs(KERNEL_DS);
306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t); 306 ret = sys_sched_rr_get_interval(pid, (struct timespec __user *)&t);
307 set_fs (old_fs); 307 set_fs(old_fs);
308 if (put_user (t.tv_sec, &interval->tv_sec) || 308 if (put_user (t.tv_sec, &interval->tv_sec) ||
309 __put_user (t.tv_nsec, &interval->tv_nsec)) 309 __put_user(t.tv_nsec, &interval->tv_nsec))
310 return -EFAULT; 310 return -EFAULT;
311 return ret; 311 return ret;
312} 312}
@@ -314,7 +314,7 @@ asmlinkage int sys32_sched_rr_get_interval(compat_pid_t pid,
314#ifdef CONFIG_SYSVIPC 314#ifdef CONFIG_SYSVIPC
315 315
316asmlinkage long 316asmlinkage long
317sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 317sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
318{ 318{
319 int version, err; 319 int version, err;
320 320
@@ -373,7 +373,7 @@ sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth)
373#else 373#else
374 374
375asmlinkage long 375asmlinkage long
376sys32_ipc (u32 call, int first, int second, int third, u32 ptr, u32 fifth) 376sys32_ipc(u32 call, int first, int second, int third, u32 ptr, u32 fifth)
377{ 377{
378 return -ENOSYS; 378 return -ENOSYS;
379} 379}
@@ -505,16 +505,16 @@ asmlinkage int sys32_ustat(dev_t dev, struct ustat32 __user * ubuf32)
505 505
506 set_fs(KERNEL_DS); 506 set_fs(KERNEL_DS);
507 err = sys_ustat(dev, (struct ustat __user *)&tmp); 507 err = sys_ustat(dev, (struct ustat __user *)&tmp);
508 set_fs (old_fs); 508 set_fs(old_fs);
509 509
510 if (err) 510 if (err)
511 goto out; 511 goto out;
512 512
513 memset(&tmp32,0,sizeof(struct ustat32)); 513 memset(&tmp32, 0, sizeof(struct ustat32));
514 tmp32.f_tfree = tmp.f_tfree; 514 tmp32.f_tfree = tmp.f_tfree;
515 tmp32.f_tinode = tmp.f_tinode; 515 tmp32.f_tinode = tmp.f_tinode;
516 516
517 err = copy_to_user(ubuf32,&tmp32,sizeof(struct ustat32)) ? -EFAULT : 0; 517 err = copy_to_user(ubuf32, &tmp32, sizeof(struct ustat32)) ? -EFAULT : 0;
518 518
519out: 519out:
520 return err; 520 return err;
diff --git a/arch/mips/kernel/mips-mt.c b/arch/mips/kernel/mips-mt.c
index 56750b02ab40..3d6b1ec1f328 100644
--- a/arch/mips/kernel/mips-mt.c
+++ b/arch/mips/kernel/mips-mt.c
@@ -236,7 +236,7 @@ void mips_mt_set_cpuoptions(void)
236 if (oconfig7 != nconfig7) { 236 if (oconfig7 != nconfig7) {
237 __asm__ __volatile("sync"); 237 __asm__ __volatile("sync");
238 write_c0_config7(nconfig7); 238 write_c0_config7(nconfig7);
239 ehb (); 239 ehb();
240 printk("Config7: 0x%08x\n", read_c0_config7()); 240 printk("Config7: 0x%08x\n", read_c0_config7());
241 } 241 }
242 242
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index ec04f5a1a5ea..efd2d1314123 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -17,76 +17,6 @@
17 17
18unsigned int vced_count, vcei_count; 18unsigned int vced_count, vcei_count;
19 19
20static const char *cpu_name[] = {
21 [CPU_UNKNOWN] = "unknown",
22 [CPU_R2000] = "R2000",
23 [CPU_R3000] = "R3000",
24 [CPU_R3000A] = "R3000A",
25 [CPU_R3041] = "R3041",
26 [CPU_R3051] = "R3051",
27 [CPU_R3052] = "R3052",
28 [CPU_R3081] = "R3081",
29 [CPU_R3081E] = "R3081E",
30 [CPU_R4000PC] = "R4000PC",
31 [CPU_R4000SC] = "R4000SC",
32 [CPU_R4000MC] = "R4000MC",
33 [CPU_R4200] = "R4200",
34 [CPU_R4400PC] = "R4400PC",
35 [CPU_R4400SC] = "R4400SC",
36 [CPU_R4400MC] = "R4400MC",
37 [CPU_R4600] = "R4600",
38 [CPU_R6000] = "R6000",
39 [CPU_R6000A] = "R6000A",
40 [CPU_R8000] = "R8000",
41 [CPU_R10000] = "R10000",
42 [CPU_R12000] = "R12000",
43 [CPU_R14000] = "R14000",
44 [CPU_R4300] = "R4300",
45 [CPU_R4650] = "R4650",
46 [CPU_R4700] = "R4700",
47 [CPU_R5000] = "R5000",
48 [CPU_R5000A] = "R5000A",
49 [CPU_R4640] = "R4640",
50 [CPU_NEVADA] = "Nevada",
51 [CPU_RM7000] = "RM7000",
52 [CPU_RM9000] = "RM9000",
53 [CPU_R5432] = "R5432",
54 [CPU_4KC] = "MIPS 4Kc",
55 [CPU_5KC] = "MIPS 5Kc",
56 [CPU_R4310] = "R4310",
57 [CPU_SB1] = "SiByte SB1",
58 [CPU_SB1A] = "SiByte SB1A",
59 [CPU_TX3912] = "TX3912",
60 [CPU_TX3922] = "TX3922",
61 [CPU_TX3927] = "TX3927",
62 [CPU_AU1000] = "Au1000",
63 [CPU_AU1500] = "Au1500",
64 [CPU_AU1100] = "Au1100",
65 [CPU_AU1550] = "Au1550",
66 [CPU_AU1200] = "Au1200",
67 [CPU_4KEC] = "MIPS 4KEc",
68 [CPU_4KSC] = "MIPS 4KSc",
69 [CPU_VR41XX] = "NEC Vr41xx",
70 [CPU_R5500] = "R5500",
71 [CPU_TX49XX] = "TX49xx",
72 [CPU_20KC] = "MIPS 20Kc",
73 [CPU_24K] = "MIPS 24K",
74 [CPU_25KF] = "MIPS 25Kf",
75 [CPU_34K] = "MIPS 34K",
76 [CPU_74K] = "MIPS 74K",
77 [CPU_VR4111] = "NEC VR4111",
78 [CPU_VR4121] = "NEC VR4121",
79 [CPU_VR4122] = "NEC VR4122",
80 [CPU_VR4131] = "NEC VR4131",
81 [CPU_VR4133] = "NEC VR4133",
82 [CPU_VR4181] = "NEC VR4181",
83 [CPU_VR4181A] = "NEC VR4181A",
84 [CPU_SR71000] = "Sandcraft SR71000",
85 [CPU_PR4450] = "Philips PR4450",
86 [CPU_LOONGSON2] = "ICT Loongson-2",
87};
88
89
90static int show_cpuinfo(struct seq_file *m, void *v) 20static int show_cpuinfo(struct seq_file *m, void *v)
91{ 21{
92 unsigned long n = (unsigned long) v - 1; 22 unsigned long n = (unsigned long) v - 1;
@@ -108,8 +38,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
108 seq_printf(m, "processor\t\t: %ld\n", n); 38 seq_printf(m, "processor\t\t: %ld\n", n);
109 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", 39 sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
110 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : ""); 40 cpu_data[n].options & MIPS_CPU_FPU ? " FPU V%d.%d" : "");
111 seq_printf(m, fmt, cpu_name[cpu_data[n].cputype <= CPU_LAST ? 41 seq_printf(m, fmt, __cpu_name[smp_processor_id()],
112 cpu_data[n].cputype : CPU_UNKNOWN],
113 (version >> 4) & 0x0f, version & 0x0f, 42 (version >> 4) & 0x0f, version & 0x0f,
114 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f); 43 (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
115 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n", 44 seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index e6ce943099a0..11cb264f59ce 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -11,6 +11,7 @@
11#include <linux/errno.h> 11#include <linux/errno.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/sched.h> 13#include <linux/sched.h>
14#include <linux/tick.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15#include <linux/mm.h> 16#include <linux/mm.h>
16#include <linux/stddef.h> 17#include <linux/stddef.h>
@@ -52,6 +53,7 @@ void __noreturn cpu_idle(void)
52{ 53{
53 /* endless idle loop with no priority at all */ 54 /* endless idle loop with no priority at all */
54 while (1) { 55 while (1) {
56 tick_nohz_stop_sched_tick();
55 while (!need_resched()) { 57 while (!need_resched()) {
56#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 58#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
57 extern void smtc_idle_loop_hook(void); 59 extern void smtc_idle_loop_hook(void);
@@ -61,6 +63,7 @@ void __noreturn cpu_idle(void)
61 if (cpu_wait) 63 if (cpu_wait)
62 (*cpu_wait)(); 64 (*cpu_wait)();
63 } 65 }
66 tick_nohz_restart_sched_tick();
64 preempt_enable_no_resched(); 67 preempt_enable_no_resched();
65 schedule(); 68 schedule();
66 preempt_disable(); 69 preempt_disable();
@@ -199,13 +202,13 @@ void elf_dump_regs(elf_greg_t *gp, struct pt_regs *regs)
199#endif 202#endif
200} 203}
201 204
202int dump_task_regs (struct task_struct *tsk, elf_gregset_t *regs) 205int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
203{ 206{
204 elf_dump_regs(*regs, task_pt_regs(tsk)); 207 elf_dump_regs(*regs, task_pt_regs(tsk));
205 return 1; 208 return 1;
206} 209}
207 210
208int dump_task_fpu (struct task_struct *t, elf_fpregset_t *fpr) 211int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpr)
209{ 212{
210 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu)); 213 memcpy(fpr, &t->thread.fpu, sizeof(current->thread.fpu));
211 214
@@ -231,8 +234,8 @@ long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
231 regs.cp0_epc = (unsigned long) kernel_thread_helper; 234 regs.cp0_epc = (unsigned long) kernel_thread_helper;
232 regs.cp0_status = read_c0_status(); 235 regs.cp0_status = read_c0_status();
233#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) 236#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
234 regs.cp0_status &= ~(ST0_KUP | ST0_IEC); 237 regs.cp0_status = (regs.cp0_status & ~(ST0_KUP | ST0_IEP | ST0_IEC)) |
235 regs.cp0_status |= ST0_IEP; 238 ((regs.cp0_status & (ST0_KUC | ST0_IEC)) << 2);
236#else 239#else
237 regs.cp0_status |= ST0_EXL; 240 regs.cp0_status |= ST0_EXL;
238#endif 241#endif
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index bbd57b20b43e..58aa6fec1146 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -54,7 +54,7 @@ void ptrace_disable(struct task_struct *child)
54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel. 54 * for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
55 * Registers are sign extended to fill the available space. 55 * Registers are sign extended to fill the available space.
56 */ 56 */
57int ptrace_getregs (struct task_struct *child, __s64 __user *data) 57int ptrace_getregs(struct task_struct *child, __s64 __user *data)
58{ 58{
59 struct pt_regs *regs; 59 struct pt_regs *regs;
60 int i; 60 int i;
@@ -65,13 +65,13 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
65 regs = task_pt_regs(child); 65 regs = task_pt_regs(child);
66 66
67 for (i = 0; i < 32; i++) 67 for (i = 0; i < 32; i++)
68 __put_user (regs->regs[i], data + i); 68 __put_user(regs->regs[i], data + i);
69 __put_user (regs->lo, data + EF_LO - EF_R0); 69 __put_user(regs->lo, data + EF_LO - EF_R0);
70 __put_user (regs->hi, data + EF_HI - EF_R0); 70 __put_user(regs->hi, data + EF_HI - EF_R0);
71 __put_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 71 __put_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
72 __put_user (regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0); 72 __put_user(regs->cp0_badvaddr, data + EF_CP0_BADVADDR - EF_R0);
73 __put_user (regs->cp0_status, data + EF_CP0_STATUS - EF_R0); 73 __put_user(regs->cp0_status, data + EF_CP0_STATUS - EF_R0);
74 __put_user (regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0); 74 __put_user(regs->cp0_cause, data + EF_CP0_CAUSE - EF_R0);
75 75
76 return 0; 76 return 0;
77} 77}
@@ -81,7 +81,7 @@ int ptrace_getregs (struct task_struct *child, __s64 __user *data)
81 * the 64-bit format. On a 32-bit kernel only the lower order half 81 * the 64-bit format. On a 32-bit kernel only the lower order half
82 * (according to endianness) will be used. 82 * (according to endianness) will be used.
83 */ 83 */
84int ptrace_setregs (struct task_struct *child, __s64 __user *data) 84int ptrace_setregs(struct task_struct *child, __s64 __user *data)
85{ 85{
86 struct pt_regs *regs; 86 struct pt_regs *regs;
87 int i; 87 int i;
@@ -92,17 +92,17 @@ int ptrace_setregs (struct task_struct *child, __s64 __user *data)
92 regs = task_pt_regs(child); 92 regs = task_pt_regs(child);
93 93
94 for (i = 0; i < 32; i++) 94 for (i = 0; i < 32; i++)
95 __get_user (regs->regs[i], data + i); 95 __get_user(regs->regs[i], data + i);
96 __get_user (regs->lo, data + EF_LO - EF_R0); 96 __get_user(regs->lo, data + EF_LO - EF_R0);
97 __get_user (regs->hi, data + EF_HI - EF_R0); 97 __get_user(regs->hi, data + EF_HI - EF_R0);
98 __get_user (regs->cp0_epc, data + EF_CP0_EPC - EF_R0); 98 __get_user(regs->cp0_epc, data + EF_CP0_EPC - EF_R0);
99 99
100 /* badvaddr, status, and cause may not be written. */ 100 /* badvaddr, status, and cause may not be written. */
101 101
102 return 0; 102 return 0;
103} 103}
104 104
105int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) 105int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
106{ 106{
107 int i; 107 int i;
108 unsigned int tmp; 108 unsigned int tmp;
@@ -113,13 +113,13 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
113 if (tsk_used_math(child)) { 113 if (tsk_used_math(child)) {
114 fpureg_t *fregs = get_fpu_regs(child); 114 fpureg_t *fregs = get_fpu_regs(child);
115 for (i = 0; i < 32; i++) 115 for (i = 0; i < 32; i++)
116 __put_user (fregs[i], i + (__u64 __user *) data); 116 __put_user(fregs[i], i + (__u64 __user *) data);
117 } else { 117 } else {
118 for (i = 0; i < 32; i++) 118 for (i = 0; i < 32; i++)
119 __put_user ((__u64) -1, i + (__u64 __user *) data); 119 __put_user((__u64) -1, i + (__u64 __user *) data);
120 } 120 }
121 121
122 __put_user (child->thread.fpu.fcr31, data + 64); 122 __put_user(child->thread.fpu.fcr31, data + 64);
123 123
124 preempt_disable(); 124 preempt_disable();
125 if (cpu_has_fpu) { 125 if (cpu_has_fpu) {
@@ -142,12 +142,12 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
142 tmp = 0; 142 tmp = 0;
143 } 143 }
144 preempt_enable(); 144 preempt_enable();
145 __put_user (tmp, data + 65); 145 __put_user(tmp, data + 65);
146 146
147 return 0; 147 return 0;
148} 148}
149 149
150int ptrace_setfpregs (struct task_struct *child, __u32 __user *data) 150int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
151{ 151{
152 fpureg_t *fregs; 152 fpureg_t *fregs;
153 int i; 153 int i;
@@ -158,9 +158,9 @@ int ptrace_setfpregs (struct task_struct *child, __u32 __user *data)
158 fregs = get_fpu_regs(child); 158 fregs = get_fpu_regs(child);
159 159
160 for (i = 0; i < 32; i++) 160 for (i = 0; i < 32; i++)
161 __get_user (fregs[i], i + (__u64 __user *) data); 161 __get_user(fregs[i], i + (__u64 __user *) data);
162 162
163 __get_user (child->thread.fpu.fcr31, data + 64); 163 __get_user(child->thread.fpu.fcr31, data + 64);
164 164
165 /* FIR may not be written. */ 165 /* FIR may not be written. */
166 166
@@ -390,19 +390,19 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
390 } 390 }
391 391
392 case PTRACE_GETREGS: 392 case PTRACE_GETREGS:
393 ret = ptrace_getregs (child, (__u64 __user *) data); 393 ret = ptrace_getregs(child, (__u64 __user *) data);
394 break; 394 break;
395 395
396 case PTRACE_SETREGS: 396 case PTRACE_SETREGS:
397 ret = ptrace_setregs (child, (__u64 __user *) data); 397 ret = ptrace_setregs(child, (__u64 __user *) data);
398 break; 398 break;
399 399
400 case PTRACE_GETFPREGS: 400 case PTRACE_GETFPREGS:
401 ret = ptrace_getfpregs (child, (__u32 __user *) data); 401 ret = ptrace_getfpregs(child, (__u32 __user *) data);
402 break; 402 break;
403 403
404 case PTRACE_SETFPREGS: 404 case PTRACE_SETFPREGS:
405 ret = ptrace_setfpregs (child, (__u32 __user *) data); 405 ret = ptrace_setfpregs(child, (__u32 __user *) data);
406 break; 406 break;
407 407
408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 408 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index d9a39c169450..f2bffed94fa3 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -36,11 +36,11 @@
36#include <asm/uaccess.h> 36#include <asm/uaccess.h>
37#include <asm/bootinfo.h> 37#include <asm/bootinfo.h>
38 38
39int ptrace_getregs (struct task_struct *child, __s64 __user *data); 39int ptrace_getregs(struct task_struct *child, __s64 __user *data);
40int ptrace_setregs (struct task_struct *child, __s64 __user *data); 40int ptrace_setregs(struct task_struct *child, __s64 __user *data);
41 41
42int ptrace_getfpregs (struct task_struct *child, __u32 __user *data); 42int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
43int ptrace_setfpregs (struct task_struct *child, __u32 __user *data); 43int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
44 44
45/* 45/*
46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not 46 * Tracing a 32-bit process with a 64-bit strace and vice versa will not
@@ -346,19 +346,19 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
346 } 346 }
347 347
348 case PTRACE_GETREGS: 348 case PTRACE_GETREGS:
349 ret = ptrace_getregs (child, (__u64 __user *) (__u64) data); 349 ret = ptrace_getregs(child, (__u64 __user *) (__u64) data);
350 break; 350 break;
351 351
352 case PTRACE_SETREGS: 352 case PTRACE_SETREGS:
353 ret = ptrace_setregs (child, (__u64 __user *) (__u64) data); 353 ret = ptrace_setregs(child, (__u64 __user *) (__u64) data);
354 break; 354 break;
355 355
356 case PTRACE_GETFPREGS: 356 case PTRACE_GETFPREGS:
357 ret = ptrace_getfpregs (child, (__u32 __user *) (__u64) data); 357 ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
358 break; 358 break;
359 359
360 case PTRACE_SETFPREGS: 360 case PTRACE_SETFPREGS:
361 ret = ptrace_setfpregs (child, (__u32 __user *) (__u64) data); 361 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
362 break; 362 break;
363 363
364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */ 364 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 316685fca059..a06a27d6cfcd 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -51,10 +51,8 @@ EXPORT_SYMBOL(PCI_DMA_BUS_IS_PHYS);
51 * These are initialized so they are in the .data section 51 * These are initialized so they are in the .data section
52 */ 52 */
53unsigned long mips_machtype __read_mostly = MACH_UNKNOWN; 53unsigned long mips_machtype __read_mostly = MACH_UNKNOWN;
54unsigned long mips_machgroup __read_mostly = MACH_GROUP_UNKNOWN;
55 54
56EXPORT_SYMBOL(mips_machtype); 55EXPORT_SYMBOL(mips_machtype);
57EXPORT_SYMBOL(mips_machgroup);
58 56
59struct boot_mem_map boot_mem_map; 57struct boot_mem_map boot_mem_map;
60 58
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 2a08ce41bf2b..a4e106c56ab5 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -613,9 +613,9 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); 613 ret = current->thread.abi->setup_frame(ka, regs, sig, oldset);
614 614
615 spin_lock_irq(&current->sighand->siglock); 615 spin_lock_irq(&current->sighand->siglock);
616 sigorsets(&current->blocked,&current->blocked,&ka->sa.sa_mask); 616 sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
617 if (!(ka->sa.sa_flags & SA_NODEFER)) 617 if (!(ka->sa.sa_flags & SA_NODEFER))
618 sigaddset(&current->blocked,sig); 618 sigaddset(&current->blocked, sig);
619 recalc_sigpending(); 619 recalc_sigpending();
620 spin_unlock_irq(&current->sighand->siglock); 620 spin_unlock_irq(&current->sighand->siglock);
621 621
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 64b612a0a622..572c610db1b1 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -261,11 +261,11 @@ static inline int put_sigset(const sigset_t *kbuf, compat_sigset_t __user *ubuf)
261 default: 261 default:
262 __put_sigset_unknown_nsig(); 262 __put_sigset_unknown_nsig();
263 case 2: 263 case 2:
264 err |= __put_user (kbuf->sig[1] >> 32, &ubuf->sig[3]); 264 err |= __put_user(kbuf->sig[1] >> 32, &ubuf->sig[3]);
265 err |= __put_user (kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]); 265 err |= __put_user(kbuf->sig[1] & 0xffffffff, &ubuf->sig[2]);
266 case 1: 266 case 1:
267 err |= __put_user (kbuf->sig[0] >> 32, &ubuf->sig[1]); 267 err |= __put_user(kbuf->sig[0] >> 32, &ubuf->sig[1]);
268 err |= __put_user (kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]); 268 err |= __put_user(kbuf->sig[0] & 0xffffffff, &ubuf->sig[0]);
269 } 269 }
270 270
271 return err; 271 return err;
@@ -283,12 +283,12 @@ static inline int get_sigset(sigset_t *kbuf, const compat_sigset_t __user *ubuf)
283 default: 283 default:
284 __get_sigset_unknown_nsig(); 284 __get_sigset_unknown_nsig();
285 case 2: 285 case 2:
286 err |= __get_user (sig[3], &ubuf->sig[3]); 286 err |= __get_user(sig[3], &ubuf->sig[3]);
287 err |= __get_user (sig[2], &ubuf->sig[2]); 287 err |= __get_user(sig[2], &ubuf->sig[2]);
288 kbuf->sig[1] = sig[2] | (sig[3] << 32); 288 kbuf->sig[1] = sig[2] | (sig[3] << 32);
289 case 1: 289 case 1:
290 err |= __get_user (sig[1], &ubuf->sig[1]); 290 err |= __get_user(sig[1], &ubuf->sig[1]);
291 err |= __get_user (sig[0], &ubuf->sig[0]); 291 err |= __get_user(sig[0], &ubuf->sig[0]);
292 kbuf->sig[0] = sig[0] | (sig[1] << 32); 292 kbuf->sig[0] = sig[0] | (sig[1] << 32);
293 } 293 }
294 294
@@ -412,10 +412,10 @@ asmlinkage int sys32_sigaltstack(nabi_no_regargs struct pt_regs regs)
412 return -EFAULT; 412 return -EFAULT;
413 } 413 }
414 414
415 set_fs (KERNEL_DS); 415 set_fs(KERNEL_DS);
416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL, 416 ret = do_sigaltstack(uss ? (stack_t __user *)&kss : NULL,
417 uoss ? (stack_t __user *)&koss : NULL, usp); 417 uoss ? (stack_t __user *)&koss : NULL, usp);
418 set_fs (old_fs); 418 set_fs(old_fs);
419 419
420 if (!ret && uoss) { 420 if (!ret && uoss) {
421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss))) 421 if (!access_ok(VERIFY_WRITE, uoss, sizeof(*uoss)))
@@ -559,9 +559,9 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
559 /* It is more difficult to avoid calling this function than to 559 /* It is more difficult to avoid calling this function than to
560 call it and ignore errors. */ 560 call it and ignore errors. */
561 old_fs = get_fs(); 561 old_fs = get_fs();
562 set_fs (KERNEL_DS); 562 set_fs(KERNEL_DS);
563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]); 563 do_sigaltstack((stack_t __user *)&st, NULL, regs.regs[29]);
564 set_fs (old_fs); 564 set_fs(old_fs);
565 565
566 /* 566 /*
567 * Don't let your children do this ... 567 * Don't let your children do this ...
@@ -746,11 +746,11 @@ asmlinkage int sys32_rt_sigprocmask(int how, compat_sigset_t __user *set,
746 if (set && get_sigset(&new_set, set)) 746 if (set && get_sigset(&new_set, set))
747 return -EFAULT; 747 return -EFAULT;
748 748
749 set_fs (KERNEL_DS); 749 set_fs(KERNEL_DS);
750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL, 750 ret = sys_rt_sigprocmask(how, set ? (sigset_t __user *)&new_set : NULL,
751 oset ? (sigset_t __user *)&old_set : NULL, 751 oset ? (sigset_t __user *)&old_set : NULL,
752 sigsetsize); 752 sigsetsize);
753 set_fs (old_fs); 753 set_fs(old_fs);
754 754
755 if (!ret && oset && put_sigset(&old_set, oset)) 755 if (!ret && oset && put_sigset(&old_set, oset))
756 return -EFAULT; 756 return -EFAULT;
@@ -765,9 +765,9 @@ asmlinkage int sys32_rt_sigpending(compat_sigset_t __user *uset,
765 sigset_t set; 765 sigset_t set;
766 mm_segment_t old_fs = get_fs(); 766 mm_segment_t old_fs = get_fs();
767 767
768 set_fs (KERNEL_DS); 768 set_fs(KERNEL_DS);
769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize); 769 ret = sys_rt_sigpending((sigset_t __user *)&set, sigsetsize);
770 set_fs (old_fs); 770 set_fs(old_fs);
771 771
772 if (!ret && put_sigset(&set, uset)) 772 if (!ret && put_sigset(&set, uset))
773 return -EFAULT; 773 return -EFAULT;
@@ -781,12 +781,12 @@ asmlinkage int sys32_rt_sigqueueinfo(int pid, int sig, compat_siginfo_t __user *
781 int ret; 781 int ret;
782 mm_segment_t old_fs = get_fs(); 782 mm_segment_t old_fs = get_fs();
783 783
784 if (copy_from_user (&info, uinfo, 3*sizeof(int)) || 784 if (copy_from_user(&info, uinfo, 3*sizeof(int)) ||
785 copy_from_user (info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE)) 785 copy_from_user(info._sifields._pad, uinfo->_sifields._pad, SI_PAD_SIZE))
786 return -EFAULT; 786 return -EFAULT;
787 set_fs (KERNEL_DS); 787 set_fs(KERNEL_DS);
788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info); 788 ret = sys_rt_sigqueueinfo(pid, sig, (siginfo_t __user *)&info);
789 set_fs (old_fs); 789 set_fs(old_fs);
790 return ret; 790 return ret;
791} 791}
792 792
@@ -801,10 +801,10 @@ sys32_waitid(int which, compat_pid_t pid,
801 mm_segment_t old_fs = get_fs(); 801 mm_segment_t old_fs = get_fs();
802 802
803 info.si_signo = 0; 803 info.si_signo = 0;
804 set_fs (KERNEL_DS); 804 set_fs(KERNEL_DS);
805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options, 805 ret = sys_waitid(which, pid, (siginfo_t __user *) &info, options,
806 uru ? (struct rusage __user *) &ru : NULL); 806 uru ? (struct rusage __user *) &ru : NULL);
807 set_fs (old_fs); 807 set_fs(old_fs);
808 808
809 if (ret < 0 || info.si_signo == 0) 809 if (ret < 0 || info.si_signo == 0)
810 return ret; 810 return ret;
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index eb7e05926ebe..bb277e82d421 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -88,7 +88,7 @@ struct rt_sigframe_n32 {
88 88
89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ 89#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */
90 90
91extern void sigset_from_compat (sigset_t *set, compat_sigset_t *compat); 91extern void sigset_from_compat(sigset_t *set, compat_sigset_t *compat);
92 92
93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) 93asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
94{ 94{
@@ -105,7 +105,7 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
105 unewset = (compat_sigset_t __user *) regs.regs[4]; 105 unewset = (compat_sigset_t __user *) regs.regs[4];
106 if (copy_from_user(&uset, unewset, sizeof(uset))) 106 if (copy_from_user(&uset, unewset, sizeof(uset)))
107 return -EFAULT; 107 return -EFAULT;
108 sigset_from_compat (&newset, &uset); 108 sigset_from_compat(&newset, &uset);
109 sigdelsetmask(&newset, ~_BLOCKABLE); 109 sigdelsetmask(&newset, ~_BLOCKABLE);
110 110
111 spin_lock_irq(&current->sighand->siglock); 111 spin_lock_irq(&current->sighand->siglock);
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 05dcce416325..94e210cc6cb6 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -353,7 +353,7 @@ void core_send_ipi(int cpu, unsigned int action)
353 unsigned long flags; 353 unsigned long flags;
354 int vpflags; 354 int vpflags;
355 355
356 local_irq_save (flags); 356 local_irq_save(flags);
357 357
358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */ 358 vpflags = dvpe(); /* cant access the other CPU's registers whilst MVPE enabled */
359 359
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 73b0dab02668..432f2e376aea 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -38,6 +38,7 @@
38#include <asm/system.h> 38#include <asm/system.h>
39#include <asm/mmu_context.h> 39#include <asm/mmu_context.h>
40#include <asm/smp.h> 40#include <asm/smp.h>
41#include <asm/time.h>
41 42
42#ifdef CONFIG_MIPS_MT_SMTC 43#ifdef CONFIG_MIPS_MT_SMTC
43#include <asm/mipsmtregs.h> 44#include <asm/mipsmtregs.h>
@@ -70,6 +71,7 @@ asmlinkage __cpuinit void start_secondary(void)
70 cpu_probe(); 71 cpu_probe();
71 cpu_report(); 72 cpu_report();
72 per_cpu_trap_init(); 73 per_cpu_trap_init();
74 mips_clockevent_init();
73 prom_init_secondary(); 75 prom_init_secondary();
74 76
75 /* 77 /*
@@ -95,6 +97,8 @@ struct call_data_struct *call_data;
95 97
96/* 98/*
97 * Run a function on all other CPUs. 99 * Run a function on all other CPUs.
100 *
101 * <mask> cpuset_t of all processors to run the function on.
98 * <func> The function to run. This must be fast and non-blocking. 102 * <func> The function to run. This must be fast and non-blocking.
99 * <info> An arbitrary pointer to pass to the function. 103 * <info> An arbitrary pointer to pass to the function.
100 * <retry> If true, keep retrying until ready. 104 * <retry> If true, keep retrying until ready.
@@ -119,18 +123,20 @@ struct call_data_struct *call_data;
119 * Spin waiting for call_lock 123 * Spin waiting for call_lock
120 * Deadlock Deadlock 124 * Deadlock Deadlock
121 */ 125 */
122int smp_call_function (void (*func) (void *info), void *info, int retry, 126int smp_call_function_mask(cpumask_t mask, void (*func) (void *info),
123 int wait) 127 void *info, int retry, int wait)
124{ 128{
125 struct call_data_struct data; 129 struct call_data_struct data;
126 int i, cpus = num_online_cpus() - 1;
127 int cpu = smp_processor_id(); 130 int cpu = smp_processor_id();
131 int cpus;
128 132
129 /* 133 /*
130 * Can die spectacularly if this CPU isn't yet marked online 134 * Can die spectacularly if this CPU isn't yet marked online
131 */ 135 */
132 BUG_ON(!cpu_online(cpu)); 136 BUG_ON(!cpu_online(cpu));
133 137
138 cpu_clear(cpu, mask);
139 cpus = cpus_weight(mask);
134 if (!cpus) 140 if (!cpus)
135 return 0; 141 return 0;
136 142
@@ -149,9 +155,7 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
149 smp_mb(); 155 smp_mb();
150 156
151 /* Send a message to all other CPUs and wait for them to respond */ 157 /* Send a message to all other CPUs and wait for them to respond */
152 for_each_online_cpu(i) 158 core_send_ipi_mask(mask, SMP_CALL_FUNCTION);
153 if (i != cpu)
154 core_send_ipi(i, SMP_CALL_FUNCTION);
155 159
156 /* Wait for response */ 160 /* Wait for response */
157 /* FIXME: lock-up detection, backtrace on lock-up */ 161 /* FIXME: lock-up detection, backtrace on lock-up */
@@ -167,6 +171,11 @@ int smp_call_function (void (*func) (void *info), void *info, int retry,
167 return 0; 171 return 0;
168} 172}
169 173
174int smp_call_function(void (*func) (void *info), void *info, int retry,
175 int wait)
176{
177 return smp_call_function_mask(cpu_online_map, func, info, retry, wait);
178}
170 179
171void smp_call_function_interrupt(void) 180void smp_call_function_interrupt(void)
172{ 181{
@@ -197,8 +206,7 @@ void smp_call_function_interrupt(void)
197int smp_call_function_single(int cpu, void (*func) (void *info), void *info, 206int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
198 int retry, int wait) 207 int retry, int wait)
199{ 208{
200 struct call_data_struct data; 209 int ret, me;
201 int me;
202 210
203 /* 211 /*
204 * Can die spectacularly if this CPU isn't yet marked online 212 * Can die spectacularly if this CPU isn't yet marked online
@@ -217,33 +225,8 @@ int smp_call_function_single(int cpu, void (*func) (void *info), void *info,
217 return 0; 225 return 0;
218 } 226 }
219 227
220 /* Can deadlock when called with interrupts disabled */ 228 ret = smp_call_function_mask(cpumask_of_cpu(cpu), func, info, retry,
221 WARN_ON(irqs_disabled()); 229 wait);
222
223 data.func = func;
224 data.info = info;
225 atomic_set(&data.started, 0);
226 data.wait = wait;
227 if (wait)
228 atomic_set(&data.finished, 0);
229
230 spin_lock(&smp_call_lock);
231 call_data = &data;
232 smp_mb();
233
234 /* Send a message to the other CPU */
235 core_send_ipi(cpu, SMP_CALL_FUNCTION);
236
237 /* Wait for response */
238 /* FIXME: lock-up detection, backtrace on lock-up */
239 while (atomic_read(&data.started) != 1)
240 barrier();
241
242 if (wait)
243 while (atomic_read(&data.finished) != 1)
244 barrier();
245 call_data = NULL;
246 spin_unlock(&smp_call_lock);
247 230
248 put_cpu(); 231 put_cpu();
249 return 0; 232 return 0;
@@ -390,12 +373,15 @@ void flush_tlb_mm(struct mm_struct *mm)
390 preempt_disable(); 373 preempt_disable();
391 374
392 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { 375 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
393 smp_on_other_tlbs(flush_tlb_mm_ipi, (void *)mm); 376 smp_on_other_tlbs(flush_tlb_mm_ipi, mm);
394 } else { 377 } else {
395 int i; 378 cpumask_t mask = cpu_online_map;
396 for (i = 0; i < num_online_cpus(); i++) 379 unsigned int cpu;
397 if (smp_processor_id() != i) 380
398 cpu_context(i, mm) = 0; 381 cpu_clear(smp_processor_id(), mask);
382 for_each_online_cpu(cpu)
383 if (cpu_context(cpu, mm))
384 cpu_context(cpu, mm) = 0;
399 } 385 }
400 local_flush_tlb_mm(mm); 386 local_flush_tlb_mm(mm);
401 387
@@ -410,7 +396,7 @@ struct flush_tlb_data {
410 396
411static void flush_tlb_range_ipi(void *info) 397static void flush_tlb_range_ipi(void *info)
412{ 398{
413 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 399 struct flush_tlb_data *fd = info;
414 400
415 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); 401 local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2);
416} 402}
@@ -421,17 +407,21 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l
421 407
422 preempt_disable(); 408 preempt_disable();
423 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) { 409 if ((atomic_read(&mm->mm_users) != 1) || (current->mm != mm)) {
424 struct flush_tlb_data fd; 410 struct flush_tlb_data fd = {
411 .vma = vma,
412 .addr1 = start,
413 .addr2 = end,
414 };
425 415
426 fd.vma = vma; 416 smp_on_other_tlbs(flush_tlb_range_ipi, &fd);
427 fd.addr1 = start;
428 fd.addr2 = end;
429 smp_on_other_tlbs(flush_tlb_range_ipi, (void *)&fd);
430 } else { 417 } else {
431 int i; 418 cpumask_t mask = cpu_online_map;
432 for (i = 0; i < num_online_cpus(); i++) 419 unsigned int cpu;
433 if (smp_processor_id() != i) 420
434 cpu_context(i, mm) = 0; 421 cpu_clear(smp_processor_id(), mask);
422 for_each_online_cpu(cpu)
423 if (cpu_context(cpu, mm))
424 cpu_context(cpu, mm) = 0;
435 } 425 }
436 local_flush_tlb_range(vma, start, end); 426 local_flush_tlb_range(vma, start, end);
437 preempt_enable(); 427 preempt_enable();
@@ -439,23 +429,24 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned l
439 429
440static void flush_tlb_kernel_range_ipi(void *info) 430static void flush_tlb_kernel_range_ipi(void *info)
441{ 431{
442 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 432 struct flush_tlb_data *fd = info;
443 433
444 local_flush_tlb_kernel_range(fd->addr1, fd->addr2); 434 local_flush_tlb_kernel_range(fd->addr1, fd->addr2);
445} 435}
446 436
447void flush_tlb_kernel_range(unsigned long start, unsigned long end) 437void flush_tlb_kernel_range(unsigned long start, unsigned long end)
448{ 438{
449 struct flush_tlb_data fd; 439 struct flush_tlb_data fd = {
440 .addr1 = start,
441 .addr2 = end,
442 };
450 443
451 fd.addr1 = start; 444 on_each_cpu(flush_tlb_kernel_range_ipi, &fd, 1, 1);
452 fd.addr2 = end;
453 on_each_cpu(flush_tlb_kernel_range_ipi, (void *)&fd, 1, 1);
454} 445}
455 446
456static void flush_tlb_page_ipi(void *info) 447static void flush_tlb_page_ipi(void *info)
457{ 448{
458 struct flush_tlb_data *fd = (struct flush_tlb_data *)info; 449 struct flush_tlb_data *fd = info;
459 450
460 local_flush_tlb_page(fd->vma, fd->addr1); 451 local_flush_tlb_page(fd->vma, fd->addr1);
461} 452}
@@ -464,16 +455,20 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
464{ 455{
465 preempt_disable(); 456 preempt_disable();
466 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) { 457 if ((atomic_read(&vma->vm_mm->mm_users) != 1) || (current->mm != vma->vm_mm)) {
467 struct flush_tlb_data fd; 458 struct flush_tlb_data fd = {
459 .vma = vma,
460 .addr1 = page,
461 };
468 462
469 fd.vma = vma; 463 smp_on_other_tlbs(flush_tlb_page_ipi, &fd);
470 fd.addr1 = page;
471 smp_on_other_tlbs(flush_tlb_page_ipi, (void *)&fd);
472 } else { 464 } else {
473 int i; 465 cpumask_t mask = cpu_online_map;
474 for (i = 0; i < num_online_cpus(); i++) 466 unsigned int cpu;
475 if (smp_processor_id() != i) 467
476 cpu_context(i, vma->vm_mm) = 0; 468 cpu_clear(smp_processor_id(), mask);
469 for_each_online_cpu(cpu)
470 if (cpu_context(cpu, vma->vm_mm))
471 cpu_context(cpu, vma->vm_mm) = 0;
477 } 472 }
478 local_flush_tlb_page(vma, page); 473 local_flush_tlb_page(vma, page);
479 preempt_enable(); 474 preempt_enable();
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f09404377ef1..a8c1a698d588 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1,5 +1,6 @@
1/* Copyright (C) 2004 Mips Technologies, Inc */ 1/* Copyright (C) 2004 Mips Technologies, Inc */
2 2
3#include <linux/clockchips.h>
3#include <linux/kernel.h> 4#include <linux/kernel.h>
4#include <linux/sched.h> 5#include <linux/sched.h>
5#include <linux/cpumask.h> 6#include <linux/cpumask.h>
@@ -62,7 +63,7 @@ asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
62 * Clock interrupt "latch" buffers, per "CPU" 63 * Clock interrupt "latch" buffers, per "CPU"
63 */ 64 */
64 65
65unsigned int ipi_timer_latch[NR_CPUS]; 66static atomic_t ipi_timer_latch[NR_CPUS];
66 67
67/* 68/*
68 * Number of InterProcessor Interupt (IPI) message buffers to allocate 69 * Number of InterProcessor Interupt (IPI) message buffers to allocate
@@ -179,7 +180,7 @@ void __init sanitize_tlb_entries(void)
179 180
180static void smtc_configure_tlb(void) 181static void smtc_configure_tlb(void)
181{ 182{
182 int i,tlbsiz,vpes; 183 int i, tlbsiz, vpes;
183 unsigned long mvpconf0; 184 unsigned long mvpconf0;
184 unsigned long config1val; 185 unsigned long config1val;
185 186
@@ -296,8 +297,10 @@ int __init mipsmt_build_cpu_map(int start_cpu_slot)
296 __cpu_number_map[i] = i; 297 __cpu_number_map[i] = i;
297 __cpu_logical_map[i] = i; 298 __cpu_logical_map[i] = i;
298 } 299 }
300#ifdef CONFIG_MIPS_MT_FPAFF
299 /* Initialize map of CPUs with FPUs */ 301 /* Initialize map of CPUs with FPUs */
300 cpus_clear(mt_fpu_cpumask); 302 cpus_clear(mt_fpu_cpumask);
303#endif
301 304
302 /* One of those TC's is the one booting, and not a secondary... */ 305 /* One of those TC's is the one booting, and not a secondary... */
303 printk("%i available secondary CPU TC(s)\n", i - 1); 306 printk("%i available secondary CPU TC(s)\n", i - 1);
@@ -359,7 +362,7 @@ void mipsmt_prepare_cpus(void)
359 IPIQ[i].head = IPIQ[i].tail = NULL; 362 IPIQ[i].head = IPIQ[i].tail = NULL;
360 spin_lock_init(&IPIQ[i].lock); 363 spin_lock_init(&IPIQ[i].lock);
361 IPIQ[i].depth = 0; 364 IPIQ[i].depth = 0;
362 ipi_timer_latch[i] = 0; 365 atomic_set(&ipi_timer_latch[i], 0);
363 } 366 }
364 367
365 /* cpu_data index starts at zero */ 368 /* cpu_data index starts at zero */
@@ -369,7 +372,7 @@ void mipsmt_prepare_cpus(void)
369 cpu++; 372 cpu++;
370 373
371 /* Report on boot-time options */ 374 /* Report on boot-time options */
372 mips_mt_set_cpuoptions (); 375 mips_mt_set_cpuoptions();
373 if (vpelimit > 0) 376 if (vpelimit > 0)
374 printk("Limit of %d VPEs set\n", vpelimit); 377 printk("Limit of %d VPEs set\n", vpelimit);
375 if (tclimit > 0) 378 if (tclimit > 0)
@@ -420,7 +423,7 @@ void mipsmt_prepare_cpus(void)
420 * code. Leave it alone! 423 * code. Leave it alone!
421 */ 424 */
422 if (tc != 0) { 425 if (tc != 0) {
423 smtc_tc_setup(vpe,tc, cpu); 426 smtc_tc_setup(vpe, tc, cpu);
424 cpu++; 427 cpu++;
425 } 428 }
426 printk(" %d", tc); 429 printk(" %d", tc);
@@ -428,7 +431,7 @@ void mipsmt_prepare_cpus(void)
428 } 431 }
429 if (slop) { 432 if (slop) {
430 if (tc != 0) { 433 if (tc != 0) {
431 smtc_tc_setup(vpe,tc, cpu); 434 smtc_tc_setup(vpe, tc, cpu);
432 cpu++; 435 cpu++;
433 } 436 }
434 printk(" %d", tc); 437 printk(" %d", tc);
@@ -482,10 +485,12 @@ void mipsmt_prepare_cpus(void)
482 485
483 /* Set up coprocessor affinity CPU mask(s) */ 486 /* Set up coprocessor affinity CPU mask(s) */
484 487
488#ifdef CONFIG_MIPS_MT_FPAFF
485 for (tc = 0; tc < ntc; tc++) { 489 for (tc = 0; tc < ntc; tc++) {
486 if (cpu_data[tc].options & MIPS_CPU_FPU) 490 if (cpu_data[tc].options & MIPS_CPU_FPU)
487 cpu_set(tc, mt_fpu_cpumask); 491 cpu_set(tc, mt_fpu_cpumask);
488 } 492 }
493#endif
489 494
490 /* set up ipi interrupts... */ 495 /* set up ipi interrupts... */
491 496
@@ -567,7 +572,7 @@ void smtc_init_secondary(void)
567 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && 572 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
568 ((read_c0_tcbind() & TCBIND_CURVPE) 573 ((read_c0_tcbind() & TCBIND_CURVPE)
569 != cpu_data[smp_processor_id() - 1].vpe_id)){ 574 != cpu_data[smp_processor_id() - 1].vpe_id)){
570 write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ); 575 write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
571 } 576 }
572 577
573 local_irq_enable(); 578 local_irq_enable();
@@ -606,6 +611,60 @@ int setup_irq_smtc(unsigned int irq, struct irqaction * new,
606 return setup_irq(irq, new); 611 return setup_irq(irq, new);
607} 612}
608 613
614#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
615/*
616 * Support for IRQ affinity to TCs
617 */
618
619void smtc_set_irq_affinity(unsigned int irq, cpumask_t affinity)
620{
621 /*
622 * If a "fast path" cache of quickly decodable affinity state
623 * is maintained, this is where it gets done, on a call up
624 * from the platform affinity code.
625 */
626}
627
628void smtc_forward_irq(unsigned int irq)
629{
630 int target;
631
632 /*
633 * OK wise guy, now figure out how to get the IRQ
634 * to be serviced on an authorized "CPU".
635 *
636 * Ideally, to handle the situation where an IRQ has multiple
637 * eligible CPUS, we would maintain state per IRQ that would
638 * allow a fair distribution of service requests. Since the
639 * expected use model is any-or-only-one, for simplicity
640 * and efficiency, we just pick the easiest one to find.
641 */
642
643 target = first_cpu(irq_desc[irq].affinity);
644
645 /*
646 * We depend on the platform code to have correctly processed
647 * IRQ affinity change requests to ensure that the IRQ affinity
648 * mask has been purged of bits corresponding to nonexistent and
649 * offline "CPUs", and to TCs bound to VPEs other than the VPE
650 * connected to the physical interrupt input for the interrupt
651 * in question. Otherwise we have a nasty problem with interrupt
652 * mask management. This is best handled in non-performance-critical
653 * platform IRQ affinity setting code, to minimize interrupt-time
654 * checks.
655 */
656
657 /* If no one is eligible, service locally */
658 if (target >= NR_CPUS) {
659 do_IRQ_no_affinity(irq);
660 return;
661 }
662
663 smtc_send_ipi(target, IRQ_AFFINITY_IPI, irq);
664}
665
666#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
667
609/* 668/*
610 * IPI model for SMTC is tricky, because interrupts aren't TC-specific. 669 * IPI model for SMTC is tricky, because interrupts aren't TC-specific.
611 * Within a VPE one TC can interrupt another by different approaches. 670 * Within a VPE one TC can interrupt another by different approaches.
@@ -648,7 +707,7 @@ static void smtc_ipi_qdump(void)
648 * be done with the atomic.h primitives). And since this is 707 * be done with the atomic.h primitives). And since this is
649 * MIPS MT, we can assume that we have LL/SC. 708 * MIPS MT, we can assume that we have LL/SC.
650 */ 709 */
651static __inline__ int atomic_postincrement(unsigned int *pv) 710static inline int atomic_postincrement(atomic_t *v)
652{ 711{
653 unsigned long result; 712 unsigned long result;
654 713
@@ -659,9 +718,9 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
659 " addu %1, %0, 1 \n" 718 " addu %1, %0, 1 \n"
660 " sc %1, %2 \n" 719 " sc %1, %2 \n"
661 " beqz %1, 1b \n" 720 " beqz %1, 1b \n"
662 " sync \n" 721 __WEAK_LLSC_MB
663 : "=&r" (result), "=&r" (temp), "=m" (*pv) 722 : "=&r" (result), "=&r" (temp), "=m" (v->counter)
664 : "m" (*pv) 723 : "m" (v->counter)
665 : "memory"); 724 : "memory");
666 725
667 return result; 726 return result;
@@ -689,6 +748,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
689 pipi->arg = (void *)action; 748 pipi->arg = (void *)action;
690 pipi->dest = cpu; 749 pipi->dest = cpu;
691 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { 750 if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
751 if (type == SMTC_CLOCK_TICK)
752 atomic_inc(&ipi_timer_latch[cpu]);
692 /* If not on same VPE, enqueue and send cross-VPE interupt */ 753 /* If not on same VPE, enqueue and send cross-VPE interupt */
693 smtc_ipi_nq(&IPIQ[cpu], pipi); 754 smtc_ipi_nq(&IPIQ[cpu], pipi);
694 LOCK_CORE_PRA(); 755 LOCK_CORE_PRA();
@@ -730,6 +791,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
730 } 791 }
731 smtc_ipi_nq(&IPIQ[cpu], pipi); 792 smtc_ipi_nq(&IPIQ[cpu], pipi);
732 } else { 793 } else {
794 if (type == SMTC_CLOCK_TICK)
795 atomic_inc(&ipi_timer_latch[cpu]);
733 post_direct_ipi(cpu, pipi); 796 post_direct_ipi(cpu, pipi);
734 write_tc_c0_tchalt(0); 797 write_tc_c0_tchalt(0);
735 UNLOCK_CORE_PRA(); 798 UNLOCK_CORE_PRA();
@@ -747,6 +810,7 @@ static void post_direct_ipi(int cpu, struct smtc_ipi *pipi)
747 unsigned long tcrestart; 810 unsigned long tcrestart;
748 extern u32 kernelsp[NR_CPUS]; 811 extern u32 kernelsp[NR_CPUS];
749 extern void __smtc_ipi_vector(void); 812 extern void __smtc_ipi_vector(void);
813//printk("%s: on %d for %d\n", __func__, smp_processor_id(), cpu);
750 814
751 /* Extract Status, EPC from halted TC */ 815 /* Extract Status, EPC from halted TC */
752 tcstatus = read_tc_c0_tcstatus(); 816 tcstatus = read_tc_c0_tcstatus();
@@ -797,25 +861,31 @@ static void ipi_call_interrupt(void)
797 smp_call_function_interrupt(); 861 smp_call_function_interrupt();
798} 862}
799 863
864DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
865
800void ipi_decode(struct smtc_ipi *pipi) 866void ipi_decode(struct smtc_ipi *pipi)
801{ 867{
868 unsigned int cpu = smp_processor_id();
869 struct clock_event_device *cd;
802 void *arg_copy = pipi->arg; 870 void *arg_copy = pipi->arg;
803 int type_copy = pipi->type; 871 int type_copy = pipi->type;
804 int dest_copy = pipi->dest; 872 int ticks;
805 873
806 smtc_ipi_nq(&freeIPIq, pipi); 874 smtc_ipi_nq(&freeIPIq, pipi);
807 switch (type_copy) { 875 switch (type_copy) {
808 case SMTC_CLOCK_TICK: 876 case SMTC_CLOCK_TICK:
809 irq_enter(); 877 irq_enter();
810 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + cp0_compare_irq]++; 878 kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
811 /* Invoke Clock "Interrupt" */ 879 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
812 ipi_timer_latch[dest_copy] = 0; 880 ticks = atomic_read(&ipi_timer_latch[cpu]);
813#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG 881 atomic_sub(ticks, &ipi_timer_latch[cpu]);
814 clock_hang_reported[dest_copy] = 0; 882 while (ticks) {
815#endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */ 883 cd->event_handler(cd);
816 local_timer_interrupt(0, NULL); 884 ticks--;
885 }
817 irq_exit(); 886 irq_exit();
818 break; 887 break;
888
819 case LINUX_SMP_IPI: 889 case LINUX_SMP_IPI:
820 switch ((int)arg_copy) { 890 switch ((int)arg_copy) {
821 case SMP_RESCHEDULE_YOURSELF: 891 case SMP_RESCHEDULE_YOURSELF:
@@ -830,6 +900,15 @@ void ipi_decode(struct smtc_ipi *pipi)
830 break; 900 break;
831 } 901 }
832 break; 902 break;
903#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
904 case IRQ_AFFINITY_IPI:
905 /*
906 * Accept a "forwarded" interrupt that was initially
907 * taken by a TC who doesn't have affinity for the IRQ.
908 */
909 do_IRQ_no_affinity((int)arg_copy);
910 break;
911#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
833 default: 912 default:
834 printk("Impossible SMTC IPI Type 0x%x\n", type_copy); 913 printk("Impossible SMTC IPI Type 0x%x\n", type_copy);
835 break; 914 break;
@@ -858,25 +937,6 @@ void deferred_smtc_ipi(void)
858} 937}
859 938
860/* 939/*
861 * Send clock tick to all TCs except the one executing the funtion
862 */
863
864void smtc_timer_broadcast(void)
865{
866 int cpu;
867 int myTC = cpu_data[smp_processor_id()].tc_id;
868 int myVPE = cpu_data[smp_processor_id()].vpe_id;
869
870 smtc_cpu_stats[smp_processor_id()].timerints++;
871
872 for_each_online_cpu(cpu) {
873 if (cpu_data[cpu].vpe_id == myVPE &&
874 cpu_data[cpu].tc_id != myTC)
875 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
876 }
877}
878
879/*
880 * Cross-VPE interrupts in the SMTC prototype use "software interrupts" 940 * Cross-VPE interrupts in the SMTC prototype use "software interrupts"
881 * set via cross-VPE MTTR manipulation of the Cause register. It would be 941 * set via cross-VPE MTTR manipulation of the Cause register. It would be
882 * in some regards preferable to have external logic for "doorbell" hardware 942 * in some regards preferable to have external logic for "doorbell" hardware
@@ -1117,11 +1177,11 @@ void smtc_idle_loop_hook(void)
1117 for (tc = 0; tc < NR_CPUS; tc++) { 1177 for (tc = 0; tc < NR_CPUS; tc++) {
1118 /* Don't check ourself - we'll dequeue IPIs just below */ 1178 /* Don't check ourself - we'll dequeue IPIs just below */
1119 if ((tc != smp_processor_id()) && 1179 if ((tc != smp_processor_id()) &&
1120 ipi_timer_latch[tc] > timerq_limit) { 1180 atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
1121 if (clock_hang_reported[tc] == 0) { 1181 if (clock_hang_reported[tc] == 0) {
1122 pdb_msg += sprintf(pdb_msg, 1182 pdb_msg += sprintf(pdb_msg,
1123 "TC %d looks hung with timer latch at %d\n", 1183 "TC %d looks hung with timer latch at %d\n",
1124 tc, ipi_timer_latch[tc]); 1184 tc, atomic_read(&ipi_timer_latch[tc]));
1125 clock_hang_reported[tc]++; 1185 clock_hang_reported[tc]++;
1126 } 1186 }
1127 } 1187 }
@@ -1162,7 +1222,7 @@ void smtc_soft_dump(void)
1162 smtc_ipi_qdump(); 1222 smtc_ipi_qdump();
1163 printk("Timer IPI Backlogs:\n"); 1223 printk("Timer IPI Backlogs:\n");
1164 for (i=0; i < NR_CPUS; i++) { 1224 for (i=0; i < NR_CPUS; i++) {
1165 printk("%d: %d\n", i, ipi_timer_latch[i]); 1225 printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
1166 } 1226 }
1167 printk("%d Recoveries of \"stolen\" FPU\n", 1227 printk("%d Recoveries of \"stolen\" FPU\n",
1168 atomic_read(&smtc_fpu_recoveries)); 1228 atomic_read(&smtc_fpu_recoveries));
@@ -1204,7 +1264,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1204 if (cpu_has_vtag_icache) 1264 if (cpu_has_vtag_icache)
1205 flush_icache_all(); 1265 flush_icache_all();
1206 /* Traverse all online CPUs (hack requires contigous range) */ 1266 /* Traverse all online CPUs (hack requires contigous range) */
1207 for (i = 0; i < num_online_cpus(); i++) { 1267 for_each_online_cpu(i) {
1208 /* 1268 /*
1209 * We don't need to worry about our own CPU, nor those of 1269 * We don't need to worry about our own CPU, nor those of
1210 * CPUs who don't share our TLB. 1270 * CPUs who don't share our TLB.
@@ -1233,7 +1293,7 @@ void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
1233 /* 1293 /*
1234 * SMTC shares the TLB within VPEs and possibly across all VPEs. 1294 * SMTC shares the TLB within VPEs and possibly across all VPEs.
1235 */ 1295 */
1236 for (i = 0; i < num_online_cpus(); i++) { 1296 for_each_online_cpu(i) {
1237 if ((smtc_status & SMTC_TLB_SHARED) || 1297 if ((smtc_status & SMTC_TLB_SHARED) ||
1238 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id)) 1298 (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
1239 cpu_context(i, mm) = asid_cache(i) = asid; 1299 cpu_context(i, mm) = asid_cache(i) = asid;
diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c
index 7c800ec3ff55..17c4374d2209 100644
--- a/arch/mips/kernel/syscall.c
+++ b/arch/mips/kernel/syscall.c
@@ -245,7 +245,7 @@ asmlinkage int sys_olduname(struct oldold_utsname __user * name)
245 245
246 if (!name) 246 if (!name)
247 return -EFAULT; 247 return -EFAULT;
248 if (!access_ok(VERIFY_WRITE,name,sizeof(struct oldold_utsname))) 248 if (!access_ok(VERIFY_WRITE, name, sizeof(struct oldold_utsname)))
249 return -EFAULT; 249 return -EFAULT;
250 250
251 error = __copy_to_user(&name->sysname, &utsname()->sysname, 251 error = __copy_to_user(&name->sysname, &utsname()->sysname,
@@ -314,8 +314,8 @@ asmlinkage int _sys_sysmips(int cmd, long arg1, int arg2, int arg3)
314 * 314 *
315 * This is really horribly ugly. 315 * This is really horribly ugly.
316 */ 316 */
317asmlinkage int sys_ipc (unsigned int call, int first, int second, 317asmlinkage int sys_ipc(unsigned int call, int first, int second,
318 unsigned long third, void __user *ptr, long fifth) 318 unsigned long third, void __user *ptr, long fifth)
319{ 319{
320 int version, ret; 320 int version, ret;
321 321
@@ -324,26 +324,26 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
324 324
325 switch (call) { 325 switch (call) {
326 case SEMOP: 326 case SEMOP:
327 return sys_semtimedop (first, (struct sembuf __user *)ptr, 327 return sys_semtimedop(first, (struct sembuf __user *)ptr,
328 second, NULL); 328 second, NULL);
329 case SEMTIMEDOP: 329 case SEMTIMEDOP:
330 return sys_semtimedop (first, (struct sembuf __user *)ptr, 330 return sys_semtimedop(first, (struct sembuf __user *)ptr,
331 second, 331 second,
332 (const struct timespec __user *)fifth); 332 (const struct timespec __user *)fifth);
333 case SEMGET: 333 case SEMGET:
334 return sys_semget (first, second, third); 334 return sys_semget(first, second, third);
335 case SEMCTL: { 335 case SEMCTL: {
336 union semun fourth; 336 union semun fourth;
337 if (!ptr) 337 if (!ptr)
338 return -EINVAL; 338 return -EINVAL;
339 if (get_user(fourth.__pad, (void __user *__user *) ptr)) 339 if (get_user(fourth.__pad, (void __user *__user *) ptr))
340 return -EFAULT; 340 return -EFAULT;
341 return sys_semctl (first, second, third, fourth); 341 return sys_semctl(first, second, third, fourth);
342 } 342 }
343 343
344 case MSGSND: 344 case MSGSND:
345 return sys_msgsnd (first, (struct msgbuf __user *) ptr, 345 return sys_msgsnd(first, (struct msgbuf __user *) ptr,
346 second, third); 346 second, third);
347 case MSGRCV: 347 case MSGRCV:
348 switch (version) { 348 switch (version) {
349 case 0: { 349 case 0: {
@@ -353,45 +353,45 @@ asmlinkage int sys_ipc (unsigned int call, int first, int second,
353 353
354 if (copy_from_user(&tmp, 354 if (copy_from_user(&tmp,
355 (struct ipc_kludge __user *) ptr, 355 (struct ipc_kludge __user *) ptr,
356 sizeof (tmp))) 356 sizeof(tmp)))
357 return -EFAULT; 357 return -EFAULT;
358 return sys_msgrcv (first, tmp.msgp, second, 358 return sys_msgrcv(first, tmp.msgp, second,
359 tmp.msgtyp, third); 359 tmp.msgtyp, third);
360 } 360 }
361 default: 361 default:
362 return sys_msgrcv (first, 362 return sys_msgrcv(first,
363 (struct msgbuf __user *) ptr, 363 (struct msgbuf __user *) ptr,
364 second, fifth, third); 364 second, fifth, third);
365 } 365 }
366 case MSGGET: 366 case MSGGET:
367 return sys_msgget ((key_t) first, second); 367 return sys_msgget((key_t) first, second);
368 case MSGCTL: 368 case MSGCTL:
369 return sys_msgctl (first, second, 369 return sys_msgctl(first, second,
370 (struct msqid_ds __user *) ptr); 370 (struct msqid_ds __user *) ptr);
371 371
372 case SHMAT: 372 case SHMAT:
373 switch (version) { 373 switch (version) {
374 default: { 374 default: {
375 unsigned long raddr; 375 unsigned long raddr;
376 ret = do_shmat (first, (char __user *) ptr, second, 376 ret = do_shmat(first, (char __user *) ptr, second,
377 &raddr); 377 &raddr);
378 if (ret) 378 if (ret)
379 return ret; 379 return ret;
380 return put_user (raddr, (unsigned long __user *) third); 380 return put_user(raddr, (unsigned long __user *) third);
381 } 381 }
382 case 1: /* iBCS2 emulator entry point */ 382 case 1: /* iBCS2 emulator entry point */
383 if (!segment_eq(get_fs(), get_ds())) 383 if (!segment_eq(get_fs(), get_ds()))
384 return -EINVAL; 384 return -EINVAL;
385 return do_shmat (first, (char __user *) ptr, second, 385 return do_shmat(first, (char __user *) ptr, second,
386 (unsigned long *) third); 386 (unsigned long *) third);
387 } 387 }
388 case SHMDT: 388 case SHMDT:
389 return sys_shmdt ((char __user *)ptr); 389 return sys_shmdt((char __user *)ptr);
390 case SHMGET: 390 case SHMGET:
391 return sys_shmget (first, second, third); 391 return sys_shmget(first, second, third);
392 case SHMCTL: 392 case SHMCTL:
393 return sys_shmctl (first, second, 393 return sys_shmctl(first, second,
394 (struct shmid_ds __user *) ptr); 394 (struct shmid_ds __user *) ptr);
395 default: 395 default:
396 return -ENOSYS; 396 return -ENOSYS;
397 } 397 }
diff --git a/arch/mips/kernel/sysirix.c b/arch/mips/kernel/sysirix.c
index 93a148486f88..ee7790d9debe 100644
--- a/arch/mips/kernel/sysirix.c
+++ b/arch/mips/kernel/sysirix.c
@@ -486,10 +486,10 @@ asmlinkage int irix_syssgi(struct pt_regs *regs)
486 486
487 switch (arg1) { 487 switch (arg1) {
488 case SGI_INV_SIZEOF: 488 case SGI_INV_SIZEOF:
489 retval = sizeof (inventory_t); 489 retval = sizeof(inventory_t);
490 break; 490 break;
491 case SGI_INV_READ: 491 case SGI_INV_READ:
492 retval = dump_inventory_to_user (buffer, count); 492 retval = dump_inventory_to_user(buffer, count);
493 break; 493 break;
494 default: 494 default:
495 retval = -EINVAL; 495 retval = -EINVAL;
@@ -778,7 +778,7 @@ asmlinkage int irix_times(struct tms __user *tbuf)
778 int err = 0; 778 int err = 0;
779 779
780 if (tbuf) { 780 if (tbuf) {
781 if (!access_ok(VERIFY_WRITE,tbuf,sizeof *tbuf)) 781 if (!access_ok(VERIFY_WRITE, tbuf, sizeof *tbuf))
782 return -EFAULT; 782 return -EFAULT;
783 783
784 err = __put_user(current->utime, &tbuf->tms_utime); 784 err = __put_user(current->utime, &tbuf->tms_utime);
@@ -1042,9 +1042,9 @@ asmlinkage unsigned long irix_mmap32(unsigned long addr, size_t len, int prot,
1042 long max_size = offset + len; 1042 long max_size = offset + len;
1043 1043
1044 if (max_size > file->f_path.dentry->d_inode->i_size) { 1044 if (max_size > file->f_path.dentry->d_inode->i_size) {
1045 old_pos = sys_lseek (fd, max_size - 1, 0); 1045 old_pos = sys_lseek(fd, max_size - 1, 0);
1046 sys_write (fd, (void __user *) "", 1); 1046 sys_write(fd, (void __user *) "", 1);
1047 sys_lseek (fd, old_pos, 0); 1047 sys_lseek(fd, old_pos, 0);
1048 } 1048 }
1049 } 1049 }
1050 } 1050 }
@@ -1176,7 +1176,7 @@ static int irix_xstat32_xlate(struct kstat *stat, void __user *ubuf)
1176 ub.st_ctime1 = stat->atime.tv_nsec; 1176 ub.st_ctime1 = stat->atime.tv_nsec;
1177 ub.st_blksize = stat->blksize; 1177 ub.st_blksize = stat->blksize;
1178 ub.st_blocks = stat->blocks; 1178 ub.st_blocks = stat->blocks;
1179 strcpy (ub.st_fstype, "efs"); 1179 strcpy(ub.st_fstype, "efs");
1180 1180
1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0; 1181 return copy_to_user(ubuf, &ub, sizeof(ub)) ? -EFAULT : 0;
1182} 1182}
@@ -1208,7 +1208,7 @@ static int irix_xstat64_xlate(struct kstat *stat, void __user *ubuf)
1208 ks.st_nlink = (u32) stat->nlink; 1208 ks.st_nlink = (u32) stat->nlink;
1209 ks.st_uid = (s32) stat->uid; 1209 ks.st_uid = (s32) stat->uid;
1210 ks.st_gid = (s32) stat->gid; 1210 ks.st_gid = (s32) stat->gid;
1211 ks.st_rdev = sysv_encode_dev (stat->rdev); 1211 ks.st_rdev = sysv_encode_dev(stat->rdev);
1212 ks.st_pad2[0] = ks.st_pad2[1] = 0; 1212 ks.st_pad2[0] = ks.st_pad2[1] = 0;
1213 ks.st_size = (long long) stat->size; 1213 ks.st_size = (long long) stat->size;
1214 ks.st_pad3 = 0; 1214 ks.st_pad3 = 0;
@@ -1527,9 +1527,9 @@ asmlinkage int irix_mmap64(struct pt_regs *regs)
1527 long max_size = off2 + len; 1527 long max_size = off2 + len;
1528 1528
1529 if (max_size > file->f_path.dentry->d_inode->i_size) { 1529 if (max_size > file->f_path.dentry->d_inode->i_size) {
1530 old_pos = sys_lseek (fd, max_size - 1, 0); 1530 old_pos = sys_lseek(fd, max_size - 1, 0);
1531 sys_write (fd, (void __user *) "", 1); 1531 sys_write(fd, (void __user *) "", 1);
1532 sys_lseek (fd, old_pos, 0); 1532 sys_lseek(fd, old_pos, 0);
1533 } 1533 }
1534 } 1534 }
1535 } 1535 }
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index 9a5596bf8571..5892491b40eb 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -11,6 +11,7 @@
11 * Free Software Foundation; either version 2 of the License, or (at your 11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 12 * option) any later version.
13 */ 13 */
14#include <linux/clockchips.h>
14#include <linux/types.h> 15#include <linux/types.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
16#include <linux/init.h> 17#include <linux/init.h>
@@ -24,6 +25,7 @@
24#include <linux/spinlock.h> 25#include <linux/spinlock.h>
25#include <linux/interrupt.h> 26#include <linux/interrupt.h>
26#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/kallsyms.h>
27 29
28#include <asm/bootinfo.h> 30#include <asm/bootinfo.h>
29#include <asm/cache.h> 31#include <asm/cache.h>
@@ -32,8 +34,11 @@
32#include <asm/cpu-features.h> 34#include <asm/cpu-features.h>
33#include <asm/div64.h> 35#include <asm/div64.h>
34#include <asm/sections.h> 36#include <asm/sections.h>
37#include <asm/smtc_ipi.h>
35#include <asm/time.h> 38#include <asm/time.h>
36 39
40#include <irq.h>
41
37/* 42/*
38 * The integer part of the number of usecs per jiffy is taken from tick, 43 * The integer part of the number of usecs per jiffy is taken from tick,
39 * but the fractional part is not recorded, so we calculate it using the 44 * but the fractional part is not recorded, so we calculate it using the
@@ -49,32 +54,27 @@
49 * forward reference 54 * forward reference
50 */ 55 */
51DEFINE_SPINLOCK(rtc_lock); 56DEFINE_SPINLOCK(rtc_lock);
57EXPORT_SYMBOL(rtc_lock);
52 58
53/* 59int __weak rtc_mips_set_time(unsigned long sec)
54 * By default we provide the null RTC ops
55 */
56static unsigned long null_rtc_get_time(void)
57{ 60{
58 return mktime(2000, 1, 1, 0, 0, 0); 61 return 0;
59} 62}
63EXPORT_SYMBOL(rtc_mips_set_time);
60 64
61static int null_rtc_set_time(unsigned long sec) 65int __weak rtc_mips_set_mmss(unsigned long nowtime)
62{ 66{
63 return 0; 67 return rtc_mips_set_time(nowtime);
64} 68}
65 69
66unsigned long (*rtc_mips_get_time)(void) = null_rtc_get_time; 70int update_persistent_clock(struct timespec now)
67int (*rtc_mips_set_time)(unsigned long) = null_rtc_set_time; 71{
68int (*rtc_mips_set_mmss)(unsigned long); 72 return rtc_mips_set_mmss(now.tv_sec);
69 73}
70 74
71/* how many counter cycles in a jiffy */ 75/* how many counter cycles in a jiffy */
72static unsigned long cycles_per_jiffy __read_mostly; 76static unsigned long cycles_per_jiffy __read_mostly;
73 77
74/* expirelo is the count value for next CPU timer interrupt */
75static unsigned int expirelo;
76
77
78/* 78/*
79 * Null timer ack for systems not needing one (e.g. i8254). 79 * Null timer ack for systems not needing one (e.g. i8254).
80 */ 80 */
@@ -93,18 +93,7 @@ static cycle_t null_hpt_read(void)
93 */ 93 */
94static void c0_timer_ack(void) 94static void c0_timer_ack(void)
95{ 95{
96 unsigned int count; 96 write_c0_compare(read_c0_compare());
97
98 /* Ack this timer interrupt and set the next one. */
99 expirelo += cycles_per_jiffy;
100 write_c0_compare(expirelo);
101
102 /* Check to see if we have missed any timer interrupts. */
103 while (((count = read_c0_count()) - expirelo) < 0x7fffffff) {
104 /* missed_timer_count++; */
105 expirelo = count + cycles_per_jiffy;
106 write_c0_compare(expirelo);
107 }
108} 97}
109 98
110/* 99/*
@@ -115,19 +104,9 @@ static cycle_t c0_hpt_read(void)
115 return read_c0_count(); 104 return read_c0_count();
116} 105}
117 106
118/* For use both as a high precision timer and an interrupt source. */
119static void __init c0_hpt_timer_init(void)
120{
121 expirelo = read_c0_count() + cycles_per_jiffy;
122 write_c0_compare(expirelo);
123}
124
125int (*mips_timer_state)(void); 107int (*mips_timer_state)(void);
126void (*mips_timer_ack)(void); 108void (*mips_timer_ack)(void);
127 109
128/* last time when xtime and rtc are sync'ed up */
129static long last_rtc_update;
130
131/* 110/*
132 * local_timer_interrupt() does profiling and process accounting 111 * local_timer_interrupt() does profiling and process accounting
133 * on a per-CPU basis. 112 * on a per-CPU basis.
@@ -144,60 +123,15 @@ void local_timer_interrupt(int irq, void *dev_id)
144 update_process_times(user_mode(get_irq_regs())); 123 update_process_times(user_mode(get_irq_regs()));
145} 124}
146 125
147/*
148 * High-level timer interrupt service routines. This function
149 * is set as irqaction->handler and is invoked through do_IRQ.
150 */
151irqreturn_t timer_interrupt(int irq, void *dev_id)
152{
153 write_seqlock(&xtime_lock);
154
155 mips_timer_ack();
156
157 /*
158 * call the generic timer interrupt handling
159 */
160 do_timer(1);
161
162 /*
163 * If we have an externally synchronized Linux clock, then update
164 * CMOS clock accordingly every ~11 minutes. rtc_mips_set_time() has to be
165 * called as close as possible to 500 ms before the new second starts.
166 */
167 if (ntp_synced() &&
168 xtime.tv_sec > last_rtc_update + 660 &&
169 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
170 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
171 if (rtc_mips_set_mmss(xtime.tv_sec) == 0) {
172 last_rtc_update = xtime.tv_sec;
173 } else {
174 /* do it again in 60 s */
175 last_rtc_update = xtime.tv_sec - 600;
176 }
177 }
178
179 write_sequnlock(&xtime_lock);
180
181 /*
182 * In UP mode, we call local_timer_interrupt() to do profiling
183 * and process accouting.
184 *
185 * In SMP mode, local_timer_interrupt() is invoked by appropriate
186 * low-level local timer interrupt handler.
187 */
188 local_timer_interrupt(irq, dev_id);
189
190 return IRQ_HANDLED;
191}
192
193int null_perf_irq(void) 126int null_perf_irq(void)
194{ 127{
195 return 0; 128 return 0;
196} 129}
197 130
131EXPORT_SYMBOL(null_perf_irq);
132
198int (*perf_irq)(void) = null_perf_irq; 133int (*perf_irq)(void) = null_perf_irq;
199 134
200EXPORT_SYMBOL(null_perf_irq);
201EXPORT_SYMBOL(perf_irq); 135EXPORT_SYMBOL(perf_irq);
202 136
203/* 137/*
@@ -215,7 +149,7 @@ EXPORT_SYMBOL_GPL(cp0_perfcount_irq);
215 * Possibly handle a performance counter interrupt. 149 * Possibly handle a performance counter interrupt.
216 * Return true if the timer interrupt should not be checked 150 * Return true if the timer interrupt should not be checked
217 */ 151 */
218static inline int handle_perf_irq (int r2) 152static inline int handle_perf_irq(int r2)
219{ 153{
220 /* 154 /*
221 * The performance counter overflow interrupt may be shared with the 155 * The performance counter overflow interrupt may be shared with the
@@ -229,63 +163,23 @@ static inline int handle_perf_irq (int r2)
229 !r2; 163 !r2;
230} 164}
231 165
232asmlinkage void ll_timer_interrupt(int irq)
233{
234 int r2 = cpu_has_mips_r2;
235
236 irq_enter();
237 kstat_this_cpu.irqs[irq]++;
238
239 if (handle_perf_irq(r2))
240 goto out;
241
242 if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
243 goto out;
244
245 timer_interrupt(irq, NULL);
246
247out:
248 irq_exit();
249}
250
251asmlinkage void ll_local_timer_interrupt(int irq)
252{
253 irq_enter();
254 if (smp_processor_id() != 0)
255 kstat_this_cpu.irqs[irq]++;
256
257 /* we keep interrupt disabled all the time */
258 local_timer_interrupt(irq, NULL);
259
260 irq_exit();
261}
262
263/* 166/*
264 * time_init() - it does the following things. 167 * time_init() - it does the following things.
265 * 168 *
266 * 1) board_time_init() - 169 * 1) plat_time_init() -
267 * a) (optional) set up RTC routines, 170 * a) (optional) set up RTC routines,
268 * b) (optional) calibrate and set the mips_hpt_frequency 171 * b) (optional) calibrate and set the mips_hpt_frequency
269 * (only needed if you intended to use cpu counter as timer interrupt 172 * (only needed if you intended to use cpu counter as timer interrupt
270 * source) 173 * source)
271 * 2) setup xtime based on rtc_mips_get_time(). 174 * 2) calculate a couple of cached variables for later usage
272 * 3) calculate a couple of cached variables for later usage 175 * 3) plat_timer_setup() -
273 * 4) plat_timer_setup() -
274 * a) (optional) over-write any choices made above by time_init(). 176 * a) (optional) over-write any choices made above by time_init().
275 * b) machine specific code should setup the timer irqaction. 177 * b) machine specific code should setup the timer irqaction.
276 * c) enable the timer interrupt 178 * c) enable the timer interrupt
277 */ 179 */
278 180
279void (*board_time_init)(void);
280
281unsigned int mips_hpt_frequency; 181unsigned int mips_hpt_frequency;
282 182
283static struct irqaction timer_irqaction = {
284 .handler = timer_interrupt,
285 .flags = IRQF_DISABLED | IRQF_PERCPU,
286 .name = "timer",
287};
288
289static unsigned int __init calibrate_hpt(void) 183static unsigned int __init calibrate_hpt(void)
290{ 184{
291 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz; 185 cycle_t frequency, hpt_start, hpt_end, hpt_count, hz;
@@ -334,6 +228,84 @@ struct clocksource clocksource_mips = {
334 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 228 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
335}; 229};
336 230
231static int mips_next_event(unsigned long delta,
232 struct clock_event_device *evt)
233{
234 unsigned int cnt;
235 int res;
236
237#ifdef CONFIG_MIPS_MT_SMTC
238 {
239 unsigned long flags, vpflags;
240 local_irq_save(flags);
241 vpflags = dvpe();
242#endif
243 cnt = read_c0_count();
244 cnt += delta;
245 write_c0_compare(cnt);
246 res = ((long)(read_c0_count() - cnt ) > 0) ? -ETIME : 0;
247#ifdef CONFIG_MIPS_MT_SMTC
248 evpe(vpflags);
249 local_irq_restore(flags);
250 }
251#endif
252 return res;
253}
254
255static void mips_set_mode(enum clock_event_mode mode,
256 struct clock_event_device *evt)
257{
258 /* Nothing to do ... */
259}
260
261static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
262static int cp0_timer_irq_installed;
263
264static irqreturn_t timer_interrupt(int irq, void *dev_id)
265{
266 const int r2 = cpu_has_mips_r2;
267 struct clock_event_device *cd;
268 int cpu = smp_processor_id();
269
270 /*
271 * Suckage alert:
272 * Before R2 of the architecture there was no way to see if a
273 * performance counter interrupt was pending, so we have to run
274 * the performance counter interrupt handler anyway.
275 */
276 if (handle_perf_irq(r2))
277 goto out;
278
279 /*
280 * The same applies to performance counter interrupts. But with the
281 * above we now know that the reason we got here must be a timer
282 * interrupt. Being the paranoiacs we are we check anyway.
283 */
284 if (!r2 || (read_c0_cause() & (1 << 30))) {
285 c0_timer_ack();
286#ifdef CONFIG_MIPS_MT_SMTC
287 if (cpu_data[cpu].vpe_id)
288 goto out;
289 cpu = 0;
290#endif
291 cd = &per_cpu(mips_clockevent_device, cpu);
292 cd->event_handler(cd);
293 }
294
295out:
296 return IRQ_HANDLED;
297}
298
299static struct irqaction timer_irqaction = {
300 .handler = timer_interrupt,
301#ifdef CONFIG_MIPS_MT_SMTC
302 .flags = IRQF_DISABLED,
303#else
304 .flags = IRQF_DISABLED | IRQF_PERCPU,
305#endif
306 .name = "timer",
307};
308
337static void __init init_mips_clocksource(void) 309static void __init init_mips_clocksource(void)
338{ 310{
339 u64 temp; 311 u64 temp;
@@ -357,19 +329,127 @@ static void __init init_mips_clocksource(void)
357 clocksource_register(&clocksource_mips); 329 clocksource_register(&clocksource_mips);
358} 330}
359 331
360void __init time_init(void) 332void __init __weak plat_time_init(void)
333{
334}
335
336void __init __weak plat_timer_setup(struct irqaction *irq)
337{
338}
339
340#ifdef CONFIG_MIPS_MT_SMTC
341DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
342
343static void smtc_set_mode(enum clock_event_mode mode,
344 struct clock_event_device *evt)
345{
346}
347
348int dummycnt[NR_CPUS];
349
350static void mips_broadcast(cpumask_t mask)
351{
352 unsigned int cpu;
353
354 for_each_cpu_mask(cpu, mask)
355 smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
356}
357
358static void setup_smtc_dummy_clockevent_device(void)
359{
360 //uint64_t mips_freq = mips_hpt_^frequency;
361 unsigned int cpu = smp_processor_id();
362 struct clock_event_device *cd;
363
364 cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
365
366 cd->name = "SMTC";
367 cd->features = CLOCK_EVT_FEAT_DUMMY;
368
369 /* Calculate the min / max delta */
370 cd->mult = 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
371 cd->shift = 0; //32;
372 cd->max_delta_ns = 0; //clockevent_delta2ns(0x7fffffff, cd);
373 cd->min_delta_ns = 0; //clockevent_delta2ns(0x30, cd);
374
375 cd->rating = 200;
376 cd->irq = 17; //-1;
377// if (cpu)
378// cd->cpumask = CPU_MASK_ALL; // cpumask_of_cpu(cpu);
379// else
380 cd->cpumask = cpumask_of_cpu(cpu);
381
382 cd->set_mode = smtc_set_mode;
383
384 cd->broadcast = mips_broadcast;
385
386 clockevents_register_device(cd);
387}
388#endif
389
390static void mips_event_handler(struct clock_event_device *dev)
361{ 391{
362 if (board_time_init) 392}
363 board_time_init();
364 393
365 if (!rtc_mips_set_mmss) 394void __cpuinit mips_clockevent_init(void)
366 rtc_mips_set_mmss = rtc_mips_set_time; 395{
396 uint64_t mips_freq = mips_hpt_frequency;
397 unsigned int cpu = smp_processor_id();
398 struct clock_event_device *cd;
399 unsigned int irq = MIPS_CPU_IRQ_BASE + 7;
367 400
368 xtime.tv_sec = rtc_mips_get_time(); 401 if (!cpu_has_counter)
369 xtime.tv_nsec = 0; 402 return;
370 403
371 set_normalized_timespec(&wall_to_monotonic, 404#ifdef CONFIG_MIPS_MT_SMTC
372 -xtime.tv_sec, -xtime.tv_nsec); 405 setup_smtc_dummy_clockevent_device();
406
407 /*
408 * On SMTC we only register VPE0's compare interrupt as clockevent
409 * device.
410 */
411 if (cpu)
412 return;
413#endif
414
415 cd = &per_cpu(mips_clockevent_device, cpu);
416
417 cd->name = "MIPS";
418 cd->features = CLOCK_EVT_FEAT_ONESHOT;
419
420 /* Calculate the min / max delta */
421 cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
422 cd->shift = 32;
423 cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
424 cd->min_delta_ns = clockevent_delta2ns(0x30, cd);
425
426 cd->rating = 300;
427 cd->irq = irq;
428#ifdef CONFIG_MIPS_MT_SMTC
429 cd->cpumask = CPU_MASK_ALL;
430#else
431 cd->cpumask = cpumask_of_cpu(cpu);
432#endif
433 cd->set_next_event = mips_next_event;
434 cd->set_mode = mips_set_mode;
435 cd->event_handler = mips_event_handler;
436
437 clockevents_register_device(cd);
438
439 if (!cp0_timer_irq_installed) {
440#ifdef CONFIG_MIPS_MT_SMTC
441#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
442 setup_irq_smtc(irq, &timer_irqaction, CPUCTR_IMASKBIT);
443#else
444 setup_irq(irq, &timer_irqaction);
445#endif /* CONFIG_MIPS_MT_SMTC */
446 cp0_timer_irq_installed = 1;
447 }
448}
449
450void __init time_init(void)
451{
452 plat_time_init();
373 453
374 /* Choose appropriate high precision timer routines. */ 454 /* Choose appropriate high precision timer routines. */
375 if (!cpu_has_counter && !clocksource_mips.read) 455 if (!cpu_has_counter && !clocksource_mips.read)
@@ -392,11 +472,6 @@ void __init time_init(void)
392 /* Calculate cache parameters. */ 472 /* Calculate cache parameters. */
393 cycles_per_jiffy = 473 cycles_per_jiffy =
394 (mips_hpt_frequency + HZ / 2) / HZ; 474 (mips_hpt_frequency + HZ / 2) / HZ;
395 /*
396 * This sets up the high precision
397 * timer for the first interrupt.
398 */
399 c0_hpt_timer_init();
400 } 475 }
401 } 476 }
402 if (!mips_hpt_frequency) 477 if (!mips_hpt_frequency)
@@ -406,6 +481,10 @@ void __init time_init(void)
406 printk("Using %u.%03u MHz high precision timer.\n", 481 printk("Using %u.%03u MHz high precision timer.\n",
407 ((mips_hpt_frequency + 500) / 1000) / 1000, 482 ((mips_hpt_frequency + 500) / 1000) / 1000,
408 ((mips_hpt_frequency + 500) / 1000) % 1000); 483 ((mips_hpt_frequency + 500) / 1000) % 1000);
484
485#ifdef CONFIG_IRQ_CPU
486 setup_irq(MIPS_CPU_IRQ_BASE + 7, &timer_irqaction);
487#endif
409 } 488 }
410 489
411 if (!mips_timer_ack) 490 if (!mips_timer_ack)
@@ -426,56 +505,5 @@ void __init time_init(void)
426 plat_timer_setup(&timer_irqaction); 505 plat_timer_setup(&timer_irqaction);
427 506
428 init_mips_clocksource(); 507 init_mips_clocksource();
508 mips_clockevent_init();
429} 509}
430
431#define FEBRUARY 2
432#define STARTOFTIME 1970
433#define SECDAY 86400L
434#define SECYR (SECDAY * 365)
435#define leapyear(y) ((!((y) % 4) && ((y) % 100)) || !((y) % 400))
436#define days_in_year(y) (leapyear(y) ? 366 : 365)
437#define days_in_month(m) (month_days[(m) - 1])
438
439static int month_days[12] = {
440 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
441};
442
443void to_tm(unsigned long tim, struct rtc_time *tm)
444{
445 long hms, day, gday;
446 int i;
447
448 gday = day = tim / SECDAY;
449 hms = tim % SECDAY;
450
451 /* Hours, minutes, seconds are easy */
452 tm->tm_hour = hms / 3600;
453 tm->tm_min = (hms % 3600) / 60;
454 tm->tm_sec = (hms % 3600) % 60;
455
456 /* Number of years in days */
457 for (i = STARTOFTIME; day >= days_in_year(i); i++)
458 day -= days_in_year(i);
459 tm->tm_year = i;
460
461 /* Number of months in days left */
462 if (leapyear(tm->tm_year))
463 days_in_month(FEBRUARY) = 29;
464 for (i = 1; day >= days_in_month(i); i++)
465 day -= days_in_month(i);
466 days_in_month(FEBRUARY) = 28;
467 tm->tm_mon = i - 1; /* tm_mon starts from 0 to 11 */
468
469 /* Days are what is left over (+1) from all that. */
470 tm->tm_mday = day + 1;
471
472 /*
473 * Determine the day of week
474 */
475 tm->tm_wday = (gday + 4) % 7; /* 1970/1/1 was Thursday */
476}
477
478EXPORT_SYMBOL(rtc_lock);
479EXPORT_SYMBOL(to_tm);
480EXPORT_SYMBOL(rtc_mips_set_time);
481EXPORT_SYMBOL(rtc_mips_get_time);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6379003f9d8d..632bce1bf420 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -295,7 +295,8 @@ void show_regs(struct pt_regs *regs)
295 if (1 <= cause && cause <= 5) 295 if (1 <= cause && cause <= 5)
296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
297 297
298 printk("PrId : %08x\n", read_c0_prid()); 298 printk("PrId : %08x (%s)\n", read_c0_prid(),
299 cpu_name_string());
299} 300}
300 301
301void show_registers(struct pt_regs *regs) 302void show_registers(struct pt_regs *regs)
@@ -627,7 +628,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
627 lose_fpu(1); 628 lose_fpu(1);
628 629
629 /* Run the emulator */ 630 /* Run the emulator */
630 sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu, 1); 631 sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
631 632
632 /* 633 /*
633 * We can't allow the emulated instruction to leave any of 634 * We can't allow the emulated instruction to leave any of
@@ -954,7 +955,7 @@ asmlinkage void do_reserved(struct pt_regs *regs)
954 */ 955 */
955static inline void parity_protection_init(void) 956static inline void parity_protection_init(void)
956{ 957{
957 switch (current_cpu_data.cputype) { 958 switch (current_cpu_type()) {
958 case CPU_24K: 959 case CPU_24K:
959 case CPU_34K: 960 case CPU_34K:
960 case CPU_5KC: 961 case CPU_5KC:
@@ -1075,8 +1076,8 @@ void *set_except_vector(int n, void *addr)
1075 1076
1076 exception_handlers[n] = handler; 1077 exception_handlers[n] = handler;
1077 if (n == 0 && cpu_has_divec) { 1078 if (n == 0 && cpu_has_divec) {
1078 *(volatile u32 *)(ebase + 0x200) = 0x08000000 | 1079 *(u32 *)(ebase + 0x200) = 0x08000000 |
1079 (0x03ffffff & (handler >> 2)); 1080 (0x03ffffff & (handler >> 2));
1080 flush_icache_range(ebase + 0x200, ebase + 0x204); 1081 flush_icache_range(ebase + 0x200, ebase + 0x204);
1081 } 1082 }
1082 return (void *)old_handler; 1083 return (void *)old_handler;
@@ -1165,11 +1166,11 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1165 1166
1166 if (cpu_has_veic) { 1167 if (cpu_has_veic) {
1167 if (board_bind_eic_interrupt) 1168 if (board_bind_eic_interrupt)
1168 board_bind_eic_interrupt (n, srs); 1169 board_bind_eic_interrupt(n, srs);
1169 } else if (cpu_has_vint) { 1170 } else if (cpu_has_vint) {
1170 /* SRSMap is only defined if shadow sets are implemented */ 1171 /* SRSMap is only defined if shadow sets are implemented */
1171 if (mips_srs_max() > 1) 1172 if (mips_srs_max() > 1)
1172 change_c0_srsmap (0xf << n*4, srs << n*4); 1173 change_c0_srsmap(0xf << n*4, srs << n*4);
1173 } 1174 }
1174 1175
1175 if (srs == 0) { 1176 if (srs == 0) {
@@ -1198,10 +1199,10 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1198 * Sigh... panicing won't help as the console 1199 * Sigh... panicing won't help as the console
1199 * is probably not configured :( 1200 * is probably not configured :(
1200 */ 1201 */
1201 panic ("VECTORSPACING too small"); 1202 panic("VECTORSPACING too small");
1202 } 1203 }
1203 1204
1204 memcpy (b, &except_vec_vi, handler_len); 1205 memcpy(b, &except_vec_vi, handler_len);
1205#ifdef CONFIG_MIPS_MT_SMTC 1206#ifdef CONFIG_MIPS_MT_SMTC
1206 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ 1207 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1207 1208
@@ -1370,9 +1371,9 @@ void __init per_cpu_trap_init(void)
1370#endif /* CONFIG_MIPS_MT_SMTC */ 1371#endif /* CONFIG_MIPS_MT_SMTC */
1371 1372
1372 if (cpu_has_veic || cpu_has_vint) { 1373 if (cpu_has_veic || cpu_has_vint) {
1373 write_c0_ebase (ebase); 1374 write_c0_ebase(ebase);
1374 /* Setting vector spacing enables EI/VI mode */ 1375 /* Setting vector spacing enables EI/VI mode */
1375 change_c0_intctl (0x3e0, VECTORSPACING); 1376 change_c0_intctl(0x3e0, VECTORSPACING);
1376 } 1377 }
1377 if (cpu_has_divec) { 1378 if (cpu_has_divec) {
1378 if (cpu_has_mipsmt) { 1379 if (cpu_has_mipsmt) {
@@ -1390,8 +1391,8 @@ void __init per_cpu_trap_init(void)
1390 * o read IntCtl.IPPCI to determine the performance counter interrupt 1391 * o read IntCtl.IPPCI to determine the performance counter interrupt
1391 */ 1392 */
1392 if (cpu_has_mips_r2) { 1393 if (cpu_has_mips_r2) {
1393 cp0_compare_irq = (read_c0_intctl () >> 29) & 7; 1394 cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
1394 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7; 1395 cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
1395 if (cp0_perfcount_irq == cp0_compare_irq) 1396 if (cp0_perfcount_irq == cp0_compare_irq)
1396 cp0_perfcount_irq = -1; 1397 cp0_perfcount_irq = -1;
1397 } else { 1398 } else {
@@ -1429,14 +1430,17 @@ void __init per_cpu_trap_init(void)
1429} 1430}
1430 1431
1431/* Install CPU exception handler */ 1432/* Install CPU exception handler */
1432void __init set_handler (unsigned long offset, void *addr, unsigned long size) 1433void __init set_handler(unsigned long offset, void *addr, unsigned long size)
1433{ 1434{
1434 memcpy((void *)(ebase + offset), addr, size); 1435 memcpy((void *)(ebase + offset), addr, size);
1435 flush_icache_range(ebase + offset, ebase + offset + size); 1436 flush_icache_range(ebase + offset, ebase + offset + size);
1436} 1437}
1437 1438
1439static char panic_null_cerr[] __initdata =
1440 "Trying to set NULL cache error exception handler";
1441
1438/* Install uncached CPU exception handler */ 1442/* Install uncached CPU exception handler */
1439void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size) 1443void __init set_uncached_handler(unsigned long offset, void *addr, unsigned long size)
1440{ 1444{
1441#ifdef CONFIG_32BIT 1445#ifdef CONFIG_32BIT
1442 unsigned long uncached_ebase = KSEG1ADDR(ebase); 1446 unsigned long uncached_ebase = KSEG1ADDR(ebase);
@@ -1445,6 +1449,9 @@ void __init set_uncached_handler (unsigned long offset, void *addr, unsigned lon
1445 unsigned long uncached_ebase = TO_UNCAC(ebase); 1449 unsigned long uncached_ebase = TO_UNCAC(ebase);
1446#endif 1450#endif
1447 1451
1452 if (!addr)
1453 panic(panic_null_cerr);
1454
1448 memcpy((void *)(uncached_ebase + offset), addr, size); 1455 memcpy((void *)(uncached_ebase + offset), addr, size);
1449} 1456}
1450 1457
@@ -1464,7 +1471,7 @@ void __init trap_init(void)
1464 unsigned long i; 1471 unsigned long i;
1465 1472
1466 if (cpu_has_veic || cpu_has_vint) 1473 if (cpu_has_veic || cpu_has_vint)
1467 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64); 1474 ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64);
1468 else 1475 else
1469 ebase = CAC_BASE; 1476 ebase = CAC_BASE;
1470 1477
@@ -1490,7 +1497,7 @@ void __init trap_init(void)
1490 * destination. 1497 * destination.
1491 */ 1498 */
1492 if (cpu_has_ejtag && board_ejtag_handler_setup) 1499 if (cpu_has_ejtag && board_ejtag_handler_setup)
1493 board_ejtag_handler_setup (); 1500 board_ejtag_handler_setup();
1494 1501
1495 /* 1502 /*
1496 * Only some CPUs have the watch exceptions. 1503 * Only some CPUs have the watch exceptions.
@@ -1543,8 +1550,8 @@ void __init trap_init(void)
1543 set_except_vector(12, handle_ov); 1550 set_except_vector(12, handle_ov);
1544 set_except_vector(13, handle_tr); 1551 set_except_vector(13, handle_tr);
1545 1552
1546 if (current_cpu_data.cputype == CPU_R6000 || 1553 if (current_cpu_type() == CPU_R6000 ||
1547 current_cpu_data.cputype == CPU_R6000A) { 1554 current_cpu_type() == CPU_R6000A) {
1548 /* 1555 /*
1549 * The R6000 is the only R-series CPU that features a machine 1556 * The R6000 is the only R-series CPU that features a machine
1550 * check exception (similar to the R4000 cache error) and 1557 * check exception (similar to the R4000 cache error) and
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index d34b1fb3665d..c327b21bca81 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -481,7 +481,7 @@ fault:
481 if (fixup_exception(regs)) 481 if (fixup_exception(regs))
482 return; 482 return;
483 483
484 die_if_kernel ("Unhandled kernel unaligned access", regs); 484 die_if_kernel("Unhandled kernel unaligned access", regs);
485 send_sig(SIGSEGV, current, 1); 485 send_sig(SIGSEGV, current, 1);
486 486
487 return; 487 return;
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 087ab997487d..84f9a4cc6f2f 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -6,163 +6,202 @@
6OUTPUT_ARCH(mips) 6OUTPUT_ARCH(mips)
7ENTRY(kernel_entry) 7ENTRY(kernel_entry)
8jiffies = JIFFIES; 8jiffies = JIFFIES;
9
9SECTIONS 10SECTIONS
10{ 11{
11#ifdef CONFIG_BOOT_ELF64 12#ifdef CONFIG_BOOT_ELF64
12 /* Read-only sections, merged into text segment: */ 13 /* Read-only sections, merged into text segment: */
13 /* . = 0xc000000000000000; */ 14 /* . = 0xc000000000000000; */
14 15
15 /* This is the value for an Origin kernel, taken from an IRIX kernel. */ 16 /* This is the value for an Origin kernel, taken from an IRIX kernel. */
16 /* . = 0xc00000000001c000; */ 17 /* . = 0xc00000000001c000; */
17 18
18 /* Set the vaddr for the text segment to a value 19 /* Set the vaddr for the text segment to a value
19 >= 0xa800 0000 0001 9000 if no symmon is going to configured 20 * >= 0xa800 0000 0001 9000 if no symmon is going to configured
20 >= 0xa800 0000 0030 0000 otherwise */ 21 * >= 0xa800 0000 0030 0000 otherwise
22 */
21 23
22 /* . = 0xa800000000300000; */ 24 /* . = 0xa800000000300000; */
23 /* . = 0xa800000000300000; */ 25 /* . = 0xa800000000300000; */
24 . = 0xffffffff80300000; 26 . = 0xffffffff80300000;
25#endif 27#endif
26 . = LOADADDR; 28 . = LOADADDR;
27 /* read-only */ 29 /* read-only */
28 _text = .; /* Text and read-only data */ 30 _text = .; /* Text and read-only data */
29 .text : { 31 .text : {
30 TEXT_TEXT 32 TEXT_TEXT
31 SCHED_TEXT 33 SCHED_TEXT
32 LOCK_TEXT 34 LOCK_TEXT
33 *(.fixup) 35 *(.fixup)
34 *(.gnu.warning) 36 *(.gnu.warning)
35 } =0 37 } =0
36 38 _etext = .; /* End of text section */
37 _etext = .; /* End of text section */ 39
38 40 /* Exception table */
39 . = ALIGN(16); /* Exception table */ 41 . = ALIGN(16);
40 __start___ex_table = .; 42 __ex_table : {
41 __ex_table : { *(__ex_table) } 43 __start___ex_table = .;
42 __stop___ex_table = .; 44 *(__ex_table)
43 45 __stop___ex_table = .;
44 __start___dbe_table = .; /* Exception table for data bus errors */ 46 }
45 __dbe_table : { *(__dbe_table) } 47
46 __stop___dbe_table = .; 48 /* Exception table for data bus errors */
47 49 __dbe_table : {
48 NOTES 50 __start___dbe_table = .;
49 51 *(__dbe_table)
50 RODATA 52 __stop___dbe_table = .;
51 53 }
52 /* writeable */ 54 RODATA
53 .data : { /* Data */ 55
54 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */ 56 /* writeable */
55 /* 57 .data : { /* Data */
56 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which 58 . = . + DATAOFFSET; /* for CONFIG_MAPPED_KERNEL */
57 * limits the maximum alignment to at most 32kB and results in the following 59 /*
58 * warning: 60 * This ALIGN is needed as a workaround for a bug a gcc bug upto 4.1 which
59 * 61 * limits the maximum alignment to at most 32kB and results in the following
60 * CC arch/mips/kernel/init_task.o 62 * warning:
61 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’ 63 *
62 * is greater than maximum object file alignment. Using 32768 64 * CC arch/mips/kernel/init_task.o
63 */ 65 * arch/mips/kernel/init_task.c:30: warning: alignment of ‘init_thread_union’
64 . = ALIGN(_PAGE_SIZE); 66 * is greater than maximum object file alignment. Using 32768
65 *(.data.init_task) 67 */
66 68 . = ALIGN(_PAGE_SIZE);
67 DATA_DATA 69 *(.data.init_task)
68 70
69 CONSTRUCTORS 71 DATA_DATA
70 } 72 CONSTRUCTORS
71 _gp = . + 0x8000; 73 }
72 .lit8 : { *(.lit8) } 74 _gp = . + 0x8000;
73 .lit4 : { *(.lit4) } 75 .lit8 : {
74 /* We want the small data sections together, so single-instruction offsets 76 *(.lit8)
75 can access them all, and initialized data all before uninitialized, so 77 }
76 we can shorten the on-disk segment size. */ 78 .lit4 : {
77 .sdata : { *(.sdata) } 79 *(.lit4)
78 80 }
79 . = ALIGN(_PAGE_SIZE); 81 /* We want the small data sections together, so single-instruction offsets
80 __nosave_begin = .; 82 can access them all, and initialized data all before uninitialized, so
81 .data_nosave : { *(.data.nosave) } 83 we can shorten the on-disk segment size. */
82 . = ALIGN(_PAGE_SIZE); 84 .sdata : {
83 __nosave_end = .; 85 *(.sdata)
84 86 }
85 . = ALIGN(32); 87
86 .data.cacheline_aligned : { *(.data.cacheline_aligned) } 88 . = ALIGN(_PAGE_SIZE);
87 89 .data_nosave : {
88 _edata = .; /* End of data section */ 90 __nosave_begin = .;
89 91 *(.data.nosave)
90 /* will be freed after init */ 92 }
91 . = ALIGN(_PAGE_SIZE); /* Init code and data */ 93 . = ALIGN(_PAGE_SIZE);
92 __init_begin = .; 94 __nosave_end = .;
93 .init.text : { 95
94 _sinittext = .; 96 . = ALIGN(32);
95 *(.init.text) 97 .data.cacheline_aligned : {
96 _einittext = .; 98 *(.data.cacheline_aligned)
97 } 99 }
98 .init.data : { *(.init.data) } 100 _edata = .; /* End of data section */
99 . = ALIGN(16); 101
100 __setup_start = .; 102 /* will be freed after init */
101 .init.setup : { *(.init.setup) } 103 . = ALIGN(_PAGE_SIZE); /* Init code and data */
102 __setup_end = .; 104 __init_begin = .;
103 105 .init.text : {
104 __initcall_start = .; 106 _sinittext = .;
105 .initcall.init : { 107 *(.init.text)
106 INITCALLS 108 _einittext = .;
107 } 109 }
108 __initcall_end = .; 110 .init.data : {
109 111 *(.init.data)
110 __con_initcall_start = .; 112 }
111 .con_initcall.init : { *(.con_initcall.init) } 113 . = ALIGN(16);
112 __con_initcall_end = .; 114 .init.setup : {
113 SECURITY_INIT 115 __setup_start = .;
114 /* .exit.text is discarded at runtime, not link time, to deal with 116 *(.init.setup)
115 references from .rodata */ 117 __setup_end = .;
116 .exit.text : { *(.exit.text) } 118 }
117 .exit.data : { *(.exit.data) } 119
120 .initcall.init : {
121 __initcall_start = .;
122 INITCALLS
123 __initcall_end = .;
124 }
125
126 .con_initcall.init : {
127 __con_initcall_start = .;
128 *(.con_initcall.init)
129 __con_initcall_end = .;
130 }
131 SECURITY_INIT
132
133 /* .exit.text is discarded at runtime, not link time, to deal with
134 * references from .rodata
135 */
136 .exit.text : {
137 *(.exit.text)
138 }
139 .exit.data : {
140 *(.exit.data)
141 }
118#if defined(CONFIG_BLK_DEV_INITRD) 142#if defined(CONFIG_BLK_DEV_INITRD)
119 . = ALIGN(_PAGE_SIZE); 143 . = ALIGN(_PAGE_SIZE);
120 __initramfs_start = .; 144 .init.ramfs : {
121 .init.ramfs : { *(.init.ramfs) } 145 __initramfs_start = .;
122 __initramfs_end = .; 146 *(.init.ramfs)
147 __initramfs_end = .;
148 }
123#endif 149#endif
124 PERCPU(_PAGE_SIZE) 150 PERCPU(_PAGE_SIZE)
125 . = ALIGN(_PAGE_SIZE); 151 . = ALIGN(_PAGE_SIZE);
126 __init_end = .; 152 __init_end = .;
127 /* freed after init ends here */ 153 /* freed after init ends here */
128 154
129 __bss_start = .; /* BSS */ 155 __bss_start = .; /* BSS */
130 .sbss : { 156 .sbss : {
131 *(.sbss) 157 *(.sbss)
132 *(.scommon) 158 *(.scommon)
133 } 159 }
134 .bss : { 160 .bss : {
135 *(.bss) 161 *(.bss)
136 *(COMMON) 162 *(COMMON)
137 } 163 }
138 __bss_stop = .; 164 __bss_stop = .;
139 165
140 _end = . ; 166 _end = . ;
141 167
142 /* Sections to be discarded */ 168 /* Sections to be discarded */
143 /DISCARD/ : { 169 /DISCARD/ : {
144 *(.exitcall.exit) 170 *(.exitcall.exit)
145 171
146 /* ABI crap starts here */ 172 /* ABI crap starts here */
147 *(.MIPS.options) 173 *(.MIPS.options)
148 *(.options) 174 *(.options)
149 *(.pdr) 175 *(.pdr)
150 *(.reginfo) 176 *(.reginfo)
151 } 177 }
152 178
153 /* These mark the ABI of the kernel for debuggers. */ 179 /* These mark the ABI of the kernel for debuggers. */
154 .mdebug.abi32 : { KEEP(*(.mdebug.abi32)) } 180 .mdebug.abi32 : {
155 .mdebug.abi64 : { KEEP(*(.mdebug.abi64)) } 181 KEEP(*(.mdebug.abi32))
156 182 }
157 /* This is the MIPS specific mdebug section. */ 183 .mdebug.abi64 : {
158 .mdebug : { *(.mdebug) } 184 KEEP(*(.mdebug.abi64))
159 185 }
160 STABS_DEBUG 186
161 187 /* This is the MIPS specific mdebug section. */
162 DWARF_DEBUG 188 .mdebug : {
163 189 *(.mdebug)
164 /* These must appear regardless of . */ 190 }
165 .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } 191
166 .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } 192 STABS_DEBUG
167 .note : { *(.note) } 193 DWARF_DEBUG
194
195 /* These must appear regardless of . */
196 .gptab.sdata : {
197 *(.gptab.data)
198 *(.gptab.sdata)
199 }
200 .gptab.sbss : {
201 *(.gptab.bss)
202 *(.gptab.sbss)
203 }
204 .note : {
205 *(.note)
206 }
168} 207}
diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c
index 3c09b9785f4c..61b729fa0548 100644
--- a/arch/mips/kernel/vpe.c
+++ b/arch/mips/kernel/vpe.c
@@ -936,8 +936,18 @@ static int vpe_elfload(struct vpe * v)
936 936
937 } 937 }
938 } else { 938 } else {
939 for (i = 0; i < hdr->e_shnum; i++) { 939 struct elf_phdr *phdr = (struct elf_phdr *) ((char *)hdr + hdr->e_phoff);
940 940
941 for (i = 0; i < hdr->e_phnum; i++) {
942 if (phdr->p_type != PT_LOAD)
943 continue;
944
945 memcpy((void *)phdr->p_vaddr, (char *)hdr + phdr->p_offset, phdr->p_filesz);
946 memset((void *)phdr->p_vaddr + phdr->p_filesz, 0, phdr->p_memsz - phdr->p_filesz);
947 phdr++;
948 }
949
950 for (i = 0; i < hdr->e_shnum; i++) {
941 /* Internal symbols and strings. */ 951 /* Internal symbols and strings. */
942 if (sechdrs[i].sh_type == SHT_SYMTAB) { 952 if (sechdrs[i].sh_type == SHT_SYMTAB) {
943 symindex = i; 953 symindex = i;
@@ -948,39 +958,6 @@ static int vpe_elfload(struct vpe * v)
948 magic symbols */ 958 magic symbols */
949 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset; 959 sechdrs[i].sh_addr = (size_t) hdr + sechdrs[i].sh_offset;
950 } 960 }
951
952 /* filter sections we dont want in the final image */
953 if (!(sechdrs[i].sh_flags & SHF_ALLOC) ||
954 (sechdrs[i].sh_type == SHT_MIPS_REGINFO)) {
955 printk( KERN_DEBUG " ignoring section, "
956 "name %s type %x address 0x%x \n",
957 secstrings + sechdrs[i].sh_name,
958 sechdrs[i].sh_type, sechdrs[i].sh_addr);
959 continue;
960 }
961
962 if (sechdrs[i].sh_addr < (unsigned int)v->load_addr) {
963 printk( KERN_WARNING "VPE loader: "
964 "fully linked image has invalid section, "
965 "name %s type %x address 0x%x, before load "
966 "address of 0x%x\n",
967 secstrings + sechdrs[i].sh_name,
968 sechdrs[i].sh_type, sechdrs[i].sh_addr,
969 (unsigned int)v->load_addr);
970 return -ENOEXEC;
971 }
972
973 printk(KERN_DEBUG " copying section sh_name %s, sh_addr 0x%x "
974 "size 0x%x0 from x%p\n",
975 secstrings + sechdrs[i].sh_name, sechdrs[i].sh_addr,
976 sechdrs[i].sh_size, hdr + sechdrs[i].sh_offset);
977
978 if (sechdrs[i].sh_type != SHT_NOBITS)
979 memcpy((void *)sechdrs[i].sh_addr,
980 (char *)hdr + sechdrs[i].sh_offset,
981 sechdrs[i].sh_size);
982 else
983 memset((void *)sechdrs[i].sh_addr, 0, sechdrs[i].sh_size);
984 } 961 }
985 } 962 }
986 963
@@ -1044,7 +1021,7 @@ static int getcwd(char *buff, int size)
1044 old_fs = get_fs(); 1021 old_fs = get_fs();
1045 set_fs(KERNEL_DS); 1022 set_fs(KERNEL_DS);
1046 1023
1047 ret = sys_getcwd(buff,size); 1024 ret = sys_getcwd(buff, size);
1048 1025
1049 set_fs(old_fs); 1026 set_fs(old_fs);
1050 1027
diff --git a/arch/mips/lasat/Kconfig b/arch/mips/lasat/Kconfig
new file mode 100644
index 000000000000..1d2ee8a9be13
--- /dev/null
+++ b/arch/mips/lasat/Kconfig
@@ -0,0 +1,15 @@
1config PICVUE
2 tristate "PICVUE LCD display driver"
3 depends on LASAT
4
5config PICVUE_PROC
6 tristate "PICVUE LCD display driver /proc interface"
7 depends on PICVUE
8
9config DS1603
10 bool "DS1603 RTC driver"
11 depends on LASAT
12
13config LASAT_SYSCTL
14 bool "LASAT sysctl interface"
15 depends on LASAT
diff --git a/arch/mips/lasat/Makefile b/arch/mips/lasat/Makefile
new file mode 100644
index 000000000000..33791609fe99
--- /dev/null
+++ b/arch/mips/lasat/Makefile
@@ -0,0 +1,16 @@
1#
2# Makefile for the LASAT specific kernel interface routines under Linux.
3#
4
5obj-y += reset.o setup.o prom.o lasat_board.o \
6 at93c.o interrupt.o serial.o
7
8obj-$(CONFIG_LASAT_SYSCTL) += sysctl.o
9obj-$(CONFIG_DS1603) += ds1603.o
10obj-$(CONFIG_PICVUE) += picvue.o
11obj-$(CONFIG_PICVUE_PROC) += picvue_proc.o
12
13clean:
14 make -C image clean
15
16EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lasat/at93c.c b/arch/mips/lasat/at93c.c
new file mode 100644
index 000000000000..793e234719a6
--- /dev/null
+++ b/arch/mips/lasat/at93c.c
@@ -0,0 +1,149 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/lasat/lasat.h>
10#include <linux/module.h>
11#include <linux/init.h>
12
13#include "at93c.h"
14
15#define AT93C_ADDR_SHIFT 7
16#define AT93C_ADDR_MAX ((1 << AT93C_ADDR_SHIFT) - 1)
17#define AT93C_RCMD (0x6 << AT93C_ADDR_SHIFT)
18#define AT93C_WCMD (0x5 << AT93C_ADDR_SHIFT)
19#define AT93C_WENCMD 0x260
20#define AT93C_WDSCMD 0x200
21
22struct at93c_defs *at93c;
23
24static void at93c_reg_write(u32 val)
25{
26 *at93c->reg = val;
27}
28
29static u32 at93c_reg_read(void)
30{
31 u32 tmp = *at93c->reg;
32 return tmp;
33}
34
35static u32 at93c_datareg_read(void)
36{
37 u32 tmp = *at93c->rdata_reg;
38 return tmp;
39}
40
41static void at93c_cycle_clk(u32 data)
42{
43 at93c_reg_write(data | at93c->clk);
44 lasat_ndelay(250);
45 at93c_reg_write(data & ~at93c->clk);
46 lasat_ndelay(250);
47}
48
49static void at93c_write_databit(u8 bit)
50{
51 u32 data = at93c_reg_read();
52 if (bit)
53 data |= 1 << at93c->wdata_shift;
54 else
55 data &= ~(1 << at93c->wdata_shift);
56
57 at93c_reg_write(data);
58 lasat_ndelay(100);
59 at93c_cycle_clk(data);
60}
61
62static unsigned int at93c_read_databit(void)
63{
64 u32 data;
65
66 at93c_cycle_clk(at93c_reg_read());
67 data = (at93c_datareg_read() >> at93c->rdata_shift) & 1;
68 return data;
69}
70
71static u8 at93c_read_byte(void)
72{
73 int i;
74 u8 data = 0;
75
76 for (i = 0; i <= 7; i++) {
77 data <<= 1;
78 data |= at93c_read_databit();
79 }
80 return data;
81}
82
83static void at93c_write_bits(u32 data, int size)
84{
85 int i;
86 int shift = size - 1;
87 u32 mask = (1 << shift);
88
89 for (i = 0; i < size; i++) {
90 at93c_write_databit((data & mask) >> shift);
91 data <<= 1;
92 }
93}
94
95static void at93c_init_op(void)
96{
97 at93c_reg_write((at93c_reg_read() | at93c->cs) &
98 ~at93c->clk & ~(1 << at93c->rdata_shift));
99 lasat_ndelay(50);
100}
101
102static void at93c_end_op(void)
103{
104 at93c_reg_write(at93c_reg_read() & ~at93c->cs);
105 lasat_ndelay(250);
106}
107
108static void at93c_wait(void)
109{
110 at93c_init_op();
111 while (!at93c_read_databit())
112 ;
113 at93c_end_op();
114};
115
116static void at93c_disable_wp(void)
117{
118 at93c_init_op();
119 at93c_write_bits(AT93C_WENCMD, 10);
120 at93c_end_op();
121}
122
123static void at93c_enable_wp(void)
124{
125 at93c_init_op();
126 at93c_write_bits(AT93C_WDSCMD, 10);
127 at93c_end_op();
128}
129
130u8 at93c_read(u8 addr)
131{
132 u8 byte;
133 at93c_init_op();
134 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_RCMD, 10);
135 byte = at93c_read_byte();
136 at93c_end_op();
137 return byte;
138}
139
140void at93c_write(u8 addr, u8 data)
141{
142 at93c_disable_wp();
143 at93c_init_op();
144 at93c_write_bits((addr & AT93C_ADDR_MAX)|AT93C_WCMD, 10);
145 at93c_write_bits(data, 8);
146 at93c_end_op();
147 at93c_wait();
148 at93c_enable_wp();
149}
diff --git a/arch/mips/lasat/at93c.h b/arch/mips/lasat/at93c.h
new file mode 100644
index 000000000000..cfe2f99b1d44
--- /dev/null
+++ b/arch/mips/lasat/at93c.h
@@ -0,0 +1,18 @@
1/*
2 * Atmel AT93C46 serial eeprom driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7
8extern struct at93c_defs {
9 volatile u32 *reg;
10 volatile u32 *rdata_reg;
11 int rdata_shift;
12 int wdata_shift;
13 u32 cs;
14 u32 clk;
15} *at93c;
16
17u8 at93c_read(u8 addr);
18void at93c_write(u8 addr, u8 data);
diff --git a/arch/mips/lasat/ds1603.c b/arch/mips/lasat/ds1603.c
new file mode 100644
index 000000000000..52cb1436a12a
--- /dev/null
+++ b/arch/mips/lasat/ds1603.c
@@ -0,0 +1,183 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <asm/lasat/lasat.h>
9#include <linux/delay.h>
10#include <asm/lasat/ds1603.h>
11#include <asm/time.h>
12
13#include "ds1603.h"
14
15#define READ_TIME_CMD 0x81
16#define SET_TIME_CMD 0x80
17#define TRIMMER_SET_CMD 0xC0
18#define TRIMMER_VALUE_MASK 0x38
19#define TRIMMER_SHIFT 3
20
21struct ds_defs *ds1603;
22
23/* HW specific register functions */
24static void rtc_reg_write(unsigned long val)
25{
26 *ds1603->reg = val;
27}
28
29static unsigned long rtc_reg_read(void)
30{
31 unsigned long tmp = *ds1603->reg;
32 return tmp;
33}
34
35static unsigned long rtc_datareg_read(void)
36{
37 unsigned long tmp = *ds1603->data_reg;
38 return tmp;
39}
40
41static void rtc_nrst_high(void)
42{
43 rtc_reg_write(rtc_reg_read() | ds1603->rst);
44}
45
46static void rtc_nrst_low(void)
47{
48 rtc_reg_write(rtc_reg_read() & ~ds1603->rst);
49}
50
51static void rtc_cycle_clock(unsigned long data)
52{
53 data |= ds1603->clk;
54 rtc_reg_write(data);
55 lasat_ndelay(250);
56 if (ds1603->data_reversed)
57 data &= ~ds1603->data;
58 else
59 data |= ds1603->data;
60 data &= ~ds1603->clk;
61 rtc_reg_write(data);
62 lasat_ndelay(250 + ds1603->huge_delay);
63}
64
65static void rtc_write_databit(unsigned int bit)
66{
67 unsigned long data = rtc_reg_read();
68 if (ds1603->data_reversed)
69 bit = !bit;
70 if (bit)
71 data |= ds1603->data;
72 else
73 data &= ~ds1603->data;
74
75 rtc_reg_write(data);
76 lasat_ndelay(50 + ds1603->huge_delay);
77 rtc_cycle_clock(data);
78}
79
80static unsigned int rtc_read_databit(void)
81{
82 unsigned int data;
83
84 data = (rtc_datareg_read() & (1 << ds1603->data_read_shift))
85 >> ds1603->data_read_shift;
86 rtc_cycle_clock(rtc_reg_read());
87 return data;
88}
89
90static void rtc_write_byte(unsigned int byte)
91{
92 int i;
93
94 for (i = 0; i <= 7; i++) {
95 rtc_write_databit(byte & 1L);
96 byte >>= 1;
97 }
98}
99
100static void rtc_write_word(unsigned long word)
101{
102 int i;
103
104 for (i = 0; i <= 31; i++) {
105 rtc_write_databit(word & 1L);
106 word >>= 1;
107 }
108}
109
110static unsigned long rtc_read_word(void)
111{
112 int i;
113 unsigned long word = 0;
114 unsigned long shift = 0;
115
116 for (i = 0; i <= 31; i++) {
117 word |= rtc_read_databit() << shift;
118 shift++;
119 }
120 return word;
121}
122
123static void rtc_init_op(void)
124{
125 rtc_nrst_high();
126
127 rtc_reg_write(rtc_reg_read() & ~ds1603->clk);
128
129 lasat_ndelay(50);
130}
131
132static void rtc_end_op(void)
133{
134 rtc_nrst_low();
135 lasat_ndelay(1000);
136}
137
138unsigned long read_persistent_clock(void)
139{
140 unsigned long word;
141 unsigned long flags;
142
143 spin_lock_irqsave(&rtc_lock, flags);
144 rtc_init_op();
145 rtc_write_byte(READ_TIME_CMD);
146 word = rtc_read_word();
147 rtc_end_op();
148 spin_unlock_irqrestore(&rtc_lock, flags);
149
150 return word;
151}
152
153int rtc_mips_set_mmss(unsigned long time)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&rtc_lock, flags);
158 rtc_init_op();
159 rtc_write_byte(SET_TIME_CMD);
160 rtc_write_word(time);
161 rtc_end_op();
162 spin_unlock_irqrestore(&rtc_lock, flags);
163
164 return 0;
165}
166
167void ds1603_set_trimmer(unsigned int trimval)
168{
169 rtc_init_op();
170 rtc_write_byte(((trimval << TRIMMER_SHIFT) & TRIMMER_VALUE_MASK)
171 | (TRIMMER_SET_CMD));
172 rtc_end_op();
173}
174
175void ds1603_disable(void)
176{
177 ds1603_set_trimmer(TRIMMER_DISABLE_RTC);
178}
179
180void ds1603_enable(void)
181{
182 ds1603_set_trimmer(TRIMMER_DEFAULT);
183}
diff --git a/arch/mips/lasat/ds1603.h b/arch/mips/lasat/ds1603.h
new file mode 100644
index 000000000000..2da3704044fd
--- /dev/null
+++ b/arch/mips/lasat/ds1603.h
@@ -0,0 +1,31 @@
1/*
2 * Dallas Semiconductors 1603 RTC driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#ifndef __DS1603_H
8#define __DS1603_H
9
10struct ds_defs {
11 volatile u32 *reg;
12 volatile u32 *data_reg;
13 u32 rst;
14 u32 clk;
15 u32 data;
16 u32 data_read_shift;
17 char data_reversed;
18 u32 huge_delay;
19};
20
21extern struct ds_defs *ds1603;
22
23void ds1603_set_trimmer(unsigned int);
24void ds1603_enable(void);
25void ds1603_disable(void);
26void ds1603_init(struct ds_defs *);
27
28#define TRIMMER_DEFAULT 3
29#define TRIMMER_DISABLE_RTC 0
30
31#endif
diff --git a/arch/mips/lasat/image/Makefile b/arch/mips/lasat/image/Makefile
new file mode 100644
index 000000000000..5332449ec040
--- /dev/null
+++ b/arch/mips/lasat/image/Makefile
@@ -0,0 +1,54 @@
1#
2# MAKEFILE FOR THE MIPS LINUX BOOTLOADER AND ROM DEBUGGER
3#
4# i-data Networks
5#
6# Author: Thomas Horsten <thh@i-data.com>
7#
8
9ifndef Version
10 Version = "$(USER)-test"
11endif
12
13MKLASATIMG = mklasatimg
14MKLASATIMG_ARCH = mq2,mqpro,sp100,sp200
15KERNEL_IMAGE = $(TOPDIR)/vmlinux
16KERNEL_START = $(shell $(NM) $(KERNEL_IMAGE) | grep " _text" | cut -f1 -d\ )
17KERNEL_ENTRY = $(shell $(NM) $(KERNEL_IMAGE) | grep kernel_entry | cut -f1 -d\ )
18
19LDSCRIPT= -L$(obj) -Tromscript.normal
20
21HEAD_DEFINES := -D_kernel_start=0x$(KERNEL_START) \
22 -D_kernel_entry=0x$(KERNEL_ENTRY) \
23 -D VERSION="\"$(Version)\"" \
24 -D TIMESTAMP=$(shell date +%s)
25
26$(obj)/head.o: $(obj)/head.S $(KERNEL_IMAGE)
27 $(CC) -fno-pic $(HEAD_DEFINES) -I$(TOPDIR)/include -c -o $@ $<
28
29OBJECTS = head.o kImage.o
30
31rom.sw: $(obj)/rom.sw
32rom.bin: $(obj)/rom.bin
33
34$(obj)/rom.sw: $(obj)/rom.bin
35 $(MKLASATIMG) -o $@ -k $^ -m $(MKLASATIMG_ARCH)
36
37$(obj)/rom.bin: $(obj)/rom
38 $(OBJCOPY) -O binary -S $^ $@
39
40# Rule to make the bootloader
41$(obj)/rom: $(addprefix $(obj)/,$(OBJECTS))
42 $(LD) $(LDFLAGS) $(LDSCRIPT) -o $@ $^
43
44$(obj)/%.o: $(obj)/%.gz
45 $(LD) -r -o $@ -b binary $<
46
47$(obj)/%.gz: $(obj)/%.bin
48 gzip -cf -9 $< > $@
49
50$(obj)/kImage.bin: $(KERNEL_IMAGE)
51 $(OBJCOPY) -O binary -S $^ $@
52
53clean:
54 rm -f rom rom.bin rom.sw kImage.bin kImage.o
diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S
new file mode 100644
index 000000000000..efb95f2609c2
--- /dev/null
+++ b/arch/mips/lasat/image/head.S
@@ -0,0 +1,31 @@
1#include <asm/lasat/head.h>
2
3 .text
4 .section .text.start, "ax"
5 .set noreorder
6 .set mips3
7
8 /* Magic words identifying a software image */
9 .word LASAT_K_MAGIC0_VAL
10 .word LASAT_K_MAGIC1_VAL
11
12 /* Image header version */
13 .word 0x00000002
14
15 /* image start and size */
16 .word _image_start
17 .word _image_size
18
19 /* start of kernel and entrypoint in uncompressed image */
20 .word _kernel_start
21 .word _kernel_entry
22
23 /* Here we have room for future flags */
24
25 .org 0x40
26reldate:
27 .word TIMESTAMP
28
29 .org 0x50
30release:
31 .string VERSION
diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal
new file mode 100644
index 000000000000..988f8ad189cb
--- /dev/null
+++ b/arch/mips/lasat/image/romscript.normal
@@ -0,0 +1,23 @@
1OUTPUT_ARCH(mips)
2
3SECTIONS
4{
5 .text :
6 {
7 *(.text.start)
8 }
9
10 /* Data in ROM */
11
12 .data ALIGN(0x10) :
13 {
14 *(.data)
15 }
16 _image_start = ADDR(.data);
17 _image_size = SIZEOF(.data);
18
19 .other :
20 {
21 *(.*)
22 }
23}
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
new file mode 100644
index 000000000000..5f35289bfff5
--- /dev/null
+++ b/arch/mips/lasat/interrupt.c
@@ -0,0 +1,130 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines for generic manipulation of the interrupts found on the
19 * Lasat boards.
20 */
21#include <linux/init.h>
22#include <linux/irq.h>
23#include <linux/sched.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h>
26#include <linux/kernel_stat.h>
27
28#include <asm/bootinfo.h>
29#include <asm/lasat/lasatint.h>
30#include <asm/time.h>
31#include <asm/gdb-stub.h>
32
33static volatile int *lasat_int_status;
34static volatile int *lasat_int_mask;
35static volatile int lasat_int_mask_shift;
36
37void disable_lasat_irq(unsigned int irq_nr)
38{
39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
40}
41
42void enable_lasat_irq(unsigned int irq_nr)
43{
44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
45}
46
47static struct irq_chip lasat_irq_type = {
48 .name = "Lasat",
49 .ack = disable_lasat_irq,
50 .mask = disable_lasat_irq,
51 .mask_ack = disable_lasat_irq,
52 .unmask = enable_lasat_irq,
53};
54
55static inline int ls1bit32(unsigned int x)
56{
57 int b = 31, s;
58
59 s = 16; if (x << 16 == 0) s = 0; b -= s; x <<= s;
60 s = 8; if (x << 8 == 0) s = 0; b -= s; x <<= s;
61 s = 4; if (x << 4 == 0) s = 0; b -= s; x <<= s;
62 s = 2; if (x << 2 == 0) s = 0; b -= s; x <<= s;
63 s = 1; if (x << 1 == 0) s = 0; b -= s;
64
65 return b;
66}
67
68static unsigned long (*get_int_status)(void);
69
70static unsigned long get_int_status_100(void)
71{
72 return *lasat_int_status & *lasat_int_mask;
73}
74
75static unsigned long get_int_status_200(void)
76{
77 unsigned long int_status;
78
79 int_status = *lasat_int_status;
80 int_status &= (int_status >> LASATINT_MASK_SHIFT_200) & 0xffff;
81 return int_status;
82}
83
84asmlinkage void plat_irq_dispatch(void)
85{
86 unsigned long int_status;
87 unsigned int cause = read_c0_cause();
88 int irq;
89
90 if (cause & CAUSEF_IP7) { /* R4000 count / compare IRQ */
91 ll_timer_interrupt(7);
92 return;
93 }
94
95 int_status = get_int_status();
96
97 /* if int_status == 0, then the interrupt has already been cleared */
98 if (int_status) {
99 irq = ls1bit32(int_status);
100
101 do_IRQ(irq);
102 }
103}
104
105void __init arch_init_irq(void)
106{
107 int i;
108
109 switch (mips_machtype) {
110 case MACH_LASAT_100:
111 lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
112 lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
113 lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
114 get_int_status = get_int_status_100;
115 *lasat_int_mask = 0;
116 break;
117 case MACH_LASAT_200:
118 lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
119 lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
120 lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
121 get_int_status = get_int_status_200;
122 *lasat_int_mask &= 0xffff;
123 break;
124 default:
125 panic("arch_init_irq: mips_machtype incorrect");
126 }
127
128 for (i = 0; i <= LASATINT_END; i++)
129 set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
130}
diff --git a/arch/mips/lasat/lasat_board.c b/arch/mips/lasat/lasat_board.c
new file mode 100644
index 000000000000..ec2f658c3709
--- /dev/null
+++ b/arch/mips/lasat/lasat_board.c
@@ -0,0 +1,280 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <linux/crc32.h>
22#include <asm/lasat/lasat.h>
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/ctype.h>
26#include <asm/bootinfo.h>
27#include <asm/addrspace.h>
28#include "at93c.h"
29/* New model description table */
30#include "lasat_models.h"
31
32#define EEPROM_CRC(data, len) (~crc32(~0, data, len))
33
34struct lasat_info lasat_board_info;
35
36void update_bcastaddr(void);
37
38int EEPROMRead(unsigned int pos, unsigned char *data, int len)
39{
40 int i;
41
42 for (i = 0; i < len; i++)
43 *data++ = at93c_read(pos++);
44
45 return 0;
46}
47
48int EEPROMWrite(unsigned int pos, unsigned char *data, int len)
49{
50 int i;
51
52 for (i = 0; i < len; i++)
53 at93c_write(pos++, *data++);
54
55 return 0;
56}
57
58static void init_flash_sizes(void)
59{
60 unsigned long *lb = lasat_board_info.li_flashpart_base;
61 unsigned long *ls = lasat_board_info.li_flashpart_size;
62 int i;
63
64 ls[LASAT_MTD_BOOTLOADER] = 0x40000;
65 ls[LASAT_MTD_SERVICE] = 0xC0000;
66 ls[LASAT_MTD_NORMAL] = 0x100000;
67
68 if (mips_machtype == MACH_LASAT_100) {
69 lasat_board_info.li_flash_base = 0x1e000000;
70
71 lb[LASAT_MTD_BOOTLOADER] = 0x1e400000;
72
73 if (lasat_board_info.li_flash_size > 0x200000) {
74 ls[LASAT_MTD_CONFIG] = 0x100000;
75 ls[LASAT_MTD_FS] = 0x500000;
76 }
77 } else {
78 lasat_board_info.li_flash_base = 0x10000000;
79
80 if (lasat_board_info.li_flash_size < 0x1000000) {
81 lb[LASAT_MTD_BOOTLOADER] = 0x10000000;
82 ls[LASAT_MTD_CONFIG] = 0x100000;
83 if (lasat_board_info.li_flash_size >= 0x400000)
84 ls[LASAT_MTD_FS] =
85 lasat_board_info.li_flash_size - 0x300000;
86 }
87 }
88
89 for (i = 1; i < LASAT_MTD_LAST; i++)
90 lb[i] = lb[i-1] + ls[i-1];
91}
92
93int lasat_init_board_info(void)
94{
95 int c;
96 unsigned long crc;
97 unsigned long cfg0, cfg1;
98 const struct product_info *ppi;
99 int i_n_base_models = N_BASE_MODELS;
100 const char * const * i_txt_base_models = txt_base_models;
101 int i_n_prids = N_PRIDS;
102
103 memset(&lasat_board_info, 0, sizeof(lasat_board_info));
104
105 /* First read the EEPROM info */
106 EEPROMRead(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
107 sizeof(struct lasat_eeprom_struct));
108
109 /* Check the CRC */
110 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
111 sizeof(struct lasat_eeprom_struct) - 4);
112
113 if (crc != lasat_board_info.li_eeprom_info.crc32) {
114 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM CRC does "
115 "not match calculated, attempting to soldier on...\n");
116 }
117
118 if (lasat_board_info.li_eeprom_info.version != LASAT_EEPROM_VERSION) {
119 printk(KERN_WARNING "WARNING...\nWARNING...\nEEPROM version "
120 "%d, wanted version %d, attempting to soldier on...\n",
121 (unsigned int)lasat_board_info.li_eeprom_info.version,
122 LASAT_EEPROM_VERSION);
123 }
124
125 cfg0 = lasat_board_info.li_eeprom_info.cfg[0];
126 cfg1 = lasat_board_info.li_eeprom_info.cfg[1];
127
128 if (LASAT_W0_DSCTYPE(cfg0) != 1) {
129 printk(KERN_WARNING "WARNING...\nWARNING...\n"
130 "Invalid configuration read from EEPROM, attempting to "
131 "soldier on...");
132 }
133 /* We have a valid configuration */
134
135 switch (LASAT_W0_SDRAMBANKSZ(cfg0)) {
136 case 0:
137 lasat_board_info.li_memsize = 0x0800000;
138 break;
139 case 1:
140 lasat_board_info.li_memsize = 0x1000000;
141 break;
142 case 2:
143 lasat_board_info.li_memsize = 0x2000000;
144 break;
145 case 3:
146 lasat_board_info.li_memsize = 0x4000000;
147 break;
148 case 4:
149 lasat_board_info.li_memsize = 0x8000000;
150 break;
151 default:
152 lasat_board_info.li_memsize = 0;
153 }
154
155 switch (LASAT_W0_SDRAMBANKS(cfg0)) {
156 case 0:
157 break;
158 case 1:
159 lasat_board_info.li_memsize *= 2;
160 break;
161 default:
162 break;
163 }
164
165 switch (LASAT_W0_BUSSPEED(cfg0)) {
166 case 0x0:
167 lasat_board_info.li_bus_hz = 60000000;
168 break;
169 case 0x1:
170 lasat_board_info.li_bus_hz = 66000000;
171 break;
172 case 0x2:
173 lasat_board_info.li_bus_hz = 66666667;
174 break;
175 case 0x3:
176 lasat_board_info.li_bus_hz = 80000000;
177 break;
178 case 0x4:
179 lasat_board_info.li_bus_hz = 83333333;
180 break;
181 case 0x5:
182 lasat_board_info.li_bus_hz = 100000000;
183 break;
184 }
185
186 switch (LASAT_W0_CPUCLK(cfg0)) {
187 case 0x0:
188 lasat_board_info.li_cpu_hz =
189 lasat_board_info.li_bus_hz;
190 break;
191 case 0x1:
192 lasat_board_info.li_cpu_hz =
193 lasat_board_info.li_bus_hz +
194 (lasat_board_info.li_bus_hz >> 1);
195 break;
196 case 0x2:
197 lasat_board_info.li_cpu_hz =
198 lasat_board_info.li_bus_hz +
199 lasat_board_info.li_bus_hz;
200 break;
201 case 0x3:
202 lasat_board_info.li_cpu_hz =
203 lasat_board_info.li_bus_hz +
204 lasat_board_info.li_bus_hz +
205 (lasat_board_info.li_bus_hz >> 1);
206 break;
207 case 0x4:
208 lasat_board_info.li_cpu_hz =
209 lasat_board_info.li_bus_hz +
210 lasat_board_info.li_bus_hz +
211 lasat_board_info.li_bus_hz;
212 break;
213 }
214
215 /* Flash size */
216 switch (LASAT_W1_FLASHSIZE(cfg1)) {
217 case 0:
218 lasat_board_info.li_flash_size = 0x200000;
219 break;
220 case 1:
221 lasat_board_info.li_flash_size = 0x400000;
222 break;
223 case 2:
224 lasat_board_info.li_flash_size = 0x800000;
225 break;
226 case 3:
227 lasat_board_info.li_flash_size = 0x1000000;
228 break;
229 case 4:
230 lasat_board_info.li_flash_size = 0x2000000;
231 break;
232 }
233
234 init_flash_sizes();
235
236 lasat_board_info.li_bmid = LASAT_W0_BMID(cfg0);
237 lasat_board_info.li_prid = lasat_board_info.li_eeprom_info.prid;
238 if (lasat_board_info.li_prid == 0xffff || lasat_board_info.li_prid == 0)
239 lasat_board_info.li_prid = lasat_board_info.li_bmid;
240
241 /* Base model stuff */
242 if (lasat_board_info.li_bmid > i_n_base_models)
243 lasat_board_info.li_bmid = i_n_base_models;
244 strcpy(lasat_board_info.li_bmstr,
245 i_txt_base_models[lasat_board_info.li_bmid]);
246
247 /* Product ID dependent values */
248 c = lasat_board_info.li_prid;
249 if (c >= i_n_prids) {
250 strcpy(lasat_board_info.li_namestr, "Unknown Model");
251 strcpy(lasat_board_info.li_typestr, "Unknown Type");
252 } else {
253 ppi = &vendor_info_table[0].vi_product_info[c];
254 strcpy(lasat_board_info.li_namestr, ppi->pi_name);
255 if (ppi->pi_type)
256 strcpy(lasat_board_info.li_typestr, ppi->pi_type);
257 else
258 sprintf(lasat_board_info.li_typestr, "%d", 10 * c);
259 }
260
261#if defined(CONFIG_INET) && defined(CONFIG_SYSCTL)
262 update_bcastaddr();
263#endif
264
265 return 0;
266}
267
268void lasat_write_eeprom_info(void)
269{
270 unsigned long crc;
271
272 /* Generate the CRC */
273 crc = EEPROM_CRC((unsigned char *)(&lasat_board_info.li_eeprom_info),
274 sizeof(struct lasat_eeprom_struct) - 4);
275 lasat_board_info.li_eeprom_info.crc32 = crc;
276
277 /* Write the EEPROM info */
278 EEPROMWrite(0, (unsigned char *)&lasat_board_info.li_eeprom_info,
279 sizeof(struct lasat_eeprom_struct));
280}
diff --git a/arch/mips/lasat/lasat_models.h b/arch/mips/lasat/lasat_models.h
new file mode 100644
index 000000000000..e1cbd26ae1b3
--- /dev/null
+++ b/arch/mips/lasat/lasat_models.h
@@ -0,0 +1,67 @@
1/*
2 * Model description tables
3 */
4#include <linux/kernel.h>
5
6struct product_info {
7 const char *pi_name;
8 const char *pi_type;
9};
10
11struct vendor_info {
12 const char *vi_name;
13 const struct product_info *vi_product_info;
14};
15
16/*
17 * Base models
18 */
19static const char * const txt_base_models[] = {
20 "MQ 2", "MQ Pro", "SP 25", "SP 50", "SP 100", "SP 5000", "SP 7000",
21 "SP 1000", "Unknown"
22};
23#define N_BASE_MODELS (ARRAY_SIZE(txt_base_models) - 1)
24
25/*
26 * Eicon Networks
27 */
28static const char txt_en_mq[] = "Masquerade";
29static const char txt_en_sp[] = "Safepipe";
30
31static const struct product_info product_info_eicon[] = {
32 { txt_en_mq, "II" }, /* 0 */
33 { txt_en_mq, "Pro" }, /* 1 */
34 { txt_en_sp, "25" }, /* 2 */
35 { txt_en_sp, "50" }, /* 3 */
36 { txt_en_sp, "100" }, /* 4 */
37 { txt_en_sp, "5000" }, /* 5 */
38 { txt_en_sp, "7000" }, /* 6 */
39 { txt_en_sp, "30" }, /* 7 */
40 { txt_en_sp, "5100" }, /* 8 */
41 { txt_en_sp, "7100" }, /* 9 */
42 { txt_en_sp, "1110" }, /* 10 */
43 { txt_en_sp, "3020" }, /* 11 */
44 { txt_en_sp, "3030" }, /* 12 */
45 { txt_en_sp, "5020" }, /* 13 */
46 { txt_en_sp, "5030" }, /* 14 */
47 { txt_en_sp, "1120" }, /* 15 */
48 { txt_en_sp, "1130" }, /* 16 */
49 { txt_en_sp, "6010" }, /* 17 */
50 { txt_en_sp, "6110" }, /* 18 */
51 { txt_en_sp, "6210" }, /* 19 */
52 { txt_en_sp, "1020" }, /* 20 */
53 { txt_en_sp, "1040" }, /* 21 */
54 { txt_en_sp, "1050" }, /* 22 */
55 { txt_en_sp, "1060" }, /* 23 */
56};
57
58#define N_PRIDS ARRAY_SIZE(product_info_eicon)
59
60/*
61 * The vendor table
62 */
63static struct vendor_info const vendor_info_table[] = {
64 { "Eicon Networks", product_info_eicon },
65};
66
67#define N_VENDORS ARRAY_SIZE(vendor_info_table)
diff --git a/arch/mips/lasat/picvue.c b/arch/mips/lasat/picvue.c
new file mode 100644
index 000000000000..6471d0663fd8
--- /dev/null
+++ b/arch/mips/lasat/picvue.c
@@ -0,0 +1,244 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian@murphy.dk>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/delay.h>
9#include <asm/bootinfo.h>
10#include <asm/lasat/lasat.h>
11#include <linux/module.h>
12#include <linux/init.h>
13#include <linux/errno.h>
14#include <linux/string.h>
15
16#include "picvue.h"
17
18#define PVC_BUSY 0x80
19#define PVC_NLINES 2
20#define PVC_DISPMEM 80
21#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
22
23struct pvc_defs *picvue;
24
25DECLARE_MUTEX(pvc_sem);
26
27static void pvc_reg_write(u32 val)
28{
29 *picvue->reg = val;
30}
31
32static u32 pvc_reg_read(void)
33{
34 u32 tmp = *picvue->reg;
35 return tmp;
36}
37
38static void pvc_write_byte(u32 data, u8 byte)
39{
40 data |= picvue->e;
41 pvc_reg_write(data);
42 data &= ~picvue->data_mask;
43 data |= byte << picvue->data_shift;
44 pvc_reg_write(data);
45 ndelay(220);
46 pvc_reg_write(data & ~picvue->e);
47 ndelay(220);
48}
49
50static u8 pvc_read_byte(u32 data)
51{
52 u8 byte;
53
54 data |= picvue->e;
55 pvc_reg_write(data);
56 ndelay(220);
57 byte = (pvc_reg_read() & picvue->data_mask) >> picvue->data_shift;
58 data &= ~picvue->e;
59 pvc_reg_write(data);
60 ndelay(220);
61 return byte;
62}
63
64static u8 pvc_read_data(void)
65{
66 u32 data = pvc_reg_read();
67 u8 byte;
68 data |= picvue->rw;
69 data &= ~picvue->rs;
70 pvc_reg_write(data);
71 ndelay(40);
72 byte = pvc_read_byte(data);
73 data |= picvue->rs;
74 pvc_reg_write(data);
75 return byte;
76}
77
78#define TIMEOUT 1000
79static int pvc_wait(void)
80{
81 int i = TIMEOUT;
82 int err = 0;
83
84 while ((pvc_read_data() & PVC_BUSY) && i)
85 i--;
86 if (i == 0)
87 err = -ETIME;
88
89 return err;
90}
91
92#define MODE_INST 0
93#define MODE_DATA 1
94static void pvc_write(u8 byte, int mode)
95{
96 u32 data = pvc_reg_read();
97 data &= ~picvue->rw;
98 if (mode == MODE_DATA)
99 data |= picvue->rs;
100 else
101 data &= ~picvue->rs;
102 pvc_reg_write(data);
103 ndelay(40);
104 pvc_write_byte(data, byte);
105 if (mode == MODE_DATA)
106 data &= ~picvue->rs;
107 else
108 data |= picvue->rs;
109 pvc_reg_write(data);
110 pvc_wait();
111}
112
113void pvc_write_string(const unsigned char *str, u8 addr, int line)
114{
115 int i = 0;
116
117 if (line > 0 && (PVC_NLINES > 1))
118 addr += 0x40 * line;
119 pvc_write(0x80 | addr, MODE_INST);
120
121 while (*str != 0 && i < PVC_LINELEN) {
122 pvc_write(*str++, MODE_DATA);
123 i++;
124 }
125}
126
127void pvc_write_string_centered(const unsigned char *str, int line)
128{
129 int len = strlen(str);
130 u8 addr;
131
132 if (len > PVC_VISIBLE_CHARS)
133 addr = 0;
134 else
135 addr = (PVC_VISIBLE_CHARS - strlen(str))/2;
136
137 pvc_write_string(str, addr, line);
138}
139
140void pvc_dump_string(const unsigned char *str)
141{
142 int len = strlen(str);
143
144 pvc_write_string(str, 0, 0);
145 if (len > PVC_VISIBLE_CHARS)
146 pvc_write_string(&str[PVC_VISIBLE_CHARS], 0, 1);
147}
148
149#define BM_SIZE 8
150#define MAX_PROGRAMMABLE_CHARS 8
151int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE])
152{
153 int i;
154 int addr;
155
156 if (charnum > MAX_PROGRAMMABLE_CHARS)
157 return -ENOENT;
158
159 addr = charnum * 8;
160 pvc_write(0x40 | addr, MODE_INST);
161
162 for (i = 0; i < BM_SIZE; i++)
163 pvc_write(bitmap[i], MODE_DATA);
164 return 0;
165}
166
167#define FUNC_SET_CMD 0x20
168#define EIGHT_BYTE (1 << 4)
169#define FOUR_BYTE 0
170#define TWO_LINES (1 << 3)
171#define ONE_LINE 0
172#define LARGE_FONT (1 << 2)
173#define SMALL_FONT 0
174
175static void pvc_funcset(u8 cmd)
176{
177 pvc_write(FUNC_SET_CMD | (cmd & (EIGHT_BYTE|TWO_LINES|LARGE_FONT)),
178 MODE_INST);
179}
180
181#define ENTRYMODE_CMD 0x4
182#define AUTO_INC (1 << 1)
183#define AUTO_DEC 0
184#define CURSOR_FOLLOWS_DISP (1 << 0)
185
186static void pvc_entrymode(u8 cmd)
187{
188 pvc_write(ENTRYMODE_CMD | (cmd & (AUTO_INC|CURSOR_FOLLOWS_DISP)),
189 MODE_INST);
190}
191
192#define DISP_CNT_CMD 0x08
193#define DISP_OFF 0
194#define DISP_ON (1 << 2)
195#define CUR_ON (1 << 1)
196#define CUR_BLINK (1 << 0)
197void pvc_dispcnt(u8 cmd)
198{
199 pvc_write(DISP_CNT_CMD | (cmd & (DISP_ON|CUR_ON|CUR_BLINK)), MODE_INST);
200}
201
202#define MOVE_CMD 0x10
203#define DISPLAY (1 << 3)
204#define CURSOR 0
205#define RIGHT (1 << 2)
206#define LEFT 0
207void pvc_move(u8 cmd)
208{
209 pvc_write(MOVE_CMD | (cmd & (DISPLAY|RIGHT)), MODE_INST);
210}
211
212#define CLEAR_CMD 0x1
213void pvc_clear(void)
214{
215 pvc_write(CLEAR_CMD, MODE_INST);
216}
217
218#define HOME_CMD 0x2
219void pvc_home(void)
220{
221 pvc_write(HOME_CMD, MODE_INST);
222}
223
224int pvc_init(void)
225{
226 u8 cmd = EIGHT_BYTE;
227
228 if (PVC_NLINES == 2)
229 cmd |= (SMALL_FONT|TWO_LINES);
230 else
231 cmd |= (LARGE_FONT|ONE_LINE);
232 pvc_funcset(cmd);
233 pvc_dispcnt(DISP_ON);
234 pvc_entrymode(AUTO_INC);
235
236 pvc_clear();
237 pvc_write_string_centered("Display", 0);
238 pvc_write_string_centered("Initialized", 1);
239
240 return 0;
241}
242
243module_init(pvc_init);
244MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/picvue.h b/arch/mips/lasat/picvue.h
new file mode 100644
index 000000000000..2a96bf971897
--- /dev/null
+++ b/arch/mips/lasat/picvue.h
@@ -0,0 +1,48 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <asm/semaphore.h>
8
9struct pvc_defs {
10 volatile u32 *reg;
11 u32 data_shift;
12 u32 data_mask;
13 u32 e;
14 u32 rw;
15 u32 rs;
16};
17
18extern struct pvc_defs *picvue;
19
20#define PVC_NLINES 2
21#define PVC_DISPMEM 80
22#define PVC_LINELEN PVC_DISPMEM / PVC_NLINES
23#define PVC_VISIBLE_CHARS 16
24
25void pvc_write_string(const unsigned char *str, u8 addr, int line);
26void pvc_write_string_centered(const unsigned char *str, int line);
27void pvc_dump_string(const unsigned char *str);
28
29#define BM_SIZE 8
30#define MAX_PROGRAMMABLE_CHARS 8
31int pvc_program_cg(int charnum, u8 bitmap[BM_SIZE]);
32
33void pvc_dispcnt(u8 cmd);
34#define DISP_OFF 0
35#define DISP_ON (1 << 2)
36#define CUR_ON (1 << 1)
37#define CUR_BLINK (1 << 0)
38
39void pvc_move(u8 cmd);
40#define DISPLAY (1 << 3)
41#define CURSOR 0
42#define RIGHT (1 << 2)
43#define LEFT 0
44
45void pvc_clear(void);
46void pvc_home(void);
47
48extern struct semaphore pvc_sem;
diff --git a/arch/mips/lasat/picvue_proc.c b/arch/mips/lasat/picvue_proc.c
new file mode 100644
index 000000000000..9947c1525822
--- /dev/null
+++ b/arch/mips/lasat/picvue_proc.c
@@ -0,0 +1,191 @@
1/*
2 * Picvue PVC160206 display driver
3 *
4 * Brian Murphy <brian.murphy@eicon.com>
5 *
6 */
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/errno.h>
11
12#include <linux/proc_fs.h>
13#include <linux/interrupt.h>
14
15#include <linux/timer.h>
16
17#include "picvue.h"
18
19static char pvc_lines[PVC_NLINES][PVC_LINELEN+1];
20static int pvc_linedata[PVC_NLINES];
21static struct proc_dir_entry *pvc_display_dir;
22static char *pvc_linename[PVC_NLINES] = {"line1", "line2"};
23#define DISPLAY_DIR_NAME "display"
24static int scroll_dir, scroll_interval;
25
26static struct timer_list timer;
27
28static void pvc_display(unsigned long data)
29{
30 int i;
31
32 pvc_clear();
33 for (i = 0; i < PVC_NLINES; i++)
34 pvc_write_string(pvc_lines[i], 0, i);
35}
36
37static DECLARE_TASKLET(pvc_display_tasklet, &pvc_display, 0);
38
39static int pvc_proc_read_line(char *page, char **start,
40 off_t off, int count,
41 int *eof, void *data)
42{
43 char *origpage = page;
44 int lineno = *(int *)data;
45
46 if (lineno < 0 || lineno > PVC_NLINES) {
47 printk(KERN_WARNING "proc_read_line: invalid lineno %d\n", lineno);
48 return 0;
49 }
50
51 down(&pvc_sem);
52 page += sprintf(page, "%s\n", pvc_lines[lineno]);
53 up(&pvc_sem);
54
55 return page - origpage;
56}
57
58static int pvc_proc_write_line(struct file *file, const char *buffer,
59 unsigned long count, void *data)
60{
61 int origcount = count;
62 int lineno = *(int *)data;
63
64 if (lineno < 0 || lineno > PVC_NLINES) {
65 printk(KERN_WARNING "proc_write_line: invalid lineno %d\n",
66 lineno);
67 return origcount;
68 }
69
70 if (count > PVC_LINELEN)
71 count = PVC_LINELEN;
72
73 if (buffer[count-1] == '\n')
74 count--;
75
76 down(&pvc_sem);
77 strncpy(pvc_lines[lineno], buffer, count);
78 pvc_lines[lineno][count] = '\0';
79 up(&pvc_sem);
80
81 tasklet_schedule(&pvc_display_tasklet);
82
83 return origcount;
84}
85
86static int pvc_proc_write_scroll(struct file *file, const char *buffer,
87 unsigned long count, void *data)
88{
89 int origcount = count;
90 int cmd = simple_strtol(buffer, NULL, 10);
91
92 down(&pvc_sem);
93 if (scroll_interval != 0)
94 del_timer(&timer);
95
96 if (cmd == 0) {
97 scroll_dir = 0;
98 scroll_interval = 0;
99 } else {
100 if (cmd < 0) {
101 scroll_dir = -1;
102 scroll_interval = -cmd;
103 } else {
104 scroll_dir = 1;
105 scroll_interval = cmd;
106 }
107 add_timer(&timer);
108 }
109 up(&pvc_sem);
110
111 return origcount;
112}
113
114static int pvc_proc_read_scroll(char *page, char **start,
115 off_t off, int count,
116 int *eof, void *data)
117{
118 char *origpage = page;
119
120 down(&pvc_sem);
121 page += sprintf(page, "%d\n", scroll_dir * scroll_interval);
122 up(&pvc_sem);
123
124 return page - origpage;
125}
126
127
128void pvc_proc_timerfunc(unsigned long data)
129{
130 if (scroll_dir < 0)
131 pvc_move(DISPLAY|RIGHT);
132 else if (scroll_dir > 0)
133 pvc_move(DISPLAY|LEFT);
134
135 timer.expires = jiffies + scroll_interval;
136 add_timer(&timer);
137}
138
139static void pvc_proc_cleanup(void)
140{
141 int i;
142 for (i = 0; i < PVC_NLINES; i++)
143 remove_proc_entry(pvc_linename[i], pvc_display_dir);
144 remove_proc_entry("scroll", pvc_display_dir);
145 remove_proc_entry(DISPLAY_DIR_NAME, NULL);
146
147 del_timer(&timer);
148}
149
150static int __init pvc_proc_init(void)
151{
152 struct proc_dir_entry *proc_entry;
153 int i;
154
155 pvc_display_dir = proc_mkdir(DISPLAY_DIR_NAME, NULL);
156 if (pvc_display_dir == NULL)
157 goto error;
158
159 for (i = 0; i < PVC_NLINES; i++) {
160 strcpy(pvc_lines[i], "");
161 pvc_linedata[i] = i;
162 }
163 for (i = 0; i < PVC_NLINES; i++) {
164 proc_entry = create_proc_entry(pvc_linename[i], 0644,
165 pvc_display_dir);
166 if (proc_entry == NULL)
167 goto error;
168
169 proc_entry->read_proc = pvc_proc_read_line;
170 proc_entry->write_proc = pvc_proc_write_line;
171 proc_entry->data = &pvc_linedata[i];
172 }
173 proc_entry = create_proc_entry("scroll", 0644, pvc_display_dir);
174 if (proc_entry == NULL)
175 goto error;
176
177 proc_entry->write_proc = pvc_proc_write_scroll;
178 proc_entry->read_proc = pvc_proc_read_scroll;
179
180 init_timer(&timer);
181 timer.function = pvc_proc_timerfunc;
182
183 return 0;
184error:
185 pvc_proc_cleanup();
186 return -ENOMEM;
187}
188
189module_init(pvc_proc_init);
190module_exit(pvc_proc_cleanup);
191MODULE_LICENSE("GPL");
diff --git a/arch/mips/lasat/prom.c b/arch/mips/lasat/prom.c
new file mode 100644
index 000000000000..209edcc26f07
--- /dev/null
+++ b/arch/mips/lasat/prom.c
@@ -0,0 +1,126 @@
1/*
2 * PROM interface routines.
3 */
4#include <linux/types.h>
5#include <linux/init.h>
6#include <linux/string.h>
7#include <linux/ctype.h>
8#include <linux/kernel.h>
9#include <linux/mm.h>
10#include <linux/bootmem.h>
11#include <linux/ioport.h>
12#include <asm/bootinfo.h>
13#include <asm/lasat/lasat.h>
14#include <asm/cpu.h>
15
16#include "at93c.h"
17#include <asm/lasat/eeprom.h>
18#include "prom.h"
19
20#define RESET_VECTOR 0xbfc00000
21#define PROM_JUMP_TABLE_ENTRY(n) (*((u32 *)(RESET_VECTOR + 0x20) + n))
22#define PROM_DISPLAY_ADDR PROM_JUMP_TABLE_ENTRY(0)
23#define PROM_PUTC_ADDR PROM_JUMP_TABLE_ENTRY(1)
24#define PROM_MONITOR_ADDR PROM_JUMP_TABLE_ENTRY(2)
25
26static void null_prom_display(const char *string, int pos, int clear)
27{
28}
29
30static void null_prom_monitor(void)
31{
32}
33
34static void null_prom_putc(char c)
35{
36}
37
38/* these are functions provided by the bootloader */
39static void (*__prom_putc)(char c) = null_prom_putc;
40
41void prom_putchar(char c)
42{
43 __prom_putc(c);
44}
45
46void (*prom_display)(const char *string, int pos, int clear) =
47 null_prom_display;
48void (*prom_monitor)(void) = null_prom_monitor;
49
50unsigned int lasat_ndelay_divider;
51
52static void setup_prom_vectors(void)
53{
54 u32 version = *(u32 *)(RESET_VECTOR + 0x90);
55
56 if (version >= 307) {
57 prom_display = (void *)PROM_DISPLAY_ADDR;
58 __prom_putc = (void *)PROM_PUTC_ADDR;
59 prom_monitor = (void *)PROM_MONITOR_ADDR;
60 }
61 printk(KERN_DEBUG "prom vectors set up\n");
62}
63
64static struct at93c_defs at93c_defs[N_MACHTYPES] = {
65 {
66 .reg = (void *)AT93C_REG_100,
67 .rdata_reg = (void *)AT93C_RDATA_REG_100,
68 .rdata_shift = AT93C_RDATA_SHIFT_100,
69 .wdata_shift = AT93C_WDATA_SHIFT_100,
70 .cs = AT93C_CS_M_100,
71 .clk = AT93C_CLK_M_100
72 }, {
73 .reg = (void *)AT93C_REG_200,
74 .rdata_reg = (void *)AT93C_RDATA_REG_200,
75 .rdata_shift = AT93C_RDATA_SHIFT_200,
76 .wdata_shift = AT93C_WDATA_SHIFT_200,
77 .cs = AT93C_CS_M_200,
78 .clk = AT93C_CLK_M_200
79 },
80};
81
82void __init prom_init(void)
83{
84 int argc = fw_arg0;
85 char **argv = (char **) fw_arg1;
86
87 setup_prom_vectors();
88
89 if (current_cpu_data.cputype == CPU_R5000) {
90 printk(KERN_INFO "LASAT 200 board\n");
91 mips_machtype = MACH_LASAT_200;
92 lasat_ndelay_divider = LASAT_200_DIVIDER;
93 } else {
94 printk(KERN_INFO "LASAT 100 board\n");
95 mips_machtype = MACH_LASAT_100;
96 lasat_ndelay_divider = LASAT_100_DIVIDER;
97 }
98
99 at93c = &at93c_defs[mips_machtype];
100
101 lasat_init_board_info(); /* Read info from EEPROM */
102
103 /* Get the command line */
104 if (argc > 0) {
105 strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
106 arcs_cmdline[CL_SIZE-1] = '\0';
107 }
108
109 /* Set the I/O base address */
110 set_io_port_base(KSEG1);
111
112 /* Set memory regions */
113 ioport_resource.start = 0;
114 ioport_resource.end = 0xffffffff; /* Wrong, fixme. */
115
116 add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM);
117}
118
119void __init prom_free_prom_memory(void)
120{
121}
122
123const char *get_system_type(void)
124{
125 return lasat_board_info.li_bmstr;
126}
diff --git a/arch/mips/lasat/prom.h b/arch/mips/lasat/prom.h
new file mode 100644
index 000000000000..337acbc27442
--- /dev/null
+++ b/arch/mips/lasat/prom.h
@@ -0,0 +1,7 @@
1#ifndef __PROM_H
2#define __PROM_H
3
4extern void (*prom_display)(const char *string, int pos, int clear);
5extern void (*prom_monitor)(void);
6
7#endif /* __PROM_H */
diff --git a/arch/mips/lasat/reset.c b/arch/mips/lasat/reset.c
new file mode 100644
index 000000000000..b1e7a89fb730
--- /dev/null
+++ b/arch/mips/lasat/reset.c
@@ -0,0 +1,61 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Reset the LASAT board.
19 */
20#include <linux/kernel.h>
21#include <linux/pm.h>
22
23#include <asm/reboot.h>
24#include <asm/system.h>
25#include <asm/lasat/lasat.h>
26
27#include "picvue.h"
28#include "prom.h"
29
30static void lasat_machine_restart(char *command);
31static void lasat_machine_halt(void);
32
33/* Used to set machine to boot in service mode via /proc interface */
34int lasat_boot_to_service;
35
36static void lasat_machine_restart(char *command)
37{
38 local_irq_disable();
39
40 if (lasat_boot_to_service) {
41 *(volatile unsigned int *)0xa0000024 = 0xdeadbeef;
42 *(volatile unsigned int *)0xa00000fc = 0xfedeabba;
43 }
44 *lasat_misc->reset_reg = 0xbedead;
45 for (;;) ;
46}
47
48static void lasat_machine_halt(void)
49{
50 local_irq_disable();
51
52 prom_monitor();
53 for (;;) ;
54}
55
56void lasat_reboot_setup(void)
57{
58 _machine_restart = lasat_machine_restart;
59 _machine_halt = lasat_machine_halt;
60 pm_power_off = lasat_machine_halt;
61}
diff --git a/arch/mips/lasat/serial.c b/arch/mips/lasat/serial.c
new file mode 100644
index 000000000000..205bd397d75b
--- /dev/null
+++ b/arch/mips/lasat/serial.c
@@ -0,0 +1,94 @@
1/*
2 * Registration of Lasat UART platform device.
3 *
4 * Copyright (C) 2007 Brian Murphy <brian@murphy.dk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/platform_device.h>
24#include <linux/serial_8250.h>
25
26#include <asm/bootinfo.h>
27#include <asm/lasat/lasat.h>
28#include <asm/lasat/serial.h>
29
30static struct resource lasat_serial_res[2] __initdata;
31
32static struct plat_serial8250_port lasat_serial8250_port[] = {
33 {
34 .iotype = UPIO_MEM,
35 .flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF |
36 UPF_SKIP_TEST,
37 },
38 {},
39};
40
41static __init int lasat_uart_add(void)
42{
43 struct platform_device *pdev;
44 int retval;
45
46 pdev = platform_device_alloc("serial8250", -1);
47 if (!pdev)
48 return -ENOMEM;
49
50 if (mips_machtype == MACH_LASAT_100) {
51 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_100);
52 lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_100 * 8 - 1;
53 lasat_serial_res[0].flags = IORESOURCE_MEM;
54 lasat_serial_res[1].start = LASATINT_UART_100;
55 lasat_serial_res[1].end = LASATINT_UART_100;
56 lasat_serial_res[1].flags = IORESOURCE_IRQ;
57
58 lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_100;
59 lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_100 * 16;
60 lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_100;
61 lasat_serial8250_port[0].irq = LASATINT_UART_100;
62 } else {
63 lasat_serial_res[0].start = KSEG1ADDR(LASAT_UART_REGS_BASE_200);
64 lasat_serial_res[0].end = lasat_serial_res[0].start + LASAT_UART_REGS_SHIFT_200 * 8 - 1;
65 lasat_serial_res[0].flags = IORESOURCE_MEM;
66 lasat_serial_res[1].start = LASATINT_UART_200;
67 lasat_serial_res[1].end = LASATINT_UART_200;
68 lasat_serial_res[1].flags = IORESOURCE_IRQ;
69
70 lasat_serial8250_port[0].mapbase = LASAT_UART_REGS_BASE_200;
71 lasat_serial8250_port[0].uartclk = LASAT_BASE_BAUD_200 * 16;
72 lasat_serial8250_port[0].regshift = LASAT_UART_REGS_SHIFT_200;
73 lasat_serial8250_port[0].irq = LASATINT_UART_200;
74 }
75
76 pdev->id = PLAT8250_DEV_PLATFORM;
77 pdev->dev.platform_data = lasat_serial8250_port;
78
79 retval = platform_device_add_resources(pdev, lasat_serial_res, ARRAY_SIZE(lasat_serial_res));
80 if (retval)
81 goto err_free_device;
82
83 retval = platform_device_add(pdev);
84 if (retval)
85 goto err_free_device;
86
87 return 0;
88
89err_free_device:
90 platform_device_put(pdev);
91
92 return retval;
93}
94device_initcall(lasat_uart_add);
diff --git a/arch/mips/lasat/setup.c b/arch/mips/lasat/setup.c
new file mode 100644
index 000000000000..54827d0174bf
--- /dev/null
+++ b/arch/mips/lasat/setup.c
@@ -0,0 +1,154 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999 MIPS Technologies, Inc. All rights reserved.
4 *
5 * Thomas Horsten <thh@lasat.com>
6 * Copyright (C) 2000 LASAT Networks A/S.
7 *
8 * Brian Murphy <brian@murphy.dk>
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * Lasat specific setup.
24 */
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/pci.h>
28#include <linux/interrupt.h>
29#include <linux/tty.h>
30
31#include <asm/time.h>
32#include <asm/cpu.h>
33#include <asm/bootinfo.h>
34#include <asm/irq.h>
35#include <asm/lasat/lasat.h>
36#include <asm/lasat/serial.h>
37
38#ifdef CONFIG_PICVUE
39#include <linux/notifier.h>
40#endif
41
42#include "ds1603.h"
43#include <asm/lasat/ds1603.h>
44#include <asm/lasat/picvue.h>
45#include <asm/lasat/eeprom.h>
46
47#include "prom.h"
48
49int lasat_command_line;
50void lasatint_init(void);
51
52extern void lasat_reboot_setup(void);
53extern void pcisetup(void);
54extern void edhac_init(void *, void *, void *);
55extern void addrflt_init(void);
56
57struct lasat_misc lasat_misc_info[N_MACHTYPES] = {
58 {
59 .reset_reg = (void *)KSEG1ADDR(0x1c840000),
60 .flash_wp_reg = (void *)KSEG1ADDR(0x1c800000), 2
61 }, {
62 .reset_reg = (void *)KSEG1ADDR(0x11080000),
63 .flash_wp_reg = (void *)KSEG1ADDR(0x11000000), 6
64 }
65};
66
67struct lasat_misc *lasat_misc;
68
69#ifdef CONFIG_DS1603
70static struct ds_defs ds_defs[N_MACHTYPES] = {
71 { (void *)DS1603_REG_100, (void *)DS1603_REG_100,
72 DS1603_RST_100, DS1603_CLK_100, DS1603_DATA_100,
73 DS1603_DATA_SHIFT_100, 0, 0 },
74 { (void *)DS1603_REG_200, (void *)DS1603_DATA_REG_200,
75 DS1603_RST_200, DS1603_CLK_200, DS1603_DATA_200,
76 DS1603_DATA_READ_SHIFT_200, 1, 2000 }
77};
78#endif
79
80#ifdef CONFIG_PICVUE
81#include "picvue.h"
82static struct pvc_defs pvc_defs[N_MACHTYPES] = {
83 { (void *)PVC_REG_100, PVC_DATA_SHIFT_100, PVC_DATA_M_100,
84 PVC_E_100, PVC_RW_100, PVC_RS_100 },
85 { (void *)PVC_REG_200, PVC_DATA_SHIFT_200, PVC_DATA_M_200,
86 PVC_E_200, PVC_RW_200, PVC_RS_200 }
87};
88#endif
89
90static int lasat_panic_display(struct notifier_block *this,
91 unsigned long event, void *ptr)
92{
93#ifdef CONFIG_PICVUE
94 unsigned char *string = ptr;
95 if (string == NULL)
96 string = "Kernel Panic";
97 pvc_dump_string(string);
98#endif
99 return NOTIFY_DONE;
100}
101
102static int lasat_panic_prom_monitor(struct notifier_block *this,
103 unsigned long event, void *ptr)
104{
105 prom_monitor();
106 return NOTIFY_DONE;
107}
108
109static struct notifier_block lasat_panic_block[] =
110{
111 {
112 .notifier_call = lasat_panic_display,
113 .priority = INT_MAX
114 }, {
115 .notifier_call = lasat_panic_prom_monitor,
116 .priority = INT_MIN
117 }
118};
119
120void plat_time_init(void)
121{
122 mips_hpt_frequency = lasat_board_info.li_cpu_hz / 2;
123}
124
125void __init plat_timer_setup(struct irqaction *irq)
126{
127 change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
128}
129
130void __init plat_mem_setup(void)
131{
132 int i;
133 lasat_misc = &lasat_misc_info[mips_machtype];
134#ifdef CONFIG_PICVUE
135 picvue = &pvc_defs[mips_machtype];
136#endif
137
138 /* Set up panic notifier */
139 for (i = 0; i < ARRAY_SIZE(lasat_panic_block); i++)
140 atomic_notifier_chain_register(&panic_notifier_list,
141 &lasat_panic_block[i]);
142
143 lasat_reboot_setup();
144
145#ifdef CONFIG_DS1603
146 ds1603 = &ds_defs[mips_machtype];
147#endif
148
149#ifdef DYNAMIC_SERIAL_INIT
150 serial_init();
151#endif
152
153 pr_info("Lasat specific initialization complete\n");
154}
diff --git a/arch/mips/lasat/sysctl.c b/arch/mips/lasat/sysctl.c
new file mode 100644
index 000000000000..389336c4ecc5
--- /dev/null
+++ b/arch/mips/lasat/sysctl.c
@@ -0,0 +1,456 @@
1/*
2 * Thomas Horsten <thh@lasat.com>
3 * Copyright (C) 2000 LASAT Networks A/S.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Routines specific to the LASAT boards
19 */
20#include <linux/types.h>
21#include <asm/lasat/lasat.h>
22
23#include <linux/module.h>
24#include <linux/sysctl.h>
25#include <linux/stddef.h>
26#include <linux/init.h>
27#include <linux/fs.h>
28#include <linux/ctype.h>
29#include <linux/string.h>
30#include <linux/net.h>
31#include <linux/inet.h>
32#include <linux/mutex.h>
33#include <linux/uaccess.h>
34
35#include <asm/time.h>
36
37#include "sysctl.h"
38#include "ds1603.h"
39
40static DEFINE_MUTEX(lasat_info_mutex);
41
42/* Strategy function to write EEPROM after changing string entry */
43int sysctl_lasatstring(ctl_table *table, int *name, int nlen,
44 void *oldval, size_t *oldlenp,
45 void *newval, size_t newlen)
46{
47 int r;
48
49 mutex_lock(&lasat_info_mutex);
50 r = sysctl_string(table, name,
51 nlen, oldval, oldlenp, newval, newlen);
52 if (r < 0) {
53 mutex_unlock(&lasat_info_mutex);
54 return r;
55 }
56 if (newval && newlen)
57 lasat_write_eeprom_info();
58 mutex_unlock(&lasat_info_mutex);
59
60 return 1;
61}
62
63
64/* And the same for proc */
65int proc_dolasatstring(ctl_table *table, int write, struct file *filp,
66 void *buffer, size_t *lenp, loff_t *ppos)
67{
68 int r;
69
70 mutex_lock(&lasat_info_mutex);
71 r = proc_dostring(table, write, filp, buffer, lenp, ppos);
72 if ((!write) || r) {
73 mutex_unlock(&lasat_info_mutex);
74 return r;
75 }
76 lasat_write_eeprom_info();
77 mutex_unlock(&lasat_info_mutex);
78
79 return 0;
80}
81
82/* proc function to write EEPROM after changing int entry */
83int proc_dolasatint(ctl_table *table, int write, struct file *filp,
84 void *buffer, size_t *lenp, loff_t *ppos)
85{
86 int r;
87
88 mutex_lock(&lasat_info_mutex);
89 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
90 if ((!write) || r) {
91 mutex_unlock(&lasat_info_mutex);
92 return r;
93 }
94 lasat_write_eeprom_info();
95 mutex_unlock(&lasat_info_mutex);
96
97 return 0;
98}
99
100static int rtctmp;
101
102#ifdef CONFIG_DS1603
103/* proc function to read/write RealTime Clock */
104int proc_dolasatrtc(ctl_table *table, int write, struct file *filp,
105 void *buffer, size_t *lenp, loff_t *ppos)
106{
107 int r;
108
109 mutex_lock(&lasat_info_mutex);
110 if (!write) {
111 rtctmp = read_persistent_clock();
112 /* check for time < 0 and set to 0 */
113 if (rtctmp < 0)
114 rtctmp = 0;
115 }
116 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
117 if ((!write) || r) {
118 mutex_unlock(&lasat_info_mutex);
119 return r;
120 }
121 rtc_mips_set_mmss(rtctmp);
122 mutex_unlock(&lasat_info_mutex);
123
124 return 0;
125}
126#endif
127
128/* Sysctl for setting the IP addresses */
129int sysctl_lasat_intvec(ctl_table *table, int *name, int nlen,
130 void *oldval, size_t *oldlenp,
131 void *newval, size_t newlen)
132{
133 int r;
134
135 mutex_lock(&lasat_info_mutex);
136 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
137 if (r < 0) {
138 mutex_unlock(&lasat_info_mutex);
139 return r;
140 }
141 if (newval && newlen)
142 lasat_write_eeprom_info();
143 mutex_unlock(&lasat_info_mutex);
144
145 return 1;
146}
147
148#ifdef CONFIG_DS1603
149/* Same for RTC */
150int sysctl_lasat_rtc(ctl_table *table, int *name, int nlen,
151 void *oldval, size_t *oldlenp,
152 void *newval, size_t newlen)
153{
154 int r;
155
156 mutex_lock(&lasat_info_mutex);
157 rtctmp = read_persistent_clock();
158 if (rtctmp < 0)
159 rtctmp = 0;
160 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
161 if (r < 0) {
162 mutex_unlock(&lasat_info_mutex);
163 return r;
164 }
165 if (newval && newlen)
166 rtc_mips_set_mmss(rtctmp);
167 mutex_unlock(&lasat_info_mutex);
168
169 return 1;
170}
171#endif
172
173#ifdef CONFIG_INET
174static char lasat_bcastaddr[16];
175
176void update_bcastaddr(void)
177{
178 unsigned int ip;
179
180 ip = (lasat_board_info.li_eeprom_info.ipaddr &
181 lasat_board_info.li_eeprom_info.netmask) |
182 ~lasat_board_info.li_eeprom_info.netmask;
183
184 sprintf(lasat_bcastaddr, "%d.%d.%d.%d",
185 (ip) & 0xff,
186 (ip >> 8) & 0xff,
187 (ip >> 16) & 0xff,
188 (ip >> 24) & 0xff);
189}
190
191static char proc_lasat_ipbuf[32];
192
193/* Parsing of IP address */
194int proc_lasat_ip(ctl_table *table, int write, struct file *filp,
195 void *buffer, size_t *lenp, loff_t *ppos)
196{
197 unsigned int ip;
198 char *p, c;
199 int len;
200
201 if (!table->data || !table->maxlen || !*lenp ||
202 (*ppos && !write)) {
203 *lenp = 0;
204 return 0;
205 }
206
207 mutex_lock(&lasat_info_mutex);
208 if (write) {
209 len = 0;
210 p = buffer;
211 while (len < *lenp) {
212 if (get_user(c, p++)) {
213 mutex_unlock(&lasat_info_mutex);
214 return -EFAULT;
215 }
216 if (c == 0 || c == '\n')
217 break;
218 len++;
219 }
220 if (len >= sizeof(proc_lasat_ipbuf)-1)
221 len = sizeof(proc_lasat_ipbuf) - 1;
222 if (copy_from_user(proc_lasat_ipbuf, buffer, len)) {
223 mutex_unlock(&lasat_info_mutex);
224 return -EFAULT;
225 }
226 proc_lasat_ipbuf[len] = 0;
227 *ppos += *lenp;
228 /* Now see if we can convert it to a valid IP */
229 ip = in_aton(proc_lasat_ipbuf);
230 *(unsigned int *)(table->data) = ip;
231 lasat_write_eeprom_info();
232 } else {
233 ip = *(unsigned int *)(table->data);
234 sprintf(proc_lasat_ipbuf, "%d.%d.%d.%d",
235 (ip) & 0xff,
236 (ip >> 8) & 0xff,
237 (ip >> 16) & 0xff,
238 (ip >> 24) & 0xff);
239 len = strlen(proc_lasat_ipbuf);
240 if (len > *lenp)
241 len = *lenp;
242 if (len)
243 if (copy_to_user(buffer, proc_lasat_ipbuf, len)) {
244 mutex_unlock(&lasat_info_mutex);
245 return -EFAULT;
246 }
247 if (len < *lenp) {
248 if (put_user('\n', ((char *) buffer) + len)) {
249 mutex_unlock(&lasat_info_mutex);
250 return -EFAULT;
251 }
252 len++;
253 }
254 *lenp = len;
255 *ppos += len;
256 }
257 update_bcastaddr();
258 mutex_unlock(&lasat_info_mutex);
259
260 return 0;
261}
262#endif /* defined(CONFIG_INET) */
263
264static int sysctl_lasat_eeprom_value(ctl_table *table, int *name, int nlen,
265 void *oldval, size_t *oldlenp,
266 void *newval, size_t newlen)
267{
268 int r;
269
270 mutex_lock(&lasat_info_mutex);
271 r = sysctl_intvec(table, name, nlen, oldval, oldlenp, newval, newlen);
272 if (r < 0) {
273 mutex_unlock(&lasat_info_mutex);
274 return r;
275 }
276
277 if (newval && newlen) {
278 if (name && *name == LASAT_PRID)
279 lasat_board_info.li_eeprom_info.prid = *(int *)newval;
280
281 lasat_write_eeprom_info();
282 lasat_init_board_info();
283 }
284 mutex_unlock(&lasat_info_mutex);
285
286 return 0;
287}
288
289int proc_lasat_eeprom_value(ctl_table *table, int write, struct file *filp,
290 void *buffer, size_t *lenp, loff_t *ppos)
291{
292 int r;
293
294 mutex_lock(&lasat_info_mutex);
295 r = proc_dointvec(table, write, filp, buffer, lenp, ppos);
296 if ((!write) || r) {
297 mutex_unlock(&lasat_info_mutex);
298 return r;
299 }
300 if (filp && filp->f_path.dentry) {
301 if (!strcmp(filp->f_path.dentry->d_name.name, "prid"))
302 lasat_board_info.li_eeprom_info.prid =
303 lasat_board_info.li_prid;
304 if (!strcmp(filp->f_path.dentry->d_name.name, "debugaccess"))
305 lasat_board_info.li_eeprom_info.debugaccess =
306 lasat_board_info.li_debugaccess;
307 }
308 lasat_write_eeprom_info();
309 mutex_unlock(&lasat_info_mutex);
310
311 return 0;
312}
313
314extern int lasat_boot_to_service;
315
316#ifdef CONFIG_SYSCTL
317
318static ctl_table lasat_table[] = {
319 {
320 .ctl_name = CTL_UNNUMBERED,
321 .procname = "cpu-hz",
322 .data = &lasat_board_info.li_cpu_hz,
323 .maxlen = sizeof(int),
324 .mode = 0444,
325 .proc_handler = &proc_dointvec,
326 .strategy = &sysctl_intvec
327 },
328 {
329 .ctl_name = CTL_UNNUMBERED,
330 .procname = "bus-hz",
331 .data = &lasat_board_info.li_bus_hz,
332 .maxlen = sizeof(int),
333 .mode = 0444,
334 .proc_handler = &proc_dointvec,
335 .strategy = &sysctl_intvec
336 },
337 {
338 .ctl_name = CTL_UNNUMBERED,
339 .procname = "bmid",
340 .data = &lasat_board_info.li_bmid,
341 .maxlen = sizeof(int),
342 .mode = 0444,
343 .proc_handler = &proc_dointvec,
344 .strategy = &sysctl_intvec
345 },
346 {
347 .ctl_name = CTL_UNNUMBERED,
348 .procname = "prid",
349 .data = &lasat_board_info.li_prid,
350 .maxlen = sizeof(int),
351 .mode = 0644,
352 .proc_handler = &proc_lasat_eeprom_value,
353 .strategy = &sysctl_lasat_eeprom_value
354 },
355#ifdef CONFIG_INET
356 {
357 .ctl_name = CTL_UNNUMBERED,
358 .procname = "ipaddr",
359 .data = &lasat_board_info.li_eeprom_info.ipaddr,
360 .maxlen = sizeof(int),
361 .mode = 0644,
362 .proc_handler = &proc_lasat_ip,
363 .strategy = &sysctl_lasat_intvec
364 },
365 {
366 .ctl_name = LASAT_NETMASK,
367 .procname = "netmask",
368 .data = &lasat_board_info.li_eeprom_info.netmask,
369 .maxlen = sizeof(int),
370 .mode = 0644,
371 .proc_handler = &proc_lasat_ip,
372 .strategy = &sysctl_lasat_intvec
373 },
374 {
375 .ctl_name = CTL_UNNUMBERED,
376 .procname = "bcastaddr",
377 .data = &lasat_bcastaddr,
378 .maxlen = sizeof(lasat_bcastaddr),
379 .mode = 0600,
380 .proc_handler = &proc_dostring,
381 .strategy = &sysctl_string
382 },
383#endif
384 {
385 .ctl_name = CTL_UNNUMBERED,
386 .procname = "passwd_hash",
387 .data = &lasat_board_info.li_eeprom_info.passwd_hash,
388 .maxlen =
389 sizeof(lasat_board_info.li_eeprom_info.passwd_hash),
390 .mode = 0600,
391 .proc_handler = &proc_dolasatstring,
392 .strategy = &sysctl_lasatstring
393 },
394 {
395 .ctl_name = CTL_UNNUMBERED,
396 .procname = "boot-service",
397 .data = &lasat_boot_to_service,
398 .maxlen = sizeof(int),
399 .mode = 0644,
400 .proc_handler = &proc_dointvec,
401 .strategy = &sysctl_intvec
402 },
403#ifdef CONFIG_DS1603
404 {
405 .ctl_name = CTL_UNNUMBERED,
406 .procname = "rtc",
407 .data = &rtctmp,
408 .maxlen = sizeof(int),
409 .mode = 0644,
410 .proc_handler = &proc_dolasatrtc,
411 .strategy = &sysctl_lasat_rtc
412 },
413#endif
414 {
415 .ctl_name = CTL_UNNUMBERED,
416 .procname = "namestr",
417 .data = &lasat_board_info.li_namestr,
418 .maxlen = sizeof(lasat_board_info.li_namestr),
419 .mode = 0444,
420 .proc_handler = &proc_dostring,
421 .strategy = &sysctl_string
422 },
423 {
424 .ctl_name = CTL_UNNUMBERED,
425 .procname = "typestr",
426 .data = &lasat_board_info.li_typestr,
427 .maxlen = sizeof(lasat_board_info.li_typestr),
428 .mode = 0444,
429 .proc_handler = &proc_dostring,
430 .strategy = &sysctl_string
431 },
432 {}
433};
434
435static ctl_table lasat_root_table[] = {
436 {
437 .ctl_name = CTL_UNNUMBERED,
438 .procname = "lasat",
439 .mode = 0555,
440 .child = lasat_table
441 },
442 {}
443};
444
445static int __init lasat_register_sysctl(void)
446{
447 struct ctl_table_header *lasat_table_header;
448
449 lasat_table_header =
450 register_sysctl_table(lasat_root_table);
451
452 return 0;
453}
454
455__initcall(lasat_register_sysctl);
456#endif /* CONFIG_SYSCTL */
diff --git a/arch/mips/lasat/sysctl.h b/arch/mips/lasat/sysctl.h
new file mode 100644
index 000000000000..341b97933423
--- /dev/null
+++ b/arch/mips/lasat/sysctl.h
@@ -0,0 +1,24 @@
1/*
2 * LASAT sysctl values
3 */
4
5#ifndef _LASAT_SYSCTL_H
6#define _LASAT_SYSCTL_H
7
8/* /proc/sys/lasat */
9enum {
10 LASAT_CPU_HZ = 1,
11 LASAT_BUS_HZ,
12 LASAT_MODEL,
13 LASAT_PRID,
14 LASAT_IPADDR,
15 LASAT_NETMASK,
16 LASAT_BCAST,
17 LASAT_PASSWORD,
18 LASAT_SBOOT,
19 LASAT_RTC,
20 LASAT_NAMESTR,
21 LASAT_TYPESTR,
22};
23
24#endif /* _LASAT_SYSCTL_H */
diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile
index dcaf6f4c3a37..d34671d1b899 100644
--- a/arch/mips/lemote/lm2e/Makefile
+++ b/arch/mips/lemote/lm2e/Makefile
@@ -4,5 +4,4 @@
4 4
5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o 5obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o
6 6
7EXTRA_AFLAGS := $(CFLAGS)
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c
index 3efb1cf111f2..824336812198 100644
--- a/arch/mips/lemote/lm2e/prom.c
+++ b/arch/mips/lemote/lm2e/prom.c
@@ -57,7 +57,6 @@ void __init prom_init(void)
57 arg = (int *)fw_arg1; 57 arg = (int *)fw_arg1;
58 env = (int *)fw_arg2; 58 env = (int *)fw_arg2;
59 59
60 mips_machgroup = MACH_GROUP_LEMOTE;
61 mips_machtype = MACH_LEMOTE_FULONG; 60 mips_machtype = MACH_LEMOTE_FULONG;
62 61
63 prom_init_cmdline(); 62 prom_init_cmdline();
diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c
index f34350a4f271..09314a20f9fb 100644
--- a/arch/mips/lemote/lm2e/setup.c
+++ b/arch/mips/lemote/lm2e/setup.c
@@ -58,13 +58,13 @@ void __init plat_timer_setup(struct irqaction *irq)
58 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq); 58 setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
59} 59}
60 60
61static void __init loongson2e_time_init(void) 61void __init plat_time_init(void)
62{ 62{
63 /* setup mips r4k timer */ 63 /* setup mips r4k timer */
64 mips_hpt_frequency = cpu_clock_freq / 2; 64 mips_hpt_frequency = cpu_clock_freq / 2;
65} 65}
66 66
67static unsigned long __init mips_rtc_get_time(void) 67unsigned long read_persistent_clock(void)
68{ 68{
69 return mc146818_get_cmos_time(); 69 return mc146818_get_cmos_time();
70} 70}
@@ -89,9 +89,6 @@ void __init plat_mem_setup(void)
89 89
90 mips_reboot_setup(); 90 mips_reboot_setup();
91 91
92 board_time_init = loongson2e_time_init;
93 rtc_mips_get_time = mips_rtc_get_time;
94
95 __wbflush = wbflush_loongson2e; 92 __wbflush = wbflush_loongson2e;
96 93
97 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); 94 add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
diff --git a/arch/mips/lib/ucmpdi2.c b/arch/mips/lib/ucmpdi2.c
index e2ff6072b5a3..b33d8569bcb0 100644
--- a/arch/mips/lib/ucmpdi2.c
+++ b/arch/mips/lib/ucmpdi2.c
@@ -2,7 +2,7 @@
2 2
3#include "libgcc.h" 3#include "libgcc.h"
4 4
5word_type __ucmpdi2 (unsigned long long a, unsigned long long b) 5word_type __ucmpdi2(unsigned long long a, unsigned long long b)
6{ 6{
7 const DWunion au = {.ll = a}; 7 const DWunion au = {.ll = a};
8 const DWunion bu = {.ll = b}; 8 const DWunion bu = {.ll = b};
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 17419e11ecad..b08fc65c13a6 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -178,24 +178,24 @@ static int isBranchInstr(mips_instruction * i)
178#define FR_BIT 0 178#define FR_BIT 0
179#endif 179#endif
180 180
181#define SIFROMREG(si,x) ((si) = \ 181#define SIFROMREG(si, x) ((si) = \
182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 182 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
183 (int)ctx->fpr[x] : \ 183 (int)ctx->fpr[x] : \
184 (int)(ctx->fpr[x & ~1] >> 32 )) 184 (int)(ctx->fpr[x & ~1] >> 32 ))
185#define SITOREG(si,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ 185#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ 186 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ 187 ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \
188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) 188 ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32)
189 189
190#define DIFROMREG(di,x) ((di) = \ 190#define DIFROMREG(di, x) ((di) = \
191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) 191 ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)])
192#define DITOREG(di,x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ 192#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
193 = (di)) 193 = (di))
194 194
195#define SPFROMREG(sp,x) SIFROMREG((sp).bits,x) 195#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
196#define SPTOREG(sp,x) SITOREG((sp).bits,x) 196#define SPTOREG(sp, x) SITOREG((sp).bits, x)
197#define DPFROMREG(dp,x) DIFROMREG((dp).bits,x) 197#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
198#define DPTOREG(dp,x) DITOREG((dp).bits,x) 198#define DPTOREG(dp, x) DITOREG((dp).bits, x)
199 199
200/* 200/*
201 * Emulate the single floating point instruction pointed at by EPC. 201 * Emulate the single floating point instruction pointed at by EPC.
@@ -549,16 +549,16 @@ static const unsigned char cmptab[8] = {
549 */ 549 */
550 550
551#define DEF3OP(name, p, f1, f2, f3) \ 551#define DEF3OP(name, p, f1, f2, f3) \
552static ieee754##p fpemu_##p##_##name (ieee754##p r, ieee754##p s, \ 552static ieee754##p fpemu_##p##_##name(ieee754##p r, ieee754##p s, \
553 ieee754##p t) \ 553 ieee754##p t) \
554{ \ 554{ \
555 struct _ieee754_csr ieee754_csr_save; \ 555 struct _ieee754_csr ieee754_csr_save; \
556 s = f1 (s, t); \ 556 s = f1(s, t); \
557 ieee754_csr_save = ieee754_csr; \ 557 ieee754_csr_save = ieee754_csr; \
558 s = f2 (s, r); \ 558 s = f2(s, r); \
559 ieee754_csr_save.cx |= ieee754_csr.cx; \ 559 ieee754_csr_save.cx |= ieee754_csr.cx; \
560 ieee754_csr_save.sx |= ieee754_csr.sx; \ 560 ieee754_csr_save.sx |= ieee754_csr.sx; \
561 s = f3 (s); \ 561 s = f3(s); \
562 ieee754_csr.cx |= ieee754_csr_save.cx; \ 562 ieee754_csr.cx |= ieee754_csr_save.cx; \
563 ieee754_csr.sx |= ieee754_csr_save.sx; \ 563 ieee754_csr.sx |= ieee754_csr_save.sx; \
564 return s; \ 564 return s; \
@@ -584,12 +584,12 @@ static ieee754sp fpemu_sp_rsqrt(ieee754sp s)
584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s)); 584 return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
585} 585}
586 586
587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add,); 587DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub,); 588DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg); 589DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg); 590DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add,); 591DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub,); 592DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 593DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 594DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
595 595
diff --git a/arch/mips/math-emu/dp_mul.c b/arch/mips/math-emu/dp_mul.c
index f2373902f524..48908a809c17 100644
--- a/arch/mips/math-emu/dp_mul.c
+++ b/arch/mips/math-emu/dp_mul.c
@@ -121,7 +121,7 @@ ieee754dp ieee754dp_mul(ieee754dp x, ieee754dp y)
121 */ 121 */
122 122
123 /* 32 * 32 => 64 */ 123 /* 32 * 32 => 64 */
124#define DPXMULT(x,y) ((u64)(x) * (u64)y) 124#define DPXMULT(x, y) ((u64)(x) * (u64)y)
125 125
126 { 126 {
127 unsigned lxm = xm; 127 unsigned lxm = xm;
diff --git a/arch/mips/math-emu/ieee754.c b/arch/mips/math-emu/ieee754.c
index a93c45dbdefd..946aee331788 100644
--- a/arch/mips/math-emu/ieee754.c
+++ b/arch/mips/math-emu/ieee754.c
@@ -47,13 +47,13 @@
47 47
48 48
49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__) 49#if (defined(BYTE_ORDER) && BYTE_ORDER == LITTLE_ENDIAN) || defined(__MIPSEL__)
50#define SPSTR(s,b,m) {m,b,s} 50#define SPSTR(s, b, m) {m, b, s}
51#define DPSTR(s,b,mh,ml) {ml,mh,b,s} 51#define DPSTR(s, b, mh, ml) {ml, mh, b, s}
52#endif 52#endif
53 53
54#ifdef __MIPSEB__ 54#ifdef __MIPSEB__
55#define SPSTR(s,b,m) {s,b,m} 55#define SPSTR(s, b, m) {s, b, m}
56#define DPSTR(s,b,mh,ml) {s,b,mh,ml} 56#define DPSTR(s, b, mh, ml) {s, b, mh, ml}
57#endif 57#endif
58 58
59const struct ieee754dp_konst __ieee754dp_spcvals[] = { 59const struct ieee754dp_konst __ieee754dp_spcvals[] = {
@@ -65,7 +65,7 @@ const struct ieee754dp_konst __ieee754dp_spcvals[] = {
65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */ 65 DPSTR(1, 3 + DP_EBIAS, 0x40000, 0), /* - 10.0 */
66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */ 66 DPSTR(0, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* + infinity */
67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */ 67 DPSTR(1, DP_EMAX + 1 + DP_EBIAS, 0, 0), /* - infinity */
68 DPSTR(0,DP_EMAX+1+DP_EBIAS,0x7FFFF,0xFFFFFFFF), /* + indef quiet Nan */ 68 DPSTR(0, DP_EMAX+1+DP_EBIAS, 0x7FFFF, 0xFFFFFFFF), /* + indef quiet Nan */
69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */ 69 DPSTR(0, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* + max */
70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */ 70 DPSTR(1, DP_EMAX + DP_EBIAS, 0xFFFFF, 0xFFFFFFFF), /* - max */
71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */ 71 DPSTR(0, DP_EMIN + DP_EBIAS, 0, 0), /* + min normal */
@@ -85,7 +85,7 @@ const struct ieee754sp_konst __ieee754sp_spcvals[] = {
85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */ 85 SPSTR(1, 3 + SP_EBIAS, 0x200000), /* - 10.0 */
86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */ 86 SPSTR(0, SP_EMAX + 1 + SP_EBIAS, 0), /* + infinity */
87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */ 87 SPSTR(1, SP_EMAX + 1 + SP_EBIAS, 0), /* - infinity */
88 SPSTR(0,SP_EMAX+1+SP_EBIAS,0x3FFFFF), /* + indef quiet Nan */ 88 SPSTR(0, SP_EMAX+1+SP_EBIAS, 0x3FFFFF), /* + indef quiet Nan */
89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */ 89 SPSTR(0, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* + max normal */
90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */ 90 SPSTR(1, SP_EMAX + SP_EBIAS, 0x7FFFFF), /* - max normal */
91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */ 91 SPSTR(0, SP_EMIN + SP_EBIAS, 0), /* + min normal */
diff --git a/arch/mips/math-emu/ieee754dp.h b/arch/mips/math-emu/ieee754dp.h
index a37370dae232..8977eb585a37 100644
--- a/arch/mips/math-emu/ieee754dp.h
+++ b/arch/mips/math-emu/ieee754dp.h
@@ -43,8 +43,8 @@
43/* convert denormal to normalized with extended exponent */ 43/* convert denormal to normalized with extended exponent */
44#define DPDNORMx(m,e) \ 44#define DPDNORMx(m,e) \
45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; } 45 while( (m >> DP_MBITS) == 0) { m <<= 1; e--; }
46#define DPDNORMX DPDNORMx(xm,xe) 46#define DPDNORMX DPDNORMx(xm, xe)
47#define DPDNORMY DPDNORMx(ym,ye) 47#define DPDNORMY DPDNORMx(ym, ye)
48 48
49static __inline ieee754dp builddp(int s, int bx, u64 m) 49static __inline ieee754dp builddp(int s, int bx, u64 m)
50{ 50{
@@ -71,13 +71,13 @@ extern ieee754dp ieee754dp_bestnan(ieee754dp, ieee754dp);
71extern ieee754dp ieee754dp_format(int, int, u64); 71extern ieee754dp ieee754dp_format(int, int, u64);
72 72
73 73
74#define DPNORMRET2(s,e,m,name,a0,a1) \ 74#define DPNORMRET2(s, e, m, name, a0, a1) \
75{ \ 75{ \
76 ieee754dp V = ieee754dp_format(s,e,m); \ 76 ieee754dp V = ieee754dp_format(s, e, m); \
77 if(TSTX()) \ 77 if(TSTX()) \
78 return ieee754dp_xcpt(V,name,a0,a1); \ 78 return ieee754dp_xcpt(V, name, a0, a1); \
79 else \ 79 else \
80 return V; \ 80 return V; \
81} 81}
82 82
83#define DPNORMRET1(s,e,m,name,a0) DPNORMRET2(s,e,m,name,a0,a0) 83#define DPNORMRET1(s, e, m, name, a0) DPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/math-emu/ieee754int.h b/arch/mips/math-emu/ieee754int.h
index 4a5a81d6b893..1a846c5425cd 100644
--- a/arch/mips/math-emu/ieee754int.h
+++ b/arch/mips/math-emu/ieee754int.h
@@ -55,16 +55,16 @@
55#define DPBEXP(dp) (dp.parts.bexp) 55#define DPBEXP(dp) (dp.parts.bexp)
56#define DPMANT(dp) (dp.parts.mant) 56#define DPMANT(dp) (dp.parts.mant)
57 57
58#define CLPAIR(x,y) ((x)*6+(y)) 58#define CLPAIR(x, y) ((x)*6+(y))
59 59
60#define CLEARCX \ 60#define CLEARCX \
61 (ieee754_csr.cx = 0) 61 (ieee754_csr.cx = 0)
62 62
63#define SETCX(x) \ 63#define SETCX(x) \
64 (ieee754_csr.cx |= (x),ieee754_csr.sx |= (x)) 64 (ieee754_csr.cx |= (x), ieee754_csr.sx |= (x))
65 65
66#define SETANDTESTCX(x) \ 66#define SETANDTESTCX(x) \
67 (SETCX(x),ieee754_csr.mx & (x)) 67 (SETCX(x), ieee754_csr.mx & (x))
68 68
69#define TSTX() \ 69#define TSTX() \
70 (ieee754_csr.cx & ieee754_csr.mx) 70 (ieee754_csr.cx & ieee754_csr.mx)
@@ -76,7 +76,7 @@
76#define COMPYSP \ 76#define COMPYSP \
77 unsigned ym; int ye; int ys; int yc 77 unsigned ym; int ye; int ys; int yc
78 78
79#define EXPLODESP(v,vc,vs,ve,vm) \ 79#define EXPLODESP(v, vc, vs, ve, vm) \
80{\ 80{\
81 vs = SPSIGN(v);\ 81 vs = SPSIGN(v);\
82 ve = SPBEXP(v);\ 82 ve = SPBEXP(v);\
@@ -100,8 +100,8 @@
100 vc = IEEE754_CLASS_NORM;\ 100 vc = IEEE754_CLASS_NORM;\
101 }\ 101 }\
102} 102}
103#define EXPLODEXSP EXPLODESP(x,xc,xs,xe,xm) 103#define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm)
104#define EXPLODEYSP EXPLODESP(y,yc,ys,ye,ym) 104#define EXPLODEYSP EXPLODESP(y, yc, ys, ye, ym)
105 105
106 106
107#define COMPXDP \ 107#define COMPXDP \
@@ -110,7 +110,7 @@ u64 xm; int xe; int xs; int xc
110#define COMPYDP \ 110#define COMPYDP \
111u64 ym; int ye; int ys; int yc 111u64 ym; int ye; int ys; int yc
112 112
113#define EXPLODEDP(v,vc,vs,ve,vm) \ 113#define EXPLODEDP(v, vc, vs, ve, vm) \
114{\ 114{\
115 vm = DPMANT(v);\ 115 vm = DPMANT(v);\
116 vs = DPSIGN(v);\ 116 vs = DPSIGN(v);\
@@ -134,10 +134,10 @@ u64 ym; int ye; int ys; int yc
134 vc = IEEE754_CLASS_NORM;\ 134 vc = IEEE754_CLASS_NORM;\
135 }\ 135 }\
136} 136}
137#define EXPLODEXDP EXPLODEDP(x,xc,xs,xe,xm) 137#define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm)
138#define EXPLODEYDP EXPLODEDP(y,yc,ys,ye,ym) 138#define EXPLODEYDP EXPLODEDP(y, yc, ys, ye, ym)
139 139
140#define FLUSHDP(v,vc,vs,ve,vm) \ 140#define FLUSHDP(v, vc, vs, ve, vm) \
141 if(vc==IEEE754_CLASS_DNORM) {\ 141 if(vc==IEEE754_CLASS_DNORM) {\
142 if(ieee754_csr.nod) {\ 142 if(ieee754_csr.nod) {\
143 SETCX(IEEE754_INEXACT);\ 143 SETCX(IEEE754_INEXACT);\
@@ -148,7 +148,7 @@ u64 ym; int ye; int ys; int yc
148 }\ 148 }\
149 } 149 }
150 150
151#define FLUSHSP(v,vc,vs,ve,vm) \ 151#define FLUSHSP(v, vc, vs, ve, vm) \
152 if(vc==IEEE754_CLASS_DNORM) {\ 152 if(vc==IEEE754_CLASS_DNORM) {\
153 if(ieee754_csr.nod) {\ 153 if(ieee754_csr.nod) {\
154 SETCX(IEEE754_INEXACT);\ 154 SETCX(IEEE754_INEXACT);\
@@ -159,7 +159,7 @@ u64 ym; int ye; int ys; int yc
159 }\ 159 }\
160 } 160 }
161 161
162#define FLUSHXDP FLUSHDP(x,xc,xs,xe,xm) 162#define FLUSHXDP FLUSHDP(x, xc, xs, xe, xm)
163#define FLUSHYDP FLUSHDP(y,yc,ys,ye,ym) 163#define FLUSHYDP FLUSHDP(y, yc, ys, ye, ym)
164#define FLUSHXSP FLUSHSP(x,xc,xs,xe,xm) 164#define FLUSHXSP FLUSHSP(x, xc, xs, xe, xm)
165#define FLUSHYSP FLUSHSP(y,yc,ys,ye,ym) 165#define FLUSHYSP FLUSHSP(y, yc, ys, ye, ym)
diff --git a/arch/mips/math-emu/ieee754sp.h b/arch/mips/math-emu/ieee754sp.h
index ae82f51297e5..9917c1e4d947 100644
--- a/arch/mips/math-emu/ieee754sp.h
+++ b/arch/mips/math-emu/ieee754sp.h
@@ -48,8 +48,8 @@
48/* convert denormal to normalized with extended exponent */ 48/* convert denormal to normalized with extended exponent */
49#define SPDNORMx(m,e) \ 49#define SPDNORMx(m,e) \
50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; } 50 while( (m >> SP_MBITS) == 0) { m <<= 1; e--; }
51#define SPDNORMX SPDNORMx(xm,xe) 51#define SPDNORMX SPDNORMx(xm, xe)
52#define SPDNORMY SPDNORMx(ym,ye) 52#define SPDNORMY SPDNORMx(ym, ye)
53 53
54static __inline ieee754sp buildsp(int s, int bx, unsigned m) 54static __inline ieee754sp buildsp(int s, int bx, unsigned m)
55{ 55{
@@ -77,13 +77,13 @@ extern ieee754sp ieee754sp_bestnan(ieee754sp, ieee754sp);
77extern ieee754sp ieee754sp_format(int, int, unsigned); 77extern ieee754sp ieee754sp_format(int, int, unsigned);
78 78
79 79
80#define SPNORMRET2(s,e,m,name,a0,a1) \ 80#define SPNORMRET2(s, e, m, name, a0, a1) \
81{ \ 81{ \
82 ieee754sp V = ieee754sp_format(s,e,m); \ 82 ieee754sp V = ieee754sp_format(s, e, m); \
83 if(TSTX()) \ 83 if(TSTX()) \
84 return ieee754sp_xcpt(V,name,a0,a1); \ 84 return ieee754sp_xcpt(V, name, a0, a1); \
85 else \ 85 else \
86 return V; \ 86 return V; \
87} 87}
88 88
89#define SPNORMRET1(s,e,m,name,a0) SPNORMRET2(s,e,m,name,a0,a0) 89#define SPNORMRET1(s, e, m, name, a0) SPNORMRET2(s, e, m, name, a0, a0)
diff --git a/arch/mips/mips-boards/atlas/atlas_gdb.c b/arch/mips/mips-boards/atlas/atlas_gdb.c
index fb65280f1780..00c98cff62dc 100644
--- a/arch/mips/mips-boards/atlas/atlas_gdb.c
+++ b/arch/mips/mips-boards/atlas/atlas_gdb.c
@@ -22,7 +22,7 @@
22#include <asm/mips-boards/saa9730_uart.h> 22#include <asm/mips-boards/saa9730_uart.h>
23 23
24#define INB(a) inb((unsigned long)a) 24#define INB(a) inb((unsigned long)a)
25#define OUTB(x,a) outb(x,(unsigned long)a) 25#define OUTB(x, a) outb(x, (unsigned long)a)
26 26
27/* 27/*
28 * This is the interface to the remote debugger stub 28 * This is the interface to the remote debugger stub
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index 3c692abc2553..6fb29c3ff62d 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -112,7 +112,7 @@ static inline void atlas_hw0_irqdispatch(void)
112 112
113static inline int clz(unsigned long x) 113static inline int clz(unsigned long x)
114{ 114{
115 __asm__ ( 115 __asm__(
116 " .set push \n" 116 " .set push \n"
117 " .set mips32 \n" 117 " .set mips32 \n"
118 " clz %0, %1 \n" 118 " clz %0, %1 \n"
@@ -194,7 +194,7 @@ asmlinkage void plat_irq_dispatch(void)
194 spurious_interrupt(); 194 spurious_interrupt();
195} 195}
196 196
197static inline void init_atlas_irqs (int base) 197static inline void init_atlas_irqs(int base)
198{ 198{
199 int i; 199 int i;
200 200
@@ -249,21 +249,21 @@ void __init arch_init_irq(void)
249 case MIPS_REVISION_CORID_CORE_24K: 249 case MIPS_REVISION_CORID_CORE_24K:
250 case MIPS_REVISION_CORID_CORE_EMUL_MSC: 250 case MIPS_REVISION_CORID_CORE_EMUL_MSC:
251 if (cpu_has_veic) 251 if (cpu_has_veic)
252 init_msc_irqs (MSC01E_INT_BASE, MSC01E_INT_BASE, 252 init_msc_irqs(MSC01E_INT_BASE, MSC01E_INT_BASE,
253 msc_eicirqmap, msc_nr_eicirqs); 253 msc_eicirqmap, msc_nr_eicirqs);
254 else 254 else
255 init_msc_irqs (MSC01E_INT_BASE, MSC01C_INT_BASE, 255 init_msc_irqs(MSC01E_INT_BASE, MSC01C_INT_BASE,
256 msc_irqmap, msc_nr_irqs); 256 msc_irqmap, msc_nr_irqs);
257 } 257 }
258 258
259 if (cpu_has_veic) { 259 if (cpu_has_veic) {
260 set_vi_handler (MSC01E_INT_ATLAS, atlas_hw0_irqdispatch); 260 set_vi_handler(MSC01E_INT_ATLAS, atlas_hw0_irqdispatch);
261 setup_irq (MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq); 261 setup_irq(MSC01E_INT_BASE + MSC01E_INT_ATLAS, &atlasirq);
262 } else if (cpu_has_vint) { 262 } else if (cpu_has_vint) {
263 set_vi_handler (MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch); 263 set_vi_handler(MIPSCPU_INT_ATLAS, atlas_hw0_irqdispatch);
264#ifdef CONFIG_MIPS_MT_SMTC 264#ifdef CONFIG_MIPS_MT_SMTC
265 setup_irq_smtc (MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, 265 setup_irq_smtc(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS,
266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS)); 266 &atlasirq, (0x100 << MIPSCPU_INT_ATLAS));
267#else /* Not SMTC */ 267#else /* Not SMTC */
268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq); 268 setup_irq(MIPS_CPU_IRQ_BASE + MIPSCPU_INT_ATLAS, &atlasirq);
269#endif /* CONFIG_MIPS_MT_SMTC */ 269#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/atlas/atlas_setup.c b/arch/mips/mips-boards/atlas/atlas_setup.c
index c68358a476dd..e405d112a067 100644
--- a/arch/mips/mips-boards/atlas/atlas_setup.c
+++ b/arch/mips/mips-boards/atlas/atlas_setup.c
@@ -35,8 +35,6 @@
35#include <asm/traps.h> 35#include <asm/traps.h>
36 36
37extern void mips_reboot_setup(void); 37extern void mips_reboot_setup(void);
38extern void mips_time_init(void);
39extern unsigned long mips_rtc_get_time(void);
40 38
41#ifdef CONFIG_KGDB 39#ifdef CONFIG_KGDB
42extern void kgdb_config(void); 40extern void kgdb_config(void);
@@ -57,15 +55,12 @@ void __init plat_mem_setup(void)
57 55
58 ioport_resource.end = 0x7fffffff; 56 ioport_resource.end = 0x7fffffff;
59 57
60 serial_init (); 58 serial_init();
61 59
62#ifdef CONFIG_KGDB 60#ifdef CONFIG_KGDB
63 kgdb_config(); 61 kgdb_config();
64#endif 62#endif
65 mips_reboot_setup(); 63 mips_reboot_setup();
66
67 board_time_init = mips_time_init;
68 rtc_mips_get_time = mips_rtc_get_time;
69} 64}
70 65
71static void __init serial_init(void) 66static void __init serial_init(void)
diff --git a/arch/mips/mips-boards/generic/init.c b/arch/mips/mips-boards/generic/init.c
index e2c7147fedf7..30f1f54cb68b 100644
--- a/arch/mips/mips-boards/generic/init.c
+++ b/arch/mips/mips-boards/generic/init.c
@@ -166,15 +166,15 @@ static void __init console_config(void)
166 bits = '8'; 166 bits = '8';
167 if (flow == '\0') 167 if (flow == '\0')
168 flow = 'r'; 168 flow = 'r';
169 sprintf (console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow); 169 sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, parity, bits, flow);
170 strcat (prom_getcmdline(), console_string); 170 strcat(prom_getcmdline(), console_string);
171 pr_info("Config serial console:%s\n", console_string); 171 pr_info("Config serial console:%s\n", console_string);
172 } 172 }
173} 173}
174#endif 174#endif
175 175
176#ifdef CONFIG_KGDB 176#ifdef CONFIG_KGDB
177void __init kgdb_config (void) 177void __init kgdb_config(void)
178{ 178{
179 extern int (*generic_putDebugChar)(char); 179 extern int (*generic_putDebugChar)(char);
180 extern char (*generic_getDebugChar)(void); 180 extern char (*generic_getDebugChar)(void);
@@ -218,7 +218,7 @@ void __init kgdb_config (void)
218 { 218 {
219 char *s; 219 char *s;
220 for (s = "Please connect GDB to this port\r\n"; *s; ) 220 for (s = "Please connect GDB to this port\r\n"; *s; )
221 generic_putDebugChar (*s++); 221 generic_putDebugChar(*s++);
222 } 222 }
223 223
224 /* Breakpoint is invoked after interrupts are initialised */ 224 /* Breakpoint is invoked after interrupts are initialised */
@@ -226,7 +226,7 @@ void __init kgdb_config (void)
226} 226}
227#endif 227#endif
228 228
229void __init mips_nmi_setup (void) 229void __init mips_nmi_setup(void)
230{ 230{
231 void *base; 231 void *base;
232 extern char except_vec_nmi; 232 extern char except_vec_nmi;
@@ -238,7 +238,7 @@ void __init mips_nmi_setup (void)
238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); 238 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80);
239} 239}
240 240
241void __init mips_ejtag_setup (void) 241void __init mips_ejtag_setup(void)
242{ 242{
243 void *base; 243 void *base;
244 extern char except_vec_ejtag_debug; 244 extern char except_vec_ejtag_debug;
diff --git a/arch/mips/mips-boards/generic/memory.c b/arch/mips/mips-boards/generic/memory.c
index ae39953da2c4..dc272c188233 100644
--- a/arch/mips/mips-boards/generic/memory.c
+++ b/arch/mips/mips-boards/generic/memory.c
@@ -125,7 +125,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
125 return &mdesc[0]; 125 return &mdesc[0];
126} 126}
127 127
128static int __init prom_memtype_classify (unsigned int type) 128static int __init prom_memtype_classify(unsigned int type)
129{ 129{
130 switch (type) { 130 switch (type) {
131 case yamon_free: 131 case yamon_free:
@@ -158,7 +158,7 @@ void __init prom_meminit(void)
158 long type; 158 long type;
159 unsigned long base, size; 159 unsigned long base, size;
160 160
161 type = prom_memtype_classify (p->type); 161 type = prom_memtype_classify(p->type);
162 base = p->base; 162 base = p->base;
163 size = p->size; 163 size = p->size;
164 164
diff --git a/arch/mips/mips-boards/generic/pci.c b/arch/mips/mips-boards/generic/pci.c
index c9852206890a..b9743190609a 100644
--- a/arch/mips/mips-boards/generic/pci.c
+++ b/arch/mips/mips-boards/generic/pci.c
@@ -239,5 +239,5 @@ void __init mips_pcibios_init(void)
239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */ 239 iomem_resource.end &= 0xfffffffffULL; /* 64 GB */
240 ioport_resource.end = controller->io_resource->end; 240 ioport_resource.end = controller->io_resource->end;
241 241
242 register_pci_controller (controller); 242 register_pci_controller(controller);
243} 243}
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index d7bff9ca5356..1d00b778ff1e 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -31,6 +31,7 @@
31#include <asm/mipsregs.h> 31#include <asm/mipsregs.h>
32#include <asm/mipsmtregs.h> 32#include <asm/mipsmtregs.h>
33#include <asm/hardirq.h> 33#include <asm/hardirq.h>
34#include <asm/i8253.h>
34#include <asm/irq.h> 35#include <asm/irq.h>
35#include <asm/div64.h> 36#include <asm/div64.h>
36#include <asm/cpu.h> 37#include <asm/cpu.h>
@@ -55,7 +56,6 @@ unsigned long cpu_khz;
55 56
56static int mips_cpu_timer_irq; 57static int mips_cpu_timer_irq;
57extern int cp0_perfcount_irq; 58extern int cp0_perfcount_irq;
58extern void smtc_timer_broadcast(void);
59 59
60static void mips_timer_dispatch(void) 60static void mips_timer_dispatch(void)
61{ 61{
@@ -68,108 +68,6 @@ static void mips_perf_dispatch(void)
68} 68}
69 69
70/* 70/*
71 * Redeclare until I get around mopping the timer code insanity on MIPS.
72 */
73extern int null_perf_irq(void);
74
75extern int (*perf_irq)(void);
76
77/*
78 * Possibly handle a performance counter interrupt.
79 * Return true if the timer interrupt should not be checked
80 */
81static inline int handle_perf_irq (int r2)
82{
83 /*
84 * The performance counter overflow interrupt may be shared with the
85 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
86 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
87 * and we can't reliably determine if a counter interrupt has also
88 * happened (!r2) then don't check for a timer interrupt.
89 */
90 return (cp0_perfcount_irq < 0) &&
91 perf_irq() == IRQ_HANDLED &&
92 !r2;
93}
94
95irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
96{
97 int cpu = smp_processor_id();
98
99#ifdef CONFIG_MIPS_MT_SMTC
100 /*
101 * In an SMTC system, one Count/Compare set exists per VPE.
102 * Which TC within a VPE gets the interrupt is essentially
103 * random - we only know that it shouldn't be one with
104 * IXMT set. Whichever TC gets the interrupt needs to
105 * send special interprocessor interrupts to the other
106 * TCs to make sure that they schedule, etc.
107 *
108 * That code is specific to the SMTC kernel, not to
109 * the a particular platform, so it's invoked from
110 * the general MIPS timer_interrupt routine.
111 */
112
113 /*
114 * We could be here due to timer interrupt,
115 * perf counter overflow, or both.
116 */
117 (void) handle_perf_irq(1);
118
119 if (read_c0_cause() & (1 << 30)) {
120 /*
121 * There are things we only want to do once per tick
122 * in an "MP" system. One TC of each VPE will take
123 * the actual timer interrupt. The others will get
124 * timer broadcast IPIs. We use whoever it is that takes
125 * the tick on VPE 0 to run the full timer_interrupt().
126 */
127 if (cpu_data[cpu].vpe_id == 0) {
128 timer_interrupt(irq, NULL);
129 } else {
130 write_c0_compare(read_c0_count() +
131 (mips_hpt_frequency/HZ));
132 local_timer_interrupt(irq, dev_id);
133 }
134 smtc_timer_broadcast();
135 }
136#else /* CONFIG_MIPS_MT_SMTC */
137 int r2 = cpu_has_mips_r2;
138
139 if (handle_perf_irq(r2))
140 goto out;
141
142 if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
143 goto out;
144
145 if (cpu == 0) {
146 /*
147 * CPU 0 handles the global timer interrupt job and process
148 * accounting resets count/compare registers to trigger next
149 * timer int.
150 */
151 timer_interrupt(irq, NULL);
152 } else {
153 /* Everyone else needs to reset the timer int here as
154 ll_local_timer_interrupt doesn't */
155 /*
156 * FIXME: need to cope with counter underflow.
157 * More support needs to be added to kernel/time for
158 * counter/timer interrupts on multiple CPU's
159 */
160 write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
161
162 /*
163 * Other CPUs should do profiling and process accounting
164 */
165 local_timer_interrupt(irq, dev_id);
166 }
167out:
168#endif /* CONFIG_MIPS_MT_SMTC */
169 return IRQ_HANDLED;
170}
171
172/*
173 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 71 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
174 */ 72 */
175static unsigned int __init estimate_cpu_frequency(void) 73static unsigned int __init estimate_cpu_frequency(void)
@@ -224,19 +122,19 @@ static unsigned int __init estimate_cpu_frequency(void)
224 return count; 122 return count;
225} 123}
226 124
227unsigned long __init mips_rtc_get_time(void) 125unsigned long read_persistent_clock(void)
228{ 126{
229 return mc146818_get_cmos_time(); 127 return mc146818_get_cmos_time();
230} 128}
231 129
232void __init mips_time_init(void) 130void __init plat_time_init(void)
233{ 131{
234 unsigned int est_freq; 132 unsigned int est_freq;
235 133
236 /* Set Data mode - binary. */ 134 /* Set Data mode - binary. */
237 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 135 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
238 136
239 est_freq = estimate_cpu_frequency (); 137 est_freq = estimate_cpu_frequency();
240 138
241 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000, 139 printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
242 (est_freq%1000000)*100/1000000); 140 (est_freq%1000000)*100/1000000);
@@ -244,38 +142,37 @@ void __init mips_time_init(void)
244 cpu_khz = est_freq / 1000; 142 cpu_khz = est_freq / 1000;
245 143
246 mips_scroll_message(); 144 mips_scroll_message();
145#ifdef CONFIG_I8253 /* Only Malta has a PIT */
146 setup_pit_timer();
147#endif
247} 148}
248 149
249irqreturn_t mips_perf_interrupt(int irq, void *dev_id) 150//static irqreturn_t mips_perf_interrupt(int irq, void *dev_id)
250{ 151//{
251 return perf_irq(); 152// return perf_irq();
252} 153//}
253 154
254static struct irqaction perf_irqaction = { 155//static struct irqaction perf_irqaction = {
255 .handler = mips_perf_interrupt, 156// .handler = mips_perf_interrupt,
256 .flags = IRQF_DISABLED | IRQF_PERCPU, 157// .flags = IRQF_DISABLED | IRQF_PERCPU,
257 .name = "performance", 158// .name = "performance",
258}; 159//};
259 160
260void __init plat_perf_setup(struct irqaction *irq) 161void __init plat_perf_setup(void)
261{ 162{
163// struct irqaction *irq = &perf_irqaction;
164
262 cp0_perfcount_irq = -1; 165 cp0_perfcount_irq = -1;
263 166
264#ifdef MSC01E_INT_BASE 167#ifdef MSC01E_INT_BASE
265 if (cpu_has_veic) { 168 if (cpu_has_veic) {
266 set_vi_handler (MSC01E_INT_PERFCTR, mips_perf_dispatch); 169 set_vi_handler(MSC01E_INT_PERFCTR, mips_perf_dispatch);
267 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR; 170 cp0_perfcount_irq = MSC01E_INT_BASE + MSC01E_INT_PERFCTR;
268 } else 171 } else
269#endif 172#endif
270 if (cp0_perfcount_irq >= 0) { 173 if (cp0_perfcount_irq >= 0) {
271 if (cpu_has_vint) 174 if (cpu_has_vint)
272 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch); 175 set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
273#ifdef CONFIG_MIPS_MT_SMTC
274 setup_irq_smtc(cp0_perfcount_irq, irq,
275 0x100 << cp0_perfcount_irq);
276#else
277 setup_irq(cp0_perfcount_irq, irq);
278#endif /* CONFIG_MIPS_MT_SMTC */
279#ifdef CONFIG_SMP 176#ifdef CONFIG_SMP
280 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq); 177 set_irq_handler(cp0_perfcount_irq, handle_percpu_irq);
281#endif 178#endif
@@ -286,7 +183,7 @@ void __init plat_timer_setup(struct irqaction *irq)
286{ 183{
287#ifdef MSC01E_INT_BASE 184#ifdef MSC01E_INT_BASE
288 if (cpu_has_veic) { 185 if (cpu_has_veic) {
289 set_vi_handler (MSC01E_INT_CPUCTR, mips_timer_dispatch); 186 set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
290 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR; 187 mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
291 } 188 }
292 else 189 else
@@ -297,8 +194,6 @@ void __init plat_timer_setup(struct irqaction *irq)
297 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; 194 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
298 } 195 }
299 196
300 /* we are using the cpu counter for timer interrupts */
301 irq->handler = mips_timer_interrupt; /* we use our own handler */
302#ifdef CONFIG_MIPS_MT_SMTC 197#ifdef CONFIG_MIPS_MT_SMTC
303 setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq); 198 setup_irq_smtc(mips_cpu_timer_irq, irq, 0x100 << cp0_compare_irq);
304#else 199#else
@@ -308,5 +203,5 @@ void __init plat_timer_setup(struct irqaction *irq)
308 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); 203 set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
309#endif 204#endif
310 205
311 plat_perf_setup(&perf_irqaction); 206 plat_perf_setup();
312} 207}
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index b73f21823c5e..f010261b75d8 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -124,7 +124,7 @@ static void corehi_irqdispatch(void)
124{ 124{
125 unsigned int intedge, intsteer, pcicmd, pcibadaddr; 125 unsigned int intedge, intsteer, pcicmd, pcibadaddr;
126 unsigned int pcimstat, intisr, inten, intpol; 126 unsigned int pcimstat, intisr, inten, intpol;
127 unsigned int intrcause,datalo,datahi; 127 unsigned int intrcause, datalo, datahi;
128 struct pt_regs *regs = get_irq_regs(); 128 struct pt_regs *regs = get_irq_regs();
129 129
130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n"); 130 printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
@@ -178,7 +178,7 @@ static void corehi_irqdispatch(void)
178 178
179static inline int clz(unsigned long x) 179static inline int clz(unsigned long x)
180{ 180{
181 __asm__ ( 181 __asm__(
182 " .set push \n" 182 " .set push \n"
183 " .set mips32 \n" 183 " .set mips32 \n"
184 " clz %0, %1 \n" 184 " clz %0, %1 \n"
@@ -303,32 +303,32 @@ void __init arch_init_irq(void)
303 case MIPS_REVISION_SCON_SOCIT: 303 case MIPS_REVISION_SCON_SOCIT:
304 case MIPS_REVISION_SCON_ROCIT: 304 case MIPS_REVISION_SCON_ROCIT:
305 if (cpu_has_veic) 305 if (cpu_has_veic)
306 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 306 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
307 else 307 else
308 init_msc_irqs (MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 308 init_msc_irqs(MIPS_MSC01_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
309 break; 309 break;
310 310
311 case MIPS_REVISION_SCON_SOCITSC: 311 case MIPS_REVISION_SCON_SOCITSC:
312 case MIPS_REVISION_SCON_SOCITSCP: 312 case MIPS_REVISION_SCON_SOCITSCP:
313 if (cpu_has_veic) 313 if (cpu_has_veic)
314 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs); 314 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01E_INT_BASE, msc_eicirqmap, msc_nr_eicirqs);
315 else 315 else
316 init_msc_irqs (MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs); 316 init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE, MSC01C_INT_BASE, msc_irqmap, msc_nr_irqs);
317 } 317 }
318 318
319 if (cpu_has_veic) { 319 if (cpu_has_veic) {
320 set_vi_handler (MSC01E_INT_I8259A, malta_hw0_irqdispatch); 320 set_vi_handler(MSC01E_INT_I8259A, malta_hw0_irqdispatch);
321 set_vi_handler (MSC01E_INT_COREHI, corehi_irqdispatch); 321 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
322 setup_irq (MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq); 322 setup_irq(MSC01E_INT_BASE+MSC01E_INT_I8259A, &i8259irq);
323 setup_irq (MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction); 323 setup_irq(MSC01E_INT_BASE+MSC01E_INT_COREHI, &corehi_irqaction);
324 } 324 }
325 else if (cpu_has_vint) { 325 else if (cpu_has_vint) {
326 set_vi_handler (MIPSCPU_INT_I8259A, malta_hw0_irqdispatch); 326 set_vi_handler(MIPSCPU_INT_I8259A, malta_hw0_irqdispatch);
327 set_vi_handler (MIPSCPU_INT_COREHI, corehi_irqdispatch); 327 set_vi_handler(MIPSCPU_INT_COREHI, corehi_irqdispatch);
328#ifdef CONFIG_MIPS_MT_SMTC 328#ifdef CONFIG_MIPS_MT_SMTC
329 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq, 329 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq,
330 (0x100 << MIPSCPU_INT_I8259A)); 330 (0x100 << MIPSCPU_INT_I8259A));
331 setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, 331 setup_irq_smtc(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI)); 332 &corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
333 /* 333 /*
334 * Temporary hack to ensure that the subsidiary device 334 * Temporary hack to ensure that the subsidiary device
@@ -343,12 +343,12 @@ void __init arch_init_irq(void)
343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A); 343 irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
344 } 344 }
345#else /* Not SMTC */ 345#else /* Not SMTC */
346 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 346 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
347 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 347 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
348#endif /* CONFIG_MIPS_MT_SMTC */ 348#endif /* CONFIG_MIPS_MT_SMTC */
349 } 349 }
350 else { 350 else {
351 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq); 351 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
352 setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction); 352 setup_irq(MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
353 } 353 }
354} 354}
diff --git a/arch/mips/mips-boards/malta/malta_setup.c b/arch/mips/mips-boards/malta/malta_setup.c
index 8f1b78dfd89f..9a2636e56243 100644
--- a/arch/mips/mips-boards/malta/malta_setup.c
+++ b/arch/mips/mips-boards/malta/malta_setup.c
@@ -36,7 +36,6 @@
36#endif 36#endif
37 37
38extern void mips_reboot_setup(void); 38extern void mips_reboot_setup(void);
39extern void mips_time_init(void);
40extern unsigned long mips_rtc_get_time(void); 39extern unsigned long mips_rtc_get_time(void);
41 40
42#ifdef CONFIG_KGDB 41#ifdef CONFIG_KGDB
@@ -100,7 +99,7 @@ void __init plat_mem_setup(void)
100 enable_dma(4); 99 enable_dma(4);
101 100
102#ifdef CONFIG_KGDB 101#ifdef CONFIG_KGDB
103 kgdb_config (); 102 kgdb_config();
104#endif 103#endif
105 104
106 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { 105 if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) {
@@ -109,7 +108,7 @@ void __init plat_mem_setup(void)
109 argptr = prom_getcmdline(); 108 argptr = prom_getcmdline();
110 if (strstr(argptr, "debug")) { 109 if (strstr(argptr, "debug")) {
111 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE; 110 BONITO_BONGENCFG |= BONITO_BONGENCFG_DEBUGMODE;
112 printk ("Enabled Bonito debug mode\n"); 111 printk("Enabled Bonito debug mode\n");
113 } 112 }
114 else 113 else
115 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE; 114 BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
@@ -160,14 +159,14 @@ void __init plat_mem_setup(void)
160 if (pciclock != 33 && !strstr (argptr, "idebus=")) { 159 if (pciclock != 33 && !strstr (argptr, "idebus=")) {
161 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock); 160 printk("WARNING: PCI clock is %dMHz, setting idebus\n", pciclock);
162 argptr += strlen(argptr); 161 argptr += strlen(argptr);
163 sprintf (argptr, " idebus=%d", pciclock); 162 sprintf(argptr, " idebus=%d", pciclock);
164 if (pciclock < 20 || pciclock > 66) 163 if (pciclock < 20 || pciclock > 66)
165 printk ("WARNING: IDE timing calculations will be incorrect\n"); 164 printk("WARNING: IDE timing calculations will be incorrect\n");
166 } 165 }
167 } 166 }
168#endif 167#endif
169#ifdef CONFIG_BLK_DEV_FD 168#ifdef CONFIG_BLK_DEV_FD
170 fd_activate (); 169 fd_activate();
171#endif 170#endif
172#ifdef CONFIG_VT 171#ifdef CONFIG_VT
173#if defined(CONFIG_VGA_CONSOLE) 172#if defined(CONFIG_VGA_CONSOLE)
@@ -177,7 +176,7 @@ void __init plat_mem_setup(void)
177 0, /* orig-video-page */ 176 0, /* orig-video-page */
178 0, /* orig-video-mode */ 177 0, /* orig-video-mode */
179 80, /* orig-video-cols */ 178 80, /* orig-video-cols */
180 0,0,0, /* ega_ax, ega_bx, ega_cx */ 179 0, 0, 0, /* ega_ax, ega_bx, ega_cx */
181 25, /* orig-video-lines */ 180 25, /* orig-video-lines */
182 VIDEO_TYPE_VGAC, /* orig-video-isVGA */ 181 VIDEO_TYPE_VGAC, /* orig-video-isVGA */
183 16 /* orig-video-points */ 182 16 /* orig-video-points */
@@ -185,7 +184,4 @@ void __init plat_mem_setup(void)
185#endif 184#endif
186#endif 185#endif
187 mips_reboot_setup(); 186 mips_reboot_setup();
188
189 board_time_init = mips_time_init;
190 rtc_mips_get_time = mips_rtc_get_time;
191} 187}
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index ae05d058cb37..5c980f4a48fe 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -88,3 +88,53 @@ void __cpuinit prom_smp_finish(void)
88void prom_cpus_done(void) 88void prom_cpus_done(void)
89{ 89{
90} 90}
91
92#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
93/*
94 * IRQ affinity hook
95 */
96
97
98void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity)
99{
100 cpumask_t tmask = affinity;
101 int cpu = 0;
102 void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff);
103
104 /*
105 * On the legacy Malta development board, all I/O interrupts
106 * are routed through the 8259 and combined in a single signal
107 * to the CPU daughterboard, and on the CoreFPGA2/3 34K models,
108 * that signal is brought to IP2 of both VPEs. To avoid racing
109 * concurrent interrupt service events, IP2 is enabled only on
110 * one VPE, by convention VPE0. So long as no bits are ever
111 * cleared in the affinity mask, there will never be any
112 * interrupt forwarding. But as soon as a program or operator
113 * sets affinity for one of the related IRQs, we need to make
114 * sure that we don't ever try to forward across the VPE boundry,
115 * at least not until we engineer a system where the interrupt
116 * _ack() or _end() function can somehow know that it corresponds
117 * to an interrupt taken on another VPE, and perform the appropriate
118 * restoration of Status.IM state using MFTR/MTTR instead of the
119 * normal local behavior. We also ensure that no attempt will
120 * be made to forward to an offline "CPU".
121 */
122
123 for_each_cpu_mask(cpu, affinity) {
124 if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu))
125 cpu_clear(cpu, tmask);
126 }
127 irq_desc[irq].affinity = tmask;
128
129 if (cpus_empty(tmask))
130 /*
131 * We could restore a default mask here, but the
132 * runtime code can anyway deal with the null set
133 */
134 printk(KERN_WARNING
135 "IRQ affinity leaves no legal CPU for IRQ %d\n", irq);
136
137 /* Do any generic SMTC IRQ affinity setup */
138 smtc_set_irq_affinity(irq, tmask);
139}
140#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9ca0f82f1360..ec6dd194c14a 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -31,7 +31,7 @@
31 31
32static inline int clz(unsigned long x) 32static inline int clz(unsigned long x)
33{ 33{
34 __asm__ ( 34 __asm__(
35 " .set push \n" 35 " .set push \n"
36 " .set mips32 \n" 36 " .set mips32 \n"
37 " clz %0, %1 \n" 37 " clz %0, %1 \n"
diff --git a/arch/mips/mips-boards/sead/sead_setup.c b/arch/mips/mips-boards/sead/sead_setup.c
index 5f70eaf01fab..1fb61b852304 100644
--- a/arch/mips/mips-boards/sead/sead_setup.c
+++ b/arch/mips/mips-boards/sead/sead_setup.c
@@ -35,7 +35,6 @@
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37extern void mips_reboot_setup(void); 37extern void mips_reboot_setup(void);
38extern void mips_time_init(void);
39 38
40static void __init serial_init(void); 39static void __init serial_init(void);
41 40
@@ -50,9 +49,7 @@ void __init plat_mem_setup(void)
50{ 49{
51 ioport_resource.end = 0x7fffffff; 50 ioport_resource.end = 0x7fffffff;
52 51
53 serial_init (); 52 serial_init();
54
55 board_time_init = mips_time_init;
56 53
57 mips_reboot_setup(); 54 mips_reboot_setup();
58} 55}
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
index 5cbc3509ab52..46067ad542dc 100644
--- a/arch/mips/mipssim/sim_int.c
+++ b/arch/mips/mipssim/sim_int.c
@@ -25,7 +25,7 @@
25 25
26static inline int clz(unsigned long x) 26static inline int clz(unsigned long x)
27{ 27{
28 __asm__ ( 28 __asm__(
29 " .set push \n" 29 " .set push \n"
30 " .set mips32 \n" 30 " .set mips32 \n"
31 " clz %0, %1 \n" 31 " clz %0, %1 \n"
diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
index 2312483eb838..953d836a7713 100644
--- a/arch/mips/mipssim/sim_mem.c
+++ b/arch/mips/mipssim/sim_mem.c
@@ -69,7 +69,7 @@ struct prom_pmemblock * __init prom_getmdesc(void)
69 return &mdesc[0]; 69 return &mdesc[0];
70} 70}
71 71
72static int __init prom_memtype_classify (unsigned int type) 72static int __init prom_memtype_classify(unsigned int type)
73{ 73{
74 switch (type) { 74 switch (type) {
75 case simmem_free: 75 case simmem_free:
@@ -90,7 +90,7 @@ void __init prom_meminit(void)
90 long type; 90 long type;
91 unsigned long base, size; 91 unsigned long base, size;
92 92
93 type = prom_memtype_classify (p->type); 93 type = prom_memtype_classify(p->type);
94 base = p->base; 94 base = p->base;
95 size = p->size; 95 size = p->size;
96 96
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
index d012719c4d24..452c129d02c1 100644
--- a/arch/mips/mipssim/sim_setup.c
+++ b/arch/mips/mipssim/sim_setup.c
@@ -36,7 +36,6 @@
36#include <asm/mips-boards/simint.h> 36#include <asm/mips-boards/simint.h>
37 37
38 38
39extern void sim_time_init(void);
40static void __init serial_init(void); 39static void __init serial_init(void);
41unsigned int _isbonito = 0; 40unsigned int _isbonito = 0;
42 41
@@ -54,7 +53,6 @@ void __init plat_mem_setup(void)
54 53
55 serial_init(); 54 serial_init();
56 55
57 board_time_init = sim_time_init;
58 pr_info("Linux started...\n"); 56 pr_info("Linux started...\n");
59 57
60#ifdef CONFIG_MIPS_MT_SMP 58#ifdef CONFIG_MIPS_MT_SMP
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
index a0f5a5dca1b2..e7fa0d1078a3 100644
--- a/arch/mips/mipssim/sim_time.c
+++ b/arch/mips/mipssim/sim_time.c
@@ -23,77 +23,6 @@
23 23
24unsigned long cpu_khz; 24unsigned long cpu_khz;
25 25
26irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
27{
28#ifdef CONFIG_SMP
29 int cpu = smp_processor_id();
30
31 /*
32 * CPU 0 handles the global timer interrupt job
33 * resets count/compare registers to trigger next timer int.
34 */
35#ifndef CONFIG_MIPS_MT_SMTC
36 if (cpu == 0) {
37 timer_interrupt(irq, dev_id);
38 } else {
39 /* Everyone else needs to reset the timer int here as
40 ll_local_timer_interrupt doesn't */
41 /*
42 * FIXME: need to cope with counter underflow.
43 * More support needs to be added to kernel/time for
44 * counter/timer interrupts on multiple CPU's
45 */
46 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
47 }
48#else /* SMTC */
49 /*
50 * In SMTC system, one Count/Compare set exists per VPE.
51 * Which TC within a VPE gets the interrupt is essentially
52 * random - we only know that it shouldn't be one with
53 * IXMT set. Whichever TC gets the interrupt needs to
54 * send special interprocessor interrupts to the other
55 * TCs to make sure that they schedule, etc.
56 *
57 * That code is specific to the SMTC kernel, not to
58 * the simulation platform, so it's invoked from
59 * the general MIPS timer_interrupt routine.
60 *
61 * We have a problem in that the interrupt vector code
62 * had to turn off the timer IM bit to avoid redundant
63 * entries, but we may never get to mips_cpu_irq_end
64 * to turn it back on again if the scheduler gets
65 * involved. So we clear the pending timer here,
66 * and re-enable the mask...
67 */
68
69 int vpflags = dvpe();
70 write_c0_compare (read_c0_count() - 1);
71 clear_c0_cause(0x100 << cp0_compare_irq);
72 set_c0_status(0x100 << cp0_compare_irq);
73 irq_enable_hazard();
74 evpe(vpflags);
75
76 if (cpu_data[cpu].vpe_id == 0)
77 timer_interrupt(irq, dev_id);
78 else
79 write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
80 smtc_timer_broadcast(cpu_data[cpu].vpe_id);
81
82#endif /* CONFIG_MIPS_MT_SMTC */
83
84 /*
85 * every CPU should do profiling and process accounting
86 */
87 local_timer_interrupt (irq, dev_id);
88
89 return IRQ_HANDLED;
90#else
91 return timer_interrupt (irq, dev_id);
92#endif
93}
94
95
96
97/* 26/*
98 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect 27 * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect
99 */ 28 */
@@ -146,7 +75,7 @@ static unsigned int __init estimate_cpu_frequency(void)
146 return count; 75 return count;
147} 76}
148 77
149void __init sim_time_init(void) 78void __init plat_time_init(void)
150{ 79{
151 unsigned int est_freq, flags; 80 unsigned int est_freq, flags;
152 81
@@ -155,7 +84,7 @@ void __init sim_time_init(void)
155 /* Set Data mode - binary. */ 84 /* Set Data mode - binary. */
156 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL); 85 CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
157 86
158 est_freq = estimate_cpu_frequency (); 87 est_freq = estimate_cpu_frequency();
159 88
160 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000, 89 printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
161 (est_freq % 1000000) * 100 / 1000000); 90 (est_freq % 1000000) * 100 / 1000000);
@@ -185,7 +114,6 @@ void __init plat_timer_setup(struct irqaction *irq)
185 } 114 }
186 115
187 /* we are using the cpu counter for timer interrupts */ 116 /* we are using the cpu counter for timer interrupts */
188 irq->handler = sim_timer_interrupt;
189 setup_irq(mips_cpu_timer_irq, irq); 117 setup_irq(mips_cpu_timer_irq, irq);
190 118
191#ifdef CONFIG_SMP 119#ifdef CONFIG_SMP
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 43e4810dcaa8..32fd5db95774 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_CPU_R5432) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
22obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o 22obj-$(CONFIG_CPU_R8000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r8k.o
23obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 23obj-$(CONFIG_CPU_RM7000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
24obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 24obj-$(CONFIG_CPU_RM9000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
25obj-$(CONFIG_CPU_SB1) += c-sb1.o cerr-sb1.o cex-sb1.o pg-sb1.o \ 25obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o pg-sb1.o \
26 tlb-r4k.o 26 tlb-r4k.o
27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o 27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o pg-r4k.o tlb-r3k.o
28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o 28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c
index 59868a1edf66..c55312f6fd3a 100644
--- a/arch/mips/mm/c-r3k.c
+++ b/arch/mips/mm/c-r3k.c
@@ -121,7 +121,7 @@ static void r3k_flush_icache_range(unsigned long start, unsigned long end)
121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 121 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
122 122
123 for (i = 0; i < size; i += 0x080) { 123 for (i = 0; i < size; i += 0x080) {
124 asm ( "sb\t$0, 0x000(%0)\n\t" 124 asm( "sb\t$0, 0x000(%0)\n\t"
125 "sb\t$0, 0x004(%0)\n\t" 125 "sb\t$0, 0x004(%0)\n\t"
126 "sb\t$0, 0x008(%0)\n\t" 126 "sb\t$0, 0x008(%0)\n\t"
127 "sb\t$0, 0x00c(%0)\n\t" 127 "sb\t$0, 0x00c(%0)\n\t"
@@ -178,7 +178,7 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
178 write_c0_status((ST0_ISC|flags)&~ST0_IEC); 178 write_c0_status((ST0_ISC|flags)&~ST0_IEC);
179 179
180 for (i = 0; i < size; i += 0x080) { 180 for (i = 0; i < size; i += 0x080) {
181 asm ( "sb\t$0, 0x000(%0)\n\t" 181 asm( "sb\t$0, 0x000(%0)\n\t"
182 "sb\t$0, 0x004(%0)\n\t" 182 "sb\t$0, 0x004(%0)\n\t"
183 "sb\t$0, 0x008(%0)\n\t" 183 "sb\t$0, 0x008(%0)\n\t"
184 "sb\t$0, 0x00c(%0)\n\t" 184 "sb\t$0, 0x00c(%0)\n\t"
@@ -217,8 +217,8 @@ static void r3k_flush_dcache_range(unsigned long start, unsigned long end)
217 write_c0_status(flags); 217 write_c0_status(flags);
218} 218}
219 219
220static inline unsigned long get_phys_page (unsigned long addr, 220static inline unsigned long get_phys_page(unsigned long addr,
221 struct mm_struct *mm) 221 struct mm_struct *mm)
222{ 222{
223 pgd_t *pgd; 223 pgd_t *pgd;
224 pud_t *pud; 224 pud_t *pud;
@@ -281,13 +281,13 @@ static void r3k_flush_cache_sigtramp(unsigned long addr)
281 write_c0_status(flags&~ST0_IEC); 281 write_c0_status(flags&~ST0_IEC);
282 282
283 /* Fill the TLB to avoid an exception with caches isolated. */ 283 /* Fill the TLB to avoid an exception with caches isolated. */
284 asm ( "lw\t$0, 0x000(%0)\n\t" 284 asm( "lw\t$0, 0x000(%0)\n\t"
285 "lw\t$0, 0x004(%0)\n\t" 285 "lw\t$0, 0x004(%0)\n\t"
286 : : "r" (addr) ); 286 : : "r" (addr) );
287 287
288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC); 288 write_c0_status((ST0_ISC|ST0_SWC|flags)&~ST0_IEC);
289 289
290 asm ( "sb\t$0, 0x000(%0)\n\t" 290 asm( "sb\t$0, 0x000(%0)\n\t"
291 "sb\t$0, 0x004(%0)\n\t" 291 "sb\t$0, 0x004(%0)\n\t"
292 : : "r" (addr) ); 292 : : "r" (addr) );
293 293
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bad571971bf6..971f6c047b8a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -8,7 +8,9 @@
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 */ 9 */
10#include <linux/init.h> 10#include <linux/init.h>
11#include <linux/highmem.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/linkage.h>
12#include <linux/sched.h> 14#include <linux/sched.h>
13#include <linux/mm.h> 15#include <linux/mm.h>
14#include <linux/bitops.h> 16#include <linux/bitops.h>
@@ -162,12 +164,12 @@ static inline void tx49_blast_icache32(void)
162 /* I'm in even chunk. blast odd chunks */ 164 /* I'm in even chunk. blast odd chunks */
163 for (ws = 0; ws < ws_end; ws += ws_inc) 165 for (ws = 0; ws < ws_end; ws += ws_inc)
164 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 166 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
165 cache32_unroll32(addr|ws,Index_Invalidate_I); 167 cache32_unroll32(addr|ws, Index_Invalidate_I);
166 CACHE32_UNROLL32_ALIGN; 168 CACHE32_UNROLL32_ALIGN;
167 /* I'm in odd chunk. blast even chunks */ 169 /* I'm in odd chunk. blast even chunks */
168 for (ws = 0; ws < ws_end; ws += ws_inc) 170 for (ws = 0; ws < ws_end; ws += ws_inc)
169 for (addr = start; addr < end; addr += 0x400 * 2) 171 for (addr = start; addr < end; addr += 0x400 * 2)
170 cache32_unroll32(addr|ws,Index_Invalidate_I); 172 cache32_unroll32(addr|ws, Index_Invalidate_I);
171} 173}
172 174
173static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page) 175static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
@@ -193,12 +195,12 @@ static inline void tx49_blast_icache32_page_indexed(unsigned long page)
193 /* I'm in even chunk. blast odd chunks */ 195 /* I'm in even chunk. blast odd chunks */
194 for (ws = 0; ws < ws_end; ws += ws_inc) 196 for (ws = 0; ws < ws_end; ws += ws_inc)
195 for (addr = start + 0x400; addr < end; addr += 0x400 * 2) 197 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
196 cache32_unroll32(addr|ws,Index_Invalidate_I); 198 cache32_unroll32(addr|ws, Index_Invalidate_I);
197 CACHE32_UNROLL32_ALIGN; 199 CACHE32_UNROLL32_ALIGN;
198 /* I'm in odd chunk. blast even chunks */ 200 /* I'm in odd chunk. blast even chunks */
199 for (ws = 0; ws < ws_end; ws += ws_inc) 201 for (ws = 0; ws < ws_end; ws += ws_inc)
200 for (addr = start; addr < end; addr += 0x400 * 2) 202 for (addr = start; addr < end; addr += 0x400 * 2)
201 cache32_unroll32(addr|ws,Index_Invalidate_I); 203 cache32_unroll32(addr|ws, Index_Invalidate_I);
202} 204}
203 205
204static void (* r4k_blast_icache_page)(unsigned long addr); 206static void (* r4k_blast_icache_page)(unsigned long addr);
@@ -317,23 +319,6 @@ static void __init r4k_blast_scache_setup(void)
317 r4k_blast_scache = blast_scache128; 319 r4k_blast_scache = blast_scache128;
318} 320}
319 321
320/*
321 * This is former mm's flush_cache_all() which really should be
322 * flush_cache_vunmap these days ...
323 */
324static inline void local_r4k_flush_cache_all(void * args)
325{
326 r4k_blast_dcache();
327}
328
329static void r4k_flush_cache_all(void)
330{
331 if (!cpu_has_dc_aliases)
332 return;
333
334 r4k_on_each_cpu(local_r4k_flush_cache_all, NULL, 1, 1);
335}
336
337static inline void local_r4k___flush_cache_all(void * args) 322static inline void local_r4k___flush_cache_all(void * args)
338{ 323{
339#if defined(CONFIG_CPU_LOONGSON2) 324#if defined(CONFIG_CPU_LOONGSON2)
@@ -343,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args)
343 r4k_blast_dcache(); 328 r4k_blast_dcache();
344 r4k_blast_icache(); 329 r4k_blast_icache();
345 330
346 switch (current_cpu_data.cputype) { 331 switch (current_cpu_type()) {
347 case CPU_R4000SC: 332 case CPU_R4000SC:
348 case CPU_R4000MC: 333 case CPU_R4000MC:
349 case CPU_R4400SC: 334 case CPU_R4400SC:
@@ -392,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args)
392 * R4000SC and R4400SC indexed S-cache ops also invalidate primary 377 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
393 * caches, so we can bail out early. 378 * caches, so we can bail out early.
394 */ 379 */
395 if (current_cpu_data.cputype == CPU_R4000SC || 380 if (current_cpu_type() == CPU_R4000SC ||
396 current_cpu_data.cputype == CPU_R4000MC || 381 current_cpu_type() == CPU_R4000MC ||
397 current_cpu_data.cputype == CPU_R4400SC || 382 current_cpu_type() == CPU_R4400SC ||
398 current_cpu_data.cputype == CPU_R4400MC) { 383 current_cpu_type() == CPU_R4400MC) {
399 r4k_blast_scache(); 384 r4k_blast_scache();
400 return; 385 return;
401 } 386 }
@@ -422,13 +407,14 @@ static inline void local_r4k_flush_cache_page(void *args)
422 struct flush_cache_page_args *fcp_args = args; 407 struct flush_cache_page_args *fcp_args = args;
423 struct vm_area_struct *vma = fcp_args->vma; 408 struct vm_area_struct *vma = fcp_args->vma;
424 unsigned long addr = fcp_args->addr; 409 unsigned long addr = fcp_args->addr;
425 unsigned long paddr = fcp_args->pfn << PAGE_SHIFT; 410 struct page *page = pfn_to_page(fcp_args->pfn);
426 int exec = vma->vm_flags & VM_EXEC; 411 int exec = vma->vm_flags & VM_EXEC;
427 struct mm_struct *mm = vma->vm_mm; 412 struct mm_struct *mm = vma->vm_mm;
428 pgd_t *pgdp; 413 pgd_t *pgdp;
429 pud_t *pudp; 414 pud_t *pudp;
430 pmd_t *pmdp; 415 pmd_t *pmdp;
431 pte_t *ptep; 416 pte_t *ptep;
417 void *vaddr;
432 418
433 /* 419 /*
434 * If ownes no valid ASID yet, cannot possibly have gotten 420 * If ownes no valid ASID yet, cannot possibly have gotten
@@ -450,43 +436,40 @@ static inline void local_r4k_flush_cache_page(void *args)
450 if (!(pte_val(*ptep) & _PAGE_PRESENT)) 436 if (!(pte_val(*ptep) & _PAGE_PRESENT))
451 return; 437 return;
452 438
453 /* 439 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
454 * Doing flushes for another ASID than the current one is 440 vaddr = NULL;
455 * too difficult since stupid R4k caches do a TLB translation 441 else {
456 * for every cache flush operation. So we do indexed flushes 442 /*
457 * in that case, which doesn't overly flush the cache too much. 443 * Use kmap_coherent or kmap_atomic to do flushes for
458 */ 444 * another ASID than the current one.
459 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) { 445 */
460 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 446 if (cpu_has_dc_aliases)
461 r4k_blast_dcache_page(addr); 447 vaddr = kmap_coherent(page, addr);
462 if (exec && !cpu_icache_snoops_remote_store) 448 else
463 r4k_blast_scache_page(addr); 449 vaddr = kmap_atomic(page, KM_USER0);
464 } 450 addr = (unsigned long)vaddr;
465 if (exec)
466 r4k_blast_icache_page(addr);
467
468 return;
469 } 451 }
470 452
471 /*
472 * Do indexed flush, too much work to get the (possible) TLB refills
473 * to work correctly.
474 */
475 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) { 453 if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
476 r4k_blast_dcache_page_indexed(cpu_has_pindexed_dcache ? 454 r4k_blast_dcache_page(addr);
477 paddr : addr); 455 if (exec && !cpu_icache_snoops_remote_store)
478 if (exec && !cpu_icache_snoops_remote_store) { 456 r4k_blast_scache_page(addr);
479 r4k_blast_scache_page_indexed(paddr);
480 }
481 } 457 }
482 if (exec) { 458 if (exec) {
483 if (cpu_has_vtag_icache && mm == current->active_mm) { 459 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
484 int cpu = smp_processor_id(); 460 int cpu = smp_processor_id();
485 461
486 if (cpu_context(cpu, mm) != 0) 462 if (cpu_context(cpu, mm) != 0)
487 drop_mmu_context(mm, cpu); 463 drop_mmu_context(mm, cpu);
488 } else 464 } else
489 r4k_blast_icache_page_indexed(addr); 465 r4k_blast_icache_page(addr);
466 }
467
468 if (vaddr) {
469 if (cpu_has_dc_aliases)
470 kunmap_coherent();
471 else
472 kunmap_atomic(vaddr, KM_USER0);
490 } 473 }
491} 474}
492 475
@@ -948,12 +931,16 @@ static void __init probe_pcache(void)
948 switch (c->cputype) { 931 switch (c->cputype) {
949 case CPU_20KC: 932 case CPU_20KC:
950 case CPU_25KF: 933 case CPU_25KF:
934 case CPU_SB1:
935 case CPU_SB1A:
951 c->dcache.flags |= MIPS_CACHE_PINDEX; 936 c->dcache.flags |= MIPS_CACHE_PINDEX;
937 break;
938
952 case CPU_R10000: 939 case CPU_R10000:
953 case CPU_R12000: 940 case CPU_R12000:
954 case CPU_R14000: 941 case CPU_R14000:
955 case CPU_SB1:
956 break; 942 break;
943
957 case CPU_24K: 944 case CPU_24K:
958 case CPU_34K: 945 case CPU_34K:
959 case CPU_74K: 946 case CPU_74K:
@@ -1210,7 +1197,7 @@ static void __init coherency_setup(void)
1210 * this bit and; some wire it to zero, others like Toshiba had the 1197 * this bit and; some wire it to zero, others like Toshiba had the
1211 * silly idea of putting something else there ... 1198 * silly idea of putting something else there ...
1212 */ 1199 */
1213 switch (current_cpu_data.cputype) { 1200 switch (current_cpu_type()) {
1214 case CPU_R4000PC: 1201 case CPU_R4000PC:
1215 case CPU_R4000SC: 1202 case CPU_R4000SC:
1216 case CPU_R4000MC: 1203 case CPU_R4000MC:
@@ -1235,11 +1222,20 @@ void __init r4k_cache_init(void)
1235{ 1222{
1236 extern void build_clear_page(void); 1223 extern void build_clear_page(void);
1237 extern void build_copy_page(void); 1224 extern void build_copy_page(void);
1238 extern char except_vec2_generic; 1225 extern char __weak except_vec2_generic;
1226 extern char __weak except_vec2_sb1;
1239 struct cpuinfo_mips *c = &current_cpu_data; 1227 struct cpuinfo_mips *c = &current_cpu_data;
1240 1228
1241 /* Default cache error handler for R4000 and R5000 family */ 1229 switch (c->cputype) {
1242 set_uncached_handler (0x100, &except_vec2_generic, 0x80); 1230 case CPU_SB1:
1231 case CPU_SB1A:
1232 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1233 break;
1234
1235 default:
1236 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1237 break;
1238 }
1243 1239
1244 probe_pcache(); 1240 probe_pcache();
1245 setup_scache(); 1241 setup_scache();
@@ -1265,7 +1261,7 @@ void __init r4k_cache_init(void)
1265 PAGE_SIZE - 1); 1261 PAGE_SIZE - 1);
1266 else 1262 else
1267 shm_align_mask = PAGE_SIZE-1; 1263 shm_align_mask = PAGE_SIZE-1;
1268 flush_cache_all = r4k_flush_cache_all; 1264 flush_cache_all = cache_noop;
1269 __flush_cache_all = r4k___flush_cache_all; 1265 __flush_cache_all = r4k___flush_cache_all;
1270 flush_cache_mm = r4k_flush_cache_mm; 1266 flush_cache_mm = r4k_flush_cache_mm;
1271 flush_cache_page = r4k_flush_cache_page; 1267 flush_cache_page = r4k_flush_cache_page;
diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c
deleted file mode 100644
index 85ce2842d0da..000000000000
--- a/arch/mips/mm/c-sb1.c
+++ /dev/null
@@ -1,535 +0,0 @@
1/*
2 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
3 * Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
4 * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
5 * Copyright (C) 2004 Maciej W. Rozycki
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21#include <linux/init.h>
22#include <linux/hardirq.h>
23
24#include <asm/asm.h>
25#include <asm/bootinfo.h>
26#include <asm/cacheops.h>
27#include <asm/cpu.h>
28#include <asm/mipsregs.h>
29#include <asm/mmu_context.h>
30#include <asm/uaccess.h>
31
32extern void sb1_dma_init(void);
33
34/* These are probed at ld_mmu time */
35static unsigned long icache_size;
36static unsigned long dcache_size;
37
38static unsigned short icache_line_size;
39static unsigned short dcache_line_size;
40
41static unsigned int icache_index_mask;
42static unsigned int dcache_index_mask;
43
44static unsigned short icache_assoc;
45static unsigned short dcache_assoc;
46
47static unsigned short icache_sets;
48static unsigned short dcache_sets;
49
50static unsigned int icache_range_cutoff;
51static unsigned int dcache_range_cutoff;
52
53static inline void sb1_on_each_cpu(void (*func) (void *info), void *info,
54 int retry, int wait)
55{
56 preempt_disable();
57 smp_call_function(func, info, retry, wait);
58 func(info);
59 preempt_enable();
60}
61
62/*
63 * The dcache is fully coherent to the system, with one
64 * big caveat: the instruction stream. In other words,
65 * if we miss in the icache, and have dirty data in the
66 * L1 dcache, then we'll go out to memory (or the L2) and
67 * get the not-as-recent data.
68 *
69 * So the only time we have to flush the dcache is when
70 * we're flushing the icache. Since the L2 is fully
71 * coherent to everything, including I/O, we never have
72 * to flush it
73 */
74
75#define cache_set_op(op, addr) \
76 __asm__ __volatile__( \
77 " .set noreorder \n" \
78 " .set mips64\n\t \n" \
79 " cache %0, (0<<13)(%1) \n" \
80 " cache %0, (1<<13)(%1) \n" \
81 " cache %0, (2<<13)(%1) \n" \
82 " cache %0, (3<<13)(%1) \n" \
83 " .set mips0 \n" \
84 " .set reorder" \
85 : \
86 : "i" (op), "r" (addr))
87
88#define sync() \
89 __asm__ __volatile( \
90 " .set mips64\n\t \n" \
91 " sync \n" \
92 " .set mips0")
93
94#define mispredict() \
95 __asm__ __volatile__( \
96 " bnezl $0, 1f \n" /* Force mispredict */ \
97 "1: \n");
98
99/*
100 * Writeback and invalidate the entire dcache
101 */
102static inline void __sb1_writeback_inv_dcache_all(void)
103{
104 unsigned long addr = 0;
105
106 while (addr < dcache_line_size * dcache_sets) {
107 cache_set_op(Index_Writeback_Inv_D, addr);
108 addr += dcache_line_size;
109 }
110}
111
112/*
113 * Writeback and invalidate a range of the dcache. The addresses are
114 * virtual, and since we're using index ops and bit 12 is part of both
115 * the virtual frame and physical index, we have to clear both sets
116 * (bit 12 set and cleared).
117 */
118static inline void __sb1_writeback_inv_dcache_range(unsigned long start,
119 unsigned long end)
120{
121 unsigned long index;
122
123 start &= ~(dcache_line_size - 1);
124 end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
125
126 while (start != end) {
127 index = start & dcache_index_mask;
128 cache_set_op(Index_Writeback_Inv_D, index);
129 cache_set_op(Index_Writeback_Inv_D, index ^ (1<<12));
130 start += dcache_line_size;
131 }
132 sync();
133}
134
135/*
136 * Writeback and invalidate a range of the dcache. With physical
137 * addresseses, we don't have to worry about possible bit 12 aliasing.
138 * XXXKW is it worth turning on KX and using hit ops with xkphys?
139 */
140static inline void __sb1_writeback_inv_dcache_phys_range(unsigned long start,
141 unsigned long end)
142{
143 start &= ~(dcache_line_size - 1);
144 end = (end + dcache_line_size - 1) & ~(dcache_line_size - 1);
145
146 while (start != end) {
147 cache_set_op(Index_Writeback_Inv_D, start & dcache_index_mask);
148 start += dcache_line_size;
149 }
150 sync();
151}
152
153
154/*
155 * Invalidate the entire icache
156 */
157static inline void __sb1_flush_icache_all(void)
158{
159 unsigned long addr = 0;
160
161 while (addr < icache_line_size * icache_sets) {
162 cache_set_op(Index_Invalidate_I, addr);
163 addr += icache_line_size;
164 }
165}
166
167/*
168 * Invalidate a range of the icache. The addresses are virtual, and
169 * the cache is virtually indexed and tagged. However, we don't
170 * necessarily have the right ASID context, so use index ops instead
171 * of hit ops.
172 */
173static inline void __sb1_flush_icache_range(unsigned long start,
174 unsigned long end)
175{
176 start &= ~(icache_line_size - 1);
177 end = (end + icache_line_size - 1) & ~(icache_line_size - 1);
178
179 while (start != end) {
180 cache_set_op(Index_Invalidate_I, start & icache_index_mask);
181 start += icache_line_size;
182 }
183 mispredict();
184 sync();
185}
186
187/*
188 * Flush the icache for a given physical page. Need to writeback the
189 * dcache first, then invalidate the icache. If the page isn't
190 * executable, nothing is required.
191 */
192static void local_sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
193{
194 int cpu = smp_processor_id();
195
196#ifndef CONFIG_SMP
197 if (!(vma->vm_flags & VM_EXEC))
198 return;
199#endif
200
201 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
202
203 /*
204 * Bumping the ASID is probably cheaper than the flush ...
205 */
206 if (vma->vm_mm == current->active_mm) {
207 if (cpu_context(cpu, vma->vm_mm) != 0)
208 drop_mmu_context(vma->vm_mm, cpu);
209 } else
210 __sb1_flush_icache_range(addr, addr + PAGE_SIZE);
211}
212
213#ifdef CONFIG_SMP
214struct flush_cache_page_args {
215 struct vm_area_struct *vma;
216 unsigned long addr;
217 unsigned long pfn;
218};
219
220static void sb1_flush_cache_page_ipi(void *info)
221{
222 struct flush_cache_page_args *args = info;
223
224 local_sb1_flush_cache_page(args->vma, args->addr, args->pfn);
225}
226
227/* Dirty dcache could be on another CPU, so do the IPIs */
228static void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
229{
230 struct flush_cache_page_args args;
231
232 if (!(vma->vm_flags & VM_EXEC))
233 return;
234
235 addr &= PAGE_MASK;
236 args.vma = vma;
237 args.addr = addr;
238 args.pfn = pfn;
239 sb1_on_each_cpu(sb1_flush_cache_page_ipi, (void *) &args, 1, 1);
240}
241#else
242void sb1_flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
243 __attribute__((alias("local_sb1_flush_cache_page")));
244#endif
245
246#ifdef CONFIG_SMP
247static void sb1_flush_cache_data_page_ipi(void *info)
248{
249 unsigned long start = (unsigned long)info;
250
251 __sb1_writeback_inv_dcache_range(start, start + PAGE_SIZE);
252}
253
254static void sb1_flush_cache_data_page(unsigned long addr)
255{
256 if (in_atomic())
257 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
258 else
259 on_each_cpu(sb1_flush_cache_data_page_ipi, (void *) addr, 1, 1);
260}
261#else
262
263static void local_sb1_flush_cache_data_page(unsigned long addr)
264{
265 __sb1_writeback_inv_dcache_range(addr, addr + PAGE_SIZE);
266}
267
268void sb1_flush_cache_data_page(unsigned long)
269 __attribute__((alias("local_sb1_flush_cache_data_page")));
270#endif
271
272/*
273 * Invalidate all caches on this CPU
274 */
275static void __used local_sb1___flush_cache_all(void)
276{
277 __sb1_writeback_inv_dcache_all();
278 __sb1_flush_icache_all();
279}
280
281#ifdef CONFIG_SMP
282void sb1___flush_cache_all_ipi(void *ignored)
283 __attribute__((alias("local_sb1___flush_cache_all")));
284
285static void sb1___flush_cache_all(void)
286{
287 sb1_on_each_cpu(sb1___flush_cache_all_ipi, 0, 1, 1);
288}
289#else
290void sb1___flush_cache_all(void)
291 __attribute__((alias("local_sb1___flush_cache_all")));
292#endif
293
294/*
295 * When flushing a range in the icache, we have to first writeback
296 * the dcache for the same range, so new ifetches will see any
297 * data that was dirty in the dcache.
298 *
299 * The start/end arguments are Kseg addresses (possibly mapped Kseg).
300 */
301
302static void local_sb1_flush_icache_range(unsigned long start,
303 unsigned long end)
304{
305 /* Just wb-inv the whole dcache if the range is big enough */
306 if ((end - start) > dcache_range_cutoff)
307 __sb1_writeback_inv_dcache_all();
308 else
309 __sb1_writeback_inv_dcache_range(start, end);
310
311 /* Just flush the whole icache if the range is big enough */
312 if ((end - start) > icache_range_cutoff)
313 __sb1_flush_icache_all();
314 else
315 __sb1_flush_icache_range(start, end);
316}
317
318#ifdef CONFIG_SMP
319struct flush_icache_range_args {
320 unsigned long start;
321 unsigned long end;
322};
323
324static void sb1_flush_icache_range_ipi(void *info)
325{
326 struct flush_icache_range_args *args = info;
327
328 local_sb1_flush_icache_range(args->start, args->end);
329}
330
331void sb1_flush_icache_range(unsigned long start, unsigned long end)
332{
333 struct flush_icache_range_args args;
334
335 args.start = start;
336 args.end = end;
337 sb1_on_each_cpu(sb1_flush_icache_range_ipi, &args, 1, 1);
338}
339#else
340void sb1_flush_icache_range(unsigned long start, unsigned long end)
341 __attribute__((alias("local_sb1_flush_icache_range")));
342#endif
343
344/*
345 * A signal trampoline must fit into a single cacheline.
346 */
347static void local_sb1_flush_cache_sigtramp(unsigned long addr)
348{
349 cache_set_op(Index_Writeback_Inv_D, addr & dcache_index_mask);
350 cache_set_op(Index_Writeback_Inv_D, (addr ^ (1<<12)) & dcache_index_mask);
351 cache_set_op(Index_Invalidate_I, addr & icache_index_mask);
352 mispredict();
353}
354
355#ifdef CONFIG_SMP
356static void sb1_flush_cache_sigtramp_ipi(void *info)
357{
358 unsigned long iaddr = (unsigned long) info;
359 local_sb1_flush_cache_sigtramp(iaddr);
360}
361
362static void sb1_flush_cache_sigtramp(unsigned long addr)
363{
364 sb1_on_each_cpu(sb1_flush_cache_sigtramp_ipi, (void *) addr, 1, 1);
365}
366#else
367void sb1_flush_cache_sigtramp(unsigned long addr)
368 __attribute__((alias("local_sb1_flush_cache_sigtramp")));
369#endif
370
371
372/*
373 * Anything that just flushes dcache state can be ignored, as we're always
374 * coherent in dcache space. This is just a dummy function that all the
375 * nop'ed routines point to
376 */
377static void sb1_nop(void)
378{
379}
380
381/*
382 * Cache set values (from the mips64 spec)
383 * 0 - 64
384 * 1 - 128
385 * 2 - 256
386 * 3 - 512
387 * 4 - 1024
388 * 5 - 2048
389 * 6 - 4096
390 * 7 - Reserved
391 */
392
393static unsigned int decode_cache_sets(unsigned int config_field)
394{
395 if (config_field == 7) {
396 /* JDCXXX - Find a graceful way to abort. */
397 return 0;
398 }
399 return (1<<(config_field + 6));
400}
401
402/*
403 * Cache line size values (from the mips64 spec)
404 * 0 - No cache present.
405 * 1 - 4 bytes
406 * 2 - 8 bytes
407 * 3 - 16 bytes
408 * 4 - 32 bytes
409 * 5 - 64 bytes
410 * 6 - 128 bytes
411 * 7 - Reserved
412 */
413
414static unsigned int decode_cache_line_size(unsigned int config_field)
415{
416 if (config_field == 0) {
417 return 0;
418 } else if (config_field == 7) {
419 /* JDCXXX - Find a graceful way to abort. */
420 return 0;
421 }
422 return (1<<(config_field + 1));
423}
424
425/*
426 * Relevant bits of the config1 register format (from the MIPS32/MIPS64 specs)
427 *
428 * 24:22 Icache sets per way
429 * 21:19 Icache line size
430 * 18:16 Icache Associativity
431 * 15:13 Dcache sets per way
432 * 12:10 Dcache line size
433 * 9:7 Dcache Associativity
434 */
435
436static char *way_string[] = {
437 "direct mapped", "2-way", "3-way", "4-way",
438 "5-way", "6-way", "7-way", "8-way",
439};
440
441static __init void probe_cache_sizes(void)
442{
443 u32 config1;
444
445 config1 = read_c0_config1();
446 icache_line_size = decode_cache_line_size((config1 >> 19) & 0x7);
447 dcache_line_size = decode_cache_line_size((config1 >> 10) & 0x7);
448 icache_sets = decode_cache_sets((config1 >> 22) & 0x7);
449 dcache_sets = decode_cache_sets((config1 >> 13) & 0x7);
450 icache_assoc = ((config1 >> 16) & 0x7) + 1;
451 dcache_assoc = ((config1 >> 7) & 0x7) + 1;
452 icache_size = icache_line_size * icache_sets * icache_assoc;
453 dcache_size = dcache_line_size * dcache_sets * dcache_assoc;
454 /* Need to remove non-index bits for index ops */
455 icache_index_mask = (icache_sets - 1) * icache_line_size;
456 dcache_index_mask = (dcache_sets - 1) * dcache_line_size;
457 /*
458 * These are for choosing range (index ops) versus all.
459 * icache flushes all ways for each set, so drop icache_assoc.
460 * dcache flushes all ways and each setting of bit 12 for each
461 * index, so drop dcache_assoc and halve the dcache_sets.
462 */
463 icache_range_cutoff = icache_sets * icache_line_size;
464 dcache_range_cutoff = (dcache_sets / 2) * icache_line_size;
465
466 printk("Primary instruction cache %ldkB, %s, linesize %d bytes.\n",
467 icache_size >> 10, way_string[icache_assoc - 1],
468 icache_line_size);
469 printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
470 dcache_size >> 10, way_string[dcache_assoc - 1],
471 dcache_line_size);
472}
473
474/*
475 * This is called from cache.c. We have to set up all the
476 * memory management function pointers, as well as initialize
477 * the caches and tlbs
478 */
479void __init sb1_cache_init(void)
480{
481 extern char except_vec2_sb1;
482
483 /* Special cache error handler for SB1 */
484 set_uncached_handler (0x100, &except_vec2_sb1, 0x80);
485
486 probe_cache_sizes();
487
488#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
489 sb1_dma_init();
490#endif
491
492 /*
493 * None of these are needed for the SB1 - the Dcache is
494 * physically indexed and tagged, so no virtual aliasing can
495 * occur
496 */
497 flush_cache_range = (void *) sb1_nop;
498 flush_cache_mm = (void (*)(struct mm_struct *))sb1_nop;
499 flush_cache_all = sb1_nop;
500
501 /* These routines are for Icache coherence with the Dcache */
502 flush_icache_range = sb1_flush_icache_range;
503 flush_icache_all = __sb1_flush_icache_all; /* local only */
504
505 /* This implies an Icache flush too, so can't be nop'ed */
506 flush_cache_page = sb1_flush_cache_page;
507
508 flush_cache_sigtramp = sb1_flush_cache_sigtramp;
509 local_flush_data_cache_page = (void *) sb1_nop;
510 flush_data_cache_page = sb1_flush_cache_data_page;
511
512 /* Full flush */
513 __flush_cache_all = sb1___flush_cache_all;
514
515 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
516
517 /*
518 * This is the only way to force the update of K0 to complete
519 * before subsequent instruction fetch.
520 */
521 __asm__ __volatile__(
522 ".set push \n"
523 " .set noat \n"
524 " .set noreorder \n"
525 " .set mips3 \n"
526 " " STR(PTR_LA) " $1, 1f \n"
527 " " STR(MTC0) " $1, $14 \n"
528 " eret \n"
529 "1: .set pop"
530 :
531 :
532 : "memory");
533
534 local_sb1___flush_cache_all();
535}
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 560a6de96556..9ea121e8cdce 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -69,7 +69,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
69/* TX39H2,TX39H3 */ 69/* TX39H2,TX39H3 */
70static inline void tx39_blast_dcache_page(unsigned long addr) 70static inline void tx39_blast_dcache_page(unsigned long addr)
71{ 71{
72 if (current_cpu_data.cputype != CPU_TX3912) 72 if (current_cpu_type() != CPU_TX3912)
73 blast_dcache16_page(addr); 73 blast_dcache16_page(addr);
74} 74}
75 75
@@ -307,7 +307,7 @@ static __init void tx39_probe_cache(void)
307 TX39_CONF_DCS_SHIFT)); 307 TX39_CONF_DCS_SHIFT));
308 308
309 current_cpu_data.icache.linesz = 16; 309 current_cpu_data.icache.linesz = 16;
310 switch (current_cpu_data.cputype) { 310 switch (current_cpu_type()) {
311 case CPU_TX3912: 311 case CPU_TX3912:
312 current_cpu_data.icache.ways = 1; 312 current_cpu_data.icache.ways = 1;
313 current_cpu_data.dcache.ways = 1; 313 current_cpu_data.dcache.ways = 1;
@@ -341,7 +341,7 @@ void __init tx39_cache_init(void)
341 341
342 tx39_probe_cache(); 342 tx39_probe_cache();
343 343
344 switch (current_cpu_data.cputype) { 344 switch (current_cpu_type()) {
345 case CPU_TX3912: 345 case CPU_TX3912:
346 /* TX39/H core (writethru direct-map cache) */ 346 /* TX39/H core (writethru direct-map cache) */
347 flush_cache_all = tx39h_flush_icache_all; 347 flush_cache_all = tx39h_flush_icache_all;
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 81f925a9a731..43dde874f414 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -3,13 +3,14 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994 - 2003, 07 by Ralf Baechle (ralf@linux-mips.org) 6 * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2007 MIPS Technologies, Inc. 7 * Copyright (C) 2007 MIPS Technologies, Inc.
8 */ 8 */
9#include <linux/fs.h> 9#include <linux/fs.h>
10#include <linux/fcntl.h> 10#include <linux/fcntl.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/linkage.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/sched.h> 15#include <linux/sched.h>
15#include <linux/mm.h> 16#include <linux/mm.h>
@@ -157,12 +158,6 @@ void __init cpu_cache_init(void)
157 tx39_cache_init(); 158 tx39_cache_init();
158 return; 159 return;
159 } 160 }
160 if (cpu_has_sb1_cache) {
161 extern void __weak sb1_cache_init(void);
162
163 sb1_cache_init();
164 return;
165 }
166 161
167 panic(cache_panic); 162 panic(cache_panic);
168} 163}
diff --git a/arch/mips/mm/cerr-sb1.c b/arch/mips/mm/cerr-sb1.c
index 4c72e650f9b6..e7f539e3284b 100644
--- a/arch/mips/mm/cerr-sb1.c
+++ b/arch/mips/mm/cerr-sb1.c
@@ -271,14 +271,22 @@ asmlinkage void sb1_cache_error(void)
271 271
272/* Parity lookup table. */ 272/* Parity lookup table. */
273static const uint8_t parity[256] = { 273static const uint8_t parity[256] = {
274 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 274 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
275 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 275 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
276 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 276 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
277 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 277 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
278 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0, 278 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
279 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 279 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
280 0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1, 280 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
281 1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0 281 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
282 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
283 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
284 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
285 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
286 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0,
287 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
288 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1,
289 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0
282}; 290};
283 291
284/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */ 292/* Masks to select bits for Hamming parity, mask_72_64[i] for bit[i] */
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f60b3dc0fc62..98b5e5bac02e 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -35,8 +35,8 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)
35static inline int cpu_is_noncoherent_r10000(struct device *dev) 35static inline int cpu_is_noncoherent_r10000(struct device *dev)
36{ 36{
37 return !plat_device_is_coherent(dev) && 37 return !plat_device_is_coherent(dev) &&
38 (current_cpu_data.cputype == CPU_R10000 || 38 (current_cpu_type() == CPU_R10000 ||
39 current_cpu_data.cputype == CPU_R12000); 39 current_cpu_type() == CPU_R12000);
40} 40}
41 41
42void *dma_alloc_noncoherent(struct device *dev, size_t size, 42void *dma_alloc_noncoherent(struct device *dev, size_t size,
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index e47e9e9486bf..4f770ac885ce 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -347,13 +347,14 @@ void __init build_clear_page(void)
347{ 347{
348 unsigned int loop_start; 348 unsigned int loop_start;
349 unsigned long off; 349 unsigned long off;
350 int i;
350 351
351 epc = (unsigned int *) &clear_page_array; 352 epc = (unsigned int *) &clear_page_array;
352 instruction_pending = 0; 353 instruction_pending = 0;
353 store_offset = 0; 354 store_offset = 0;
354 355
355 if (cpu_has_prefetch) { 356 if (cpu_has_prefetch) {
356 switch (current_cpu_data.cputype) { 357 switch (current_cpu_type()) {
357 case CPU_TX49XX: 358 case CPU_TX49XX:
358 /* TX49 supports only Pref_Load */ 359 /* TX49 supports only Pref_Load */
359 pref_offset_clear = 0; 360 pref_offset_clear = 0;
@@ -434,12 +435,22 @@ dest = label();
434 build_jr_ra(); 435 build_jr_ra();
435 436
436 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array)); 437 BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
438
439 pr_info("Synthesized clear page handler (%u instructions).\n",
440 (unsigned int)(epc - clear_page_array));
441
442 pr_debug("\t.set push\n");
443 pr_debug("\t.set noreorder\n");
444 for (i = 0; i < (epc - clear_page_array); i++)
445 pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
446 pr_debug("\t.set pop\n");
437} 447}
438 448
439void __init build_copy_page(void) 449void __init build_copy_page(void)
440{ 450{
441 unsigned int loop_start; 451 unsigned int loop_start;
442 unsigned long off; 452 unsigned long off;
453 int i;
443 454
444 epc = (unsigned int *) &copy_page_array; 455 epc = (unsigned int *) &copy_page_array;
445 store_offset = load_offset = 0; 456 store_offset = load_offset = 0;
@@ -515,4 +526,13 @@ dest = label();
515 build_jr_ra(); 526 build_jr_ra();
516 527
517 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array)); 528 BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
529
530 pr_info("Synthesized copy page handler (%u instructions).\n",
531 (unsigned int)(epc - copy_page_array));
532
533 pr_debug("\t.set push\n");
534 pr_debug("\t.set noreorder\n");
535 for (i = 0; i < (epc - copy_page_array); i++)
536 pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
537 pr_debug("\t.set pop\n");
518} 538}
diff --git a/arch/mips/mm/pg-sb1.c b/arch/mips/mm/pg-sb1.c
index adb37d0a30ea..a3e98c243a89 100644
--- a/arch/mips/mm/pg-sb1.c
+++ b/arch/mips/mm/pg-sb1.c
@@ -188,9 +188,9 @@ static inline void copy_page_cpu(void *to, void *from)
188 : "+r" (src), "+r" (dst) 188 : "+r" (src), "+r" (dst)
189 : "r" (end) 189 : "r" (end)
190#ifdef CONFIG_64BIT 190#ifdef CONFIG_64BIT
191 : "$8","$9","$10","$11","memory"); 191 : "$8", "$9", "$10", "$11", "memory");
192#else 192#else
193 : "$2","$3","$6","$7","$8","$9","$10","$11","memory"); 193 : "$2", "$3", "$6", "$7", "$8", "$9", "$10", "$11", "memory");
194#endif 194#endif
195} 195}
196 196
@@ -292,3 +292,11 @@ void copy_page(void *to, void *from)
292 292
293EXPORT_SYMBOL(clear_page); 293EXPORT_SYMBOL(clear_page);
294EXPORT_SYMBOL(copy_page); 294EXPORT_SYMBOL(copy_page);
295
296void __init build_clear_page(void)
297{
298}
299
300void __init build_copy_page(void)
301{
302}
diff --git a/arch/mips/mm/pgtable.c b/arch/mips/mm/pgtable.c
index c93aa6cbcaca..57df1c38e303 100644
--- a/arch/mips/mm/pgtable.c
+++ b/arch/mips/mm/pgtable.c
@@ -29,9 +29,9 @@ void show_mem(void)
29 shared += page_count(page) - 1; 29 shared += page_count(page) - 1;
30 } 30 }
31 printk("%d pages of RAM\n", total); 31 printk("%d pages of RAM\n", total);
32 printk("%d pages of HIGHMEM\n",highmem); 32 printk("%d pages of HIGHMEM\n", highmem);
33 printk("%d reserved pages\n",reserved); 33 printk("%d reserved pages\n", reserved);
34 printk("%d pages shared\n",shared); 34 printk("%d pages shared\n", shared);
35 printk("%d pages swap cached\n",cached); 35 printk("%d pages swap cached\n", cached);
36#endif 36#endif
37} 37}
diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 42b50964c644..c13170bc675c 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -102,7 +102,7 @@ static inline int __init mips_sc_probe(void)
102 102
103int __init mips_sc_init(void) 103int __init mips_sc_init(void)
104{ 104{
105 int found = mips_sc_probe (); 105 int found = mips_sc_probe();
106 if (found) { 106 if (found) {
107 mips_sc_enable(); 107 mips_sc_enable();
108 bcops = &mips_sc_ops; 108 bcops = &mips_sc_ops;
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index dcd6913dc1ff..74ae0348cc92 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -491,7 +491,7 @@ void __init tlb_init(void)
491 int wired = current_cpu_data.tlbsize - ntlb; 491 int wired = current_cpu_data.tlbsize - ntlb;
492 write_c0_wired(wired); 492 write_c0_wired(wired);
493 write_c0_index(wired-1); 493 write_c0_index(wired-1);
494 printk ("Restricting TLB to %d entries\n", ntlb); 494 printk("Restricting TLB to %d entries\n", ntlb);
495 } else 495 } else
496 printk("Ignoring invalid argument ntlb=%d\n", ntlb); 496 printk("Ignoring invalid argument ntlb=%d\n", ntlb);
497 } 497 }
diff --git a/arch/mips/mm/tlb-r8k.c b/arch/mips/mm/tlb-r8k.c
index 266a47d65eed..bd8409d8ff62 100644
--- a/arch/mips/mm/tlb-r8k.c
+++ b/arch/mips/mm/tlb-r8k.c
@@ -56,7 +56,7 @@ void local_flush_tlb_mm(struct mm_struct *mm)
56 int cpu = smp_processor_id(); 56 int cpu = smp_processor_id();
57 57
58 if (cpu_context(cpu, mm) != 0) 58 if (cpu_context(cpu, mm) != 0)
59 drop_mmu_context(mm,cpu); 59 drop_mmu_context(mm, cpu);
60} 60}
61 61
62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 62void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 6c425b052442..01b0961acfb6 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -35,24 +35,24 @@
35#include <asm/smp.h> 35#include <asm/smp.h>
36#include <asm/war.h> 36#include <asm/war.h>
37 37
38static __init int __maybe_unused r45k_bvahwbug(void) 38static inline int r45k_bvahwbug(void)
39{ 39{
40 /* XXX: We should probe for the presence of this bug, but we don't. */ 40 /* XXX: We should probe for the presence of this bug, but we don't. */
41 return 0; 41 return 0;
42} 42}
43 43
44static __init int __maybe_unused r4k_250MHZhwbug(void) 44static inline int r4k_250MHZhwbug(void)
45{ 45{
46 /* XXX: We should probe for the presence of this bug, but we don't. */ 46 /* XXX: We should probe for the presence of this bug, but we don't. */
47 return 0; 47 return 0;
48} 48}
49 49
50static __init int __maybe_unused bcm1250_m3_war(void) 50static inline int __maybe_unused bcm1250_m3_war(void)
51{ 51{
52 return BCM1250_M3_WAR; 52 return BCM1250_M3_WAR;
53} 53}
54 54
55static __init int __maybe_unused r10000_llsc_war(void) 55static inline int __maybe_unused r10000_llsc_war(void)
56{ 56{
57 return R10000_LLSC_WAR; 57 return R10000_LLSC_WAR;
58} 58}
@@ -66,7 +66,7 @@ static __init int __maybe_unused r10000_llsc_war(void)
66 * why; it's not an issue caused by the core RTL. 66 * why; it's not an issue caused by the core RTL.
67 * 67 *
68 */ 68 */
69static __init int __attribute__((unused)) m4kc_tlbp_war(void) 69static int __init m4kc_tlbp_war(void)
70{ 70{
71 return (current_cpu_data.processor_id & 0xffff00) == 71 return (current_cpu_data.processor_id & 0xffff00) ==
72 (PRID_COMP_MIPS | PRID_IMP_4KC); 72 (PRID_COMP_MIPS | PRID_IMP_4KC);
@@ -140,60 +140,60 @@ struct insn {
140 | (e) << RE_SH \ 140 | (e) << RE_SH \
141 | (f) << FUNC_SH) 141 | (f) << FUNC_SH)
142 142
143static __initdata struct insn insn_table[] = { 143static struct insn insn_table[] __initdata = {
144 { insn_addiu, M(addiu_op,0,0,0,0,0), RS | RT | SIMM }, 144 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
145 { insn_addu, M(spec_op,0,0,0,0,addu_op), RS | RT | RD }, 145 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
146 { insn_and, M(spec_op,0,0,0,0,and_op), RS | RT | RD }, 146 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
147 { insn_andi, M(andi_op,0,0,0,0,0), RS | RT | UIMM }, 147 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
148 { insn_beq, M(beq_op,0,0,0,0,0), RS | RT | BIMM }, 148 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
149 { insn_beql, M(beql_op,0,0,0,0,0), RS | RT | BIMM }, 149 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
150 { insn_bgez, M(bcond_op,0,bgez_op,0,0,0), RS | BIMM }, 150 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
151 { insn_bgezl, M(bcond_op,0,bgezl_op,0,0,0), RS | BIMM }, 151 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
152 { insn_bltz, M(bcond_op,0,bltz_op,0,0,0), RS | BIMM }, 152 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
153 { insn_bltzl, M(bcond_op,0,bltzl_op,0,0,0), RS | BIMM }, 153 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
154 { insn_bne, M(bne_op,0,0,0,0,0), RS | RT | BIMM }, 154 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
155 { insn_daddiu, M(daddiu_op,0,0,0,0,0), RS | RT | SIMM }, 155 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
156 { insn_daddu, M(spec_op,0,0,0,0,daddu_op), RS | RT | RD }, 156 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
157 { insn_dmfc0, M(cop0_op,dmfc_op,0,0,0,0), RT | RD | SET}, 157 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
158 { insn_dmtc0, M(cop0_op,dmtc_op,0,0,0,0), RT | RD | SET}, 158 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
159 { insn_dsll, M(spec_op,0,0,0,0,dsll_op), RT | RD | RE }, 159 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
160 { insn_dsll32, M(spec_op,0,0,0,0,dsll32_op), RT | RD | RE }, 160 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
161 { insn_dsra, M(spec_op,0,0,0,0,dsra_op), RT | RD | RE }, 161 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
162 { insn_dsrl, M(spec_op,0,0,0,0,dsrl_op), RT | RD | RE }, 162 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
163 { insn_dsrl32, M(spec_op,0,0,0,0,dsrl32_op), RT | RD | RE }, 163 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
164 { insn_dsubu, M(spec_op,0,0,0,0,dsubu_op), RS | RT | RD }, 164 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
165 { insn_eret, M(cop0_op,cop_op,0,0,0,eret_op), 0 }, 165 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
166 { insn_j, M(j_op,0,0,0,0,0), JIMM }, 166 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
167 { insn_jal, M(jal_op,0,0,0,0,0), JIMM }, 167 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
168 { insn_jr, M(spec_op,0,0,0,0,jr_op), RS }, 168 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
169 { insn_ld, M(ld_op,0,0,0,0,0), RS | RT | SIMM }, 169 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
170 { insn_ll, M(ll_op,0,0,0,0,0), RS | RT | SIMM }, 170 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
171 { insn_lld, M(lld_op,0,0,0,0,0), RS | RT | SIMM }, 171 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
172 { insn_lui, M(lui_op,0,0,0,0,0), RT | SIMM }, 172 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
173 { insn_lw, M(lw_op,0,0,0,0,0), RS | RT | SIMM }, 173 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
174 { insn_mfc0, M(cop0_op,mfc_op,0,0,0,0), RT | RD | SET}, 174 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
175 { insn_mtc0, M(cop0_op,mtc_op,0,0,0,0), RT | RD | SET}, 175 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
176 { insn_ori, M(ori_op,0,0,0,0,0), RS | RT | UIMM }, 176 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
177 { insn_rfe, M(cop0_op,cop_op,0,0,0,rfe_op), 0 }, 177 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
178 { insn_sc, M(sc_op,0,0,0,0,0), RS | RT | SIMM }, 178 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
179 { insn_scd, M(scd_op,0,0,0,0,0), RS | RT | SIMM }, 179 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
180 { insn_sd, M(sd_op,0,0,0,0,0), RS | RT | SIMM }, 180 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
181 { insn_sll, M(spec_op,0,0,0,0,sll_op), RT | RD | RE }, 181 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
182 { insn_sra, M(spec_op,0,0,0,0,sra_op), RT | RD | RE }, 182 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
183 { insn_srl, M(spec_op,0,0,0,0,srl_op), RT | RD | RE }, 183 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
184 { insn_subu, M(spec_op,0,0,0,0,subu_op), RS | RT | RD }, 184 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
185 { insn_sw, M(sw_op,0,0,0,0,0), RS | RT | SIMM }, 185 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
186 { insn_tlbp, M(cop0_op,cop_op,0,0,0,tlbp_op), 0 }, 186 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
187 { insn_tlbwi, M(cop0_op,cop_op,0,0,0,tlbwi_op), 0 }, 187 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
188 { insn_tlbwr, M(cop0_op,cop_op,0,0,0,tlbwr_op), 0 }, 188 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
189 { insn_xor, M(spec_op,0,0,0,0,xor_op), RS | RT | RD }, 189 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
190 { insn_xori, M(xori_op,0,0,0,0,0), RS | RT | UIMM }, 190 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
191 { insn_invalid, 0, 0 } 191 { insn_invalid, 0, 0 }
192}; 192};
193 193
194#undef M 194#undef M
195 195
196static __init u32 build_rs(u32 arg) 196static u32 __init build_rs(u32 arg)
197{ 197{
198 if (arg & ~RS_MASK) 198 if (arg & ~RS_MASK)
199 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 199 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -201,7 +201,7 @@ static __init u32 build_rs(u32 arg)
201 return (arg & RS_MASK) << RS_SH; 201 return (arg & RS_MASK) << RS_SH;
202} 202}
203 203
204static __init u32 build_rt(u32 arg) 204static u32 __init build_rt(u32 arg)
205{ 205{
206 if (arg & ~RT_MASK) 206 if (arg & ~RT_MASK)
207 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 207 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -209,7 +209,7 @@ static __init u32 build_rt(u32 arg)
209 return (arg & RT_MASK) << RT_SH; 209 return (arg & RT_MASK) << RT_SH;
210} 210}
211 211
212static __init u32 build_rd(u32 arg) 212static u32 __init build_rd(u32 arg)
213{ 213{
214 if (arg & ~RD_MASK) 214 if (arg & ~RD_MASK)
215 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 215 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -217,7 +217,7 @@ static __init u32 build_rd(u32 arg)
217 return (arg & RD_MASK) << RD_SH; 217 return (arg & RD_MASK) << RD_SH;
218} 218}
219 219
220static __init u32 build_re(u32 arg) 220static u32 __init build_re(u32 arg)
221{ 221{
222 if (arg & ~RE_MASK) 222 if (arg & ~RE_MASK)
223 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 223 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -225,7 +225,7 @@ static __init u32 build_re(u32 arg)
225 return (arg & RE_MASK) << RE_SH; 225 return (arg & RE_MASK) << RE_SH;
226} 226}
227 227
228static __init u32 build_simm(s32 arg) 228static u32 __init build_simm(s32 arg)
229{ 229{
230 if (arg > 0x7fff || arg < -0x8000) 230 if (arg > 0x7fff || arg < -0x8000)
231 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 231 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -233,7 +233,7 @@ static __init u32 build_simm(s32 arg)
233 return arg & 0xffff; 233 return arg & 0xffff;
234} 234}
235 235
236static __init u32 build_uimm(u32 arg) 236static u32 __init build_uimm(u32 arg)
237{ 237{
238 if (arg & ~IMM_MASK) 238 if (arg & ~IMM_MASK)
239 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 239 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -241,7 +241,7 @@ static __init u32 build_uimm(u32 arg)
241 return arg & IMM_MASK; 241 return arg & IMM_MASK;
242} 242}
243 243
244static __init u32 build_bimm(s32 arg) 244static u32 __init build_bimm(s32 arg)
245{ 245{
246 if (arg > 0x1ffff || arg < -0x20000) 246 if (arg > 0x1ffff || arg < -0x20000)
247 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 247 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -252,7 +252,7 @@ static __init u32 build_bimm(s32 arg)
252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff); 252 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
253} 253}
254 254
255static __init u32 build_jimm(u32 arg) 255static u32 __init build_jimm(u32 arg)
256{ 256{
257 if (arg & ~((JIMM_MASK) << 2)) 257 if (arg & ~((JIMM_MASK) << 2))
258 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 258 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -260,7 +260,7 @@ static __init u32 build_jimm(u32 arg)
260 return (arg >> 2) & JIMM_MASK; 260 return (arg >> 2) & JIMM_MASK;
261} 261}
262 262
263static __init u32 build_func(u32 arg) 263static u32 __init build_func(u32 arg)
264{ 264{
265 if (arg & ~FUNC_MASK) 265 if (arg & ~FUNC_MASK)
266 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 266 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -268,7 +268,7 @@ static __init u32 build_func(u32 arg)
268 return arg & FUNC_MASK; 268 return arg & FUNC_MASK;
269} 269}
270 270
271static __init u32 build_set(u32 arg) 271static u32 __init build_set(u32 arg)
272{ 272{
273 if (arg & ~SET_MASK) 273 if (arg & ~SET_MASK)
274 printk(KERN_WARNING "TLB synthesizer field overflow\n"); 274 printk(KERN_WARNING "TLB synthesizer field overflow\n");
@@ -315,69 +315,69 @@ static void __init build_insn(u32 **buf, enum opcode opc, ...)
315} 315}
316 316
317#define I_u1u2u3(op) \ 317#define I_u1u2u3(op) \
318 static inline void __init i##op(u32 **buf, unsigned int a, \ 318 static inline void i##op(u32 **buf, unsigned int a, \
319 unsigned int b, unsigned int c) \ 319 unsigned int b, unsigned int c) \
320 { \ 320 { \
321 build_insn(buf, insn##op, a, b, c); \ 321 build_insn(buf, insn##op, a, b, c); \
322 } 322 }
323 323
324#define I_u2u1u3(op) \ 324#define I_u2u1u3(op) \
325 static inline void __init i##op(u32 **buf, unsigned int a, \ 325 static inline void i##op(u32 **buf, unsigned int a, \
326 unsigned int b, unsigned int c) \ 326 unsigned int b, unsigned int c) \
327 { \ 327 { \
328 build_insn(buf, insn##op, b, a, c); \ 328 build_insn(buf, insn##op, b, a, c); \
329 } 329 }
330 330
331#define I_u3u1u2(op) \ 331#define I_u3u1u2(op) \
332 static inline void __init i##op(u32 **buf, unsigned int a, \ 332 static inline void i##op(u32 **buf, unsigned int a, \
333 unsigned int b, unsigned int c) \ 333 unsigned int b, unsigned int c) \
334 { \ 334 { \
335 build_insn(buf, insn##op, b, c, a); \ 335 build_insn(buf, insn##op, b, c, a); \
336 } 336 }
337 337
338#define I_u1u2s3(op) \ 338#define I_u1u2s3(op) \
339 static inline void __init i##op(u32 **buf, unsigned int a, \ 339 static inline void i##op(u32 **buf, unsigned int a, \
340 unsigned int b, signed int c) \ 340 unsigned int b, signed int c) \
341 { \ 341 { \
342 build_insn(buf, insn##op, a, b, c); \ 342 build_insn(buf, insn##op, a, b, c); \
343 } 343 }
344 344
345#define I_u2s3u1(op) \ 345#define I_u2s3u1(op) \
346 static inline void __init i##op(u32 **buf, unsigned int a, \ 346 static inline void i##op(u32 **buf, unsigned int a, \
347 signed int b, unsigned int c) \ 347 signed int b, unsigned int c) \
348 { \ 348 { \
349 build_insn(buf, insn##op, c, a, b); \ 349 build_insn(buf, insn##op, c, a, b); \
350 } 350 }
351 351
352#define I_u2u1s3(op) \ 352#define I_u2u1s3(op) \
353 static inline void __init i##op(u32 **buf, unsigned int a, \ 353 static inline void i##op(u32 **buf, unsigned int a, \
354 unsigned int b, signed int c) \ 354 unsigned int b, signed int c) \
355 { \ 355 { \
356 build_insn(buf, insn##op, b, a, c); \ 356 build_insn(buf, insn##op, b, a, c); \
357 } 357 }
358 358
359#define I_u1u2(op) \ 359#define I_u1u2(op) \
360 static inline void __init i##op(u32 **buf, unsigned int a, \ 360 static inline void i##op(u32 **buf, unsigned int a, \
361 unsigned int b) \ 361 unsigned int b) \
362 { \ 362 { \
363 build_insn(buf, insn##op, a, b); \ 363 build_insn(buf, insn##op, a, b); \
364 } 364 }
365 365
366#define I_u1s2(op) \ 366#define I_u1s2(op) \
367 static inline void __init i##op(u32 **buf, unsigned int a, \ 367 static inline void i##op(u32 **buf, unsigned int a, \
368 signed int b) \ 368 signed int b) \
369 { \ 369 { \
370 build_insn(buf, insn##op, a, b); \ 370 build_insn(buf, insn##op, a, b); \
371 } 371 }
372 372
373#define I_u1(op) \ 373#define I_u1(op) \
374 static inline void __init i##op(u32 **buf, unsigned int a) \ 374 static inline void i##op(u32 **buf, unsigned int a) \
375 { \ 375 { \
376 build_insn(buf, insn##op, a); \ 376 build_insn(buf, insn##op, a); \
377 } 377 }
378 378
379#define I_0(op) \ 379#define I_0(op) \
380 static inline void __init i##op(u32 **buf) \ 380 static inline void i##op(u32 **buf) \
381 { \ 381 { \
382 build_insn(buf, insn##op); \ 382 build_insn(buf, insn##op); \
383 } 383 }
@@ -457,7 +457,7 @@ struct label {
457 enum label_id lab; 457 enum label_id lab;
458}; 458};
459 459
460static __init void build_label(struct label **lab, u32 *addr, 460static void __init build_label(struct label **lab, u32 *addr,
461 enum label_id l) 461 enum label_id l)
462{ 462{
463 (*lab)->addr = addr; 463 (*lab)->addr = addr;
@@ -526,34 +526,34 @@ L_LA(_r3000_write_probe_fail)
526#define i_ehb(buf) i_sll(buf, 0, 0, 3) 526#define i_ehb(buf) i_sll(buf, 0, 0, 3)
527 527
528#ifdef CONFIG_64BIT 528#ifdef CONFIG_64BIT
529static __init int __maybe_unused in_compat_space_p(long addr) 529static int __init __maybe_unused in_compat_space_p(long addr)
530{ 530{
531 /* Is this address in 32bit compat space? */ 531 /* Is this address in 32bit compat space? */
532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L); 532 return (((addr) & 0xffffffff00000000L) == 0xffffffff00000000L);
533} 533}
534 534
535static __init int __maybe_unused rel_highest(long val) 535static int __init __maybe_unused rel_highest(long val)
536{ 536{
537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; 537 return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000;
538} 538}
539 539
540static __init int __maybe_unused rel_higher(long val) 540static int __init __maybe_unused rel_higher(long val)
541{ 541{
542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; 542 return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000;
543} 543}
544#endif 544#endif
545 545
546static __init int rel_hi(long val) 546static int __init rel_hi(long val)
547{ 547{
548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000; 548 return ((((val + 0x8000L) >> 16) & 0xffff) ^ 0x8000) - 0x8000;
549} 549}
550 550
551static __init int rel_lo(long val) 551static int __init rel_lo(long val)
552{ 552{
553 return ((val & 0xffff) ^ 0x8000) - 0x8000; 553 return ((val & 0xffff) ^ 0x8000) - 0x8000;
554} 554}
555 555
556static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr) 556static void __init i_LA_mostly(u32 **buf, unsigned int rs, long addr)
557{ 557{
558#ifdef CONFIG_64BIT 558#ifdef CONFIG_64BIT
559 if (!in_compat_space_p(addr)) { 559 if (!in_compat_space_p(addr)) {
@@ -571,7 +571,7 @@ static __init void i_LA_mostly(u32 **buf, unsigned int rs, long addr)
571 i_lui(buf, rs, rel_hi(addr)); 571 i_lui(buf, rs, rel_hi(addr));
572} 572}
573 573
574static __init void __maybe_unused i_LA(u32 **buf, unsigned int rs, 574static void __init __maybe_unused i_LA(u32 **buf, unsigned int rs,
575 long addr) 575 long addr)
576{ 576{
577 i_LA_mostly(buf, rs, addr); 577 i_LA_mostly(buf, rs, addr);
@@ -589,7 +589,7 @@ struct reloc {
589 enum label_id lab; 589 enum label_id lab;
590}; 590};
591 591
592static __init void r_mips_pc16(struct reloc **rel, u32 *addr, 592static void __init r_mips_pc16(struct reloc **rel, u32 *addr,
593 enum label_id l) 593 enum label_id l)
594{ 594{
595 (*rel)->addr = addr; 595 (*rel)->addr = addr;
@@ -614,7 +614,7 @@ static inline void __resolve_relocs(struct reloc *rel, struct label *lab)
614 } 614 }
615} 615}
616 616
617static __init void resolve_relocs(struct reloc *rel, struct label *lab) 617static void __init resolve_relocs(struct reloc *rel, struct label *lab)
618{ 618{
619 struct label *l; 619 struct label *l;
620 620
@@ -624,7 +624,7 @@ static __init void resolve_relocs(struct reloc *rel, struct label *lab)
624 __resolve_relocs(rel, l); 624 __resolve_relocs(rel, l);
625} 625}
626 626
627static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end, 627static void __init move_relocs(struct reloc *rel, u32 *first, u32 *end,
628 long off) 628 long off)
629{ 629{
630 for (; rel->lab != label_invalid; rel++) 630 for (; rel->lab != label_invalid; rel++)
@@ -632,7 +632,7 @@ static __init void move_relocs(struct reloc *rel, u32 *first, u32 *end,
632 rel->addr += off; 632 rel->addr += off;
633} 633}
634 634
635static __init void move_labels(struct label *lab, u32 *first, u32 *end, 635static void __init move_labels(struct label *lab, u32 *first, u32 *end,
636 long off) 636 long off)
637{ 637{
638 for (; lab->lab != label_invalid; lab++) 638 for (; lab->lab != label_invalid; lab++)
@@ -640,7 +640,7 @@ static __init void move_labels(struct label *lab, u32 *first, u32 *end,
640 lab->addr += off; 640 lab->addr += off;
641} 641}
642 642
643static __init void copy_handler(struct reloc *rel, struct label *lab, 643static void __init copy_handler(struct reloc *rel, struct label *lab,
644 u32 *first, u32 *end, u32 *target) 644 u32 *first, u32 *end, u32 *target)
645{ 645{
646 long off = (long)(target - first); 646 long off = (long)(target - first);
@@ -651,7 +651,7 @@ static __init void copy_handler(struct reloc *rel, struct label *lab,
651 move_labels(lab, first, end, off); 651 move_labels(lab, first, end, off);
652} 652}
653 653
654static __init int __maybe_unused insn_has_bdelay(struct reloc *rel, 654static int __init __maybe_unused insn_has_bdelay(struct reloc *rel,
655 u32 *addr) 655 u32 *addr)
656{ 656{
657 for (; rel->lab != label_invalid; rel++) { 657 for (; rel->lab != label_invalid; rel++) {
@@ -743,11 +743,11 @@ il_bgez(u32 **p, struct reloc **r, unsigned int reg, enum label_id l)
743 * We deliberately chose a buffer size of 128, so we won't scribble 743 * We deliberately chose a buffer size of 128, so we won't scribble
744 * over anything important on overflow before we panic. 744 * over anything important on overflow before we panic.
745 */ 745 */
746static __initdata u32 tlb_handler[128]; 746static u32 tlb_handler[128] __initdata;
747 747
748/* simply assume worst case size for labels and relocs */ 748/* simply assume worst case size for labels and relocs */
749static __initdata struct label labels[128]; 749static struct label labels[128] __initdata;
750static __initdata struct reloc relocs[128]; 750static struct reloc relocs[128] __initdata;
751 751
752/* 752/*
753 * The R3000 TLB handler is simple. 753 * The R3000 TLB handler is simple.
@@ -801,7 +801,7 @@ static void __init build_r3000_tlb_refill_handler(void)
801 * other one.To keep things simple, we first assume linear space, 801 * other one.To keep things simple, we first assume linear space,
802 * then we relocate it to the final handler layout as needed. 802 * then we relocate it to the final handler layout as needed.
803 */ 803 */
804static __initdata u32 final_handler[64]; 804static u32 final_handler[64] __initdata;
805 805
806/* 806/*
807 * Hazards 807 * Hazards
@@ -825,9 +825,9 @@ static __initdata u32 final_handler[64];
825 * 825 *
826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ... 826 * As if we MIPS hackers wouldn't know how to nop pipelines happy ...
827 */ 827 */
828static __init void __maybe_unused build_tlb_probe_entry(u32 **p) 828static void __init __maybe_unused build_tlb_probe_entry(u32 **p)
829{ 829{
830 switch (current_cpu_data.cputype) { 830 switch (current_cpu_type()) {
831 /* Found by experiment: R4600 v2.0 needs this, too. */ 831 /* Found by experiment: R4600 v2.0 needs this, too. */
832 case CPU_R4600: 832 case CPU_R4600:
833 case CPU_R5000: 833 case CPU_R5000:
@@ -849,7 +849,7 @@ static __init void __maybe_unused build_tlb_probe_entry(u32 **p)
849 */ 849 */
850enum tlb_write_entry { tlb_random, tlb_indexed }; 850enum tlb_write_entry { tlb_random, tlb_indexed };
851 851
852static __init void build_tlb_write_entry(u32 **p, struct label **l, 852static void __init build_tlb_write_entry(u32 **p, struct label **l,
853 struct reloc **r, 853 struct reloc **r,
854 enum tlb_write_entry wmode) 854 enum tlb_write_entry wmode)
855{ 855{
@@ -860,7 +860,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
860 case tlb_indexed: tlbw = i_tlbwi; break; 860 case tlb_indexed: tlbw = i_tlbwi; break;
861 } 861 }
862 862
863 switch (current_cpu_data.cputype) { 863 switch (current_cpu_type()) {
864 case CPU_R4000PC: 864 case CPU_R4000PC:
865 case CPU_R4000SC: 865 case CPU_R4000SC:
866 case CPU_R4000MC: 866 case CPU_R4000MC:
@@ -908,6 +908,8 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
908 case CPU_4KSC: 908 case CPU_4KSC:
909 case CPU_20KC: 909 case CPU_20KC:
910 case CPU_25KF: 910 case CPU_25KF:
911 case CPU_BCM3302:
912 case CPU_BCM4710:
911 case CPU_LOONGSON2: 913 case CPU_LOONGSON2:
912 if (m4kc_tlbp_war()) 914 if (m4kc_tlbp_war())
913 i_nop(p); 915 i_nop(p);
@@ -991,7 +993,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
991 * TMP and PTR are scratch. 993 * TMP and PTR are scratch.
992 * TMP will be clobbered, PTR will hold the pmd entry. 994 * TMP will be clobbered, PTR will hold the pmd entry.
993 */ 995 */
994static __init void 996static void __init
995build_get_pmde64(u32 **p, struct label **l, struct reloc **r, 997build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
996 unsigned int tmp, unsigned int ptr) 998 unsigned int tmp, unsigned int ptr)
997{ 999{
@@ -1052,7 +1054,7 @@ build_get_pmde64(u32 **p, struct label **l, struct reloc **r,
1052 * BVADDR is the faulting address, PTR is scratch. 1054 * BVADDR is the faulting address, PTR is scratch.
1053 * PTR will hold the pgd for vmalloc. 1055 * PTR will hold the pgd for vmalloc.
1054 */ 1056 */
1055static __init void 1057static void __init
1056build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r, 1058build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1057 unsigned int bvaddr, unsigned int ptr) 1059 unsigned int bvaddr, unsigned int ptr)
1058{ 1060{
@@ -1116,7 +1118,7 @@ build_get_pgd_vmalloc64(u32 **p, struct label **l, struct reloc **r,
1116 * TMP and PTR are scratch. 1118 * TMP and PTR are scratch.
1117 * TMP will be clobbered, PTR will hold the pgd entry. 1119 * TMP will be clobbered, PTR will hold the pgd entry.
1118 */ 1120 */
1119static __init void __maybe_unused 1121static void __init __maybe_unused
1120build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr) 1122build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1121{ 1123{
1122 long pgdc = (long)pgd_current; 1124 long pgdc = (long)pgd_current;
@@ -1151,12 +1153,12 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
1151 1153
1152#endif /* !CONFIG_64BIT */ 1154#endif /* !CONFIG_64BIT */
1153 1155
1154static __init void build_adjust_context(u32 **p, unsigned int ctx) 1156static void __init build_adjust_context(u32 **p, unsigned int ctx)
1155{ 1157{
1156 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12; 1158 unsigned int shift = 4 - (PTE_T_LOG2 + 1) + PAGE_SHIFT - 12;
1157 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1); 1159 unsigned int mask = (PTRS_PER_PTE / 2 - 1) << (PTE_T_LOG2 + 1);
1158 1160
1159 switch (current_cpu_data.cputype) { 1161 switch (current_cpu_type()) {
1160 case CPU_VR41XX: 1162 case CPU_VR41XX:
1161 case CPU_VR4111: 1163 case CPU_VR4111:
1162 case CPU_VR4121: 1164 case CPU_VR4121:
@@ -1177,7 +1179,7 @@ static __init void build_adjust_context(u32 **p, unsigned int ctx)
1177 i_andi(p, ctx, ctx, mask); 1179 i_andi(p, ctx, ctx, mask);
1178} 1180}
1179 1181
1180static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr) 1182static void __init build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1181{ 1183{
1182 /* 1184 /*
1183 * Bug workaround for the Nevada. It seems as if under certain 1185 * Bug workaround for the Nevada. It seems as if under certain
@@ -1186,7 +1188,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1186 * in a different cacheline or a load instruction, probably any 1188 * in a different cacheline or a load instruction, probably any
1187 * memory reference, is between them. 1189 * memory reference, is between them.
1188 */ 1190 */
1189 switch (current_cpu_data.cputype) { 1191 switch (current_cpu_type()) {
1190 case CPU_NEVADA: 1192 case CPU_NEVADA:
1191 i_LW(p, ptr, 0, ptr); 1193 i_LW(p, ptr, 0, ptr);
1192 GET_CONTEXT(p, tmp); /* get context reg */ 1194 GET_CONTEXT(p, tmp); /* get context reg */
@@ -1202,7 +1204,7 @@ static __init void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
1202 i_ADDU(p, ptr, ptr, tmp); /* add in offset */ 1204 i_ADDU(p, ptr, ptr, tmp); /* add in offset */
1203} 1205}
1204 1206
1205static __init void build_update_entries(u32 **p, unsigned int tmp, 1207static void __init build_update_entries(u32 **p, unsigned int tmp,
1206 unsigned int ptep) 1208 unsigned int ptep)
1207{ 1209{
1208 /* 1210 /*
@@ -1870,7 +1872,7 @@ void __init build_tlb_refill_handler(void)
1870 */ 1872 */
1871 static int run_once = 0; 1873 static int run_once = 0;
1872 1874
1873 switch (current_cpu_data.cputype) { 1875 switch (current_cpu_type()) {
1874 case CPU_R2000: 1876 case CPU_R2000:
1875 case CPU_R3000: 1877 case CPU_R3000:
1876 case CPU_R3000A: 1878 case CPU_R3000A:
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 4e0a90b3916b..aa52aa146cea 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -74,7 +74,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
74 struct op_mips_model *lmodel = NULL; 74 struct op_mips_model *lmodel = NULL;
75 int res; 75 int res;
76 76
77 switch (current_cpu_data.cputype) { 77 switch (current_cpu_type()) {
78 case CPU_5KC: 78 case CPU_5KC:
79 case CPU_20KC: 79 case CPU_20KC:
80 case CPU_24K: 80 case CPU_24K:
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 1ea5c9c1010b..423bc2c473df 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -118,7 +118,7 @@ static void mipsxx_reg_setup(struct op_counter_config *ctr)
118 118
119/* Program all of the registers in preparation for enabling profiling. */ 119/* Program all of the registers in preparation for enabling profiling. */
120 120
121static void mipsxx_cpu_setup (void *args) 121static void mipsxx_cpu_setup(void *args)
122{ 122{
123 unsigned int counters = op_model_mipsxx_ops.num_counters; 123 unsigned int counters = op_model_mipsxx_ops.num_counters;
124 124
@@ -222,7 +222,7 @@ static inline int n_counters(void)
222{ 222{
223 int counters; 223 int counters;
224 224
225 switch (current_cpu_data.cputype) { 225 switch (current_cpu_type()) {
226 case CPU_R10000: 226 case CPU_R10000:
227 counters = 2; 227 counters = 2;
228 break; 228 break;
@@ -274,7 +274,7 @@ static int __init mipsxx_init(void)
274#endif 274#endif
275 275
276 op_model_mipsxx_ops.num_counters = counters; 276 op_model_mipsxx_ops.num_counters = counters;
277 switch (current_cpu_data.cputype) { 277 switch (current_cpu_type()) {
278 case CPU_20KC: 278 case CPU_20KC:
279 op_model_mipsxx_ops.cpu_type = "mips/20K"; 279 op_model_mipsxx_ops.cpu_type = "mips/20K";
280 break; 280 break;
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
index d29040a56aea..a45d3202894f 100644
--- a/arch/mips/oprofile/op_model_rm9000.c
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -60,7 +60,7 @@ static void rm9000_reg_setup(struct op_counter_config *ctr)
60 60
61/* Program all of the registers in preparation for enabling profiling. */ 61/* Program all of the registers in preparation for enabling profiling. */
62 62
63static void rm9000_cpu_setup (void *args) 63static void rm9000_cpu_setup(void *args)
64{ 64{
65 uint64_t perfcount; 65 uint64_t perfcount;
66 66
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4ee6800e67e6..ed0c07622baa 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -10,6 +10,7 @@ obj-y += pci.o
10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o 10obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o
11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o 11obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o
12obj-$(CONFIG_MIPS_MSC) += ops-msc.o 12obj-$(CONFIG_MIPS_MSC) += ops-msc.o
13obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
13obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o 14obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
14obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
15obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
19# These are still pretty much in the old state, watch, go blind. 20# These are still pretty much in the old state, watch, go blind.
20# 21#
21obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o 22obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o
23obj-$(CONFIG_LASAT) += pci-lasat.o
22obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o 24obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
23obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o 25obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
24obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o 26obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o
diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c
index 45224fd2c7ba..506e883a8c71 100644
--- a/arch/mips/pci/fixup-atlas.c
+++ b/arch/mips/pci/fixup-atlas.c
@@ -77,12 +77,12 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
77 * code, but it is better than nothing... 77 * code, but it is better than nothing...
78 */ 78 */
79 79
80static void atlas_saa9730_base_fixup (struct pci_dev *pdev) 80static void atlas_saa9730_base_fixup(struct pci_dev *pdev)
81{ 81{
82 extern void *saa9730_base; 82 extern void *saa9730_base;
83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19) 83 if (pdev->bus == 0 && PCI_SLOT(pdev->devfn) == 19)
84 (void) pci_read_config_dword (pdev, 0x14, (u32 *)&saa9730_base); 84 (void) pci_read_config_dword(pdev, 0x14, (u32 *)&saa9730_base);
85 printk ("saa9730_base = %x\n", saa9730_base); 85 printk("saa9730_base = %x\n", saa9730_base);
86} 86}
87 87
88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730, 88DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA9730,
diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c
index 76b4f0ffb1e5..f7df1142912b 100644
--- a/arch/mips/pci/fixup-cobalt.c
+++ b/arch/mips/pci/fixup-cobalt.c
@@ -18,6 +18,24 @@
18#include <asm/gt64120.h> 18#include <asm/gt64120.h>
19 19
20#include <cobalt.h> 20#include <cobalt.h>
21#include <irq.h>
22
23/*
24 * PCI slot numbers
25 */
26#define COBALT_PCICONF_CPU 0x06
27#define COBALT_PCICONF_ETH0 0x07
28#define COBALT_PCICONF_RAQSCSI 0x08
29#define COBALT_PCICONF_VIA 0x09
30#define COBALT_PCICONF_PCISLOT 0x0A
31#define COBALT_PCICONF_ETH1 0x0C
32
33/*
34 * The Cobalt board ID information. The boards have an ID number wired
35 * into the VIA that is available in the high nibble of register 94.
36 */
37#define VIA_COBALT_BRD_ID_REG 0x94
38#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char)(reg) >> 4)
21 39
22static void qube_raq_galileo_early_fixup(struct pci_dev *dev) 40static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
23{ 41{
@@ -132,29 +150,29 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
132 150
133static char irq_tab_qube1[] __initdata = { 151static char irq_tab_qube1[] __initdata = {
134 [COBALT_PCICONF_CPU] = 0, 152 [COBALT_PCICONF_CPU] = 0,
135 [COBALT_PCICONF_ETH0] = COBALT_QUBE1_ETH0_IRQ, 153 [COBALT_PCICONF_ETH0] = QUBE1_ETH0_IRQ,
136 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 154 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
137 [COBALT_PCICONF_VIA] = 0, 155 [COBALT_PCICONF_VIA] = 0,
138 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 156 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
139 [COBALT_PCICONF_ETH1] = 0 157 [COBALT_PCICONF_ETH1] = 0
140}; 158};
141 159
142static char irq_tab_cobalt[] __initdata = { 160static char irq_tab_cobalt[] __initdata = {
143 [COBALT_PCICONF_CPU] = 0, 161 [COBALT_PCICONF_CPU] = 0,
144 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 162 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
145 [COBALT_PCICONF_RAQSCSI] = COBALT_SCSI_IRQ, 163 [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
146 [COBALT_PCICONF_VIA] = 0, 164 [COBALT_PCICONF_VIA] = 0,
147 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 165 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
148 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 166 [COBALT_PCICONF_ETH1] = ETH1_IRQ
149}; 167};
150 168
151static char irq_tab_raq2[] __initdata = { 169static char irq_tab_raq2[] __initdata = {
152 [COBALT_PCICONF_CPU] = 0, 170 [COBALT_PCICONF_CPU] = 0,
153 [COBALT_PCICONF_ETH0] = COBALT_ETH0_IRQ, 171 [COBALT_PCICONF_ETH0] = ETH0_IRQ,
154 [COBALT_PCICONF_RAQSCSI] = COBALT_RAQ_SCSI_IRQ, 172 [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
155 [COBALT_PCICONF_VIA] = 0, 173 [COBALT_PCICONF_VIA] = 0,
156 [COBALT_PCICONF_PCISLOT] = COBALT_QUBE_SLOT_IRQ, 174 [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
157 [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ 175 [COBALT_PCICONF_ETH1] = ETH1_IRQ
158}; 176};
159 177
160int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 178int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
index 7932dfe5eb9b..6b29904acf45 100644
--- a/arch/mips/pci/ops-au1000.c
+++ b/arch/mips/pci/ops-au1000.c
@@ -112,7 +112,7 @@ static int config_access(unsigned char access_type, struct pci_bus *bus,
112 first_cfg = 0; 112 first_cfg = 0;
113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); 113 pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
114 if (!pci_cfg_vm) 114 if (!pci_cfg_vm)
115 panic (KERN_ERR "PCI unable to get vm area\n"); 115 panic(KERN_ERR "PCI unable to get vm area\n");
116 pci_cfg_wired_entry = read_c0_wired(); 116 pci_cfg_wired_entry = read_c0_wired();
117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); 117 add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
118 last_entryLo0 = last_entryLo1 = 0xffffffff; 118 last_entryLo0 = last_entryLo1 = 0xffffffff;
diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c
new file mode 100644
index 000000000000..b7f0fb0210f4
--- /dev/null
+++ b/arch/mips/pci/ops-nile4.c
@@ -0,0 +1,147 @@
1#include <linux/kernel.h>
2#include <linux/init.h>
3#include <linux/pci.h>
4#include <asm/bootinfo.h>
5
6#include <asm/lasat/lasat.h>
7#include <asm/gt64120.h>
8#include <asm/nile4.h>
9
10#define PCI_ACCESS_READ 0
11#define PCI_ACCESS_WRITE 1
12
13#define LO(reg) (reg / 4)
14#define HI(reg) (reg / 4 + 1)
15
16volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE;
17
18static DEFINE_SPINLOCK(nile4_pci_lock);
19
20static int nile4_pcibios_config_access(unsigned char access_type,
21 struct pci_bus *bus, unsigned int devfn, int where, u32 *val)
22{
23 unsigned char busnum = bus->number;
24 u32 adr, mask, err;
25
26 if ((busnum == 0) && (PCI_SLOT(devfn) > 8))
27 /* The addressing scheme chosen leaves room for just
28 * 8 devices on the first busnum (besides the PCI
29 * controller itself) */
30 return PCIBIOS_DEVICE_NOT_FOUND;
31
32 if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) {
33 /* Access controller registers directly */
34 if (access_type == PCI_ACCESS_WRITE) {
35 vrc_pciregs[(0x200 + where) >> 2] = *val;
36 } else {
37 *val = vrc_pciregs[(0x200 + where) >> 2];
38 }
39 return PCIBIOS_SUCCESSFUL;
40 }
41
42 /* Temporarily map PCI Window 1 to config space */
43 mask = vrc_pciregs[LO(NILE4_PCIINIT1)];
44 vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0);
45
46 /* Clear PCI Error register. This also clears the Error Type
47 * bits in the Control register */
48 vrc_pciregs[LO(NILE4_PCIERR)] = 0;
49 vrc_pciregs[HI(NILE4_PCIERR)] = 0;
50
51 /* Setup address */
52 if (busnum == 0)
53 adr =
54 KSEG1ADDR(PCI_WINDOW1) +
55 ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8)
56 | (where & ~3));
57 else
58 adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) |
59 (where & ~3);
60
61 if (access_type == PCI_ACCESS_WRITE)
62 *(u32 *) adr = *val;
63 else
64 *val = *(u32 *) adr;
65
66 /* Check for master or target abort */
67 err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7;
68
69 /* Restore PCI Window 1 */
70 vrc_pciregs[LO(NILE4_PCIINIT1)] = mask;
71
72 if (err)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 return PCIBIOS_SUCCESSFUL;
76}
77
78static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn,
79 int where, int size, u32 *val)
80{
81 unsigned long flags;
82 u32 data = 0;
83 int err;
84
85 if ((size == 2) && (where & 1))
86 return PCIBIOS_BAD_REGISTER_NUMBER;
87 else if ((size == 4) && (where & 3))
88 return PCIBIOS_BAD_REGISTER_NUMBER;
89
90 spin_lock_irqsave(&nile4_pci_lock, flags);
91 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
92 &data);
93 spin_unlock_irqrestore(&nile4_pci_lock, flags);
94
95 if (err)
96 return err;
97
98 if (size == 1)
99 *val = (data >> ((where & 3) << 3)) & 0xff;
100 else if (size == 2)
101 *val = (data >> ((where & 3) << 3)) & 0xffff;
102 else
103 *val = data;
104
105 return PCIBIOS_SUCCESSFUL;
106}
107
108static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn,
109 int where, int size, u32 val)
110{
111 unsigned long flags;
112 u32 data = 0;
113 int err;
114
115 if ((size == 2) && (where & 1))
116 return PCIBIOS_BAD_REGISTER_NUMBER;
117 else if ((size == 4) && (where & 3))
118 return PCIBIOS_BAD_REGISTER_NUMBER;
119
120 spin_lock_irqsave(&nile4_pci_lock, flags);
121 err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
122 &data);
123 spin_unlock_irqrestore(&nile4_pci_lock, flags);
124
125 if (err)
126 return err;
127
128 if (size == 1)
129 data = (data & ~(0xff << ((where & 3) << 3))) |
130 (val << ((where & 3) << 3));
131 else if (size == 2)
132 data = (data & ~(0xffff << ((where & 3) << 3))) |
133 (val << ((where & 3) << 3));
134 else
135 data = val;
136
137 if (nile4_pcibios_config_access
138 (PCI_ACCESS_WRITE, bus, devfn, where, &data))
139 return -1;
140
141 return PCIBIOS_SUCCESSFUL;
142}
143
144struct pci_ops nile4_pci_ops = {
145 .read = nile4_pcibios_read,
146 .write = nile4_pcibios_write,
147};
diff --git a/arch/mips/pci/ops-sni.c b/arch/mips/pci/ops-sni.c
index fa2d2c60f797..97ed25b92edf 100644
--- a/arch/mips/pci/ops-sni.c
+++ b/arch/mips/pci/ops-sni.c
@@ -70,13 +70,13 @@ static int pcimt_write(struct pci_bus *bus, unsigned int devfn, int reg,
70 70
71 switch (size) { 71 switch (size) {
72 case 1: 72 case 1:
73 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 73 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
74 break; 74 break;
75 case 2: 75 case 2:
76 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 76 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
77 break; 77 break;
78 case 4: 78 case 4:
79 outl (val, PCIMT_CONFIG_DATA); 79 outl(val, PCIMT_CONFIG_DATA);
80 break; 80 break;
81 } 81 }
82 82
@@ -93,7 +93,7 @@ static int pcit_set_config_address(unsigned int busno, unsigned int devfn, int r
93 if ((devfn > 255) || (reg > 255) || (busno > 255)) 93 if ((devfn > 255) || (reg > 255) || (busno > 255))
94 return PCIBIOS_BAD_REGISTER_NUMBER; 94 return PCIBIOS_BAD_REGISTER_NUMBER;
95 95
96 outl ((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8); 96 outl((1 << 31) | ((busno & 0xff) << 16) | ((devfn & 0xff) << 8) | (reg & 0xfc), 0xcf8);
97 return PCIBIOS_SUCCESSFUL; 97 return PCIBIOS_SUCCESSFUL;
98} 98}
99 99
@@ -108,12 +108,12 @@ static int pcit_read(struct pci_bus *bus, unsigned int devfn, int reg,
108 * we don't do it, we will get a data bus error 108 * we don't do it, we will get a data bus error
109 */ 109 */
110 if (bus->number == 0) { 110 if (bus->number == 0) {
111 pcit_set_config_address (0, 0, 0x68); 111 pcit_set_config_address(0, 0, 0x68);
112 outl (inl (0xcfc) | 0xc0000000, 0xcfc); 112 outl(inl(0xcfc) | 0xc0000000, 0xcfc);
113 if ((res = pcit_set_config_address(0, devfn, 0))) 113 if ((res = pcit_set_config_address(0, devfn, 0)))
114 return res; 114 return res;
115 outl (0xffffffff, 0xcfc); 115 outl(0xffffffff, 0xcfc);
116 pcit_set_config_address (0, 0, 0x68); 116 pcit_set_config_address(0, 0, 0x68);
117 if (inl(0xcfc) & 0x100000) 117 if (inl(0xcfc) & 0x100000)
118 return PCIBIOS_DEVICE_NOT_FOUND; 118 return PCIBIOS_DEVICE_NOT_FOUND;
119 } 119 }
@@ -144,13 +144,13 @@ static int pcit_write(struct pci_bus *bus, unsigned int devfn, int reg,
144 144
145 switch (size) { 145 switch (size) {
146 case 1: 146 case 1:
147 outb (val, PCIMT_CONFIG_DATA + (reg & 3)); 147 outb(val, PCIMT_CONFIG_DATA + (reg & 3));
148 break; 148 break;
149 case 2: 149 case 2:
150 outw (val, PCIMT_CONFIG_DATA + (reg & 2)); 150 outw(val, PCIMT_CONFIG_DATA + (reg & 2));
151 break; 151 break;
152 case 4: 152 case 4:
153 outl (val, PCIMT_CONFIG_DATA); 153 outl(val, PCIMT_CONFIG_DATA);
154 break; 154 break;
155 } 155 }
156 156
diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c
index 2b4e30c7d105..5443ea3596f8 100644
--- a/arch/mips/pci/pci-bcm1480.c
+++ b/arch/mips/pci/pci-bcm1480.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
@@ -255,7 +255,7 @@ static int __init bcm1480_pcibios_init(void)
255 register_pci_controller(&bcm1480_controller); 255 register_pci_controller(&bcm1480_controller);
256 256
257#ifdef CONFIG_VGA_CONSOLE 257#ifdef CONFIG_VGA_CONSOLE
258 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1); 258 take_over_console(&vga_con, 0, MAX_NR_CONSOLES-1, 1);
259#endif 259#endif
260 return 0; 260 return 0;
261} 261}
diff --git a/arch/mips/pci/pci-bcm1480ht.c b/arch/mips/pci/pci-bcm1480ht.c
index ba2e34b09231..a63e3bd6b0ac 100644
--- a/arch/mips/pci/pci-bcm1480ht.c
+++ b/arch/mips/pci/pci-bcm1480ht.c
@@ -48,8 +48,8 @@
48 * Macros for calculating offsets into config space given a device 48 * Macros for calculating offsets into config space given a device
49 * structure or dev/fun/reg 49 * structure or dev/fun/reg
50 */ 50 */
51#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where)) 51#define CFGOFFSET(bus, devfn, where) (((bus)<<16)+((devfn)<<8)+(where))
52#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 52#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
53 53
54static void *ht_cfg_space; 54static void *ht_cfg_space;
55 55
diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c
new file mode 100644
index 000000000000..5abd5c7119be
--- /dev/null
+++ b/arch/mips/pci/pci-lasat.c
@@ -0,0 +1,91 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000, 2001, 04 Keith M Wesolowski
7 */
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/pci.h>
11#include <linux/types.h>
12#include <asm/bootinfo.h>
13
14extern struct pci_ops nile4_pci_ops;
15extern struct pci_ops gt64xxx_pci0_ops;
16static struct resource lasat_pci_mem_resource = {
17 .name = "LASAT PCI MEM",
18 .start = 0x18000000,
19 .end = 0x19ffffff,
20 .flags = IORESOURCE_MEM,
21};
22
23static struct resource lasat_pci_io_resource = {
24 .name = "LASAT PCI IO",
25 .start = 0x1a000000,
26 .end = 0x1bffffff,
27 .flags = IORESOURCE_IO,
28};
29
30static struct pci_controller lasat_pci_controller = {
31 .mem_resource = &lasat_pci_mem_resource,
32 .io_resource = &lasat_pci_io_resource,
33};
34
35static int __init lasat_pci_setup(void)
36{
37 printk(KERN_DEBUG "PCI: starting\n");
38
39 switch (mips_machtype) {
40 case MACH_LASAT_100:
41 lasat_pci_controller.pci_ops = &gt64xxx_pci0_ops;
42 break;
43 case MACH_LASAT_200:
44 lasat_pci_controller.pci_ops = &nile4_pci_ops;
45 break;
46 default:
47 panic("pcibios_init: mips_machtype incorrect");
48 }
49
50 register_pci_controller(&lasat_pci_controller);
51
52 return 0;
53}
54
55arch_initcall(lasat_pci_setup);
56
57#define LASATINT_ETH1 0
58#define LASATINT_ETH0 1
59#define LASATINT_HDC 2
60#define LASATINT_COMP 3
61#define LASATINT_HDLC 4
62#define LASATINT_PCIA 5
63#define LASATINT_PCIB 6
64#define LASATINT_PCIC 7
65#define LASATINT_PCID 8
66
67int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
68{
69 switch (slot) {
70 case 1:
71 case 2:
72 case 3:
73 return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4);
74 case 4:
75 return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */
76 case 5:
77 return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */
78 case 6:
79 return LASATINT_HDC; /* IDE controller */
80 default:
81 return 0xff; /* Illegal */
82 }
83
84 return -1;
85}
86
87/* Do platform specific device initialization at pci_enable_device() time */
88int pcibios_plat_dev_init(struct pci_dev *dev)
89{
90 return 0;
91}
diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c
index c1ac6493155e..42e4d2c800fa 100644
--- a/arch/mips/pci/pci-sb1250.c
+++ b/arch/mips/pci/pci-sb1250.c
@@ -49,8 +49,8 @@
49 * Macros for calculating offsets into config space given a device 49 * Macros for calculating offsets into config space given a device
50 * structure or dev/fun/reg 50 * structure or dev/fun/reg
51 */ 51 */
52#define CFGOFFSET(bus,devfn,where) (((bus)<<16) + ((devfn)<<8) + (where)) 52#define CFGOFFSET(bus, devfn, where) (((bus)<<16) + ((devfn)<<8) + (where))
53#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where) 53#define CFGADDR(bus, devfn, where) CFGOFFSET((bus)->number, (devfn), where)
54 54
55static void *cfg_space; 55static void *cfg_space;
56 56
diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c
index 9885fa403603..240df9e33813 100644
--- a/arch/mips/pci/pci-vr41xx.c
+++ b/arch/mips/pci/pci-vr41xx.c
@@ -228,7 +228,7 @@ static int __init vr41xx_pciu_init(void)
228 else 228 else
229 pciu_write(PCIEXACCREG, 0); 229 pciu_write(PCIEXACCREG, 0);
230 230
231 if (current_cpu_data.cputype == CPU_VR4122) 231 if (current_cpu_type() == CPU_VR4122)
232 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy)); 232 pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
233 233
234 pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer)); 234 pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
diff --git a/arch/mips/philips/pnx8550/common/proc.c b/arch/mips/philips/pnx8550/common/proc.c
index 92311e95b700..18b125e3b65d 100644
--- a/arch/mips/philips/pnx8550/common/proc.c
+++ b/arch/mips/philips/pnx8550/common/proc.c
@@ -27,20 +27,20 @@
27#include <uart.h> 27#include <uart.h>
28 28
29 29
30static int pnx8550_timers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 30static int pnx8550_timers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
31{ 31{
32 int len = 0; 32 int len = 0;
33 int configPR = read_c0_config7(); 33 int configPR = read_c0_config7();
34 34
35 if (offset==0) { 35 if (offset==0) {
36 len += sprintf(&page[len],"Timer: count, compare, tc, status\n"); 36 len += sprintf(&page[len], "Timer: count, compare, tc, status\n");
37 len += sprintf(&page[len]," 1: %11i, %8i, %1i, %s\n", 37 len += sprintf(&page[len], " 1: %11i, %8i, %1i, %s\n",
38 read_c0_count(), read_c0_compare(), 38 read_c0_count(), read_c0_compare(),
39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on"); 39 (configPR>>6)&0x1, ((configPR>>3)&0x1)? "off":"on");
40 len += sprintf(&page[len]," 2: %11i, %8i, %1i, %s\n", 40 len += sprintf(&page[len], " 2: %11i, %8i, %1i, %s\n",
41 read_c0_count2(), read_c0_compare2(), 41 read_c0_count2(), read_c0_compare2(),
42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on"); 42 (configPR>>7)&0x1, ((configPR>>4)&0x1)? "off":"on");
43 len += sprintf(&page[len]," 3: %11i, %8i, %1i, %s\n", 43 len += sprintf(&page[len], " 3: %11i, %8i, %1i, %s\n",
44 read_c0_count3(), read_c0_compare3(), 44 read_c0_count3(), read_c0_compare3(),
45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on"); 45 (configPR>>8)&0x1, ((configPR>>5)&0x1)? "off":"on");
46 } 46 }
@@ -48,23 +48,23 @@ static int pnx8550_timers_read (char* page, char** start, off_t offset, int coun
48 return len; 48 return len;
49} 49}
50 50
51static int pnx8550_registers_read (char* page, char** start, off_t offset, int count, int* eof, void* data) 51static int pnx8550_registers_read(char* page, char** start, off_t offset, int count, int* eof, void* data)
52{ 52{
53 int len = 0; 53 int len = 0;
54 54
55 if (offset==0) { 55 if (offset==0) {
56 len += sprintf(&page[len],"config1: %#10.8x\n",read_c0_config1()); 56 len += sprintf(&page[len], "config1: %#10.8x\n", read_c0_config1());
57 len += sprintf(&page[len],"config2: %#10.8x\n",read_c0_config2()); 57 len += sprintf(&page[len], "config2: %#10.8x\n", read_c0_config2());
58 len += sprintf(&page[len],"config3: %#10.8x\n",read_c0_config3()); 58 len += sprintf(&page[len], "config3: %#10.8x\n", read_c0_config3());
59 len += sprintf(&page[len],"configPR: %#10.8x\n",read_c0_config7()); 59 len += sprintf(&page[len], "configPR: %#10.8x\n", read_c0_config7());
60 len += sprintf(&page[len],"status: %#10.8x\n",read_c0_status()); 60 len += sprintf(&page[len], "status: %#10.8x\n", read_c0_status());
61 len += sprintf(&page[len],"cause: %#10.8x\n",read_c0_cause()); 61 len += sprintf(&page[len], "cause: %#10.8x\n", read_c0_cause());
62 len += sprintf(&page[len],"count: %#10.8x\n",read_c0_count()); 62 len += sprintf(&page[len], "count: %#10.8x\n", read_c0_count());
63 len += sprintf(&page[len],"count_2: %#10.8x\n",read_c0_count2()); 63 len += sprintf(&page[len], "count_2: %#10.8x\n", read_c0_count2());
64 len += sprintf(&page[len],"count_3: %#10.8x\n",read_c0_count3()); 64 len += sprintf(&page[len], "count_3: %#10.8x\n", read_c0_count3());
65 len += sprintf(&page[len],"compare: %#10.8x\n",read_c0_compare()); 65 len += sprintf(&page[len], "compare: %#10.8x\n", read_c0_compare());
66 len += sprintf(&page[len],"compare_2: %#10.8x\n",read_c0_compare2()); 66 len += sprintf(&page[len], "compare_2: %#10.8x\n", read_c0_compare2());
67 len += sprintf(&page[len],"compare_3: %#10.8x\n",read_c0_compare3()); 67 len += sprintf(&page[len], "compare_3: %#10.8x\n", read_c0_compare3());
68 } 68 }
69 69
70 return len; 70 return len;
diff --git a/arch/mips/philips/pnx8550/common/setup.c b/arch/mips/philips/pnx8550/common/setup.c
index 5bd737477685..2ce298f4d19a 100644
--- a/arch/mips/philips/pnx8550/common/setup.c
+++ b/arch/mips/philips/pnx8550/common/setup.c
@@ -47,7 +47,6 @@ extern void pnx8550_machine_halt(void);
47extern void pnx8550_machine_power_off(void); 47extern void pnx8550_machine_power_off(void);
48extern struct resource ioport_resource; 48extern struct resource ioport_resource;
49extern struct resource iomem_resource; 49extern struct resource iomem_resource;
50extern void pnx8550_time_init(void);
51extern void rs_kgdb_hook(int tty_no); 50extern void rs_kgdb_hook(int tty_no);
52extern char *prom_getcmdline(void); 51extern char *prom_getcmdline(void);
53 52
@@ -104,8 +103,6 @@ void __init plat_mem_setup(void)
104 _machine_halt = pnx8550_machine_halt; 103 _machine_halt = pnx8550_machine_halt;
105 pm_power_off = pnx8550_machine_power_off; 104 pm_power_off = pnx8550_machine_power_off;
106 105
107 board_time_init = pnx8550_time_init;
108
109 /* Clear the Global 2 Register, PCI Inta Output Enable Registers 106 /* Clear the Global 2 Register, PCI Inta Output Enable Registers
110 Bit 1:Enable DAC Powerdown 107 Bit 1:Enable DAC Powerdown
111 -> 0:DACs are enabled and are working normally 108 -> 0:DACs are enabled and are working normally
diff --git a/arch/mips/philips/pnx8550/common/time.c b/arch/mips/philips/pnx8550/common/time.c
index 68def3880a1c..e818fd0f1584 100644
--- a/arch/mips/philips/pnx8550/common/time.c
+++ b/arch/mips/philips/pnx8550/common/time.c
@@ -1,6 +1,7 @@
1/* 1/*
2 * Copyright 2001, 2002, 2003 MontaVista Software Inc. 2 * Copyright 2001, 2002, 2003 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
4 * 5 *
5 * Common time service routines for MIPS machines. See 6 * Common time service routines for MIPS machines. See
6 * Documents/MIPS/README.txt. 7 * Documents/MIPS/README.txt.
@@ -46,16 +47,16 @@ static void timer_ack(void)
46} 47}
47 48
48/* 49/*
49 * pnx8550_time_init() - it does the following things: 50 * plat_time_init() - it does the following things:
50 * 51 *
51 * 1) board_time_init() - 52 * 1) plat_time_init() -
52 * a) (optional) set up RTC routines, 53 * a) (optional) set up RTC routines,
53 * b) (optional) calibrate and set the mips_hpt_frequency 54 * b) (optional) calibrate and set the mips_hpt_frequency
54 * (only needed if you intended to use cpu counter as timer interrupt 55 * (only needed if you intended to use cpu counter as timer interrupt
55 * source) 56 * source)
56 */ 57 */
57 58
58void pnx8550_time_init(void) 59__init void plat_time_init(void)
59{ 60{
60 unsigned int n; 61 unsigned int n;
61 unsigned int m; 62 unsigned int m;
diff --git a/arch/mips/philips/pnx8550/jbs/init.c b/arch/mips/philips/pnx8550/jbs/init.c
index 85f449174bc3..cfd90fa3d799 100644
--- a/arch/mips/philips/pnx8550/jbs/init.c
+++ b/arch/mips/philips/pnx8550/jbs/init.c
@@ -48,7 +48,6 @@ void __init prom_init(void)
48 48
49 unsigned long memsize; 49 unsigned long memsize;
50 50
51 mips_machgroup = MACH_GROUP_PHILIPS;
52 mips_machtype = MACH_PHILIPS_JBS; 51 mips_machtype = MACH_PHILIPS_JBS;
53 52
54 //memsize = 0x02800000; /* Trimedia uses memory above */ 53 //memsize = 0x02800000; /* Trimedia uses memory above */
diff --git a/arch/mips/philips/pnx8550/stb810/prom_init.c b/arch/mips/philips/pnx8550/stb810/prom_init.c
index ea5b4e0fb47d..fdb33ed089b9 100644
--- a/arch/mips/philips/pnx8550/stb810/prom_init.c
+++ b/arch/mips/philips/pnx8550/stb810/prom_init.c
@@ -41,7 +41,6 @@ void __init prom_init(void)
41 41
42 prom_init_cmdline(); 42 prom_init_cmdline();
43 43
44 mips_machgroup = MACH_GROUP_PHILIPS;
45 mips_machtype = MACH_PHILIPS_STB810; 44 mips_machtype = MACH_PHILIPS_STB810;
46 45
47 memsize = 0x08000000; /* Trimedia uses memory above */ 46 memsize = 0x08000000; /* Trimedia uses memory above */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
index 6fa85728158b..ab96a2d7f4c4 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_hwbutton.c
@@ -163,7 +163,7 @@ static int msp_hwbutton_register(struct hwbutton_interrupt *hirq)
163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq); 163 CIC_EXT_SET_ACTIVE_HI(cic_ext, hirq->eirq);
164 *CIC_EXT_CFG_REG = cic_ext; 164 *CIC_EXT_CFG_REG = cic_ext;
165 165
166 return request_irq(hirq->irq, hwbutton_handler, SA_INTERRUPT, 166 return request_irq(hirq->irq, hwbutton_handler, IRQF_DISABLED,
167 hirq->name, (void *)hirq); 167 hirq->name, (void *)hirq);
168} 168}
169 169
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_serial.c b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
index e25bac537d77..15e7b8000b4c 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_serial.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_serial.c
@@ -117,7 +117,7 @@ void __init msp_serial_setup(void)
117 117
118 /* Initialize first serial port */ 118 /* Initialize first serial port */
119 up.mapbase = MSP_UART0_BASE; 119 up.mapbase = MSP_UART0_BASE;
120 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 120 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
121 up.irq = MSP_INT_UART0; 121 up.irq = MSP_INT_UART0;
122 up.uartclk = uartclk; 122 up.uartclk = uartclk;
123 up.regshift = 2; 123 up.regshift = 2;
@@ -145,9 +145,9 @@ void __init msp_serial_setup(void)
145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) { 145 if( DEBUG_PORT_BASE == KSEG1ADDR(MSP_UART1_BASE) ) {
146 if( mips_machtype == MACH_MSP4200_FPGA 146 if( mips_machtype == MACH_MSP4200_FPGA
147 || mips_machtype == MACH_MSP7120_FPGA ) 147 || mips_machtype == MACH_MSP7120_FPGA )
148 initDebugPort(uartclk,19200); 148 initDebugPort(uartclk, 19200);
149 else 149 else
150 initDebugPort(uartclk,57600); 150 initDebugPort(uartclk, 57600);
151 } 151 }
152#endif 152#endif
153 break; 153 break;
@@ -157,7 +157,7 @@ void __init msp_serial_setup(void)
157 } 157 }
158 158
159 up.mapbase = MSP_UART1_BASE; 159 up.mapbase = MSP_UART1_BASE;
160 up.membase = ioremap_nocache(up.mapbase,MSP_UART_REG_LEN); 160 up.membase = ioremap_nocache(up.mapbase, MSP_UART_REG_LEN);
161 up.irq = MSP_INT_UART1; 161 up.irq = MSP_INT_UART1;
162 up.line = 1; 162 up.line = 1;
163 up.private_data = (void*)UART1_STATUS_REG; 163 up.private_data = (void*)UART1_STATUS_REG;
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_setup.c b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
index 8f69b789be90..c93675615f5d 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_setup.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_setup.c
@@ -25,7 +25,6 @@
25#define MSP_BOARD_RESET_GPIO 9 25#define MSP_BOARD_RESET_GPIO 9
26#endif 26#endif
27 27
28extern void msp_timer_init(void);
29extern void msp_serial_setup(void); 28extern void msp_serial_setup(void);
30extern void pmctwiled_setup(void); 29extern void pmctwiled_setup(void);
31 30
@@ -149,8 +148,6 @@ void __init plat_mem_setup(void)
149 _machine_restart = msp_restart; 148 _machine_restart = msp_restart;
150 _machine_halt = msp_halt; 149 _machine_halt = msp_halt;
151 pm_power_off = msp_power_off; 150 pm_power_off = msp_power_off;
152
153 board_time_init = msp_timer_init;
154} 151}
155 152
156void __init prom_init(void) 153void __init prom_init(void)
@@ -176,16 +173,13 @@ void __init prom_init(void)
176 case FAMILY_FPGA: 173 case FAMILY_FPGA:
177 if (FPGA_IS_MSP4200(revision)) { 174 if (FPGA_IS_MSP4200(revision)) {
178 /* Old-style revision ID */ 175 /* Old-style revision ID */
179 mips_machgroup = MACH_GROUP_MSP;
180 mips_machtype = MACH_MSP4200_FPGA; 176 mips_machtype = MACH_MSP4200_FPGA;
181 } else { 177 } else {
182 mips_machgroup = MACH_GROUP_MSP;
183 mips_machtype = MACH_MSP_OTHER; 178 mips_machtype = MACH_MSP_OTHER;
184 } 179 }
185 break; 180 break;
186 181
187 case FAMILY_MSP4200: 182 case FAMILY_MSP4200:
188 mips_machgroup = MACH_GROUP_MSP;
189#if defined(CONFIG_PMC_MSP4200_EVAL) 183#if defined(CONFIG_PMC_MSP4200_EVAL)
190 mips_machtype = MACH_MSP4200_EVAL; 184 mips_machtype = MACH_MSP4200_EVAL;
191#elif defined(CONFIG_PMC_MSP4200_GW) 185#elif defined(CONFIG_PMC_MSP4200_GW)
@@ -196,12 +190,10 @@ void __init prom_init(void)
196 break; 190 break;
197 191
198 case FAMILY_MSP4200_FPGA: 192 case FAMILY_MSP4200_FPGA:
199 mips_machgroup = MACH_GROUP_MSP;
200 mips_machtype = MACH_MSP4200_FPGA; 193 mips_machtype = MACH_MSP4200_FPGA;
201 break; 194 break;
202 195
203 case FAMILY_MSP7100: 196 case FAMILY_MSP7100:
204 mips_machgroup = MACH_GROUP_MSP;
205#if defined(CONFIG_PMC_MSP7120_EVAL) 197#if defined(CONFIG_PMC_MSP7120_EVAL)
206 mips_machtype = MACH_MSP7120_EVAL; 198 mips_machtype = MACH_MSP7120_EVAL;
207#elif defined(CONFIG_PMC_MSP7120_GW) 199#elif defined(CONFIG_PMC_MSP7120_GW)
@@ -212,22 +204,14 @@ void __init prom_init(void)
212 break; 204 break;
213 205
214 case FAMILY_MSP7100_FPGA: 206 case FAMILY_MSP7100_FPGA:
215 mips_machgroup = MACH_GROUP_MSP;
216 mips_machtype = MACH_MSP7120_FPGA; 207 mips_machtype = MACH_MSP7120_FPGA;
217 break; 208 break;
218 209
219 default: 210 default:
220 /* we don't recognize the machine */ 211 /* we don't recognize the machine */
221 mips_machgroup = MACH_GROUP_UNKNOWN;
222 mips_machtype = MACH_UNKNOWN; 212 mips_machtype = MACH_UNKNOWN;
223 break;
224 }
225
226 /* make sure we have the right initialization routine - sanity */
227 if (mips_machgroup != MACH_GROUP_MSP) {
228 ppfinit("Unknown machine group in a "
229 "MSP initialization routine\n");
230 panic("***Bogosity factor five***, exiting\n"); 213 panic("***Bogosity factor five***, exiting\n");
214 break;
231 } 215 }
232 216
233 prom_init_cmdline(); 217 prom_init_cmdline();
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_time.c b/arch/mips/pmc-sierra/msp71xx/msp_time.c
index 2a2beac5a4f8..f221d4763625 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_time.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_time.c
@@ -36,7 +36,7 @@
36#include <msp_int.h> 36#include <msp_int.h>
37#include <msp_regs.h> 37#include <msp_regs.h>
38 38
39void __init msp_timer_init(void) 39void __init plat_time_init(void)
40{ 40{
41 char *endp, *s; 41 char *endp, *s;
42 unsigned long cpu_rate = 0; 42 unsigned long cpu_rate = 0;
@@ -81,7 +81,6 @@ void __init msp_timer_init(void)
81 mips_hpt_frequency = cpu_rate/2; 81 mips_hpt_frequency = cpu_rate/2;
82} 82}
83 83
84
85void __init plat_timer_setup(struct irqaction *irq) 84void __init plat_timer_setup(struct irqaction *irq)
86{ 85{
87#ifdef CONFIG_IRQ_MSP_CIC 86#ifdef CONFIG_IRQ_MSP_CIC
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_usb.c b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
index 21f9c70b6923..f7ca4f582331 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_usb.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_usb.c
@@ -58,7 +58,7 @@ static struct platform_device msp_usbhost_device = {
58 .dma_mask = &msp_usbhost_dma_mask, 58 .dma_mask = &msp_usbhost_dma_mask,
59 .coherent_dma_mask = DMA_32BIT_MASK, 59 .coherent_dma_mask = DMA_32BIT_MASK,
60 }, 60 },
61 .num_resources = ARRAY_SIZE (msp_usbhost_resources), 61 .num_resources = ARRAY_SIZE(msp_usbhost_resources),
62 .resource = msp_usbhost_resources, 62 .resource = msp_usbhost_resources,
63}; 63};
64#endif /* CONFIG_USB_EHCI_HCD */ 64#endif /* CONFIG_USB_EHCI_HCD */
@@ -86,7 +86,7 @@ static struct platform_device msp_usbdev_device = {
86 .dma_mask = &msp_usbdev_dma_mask, 86 .dma_mask = &msp_usbdev_dma_mask,
87 .coherent_dma_mask = DMA_32BIT_MASK, 87 .coherent_dma_mask = DMA_32BIT_MASK,
88 }, 88 },
89 .num_resources = ARRAY_SIZE (msp_usbdev_resources), 89 .num_resources = ARRAY_SIZE(msp_usbdev_resources),
90 .resource = msp_usbdev_resources, 90 .resource = msp_usbdev_resources,
91}; 91};
92#endif /* CONFIG_USB_GADGET */ 92#endif /* CONFIG_USB_GADGET */
@@ -129,7 +129,7 @@ static int __init msp_usb_setup(void)
129 ppfinit("platform add USB HOST done %s.\n", 129 ppfinit("platform add USB HOST done %s.\n",
130 msp_devs[0]->name); 130 msp_devs[0]->name);
131 131
132 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 132 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
133#endif /* CONFIG_USB_EHCI_HCD */ 133#endif /* CONFIG_USB_EHCI_HCD */
134 } 134 }
135#if defined(CONFIG_USB_GADGET) 135#if defined(CONFIG_USB_GADGET)
@@ -139,7 +139,7 @@ static int __init msp_usb_setup(void)
139 ppfinit("platform add USB DEVICE done %s.\n", 139 ppfinit("platform add USB DEVICE done %s.\n",
140 msp_devs[0]->name); 140 msp_devs[0]->name);
141 141
142 result = platform_add_devices(msp_devs, ARRAY_SIZE (msp_devs)); 142 result = platform_add_devices(msp_devs, ARRAY_SIZE(msp_devs));
143 } 143 }
144#endif /* CONFIG_USB_GADGET */ 144#endif /* CONFIG_USB_GADGET */
145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */ 145#endif /* CONFIG_USB_EHCI_HCD || CONFIG_USB_GADGET */
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
index 1f7c999eb7c6..6380662bbf3c 100644
--- a/arch/mips/pmc-sierra/yosemite/ht.c
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -115,7 +115,7 @@ static int titan_ht_config_read_word(struct pci_dev *device,
115 115
116u32 longswap(unsigned long l) 116u32 longswap(unsigned long l)
117{ 117{
118 unsigned char b1,b2,b3,b4; 118 unsigned char b1, b2, b3, b4;
119 119
120 b1 = l&255; 120 b1 = l&255;
121 b2 = (l>>8)&255; 121 b2 = (l>>8)&255;
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
index 0cd78f0f5f2d..9b9936de6589 100644
--- a/arch/mips/pmc-sierra/yosemite/prom.c
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -126,7 +126,6 @@ void __init prom_init(void)
126 env++; 126 env++;
127 } 127 }
128 128
129 mips_machgroup = MACH_GROUP_TITAN;
130 mips_machtype = MACH_TITAN_YOSEMITE; 129 mips_machtype = MACH_TITAN_YOSEMITE;
131 130
132 prom_grab_secondary(); 131 prom_grab_secondary();
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
index 58862c8d1d00..015fcc363dc0 100644
--- a/arch/mips/pmc-sierra/yosemite/setup.c
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -70,7 +70,7 @@ void __init bus_error_init(void)
70} 70}
71 71
72 72
73unsigned long m48t37y_get_time(void) 73unsigned long read_persistent_clock(void)
74{ 74{
75 unsigned int year, month, day, hour, min, sec; 75 unsigned int year, month, day, hour, min, sec;
76 unsigned long flags; 76 unsigned long flags;
@@ -95,13 +95,17 @@ unsigned long m48t37y_get_time(void)
95 return mktime(year, month, day, hour, min, sec); 95 return mktime(year, month, day, hour, min, sec);
96} 96}
97 97
98int m48t37y_set_time(unsigned long sec) 98int rtc_mips_set_time(unsigned long tim)
99{ 99{
100 struct rtc_time tm; 100 struct rtc_time tm;
101 unsigned long flags; 101 unsigned long flags;
102 102
103 /* convert to a more useful format -- note months count from 0 */ 103 /*
104 to_tm(sec, &tm); 104 * Convert to a more useful format -- note months count from 0
105 * and years from 1900
106 */
107 rtc_time_to_tm(tim, &tm);
108 tm.tm_year += 1900;
105 tm.tm_mon += 1; 109 tm.tm_mon += 1;
106 110
107 spin_lock_irqsave(&rtc_lock, flags); 111 spin_lock_irqsave(&rtc_lock, flags);
@@ -138,7 +142,7 @@ void __init plat_timer_setup(struct irqaction *irq)
138 setup_irq(7, irq); 142 setup_irq(7, irq);
139} 143}
140 144
141void yosemite_time_init(void) 145void __init plat_time_init(void)
142{ 146{
143 mips_hpt_frequency = cpu_clock_freq / 2; 147 mips_hpt_frequency = cpu_clock_freq / 2;
144mips_hpt_frequency = 33000000 * 3 * 5; 148mips_hpt_frequency = 33000000 * 3 * 5;
@@ -198,17 +202,6 @@ static void __init py_rtc_setup(void)
198 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE); 202 m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
199 if (!m48t37_base) 203 if (!m48t37_base)
200 printk(KERN_ERR "Mapping the RTC failed\n"); 204 printk(KERN_ERR "Mapping the RTC failed\n");
201
202 rtc_mips_get_time = m48t37y_get_time;
203 rtc_mips_set_time = m48t37y_set_time;
204
205 write_seqlock(&xtime_lock);
206 xtime.tv_sec = m48t37y_get_time();
207 xtime.tv_nsec = 0;
208
209 set_normalized_timespec(&wall_to_monotonic,
210 -xtime.tv_sec, -xtime.tv_nsec);
211 write_sequnlock(&xtime_lock);
212} 205}
213 206
214/* Not only time init but that's what the hook it's called through is named */ 207/* Not only time init but that's what the hook it's called through is named */
@@ -221,7 +214,6 @@ static void __init py_late_time_init(void)
221 214
222void __init plat_mem_setup(void) 215void __init plat_mem_setup(void)
223{ 216{
224 board_time_init = yosemite_time_init;
225 late_time_init = py_late_time_init; 217 late_time_init = py_late_time_init;
226 218
227 /* Add memory regions */ 219 /* Add memory regions */
diff --git a/arch/mips/qemu/q-firmware.c b/arch/mips/qemu/q-firmware.c
index fb2a8673a6bf..c2239b417587 100644
--- a/arch/mips/qemu/q-firmware.c
+++ b/arch/mips/qemu/q-firmware.c
@@ -10,7 +10,7 @@ void __init prom_init(void)
10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260); 10 cmdline = (int *) (CKSEG0 + (0x10 << 20) - 260);
11 if (*cmdline == 0x12345678) { 11 if (*cmdline == 0x12345678) {
12 if (*(char *)(cmdline + 1)) 12 if (*(char *)(cmdline + 1))
13 strcpy (arcs_cmdline, (char *)(cmdline + 1)); 13 strcpy(arcs_cmdline, (char *)(cmdline + 1));
14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM); 14 add_memory_region(0x0<<20, cmdline[-1], BOOT_MEM_RAM);
15 } else { 15 } else {
16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM); 16 add_memory_region(0x0<<20, 0x10<<20, BOOT_MEM_RAM);
diff --git a/arch/mips/qemu/q-irq.c b/arch/mips/qemu/q-irq.c
index 89891e984b3b..4681757460a1 100644
--- a/arch/mips/qemu/q-irq.c
+++ b/arch/mips/qemu/q-irq.c
@@ -2,6 +2,7 @@
2#include <linux/linkage.h> 2#include <linux/linkage.h>
3 3
4#include <asm/i8259.h> 4#include <asm/i8259.h>
5#include <asm/irq_cpu.h>
5#include <asm/mipsregs.h> 6#include <asm/mipsregs.h>
6#include <asm/qemu.h> 7#include <asm/qemu.h>
7#include <asm/system.h> 8#include <asm/system.h>
@@ -12,7 +13,7 @@ asmlinkage void plat_irq_dispatch(void)
12 unsigned int pending = read_c0_status() & read_c0_cause(); 13 unsigned int pending = read_c0_status() & read_c0_cause();
13 14
14 if (pending & 0x8000) { 15 if (pending & 0x8000) {
15 ll_timer_interrupt(Q_COUNT_COMPARE_IRQ); 16 do_IRQ(Q_COUNT_COMPARE_IRQ);
16 return; 17 return;
17 } 18 }
18 if (pending & 0x0400) { 19 if (pending & 0x0400) {
@@ -29,6 +30,7 @@ void __init arch_init_irq(void)
29{ 30{
30 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */ 31 mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK; /* 100MHz */
31 32
33 mips_cpu_irq_init();
32 init_i8259_irqs(); 34 init_i8259_irqs();
33 set_c0_status(0x8400); 35 set_c0_status(0x8400);
34} 36}
diff --git a/arch/mips/qemu/q-setup.c b/arch/mips/qemu/q-setup.c
index 841394336f00..23d34c1917c0 100644
--- a/arch/mips/qemu/q-setup.c
+++ b/arch/mips/qemu/q-setup.c
@@ -1,4 +1,6 @@
1#include <linux/init.h> 1#include <linux/init.h>
2
3#include <asm/i8253.h>
2#include <asm/io.h> 4#include <asm/io.h>
3#include <asm/time.h> 5#include <asm/time.h>
4 6
@@ -11,13 +13,9 @@ const char *get_system_type(void)
11 return "Qemu"; 13 return "Qemu";
12} 14}
13 15
14void __init plat_timer_setup(struct irqaction *irq) 16void __init plat_time_init(void)
15{ 17{
16 /* set the clock to 100 Hz */ 18 setup_pit_timer();
17 outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
18 outb_p(LATCH & 0xff , 0x40); /* LSB */
19 outb(LATCH >> 8 , 0x40); /* MSB */
20 setup_irq(0, irq);
21} 19}
22 20
23void __init plat_mem_setup(void) 21void __init plat_mem_setup(void)
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 6b6e97b90c6e..26854fb11e7c 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -55,7 +55,7 @@ static char __init *decode_eisa_sig(unsigned long addr)
55 int i; 55 int i;
56 56
57 for (i = 0; i < 4; i++) { 57 for (i = 0; i < 4; i++) {
58 sig[i] = inb (addr + i); 58 sig[i] = inb(addr + i);
59 59
60 if (!i && (sig[0] & 0x80)) 60 if (!i && (sig[0] & 0x80))
61 return NULL; 61 return NULL;
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index 18348321795d..f6d9bf4b26e7 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -20,10 +20,10 @@
20#include <asm/mipsregs.h> 20#include <asm/mipsregs.h>
21#include <asm/addrspace.h> 21#include <asm/addrspace.h>
22#include <asm/irq_cpu.h> 22#include <asm/irq_cpu.h>
23
24#include <asm/sgi/ioc.h> 23#include <asm/sgi/ioc.h>
25#include <asm/sgi/hpc3.h> 24#include <asm/sgi/hpc3.h>
26#include <asm/sgi/ip22.h> 25#include <asm/sgi/ip22.h>
26#include <asm/time.h>
27 27
28/* #define DEBUG_SGINT */ 28/* #define DEBUG_SGINT */
29 29
@@ -204,7 +204,6 @@ static struct irqaction map1_cascade = {
204#define SGI_INTERRUPTS SGINT_LOCAL3 204#define SGI_INTERRUPTS SGINT_LOCAL3
205#endif 205#endif
206 206
207extern void indy_r4k_timer_interrupt(void);
208extern void indy_8254timer_irq(void); 207extern void indy_8254timer_irq(void);
209 208
210/* 209/*
@@ -243,7 +242,7 @@ asmlinkage void plat_irq_dispatch(void)
243 * First we check for r4k counter/timer IRQ. 242 * First we check for r4k counter/timer IRQ.
244 */ 243 */
245 if (pending & CAUSEF_IP7) 244 if (pending & CAUSEF_IP7)
246 indy_r4k_timer_interrupt(); 245 do_IRQ(SGI_TIMER_IRQ);
247 else if (pending & CAUSEF_IP2) 246 else if (pending & CAUSEF_IP2)
248 indy_local0_irqdispatch(); 247 indy_local0_irqdispatch();
249 else if (pending & CAUSEF_IP3) 248 else if (pending & CAUSEF_IP3)
@@ -345,6 +344,6 @@ void __init arch_init_irq(void)
345 344
346#ifdef CONFIG_EISA 345#ifdef CONFIG_EISA
347 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */ 346 if (ip22_is_fullhouse()) /* Only Indigo-2 has EISA stuff */
348 ip22_eisa_init (); 347 ip22_eisa_init();
349#endif 348#endif
350} 349}
diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c
index e7ce7982db72..174f09e42f6b 100644
--- a/arch/mips/sgi-ip22/ip22-setup.c
+++ b/arch/mips/sgi-ip22/ip22-setup.c
@@ -51,7 +51,6 @@ void ip22_do_break(void)
51EXPORT_SYMBOL(ip22_do_break); 51EXPORT_SYMBOL(ip22_do_break);
52 52
53extern void ip22_be_init(void) __init; 53extern void ip22_be_init(void) __init;
54extern void ip22_time_init(void) __init;
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
57{ 56{
@@ -59,7 +58,6 @@ void __init plat_mem_setup(void)
59 char *cserial; 58 char *cserial;
60 59
61 board_be_init = ip22_be_init; 60 board_be_init = ip22_be_init;
62 ip22_time_init();
63 61
64 /* Init the INDY HPC I/O controller. Need to call this before 62 /* Init the INDY HPC I/O controller. Need to call this before
65 * fucking with the memory controller because it needs to know the 63 * fucking with the memory controller because it needs to know the
diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c
index de3d01823ad5..9b9bffd2e8fb 100644
--- a/arch/mips/sgi-ip22/ip22-time.c
+++ b/arch/mips/sgi-ip22/ip22-time.c
@@ -20,6 +20,7 @@
20 20
21#include <asm/cpu.h> 21#include <asm/cpu.h>
22#include <asm/mipsregs.h> 22#include <asm/mipsregs.h>
23#include <asm/i8253.h>
23#include <asm/io.h> 24#include <asm/io.h>
24#include <asm/irq.h> 25#include <asm/irq.h>
25#include <asm/time.h> 26#include <asm/time.h>
@@ -29,10 +30,10 @@
29#include <asm/sgi/ip22.h> 30#include <asm/sgi/ip22.h>
30 31
31/* 32/*
32 * note that mktime uses month from 1 to 12 while to_tm 33 * Note that mktime uses month from 1 to 12 while rtc_time_to_tm
33 * uses 0 to 11. 34 * uses 0 to 11.
34 */ 35 */
35static unsigned long indy_rtc_get_time(void) 36unsigned long read_persistent_clock(void)
36{ 37{
37 unsigned int yrs, mon, day, hrs, min, sec; 38 unsigned int yrs, mon, day, hrs, min, sec;
38 unsigned int save_control; 39 unsigned int save_control;
@@ -60,16 +61,16 @@ static unsigned long indy_rtc_get_time(void)
60 return mktime(yrs + 1900, mon, day, hrs, min, sec); 61 return mktime(yrs + 1900, mon, day, hrs, min, sec);
61} 62}
62 63
63static int indy_rtc_set_time(unsigned long tim) 64int rtc_mips_set_time(unsigned long tim)
64{ 65{
65 struct rtc_time tm; 66 struct rtc_time tm;
66 unsigned int save_control; 67 unsigned int save_control;
67 unsigned long flags; 68 unsigned long flags;
68 69
69 to_tm(tim, &tm); 70 rtc_time_to_tm(tim, &tm);
70 71
71 tm.tm_mon += 1; /* tm_mon starts at zero */ 72 tm.tm_mon += 1; /* tm_mon starts at zero */
72 tm.tm_year -= 1940; 73 tm.tm_year -= 40;
73 if (tm.tm_year >= 100) 74 if (tm.tm_year >= 100)
74 tm.tm_year -= 100; 75 tm.tm_year -= 100;
75 76
@@ -128,7 +129,7 @@ static unsigned long dosample(void)
128/* 129/*
129 * Here we need to calibrate the cycle counter to at least be close. 130 * Here we need to calibrate the cycle counter to at least be close.
130 */ 131 */
131static __init void indy_time_init(void) 132__init void plat_time_init(void)
132{ 133{
133 unsigned long r4k_ticks[3]; 134 unsigned long r4k_ticks[3];
134 unsigned long r4k_tick; 135 unsigned long r4k_tick;
@@ -172,6 +173,9 @@ static __init void indy_time_init(void)
172 (int) (r4k_tick % (500000 / HZ))); 173 (int) (r4k_tick % (500000 / HZ)));
173 174
174 mips_hpt_frequency = r4k_tick * HZ; 175 mips_hpt_frequency = r4k_tick * HZ;
176
177 if (ip22_is_fullhouse())
178 setup_pit_timer();
175} 179}
176 180
177/* Generic SGI handler for (spurious) 8254 interrupts */ 181/* Generic SGI handler for (spurious) 8254 interrupts */
@@ -189,16 +193,6 @@ void indy_8254timer_irq(void)
189 irq_exit(); 193 irq_exit();
190} 194}
191 195
192void indy_r4k_timer_interrupt(void)
193{
194 int irq = SGI_TIMER_IRQ;
195
196 irq_enter();
197 kstat_this_cpu.irqs[irq]++;
198 timer_interrupt(irq, NULL);
199 irq_exit();
200}
201
202void __init plat_timer_setup(struct irqaction *irq) 196void __init plat_timer_setup(struct irqaction *irq)
203{ 197{
204 /* over-write the handler, we use our own way */ 198 /* over-write the handler, we use our own way */
@@ -207,12 +201,3 @@ void __init plat_timer_setup(struct irqaction *irq)
207 /* setup irqaction */ 201 /* setup irqaction */
208 setup_irq(SGI_TIMER_IRQ, irq); 202 setup_irq(SGI_TIMER_IRQ, irq);
209} 203}
210
211void __init ip22_time_init(void)
212{
213 /* setup hookup functions */
214 rtc_mips_get_time = indy_rtc_get_time;
215 rtc_mips_set_time = indy_rtc_set_time;
216
217 board_time_init = indy_time_init;
218}
diff --git a/arch/mips/sgi-ip27/ip27-berr.c b/arch/mips/sgi-ip27/ip27-berr.c
index 123141ab21a2..7d05e68fdc77 100644
--- a/arch/mips/sgi-ip27/ip27-berr.c
+++ b/arch/mips/sgi-ip27/ip27-berr.c
@@ -21,8 +21,6 @@
21#include <asm/traps.h> 21#include <asm/traps.h>
22#include <asm/uaccess.h> 22#include <asm/uaccess.h>
23 23
24extern void dump_tlb_all(void);
25
26static void dump_hub_information(unsigned long errst0, unsigned long errst1) 24static void dump_hub_information(unsigned long errst0, unsigned long errst1)
27{ 25{
28 static char *err_type[2][8] = { 26 static char *err_type[2][8] = {
diff --git a/arch/mips/sgi-ip27/ip27-init.c b/arch/mips/sgi-ip27/ip27-init.c
index 74158d349630..681b593071cb 100644
--- a/arch/mips/sgi-ip27/ip27-init.c
+++ b/arch/mips/sgi-ip27/ip27-init.c
@@ -47,6 +47,9 @@ cnodeid_t cpuid_to_compact_node[MAXCPUS];
47 47
48EXPORT_SYMBOL(nasid_to_compact_node); 48EXPORT_SYMBOL(nasid_to_compact_node);
49 49
50struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
51EXPORT_SYMBOL_GPL(sn_cpu_info);
52
50extern void pcibr_setup(cnodeid_t); 53extern void pcibr_setup(cnodeid_t);
51 54
52extern void xtalk_probe_node(cnodeid_t nid); 55extern void xtalk_probe_node(cnodeid_t nid);
@@ -191,7 +194,6 @@ static inline void ioc3_eth_init(void)
191 ioc3->eier = 0; 194 ioc3->eier = 0;
192} 195}
193 196
194extern void ip27_time_init(void);
195extern void ip27_reboot_setup(void); 197extern void ip27_reboot_setup(void);
196 198
197void __init plat_mem_setup(void) 199void __init plat_mem_setup(void)
@@ -238,6 +240,4 @@ void __init plat_mem_setup(void)
238 per_cpu_init(); 240 per_cpu_init();
239 241
240 set_io_port_base(IO_BASE); 242 set_io_port_base(IO_BASE);
241
242 board_time_init = ip27_time_init;
243} 243}
diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c
index fbb27728a76a..a70656d42191 100644
--- a/arch/mips/sgi-ip27/ip27-smp.c
+++ b/arch/mips/sgi-ip27/ip27-smp.c
@@ -33,7 +33,7 @@ static void alloc_cpupda(cpuid_t cpu, int cpunum)
33 nasid_t nasid = COMPACT_TO_NASID_NODEID(node); 33 nasid_t nasid = COMPACT_TO_NASID_NODEID(node);
34 34
35 cputonasid(cpunum) = nasid; 35 cputonasid(cpunum) = nasid;
36 cpu_data[cpunum].p_nodeid = node; 36 sn_cpu_info[cpunum].p_nodeid = node;
37 cputoslice(cpunum) = get_cpu_slice(cpu); 37 cputoslice(cpunum) = get_cpu_slice(cpu);
38} 38}
39 39
@@ -176,7 +176,7 @@ void __cpuinit prom_boot_secondary(int cpu, struct task_struct *idle)
176 unsigned long gp = (unsigned long)task_thread_info(idle); 176 unsigned long gp = (unsigned long)task_thread_info(idle);
177 unsigned long sp = __KSTK_TOS(idle); 177 unsigned long sp = __KSTK_TOS(idle);
178 178
179 LAUNCH_SLAVE(cputonasid(cpu),cputoslice(cpu), 179 LAUNCH_SLAVE(cputonasid(cpu), cputoslice(cpu),
180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap), 180 (launch_proc_t)MAPPED_KERN_RW_TO_K0(smp_bootstrap),
181 0, (void *) sp, (void *) gp); 181 0, (void *) sp, (void *) gp);
182} 182}
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 8c3c78c63ccd..b7b3479b6bce 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -40,7 +40,6 @@
40#define TICK_SIZE (tick_nsec / 1000) 40#define TICK_SIZE (tick_nsec / 1000)
41 41
42static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */ 42static unsigned long ct_cur[NR_CPUS]; /* What counter should be at next timer irq */
43static long last_rtc_update; /* Last time the rtc clock got updated */
44 43
45#if 0 44#if 0
46static int set_rtc_mmss(unsigned long nowtime) 45static int set_rtc_mmss(unsigned long nowtime)
@@ -113,23 +112,6 @@ again:
113 112
114 update_process_times(user_mode(get_irq_regs())); 113 update_process_times(user_mode(get_irq_regs()));
115 114
116 /*
117 * If we have an externally synchronized Linux clock, then update
118 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
119 * called as close as possible to when a second starts.
120 */
121 if (ntp_synced() &&
122 xtime.tv_sec > last_rtc_update + 660 &&
123 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
124 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
125 if (rtc_mips_set_time(xtime.tv_sec) == 0) {
126 last_rtc_update = xtime.tv_sec;
127 } else {
128 last_rtc_update = xtime.tv_sec - 600;
129 /* do it again in 60 s */
130 }
131 }
132
133 write_sequnlock(&xtime_lock); 115 write_sequnlock(&xtime_lock);
134 irq_exit(); 116 irq_exit();
135} 117}
@@ -141,7 +123,7 @@ again:
141#include <asm/sn/sn0/hubio.h> 123#include <asm/sn/sn0/hubio.h>
142#include <asm/pci/bridge.h> 124#include <asm/pci/bridge.h>
143 125
144static __init unsigned long get_m48t35_time(void) 126unsigned long read_persistent_clock(void)
145{ 127{
146 unsigned int year, month, date, hour, min, sec; 128 unsigned int year, month, date, hour, min, sec;
147 struct m48t35_rtc *rtc; 129 struct m48t35_rtc *rtc;
@@ -218,17 +200,23 @@ void __init plat_timer_setup(struct irqaction *irq)
218 setup_irq(irqno, &rt_irqaction); 200 setup_irq(irqno, &rt_irqaction);
219} 201}
220 202
221static cycle_t ip27_hpt_read(void) 203static cycle_t hub_rt_read(void)
222{ 204{
223 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT); 205 return REMOTE_HUB_L(cputonasid(0), PI_RT_COUNT);
224} 206}
225 207
226void __init ip27_time_init(void) 208struct clocksource ht_rt_clocksource = {
209 .name = "HUB",
210 .rating = 200,
211 .read = hub_rt_read,
212 .mask = CLOCKSOURCE_MASK(52),
213 .shift = 32,
214 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
215};
216
217void __init plat_time_init(void)
227{ 218{
228 clocksource_mips.read = ip27_hpt_read; 219 clocksource_register(&ht_rt_clocksource);
229 mips_hpt_frequency = CYCLES_PER_SEC;
230 xtime.tv_sec = get_m48t35_time();
231 xtime.tv_nsec = 0;
232} 220}
233 221
234void __init cpu_time_init(void) 222void __init cpu_time_init(void)
diff --git a/arch/mips/sgi-ip32/crime.c b/arch/mips/sgi-ip32/crime.c
index bff508704d03..563c614ad021 100644
--- a/arch/mips/sgi-ip32/crime.c
+++ b/arch/mips/sgi-ip32/crime.c
@@ -35,8 +35,8 @@ void __init crime_init(void)
35 id = crime->id; 35 id = crime->id;
36 rev = id & CRIME_ID_REV; 36 rev = id & CRIME_ID_REV;
37 id = (id & CRIME_ID_IDBITS) >> 4; 37 id = (id & CRIME_ID_IDBITS) >> 4;
38 printk (KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n", 38 printk(KERN_INFO "CRIME id %1x rev %d at 0x%0*lx\n",
39 id, rev, field, (unsigned long) CRIME_BASE); 39 id, rev, field, (unsigned long) CRIME_BASE);
40} 40}
41 41
42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id) 42irqreturn_t crime_memerr_intr(unsigned int irq, void *dev_id)
@@ -96,7 +96,7 @@ irqreturn_t crime_cpuerr_intr(unsigned int irq, void *dev_id)
96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK; 96 unsigned long addr = crime->cpu_error_addr & CRIME_CPU_ERROR_ADDR_MASK;
97 97
98 addr <<= 2; 98 addr <<= 2;
99 printk ("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat); 99 printk("CRIME CPU error at 0x%09lx status 0x%08lx\n", addr, stat);
100 crime->cpu_error_stat = 0; 100 crime->cpu_error_stat = 0;
101 101
102 return IRQ_HANDLED; 102 return IRQ_HANDLED;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index fb9da9acf53f..7f4b793c3df3 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -117,10 +117,18 @@ static void inline flush_mace_bus(void)
117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
119 119
120struct irqaction memerr_irq = { crime_memerr_intr, IRQF_DISABLED, 120struct irqaction memerr_irq = {
121 CPU_MASK_NONE, "CRIME memory error", NULL, NULL }; 121 .handler = crime_memerr_intr,
122struct irqaction cpuerr_irq = { crime_cpuerr_intr, IRQF_DISABLED, 122 .flags = IRQF_DISABLED,
123 CPU_MASK_NONE, "CRIME CPU error", NULL, NULL }; 123 .mask = CPU_MASK_NONE,
124 .name = "CRIME memory error",
125};
126struct irqaction cpuerr_irq = {
127 .handler = crime_cpuerr_intr,
128 .flags = IRQF_DISABLED,
129 .mask = CPU_MASK_NONE,
130 .name = "CRIME CPU error",
131};
124 132
125/* 133/*
126 * For interrupts wired from a single device to the CPU. Only the clock 134 * For interrupts wired from a single device to the CPU. Only the clock
@@ -140,7 +148,7 @@ static void disable_cpu_irq(unsigned int irq)
140static void end_cpu_irq(unsigned int irq) 148static void end_cpu_irq(unsigned int irq)
141{ 149{
142 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 150 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
143 enable_cpu_irq (irq); 151 enable_cpu_irq(irq);
144} 152}
145 153
146static struct irq_chip ip32_cpu_interrupt = { 154static struct irq_chip ip32_cpu_interrupt = {
@@ -281,11 +289,11 @@ static struct irq_chip ip32_macepci_interrupt = {
281 289
282static unsigned long maceisa_mask; 290static unsigned long maceisa_mask;
283 291
284static void enable_maceisa_irq (unsigned int irq) 292static void enable_maceisa_irq(unsigned int irq)
285{ 293{
286 unsigned int crime_int = 0; 294 unsigned int crime_int = 0;
287 295
288 DBG ("maceisa enable: %u\n", irq); 296 DBG("maceisa enable: %u\n", irq);
289 297
290 switch (irq) { 298 switch (irq) {
291 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ: 299 case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
@@ -298,7 +306,7 @@ static void enable_maceisa_irq (unsigned int irq)
298 crime_int = MACE_SUPERIO_INT; 306 crime_int = MACE_SUPERIO_INT;
299 break; 307 break;
300 } 308 }
301 DBG ("crime_int %08x enabled\n", crime_int); 309 DBG("crime_int %08x enabled\n", crime_int);
302 crime_mask |= crime_int; 310 crime_mask |= crime_int;
303 crime->imask = crime_mask; 311 crime->imask = crime_mask;
304 maceisa_mask |= 1 << (irq - 33); 312 maceisa_mask |= 1 << (irq - 33);
@@ -389,15 +397,15 @@ static struct irq_chip ip32_mace_interrupt = {
389 397
390static void ip32_unknown_interrupt(void) 398static void ip32_unknown_interrupt(void)
391{ 399{
392 printk ("Unknown interrupt occurred!\n"); 400 printk("Unknown interrupt occurred!\n");
393 printk ("cp0_status: %08x\n", read_c0_status()); 401 printk("cp0_status: %08x\n", read_c0_status());
394 printk ("cp0_cause: %08x\n", read_c0_cause()); 402 printk("cp0_cause: %08x\n", read_c0_cause());
395 printk ("CRIME intr mask: %016lx\n", crime->imask); 403 printk("CRIME intr mask: %016lx\n", crime->imask);
396 printk ("CRIME intr status: %016lx\n", crime->istat); 404 printk("CRIME intr status: %016lx\n", crime->istat);
397 printk ("CRIME hardware intr register: %016lx\n", crime->hard_int); 405 printk("CRIME hardware intr register: %016lx\n", crime->hard_int);
398 printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask); 406 printk("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
399 printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat); 407 printk("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
400 printk ("MACE PCI control register: %08x\n", mace->pci.control); 408 printk("MACE PCI control register: %08x\n", mace->pci.control);
401 409
402 printk("Register dump:\n"); 410 printk("Register dump:\n");
403 show_regs(get_irq_regs()); 411 show_regs(get_irq_regs());
@@ -449,7 +457,7 @@ static void ip32_irq4(void)
449 457
450static void ip32_irq5(void) 458static void ip32_irq5(void)
451{ 459{
452 ll_timer_interrupt(IP32_R4K_TIMER_IRQ); 460 do_IRQ(IP32_R4K_TIMER_IRQ);
453} 461}
454 462
455asmlinkage void plat_irq_dispatch(void) 463asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/sgi-ip32/ip32-memory.c b/arch/mips/sgi-ip32/ip32-memory.c
index 849d392a0013..ca93ecf825ae 100644
--- a/arch/mips/sgi-ip32/ip32-memory.c
+++ b/arch/mips/sgi-ip32/ip32-memory.c
@@ -19,7 +19,7 @@
19 19
20extern void crime_init(void); 20extern void crime_init(void);
21 21
22void __init prom_meminit (void) 22void __init prom_meminit(void)
23{ 23{
24 u64 base, size; 24 u64 base, size;
25 int bank; 25 int bank;
@@ -38,7 +38,7 @@ void __init prom_meminit (void)
38 38
39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n", 39 printk("CRIME MC: bank %u base 0x%016lx size %luMiB\n",
40 bank, base, size >> 20); 40 bank, base, size >> 20);
41 add_memory_region (base, size, BOOT_MEM_RAM); 41 add_memory_region(base, size, BOOT_MEM_RAM);
42 } 42 }
43} 43}
44 44
diff --git a/arch/mips/sgi-ip32/ip32-setup.c b/arch/mips/sgi-ip32/ip32-setup.c
index bbba066cb405..4125a5ba119e 100644
--- a/arch/mips/sgi-ip32/ip32-setup.c
+++ b/arch/mips/sgi-ip32/ip32-setup.c
@@ -62,10 +62,15 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str)
62} 62}
63#endif 63#endif
64 64
65unsigned long read_persistent_clock(void)
66{
67 return mc146818_get_cmos_time();
68}
69
65/* An arbitrary time; this can be decreased if reliability looks good */ 70/* An arbitrary time; this can be decreased if reliability looks good */
66#define WAIT_MS 10 71#define WAIT_MS 10
67 72
68void __init ip32_time_init(void) 73void __init plat_time_init(void)
69{ 74{
70 printk(KERN_INFO "Calibrating system timer... "); 75 printk(KERN_INFO "Calibrating system timer... ");
71 write_c0_count(0); 76 write_c0_count(0);
@@ -85,11 +90,6 @@ void __init plat_mem_setup(void)
85{ 90{
86 board_be_init = ip32_be_init; 91 board_be_init = ip32_be_init;
87 92
88 rtc_mips_get_time = mc146818_get_cmos_time;
89 rtc_mips_set_mmss = mc146818_set_rtc_mmss;
90
91 board_time_init = ip32_time_init;
92
93#ifdef CONFIG_SGI_O2MACE_ETH 93#ifdef CONFIG_SGI_O2MACE_ETH
94 { 94 {
95 char *mac = ArcGetEnvironmentVariable("eaddr"); 95 char *mac = ArcGetEnvironmentVariable("eaddr");
diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig
index fdd7bd98fb44..e8fb880272bd 100644
--- a/arch/mips/sibyte/Kconfig
+++ b/arch/mips/sibyte/Kconfig
@@ -1,6 +1,7 @@
1config SIBYTE_SB1250 1config SIBYTE_SB1250
2 bool 2 bool
3 select HW_HAS_PCI 3 select HW_HAS_PCI
4 select IRQ_CPU
4 select SIBYTE_ENABLE_LDT_IF_PCI 5 select SIBYTE_ENABLE_LDT_IF_PCI
5 select SIBYTE_HAS_ZBUS_PROFILING 6 select SIBYTE_HAS_ZBUS_PROFILING
6 select SIBYTE_SB1xxx_SOC 7 select SIBYTE_SB1xxx_SOC
@@ -8,6 +9,7 @@ config SIBYTE_SB1250
8 9
9config SIBYTE_BCM1120 10config SIBYTE_BCM1120
10 bool 11 bool
12 select IRQ_CPU
11 select SIBYTE_BCM112X 13 select SIBYTE_BCM112X
12 select SIBYTE_HAS_ZBUS_PROFILING 14 select SIBYTE_HAS_ZBUS_PROFILING
13 select SIBYTE_SB1xxx_SOC 15 select SIBYTE_SB1xxx_SOC
@@ -15,6 +17,7 @@ config SIBYTE_BCM1120
15config SIBYTE_BCM1125 17config SIBYTE_BCM1125
16 bool 18 bool
17 select HW_HAS_PCI 19 select HW_HAS_PCI
20 select IRQ_CPU
18 select SIBYTE_BCM112X 21 select SIBYTE_BCM112X
19 select SIBYTE_HAS_ZBUS_PROFILING 22 select SIBYTE_HAS_ZBUS_PROFILING
20 select SIBYTE_SB1xxx_SOC 23 select SIBYTE_SB1xxx_SOC
@@ -22,6 +25,7 @@ config SIBYTE_BCM1125
22config SIBYTE_BCM1125H 25config SIBYTE_BCM1125H
23 bool 26 bool
24 select HW_HAS_PCI 27 select HW_HAS_PCI
28 select IRQ_CPU
25 select SIBYTE_BCM112X 29 select SIBYTE_BCM112X
26 select SIBYTE_ENABLE_LDT_IF_PCI 30 select SIBYTE_ENABLE_LDT_IF_PCI
27 select SIBYTE_HAS_ZBUS_PROFILING 31 select SIBYTE_HAS_ZBUS_PROFILING
@@ -29,12 +33,14 @@ config SIBYTE_BCM1125H
29 33
30config SIBYTE_BCM112X 34config SIBYTE_BCM112X
31 bool 35 bool
36 select IRQ_CPU
32 select SIBYTE_SB1xxx_SOC 37 select SIBYTE_SB1xxx_SOC
33 select SIBYTE_HAS_ZBUS_PROFILING 38 select SIBYTE_HAS_ZBUS_PROFILING
34 39
35config SIBYTE_BCM1x80 40config SIBYTE_BCM1x80
36 bool 41 bool
37 select HW_HAS_PCI 42 select HW_HAS_PCI
43 select IRQ_CPU
38 select SIBYTE_HAS_ZBUS_PROFILING 44 select SIBYTE_HAS_ZBUS_PROFILING
39 select SIBYTE_SB1xxx_SOC 45 select SIBYTE_SB1xxx_SOC
40 select SYS_SUPPORTS_SMP 46 select SYS_SUPPORTS_SMP
@@ -42,6 +48,7 @@ config SIBYTE_BCM1x80
42config SIBYTE_BCM1x55 48config SIBYTE_BCM1x55
43 bool 49 bool
44 select HW_HAS_PCI 50 select HW_HAS_PCI
51 select IRQ_CPU
45 select SIBYTE_SB1xxx_SOC 52 select SIBYTE_SB1xxx_SOC
46 select SIBYTE_HAS_ZBUS_PROFILING 53 select SIBYTE_HAS_ZBUS_PROFILING
47 select SYS_SUPPORTS_SMP 54 select SYS_SUPPORTS_SMP
@@ -49,6 +56,7 @@ config SIBYTE_BCM1x55
49config SIBYTE_SB1xxx_SOC 56config SIBYTE_SB1xxx_SOC
50 bool 57 bool
51 select DMA_COHERENT 58 select DMA_COHERENT
59 select IRQ_CPU
52 select SIBYTE_CFE 60 select SIBYTE_CFE
53 select SWAP_IO_SPACE 61 select SWAP_IO_SPACE
54 select SYS_SUPPORTS_32BIT_KERNEL 62 select SYS_SUPPORTS_32BIT_KERNEL
@@ -124,6 +132,7 @@ config SB1_CERR_STALL
124config SIBYTE_CFE 132config SIBYTE_CFE
125 bool "Booting from CFE" 133 bool "Booting from CFE"
126 depends on SIBYTE_SB1xxx_SOC 134 depends on SIBYTE_SB1xxx_SOC
135 select CFE
127 select SYS_HAS_EARLY_PRINTK 136 select SYS_HAS_EARLY_PRINTK
128 help 137 help
129 Make use of the CFE API for enumerating available memory, 138 Make use of the CFE API for enumerating available memory,
@@ -165,10 +174,6 @@ config SIBYTE_BW_TRACE
165 buffer activity. Raw buffer data is dumped to console, and 174 buffer activity. Raw buffer data is dumped to console, and
166 must be processed off-line. 175 must be processed off-line.
167 176
168config SIBYTE_SB1250_PROF
169 bool "Support for SB1/SOC profiling - SB1/SCD perf counters"
170 depends on SIBYTE_SB1xxx_SOC
171
172config SIBYTE_TBPROF 177config SIBYTE_TBPROF
173 tristate "Support for ZBbus profiling" 178 tristate "Support for ZBbus profiling"
174 depends on SIBYTE_HAS_ZBUS_PROFILING 179 depends on SIBYTE_HAS_ZBUS_PROFILING
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index e729b5f30264..7aa79bf63c4a 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -289,7 +289,7 @@ int bcm1480_steal_irq(int irq)
289 if (irq >= BCM1480_NR_IRQS) 289 if (irq >= BCM1480_NR_IRQS)
290 return -EINVAL; 290 return -EINVAL;
291 291
292 spin_lock_irqsave(&desc->lock,flags); 292 spin_lock_irqsave(&desc->lock, flags);
293 /* Don't allow sharing at all for these */ 293 /* Don't allow sharing at all for these */
294 if (desc->action != NULL) 294 if (desc->action != NULL)
295 retval = -EBUSY; 295 retval = -EBUSY;
@@ -297,7 +297,7 @@ int bcm1480_steal_irq(int irq)
297 desc->action = &bcm1480_dummy_action; 297 desc->action = &bcm1480_dummy_action;
298 desc->depth = 0; 298 desc->depth = 0;
299 } 299 }
300 spin_unlock_irqrestore(&desc->lock,flags); 300 spin_unlock_irqrestore(&desc->lock, flags);
301 return 0; 301 return 0;
302} 302}
303 303
@@ -431,8 +431,8 @@ void __init arch_init_irq(void)
431 431
432#include <linux/delay.h> 432#include <linux/delay.h>
433 433
434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 434#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 435#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
436 436
437static void bcm1480_kgdb_interrupt(void) 437static void bcm1480_kgdb_interrupt(void)
438{ 438{
@@ -450,7 +450,6 @@ static void bcm1480_kgdb_interrupt(void)
450 450
451#endif /* CONFIG_KGDB */ 451#endif /* CONFIG_KGDB */
452 452
453extern void bcm1480_timer_interrupt(void);
454extern void bcm1480_mailbox_interrupt(void); 453extern void bcm1480_mailbox_interrupt(void);
455 454
456asmlinkage void plat_irq_dispatch(void) 455asmlinkage void plat_irq_dispatch(void)
@@ -470,8 +469,16 @@ asmlinkage void plat_irq_dispatch(void)
470 else 469 else
471#endif 470#endif
472 471
473 if (pending & CAUSEF_IP4) 472 if (pending & CAUSEF_IP4) {
474 bcm1480_timer_interrupt(); 473 int cpu = smp_processor_id();
474 int irq = K_BCM1480_INT_TIMER_0 + cpu;
475
476 /* Reset the timer */
477 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
478 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
479
480 do_IRQ(irq);
481 }
475 482
476#ifdef CONFIG_SMP 483#ifdef CONFIG_SMP
477 else if (pending & CAUSEF_IP3) 484 else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/bcm1480/setup.c b/arch/mips/sibyte/bcm1480/setup.c
index 7e1aa348b8e0..05ed92c92b69 100644
--- a/arch/mips/sibyte/bcm1480/setup.c
+++ b/arch/mips/sibyte/bcm1480/setup.c
@@ -43,16 +43,49 @@ static unsigned int part_type;
43static char *soc_str; 43static char *soc_str;
44static char *pass_str; 44static char *pass_str;
45 45
46static inline int setup_bcm1x80_bcm1x55(void); 46static int __init setup_bcm1x80_bcm1x55(void)
47{
48 int ret = 0;
49
50 switch (soc_pass) {
51 case K_SYS_REVISION_BCM1480_S0:
52 periph_rev = 1;
53 pass_str = "S0 (pass1)";
54 break;
55 case K_SYS_REVISION_BCM1480_A1:
56 periph_rev = 1;
57 pass_str = "A1 (pass1)";
58 break;
59 case K_SYS_REVISION_BCM1480_A2:
60 periph_rev = 1;
61 pass_str = "A2 (pass1)";
62 break;
63 case K_SYS_REVISION_BCM1480_A3:
64 periph_rev = 1;
65 pass_str = "A3 (pass1)";
66 break;
67 case K_SYS_REVISION_BCM1480_B0:
68 periph_rev = 1;
69 pass_str = "B0 (pass2)";
70 break;
71 default:
72 printk("Unknown %s rev %x\n", soc_str, soc_pass);
73 periph_rev = 1;
74 pass_str = "Unknown Revision";
75 break;
76 }
77
78 return ret;
79}
47 80
48/* Setup code likely to be common to all SiByte platforms */ 81/* Setup code likely to be common to all SiByte platforms */
49 82
50static inline int sys_rev_decode(void) 83static int __init sys_rev_decode(void)
51{ 84{
52 int ret = 0; 85 int ret = 0;
53 86
54 switch (soc_type) { 87 switch (soc_type) {
55 case K_SYS_SOC_TYPE_BCM1x80: 88 case K_SYS_SOC_TYPE_BCM1x80:
56 if (part_type == K_SYS_PART_BCM1480) 89 if (part_type == K_SYS_PART_BCM1480)
57 soc_str = "BCM1480"; 90 soc_str = "BCM1480";
58 else if (part_type == K_SYS_PART_BCM1280) 91 else if (part_type == K_SYS_PART_BCM1280)
@@ -62,7 +95,7 @@ static inline int sys_rev_decode(void)
62 ret = setup_bcm1x80_bcm1x55(); 95 ret = setup_bcm1x80_bcm1x55();
63 break; 96 break;
64 97
65 case K_SYS_SOC_TYPE_BCM1x55: 98 case K_SYS_SOC_TYPE_BCM1x55:
66 if (part_type == K_SYS_PART_BCM1455) 99 if (part_type == K_SYS_PART_BCM1455)
67 soc_str = "BCM1455"; 100 soc_str = "BCM1455";
68 else if (part_type == K_SYS_PART_BCM1255) 101 else if (part_type == K_SYS_PART_BCM1255)
@@ -72,49 +105,16 @@ static inline int sys_rev_decode(void)
72 ret = setup_bcm1x80_bcm1x55(); 105 ret = setup_bcm1x80_bcm1x55();
73 break; 106 break;
74 107
75 default: 108 default:
76 printk("Unknown part type %x\n", part_type); 109 printk("Unknown part type %x\n", part_type);
77 ret = 1; 110 ret = 1;
78 break; 111 break;
79 } 112 }
80 return ret;
81}
82 113
83static inline int setup_bcm1x80_bcm1x55(void)
84{
85 int ret = 0;
86
87 switch (soc_pass) {
88 case K_SYS_REVISION_BCM1480_S0:
89 periph_rev = 1;
90 pass_str = "S0 (pass1)";
91 break;
92 case K_SYS_REVISION_BCM1480_A1:
93 periph_rev = 1;
94 pass_str = "A1 (pass1)";
95 break;
96 case K_SYS_REVISION_BCM1480_A2:
97 periph_rev = 1;
98 pass_str = "A2 (pass1)";
99 break;
100 case K_SYS_REVISION_BCM1480_A3:
101 periph_rev = 1;
102 pass_str = "A3 (pass1)";
103 break;
104 case K_SYS_REVISION_BCM1480_B0:
105 periph_rev = 1;
106 pass_str = "B0 (pass2)";
107 break;
108 default:
109 printk("Unknown %s rev %x\n", soc_str, soc_pass);
110 periph_rev = 1;
111 pass_str = "Unknown Revision";
112 break;
113 }
114 return ret; 114 return ret;
115} 115}
116 116
117void bcm1480_setup(void) 117void __init bcm1480_setup(void)
118{ 118{
119 uint64_t sys_rev; 119 uint64_t sys_rev;
120 int plldiv; 120 int plldiv;
diff --git a/arch/mips/sibyte/bcm1480/time.c b/arch/mips/sibyte/bcm1480/time.c
index 6f3f71bf4244..40d7126cd5bf 100644
--- a/arch/mips/sibyte/bcm1480/time.c
+++ b/arch/mips/sibyte/bcm1480/time.c
@@ -25,6 +25,7 @@
25 * code to do general bookkeeping (e.g. update jiffies, run 25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.) 26 * bottom halves, etc.)
27 */ 27 */
28#include <linux/clockchips.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/sched.h> 30#include <linux/sched.h>
30#include <linux/spinlock.h> 31#include <linux/spinlock.h>
@@ -55,15 +56,12 @@
55 56
56extern int bcm1480_steal_irq(int irq); 57extern int bcm1480_steal_irq(int irq);
57 58
58void bcm1480_time_init(void) 59void __init plat_time_init(void)
59{ 60{
60 int cpu = smp_processor_id(); 61 unsigned int cpu = smp_processor_id();
61 int irq = K_BCM1480_INT_TIMER_0+cpu; 62 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
62 63
63 /* Only have 4 general purpose timers */ 64 BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
64 if (cpu > 3) {
65 BUG();
66 }
67 65
68 bcm1480_mask_irq(cpu, irq); 66 bcm1480_mask_irq(cpu, irq);
69 67
@@ -71,27 +69,83 @@ void bcm1480_time_init(void)
71 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) 69 __raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H)
72 + (irq<<3))); 70 + (irq<<3)));
73 71
74 /* the general purpose timer ticks at 1 Mhz independent of the rest of the system */ 72 bcm1480_unmask_irq(cpu, irq);
75 /* Disable the timer and set up the count */ 73 bcm1480_steal_irq(irq);
76 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 74}
77 __raw_writeq( 75
78 BCM1480_HPT_VALUE/HZ 76/*
79 , IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); 77 * The general purpose timer ticks at 1 Mhz independent if
78 * the rest of the system
79 */
80static void sibyte_set_mode(enum clock_event_mode mode,
81 struct clock_event_device *evt)
82{
83 unsigned int cpu = smp_processor_id();
84 void __iomem *timer_cfg, *timer_init;
85
86 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
87 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
88
89 switch (mode) {
90 case CLOCK_EVT_MODE_PERIODIC:
91 __raw_writeq(0, timer_cfg);
92 __raw_writeq(BCM1480_HPT_VALUE / HZ - 1, timer_init);
93 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
94 timer_cfg);
95 break;
96
97 case CLOCK_EVT_MODE_ONESHOT:
98 /* Stop the timer until we actually program a shot */
99 case CLOCK_EVT_MODE_SHUTDOWN:
100 __raw_writeq(0, timer_cfg);
101 break;
102
103 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
104 ;
105 }
106}
107
108struct clock_event_device sibyte_hpt_clockevent = {
109 .name = "bcm1480-counter",
110 .features = CLOCK_EVT_FEAT_PERIODIC,
111 .set_mode = sibyte_set_mode,
112 .shift = 32,
113 .irq = 0,
114};
115
116static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
117{
118 struct clock_event_device *cd = &sibyte_hpt_clockevent;
119 unsigned int cpu = smp_processor_id();
80 120
81 /* Set the timer running */ 121 /* Reset the timer */
82 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 122 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
83 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 123 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
124 cd->event_handler(cd);
84 125
85 bcm1480_unmask_irq(cpu, irq); 126 return IRQ_HANDLED;
86 bcm1480_steal_irq(irq); 127}
87 /* 128
88 * This interrupt is "special" in that it doesn't use the request_irq 129static struct irqaction sibyte_counter_irqaction = {
89 * way to hook the irq line. The timer interrupt is initialized early 130 .handler = sibyte_counter_handler,
90 * enough to make this a major pain, and it's also firing enough to 131 .flags = IRQF_DISABLED | IRQF_PERCPU,
91 * warrant a bit of special case code. bcm1480_timer_interrupt is 132 .name = "timer",
92 * called directly from irq_handler.S when IP[4] is set during an 133};
93 * interrupt 134
94 */ 135/*
136 * This interrupt is "special" in that it doesn't use the request_irq
137 * way to hook the irq line. The timer interrupt is initialized early
138 * enough to make this a major pain, and it's also firing enough to
139 * warrant a bit of special case code. bcm1480_timer_interrupt is
140 * called directly from irq_handler.S when IP[4] is set during an
141 * interrupt
142 */
143static void __init sb1480_clockevent_init(void)
144{
145 unsigned int cpu = smp_processor_id();
146 unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
147
148 setup_irq(irq, &sibyte_counter_irqaction);
95} 149}
96 150
97void bcm1480_timer_interrupt(void) 151void bcm1480_timer_interrupt(void)
@@ -103,18 +157,7 @@ void bcm1480_timer_interrupt(void)
103 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS, 157 __raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
104 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); 158 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
105 159
106 if (cpu == 0) { 160 ll_timer_interrupt(irq);
107 /*
108 * CPU 0 handles the global timer interrupt job
109 */
110 ll_timer_interrupt(irq);
111 }
112 else {
113 /*
114 * other CPUs should just do profiling and process accounting
115 */
116 ll_local_timer_interrupt(irq);
117 }
118} 161}
119 162
120static cycle_t bcm1480_hpt_read(void) 163static cycle_t bcm1480_hpt_read(void)
@@ -129,4 +172,5 @@ void __init bcm1480_hpt_setup(void)
129{ 172{
130 clocksource_mips.read = bcm1480_hpt_read; 173 clocksource_mips.read = bcm1480_hpt_read;
131 mips_hpt_frequency = BCM1480_HPT_VALUE; 174 mips_hpt_frequency = BCM1480_HPT_VALUE;
175 sb1480_clockevent_init();
132} 176}
diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile
index 059d84a1d8a8..a1214937b705 100644
--- a/arch/mips/sibyte/cfe/Makefile
+++ b/arch/mips/sibyte/cfe/Makefile
@@ -1,3 +1,3 @@
1lib-y = cfe_api.o setup.o 1lib-y = setup.o
2lib-$(CONFIG_SMP) += smp.o 2lib-$(CONFIG_SMP) += smp.o
3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o 3lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o
diff --git a/arch/mips/sibyte/cfe/cfe_api.h b/arch/mips/sibyte/cfe/cfe_api.h
deleted file mode 100644
index d8230cc53b81..000000000000
--- a/arch/mips/sibyte/cfe/cfe_api.h
+++ /dev/null
@@ -1,185 +0,0 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Device function prototypes File: cfe_api.h
24 *
25 * This file contains declarations for doing callbacks to
26 * cfe from an application. It should be the only header
27 * needed by the application to use this library
28 *
29 * Authors: Mitch Lichtenberg, Chris Demetriou
30 *
31 ********************************************************************* */
32
33#ifndef CFE_API_H
34#define CFE_API_H
35
36/*
37 * Apply customizations here for different OSes. These need to:
38 * * typedef uint64_t, int64_t, intptr_t, uintptr_t.
39 * * define cfe_strlen() if use of an existing function is desired.
40 * * define CFE_API_IMPL_NAMESPACE if API functions are to use
41 * names in the implementation namespace.
42 * Also, optionally, if the build environment does not do so automatically,
43 * CFE_API_* can be defined here as desired.
44 */
45/* Begin customization. */
46#include <linux/types.h>
47#include <linux/string.h>
48
49typedef long intptr_t;
50
51#define cfe_strlen strlen
52
53#define CFE_API_ALL
54#define CFE_API_STRLEN_CUSTOM
55/* End customization. */
56
57
58/* *********************************************************************
59 * Constants
60 ********************************************************************* */
61
62/* Seal indicating CFE's presence, passed to user program. */
63#define CFE_EPTSEAL 0x43464531
64
65#define CFE_MI_RESERVED 0 /* memory is reserved, do not use */
66#define CFE_MI_AVAILABLE 1 /* memory is available */
67
68#define CFE_FLG_WARMSTART 0x00000001
69#define CFE_FLG_FULL_ARENA 0x00000001
70#define CFE_FLG_ENV_PERMANENT 0x00000001
71
72#define CFE_CPU_CMD_START 1
73#define CFE_CPU_CMD_STOP 0
74
75#define CFE_STDHANDLE_CONSOLE 0
76
77#define CFE_DEV_NETWORK 1
78#define CFE_DEV_DISK 2
79#define CFE_DEV_FLASH 3
80#define CFE_DEV_SERIAL 4
81#define CFE_DEV_CPU 5
82#define CFE_DEV_NVRAM 6
83#define CFE_DEV_CLOCK 7
84#define CFE_DEV_OTHER 8
85#define CFE_DEV_MASK 0x0F
86
87#define CFE_CACHE_FLUSH_D 1
88#define CFE_CACHE_INVAL_I 2
89#define CFE_CACHE_INVAL_D 4
90#define CFE_CACHE_INVAL_L2 8
91
92#define CFE_FWI_64BIT 0x00000001
93#define CFE_FWI_32BIT 0x00000002
94#define CFE_FWI_RELOC 0x00000004
95#define CFE_FWI_UNCACHED 0x00000008
96#define CFE_FWI_MULTICPU 0x00000010
97#define CFE_FWI_FUNCSIM 0x00000020
98#define CFE_FWI_RTLSIM 0x00000040
99
100typedef struct {
101 int64_t fwi_version; /* major, minor, eco version */
102 int64_t fwi_totalmem; /* total installed mem */
103 int64_t fwi_flags; /* various flags */
104 int64_t fwi_boardid; /* board ID */
105 int64_t fwi_bootarea_va; /* VA of boot area */
106 int64_t fwi_bootarea_pa; /* PA of boot area */
107 int64_t fwi_bootarea_size; /* size of boot area */
108} cfe_fwinfo_t;
109
110
111/*
112 * cfe_strlen is handled specially: If already defined, it has been
113 * overridden in this environment with a standard strlen-like function.
114 */
115#ifdef cfe_strlen
116# define CFE_API_STRLEN_CUSTOM
117#else
118# ifdef CFE_API_IMPL_NAMESPACE
119# define cfe_strlen(a) __cfe_strlen(a)
120# endif
121int cfe_strlen(char *name);
122#endif
123
124/*
125 * Defines and prototypes for functions which take no arguments.
126 */
127#ifdef CFE_API_IMPL_NAMESPACE
128int64_t __cfe_getticks(void);
129#define cfe_getticks() __cfe_getticks()
130#else
131int64_t cfe_getticks(void);
132#endif
133
134/*
135 * Defines and prototypes for the rest of the functions.
136 */
137#ifdef CFE_API_IMPL_NAMESPACE
138#define cfe_close(a) __cfe_close(a)
139#define cfe_cpu_start(a,b,c,d,e) __cfe_cpu_start(a,b,c,d,e)
140#define cfe_cpu_stop(a) __cfe_cpu_stop(a)
141#define cfe_enumenv(a,b,d,e,f) __cfe_enumenv(a,b,d,e,f)
142#define cfe_enummem(a,b,c,d,e) __cfe_enummem(a,b,c,d,e)
143#define cfe_exit(a,b) __cfe_exit(a,b)
144#define cfe_flushcache(a) __cfe_cacheflush(a)
145#define cfe_getdevinfo(a) __cfe_getdevinfo(a)
146#define cfe_getenv(a,b,c) __cfe_getenv(a,b,c)
147#define cfe_getfwinfo(a) __cfe_getfwinfo(a)
148#define cfe_getstdhandle(a) __cfe_getstdhandle(a)
149#define cfe_init(a,b) __cfe_init(a,b)
150#define cfe_inpstat(a) __cfe_inpstat(a)
151#define cfe_ioctl(a,b,c,d,e,f) __cfe_ioctl(a,b,c,d,e,f)
152#define cfe_open(a) __cfe_open(a)
153#define cfe_read(a,b,c) __cfe_read(a,b,c)
154#define cfe_readblk(a,b,c,d) __cfe_readblk(a,b,c,d)
155#define cfe_setenv(a,b) __cfe_setenv(a,b)
156#define cfe_write(a,b,c) __cfe_write(a,b,c)
157#define cfe_writeblk(a,b,c,d) __cfe_writeblk(a,b,c,d)
158#endif /* CFE_API_IMPL_NAMESPACE */
159
160int cfe_close(int handle);
161int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
162int cfe_cpu_stop(int cpu);
163int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
164int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
165 uint64_t * type);
166int cfe_exit(int warm, int status);
167int cfe_flushcache(int flg);
168int cfe_getdevinfo(char *name);
169int cfe_getenv(char *name, char *dest, int destlen);
170int cfe_getfwinfo(cfe_fwinfo_t * info);
171int cfe_getstdhandle(int flg);
172int cfe_init(uint64_t handle, uint64_t ept);
173int cfe_inpstat(int handle);
174int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
175 int length, int *retlen, uint64_t offset);
176int cfe_open(char *name);
177int cfe_read(int handle, unsigned char *buffer, int length);
178int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
179 int length);
180int cfe_setenv(char *name, char *val);
181int cfe_write(int handle, unsigned char *buffer, int length);
182int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
183 int length);
184
185#endif /* CFE_API_H */
diff --git a/arch/mips/sibyte/cfe/cfe_error.h b/arch/mips/sibyte/cfe/cfe_error.h
deleted file mode 100644
index 975f00002cbe..000000000000
--- a/arch/mips/sibyte/cfe/cfe_error.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 */
18
19/* *********************************************************************
20 *
21 * Broadcom Common Firmware Environment (CFE)
22 *
23 * Error codes File: cfe_error.h
24 *
25 * CFE's global error code list is here.
26 *
27 * Author: Mitch Lichtenberg
28 *
29 ********************************************************************* */
30
31
32#define CFE_OK 0
33#define CFE_ERR -1 /* generic error */
34#define CFE_ERR_INV_COMMAND -2
35#define CFE_ERR_EOF -3
36#define CFE_ERR_IOERR -4
37#define CFE_ERR_NOMEM -5
38#define CFE_ERR_DEVNOTFOUND -6
39#define CFE_ERR_DEVOPEN -7
40#define CFE_ERR_INV_PARAM -8
41#define CFE_ERR_ENVNOTFOUND -9
42#define CFE_ERR_ENVREADONLY -10
43
44#define CFE_ERR_NOTELF -11
45#define CFE_ERR_NOT32BIT -12
46#define CFE_ERR_WRONGENDIAN -13
47#define CFE_ERR_BADELFVERS -14
48#define CFE_ERR_NOTMIPS -15
49#define CFE_ERR_BADELFFMT -16
50#define CFE_ERR_BADADDR -17
51
52#define CFE_ERR_FILENOTFOUND -18
53#define CFE_ERR_UNSUPPORTED -19
54
55#define CFE_ERR_HOSTUNKNOWN -20
56
57#define CFE_ERR_TIMEOUT -21
58
59#define CFE_ERR_PROTOCOLERR -22
60
61#define CFE_ERR_NETDOWN -23
62#define CFE_ERR_NONAMESERVER -24
63
64#define CFE_ERR_NOHANDLES -25
65#define CFE_ERR_ALREADYBOUND -26
66
67#define CFE_ERR_CANNOTSET -27
68#define CFE_ERR_NOMORE -28
69#define CFE_ERR_BADFILESYS -29
70#define CFE_ERR_FSNOTAVAIL -30
71
72#define CFE_ERR_INVBOOTBLOCK -31
73#define CFE_ERR_WRONGDEVTYPE -32
74#define CFE_ERR_BBCHECKSUM -33
75#define CFE_ERR_BOOTPROGCHKSUM -34
76
77#define CFE_ERR_LDRNOTAVAIL -35
78
79#define CFE_ERR_NOTREADY -36
80
81#define CFE_ERR_GETMEM -37
82#define CFE_ERR_SETMEM -38
83
84#define CFE_ERR_NOTCONN -39
85#define CFE_ERR_ADDRINUSE -40
diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c
index 4cec9d798d2f..81e3d54376e9 100644
--- a/arch/mips/sibyte/cfe/console.c
+++ b/arch/mips/sibyte/cfe/console.c
@@ -4,8 +4,8 @@
4 4
5#include <asm/sibyte/board.h> 5#include <asm/sibyte/board.h>
6 6
7#include "cfe_api.h" 7#include <asm/fw/cfe/cfe_api.h>
8#include "cfe_error.h" 8#include <asm/fw/cfe/cfe_error.h>
9 9
10extern int cfe_cons_handle; 10extern int cfe_cons_handle;
11 11
@@ -14,7 +14,7 @@ static void cfe_console_write(struct console *cons, const char *str,
14{ 14{
15 int i, last, written; 15 int i, last, written;
16 16
17 for (i=0,last=0; i<count; i++) { 17 for (i=0, last=0; i<count; i++) {
18 if (!str[i]) 18 if (!str[i])
19 /* XXXKW can/should this ever happen? */ 19 /* XXXKW can/should this ever happen? */
20 return; 20 return;
diff --git a/arch/mips/sibyte/cfe/setup.c b/arch/mips/sibyte/cfe/setup.c
index 51898dd1304a..dbd6e6fdd3f9 100644
--- a/arch/mips/sibyte/cfe/setup.c
+++ b/arch/mips/sibyte/cfe/setup.c
@@ -29,8 +29,8 @@
29#include <asm/reboot.h> 29#include <asm/reboot.h>
30#include <asm/sibyte/board.h> 30#include <asm/sibyte/board.h>
31 31
32#include "cfe_api.h" 32#include <asm/fw/cfe/cfe_api.h>
33#include "cfe_error.h" 33#include <asm/fw/cfe/cfe_error.h>
34 34
35/* Max ram addressable in 32-bit segments */ 35/* Max ram addressable in 32-bit segments */
36#ifdef CONFIG_64BIT 36#ifdef CONFIG_64BIT
@@ -309,7 +309,7 @@ void __init prom_init(void)
309 } 309 }
310 310
311#ifdef CONFIG_KGDB 311#ifdef CONFIG_KGDB
312 if ((arg = strstr(arcs_cmdline,"kgdb=duart")) != NULL) 312 if ((arg = strstr(arcs_cmdline, "kgdb=duart")) != NULL)
313 kgdb_port = (arg[10] == '0') ? 0 : 1; 313 kgdb_port = (arg[10] == '0') ? 0 : 1;
314 else 314 else
315 kgdb_port = 1; 315 kgdb_port = 1;
@@ -339,7 +339,6 @@ void __init prom_init(void)
339 /* Not sure this is needed, but it's the safe way. */ 339 /* Not sure this is needed, but it's the safe way. */
340 arcs_cmdline[CL_SIZE-1] = 0; 340 arcs_cmdline[CL_SIZE-1] = 0;
341 341
342 mips_machgroup = MACH_GROUP_SIBYTE;
343 prom_meminit(); 342 prom_meminit();
344} 343}
345 344
diff --git a/arch/mips/sibyte/cfe/smp.c b/arch/mips/sibyte/cfe/smp.c
index 5de4cff9d14a..534a62912f21 100644
--- a/arch/mips/sibyte/cfe/smp.c
+++ b/arch/mips/sibyte/cfe/smp.c
@@ -21,8 +21,8 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <asm/processor.h> 22#include <asm/processor.h>
23 23
24#include "cfe_api.h" 24#include <asm/fw/cfe/cfe_api.h>
25#include "cfe_error.h" 25#include <asm/fw/cfe/cfe_error.h>
26 26
27/* 27/*
28 * Use CFE to find out how many CPUs are available, setting up 28 * Use CFE to find out how many CPUs are available, setting up
diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile
index f8ae30066a05..48a91b9e5870 100644
--- a/arch/mips/sibyte/common/Makefile
+++ b/arch/mips/sibyte/common/Makefile
@@ -2,5 +2,4 @@ obj-y :=
2 2
3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o 3obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o
4 4
5EXTRA_AFLAGS := $(CFLAGS)
6EXTRA_CFLAGS += -Werror 5EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/sibyte/common/sb_tbprof.c b/arch/mips/sibyte/common/sb_tbprof.c
index 4fcdaa8ba514..63b444eaf01e 100644
--- a/arch/mips/sibyte/common/sb_tbprof.c
+++ b/arch/mips/sibyte/common/sb_tbprof.c
@@ -276,8 +276,8 @@ static int sbprof_zbprof_start(struct file *filp)
276 sbp.next_tb_sample = 0; 276 sbp.next_tb_sample = 0;
277 filp->f_pos = 0; 277 filp->f_pos = 0;
278 278
279 err = request_irq (K_INT_TRACE_FREEZE, sbprof_tb_intr, 0, 279 err = request_irq(K_INT_TRACE_FREEZE, sbprof_tb_intr, 0,
280 DEVNAME " trace freeze", &sbp); 280 DEVNAME " trace freeze", &sbp);
281 if (err) 281 if (err)
282 return -EBUSY; 282 return -EBUSY;
283 283
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index ad593a6c20be..7659174819c6 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -28,6 +28,7 @@
28#include <asm/errno.h> 28#include <asm/errno.h>
29#include <asm/signal.h> 29#include <asm/signal.h>
30#include <asm/system.h> 30#include <asm/system.h>
31#include <asm/time.h>
31#include <asm/io.h> 32#include <asm/io.h>
32 33
33#include <asm/sibyte/sb1250_regs.h> 34#include <asm/sibyte/sb1250_regs.h>
@@ -258,7 +259,7 @@ int sb1250_steal_irq(int irq)
258 if (irq >= SB1250_NR_IRQS) 259 if (irq >= SB1250_NR_IRQS)
259 return -EINVAL; 260 return -EINVAL;
260 261
261 spin_lock_irqsave(&desc->lock,flags); 262 spin_lock_irqsave(&desc->lock, flags);
262 /* Don't allow sharing at all for these */ 263 /* Don't allow sharing at all for these */
263 if (desc->action != NULL) 264 if (desc->action != NULL)
264 retval = -EBUSY; 265 retval = -EBUSY;
@@ -266,7 +267,7 @@ int sb1250_steal_irq(int irq)
266 desc->action = &sb1250_dummy_action; 267 desc->action = &sb1250_dummy_action;
267 desc->depth = 0; 268 desc->depth = 0;
268 } 269 }
269 spin_unlock_irqrestore(&desc->lock,flags); 270 spin_unlock_irqrestore(&desc->lock, flags);
270 return 0; 271 return 0;
271} 272}
272 273
@@ -380,8 +381,8 @@ void __init arch_init_irq(void)
380 381
381#include <linux/delay.h> 382#include <linux/delay.h>
382 383
383#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 384#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
384#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 385#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
385 386
386static void sb1250_kgdb_interrupt(void) 387static void sb1250_kgdb_interrupt(void)
387{ 388{
@@ -399,18 +400,45 @@ static void sb1250_kgdb_interrupt(void)
399 400
400#endif /* CONFIG_KGDB */ 401#endif /* CONFIG_KGDB */
401 402
402extern void sb1250_timer_interrupt(void); 403static inline void sb1250_timer_interrupt(void)
404{
405 int cpu = smp_processor_id();
406 int irq = K_INT_TIMER_0 + cpu;
407
408 irq_enter();
409 kstat_this_cpu.irqs[irq]++;
410
411 write_seqlock(&xtime_lock);
412
413 /* ACK interrupt */
414 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
415 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
416
417 /*
418 * call the generic timer interrupt handling
419 */
420 do_timer(1);
421
422 write_sequnlock(&xtime_lock);
423
424 /*
425 * In UP mode, we call local_timer_interrupt() to do profiling
426 * and process accouting.
427 *
428 * In SMP mode, local_timer_interrupt() is invoked by appropriate
429 * low-level local timer interrupt handler.
430 */
431 local_timer_interrupt(irq);
432
433 irq_exit();
434}
435
403extern void sb1250_mailbox_interrupt(void); 436extern void sb1250_mailbox_interrupt(void);
404 437
405asmlinkage void plat_irq_dispatch(void) 438asmlinkage void plat_irq_dispatch(void)
406{ 439{
407 unsigned int pending; 440 unsigned int pending;
408 441
409#ifdef CONFIG_SIBYTE_SB1250_PROF
410 /* Set compare to count to silence count/compare timer interrupts */
411 write_c0_compare(read_c0_count());
412#endif
413
414 /* 442 /*
415 * What a pain. We have to be really careful saving the upper 32 bits 443 * What a pain. We have to be really careful saving the upper 32 bits
416 * of any * register across function calls if we don't want them 444 * of any * register across function calls if we don't want them
@@ -423,13 +451,9 @@ asmlinkage void plat_irq_dispatch(void)
423 451
424 pending = read_c0_cause() & read_c0_status() & ST0_IM; 452 pending = read_c0_cause() & read_c0_status() & ST0_IM;
425 453
426#ifdef CONFIG_SIBYTE_SB1250_PROF 454 if (pending & CAUSEF_IP7) /* CPU performance counter interrupt */
427 if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */ 455 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
428 sbprof_cpu_intr(); 456 else if (pending & CAUSEF_IP4)
429 else
430#endif
431
432 if (pending & CAUSEF_IP4)
433 sb1250_timer_interrupt(); 457 sb1250_timer_interrupt();
434 458
435#ifdef CONFIG_SMP 459#ifdef CONFIG_SMP
diff --git a/arch/mips/sibyte/sb1250/prom.c b/arch/mips/sibyte/sb1250/prom.c
index 257c4e674353..cf8f6b3de86c 100644
--- a/arch/mips/sibyte/sb1250/prom.c
+++ b/arch/mips/sibyte/sb1250/prom.c
@@ -66,7 +66,7 @@ static void prom_linux_exit(void)
66{ 66{
67#ifdef CONFIG_SMP 67#ifdef CONFIG_SMP
68 if (smp_processor_id()) { 68 if (smp_processor_id()) {
69 smp_call_function(prom_cpu0_exit,NULL,1,1); 69 smp_call_function(prom_cpu0_exit, NULL, 1, 1);
70 } 70 }
71#endif 71#endif
72 while(1); 72 while(1);
@@ -83,7 +83,6 @@ void __init prom_init(void)
83 83
84 strcpy(arcs_cmdline, "root=/dev/ram0 "); 84 strcpy(arcs_cmdline, "root=/dev/ram0 ");
85 85
86 mips_machgroup = MACH_GROUP_SIBYTE;
87 prom_meminit(); 86 prom_meminit();
88} 87}
89 88
diff --git a/arch/mips/sibyte/sb1250/setup.c b/arch/mips/sibyte/sb1250/setup.c
index 2d5c6d8b41f2..0444da1e23c2 100644
--- a/arch/mips/sibyte/sb1250/setup.c
+++ b/arch/mips/sibyte/sb1250/setup.c
@@ -40,43 +40,6 @@ static char *soc_str;
40static char *pass_str; 40static char *pass_str;
41static unsigned int war_pass; /* XXXKW don't overload PASS defines? */ 41static unsigned int war_pass; /* XXXKW don't overload PASS defines? */
42 42
43static inline int setup_bcm1250(void);
44static inline int setup_bcm112x(void);
45
46/* Setup code likely to be common to all SiByte platforms */
47
48static int __init sys_rev_decode(void)
49{
50 int ret = 0;
51
52 war_pass = soc_pass;
53 switch (soc_type) {
54 case K_SYS_SOC_TYPE_BCM1250:
55 case K_SYS_SOC_TYPE_BCM1250_ALT:
56 case K_SYS_SOC_TYPE_BCM1250_ALT2:
57 soc_str = "BCM1250";
58 ret = setup_bcm1250();
59 break;
60 case K_SYS_SOC_TYPE_BCM1120:
61 soc_str = "BCM1120";
62 ret = setup_bcm112x();
63 break;
64 case K_SYS_SOC_TYPE_BCM1125:
65 soc_str = "BCM1125";
66 ret = setup_bcm112x();
67 break;
68 case K_SYS_SOC_TYPE_BCM1125H:
69 soc_str = "BCM1125H";
70 ret = setup_bcm112x();
71 break;
72 default:
73 printk("Unknown SOC type %x\n", soc_type);
74 ret = 1;
75 break;
76 }
77 return ret;
78}
79
80static int __init setup_bcm1250(void) 43static int __init setup_bcm1250(void)
81{ 44{
82 int ret = 0; 45 int ret = 0;
@@ -120,6 +83,7 @@ static int __init setup_bcm1250(void)
120 } 83 }
121 break; 84 break;
122 } 85 }
86
123 return ret; 87 return ret;
124} 88}
125 89
@@ -158,6 +122,42 @@ static int __init setup_bcm112x(void)
158 printk("Unknown %s rev %x\n", soc_str, soc_pass); 122 printk("Unknown %s rev %x\n", soc_str, soc_pass);
159 ret = 1; 123 ret = 1;
160 } 124 }
125
126 return ret;
127}
128
129/* Setup code likely to be common to all SiByte platforms */
130
131static int __init sys_rev_decode(void)
132{
133 int ret = 0;
134
135 war_pass = soc_pass;
136 switch (soc_type) {
137 case K_SYS_SOC_TYPE_BCM1250:
138 case K_SYS_SOC_TYPE_BCM1250_ALT:
139 case K_SYS_SOC_TYPE_BCM1250_ALT2:
140 soc_str = "BCM1250";
141 ret = setup_bcm1250();
142 break;
143 case K_SYS_SOC_TYPE_BCM1120:
144 soc_str = "BCM1120";
145 ret = setup_bcm112x();
146 break;
147 case K_SYS_SOC_TYPE_BCM1125:
148 soc_str = "BCM1125";
149 ret = setup_bcm112x();
150 break;
151 case K_SYS_SOC_TYPE_BCM1125H:
152 soc_str = "BCM1125H";
153 ret = setup_bcm112x();
154 break;
155 default:
156 printk("Unknown SOC type %x\n", soc_type);
157 ret = 1;
158 break;
159 }
160
161 return ret; 161 return ret;
162} 162}
163 163
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c
index 2efffe15ff23..38199ad8fc54 100644
--- a/arch/mips/sibyte/sb1250/time.c
+++ b/arch/mips/sibyte/sb1250/time.c
@@ -25,6 +25,7 @@
25 * code to do general bookkeeping (e.g. update jiffies, run 25 * code to do general bookkeeping (e.g. update jiffies, run
26 * bottom halves, etc.) 26 * bottom halves, etc.)
27 */ 27 */
28#include <linux/clockchips.h>
28#include <linux/interrupt.h> 29#include <linux/interrupt.h>
29#include <linux/sched.h> 30#include <linux/sched.h>
30#include <linux/spinlock.h> 31#include <linux/spinlock.h>
@@ -71,16 +72,158 @@ void __init sb1250_hpt_setup(void)
71 } 72 }
72} 73}
73 74
75/*
76 * The general purpose timer ticks at 1 Mhz independent if
77 * the rest of the system
78 */
79static void sibyte_set_mode(enum clock_event_mode mode,
80 struct clock_event_device *evt)
81{
82 unsigned int cpu = smp_processor_id();
83 void __iomem *timer_cfg, *timer_init;
84
85 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
86 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
74 87
75void sb1250_time_init(void) 88 switch(mode) {
89 case CLOCK_EVT_MODE_PERIODIC:
90 __raw_writeq(0, timer_cfg);
91 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
92 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
93 timer_cfg);
94 break;
95
96 case CLOCK_EVT_MODE_ONESHOT:
97 /* Stop the timer until we actually program a shot */
98 case CLOCK_EVT_MODE_SHUTDOWN:
99 __raw_writeq(0, timer_cfg);
100 break;
101
102 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
103 ;
104 }
105}
106
107static int
108sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
76{ 109{
77 int cpu = smp_processor_id(); 110 unsigned int cpu = smp_processor_id();
78 int irq = K_INT_TIMER_0+cpu; 111 void __iomem *timer_cfg, *timer_init;
79 112
80 /* Only have 4 general purpose timers, and we use last one as hpt */ 113 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
81 if (cpu > 2) { 114 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
82 BUG(); 115
116 __raw_writeq(0, timer_cfg);
117 __raw_writeq(delta, timer_init);
118 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
119
120 return 0;
121}
122
123struct clock_event_device sibyte_hpt_clockevent = {
124 .name = "sb1250-counter",
125 .features = CLOCK_EVT_FEAT_PERIODIC,
126 .set_mode = sibyte_set_mode,
127 .set_next_event = sibyte_next_event,
128 .shift = 32,
129 .irq = 0,
130};
131
132static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
133{
134 struct clock_event_device *cd = &sibyte_hpt_clockevent;
135
136 cd->event_handler(cd);
137
138 return IRQ_HANDLED;
139}
140
141static struct irqaction sibyte_irqaction = {
142 .handler = sibyte_counter_handler,
143 .flags = IRQF_DISABLED | IRQF_PERCPU,
144 .name = "timer",
145};
146
147/*
148 * The general purpose timer ticks at 1 Mhz independent if
149 * the rest of the system
150 */
151static void sibyte_set_mode(enum clock_event_mode mode,
152 struct clock_event_device *evt)
153{
154 unsigned int cpu = smp_processor_id();
155 void __iomem *timer_cfg, *timer_init;
156
157 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
158 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
159
160 switch (mode) {
161 case CLOCK_EVT_MODE_PERIODIC:
162 __raw_writeq(0, timer_cfg);
163 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
164 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
165 timer_cfg);
166 break;
167
168 case CLOCK_EVT_MODE_ONESHOT:
169 /* Stop the timer until we actually program a shot */
170 case CLOCK_EVT_MODE_SHUTDOWN:
171 __raw_writeq(0, timer_cfg);
172 break;
173
174 case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
175 ;
83 } 176 }
177}
178
179static int
180sibyte_next_event(unsigned long delta, struct clock_event_device *evt)
181{
182 unsigned int cpu = smp_processor_id();
183 void __iomem *timer_cfg, *timer_init;
184
185 timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
186 timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
187
188 __raw_writeq(0, timer_cfg);
189 __raw_writeq(delta, timer_init);
190 __raw_writeq(M_SCD_TIMER_ENABLE, timer_cfg);
191
192 return 0;
193}
194
195struct clock_event_device sibyte_hpt_clockevent = {
196 .name = "sb1250-counter",
197 .features = CLOCK_EVT_FEAT_PERIODIC,
198 .set_mode = sibyte_set_mode,
199 .set_next_event = sibyte_next_event,
200 .shift = 32,
201 .irq = 0,
202};
203
204static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
205{
206 struct clock_event_device *cd = &sibyte_hpt_clockevent;
207
208 cd->event_handler(cd);
209
210 return IRQ_HANDLED;
211}
212
213static struct irqaction sibyte_irqaction = {
214 .handler = sibyte_counter_handler,
215 .flags = IRQF_DISABLED | IRQF_PERCPU,
216 .name = "timer",
217};
218
219static void __init sb1250_clockevent_init(void)
220{
221 struct clock_event_device *cd = &sibyte_hpt_clockevent;
222 unsigned int cpu = smp_processor_id();
223 int irq = K_INT_TIMER_0 + cpu;
224
225 /* Only have 4 general purpose timers, and we use last one as hpt */
226 BUG_ON(cpu > 2);
84 227
85 sb1250_mask_irq(cpu, irq); 228 sb1250_mask_irq(cpu, irq);
86 229
@@ -88,24 +231,11 @@ void sb1250_time_init(void)
88 __raw_writeq(IMR_IP4_VAL, 231 __raw_writeq(IMR_IP4_VAL,
89 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) + 232 IOADDR(A_IMR_REGISTER(cpu, R_IMR_INTERRUPT_MAP_BASE) +
90 (irq << 3))); 233 (irq << 3)));
91 234 cd->cpumask = cpumask_of_cpu(0);
92 /* the general purpose timer ticks at 1 Mhz independent if the rest of the system */
93 /* Disable the timer and set up the count */
94 __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
95#ifdef CONFIG_SIMULATION
96 __raw_writeq((50000 / HZ) - 1,
97 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
98#else
99 __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1,
100 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
101#endif
102
103 /* Set the timer running */
104 __raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
105 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
106 235
107 sb1250_unmask_irq(cpu, irq); 236 sb1250_unmask_irq(cpu, irq);
108 sb1250_steal_irq(irq); 237 sb1250_steal_irq(irq);
238
109 /* 239 /*
110 * This interrupt is "special" in that it doesn't use the request_irq 240 * This interrupt is "special" in that it doesn't use the request_irq
111 * way to hook the irq line. The timer interrupt is initialized early 241 * way to hook the irq line. The timer interrupt is initialized early
@@ -114,29 +244,15 @@ void sb1250_time_init(void)
114 * called directly from irq_handler.S when IP[4] is set during an 244 * called directly from irq_handler.S when IP[4] is set during an
115 * interrupt 245 * interrupt
116 */ 246 */
247 setup_irq(irq, &sibyte_irqaction);
248
249 clockevents_register_device(cd);
117} 250}
118 251
119void sb1250_timer_interrupt(void) 252void __init plat_time_init(void)
120{ 253{
121 int cpu = smp_processor_id(); 254 sb1250_clocksource_init();
122 int irq = K_INT_TIMER_0 + cpu; 255 sb1250_clockevent_init();
123
124 /* ACK interrupt */
125 ____raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
126 IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
127
128 if (cpu == 0) {
129 /*
130 * CPU 0 handles the global timer interrupt job
131 */
132 ll_timer_interrupt(irq);
133 }
134 else {
135 /*
136 * other CPUs should just do profiling and process accounting
137 */
138 ll_local_timer_interrupt(irq);
139 }
140} 256}
141 257
142/* 258/*
diff --git a/arch/mips/sibyte/swarm/dbg_io.c b/arch/mips/sibyte/swarm/dbg_io.c
index 75ce14c8eb69..b97ae3048482 100644
--- a/arch/mips/sibyte/swarm/dbg_io.c
+++ b/arch/mips/sibyte/swarm/dbg_io.c
@@ -37,8 +37,8 @@ static int duart_initialized = 0; /* 0: need to be init'ed by kgdb */
37/* -------------------- END OF CONFIG --------------------- */ 37/* -------------------- END OF CONFIG --------------------- */
38extern int kgdb_port; 38extern int kgdb_port;
39 39
40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 40#define duart_out(reg, val) csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg))) 41#define duart_in(reg) csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port, reg)))
42 42
43void putDebugChar(unsigned char c); 43void putDebugChar(unsigned char c);
44unsigned char getDebugChar(void); 44unsigned char getDebugChar(void);
diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c
index c13914bdda59..26fbff4c15b1 100644
--- a/arch/mips/sibyte/swarm/rtc_m41t81.c
+++ b/arch/mips/sibyte/swarm/rtc_m41t81.c
@@ -146,7 +146,8 @@ int m41t81_set_time(unsigned long t)
146 struct rtc_time tm; 146 struct rtc_time tm;
147 unsigned long flags; 147 unsigned long flags;
148 148
149 to_tm(t, &tm); 149 /* Note we don't care about the century */
150 rtc_time_to_tm(t, &tm);
150 151
151 /* 152 /*
152 * Note the write order matters as it ensures the correctness. 153 * Note the write order matters as it ensures the correctness.
diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c
index f4a178836415..ff3e5dabb348 100644
--- a/arch/mips/sibyte/swarm/rtc_xicor1241.c
+++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c
@@ -115,7 +115,8 @@ int xicor_set_time(unsigned long t)
115 int tmp; 115 int tmp;
116 unsigned long flags; 116 unsigned long flags;
117 117
118 to_tm(t, &tm); 118 rtc_time_to_tm(t, &tm);
119 tm.tm_year += 1900;
119 120
120 spin_lock_irqsave(&rtc_lock, flags); 121 spin_lock_irqsave(&rtc_lock, flags);
121 /* unlock writes to the CCR */ 122 /* unlock writes to the CCR */
diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c
index 83572d8f3e14..8b3ef0e4cd55 100644
--- a/arch/mips/sibyte/swarm/setup.c
+++ b/arch/mips/sibyte/swarm/setup.c
@@ -69,7 +69,7 @@ const char *get_system_type(void)
69 return "SiByte " SIBYTE_BOARD_NAME; 69 return "SiByte " SIBYTE_BOARD_NAME;
70} 70}
71 71
72void __init swarm_time_init(void) 72void __init plat_time_init(void)
73{ 73{
74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 74#if defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
75 /* Setup HPT */ 75 /* Setup HPT */
@@ -104,6 +104,44 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
104 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL); 104 return (is_fixup ? MIPS_BE_FIXUP : MIPS_BE_FATAL);
105} 105}
106 106
107enum swarm_rtc_type {
108 RTC_NONE,
109 RTC_XICOR,
110 RTC_M4LT81
111};
112
113enum swarm_rtc_type swarm_rtc_type;
114
115unsigned long read_persistent_clock(void)
116{
117 switch (swarm_rtc_type) {
118 case RTC_XICOR:
119 return xicor_get_time();
120
121 case RTC_M4LT81:
122 return m41t81_get_time();
123
124 case RTC_NONE:
125 default:
126 return mktime(2000, 1, 1, 0, 0, 0);
127 }
128}
129
130int rtc_mips_set_time(unsigned long sec)
131{
132 switch (swarm_rtc_type) {
133 case RTC_XICOR:
134 return xicor_set_time(sec);
135
136 case RTC_M4LT81:
137 return m41t81_set_time(sec);
138
139 case RTC_NONE:
140 default:
141 return -1;
142 }
143}
144
107void __init plat_mem_setup(void) 145void __init plat_mem_setup(void)
108{ 146{
109#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 147#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
@@ -116,20 +154,12 @@ void __init plat_mem_setup(void)
116 154
117 panic_timeout = 5; /* For debug. */ 155 panic_timeout = 5; /* For debug. */
118 156
119 board_time_init = swarm_time_init;
120 board_be_handler = swarm_be_handler; 157 board_be_handler = swarm_be_handler;
121 158
122 if (xicor_probe()) { 159 if (xicor_probe())
123 printk("swarm setup: Xicor 1241 RTC detected.\n"); 160 swarm_rtc_type = RTC_XICOR;
124 rtc_mips_get_time = xicor_get_time; 161 if (m41t81_probe())
125 rtc_mips_set_time = xicor_set_time; 162 swarm_rtc_type = RTC_M4LT81;
126 }
127
128 if (m41t81_probe()) {
129 printk("swarm setup: M41T81 RTC detected.\n");
130 rtc_mips_get_time = m41t81_get_time;
131 rtc_mips_set_time = m41t81_set_time;
132 }
133 163
134 printk("This kernel optimized for " 164 printk("This kernel optimized for "
135#ifdef CONFIG_SIMULATION 165#ifdef CONFIG_SIMULATION
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index acc9ba76c1a9..b74607599971 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -127,7 +127,7 @@ static u32 a20r_ack_hwint(void)
127{ 127{
128 u32 status = read_c0_status(); 128 u32 status = read_c0_status();
129 129
130 write_c0_status (status | 0x00010000); 130 write_c0_status(status | 0x00010000);
131 asm volatile( 131 asm volatile(
132 " .set push \n" 132 " .set push \n"
133 " .set noat \n" 133 " .set noat \n"
@@ -195,7 +195,7 @@ static void a20r_hwint(void)
195 u32 cause, status; 195 u32 cause, status;
196 int irq; 196 int irq;
197 197
198 clear_c0_status (IE_IRQ0); 198 clear_c0_status(IE_IRQ0);
199 status = a20r_ack_hwint(); 199 status = a20r_ack_hwint();
200 cause = read_c0_cause(); 200 cause = read_c0_cause();
201 201
@@ -213,7 +213,7 @@ void __init sni_a20r_irq_init(void)
213 set_irq_chip(i, &a20r_irq_type); 213 set_irq_chip(i, &a20r_irq_type);
214 sni_hwint = a20r_hwint; 214 sni_hwint = a20r_hwint;
215 change_c0_status(ST0_IM, IE_IRQ0); 215 change_c0_status(ST0_IM, IE_IRQ0);
216 setup_irq (SNI_A20R_IRQ_BASE + 3, &sni_isa_irq); 216 setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
217} 217}
218 218
219void sni_a20r_init(void) 219void sni_a20r_init(void)
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index 44b1ae62aa4a..39bb15f1f2a6 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -284,9 +284,9 @@ static void sni_pcimt_hwint(void)
284 u32 pending = read_c0_cause() & read_c0_status(); 284 u32 pending = read_c0_cause() & read_c0_status();
285 285
286 if (pending & C_IRQ5) 286 if (pending & C_IRQ5)
287 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 287 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
288 else if (pending & C_IRQ4) 288 else if (pending & C_IRQ4)
289 do_IRQ (MIPS_CPU_IRQ_BASE + 6); 289 do_IRQ(MIPS_CPU_IRQ_BASE + 6);
290 else if (pending & C_IRQ3) 290 else if (pending & C_IRQ3)
291 pcimt_hwint3(); 291 pcimt_hwint3();
292 else if (pending & C_IRQ1) 292 else if (pending & C_IRQ1)
@@ -313,7 +313,6 @@ void __init sni_pcimt_init(void)
313{ 313{
314 sni_pcimt_detect(); 314 sni_pcimt_detect();
315 sni_pcimt_sc_init(); 315 sni_pcimt_sc_init();
316 board_time_init = sni_cpu_time_init;
317 ioport_resource.end = sni_io_resource.end; 316 ioport_resource.end = sni_io_resource.end;
318#ifdef CONFIG_PCI 317#ifdef CONFIG_PCI
319 PCIBIOS_MIN_IO = 0x9000; 318 PCIBIOS_MIN_IO = 0x9000;
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 2480c478dcbd..416f397c768b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -188,8 +188,8 @@ static void pcit_hwint1(void)
188 irq = ffs((pending >> 16) & 0x7f); 188 irq = ffs((pending >> 16) & 0x7f);
189 189
190 if (likely(irq > 0)) 190 if (likely(irq > 0))
191 do_IRQ (irq + SNI_PCIT_INT_START - 1); 191 do_IRQ(irq + SNI_PCIT_INT_START - 1);
192 set_c0_status (IE_IRQ1); 192 set_c0_status(IE_IRQ1);
193} 193}
194 194
195static void pcit_hwint0(void) 195static void pcit_hwint0(void)
@@ -201,8 +201,8 @@ static void pcit_hwint0(void)
201 irq = ffs((pending >> 16) & 0x3f); 201 irq = ffs((pending >> 16) & 0x3f);
202 202
203 if (likely(irq > 0)) 203 if (likely(irq > 0))
204 do_IRQ (irq + SNI_PCIT_INT_START - 1); 204 do_IRQ(irq + SNI_PCIT_INT_START - 1);
205 set_c0_status (IE_IRQ0); 205 set_c0_status(IE_IRQ0);
206} 206}
207 207
208static void sni_pcit_hwint(void) 208static void sni_pcit_hwint(void)
@@ -212,11 +212,11 @@ static void sni_pcit_hwint(void)
212 if (pending & C_IRQ1) 212 if (pending & C_IRQ1)
213 pcit_hwint1(); 213 pcit_hwint1();
214 else if (pending & C_IRQ2) 214 else if (pending & C_IRQ2)
215 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 215 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
216 else if (pending & C_IRQ3) 216 else if (pending & C_IRQ3)
217 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 217 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
218 else if (pending & C_IRQ5) 218 else if (pending & C_IRQ5)
219 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 219 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
220} 220}
221 221
222static void sni_pcit_hwint_cplus(void) 222static void sni_pcit_hwint_cplus(void)
@@ -226,13 +226,13 @@ static void sni_pcit_hwint_cplus(void)
226 if (pending & C_IRQ0) 226 if (pending & C_IRQ0)
227 pcit_hwint0(); 227 pcit_hwint0();
228 else if (pending & C_IRQ1) 228 else if (pending & C_IRQ1)
229 do_IRQ (MIPS_CPU_IRQ_BASE + 3); 229 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
230 else if (pending & C_IRQ2) 230 else if (pending & C_IRQ2)
231 do_IRQ (MIPS_CPU_IRQ_BASE + 4); 231 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
232 else if (pending & C_IRQ3) 232 else if (pending & C_IRQ3)
233 do_IRQ (MIPS_CPU_IRQ_BASE + 5); 233 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
234 else if (pending & C_IRQ5) 234 else if (pending & C_IRQ5)
235 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 235 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
236} 236}
237 237
238void __init sni_pcit_irq_init(void) 238void __init sni_pcit_irq_init(void)
@@ -245,7 +245,7 @@ void __init sni_pcit_irq_init(void)
245 *(volatile u32 *)SNI_PCIT_INT_REG = 0; 245 *(volatile u32 *)SNI_PCIT_INT_REG = 0;
246 sni_hwint = sni_pcit_hwint; 246 sni_hwint = sni_pcit_hwint;
247 change_c0_status(ST0_IM, IE_IRQ1); 247 change_c0_status(ST0_IM, IE_IRQ1);
248 setup_irq (SNI_PCIT_INT_START + 6, &sni_isa_irq); 248 setup_irq(SNI_PCIT_INT_START + 6, &sni_isa_irq);
249} 249}
250 250
251void __init sni_pcit_cplus_irq_init(void) 251void __init sni_pcit_cplus_irq_init(void)
@@ -258,12 +258,11 @@ void __init sni_pcit_cplus_irq_init(void)
258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000; 258 *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
259 sni_hwint = sni_pcit_hwint_cplus; 259 sni_hwint = sni_pcit_hwint_cplus;
260 change_c0_status(ST0_IM, IE_IRQ0); 260 change_c0_status(ST0_IM, IE_IRQ0);
261 setup_irq (MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); 261 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq);
262} 262}
263 263
264void __init sni_pcit_init(void) 264void __init sni_pcit_init(void)
265{ 265{
266 board_time_init = sni_cpu_time_init;
267 ioport_resource.end = sni_io_resource.end; 266 ioport_resource.end = sni_io_resource.end;
268#ifdef CONFIG_PCI 267#ifdef CONFIG_PCI
269 PCIBIOS_MIN_IO = 0x9000; 268 PCIBIOS_MIN_IO = 0x9000;
diff --git a/arch/mips/sni/reset.c b/arch/mips/sni/reset.c
index 38b6a97a31b5..79f8d70f48c9 100644
--- a/arch/mips/sni/reset.c
+++ b/arch/mips/sni/reset.c
@@ -35,7 +35,7 @@ void sni_machine_restart(char *command)
35 kb_wait(); 35 kb_wait();
36 for (j = 0; j < 100000 ; j++) 36 for (j = 0; j < 100000 ; j++)
37 /* nothing */; 37 /* nothing */;
38 outb_p(0xfe,0x64); /* pulse reset low */ 38 outb_p(0xfe, 0x64); /* pulse reset low */
39 } 39 }
40 } 40 }
41} 41}
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 28a11d8605ce..67b061eef6cd 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -162,16 +162,16 @@ static void sni_rm200_hwint(void)
162 int irq; 162 int irq;
163 163
164 if (pending & C_IRQ5) 164 if (pending & C_IRQ5)
165 do_IRQ (MIPS_CPU_IRQ_BASE + 7); 165 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
166 else if (pending & C_IRQ0) { 166 else if (pending & C_IRQ0) {
167 clear_c0_status (IE_IRQ0); 167 clear_c0_status(IE_IRQ0);
168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f; 168 mask = *(volatile u8 *)SNI_RM200_INT_ENA_REG ^ 0x1f;
169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14; 169 stat = *(volatile u8 *)SNI_RM200_INT_STAT_REG ^ 0x14;
170 irq = ffs(stat & mask & 0x1f); 170 irq = ffs(stat & mask & 0x1f);
171 171
172 if (likely(irq > 0)) 172 if (likely(irq > 0))
173 do_IRQ (irq + SNI_RM200_INT_START - 1); 173 do_IRQ(irq + SNI_RM200_INT_START - 1);
174 set_c0_status (IE_IRQ0); 174 set_c0_status(IE_IRQ0);
175 } 175 }
176} 176}
177 177
@@ -187,12 +187,11 @@ void __init sni_rm200_irq_init(void)
187 set_irq_chip(i, &rm200_irq_type); 187 set_irq_chip(i, &rm200_irq_type);
188 sni_hwint = sni_rm200_hwint; 188 sni_hwint = sni_rm200_hwint;
189 change_c0_status(ST0_IM, IE_IRQ0); 189 change_c0_status(ST0_IM, IE_IRQ0);
190 setup_irq (SNI_RM200_INT_START + 0, &sni_isa_irq); 190 setup_irq(SNI_RM200_INT_START + 0, &sni_isa_irq);
191} 191}
192 192
193void __init sni_rm200_init(void) 193void __init sni_rm200_init(void)
194{ 194{
195 set_io_port_base(SNI_PORT_BASE + 0x02000000); 195 set_io_port_base(SNI_PORT_BASE + 0x02000000);
196 ioport_resource.end += 0x02000000; 196 ioport_resource.end += 0x02000000;
197 board_time_init = sni_cpu_time_init;
198} 197}
diff --git a/arch/mips/sni/setup.c b/arch/mips/sni/setup.c
index 6edbb3051c82..e8b26bdee24c 100644
--- a/arch/mips/sni/setup.c
+++ b/arch/mips/sni/setup.c
@@ -15,7 +15,7 @@
15#include <linux/screen_info.h> 15#include <linux/screen_info.h>
16 16
17#ifdef CONFIG_ARC 17#ifdef CONFIG_ARC
18#include <asm/arc/types.h> 18#include <asm/fw/arc/types.h>
19#include <asm/sgialib.h> 19#include <asm/sgialib.h>
20#endif 20#endif
21 21
@@ -106,11 +106,11 @@ static void __devinit quirk_cirrus_ram_size(struct pci_dev *dev)
106 * need to do it here, otherwise we get screen corruption 106 * need to do it here, otherwise we get screen corruption
107 * on older Cirrus chips 107 * on older Cirrus chips
108 */ 108 */
109 pci_read_config_word (dev, PCI_COMMAND, &cmd); 109 pci_read_config_word(dev, PCI_COMMAND, &cmd);
110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) 110 if ((cmd & (PCI_COMMAND_IO|PCI_COMMAND_MEMORY))
111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) { 111 == (PCI_COMMAND_IO|PCI_COMMAND_MEMORY)) {
112 vga_wseq (NULL, CL_SEQR6, 0x12); /* unlock all extension registers */ 112 vga_wseq(NULL, CL_SEQR6, 0x12); /* unlock all extension registers */
113 vga_wseq (NULL, CL_SEQRF, 0x18); 113 vga_wseq(NULL, CL_SEQRF, 0x18);
114 } 114 }
115} 115}
116 116
diff --git a/arch/mips/sni/sniprom.c b/arch/mips/sni/sniprom.c
index db544a6e23f3..eff4b89d7b75 100644
--- a/arch/mips/sni/sniprom.c
+++ b/arch/mips/sni/sniprom.c
@@ -45,7 +45,7 @@ void prom_putchar(char c)
45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV); 45static char *(*__prom_getenv)(char *) = (char *(*)(char *))PROM_ENTRY(PROM_GETENV);
46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF); 46static void (*__prom_get_memconf)(void *) = (void (*)(void *))PROM_ENTRY(PROM_GET_MEMCONF);
47 47
48char *prom_getenv (char *s) 48char *prom_getenv(char *s)
49{ 49{
50 return __prom_getenv(s); 50 return __prom_getenv(s);
51} 51}
@@ -131,9 +131,9 @@ static void __init sni_console_setup(void)
131 int port; 131 int port;
132 static char options[8]; 132 static char options[8];
133 133
134 cdev = prom_getenv ("console_dev"); 134 cdev = prom_getenv("console_dev");
135 if (strncmp (cdev, "tty", 3) == 0) { 135 if (strncmp (cdev, "tty", 3) == 0) {
136 ctype = prom_getenv ("console"); 136 ctype = prom_getenv("console");
137 switch (*ctype) { 137 switch (*ctype) {
138 default: 138 default:
139 case 'l': 139 case 'l':
@@ -233,7 +233,7 @@ void __init prom_init(void)
233 systype = "RM300-Exx"; 233 systype = "RM300-Exx";
234 break; 234 break;
235 } 235 }
236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type,systype); 236 pr_debug("Found SNI brdtype %02x name %s\n", sni_brd_type, systype);
237 237
238#ifdef DEBUG 238#ifdef DEBUG
239 sni_idprom_dump(); 239 sni_idprom_dump();
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 20028fc7757e..b80877349d38 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -2,8 +2,10 @@
2#include <linux/interrupt.h> 2#include <linux/interrupt.h>
3#include <linux/time.h> 3#include <linux/time.h>
4 4
5#include <asm/i8253.h>
5#include <asm/sni.h> 6#include <asm/sni.h>
6#include <asm/time.h> 7#include <asm/time.h>
8#include <asm-generic/rtc.h>
7 9
8#define SNI_CLOCK_TICK_RATE 3686400 10#define SNI_CLOCK_TICK_RATE 3686400
9#define SNI_COUNTER2_DIV 64 11#define SNI_COUNTER2_DIV 64
@@ -42,23 +44,23 @@ static __init unsigned long dosample(void)
42 volatile u8 msb, lsb; 44 volatile u8 msb, lsb;
43 45
44 /* Start the counter. */ 46 /* Start the counter. */
45 outb_p (0x34, 0x43); 47 outb_p(0x34, 0x43);
46 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40); 48 outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
47 outb (SNI_8254_TCSAMP_COUNTER >> 8, 0x40); 49 outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
48 50
49 /* Get initial counter invariant */ 51 /* Get initial counter invariant */
50 ct0 = read_c0_count(); 52 ct0 = read_c0_count();
51 53
52 /* Latch and spin until top byte of counter0 is zero */ 54 /* Latch and spin until top byte of counter0 is zero */
53 do { 55 do {
54 outb (0x00, 0x43); 56 outb(0x00, 0x43);
55 lsb = inb (0x40); 57 lsb = inb(0x40);
56 msb = inb (0x40); 58 msb = inb(0x40);
57 ct1 = read_c0_count(); 59 ct1 = read_c0_count();
58 } while (msb); 60 } while (msb);
59 61
60 /* Stop the counter. */ 62 /* Stop the counter. */
61 outb (0x38, 0x43); 63 outb(0x38, 0x43);
62 /* 64 /*
63 * Return the difference, this is how far the r4k counter increments 65 * Return the difference, this is how far the r4k counter increments
64 * for every 1/HZ seconds. We round off the nearest 1 MHz of master 66 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
@@ -71,7 +73,7 @@ static __init unsigned long dosample(void)
71/* 73/*
72 * Here we need to calibrate the cycle counter to at least be close. 74 * Here we need to calibrate the cycle counter to at least be close.
73 */ 75 */
74__init void sni_cpu_time_init(void) 76void __init plat_time_init(void)
75{ 77{
76 unsigned long r4k_ticks[3]; 78 unsigned long r4k_ticks[3];
77 unsigned long r4k_tick; 79 unsigned long r4k_tick;
@@ -115,6 +117,8 @@ __init void sni_cpu_time_init(void)
115 (int) (r4k_tick % (500000 / HZ))); 117 (int) (r4k_tick % (500000 / HZ)));
116 118
117 mips_hpt_frequency = r4k_tick * HZ; 119 mips_hpt_frequency = r4k_tick * HZ;
120
121 setup_pit_timer();
118} 122}
119 123
120/* 124/*
@@ -133,7 +137,7 @@ void __init plat_timer_setup(struct irqaction *irq)
133 case SNI_BRD_10NEW: 137 case SNI_BRD_10NEW:
134 case SNI_BRD_TOWER_OASIC: 138 case SNI_BRD_TOWER_OASIC:
135 case SNI_BRD_MINITOWER: 139 case SNI_BRD_MINITOWER:
136 sni_a20r_timer_setup (irq); 140 sni_a20r_timer_setup(irq);
137 break; 141 break;
138 142
139 case SNI_BRD_PCI_TOWER: 143 case SNI_BRD_PCI_TOWER:
@@ -142,7 +146,12 @@ void __init plat_timer_setup(struct irqaction *irq)
142 case SNI_BRD_PCI_DESKTOP: 146 case SNI_BRD_PCI_DESKTOP:
143 case SNI_BRD_PCI_TOWER_CPLUS: 147 case SNI_BRD_PCI_TOWER_CPLUS:
144 case SNI_BRD_PCI_MTOWER_CPLUS: 148 case SNI_BRD_PCI_MTOWER_CPLUS:
145 sni_cpu_timer_setup (irq); 149 sni_cpu_timer_setup(irq);
146 break; 150 break;
147 } 151 }
148} 152}
153
154unsigned long read_persistent_clock(void)
155{
156 return -1;
157}
diff --git a/arch/mips/tx4927/common/tx4927_dbgio.c b/arch/mips/tx4927/common/tx4927_dbgio.c
index 09bdf2baa835..d8423e001b2d 100644
--- a/arch/mips/tx4927/common/tx4927_dbgio.c
+++ b/arch/mips/tx4927/common/tx4927_dbgio.c
@@ -31,7 +31,6 @@
31 31
32#include <asm/mipsregs.h> 32#include <asm/mipsregs.h>
33#include <asm/system.h> 33#include <asm/system.h>
34#include <asm/tx4927/tx4927_mips.h>
35 34
36u8 getDebugChar(void) 35u8 getDebugChar(void)
37{ 36{
diff --git a/arch/mips/tx4927/common/tx4927_prom.c b/arch/mips/tx4927/common/tx4927_prom.c
index 7d4cbf512d8a..6eed53d8f386 100644
--- a/arch/mips/tx4927/common/tx4927_prom.c
+++ b/arch/mips/tx4927/common/tx4927_prom.c
@@ -38,7 +38,7 @@
38#include <asm/bootinfo.h> 38#include <asm/bootinfo.h>
39#include <asm/tx4927/tx4927.h> 39#include <asm/tx4927/tx4927.h>
40 40
41static unsigned int __init tx4927_process_sdccr(u64 * addr) 41static unsigned int __init tx4927_process_sdccr(unsigned long addr)
42{ 42{
43 u64 val; 43 u64 val;
44 unsigned int sdccr_ce; 44 unsigned int sdccr_ce;
@@ -52,7 +52,7 @@ static unsigned int __init tx4927_process_sdccr(u64 * addr)
52 unsigned int mw = 0; 52 unsigned int mw = 0;
53 unsigned int msize = 0; 53 unsigned int msize = 0;
54 54
55 val = (*((vu64 *) (addr))); 55 val = __raw_readq((void __iomem *)addr);
56 56
57 /* MVMCP -- need #defs for these bits masks */ 57 /* MVMCP -- need #defs for these bits masks */
58 sdccr_ce = ((val & (1 << 10)) >> 10); 58 sdccr_ce = ((val & (1 << 10)) >> 10);
@@ -136,10 +136,10 @@ unsigned int __init tx4927_get_mem_size(void)
136 unsigned int total; 136 unsigned int total;
137 137
138 /* MVMCP -- need #defs for these registers */ 138 /* MVMCP -- need #defs for these registers */
139 c0 = tx4927_process_sdccr((u64 *) 0xff1f8000); 139 c0 = tx4927_process_sdccr(0xff1f8000);
140 c1 = tx4927_process_sdccr((u64 *) 0xff1f8008); 140 c1 = tx4927_process_sdccr(0xff1f8008);
141 c2 = tx4927_process_sdccr((u64 *) 0xff1f8010); 141 c2 = tx4927_process_sdccr(0xff1f8010);
142 c3 = tx4927_process_sdccr((u64 *) 0xff1f8018); 142 c3 = tx4927_process_sdccr(0xff1f8018);
143 total = c0 + c1 + c2 + c3; 143 total = c0 + c1 + c2 + c3;
144 144
145 return (total); 145 return (total);
diff --git a/arch/mips/tx4927/common/tx4927_setup.c b/arch/mips/tx4927/common/tx4927_setup.c
index c8e49feb345b..8ce0989671d8 100644
--- a/arch/mips/tx4927/common/tx4927_setup.c
+++ b/arch/mips/tx4927/common/tx4927_setup.c
@@ -49,14 +49,11 @@
49 49
50#undef DEBUG 50#undef DEBUG
51 51
52void __init tx4927_time_init(void);
53void dump_cp0(char *key); 52void dump_cp0(char *key);
54 53
55 54
56void __init plat_mem_setup(void) 55void __init plat_mem_setup(void)
57{ 56{
58 board_time_init = tx4927_time_init;
59
60#ifdef CONFIG_TOSHIBA_RBTX4927 57#ifdef CONFIG_TOSHIBA_RBTX4927
61 { 58 {
62 extern void toshiba_rbtx4927_setup(void); 59 extern void toshiba_rbtx4927_setup(void);
@@ -65,20 +62,16 @@ void __init plat_mem_setup(void)
65#endif 62#endif
66} 63}
67 64
68void __init tx4927_time_init(void) 65void __init plat_time_init(void)
69{ 66{
70
71#ifdef CONFIG_TOSHIBA_RBTX4927 67#ifdef CONFIG_TOSHIBA_RBTX4927
72 { 68 {
73 extern void toshiba_rbtx4927_time_init(void); 69 extern void toshiba_rbtx4927_time_init(void);
74 toshiba_rbtx4927_time_init(); 70 toshiba_rbtx4927_time_init();
75 } 71 }
76#endif 72#endif
77
78 return;
79} 73}
80 74
81
82void __init plat_timer_setup(struct irqaction *irq) 75void __init plat_timer_setup(struct irqaction *irq)
83{ 76{
84 setup_irq(TX4927_IRQ_CPU_TIMER, irq); 77 setup_irq(TX4927_IRQ_CPU_TIMER, irq);
@@ -124,10 +117,10 @@ dump_cp0(char *key)
124 return; 117 return;
125} 118}
126 119
127void print_pic(char *key, u32 reg, char *name) 120void print_pic(char *key, unsigned long reg, char *name)
128{ 121{
129 printk("%s pic:0x%08x:%s=0x%08x\n", key, reg, name, 122 printk(KERN_INFO "%s pic:0x%08lx:%s=0x%08x\n", key, reg, name,
130 TX4927_RD(reg)); 123 __raw_readl((void __iomem *)reg));
131 return; 124 return;
132} 125}
133 126
@@ -166,9 +159,10 @@ void dump_pic(char *key)
166} 159}
167 160
168 161
169void print_addr(char *hdr, char *key, u32 addr) 162void print_addr(char *hdr, char *key, unsigned long addr)
170{ 163{
171 printk("%s %s:0x%08x=0x%08x\n", hdr, key, addr, TX4927_RD(addr)); 164 printk(KERN_INFO "%s %s:0x%08lx=0x%08x\n", hdr, key, addr,
165 __raw_readl((void __iomem *)addr));
172 return; 166 return;
173} 167}
174 168
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 9607ad5e734a..3f808b629242 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -176,7 +176,7 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 176 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
177 } 177 }
178#else 178#else
179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) 179#define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag, str...)
180#endif 180#endif
181 181
182 182
@@ -204,8 +204,8 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
204 .mask_ack = toshiba_rbtx4927_irq_ioc_disable, 204 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
205 .unmask = toshiba_rbtx4927_irq_ioc_enable, 205 .unmask = toshiba_rbtx4927_irq_ioc_enable,
206}; 206};
207#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 207#define TOSHIBA_RBTX4927_IOC_INTR_ENAB (void __iomem *)0xbc002000UL
208#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 208#define TOSHIBA_RBTX4927_IOC_INTR_STAT (void __iomem *)0xbc002006UL
209 209
210 210
211u32 bit2num(u32 num) 211u32 bit2num(u32 num)
@@ -224,7 +224,7 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
224{ 224{
225 u32 level3; 225 u32 level3;
226 226
227 level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 227 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
228 if (level3) { 228 if (level3) {
229 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3); 229 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
230 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) { 230 if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
@@ -243,10 +243,12 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
243 return (sw_irq); 243 return (sw_irq);
244} 244}
245 245
246//#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 246static struct irqaction toshiba_rbtx4927_irq_ioc_action = {
247#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, IRQF_SHARED, CPU_MASK_NONE, s, NULL, NULL } 247 .handler = no_action,
248static struct irqaction toshiba_rbtx4927_irq_ioc_action = 248 .flags = IRQF_SHARED,
249TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME); 249 .mask = CPU_MASK_NONE,
250 .name = TOSHIBA_RBTX4927_IOC_NAME
251};
250 252
251 253
252/**********************************************************************************/ 254/**********************************************************************************/
@@ -286,9 +288,9 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
286 panic("\n"); 288 panic("\n");
287 } 289 }
288 290
289 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 291 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
290 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 292 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
291 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 293 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
292} 294}
293 295
294 296
@@ -306,9 +308,10 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
306 panic("\n"); 308 panic("\n");
307 } 309 }
308 310
309 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 311 v = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
310 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 312 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
311 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 313 writeb(v, TOSHIBA_RBTX4927_IOC_INTR_ENAB);
314 mmiowb();
312} 315}
313 316
314 317
@@ -385,12 +388,12 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
385 level1_m = level0_m; 388 level1_m = level0_m;
386 level1_s = level0_s & 0x87; 389 level1_s = level0_s & 0x87;
387 390
388 level2 = TX4927_RD(0xff1ff6a0); 391 level2 = __raw_readl((void __iomem *)0xff1ff6a0UL);
389 level2_p = (((level2 & 0x10000)) ? 0 : 1); 392 level2_p = (((level2 & 0x10000)) ? 0 : 1);
390 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f)); 393 level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
391 394
392 level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f; 395 level3_m = readb(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
393 level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 396 level3_s = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
394 397
395 level4_m = inb(0x21); 398 level4_m = inb(0x21);
396 outb(0x0A, 0x20); 399 outb(0x0A, 0x20);
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
index 9a3a5babd1fb..f3f86857beae 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_prom.c
@@ -66,8 +66,6 @@ void __init prom_init(void)
66 66
67 prom_init_cmdline(); 67 prom_init_cmdline();
68 68
69 mips_machgroup = MACH_GROUP_TOSHIBA;
70
71 if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) { 69 if ((read_c0_prid() & 0xff) == PRID_REV_TX4927) {
72 mips_machtype = MACH_TOSHIBA_RBTX4927; 70 mips_machtype = MACH_TOSHIBA_RBTX4927;
73 toshiba_name = "TX4927"; 71 toshiba_name = "TX4927";
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
index 3e84237abe63..acaf613358c7 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_setup.c
@@ -122,7 +122,7 @@ static const u32 toshiba_rbtx4927_setup_debug_flag =
122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \ 122 printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
123 } 123 }
124#else 124#else
125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) 125#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
126#endif 126#endif
127 127
128/* These functions are used for rebooting or halting the machine*/ 128/* These functions are used for rebooting or halting the machine*/
@@ -497,7 +497,7 @@ void __init tx4927_pci_setup(void)
497 "Internal"); 497 "Internal");
498 called = 1; 498 called = 1;
499 } 499 }
500 printk("%s PCIC --%s PCICLK:",toshiba_name, 500 printk("%s PCIC --%s PCICLK:", toshiba_name,
501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : ""); 501 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) { 502 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
503 int pciclk = 0; 503 int pciclk = 0;
@@ -679,25 +679,30 @@ void __init tx4927_pci_setup(void)
679 679
680#endif /* CONFIG_PCI */ 680#endif /* CONFIG_PCI */
681 681
682static void __noreturn wait_forever(void)
683{
684 while (1)
685 if (cpu_wait)
686 (*cpu_wait)();
687}
688
682void toshiba_rbtx4927_restart(char *command) 689void toshiba_rbtx4927_restart(char *command)
683{ 690{
684 printk(KERN_NOTICE "System Rebooting...\n"); 691 printk(KERN_NOTICE "System Rebooting...\n");
685 692
686 /* enable the s/w reset register */ 693 /* enable the s/w reset register */
687 reg_wr08(RBTX4927_SW_RESET_ENABLE, RBTX4927_SW_RESET_ENABLE_SET); 694 writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
688 695
689 /* wait for enable to be seen */ 696 /* wait for enable to be seen */
690 while ((reg_rd08(RBTX4927_SW_RESET_ENABLE) & 697 while ((readb(RBTX4927_SW_RESET_ENABLE) &
691 RBTX4927_SW_RESET_ENABLE_SET) == 0x00); 698 RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
692 699
693 /* do a s/w reset */ 700 /* do a s/w reset */
694 reg_wr08(RBTX4927_SW_RESET_DO, RBTX4927_SW_RESET_DO_SET); 701 writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
695 702
696 /* do something passive while waiting for reset */ 703 /* do something passive while waiting for reset */
697 local_irq_disable(); 704 local_irq_disable();
698 while (1) 705 wait_forever();
699 asm_wait();
700
701 /* no return */ 706 /* no return */
702} 707}
703 708
@@ -706,9 +711,7 @@ void toshiba_rbtx4927_halt(void)
706{ 711{
707 printk(KERN_NOTICE "System Halted\n"); 712 printk(KERN_NOTICE "System Halted\n");
708 local_irq_disable(); 713 local_irq_disable();
709 while (1) { 714 wait_forever();
710 asm_wait();
711 }
712 /* no return */ 715 /* no return */
713} 716}
714 717
@@ -720,7 +723,7 @@ void toshiba_rbtx4927_power_off(void)
720 723
721void __init toshiba_rbtx4927_setup(void) 724void __init toshiba_rbtx4927_setup(void)
722{ 725{
723 vu32 cp0_config; 726 u32 cp0_config;
724 char *argptr; 727 char *argptr;
725 728
726 printk("CPU is %s\n", toshiba_name); 729 printk("CPU is %s\n", toshiba_name);
@@ -747,15 +750,6 @@ void __init toshiba_rbtx4927_setup(void)
747 } 750 }
748#endif 751#endif
749 752
750 /* setup serial stuff */
751 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
752 ":Setting up tx4927 sio.\n");
753 TX4927_WR(0xff1ff314, 0x00000000); /* h/w flow control off */
754 TX4927_WR(0xff1ff414, 0x00000000); /* h/w flow control off */
755
756 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
757 "+\n");
758
759 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET); 753 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
760 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP, 754 TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
761 ":mips_io_port_base=0x%08lx\n", 755 ":mips_io_port_base=0x%08lx\n",
diff --git a/arch/mips/tx4938/common/setup.c b/arch/mips/tx4938/common/setup.c
index 142abf453e40..ab4082267553 100644
--- a/arch/mips/tx4938/common/setup.c
+++ b/arch/mips/tx4938/common/setup.c
@@ -34,25 +34,16 @@
34#include <asm/tx4938/rbtx4938.h> 34#include <asm/tx4938/rbtx4938.h>
35 35
36extern void toshiba_rbtx4938_setup(void); 36extern void toshiba_rbtx4938_setup(void);
37extern void rbtx4938_time_init(void);
38 37
39void __init tx4938_setup(void); 38void __init tx4938_setup(void);
40void __init tx4938_time_init(void);
41void dump_cp0(char *key); 39void dump_cp0(char *key);
42 40
43void __init 41void __init
44plat_mem_setup(void) 42plat_mem_setup(void)
45{ 43{
46 board_time_init = tx4938_time_init;
47 toshiba_rbtx4938_setup(); 44 toshiba_rbtx4938_setup();
48} 45}
49 46
50void __init
51tx4938_time_init(void)
52{
53 rbtx4938_time_init();
54}
55
56void __init plat_timer_setup(struct irqaction *irq) 47void __init plat_timer_setup(struct irqaction *irq)
57{ 48{
58 setup_irq(TX4938_IRQ_CPU_TIMER, irq); 49 setup_irq(TX4938_IRQ_CPU_TIMER, irq);
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/prom.c b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
index 7dc6a0aae21c..69f21c1b7942 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/prom.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/prom.c
@@ -47,7 +47,6 @@ void __init prom_init(void)
47#ifndef CONFIG_TX4938_NAND_BOOT 47#ifndef CONFIG_TX4938_NAND_BOOT
48 prom_init_cmdline(); 48 prom_init_cmdline();
49#endif 49#endif
50 mips_machgroup = MACH_GROUP_TOSHIBA;
51 mips_machtype = MACH_TOSHIBA_RBTX4938; 50 mips_machtype = MACH_TOSHIBA_RBTX4938;
52 51
53 msize = tx4938_get_mem_size(); 52 msize = tx4938_get_mem_size();
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/setup.c b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
index f236b1ff8923..ceecaf498957 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/setup.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/setup.c
@@ -39,7 +39,6 @@
39#include <asm/tx4938/spi.h> 39#include <asm/tx4938/spi.h>
40#include <asm/gpio.h> 40#include <asm/gpio.h>
41 41
42extern void rbtx4938_time_init(void) __init;
43extern char * __init prom_getcmdline(void); 42extern char * __init prom_getcmdline(void);
44static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr); 43static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
45 44
@@ -458,9 +457,9 @@ extern struct pci_controller tx4938_pci_controller[];
458static int __init tx4938_pcibios_init(void) 457static int __init tx4938_pcibios_init(void)
459{ 458{
460 unsigned long mem_base[2]; 459 unsigned long mem_base[2];
461 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */ 460 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
462 unsigned long io_base[2]; 461 unsigned long io_base[2];
463 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */ 462 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
464 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */ 463 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
465 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB); 464 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
466 465
@@ -856,7 +855,7 @@ void tx4938_report_pcic_status(void)
856/* We use onchip r4k counter or TMR timer as our system wide timer 855/* We use onchip r4k counter or TMR timer as our system wide timer
857 * interrupt running at 100HZ. */ 856 * interrupt running at 100HZ. */
858 857
859void __init rbtx4938_time_init(void) 858void __init plat_time_init(void)
860{ 859{
861 mips_hpt_frequency = txx9_cpu_clock / 2; 860 mips_hpt_frequency = txx9_cpu_clock / 2;
862} 861}
diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c
index ff272b2e8395..d77c330a0d59 100644
--- a/arch/mips/vr41xx/common/bcu.c
+++ b/arch/mips/vr41xx/common/bcu.c
@@ -70,7 +70,7 @@ EXPORT_SYMBOL_GPL(vr41xx_get_tclock_frequency);
70 70
71static inline uint16_t read_clkspeed(void) 71static inline uint16_t read_clkspeed(void)
72{ 72{
73 switch (current_cpu_data.cputype) { 73 switch (current_cpu_type()) {
74 case CPU_VR4111: 74 case CPU_VR4111:
75 case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1); 75 case CPU_VR4121: return readw(CLKSPEEDREG_TYPE1);
76 case CPU_VR4122: 76 case CPU_VR4122:
@@ -88,7 +88,7 @@ static inline unsigned long calculate_pclock(uint16_t clkspeed)
88{ 88{
89 unsigned long pclock = 0; 89 unsigned long pclock = 0;
90 90
91 switch (current_cpu_data.cputype) { 91 switch (current_cpu_type()) {
92 case CPU_VR4111: 92 case CPU_VR4111:
93 case CPU_VR4121: 93 case CPU_VR4121:
94 pclock = 18432000 * 64; 94 pclock = 18432000 * 64;
@@ -138,7 +138,7 @@ static inline unsigned long calculate_vtclock(uint16_t clkspeed, unsigned long p
138{ 138{
139 unsigned long vtclock = 0; 139 unsigned long vtclock = 0;
140 140
141 switch (current_cpu_data.cputype) { 141 switch (current_cpu_type()) {
142 case CPU_VR4111: 142 case CPU_VR4111:
143 /* The NEC VR4111 doesn't have the VTClock. */ 143 /* The NEC VR4111 doesn't have the VTClock. */
144 break; 144 break;
@@ -180,7 +180,7 @@ static inline unsigned long calculate_tclock(uint16_t clkspeed, unsigned long pc
180{ 180{
181 unsigned long tclock = 0; 181 unsigned long tclock = 0;
182 182
183 switch (current_cpu_data.cputype) { 183 switch (current_cpu_type()) {
184 case CPU_VR4111: 184 case CPU_VR4111:
185 if (!(clkspeed & DIV2B)) 185 if (!(clkspeed & DIV2B))
186 tclock = pclock / 2; 186 tclock = pclock / 2;
diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c
index 657c5133c933..ad0e8e3409d9 100644
--- a/arch/mips/vr41xx/common/cmu.c
+++ b/arch/mips/vr41xx/common/cmu.c
@@ -95,8 +95,8 @@ void vr41xx_supply_clock(vr41xx_clock_t clock)
95 cmuclkmsk |= MSKFIR | MSKFFIR; 95 cmuclkmsk |= MSKFIR | MSKFFIR;
96 break; 96 break;
97 case DSIU_CLOCK: 97 case DSIU_CLOCK:
98 if (current_cpu_data.cputype == CPU_VR4111 || 98 if (current_cpu_type() == CPU_VR4111 ||
99 current_cpu_data.cputype == CPU_VR4121) 99 current_cpu_type() == CPU_VR4121)
100 cmuclkmsk |= MSKDSIU; 100 cmuclkmsk |= MSKDSIU;
101 else 101 else
102 cmuclkmsk |= MSKSIU | MSKDSIU; 102 cmuclkmsk |= MSKSIU | MSKDSIU;
@@ -146,8 +146,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
146 cmuclkmsk &= ~MSKPIU; 146 cmuclkmsk &= ~MSKPIU;
147 break; 147 break;
148 case SIU_CLOCK: 148 case SIU_CLOCK:
149 if (current_cpu_data.cputype == CPU_VR4111 || 149 if (current_cpu_type() == CPU_VR4111 ||
150 current_cpu_data.cputype == CPU_VR4121) { 150 current_cpu_type() == CPU_VR4121) {
151 cmuclkmsk &= ~(MSKSIU | MSKSSIU); 151 cmuclkmsk &= ~(MSKSIU | MSKSSIU);
152 } else { 152 } else {
153 if (cmuclkmsk & MSKDSIU) 153 if (cmuclkmsk & MSKDSIU)
@@ -166,8 +166,8 @@ void vr41xx_mask_clock(vr41xx_clock_t clock)
166 cmuclkmsk &= ~(MSKFIR | MSKFFIR); 166 cmuclkmsk &= ~(MSKFIR | MSKFFIR);
167 break; 167 break;
168 case DSIU_CLOCK: 168 case DSIU_CLOCK:
169 if (current_cpu_data.cputype == CPU_VR4111 || 169 if (current_cpu_type() == CPU_VR4111 ||
170 current_cpu_data.cputype == CPU_VR4121) { 170 current_cpu_type() == CPU_VR4121) {
171 cmuclkmsk &= ~MSKDSIU; 171 cmuclkmsk &= ~MSKDSIU;
172 } else { 172 } else {
173 if (cmuclkmsk & MSKSSIU) 173 if (cmuclkmsk & MSKSSIU)
@@ -216,7 +216,7 @@ static int __init vr41xx_cmu_init(void)
216{ 216{
217 unsigned long start, size; 217 unsigned long start, size;
218 218
219 switch (current_cpu_data.cputype) { 219 switch (current_cpu_type()) {
220 case CPU_VR4111: 220 case CPU_VR4111:
221 case CPU_VR4121: 221 case CPU_VR4121:
222 start = CMU_TYPE1_BASE; 222 start = CMU_TYPE1_BASE;
@@ -246,7 +246,7 @@ static int __init vr41xx_cmu_init(void)
246 } 246 }
247 247
248 cmuclkmsk = cmu_read(CMUCLKMSK); 248 cmuclkmsk = cmu_read(CMUCLKMSK);
249 if (current_cpu_data.cputype == CPU_VR4133) 249 if (current_cpu_type() == CPU_VR4133)
250 cmuclkmsk2 = cmu_read(CMUCLKMSK2); 250 cmuclkmsk2 = cmu_read(CMUCLKMSK2);
251 251
252 spin_lock_init(&cmu_lock); 252 spin_lock_init(&cmu_lock);
diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c
index d21f6f2d22a3..2b272f1496fe 100644
--- a/arch/mips/vr41xx/common/giu.c
+++ b/arch/mips/vr41xx/common/giu.c
@@ -81,7 +81,7 @@ static int __init vr41xx_giu_add(void)
81 if (!pdev) 81 if (!pdev)
82 return -ENOMEM; 82 return -ENOMEM;
83 83
84 switch (current_cpu_data.cputype) { 84 switch (current_cpu_type()) {
85 case CPU_VR4111: 85 case CPU_VR4111:
86 case CPU_VR4121: 86 case CPU_VR4121:
87 pdev->id = GPIO_50PINS_PULLUPDOWN; 87 pdev->id = GPIO_50PINS_PULLUPDOWN;
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index adabc6bad440..1899601e5862 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -157,8 +157,8 @@ void vr41xx_enable_piuint(uint16_t mask)
157 struct irq_desc *desc = irq_desc + PIU_IRQ; 157 struct irq_desc *desc = irq_desc + PIU_IRQ;
158 unsigned long flags; 158 unsigned long flags;
159 159
160 if (current_cpu_data.cputype == CPU_VR4111 || 160 if (current_cpu_type() == CPU_VR4111 ||
161 current_cpu_data.cputype == CPU_VR4121) { 161 current_cpu_type() == CPU_VR4121) {
162 spin_lock_irqsave(&desc->lock, flags); 162 spin_lock_irqsave(&desc->lock, flags);
163 icu1_set(MPIUINTREG, mask); 163 icu1_set(MPIUINTREG, mask);
164 spin_unlock_irqrestore(&desc->lock, flags); 164 spin_unlock_irqrestore(&desc->lock, flags);
@@ -172,8 +172,8 @@ void vr41xx_disable_piuint(uint16_t mask)
172 struct irq_desc *desc = irq_desc + PIU_IRQ; 172 struct irq_desc *desc = irq_desc + PIU_IRQ;
173 unsigned long flags; 173 unsigned long flags;
174 174
175 if (current_cpu_data.cputype == CPU_VR4111 || 175 if (current_cpu_type() == CPU_VR4111 ||
176 current_cpu_data.cputype == CPU_VR4121) { 176 current_cpu_type() == CPU_VR4121) {
177 spin_lock_irqsave(&desc->lock, flags); 177 spin_lock_irqsave(&desc->lock, flags);
178 icu1_clear(MPIUINTREG, mask); 178 icu1_clear(MPIUINTREG, mask);
179 spin_unlock_irqrestore(&desc->lock, flags); 179 spin_unlock_irqrestore(&desc->lock, flags);
@@ -187,8 +187,8 @@ void vr41xx_enable_aiuint(uint16_t mask)
187 struct irq_desc *desc = irq_desc + AIU_IRQ; 187 struct irq_desc *desc = irq_desc + AIU_IRQ;
188 unsigned long flags; 188 unsigned long flags;
189 189
190 if (current_cpu_data.cputype == CPU_VR4111 || 190 if (current_cpu_type() == CPU_VR4111 ||
191 current_cpu_data.cputype == CPU_VR4121) { 191 current_cpu_type() == CPU_VR4121) {
192 spin_lock_irqsave(&desc->lock, flags); 192 spin_lock_irqsave(&desc->lock, flags);
193 icu1_set(MAIUINTREG, mask); 193 icu1_set(MAIUINTREG, mask);
194 spin_unlock_irqrestore(&desc->lock, flags); 194 spin_unlock_irqrestore(&desc->lock, flags);
@@ -202,8 +202,8 @@ void vr41xx_disable_aiuint(uint16_t mask)
202 struct irq_desc *desc = irq_desc + AIU_IRQ; 202 struct irq_desc *desc = irq_desc + AIU_IRQ;
203 unsigned long flags; 203 unsigned long flags;
204 204
205 if (current_cpu_data.cputype == CPU_VR4111 || 205 if (current_cpu_type() == CPU_VR4111 ||
206 current_cpu_data.cputype == CPU_VR4121) { 206 current_cpu_type() == CPU_VR4121) {
207 spin_lock_irqsave(&desc->lock, flags); 207 spin_lock_irqsave(&desc->lock, flags);
208 icu1_clear(MAIUINTREG, mask); 208 icu1_clear(MAIUINTREG, mask);
209 spin_unlock_irqrestore(&desc->lock, flags); 209 spin_unlock_irqrestore(&desc->lock, flags);
@@ -217,8 +217,8 @@ void vr41xx_enable_kiuint(uint16_t mask)
217 struct irq_desc *desc = irq_desc + KIU_IRQ; 217 struct irq_desc *desc = irq_desc + KIU_IRQ;
218 unsigned long flags; 218 unsigned long flags;
219 219
220 if (current_cpu_data.cputype == CPU_VR4111 || 220 if (current_cpu_type() == CPU_VR4111 ||
221 current_cpu_data.cputype == CPU_VR4121) { 221 current_cpu_type() == CPU_VR4121) {
222 spin_lock_irqsave(&desc->lock, flags); 222 spin_lock_irqsave(&desc->lock, flags);
223 icu1_set(MKIUINTREG, mask); 223 icu1_set(MKIUINTREG, mask);
224 spin_unlock_irqrestore(&desc->lock, flags); 224 spin_unlock_irqrestore(&desc->lock, flags);
@@ -232,8 +232,8 @@ void vr41xx_disable_kiuint(uint16_t mask)
232 struct irq_desc *desc = irq_desc + KIU_IRQ; 232 struct irq_desc *desc = irq_desc + KIU_IRQ;
233 unsigned long flags; 233 unsigned long flags;
234 234
235 if (current_cpu_data.cputype == CPU_VR4111 || 235 if (current_cpu_type() == CPU_VR4111 ||
236 current_cpu_data.cputype == CPU_VR4121) { 236 current_cpu_type() == CPU_VR4121) {
237 spin_lock_irqsave(&desc->lock, flags); 237 spin_lock_irqsave(&desc->lock, flags);
238 icu1_clear(MKIUINTREG, mask); 238 icu1_clear(MKIUINTREG, mask);
239 spin_unlock_irqrestore(&desc->lock, flags); 239 spin_unlock_irqrestore(&desc->lock, flags);
@@ -319,9 +319,9 @@ void vr41xx_enable_pciint(void)
319 struct irq_desc *desc = irq_desc + PCI_IRQ; 319 struct irq_desc *desc = irq_desc + PCI_IRQ;
320 unsigned long flags; 320 unsigned long flags;
321 321
322 if (current_cpu_data.cputype == CPU_VR4122 || 322 if (current_cpu_type() == CPU_VR4122 ||
323 current_cpu_data.cputype == CPU_VR4131 || 323 current_cpu_type() == CPU_VR4131 ||
324 current_cpu_data.cputype == CPU_VR4133) { 324 current_cpu_type() == CPU_VR4133) {
325 spin_lock_irqsave(&desc->lock, flags); 325 spin_lock_irqsave(&desc->lock, flags);
326 icu2_write(MPCIINTREG, PCIINT0); 326 icu2_write(MPCIINTREG, PCIINT0);
327 spin_unlock_irqrestore(&desc->lock, flags); 327 spin_unlock_irqrestore(&desc->lock, flags);
@@ -335,9 +335,9 @@ void vr41xx_disable_pciint(void)
335 struct irq_desc *desc = irq_desc + PCI_IRQ; 335 struct irq_desc *desc = irq_desc + PCI_IRQ;
336 unsigned long flags; 336 unsigned long flags;
337 337
338 if (current_cpu_data.cputype == CPU_VR4122 || 338 if (current_cpu_type() == CPU_VR4122 ||
339 current_cpu_data.cputype == CPU_VR4131 || 339 current_cpu_type() == CPU_VR4131 ||
340 current_cpu_data.cputype == CPU_VR4133) { 340 current_cpu_type() == CPU_VR4133) {
341 spin_lock_irqsave(&desc->lock, flags); 341 spin_lock_irqsave(&desc->lock, flags);
342 icu2_write(MPCIINTREG, 0); 342 icu2_write(MPCIINTREG, 0);
343 spin_unlock_irqrestore(&desc->lock, flags); 343 spin_unlock_irqrestore(&desc->lock, flags);
@@ -351,9 +351,9 @@ void vr41xx_enable_scuint(void)
351 struct irq_desc *desc = irq_desc + SCU_IRQ; 351 struct irq_desc *desc = irq_desc + SCU_IRQ;
352 unsigned long flags; 352 unsigned long flags;
353 353
354 if (current_cpu_data.cputype == CPU_VR4122 || 354 if (current_cpu_type() == CPU_VR4122 ||
355 current_cpu_data.cputype == CPU_VR4131 || 355 current_cpu_type() == CPU_VR4131 ||
356 current_cpu_data.cputype == CPU_VR4133) { 356 current_cpu_type() == CPU_VR4133) {
357 spin_lock_irqsave(&desc->lock, flags); 357 spin_lock_irqsave(&desc->lock, flags);
358 icu2_write(MSCUINTREG, SCUINT0); 358 icu2_write(MSCUINTREG, SCUINT0);
359 spin_unlock_irqrestore(&desc->lock, flags); 359 spin_unlock_irqrestore(&desc->lock, flags);
@@ -367,9 +367,9 @@ void vr41xx_disable_scuint(void)
367 struct irq_desc *desc = irq_desc + SCU_IRQ; 367 struct irq_desc *desc = irq_desc + SCU_IRQ;
368 unsigned long flags; 368 unsigned long flags;
369 369
370 if (current_cpu_data.cputype == CPU_VR4122 || 370 if (current_cpu_type() == CPU_VR4122 ||
371 current_cpu_data.cputype == CPU_VR4131 || 371 current_cpu_type() == CPU_VR4131 ||
372 current_cpu_data.cputype == CPU_VR4133) { 372 current_cpu_type() == CPU_VR4133) {
373 spin_lock_irqsave(&desc->lock, flags); 373 spin_lock_irqsave(&desc->lock, flags);
374 icu2_write(MSCUINTREG, 0); 374 icu2_write(MSCUINTREG, 0);
375 spin_unlock_irqrestore(&desc->lock, flags); 375 spin_unlock_irqrestore(&desc->lock, flags);
@@ -383,9 +383,9 @@ void vr41xx_enable_csiint(uint16_t mask)
383 struct irq_desc *desc = irq_desc + CSI_IRQ; 383 struct irq_desc *desc = irq_desc + CSI_IRQ;
384 unsigned long flags; 384 unsigned long flags;
385 385
386 if (current_cpu_data.cputype == CPU_VR4122 || 386 if (current_cpu_type() == CPU_VR4122 ||
387 current_cpu_data.cputype == CPU_VR4131 || 387 current_cpu_type() == CPU_VR4131 ||
388 current_cpu_data.cputype == CPU_VR4133) { 388 current_cpu_type() == CPU_VR4133) {
389 spin_lock_irqsave(&desc->lock, flags); 389 spin_lock_irqsave(&desc->lock, flags);
390 icu2_set(MCSIINTREG, mask); 390 icu2_set(MCSIINTREG, mask);
391 spin_unlock_irqrestore(&desc->lock, flags); 391 spin_unlock_irqrestore(&desc->lock, flags);
@@ -399,9 +399,9 @@ void vr41xx_disable_csiint(uint16_t mask)
399 struct irq_desc *desc = irq_desc + CSI_IRQ; 399 struct irq_desc *desc = irq_desc + CSI_IRQ;
400 unsigned long flags; 400 unsigned long flags;
401 401
402 if (current_cpu_data.cputype == CPU_VR4122 || 402 if (current_cpu_type() == CPU_VR4122 ||
403 current_cpu_data.cputype == CPU_VR4131 || 403 current_cpu_type() == CPU_VR4131 ||
404 current_cpu_data.cputype == CPU_VR4133) { 404 current_cpu_type() == CPU_VR4133) {
405 spin_lock_irqsave(&desc->lock, flags); 405 spin_lock_irqsave(&desc->lock, flags);
406 icu2_clear(MCSIINTREG, mask); 406 icu2_clear(MCSIINTREG, mask);
407 spin_unlock_irqrestore(&desc->lock, flags); 407 spin_unlock_irqrestore(&desc->lock, flags);
@@ -415,9 +415,9 @@ void vr41xx_enable_bcuint(void)
415 struct irq_desc *desc = irq_desc + BCU_IRQ; 415 struct irq_desc *desc = irq_desc + BCU_IRQ;
416 unsigned long flags; 416 unsigned long flags;
417 417
418 if (current_cpu_data.cputype == CPU_VR4122 || 418 if (current_cpu_type() == CPU_VR4122 ||
419 current_cpu_data.cputype == CPU_VR4131 || 419 current_cpu_type() == CPU_VR4131 ||
420 current_cpu_data.cputype == CPU_VR4133) { 420 current_cpu_type() == CPU_VR4133) {
421 spin_lock_irqsave(&desc->lock, flags); 421 spin_lock_irqsave(&desc->lock, flags);
422 icu2_write(MBCUINTREG, BCUINTR); 422 icu2_write(MBCUINTREG, BCUINTR);
423 spin_unlock_irqrestore(&desc->lock, flags); 423 spin_unlock_irqrestore(&desc->lock, flags);
@@ -431,9 +431,9 @@ void vr41xx_disable_bcuint(void)
431 struct irq_desc *desc = irq_desc + BCU_IRQ; 431 struct irq_desc *desc = irq_desc + BCU_IRQ;
432 unsigned long flags; 432 unsigned long flags;
433 433
434 if (current_cpu_data.cputype == CPU_VR4122 || 434 if (current_cpu_type() == CPU_VR4122 ||
435 current_cpu_data.cputype == CPU_VR4131 || 435 current_cpu_type() == CPU_VR4131 ||
436 current_cpu_data.cputype == CPU_VR4133) { 436 current_cpu_type() == CPU_VR4133) {
437 spin_lock_irqsave(&desc->lock, flags); 437 spin_lock_irqsave(&desc->lock, flags);
438 icu2_write(MBCUINTREG, 0); 438 icu2_write(MBCUINTREG, 0);
439 spin_unlock_irqrestore(&desc->lock, flags); 439 spin_unlock_irqrestore(&desc->lock, flags);
@@ -608,7 +608,7 @@ int vr41xx_set_intassign(unsigned int irq, unsigned char intassign)
608{ 608{
609 int retval = -EINVAL; 609 int retval = -EINVAL;
610 610
611 if (current_cpu_data.cputype != CPU_VR4133) 611 if (current_cpu_type() != CPU_VR4133)
612 return -EINVAL; 612 return -EINVAL;
613 613
614 if (intassign > INTASSIGN_MAX) 614 if (intassign > INTASSIGN_MAX)
@@ -665,7 +665,7 @@ static int __init vr41xx_icu_init(void)
665 unsigned long icu1_start, icu2_start; 665 unsigned long icu1_start, icu2_start;
666 int i; 666 int i;
667 667
668 switch (current_cpu_data.cputype) { 668 switch (current_cpu_type()) {
669 case CPU_VR4111: 669 case CPU_VR4111:
670 case CPU_VR4121: 670 case CPU_VR4121:
671 icu1_start = ICU1_TYPE1_BASE; 671 icu1_start = ICU1_TYPE1_BASE;
diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c
index 4f97e0ba9e24..407cec203b29 100644
--- a/arch/mips/vr41xx/common/init.c
+++ b/arch/mips/vr41xx/common/init.c
@@ -36,7 +36,7 @@ static void __init iomem_resource_init(void)
36 iomem_resource.end = IO_MEM_RESOURCE_END; 36 iomem_resource.end = IO_MEM_RESOURCE_END;
37} 37}
38 38
39static void __init setup_timer_frequency(void) 39void __init plat_time_init(void)
40{ 40{
41 unsigned long tclock; 41 unsigned long tclock;
42 42
@@ -53,16 +53,10 @@ void __init plat_timer_setup(struct irqaction *irq)
53 setup_irq(TIMER_IRQ, irq); 53 setup_irq(TIMER_IRQ, irq);
54} 54}
55 55
56static void __init timer_init(void)
57{
58 board_time_init = setup_timer_frequency;
59}
60
61void __init plat_mem_setup(void) 56void __init plat_mem_setup(void)
62{ 57{
63 vr41xx_calculate_clock_frequency(); 58 vr41xx_calculate_clock_frequency();
64 59
65 timer_init();
66 iomem_resource_init(); 60 iomem_resource_init();
67} 61}
68 62
diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c
index 5e469796413f..028aaf75eb21 100644
--- a/arch/mips/vr41xx/common/pmu.c
+++ b/arch/mips/vr41xx/common/pmu.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * pmu.c, Power Management Unit routines for NEC VR4100 series. 2 * pmu.c, Power Management Unit routines for NEC VR4100 series.
3 * 3 *
4 * Copyright (C) 2003-2005 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> 4 * Copyright (C) 2003-2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by 7 * it under the terms of the GNU General Public License as published by
@@ -22,11 +22,13 @@
22#include <linux/ioport.h> 22#include <linux/ioport.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/pm.h> 24#include <linux/pm.h>
25#include <linux/smp.h> 25#include <linux/sched.h>
26#include <linux/types.h> 26#include <linux/types.h>
27 27
28#include <asm/cacheflush.h>
28#include <asm/cpu.h> 29#include <asm/cpu.h>
29#include <asm/io.h> 30#include <asm/io.h>
31#include <asm/processor.h>
30#include <asm/reboot.h> 32#include <asm/reboot.h>
31#include <asm/system.h> 33#include <asm/system.h>
32 34
@@ -44,11 +46,23 @@ static void __iomem *pmu_base;
44#define pmu_read(offset) readw(pmu_base + (offset)) 46#define pmu_read(offset) readw(pmu_base + (offset))
45#define pmu_write(offset, value) writew((value), pmu_base + (offset)) 47#define pmu_write(offset, value) writew((value), pmu_base + (offset))
46 48
49static void vr41xx_cpu_wait(void)
50{
51 local_irq_disable();
52 if (!need_resched())
53 /*
54 * "standby" sets IE bit of the CP0_STATUS to 1.
55 */
56 __asm__("standby;\n");
57 else
58 local_irq_enable();
59}
60
47static inline void software_reset(void) 61static inline void software_reset(void)
48{ 62{
49 uint16_t pmucnt2; 63 uint16_t pmucnt2;
50 64
51 switch (current_cpu_data.cputype) { 65 switch (current_cpu_type()) {
52 case CPU_VR4122: 66 case CPU_VR4122:
53 case CPU_VR4131: 67 case CPU_VR4131:
54 case CPU_VR4133: 68 case CPU_VR4133:
@@ -57,6 +71,11 @@ static inline void software_reset(void)
57 pmu_write(PMUCNT2REG, pmucnt2); 71 pmu_write(PMUCNT2REG, pmucnt2);
58 break; 72 break;
59 default: 73 default:
74 set_c0_status(ST0_BEV | ST0_ERL);
75 change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED);
76 flush_cache_all();
77 write_c0_wired(0);
78 __asm__("jr %0"::"r"(0xbfc00000));
60 break; 79 break;
61 } 80 }
62} 81}
@@ -65,7 +84,6 @@ static void vr41xx_restart(char *command)
65{ 84{
66 local_irq_disable(); 85 local_irq_disable();
67 software_reset(); 86 software_reset();
68 printk(KERN_NOTICE "\nYou can reset your system\n");
69 while (1) ; 87 while (1) ;
70} 88}
71 89
@@ -73,21 +91,14 @@ static void vr41xx_halt(void)
73{ 91{
74 local_irq_disable(); 92 local_irq_disable();
75 printk(KERN_NOTICE "\nYou can turn off the power supply\n"); 93 printk(KERN_NOTICE "\nYou can turn off the power supply\n");
76 while (1) ; 94 __asm__("hibernate;\n");
77}
78
79static void vr41xx_power_off(void)
80{
81 local_irq_disable();
82 printk(KERN_NOTICE "\nYou can turn off the power supply\n");
83 while (1) ;
84} 95}
85 96
86static int __init vr41xx_pmu_init(void) 97static int __init vr41xx_pmu_init(void)
87{ 98{
88 unsigned long start, size; 99 unsigned long start, size;
89 100
90 switch (current_cpu_data.cputype) { 101 switch (current_cpu_type()) {
91 case CPU_VR4111: 102 case CPU_VR4111:
92 case CPU_VR4121: 103 case CPU_VR4121:
93 start = PMU_TYPE1_BASE; 104 start = PMU_TYPE1_BASE;
@@ -113,9 +124,10 @@ static int __init vr41xx_pmu_init(void)
113 return -EBUSY; 124 return -EBUSY;
114 } 125 }
115 126
127 cpu_wait = vr41xx_cpu_wait;
116 _machine_restart = vr41xx_restart; 128 _machine_restart = vr41xx_restart;
117 _machine_halt = vr41xx_halt; 129 _machine_halt = vr41xx_halt;
118 pm_power_off = vr41xx_power_off; 130 pm_power_off = vr41xx_halt;
119 131
120 return 0; 132 return 0;
121} 133}
diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c
index cce605b3d688..9f26c14edcac 100644
--- a/arch/mips/vr41xx/common/rtc.c
+++ b/arch/mips/vr41xx/common/rtc.c
@@ -82,7 +82,7 @@ static int __init vr41xx_rtc_add(void)
82 if (!pdev) 82 if (!pdev)
83 return -ENOMEM; 83 return -ENOMEM;
84 84
85 switch (current_cpu_data.cputype) { 85 switch (current_cpu_type()) {
86 case CPU_VR4111: 86 case CPU_VR4111:
87 case CPU_VR4121: 87 case CPU_VR4121:
88 res = rtc_type1_resource; 88 res = rtc_type1_resource;
diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c
index a1e774142163..b735f45b25f0 100644
--- a/arch/mips/vr41xx/common/siu.c
+++ b/arch/mips/vr41xx/common/siu.c
@@ -83,7 +83,7 @@ static int __init vr41xx_siu_add(void)
83 if (!pdev) 83 if (!pdev)
84 return -ENOMEM; 84 return -ENOMEM;
85 85
86 switch (current_cpu_data.cputype) { 86 switch (current_cpu_type()) {
87 case CPU_VR4111: 87 case CPU_VR4111:
88 case CPU_VR4121: 88 case CPU_VR4121:
89 pdev->dev.platform_data = siu_type1_ports; 89 pdev->dev.platform_data = siu_type1_ports;
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/init.c b/arch/mips/vr41xx/nec-cmbvr4133/init.c
index ae1af6b21c45..7c5e18ee2231 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/init.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/init.c
@@ -36,7 +36,7 @@ void disable_pcnet(void)
36 */ 36 */
37 37
38 writel((2 << 16) | 38 writel((2 << 16) |
39 (PCI_DEVFN(1,0) << 8) | 39 (PCI_DEVFN(1, 0) << 8) |
40 (0 & 0xfc) | 40 (0 & 0xfc) |
41 1UL, 41 1UL,
42 PCICONFAREG); 42 PCICONFAREG);
@@ -44,7 +44,7 @@ void disable_pcnet(void)
44 data = readl(PCICONFDREG); 44 data = readl(PCICONFDREG);
45 45
46 writel((2 << 16) | 46 writel((2 << 16) |
47 (PCI_DEVFN(1,0) << 8) | 47 (PCI_DEVFN(1, 0) << 8) |
48 (4 & 0xfc) | 48 (4 & 0xfc) |
49 1UL, 49 1UL,
50 PCICONFAREG); 50 PCICONFAREG);
@@ -52,7 +52,7 @@ void disable_pcnet(void)
52 data = readl(PCICONFDREG); 52 data = readl(PCICONFDREG);
53 53
54 writel((2 << 16) | 54 writel((2 << 16) |
55 (PCI_DEVFN(1,0) << 8) | 55 (PCI_DEVFN(1, 0) << 8) |
56 (4 & 0xfc) | 56 (4 & 0xfc) |
57 1UL, 57 1UL,
58 PCICONFAREG); 58 PCICONFAREG);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
index f45caccedc07..1341f3287d04 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/m1535plus.c
@@ -38,7 +38,7 @@
38 outb_p((dev_no), DATA_PORT(port)); \ 38 outb_p((dev_no), DATA_PORT(port)); \
39 } while(0) 39 } while(0)
40 40
41#define WRITE_CONFIG_DATA(port,index,data) \ 41#define WRITE_CONFIG_DATA(port, index, data) \
42 do { \ 42 do { \
43 outb_p((index), INDEX_PORT(port)); \ 43 outb_p((index), INDEX_PORT(port)); \
44 outb_p((data), DATA_PORT(port)); \ 44 outb_p((data), DATA_PORT(port)); \
@@ -206,8 +206,8 @@ static inline u16 ali_config_readw(u8 reg, int devfn)
206int vr4133_rockhopper = 0; 206int vr4133_rockhopper = 0;
207void __init ali_m5229_preinit(void) 207void __init ali_m5229_preinit(void)
208{ 208{
209 if (ali_config_readw(PCI_VENDOR_ID,16) == PCI_VENDOR_ID_AL && 209 if (ali_config_readw(PCI_VENDOR_ID, 16) == PCI_VENDOR_ID_AL &&
210 ali_config_readw(PCI_DEVICE_ID,16) == PCI_DEVICE_ID_AL_M1533) { 210 ali_config_readw(PCI_DEVICE_ID, 16) == PCI_DEVICE_ID_AL_M1533) {
211 printk(KERN_INFO "Found an NEC Rockhopper \n"); 211 printk(KERN_INFO "Found an NEC Rockhopper \n");
212 vr4133_rockhopper = 1; 212 vr4133_rockhopper = 1;
213 /* 213 /*
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/setup.c b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
index b20b93b2b95e..58e47686b499 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/setup.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/setup.c
@@ -64,7 +64,6 @@ static void __init nec_cmbvr4133_setup(void)
64#endif 64#endif
65 set_io_port_base(KSEG1ADDR(0x16000000)); 65 set_io_port_base(KSEG1ADDR(0x16000000));
66 66
67 mips_machgroup = MACH_GROUP_NEC_VR41XX;
68 mips_machtype = MACH_NEC_CMBVR4133; 67 mips_machtype = MACH_NEC_CMBVR4133;
69 68
70#ifdef CONFIG_PCI 69#ifdef CONFIG_PCI
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 00:02:38 -0500