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-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts50
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts118
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts250
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi156
-rw-r--r--arch/arm/boot/dts/omap2.dtsi86
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi16
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi19
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts6
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts67
-rw-r--r--arch/arm/boot/dts/omap3.dtsi107
-rw-r--r--arch/arm/boot/dts/omap4-panda-a4.dts17
-rw-r--r--arch/arm/boot/dts/omap4-panda-es.dts (renamed from arch/arm/boot/dts/omap4-pandaES.dts)9
-rw-r--r--arch/arm/boot/dts/omap4-panda.dts22
-rw-r--r--arch/arm/boot/dts/omap4-sdp-es23plus.dts17
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts22
-rw-r--r--arch/arm/boot/dts/omap4-var-som.dts (renamed from arch/arm/boot/dts/omap4-var_som.dts)0
-rw-r--r--arch/arm/boot/dts/omap4.dtsi105
-rw-r--r--arch/arm/boot/dts/omap5-evm.dts13
-rw-r--r--arch/arm/boot/dts/omap5.dtsi178
-rw-r--r--arch/arm/boot/dts/samsung_k3pe0e000b.dtsi67
-rw-r--r--arch/arm/boot/dts/twl4030.dtsi27
-rw-r--r--arch/arm/boot/dts/twl6030.dtsi5
-rw-r--r--arch/arm/mach-omap1/timer.c1
-rw-r--r--arch/arm/mach-omap1/timer32k.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c17
-rw-r--r--arch/arm/mach-omap2/common.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c15
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c41
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c4
-rw-r--r--arch/arm/mach-omap2/pm-debug.c1
-rw-r--r--arch/arm/mach-omap2/timer.c382
-rw-r--r--arch/arm/plat-omap/Kconfig6
-rw-r--r--arch/arm/plat-omap/dmtimer.c218
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h143
38 files changed, 1875 insertions, 322 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f37cf9fa5fa0..2458b69e2be6 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -63,15 +63,17 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
63 imx28-m28evk.dtb \ 63 imx28-m28evk.dtb \
64 imx28-tx28.dtb 64 imx28-tx28.dtb
65dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \ 65dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
66 omap3-beagle.dtb \
66 omap3-beagle-xm.dtb \ 67 omap3-beagle-xm.dtb \
67 omap3-evm.dtb \ 68 omap3-evm.dtb \
68 omap3-tobi.dtb \ 69 omap3-tobi.dtb \
69 omap4-panda.dtb \ 70 omap4-panda.dtb \
70 omap4-pandaES.dtb \ 71 omap4-panda-es.dtb \
71 omap4-var_som.dtb \ 72 omap4-var-som.dtb \
72 omap4-sdp.dtb \ 73 omap4-sdp.dtb \
73 omap5-evm.dtb \ 74 omap5-evm.dtb \
74 am335x-evm.dtb \ 75 am335x-evm.dtb \
76 am335x-evmsk.dtb \
75 am335x-bone.dtb 77 am335x-bone.dtb
76dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 78dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
77dtb-$(CONFIG_ARCH_U8500) += snowball.dtb 79dtb-$(CONFIG_ARCH_U8500) += snowball.dtb
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index c634f87e230e..2c338889df1b 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -13,11 +13,31 @@
13 model = "TI AM335x BeagleBone"; 13 model = "TI AM335x BeagleBone";
14 compatible = "ti,am335x-bone", "ti,am33xx"; 14 compatible = "ti,am335x-bone", "ti,am33xx";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&dcdc2_reg>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 25 };
20 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&user_leds_s0>;
30
31 user_leds_s0: user_leds_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x17 /* gpmc_a6.gpio1_22, OUTPUT_PULLUP | MODE7 */
35 0x5c 0x7 /* gpmc_a7.gpio1_23, OUTPUT | MODE7 */
36 0x60 0x17 /* gpmc_a8.gpio1_24, OUTPUT_PULLUP | MODE7 */
37 >;
38 };
39 };
40
21 ocp { 41 ocp {
22 uart1: serial@44e09000 { 42 uart1: serial@44e09000 {
23 status = "okay"; 43 status = "okay";
@@ -33,6 +53,36 @@
33 53
34 }; 54 };
35 }; 55 };
56
57 leds {
58 compatible = "gpio-leds";
59
60 led@2 {
61 label = "beaglebone:green:heartbeat";
62 gpios = <&gpio2 21 0>;
63 linux,default-trigger = "heartbeat";
64 default-state = "off";
65 };
66
67 led@3 {
68 label = "beaglebone:green:mmc0";
69 gpios = <&gpio2 22 0>;
70 linux,default-trigger = "mmc0";
71 default-state = "off";
72 };
73
74 led@4 {
75 label = "beaglebone:green:usr2";
76 gpios = <&gpio2 23 0>;
77 default-state = "off";
78 };
79
80 led@5 {
81 label = "beaglebone:green:usr3";
82 gpios = <&gpio2 24 0>;
83 default-state = "off";
84 };
85 };
36}; 86};
37 87
38/include/ "tps65217.dtsi" 88/include/ "tps65217.dtsi"
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 185d6325a458..9f65f17ebdf8 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -13,11 +13,39 @@
13 model = "TI AM335x EVM"; 13 model = "TI AM335x EVM";
14 compatible = "ti,am335x-evm", "ti,am33xx"; 14 compatible = "ti,am335x-evm", "ti,am33xx";
15 15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
16 memory { 22 memory {
17 device_type = "memory"; 23 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
19 }; 25 };
20 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 0x7 /* gpmc_a5.gpio1_21, OUTPUT | MODE7 */
34 0x58 0x7 /* gpmc_a6.gpio1_22, OUTPUT | MODE7 */
35 0x64 0x27 /* gpmc_a9.gpio1_25, INPUT | MODE7 */
36 0x68 0x27 /* gpmc_a10.gpio1_26, INPUT | MODE7 */
37 0x6c 0x27 /* gpmc_a11.gpio1_27, INPUT | MODE7 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 0x27 /* spi0_sclk.gpio0_2, INPUT | MODE7 */
44 0x154 0x27 /* spi0_d0.gpio0_3, INPUT | MODE7 */
45 >;
46 };
47 };
48
21 ocp { 49 ocp {
22 uart1: serial@44e09000 { 50 uart1: serial@44e09000 {
23 status = "okay"; 51 status = "okay";
@@ -31,6 +59,49 @@
31 reg = <0x2d>; 59 reg = <0x2d>;
32 }; 60 };
33 }; 61 };
62
63 i2c2: i2c@4802a000 {
64 status = "okay";
65 clock-frequency = <100000>;
66
67 lis331dlh: lis331dlh@18 {
68 compatible = "st,lis331dlh", "st,lis3lv02d";
69 reg = <0x18>;
70 Vdd-supply = <&lis3_reg>;
71 Vdd_IO-supply = <&lis3_reg>;
72
73 st,click-single-x;
74 st,click-single-y;
75 st,click-single-z;
76 st,click-thresh-x = <10>;
77 st,click-thresh-y = <10>;
78 st,click-thresh-z = <10>;
79 st,irq1-click;
80 st,irq2-click;
81 st,wakeup-x-lo;
82 st,wakeup-x-hi;
83 st,wakeup-y-lo;
84 st,wakeup-y-hi;
85 st,wakeup-z-lo;
86 st,wakeup-z-hi;
87 st,min-limit-x = <120>;
88 st,min-limit-y = <120>;
89 st,min-limit-z = <140>;
90 st,max-limit-x = <550>;
91 st,max-limit-y = <550>;
92 st,max-limit-z = <750>;
93 };
94
95 tsl2550: tsl2550@39 {
96 compatible = "taos,tsl2550";
97 reg = <0x39>;
98 };
99
100 tmp275: tmp275@48 {
101 compatible = "ti,tmp275";
102 reg = <0x48>;
103 };
104 };
34 }; 105 };
35 106
36 vbat: fixedregulator@0 { 107 vbat: fixedregulator@0 {
@@ -40,6 +111,53 @@
40 regulator-max-microvolt = <5000000>; 111 regulator-max-microvolt = <5000000>;
41 regulator-boot-on; 112 regulator-boot-on;
42 }; 113 };
114
115 lis3_reg: fixedregulator@1 {
116 compatible = "regulator-fixed";
117 regulator-name = "lis3_reg";
118 regulator-boot-on;
119 };
120
121 matrix_keypad: matrix_keypad@0 {
122 compatible = "gpio-matrix-keypad";
123 debounce-delay-ms = <5>;
124 col-scan-delay-us = <2>;
125
126 row-gpios = <&gpio2 25 0 /* Bank1, pin25 */
127 &gpio2 26 0 /* Bank1, pin26 */
128 &gpio2 27 0>; /* Bank1, pin27 */
129
130 col-gpios = <&gpio2 21 0 /* Bank1, pin21 */
131 &gpio2 22 0>; /* Bank1, pin22 */
132
133 linux,keymap = <0x0000008b /* MENU */
134 0x0100009e /* BACK */
135 0x02000069 /* LEFT */
136 0x0001006a /* RIGHT */
137 0x0101001c /* ENTER */
138 0x0201006c>; /* DOWN */
139 };
140
141 gpio_keys: volume_keys@0 {
142 compatible = "gpio-keys";
143 #address-cells = <1>;
144 #size-cells = <0>;
145 autorepeat;
146
147 switch@9 {
148 label = "volume-up";
149 linux,code = <115>;
150 gpios = <&gpio1 2 1>;
151 gpio-key,wakeup;
152 };
153
154 switch@10 {
155 label = "volume-down";
156 linux,code = <114>;
157 gpios = <&gpio1 3 1>;
158 gpio-key,wakeup;
159 };
160 };
43}; 161};
44 162
45/include/ "tps65910.dtsi" 163/include/ "tps65910.dtsi"
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
new file mode 100644
index 000000000000..f5a6162a4ff2
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -0,0 +1,250 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * AM335x Starter Kit
11 * http://www.ti.com/tool/tmdssk3358
12 */
13
14/dts-v1/;
15
16/include/ "am33xx.dtsi"
17
18/ {
19 model = "TI AM335x EVM-SK";
20 compatible = "ti,am335x-evmsk", "ti,am33xx";
21
22 cpus {
23 cpu@0 {
24 cpu0-supply = <&vdd1_reg>;
25 };
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x80000000 0x10000000>; /* 256 MB */
31 };
32
33 am33xx_pinmux: pinmux@44e10800 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&user_leds_s0 &gpio_keys_s0>;
36
37 user_leds_s0: user_leds_s0 {
38 pinctrl-single,pins = <
39 0x10 0x7 /* gpmc_ad4.gpio1_4, OUTPUT | MODE7 */
40 0x14 0x7 /* gpmc_ad5.gpio1_5, OUTPUT | MODE7 */
41 0x18 0x7 /* gpmc_ad6.gpio1_6, OUTPUT | MODE7 */
42 0x1c 0x7 /* gpmc_ad7.gpio1_7, OUTPUT | MODE7 */
43 >;
44 };
45
46 gpio_keys_s0: gpio_keys_s0 {
47 pinctrl-single,pins = <
48 0x94 0x27 /* gpmc_oen_ren.gpio2_3, INPUT | MODE7 */
49 0x90 0x27 /* gpmc_advn_ale.gpio2_2, INPUT | MODE7 */
50 0x70 0x27 /* gpmc_wait0.gpio0_30, INPUT | MODE7 */
51 0x9c 0x27 /* gpmc_ben0_cle.gpio2_5, INPUT | MODE7 */
52 >;
53 };
54 };
55
56 ocp {
57 uart1: serial@44e09000 {
58 status = "okay";
59 };
60
61 i2c1: i2c@44e0b000 {
62 status = "okay";
63 clock-frequency = <400000>;
64
65 tps: tps@2d {
66 reg = <0x2d>;
67 };
68
69 lis331dlh: lis331dlh@18 {
70 compatible = "st,lis331dlh", "st,lis3lv02d";
71 reg = <0x18>;
72 Vdd-supply = <&lis3_reg>;
73 Vdd_IO-supply = <&lis3_reg>;
74
75 st,click-single-x;
76 st,click-single-y;
77 st,click-single-z;
78 st,click-thresh-x = <10>;
79 st,click-thresh-y = <10>;
80 st,click-thresh-z = <10>;
81 st,irq1-click;
82 st,irq2-click;
83 st,wakeup-x-lo;
84 st,wakeup-x-hi;
85 st,wakeup-y-lo;
86 st,wakeup-y-hi;
87 st,wakeup-z-lo;
88 st,wakeup-z-hi;
89 st,min-limit-x = <120>;
90 st,min-limit-y = <120>;
91 st,min-limit-z = <140>;
92 st,max-limit-x = <550>;
93 st,max-limit-y = <550>;
94 st,max-limit-z = <750>;
95 };
96 };
97 };
98
99 vbat: fixedregulator@0 {
100 compatible = "regulator-fixed";
101 regulator-name = "vbat";
102 regulator-min-microvolt = <5000000>;
103 regulator-max-microvolt = <5000000>;
104 regulator-boot-on;
105 };
106
107 lis3_reg: fixedregulator@1 {
108 compatible = "regulator-fixed";
109 regulator-name = "lis3_reg";
110 regulator-boot-on;
111 };
112
113 leds {
114 compatible = "gpio-leds";
115
116 led@1 {
117 label = "evmsk:green:usr0";
118 gpios = <&gpio2 4 0>;
119 default-state = "off";
120 };
121
122 led@2 {
123 label = "evmsk:green:usr1";
124 gpios = <&gpio2 5 0>;
125 default-state = "off";
126 };
127
128 led@3 {
129 label = "evmsk:green:mmc0";
130 gpios = <&gpio2 6 0>;
131 linux,default-trigger = "mmc0";
132 default-state = "off";
133 };
134
135 led@4 {
136 label = "evmsk:green:heartbeat";
137 gpios = <&gpio2 7 0>;
138 linux,default-trigger = "heartbeat";
139 default-state = "off";
140 };
141 };
142
143 gpio_buttons: gpio_buttons@0 {
144 compatible = "gpio-keys";
145 #address-cells = <1>;
146 #size-cells = <0>;
147
148 switch@1 {
149 label = "button0";
150 linux,code = <0x100>;
151 gpios = <&gpio3 3 0>;
152 };
153
154 switch@2 {
155 label = "button1";
156 linux,code = <0x101>;
157 gpios = <&gpio3 2 0>;
158 };
159
160 switch@3 {
161 label = "button2";
162 linux,code = <0x102>;
163 gpios = <&gpio1 30 0>;
164 gpio-key,wakeup;
165 };
166
167 switch@4 {
168 label = "button3";
169 linux,code = <0x103>;
170 gpios = <&gpio3 5 0>;
171 };
172 };
173};
174
175/include/ "tps65910.dtsi"
176
177&tps {
178 vcc1-supply = <&vbat>;
179 vcc2-supply = <&vbat>;
180 vcc3-supply = <&vbat>;
181 vcc4-supply = <&vbat>;
182 vcc5-supply = <&vbat>;
183 vcc6-supply = <&vbat>;
184 vcc7-supply = <&vbat>;
185 vccio-supply = <&vbat>;
186
187 regulators {
188 vrtc_reg: regulator@0 {
189 regulator-always-on;
190 };
191
192 vio_reg: regulator@1 {
193 regulator-always-on;
194 };
195
196 vdd1_reg: regulator@2 {
197 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
198 regulator-name = "vdd_mpu";
199 regulator-min-microvolt = <912500>;
200 regulator-max-microvolt = <1312500>;
201 regulator-boot-on;
202 regulator-always-on;
203 };
204
205 vdd2_reg: regulator@3 {
206 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
207 regulator-name = "vdd_core";
208 regulator-min-microvolt = <912500>;
209 regulator-max-microvolt = <1150000>;
210 regulator-boot-on;
211 regulator-always-on;
212 };
213
214 vdd3_reg: regulator@4 {
215 regulator-always-on;
216 };
217
218 vdig1_reg: regulator@5 {
219 regulator-always-on;
220 };
221
222 vdig2_reg: regulator@6 {
223 regulator-always-on;
224 };
225
226 vpll_reg: regulator@7 {
227 regulator-always-on;
228 };
229
230 vdac_reg: regulator@8 {
231 regulator-always-on;
232 };
233
234 vaux1_reg: regulator@9 {
235 regulator-always-on;
236 };
237
238 vaux2_reg: regulator@10 {
239 regulator-always-on;
240 };
241
242 vaux33_reg: regulator@11 {
243 regulator-always-on;
244 };
245
246 vmmc_reg: regulator@12 {
247 regulator-always-on;
248 };
249 };
250};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index bb31bff01998..20a3f29a6bfe 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,am33xx"; 14 compatible = "ti,am33xx";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -25,6 +26,21 @@
25 cpus { 26 cpus {
26 cpu@0 { 27 cpu@0 {
27 compatible = "arm,cortex-a8"; 28 compatible = "arm,cortex-a8";
29
30 /*
31 * To consider voltage drop between PMIC and SoC,
32 * tolerance value is reduced to 2% from 4% and
33 * voltage value is increased as a precaution.
34 */
35 operating-points = <
36 /* kHz uV */
37 720000 1285000
38 600000 1225000
39 500000 1125000
40 275000 1125000
41 >;
42 voltage-tolerance = <2>; /* 2 percentage */
43 clock-latency = <300000>; /* From omap-cpufreq driver */
28 }; 44 };
29 }; 45 };
30 46
@@ -40,6 +56,15 @@
40 }; 56 };
41 }; 57 };
42 58
59 am33xx_pinmux: pinmux@44e10800 {
60 compatible = "pinctrl-single";
61 reg = <0x44e10800 0x0238>;
62 #address-cells = <1>;
63 #size-cells = <0>;
64 pinctrl-single,register-width = <32>;
65 pinctrl-single,function-mask = <0x7f>;
66 };
67
43 /* 68 /*
44 * XXX: Use a flat representation of the AM33XX interconnect. 69 * XXX: Use a flat representation of the AM33XX interconnect.
45 * The real AM33XX interconnect network is quite complex.Since 70 * The real AM33XX interconnect network is quite complex.Since
@@ -70,7 +95,6 @@
70 interrupt-controller; 95 interrupt-controller;
71 #interrupt-cells = <1>; 96 #interrupt-cells = <1>;
72 reg = <0x44e07000 0x1000>; 97 reg = <0x44e07000 0x1000>;
73 interrupt-parent = <&intc>;
74 interrupts = <96>; 98 interrupts = <96>;
75 }; 99 };
76 100
@@ -82,7 +106,6 @@
82 interrupt-controller; 106 interrupt-controller;
83 #interrupt-cells = <1>; 107 #interrupt-cells = <1>;
84 reg = <0x4804c000 0x1000>; 108 reg = <0x4804c000 0x1000>;
85 interrupt-parent = <&intc>;
86 interrupts = <98>; 109 interrupts = <98>;
87 }; 110 };
88 111
@@ -94,7 +117,6 @@
94 interrupt-controller; 117 interrupt-controller;
95 #interrupt-cells = <1>; 118 #interrupt-cells = <1>;
96 reg = <0x481ac000 0x1000>; 119 reg = <0x481ac000 0x1000>;
97 interrupt-parent = <&intc>;
98 interrupts = <32>; 120 interrupts = <32>;
99 }; 121 };
100 122
@@ -106,7 +128,6 @@
106 interrupt-controller; 128 interrupt-controller;
107 #interrupt-cells = <1>; 129 #interrupt-cells = <1>;
108 reg = <0x481ae000 0x1000>; 130 reg = <0x481ae000 0x1000>;
109 interrupt-parent = <&intc>;
110 interrupts = <62>; 131 interrupts = <62>;
111 }; 132 };
112 133
@@ -115,7 +136,6 @@
115 ti,hwmods = "uart1"; 136 ti,hwmods = "uart1";
116 clock-frequency = <48000000>; 137 clock-frequency = <48000000>;
117 reg = <0x44e09000 0x2000>; 138 reg = <0x44e09000 0x2000>;
118 interrupt-parent = <&intc>;
119 interrupts = <72>; 139 interrupts = <72>;
120 status = "disabled"; 140 status = "disabled";
121 }; 141 };
@@ -125,7 +145,6 @@
125 ti,hwmods = "uart2"; 145 ti,hwmods = "uart2";
126 clock-frequency = <48000000>; 146 clock-frequency = <48000000>;
127 reg = <0x48022000 0x2000>; 147 reg = <0x48022000 0x2000>;
128 interrupt-parent = <&intc>;
129 interrupts = <73>; 148 interrupts = <73>;
130 status = "disabled"; 149 status = "disabled";
131 }; 150 };
@@ -135,7 +154,6 @@
135 ti,hwmods = "uart3"; 154 ti,hwmods = "uart3";
136 clock-frequency = <48000000>; 155 clock-frequency = <48000000>;
137 reg = <0x48024000 0x2000>; 156 reg = <0x48024000 0x2000>;
138 interrupt-parent = <&intc>;
139 interrupts = <74>; 157 interrupts = <74>;
140 status = "disabled"; 158 status = "disabled";
141 }; 159 };
@@ -145,7 +163,6 @@
145 ti,hwmods = "uart4"; 163 ti,hwmods = "uart4";
146 clock-frequency = <48000000>; 164 clock-frequency = <48000000>;
147 reg = <0x481a6000 0x2000>; 165 reg = <0x481a6000 0x2000>;
148 interrupt-parent = <&intc>;
149 interrupts = <44>; 166 interrupts = <44>;
150 status = "disabled"; 167 status = "disabled";
151 }; 168 };
@@ -155,7 +172,6 @@
155 ti,hwmods = "uart5"; 172 ti,hwmods = "uart5";
156 clock-frequency = <48000000>; 173 clock-frequency = <48000000>;
157 reg = <0x481a8000 0x2000>; 174 reg = <0x481a8000 0x2000>;
158 interrupt-parent = <&intc>;
159 interrupts = <45>; 175 interrupts = <45>;
160 status = "disabled"; 176 status = "disabled";
161 }; 177 };
@@ -165,7 +181,6 @@
165 ti,hwmods = "uart6"; 181 ti,hwmods = "uart6";
166 clock-frequency = <48000000>; 182 clock-frequency = <48000000>;
167 reg = <0x481aa000 0x2000>; 183 reg = <0x481aa000 0x2000>;
168 interrupt-parent = <&intc>;
169 interrupts = <46>; 184 interrupts = <46>;
170 status = "disabled"; 185 status = "disabled";
171 }; 186 };
@@ -176,7 +191,6 @@
176 #size-cells = <0>; 191 #size-cells = <0>;
177 ti,hwmods = "i2c1"; 192 ti,hwmods = "i2c1";
178 reg = <0x44e0b000 0x1000>; 193 reg = <0x44e0b000 0x1000>;
179 interrupt-parent = <&intc>;
180 interrupts = <70>; 194 interrupts = <70>;
181 status = "disabled"; 195 status = "disabled";
182 }; 196 };
@@ -187,7 +201,6 @@
187 #size-cells = <0>; 201 #size-cells = <0>;
188 ti,hwmods = "i2c2"; 202 ti,hwmods = "i2c2";
189 reg = <0x4802a000 0x1000>; 203 reg = <0x4802a000 0x1000>;
190 interrupt-parent = <&intc>;
191 interrupts = <71>; 204 interrupts = <71>;
192 status = "disabled"; 205 status = "disabled";
193 }; 206 };
@@ -198,7 +211,6 @@
198 #size-cells = <0>; 211 #size-cells = <0>;
199 ti,hwmods = "i2c3"; 212 ti,hwmods = "i2c3";
200 reg = <0x4819c000 0x1000>; 213 reg = <0x4819c000 0x1000>;
201 interrupt-parent = <&intc>;
202 interrupts = <30>; 214 interrupts = <30>;
203 status = "disabled"; 215 status = "disabled";
204 }; 216 };
@@ -207,8 +219,124 @@
207 compatible = "ti,omap3-wdt"; 219 compatible = "ti,omap3-wdt";
208 ti,hwmods = "wd_timer2"; 220 ti,hwmods = "wd_timer2";
209 reg = <0x44e35000 0x1000>; 221 reg = <0x44e35000 0x1000>;
210 interrupt-parent = <&intc>;
211 interrupts = <91>; 222 interrupts = <91>;
212 }; 223 };
224
225 dcan0: d_can@481cc000 {
226 compatible = "bosch,d_can";
227 ti,hwmods = "d_can0";
228 reg = <0x481cc000 0x2000>;
229 interrupts = <52>;
230 status = "disabled";
231 };
232
233 dcan1: d_can@481d0000 {
234 compatible = "bosch,d_can";
235 ti,hwmods = "d_can1";
236 reg = <0x481d0000 0x2000>;
237 interrupts = <55>;
238 status = "disabled";
239 };
240
241 timer1: timer@44e31000 {
242 compatible = "ti,omap2-timer";
243 reg = <0x44e31000 0x400>;
244 interrupts = <67>;
245 ti,hwmods = "timer1";
246 ti,timer-alwon;
247 };
248
249 timer2: timer@48040000 {
250 compatible = "ti,omap2-timer";
251 reg = <0x48040000 0x400>;
252 interrupts = <68>;
253 ti,hwmods = "timer2";
254 };
255
256 timer3: timer@48042000 {
257 compatible = "ti,omap2-timer";
258 reg = <0x48042000 0x400>;
259 interrupts = <69>;
260 ti,hwmods = "timer3";
261 };
262
263 timer4: timer@48044000 {
264 compatible = "ti,omap2-timer";
265 reg = <0x48044000 0x400>;
266 interrupts = <92>;
267 ti,hwmods = "timer4";
268 ti,timer-pwm;
269 };
270
271 timer5: timer@48046000 {
272 compatible = "ti,omap2-timer";
273 reg = <0x48046000 0x400>;
274 interrupts = <93>;
275 ti,hwmods = "timer5";
276 ti,timer-pwm;
277 };
278
279 timer6: timer@48048000 {
280 compatible = "ti,omap2-timer";
281 reg = <0x48048000 0x400>;
282 interrupts = <94>;
283 ti,hwmods = "timer6";
284 ti,timer-pwm;
285 };
286
287 timer7: timer@4804a000 {
288 compatible = "ti,omap2-timer";
289 reg = <0x4804a000 0x400>;
290 interrupts = <95>;
291 ti,hwmods = "timer7";
292 ti,timer-pwm;
293 };
294
295 rtc@44e3e000 {
296 compatible = "ti,da830-rtc";
297 reg = <0x44e3e000 0x1000>;
298 interrupts = <75
299 76>;
300 ti,hwmods = "rtc";
301 };
302
303 spi0: spi@48030000 {
304 compatible = "ti,omap4-mcspi";
305 #address-cells = <1>;
306 #size-cells = <0>;
307 reg = <0x48030000 0x400>;
308 interrupt = <65>;
309 ti,spi-num-cs = <2>;
310 ti,hwmods = "spi0";
311 status = "disabled";
312 };
313
314 spi1: spi@481a0000 {
315 compatible = "ti,omap4-mcspi";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 reg = <0x481a0000 0x400>;
319 interrupt = <125>;
320 ti,spi-num-cs = <2>;
321 ti,hwmods = "spi1";
322 status = "disabled";
323 };
324
325 usb@47400000 {
326 compatible = "ti,musb-am33xx";
327 reg = <0x47400000 0x1000 /* usbss */
328 0x47401000 0x800 /* musb instance 0 */
329 0x47401800 0x800>; /* musb instance 1 */
330 interrupts = <17 /* usbss */
331 18 /* musb instance 0 */
332 19>; /* musb instance 1 */
333 multipoint = <1>;
334 num-eps = <16>;
335 ram-bits = <12>;
336 port0-mode = <3>;
337 port1-mode = <3>;
338 power = <250>;
339 ti,hwmods = "usb_otg_hs";
340 };
213 }; 341 };
214}; 342};
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 581cb081cb0f..761c4b69b25b 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2420", "ti,omap2";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -65,5 +66,90 @@
65 ti,hwmods = "uart3"; 66 ti,hwmods = "uart3";
66 clock-frequency = <48000000>; 67 clock-frequency = <48000000>;
67 }; 68 };
69
70 timer2: timer@4802a000 {
71 compatible = "ti,omap2-timer";
72 reg = <0x4802a000 0x400>;
73 interrupts = <38>;
74 ti,hwmods = "timer2";
75 };
76
77 timer3: timer@48078000 {
78 compatible = "ti,omap2-timer";
79 reg = <0x48078000 0x400>;
80 interrupts = <39>;
81 ti,hwmods = "timer3";
82 };
83
84 timer4: timer@4807a000 {
85 compatible = "ti,omap2-timer";
86 reg = <0x4807a000 0x400>;
87 interrupts = <40>;
88 ti,hwmods = "timer4";
89 };
90
91 timer5: timer@4807c000 {
92 compatible = "ti,omap2-timer";
93 reg = <0x4807c000 0x400>;
94 interrupts = <41>;
95 ti,hwmods = "timer5";
96 ti,timer-dsp;
97 };
98
99 timer6: timer@4807e000 {
100 compatible = "ti,omap2-timer";
101 reg = <0x4807e000 0x400>;
102 interrupts = <42>;
103 ti,hwmods = "timer6";
104 ti,timer-dsp;
105 };
106
107 timer7: timer@48080000 {
108 compatible = "ti,omap2-timer";
109 reg = <0x48080000 0x400>;
110 interrupts = <43>;
111 ti,hwmods = "timer7";
112 ti,timer-dsp;
113 };
114
115 timer8: timer@48082000 {
116 compatible = "ti,omap2-timer";
117 reg = <0x48082000 0x400>;
118 interrupts = <44>;
119 ti,hwmods = "timer8";
120 ti,timer-dsp;
121 };
122
123 timer9: timer@48084000 {
124 compatible = "ti,omap2-timer";
125 reg = <0x48084000 0x400>;
126 interrupts = <45>;
127 ti,hwmods = "timer9";
128 ti,timer-pwm;
129 };
130
131 timer10: timer@48086000 {
132 compatible = "ti,omap2-timer";
133 reg = <0x48086000 0x400>;
134 interrupts = <46>;
135 ti,hwmods = "timer10";
136 ti,timer-pwm;
137 };
138
139 timer11: timer@48088000 {
140 compatible = "ti,omap2-timer";
141 reg = <0x48088000 0x400>;
142 interrupts = <47>;
143 ti,hwmods = "timer11";
144 ti,timer-pwm;
145 };
146
147 timer12: timer@4808a000 {
148 compatible = "ti,omap2-timer";
149 reg = <0x4808a000 0x400>;
150 interrupts = <48>;
151 ti,hwmods = "timer12";
152 ti,timer-pwm;
153 };
68 }; 154 };
69}; 155};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index bfd76b4a0ddc..af6560908905 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,12 @@
14 compatible = "ti,omap2420", "ti,omap2"; 14 compatible = "ti,omap2420", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 counter32k: counter@48004000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x48004000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
17 omap2420_pmx: pinmux@48000030 { 23 omap2420_pmx: pinmux@48000030 {
18 compatible = "ti,omap2420-padconf", "pinctrl-single"; 24 compatible = "ti,omap2420-padconf", "pinctrl-single";
19 reg = <0x48000030 0x0113>; 25 reg = <0x48000030 0x0113>;
@@ -30,7 +36,6 @@
30 interrupts = <59>, /* TX interrupt */ 36 interrupts = <59>, /* TX interrupt */
31 <60>; /* RX interrupt */ 37 <60>; /* RX interrupt */
32 interrupt-names = "tx", "rx"; 38 interrupt-names = "tx", "rx";
33 interrupt-parent = <&intc>;
34 ti,hwmods = "mcbsp1"; 39 ti,hwmods = "mcbsp1";
35 }; 40 };
36 41
@@ -41,8 +46,15 @@
41 interrupts = <62>, /* TX interrupt */ 46 interrupts = <62>, /* TX interrupt */
42 <63>; /* RX interrupt */ 47 <63>; /* RX interrupt */
43 interrupt-names = "tx", "rx"; 48 interrupt-names = "tx", "rx";
44 interrupt-parent = <&intc>;
45 ti,hwmods = "mcbsp2"; 49 ti,hwmods = "mcbsp2";
46 }; 50 };
51
52 timer1: timer@48028000 {
53 compatible = "ti,omap2-timer";
54 reg = <0x48028000 0x400>;
55 interrupts = <37>;
56 ti,hwmods = "timer1";
57 ti,timer-alwon;
58 };
47 }; 59 };
48}; 60};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index 4565d9750f4d..c3924457c9b6 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,12 @@
14 compatible = "ti,omap2430", "ti,omap2"; 14 compatible = "ti,omap2430", "ti,omap2";
15 15
16 ocp { 16 ocp {
17 counter32k: counter@49020000 {
18 compatible = "ti,omap-counter32k";
19 reg = <0x49020000 0x20>;
20 ti,hwmods = "counter_32k";
21 };
22
17 omap2430_pmx: pinmux@49002030 { 23 omap2430_pmx: pinmux@49002030 {
18 compatible = "ti,omap2430-padconf", "pinctrl-single"; 24 compatible = "ti,omap2430-padconf", "pinctrl-single";
19 reg = <0x49002030 0x0154>; 25 reg = <0x49002030 0x0154>;
@@ -32,7 +38,6 @@
32 <60>, /* RX interrupt */ 38 <60>, /* RX interrupt */
33 <61>; /* RX overflow interrupt */ 39 <61>; /* RX overflow interrupt */
34 interrupt-names = "common", "tx", "rx", "rx_overflow"; 40 interrupt-names = "common", "tx", "rx", "rx_overflow";
35 interrupt-parent = <&intc>;
36 ti,buffer-size = <128>; 41 ti,buffer-size = <128>;
37 ti,hwmods = "mcbsp1"; 42 ti,hwmods = "mcbsp1";
38 }; 43 };
@@ -45,7 +50,6 @@
45 <62>, /* TX interrupt */ 50 <62>, /* TX interrupt */
46 <63>; /* RX interrupt */ 51 <63>; /* RX interrupt */
47 interrupt-names = "common", "tx", "rx"; 52 interrupt-names = "common", "tx", "rx";
48 interrupt-parent = <&intc>;
49 ti,buffer-size = <128>; 53 ti,buffer-size = <128>;
50 ti,hwmods = "mcbsp2"; 54 ti,hwmods = "mcbsp2";
51 }; 55 };
@@ -58,7 +62,6 @@
58 <89>, /* TX interrupt */ 62 <89>, /* TX interrupt */
59 <90>; /* RX interrupt */ 63 <90>; /* RX interrupt */
60 interrupt-names = "common", "tx", "rx"; 64 interrupt-names = "common", "tx", "rx";
61 interrupt-parent = <&intc>;
62 ti,buffer-size = <128>; 65 ti,buffer-size = <128>;
63 ti,hwmods = "mcbsp3"; 66 ti,hwmods = "mcbsp3";
64 }; 67 };
@@ -71,7 +74,6 @@
71 <54>, /* TX interrupt */ 74 <54>, /* TX interrupt */
72 <55>; /* RX interrupt */ 75 <55>; /* RX interrupt */
73 interrupt-names = "common", "tx", "rx"; 76 interrupt-names = "common", "tx", "rx";
74 interrupt-parent = <&intc>;
75 ti,buffer-size = <128>; 77 ti,buffer-size = <128>;
76 ti,hwmods = "mcbsp4"; 78 ti,hwmods = "mcbsp4";
77 }; 79 };
@@ -84,9 +86,16 @@
84 <81>, /* TX interrupt */ 86 <81>, /* TX interrupt */
85 <82>; /* RX interrupt */ 87 <82>; /* RX interrupt */
86 interrupt-names = "common", "tx", "rx"; 88 interrupt-names = "common", "tx", "rx";
87 interrupt-parent = <&intc>;
88 ti,buffer-size = <128>; 89 ti,buffer-size = <128>;
89 ti,hwmods = "mcbsp5"; 90 ti,hwmods = "mcbsp5";
90 }; 91 };
92
93 timer1: timer@49018000 {
94 compatible = "ti,omap2-timer";
95 reg = <0x49018000 0x400>;
96 interrupts = <37>;
97 ti,hwmods = "timer1";
98 ti,timer-alwon;
99 };
91 }; 100 };
92}; 101};
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index c38cf76df81f..3705a81c1fc2 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -55,12 +55,6 @@
55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */ 55 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
56 interrupt-parent = <&intc>; 56 interrupt-parent = <&intc>;
57 57
58 vsim: regulator-vsim {
59 compatible = "ti,twl4030-vsim";
60 regulator-min-microvolt = <1800000>;
61 regulator-max-microvolt = <3000000>;
62 };
63
64 twl_audio: audio { 58 twl_audio: audio {
65 compatible = "ti,twl4030-audio"; 59 compatible = "ti,twl4030-audio";
66 codec { 60 codec {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
new file mode 100644
index 000000000000..f624dc85d441
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -0,0 +1,67 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10/include/ "omap3.dtsi"
11
12/ {
13 model = "TI OMAP3 BeagleBoard";
14 compatible = "ti,omap3-beagle", "ti,omap3";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x10000000>; /* 256 MB */
19 };
20
21 leds {
22 compatible = "gpio-leds";
23 pmu_stat {
24 label = "beagleboard::pmu_stat";
25 gpios = <&twl_gpio 19 0>; /* LEDB */
26 };
27
28 heartbeat {
29 label = "beagleboard::usr0";
30 gpios = <&gpio5 22 0>; /* 150 -> D6 LED */
31 linux,default-trigger = "heartbeat";
32 };
33
34 mmc {
35 label = "beagleboard::usr1";
36 gpios = <&gpio5 21 0>; /* 149 -> D7 LED */
37 linux,default-trigger = "mmc0";
38 };
39 };
40
41};
42
43&i2c1 {
44 clock-frequency = <2600000>;
45
46 twl: twl@48 {
47 reg = <0x48>;
48 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
49 interrupt-parent = <&intc>;
50 };
51};
52
53/include/ "twl4030.dtsi"
54
55&mmc1 {
56 vmmc-supply = <&vmmc1>;
57 vmmc_aux-supply = <&vsim>;
58 bus-width = <8>;
59};
60
61&mmc2 {
62 status = "disabled";
63};
64
65&mmc3 {
66 status = "disabled";
67};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 696e929d0304..1acc26148ffc 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -12,6 +12,7 @@
12 12
13/ { 13/ {
14 compatible = "ti,omap3430", "ti,omap3"; 14 compatible = "ti,omap3430", "ti,omap3";
15 interrupt-parent = <&intc>;
15 16
16 aliases { 17 aliases {
17 serial0 = &uart1; 18 serial0 = &uart1;
@@ -60,6 +61,12 @@
60 ranges; 61 ranges;
61 ti,hwmods = "l3_main"; 62 ti,hwmods = "l3_main";
62 63
64 counter32k: counter@48320000 {
65 compatible = "ti,omap-counter32k";
66 reg = <0x48320000 0x20>;
67 ti,hwmods = "counter_32k";
68 };
69
63 intc: interrupt-controller@48200000 { 70 intc: interrupt-controller@48200000 {
64 compatible = "ti,omap2-intc"; 71 compatible = "ti,omap2-intc";
65 interrupt-controller; 72 interrupt-controller;
@@ -240,7 +247,6 @@
240 <59>, /* TX interrupt */ 247 <59>, /* TX interrupt */
241 <60>; /* RX interrupt */ 248 <60>; /* RX interrupt */
242 interrupt-names = "common", "tx", "rx"; 249 interrupt-names = "common", "tx", "rx";
243 interrupt-parent = <&intc>;
244 ti,buffer-size = <128>; 250 ti,buffer-size = <128>;
245 ti,hwmods = "mcbsp1"; 251 ti,hwmods = "mcbsp1";
246 }; 252 };
@@ -255,7 +261,6 @@
255 <63>, /* RX interrupt */ 261 <63>, /* RX interrupt */
256 <4>; /* Sidetone */ 262 <4>; /* Sidetone */
257 interrupt-names = "common", "tx", "rx", "sidetone"; 263 interrupt-names = "common", "tx", "rx", "sidetone";
258 interrupt-parent = <&intc>;
259 ti,buffer-size = <1280>; 264 ti,buffer-size = <1280>;
260 ti,hwmods = "mcbsp2", "mcbsp2_sidetone"; 265 ti,hwmods = "mcbsp2", "mcbsp2_sidetone";
261 }; 266 };
@@ -270,7 +275,6 @@
270 <90>, /* RX interrupt */ 275 <90>, /* RX interrupt */
271 <5>; /* Sidetone */ 276 <5>; /* Sidetone */
272 interrupt-names = "common", "tx", "rx", "sidetone"; 277 interrupt-names = "common", "tx", "rx", "sidetone";
273 interrupt-parent = <&intc>;
274 ti,buffer-size = <128>; 278 ti,buffer-size = <128>;
275 ti,hwmods = "mcbsp3", "mcbsp3_sidetone"; 279 ti,hwmods = "mcbsp3", "mcbsp3_sidetone";
276 }; 280 };
@@ -283,7 +287,6 @@
283 <54>, /* TX interrupt */ 287 <54>, /* TX interrupt */
284 <55>; /* RX interrupt */ 288 <55>; /* RX interrupt */
285 interrupt-names = "common", "tx", "rx"; 289 interrupt-names = "common", "tx", "rx";
286 interrupt-parent = <&intc>;
287 ti,buffer-size = <128>; 290 ti,buffer-size = <128>;
288 ti,hwmods = "mcbsp4"; 291 ti,hwmods = "mcbsp4";
289 }; 292 };
@@ -296,9 +299,103 @@
296 <81>, /* TX interrupt */ 299 <81>, /* TX interrupt */
297 <82>; /* RX interrupt */ 300 <82>; /* RX interrupt */
298 interrupt-names = "common", "tx", "rx"; 301 interrupt-names = "common", "tx", "rx";
299 interrupt-parent = <&intc>;
300 ti,buffer-size = <128>; 302 ti,buffer-size = <128>;
301 ti,hwmods = "mcbsp5"; 303 ti,hwmods = "mcbsp5";
302 }; 304 };
305
306 timer1: timer@48318000 {
307 compatible = "ti,omap2-timer";
308 reg = <0x48318000 0x400>;
309 interrupts = <37>;
310 ti,hwmods = "timer1";
311 ti,timer-alwon;
312 };
313
314 timer2: timer@49032000 {
315 compatible = "ti,omap2-timer";
316 reg = <0x49032000 0x400>;
317 interrupts = <38>;
318 ti,hwmods = "timer2";
319 };
320
321 timer3: timer@49034000 {
322 compatible = "ti,omap2-timer";
323 reg = <0x49034000 0x400>;
324 interrupts = <39>;
325 ti,hwmods = "timer3";
326 };
327
328 timer4: timer@49036000 {
329 compatible = "ti,omap2-timer";
330 reg = <0x49036000 0x400>;
331 interrupts = <40>;
332 ti,hwmods = "timer4";
333 };
334
335 timer5: timer@49038000 {
336 compatible = "ti,omap2-timer";
337 reg = <0x49038000 0x400>;
338 interrupts = <41>;
339 ti,hwmods = "timer5";
340 ti,timer-dsp;
341 };
342
343 timer6: timer@4903a000 {
344 compatible = "ti,omap2-timer";
345 reg = <0x4903a000 0x400>;
346 interrupts = <42>;
347 ti,hwmods = "timer6";
348 ti,timer-dsp;
349 };
350
351 timer7: timer@4903c000 {
352 compatible = "ti,omap2-timer";
353 reg = <0x4903c000 0x400>;
354 interrupts = <43>;
355 ti,hwmods = "timer7";
356 ti,timer-dsp;
357 };
358
359 timer8: timer@4903e000 {
360 compatible = "ti,omap2-timer";
361 reg = <0x4903e000 0x400>;
362 interrupts = <44>;
363 ti,hwmods = "timer8";
364 ti,timer-pwm;
365 ti,timer-dsp;
366 };
367
368 timer9: timer@49040000 {
369 compatible = "ti,omap2-timer";
370 reg = <0x49040000 0x400>;
371 interrupts = <45>;
372 ti,hwmods = "timer9";
373 ti,timer-pwm;
374 };
375
376 timer10: timer@48086000 {
377 compatible = "ti,omap2-timer";
378 reg = <0x48086000 0x400>;
379 interrupts = <46>;
380 ti,hwmods = "timer10";
381 ti,timer-pwm;
382 };
383
384 timer11: timer@48088000 {
385 compatible = "ti,omap2-timer";
386 reg = <0x48088000 0x400>;
387 interrupts = <47>;
388 ti,hwmods = "timer11";
389 ti,timer-pwm;
390 };
391
392 timer12: timer@48304000 {
393 compatible = "ti,omap2-timer";
394 reg = <0x48304000 0x400>;
395 interrupts = <95>;
396 ti,hwmods = "timer12";
397 ti,timer-alwon;
398 ti,timer-secure;
399 };
303 }; 400 };
304}; 401};
diff --git a/arch/arm/boot/dts/omap4-panda-a4.dts b/arch/arm/boot/dts/omap4-panda-a4.dts
new file mode 100644
index 000000000000..75466d2abfb5
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-panda-a4.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-panda.dts"
9
10/* Pandaboard Rev A4+ have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-panda-es.dts
index d4ba43a48d9b..73bc1a67e444 100644
--- a/arch/arm/boot/dts/omap4-pandaES.dts
+++ b/arch/arm/boot/dts/omap4-panda-es.dts
@@ -22,3 +22,12 @@
22 "AFML", "Line In", 22 "AFML", "Line In",
23 "AFMR", "Line In"; 23 "AFMR", "Line In";
24}; 24};
25
26/* PandaboardES has external pullups on SCL & SDA */
27&dss_hdmi_pins {
28 pinctrl-single,pins = <
29 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
30 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
31 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
32 >;
33};
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index e8f927cbb376..4122efe31cfd 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -65,6 +65,8 @@
65 &twl6040_pins 65 &twl6040_pins
66 &mcpdm_pins 66 &mcpdm_pins
67 &mcbsp1_pins 67 &mcbsp1_pins
68 &dss_hdmi_pins
69 &tpd12s015_pins
68 >; 70 >;
69 71
70 twl6040_pins: pinmux_twl6040_pins { 72 twl6040_pins: pinmux_twl6040_pins {
@@ -92,6 +94,22 @@
92 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */ 94 0xc4 0x100 /* abe_mcbsp1_fsx.abe_mcbsp1_fsx INPUT | MODE0 */
93 >; 95 >;
94 }; 96 };
97
98 dss_hdmi_pins: pinmux_dss_hdmi_pins {
99 pinctrl-single,pins = <
100 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
101 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
102 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
103 >;
104 };
105
106 tpd12s015_pins: pinmux_tpd12s015_pins {
107 pinctrl-single,pins = <
108 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
109 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
110 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
111 >;
112 };
95}; 113};
96 114
97&i2c1 { 115&i2c1 {
@@ -184,3 +202,7 @@
184&dmic { 202&dmic {
185 status = "disabled"; 203 status = "disabled";
186}; 204};
205
206&twl_usb_comparator {
207 usb-supply = <&vusb>;
208};
diff --git a/arch/arm/boot/dts/omap4-sdp-es23plus.dts b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
new file mode 100644
index 000000000000..b4a40ffbce31
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-sdp-es23plus.dts
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/include/ "omap4-sdp.dts"
9
10/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
11&dss_hdmi_pins {
12 pinctrl-single,pins = <
13 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
14 0x5c 0x100 /* hdmi_scl.hdmi_scl INPUT | MODE 0 */
15 0x5e 0x100 /* hdmi_sda.hdmi_sda INPUT | MODE 0 */
16 >;
17};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 5b7e04fbff50..43e5258a9372 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -124,6 +124,8 @@
124 &dmic_pins 124 &dmic_pins
125 &mcbsp1_pins 125 &mcbsp1_pins
126 &mcbsp2_pins 126 &mcbsp2_pins
127 &dss_hdmi_pins
128 &tpd12s015_pins
127 >; 129 >;
128 130
129 uart2_pins: pinmux_uart2_pins { 131 uart2_pins: pinmux_uart2_pins {
@@ -194,6 +196,22 @@
194 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */ 196 0xbc 0x100 /* abe_mcbsp2_fsx.abe_mcbsp2_fsx INPUT | MODE0 */
195 >; 197 >;
196 }; 198 };
199
200 dss_hdmi_pins: pinmux_dss_hdmi_pins {
201 pinctrl-single,pins = <
202 0x5a 0x118 /* hdmi_cec.hdmi_cec INPUT PULLUP | MODE 0 */
203 0x5c 0x118 /* hdmi_scl.hdmi_scl INPUT PULLUP | MODE 0 */
204 0x5e 0x118 /* hdmi_sda.hdmi_sda INPUT PULLUP | MODE 0 */
205 >;
206 };
207
208 tpd12s015_pins: pinmux_tpd12s015_pins {
209 pinctrl-single,pins = <
210 0x22 0x3 /* gpmc_a17.gpio_41 OUTPUT | MODE3 */
211 0x48 0x3 /* gpmc_nbe1.gpio_60 OUTPUT | MODE3 */
212 0x58 0x10b /* hdmi_hpd.gpio_63 INPUT PULLDOWN | MODE3 */
213 >;
214 };
197}; 215};
198 216
199&i2c1 { 217&i2c1 {
@@ -406,3 +424,7 @@
406&mcbsp3 { 424&mcbsp3 {
407 status = "disabled"; 425 status = "disabled";
408}; 426};
427
428&twl_usb_comparator {
429 usb-supply = <&vusb>;
430};
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var-som.dts
index 6601e6af6092..6601e6af6092 100644
--- a/arch/arm/boot/dts/omap4-var_som.dts
+++ b/arch/arm/boot/dts/omap4-var-som.dts
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 3883f94fdbd0..739bb79e410e 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -95,6 +95,12 @@
95 ranges; 95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
97 97
98 counter32k: counter@4a304000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4a304000 0x20>;
101 ti,hwmods = "counter_32k";
102 };
103
98 omap4_pmx_core: pinmux@4a100040 { 104 omap4_pmx_core: pinmux@4a100040 {
99 compatible = "ti,omap4-padconf", "pinctrl-single"; 105 compatible = "ti,omap4-padconf", "pinctrl-single";
100 reg = <0x4a100040 0x0196>; 106 reg = <0x4a100040 0x0196>;
@@ -340,7 +346,6 @@
340 <0x49032000 0x7f>; /* L3 Interconnect */ 346 <0x49032000 0x7f>; /* L3 Interconnect */
341 reg-names = "mpu", "dma"; 347 reg-names = "mpu", "dma";
342 interrupts = <0 112 0x4>; 348 interrupts = <0 112 0x4>;
343 interrupt-parent = <&gic>;
344 ti,hwmods = "mcpdm"; 349 ti,hwmods = "mcpdm";
345 }; 350 };
346 351
@@ -350,7 +355,6 @@
350 <0x4902e000 0x7f>; /* L3 Interconnect */ 355 <0x4902e000 0x7f>; /* L3 Interconnect */
351 reg-names = "mpu", "dma"; 356 reg-names = "mpu", "dma";
352 interrupts = <0 114 0x4>; 357 interrupts = <0 114 0x4>;
353 interrupt-parent = <&gic>;
354 ti,hwmods = "dmic"; 358 ti,hwmods = "dmic";
355 }; 359 };
356 360
@@ -361,7 +365,6 @@
361 reg-names = "mpu", "dma"; 365 reg-names = "mpu", "dma";
362 interrupts = <0 17 0x4>; 366 interrupts = <0 17 0x4>;
363 interrupt-names = "common"; 367 interrupt-names = "common";
364 interrupt-parent = <&gic>;
365 ti,buffer-size = <128>; 368 ti,buffer-size = <128>;
366 ti,hwmods = "mcbsp1"; 369 ti,hwmods = "mcbsp1";
367 }; 370 };
@@ -373,7 +376,6 @@
373 reg-names = "mpu", "dma"; 376 reg-names = "mpu", "dma";
374 interrupts = <0 22 0x4>; 377 interrupts = <0 22 0x4>;
375 interrupt-names = "common"; 378 interrupt-names = "common";
376 interrupt-parent = <&gic>;
377 ti,buffer-size = <128>; 379 ti,buffer-size = <128>;
378 ti,hwmods = "mcbsp2"; 380 ti,hwmods = "mcbsp2";
379 }; 381 };
@@ -385,7 +387,6 @@
385 reg-names = "mpu", "dma"; 387 reg-names = "mpu", "dma";
386 interrupts = <0 23 0x4>; 388 interrupts = <0 23 0x4>;
387 interrupt-names = "common"; 389 interrupt-names = "common";
388 interrupt-parent = <&gic>;
389 ti,buffer-size = <128>; 390 ti,buffer-size = <128>;
390 ti,hwmods = "mcbsp3"; 391 ti,hwmods = "mcbsp3";
391 }; 392 };
@@ -396,7 +397,6 @@
396 reg-names = "mpu"; 397 reg-names = "mpu";
397 interrupts = <0 16 0x4>; 398 interrupts = <0 16 0x4>;
398 interrupt-names = "common"; 399 interrupt-names = "common";
399 interrupt-parent = <&gic>;
400 ti,buffer-size = <128>; 400 ti,buffer-size = <128>;
401 ti,hwmods = "mcbsp4"; 401 ti,hwmods = "mcbsp4";
402 }; 402 };
@@ -431,12 +431,103 @@
431 hw-caps-temp-alert; 431 hw-caps-temp-alert;
432 }; 432 };
433 433
434 ocp2scp { 434 ocp2scp@4a0ad000 {
435 compatible = "ti,omap-ocp2scp"; 435 compatible = "ti,omap-ocp2scp";
436 reg = <0x4a0ad000 0x1f>;
436 #address-cells = <1>; 437 #address-cells = <1>;
437 #size-cells = <1>; 438 #size-cells = <1>;
438 ranges; 439 ranges;
439 ti,hwmods = "ocp2scp_usb_phy"; 440 ti,hwmods = "ocp2scp_usb_phy";
440 }; 441 };
442
443 timer1: timer@4a318000 {
444 compatible = "ti,omap2-timer";
445 reg = <0x4a318000 0x80>;
446 interrupts = <0 37 0x4>;
447 ti,hwmods = "timer1";
448 ti,timer-alwon;
449 };
450
451 timer2: timer@48032000 {
452 compatible = "ti,omap2-timer";
453 reg = <0x48032000 0x80>;
454 interrupts = <0 38 0x4>;
455 ti,hwmods = "timer2";
456 };
457
458 timer3: timer@48034000 {
459 compatible = "ti,omap2-timer";
460 reg = <0x48034000 0x80>;
461 interrupts = <0 39 0x4>;
462 ti,hwmods = "timer3";
463 };
464
465 timer4: timer@48036000 {
466 compatible = "ti,omap2-timer";
467 reg = <0x48036000 0x80>;
468 interrupts = <0 40 0x4>;
469 ti,hwmods = "timer4";
470 };
471
472 timer5: timer@40138000 {
473 compatible = "ti,omap2-timer";
474 reg = <0x40138000 0x80>,
475 <0x49038000 0x80>;
476 interrupts = <0 41 0x4>;
477 ti,hwmods = "timer5";
478 ti,timer-dsp;
479 };
480
481 timer6: timer@4013a000 {
482 compatible = "ti,omap2-timer";
483 reg = <0x4013a000 0x80>,
484 <0x4903a000 0x80>;
485 interrupts = <0 42 0x4>;
486 ti,hwmods = "timer6";
487 ti,timer-dsp;
488 };
489
490 timer7: timer@4013c000 {
491 compatible = "ti,omap2-timer";
492 reg = <0x4013c000 0x80>,
493 <0x4903c000 0x80>;
494 interrupts = <0 43 0x4>;
495 ti,hwmods = "timer7";
496 ti,timer-dsp;
497 };
498
499 timer8: timer@4013e000 {
500 compatible = "ti,omap2-timer";
501 reg = <0x4013e000 0x80>,
502 <0x4903e000 0x80>;
503 interrupts = <0 44 0x4>;
504 ti,hwmods = "timer8";
505 ti,timer-pwm;
506 ti,timer-dsp;
507 };
508
509 timer9: timer@4803e000 {
510 compatible = "ti,omap2-timer";
511 reg = <0x4803e000 0x80>;
512 interrupts = <0 45 0x4>;
513 ti,hwmods = "timer9";
514 ti,timer-pwm;
515 };
516
517 timer10: timer@48086000 {
518 compatible = "ti,omap2-timer";
519 reg = <0x48086000 0x80>;
520 interrupts = <0 46 0x4>;
521 ti,hwmods = "timer10";
522 ti,timer-pwm;
523 };
524
525 timer11: timer@48088000 {
526 compatible = "ti,omap2-timer";
527 reg = <0x48088000 0x80>;
528 interrupts = <0 47 0x4>;
529 ti,hwmods = "timer11";
530 ti,timer-pwm;
531 };
441 }; 532 };
442}; 533};
diff --git a/arch/arm/boot/dts/omap5-evm.dts b/arch/arm/boot/dts/omap5-evm.dts
index c663eba73168..8722c15bbba2 100644
--- a/arch/arm/boot/dts/omap5-evm.dts
+++ b/arch/arm/boot/dts/omap5-evm.dts
@@ -8,6 +8,7 @@
8/dts-v1/; 8/dts-v1/;
9 9
10/include/ "omap5.dtsi" 10/include/ "omap5.dtsi"
11/include/ "samsung_k3pe0e000b.dtsi"
11 12
12/ { 13/ {
13 model = "TI OMAP5 EVM board"; 14 model = "TI OMAP5 EVM board";
@@ -15,7 +16,7 @@
15 16
16 memory { 17 memory {
17 device_type = "memory"; 18 device_type = "memory";
18 reg = <0x80000000 0x40000000>; /* 1 GB */ 19 reg = <0x80000000 0x80000000>; /* 2 GB */
19 }; 20 };
20 21
21 vmmcsd_fixed: fixedregulator-mmcsd { 22 vmmcsd_fixed: fixedregulator-mmcsd {
@@ -140,3 +141,13 @@
140&mcbsp3 { 141&mcbsp3 {
141 status = "disabled"; 142 status = "disabled";
142}; 143};
144
145&emif1 {
146 cs1-used;
147 device-handle = <&samsung_K3PE0E000B>;
148};
149
150&emif2 {
151 cs1-used;
152 device-handle = <&samsung_K3PE0E000B>;
153};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 42c78beb4fdc..790bb2a4b343 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -77,6 +77,12 @@
77 ranges; 77 ranges;
78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 78 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
79 79
80 counter32k: counter@4ae04000 {
81 compatible = "ti,omap-counter32k";
82 reg = <0x4ae04000 0x40>;
83 ti,hwmods = "counter_32k";
84 };
85
80 omap5_pmx_core: pinmux@4a002840 { 86 omap5_pmx_core: pinmux@4a002840 {
81 compatible = "ti,omap4-padconf", "pinctrl-single"; 87 compatible = "ti,omap4-padconf", "pinctrl-single";
82 reg = <0x4a002840 0x01b6>; 88 reg = <0x4a002840 0x01b6>;
@@ -104,6 +110,8 @@
104 110
105 gpio1: gpio@4ae10000 { 111 gpio1: gpio@4ae10000 {
106 compatible = "ti,omap4-gpio"; 112 compatible = "ti,omap4-gpio";
113 reg = <0x4ae10000 0x200>;
114 interrupts = <0 29 0x4>;
107 ti,hwmods = "gpio1"; 115 ti,hwmods = "gpio1";
108 gpio-controller; 116 gpio-controller;
109 #gpio-cells = <2>; 117 #gpio-cells = <2>;
@@ -113,6 +121,8 @@
113 121
114 gpio2: gpio@48055000 { 122 gpio2: gpio@48055000 {
115 compatible = "ti,omap4-gpio"; 123 compatible = "ti,omap4-gpio";
124 reg = <0x48055000 0x200>;
125 interrupts = <0 30 0x4>;
116 ti,hwmods = "gpio2"; 126 ti,hwmods = "gpio2";
117 gpio-controller; 127 gpio-controller;
118 #gpio-cells = <2>; 128 #gpio-cells = <2>;
@@ -122,6 +132,8 @@
122 132
123 gpio3: gpio@48057000 { 133 gpio3: gpio@48057000 {
124 compatible = "ti,omap4-gpio"; 134 compatible = "ti,omap4-gpio";
135 reg = <0x48057000 0x200>;
136 interrupts = <0 31 0x4>;
125 ti,hwmods = "gpio3"; 137 ti,hwmods = "gpio3";
126 gpio-controller; 138 gpio-controller;
127 #gpio-cells = <2>; 139 #gpio-cells = <2>;
@@ -131,6 +143,8 @@
131 143
132 gpio4: gpio@48059000 { 144 gpio4: gpio@48059000 {
133 compatible = "ti,omap4-gpio"; 145 compatible = "ti,omap4-gpio";
146 reg = <0x48059000 0x200>;
147 interrupts = <0 32 0x4>;
134 ti,hwmods = "gpio4"; 148 ti,hwmods = "gpio4";
135 gpio-controller; 149 gpio-controller;
136 #gpio-cells = <2>; 150 #gpio-cells = <2>;
@@ -140,6 +154,8 @@
140 154
141 gpio5: gpio@4805b000 { 155 gpio5: gpio@4805b000 {
142 compatible = "ti,omap4-gpio"; 156 compatible = "ti,omap4-gpio";
157 reg = <0x4805b000 0x200>;
158 interrupts = <0 33 0x4>;
143 ti,hwmods = "gpio5"; 159 ti,hwmods = "gpio5";
144 gpio-controller; 160 gpio-controller;
145 #gpio-cells = <2>; 161 #gpio-cells = <2>;
@@ -149,6 +165,8 @@
149 165
150 gpio6: gpio@4805d000 { 166 gpio6: gpio@4805d000 {
151 compatible = "ti,omap4-gpio"; 167 compatible = "ti,omap4-gpio";
168 reg = <0x4805d000 0x200>;
169 interrupts = <0 34 0x4>;
152 ti,hwmods = "gpio6"; 170 ti,hwmods = "gpio6";
153 gpio-controller; 171 gpio-controller;
154 #gpio-cells = <2>; 172 #gpio-cells = <2>;
@@ -158,6 +176,8 @@
158 176
159 gpio7: gpio@48051000 { 177 gpio7: gpio@48051000 {
160 compatible = "ti,omap4-gpio"; 178 compatible = "ti,omap4-gpio";
179 reg = <0x48051000 0x200>;
180 interrupts = <0 35 0x4>;
161 ti,hwmods = "gpio7"; 181 ti,hwmods = "gpio7";
162 gpio-controller; 182 gpio-controller;
163 #gpio-cells = <2>; 183 #gpio-cells = <2>;
@@ -167,6 +187,8 @@
167 187
168 gpio8: gpio@48053000 { 188 gpio8: gpio@48053000 {
169 compatible = "ti,omap4-gpio"; 189 compatible = "ti,omap4-gpio";
190 reg = <0x48053000 0x200>;
191 interrupts = <0 121 0x4>;
170 ti,hwmods = "gpio8"; 192 ti,hwmods = "gpio8";
171 gpio-controller; 193 gpio-controller;
172 #gpio-cells = <2>; 194 #gpio-cells = <2>;
@@ -176,6 +198,8 @@
176 198
177 i2c1: i2c@48070000 { 199 i2c1: i2c@48070000 {
178 compatible = "ti,omap4-i2c"; 200 compatible = "ti,omap4-i2c";
201 reg = <0x48070000 0x100>;
202 interrupts = <0 56 0x4>;
179 #address-cells = <1>; 203 #address-cells = <1>;
180 #size-cells = <0>; 204 #size-cells = <0>;
181 ti,hwmods = "i2c1"; 205 ti,hwmods = "i2c1";
@@ -183,6 +207,8 @@
183 207
184 i2c2: i2c@48072000 { 208 i2c2: i2c@48072000 {
185 compatible = "ti,omap4-i2c"; 209 compatible = "ti,omap4-i2c";
210 reg = <0x48072000 0x100>;
211 interrupts = <0 57 0x4>;
186 #address-cells = <1>; 212 #address-cells = <1>;
187 #size-cells = <0>; 213 #size-cells = <0>;
188 ti,hwmods = "i2c2"; 214 ti,hwmods = "i2c2";
@@ -190,20 +216,26 @@
190 216
191 i2c3: i2c@48060000 { 217 i2c3: i2c@48060000 {
192 compatible = "ti,omap4-i2c"; 218 compatible = "ti,omap4-i2c";
219 reg = <0x48060000 0x100>;
220 interrupts = <0 61 0x4>;
193 #address-cells = <1>; 221 #address-cells = <1>;
194 #size-cells = <0>; 222 #size-cells = <0>;
195 ti,hwmods = "i2c3"; 223 ti,hwmods = "i2c3";
196 }; 224 };
197 225
198 i2c4: i2c@4807A000 { 226 i2c4: i2c@4807a000 {
199 compatible = "ti,omap4-i2c"; 227 compatible = "ti,omap4-i2c";
228 reg = <0x4807a000 0x100>;
229 interrupts = <0 62 0x4>;
200 #address-cells = <1>; 230 #address-cells = <1>;
201 #size-cells = <0>; 231 #size-cells = <0>;
202 ti,hwmods = "i2c4"; 232 ti,hwmods = "i2c4";
203 }; 233 };
204 234
205 i2c5: i2c@4807C000 { 235 i2c5: i2c@4807c000 {
206 compatible = "ti,omap4-i2c"; 236 compatible = "ti,omap4-i2c";
237 reg = <0x4807c000 0x100>;
238 interrupts = <0 60 0x4>;
207 #address-cells = <1>; 239 #address-cells = <1>;
208 #size-cells = <0>; 240 #size-cells = <0>;
209 ti,hwmods = "i2c5"; 241 ti,hwmods = "i2c5";
@@ -211,42 +243,56 @@
211 243
212 uart1: serial@4806a000 { 244 uart1: serial@4806a000 {
213 compatible = "ti,omap4-uart"; 245 compatible = "ti,omap4-uart";
246 reg = <0x4806a000 0x100>;
247 interrupts = <0 72 0x4>;
214 ti,hwmods = "uart1"; 248 ti,hwmods = "uart1";
215 clock-frequency = <48000000>; 249 clock-frequency = <48000000>;
216 }; 250 };
217 251
218 uart2: serial@4806c000 { 252 uart2: serial@4806c000 {
219 compatible = "ti,omap4-uart"; 253 compatible = "ti,omap4-uart";
254 reg = <0x4806c000 0x100>;
255 interrupts = <0 73 0x4>;
220 ti,hwmods = "uart2"; 256 ti,hwmods = "uart2";
221 clock-frequency = <48000000>; 257 clock-frequency = <48000000>;
222 }; 258 };
223 259
224 uart3: serial@48020000 { 260 uart3: serial@48020000 {
225 compatible = "ti,omap4-uart"; 261 compatible = "ti,omap4-uart";
262 reg = <0x48020000 0x100>;
263 interrupts = <0 74 0x4>;
226 ti,hwmods = "uart3"; 264 ti,hwmods = "uart3";
227 clock-frequency = <48000000>; 265 clock-frequency = <48000000>;
228 }; 266 };
229 267
230 uart4: serial@4806e000 { 268 uart4: serial@4806e000 {
231 compatible = "ti,omap4-uart"; 269 compatible = "ti,omap4-uart";
270 reg = <0x4806e000 0x100>;
271 interrupts = <0 70 0x4>;
232 ti,hwmods = "uart4"; 272 ti,hwmods = "uart4";
233 clock-frequency = <48000000>; 273 clock-frequency = <48000000>;
234 }; 274 };
235 275
236 uart5: serial@48066000 { 276 uart5: serial@48066000 {
237 compatible = "ti,omap5-uart"; 277 compatible = "ti,omap4-uart";
278 reg = <0x48066000 0x100>;
279 interrupts = <0 105 0x4>;
238 ti,hwmods = "uart5"; 280 ti,hwmods = "uart5";
239 clock-frequency = <48000000>; 281 clock-frequency = <48000000>;
240 }; 282 };
241 283
242 uart6: serial@48068000 { 284 uart6: serial@48068000 {
243 compatible = "ti,omap6-uart"; 285 compatible = "ti,omap4-uart";
286 reg = <0x48068000 0x100>;
287 interrupts = <0 106 0x4>;
244 ti,hwmods = "uart6"; 288 ti,hwmods = "uart6";
245 clock-frequency = <48000000>; 289 clock-frequency = <48000000>;
246 }; 290 };
247 291
248 mmc1: mmc@4809c000 { 292 mmc1: mmc@4809c000 {
249 compatible = "ti,omap4-hsmmc"; 293 compatible = "ti,omap4-hsmmc";
294 reg = <0x4809c000 0x400>;
295 interrupts = <0 83 0x4>;
250 ti,hwmods = "mmc1"; 296 ti,hwmods = "mmc1";
251 ti,dual-volt; 297 ti,dual-volt;
252 ti,needs-special-reset; 298 ti,needs-special-reset;
@@ -254,24 +300,32 @@
254 300
255 mmc2: mmc@480b4000 { 301 mmc2: mmc@480b4000 {
256 compatible = "ti,omap4-hsmmc"; 302 compatible = "ti,omap4-hsmmc";
303 reg = <0x480b4000 0x400>;
304 interrupts = <0 86 0x4>;
257 ti,hwmods = "mmc2"; 305 ti,hwmods = "mmc2";
258 ti,needs-special-reset; 306 ti,needs-special-reset;
259 }; 307 };
260 308
261 mmc3: mmc@480ad000 { 309 mmc3: mmc@480ad000 {
262 compatible = "ti,omap4-hsmmc"; 310 compatible = "ti,omap4-hsmmc";
311 reg = <0x480ad000 0x400>;
312 interrupts = <0 94 0x4>;
263 ti,hwmods = "mmc3"; 313 ti,hwmods = "mmc3";
264 ti,needs-special-reset; 314 ti,needs-special-reset;
265 }; 315 };
266 316
267 mmc4: mmc@480d1000 { 317 mmc4: mmc@480d1000 {
268 compatible = "ti,omap4-hsmmc"; 318 compatible = "ti,omap4-hsmmc";
319 reg = <0x480d1000 0x400>;
320 interrupts = <0 96 0x4>;
269 ti,hwmods = "mmc4"; 321 ti,hwmods = "mmc4";
270 ti,needs-special-reset; 322 ti,needs-special-reset;
271 }; 323 };
272 324
273 mmc5: mmc@480d5000 { 325 mmc5: mmc@480d5000 {
274 compatible = "ti,omap4-hsmmc"; 326 compatible = "ti,omap4-hsmmc";
327 reg = <0x480d5000 0x400>;
328 interrupts = <0 59 0x4>;
275 ti,hwmods = "mmc5"; 329 ti,hwmods = "mmc5";
276 ti,needs-special-reset; 330 ti,needs-special-reset;
277 }; 331 };
@@ -287,7 +341,6 @@
287 <0x49032000 0x7f>; /* L3 Interconnect */ 341 <0x49032000 0x7f>; /* L3 Interconnect */
288 reg-names = "mpu", "dma"; 342 reg-names = "mpu", "dma";
289 interrupts = <0 112 0x4>; 343 interrupts = <0 112 0x4>;
290 interrupt-parent = <&gic>;
291 ti,hwmods = "mcpdm"; 344 ti,hwmods = "mcpdm";
292 }; 345 };
293 346
@@ -297,7 +350,6 @@
297 <0x4902e000 0x7f>; /* L3 Interconnect */ 350 <0x4902e000 0x7f>; /* L3 Interconnect */
298 reg-names = "mpu", "dma"; 351 reg-names = "mpu", "dma";
299 interrupts = <0 114 0x4>; 352 interrupts = <0 114 0x4>;
300 interrupt-parent = <&gic>;
301 ti,hwmods = "dmic"; 353 ti,hwmods = "dmic";
302 }; 354 };
303 355
@@ -308,7 +360,6 @@
308 reg-names = "mpu", "dma"; 360 reg-names = "mpu", "dma";
309 interrupts = <0 17 0x4>; 361 interrupts = <0 17 0x4>;
310 interrupt-names = "common"; 362 interrupt-names = "common";
311 interrupt-parent = <&gic>;
312 ti,buffer-size = <128>; 363 ti,buffer-size = <128>;
313 ti,hwmods = "mcbsp1"; 364 ti,hwmods = "mcbsp1";
314 }; 365 };
@@ -320,7 +371,6 @@
320 reg-names = "mpu", "dma"; 371 reg-names = "mpu", "dma";
321 interrupts = <0 22 0x4>; 372 interrupts = <0 22 0x4>;
322 interrupt-names = "common"; 373 interrupt-names = "common";
323 interrupt-parent = <&gic>;
324 ti,buffer-size = <128>; 374 ti,buffer-size = <128>;
325 ti,hwmods = "mcbsp2"; 375 ti,hwmods = "mcbsp2";
326 }; 376 };
@@ -332,9 +382,119 @@
332 reg-names = "mpu", "dma"; 382 reg-names = "mpu", "dma";
333 interrupts = <0 23 0x4>; 383 interrupts = <0 23 0x4>;
334 interrupt-names = "common"; 384 interrupt-names = "common";
335 interrupt-parent = <&gic>;
336 ti,buffer-size = <128>; 385 ti,buffer-size = <128>;
337 ti,hwmods = "mcbsp3"; 386 ti,hwmods = "mcbsp3";
338 }; 387 };
388
389 timer1: timer@4ae18000 {
390 compatible = "ti,omap2-timer";
391 reg = <0x4ae18000 0x80>;
392 interrupts = <0 37 0x4>;
393 ti,hwmods = "timer1";
394 ti,timer-alwon;
395 };
396
397 timer2: timer@48032000 {
398 compatible = "ti,omap2-timer";
399 reg = <0x48032000 0x80>;
400 interrupts = <0 38 0x4>;
401 ti,hwmods = "timer2";
402 };
403
404 timer3: timer@48034000 {
405 compatible = "ti,omap2-timer";
406 reg = <0x48034000 0x80>;
407 interrupts = <0 39 0x4>;
408 ti,hwmods = "timer3";
409 };
410
411 timer4: timer@48036000 {
412 compatible = "ti,omap2-timer";
413 reg = <0x48036000 0x80>;
414 interrupts = <0 40 0x4>;
415 ti,hwmods = "timer4";
416 };
417
418 timer5: timer@40138000 {
419 compatible = "ti,omap2-timer";
420 reg = <0x40138000 0x80>,
421 <0x49038000 0x80>;
422 interrupts = <0 41 0x4>;
423 ti,hwmods = "timer5";
424 ti,timer-dsp;
425 };
426
427 timer6: timer@4013a000 {
428 compatible = "ti,omap2-timer";
429 reg = <0x4013a000 0x80>,
430 <0x4903a000 0x80>;
431 interrupts = <0 42 0x4>;
432 ti,hwmods = "timer6";
433 ti,timer-dsp;
434 ti,timer-pwm;
435 };
436
437 timer7: timer@4013c000 {
438 compatible = "ti,omap2-timer";
439 reg = <0x4013c000 0x80>,
440 <0x4903c000 0x80>;
441 interrupts = <0 43 0x4>;
442 ti,hwmods = "timer7";
443 ti,timer-dsp;
444 };
445
446 timer8: timer@4013e000 {
447 compatible = "ti,omap2-timer";
448 reg = <0x4013e000 0x80>,
449 <0x4903e000 0x80>;
450 interrupts = <0 44 0x4>;
451 ti,hwmods = "timer8";
452 ti,timer-dsp;
453 ti,timer-pwm;
454 };
455
456 timer9: timer@4803e000 {
457 compatible = "ti,omap2-timer";
458 reg = <0x4803e000 0x80>;
459 interrupts = <0 45 0x4>;
460 ti,hwmods = "timer9";
461 };
462
463 timer10: timer@48086000 {
464 compatible = "ti,omap2-timer";
465 reg = <0x48086000 0x80>;
466 interrupts = <0 46 0x4>;
467 ti,hwmods = "timer10";
468 };
469
470 timer11: timer@48088000 {
471 compatible = "ti,omap2-timer";
472 reg = <0x48088000 0x80>;
473 interrupts = <0 47 0x4>;
474 ti,hwmods = "timer11";
475 ti,timer-pwm;
476 };
477
478 emif1: emif@0x4c000000 {
479 compatible = "ti,emif-4d5";
480 ti,hwmods = "emif1";
481 phy-type = <2>; /* DDR PHY type: Intelli PHY */
482 reg = <0x4c000000 0x400>;
483 interrupts = <0 110 0x4>;
484 hw-caps-read-idle-ctrl;
485 hw-caps-ll-interface;
486 hw-caps-temp-alert;
487 };
488
489 emif2: emif@0x4d000000 {
490 compatible = "ti,emif-4d5";
491 ti,hwmods = "emif2";
492 phy-type = <2>; /* DDR PHY type: Intelli PHY */
493 reg = <0x4d000000 0x400>;
494 interrupts = <0 111 0x4>;
495 hw-caps-read-idle-ctrl;
496 hw-caps-ll-interface;
497 hw-caps-temp-alert;
498 };
339 }; 499 };
340}; 500};
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
new file mode 100644
index 000000000000..9657a5cbc3ad
--- /dev/null
+++ b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
@@ -0,0 +1,67 @@
1/*
2 * Timings and Geometry for Samsung K3PE0E000B memory part
3 */
4
5/ {
6 samsung_K3PE0E000B: lpddr2 {
7 compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
8 density = <4096>;
9 io-width = <32>;
10
11 tRPab-min-tck = <3>;
12 tRCD-min-tck = <3>;
13 tWR-min-tck = <3>;
14 tRASmin-min-tck = <3>;
15 tRRD-min-tck = <2>;
16 tWTR-min-tck = <2>;
17 tXP-min-tck = <2>;
18 tRTP-min-tck = <2>;
19 tCKE-min-tck = <3>;
20 tCKESR-min-tck = <3>;
21 tFAW-min-tck = <8>;
22
23 timings_samsung_K3PE0E000B_533MHz: lpddr2-timings@0 {
24 compatible = "jedec,lpddr2-timings";
25 min-freq = <10000000>;
26 max-freq = <533333333>;
27 tRPab = <21000>;
28 tRCD = <18000>;
29 tWR = <15000>;
30 tRAS-min = <42000>;
31 tRRD = <10000>;
32 tWTR = <7500>;
33 tXP = <7500>;
34 tRTP = <7500>;
35 tCKESR = <15000>;
36 tDQSCK-max = <5500>;
37 tFAW = <50000>;
38 tZQCS = <90000>;
39 tZQCL = <360000>;
40 tZQinit = <1000000>;
41 tRAS-max-ns = <70000>;
42 tDQSCK-max-derated = <6000>;
43 };
44
45 timings_samsung_K3PE0E000B_266MHz: lpddr2-timings@1 {
46 compatible = "jedec,lpddr2-timings";
47 min-freq = <10000000>;
48 max-freq = <266666666>;
49 tRPab = <21000>;
50 tRCD = <18000>;
51 tWR = <15000>;
52 tRAS-min = <42000>;
53 tRRD = <10000>;
54 tWTR = <7500>;
55 tXP = <7500>;
56 tRTP = <7500>;
57 tCKESR = <15000>;
58 tDQSCK-max = <5500>;
59 tFAW = <50000>;
60 tZQCS = <90000>;
61 tZQCL = <360000>;
62 tZQinit = <1000000>;
63 tRAS-max-ns = <70000>;
64 tDQSCK-max-derated = <6000>;
65 };
66 };
67};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index ff000172c93c..63411b036932 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -37,6 +37,24 @@
37 regulator-max-microvolt = <3150000>; 37 regulator-max-microvolt = <3150000>;
38 }; 38 };
39 39
40 vusb1v5: regulator-vusb1v5 {
41 compatible = "ti,twl4030-vusb1v5";
42 };
43
44 vusb1v8: regulator-vusb1v8 {
45 compatible = "ti,twl4030-vusb1v8";
46 };
47
48 vusb3v1: regulator-vusb3v1 {
49 compatible = "ti,twl4030-vusb3v1";
50 };
51
52 vsim: regulator-vsim {
53 compatible = "ti,twl4030-vsim";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <3000000>;
56 };
57
40 twl_gpio: gpio { 58 twl_gpio: gpio {
41 compatible = "ti,twl4030-gpio"; 59 compatible = "ti,twl4030-gpio";
42 gpio-controller; 60 gpio-controller;
@@ -44,4 +62,13 @@
44 interrupt-controller; 62 interrupt-controller;
45 #interrupt-cells = <1>; 63 #interrupt-cells = <1>;
46 }; 64 };
65
66 twl4030-usb {
67 compatible = "ti,twl4030-usb";
68 interrupts = <10>, <4>;
69 usb1v5-supply = <&vusb1v5>;
70 usb1v8-supply = <&vusb1v8>;
71 usb3v1-supply = <&vusb3v1>;
72 usb_mode = <1>;
73 };
47}; 74};
diff --git a/arch/arm/boot/dts/twl6030.dtsi b/arch/arm/boot/dts/twl6030.dtsi
index 123e2c40218a..9996cfc5ee80 100644
--- a/arch/arm/boot/dts/twl6030.dtsi
+++ b/arch/arm/boot/dts/twl6030.dtsi
@@ -86,4 +86,9 @@
86 clk32kg: regulator-clk32kg { 86 clk32kg: regulator-clk32kg {
87 compatible = "ti,twl6030-clk32kg"; 87 compatible = "ti,twl6030-clk32kg";
88 }; 88 };
89
90 twl_usb_comparator: usb-comparator {
91 compatible = "ti,twl6030-usb";
92 interrupts = <4>, <10>;
93 };
89}; 94};
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index cdeb9d3ef640..bde7a35e5000 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -25,6 +25,7 @@
25#include <linux/err.h> 25#include <linux/err.h>
26#include <linux/slab.h> 26#include <linux/slab.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/platform_data/dmtimer-omap.h>
28 29
29#include <mach/irqs.h> 30#include <mach/irqs.h>
30 31
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 89368195bf08..41152fadd4c0 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -51,7 +51,6 @@
51#include <asm/mach/time.h> 51#include <asm/mach/time.h>
52 52
53#include <plat/counter-32k.h> 53#include <plat/counter-32k.h>
54#include <plat/dmtimer.h>
55 54
56#include <mach/hardware.h> 55#include <mach/hardware.h>
57 56
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 699caec8f9e2..ebbc2adb499e 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -297,6 +297,6 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
297 .handle_irq = omap3_intc_handle_irq, 297 .handle_irq = omap3_intc_handle_irq,
298 .init_machine = cm_t3517_init, 298 .init_machine = cm_t3517_init,
299 .init_late = am35xx_init_late, 299 .init_late = am35xx_init_late,
300 .timer = &omap3_timer, 300 .timer = &omap3_gp_timer,
301 .restart = omap3xxx_restart, 301 .restart = omap3xxx_restart,
302MACHINE_END 302MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 475e14f07216..aa6e4a19dd90 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -97,6 +97,23 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
97 .dt_compat = omap3_boards_compat, 97 .dt_compat = omap3_boards_compat,
98 .restart = omap3xxx_restart, 98 .restart = omap3xxx_restart,
99MACHINE_END 99MACHINE_END
100
101static const char *omap3_gp_boards_compat[] __initdata = {
102 "ti,omap3-beagle",
103 NULL,
104};
105
106DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
107 .reserve = omap_reserve,
108 .map_io = omap3_map_io,
109 .init_early = omap3430_init_early,
110 .init_irq = omap_intc_of_init,
111 .handle_irq = omap3_intc_handle_irq,
112 .init_machine = omap_generic_init,
113 .timer = &omap3_secure_timer,
114 .dt_compat = omap3_gp_boards_compat,
115 .restart = omap_prcm_restart,
116MACHINE_END
100#endif 117#endif
101 118
102#ifdef CONFIG_SOC_AM33XX 119#ifdef CONFIG_SOC_AM33XX
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 08c586451f93..3bbcde87dead 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -82,6 +82,7 @@ extern void omap2_init_common_infrastructure(void);
82extern struct sys_timer omap2_timer; 82extern struct sys_timer omap2_timer;
83extern struct sys_timer omap3_timer; 83extern struct sys_timer omap3_timer;
84extern struct sys_timer omap3_secure_timer; 84extern struct sys_timer omap3_secure_timer;
85extern struct sys_timer omap3_gp_timer;
85extern struct sys_timer omap3_am33xx_timer; 86extern struct sys_timer omap3_am33xx_timer;
86extern struct sys_timer omap4_timer; 87extern struct sys_timer omap4_timer;
87extern struct sys_timer omap5_timer; 88extern struct sys_timer omap5_timer;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a8b3368dca3d..e8efe3d1da6c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -17,7 +17,6 @@
17#include <linux/platform_data/spi-omap2-mcspi.h> 17#include <linux/platform_data/spi-omap2-mcspi.h>
18 18
19#include <plat-omap/dma-omap.h> 19#include <plat-omap/dma-omap.h>
20#include <plat/dmtimer.h>
21 20
22#include "omap_hwmod.h" 21#include "omap_hwmod.h"
23#include "l3_2xxx.h" 22#include "l3_2xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index dc768c50e523..32d17e3fd727 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,6 @@
18#include <linux/platform_data/spi-omap2-mcspi.h> 18#include <linux/platform_data/spi-omap2-mcspi.h>
19 19
20#include <plat-omap/dma-omap.h> 20#include <plat-omap/dma-omap.h>
21#include <plat/dmtimer.h>
22 21
23#include "omap_hwmod.h" 22#include "omap_hwmod.h"
24#include "mmc.h" 23#include "mmc.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index a0116d08cf45..0db8f450bad9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -58,8 +58,9 @@ static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
58 .syss_offs = 0x0014, 58 .syss_offs = 0x0014,
59 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | 59 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | 60 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
61 SYSC_HAS_AUTOIDLE), 61 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 62 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
63 .clockact = CLOCKACT_TEST_ICLK,
63 .sysc_fields = &omap_hwmod_sysc_type1, 64 .sysc_fields = &omap_hwmod_sysc_type1,
64}; 65};
65 66
@@ -268,6 +269,7 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
268 }, 269 },
269 .dev_attr = &capability_alwon_dev_attr, 270 .dev_attr = &capability_alwon_dev_attr,
270 .class = &omap2xxx_timer_hwmod_class, 271 .class = &omap2xxx_timer_hwmod_class,
272 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
271}; 273};
272 274
273/* timer2 */ 275/* timer2 */
@@ -286,6 +288,7 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
286 }, 288 },
287 }, 289 },
288 .class = &omap2xxx_timer_hwmod_class, 290 .class = &omap2xxx_timer_hwmod_class,
291 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
289}; 292};
290 293
291/* timer3 */ 294/* timer3 */
@@ -304,6 +307,7 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
304 }, 307 },
305 }, 308 },
306 .class = &omap2xxx_timer_hwmod_class, 309 .class = &omap2xxx_timer_hwmod_class,
310 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
307}; 311};
308 312
309/* timer4 */ 313/* timer4 */
@@ -322,6 +326,7 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
322 }, 326 },
323 }, 327 },
324 .class = &omap2xxx_timer_hwmod_class, 328 .class = &omap2xxx_timer_hwmod_class,
329 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
325}; 330};
326 331
327/* timer5 */ 332/* timer5 */
@@ -341,6 +346,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
341 }, 346 },
342 .dev_attr = &capability_dsp_dev_attr, 347 .dev_attr = &capability_dsp_dev_attr,
343 .class = &omap2xxx_timer_hwmod_class, 348 .class = &omap2xxx_timer_hwmod_class,
349 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
344}; 350};
345 351
346/* timer6 */ 352/* timer6 */
@@ -360,6 +366,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
360 }, 366 },
361 .dev_attr = &capability_dsp_dev_attr, 367 .dev_attr = &capability_dsp_dev_attr,
362 .class = &omap2xxx_timer_hwmod_class, 368 .class = &omap2xxx_timer_hwmod_class,
369 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
363}; 370};
364 371
365/* timer7 */ 372/* timer7 */
@@ -379,6 +386,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
379 }, 386 },
380 .dev_attr = &capability_dsp_dev_attr, 387 .dev_attr = &capability_dsp_dev_attr,
381 .class = &omap2xxx_timer_hwmod_class, 388 .class = &omap2xxx_timer_hwmod_class,
389 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
382}; 390};
383 391
384/* timer8 */ 392/* timer8 */
@@ -398,6 +406,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
398 }, 406 },
399 .dev_attr = &capability_dsp_dev_attr, 407 .dev_attr = &capability_dsp_dev_attr,
400 .class = &omap2xxx_timer_hwmod_class, 408 .class = &omap2xxx_timer_hwmod_class,
409 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
401}; 410};
402 411
403/* timer9 */ 412/* timer9 */
@@ -417,6 +426,7 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
417 }, 426 },
418 .dev_attr = &capability_pwm_dev_attr, 427 .dev_attr = &capability_pwm_dev_attr,
419 .class = &omap2xxx_timer_hwmod_class, 428 .class = &omap2xxx_timer_hwmod_class,
429 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
420}; 430};
421 431
422/* timer10 */ 432/* timer10 */
@@ -436,6 +446,7 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
436 }, 446 },
437 .dev_attr = &capability_pwm_dev_attr, 447 .dev_attr = &capability_pwm_dev_attr,
438 .class = &omap2xxx_timer_hwmod_class, 448 .class = &omap2xxx_timer_hwmod_class,
449 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
439}; 450};
440 451
441/* timer11 */ 452/* timer11 */
@@ -455,6 +466,7 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
455 }, 466 },
456 .dev_attr = &capability_pwm_dev_attr, 467 .dev_attr = &capability_pwm_dev_attr,
457 .class = &omap2xxx_timer_hwmod_class, 468 .class = &omap2xxx_timer_hwmod_class,
469 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
458}; 470};
459 471
460/* timer12 */ 472/* timer12 */
@@ -474,6 +486,7 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
474 }, 486 },
475 .dev_attr = &capability_pwm_dev_attr, 487 .dev_attr = &capability_pwm_dev_attr,
476 .class = &omap2xxx_timer_hwmod_class, 488 .class = &omap2xxx_timer_hwmod_class,
489 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
477}; 490};
478 491
479/* wd_timer2 */ 492/* wd_timer2 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index abe66ced903f..addc1c24ca2e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -153,29 +153,16 @@ static struct omap_hwmod omap3xxx_debugss_hwmod = {
153}; 153};
154 154
155/* timer class */ 155/* timer class */
156static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
157 .rev_offs = 0x0000,
158 .sysc_offs = 0x0010,
159 .syss_offs = 0x0014,
160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
163 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
164 .sysc_fields = &omap_hwmod_sysc_type1,
165};
166
167static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
168 .name = "timer",
169 .sysc = &omap3xxx_timer_1ms_sysc,
170};
171
172static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = { 156static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
173 .rev_offs = 0x0000, 157 .rev_offs = 0x0000,
174 .sysc_offs = 0x0010, 158 .sysc_offs = 0x0010,
175 .syss_offs = 0x0014, 159 .syss_offs = 0x0014,
176 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP | 160 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
177 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), 161 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
162 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
163 SYSS_HAS_RESET_STATUS),
178 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 164 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
165 .clockact = CLOCKACT_TEST_ICLK,
179 .sysc_fields = &omap_hwmod_sysc_type1, 166 .sysc_fields = &omap_hwmod_sysc_type1,
180}; 167};
181 168
@@ -224,7 +211,8 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
224 }, 211 },
225 }, 212 },
226 .dev_attr = &capability_alwon_dev_attr, 213 .dev_attr = &capability_alwon_dev_attr,
227 .class = &omap3xxx_timer_1ms_hwmod_class, 214 .class = &omap3xxx_timer_hwmod_class,
215 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
228}; 216};
229 217
230/* timer2 */ 218/* timer2 */
@@ -241,7 +229,8 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
241 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT, 229 .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
242 }, 230 },
243 }, 231 },
244 .class = &omap3xxx_timer_1ms_hwmod_class, 232 .class = &omap3xxx_timer_hwmod_class,
233 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
245}; 234};
246 235
247/* timer3 */ 236/* timer3 */
@@ -259,6 +248,7 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
259 }, 248 },
260 }, 249 },
261 .class = &omap3xxx_timer_hwmod_class, 250 .class = &omap3xxx_timer_hwmod_class,
251 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
262}; 252};
263 253
264/* timer4 */ 254/* timer4 */
@@ -276,6 +266,7 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
276 }, 266 },
277 }, 267 },
278 .class = &omap3xxx_timer_hwmod_class, 268 .class = &omap3xxx_timer_hwmod_class,
269 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
279}; 270};
280 271
281/* timer5 */ 272/* timer5 */
@@ -294,6 +285,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
294 }, 285 },
295 .dev_attr = &capability_dsp_dev_attr, 286 .dev_attr = &capability_dsp_dev_attr,
296 .class = &omap3xxx_timer_hwmod_class, 287 .class = &omap3xxx_timer_hwmod_class,
288 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
297}; 289};
298 290
299/* timer6 */ 291/* timer6 */
@@ -312,6 +304,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
312 }, 304 },
313 .dev_attr = &capability_dsp_dev_attr, 305 .dev_attr = &capability_dsp_dev_attr,
314 .class = &omap3xxx_timer_hwmod_class, 306 .class = &omap3xxx_timer_hwmod_class,
307 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
315}; 308};
316 309
317/* timer7 */ 310/* timer7 */
@@ -330,6 +323,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
330 }, 323 },
331 .dev_attr = &capability_dsp_dev_attr, 324 .dev_attr = &capability_dsp_dev_attr,
332 .class = &omap3xxx_timer_hwmod_class, 325 .class = &omap3xxx_timer_hwmod_class,
326 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
333}; 327};
334 328
335/* timer8 */ 329/* timer8 */
@@ -348,6 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
348 }, 342 },
349 .dev_attr = &capability_dsp_pwm_dev_attr, 343 .dev_attr = &capability_dsp_pwm_dev_attr,
350 .class = &omap3xxx_timer_hwmod_class, 344 .class = &omap3xxx_timer_hwmod_class,
345 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
351}; 346};
352 347
353/* timer9 */ 348/* timer9 */
@@ -366,6 +361,7 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
366 }, 361 },
367 .dev_attr = &capability_pwm_dev_attr, 362 .dev_attr = &capability_pwm_dev_attr,
368 .class = &omap3xxx_timer_hwmod_class, 363 .class = &omap3xxx_timer_hwmod_class,
364 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
369}; 365};
370 366
371/* timer10 */ 367/* timer10 */
@@ -383,7 +379,8 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
383 }, 379 },
384 }, 380 },
385 .dev_attr = &capability_pwm_dev_attr, 381 .dev_attr = &capability_pwm_dev_attr,
386 .class = &omap3xxx_timer_1ms_hwmod_class, 382 .class = &omap3xxx_timer_hwmod_class,
383 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
387}; 384};
388 385
389/* timer11 */ 386/* timer11 */
@@ -402,6 +399,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
402 }, 399 },
403 .dev_attr = &capability_pwm_dev_attr, 400 .dev_attr = &capability_pwm_dev_attr,
404 .class = &omap3xxx_timer_hwmod_class, 401 .class = &omap3xxx_timer_hwmod_class,
402 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
405}; 403};
406 404
407/* timer12 */ 405/* timer12 */
@@ -425,6 +423,7 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
425 }, 423 },
426 .dev_attr = &capability_secure_dev_attr, 424 .dev_attr = &capability_secure_dev_attr,
427 .class = &omap3xxx_timer_hwmod_class, 425 .class = &omap3xxx_timer_hwmod_class,
426 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
428}; 427};
429 428
430/* 429/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index b80bbf607ef8..f5b55a78a5f0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3103,6 +3103,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
3103 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | 3103 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
3104 SYSS_HAS_RESET_STATUS), 3104 SYSS_HAS_RESET_STATUS),
3105 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), 3105 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3106 .clockact = CLOCKACT_TEST_ICLK,
3106 .sysc_fields = &omap_hwmod_sysc_type1, 3107 .sysc_fields = &omap_hwmod_sysc_type1,
3107}; 3108};
3108 3109
@@ -3156,6 +3157,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
3156 .name = "timer1", 3157 .name = "timer1",
3157 .class = &omap44xx_timer_1ms_hwmod_class, 3158 .class = &omap44xx_timer_1ms_hwmod_class,
3158 .clkdm_name = "l4_wkup_clkdm", 3159 .clkdm_name = "l4_wkup_clkdm",
3160 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3159 .mpu_irqs = omap44xx_timer1_irqs, 3161 .mpu_irqs = omap44xx_timer1_irqs,
3160 .main_clk = "timer1_fck", 3162 .main_clk = "timer1_fck",
3161 .prcm = { 3163 .prcm = {
@@ -3178,6 +3180,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
3178 .name = "timer2", 3180 .name = "timer2",
3179 .class = &omap44xx_timer_1ms_hwmod_class, 3181 .class = &omap44xx_timer_1ms_hwmod_class,
3180 .clkdm_name = "l4_per_clkdm", 3182 .clkdm_name = "l4_per_clkdm",
3183 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3181 .mpu_irqs = omap44xx_timer2_irqs, 3184 .mpu_irqs = omap44xx_timer2_irqs,
3182 .main_clk = "timer2_fck", 3185 .main_clk = "timer2_fck",
3183 .prcm = { 3186 .prcm = {
@@ -3352,6 +3355,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
3352 .name = "timer10", 3355 .name = "timer10",
3353 .class = &omap44xx_timer_1ms_hwmod_class, 3356 .class = &omap44xx_timer_1ms_hwmod_class,
3354 .clkdm_name = "l4_per_clkdm", 3357 .clkdm_name = "l4_per_clkdm",
3358 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
3355 .mpu_irqs = omap44xx_timer10_irqs, 3359 .mpu_irqs = omap44xx_timer10_irqs,
3356 .main_clk = "timer10_fck", 3360 .main_clk = "timer10_fck",
3357 .prcm = { 3361 .prcm = {
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 3cf4fdfd7ab0..e2c291f52f92 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -30,7 +30,6 @@
30#include "clock.h" 30#include "clock.h"
31#include "powerdomain.h" 31#include "powerdomain.h"
32#include "clockdomain.h" 32#include "clockdomain.h"
33#include <plat/dmtimer.h>
34#include "omap-pm.h" 33#include "omap-pm.h"
35 34
36#include "soc.h" 35#include "soc.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index c5bc2cb4d8d3..b9cff72ceaec 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -37,6 +37,10 @@
37#include <linux/clockchips.h> 37#include <linux/clockchips.h>
38#include <linux/slab.h> 38#include <linux/slab.h>
39#include <linux/of.h> 39#include <linux/of.h>
40#include <linux/of_address.h>
41#include <linux/of_irq.h>
42#include <linux/platform_device.h>
43#include <linux/platform_data/dmtimer-omap.h>
40 44
41#include <asm/mach/time.h> 45#include <asm/mach/time.h>
42#include <asm/smp_twd.h> 46#include <asm/smp_twd.h>
@@ -62,18 +66,6 @@
62#define OMAP3_32K_SOURCE "omap_32k_fck" 66#define OMAP3_32K_SOURCE "omap_32k_fck"
63#define OMAP4_32K_SOURCE "sys_32k_ck" 67#define OMAP4_32K_SOURCE "sys_32k_ck"
64 68
65#ifdef CONFIG_OMAP_32K_TIMER
66#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
67#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
68#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
69#define OMAP3_SECURE_TIMER 12
70#else
71#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
72#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
73#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
74#define OMAP3_SECURE_TIMER 1
75#endif
76
77#define REALTIME_COUNTER_BASE 0x48243200 69#define REALTIME_COUNTER_BASE 0x48243200
78#define INCREMENTER_NUMERATOR_OFFSET 0x10 70#define INCREMENTER_NUMERATOR_OFFSET 0x10
79#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 71#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
@@ -104,7 +96,7 @@ static int omap2_gp_timer_set_next_event(unsigned long cycles,
104 struct clock_event_device *evt) 96 struct clock_event_device *evt)
105{ 97{
106 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST, 98 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
107 0xffffffff - cycles, 1); 99 0xffffffff - cycles, OMAP_TIMER_POSTED);
108 100
109 return 0; 101 return 0;
110} 102}
@@ -114,7 +106,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
114{ 106{
115 u32 period; 107 u32 period;
116 108
117 __omap_dm_timer_stop(&clkev, 1, clkev.rate); 109 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
118 110
119 switch (mode) { 111 switch (mode) {
120 case CLOCK_EVT_MODE_PERIODIC: 112 case CLOCK_EVT_MODE_PERIODIC:
@@ -122,10 +114,10 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
122 period -= 1; 114 period -= 1;
123 /* Looks like we need to first set the load value separately */ 115 /* Looks like we need to first set the load value separately */
124 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 116 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG,
125 0xffffffff - period, 1); 117 0xffffffff - period, OMAP_TIMER_POSTED);
126 __omap_dm_timer_load_start(&clkev, 118 __omap_dm_timer_load_start(&clkev,
127 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST, 119 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
128 0xffffffff - period, 1); 120 0xffffffff - period, OMAP_TIMER_POSTED);
129 break; 121 break;
130 case CLOCK_EVT_MODE_ONESHOT: 122 case CLOCK_EVT_MODE_ONESHOT:
131 break; 123 break;
@@ -145,36 +137,144 @@ static struct clock_event_device clockevent_gpt = {
145 .set_mode = omap2_gp_timer_set_mode, 137 .set_mode = omap2_gp_timer_set_mode,
146}; 138};
147 139
140static struct property device_disabled = {
141 .name = "status",
142 .length = sizeof("disabled"),
143 .value = "disabled",
144};
145
146static struct of_device_id omap_timer_match[] __initdata = {
147 { .compatible = "ti,omap2-timer", },
148 { }
149};
150
151/**
152 * omap_get_timer_dt - get a timer using device-tree
153 * @match - device-tree match structure for matching a device type
154 * @property - optional timer property to match
155 *
156 * Helper function to get a timer during early boot using device-tree for use
157 * as kernel system timer. Optionally, the property argument can be used to
158 * select a timer with a specific property. Once a timer is found then mark
159 * the timer node in device-tree as disabled, to prevent the kernel from
160 * registering this timer as a platform device and so no one else can use it.
161 */
162static struct device_node * __init omap_get_timer_dt(struct of_device_id *match,
163 const char *property)
164{
165 struct device_node *np;
166
167 for_each_matching_node(np, match) {
168 if (!of_device_is_available(np)) {
169 of_node_put(np);
170 continue;
171 }
172
173 if (property && !of_get_property(np, property, NULL)) {
174 of_node_put(np);
175 continue;
176 }
177
178 prom_add_property(np, &device_disabled);
179 return np;
180 }
181
182 return NULL;
183}
184
185/**
186 * omap_dmtimer_init - initialisation function when device tree is used
187 *
188 * For secure OMAP3 devices, timers with device type "timer-secure" cannot
189 * be used by the kernel as they are reserved. Therefore, to prevent the
190 * kernel registering these devices remove them dynamically from the device
191 * tree on boot.
192 */
193void __init omap_dmtimer_init(void)
194{
195 struct device_node *np;
196
197 if (!cpu_is_omap34xx())
198 return;
199
200 /* If we are a secure device, remove any secure timer nodes */
201 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
202 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
203 if (np)
204 of_node_put(np);
205 }
206}
207
208/**
209 * omap_dm_timer_get_errata - get errata flags for a timer
210 *
211 * Get the timer errata flags that are specific to the OMAP device being used.
212 */
213u32 __init omap_dm_timer_get_errata(void)
214{
215 if (cpu_is_omap24xx())
216 return 0;
217
218 return OMAP_TIMER_ERRATA_I103_I767;
219}
220
148static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer, 221static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
149 int gptimer_id, 222 int gptimer_id,
150 const char *fck_source) 223 const char *fck_source,
224 const char *property,
225 int posted)
151{ 226{
152 char name[10]; /* 10 = sizeof("gptXX_Xck0") */ 227 char name[10]; /* 10 = sizeof("gptXX_Xck0") */
228 const char *oh_name;
229 struct device_node *np;
153 struct omap_hwmod *oh; 230 struct omap_hwmod *oh;
154 struct resource irq_rsrc, mem_rsrc; 231 struct resource irq, mem;
155 size_t size; 232 int r = 0;
156 int res = 0; 233
157 int r; 234 if (of_have_populated_dt()) {
158 235 np = omap_get_timer_dt(omap_timer_match, NULL);
159 sprintf(name, "timer%d", gptimer_id); 236 if (!np)
160 omap_hwmod_setup_one(name); 237 return -ENODEV;
161 oh = omap_hwmod_lookup(name); 238
239 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
240 if (!oh_name)
241 return -ENODEV;
242
243 timer->irq = irq_of_parse_and_map(np, 0);
244 if (!timer->irq)
245 return -ENXIO;
246
247 timer->io_base = of_iomap(np, 0);
248
249 of_node_put(np);
250 } else {
251 if (omap_dm_timer_reserve_systimer(gptimer_id))
252 return -ENODEV;
253
254 sprintf(name, "timer%d", gptimer_id);
255 oh_name = name;
256 }
257
258 oh = omap_hwmod_lookup(oh_name);
162 if (!oh) 259 if (!oh)
163 return -ENODEV; 260 return -ENODEV;
164 261
165 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL, &irq_rsrc); 262 if (!of_have_populated_dt()) {
166 if (r) 263 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
167 return -ENXIO; 264 &irq);
168 timer->irq = irq_rsrc.start; 265 if (r)
266 return -ENXIO;
267 timer->irq = irq.start;
169 268
170 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL, &mem_rsrc); 269 r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
171 if (r) 270 &mem);
172 return -ENXIO; 271 if (r)
173 timer->phys_base = mem_rsrc.start; 272 return -ENXIO;
174 size = mem_rsrc.end - mem_rsrc.start; 273
274 /* Static mapping, never released */
275 timer->io_base = ioremap(mem.start, mem.end - mem.start);
276 }
175 277
176 /* Static mapping, never released */
177 timer->io_base = ioremap(timer->phys_base, size);
178 if (!timer->io_base) 278 if (!timer->io_base)
179 return -ENXIO; 279 return -ENXIO;
180 280
@@ -183,42 +283,56 @@ static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
183 if (IS_ERR(timer->fclk)) 283 if (IS_ERR(timer->fclk))
184 return -ENODEV; 284 return -ENODEV;
185 285
186 omap_hwmod_enable(oh); 286 /* FIXME: Need to remove hard-coded test on timer ID */
187
188 if (omap_dm_timer_reserve_systimer(gptimer_id))
189 return -ENODEV;
190
191 if (gptimer_id != 12) { 287 if (gptimer_id != 12) {
192 struct clk *src; 288 struct clk *src;
193 289
194 src = clk_get(NULL, fck_source); 290 src = clk_get(NULL, fck_source);
195 if (IS_ERR(src)) { 291 if (IS_ERR(src)) {
196 res = -EINVAL; 292 r = -EINVAL;
197 } else { 293 } else {
198 res = __omap_dm_timer_set_source(timer->fclk, src); 294 r = clk_set_parent(timer->fclk, src);
199 if (IS_ERR_VALUE(res)) 295 if (IS_ERR_VALUE(r))
200 pr_warning("%s: timer%i cannot set source\n", 296 pr_warn("%s: %s cannot set source\n",
201 __func__, gptimer_id); 297 __func__, oh->name);
202 clk_put(src); 298 clk_put(src);
203 } 299 }
204 } 300 }
301
302 omap_hwmod_setup_one(oh_name);
303 omap_hwmod_enable(oh);
205 __omap_dm_timer_init_regs(timer); 304 __omap_dm_timer_init_regs(timer);
206 __omap_dm_timer_reset(timer, 1, 1);
207 timer->posted = 1;
208 305
209 timer->rate = clk_get_rate(timer->fclk); 306 if (posted)
307 __omap_dm_timer_enable_posted(timer);
308
309 /* Check that the intended posted configuration matches the actual */
310 if (posted != timer->posted)
311 return -EINVAL;
210 312
313 timer->rate = clk_get_rate(timer->fclk);
211 timer->reserved = 1; 314 timer->reserved = 1;
212 315
213 return res; 316 return r;
214} 317}
215 318
216static void __init omap2_gp_clockevent_init(int gptimer_id, 319static void __init omap2_gp_clockevent_init(int gptimer_id,
217 const char *fck_source) 320 const char *fck_source,
321 const char *property)
218{ 322{
219 int res; 323 int res;
220 324
221 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source); 325 clkev.errata = omap_dm_timer_get_errata();
326
327 /*
328 * For clock-event timers we never read the timer counter and
329 * so we are not impacted by errata i103 and i767. Therefore,
330 * we can safely ignore this errata for clock-event timers.
331 */
332 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
333
334 res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source, property,
335 OMAP_TIMER_POSTED);
222 BUG_ON(res); 336 BUG_ON(res);
223 337
224 omap2_gp_timer_irq.dev_id = &clkev; 338 omap2_gp_timer_irq.dev_id = &clkev;
@@ -251,7 +365,8 @@ static bool use_gptimer_clksrc;
251 */ 365 */
252static cycle_t clocksource_read_cycles(struct clocksource *cs) 366static cycle_t clocksource_read_cycles(struct clocksource *cs)
253{ 367{
254 return (cycle_t)__omap_dm_timer_read_counter(&clksrc, 1); 368 return (cycle_t)__omap_dm_timer_read_counter(&clksrc,
369 OMAP_TIMER_NONPOSTED);
255} 370}
256 371
257static struct clocksource clocksource_gpt = { 372static struct clocksource clocksource_gpt = {
@@ -265,21 +380,41 @@ static struct clocksource clocksource_gpt = {
265static u32 notrace dmtimer_read_sched_clock(void) 380static u32 notrace dmtimer_read_sched_clock(void)
266{ 381{
267 if (clksrc.reserved) 382 if (clksrc.reserved)
268 return __omap_dm_timer_read_counter(&clksrc, 1); 383 return __omap_dm_timer_read_counter(&clksrc,
384 OMAP_TIMER_NONPOSTED);
269 385
270 return 0; 386 return 0;
271} 387}
272 388
273#ifdef CONFIG_OMAP_32K_TIMER 389static struct of_device_id omap_counter_match[] __initdata = {
390 { .compatible = "ti,omap-counter32k", },
391 { }
392};
393
274/* Setup free-running counter for clocksource */ 394/* Setup free-running counter for clocksource */
275static int __init omap2_sync32k_clocksource_init(void) 395static int __init omap2_sync32k_clocksource_init(void)
276{ 396{
277 int ret; 397 int ret;
398 struct device_node *np = NULL;
278 struct omap_hwmod *oh; 399 struct omap_hwmod *oh;
279 void __iomem *vbase; 400 void __iomem *vbase;
280 const char *oh_name = "counter_32k"; 401 const char *oh_name = "counter_32k";
281 402
282 /* 403 /*
404 * If device-tree is present, then search the DT blob
405 * to see if the 32kHz counter is supported.
406 */
407 if (of_have_populated_dt()) {
408 np = omap_get_timer_dt(omap_counter_match, NULL);
409 if (!np)
410 return -ENODEV;
411
412 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
413 if (!oh_name)
414 return -ENODEV;
415 }
416
417 /*
283 * First check hwmod data is available for sync32k counter 418 * First check hwmod data is available for sync32k counter
284 */ 419 */
285 oh = omap_hwmod_lookup(oh_name); 420 oh = omap_hwmod_lookup(oh_name);
@@ -288,7 +423,13 @@ static int __init omap2_sync32k_clocksource_init(void)
288 423
289 omap_hwmod_setup_one(oh_name); 424 omap_hwmod_setup_one(oh_name);
290 425
291 vbase = omap_hwmod_get_mpu_rt_va(oh); 426 if (np) {
427 vbase = of_iomap(np, 0);
428 of_node_put(np);
429 } else {
430 vbase = omap_hwmod_get_mpu_rt_va(oh);
431 }
432
292 if (!vbase) { 433 if (!vbase) {
293 pr_warn("%s: failed to get counter_32k resource\n", __func__); 434 pr_warn("%s: failed to get counter_32k resource\n", __func__);
294 return -ENXIO; 435 return -ENXIO;
@@ -310,23 +451,21 @@ static int __init omap2_sync32k_clocksource_init(void)
310 451
311 return ret; 452 return ret;
312} 453}
313#else
314static inline int omap2_sync32k_clocksource_init(void)
315{
316 return -ENODEV;
317}
318#endif
319 454
320static void __init omap2_gptimer_clocksource_init(int gptimer_id, 455static void __init omap2_gptimer_clocksource_init(int gptimer_id,
321 const char *fck_source) 456 const char *fck_source)
322{ 457{
323 int res; 458 int res;
324 459
325 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source); 460 clksrc.errata = omap_dm_timer_get_errata();
461
462 res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source, NULL,
463 OMAP_TIMER_NONPOSTED);
326 BUG_ON(res); 464 BUG_ON(res);
327 465
328 __omap_dm_timer_load_start(&clksrc, 466 __omap_dm_timer_load_start(&clksrc,
329 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, 1); 467 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
468 OMAP_TIMER_NONPOSTED);
330 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); 469 setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate);
331 470
332 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) 471 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
@@ -337,25 +476,6 @@ static void __init omap2_gptimer_clocksource_init(int gptimer_id,
337 gptimer_id, clksrc.rate); 476 gptimer_id, clksrc.rate);
338} 477}
339 478
340static void __init omap2_clocksource_init(int gptimer_id,
341 const char *fck_source)
342{
343 /*
344 * First give preference to kernel parameter configuration
345 * by user (clocksource="gp_timer").
346 *
347 * In case of missing kernel parameter for clocksource,
348 * first check for availability for 32k-sync timer, in case
349 * of failure in finding 32k_counter module or registering
350 * it as clocksource, execution will fallback to gp-timer.
351 */
352 if (use_gptimer_clksrc == true)
353 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
354 else if (omap2_sync32k_clocksource_init())
355 /* Fall back to gp-timer code */
356 omap2_gptimer_clocksource_init(gptimer_id, fck_source);
357}
358
359#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER 479#ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
360/* 480/*
361 * The realtime counter also called master counter, is a free-running 481 * The realtime counter also called master counter, is a free-running
@@ -434,48 +554,65 @@ static inline void __init realtime_counter_init(void)
434{} 554{}
435#endif 555#endif
436 556
437#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \ 557#define OMAP_SYS_GP_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
558 clksrc_nr, clksrc_src) \
559static void __init omap##name##_gptimer_timer_init(void) \
560{ \
561 omap_dmtimer_init(); \
562 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
563 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src); \
564}
565
566#define OMAP_SYS_32K_TIMER_INIT(name, clkev_nr, clkev_src, clkev_prop, \
438 clksrc_nr, clksrc_src) \ 567 clksrc_nr, clksrc_src) \
439static void __init omap##name##_timer_init(void) \ 568static void __init omap##name##_sync32k_timer_init(void) \
440{ \ 569{ \
441 omap2_gp_clockevent_init((clkev_nr), clkev_src); \ 570 omap_dmtimer_init(); \
442 omap2_clocksource_init((clksrc_nr), clksrc_src); \ 571 omap2_gp_clockevent_init((clkev_nr), clkev_src, clkev_prop); \
572 /* Enable the use of clocksource="gp_timer" kernel parameter */ \
573 if (use_gptimer_clksrc) \
574 omap2_gptimer_clocksource_init((clksrc_nr), clksrc_src);\
575 else \
576 omap2_sync32k_clocksource_init(); \
443} 577}
444 578
445#define OMAP_SYS_TIMER(name) \ 579#define OMAP_SYS_TIMER(name, clksrc) \
446struct sys_timer omap##name##_timer = { \ 580struct sys_timer omap##name##_timer = { \
447 .init = omap##name##_timer_init, \ 581 .init = omap##name##_##clksrc##_timer_init, \
448}; 582};
449 583
450#ifdef CONFIG_ARCH_OMAP2 584#ifdef CONFIG_ARCH_OMAP2
451OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE) 585OMAP_SYS_32K_TIMER_INIT(2, 1, OMAP2_32K_SOURCE, "ti,timer-alwon",
452OMAP_SYS_TIMER(2) 586 2, OMAP2_MPU_SOURCE);
453#endif 587OMAP_SYS_TIMER(2, sync32k);
588#endif /* CONFIG_ARCH_OMAP2 */
454 589
455#ifdef CONFIG_ARCH_OMAP3 590#ifdef CONFIG_ARCH_OMAP3
456OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE) 591OMAP_SYS_32K_TIMER_INIT(3, 1, OMAP3_32K_SOURCE, "ti,timer-alwon",
457OMAP_SYS_TIMER(3) 592 2, OMAP3_MPU_SOURCE);
458OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE, 593OMAP_SYS_TIMER(3, sync32k);
459 2, OMAP3_MPU_SOURCE) 594OMAP_SYS_32K_TIMER_INIT(3_secure, 12, OMAP3_32K_SOURCE, "ti,timer-secure",
460OMAP_SYS_TIMER(3_secure) 595 2, OMAP3_MPU_SOURCE);
461#endif 596OMAP_SYS_TIMER(3_secure, sync32k);
597OMAP_SYS_GP_TIMER_INIT(3_gp, 1, OMAP3_MPU_SOURCE, "ti,timer-alwon",
598 2, OMAP3_MPU_SOURCE);
599OMAP_SYS_TIMER(3_gp, gptimer);
600#endif /* CONFIG_ARCH_OMAP3 */
462 601
463#ifdef CONFIG_SOC_AM33XX 602#ifdef CONFIG_SOC_AM33XX
464OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE) 603OMAP_SYS_GP_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, "ti,timer-alwon",
465OMAP_SYS_TIMER(3_am33xx) 604 2, OMAP4_MPU_SOURCE);
466#endif 605OMAP_SYS_TIMER(3_am33xx, gptimer);
606#endif /* CONFIG_SOC_AM33XX */
467 607
468#ifdef CONFIG_ARCH_OMAP4 608#ifdef CONFIG_ARCH_OMAP4
609OMAP_SYS_32K_TIMER_INIT(4, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
610 2, OMAP4_MPU_SOURCE);
469#ifdef CONFIG_LOCAL_TIMERS 611#ifdef CONFIG_LOCAL_TIMERS
470static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 612static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
471 OMAP44XX_LOCAL_TWD_BASE, 29); 613static void __init omap4_local_timer_init(void)
472#endif
473
474static void __init omap4_timer_init(void)
475{ 614{
476 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 615 omap4_sync32k_timer_init();
477 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
478#ifdef CONFIG_LOCAL_TIMERS
479 /* Local timers are not supprted on OMAP4430 ES1.0 */ 616 /* Local timers are not supprted on OMAP4430 ES1.0 */
480 if (omap_rev() != OMAP4430_REV_ES1_0) { 617 if (omap_rev() != OMAP4430_REV_ES1_0) {
481 int err; 618 int err;
@@ -489,26 +626,32 @@ static void __init omap4_timer_init(void)
489 if (err) 626 if (err)
490 pr_err("twd_local_timer_register failed %d\n", err); 627 pr_err("twd_local_timer_register failed %d\n", err);
491 } 628 }
492#endif
493} 629}
494OMAP_SYS_TIMER(4) 630#else /* CONFIG_LOCAL_TIMERS */
495#endif 631static inline void omap4_local_timer_init(void)
632{
633 omap4_sync32_timer_init();
634}
635#endif /* CONFIG_LOCAL_TIMERS */
636OMAP_SYS_TIMER(4, local);
637#endif /* CONFIG_ARCH_OMAP4 */
496 638
497#ifdef CONFIG_SOC_OMAP5 639#ifdef CONFIG_SOC_OMAP5
498static void __init omap5_timer_init(void) 640OMAP_SYS_32K_TIMER_INIT(5, 1, OMAP4_32K_SOURCE, "ti,timer-alwon",
641 2, OMAP4_MPU_SOURCE);
642static void __init omap5_realtime_timer_init(void)
499{ 643{
500 int err; 644 int err;
501 645
502 omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE); 646 omap5_sync32k_timer_init();
503 omap2_clocksource_init(2, OMAP4_MPU_SOURCE);
504 realtime_counter_init(); 647 realtime_counter_init();
505 648
506 err = arch_timer_of_register(); 649 err = arch_timer_of_register();
507 if (err) 650 if (err)
508 pr_err("%s: arch_timer_register failed %d\n", __func__, err); 651 pr_err("%s: arch_timer_register failed %d\n", __func__, err);
509} 652}
510OMAP_SYS_TIMER(5) 653OMAP_SYS_TIMER(5, realtime);
511#endif 654#endif /* CONFIG_SOC_OMAP5 */
512 655
513/** 656/**
514 * omap_timer_init - build and register timer device with an 657 * omap_timer_init - build and register timer device with an
@@ -560,6 +703,7 @@ static int __init omap_timer_init(struct omap_hwmod *oh, void *unused)
560 if (timer_dev_attr) 703 if (timer_dev_attr)
561 pdata->timer_capability = timer_dev_attr->timer_capability; 704 pdata->timer_capability = timer_dev_attr->timer_capability;
562 705
706 pdata->timer_errata = omap_dm_timer_get_errata();
563 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count; 707 pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
564 708
565 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata), 709 pdev = omap_device_build(name, id, oh, pdata, sizeof(*pdata),
@@ -586,6 +730,10 @@ static int __init omap2_dm_timer_init(void)
586{ 730{
587 int ret; 731 int ret;
588 732
733 /* If dtb is there, the devices will be created dynamically */
734 if (of_have_populated_dt())
735 return -ENODEV;
736
589 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); 737 ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL);
590 if (unlikely(ret)) { 738 if (unlikely(ret)) {
591 pr_err("%s: device registration failed.\n", __func__); 739 pr_err("%s: device registration failed.\n", __func__);
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 82fcb206b5b2..665870dce3c8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -154,6 +154,12 @@ config OMAP_32K_TIMER
154 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 154 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
155 currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5. 155 currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5.
156 156
157 On OMAP2PLUS this value is only used for CONFIG_HZ and
158 CLOCK_TICK_RATE compile time calculation.
159 The actual timer selection is done in the board file
160 through the (DT_)MACHINE_START structure.
161
162
157config OMAP3_L2_AUX_SECURE_SAVE_RESTORE 163config OMAP3_L2_AUX_SECURE_SAVE_RESTORE
158 bool "OMAP3 HS/EMU save and restore for L2 AUX control register" 164 bool "OMAP3 HS/EMU save and restore for L2 AUX control register"
159 depends on ARCH_OMAP3 && PM 165 depends on ARCH_OMAP3 && PM
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 82231a75abd6..89585c293554 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -35,11 +35,16 @@
35 * 675 Mass Ave, Cambridge, MA 02139, USA. 35 * 675 Mass Ave, Cambridge, MA 02139, USA.
36 */ 36 */
37 37
38#include <linux/clk.h>
38#include <linux/module.h> 39#include <linux/module.h>
39#include <linux/io.h> 40#include <linux/io.h>
40#include <linux/device.h> 41#include <linux/device.h>
41#include <linux/err.h> 42#include <linux/err.h>
42#include <linux/pm_runtime.h> 43#include <linux/pm_runtime.h>
44#include <linux/of.h>
45#include <linux/of_device.h>
46#include <linux/platform_device.h>
47#include <linux/platform_data/dmtimer-omap.h>
43 48
44#include <plat/dmtimer.h> 49#include <plat/dmtimer.h>
45 50
@@ -81,10 +86,6 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
81 86
82static void omap_timer_restore_context(struct omap_dm_timer *timer) 87static void omap_timer_restore_context(struct omap_dm_timer *timer)
83{ 88{
84 if (timer->revision == 1)
85 __raw_writel(timer->context.tistat, timer->sys_stat);
86
87 __raw_writel(timer->context.tisr, timer->irq_stat);
88 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, 89 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
89 timer->context.twer); 90 timer->context.twer);
90 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, 91 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
@@ -100,39 +101,38 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
100 timer->context.tclr); 101 timer->context.tclr);
101} 102}
102 103
103static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 104static int omap_dm_timer_reset(struct omap_dm_timer *timer)
104{ 105{
105 int c; 106 u32 l, timeout = 100000;
106 107
107 if (!timer->sys_stat) 108 if (timer->revision != 1)
108 return; 109 return -EINVAL;
109 110
110 c = 0; 111 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
111 while (!(__raw_readl(timer->sys_stat) & 1)) {
112 c++;
113 if (c > 100000) {
114 printk(KERN_ERR "Timer failed to reset\n");
115 return;
116 }
117 }
118}
119 112
120static void omap_dm_timer_reset(struct omap_dm_timer *timer) 113 do {
121{ 114 l = __omap_dm_timer_read(timer,
122 omap_dm_timer_enable(timer); 115 OMAP_TIMER_V1_SYS_STAT_OFFSET, 0);
123 if (timer->pdev->id != 1) { 116 } while (!l && timeout--);
124 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06); 117
125 omap_dm_timer_wait_for_reset(timer); 118 if (!timeout) {
119 dev_err(&timer->pdev->dev, "Timer failed to reset\n");
120 return -ETIMEDOUT;
126 } 121 }
127 122
128 __omap_dm_timer_reset(timer, 0, 0); 123 /* Configure timer for smart-idle mode */
129 omap_dm_timer_disable(timer); 124 l = __omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
130 timer->posted = 1; 125 l |= 0x2 << 0x3;
126 __omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET, l, 0);
127
128 timer->posted = 0;
129
130 return 0;
131} 131}
132 132
133int omap_dm_timer_prepare(struct omap_dm_timer *timer) 133static int omap_dm_timer_prepare(struct omap_dm_timer *timer)
134{ 134{
135 int ret; 135 int rc;
136 136
137 /* 137 /*
138 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so 138 * FIXME: OMAP1 devices do not use the clock framework for dmtimers so
@@ -147,13 +147,20 @@ int omap_dm_timer_prepare(struct omap_dm_timer *timer)
147 } 147 }
148 } 148 }
149 149
150 if (timer->capability & OMAP_TIMER_NEEDS_RESET) 150 omap_dm_timer_enable(timer);
151 omap_dm_timer_reset(timer); 151
152 if (timer->capability & OMAP_TIMER_NEEDS_RESET) {
153 rc = omap_dm_timer_reset(timer);
154 if (rc) {
155 omap_dm_timer_disable(timer);
156 return rc;
157 }
158 }
152 159
153 ret = omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 160 __omap_dm_timer_enable_posted(timer);
161 omap_dm_timer_disable(timer);
154 162
155 timer->posted = 1; 163 return omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
156 return ret;
157} 164}
158 165
159static inline u32 omap_dm_timer_reserved_systimer(int id) 166static inline u32 omap_dm_timer_reserved_systimer(int id)
@@ -209,6 +216,13 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
209 unsigned long flags; 216 unsigned long flags;
210 int ret = 0; 217 int ret = 0;
211 218
219 /* Requesting timer by ID is not supported when device tree is used */
220 if (of_have_populated_dt()) {
221 pr_warn("%s: Please use omap_dm_timer_request_by_cap()\n",
222 __func__);
223 return NULL;
224 }
225
212 spin_lock_irqsave(&dm_timer_lock, flags); 226 spin_lock_irqsave(&dm_timer_lock, flags);
213 list_for_each_entry(t, &omap_timer_list, node) { 227 list_for_each_entry(t, &omap_timer_list, node) {
214 if (t->pdev->id == id && !t->reserved) { 228 if (t->pdev->id == id && !t->reserved) {
@@ -234,6 +248,58 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
234} 248}
235EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); 249EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
236 250
251/**
252 * omap_dm_timer_request_by_cap - Request a timer by capability
253 * @cap: Bit mask of capabilities to match
254 *
255 * Find a timer based upon capabilities bit mask. Callers of this function
256 * should use the definitions found in the plat/dmtimer.h file under the
257 * comment "timer capabilities used in hwmod database". Returns pointer to
258 * timer handle on success and a NULL pointer on failure.
259 */
260struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
261{
262 struct omap_dm_timer *timer = NULL, *t;
263 unsigned long flags;
264
265 if (!cap)
266 return NULL;
267
268 spin_lock_irqsave(&dm_timer_lock, flags);
269 list_for_each_entry(t, &omap_timer_list, node) {
270 if ((!t->reserved) && ((t->capability & cap) == cap)) {
271 /*
272 * If timer is not NULL, we have already found one timer
273 * but it was not an exact match because it had more
274 * capabilites that what was required. Therefore,
275 * unreserve the last timer found and see if this one
276 * is a better match.
277 */
278 if (timer)
279 timer->reserved = 0;
280
281 timer = t;
282 timer->reserved = 1;
283
284 /* Exit loop early if we find an exact match */
285 if (t->capability == cap)
286 break;
287 }
288 }
289 spin_unlock_irqrestore(&dm_timer_lock, flags);
290
291 if (timer && omap_dm_timer_prepare(timer)) {
292 timer->reserved = 0;
293 timer = NULL;
294 }
295
296 if (!timer)
297 pr_debug("%s: timer request failed!\n", __func__);
298
299 return timer;
300}
301EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
302
237int omap_dm_timer_free(struct omap_dm_timer *timer) 303int omap_dm_timer_free(struct omap_dm_timer *timer)
238{ 304{
239 if (unlikely(!timer)) 305 if (unlikely(!timer))
@@ -388,7 +454,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
388 */ 454 */
389 timer->context.tclr = 455 timer->context.tclr =
390 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG); 456 omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
391 timer->context.tisr = __raw_readl(timer->irq_stat);
392 omap_dm_timer_disable(timer); 457 omap_dm_timer_disable(timer);
393 return 0; 458 return 0;
394} 459}
@@ -398,7 +463,7 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
398{ 463{
399 int ret; 464 int ret;
400 char *parent_name = NULL; 465 char *parent_name = NULL;
401 struct clk *fclk, *parent; 466 struct clk *parent;
402 struct dmtimer_platform_data *pdata; 467 struct dmtimer_platform_data *pdata;
403 468
404 if (unlikely(!timer)) 469 if (unlikely(!timer))
@@ -414,14 +479,11 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
414 * use the clock framework to set the parent clock. To be removed 479 * use the clock framework to set the parent clock. To be removed
415 * once OMAP1 migrated to using clock framework for dmtimers 480 * once OMAP1 migrated to using clock framework for dmtimers
416 */ 481 */
417 if (pdata->set_timer_src) 482 if (pdata && pdata->set_timer_src)
418 return pdata->set_timer_src(timer->pdev, source); 483 return pdata->set_timer_src(timer->pdev, source);
419 484
420 fclk = clk_get(&timer->pdev->dev, "fck"); 485 if (!timer->fclk)
421 if (IS_ERR_OR_NULL(fclk)) {
422 pr_err("%s: fck not found\n", __func__);
423 return -EINVAL; 486 return -EINVAL;
424 }
425 487
426 switch (source) { 488 switch (source) {
427 case OMAP_TIMER_SRC_SYS_CLK: 489 case OMAP_TIMER_SRC_SYS_CLK:
@@ -440,18 +502,15 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
440 parent = clk_get(&timer->pdev->dev, parent_name); 502 parent = clk_get(&timer->pdev->dev, parent_name);
441 if (IS_ERR_OR_NULL(parent)) { 503 if (IS_ERR_OR_NULL(parent)) {
442 pr_err("%s: %s not found\n", __func__, parent_name); 504 pr_err("%s: %s not found\n", __func__, parent_name);
443 ret = -EINVAL; 505 return -EINVAL;
444 goto out;
445 } 506 }
446 507
447 ret = clk_set_parent(fclk, parent); 508 ret = clk_set_parent(timer->fclk, parent);
448 if (IS_ERR_VALUE(ret)) 509 if (IS_ERR_VALUE(ret))
449 pr_err("%s: failed to set %s as parent\n", __func__, 510 pr_err("%s: failed to set %s as parent\n", __func__,
450 parent_name); 511 parent_name);
451 512
452 clk_put(parent); 513 clk_put(parent);
453out:
454 clk_put(fclk);
455 514
456 return ret; 515 return ret;
457} 516}
@@ -534,8 +593,8 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
534 l |= OMAP_TIMER_CTRL_CE; 593 l |= OMAP_TIMER_CTRL_CE;
535 else 594 else
536 l &= ~OMAP_TIMER_CTRL_CE; 595 l &= ~OMAP_TIMER_CTRL_CE;
537 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
538 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 596 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
597 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
539 598
540 /* Save the context */ 599 /* Save the context */
541 timer->context.tclr = l; 600 timer->context.tclr = l;
@@ -611,6 +670,37 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
611} 670}
612EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); 671EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
613 672
673/**
674 * omap_dm_timer_set_int_disable - disable timer interrupts
675 * @timer: pointer to timer handle
676 * @mask: bit mask of interrupts to be disabled
677 *
678 * Disables the specified timer interrupts for a timer.
679 */
680int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
681{
682 u32 l = mask;
683
684 if (unlikely(!timer))
685 return -EINVAL;
686
687 omap_dm_timer_enable(timer);
688
689 if (timer->revision == 1)
690 l = __raw_readl(timer->irq_ena) & ~mask;
691
692 __raw_writel(l, timer->irq_dis);
693 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
694 omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
695
696 /* Save the context */
697 timer->context.tier &= ~mask;
698 timer->context.twer &= ~mask;
699 omap_dm_timer_disable(timer);
700 return 0;
701}
702EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
703
614unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) 704unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
615{ 705{
616 unsigned int l; 706 unsigned int l;
@@ -632,8 +722,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
632 return -EINVAL; 722 return -EINVAL;
633 723
634 __omap_dm_timer_write_status(timer, value); 724 __omap_dm_timer_write_status(timer, value);
635 /* Save the context */ 725
636 timer->context.tisr = value;
637 return 0; 726 return 0;
638} 727}
639EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); 728EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
@@ -696,7 +785,7 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
696 struct device *dev = &pdev->dev; 785 struct device *dev = &pdev->dev;
697 struct dmtimer_platform_data *pdata = pdev->dev.platform_data; 786 struct dmtimer_platform_data *pdata = pdev->dev.platform_data;
698 787
699 if (!pdata) { 788 if (!pdata && !dev->of_node) {
700 dev_err(dev, "%s: no platform data.\n", __func__); 789 dev_err(dev, "%s: no platform data.\n", __func__);
701 return -ENODEV; 790 return -ENODEV;
702 } 791 }
@@ -725,12 +814,25 @@ static int __devinit omap_dm_timer_probe(struct platform_device *pdev)
725 return -ENOMEM; 814 return -ENOMEM;
726 } 815 }
727 816
728 timer->id = pdev->id; 817 if (dev->of_node) {
818 if (of_find_property(dev->of_node, "ti,timer-alwon", NULL))
819 timer->capability |= OMAP_TIMER_ALWON;
820 if (of_find_property(dev->of_node, "ti,timer-dsp", NULL))
821 timer->capability |= OMAP_TIMER_HAS_DSP_IRQ;
822 if (of_find_property(dev->of_node, "ti,timer-pwm", NULL))
823 timer->capability |= OMAP_TIMER_HAS_PWM;
824 if (of_find_property(dev->of_node, "ti,timer-secure", NULL))
825 timer->capability |= OMAP_TIMER_SECURE;
826 } else {
827 timer->id = pdev->id;
828 timer->errata = pdata->timer_errata;
829 timer->capability = pdata->timer_capability;
830 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
831 timer->get_context_loss_count = pdata->get_context_loss_count;
832 }
833
729 timer->irq = irq->start; 834 timer->irq = irq->start;
730 timer->reserved = omap_dm_timer_reserved_systimer(timer->id);
731 timer->pdev = pdev; 835 timer->pdev = pdev;
732 timer->capability = pdata->timer_capability;
733 timer->get_context_loss_count = pdata->get_context_loss_count;
734 836
735 /* Skip pm_runtime_enable for OMAP1 */ 837 /* Skip pm_runtime_enable for OMAP1 */
736 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) { 838 if (!(timer->capability & OMAP_TIMER_NEEDS_RESET)) {
@@ -770,7 +872,8 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
770 872
771 spin_lock_irqsave(&dm_timer_lock, flags); 873 spin_lock_irqsave(&dm_timer_lock, flags);
772 list_for_each_entry(timer, &omap_timer_list, node) 874 list_for_each_entry(timer, &omap_timer_list, node)
773 if (timer->pdev->id == pdev->id) { 875 if (!strcmp(dev_name(&timer->pdev->dev),
876 dev_name(&pdev->dev))) {
774 list_del(&timer->node); 877 list_del(&timer->node);
775 ret = 0; 878 ret = 0;
776 break; 879 break;
@@ -780,11 +883,18 @@ static int __devexit omap_dm_timer_remove(struct platform_device *pdev)
780 return ret; 883 return ret;
781} 884}
782 885
886static const struct of_device_id omap_timer_match[] = {
887 { .compatible = "ti,omap2-timer", },
888 {},
889};
890MODULE_DEVICE_TABLE(of, omap_timer_match);
891
783static struct platform_driver omap_dm_timer_driver = { 892static struct platform_driver omap_dm_timer_driver = {
784 .probe = omap_dm_timer_probe, 893 .probe = omap_dm_timer_probe,
785 .remove = __devexit_p(omap_dm_timer_remove), 894 .remove = __devexit_p(omap_dm_timer_remove),
786 .driver = { 895 .driver = {
787 .name = "omap_timer", 896 .name = "omap_timer",
897 .of_match_table = of_match_ptr(omap_timer_match),
788 }, 898 },
789}; 899};
790 900
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 3f5b9cfd9c0b..a3fbc48c332e 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,7 +32,6 @@
32 * 675 Mass Ave, Cambridge, MA 02139, USA. 32 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 */ 33 */
34 34
35#include <linux/clk.h>
36#include <linux/delay.h> 35#include <linux/delay.h>
37#include <linux/io.h> 36#include <linux/io.h>
38#include <linux/platform_device.h> 37#include <linux/platform_device.h>
@@ -55,6 +54,10 @@
55#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01 54#define OMAP_TIMER_TRIGGER_OVERFLOW 0x01
56#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02 55#define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
57 56
57/* posted mode types */
58#define OMAP_TIMER_NONPOSTED 0x00
59#define OMAP_TIMER_POSTED 0x01
60
58/* timer capabilities used in hwmod database */ 61/* timer capabilities used in hwmod database */
59#define OMAP_TIMER_SECURE 0x80000000 62#define OMAP_TIMER_SECURE 0x80000000
60#define OMAP_TIMER_ALWON 0x40000000 63#define OMAP_TIMER_ALWON 0x40000000
@@ -62,16 +65,22 @@
62#define OMAP_TIMER_NEEDS_RESET 0x10000000 65#define OMAP_TIMER_NEEDS_RESET 0x10000000
63#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000 66#define OMAP_TIMER_HAS_DSP_IRQ 0x08000000
64 67
68/*
69 * timer errata flags
70 *
71 * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
72 * errata prevents us from using posted mode on these devices, unless the
73 * timer counter register is never read. For more details please refer to
74 * the OMAP3/4/5 errata documents.
75 */
76#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
77
65struct omap_timer_capability_dev_attr { 78struct omap_timer_capability_dev_attr {
66 u32 timer_capability; 79 u32 timer_capability;
67}; 80};
68 81
69struct omap_dm_timer;
70
71struct timer_regs { 82struct timer_regs {
72 u32 tidr; 83 u32 tidr;
73 u32 tistat;
74 u32 tisr;
75 u32 tier; 84 u32 tier;
76 u32 twer; 85 u32 twer;
77 u32 tclr; 86 u32 tclr;
@@ -90,16 +99,35 @@ struct timer_regs {
90 u32 towr; 99 u32 towr;
91}; 100};
92 101
93struct dmtimer_platform_data { 102struct omap_dm_timer {
94 /* set_timer_src - Only used for OMAP1 devices */ 103 int id;
95 int (*set_timer_src)(struct platform_device *pdev, int source); 104 int irq;
96 u32 timer_capability; 105 struct clk *fclk;
106
107 void __iomem *io_base;
108 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
109 void __iomem *irq_ena; /* irq enable */
110 void __iomem *irq_dis; /* irq disable, only on v2 ip */
111 void __iomem *pend; /* write pending */
112 void __iomem *func_base; /* function register base */
113
114 unsigned long rate;
115 unsigned reserved:1;
116 unsigned posted:1;
117 struct timer_regs context;
97 int (*get_context_loss_count)(struct device *); 118 int (*get_context_loss_count)(struct device *);
119 int ctx_loss_count;
120 int revision;
121 u32 capability;
122 u32 errata;
123 struct platform_device *pdev;
124 struct list_head node;
98}; 125};
99 126
100int omap_dm_timer_reserve_systimer(int id); 127int omap_dm_timer_reserve_systimer(int id);
101struct omap_dm_timer *omap_dm_timer_request(void); 128struct omap_dm_timer *omap_dm_timer_request(void);
102struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id); 129struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
130struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
103int omap_dm_timer_free(struct omap_dm_timer *timer); 131int omap_dm_timer_free(struct omap_dm_timer *timer);
104void omap_dm_timer_enable(struct omap_dm_timer *timer); 132void omap_dm_timer_enable(struct omap_dm_timer *timer);
105void omap_dm_timer_disable(struct omap_dm_timer *timer); 133void omap_dm_timer_disable(struct omap_dm_timer *timer);
@@ -121,6 +149,7 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, i
121int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 149int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
122 150
123int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value); 151int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
152int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
124 153
125unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer); 154unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
126int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value); 155int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
@@ -246,34 +275,6 @@ int omap_dm_timers_active(void);
246#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \ 275#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
247 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT)) 276 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
248 277
249struct omap_dm_timer {
250 unsigned long phys_base;
251 int id;
252 int irq;
253 struct clk *fclk;
254
255 void __iomem *io_base;
256 void __iomem *sys_stat; /* TISTAT timer status */
257 void __iomem *irq_stat; /* TISR/IRQSTATUS interrupt status */
258 void __iomem *irq_ena; /* irq enable */
259 void __iomem *irq_dis; /* irq disable, only on v2 ip */
260 void __iomem *pend; /* write pending */
261 void __iomem *func_base; /* function register base */
262
263 unsigned long rate;
264 unsigned reserved:1;
265 unsigned posted:1;
266 struct timer_regs context;
267 int (*get_context_loss_count)(struct device *);
268 int ctx_loss_count;
269 int revision;
270 u32 capability;
271 struct platform_device *pdev;
272 struct list_head node;
273};
274
275int omap_dm_timer_prepare(struct omap_dm_timer *timer);
276
277static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg, 278static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
278 int posted) 279 int posted)
279{ 280{
@@ -302,16 +303,13 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
302 tidr = __raw_readl(timer->io_base); 303 tidr = __raw_readl(timer->io_base);
303 if (!(tidr >> 16)) { 304 if (!(tidr >> 16)) {
304 timer->revision = 1; 305 timer->revision = 1;
305 timer->sys_stat = timer->io_base +
306 OMAP_TIMER_V1_SYS_STAT_OFFSET;
307 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET; 306 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
308 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET; 307 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
309 timer->irq_dis = NULL; 308 timer->irq_dis = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
310 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET; 309 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
311 timer->func_base = timer->io_base; 310 timer->func_base = timer->io_base;
312 } else { 311 } else {
313 timer->revision = 2; 312 timer->revision = 2;
314 timer->sys_stat = NULL;
315 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS; 313 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
316 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET; 314 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
317 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR; 315 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
@@ -322,45 +320,44 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
322 } 320 }
323} 321}
324 322
325/* Assumes the source clock has been set by caller */ 323/*
326static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer, 324 * __omap_dm_timer_enable_posted - enables write posted mode
327 int autoidle, int wakeup) 325 * @timer: pointer to timer instance handle
326 *
327 * Enables the write posted mode for the timer. When posted mode is enabled
328 * writes to certain timer registers are immediately acknowledged by the
329 * internal bus and hence prevents stalling the CPU waiting for the write to
330 * complete. Enabling this feature can improve performance for writing to the
331 * timer registers.
332 */
333static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
328{ 334{
329 u32 l; 335 if (timer->posted)
336 return;
330 337
331 l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET); 338 if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
332 l |= 0x02 << 3; /* Set to smart-idle mode */ 339 return;
333 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
334 340
335 if (autoidle)
336 l |= 0x1 << 0;
337
338 if (wakeup)
339 l |= 1 << 2;
340
341 __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
342
343 /* Match hardware reset default of posted mode */
344 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG, 341 __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
345 OMAP_TIMER_CTRL_POSTED, 0); 342 OMAP_TIMER_CTRL_POSTED, 0);
343 timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
344 timer->posted = OMAP_TIMER_POSTED;
346} 345}
347 346
348static inline int __omap_dm_timer_set_source(struct clk *timer_fck, 347/**
349 struct clk *parent) 348 * __omap_dm_timer_override_errata - override errata flags for a timer
349 * @timer: pointer to timer handle
350 * @errata: errata flags to be ignored
351 *
352 * For a given timer, override a timer errata by clearing the flags
353 * specified by the errata argument. A specific erratum should only be
354 * overridden for a timer if the timer is used in such a way the erratum
355 * has no impact.
356 */
357static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
358 u32 errata)
350{ 359{
351 int ret; 360 timer->errata &= ~errata;
352
353 clk_disable(timer_fck);
354 ret = clk_set_parent(timer_fck, parent);
355 clk_enable(timer_fck);
356
357 /*
358 * When the functional clock disappears, too quick writes seem
359 * to cause an abort. XXX Is this still necessary?
360 */
361 __delay(300000);
362
363 return ret;
364} 361}
365 362
366static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer, 363static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-12 03:50:30 -0400