aboutsummaryrefslogtreecommitdiffstats
path: root/arch
diff options
context:
space:
mode:
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap1/mcbsp.c327
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c7
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c16
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c19
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c6
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c10
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c11
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c6
-rw-r--r--arch/arm/mach-omap2/board-flash.c2
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c5
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c10
-rw-r--r--arch/arm/mach-omap2/board-igep0030.c6
-rw-r--r--arch/arm/mach-omap2/board-ldp.c25
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c4
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c11
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c10
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c8
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c11
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c15
-rw-r--r--arch/arm/mach-omap2/board-overo.c8
-rw-r--r--arch/arm/mach-omap2/board-rm680.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c61
-rw-r--r--arch/arm/mach-omap2/board-rx51.c6
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c4
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c6
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c12
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c12
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c20
-rw-r--r--arch/arm/mach-omap2/devices.c391
-rw-r--r--arch/arm/mach-omap2/hsmmc.c424
-rw-r--r--arch/arm/mach-omap2/iommu2.c33
-rw-r--r--arch/arm/mach-omap2/mailbox.c72
-rw-r--r--arch/arm/mach-omap2/mcbsp.c231
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c202
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c546
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c735
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c26
-rw-r--r--arch/arm/mach-omap2/prcm-common.h8
-rw-r--r--arch/arm/plat-omap/devices.c10
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h14
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h50
-rw-r--r--arch/arm/plat-omap/include/plat/mmc.h29
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h4
-rw-r--r--arch/arm/plat-omap/iommu.c55
-rw-r--r--arch/arm/plat-omap/mcbsp.c203
51 files changed, 2620 insertions, 1073 deletions
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 820973666f34..e68f6c012fde 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -10,6 +10,7 @@
10 * 10 *
11 * Multichannel mode not supported. 11 * Multichannel mode not supported.
12 */ 12 */
13#include <linux/ioport.h>
13#include <linux/module.h> 14#include <linux/module.h>
14#include <linux/init.h> 15#include <linux/init.h>
15#include <linux/clk.h> 16#include <linux/clk.h>
@@ -78,100 +79,288 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
78}; 79};
79 80
80#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 81#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
82struct resource omap7xx_mcbsp_res[][6] = {
83 {
84 {
85 .start = OMAP7XX_MCBSP1_BASE,
86 .end = OMAP7XX_MCBSP1_BASE + SZ_256,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .name = "rx",
91 .start = INT_7XX_McBSP1RX,
92 .flags = IORESOURCE_IRQ,
93 },
94 {
95 .name = "tx",
96 .start = INT_7XX_McBSP1TX,
97 .flags = IORESOURCE_IRQ,
98 },
99 {
100 .name = "rx",
101 .start = OMAP_DMA_MCBSP1_RX,
102 .flags = IORESOURCE_DMA,
103 },
104 {
105 .name = "tx",
106 .start = OMAP_DMA_MCBSP1_TX,
107 .flags = IORESOURCE_DMA,
108 },
109 },
110 {
111 {
112 .start = OMAP7XX_MCBSP2_BASE,
113 .end = OMAP7XX_MCBSP2_BASE + SZ_256,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "rx",
118 .start = INT_7XX_McBSP2RX,
119 .flags = IORESOURCE_IRQ,
120 },
121 {
122 .name = "tx",
123 .start = INT_7XX_McBSP2TX,
124 .flags = IORESOURCE_IRQ,
125 },
126 {
127 .name = "rx",
128 .start = OMAP_DMA_MCBSP3_RX,
129 .flags = IORESOURCE_DMA,
130 },
131 {
132 .name = "tx",
133 .start = OMAP_DMA_MCBSP3_TX,
134 .flags = IORESOURCE_DMA,
135 },
136 },
137};
138
81static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = { 139static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
82 { 140 {
83 .phys_base = OMAP7XX_MCBSP1_BASE,
84 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
85 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
86 .rx_irq = INT_7XX_McBSP1RX,
87 .tx_irq = INT_7XX_McBSP1TX,
88 .ops = &omap1_mcbsp_ops, 141 .ops = &omap1_mcbsp_ops,
89 }, 142 },
90 { 143 {
91 .phys_base = OMAP7XX_MCBSP2_BASE,
92 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
93 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
94 .rx_irq = INT_7XX_McBSP2RX,
95 .tx_irq = INT_7XX_McBSP2TX,
96 .ops = &omap1_mcbsp_ops, 144 .ops = &omap1_mcbsp_ops,
97 }, 145 },
98}; 146};
99#define OMAP7XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap7xx_mcbsp_pdata) 147#define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
100#define OMAP7XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 148#define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
101#else 149#else
150#define omap7xx_mcbsp_res NULL
102#define omap7xx_mcbsp_pdata NULL 151#define omap7xx_mcbsp_pdata NULL
103#define OMAP7XX_MCBSP_PDATA_SZ 0 152#define OMAP7XX_MCBSP_RES_SZ 0
104#define OMAP7XX_MCBSP_REG_NUM 0 153#define OMAP7XX_MCBSP_COUNT 0
105#endif 154#endif
106 155
107#ifdef CONFIG_ARCH_OMAP15XX 156#ifdef CONFIG_ARCH_OMAP15XX
157struct resource omap15xx_mcbsp_res[][6] = {
158 {
159 {
160 .start = OMAP1510_MCBSP1_BASE,
161 .end = OMAP1510_MCBSP1_BASE + SZ_256,
162 .flags = IORESOURCE_MEM,
163 },
164 {
165 .name = "rx",
166 .start = INT_McBSP1RX,
167 .flags = IORESOURCE_IRQ,
168 },
169 {
170 .name = "tx",
171 .start = INT_McBSP1TX,
172 .flags = IORESOURCE_IRQ,
173 },
174 {
175 .name = "rx",
176 .start = OMAP_DMA_MCBSP1_RX,
177 .flags = IORESOURCE_DMA,
178 },
179 {
180 .name = "tx",
181 .start = OMAP_DMA_MCBSP1_TX,
182 .flags = IORESOURCE_DMA,
183 },
184 },
185 {
186 {
187 .start = OMAP1510_MCBSP2_BASE,
188 .end = OMAP1510_MCBSP2_BASE + SZ_256,
189 .flags = IORESOURCE_MEM,
190 },
191 {
192 .name = "rx",
193 .start = INT_1510_SPI_RX,
194 .flags = IORESOURCE_IRQ,
195 },
196 {
197 .name = "tx",
198 .start = INT_1510_SPI_TX,
199 .flags = IORESOURCE_IRQ,
200 },
201 {
202 .name = "rx",
203 .start = OMAP_DMA_MCBSP2_RX,
204 .flags = IORESOURCE_DMA,
205 },
206 {
207 .name = "tx",
208 .start = OMAP_DMA_MCBSP2_TX,
209 .flags = IORESOURCE_DMA,
210 },
211 },
212 {
213 {
214 .start = OMAP1510_MCBSP3_BASE,
215 .end = OMAP1510_MCBSP3_BASE + SZ_256,
216 .flags = IORESOURCE_MEM,
217 },
218 {
219 .name = "rx",
220 .start = INT_McBSP3RX,
221 .flags = IORESOURCE_IRQ,
222 },
223 {
224 .name = "tx",
225 .start = INT_McBSP3TX,
226 .flags = IORESOURCE_IRQ,
227 },
228 {
229 .name = "rx",
230 .start = OMAP_DMA_MCBSP3_RX,
231 .flags = IORESOURCE_DMA,
232 },
233 {
234 .name = "tx",
235 .start = OMAP_DMA_MCBSP3_TX,
236 .flags = IORESOURCE_DMA,
237 },
238 },
239};
240
108static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { 241static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
109 { 242 {
110 .phys_base = OMAP1510_MCBSP1_BASE,
111 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
112 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
113 .rx_irq = INT_McBSP1RX,
114 .tx_irq = INT_McBSP1TX,
115 .ops = &omap1_mcbsp_ops, 243 .ops = &omap1_mcbsp_ops,
116 }, 244 },
117 { 245 {
118 .phys_base = OMAP1510_MCBSP2_BASE,
119 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
120 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
121 .rx_irq = INT_1510_SPI_RX,
122 .tx_irq = INT_1510_SPI_TX,
123 .ops = &omap1_mcbsp_ops, 246 .ops = &omap1_mcbsp_ops,
124 }, 247 },
125 { 248 {
126 .phys_base = OMAP1510_MCBSP3_BASE,
127 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
128 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
129 .rx_irq = INT_McBSP3RX,
130 .tx_irq = INT_McBSP3TX,
131 .ops = &omap1_mcbsp_ops, 249 .ops = &omap1_mcbsp_ops,
132 }, 250 },
133}; 251};
134#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) 252#define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
135#define OMAP15XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 253#define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
136#else 254#else
255#define omap15xx_mcbsp_res NULL
137#define omap15xx_mcbsp_pdata NULL 256#define omap15xx_mcbsp_pdata NULL
138#define OMAP15XX_MCBSP_PDATA_SZ 0 257#define OMAP15XX_MCBSP_RES_SZ 0
139#define OMAP15XX_MCBSP_REG_NUM 0 258#define OMAP15XX_MCBSP_COUNT 0
140#endif 259#endif
141 260
142#ifdef CONFIG_ARCH_OMAP16XX 261#ifdef CONFIG_ARCH_OMAP16XX
262struct resource omap16xx_mcbsp_res[][6] = {
263 {
264 {
265 .start = OMAP1610_MCBSP1_BASE,
266 .end = OMAP1610_MCBSP1_BASE + SZ_256,
267 .flags = IORESOURCE_MEM,
268 },
269 {
270 .name = "rx",
271 .start = INT_McBSP1RX,
272 .flags = IORESOURCE_IRQ,
273 },
274 {
275 .name = "tx",
276 .start = INT_McBSP1TX,
277 .flags = IORESOURCE_IRQ,
278 },
279 {
280 .name = "rx",
281 .start = OMAP_DMA_MCBSP1_RX,
282 .flags = IORESOURCE_DMA,
283 },
284 {
285 .name = "tx",
286 .start = OMAP_DMA_MCBSP1_TX,
287 .flags = IORESOURCE_DMA,
288 },
289 },
290 {
291 {
292 .start = OMAP1610_MCBSP2_BASE,
293 .end = OMAP1610_MCBSP2_BASE + SZ_256,
294 .flags = IORESOURCE_MEM,
295 },
296 {
297 .name = "rx",
298 .start = INT_1610_McBSP2_RX,
299 .flags = IORESOURCE_IRQ,
300 },
301 {
302 .name = "tx",
303 .start = INT_1610_McBSP2_TX,
304 .flags = IORESOURCE_IRQ,
305 },
306 {
307 .name = "rx",
308 .start = OMAP_DMA_MCBSP2_RX,
309 .flags = IORESOURCE_DMA,
310 },
311 {
312 .name = "tx",
313 .start = OMAP_DMA_MCBSP2_TX,
314 .flags = IORESOURCE_DMA,
315 },
316 },
317 {
318 {
319 .start = OMAP1610_MCBSP3_BASE,
320 .end = OMAP1610_MCBSP3_BASE + SZ_256,
321 .flags = IORESOURCE_MEM,
322 },
323 {
324 .name = "rx",
325 .start = INT_McBSP3RX,
326 .flags = IORESOURCE_IRQ,
327 },
328 {
329 .name = "tx",
330 .start = INT_McBSP3TX,
331 .flags = IORESOURCE_IRQ,
332 },
333 {
334 .name = "rx",
335 .start = OMAP_DMA_MCBSP3_RX,
336 .flags = IORESOURCE_DMA,
337 },
338 {
339 .name = "tx",
340 .start = OMAP_DMA_MCBSP3_TX,
341 .flags = IORESOURCE_DMA,
342 },
343 },
344};
345
143static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { 346static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
144 { 347 {
145 .phys_base = OMAP1610_MCBSP1_BASE,
146 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
147 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
148 .rx_irq = INT_McBSP1RX,
149 .tx_irq = INT_McBSP1TX,
150 .ops = &omap1_mcbsp_ops, 348 .ops = &omap1_mcbsp_ops,
151 }, 349 },
152 { 350 {
153 .phys_base = OMAP1610_MCBSP2_BASE,
154 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
155 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
156 .rx_irq = INT_1610_McBSP2_RX,
157 .tx_irq = INT_1610_McBSP2_TX,
158 .ops = &omap1_mcbsp_ops, 351 .ops = &omap1_mcbsp_ops,
159 }, 352 },
160 { 353 {
161 .phys_base = OMAP1610_MCBSP3_BASE,
162 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
163 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
164 .rx_irq = INT_McBSP3RX,
165 .tx_irq = INT_McBSP3TX,
166 .ops = &omap1_mcbsp_ops, 354 .ops = &omap1_mcbsp_ops,
167 }, 355 },
168}; 356};
169#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) 357#define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
170#define OMAP16XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1) 358#define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
171#else 359#else
360#define omap16xx_mcbsp_res NULL
172#define omap16xx_mcbsp_pdata NULL 361#define omap16xx_mcbsp_pdata NULL
173#define OMAP16XX_MCBSP_PDATA_SZ 0 362#define OMAP16XX_MCBSP_RES_SZ 0
174#define OMAP16XX_MCBSP_REG_NUM 0 363#define OMAP16XX_MCBSP_COUNT 0
175#endif 364#endif
176 365
177static int __init omap1_mcbsp_init(void) 366static int __init omap1_mcbsp_init(void)
@@ -179,16 +368,12 @@ static int __init omap1_mcbsp_init(void)
179 if (!cpu_class_is_omap1()) 368 if (!cpu_class_is_omap1())
180 return -ENODEV; 369 return -ENODEV;
181 370
182 if (cpu_is_omap7xx()) { 371 if (cpu_is_omap7xx())
183 omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; 372 omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
184 omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16); 373 else if (cpu_is_omap15xx())
185 } else if (cpu_is_omap15xx()) { 374 omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
186 omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ; 375 else if (cpu_is_omap16xx())
187 omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16); 376 omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
188 } else if (cpu_is_omap16xx()) {
189 omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
190 omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
191 }
192 377
193 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 378 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
194 GFP_KERNEL); 379 GFP_KERNEL);
@@ -196,16 +381,22 @@ static int __init omap1_mcbsp_init(void)
196 return -ENOMEM; 381 return -ENOMEM;
197 382
198 if (cpu_is_omap7xx()) 383 if (cpu_is_omap7xx())
199 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata, 384 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res[0],
200 OMAP7XX_MCBSP_PDATA_SZ); 385 OMAP7XX_MCBSP_RES_SZ,
386 omap7xx_mcbsp_pdata,
387 OMAP7XX_MCBSP_COUNT);
201 388
202 if (cpu_is_omap15xx()) 389 if (cpu_is_omap15xx())
203 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata, 390 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res[0],
204 OMAP15XX_MCBSP_PDATA_SZ); 391 OMAP15XX_MCBSP_RES_SZ,
392 omap15xx_mcbsp_pdata,
393 OMAP15XX_MCBSP_COUNT);
205 394
206 if (cpu_is_omap16xx()) 395 if (cpu_is_omap16xx())
207 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata, 396 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res[0],
208 OMAP16XX_MCBSP_PDATA_SZ); 397 OMAP16XX_MCBSP_RES_SZ,
398 omap16xx_mcbsp_pdata,
399 OMAP16XX_MCBSP_COUNT);
209 400
210 return omap_mcbsp_init(); 401 return omap_mcbsp_init();
211} 402}
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index cc42d474c443..1fa6bb896f41 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -142,14 +142,12 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
142 142
143static void __init omap_2430sdp_init_early(void) 143static void __init omap_2430sdp_init_early(void)
144{ 144{
145 omap_board_config = sdp2430_config;
146 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
147 omap2_init_common_infrastructure(); 145 omap2_init_common_infrastructure();
148 omap2_init_common_devices(NULL, NULL); 146 omap2_init_common_devices(NULL, NULL);
149} 147}
150 148
151static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = { 149static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
152 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), 150 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
153}; 151};
154 152
155/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 153/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -246,6 +244,9 @@ static void __init omap_2430sdp_init(void)
246 244
247 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC); 245 omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
248 246
247 omap_board_config = sdp2430_config;
248 omap_board_config_size = ARRAY_SIZE(sdp2430_config);
249
249 omap2430_i2c_init(); 250 omap2430_i2c_init();
250 251
251 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices)); 252 platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 8950ecc9b940..5464bec156ad 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -315,9 +315,6 @@ static struct omap_board_config_kernel sdp3430_config[] __initdata = {
315 315
316static void __init omap_3430sdp_init_early(void) 316static void __init omap_3430sdp_init_early(void)
317{ 317{
318 omap_board_config = sdp3430_config;
319 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
320 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
321 omap2_init_common_infrastructure(); 318 omap2_init_common_infrastructure();
322 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL); 319 omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
323} 320}
@@ -410,15 +407,15 @@ static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
410}; 407};
411 408
412static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = { 409static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
413 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"), 410 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
414}; 411};
415 412
416static struct regulator_consumer_supply sdp3430_vsim_supplies[] = { 413static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
417 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.0"), 414 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
418}; 415};
419 416
420static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = { 417static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
421 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), 418 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
422}; 419};
423 420
424/* 421/*
@@ -555,9 +552,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
555 .consumer_supplies = sdp3430_vpll2_supplies, 552 .consumer_supplies = sdp3430_vpll2_supplies,
556}; 553};
557 554
558static struct twl4030_codec_audio_data sdp3430_audio = { 555static struct twl4030_codec_audio_data sdp3430_audio;
559 .audio_mclk = 26000000,
560};
561 556
562static struct twl4030_codec_data sdp3430_codec = { 557static struct twl4030_codec_data sdp3430_codec = {
563 .audio_mclk = 26000000, 558 .audio_mclk = 26000000,
@@ -788,6 +783,9 @@ static struct omap_musb_board_data musb_board_data = {
788static void __init omap_3430sdp_init(void) 783static void __init omap_3430sdp_init(void)
789{ 784{
790 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 785 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
786 omap_board_config = sdp3430_config;
787 omap_board_config_size = ARRAY_SIZE(sdp3430_config);
788 omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
791 omap3430_i2c_init(); 789 omap3430_i2c_init();
792 omap_display_init(&sdp3430_dss_data); 790 omap_display_init(&sdp3430_dss_data);
793 if (omap_rev() > OMAP3430_REV_ES1_0) 791 if (omap_rev() > OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 8d1c4358ecf9..c4e22b32e47f 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -72,8 +72,6 @@ static struct omap_board_config_kernel sdp_config[] __initdata = {
72 72
73static void __init omap_sdp_init_early(void) 73static void __init omap_sdp_init_early(void)
74{ 74{
75 omap_board_config = sdp_config;
76 omap_board_config_size = ARRAY_SIZE(sdp_config);
77 omap2_init_common_infrastructure(); 75 omap2_init_common_infrastructure();
78 omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params, 76 omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
79 h8mbx00u0mer0em_sdrc_params); 77 h8mbx00u0mer0em_sdrc_params);
@@ -206,6 +204,8 @@ static struct flash_partitions sdp_flash_partitions[] = {
206static void __init omap_sdp_init(void) 204static void __init omap_sdp_init(void)
207{ 205{
208 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); 206 omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
207 omap_board_config = sdp_config;
208 omap_board_config_size = ARRAY_SIZE(sdp_config);
209 zoom_peripherals_init(); 209 zoom_peripherals_init();
210 zoom_display_init(); 210 zoom_display_init();
211 board_smc91x_init(); 211 board_smc91x_init();
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 1a943be822c3..85805d432e38 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -325,8 +325,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
325 325
326static void __init omap_4430sdp_init_early(void) 326static void __init omap_4430sdp_init_early(void)
327{ 327{
328 omap_board_config = sdp4430_config;
329 omap_board_config_size = ARRAY_SIZE(sdp4430_config);
330 omap2_init_common_infrastructure(); 328 omap2_init_common_infrastructure();
331 omap2_init_common_devices(NULL, NULL); 329 omap2_init_common_devices(NULL, NULL);
332#ifdef CONFIG_OMAP_32K_TIMER 330#ifdef CONFIG_OMAP_32K_TIMER
@@ -349,11 +347,6 @@ static struct twl4030_usb_data omap4_usbphy_data = {
349 347
350static struct omap2_hsmmc_info mmc[] = { 348static struct omap2_hsmmc_info mmc[] = {
351 { 349 {
352 .mmc = 1,
353 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
354 .gpio_wp = -EINVAL,
355 },
356 {
357 .mmc = 2, 350 .mmc = 2,
358 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, 351 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
359 .gpio_cd = -EINVAL, 352 .gpio_cd = -EINVAL,
@@ -361,19 +354,24 @@ static struct omap2_hsmmc_info mmc[] = {
361 .nonremovable = true, 354 .nonremovable = true,
362 .ocr_mask = MMC_VDD_29_30, 355 .ocr_mask = MMC_VDD_29_30,
363 }, 356 },
357 {
358 .mmc = 1,
359 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
360 .gpio_wp = -EINVAL,
361 },
364 {} /* Terminator */ 362 {} /* Terminator */
365}; 363};
366 364
367static struct regulator_consumer_supply sdp4430_vaux_supply[] = { 365static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
368 { 366 {
369 .supply = "vmmc", 367 .supply = "vmmc",
370 .dev_name = "mmci-omap-hs.1", 368 .dev_name = "omap_hsmmc.1",
371 }, 369 },
372}; 370};
373static struct regulator_consumer_supply sdp4430_vmmc_supply[] = { 371static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
374 { 372 {
375 .supply = "vmmc", 373 .supply = "vmmc",
376 .dev_name = "mmci-omap-hs.0", 374 .dev_name = "omap_hsmmc.0",
377 }, 375 },
378}; 376};
379 377
@@ -640,6 +638,9 @@ static void __init omap_4430sdp_init(void)
640 package = OMAP_PACKAGE_CBL; 638 package = OMAP_PACKAGE_CBL;
641 omap4_mux_init(board_mux, package); 639 omap4_mux_init(board_mux, package);
642 640
641 omap_board_config = sdp4430_config;
642 omap_board_config_size = ARRAY_SIZE(sdp4430_config);
643
643 omap4_i2c_init(); 644 omap4_i2c_init();
644 omap_sfh7741prox_init(); 645 omap_sfh7741prox_init();
645 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); 646 platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index ae3a83d47dab..f53bbb2c3478 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -51,9 +51,6 @@ static struct omap_board_mux board_mux[] __initdata = {
51 51
52static void __init am3517_crane_init_early(void) 52static void __init am3517_crane_init_early(void)
53{ 53{
54 omap_board_config = am3517_crane_config;
55 omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
56
57 omap2_init_common_infrastructure(); 54 omap2_init_common_infrastructure();
58 omap2_init_common_devices(NULL, NULL); 55 omap2_init_common_devices(NULL, NULL);
59} 56}
@@ -76,6 +73,9 @@ static void __init am3517_crane_init(void)
76 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 73 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
77 omap_serial_init(); 74 omap_serial_init();
78 75
76 omap_board_config = am3517_crane_config;
77 omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
78
79 /* Configure GPIO for EHCI port */ 79 /* Configure GPIO for EHCI port */
80 if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) { 80 if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
81 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n", 81 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 634fe65b33c8..30ec45193268 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -381,13 +381,8 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
381/* 381/*
382 * Board initialization 382 * Board initialization
383 */ 383 */
384static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
385};
386
387static void __init am3517_evm_init_early(void) 384static void __init am3517_evm_init_early(void)
388{ 385{
389 omap_board_config = am3517_evm_config;
390 omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
391 omap2_init_common_infrastructure(); 386 omap2_init_common_infrastructure();
392 omap2_init_common_devices(NULL, NULL); 387 omap2_init_common_devices(NULL, NULL);
393} 388}
@@ -481,8 +476,13 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
481 platform_device_register(&am3517_hecc_device); 476 platform_device_register(&am3517_hecc_device);
482} 477}
483 478
479static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
480};
481
484static void __init am3517_evm_init(void) 482static void __init am3517_evm_init(void)
485{ 483{
484 omap_board_config = am3517_evm_config;
485 omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
486 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 486 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
487 487
488 am3517_evm_i2c_init(); 488 am3517_evm_i2c_init();
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 4ef4aad4e719..f4f8374a0298 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -276,8 +276,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
276 276
277static void __init omap_apollon_init_early(void) 277static void __init omap_apollon_init_early(void)
278{ 278{
279 omap_board_config = apollon_config;
280 omap_board_config_size = ARRAY_SIZE(apollon_config);
281 omap2_init_common_infrastructure(); 279 omap2_init_common_infrastructure();
282 omap2_init_common_devices(NULL, NULL); 280 omap2_init_common_devices(NULL, NULL);
283} 281}
@@ -319,6 +317,8 @@ static void __init omap_apollon_init(void)
319 u32 v; 317 u32 v;
320 318
321 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC); 319 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
320 omap_board_config = apollon_config;
321 omap_board_config_size = ARRAY_SIZE(apollon_config);
322 322
323 apollon_init_smc91x(); 323 apollon_init_smc91x();
324 apollon_led_init(); 324 apollon_led_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 7311824be993..27bea540ccbb 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -668,14 +668,8 @@ static void __init cm_t35_init_i2c(void)
668 ARRAY_SIZE(cm_t35_i2c_boardinfo)); 668 ARRAY_SIZE(cm_t35_i2c_boardinfo));
669} 669}
670 670
671static struct omap_board_config_kernel cm_t35_config[] __initdata = {
672};
673
674static void __init cm_t35_init_early(void) 671static void __init cm_t35_init_early(void)
675{ 672{
676 omap_board_config = cm_t35_config;
677 omap_board_config_size = ARRAY_SIZE(cm_t35_config);
678
679 omap2_init_common_infrastructure(); 673 omap2_init_common_infrastructure();
680 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 674 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
681 mt46h32m32lf6_sdrc_params); 675 mt46h32m32lf6_sdrc_params);
@@ -785,8 +779,13 @@ static struct omap_musb_board_data musb_board_data = {
785 .power = 100, 779 .power = 100,
786}; 780};
787 781
782static struct omap_board_config_kernel cm_t35_config[] __initdata = {
783};
784
788static void __init cm_t35_init(void) 785static void __init cm_t35_init(void)
789{ 786{
787 omap_board_config = cm_t35_config;
788 omap_board_config_size = ARRAY_SIZE(cm_t35_config);
790 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); 789 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
791 omap_serial_init(); 790 omap_serial_init();
792 cm_t35_init_i2c(); 791 cm_t35_init_i2c();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 38bef6d004c9..9da6e8240e8b 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -256,9 +256,6 @@ static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
256 256
257static void __init cm_t3517_init_early(void) 257static void __init cm_t3517_init_early(void)
258{ 258{
259 omap_board_config = cm_t3517_config;
260 omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
261
262 omap2_init_common_infrastructure(); 259 omap2_init_common_infrastructure();
263 omap2_init_common_devices(NULL, NULL); 260 omap2_init_common_devices(NULL, NULL);
264} 261}
@@ -293,6 +290,8 @@ static void __init cm_t3517_init(void)
293{ 290{
294 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 291 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
295 omap_serial_init(); 292 omap_serial_init();
293 omap_board_config = cm_t3517_config;
294 omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
296 cm_t3517_init_leds(); 295 cm_t3517_init_leds();
297 cm_t3517_init_nand(); 296 cm_t3517_init_nand();
298 cm_t3517_init_rtc(); 297 cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 54abdd064364..728f27c5bcb1 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
140} 140}
141 141
142static struct regulator_consumer_supply devkit8000_vmmc1_supply = 142static struct regulator_consumer_supply devkit8000_vmmc1_supply =
143 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 143 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
144 144
145 145
146/* ads7846 on SPI */ 146/* ads7846 on SPI */
@@ -342,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
342 .usb_mode = T2_USB_MODE_ULPI, 342 .usb_mode = T2_USB_MODE_ULPI,
343}; 343};
344 344
345static struct twl4030_codec_audio_data devkit8000_audio_data = { 345static struct twl4030_codec_audio_data devkit8000_audio_data;
346 .audio_mclk = 26000000,
347};
348 346
349static struct twl4030_codec_data devkit8000_codec_data = { 347static struct twl4030_codec_data devkit8000_codec_data = {
350 .audio_mclk = 26000000, 348 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index c32c06828f08..729892fdcf2e 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -154,7 +154,7 @@ __init board_nand_init(struct mtd_partition *nand_parts,
154} 154}
155#else 155#else
156void 156void
157__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs) 157__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
158{ 158{
159} 159}
160#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */ 160#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 682da9251db6..73e3c31e8508 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -35,8 +35,6 @@ static struct omap_board_config_kernel generic_config[] = {
35 35
36static void __init omap_generic_init_early(void) 36static void __init omap_generic_init_early(void)
37{ 37{
38 omap_board_config = generic_config;
39 omap_board_config_size = ARRAY_SIZE(generic_config);
40 omap2_init_common_infrastructure(); 38 omap2_init_common_infrastructure();
41 omap2_init_common_devices(NULL, NULL); 39 omap2_init_common_devices(NULL, NULL);
42} 40}
@@ -44,6 +42,8 @@ static void __init omap_generic_init_early(void)
44static void __init omap_generic_init(void) 42static void __init omap_generic_init(void)
45{ 43{
46 omap_serial_init(); 44 omap_serial_init();
45 omap_board_config = generic_config;
46 omap_board_config_size = ARRAY_SIZE(generic_config);
47} 47}
48 48
49static void __init omap_generic_map_io(void) 49static void __init omap_generic_map_io(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f6a3872f72fa..7e6bf4fa1535 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -292,8 +292,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
292 292
293static void __init omap_h4_init_early(void) 293static void __init omap_h4_init_early(void)
294{ 294{
295 omap_board_config = h4_config;
296 omap_board_config_size = ARRAY_SIZE(h4_config);
297 omap2_init_common_infrastructure(); 295 omap2_init_common_infrastructure();
298 omap2_init_common_devices(NULL, NULL); 296 omap2_init_common_devices(NULL, NULL);
299} 297}
@@ -334,6 +332,9 @@ static void __init omap_h4_init(void)
334{ 332{
335 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF); 333 omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
336 334
335 omap_board_config = h4_config;
336 omap_board_config_size = ARRAY_SIZE(h4_config);
337
337 /* 338 /*
338 * Make sure the serial ports are muxed on at this point. 339 * Make sure the serial ports are muxed on at this point.
339 * You have to mux them off in device drivers later on 340 * You have to mux them off in device drivers later on
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 54e6318f4a8f..c4b3c1c47ec6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { }
250#endif 250#endif
251 251
252static struct regulator_consumer_supply igep2_vmmc1_supply = 252static struct regulator_consumer_supply igep2_vmmc1_supply =
253 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 253 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
254 254
255/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 255/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
256static struct regulator_init_data igep2_vmmc1 = { 256static struct regulator_init_data igep2_vmmc1 = {
@@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = {
268}; 268};
269 269
270static struct regulator_consumer_supply igep2_vio_supply = 270static struct regulator_consumer_supply igep2_vio_supply =
271 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 271 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
272 272
273static struct regulator_init_data igep2_vio = { 273static struct regulator_init_data igep2_vio = {
274 .constraints = { 274 .constraints = {
@@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = {
286}; 286};
287 287
288static struct regulator_consumer_supply igep2_vmmc2_supply = 288static struct regulator_consumer_supply igep2_vmmc2_supply =
289 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 289 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
290 290
291static struct regulator_init_data igep2_vmmc2 = { 291static struct regulator_init_data igep2_vmmc2 = {
292 .constraints = { 292 .constraints = {
@@ -521,9 +521,7 @@ static void __init igep2_init_early(void)
521 m65kxxxxam_sdrc_params); 521 m65kxxxxam_sdrc_params);
522} 522}
523 523
524static struct twl4030_codec_audio_data igep2_audio_data = { 524static struct twl4030_codec_audio_data igep2_audio_data;
525 .audio_mclk = 26000000,
526};
527 525
528static struct twl4030_codec_data igep2_codec_data = { 526static struct twl4030_codec_data igep2_codec_data = {
529 .audio_mclk = 26000000, 527 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index d75028e48f5d..4273d0672ef6 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {}
142#endif 142#endif
143 143
144static struct regulator_consumer_supply igep3_vmmc1_supply = 144static struct regulator_consumer_supply igep3_vmmc1_supply =
145 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 145 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
146 146
147/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 147/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
148static struct regulator_init_data igep3_vmmc1 = { 148static struct regulator_init_data igep3_vmmc1 = {
@@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = {
160}; 160};
161 161
162static struct regulator_consumer_supply igep3_vio_supply = 162static struct regulator_consumer_supply igep3_vio_supply =
163 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 163 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
164 164
165static struct regulator_init_data igep3_vio = { 165static struct regulator_init_data igep3_vio = {
166 .constraints = { 166 .constraints = {
@@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = {
178}; 178};
179 179
180static struct regulator_consumer_supply igep3_vmmc2_supply = 180static struct regulator_consumer_supply igep3_vmmc2_supply =
181 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 181 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
182 182
183static struct regulator_init_data igep3_vmmc2 = { 183static struct regulator_init_data igep3_vmmc2 = {
184 .constraints = { 184 .constraints = {
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index a3fae5697a72..e2ba77957a8c 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -290,8 +290,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
290 290
291static void __init omap_ldp_init_early(void) 291static void __init omap_ldp_init_early(void)
292{ 292{
293 omap_board_config = ldp_config;
294 omap_board_config_size = ARRAY_SIZE(ldp_config);
295 omap2_init_common_infrastructure(); 293 omap2_init_common_infrastructure();
296 omap2_init_common_devices(NULL, NULL); 294 omap2_init_common_devices(NULL, NULL);
297} 295}
@@ -329,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = {
329 .consumer_supplies = &ldp_vmmc1_supply, 327 .consumer_supplies = &ldp_vmmc1_supply,
330}; 328};
331 329
330/* ads7846 on SPI */
331static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
332 REGULATOR_SUPPLY("vcc", "spi1.0"),
333};
334
335/* VAUX1 */
336static struct regulator_init_data ldp_vaux1 = {
337 .constraints = {
338 .min_uV = 3000000,
339 .max_uV = 3000000,
340 .apply_uV = true,
341 .valid_modes_mask = REGULATOR_MODE_NORMAL
342 | REGULATOR_MODE_STANDBY,
343 .valid_ops_mask = REGULATOR_CHANGE_MODE
344 | REGULATOR_CHANGE_STATUS,
345 },
346 .num_consumer_supplies = ARRAY_SIZE(ldp_vaux1_supplies),
347 .consumer_supplies = ldp_vaux1_supplies,
348};
349
332static struct twl4030_platform_data ldp_twldata = { 350static struct twl4030_platform_data ldp_twldata = {
333 .irq_base = TWL4030_IRQ_BASE, 351 .irq_base = TWL4030_IRQ_BASE,
334 .irq_end = TWL4030_IRQ_END, 352 .irq_end = TWL4030_IRQ_END,
@@ -337,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = {
337 .madc = &ldp_madc_data, 355 .madc = &ldp_madc_data,
338 .usb = &ldp_usb_data, 356 .usb = &ldp_usb_data,
339 .vmmc1 = &ldp_vmmc1, 357 .vmmc1 = &ldp_vmmc1,
358 .vaux1 = &ldp_vaux1,
340 .gpio = &ldp_gpio_data, 359 .gpio = &ldp_gpio_data,
341 .keypad = &ldp_kp_twl4030_data, 360 .keypad = &ldp_kp_twl4030_data,
342}; 361};
@@ -422,6 +441,8 @@ static struct mtd_partition ldp_nand_partitions[] = {
422static void __init omap_ldp_init(void) 441static void __init omap_ldp_init(void)
423{ 442{
424 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 443 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
444 omap_board_config = ldp_config;
445 omap_board_config_size = ARRAY_SIZE(ldp_config);
425 ldp_init_smsc911x(); 446 ldp_init_smsc911x();
426 omap_i2c_init(); 447 omap_i2c_init();
427 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices)); 448 platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index b36cbd21e2d0..e710cd9e079b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void)
536 } 536 }
537 537
538 mmc_data[0] = &mmc1_data; 538 mmc_data[0] = &mmc1_data;
539 omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC); 539 omap242x_init_mmc(mmc_data);
540} 540}
541#else 541#else
542 542
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index a1faea3b7764..b6752ac5b97e 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -427,9 +427,7 @@ static struct twl4030_usb_data beagle_usb_data = {
427 .usb_mode = T2_USB_MODE_ULPI, 427 .usb_mode = T2_USB_MODE_ULPI,
428}; 428};
429 429
430static struct twl4030_codec_audio_data beagle_audio_data = { 430static struct twl4030_codec_audio_data beagle_audio_data;
431 .audio_mclk = 26000000,
432};
433 431
434static struct twl4030_codec_data beagle_codec_data = { 432static struct twl4030_codec_data beagle_codec_data = {
435 .audio_mclk = 26000000, 433 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 7341f966bf1a..b65848c59e1d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -534,9 +534,7 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
534 .irq_line = 1, 534 .irq_line = 1,
535}; 535};
536 536
537static struct twl4030_codec_audio_data omap3evm_audio_data = { 537static struct twl4030_codec_audio_data omap3evm_audio_data;
538 .audio_mclk = 26000000,
539};
540 538
541static struct twl4030_codec_data omap3evm_codec_data = { 539static struct twl4030_codec_data omap3evm_codec_data = {
542 .audio_mclk = 26000000, 540 .audio_mclk = 26000000,
@@ -604,7 +602,7 @@ static struct regulator_init_data omap3evm_vio = {
604#define OMAP3EVM_WLAN_IRQ_GPIO (149) 602#define OMAP3EVM_WLAN_IRQ_GPIO (149)
605 603
606static struct regulator_consumer_supply omap3evm_vmmc2_supply = 604static struct regulator_consumer_supply omap3evm_vmmc2_supply =
607 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 605 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
608 606
609/* VMMC2 for driving the WL12xx module */ 607/* VMMC2 for driving the WL12xx module */
610static struct regulator_init_data omap3evm_vmmc2 = { 608static struct regulator_init_data omap3evm_vmmc2 = {
@@ -729,8 +727,6 @@ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
729 727
730static void __init omap3_evm_init_early(void) 728static void __init omap3_evm_init_early(void)
731{ 729{
732 omap_board_config = omap3_evm_config;
733 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
734 omap2_init_common_infrastructure(); 730 omap2_init_common_infrastructure();
735 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); 731 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
736} 732}
@@ -836,6 +832,9 @@ static void __init omap3_evm_init(void)
836 else 832 else
837 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB); 833 omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
838 834
835 omap_board_config = omap3_evm_config;
836 omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
837
839 omap3_evm_i2c_init(); 838 omap3_evm_i2c_init();
840 839
841 omap_display_init(&omap3_evm_dss_data); 840 omap_display_init(&omap3_evm_dss_data);
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 17ef5479c7ff..5386a8190ea1 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -333,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
333}; 333};
334 334
335static struct regulator_consumer_supply pandora_vmmc1_supply = 335static struct regulator_consumer_supply pandora_vmmc1_supply =
336 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 336 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
337 337
338static struct regulator_consumer_supply pandora_vmmc2_supply = 338static struct regulator_consumer_supply pandora_vmmc2_supply =
339 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 339 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
340 340
341static struct regulator_consumer_supply pandora_vmmc3_supply = 341static struct regulator_consumer_supply pandora_vmmc3_supply =
342 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2"); 342 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
343 343
344static struct regulator_consumer_supply pandora_vdda_dac_supply = 344static struct regulator_consumer_supply pandora_vdda_dac_supply =
345 REGULATOR_SUPPLY("vdda_dac", "omapdss"); 345 REGULATOR_SUPPLY("vdda_dac", "omapdss");
@@ -516,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
516 .usb_mode = T2_USB_MODE_ULPI, 516 .usb_mode = T2_USB_MODE_ULPI,
517}; 517};
518 518
519static struct twl4030_codec_audio_data omap3pandora_audio_data = { 519static struct twl4030_codec_audio_data omap3pandora_audio_data;
520 .audio_mclk = 26000000,
521};
522 520
523static struct twl4030_codec_data omap3pandora_codec_data = { 521static struct twl4030_codec_data omap3pandora_codec_data = {
524 .audio_mclk = 26000000, 522 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 07006c323fc2..15ede8b49815 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -431,9 +431,7 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
431 .irq_line = 1, 431 .irq_line = 1,
432}; 432};
433 433
434static struct twl4030_codec_audio_data omap3stalker_audio_data = { 434static struct twl4030_codec_audio_data omap3stalker_audio_data;
435 .audio_mclk = 26000000,
436};
437 435
438static struct twl4030_codec_data omap3stalker_codec_data = { 436static struct twl4030_codec_data omap3stalker_codec_data = {
439 .audio_mclk = 26000000, 437 .audio_mclk = 26000000,
@@ -581,8 +579,6 @@ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
581 579
582static void __init omap3_stalker_init_early(void) 580static void __init omap3_stalker_init_early(void)
583{ 581{
584 omap_board_config = omap3_stalker_config;
585 omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
586 omap2_init_common_infrastructure(); 582 omap2_init_common_infrastructure();
587 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL); 583 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
588} 584}
@@ -629,6 +625,8 @@ static struct omap_musb_board_data musb_board_data = {
629static void __init omap3_stalker_init(void) 625static void __init omap3_stalker_init(void)
630{ 626{
631 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); 627 omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
628 omap_board_config = omap3_stalker_config;
629 omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
632 630
633 omap3_stalker_i2c_init(); 631 omap3_stalker_i2c_init();
634 632
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 6a60f79dcccb..5554f5814aa4 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
252 .usb_mode = T2_USB_MODE_ULPI, 252 .usb_mode = T2_USB_MODE_ULPI,
253}; 253};
254 254
255static struct twl4030_codec_audio_data touchbook_audio_data = { 255static struct twl4030_codec_audio_data touchbook_audio_data;
256 .audio_mclk = 26000000,
257};
258 256
259static struct twl4030_codec_data touchbook_codec_data = { 257static struct twl4030_codec_data touchbook_codec_data = {
260 .audio_mclk = 26000000, 258 .audio_mclk = 26000000,
@@ -417,9 +415,6 @@ static struct omap_board_mux board_mux[] __initdata = {
417 415
418static void __init omap3_touchbook_init_early(void) 416static void __init omap3_touchbook_init_early(void)
419{ 417{
420 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
421 omap_board_config = omap3_touchbook_config;
422 omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
423 omap2_init_common_infrastructure(); 418 omap2_init_common_infrastructure();
424 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 419 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
425 mt46h32m32lf6_sdrc_params); 420 mt46h32m32lf6_sdrc_params);
@@ -514,6 +509,10 @@ static struct omap_musb_board_data musb_board_data = {
514 509
515static void __init omap3_touchbook_init(void) 510static void __init omap3_touchbook_init(void)
516{ 511{
512 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
513 omap_board_config = omap3_touchbook_config;
514 omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
515
517 pm_power_off = omap3_touchbook_poweroff; 516 pm_power_off = omap3_touchbook_poweroff;
518 517
519 omap3_touchbook_i2c_init(); 518 omap3_touchbook_i2c_init();
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 3dd241b95159..a94ce07be72f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -50,6 +50,16 @@
50#define GPIO_WIFI_PMENA 43 50#define GPIO_WIFI_PMENA 43
51#define GPIO_WIFI_IRQ 53 51#define GPIO_WIFI_IRQ 53
52 52
53/* wl127x BT, FM, GPS connectivity chip */
54static int wl1271_gpios[] = {46, -1, -1};
55static struct platform_device wl1271_device = {
56 .name = "kim",
57 .id = -1,
58 .dev = {
59 .platform_data = &wl1271_gpios,
60 },
61};
62
53static struct gpio_led gpio_leds[] = { 63static struct gpio_led gpio_leds[] = {
54 { 64 {
55 .name = "pandaboard::status1", 65 .name = "pandaboard::status1",
@@ -78,6 +88,7 @@ static struct platform_device leds_gpio = {
78 88
79static struct platform_device *panda_devices[] __initdata = { 89static struct platform_device *panda_devices[] __initdata = {
80 &leds_gpio, 90 &leds_gpio,
91 &wl1271_device,
81}; 92};
82 93
83static void __init omap4_panda_init_early(void) 94static void __init omap4_panda_init_early(void)
@@ -180,13 +191,13 @@ static struct omap2_hsmmc_info mmc[] = {
180static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = { 191static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
181 { 192 {
182 .supply = "vmmc", 193 .supply = "vmmc",
183 .dev_name = "mmci-omap-hs.0", 194 .dev_name = "omap_hsmmc.0",
184 }, 195 },
185}; 196};
186 197
187static struct regulator_consumer_supply omap4_panda_vmmc5_supply = { 198static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
188 .supply = "vmmc", 199 .supply = "vmmc",
189 .dev_name = "mmci-omap-hs.4", 200 .dev_name = "omap_hsmmc.4",
190}; 201};
191 202
192static struct regulator_init_data panda_vmmc5 = { 203static struct regulator_init_data panda_vmmc5 = {
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index a33ec0edec13..60f8db31763c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = {
358 .consumer_supplies = &overo_vmmc1_supply, 358 .consumer_supplies = &overo_vmmc1_supply,
359}; 359};
360 360
361static struct twl4030_codec_audio_data overo_audio_data = { 361static struct twl4030_codec_audio_data overo_audio_data;
362 .audio_mclk = 26000000,
363};
364 362
365static struct twl4030_codec_data overo_codec_data = { 363static struct twl4030_codec_data overo_codec_data = {
366 .audio_mclk = 26000000, 364 .audio_mclk = 26000000,
@@ -411,8 +409,6 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
411 409
412static void __init overo_init_early(void) 410static void __init overo_init_early(void)
413{ 411{
414 omap_board_config = overo_config;
415 omap_board_config_size = ARRAY_SIZE(overo_config);
416 omap2_init_common_infrastructure(); 412 omap2_init_common_infrastructure();
417 omap2_init_common_devices(mt46h32m32lf6_sdrc_params, 413 omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
418 mt46h32m32lf6_sdrc_params); 414 mt46h32m32lf6_sdrc_params);
@@ -448,6 +444,8 @@ static struct omap_musb_board_data musb_board_data = {
448static void __init overo_init(void) 444static void __init overo_init(void)
449{ 445{
450 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 446 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
447 omap_board_config = overo_config;
448 omap_board_config_size = ARRAY_SIZE(overo_config);
451 overo_i2c_init(); 449 overo_i2c_init();
452 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices)); 450 platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
453 omap_serial_init(); 451 omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index bdebcb7328e6..2af8b05e786d 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -33,7 +33,7 @@
33#include "sdram-nokia.h" 33#include "sdram-nokia.h"
34 34
35static struct regulator_consumer_supply rm680_vemmc_consumers[] = { 35static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
36 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), 36 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
37}; 37};
38 38
39/* Fixed regulator for internal eMMC */ 39/* Fixed regulator for internal eMMC */
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index e75e240cad67..5f1900c532ec 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -36,6 +36,8 @@
36 36
37#include <sound/tlv320aic3x.h> 37#include <sound/tlv320aic3x.h>
38#include <sound/tpa6130a2-plat.h> 38#include <sound/tpa6130a2-plat.h>
39#include <media/radio-si4713.h>
40#include <media/si4713.h>
39 41
40#include <../drivers/staging/iio/light/tsl2563.h> 42#include <../drivers/staging/iio/light/tsl2563.h>
41 43
@@ -47,6 +49,8 @@
47 49
48#define RX51_WL1251_POWER_GPIO 87 50#define RX51_WL1251_POWER_GPIO 87
49#define RX51_WL1251_IRQ_GPIO 42 51#define RX51_WL1251_IRQ_GPIO 42
52#define RX51_FMTX_RESET_GPIO 163
53#define RX51_FMTX_IRQ 53
50 54
51/* list all spi devices here */ 55/* list all spi devices here */
52enum { 56enum {
@@ -331,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
331}; 335};
332 336
333static struct regulator_consumer_supply rx51_vmmc1_supply = 337static struct regulator_consumer_supply rx51_vmmc1_supply =
334 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0"); 338 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
335 339
336static struct regulator_consumer_supply rx51_vaux3_supply = 340static struct regulator_consumer_supply rx51_vaux3_supply =
337 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"); 341 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
338 342
339static struct regulator_consumer_supply rx51_vsim_supply = 343static struct regulator_consumer_supply rx51_vsim_supply =
340 REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1"); 344 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
341 345
342static struct regulator_consumer_supply rx51_vmmc2_supplies[] = { 346static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
343 /* tlv320aic3x analog supplies */ 347 /* tlv320aic3x analog supplies */
@@ -348,7 +352,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
348 /* tpa6130a2 */ 352 /* tpa6130a2 */
349 REGULATOR_SUPPLY("Vdd", "2-0060"), 353 REGULATOR_SUPPLY("Vdd", "2-0060"),
350 /* Keep vmmc as last item. It is not iterated for newer boards */ 354 /* Keep vmmc as last item. It is not iterated for newer boards */
351 REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"), 355 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
352}; 356};
353 357
354static struct regulator_consumer_supply rx51_vio_supplies[] = { 358static struct regulator_consumer_supply rx51_vio_supplies[] = {
@@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
357 REGULATOR_SUPPLY("DVDD", "2-0018"), 361 REGULATOR_SUPPLY("DVDD", "2-0018"),
358 REGULATOR_SUPPLY("IOVDD", "2-0019"), 362 REGULATOR_SUPPLY("IOVDD", "2-0019"),
359 REGULATOR_SUPPLY("DVDD", "2-0019"), 363 REGULATOR_SUPPLY("DVDD", "2-0019"),
364 /* Si4713 IO supply */
365 REGULATOR_SUPPLY("vio", "2-0063"),
360}; 366};
361 367
362static struct regulator_consumer_supply rx51_vaux1_consumers[] = { 368static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
363 REGULATOR_SUPPLY("vdds_sdi", "omapdss"), 369 REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
370 /* Si4713 supply */
371 REGULATOR_SUPPLY("vdd", "2-0063"),
364}; 372};
365 373
366static struct regulator_consumer_supply rx51_vdac_supply[] = { 374static struct regulator_consumer_supply rx51_vdac_supply[] = {
@@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = {
511 .consumer_supplies = rx51_vio_supplies, 519 .consumer_supplies = rx51_vio_supplies,
512}; 520};
513 521
522static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
523 .gpio_reset = RX51_FMTX_RESET_GPIO,
524};
525
526static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
527 I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
528 .platform_data = &rx51_si4713_i2c_data,
529};
530
531static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
532 .i2c_bus = 2,
533 .subdev_board_info = &rx51_si4713_board_info,
534};
535
536static struct platform_device rx51_si4713_dev __initdata_or_module = {
537 .name = "radio-si4713",
538 .id = -1,
539 .dev = {
540 .platform_data = &rx51_si4713_data,
541 },
542};
543
544static __init void rx51_init_si4713(void)
545{
546 int err;
547
548 err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
549 if (err) {
550 printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
551 return;
552 }
553 rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
554 platform_device_register(&rx51_si4713_dev);
555}
556
514static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) 557static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
515{ 558{
516 /* FIXME this gpio setup is just a placeholder for now */ 559 /* FIXME this gpio setup is just a placeholder for now */
@@ -699,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
699 .resource_config = twl4030_rconfig, 742 .resource_config = twl4030_rconfig,
700}; 743};
701 744
745struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
746 .coexist = 0,
747};
748
749struct twl4030_codec_data rx51_codec_data __initdata = {
750 .audio_mclk = 26000000,
751 .vibra = &rx51_vibra_data,
752};
702 753
703static struct twl4030_platform_data rx51_twldata __initdata = { 754static struct twl4030_platform_data rx51_twldata __initdata = {
704 .irq_base = TWL4030_IRQ_BASE, 755 .irq_base = TWL4030_IRQ_BASE,
@@ -710,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
710 .madc = &rx51_madc_data, 761 .madc = &rx51_madc_data,
711 .usb = &rx51_usb_data, 762 .usb = &rx51_usb_data,
712 .power = &rx51_t2scripts_data, 763 .power = &rx51_t2scripts_data,
764 .codec = &rx51_codec_data,
713 765
714 .vaux1 = &rx51_vaux1, 766 .vaux1 = &rx51_vaux1,
715 .vaux2 = &rx51_vaux2, 767 .vaux2 = &rx51_vaux2,
@@ -921,6 +973,7 @@ void __init rx51_peripherals_init(void)
921 board_smc91x_init(); 973 board_smc91x_init();
922 rx51_add_gpio_keys(); 974 rx51_add_gpio_keys();
923 rx51_init_wl1251(); 975 rx51_init_wl1251();
976 rx51_init_si4713();
924 spi_register_board_info(rx51_peripherals_spi_board_info, 977 spi_register_board_info(rx51_peripherals_spi_board_info,
925 ARRAY_SIZE(rx51_peripherals_spi_board_info)); 978 ARRAY_SIZE(rx51_peripherals_spi_board_info));
926 979
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 3cf72fe6d75b..e964895b80e8 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -102,9 +102,6 @@ static void __init rx51_init_early(void)
102{ 102{
103 struct omap_sdrc_params *sdrc_params; 103 struct omap_sdrc_params *sdrc_params;
104 104
105 omap_board_config = rx51_config;
106 omap_board_config_size = ARRAY_SIZE(rx51_config);
107 omap3_pm_init_cpuidle(rx51_cpuidle_params);
108 omap2_init_common_infrastructure(); 105 omap2_init_common_infrastructure();
109 sdrc_params = nokia_get_sdram_timings(); 106 sdrc_params = nokia_get_sdram_timings();
110 omap2_init_common_devices(sdrc_params, sdrc_params); 107 omap2_init_common_devices(sdrc_params, sdrc_params);
@@ -127,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = {
127static void __init rx51_init(void) 124static void __init rx51_init(void)
128{ 125{
129 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 126 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
127 omap_board_config = rx51_config;
128 omap_board_config_size = ARRAY_SIZE(rx51_config);
129 omap3_pm_init_cpuidle(rx51_cpuidle_params);
130 omap_serial_init(); 130 omap_serial_init();
131 usb_musb_init(&musb_board_data); 131 usb_musb_init(&musb_board_data);
132 rx51_peripherals_init(); 132 rx51_peripherals_init();
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index f2b097190e07..09fa7bfff8d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -29,8 +29,6 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
29 29
30static void __init ti8168_init_early(void) 30static void __init ti8168_init_early(void)
31{ 31{
32 omap_board_config = ti8168_evm_config;
33 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
34 omap2_init_common_infrastructure(); 32 omap2_init_common_infrastructure();
35 omap2_init_common_devices(NULL, NULL); 33 omap2_init_common_devices(NULL, NULL);
36} 34}
@@ -43,6 +41,8 @@ static void __init ti8168_evm_init_irq(void)
43static void __init ti8168_evm_init(void) 41static void __init ti8168_evm_init(void)
44{ 42{
45 omap_serial_init(); 43 omap_serial_init();
44 omap_board_config = ti8168_evm_config;
45 omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
46} 46}
47 47
48static void __init ti8168_evm_map_io(void) 48static void __init ti8168_evm_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index e0e040f34c68..448ab60195d5 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
118 118
119static struct regulator_consumer_supply zoom_vmmc3_supply = { 119static struct regulator_consumer_supply zoom_vmmc3_supply = {
120 .supply = "vmmc", 120 .supply = "vmmc",
121 .dev_name = "mmci-omap-hs.2", 121 .dev_name = "omap_hsmmc.2",
122}; 122};
123 123
124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ 124/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
322 .irq_line = 1, 322 .irq_line = 1,
323}; 323};
324 324
325static struct twl4030_codec_audio_data zoom_audio_data = { 325static struct twl4030_codec_audio_data zoom_audio_data;
326 .audio_mclk = 26000000,
327};
328 326
329static struct twl4030_codec_data zoom_codec_data = { 327static struct twl4030_codec_data zoom_codec_data = {
330 .audio_mclk = 26000000, 328 .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index c047dcd007e5..5c647ce05b04 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1984,15 +1984,15 @@ static struct omap_clk omap2430_clks[] = {
1984 CLK(NULL, "pka_ick", &pka_ick, CK_243X), 1984 CLK(NULL, "pka_ick", &pka_ick, CK_243X),
1985 CLK(NULL, "usb_fck", &usb_fck, CK_243X), 1985 CLK(NULL, "usb_fck", &usb_fck, CK_243X),
1986 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X), 1986 CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
1987 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), 1987 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
1988 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), 1988 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
1989 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), 1989 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
1990 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), 1990 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
1991 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), 1991 CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
1992 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), 1992 CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
1993 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), 1993 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
1994 CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), 1994 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X),
1995 CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), 1995 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X),
1996}; 1996};
1997 1997
1998/* 1998/*
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f14d986f0b5d..052ac329282f 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3290,10 +3290,10 @@ static struct omap_clk omap3xxx_clks[] = {
3290 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX), 3290 CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
3291 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX), 3291 CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
3292 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX), 3292 CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
3293 CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3293 CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3294 CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_3XXX), 3294 CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
3295 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX), 3295 CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
3296 CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_3XXX), 3296 CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
3297 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX), 3297 CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
3298 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX), 3298 CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
3299 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX), 3299 CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
@@ -3323,13 +3323,13 @@ static struct omap_clk omap3xxx_clks[] = {
3323 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX), 3323 CLK(NULL, "core_l4_ick", &core_l4_ick, CK_3XXX),
3324 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3324 CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3325 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3325 CLK("ehci-omap.0", "usbtll_ick", &usbtll_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3326 CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX), 3326 CLK("omap_hsmmc.2", "ick", &mmchs3_ick, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
3327 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX), 3327 CLK(NULL, "icr_ick", &icr_ick, CK_34XX | CK_36XX),
3328 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX), 3328 CLK("omap-aes", "ick", &aes2_ick, CK_34XX | CK_36XX),
3329 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX), 3329 CLK("omap-sham", "ick", &sha12_ick, CK_34XX | CK_36XX),
3330 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX), 3330 CLK(NULL, "des2_ick", &des2_ick, CK_34XX | CK_36XX),
3331 CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_3XXX), 3331 CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_3XXX),
3332 CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_3XXX), 3332 CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_3XXX),
3333 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX), 3333 CLK(NULL, "mspro_ick", &mspro_ick, CK_34XX | CK_36XX),
3334 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX), 3334 CLK("omap_hdq.0", "ick", &hdq_ick, CK_3XXX),
3335 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX), 3335 CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index de9ec8ddd2ae..fdbc0426b6f4 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3158,11 +3158,11 @@ static struct omap_clk omap44xx_clks[] = {
3158 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X), 3158 CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
3159 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X), 3159 CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
3160 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X), 3160 CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
3161 CLK("mmci-omap-hs.0", "fck", &mmc1_fck, CK_443X), 3161 CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
3162 CLK("mmci-omap-hs.1", "fck", &mmc2_fck, CK_443X), 3162 CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
3163 CLK("mmci-omap-hs.2", "fck", &mmc3_fck, CK_443X), 3163 CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
3164 CLK("mmci-omap-hs.3", "fck", &mmc4_fck, CK_443X), 3164 CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
3165 CLK("mmci-omap-hs.4", "fck", &mmc5_fck, CK_443X), 3165 CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
3166 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X), 3166 CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
3167 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X), 3167 CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
3168 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X), 3168 CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@@ -3245,11 +3245,11 @@ static struct omap_clk omap44xx_clks[] = {
3245 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X), 3245 CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
3246 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X), 3246 CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
3247 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X), 3247 CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
3248 CLK("mmci-omap-hs.0", "ick", &dummy_ck, CK_443X), 3248 CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
3249 CLK("mmci-omap-hs.1", "ick", &dummy_ck, CK_443X), 3249 CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
3250 CLK("mmci-omap-hs.2", "ick", &dummy_ck, CK_443X), 3250 CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
3251 CLK("mmci-omap-hs.3", "ick", &dummy_ck, CK_443X), 3251 CLK("omap_hsmmc.3", "ick", &dummy_ck, CK_443X),
3252 CLK("mmci-omap-hs.4", "ick", &dummy_ck, CK_443X), 3252 CLK("omap_hsmmc.4", "ick", &dummy_ck, CK_443X),
3253 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X), 3253 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_443X),
3254 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X), 3254 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_443X),
3255 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X), 3255 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_443X),
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 9ee876fd367a..2cb720b5b12e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -184,95 +184,29 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
184} 184}
185 185
186#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) 186#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
187 187static struct omap_device_pm_latency mbox_latencies[] = {
188#define MBOX_REG_SIZE 0x120 188 [0] = {
189 189 .activate_func = omap_device_enable_hwmods,
190#ifdef CONFIG_ARCH_OMAP2 190 .deactivate_func = omap_device_idle_hwmods,
191static struct resource omap2_mbox_resources[] = { 191 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
192 {
193 .start = OMAP24XX_MAILBOX_BASE,
194 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
195 .flags = IORESOURCE_MEM,
196 },
197 {
198 .start = INT_24XX_MAIL_U0_MPU,
199 .flags = IORESOURCE_IRQ,
200 .name = "dsp",
201 },
202 {
203 .start = INT_24XX_MAIL_U3_MPU,
204 .flags = IORESOURCE_IRQ,
205 .name = "iva",
206 },
207};
208static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
209#else
210#define omap2_mbox_resources NULL
211#define omap2_mbox_resources_sz 0
212#endif
213
214#ifdef CONFIG_ARCH_OMAP3
215static struct resource omap3_mbox_resources[] = {
216 {
217 .start = OMAP34XX_MAILBOX_BASE,
218 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .start = INT_24XX_MAIL_U0_MPU,
223 .flags = IORESOURCE_IRQ,
224 .name = "dsp",
225 },
226};
227static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
228#else
229#define omap3_mbox_resources NULL
230#define omap3_mbox_resources_sz 0
231#endif
232
233#ifdef CONFIG_ARCH_OMAP4
234
235#define OMAP4_MBOX_REG_SIZE 0x130
236static struct resource omap4_mbox_resources[] = {
237 {
238 .start = OMAP44XX_MAILBOX_BASE,
239 .end = OMAP44XX_MAILBOX_BASE +
240 OMAP4_MBOX_REG_SIZE - 1,
241 .flags = IORESOURCE_MEM,
242 },
243 {
244 .start = OMAP44XX_IRQ_MAIL_U0,
245 .flags = IORESOURCE_IRQ,
246 .name = "mbox",
247 }, 192 },
248}; 193};
249static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
250#else
251#define omap4_mbox_resources NULL
252#define omap4_mbox_resources_sz 0
253#endif
254
255static struct platform_device mbox_device = {
256 .name = "omap-mailbox",
257 .id = -1,
258};
259 194
260static inline void omap_init_mbox(void) 195static inline void omap_init_mbox(void)
261{ 196{
262 if (cpu_is_omap24xx()) { 197 struct omap_hwmod *oh;
263 mbox_device.resource = omap2_mbox_resources; 198 struct omap_device *od;
264 mbox_device.num_resources = omap2_mbox_resources_sz; 199
265 } else if (cpu_is_omap34xx()) { 200 oh = omap_hwmod_lookup("mailbox");
266 mbox_device.resource = omap3_mbox_resources; 201 if (!oh) {
267 mbox_device.num_resources = omap3_mbox_resources_sz; 202 pr_err("%s: unable to find hwmod\n", __func__);
268 } else if (cpu_is_omap44xx()) {
269 mbox_device.resource = omap4_mbox_resources;
270 mbox_device.num_resources = omap4_mbox_resources_sz;
271 } else {
272 pr_err("%s: platform not supported\n", __func__);
273 return; 203 return;
274 } 204 }
275 platform_device_register(&mbox_device); 205
206 od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
207 mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
208 WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
209 __func__, PTR_ERR(od));
276} 210}
277#else 211#else
278static inline void omap_init_mbox(void) { } 212static inline void omap_init_mbox(void) { }
@@ -544,117 +478,10 @@ static inline void omap_init_aes(void) { }
544 478
545/*-------------------------------------------------------------------------*/ 479/*-------------------------------------------------------------------------*/
546 480
547#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) 481#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
548
549#define MMCHS_SYSCONFIG 0x0010
550#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
551#define MMCHS_SYSSTATUS 0x0014
552#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
553 482
554static struct platform_device dummy_pdev = { 483static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
555 .dev = { 484 *mmc_controller)
556 .bus = &platform_bus_type,
557 },
558};
559
560/**
561 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
562 *
563 * Ensure that each MMC controller is fully reset. Controllers
564 * left in an unknown state (by bootloader) may prevent retention
565 * or OFF-mode. This is especially important in cases where the
566 * MMC driver is not enabled, _or_ built as a module.
567 *
568 * In order for reset to work, interface, functional and debounce
569 * clocks must be enabled. The debounce clock comes from func_32k_clk
570 * and is not under SW control, so we only enable i- and f-clocks.
571 **/
572static void __init omap_hsmmc_reset(void)
573{
574 u32 i, nr_controllers;
575 struct clk *iclk, *fclk;
576
577 if (cpu_is_omap242x())
578 return;
579
580 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
581 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
582
583 for (i = 0; i < nr_controllers; i++) {
584 u32 v, base = 0;
585 struct device *dev = &dummy_pdev.dev;
586
587 switch (i) {
588 case 0:
589 base = OMAP2_MMC1_BASE;
590 break;
591 case 1:
592 base = OMAP2_MMC2_BASE;
593 break;
594 case 2:
595 base = OMAP3_MMC3_BASE;
596 break;
597 case 3:
598 if (!cpu_is_omap44xx())
599 return;
600 base = OMAP4_MMC4_BASE;
601 break;
602 case 4:
603 if (!cpu_is_omap44xx())
604 return;
605 base = OMAP4_MMC5_BASE;
606 break;
607 }
608
609 if (cpu_is_omap44xx())
610 base += OMAP4_MMC_REG_OFFSET;
611
612 dummy_pdev.id = i;
613 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
614 iclk = clk_get(dev, "ick");
615 if (IS_ERR(iclk))
616 goto err1;
617 if (clk_enable(iclk))
618 goto err2;
619
620 fclk = clk_get(dev, "fck");
621 if (IS_ERR(fclk))
622 goto err3;
623 if (clk_enable(fclk))
624 goto err4;
625
626 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
627 v = omap_readl(base + MMCHS_SYSSTATUS);
628 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
629 MMCHS_SYSSTATUS_RESETDONE))
630 cpu_relax();
631
632 clk_disable(fclk);
633 clk_put(fclk);
634 clk_disable(iclk);
635 clk_put(iclk);
636 }
637 return;
638
639err4:
640 clk_put(fclk);
641err3:
642 clk_disable(iclk);
643err2:
644 clk_put(iclk);
645err1:
646 printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
647 "cannot reset.\n", __func__, i);
648}
649#else
650static inline void omap_hsmmc_reset(void) {}
651#endif
652
653#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
654 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
655
656static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
657 int controller_nr)
658{ 485{
659 if ((mmc_controller->slots[0].switch_pin > 0) && \ 486 if ((mmc_controller->slots[0].switch_pin > 0) && \
660 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES)) 487 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@@ -665,163 +492,44 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
665 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp, 492 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
666 OMAP_PIN_INPUT_PULLUP); 493 OMAP_PIN_INPUT_PULLUP);
667 494
668 if (cpu_is_omap2420() && controller_nr == 0) { 495 omap_mux_init_signal("sdmmc_cmd", 0);
669 omap_mux_init_signal("sdmmc_cmd", 0); 496 omap_mux_init_signal("sdmmc_clki", 0);
670 omap_mux_init_signal("sdmmc_clki", 0); 497 omap_mux_init_signal("sdmmc_clko", 0);
671 omap_mux_init_signal("sdmmc_clko", 0); 498 omap_mux_init_signal("sdmmc_dat0", 0);
672 omap_mux_init_signal("sdmmc_dat0", 0); 499 omap_mux_init_signal("sdmmc_dat_dir0", 0);
673 omap_mux_init_signal("sdmmc_dat_dir0", 0); 500 omap_mux_init_signal("sdmmc_cmd_dir", 0);
674 omap_mux_init_signal("sdmmc_cmd_dir", 0); 501 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
675 if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) { 502 omap_mux_init_signal("sdmmc_dat1", 0);
676 omap_mux_init_signal("sdmmc_dat1", 0); 503 omap_mux_init_signal("sdmmc_dat2", 0);
677 omap_mux_init_signal("sdmmc_dat2", 0); 504 omap_mux_init_signal("sdmmc_dat3", 0);
678 omap_mux_init_signal("sdmmc_dat3", 0); 505 omap_mux_init_signal("sdmmc_dat_dir1", 0);
679 omap_mux_init_signal("sdmmc_dat_dir1", 0); 506 omap_mux_init_signal("sdmmc_dat_dir2", 0);
680 omap_mux_init_signal("sdmmc_dat_dir2", 0); 507 omap_mux_init_signal("sdmmc_dat_dir3", 0);
681 omap_mux_init_signal("sdmmc_dat_dir3", 0);
682 }
683
684 /*
685 * Use internal loop-back in MMC/SDIO Module Input Clock
686 * selection
687 */
688 if (mmc_controller->slots[0].internal_clock) {
689 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
690 v |= (1 << 24);
691 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
692 }
693 } 508 }
694 509
695 if (cpu_is_omap34xx()) { 510 /*
696 if (controller_nr == 0) { 511 * Use internal loop-back in MMC/SDIO Module Input Clock
697 omap_mux_init_signal("sdmmc1_clk", 512 * selection
698 OMAP_PIN_INPUT_PULLUP); 513 */
699 omap_mux_init_signal("sdmmc1_cmd", 514 if (mmc_controller->slots[0].internal_clock) {
700 OMAP_PIN_INPUT_PULLUP); 515 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
701 omap_mux_init_signal("sdmmc1_dat0", 516 v |= (1 << 24);
702 OMAP_PIN_INPUT_PULLUP); 517 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
703 if (mmc_controller->slots[0].caps &
704 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
705 omap_mux_init_signal("sdmmc1_dat1",
706 OMAP_PIN_INPUT_PULLUP);
707 omap_mux_init_signal("sdmmc1_dat2",
708 OMAP_PIN_INPUT_PULLUP);
709 omap_mux_init_signal("sdmmc1_dat3",
710 OMAP_PIN_INPUT_PULLUP);
711 }
712 if (mmc_controller->slots[0].caps &
713 MMC_CAP_8_BIT_DATA) {
714 omap_mux_init_signal("sdmmc1_dat4",
715 OMAP_PIN_INPUT_PULLUP);
716 omap_mux_init_signal("sdmmc1_dat5",
717 OMAP_PIN_INPUT_PULLUP);
718 omap_mux_init_signal("sdmmc1_dat6",
719 OMAP_PIN_INPUT_PULLUP);
720 omap_mux_init_signal("sdmmc1_dat7",
721 OMAP_PIN_INPUT_PULLUP);
722 }
723 }
724 if (controller_nr == 1) {
725 /* MMC2 */
726 omap_mux_init_signal("sdmmc2_clk",
727 OMAP_PIN_INPUT_PULLUP);
728 omap_mux_init_signal("sdmmc2_cmd",
729 OMAP_PIN_INPUT_PULLUP);
730 omap_mux_init_signal("sdmmc2_dat0",
731 OMAP_PIN_INPUT_PULLUP);
732
733 /*
734 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
735 * in the board-*.c files
736 */
737 if (mmc_controller->slots[0].caps &
738 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
739 omap_mux_init_signal("sdmmc2_dat1",
740 OMAP_PIN_INPUT_PULLUP);
741 omap_mux_init_signal("sdmmc2_dat2",
742 OMAP_PIN_INPUT_PULLUP);
743 omap_mux_init_signal("sdmmc2_dat3",
744 OMAP_PIN_INPUT_PULLUP);
745 }
746 if (mmc_controller->slots[0].caps &
747 MMC_CAP_8_BIT_DATA) {
748 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
749 OMAP_PIN_INPUT_PULLUP);
750 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
751 OMAP_PIN_INPUT_PULLUP);
752 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
753 OMAP_PIN_INPUT_PULLUP);
754 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
755 OMAP_PIN_INPUT_PULLUP);
756 }
757 }
758
759 /*
760 * For MMC3 the pins need to be muxed in the board-*.c files
761 */
762 } 518 }
763} 519}
764 520
765void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 521void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
766 int nr_controllers)
767{ 522{
768 int i; 523 char *name = "mmci-omap";
769 char *name;
770 524
771 for (i = 0; i < nr_controllers; i++) { 525 if (!mmc_data[0]) {
772 unsigned long base, size; 526 pr_err("%s fails: Incomplete platform data\n", __func__);
773 unsigned int irq = 0; 527 return;
774 528 }
775 if (!mmc_data[i])
776 continue;
777
778 omap2_mmc_mux(mmc_data[i], i);
779 529
780 switch (i) { 530 omap242x_mmc_mux(mmc_data[0]);
781 case 0: 531 omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
782 base = OMAP2_MMC1_BASE; 532 INT_24XX_MMC_IRQ, mmc_data[0]);
783 irq = INT_24XX_MMC_IRQ;
784 break;
785 case 1:
786 base = OMAP2_MMC2_BASE;
787 irq = INT_24XX_MMC2_IRQ;
788 break;
789 case 2:
790 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
791 return;
792 base = OMAP3_MMC3_BASE;
793 irq = INT_34XX_MMC3_IRQ;
794 break;
795 case 3:
796 if (!cpu_is_omap44xx())
797 return;
798 base = OMAP4_MMC4_BASE;
799 irq = OMAP44XX_IRQ_MMC4;
800 break;
801 case 4:
802 if (!cpu_is_omap44xx())
803 return;
804 base = OMAP4_MMC5_BASE;
805 irq = OMAP44XX_IRQ_MMC5;
806 break;
807 default:
808 continue;
809 }
810
811 if (cpu_is_omap2420()) {
812 size = OMAP2420_MMC_SIZE;
813 name = "mmci-omap";
814 } else if (cpu_is_omap44xx()) {
815 if (i < 3)
816 irq += OMAP44XX_IRQ_GIC_START;
817 size = OMAP4_HSMMC_SIZE;
818 name = "mmci-omap-hs";
819 } else {
820 size = OMAP3_HSMMC_SIZE;
821 name = "mmci-omap-hs";
822 }
823 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
824 };
825} 533}
826 534
827#endif 535#endif
@@ -895,7 +603,6 @@ static int __init omap2_init_devices(void)
895 * please keep these calls, and their implementations above, 603 * please keep these calls, and their implementations above,
896 * in alphabetical order so they're easier to sort through. 604 * in alphabetical order so they're easier to sort through.
897 */ 605 */
898 omap_hsmmc_reset();
899 omap_init_audio(); 606 omap_init_audio();
900 omap_init_camera(); 607 omap_init_camera();
901 omap_init_mbox(); 608 omap_init_mbox();
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 5496bc7d40ad..137e1a5f3d85 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -16,7 +16,10 @@
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17#include <plat/mmc.h> 17#include <plat/mmc.h>
18#include <plat/omap-pm.h> 18#include <plat/omap-pm.h>
19#include <plat/mux.h>
20#include <plat/omap_device.h>
19 21
22#include "mux.h"
20#include "hsmmc.h" 23#include "hsmmc.h"
21#include "control.h" 24#include "control.h"
22 25
@@ -28,10 +31,6 @@ static u16 control_mmc1;
28 31
29#define HSMMC_NAME_LEN 9 32#define HSMMC_NAME_LEN 9
30 33
31static struct hsmmc_controller {
32 char name[HSMMC_NAME_LEN + 1];
33} hsmmc[OMAP34XX_NR_MMC];
34
35#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) 34#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
36 35
37static int hsmmc_get_context_loss(struct device *dev) 36static int hsmmc_get_context_loss(struct device *dev)
@@ -204,179 +203,312 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
204 return 0; 203 return 0;
205} 204}
206 205
207static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; 206static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
208 207 int controller_nr)
209void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
210{ 208{
211 struct omap2_hsmmc_info *c; 209 if ((mmc_controller->slots[0].switch_pin > 0) && \
212 int nr_hsmmc = ARRAY_SIZE(hsmmc_data); 210 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
213 int i; 211 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
214 u32 reg; 212 OMAP_PIN_INPUT_PULLUP);
215 213 if ((mmc_controller->slots[0].gpio_wp > 0) && \
216 if (!cpu_is_omap44xx()) { 214 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
217 if (cpu_is_omap2430()) { 215 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
218 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE; 216 OMAP_PIN_INPUT_PULLUP);
219 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1; 217 if (cpu_is_omap34xx()) {
220 } else { 218 if (controller_nr == 0) {
221 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE; 219 omap_mux_init_signal("sdmmc1_clk",
222 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1; 220 OMAP_PIN_INPUT_PULLUP);
223 } 221 omap_mux_init_signal("sdmmc1_cmd",
224 } else { 222 OMAP_PIN_INPUT_PULLUP);
225 control_pbias_offset = 223 omap_mux_init_signal("sdmmc1_dat0",
226 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE; 224 OMAP_PIN_INPUT_PULLUP);
227 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1; 225 if (mmc_controller->slots[0].caps &
228 reg = omap4_ctrl_pad_readl(control_mmc1); 226 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
229 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK | 227 omap_mux_init_signal("sdmmc1_dat1",
230 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK); 228 OMAP_PIN_INPUT_PULLUP);
231 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK | 229 omap_mux_init_signal("sdmmc1_dat2",
232 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK); 230 OMAP_PIN_INPUT_PULLUP);
233 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK| 231 omap_mux_init_signal("sdmmc1_dat3",
234 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK | 232 OMAP_PIN_INPUT_PULLUP);
235 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK); 233 }
236 omap4_ctrl_pad_writel(reg, control_mmc1); 234 if (mmc_controller->slots[0].caps &
237 } 235 MMC_CAP_8_BIT_DATA) {
238 236 omap_mux_init_signal("sdmmc1_dat4",
239 for (c = controllers; c->mmc; c++) { 237 OMAP_PIN_INPUT_PULLUP);
240 struct hsmmc_controller *hc = hsmmc + c->mmc - 1; 238 omap_mux_init_signal("sdmmc1_dat5",
241 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 239 OMAP_PIN_INPUT_PULLUP);
242 240 omap_mux_init_signal("sdmmc1_dat6",
243 if (!c->mmc || c->mmc > nr_hsmmc) { 241 OMAP_PIN_INPUT_PULLUP);
244 pr_debug("MMC%d: no such controller\n", c->mmc); 242 omap_mux_init_signal("sdmmc1_dat7",
245 continue; 243 OMAP_PIN_INPUT_PULLUP);
246 } 244 }
247 if (mmc) {
248 pr_debug("MMC%d: already configured\n", c->mmc);
249 continue;
250 } 245 }
251 246 if (controller_nr == 1) {
252 mmc = kzalloc(sizeof(struct omap_mmc_platform_data), 247 /* MMC2 */
253 GFP_KERNEL); 248 omap_mux_init_signal("sdmmc2_clk",
254 if (!mmc) { 249 OMAP_PIN_INPUT_PULLUP);
255 pr_err("Cannot allocate memory for mmc device!\n"); 250 omap_mux_init_signal("sdmmc2_cmd",
256 goto done; 251 OMAP_PIN_INPUT_PULLUP);
252 omap_mux_init_signal("sdmmc2_dat0",
253 OMAP_PIN_INPUT_PULLUP);
254
255 /*
256 * For 8 wire configurations, Lines DAT4, 5, 6 and 7
257 * need to be muxed in the board-*.c files
258 */
259 if (mmc_controller->slots[0].caps &
260 (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
261 omap_mux_init_signal("sdmmc2_dat1",
262 OMAP_PIN_INPUT_PULLUP);
263 omap_mux_init_signal("sdmmc2_dat2",
264 OMAP_PIN_INPUT_PULLUP);
265 omap_mux_init_signal("sdmmc2_dat3",
266 OMAP_PIN_INPUT_PULLUP);
267 }
268 if (mmc_controller->slots[0].caps &
269 MMC_CAP_8_BIT_DATA) {
270 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
271 OMAP_PIN_INPUT_PULLUP);
272 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
273 OMAP_PIN_INPUT_PULLUP);
274 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
275 OMAP_PIN_INPUT_PULLUP);
276 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
277 OMAP_PIN_INPUT_PULLUP);
278 }
257 } 279 }
258 280
259 if (c->name) 281 /*
260 strncpy(hc->name, c->name, HSMMC_NAME_LEN); 282 * For MMC3 the pins need to be muxed in the board-*.c files
261 else 283 */
262 snprintf(hc->name, ARRAY_SIZE(hc->name), 284 }
263 "mmc%islot%i", c->mmc, 1); 285}
264 mmc->slots[0].name = hc->name;
265 mmc->nr_slots = 1;
266 mmc->slots[0].caps = c->caps;
267 mmc->slots[0].internal_clock = !c->ext_clock;
268 mmc->dma_mask = 0xffffffff;
269 if (cpu_is_omap44xx())
270 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
271 else
272 mmc->reg_offset = 0;
273 286
274 mmc->get_context_loss_count = hsmmc_get_context_loss; 287static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
288 struct omap_mmc_platform_data *mmc)
289{
290 char *hc_name;
275 291
276 mmc->slots[0].switch_pin = c->gpio_cd; 292 hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
277 mmc->slots[0].gpio_wp = c->gpio_wp; 293 if (!hc_name) {
294 pr_err("Cannot allocate memory for controller slot name\n");
295 kfree(hc_name);
296 return -ENOMEM;
297 }
278 298
279 mmc->slots[0].remux = c->remux; 299 if (c->name)
280 mmc->slots[0].init_card = c->init_card; 300 strncpy(hc_name, c->name, HSMMC_NAME_LEN);
301 else
302 snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
303 c->mmc, 1);
304 mmc->slots[0].name = hc_name;
305 mmc->nr_slots = 1;
306 mmc->slots[0].caps = c->caps;
307 mmc->slots[0].internal_clock = !c->ext_clock;
308 mmc->dma_mask = 0xffffffff;
309 if (cpu_is_omap44xx())
310 mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
311 else
312 mmc->reg_offset = 0;
281 313
282 if (c->cover_only) 314 mmc->get_context_loss_count = hsmmc_get_context_loss;
283 mmc->slots[0].cover = 1;
284 315
285 if (c->nonremovable) 316 mmc->slots[0].switch_pin = c->gpio_cd;
286 mmc->slots[0].nonremovable = 1; 317 mmc->slots[0].gpio_wp = c->gpio_wp;
287 318
288 if (c->power_saving) 319 mmc->slots[0].remux = c->remux;
289 mmc->slots[0].power_saving = 1; 320 mmc->slots[0].init_card = c->init_card;
290 321
291 if (c->no_off) 322 if (c->cover_only)
292 mmc->slots[0].no_off = 1; 323 mmc->slots[0].cover = 1;
293 324
294 if (c->vcc_aux_disable_is_sleep) 325 if (c->nonremovable)
295 mmc->slots[0].vcc_aux_disable_is_sleep = 1; 326 mmc->slots[0].nonremovable = 1;
296 327
297 /* NOTE: MMC slots should have a Vcc regulator set up. 328 if (c->power_saving)
298 * This may be from a TWL4030-family chip, another 329 mmc->slots[0].power_saving = 1;
299 * controllable regulator, or a fixed supply.
300 *
301 * temporary HACK: ocr_mask instead of fixed supply
302 */
303 mmc->slots[0].ocr_mask = c->ocr_mask;
304 330
305 if (cpu_is_omap3517() || cpu_is_omap3505()) 331 if (c->no_off)
306 mmc->slots[0].set_power = nop_mmc_set_power; 332 mmc->slots[0].no_off = 1;
307 else
308 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
309 333
310 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0)) 334 if (c->vcc_aux_disable_is_sleep)
311 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 335 mmc->slots[0].vcc_aux_disable_is_sleep = 1;
312 336
313 switch (c->mmc) { 337 /*
314 case 1: 338 * NOTE: MMC slots should have a Vcc regulator set up.
315 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 339 * This may be from a TWL4030-family chip, another
316 /* on-chip level shifting via PBIAS0/PBIAS1 */ 340 * controllable regulator, or a fixed supply.
317 if (cpu_is_omap44xx()) { 341 *
318 mmc->slots[0].before_set_reg = 342 * temporary HACK: ocr_mask instead of fixed supply
343 */
344 mmc->slots[0].ocr_mask = c->ocr_mask;
345
346 if (cpu_is_omap3517() || cpu_is_omap3505())
347 mmc->slots[0].set_power = nop_mmc_set_power;
348 else
349 mmc->slots[0].features |= HSMMC_HAS_PBIAS;
350
351 if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
352 mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
353
354 switch (c->mmc) {
355 case 1:
356 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
357 /* on-chip level shifting via PBIAS0/PBIAS1 */
358 if (cpu_is_omap44xx()) {
359 mmc->slots[0].before_set_reg =
319 omap4_hsmmc1_before_set_reg; 360 omap4_hsmmc1_before_set_reg;
320 mmc->slots[0].after_set_reg = 361 mmc->slots[0].after_set_reg =
321 omap4_hsmmc1_after_set_reg; 362 omap4_hsmmc1_after_set_reg;
322 } else { 363 } else {
323 mmc->slots[0].before_set_reg = 364 mmc->slots[0].before_set_reg =
324 omap_hsmmc1_before_set_reg; 365 omap_hsmmc1_before_set_reg;
325 mmc->slots[0].after_set_reg = 366 mmc->slots[0].after_set_reg =
326 omap_hsmmc1_after_set_reg; 367 omap_hsmmc1_after_set_reg;
327 }
328 } 368 }
369 }
329 370
330 /* Omap3630 HSMMC1 supports only 4-bit */ 371 /* OMAP3630 HSMMC1 supports only 4-bit */
331 if (cpu_is_omap3630() && 372 if (cpu_is_omap3630() &&
332 (c->caps & MMC_CAP_8_BIT_DATA)) { 373 (c->caps & MMC_CAP_8_BIT_DATA)) {
333 c->caps &= ~MMC_CAP_8_BIT_DATA; 374 c->caps &= ~MMC_CAP_8_BIT_DATA;
334 c->caps |= MMC_CAP_4_BIT_DATA; 375 c->caps |= MMC_CAP_4_BIT_DATA;
335 mmc->slots[0].caps = c->caps; 376 mmc->slots[0].caps = c->caps;
336 } 377 }
337 break; 378 break;
338 case 2: 379 case 2:
339 if (c->ext_clock) 380 if (c->ext_clock)
340 c->transceiver = 1; 381 c->transceiver = 1;
341 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) { 382 if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
342 c->caps &= ~MMC_CAP_8_BIT_DATA; 383 c->caps &= ~MMC_CAP_8_BIT_DATA;
343 c->caps |= MMC_CAP_4_BIT_DATA; 384 c->caps |= MMC_CAP_4_BIT_DATA;
344 } 385 }
345 /* FALLTHROUGH */ 386 /* FALLTHROUGH */
346 case 3: 387 case 3:
347 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) { 388 if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
348 /* off-chip level shifting, or none */ 389 /* off-chip level shifting, or none */
349 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg; 390 mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
350 mmc->slots[0].after_set_reg = NULL;
351 }
352 break;
353 case 4:
354 case 5:
355 mmc->slots[0].before_set_reg = NULL;
356 mmc->slots[0].after_set_reg = NULL; 391 mmc->slots[0].after_set_reg = NULL;
357 break;
358 default:
359 pr_err("MMC%d configuration not supported!\n", c->mmc);
360 kfree(mmc);
361 continue;
362 } 392 }
363 hsmmc_data[c->mmc - 1] = mmc; 393 break;
394 case 4:
395 case 5:
396 mmc->slots[0].before_set_reg = NULL;
397 mmc->slots[0].after_set_reg = NULL;
398 break;
399 default:
400 pr_err("MMC%d configuration not supported!\n", c->mmc);
401 kfree(hc_name);
402 return -ENODEV;
403 }
404 return 0;
405}
406
407static struct omap_device_pm_latency omap_hsmmc_latency[] = {
408 [0] = {
409 .deactivate_func = omap_device_idle_hwmods,
410 .activate_func = omap_device_enable_hwmods,
411 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
412 },
413 /*
414 * XXX There should also be an entry here to power off/on the
415 * MMC regulators/PBIAS cells, etc.
416 */
417};
418
419#define MAX_OMAP_MMC_HWMOD_NAME_LEN 16
420
421void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
422{
423 struct omap_hwmod *oh;
424 struct omap_device *od;
425 struct omap_device_pm_latency *ohl;
426 char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
427 struct omap_mmc_platform_data *mmc_data;
428 struct omap_mmc_dev_attr *mmc_dev_attr;
429 char *name;
430 int l;
431 int ohl_cnt = 0;
432
433 mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
434 if (!mmc_data) {
435 pr_err("Cannot allocate memory for mmc device!\n");
436 goto done;
364 } 437 }
365 438
366 omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); 439 if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
440 pr_err("%s fails!\n", __func__);
441 goto done;
442 }
443 omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
444
445 name = "omap_hsmmc";
446 ohl = omap_hsmmc_latency;
447 ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
448
449 l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
450 "mmc%d", ctrl_nr);
451 WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
452 "String buffer overflow in MMC%d device setup\n", ctrl_nr);
453 oh = omap_hwmod_lookup(oh_name);
454 if (!oh) {
455 pr_err("Could not look up %s\n", oh_name);
456 kfree(mmc_data->slots[0].name);
457 goto done;
458 }
367 459
368 /* pass the device nodes back to board setup code */ 460 if (oh->dev_attr != NULL) {
369 for (c = controllers; c->mmc; c++) { 461 mmc_dev_attr = oh->dev_attr;
370 struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; 462 mmc_data->controller_flags = mmc_dev_attr->flags;
463 }
371 464
372 if (!c->mmc || c->mmc > nr_hsmmc) 465 od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
373 continue; 466 sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
374 c->dev = mmc->dev; 467 if (IS_ERR(od)) {
468 WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
469 kfree(mmc_data->slots[0].name);
470 goto done;
375 } 471 }
472 /*
473 * return device handle to board setup code
474 * required to populate for regulator framework structure
475 */
476 hsmmcinfo->dev = &od->pdev.dev;
376 477
377done: 478done:
378 for (i = 0; i < nr_hsmmc; i++) 479 kfree(mmc_data);
379 kfree(hsmmc_data[i]); 480}
481
482void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
483{
484 u32 reg;
485
486 if (!cpu_is_omap44xx()) {
487 if (cpu_is_omap2430()) {
488 control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
489 control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
490 } else {
491 control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
492 control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
493 }
494 } else {
495 control_pbias_offset =
496 OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
497 control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
498 reg = omap4_ctrl_pad_readl(control_mmc1);
499 reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
500 OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
501 reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
502 OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
503 reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
504 OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
505 OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
506 omap4_ctrl_pad_writel(reg, control_mmc1);
507 }
508
509 for (; controllers->mmc; controllers++)
510 omap_init_hsmmc(controllers, controllers->mmc);
511
380} 512}
381 513
382#endif 514#endif
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 14ee686b6492..adb083e41acd 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -145,35 +145,32 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
145 145
146static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra) 146static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
147{ 147{
148 int i;
149 u32 stat, da; 148 u32 stat, da;
150 const char *err_msg[] = { 149 u32 errs = 0;
151 "tlb miss",
152 "translation fault",
153 "emulation miss",
154 "table walk fault",
155 "multi hit fault",
156 };
157 150
158 stat = iommu_read_reg(obj, MMU_IRQSTATUS); 151 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
159 stat &= MMU_IRQ_MASK; 152 stat &= MMU_IRQ_MASK;
160 if (!stat) 153 if (!stat) {
154 *ra = 0;
161 return 0; 155 return 0;
156 }
162 157
163 da = iommu_read_reg(obj, MMU_FAULT_AD); 158 da = iommu_read_reg(obj, MMU_FAULT_AD);
164 *ra = da; 159 *ra = da;
165 160
166 dev_err(obj->dev, "%s:\tda:%08x ", __func__, da); 161 if (stat & MMU_IRQ_TLBMISS)
167 162 errs |= OMAP_IOMMU_ERR_TLB_MISS;
168 for (i = 0; i < ARRAY_SIZE(err_msg); i++) { 163 if (stat & MMU_IRQ_TRANSLATIONFAULT)
169 if (stat & (1 << i)) 164 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
170 printk("%s ", err_msg[i]); 165 if (stat & MMU_IRQ_EMUMISS)
171 } 166 errs |= OMAP_IOMMU_ERR_EMU_MISS;
172 printk("\n"); 167 if (stat & MMU_IRQ_TABLEWALKFAULT)
173 168 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
169 if (stat & MMU_IRQ_MULTIHITFAULT)
170 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
174 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 171 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
175 172
176 return stat; 173 return errs;
177} 174}
178 175
179static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr) 176static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 537d3484b475..6e15e3d7c65e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/pm_runtime.h>
17#include <plat/mailbox.h> 18#include <plat/mailbox.h>
18#include <mach/irqs.h> 19#include <mach/irqs.h>
19 20
20#define MAILBOX_REVISION 0x000 21#define MAILBOX_REVISION 0x000
21#define MAILBOX_SYSCONFIG 0x010
22#define MAILBOX_SYSSTATUS 0x014
23#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) 22#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
24#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) 23#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
25#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) 24#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
33#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m))) 32#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
34#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1)) 33#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
35 34
36/* SYSCONFIG: register bit definition */
37#define AUTOIDLE (1 << 0)
38#define SOFTRESET (1 << 1)
39#define SMARTIDLE (2 << 3)
40#define OMAP4_SOFTRESET (1 << 0)
41#define OMAP4_NOIDLE (1 << 2)
42#define OMAP4_SMARTIDLE (2 << 2)
43
44/* SYSSTATUS: register bit definition */
45#define RESETDONE (1 << 0)
46
47#define MBOX_REG_SIZE 0x120 35#define MBOX_REG_SIZE 0x120
48 36
49#define OMAP4_MBOX_REG_SIZE 0x130 37#define OMAP4_MBOX_REG_SIZE 0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
70 unsigned long irqdisable; 58 unsigned long irqdisable;
71}; 59};
72 60
73static struct clk *mbox_ick_handle;
74
75static void omap2_mbox_enable_irq(struct omap_mbox *mbox, 61static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
76 omap_mbox_type_t irq); 62 omap_mbox_type_t irq);
77 63
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
89static int omap2_mbox_startup(struct omap_mbox *mbox) 75static int omap2_mbox_startup(struct omap_mbox *mbox)
90{ 76{
91 u32 l; 77 u32 l;
92 unsigned long timeout;
93 78
94 mbox_ick_handle = clk_get(NULL, "mailboxes_ick"); 79 pm_runtime_enable(mbox->dev->parent);
95 if (IS_ERR(mbox_ick_handle)) { 80 pm_runtime_get_sync(mbox->dev->parent);
96 printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
97 PTR_ERR(mbox_ick_handle));
98 return PTR_ERR(mbox_ick_handle);
99 }
100 clk_enable(mbox_ick_handle);
101
102 if (cpu_is_omap44xx()) {
103 mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
104 timeout = jiffies + msecs_to_jiffies(20);
105 do {
106 l = mbox_read_reg(MAILBOX_SYSCONFIG);
107 if (!(l & OMAP4_SOFTRESET))
108 break;
109 } while (!time_after(jiffies, timeout));
110
111 if (l & OMAP4_SOFTRESET) {
112 pr_err("Can't take mailbox out of reset\n");
113 return -ENODEV;
114 }
115 } else {
116 mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
117 timeout = jiffies + msecs_to_jiffies(20);
118 do {
119 l = mbox_read_reg(MAILBOX_SYSSTATUS);
120 if (l & RESETDONE)
121 break;
122 } while (!time_after(jiffies, timeout));
123
124 if (!(l & RESETDONE)) {
125 pr_err("Can't take mailbox out of reset\n");
126 return -ENODEV;
127 }
128 }
129 81
130 l = mbox_read_reg(MAILBOX_REVISION); 82 l = mbox_read_reg(MAILBOX_REVISION);
131 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); 83 pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
132 84
133 if (cpu_is_omap44xx())
134 l = OMAP4_SMARTIDLE;
135 else
136 l = SMARTIDLE | AUTOIDLE;
137 mbox_write_reg(l, MAILBOX_SYSCONFIG);
138
139 omap2_mbox_enable_irq(mbox, IRQ_RX); 85 omap2_mbox_enable_irq(mbox, IRQ_RX);
140 86
141 return 0; 87 return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
143 89
144static void omap2_mbox_shutdown(struct omap_mbox *mbox) 90static void omap2_mbox_shutdown(struct omap_mbox *mbox)
145{ 91{
146 clk_disable(mbox_ick_handle); 92 pm_runtime_put_sync(mbox->dev->parent);
147 clk_put(mbox_ick_handle); 93 pm_runtime_disable(mbox->dev->parent);
148 mbox_ick_handle = NULL;
149} 94}
150 95
151/* Mailbox FIFO handle functions */ 96/* Mailbox FIFO handle functions */
@@ -398,14 +343,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
398 else if (cpu_is_omap34xx()) { 343 else if (cpu_is_omap34xx()) {
399 list = omap3_mboxes; 344 list = omap3_mboxes;
400 345
401 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); 346 list[0]->irq = platform_get_irq(pdev, 0);
402 } 347 }
403#endif 348#endif
404#if defined(CONFIG_ARCH_OMAP2) 349#if defined(CONFIG_ARCH_OMAP2)
405 else if (cpu_is_omap2430()) { 350 else if (cpu_is_omap2430()) {
406 list = omap2_mboxes; 351 list = omap2_mboxes;
407 352
408 list[0]->irq = platform_get_irq_byname(pdev, "dsp"); 353 list[0]->irq = platform_get_irq(pdev, 0);
409 } else if (cpu_is_omap2420()) { 354 } else if (cpu_is_omap2420()) {
410 list = omap2_mboxes; 355 list = omap2_mboxes;
411 356
@@ -417,8 +362,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
417 else if (cpu_is_omap44xx()) { 362 else if (cpu_is_omap44xx()) {
418 list = omap4_mboxes; 363 list = omap4_mboxes;
419 364
420 list[0]->irq = list[1]->irq = 365 list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
421 platform_get_irq_byname(pdev, "mbox");
422 } 366 }
423#endif 367#endif
424 else { 368 else {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 0526b758bdcc..565b9064a328 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,10 +22,11 @@
22#include <plat/dma.h> 22#include <plat/dma.h>
23#include <plat/cpu.h> 23#include <plat/cpu.h>
24#include <plat/mcbsp.h> 24#include <plat/mcbsp.h>
25#include <plat/omap_device.h>
26#include <linux/pm_runtime.h>
25 27
26#include "control.h" 28#include "control.h"
27 29
28
29/* McBSP internal signal muxing functions */ 30/* McBSP internal signal muxing functions */
30 31
31void omap2_mcbsp1_mux_clkr_src(u8 mux) 32void omap2_mcbsp1_mux_clkr_src(u8 mux)
@@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
83 return -EINVAL; 84 return -EINVAL;
84 } 85 }
85 86
86 clk_disable(mcbsp->fclk); 87 pm_runtime_put_sync(mcbsp->dev);
87 88
88 r = clk_set_parent(mcbsp->fclk, fck_src); 89 r = clk_set_parent(mcbsp->fclk, fck_src);
89 if (IS_ERR_VALUE(r)) { 90 if (IS_ERR_VALUE(r)) {
@@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
93 return -EINVAL; 94 return -EINVAL;
94 } 95 }
95 96
96 clk_enable(mcbsp->fclk); 97 pm_runtime_get_sync(mcbsp->dev);
97 98
98 clk_put(fck_src); 99 clk_put(fck_src);
99 100
@@ -101,196 +102,70 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
101} 102}
102EXPORT_SYMBOL(omap2_mcbsp_set_clks_src); 103EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
103 104
104 105struct omap_device_pm_latency omap2_mcbsp_latency[] = {
105/* Platform data */
106
107#ifdef CONFIG_SOC_OMAP2420
108static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
109 { 106 {
110 .phys_base = OMAP24XX_MCBSP1_BASE, 107 .deactivate_func = omap_device_idle_hwmods,
111 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 108 .activate_func = omap_device_enable_hwmods,
112 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 109 .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
113 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
114 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
115 },
116 {
117 .phys_base = OMAP24XX_MCBSP2_BASE,
118 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
119 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
120 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
121 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
122 }, 110 },
123}; 111};
124#define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata)
125#define OMAP2420_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
126#else
127#define omap2420_mcbsp_pdata NULL
128#define OMAP2420_MCBSP_PDATA_SZ 0
129#define OMAP2420_MCBSP_REG_NUM 0
130#endif
131 112
132#ifdef CONFIG_SOC_OMAP2430 113static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
133static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { 114{
134 { 115 int id, count = 1;
135 .phys_base = OMAP24XX_MCBSP1_BASE, 116 char *name = "omap-mcbsp";
136 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX, 117 struct omap_hwmod *oh_device[2];
137 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX, 118 struct omap_mcbsp_platform_data *pdata = NULL;
138 .rx_irq = INT_24XX_MCBSP1_IRQ_RX, 119 struct omap_device *od;
139 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
140 },
141 {
142 .phys_base = OMAP24XX_MCBSP2_BASE,
143 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
144 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
145 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
146 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
147 },
148 {
149 .phys_base = OMAP2430_MCBSP3_BASE,
150 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
151 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
152 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
153 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
154 },
155 {
156 .phys_base = OMAP2430_MCBSP4_BASE,
157 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
158 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
159 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
160 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
161 },
162 {
163 .phys_base = OMAP2430_MCBSP5_BASE,
164 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
165 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
166 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
167 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
168 },
169};
170#define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata)
171#define OMAP2430_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
172#else
173#define omap2430_mcbsp_pdata NULL
174#define OMAP2430_MCBSP_PDATA_SZ 0
175#define OMAP2430_MCBSP_REG_NUM 0
176#endif
177 120
178#ifdef CONFIG_ARCH_OMAP3 121 sscanf(oh->name, "mcbsp%d", &id);
179static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
180 {
181 .phys_base = OMAP34XX_MCBSP1_BASE,
182 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
183 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
184 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
185 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
186 .buffer_size = 0x80, /* The FIFO has 128 locations */
187 },
188 {
189 .phys_base = OMAP34XX_MCBSP2_BASE,
190 .phys_base_st = OMAP34XX_MCBSP2_ST_BASE,
191 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
192 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
193 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
194 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
195 .buffer_size = 0x500, /* The FIFO has 1024 + 256 locations */
196 },
197 {
198 .phys_base = OMAP34XX_MCBSP3_BASE,
199 .phys_base_st = OMAP34XX_MCBSP3_ST_BASE,
200 .dma_rx_sync = OMAP24XX_DMA_MCBSP3_RX,
201 .dma_tx_sync = OMAP24XX_DMA_MCBSP3_TX,
202 .rx_irq = INT_24XX_MCBSP3_IRQ_RX,
203 .tx_irq = INT_24XX_MCBSP3_IRQ_TX,
204 .buffer_size = 0x80, /* The FIFO has 128 locations */
205 },
206 {
207 .phys_base = OMAP34XX_MCBSP4_BASE,
208 .dma_rx_sync = OMAP24XX_DMA_MCBSP4_RX,
209 .dma_tx_sync = OMAP24XX_DMA_MCBSP4_TX,
210 .rx_irq = INT_24XX_MCBSP4_IRQ_RX,
211 .tx_irq = INT_24XX_MCBSP4_IRQ_TX,
212 .buffer_size = 0x80, /* The FIFO has 128 locations */
213 },
214 {
215 .phys_base = OMAP34XX_MCBSP5_BASE,
216 .dma_rx_sync = OMAP24XX_DMA_MCBSP5_RX,
217 .dma_tx_sync = OMAP24XX_DMA_MCBSP5_TX,
218 .rx_irq = INT_24XX_MCBSP5_IRQ_RX,
219 .tx_irq = INT_24XX_MCBSP5_IRQ_TX,
220 .buffer_size = 0x80, /* The FIFO has 128 locations */
221 },
222};
223#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
224#define OMAP34XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
225#else
226#define omap34xx_mcbsp_pdata NULL
227#define OMAP34XX_MCBSP_PDATA_SZ 0
228#define OMAP34XX_MCBSP_REG_NUM 0
229#endif
230 122
231static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = { 123 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
232 { 124 if (!pdata) {
233 .phys_base = OMAP44XX_MCBSP1_BASE, 125 pr_err("%s: No memory for mcbsp\n", __func__);
234 .dma_rx_sync = OMAP44XX_DMA_MCBSP1_RX, 126 return -ENOMEM;
235 .dma_tx_sync = OMAP44XX_DMA_MCBSP1_TX, 127 }
236 .tx_irq = OMAP44XX_IRQ_MCBSP1, 128
237 }, 129 pdata->mcbsp_config_type = oh->class->rev;
238 { 130
239 .phys_base = OMAP44XX_MCBSP2_BASE, 131 if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
240 .dma_rx_sync = OMAP44XX_DMA_MCBSP2_RX, 132 if (id == 2)
241 .dma_tx_sync = OMAP44XX_DMA_MCBSP2_TX, 133 /* The FIFO has 1024 + 256 locations */
242 .tx_irq = OMAP44XX_IRQ_MCBSP2, 134 pdata->buffer_size = 0x500;
243 }, 135 else
244 { 136 /* The FIFO has 128 locations */
245 .phys_base = OMAP44XX_MCBSP3_BASE, 137 pdata->buffer_size = 0x80;
246 .dma_rx_sync = OMAP44XX_DMA_MCBSP3_RX, 138 }
247 .dma_tx_sync = OMAP44XX_DMA_MCBSP3_TX, 139
248 .tx_irq = OMAP44XX_IRQ_MCBSP3, 140 oh_device[0] = oh;
249 }, 141
250 { 142 if (oh->dev_attr) {
251 .phys_base = OMAP44XX_MCBSP4_BASE, 143 oh_device[1] = omap_hwmod_lookup((
252 .dma_rx_sync = OMAP44XX_DMA_MCBSP4_RX, 144 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
253 .dma_tx_sync = OMAP44XX_DMA_MCBSP4_TX, 145 count++;
254 .tx_irq = OMAP44XX_IRQ_MCBSP4, 146 }
255 }, 147 od = omap_device_build_ss(name, id, oh_device, count, pdata,
256}; 148 sizeof(*pdata), omap2_mcbsp_latency,
257#define OMAP44XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap44xx_mcbsp_pdata) 149 ARRAY_SIZE(omap2_mcbsp_latency), false);
258#define OMAP44XX_MCBSP_REG_NUM (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1) 150 kfree(pdata);
151 if (IS_ERR(od)) {
152 pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
153 name, oh->name);
154 return PTR_ERR(od);
155 }
156 omap_mcbsp_count++;
157 return 0;
158}
259 159
260static int __init omap2_mcbsp_init(void) 160static int __init omap2_mcbsp_init(void)
261{ 161{
262 if (cpu_is_omap2420()) { 162 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
263 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
264 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
265 } else if (cpu_is_omap2430()) {
266 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
267 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
268 } else if (cpu_is_omap34xx()) {
269 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
270 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
271 } else if (cpu_is_omap44xx()) {
272 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
273 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
274 }
275 163
276 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *), 164 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
277 GFP_KERNEL); 165 GFP_KERNEL);
278 if (!mcbsp_ptr) 166 if (!mcbsp_ptr)
279 return -ENOMEM; 167 return -ENOMEM;
280 168
281 if (cpu_is_omap2420())
282 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
283 OMAP2420_MCBSP_PDATA_SZ);
284 if (cpu_is_omap2430())
285 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
286 OMAP2430_MCBSP_PDATA_SZ);
287 if (cpu_is_omap34xx())
288 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
289 OMAP34XX_MCBSP_PDATA_SZ);
290 if (cpu_is_omap44xx())
291 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
292 OMAP44XX_MCBSP_PDATA_SZ);
293
294 return omap_mcbsp_init(); 169 return omap_mcbsp_init();
295} 170}
296arch_initcall(omap2_mcbsp_init); 171arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index f76f133780c8..1125134c9a7f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1929,6 +1929,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
1929 os = oh->slaves[i]; 1929 os = oh->slaves[i];
1930 1930
1931 for (j = 0; j < os->addr_cnt; j++) { 1931 for (j = 0; j < os->addr_cnt; j++) {
1932 (res + r)->name = (os->addr + j)->name;
1932 (res + r)->start = (os->addr + j)->pa_start; 1933 (res + r)->start = (os->addr + j)->pa_start;
1933 (res + r)->end = (os->addr + j)->pa_end; 1934 (res + r)->end = (os->addr + j)->pa_end;
1934 (res + r)->flags = IORESOURCE_MEM; 1935 (res + r)->flags = IORESOURCE_MEM;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index e58621aa9b34..e0bc2c7a15de 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -110,6 +110,8 @@ static struct omap_hwmod omap2420_uart2_hwmod;
110static struct omap_hwmod omap2420_uart3_hwmod; 110static struct omap_hwmod omap2420_uart3_hwmod;
111static struct omap_hwmod omap2420_i2c1_hwmod; 111static struct omap_hwmod omap2420_i2c1_hwmod;
112static struct omap_hwmod omap2420_i2c2_hwmod; 112static struct omap_hwmod omap2420_i2c2_hwmod;
113static struct omap_hwmod omap2420_mcbsp1_hwmod;
114static struct omap_hwmod omap2420_mcbsp2_hwmod;
113 115
114/* l4 core -> mcspi1 interface */ 116/* l4 core -> mcspi1 interface */
115static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = { 117static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
@@ -1828,6 +1830,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
1828}; 1830};
1829 1831
1830/* 1832/*
1833 * 'mailbox' class
1834 * mailbox module allowing communication between the on-chip processors
1835 * using a queued mailbox-interrupt mechanism.
1836 */
1837
1838static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
1839 .rev_offs = 0x000,
1840 .sysc_offs = 0x010,
1841 .syss_offs = 0x014,
1842 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1843 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1844 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1845 .sysc_fields = &omap_hwmod_sysc_type1,
1846};
1847
1848static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
1849 .name = "mailbox",
1850 .sysc = &omap2420_mailbox_sysc,
1851};
1852
1853/* mailbox */
1854static struct omap_hwmod omap2420_mailbox_hwmod;
1855static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
1856 { .name = "dsp", .irq = 26 },
1857 { .name = "iva", .irq = 34 },
1858};
1859
1860static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
1861 {
1862 .pa_start = 0x48094000,
1863 .pa_end = 0x480941ff,
1864 .flags = ADDR_TYPE_RT,
1865 },
1866};
1867
1868/* l4_core -> mailbox */
1869static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
1870 .master = &omap2420_l4_core_hwmod,
1871 .slave = &omap2420_mailbox_hwmod,
1872 .addr = omap2420_mailbox_addrs,
1873 .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
1874 .user = OCP_USER_MPU | OCP_USER_SDMA,
1875};
1876
1877/* mailbox slave ports */
1878static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
1879 &omap2420_l4_core__mailbox,
1880};
1881
1882static struct omap_hwmod omap2420_mailbox_hwmod = {
1883 .name = "mailbox",
1884 .class = &omap2420_mailbox_hwmod_class,
1885 .mpu_irqs = omap2420_mailbox_irqs,
1886 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
1887 .main_clk = "mailboxes_ick",
1888 .prcm = {
1889 .omap2 = {
1890 .prcm_reg_id = 1,
1891 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1892 .module_offs = CORE_MOD,
1893 .idlest_reg_id = 1,
1894 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
1895 },
1896 },
1897 .slaves = omap2420_mailbox_slaves,
1898 .slaves_cnt = ARRAY_SIZE(omap2420_mailbox_slaves),
1899 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1900};
1901
1902/*
1831 * 'mcspi' class 1903 * 'mcspi' class
1832 * multichannel serial port interface (mcspi) / master/slave synchronous serial 1904 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1833 * bus 1905 * bus
@@ -1940,6 +2012,129 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
1940 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), 2012 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
1941}; 2013};
1942 2014
2015/*
2016 * 'mcbsp' class
2017 * multi channel buffered serial port controller
2018 */
2019
2020static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
2021 .name = "mcbsp",
2022};
2023
2024/* mcbsp1 */
2025static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
2026 { .name = "tx", .irq = 59 },
2027 { .name = "rx", .irq = 60 },
2028};
2029
2030static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
2031 { .name = "rx", .dma_req = 32 },
2032 { .name = "tx", .dma_req = 31 },
2033};
2034
2035static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
2036 {
2037 .name = "mpu",
2038 .pa_start = 0x48074000,
2039 .pa_end = 0x480740ff,
2040 .flags = ADDR_TYPE_RT
2041 },
2042};
2043
2044/* l4_core -> mcbsp1 */
2045static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
2046 .master = &omap2420_l4_core_hwmod,
2047 .slave = &omap2420_mcbsp1_hwmod,
2048 .clk = "mcbsp1_ick",
2049 .addr = omap2420_mcbsp1_addrs,
2050 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
2051 .user = OCP_USER_MPU | OCP_USER_SDMA,
2052};
2053
2054/* mcbsp1 slave ports */
2055static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
2056 &omap2420_l4_core__mcbsp1,
2057};
2058
2059static struct omap_hwmod omap2420_mcbsp1_hwmod = {
2060 .name = "mcbsp1",
2061 .class = &omap2420_mcbsp_hwmod_class,
2062 .mpu_irqs = omap2420_mcbsp1_irqs,
2063 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
2064 .sdma_reqs = omap2420_mcbsp1_sdma_chs,
2065 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
2066 .main_clk = "mcbsp1_fck",
2067 .prcm = {
2068 .omap2 = {
2069 .prcm_reg_id = 1,
2070 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2071 .module_offs = CORE_MOD,
2072 .idlest_reg_id = 1,
2073 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2074 },
2075 },
2076 .slaves = omap2420_mcbsp1_slaves,
2077 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp1_slaves),
2078 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2079};
2080
2081/* mcbsp2 */
2082static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
2083 { .name = "tx", .irq = 62 },
2084 { .name = "rx", .irq = 63 },
2085};
2086
2087static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
2088 { .name = "rx", .dma_req = 34 },
2089 { .name = "tx", .dma_req = 33 },
2090};
2091
2092static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
2093 {
2094 .name = "mpu",
2095 .pa_start = 0x48076000,
2096 .pa_end = 0x480760ff,
2097 .flags = ADDR_TYPE_RT
2098 },
2099};
2100
2101/* l4_core -> mcbsp2 */
2102static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
2103 .master = &omap2420_l4_core_hwmod,
2104 .slave = &omap2420_mcbsp2_hwmod,
2105 .clk = "mcbsp2_ick",
2106 .addr = omap2420_mcbsp2_addrs,
2107 .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
2108 .user = OCP_USER_MPU | OCP_USER_SDMA,
2109};
2110
2111/* mcbsp2 slave ports */
2112static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
2113 &omap2420_l4_core__mcbsp2,
2114};
2115
2116static struct omap_hwmod omap2420_mcbsp2_hwmod = {
2117 .name = "mcbsp2",
2118 .class = &omap2420_mcbsp_hwmod_class,
2119 .mpu_irqs = omap2420_mcbsp2_irqs,
2120 .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
2121 .sdma_reqs = omap2420_mcbsp2_sdma_chs,
2122 .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
2123 .main_clk = "mcbsp2_fck",
2124 .prcm = {
2125 .omap2 = {
2126 .prcm_reg_id = 1,
2127 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2128 .module_offs = CORE_MOD,
2129 .idlest_reg_id = 1,
2130 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2131 },
2132 },
2133 .slaves = omap2420_mcbsp2_slaves,
2134 .slaves_cnt = ARRAY_SIZE(omap2420_mcbsp2_slaves),
2135 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
2136};
2137
1943static __initdata struct omap_hwmod *omap2420_hwmods[] = { 2138static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1944 &omap2420_l3_main_hwmod, 2139 &omap2420_l3_main_hwmod,
1945 &omap2420_l4_core_hwmod, 2140 &omap2420_l4_core_hwmod,
@@ -1982,6 +2177,13 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
1982 /* dma_system class*/ 2177 /* dma_system class*/
1983 &omap2420_dma_system_hwmod, 2178 &omap2420_dma_system_hwmod,
1984 2179
2180 /* mailbox class */
2181 &omap2420_mailbox_hwmod,
2182
2183 /* mcbsp class */
2184 &omap2420_mcbsp1_hwmod,
2185 &omap2420_mcbsp2_hwmod,
2186
1985 /* mcspi class */ 2187 /* mcspi class */
1986 &omap2420_mcspi1_hwmod, 2188 &omap2420_mcspi1_hwmod,
1987 &omap2420_mcspi2_hwmod, 2189 &omap2420_mcspi2_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index b46a54ce1a41..4aa74d78289c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,8 +18,10 @@
18#include <plat/serial.h> 18#include <plat/serial.h>
19#include <plat/i2c.h> 19#include <plat/i2c.h>
20#include <plat/gpio.h> 20#include <plat/gpio.h>
21#include <plat/mcbsp.h>
21#include <plat/mcspi.h> 22#include <plat/mcspi.h>
22#include <plat/dmtimer.h> 23#include <plat/dmtimer.h>
24#include <plat/mmc.h>
23#include <plat/l3_2xxx.h> 25#include <plat/l3_2xxx.h>
24 26
25#include "omap_hwmod_common_data.h" 27#include "omap_hwmod_common_data.h"
@@ -52,9 +54,16 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
52static struct omap_hwmod omap2430_gpio4_hwmod; 54static struct omap_hwmod omap2430_gpio4_hwmod;
53static struct omap_hwmod omap2430_gpio5_hwmod; 55static struct omap_hwmod omap2430_gpio5_hwmod;
54static struct omap_hwmod omap2430_dma_system_hwmod; 56static struct omap_hwmod omap2430_dma_system_hwmod;
57static struct omap_hwmod omap2430_mcbsp1_hwmod;
58static struct omap_hwmod omap2430_mcbsp2_hwmod;
59static struct omap_hwmod omap2430_mcbsp3_hwmod;
60static struct omap_hwmod omap2430_mcbsp4_hwmod;
61static struct omap_hwmod omap2430_mcbsp5_hwmod;
55static struct omap_hwmod omap2430_mcspi1_hwmod; 62static struct omap_hwmod omap2430_mcspi1_hwmod;
56static struct omap_hwmod omap2430_mcspi2_hwmod; 63static struct omap_hwmod omap2430_mcspi2_hwmod;
57static struct omap_hwmod omap2430_mcspi3_hwmod; 64static struct omap_hwmod omap2430_mcspi3_hwmod;
65static struct omap_hwmod omap2430_mmc1_hwmod;
66static struct omap_hwmod omap2430_mmc2_hwmod;
58 67
59/* L3 -> L4_CORE interface */ 68/* L3 -> L4_CORE interface */
60static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = { 69static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -251,6 +260,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
251 &omap2430_l4_core__usbhsotg, 260 &omap2430_l4_core__usbhsotg,
252}; 261};
253 262
263/* L4 CORE -> MMC1 interface */
264static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
265 {
266 .pa_start = 0x4809c000,
267 .pa_end = 0x4809c1ff,
268 .flags = ADDR_TYPE_RT,
269 },
270};
271
272static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
273 .master = &omap2430_l4_core_hwmod,
274 .slave = &omap2430_mmc1_hwmod,
275 .clk = "mmchs1_ick",
276 .addr = omap2430_mmc1_addr_space,
277 .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
278 .user = OCP_USER_MPU | OCP_USER_SDMA,
279};
280
281/* L4 CORE -> MMC2 interface */
282static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
283 {
284 .pa_start = 0x480b4000,
285 .pa_end = 0x480b41ff,
286 .flags = ADDR_TYPE_RT,
287 },
288};
289
290static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
291 .master = &omap2430_l4_core_hwmod,
292 .slave = &omap2430_mmc2_hwmod,
293 .addr = omap2430_mmc2_addr_space,
294 .clk = "mmchs2_ick",
295 .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
296 .user = OCP_USER_MPU | OCP_USER_SDMA,
297};
298
254/* Slave interfaces on the L4_CORE interconnect */ 299/* Slave interfaces on the L4_CORE interconnect */
255static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = { 300static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
256 &omap2430_l3_main__l4_core, 301 &omap2430_l3_main__l4_core,
@@ -259,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
259/* Master interfaces on the L4_CORE interconnect */ 304/* Master interfaces on the L4_CORE interconnect */
260static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = { 305static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
261 &omap2430_l4_core__l4_wkup, 306 &omap2430_l4_core__l4_wkup,
307 &omap2430_l4_core__mmc1,
308 &omap2430_l4_core__mmc2,
262}; 309};
263 310
264/* L4 CORE */ 311/* L4 CORE */
@@ -1914,6 +1961,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
1914}; 1961};
1915 1962
1916/* 1963/*
1964 * 'mailbox' class
1965 * mailbox module allowing communication between the on-chip processors
1966 * using a queued mailbox-interrupt mechanism.
1967 */
1968
1969static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
1970 .rev_offs = 0x000,
1971 .sysc_offs = 0x010,
1972 .syss_offs = 0x014,
1973 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1974 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1975 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1976 .sysc_fields = &omap_hwmod_sysc_type1,
1977};
1978
1979static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
1980 .name = "mailbox",
1981 .sysc = &omap2430_mailbox_sysc,
1982};
1983
1984/* mailbox */
1985static struct omap_hwmod omap2430_mailbox_hwmod;
1986static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
1987 { .irq = 26 },
1988};
1989
1990static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
1991 {
1992 .pa_start = 0x48094000,
1993 .pa_end = 0x480941ff,
1994 .flags = ADDR_TYPE_RT,
1995 },
1996};
1997
1998/* l4_core -> mailbox */
1999static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
2000 .master = &omap2430_l4_core_hwmod,
2001 .slave = &omap2430_mailbox_hwmod,
2002 .addr = omap2430_mailbox_addrs,
2003 .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
2004 .user = OCP_USER_MPU | OCP_USER_SDMA,
2005};
2006
2007/* mailbox slave ports */
2008static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
2009 &omap2430_l4_core__mailbox,
2010};
2011
2012static struct omap_hwmod omap2430_mailbox_hwmod = {
2013 .name = "mailbox",
2014 .class = &omap2430_mailbox_hwmod_class,
2015 .mpu_irqs = omap2430_mailbox_irqs,
2016 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
2017 .main_clk = "mailboxes_ick",
2018 .prcm = {
2019 .omap2 = {
2020 .prcm_reg_id = 1,
2021 .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
2022 .module_offs = CORE_MOD,
2023 .idlest_reg_id = 1,
2024 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
2025 },
2026 },
2027 .slaves = omap2430_mailbox_slaves,
2028 .slaves_cnt = ARRAY_SIZE(omap2430_mailbox_slaves),
2029 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2030};
2031
2032/*
1917 * 'mcspi' class 2033 * 'mcspi' class
1918 * multichannel serial port interface (mcspi) / master/slave synchronous serial 2034 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1919 * bus 2035 * bus
@@ -2125,7 +2241,425 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
2125 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430) 2241 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
2126}; 2242};
2127 2243
2244/*
2245 * 'mcbsp' class
2246 * multi channel buffered serial port controller
2247 */
2248
2249static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
2250 .rev_offs = 0x007C,
2251 .sysc_offs = 0x008C,
2252 .sysc_flags = (SYSC_HAS_SOFTRESET),
2253 .sysc_fields = &omap_hwmod_sysc_type1,
2254};
2255
2256static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
2257 .name = "mcbsp",
2258 .sysc = &omap2430_mcbsp_sysc,
2259 .rev = MCBSP_CONFIG_TYPE2,
2260};
2128 2261
2262/* mcbsp1 */
2263static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
2264 { .name = "tx", .irq = 59 },
2265 { .name = "rx", .irq = 60 },
2266 { .name = "ovr", .irq = 61 },
2267 { .name = "common", .irq = 64 },
2268};
2269
2270static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
2271 { .name = "rx", .dma_req = 32 },
2272 { .name = "tx", .dma_req = 31 },
2273};
2274
2275static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
2276 {
2277 .name = "mpu",
2278 .pa_start = 0x48074000,
2279 .pa_end = 0x480740ff,
2280 .flags = ADDR_TYPE_RT
2281 },
2282};
2283
2284/* l4_core -> mcbsp1 */
2285static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
2286 .master = &omap2430_l4_core_hwmod,
2287 .slave = &omap2430_mcbsp1_hwmod,
2288 .clk = "mcbsp1_ick",
2289 .addr = omap2430_mcbsp1_addrs,
2290 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292};
2293
2294/* mcbsp1 slave ports */
2295static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
2296 &omap2430_l4_core__mcbsp1,
2297};
2298
2299static struct omap_hwmod omap2430_mcbsp1_hwmod = {
2300 .name = "mcbsp1",
2301 .class = &omap2430_mcbsp_hwmod_class,
2302 .mpu_irqs = omap2430_mcbsp1_irqs,
2303 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
2304 .sdma_reqs = omap2430_mcbsp1_sdma_chs,
2305 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
2306 .main_clk = "mcbsp1_fck",
2307 .prcm = {
2308 .omap2 = {
2309 .prcm_reg_id = 1,
2310 .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
2311 .module_offs = CORE_MOD,
2312 .idlest_reg_id = 1,
2313 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
2314 },
2315 },
2316 .slaves = omap2430_mcbsp1_slaves,
2317 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp1_slaves),
2318 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2319};
2320
2321/* mcbsp2 */
2322static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
2323 { .name = "tx", .irq = 62 },
2324 { .name = "rx", .irq = 63 },
2325 { .name = "common", .irq = 16 },
2326};
2327
2328static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
2329 { .name = "rx", .dma_req = 34 },
2330 { .name = "tx", .dma_req = 33 },
2331};
2332
2333static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
2334 {
2335 .name = "mpu",
2336 .pa_start = 0x48076000,
2337 .pa_end = 0x480760ff,
2338 .flags = ADDR_TYPE_RT
2339 },
2340};
2341
2342/* l4_core -> mcbsp2 */
2343static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
2344 .master = &omap2430_l4_core_hwmod,
2345 .slave = &omap2430_mcbsp2_hwmod,
2346 .clk = "mcbsp2_ick",
2347 .addr = omap2430_mcbsp2_addrs,
2348 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
2349 .user = OCP_USER_MPU | OCP_USER_SDMA,
2350};
2351
2352/* mcbsp2 slave ports */
2353static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
2354 &omap2430_l4_core__mcbsp2,
2355};
2356
2357static struct omap_hwmod omap2430_mcbsp2_hwmod = {
2358 .name = "mcbsp2",
2359 .class = &omap2430_mcbsp_hwmod_class,
2360 .mpu_irqs = omap2430_mcbsp2_irqs,
2361 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
2362 .sdma_reqs = omap2430_mcbsp2_sdma_chs,
2363 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
2364 .main_clk = "mcbsp2_fck",
2365 .prcm = {
2366 .omap2 = {
2367 .prcm_reg_id = 1,
2368 .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
2369 .module_offs = CORE_MOD,
2370 .idlest_reg_id = 1,
2371 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
2372 },
2373 },
2374 .slaves = omap2430_mcbsp2_slaves,
2375 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp2_slaves),
2376 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2377};
2378
2379/* mcbsp3 */
2380static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
2381 { .name = "tx", .irq = 89 },
2382 { .name = "rx", .irq = 90 },
2383 { .name = "common", .irq = 17 },
2384};
2385
2386static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
2387 { .name = "rx", .dma_req = 18 },
2388 { .name = "tx", .dma_req = 17 },
2389};
2390
2391static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
2392 {
2393 .name = "mpu",
2394 .pa_start = 0x4808C000,
2395 .pa_end = 0x4808C0ff,
2396 .flags = ADDR_TYPE_RT
2397 },
2398};
2399
2400/* l4_core -> mcbsp3 */
2401static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
2402 .master = &omap2430_l4_core_hwmod,
2403 .slave = &omap2430_mcbsp3_hwmod,
2404 .clk = "mcbsp3_ick",
2405 .addr = omap2430_mcbsp3_addrs,
2406 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
2407 .user = OCP_USER_MPU | OCP_USER_SDMA,
2408};
2409
2410/* mcbsp3 slave ports */
2411static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
2412 &omap2430_l4_core__mcbsp3,
2413};
2414
2415static struct omap_hwmod omap2430_mcbsp3_hwmod = {
2416 .name = "mcbsp3",
2417 .class = &omap2430_mcbsp_hwmod_class,
2418 .mpu_irqs = omap2430_mcbsp3_irqs,
2419 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
2420 .sdma_reqs = omap2430_mcbsp3_sdma_chs,
2421 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
2422 .main_clk = "mcbsp3_fck",
2423 .prcm = {
2424 .omap2 = {
2425 .prcm_reg_id = 1,
2426 .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
2427 .module_offs = CORE_MOD,
2428 .idlest_reg_id = 2,
2429 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
2430 },
2431 },
2432 .slaves = omap2430_mcbsp3_slaves,
2433 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp3_slaves),
2434 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2435};
2436
2437/* mcbsp4 */
2438static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
2439 { .name = "tx", .irq = 54 },
2440 { .name = "rx", .irq = 55 },
2441 { .name = "common", .irq = 18 },
2442};
2443
2444static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
2445 { .name = "rx", .dma_req = 20 },
2446 { .name = "tx", .dma_req = 19 },
2447};
2448
2449static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
2450 {
2451 .name = "mpu",
2452 .pa_start = 0x4808E000,
2453 .pa_end = 0x4808E0ff,
2454 .flags = ADDR_TYPE_RT
2455 },
2456};
2457
2458/* l4_core -> mcbsp4 */
2459static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
2460 .master = &omap2430_l4_core_hwmod,
2461 .slave = &omap2430_mcbsp4_hwmod,
2462 .clk = "mcbsp4_ick",
2463 .addr = omap2430_mcbsp4_addrs,
2464 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
2465 .user = OCP_USER_MPU | OCP_USER_SDMA,
2466};
2467
2468/* mcbsp4 slave ports */
2469static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
2470 &omap2430_l4_core__mcbsp4,
2471};
2472
2473static struct omap_hwmod omap2430_mcbsp4_hwmod = {
2474 .name = "mcbsp4",
2475 .class = &omap2430_mcbsp_hwmod_class,
2476 .mpu_irqs = omap2430_mcbsp4_irqs,
2477 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
2478 .sdma_reqs = omap2430_mcbsp4_sdma_chs,
2479 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
2480 .main_clk = "mcbsp4_fck",
2481 .prcm = {
2482 .omap2 = {
2483 .prcm_reg_id = 1,
2484 .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
2485 .module_offs = CORE_MOD,
2486 .idlest_reg_id = 2,
2487 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
2488 },
2489 },
2490 .slaves = omap2430_mcbsp4_slaves,
2491 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp4_slaves),
2492 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2493};
2494
2495/* mcbsp5 */
2496static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
2497 { .name = "tx", .irq = 81 },
2498 { .name = "rx", .irq = 82 },
2499 { .name = "common", .irq = 19 },
2500};
2501
2502static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
2503 { .name = "rx", .dma_req = 22 },
2504 { .name = "tx", .dma_req = 21 },
2505};
2506
2507static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
2508 {
2509 .name = "mpu",
2510 .pa_start = 0x48096000,
2511 .pa_end = 0x480960ff,
2512 .flags = ADDR_TYPE_RT
2513 },
2514};
2515
2516/* l4_core -> mcbsp5 */
2517static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
2518 .master = &omap2430_l4_core_hwmod,
2519 .slave = &omap2430_mcbsp5_hwmod,
2520 .clk = "mcbsp5_ick",
2521 .addr = omap2430_mcbsp5_addrs,
2522 .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2524};
2525
2526/* mcbsp5 slave ports */
2527static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
2528 &omap2430_l4_core__mcbsp5,
2529};
2530
2531static struct omap_hwmod omap2430_mcbsp5_hwmod = {
2532 .name = "mcbsp5",
2533 .class = &omap2430_mcbsp_hwmod_class,
2534 .mpu_irqs = omap2430_mcbsp5_irqs,
2535 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
2536 .sdma_reqs = omap2430_mcbsp5_sdma_chs,
2537 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
2538 .main_clk = "mcbsp5_fck",
2539 .prcm = {
2540 .omap2 = {
2541 .prcm_reg_id = 1,
2542 .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
2543 .module_offs = CORE_MOD,
2544 .idlest_reg_id = 2,
2545 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
2546 },
2547 },
2548 .slaves = omap2430_mcbsp5_slaves,
2549 .slaves_cnt = ARRAY_SIZE(omap2430_mcbsp5_slaves),
2550 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2551};
2552
2553/* MMC/SD/SDIO common */
2554
2555static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
2556 .rev_offs = 0x1fc,
2557 .sysc_offs = 0x10,
2558 .syss_offs = 0x14,
2559 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2560 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2561 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
2562 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2563 .sysc_fields = &omap_hwmod_sysc_type1,
2564};
2565
2566static struct omap_hwmod_class omap2430_mmc_class = {
2567 .name = "mmc",
2568 .sysc = &omap2430_mmc_sysc,
2569};
2570
2571/* MMC/SD/SDIO1 */
2572
2573static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
2574 { .irq = 83 },
2575};
2576
2577static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
2578 { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
2579 { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
2580};
2581
2582static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
2583 { .role = "dbck", .clk = "mmchsdb1_fck" },
2584};
2585
2586static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
2587 &omap2430_l4_core__mmc1,
2588};
2589
2590static struct omap_mmc_dev_attr mmc1_dev_attr = {
2591 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
2592};
2593
2594static struct omap_hwmod omap2430_mmc1_hwmod = {
2595 .name = "mmc1",
2596 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2597 .mpu_irqs = omap2430_mmc1_mpu_irqs,
2598 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
2599 .sdma_reqs = omap2430_mmc1_sdma_reqs,
2600 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
2601 .opt_clks = omap2430_mmc1_opt_clks,
2602 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
2603 .main_clk = "mmchs1_fck",
2604 .prcm = {
2605 .omap2 = {
2606 .module_offs = CORE_MOD,
2607 .prcm_reg_id = 2,
2608 .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
2609 .idlest_reg_id = 2,
2610 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
2611 },
2612 },
2613 .dev_attr = &mmc1_dev_attr,
2614 .slaves = omap2430_mmc1_slaves,
2615 .slaves_cnt = ARRAY_SIZE(omap2430_mmc1_slaves),
2616 .class = &omap2430_mmc_class,
2617 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2618};
2619
2620/* MMC/SD/SDIO2 */
2621
2622static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
2623 { .irq = 86 },
2624};
2625
2626static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
2627 { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
2628 { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
2629};
2630
2631static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
2632 { .role = "dbck", .clk = "mmchsdb2_fck" },
2633};
2634
2635static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
2636 &omap2430_l4_core__mmc2,
2637};
2638
2639static struct omap_hwmod omap2430_mmc2_hwmod = {
2640 .name = "mmc2",
2641 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
2642 .mpu_irqs = omap2430_mmc2_mpu_irqs,
2643 .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
2644 .sdma_reqs = omap2430_mmc2_sdma_reqs,
2645 .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
2646 .opt_clks = omap2430_mmc2_opt_clks,
2647 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
2648 .main_clk = "mmchs2_fck",
2649 .prcm = {
2650 .omap2 = {
2651 .module_offs = CORE_MOD,
2652 .prcm_reg_id = 2,
2653 .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
2654 .idlest_reg_id = 2,
2655 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
2656 },
2657 },
2658 .slaves = omap2430_mmc2_slaves,
2659 .slaves_cnt = ARRAY_SIZE(omap2430_mmc2_slaves),
2660 .class = &omap2430_mmc_class,
2661 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
2662};
2129 2663
2130static __initdata struct omap_hwmod *omap2430_hwmods[] = { 2664static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2131 &omap2430_l3_main_hwmod, 2665 &omap2430_l3_main_hwmod,
@@ -2159,6 +2693,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2159 /* i2c class */ 2693 /* i2c class */
2160 &omap2430_i2c1_hwmod, 2694 &omap2430_i2c1_hwmod,
2161 &omap2430_i2c2_hwmod, 2695 &omap2430_i2c2_hwmod,
2696 &omap2430_mmc1_hwmod,
2697 &omap2430_mmc2_hwmod,
2162 2698
2163 /* gpio class */ 2699 /* gpio class */
2164 &omap2430_gpio1_hwmod, 2700 &omap2430_gpio1_hwmod,
@@ -2170,6 +2706,16 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
2170 /* dma_system class*/ 2706 /* dma_system class*/
2171 &omap2430_dma_system_hwmod, 2707 &omap2430_dma_system_hwmod,
2172 2708
2709 /* mcbsp class */
2710 &omap2430_mcbsp1_hwmod,
2711 &omap2430_mcbsp2_hwmod,
2712 &omap2430_mcbsp3_hwmod,
2713 &omap2430_mcbsp4_hwmod,
2714 &omap2430_mcbsp5_hwmod,
2715
2716 /* mailbox class */
2717 &omap2430_mailbox_hwmod,
2718
2173 /* mcspi class */ 2719 /* mcspi class */
2174 &omap2430_mcspi1_hwmod, 2720 &omap2430_mcspi1_hwmod,
2175 &omap2430_mcspi2_hwmod, 2721 &omap2430_mcspi2_hwmod,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index fc1b2b963bb9..e2792cf9c54d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,7 +22,9 @@
22#include <plat/l4_3xxx.h> 22#include <plat/l4_3xxx.h>
23#include <plat/i2c.h> 23#include <plat/i2c.h>
24#include <plat/gpio.h> 24#include <plat/gpio.h>
25#include <plat/mmc.h>
25#include <plat/smartreflex.h> 26#include <plat/smartreflex.h>
27#include <plat/mcbsp.h>
26#include <plat/mcspi.h> 28#include <plat/mcspi.h>
27#include <plat/dmtimer.h> 29#include <plat/dmtimer.h>
28 30
@@ -69,10 +71,21 @@ static struct omap_hwmod omap34xx_mcspi1;
69static struct omap_hwmod omap34xx_mcspi2; 71static struct omap_hwmod omap34xx_mcspi2;
70static struct omap_hwmod omap34xx_mcspi3; 72static struct omap_hwmod omap34xx_mcspi3;
71static struct omap_hwmod omap34xx_mcspi4; 73static struct omap_hwmod omap34xx_mcspi4;
74static struct omap_hwmod omap3xxx_mmc1_hwmod;
75static struct omap_hwmod omap3xxx_mmc2_hwmod;
76static struct omap_hwmod omap3xxx_mmc3_hwmod;
72static struct omap_hwmod am35xx_usbhsotg_hwmod; 77static struct omap_hwmod am35xx_usbhsotg_hwmod;
73 78
74static struct omap_hwmod omap3xxx_dma_system_hwmod; 79static struct omap_hwmod omap3xxx_dma_system_hwmod;
75 80
81static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
82static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
83static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
84static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
85static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
86static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
87static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
88
76/* L3 -> L4_CORE interface */ 89/* L3 -> L4_CORE interface */
77static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { 90static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
78 .master = &omap3xxx_l3_main_hwmod, 91 .master = &omap3xxx_l3_main_hwmod,
@@ -159,6 +172,63 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
159 .user = OCP_USER_MPU | OCP_USER_SDMA, 172 .user = OCP_USER_MPU | OCP_USER_SDMA,
160}; 173};
161 174
175/* L4 CORE -> MMC1 interface */
176static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
177 {
178 .pa_start = 0x4809c000,
179 .pa_end = 0x4809c1ff,
180 .flags = ADDR_TYPE_RT,
181 },
182};
183
184static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
185 .master = &omap3xxx_l4_core_hwmod,
186 .slave = &omap3xxx_mmc1_hwmod,
187 .clk = "mmchs1_ick",
188 .addr = omap3xxx_mmc1_addr_space,
189 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
190 .user = OCP_USER_MPU | OCP_USER_SDMA,
191 .flags = OMAP_FIREWALL_L4
192};
193
194/* L4 CORE -> MMC2 interface */
195static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
196 {
197 .pa_start = 0x480b4000,
198 .pa_end = 0x480b41ff,
199 .flags = ADDR_TYPE_RT,
200 },
201};
202
203static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
204 .master = &omap3xxx_l4_core_hwmod,
205 .slave = &omap3xxx_mmc2_hwmod,
206 .clk = "mmchs2_ick",
207 .addr = omap3xxx_mmc2_addr_space,
208 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
209 .user = OCP_USER_MPU | OCP_USER_SDMA,
210 .flags = OMAP_FIREWALL_L4
211};
212
213/* L4 CORE -> MMC3 interface */
214static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
215 {
216 .pa_start = 0x480ad000,
217 .pa_end = 0x480ad1ff,
218 .flags = ADDR_TYPE_RT,
219 },
220};
221
222static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
223 .master = &omap3xxx_l4_core_hwmod,
224 .slave = &omap3xxx_mmc3_hwmod,
225 .clk = "mmchs3_ick",
226 .addr = omap3xxx_mmc3_addr_space,
227 .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
228 .user = OCP_USER_MPU | OCP_USER_SDMA,
229 .flags = OMAP_FIREWALL_L4
230};
231
162/* L4 CORE -> UART1 interface */ 232/* L4 CORE -> UART1 interface */
163static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = { 233static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
164 { 234 {
@@ -2364,6 +2434,437 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
2364 .flags = HWMOD_NO_IDLEST, 2434 .flags = HWMOD_NO_IDLEST,
2365}; 2435};
2366 2436
2437/*
2438 * 'mcbsp' class
2439 * multi channel buffered serial port controller
2440 */
2441
2442static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
2443 .sysc_offs = 0x008c,
2444 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
2445 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2446 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2447 .sysc_fields = &omap_hwmod_sysc_type1,
2448 .clockact = 0x2,
2449};
2450
2451static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
2452 .name = "mcbsp",
2453 .sysc = &omap3xxx_mcbsp_sysc,
2454 .rev = MCBSP_CONFIG_TYPE3,
2455};
2456
2457/* mcbsp1 */
2458static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
2459 { .name = "irq", .irq = 16 },
2460 { .name = "tx", .irq = 59 },
2461 { .name = "rx", .irq = 60 },
2462};
2463
2464static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
2465 { .name = "rx", .dma_req = 32 },
2466 { .name = "tx", .dma_req = 31 },
2467};
2468
2469static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2470 {
2471 .name = "mpu",
2472 .pa_start = 0x48074000,
2473 .pa_end = 0x480740ff,
2474 .flags = ADDR_TYPE_RT
2475 },
2476};
2477
2478/* l4_core -> mcbsp1 */
2479static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2480 .master = &omap3xxx_l4_core_hwmod,
2481 .slave = &omap3xxx_mcbsp1_hwmod,
2482 .clk = "mcbsp1_ick",
2483 .addr = omap3xxx_mcbsp1_addrs,
2484 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
2485 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486};
2487
2488/* mcbsp1 slave ports */
2489static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
2490 &omap3xxx_l4_core__mcbsp1,
2491};
2492
2493static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
2494 .name = "mcbsp1",
2495 .class = &omap3xxx_mcbsp_hwmod_class,
2496 .mpu_irqs = omap3xxx_mcbsp1_irqs,
2497 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
2498 .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
2499 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
2500 .main_clk = "mcbsp1_fck",
2501 .prcm = {
2502 .omap2 = {
2503 .prcm_reg_id = 1,
2504 .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
2505 .module_offs = CORE_MOD,
2506 .idlest_reg_id = 1,
2507 .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
2508 },
2509 },
2510 .slaves = omap3xxx_mcbsp1_slaves,
2511 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
2512 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2513};
2514
2515/* mcbsp2 */
2516static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
2517 { .name = "irq", .irq = 17 },
2518 { .name = "tx", .irq = 62 },
2519 { .name = "rx", .irq = 63 },
2520};
2521
2522static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
2523 { .name = "rx", .dma_req = 34 },
2524 { .name = "tx", .dma_req = 33 },
2525};
2526
2527static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2528 {
2529 .name = "mpu",
2530 .pa_start = 0x49022000,
2531 .pa_end = 0x490220ff,
2532 .flags = ADDR_TYPE_RT
2533 },
2534};
2535
2536/* l4_per -> mcbsp2 */
2537static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2538 .master = &omap3xxx_l4_per_hwmod,
2539 .slave = &omap3xxx_mcbsp2_hwmod,
2540 .clk = "mcbsp2_ick",
2541 .addr = omap3xxx_mcbsp2_addrs,
2542 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
2543 .user = OCP_USER_MPU | OCP_USER_SDMA,
2544};
2545
2546/* mcbsp2 slave ports */
2547static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
2548 &omap3xxx_l4_per__mcbsp2,
2549};
2550
2551static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
2552 .sidetone = "mcbsp2_sidetone",
2553};
2554
2555static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
2556 .name = "mcbsp2",
2557 .class = &omap3xxx_mcbsp_hwmod_class,
2558 .mpu_irqs = omap3xxx_mcbsp2_irqs,
2559 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
2560 .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
2561 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
2562 .main_clk = "mcbsp2_fck",
2563 .prcm = {
2564 .omap2 = {
2565 .prcm_reg_id = 1,
2566 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2567 .module_offs = OMAP3430_PER_MOD,
2568 .idlest_reg_id = 1,
2569 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2570 },
2571 },
2572 .slaves = omap3xxx_mcbsp2_slaves,
2573 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
2574 .dev_attr = &omap34xx_mcbsp2_dev_attr,
2575 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2576};
2577
2578/* mcbsp3 */
2579static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
2580 { .name = "irq", .irq = 22 },
2581 { .name = "tx", .irq = 89 },
2582 { .name = "rx", .irq = 90 },
2583};
2584
2585static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
2586 { .name = "rx", .dma_req = 18 },
2587 { .name = "tx", .dma_req = 17 },
2588};
2589
2590static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2591 {
2592 .name = "mpu",
2593 .pa_start = 0x49024000,
2594 .pa_end = 0x490240ff,
2595 .flags = ADDR_TYPE_RT
2596 },
2597};
2598
2599/* l4_per -> mcbsp3 */
2600static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2601 .master = &omap3xxx_l4_per_hwmod,
2602 .slave = &omap3xxx_mcbsp3_hwmod,
2603 .clk = "mcbsp3_ick",
2604 .addr = omap3xxx_mcbsp3_addrs,
2605 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
2606 .user = OCP_USER_MPU | OCP_USER_SDMA,
2607};
2608
2609/* mcbsp3 slave ports */
2610static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
2611 &omap3xxx_l4_per__mcbsp3,
2612};
2613
2614static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
2615 .sidetone = "mcbsp3_sidetone",
2616};
2617
2618static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
2619 .name = "mcbsp3",
2620 .class = &omap3xxx_mcbsp_hwmod_class,
2621 .mpu_irqs = omap3xxx_mcbsp3_irqs,
2622 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
2623 .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
2624 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
2625 .main_clk = "mcbsp3_fck",
2626 .prcm = {
2627 .omap2 = {
2628 .prcm_reg_id = 1,
2629 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2630 .module_offs = OMAP3430_PER_MOD,
2631 .idlest_reg_id = 1,
2632 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2633 },
2634 },
2635 .slaves = omap3xxx_mcbsp3_slaves,
2636 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
2637 .dev_attr = &omap34xx_mcbsp3_dev_attr,
2638 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2639};
2640
2641/* mcbsp4 */
2642static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
2643 { .name = "irq", .irq = 23 },
2644 { .name = "tx", .irq = 54 },
2645 { .name = "rx", .irq = 55 },
2646};
2647
2648static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
2649 { .name = "rx", .dma_req = 20 },
2650 { .name = "tx", .dma_req = 19 },
2651};
2652
2653static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2654 {
2655 .name = "mpu",
2656 .pa_start = 0x49026000,
2657 .pa_end = 0x490260ff,
2658 .flags = ADDR_TYPE_RT
2659 },
2660};
2661
2662/* l4_per -> mcbsp4 */
2663static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2664 .master = &omap3xxx_l4_per_hwmod,
2665 .slave = &omap3xxx_mcbsp4_hwmod,
2666 .clk = "mcbsp4_ick",
2667 .addr = omap3xxx_mcbsp4_addrs,
2668 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
2669 .user = OCP_USER_MPU | OCP_USER_SDMA,
2670};
2671
2672/* mcbsp4 slave ports */
2673static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
2674 &omap3xxx_l4_per__mcbsp4,
2675};
2676
2677static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
2678 .name = "mcbsp4",
2679 .class = &omap3xxx_mcbsp_hwmod_class,
2680 .mpu_irqs = omap3xxx_mcbsp4_irqs,
2681 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
2682 .sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
2683 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
2684 .main_clk = "mcbsp4_fck",
2685 .prcm = {
2686 .omap2 = {
2687 .prcm_reg_id = 1,
2688 .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
2689 .module_offs = OMAP3430_PER_MOD,
2690 .idlest_reg_id = 1,
2691 .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
2692 },
2693 },
2694 .slaves = omap3xxx_mcbsp4_slaves,
2695 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
2696 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2697};
2698
2699/* mcbsp5 */
2700static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
2701 { .name = "irq", .irq = 27 },
2702 { .name = "tx", .irq = 81 },
2703 { .name = "rx", .irq = 82 },
2704};
2705
2706static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
2707 { .name = "rx", .dma_req = 22 },
2708 { .name = "tx", .dma_req = 21 },
2709};
2710
2711static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2712 {
2713 .name = "mpu",
2714 .pa_start = 0x48096000,
2715 .pa_end = 0x480960ff,
2716 .flags = ADDR_TYPE_RT
2717 },
2718};
2719
2720/* l4_core -> mcbsp5 */
2721static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2722 .master = &omap3xxx_l4_core_hwmod,
2723 .slave = &omap3xxx_mcbsp5_hwmod,
2724 .clk = "mcbsp5_ick",
2725 .addr = omap3xxx_mcbsp5_addrs,
2726 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
2727 .user = OCP_USER_MPU | OCP_USER_SDMA,
2728};
2729
2730/* mcbsp5 slave ports */
2731static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
2732 &omap3xxx_l4_core__mcbsp5,
2733};
2734
2735static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
2736 .name = "mcbsp5",
2737 .class = &omap3xxx_mcbsp_hwmod_class,
2738 .mpu_irqs = omap3xxx_mcbsp5_irqs,
2739 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
2740 .sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
2741 .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
2742 .main_clk = "mcbsp5_fck",
2743 .prcm = {
2744 .omap2 = {
2745 .prcm_reg_id = 1,
2746 .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
2747 .module_offs = CORE_MOD,
2748 .idlest_reg_id = 1,
2749 .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
2750 },
2751 },
2752 .slaves = omap3xxx_mcbsp5_slaves,
2753 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
2754 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2755};
2756/* 'mcbsp sidetone' class */
2757
2758static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
2759 .sysc_offs = 0x0010,
2760 .sysc_flags = SYSC_HAS_AUTOIDLE,
2761 .sysc_fields = &omap_hwmod_sysc_type1,
2762};
2763
2764static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
2765 .name = "mcbsp_sidetone",
2766 .sysc = &omap3xxx_mcbsp_sidetone_sysc,
2767};
2768
2769/* mcbsp2_sidetone */
2770static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
2771 { .name = "irq", .irq = 4 },
2772};
2773
2774static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2775 {
2776 .name = "sidetone",
2777 .pa_start = 0x49028000,
2778 .pa_end = 0x490280ff,
2779 .flags = ADDR_TYPE_RT
2780 },
2781};
2782
2783/* l4_per -> mcbsp2_sidetone */
2784static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2785 .master = &omap3xxx_l4_per_hwmod,
2786 .slave = &omap3xxx_mcbsp2_sidetone_hwmod,
2787 .clk = "mcbsp2_ick",
2788 .addr = omap3xxx_mcbsp2_sidetone_addrs,
2789 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
2790 .user = OCP_USER_MPU,
2791};
2792
2793/* mcbsp2_sidetone slave ports */
2794static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
2795 &omap3xxx_l4_per__mcbsp2_sidetone,
2796};
2797
2798static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
2799 .name = "mcbsp2_sidetone",
2800 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2801 .mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
2802 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
2803 .main_clk = "mcbsp2_fck",
2804 .prcm = {
2805 .omap2 = {
2806 .prcm_reg_id = 1,
2807 .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
2808 .module_offs = OMAP3430_PER_MOD,
2809 .idlest_reg_id = 1,
2810 .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
2811 },
2812 },
2813 .slaves = omap3xxx_mcbsp2_sidetone_slaves,
2814 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
2815 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2816};
2817
2818/* mcbsp3_sidetone */
2819static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
2820 { .name = "irq", .irq = 5 },
2821};
2822
2823static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2824 {
2825 .name = "sidetone",
2826 .pa_start = 0x4902A000,
2827 .pa_end = 0x4902A0ff,
2828 .flags = ADDR_TYPE_RT
2829 },
2830};
2831
2832/* l4_per -> mcbsp3_sidetone */
2833static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2834 .master = &omap3xxx_l4_per_hwmod,
2835 .slave = &omap3xxx_mcbsp3_sidetone_hwmod,
2836 .clk = "mcbsp3_ick",
2837 .addr = omap3xxx_mcbsp3_sidetone_addrs,
2838 .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
2839 .user = OCP_USER_MPU,
2840};
2841
2842/* mcbsp3_sidetone slave ports */
2843static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
2844 &omap3xxx_l4_per__mcbsp3_sidetone,
2845};
2846
2847static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
2848 .name = "mcbsp3_sidetone",
2849 .class = &omap3xxx_mcbsp_sidetone_hwmod_class,
2850 .mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
2851 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
2852 .main_clk = "mcbsp3_fck",
2853 .prcm = {
2854 .omap2 = {
2855 .prcm_reg_id = 1,
2856 .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
2857 .module_offs = OMAP3430_PER_MOD,
2858 .idlest_reg_id = 1,
2859 .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
2860 },
2861 },
2862 .slaves = omap3xxx_mcbsp3_sidetone_slaves,
2863 .slaves_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
2864 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
2865};
2866
2867
2367/* SR common */ 2868/* SR common */
2368static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = { 2869static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
2369 .clkact_shift = 20, 2870 .clkact_shift = 20,
@@ -2493,6 +2994,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
2493 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), 2994 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
2494}; 2995};
2495 2996
2997/*
2998 * 'mailbox' class
2999 * mailbox module allowing communication between the on-chip processors
3000 * using a queued mailbox-interrupt mechanism.
3001 */
3002
3003static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
3004 .rev_offs = 0x000,
3005 .sysc_offs = 0x010,
3006 .syss_offs = 0x014,
3007 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3008 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
3009 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3010 .sysc_fields = &omap_hwmod_sysc_type1,
3011};
3012
3013static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
3014 .name = "mailbox",
3015 .sysc = &omap3xxx_mailbox_sysc,
3016};
3017
3018static struct omap_hwmod omap3xxx_mailbox_hwmod;
3019static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
3020 { .irq = 26 },
3021};
3022
3023static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3024 {
3025 .pa_start = 0x48094000,
3026 .pa_end = 0x480941ff,
3027 .flags = ADDR_TYPE_RT,
3028 },
3029};
3030
3031/* l4_core -> mailbox */
3032static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3033 .master = &omap3xxx_l4_core_hwmod,
3034 .slave = &omap3xxx_mailbox_hwmod,
3035 .addr = omap3xxx_mailbox_addrs,
3036 .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3038};
3039
3040/* mailbox slave ports */
3041static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
3042 &omap3xxx_l4_core__mailbox,
3043};
3044
3045static struct omap_hwmod omap3xxx_mailbox_hwmod = {
3046 .name = "mailbox",
3047 .class = &omap3xxx_mailbox_hwmod_class,
3048 .mpu_irqs = omap3xxx_mailbox_irqs,
3049 .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
3050 .main_clk = "mailboxes_ick",
3051 .prcm = {
3052 .omap2 = {
3053 .prcm_reg_id = 1,
3054 .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
3055 .module_offs = CORE_MOD,
3056 .idlest_reg_id = 1,
3057 .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
3058 },
3059 },
3060 .slaves = omap3xxx_mailbox_slaves,
3061 .slaves_cnt = ARRAY_SIZE(omap3xxx_mailbox_slaves),
3062 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3063};
3064
2496/* l4 core -> mcspi1 interface */ 3065/* l4 core -> mcspi1 interface */
2497static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = { 3066static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
2498 { 3067 {
@@ -2847,11 +3416,165 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
2847 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1) 3416 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
2848}; 3417};
2849 3418
3419/* MMC/SD/SDIO common */
3420
3421static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
3422 .rev_offs = 0x1fc,
3423 .sysc_offs = 0x10,
3424 .syss_offs = 0x14,
3425 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
3426 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
3427 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
3428 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
3429 .sysc_fields = &omap_hwmod_sysc_type1,
3430};
3431
3432static struct omap_hwmod_class omap34xx_mmc_class = {
3433 .name = "mmc",
3434 .sysc = &omap34xx_mmc_sysc,
3435};
3436
3437/* MMC/SD/SDIO1 */
3438
3439static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
3440 { .irq = 83, },
3441};
3442
3443static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
3444 { .name = "tx", .dma_req = 61, },
3445 { .name = "rx", .dma_req = 62, },
3446};
3447
3448static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
3449 { .role = "dbck", .clk = "omap_32k_fck", },
3450};
3451
3452static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
3453 &omap3xxx_l4_core__mmc1,
3454};
3455
3456static struct omap_mmc_dev_attr mmc1_dev_attr = {
3457 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3458};
3459
3460static struct omap_hwmod omap3xxx_mmc1_hwmod = {
3461 .name = "mmc1",
3462 .mpu_irqs = omap34xx_mmc1_mpu_irqs,
3463 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
3464 .sdma_reqs = omap34xx_mmc1_sdma_reqs,
3465 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
3466 .opt_clks = omap34xx_mmc1_opt_clks,
3467 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
3468 .main_clk = "mmchs1_fck",
3469 .prcm = {
3470 .omap2 = {
3471 .module_offs = CORE_MOD,
3472 .prcm_reg_id = 1,
3473 .module_bit = OMAP3430_EN_MMC1_SHIFT,
3474 .idlest_reg_id = 1,
3475 .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
3476 },
3477 },
3478 .dev_attr = &mmc1_dev_attr,
3479 .slaves = omap3xxx_mmc1_slaves,
3480 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc1_slaves),
3481 .class = &omap34xx_mmc_class,
3482 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3483};
3484
3485/* MMC/SD/SDIO2 */
3486
3487static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
3488 { .irq = INT_24XX_MMC2_IRQ, },
3489};
3490
3491static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
3492 { .name = "tx", .dma_req = 47, },
3493 { .name = "rx", .dma_req = 48, },
3494};
3495
3496static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
3497 { .role = "dbck", .clk = "omap_32k_fck", },
3498};
3499
3500static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
3501 &omap3xxx_l4_core__mmc2,
3502};
3503
3504static struct omap_hwmod omap3xxx_mmc2_hwmod = {
3505 .name = "mmc2",
3506 .mpu_irqs = omap34xx_mmc2_mpu_irqs,
3507 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
3508 .sdma_reqs = omap34xx_mmc2_sdma_reqs,
3509 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
3510 .opt_clks = omap34xx_mmc2_opt_clks,
3511 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
3512 .main_clk = "mmchs2_fck",
3513 .prcm = {
3514 .omap2 = {
3515 .module_offs = CORE_MOD,
3516 .prcm_reg_id = 1,
3517 .module_bit = OMAP3430_EN_MMC2_SHIFT,
3518 .idlest_reg_id = 1,
3519 .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
3520 },
3521 },
3522 .slaves = omap3xxx_mmc2_slaves,
3523 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc2_slaves),
3524 .class = &omap34xx_mmc_class,
3525 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3526};
3527
3528/* MMC/SD/SDIO3 */
3529
3530static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
3531 { .irq = 94, },
3532};
3533
3534static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
3535 { .name = "tx", .dma_req = 77, },
3536 { .name = "rx", .dma_req = 78, },
3537};
3538
3539static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
3540 { .role = "dbck", .clk = "omap_32k_fck", },
3541};
3542
3543static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
3544 &omap3xxx_l4_core__mmc3,
3545};
3546
3547static struct omap_hwmod omap3xxx_mmc3_hwmod = {
3548 .name = "mmc3",
3549 .mpu_irqs = omap34xx_mmc3_mpu_irqs,
3550 .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
3551 .sdma_reqs = omap34xx_mmc3_sdma_reqs,
3552 .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
3553 .opt_clks = omap34xx_mmc3_opt_clks,
3554 .opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
3555 .main_clk = "mmchs3_fck",
3556 .prcm = {
3557 .omap2 = {
3558 .prcm_reg_id = 1,
3559 .module_bit = OMAP3430_EN_MMC3_SHIFT,
3560 .idlest_reg_id = 1,
3561 .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
3562 },
3563 },
3564 .slaves = omap3xxx_mmc3_slaves,
3565 .slaves_cnt = ARRAY_SIZE(omap3xxx_mmc3_slaves),
3566 .class = &omap34xx_mmc_class,
3567 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
3568};
3569
2850static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { 3570static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2851 &omap3xxx_l3_main_hwmod, 3571 &omap3xxx_l3_main_hwmod,
2852 &omap3xxx_l4_core_hwmod, 3572 &omap3xxx_l4_core_hwmod,
2853 &omap3xxx_l4_per_hwmod, 3573 &omap3xxx_l4_per_hwmod,
2854 &omap3xxx_l4_wkup_hwmod, 3574 &omap3xxx_l4_wkup_hwmod,
3575 &omap3xxx_mmc1_hwmod,
3576 &omap3xxx_mmc2_hwmod,
3577 &omap3xxx_mmc3_hwmod,
2855 &omap3xxx_mpu_hwmod, 3578 &omap3xxx_mpu_hwmod,
2856 &omap3xxx_iva_hwmod, 3579 &omap3xxx_iva_hwmod,
2857 3580
@@ -2902,6 +3625,18 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
2902 /* dma_system class*/ 3625 /* dma_system class*/
2903 &omap3xxx_dma_system_hwmod, 3626 &omap3xxx_dma_system_hwmod,
2904 3627
3628 /* mcbsp class */
3629 &omap3xxx_mcbsp1_hwmod,
3630 &omap3xxx_mcbsp2_hwmod,
3631 &omap3xxx_mcbsp3_hwmod,
3632 &omap3xxx_mcbsp4_hwmod,
3633 &omap3xxx_mcbsp5_hwmod,
3634 &omap3xxx_mcbsp2_sidetone_hwmod,
3635 &omap3xxx_mcbsp3_sidetone_hwmod,
3636
3637 /* mailbox class */
3638 &omap3xxx_mailbox_hwmod,
3639
2905 /* mcspi class */ 3640 /* mcspi class */
2906 &omap34xx_mcspi1, 3641 &omap34xx_mcspi1,
2907 &omap34xx_mcspi2, 3642 &omap34xx_mcspi2,
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 2c5882792e01..7dbcdf751c02 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -25,6 +25,8 @@
25#include <plat/gpio.h> 25#include <plat/gpio.h>
26#include <plat/dma.h> 26#include <plat/dma.h>
27#include <plat/mcspi.h> 27#include <plat/mcspi.h>
28#include <plat/mcbsp.h>
29#include <plat/mmc.h>
28 30
29#include "omap_hwmod_common_data.h" 31#include "omap_hwmod_common_data.h"
30 32
@@ -2737,6 +2739,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
2737static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { 2739static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
2738 .name = "mcbsp", 2740 .name = "mcbsp",
2739 .sysc = &omap44xx_mcbsp_sysc, 2741 .sysc = &omap44xx_mcbsp_sysc,
2742 .rev = MCBSP_CONFIG_TYPE4,
2740}; 2743};
2741 2744
2742/* mcbsp1 */ 2745/* mcbsp1 */
@@ -2752,6 +2755,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
2752 2755
2753static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { 2756static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
2754 { 2757 {
2758 .name = "mpu",
2755 .pa_start = 0x40122000, 2759 .pa_start = 0x40122000,
2756 .pa_end = 0x401220ff, 2760 .pa_end = 0x401220ff,
2757 .flags = ADDR_TYPE_RT 2761 .flags = ADDR_TYPE_RT
@@ -2770,6 +2774,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
2770 2774
2771static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { 2775static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
2772 { 2776 {
2777 .name = "dma",
2773 .pa_start = 0x49022000, 2778 .pa_start = 0x49022000,
2774 .pa_end = 0x490220ff, 2779 .pa_end = 0x490220ff,
2775 .flags = ADDR_TYPE_RT 2780 .flags = ADDR_TYPE_RT
@@ -2823,6 +2828,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
2823 2828
2824static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { 2829static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
2825 { 2830 {
2831 .name = "mpu",
2826 .pa_start = 0x40124000, 2832 .pa_start = 0x40124000,
2827 .pa_end = 0x401240ff, 2833 .pa_end = 0x401240ff,
2828 .flags = ADDR_TYPE_RT 2834 .flags = ADDR_TYPE_RT
@@ -2841,6 +2847,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
2841 2847
2842static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { 2848static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
2843 { 2849 {
2850 .name = "dma",
2844 .pa_start = 0x49024000, 2851 .pa_start = 0x49024000,
2845 .pa_end = 0x490240ff, 2852 .pa_end = 0x490240ff,
2846 .flags = ADDR_TYPE_RT 2853 .flags = ADDR_TYPE_RT
@@ -2894,6 +2901,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
2894 2901
2895static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { 2902static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
2896 { 2903 {
2904 .name = "mpu",
2897 .pa_start = 0x40126000, 2905 .pa_start = 0x40126000,
2898 .pa_end = 0x401260ff, 2906 .pa_end = 0x401260ff,
2899 .flags = ADDR_TYPE_RT 2907 .flags = ADDR_TYPE_RT
@@ -2912,6 +2920,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
2912 2920
2913static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { 2921static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
2914 { 2922 {
2923 .name = "dma",
2915 .pa_start = 0x49026000, 2924 .pa_start = 0x49026000,
2916 .pa_end = 0x490260ff, 2925 .pa_end = 0x490260ff,
2917 .flags = ADDR_TYPE_RT 2926 .flags = ADDR_TYPE_RT
@@ -3383,6 +3392,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
3383}; 3392};
3384 3393
3385/* mmc1 */ 3394/* mmc1 */
3395
3386static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { 3396static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
3387 { .irq = 83 + OMAP44XX_IRQ_GIC_START }, 3397 { .irq = 83 + OMAP44XX_IRQ_GIC_START },
3388}; 3398};
@@ -3420,6 +3430,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
3420 &omap44xx_l4_per__mmc1, 3430 &omap44xx_l4_per__mmc1,
3421}; 3431};
3422 3432
3433/* mmc1 dev_attr */
3434static struct omap_mmc_dev_attr mmc1_dev_attr = {
3435 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
3436};
3437
3423static struct omap_hwmod omap44xx_mmc1_hwmod = { 3438static struct omap_hwmod omap44xx_mmc1_hwmod = {
3424 .name = "mmc1", 3439 .name = "mmc1",
3425 .class = &omap44xx_mmc_hwmod_class, 3440 .class = &omap44xx_mmc_hwmod_class,
@@ -3433,6 +3448,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
3433 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL, 3448 .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
3434 }, 3449 },
3435 }, 3450 },
3451 .dev_attr = &mmc1_dev_attr,
3436 .slaves = omap44xx_mmc1_slaves, 3452 .slaves = omap44xx_mmc1_slaves,
3437 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves), 3453 .slaves_cnt = ARRAY_SIZE(omap44xx_mmc1_slaves),
3438 .masters = omap44xx_mmc1_masters, 3454 .masters = omap44xx_mmc1_masters,
@@ -5077,11 +5093,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
5077 &omap44xx_mcspi4_hwmod, 5093 &omap44xx_mcspi4_hwmod,
5078 5094
5079 /* mmc class */ 5095 /* mmc class */
5080/* &omap44xx_mmc1_hwmod, */ 5096 &omap44xx_mmc1_hwmod,
5081/* &omap44xx_mmc2_hwmod, */ 5097 &omap44xx_mmc2_hwmod,
5082/* &omap44xx_mmc3_hwmod, */ 5098 &omap44xx_mmc3_hwmod,
5083/* &omap44xx_mmc4_hwmod, */ 5099 &omap44xx_mmc4_hwmod,
5084/* &omap44xx_mmc5_hwmod, */ 5100 &omap44xx_mmc5_hwmod,
5085 5101
5086 /* mpu class */ 5102 /* mpu class */
5087 &omap44xx_mpu_hwmod, 5103 &omap44xx_mpu_hwmod,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 87486f559784..0363dcb0ef93 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -121,6 +121,10 @@
121#define OMAP24XX_ST_MCSPI2_MASK (1 << 18) 121#define OMAP24XX_ST_MCSPI2_MASK (1 << 18)
122#define OMAP24XX_ST_MCSPI1_SHIFT 17 122#define OMAP24XX_ST_MCSPI1_SHIFT 17
123#define OMAP24XX_ST_MCSPI1_MASK (1 << 17) 123#define OMAP24XX_ST_MCSPI1_MASK (1 << 17)
124#define OMAP24XX_ST_MCBSP2_SHIFT 16
125#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
126#define OMAP24XX_ST_MCBSP1_SHIFT 15
127#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
124#define OMAP24XX_ST_GPT12_SHIFT 14 128#define OMAP24XX_ST_GPT12_SHIFT 14
125#define OMAP24XX_ST_GPT12_MASK (1 << 14) 129#define OMAP24XX_ST_GPT12_MASK (1 << 14)
126#define OMAP24XX_ST_GPT11_SHIFT 13 130#define OMAP24XX_ST_GPT11_SHIFT 13
@@ -191,6 +195,8 @@
191#define OMAP3430_AUTOIDLE_MASK (1 << 0) 195#define OMAP3430_AUTOIDLE_MASK (1 << 0)
192 196
193/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ 197/* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
198#define OMAP3430_EN_MMC3_MASK (1 << 30)
199#define OMAP3430_EN_MMC3_SHIFT 30
194#define OMAP3430_EN_MMC2_MASK (1 << 25) 200#define OMAP3430_EN_MMC2_MASK (1 << 25)
195#define OMAP3430_EN_MMC2_SHIFT 25 201#define OMAP3430_EN_MMC2_SHIFT 25
196#define OMAP3430_EN_MMC1_MASK (1 << 24) 202#define OMAP3430_EN_MMC1_MASK (1 << 24)
@@ -231,6 +237,8 @@
231#define OMAP3430_EN_HSOTGUSB_SHIFT 4 237#define OMAP3430_EN_HSOTGUSB_SHIFT 4
232 238
233/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ 239/* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
240#define OMAP3430_ST_MMC3_SHIFT 30
241#define OMAP3430_ST_MMC3_MASK (1 << 30)
234#define OMAP3430_ST_MMC2_SHIFT 25 242#define OMAP3430_ST_MMC2_SHIFT 25
235#define OMAP3430_ST_MMC2_MASK (1 << 25) 243#define OMAP3430_ST_MMC2_MASK (1 << 25)
236#define OMAP3430_ST_MMC1_SHIFT 24 244#define OMAP3430_ST_MMC1_SHIFT 24
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 10245b837c10..7d9f815cedec 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -35,8 +35,8 @@
35 35
36static struct platform_device **omap_mcbsp_devices; 36static struct platform_device **omap_mcbsp_devices;
37 37
38void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 38void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
39 int size) 39 struct omap_mcbsp_platform_data *config, int size)
40{ 40{
41 int i; 41 int i;
42 42
@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1); 54 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
55 if (!new_mcbsp) 55 if (!new_mcbsp)
56 continue; 56 continue;
57 platform_device_add_resources(new_mcbsp, &res[i * res_count],
58 res_count);
57 new_mcbsp->dev.platform_data = &config[i]; 59 new_mcbsp->dev.platform_data = &config[i];
58 ret = platform_device_add(new_mcbsp); 60 ret = platform_device_add(new_mcbsp);
59 if (ret) { 61 if (ret) {
@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
65} 67}
66 68
67#else 69#else
68void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 70void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
69 int size) 71 struct omap_mcbsp_platform_data *config, int size)
70{ } 72{ }
71#endif 73#endif
72 74
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 19cbb5e9ece2..174f1b9c8c03 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
31 struct clk *clk; 31 struct clk *clk;
32 void __iomem *regbase; 32 void __iomem *regbase;
33 struct device *dev; 33 struct device *dev;
34 void *isr_priv;
34 35
35 unsigned int refcount; 36 unsigned int refcount;
36 struct mutex iommu_lock; /* global for this whole object */ 37 struct mutex iommu_lock; /* global for this whole object */
@@ -47,7 +48,7 @@ struct iommu {
47 struct list_head mmap; 48 struct list_head mmap;
48 struct mutex mmap_lock; /* protect mmap */ 49 struct mutex mmap_lock; /* protect mmap */
49 50
50 int (*isr)(struct iommu *obj); 51 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
51 52
52 void *ctx; /* iommu context: registres saved area */ 53 void *ctx; /* iommu context: registres saved area */
53 u32 da_start; 54 u32 da_start;
@@ -109,6 +110,13 @@ struct iommu_platform_data {
109 u32 da_end; 110 u32 da_end;
110}; 111};
111 112
113/* IOMMU errors */
114#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
115#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
116#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
117#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
118#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
119
112#if defined(CONFIG_ARCH_OMAP1) 120#if defined(CONFIG_ARCH_OMAP1)
113#error "iommu for this processor not implemented yet" 121#error "iommu for this processor not implemented yet"
114#else 122#else
@@ -161,6 +169,10 @@ extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
161extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end); 169extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
162extern struct iommu *iommu_get(const char *name); 170extern struct iommu *iommu_get(const char *name);
163extern void iommu_put(struct iommu *obj); 171extern void iommu_put(struct iommu *obj);
172extern int iommu_set_isr(const char *name,
173 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
174 void *priv),
175 void *isr_priv);
164 176
165extern void iommu_save_ctx(struct iommu *obj); 177extern void iommu_save_ctx(struct iommu *obj);
166extern void iommu_restore_ctx(struct iommu *obj); 178extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 6ecf1051e5f4..f8f690ab2997 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -37,6 +37,10 @@ static struct platform_device omap_mcbsp##port_nr = { \
37 .id = OMAP_MCBSP##port_nr, \ 37 .id = OMAP_MCBSP##port_nr, \
38} 38}
39 39
40#define MCBSP_CONFIG_TYPE2 0x2
41#define MCBSP_CONFIG_TYPE3 0x3
42#define MCBSP_CONFIG_TYPE4 0x4
43
40#define OMAP7XX_MCBSP1_BASE 0xfffb1000 44#define OMAP7XX_MCBSP1_BASE 0xfffb1000
41#define OMAP7XX_MCBSP2_BASE 0xfffb1800 45#define OMAP7XX_MCBSP2_BASE 0xfffb1800
42 46
@@ -48,32 +52,14 @@ static struct platform_device omap_mcbsp##port_nr = { \
48#define OMAP1610_MCBSP2_BASE 0xfffb1000 52#define OMAP1610_MCBSP2_BASE 0xfffb1000
49#define OMAP1610_MCBSP3_BASE 0xe1017000 53#define OMAP1610_MCBSP3_BASE 0xe1017000
50 54
51#define OMAP24XX_MCBSP1_BASE 0x48074000 55#ifdef CONFIG_ARCH_OMAP1
52#define OMAP24XX_MCBSP2_BASE 0x48076000
53#define OMAP2430_MCBSP3_BASE 0x4808c000
54#define OMAP2430_MCBSP4_BASE 0x4808e000
55#define OMAP2430_MCBSP5_BASE 0x48096000
56
57#define OMAP34XX_MCBSP1_BASE 0x48074000
58#define OMAP34XX_MCBSP2_BASE 0x49022000
59#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
60#define OMAP34XX_MCBSP3_BASE 0x49024000
61#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
62#define OMAP34XX_MCBSP3_BASE 0x49024000
63#define OMAP34XX_MCBSP4_BASE 0x49026000
64#define OMAP34XX_MCBSP5_BASE 0x48096000
65
66#define OMAP44XX_MCBSP1_BASE 0x49022000
67#define OMAP44XX_MCBSP2_BASE 0x49024000
68#define OMAP44XX_MCBSP3_BASE 0x49026000
69#define OMAP44XX_MCBSP4_BASE 0x48096000
70
71#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
72 56
73#define OMAP_MCBSP_REG_DRR2 0x00 57#define OMAP_MCBSP_REG_DRR2 0x00
74#define OMAP_MCBSP_REG_DRR1 0x02 58#define OMAP_MCBSP_REG_DRR1 0x02
75#define OMAP_MCBSP_REG_DXR2 0x04 59#define OMAP_MCBSP_REG_DXR2 0x04
76#define OMAP_MCBSP_REG_DXR1 0x06 60#define OMAP_MCBSP_REG_DXR1 0x06
61#define OMAP_MCBSP_REG_DRR 0x02
62#define OMAP_MCBSP_REG_DXR 0x06
77#define OMAP_MCBSP_REG_SPCR2 0x08 63#define OMAP_MCBSP_REG_SPCR2 0x08
78#define OMAP_MCBSP_REG_SPCR1 0x0a 64#define OMAP_MCBSP_REG_SPCR1 0x0a
79#define OMAP_MCBSP_REG_RCR2 0x0c 65#define OMAP_MCBSP_REG_RCR2 0x0c
@@ -414,8 +400,9 @@ struct omap_mcbsp_platform_data {
414#ifdef CONFIG_ARCH_OMAP3 400#ifdef CONFIG_ARCH_OMAP3
415 /* Sidetone block for McBSP 2 and 3 */ 401 /* Sidetone block for McBSP 2 and 3 */
416 unsigned long phys_base_st; 402 unsigned long phys_base_st;
417 u16 buffer_size;
418#endif 403#endif
404 u16 buffer_size;
405 unsigned int mcbsp_config_type;
419}; 406};
420 407
421struct omap_mcbsp_st_data { 408struct omap_mcbsp_st_data {
@@ -431,6 +418,7 @@ struct omap_mcbsp_st_data {
431struct omap_mcbsp { 418struct omap_mcbsp {
432 struct device *dev; 419 struct device *dev;
433 unsigned long phys_base; 420 unsigned long phys_base;
421 unsigned long phys_dma_base;
434 void __iomem *io_base; 422 void __iomem *io_base;
435 u8 id; 423 u8 id;
436 u8 free; 424 u8 free;
@@ -457,7 +445,6 @@ struct omap_mcbsp {
457 /* Protect the field .free, while checking if the mcbsp is in use */ 445 /* Protect the field .free, while checking if the mcbsp is in use */
458 spinlock_t lock; 446 spinlock_t lock;
459 struct omap_mcbsp_platform_data *pdata; 447 struct omap_mcbsp_platform_data *pdata;
460 struct clk *iclk;
461 struct clk *fclk; 448 struct clk *fclk;
462#ifdef CONFIG_ARCH_OMAP3 449#ifdef CONFIG_ARCH_OMAP3
463 struct omap_mcbsp_st_data *st_data; 450 struct omap_mcbsp_st_data *st_data;
@@ -466,7 +453,17 @@ struct omap_mcbsp {
466 u16 max_rx_thres; 453 u16 max_rx_thres;
467#endif 454#endif
468 void *reg_cache; 455 void *reg_cache;
456 unsigned int mcbsp_config_type;
469}; 457};
458
459/**
460 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
461 * @sidetone: name of the sidetone device
462 */
463struct omap_mcbsp_dev_attr {
464 const char *sidetone;
465};
466
470extern struct omap_mcbsp **mcbsp_ptr; 467extern struct omap_mcbsp **mcbsp_ptr;
471extern int omap_mcbsp_count, omap_mcbsp_cache_size; 468extern int omap_mcbsp_count, omap_mcbsp_cache_size;
472 469
@@ -474,8 +471,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
474#define id_to_mcbsp_ptr(id) mcbsp_ptr[id]; 471#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
475 472
476int omap_mcbsp_init(void); 473int omap_mcbsp_init(void);
477void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, 474void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
478 int size); 475 struct omap_mcbsp_platform_data *config, int size);
479void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 476void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
480#ifdef CONFIG_ARCH_OMAP3 477#ifdef CONFIG_ARCH_OMAP3
481void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); 478void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
@@ -525,6 +522,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
525void omap2_mcbsp1_mux_clkr_src(u8 mux); 522void omap2_mcbsp1_mux_clkr_src(u8 mux);
526void omap2_mcbsp1_mux_fsr_src(u8 mux); 523void omap2_mcbsp1_mux_fsr_src(u8 mux);
527 524
525int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
526int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
527
528#ifdef CONFIG_ARCH_OMAP3 528#ifdef CONFIG_ARCH_OMAP3
529/* Sidetone specific API */ 529/* Sidetone specific API */
530int omap_st_set_chgain(unsigned int id, int channel, s16 chgain); 530int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f57f36abb07e..f38fef9f1310 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -24,25 +24,19 @@
24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */ 24#define OMAP1_MMC2_BASE 0xfffb7c00 /* omap16xx only */
25 25
26#define OMAP24XX_NR_MMC 2 26#define OMAP24XX_NR_MMC 2
27#define OMAP34XX_NR_MMC 3
28#define OMAP44XX_NR_MMC 5
29#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE 27#define OMAP2420_MMC_SIZE OMAP1_MMC_SIZE
30#define OMAP3_HSMMC_SIZE 0x200
31#define OMAP4_HSMMC_SIZE 0x1000
32#define OMAP2_MMC1_BASE 0x4809c000 28#define OMAP2_MMC1_BASE 0x4809c000
33#define OMAP2_MMC2_BASE 0x480b4000 29
34#define OMAP3_MMC3_BASE 0x480ad000
35#define OMAP4_MMC4_BASE 0x480d1000
36#define OMAP4_MMC5_BASE 0x480d5000
37#define OMAP4_MMC_REG_OFFSET 0x100 30#define OMAP4_MMC_REG_OFFSET 0x100
38#define HSMMC5 (1 << 4)
39#define HSMMC4 (1 << 3)
40#define HSMMC3 (1 << 2)
41#define HSMMC2 (1 << 1)
42#define HSMMC1 (1 << 0)
43 31
44#define OMAP_MMC_MAX_SLOTS 2 32#define OMAP_MMC_MAX_SLOTS 2
45 33
34#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT BIT(1)
35
36struct omap_mmc_dev_attr {
37 u8 flags;
38};
39
46struct omap_mmc_platform_data { 40struct omap_mmc_platform_data {
47 /* back-link to device */ 41 /* back-link to device */
48 struct device *dev; 42 struct device *dev;
@@ -71,6 +65,9 @@ struct omap_mmc_platform_data {
71 65
72 u64 dma_mask; 66 u64 dma_mask;
73 67
68 /* Integrating attributes from the omap_hwmod layer */
69 u8 controller_flags;
70
74 /* Register offset deviation */ 71 /* Register offset deviation */
75 u16 reg_offset; 72 u16 reg_offset;
76 73
@@ -159,8 +156,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
159 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE) 156 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
160void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data, 157void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
161 int nr_controllers); 158 int nr_controllers);
162void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 159void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
163 int nr_controllers);
164int omap_mmc_add(const char *name, int id, unsigned long base, 160int omap_mmc_add(const char *name, int id, unsigned long base,
165 unsigned long size, unsigned int irq, 161 unsigned long size, unsigned int irq,
166 struct omap_mmc_platform_data *data); 162 struct omap_mmc_platform_data *data);
@@ -169,8 +165,7 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
169 int nr_controllers) 165 int nr_controllers)
170{ 166{
171} 167}
172static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data, 168static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
173 int nr_controllers)
174{ 169{
175} 170}
176static inline int omap_mmc_add(const char *name, int id, unsigned long base, 171static inline int omap_mmc_add(const char *name, int id, unsigned long base,
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index f96e72ed4db1..97aa8e763e16 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -179,7 +179,8 @@ struct omap_hwmod_omap2_firewall {
179#define ADDR_TYPE_RT (1 << 1) 179#define ADDR_TYPE_RT (1 << 1)
180 180
181/** 181/**
182 * struct omap_hwmod_addr_space - MPU address space handled by the hwmod 182 * struct omap_hwmod_addr_space - address space handled by the hwmod
183 * @name: name of the address space
183 * @pa_start: starting physical address 184 * @pa_start: starting physical address
184 * @pa_end: ending physical address 185 * @pa_end: ending physical address
185 * @flags: (see omap_hwmod_addr_space.flags macros above) 186 * @flags: (see omap_hwmod_addr_space.flags macros above)
@@ -188,6 +189,7 @@ struct omap_hwmod_omap2_firewall {
188 * structure. GPMC is one example. 189 * structure. GPMC is one example.
189 */ 190 */
190struct omap_hwmod_addr_space { 191struct omap_hwmod_addr_space {
192 const char *name;
191 u32 pa_start; 193 u32 pa_start;
192 u32 pa_end; 194 u32 pa_end;
193 u8 flags; 195 u8 flags;
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b1107c08da56..e3eb0380090a 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -104,6 +104,9 @@ static int iommu_enable(struct iommu *obj)
104 if (!obj) 104 if (!obj)
105 return -EINVAL; 105 return -EINVAL;
106 106
107 if (!arch_iommu)
108 return -ENODEV;
109
107 clk_enable(obj->clk); 110 clk_enable(obj->clk);
108 111
109 err = arch_iommu->enable(obj); 112 err = arch_iommu->enable(obj);
@@ -780,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
780 */ 783 */
781static irqreturn_t iommu_fault_handler(int irq, void *data) 784static irqreturn_t iommu_fault_handler(int irq, void *data)
782{ 785{
783 u32 stat, da; 786 u32 da, errs;
784 u32 *iopgd, *iopte; 787 u32 *iopgd, *iopte;
785 int err = -EIO;
786 struct iommu *obj = data; 788 struct iommu *obj = data;
787 789
788 if (!obj->refcount) 790 if (!obj->refcount)
789 return IRQ_NONE; 791 return IRQ_NONE;
790 792
791 /* Dynamic loading TLB or PTE */
792 if (obj->isr)
793 err = obj->isr(obj);
794
795 if (!err)
796 return IRQ_HANDLED;
797
798 clk_enable(obj->clk); 793 clk_enable(obj->clk);
799 stat = iommu_report_fault(obj, &da); 794 errs = iommu_report_fault(obj, &da);
800 clk_disable(obj->clk); 795 clk_disable(obj->clk);
801 if (!stat) 796
797 /* Fault callback or TLB/PTE Dynamic loading */
798 if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
802 return IRQ_HANDLED; 799 return IRQ_HANDLED;
803 800
804 iommu_disable(obj); 801 iommu_disable(obj);
@@ -806,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
806 iopgd = iopgd_offset(obj, da); 803 iopgd = iopgd_offset(obj, da);
807 804
808 if (!iopgd_is_table(*iopgd)) { 805 if (!iopgd_is_table(*iopgd)) {
809 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__, 806 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
810 da, iopgd, *iopgd); 807 "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
811 return IRQ_NONE; 808 return IRQ_NONE;
812 } 809 }
813 810
814 iopte = iopte_offset(iopgd, da); 811 iopte = iopte_offset(iopgd, da);
815 812
816 dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n", 813 dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
817 __func__, da, iopgd, *iopgd, iopte, *iopte); 814 "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
815 iopte, *iopte);
818 816
819 return IRQ_NONE; 817 return IRQ_NONE;
820} 818}
@@ -917,6 +915,33 @@ void iommu_put(struct iommu *obj)
917} 915}
918EXPORT_SYMBOL_GPL(iommu_put); 916EXPORT_SYMBOL_GPL(iommu_put);
919 917
918int iommu_set_isr(const char *name,
919 int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
920 void *priv),
921 void *isr_priv)
922{
923 struct device *dev;
924 struct iommu *obj;
925
926 dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
927 device_match_by_alias);
928 if (!dev)
929 return -ENODEV;
930
931 obj = to_iommu(dev);
932 mutex_lock(&obj->iommu_lock);
933 if (obj->refcount != 0) {
934 mutex_unlock(&obj->iommu_lock);
935 return -EBUSY;
936 }
937 obj->isr = isr;
938 obj->isr_priv = isr_priv;
939 mutex_unlock(&obj->iommu_lock);
940
941 return 0;
942}
943EXPORT_SYMBOL_GPL(iommu_set_isr);
944
920/* 945/*
921 * OMAP Device MMU(IOMMU) detection 946 * OMAP Device MMU(IOMMU) detection
922 */ 947 */
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b5a6e178a7f9..d598d9fd65ac 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,6 +27,8 @@
27 27
28#include <plat/dma.h> 28#include <plat/dma.h>
29#include <plat/mcbsp.h> 29#include <plat/mcbsp.h>
30#include <plat/omap_device.h>
31#include <linux/pm_runtime.h>
30 32
31/* XXX These "sideways" includes are a sign that something is wrong */ 33/* XXX These "sideways" includes are a sign that something is wrong */
32#include "../mach-omap2/cm2xxx_3xxx.h" 34#include "../mach-omap2/cm2xxx_3xxx.h"
@@ -227,10 +229,83 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
227} 229}
228EXPORT_SYMBOL(omap_mcbsp_config); 230EXPORT_SYMBOL(omap_mcbsp_config);
229 231
232/**
233 * omap_mcbsp_dma_params - returns the dma channel number
234 * @id - mcbsp id
235 * @stream - indicates the direction of data flow (rx or tx)
236 *
237 * Returns the dma channel number for the rx channel or tx channel
238 * based on the value of @stream for the requested mcbsp given by @id
239 */
240int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
241{
242 struct omap_mcbsp *mcbsp;
243
244 if (!omap_mcbsp_check_valid_id(id)) {
245 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
246 return -ENODEV;
247 }
248 mcbsp = id_to_mcbsp_ptr(id);
249
250 if (stream)
251 return mcbsp->dma_rx_sync;
252 else
253 return mcbsp->dma_tx_sync;
254}
255EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
256
257/**
258 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
259 * @id - mcbsp id
260 * @stream - indicates the direction of data flow (rx or tx)
261 *
262 * Returns the address of mcbsp data transmit register or data receive register
263 * to be used by DMA for transferring/receiving data based on the value of
264 * @stream for the requested mcbsp given by @id
265 */
266int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
267{
268 struct omap_mcbsp *mcbsp;
269 int data_reg;
270
271 if (!omap_mcbsp_check_valid_id(id)) {
272 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
273 return -ENODEV;
274 }
275 mcbsp = id_to_mcbsp_ptr(id);
276
277 data_reg = mcbsp->phys_dma_base;
278
279 if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
280 if (stream)
281 data_reg += OMAP_MCBSP_REG_DRR1;
282 else
283 data_reg += OMAP_MCBSP_REG_DXR1;
284 } else {
285 if (stream)
286 data_reg += OMAP_MCBSP_REG_DRR;
287 else
288 data_reg += OMAP_MCBSP_REG_DXR;
289 }
290
291 return data_reg;
292}
293EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
294
230#ifdef CONFIG_ARCH_OMAP3 295#ifdef CONFIG_ARCH_OMAP3
296static struct omap_device *find_omap_device_by_dev(struct device *dev)
297{
298 struct platform_device *pdev = container_of(dev,
299 struct platform_device, dev);
300 return container_of(pdev, struct omap_device, pdev);
301}
302
231static void omap_st_on(struct omap_mcbsp *mcbsp) 303static void omap_st_on(struct omap_mcbsp *mcbsp)
232{ 304{
233 unsigned int w; 305 unsigned int w;
306 struct omap_device *od;
307
308 od = find_omap_device_by_dev(mcbsp->dev);
234 309
235 /* 310 /*
236 * Sidetone uses McBSP ICLK - which must not idle when sidetones 311 * Sidetone uses McBSP ICLK - which must not idle when sidetones
@@ -244,9 +319,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
244 w = MCBSP_READ(mcbsp, SSELCR); 319 w = MCBSP_READ(mcbsp, SSELCR);
245 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN); 320 MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
246 321
247 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
248 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
249
250 /* Enable Sidetone from Sidetone Core */ 322 /* Enable Sidetone from Sidetone Core */
251 w = MCBSP_ST_READ(mcbsp, SSELCR); 323 w = MCBSP_ST_READ(mcbsp, SSELCR);
252 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN); 324 MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
@@ -255,13 +327,13 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
255static void omap_st_off(struct omap_mcbsp *mcbsp) 327static void omap_st_off(struct omap_mcbsp *mcbsp)
256{ 328{
257 unsigned int w; 329 unsigned int w;
330 struct omap_device *od;
331
332 od = find_omap_device_by_dev(mcbsp->dev);
258 333
259 w = MCBSP_ST_READ(mcbsp, SSELCR); 334 w = MCBSP_ST_READ(mcbsp, SSELCR);
260 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN)); 335 MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
261 336
262 w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
263 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
264
265 w = MCBSP_READ(mcbsp, SSELCR); 337 w = MCBSP_READ(mcbsp, SSELCR);
266 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); 338 MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
267 339
@@ -273,9 +345,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
273static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) 345static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
274{ 346{
275 u16 val, i; 347 u16 val, i;
348 struct omap_device *od;
276 349
277 val = MCBSP_ST_READ(mcbsp, SYSCONFIG); 350 od = find_omap_device_by_dev(mcbsp->dev);
278 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
279 351
280 val = MCBSP_ST_READ(mcbsp, SSELCR); 352 val = MCBSP_ST_READ(mcbsp, SSELCR);
281 353
@@ -303,9 +375,9 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
303{ 375{
304 u16 w; 376 u16 w;
305 struct omap_mcbsp_st_data *st_data = mcbsp->st_data; 377 struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
378 struct omap_device *od;
306 379
307 w = MCBSP_ST_READ(mcbsp, SYSCONFIG); 380 od = find_omap_device_by_dev(mcbsp->dev);
308 MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
309 381
310 w = MCBSP_ST_READ(mcbsp, SSELCR); 382 w = MCBSP_ST_READ(mcbsp, SSELCR);
311 383
@@ -648,48 +720,33 @@ EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
648 720
649static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) 721static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
650{ 722{
723 struct omap_device *od;
724
725 od = find_omap_device_by_dev(mcbsp->dev);
651 /* 726 /*
652 * Enable wakup behavior, smart idle and all wakeups 727 * Enable wakup behavior, smart idle and all wakeups
653 * REVISIT: some wakeups may be unnecessary 728 * REVISIT: some wakeups may be unnecessary
654 */ 729 */
655 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 730 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
656 u16 syscon; 731 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
657
658 syscon = MCBSP_READ(mcbsp, SYSCON);
659 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
660
661 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
662 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
663 CLOCKACTIVITY(0x02));
664 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
665 } else {
666 syscon |= SIDLEMODE(0x01);
667 }
668
669 MCBSP_WRITE(mcbsp, SYSCON, syscon);
670 } 732 }
671} 733}
672 734
673static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) 735static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
674{ 736{
737 struct omap_device *od;
738
739 od = find_omap_device_by_dev(mcbsp->dev);
740
675 /* 741 /*
676 * Disable wakup behavior, smart idle and all wakeups 742 * Disable wakup behavior, smart idle and all wakeups
677 */ 743 */
678 if (cpu_is_omap34xx() || cpu_is_omap44xx()) { 744 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
679 u16 syscon;
680
681 syscon = MCBSP_READ(mcbsp, SYSCON);
682 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
683 /* 745 /*
684 * HW bug workaround - If no_idle mode is taken, we need to 746 * HW bug workaround - If no_idle mode is taken, we need to
685 * go to smart_idle before going to always_idle, or the 747 * go to smart_idle before going to always_idle, or the
686 * device will not hit retention anymore. 748 * device will not hit retention anymore.
687 */ 749 */
688 syscon |= SIDLEMODE(0x02);
689 MCBSP_WRITE(mcbsp, SYSCON, syscon);
690
691 syscon &= ~(SIDLEMODE(0x03));
692 MCBSP_WRITE(mcbsp, SYSCON, syscon);
693 750
694 MCBSP_WRITE(mcbsp, WAKEUPEN, 0); 751 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
695 } 752 }
@@ -764,8 +821,7 @@ int omap_mcbsp_request(unsigned int id)
764 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) 821 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
765 mcbsp->pdata->ops->request(id); 822 mcbsp->pdata->ops->request(id);
766 823
767 clk_enable(mcbsp->iclk); 824 pm_runtime_get_sync(mcbsp->dev);
768 clk_enable(mcbsp->fclk);
769 825
770 /* Do procedure specific to omap34xx arch, if applicable */ 826 /* Do procedure specific to omap34xx arch, if applicable */
771 omap34xx_mcbsp_request(mcbsp); 827 omap34xx_mcbsp_request(mcbsp);
@@ -813,8 +869,7 @@ err_clk_disable:
813 /* Do procedure specific to omap34xx arch, if applicable */ 869 /* Do procedure specific to omap34xx arch, if applicable */
814 omap34xx_mcbsp_free(mcbsp); 870 omap34xx_mcbsp_free(mcbsp);
815 871
816 clk_disable(mcbsp->fclk); 872 pm_runtime_put_sync(mcbsp->dev);
817 clk_disable(mcbsp->iclk);
818 873
819 spin_lock(&mcbsp->lock); 874 spin_lock(&mcbsp->lock);
820 mcbsp->free = true; 875 mcbsp->free = true;
@@ -844,8 +899,7 @@ void omap_mcbsp_free(unsigned int id)
844 /* Do procedure specific to omap34xx arch, if applicable */ 899 /* Do procedure specific to omap34xx arch, if applicable */
845 omap34xx_mcbsp_free(mcbsp); 900 omap34xx_mcbsp_free(mcbsp);
846 901
847 clk_disable(mcbsp->fclk); 902 pm_runtime_put_sync(mcbsp->dev);
848 clk_disable(mcbsp->iclk);
849 903
850 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { 904 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
851 /* Free IRQs */ 905 /* Free IRQs */
@@ -1649,7 +1703,8 @@ static const struct attribute_group sidetone_attr_group = {
1649 1703
1650static int __devinit omap_st_add(struct omap_mcbsp *mcbsp) 1704static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1651{ 1705{
1652 struct omap_mcbsp_platform_data *pdata = mcbsp->pdata; 1706 struct platform_device *pdev;
1707 struct resource *res;
1653 struct omap_mcbsp_st_data *st_data; 1708 struct omap_mcbsp_st_data *st_data;
1654 int err; 1709 int err;
1655 1710
@@ -1659,7 +1714,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1659 goto err1; 1714 goto err1;
1660 } 1715 }
1661 1716
1662 st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K); 1717 pdev = container_of(mcbsp->dev, struct platform_device, dev);
1718
1719 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1720 st_data->io_base_st = ioremap(res->start, resource_size(res));
1663 if (!st_data->io_base_st) { 1721 if (!st_data->io_base_st) {
1664 err = -ENOMEM; 1722 err = -ENOMEM;
1665 goto err2; 1723 goto err2;
@@ -1748,6 +1806,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1748 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; 1806 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1749 struct omap_mcbsp *mcbsp; 1807 struct omap_mcbsp *mcbsp;
1750 int id = pdev->id - 1; 1808 int id = pdev->id - 1;
1809 struct resource *res;
1751 int ret = 0; 1810 int ret = 0;
1752 1811
1753 if (!pdata) { 1812 if (!pdata) {
@@ -1777,47 +1836,78 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1777 mcbsp->dma_tx_lch = -1; 1836 mcbsp->dma_tx_lch = -1;
1778 mcbsp->dma_rx_lch = -1; 1837 mcbsp->dma_rx_lch = -1;
1779 1838
1780 mcbsp->phys_base = pdata->phys_base; 1839 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1781 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K); 1840 if (!res) {
1841 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842 if (!res) {
1843 dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1844 "resource\n", __func__, pdev->id);
1845 ret = -ENOMEM;
1846 goto exit;
1847 }
1848 }
1849 mcbsp->phys_base = res->start;
1850 omap_mcbsp_cache_size = resource_size(res);
1851 mcbsp->io_base = ioremap(res->start, resource_size(res));
1782 if (!mcbsp->io_base) { 1852 if (!mcbsp->io_base) {
1783 ret = -ENOMEM; 1853 ret = -ENOMEM;
1784 goto err_ioremap; 1854 goto err_ioremap;
1785 } 1855 }
1786 1856
1857 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1858 if (!res)
1859 mcbsp->phys_dma_base = mcbsp->phys_base;
1860 else
1861 mcbsp->phys_dma_base = res->start;
1862
1787 /* Default I/O is IRQ based */ 1863 /* Default I/O is IRQ based */
1788 mcbsp->io_type = OMAP_MCBSP_IRQ_IO; 1864 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1789 mcbsp->tx_irq = pdata->tx_irq;
1790 mcbsp->rx_irq = pdata->rx_irq;
1791 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1792 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1793 1865
1794 mcbsp->iclk = clk_get(&pdev->dev, "ick"); 1866 mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1795 if (IS_ERR(mcbsp->iclk)) { 1867 mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1796 ret = PTR_ERR(mcbsp->iclk); 1868
1797 dev_err(&pdev->dev, "unable to get ick: %d\n", ret); 1869 /* From OMAP4 there will be a single irq line */
1798 goto err_iclk; 1870 if (mcbsp->tx_irq == -ENXIO)
1871 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1872
1873 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1874 if (!res) {
1875 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1876 __func__, pdev->id);
1877 ret = -ENODEV;
1878 goto err_res;
1879 }
1880 mcbsp->dma_rx_sync = res->start;
1881
1882 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1883 if (!res) {
1884 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1885 __func__, pdev->id);
1886 ret = -ENODEV;
1887 goto err_res;
1799 } 1888 }
1889 mcbsp->dma_tx_sync = res->start;
1800 1890
1801 mcbsp->fclk = clk_get(&pdev->dev, "fck"); 1891 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1802 if (IS_ERR(mcbsp->fclk)) { 1892 if (IS_ERR(mcbsp->fclk)) {
1803 ret = PTR_ERR(mcbsp->fclk); 1893 ret = PTR_ERR(mcbsp->fclk);
1804 dev_err(&pdev->dev, "unable to get fck: %d\n", ret); 1894 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1805 goto err_fclk; 1895 goto err_res;
1806 } 1896 }
1807 1897
1808 mcbsp->pdata = pdata; 1898 mcbsp->pdata = pdata;
1809 mcbsp->dev = &pdev->dev; 1899 mcbsp->dev = &pdev->dev;
1810 mcbsp_ptr[id] = mcbsp; 1900 mcbsp_ptr[id] = mcbsp;
1901 mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
1811 platform_set_drvdata(pdev, mcbsp); 1902 platform_set_drvdata(pdev, mcbsp);
1903 pm_runtime_enable(mcbsp->dev);
1812 1904
1813 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */ 1905 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1814 omap34xx_device_init(mcbsp); 1906 omap34xx_device_init(mcbsp);
1815 1907
1816 return 0; 1908 return 0;
1817 1909
1818err_fclk: 1910err_res:
1819 clk_put(mcbsp->iclk);
1820err_iclk:
1821 iounmap(mcbsp->io_base); 1911 iounmap(mcbsp->io_base);
1822err_ioremap: 1912err_ioremap:
1823 kfree(mcbsp); 1913 kfree(mcbsp);
@@ -1839,7 +1929,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1839 omap34xx_device_exit(mcbsp); 1929 omap34xx_device_exit(mcbsp);
1840 1930
1841 clk_put(mcbsp->fclk); 1931 clk_put(mcbsp->fclk);
1842 clk_put(mcbsp->iclk);
1843 1932
1844 iounmap(mcbsp->io_base); 1933 iounmap(mcbsp->io_base);
1845 kfree(mcbsp); 1934 kfree(mcbsp);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-01 15:54:13 -0500